drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12 #include <net/if.h>
  13 #include <sys/mman.h>
  14 #include <linux/rtnetlink.h>
  15
  16 /* Verbs header. */
  17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic ignored "-Wpedantic"
  20 #endif
  21 #include <infiniband/verbs.h>
  22 #ifdef PEDANTIC
  23 #pragma GCC diagnostic error "-Wpedantic"
  24 #endif
  25
  26 #include <rte_malloc.h>
  27 #include <rte_ethdev_driver.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_pci.h>
  30 #include <rte_bus_pci.h>
  31 #include <rte_common.h>
  32 #include <rte_kvargs.h>
  33 #include <rte_rwlock.h>
  34 #include <rte_spinlock.h>
  35 #include <rte_string_fns.h>
  36 #include <rte_alarm.h>
  37
  38 #include <mlx5_glue.h>
  39 #include <mlx5_devx_cmds.h>
  40 #include <mlx5_common.h>
  41 #include <mlx5_common_os.h>
  42 #include <mlx5_common_mp.h>
  43
  44 #include "mlx5_defs.h"
  45 #include "mlx5.h"
  46 #include "mlx5_utils.h"
  47 #include "mlx5_rxtx.h"
  48 #include "mlx5_autoconf.h"
  49 #include "mlx5_mr.h"
  50 #include "mlx5_flow.h"
  51 #include "rte_pmd_mlx5.h"
  52
  53 /* Device parameter to enable RX completion queue compression. */
  54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  55
  56 /* Device parameter to enable RX completion entry padding to 128B. */
  57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
  58
  59 /* Device parameter to enable padding Rx packet to cacheline size. */
  60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  61
  62 /* Device parameter to enable Multi-Packet Rx queue. */
  63 #define MLX5_RX_MPRQ_EN "mprq_en"
  64
  65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  67
  68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  70
  71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  73
  74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  76
  77 /* Device parameter to configure inline send. Deprecated, ignored.*/
  78 #define MLX5_TXQ_INLINE "txq_inline"
  79
  80 /* Device parameter to limit packet size to inline with ordinary SEND. */
  81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  82
  83 /* Device parameter to configure minimal data size to inline. */
  84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  85
  86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  88
  89 /*
  90  * Device parameter to configure the number of TX queues threshold for
  91  * enabling inline send.
  92  */
  93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  94
  95 /*
  96  * Device parameter to configure the number of TX queues threshold for
  97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  98  */
  99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
 100
 101 /* Device parameter to enable multi-packet send WQEs. */
 102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
 103
 104 /*
 105  * Device parameter to force doorbell register mapping
 106  * to non-cahed region eliminating the extra write memory barrier.
 107  */
 108 #define MLX5_TX_DB_NC "tx_db_nc"
 109
 110 /*
 111  * Device parameter to include 2 dsegs in the title WQEBB.
 112  * Deprecated, ignored.
 113  */
 114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 115
 116 /*
 117  * Device parameter to limit the size of inlining packet.
 118  * Deprecated, ignored.
 119  */
 120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 121
 122 /*
 123  * Device parameter to enable Tx scheduling on timestamps
 124  * and specify the packet pacing granularity in nanoseconds.
 125  */
 126 #define MLX5_TX_PP "tx_pp"
 127
 128 /*
 129  * Device parameter to specify skew in nanoseconds on Tx datapath,
 130  * it represents the time between SQ start WQE processing and
 131  * appearing actual packet data on the wire.
 132  */
 133 #define MLX5_TX_SKEW "tx_skew"
 134
 135 /*
 136  * Device parameter to enable hardware Tx vector.
 137  * Deprecated, ignored (no vectorized Tx routines anymore).
 138  */
 139 #define MLX5_TX_VEC_EN "tx_vec_en"
 140
 141 /* Device parameter to enable hardware Rx vector. */
 142 #define MLX5_RX_VEC_EN "rx_vec_en"
 143
 144 /* Allow L3 VXLAN flow creation. */
 145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 146
 147 /* Activate DV E-Switch flow steering. */
 148 #define MLX5_DV_ESW_EN "dv_esw_en"
 149
 150 /* Activate DV flow steering. */
 151 #define MLX5_DV_FLOW_EN "dv_flow_en"
 152
 153 /* Enable extensive flow metadata support. */
 154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 155
 156 /* Device parameter to let the user manage the lacp traffic of bonded device */
 157 #define MLX5_LACP_BY_USER "lacp_by_user"
 158
 159 /* Activate Netlink support in VF mode. */
 160 #define MLX5_VF_NL_EN "vf_nl_en"
 161
 162 /* Enable extending memsegs when creating a MR. */
 163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 164
 165 /* Select port representors to instantiate. */
 166 #define MLX5_REPRESENTOR "representor"
 167
 168 /* Device parameter to configure the maximum number of dump files per queue. */
 169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 170
 171 /* Configure timeout of LRO session (in microseconds). */
 172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 173
 174 /*
 175  * Device parameter to configure the total data buffer size for a single
 176  * hairpin queue (logarithm value).
 177  */
 178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 179
 180 /* Flow memory reclaim mode. */
 181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 182
 183 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
 184
 185 /* Shared memory between primary and secondary processes. */
 186 struct mlx5_shared_data *mlx5_shared_data;
 187
 188 /* Spinlock for mlx5_shared_data allocation. */
 189 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
 190
 191 /* Process local data for secondary processes. */
 192 static struct mlx5_local_data mlx5_local_data;
 193
 194 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 195                                                 LIST_HEAD_INITIALIZER();
 196 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
 197
 198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 199 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 200         {
 201                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 0,
 206                 .release_mem_en = 1,
 207                 .malloc = rte_malloc_socket,
 208                 .free = rte_free,
 209                 .type = "mlx5_encap_decap_ipool",
 210         },
 211         {
 212                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 0,
 217                 .release_mem_en = 1,
 218                 .malloc = rte_malloc_socket,
 219                 .free = rte_free,
 220                 .type = "mlx5_push_vlan_ipool",
 221         },
 222         {
 223                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 0,
 228                 .release_mem_en = 1,
 229                 .malloc = rte_malloc_socket,
 230                 .free = rte_free,
 231                 .type = "mlx5_tag_ipool",
 232         },
 233         {
 234                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 0,
 239                 .release_mem_en = 1,
 240                 .malloc = rte_malloc_socket,
 241                 .free = rte_free,
 242                 .type = "mlx5_port_id_ipool",
 243         },
 244         {
 245                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 0,
 250                 .release_mem_en = 1,
 251                 .malloc = rte_malloc_socket,
 252                 .free = rte_free,
 253                 .type = "mlx5_jump_ipool",
 254         },
 255 #endif
 256         {
 257                 .size = sizeof(struct mlx5_flow_meter),
 258                 .trunk_size = 64,
 259                 .grow_trunk = 3,
 260                 .grow_shift = 2,
 261                 .need_lock = 0,
 262                 .release_mem_en = 1,
 263                 .malloc = rte_malloc_socket,
 264                 .free = rte_free,
 265                 .type = "mlx5_meter_ipool",
 266         },
 267         {
 268                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 269                 .trunk_size = 64,
 270                 .grow_trunk = 3,
 271                 .grow_shift = 2,
 272                 .need_lock = 0,
 273                 .release_mem_en = 1,
 274                 .malloc = rte_malloc_socket,
 275                 .free = rte_free,
 276                 .type = "mlx5_mcp_ipool",
 277         },
 278         {
 279                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 280                 .trunk_size = 64,
 281                 .grow_trunk = 3,
 282                 .grow_shift = 2,
 283                 .need_lock = 0,
 284                 .release_mem_en = 1,
 285                 .malloc = rte_malloc_socket,
 286                 .free = rte_free,
 287                 .type = "mlx5_hrxq_ipool",
 288         },
 289         {
 290                 /*
 291                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 292                  * It set in run time according to PCI function configuration.
 293                  */
 294                 .size = 0,
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 0,
 299                 .release_mem_en = 1,
 300                 .malloc = rte_malloc_socket,
 301                 .free = rte_free,
 302                 .type = "mlx5_flow_handle_ipool",
 303         },
 304         {
 305                 .size = sizeof(struct rte_flow),
 306                 .trunk_size = 4096,
 307                 .need_lock = 1,
 308                 .release_mem_en = 1,
 309                 .malloc = rte_malloc_socket,
 310                 .free = rte_free,
 311                 .type = "rte_flow_ipool",
 312         },
 313 };
 314
 315
 316 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 317 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 318
 319 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 320
 321 /**
 322  * Allocate ID pool structure.
 323  *
 324  * @param[in] max_id
 325  *   The maximum id can be allocated from the pool.
 326  *
 327  * @return
 328  *   Pointer to pool object, NULL value otherwise.
 329  */
 330 struct mlx5_flow_id_pool *
 331 mlx5_flow_id_pool_alloc(uint32_t max_id)
 332 {
 333         struct mlx5_flow_id_pool *pool;
 334         void *mem;
 335
 336         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
 337                            RTE_CACHE_LINE_SIZE);
 338         if (!pool) {
 339                 DRV_LOG(ERR, "can't allocate id pool");
 340                 rte_errno  = ENOMEM;
 341                 return NULL;
 342         }
 343         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
 344                           RTE_CACHE_LINE_SIZE);
 345         if (!mem) {
 346                 DRV_LOG(ERR, "can't allocate mem for id pool");
 347                 rte_errno  = ENOMEM;
 348                 goto error;
 349         }
 350         pool->free_arr = mem;
 351         pool->curr = pool->free_arr;
 352         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
 353         pool->base_index = 0;
 354         pool->max_id = max_id;
 355         return pool;
 356 error:
 357         rte_free(pool);
 358         return NULL;
 359 }
 360
 361 /**
 362  * Release ID pool structure.
 363  *
 364  * @param[in] pool
 365  *   Pointer to flow id pool object to free.
 366  */
 367 void
 368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
 369 {
 370         rte_free(pool->free_arr);
 371         rte_free(pool);
 372 }
 373
 374 /**
 375  * Generate ID.
 376  *
 377  * @param[in] pool
 378  *   Pointer to flow id pool.
 379  * @param[out] id
 380  *   The generated ID.
 381  *
 382  * @return
 383  *   0 on success, error value otherwise.
 384  */
 385 uint32_t
 386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
 387 {
 388         if (pool->curr == pool->free_arr) {
 389                 if (pool->base_index == pool->max_id) {
 390                         rte_errno  = ENOMEM;
 391                         DRV_LOG(ERR, "no free id");
 392                         return -rte_errno;
 393                 }
 394                 *id = ++pool->base_index;
 395                 return 0;
 396         }
 397         *id = *(--pool->curr);
 398         return 0;
 399 }
 400
 401 /**
 402  * Release ID.
 403  *
 404  * @param[in] pool
 405  *   Pointer to flow id pool.
 406  * @param[out] id
 407  *   The generated ID.
 408  *
 409  * @return
 410  *   0 on success, error value otherwise.
 411  */
 412 uint32_t
 413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
 414 {
 415         uint32_t size;
 416         uint32_t size2;
 417         void *mem;
 418
 419         if (pool->curr == pool->last) {
 420                 size = pool->curr - pool->free_arr;
 421                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
 422                 MLX5_ASSERT(size2 > size);
 423                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
 424                 if (!mem) {
 425                         DRV_LOG(ERR, "can't allocate mem for id pool");
 426                         rte_errno  = ENOMEM;
 427                         return -rte_errno;
 428                 }
 429                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
 430                 rte_free(pool->free_arr);
 431                 pool->free_arr = mem;
 432                 pool->curr = pool->free_arr + size;
 433                 pool->last = pool->free_arr + size2;
 434         }
 435         *pool->curr = id;
 436         pool->curr++;
 437         return 0;
 438 }
 439
 440 /**
 441  * Initialize the shared aging list information per port.
 442  *
 443  * @param[in] sh
 444  *   Pointer to mlx5_dev_ctx_shared object.
 445  */
 446 static void
 447 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 448 {
 449         uint32_t i;
 450         struct mlx5_age_info *age_info;
 451
 452         for (i = 0; i < sh->max_port; i++) {
 453                 age_info = &sh->port[i].age_info;
 454                 age_info->flags = 0;
 455                 TAILQ_INIT(&age_info->aged_counters);
 456                 rte_spinlock_init(&age_info->aged_sl);
 457                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 458         }
 459 }
 460
 461 /**
 462  * Initialize the counters management structure.
 463  *
 464  * @param[in] sh
 465  *   Pointer to mlx5_dev_ctx_shared object to free
 466  */
 467 static void
 468 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 469 {
 470         int i;
 471
 472         memset(&sh->cmng, 0, sizeof(sh->cmng));
 473         TAILQ_INIT(&sh->cmng.flow_counters);
 474         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 475                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
 476                 sh->cmng.ccont[i].max_id = -1;
 477                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
 478                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
 479                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
 480                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
 481                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
 482         }
 483 }
 484
 485 /**
 486  * Destroy all the resources allocated for a counter memory management.
 487  *
 488  * @param[in] mng
 489  *   Pointer to the memory management structure.
 490  */
 491 static void
 492 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 493 {
 494         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 495
 496         LIST_REMOVE(mng, next);
 497         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 498         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
 499         rte_free(mem);
 500 }
 501
 502 /**
 503  * Close and release all the resources of the counters management.
 504  *
 505  * @param[in] sh
 506  *   Pointer to mlx5_dev_ctx_shared object to free.
 507  */
 508 static void
 509 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 510 {
 511         struct mlx5_counter_stats_mem_mng *mng;
 512         int i;
 513         int j;
 514         int retries = 1024;
 515
 516         rte_errno = 0;
 517         while (--retries) {
 518                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 519                 if (rte_errno != EINPROGRESS)
 520                         break;
 521                 rte_pause();
 522         }
 523         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
 524                 struct mlx5_flow_counter_pool *pool;
 525                 uint32_t batch = !!(i > 1);
 526
 527                 if (!sh->cmng.ccont[i].pools)
 528                         continue;
 529                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 530                 while (pool) {
 531                         if (batch && pool->min_dcs)
 532                                 claim_zero(mlx5_devx_cmd_destroy
 533                                                                (pool->min_dcs));
 534                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 535                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
 536                                         claim_zero
 537                                          (mlx5_glue->destroy_flow_action
 538                                           (MLX5_POOL_GET_CNT
 539                                           (pool, j)->action));
 540                                 if (!batch && MLX5_GET_POOL_CNT_EXT
 541                                     (pool, j)->dcs)
 542                                         claim_zero(mlx5_devx_cmd_destroy
 543                                                    (MLX5_GET_POOL_CNT_EXT
 544                                                     (pool, j)->dcs));
 545                         }
 546                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
 547                         rte_free(pool);
 548                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
 549                 }
 550                 rte_free(sh->cmng.ccont[i].pools);
 551         }
 552         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 553         while (mng) {
 554                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 555                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 556         }
 557         memset(&sh->cmng, 0, sizeof(sh->cmng));
 558 }
 559
 560 /**
 561  * Initialize the flow resources' indexed mempool.
 562  *
 563  * @param[in] sh
 564  *   Pointer to mlx5_dev_ctx_shared object.
 565  * @param[in] sh
 566  *   Pointer to user dev config.
 567  */
 568 static void
 569 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 570                        const struct mlx5_dev_config *config)
 571 {
 572         uint8_t i;
 573         struct mlx5_indexed_pool_config cfg;
 574
 575         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 576                 cfg = mlx5_ipool_cfg[i];
 577                 switch (i) {
 578                 default:
 579                         break;
 580                 /*
 581                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 582                  * according to PCI function flow configuration.
 583                  */
 584                 case MLX5_IPOOL_MLX5_FLOW:
 585                         cfg.size = config->dv_flow_en ?
 586                                 sizeof(struct mlx5_flow_handle) :
 587                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 588                         break;
 589                 }
 590                 if (config->reclaim_mode)
 591                         cfg.release_mem_en = 1;
 592                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 593         }
 594 }
 595
 596 /**
 597  * Release the flow resources' indexed mempool.
 598  *
 599  * @param[in] sh
 600  *   Pointer to mlx5_dev_ctx_shared object.
 601  */
 602 static void
 603 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 604 {
 605         uint8_t i;
 606
 607         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 608                 mlx5_ipool_destroy(sh->ipool[i]);
 609 }
 610
 611 /**
 612  * Allocate shared device context. If there is multiport device the
 613  * master and representors will share this context, if there is single
 614  * port dedicated device, the context will be used by only given
 615  * port due to unification.
 616  *
 617  * Routine first searches the context for the specified device name,
 618  * if found the shared context assumed and reference counter is incremented.
 619  * If no context found the new one is created and initialized with specified
 620  * device context and parameters.
 621  *
 622  * @param[in] spawn
 623  *   Pointer to the device attributes (name, port, etc).
 624  * @param[in] config
 625  *   Pointer to device configuration structure.
 626  *
 627  * @return
 628  *   Pointer to mlx5_dev_ctx_shared object on success,
 629  *   otherwise NULL and rte_errno is set.
 630  */
 631 struct mlx5_dev_ctx_shared *
 632 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
 633                            const struct mlx5_dev_config *config)
 634 {
 635         struct mlx5_dev_ctx_shared *sh;
 636         int err = 0;
 637         uint32_t i;
 638         struct mlx5_devx_tis_attr tis_attr = { 0 };
 639
 640         MLX5_ASSERT(spawn);
 641         /* Secondary process should not create the shared context. */
 642         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 643         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 644         /* Search for IB context by device name. */
 645         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
 646                 if (!strcmp(sh->ibdev_name,
 647                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
 648                         sh->refcnt++;
 649                         goto exit;
 650                 }
 651         }
 652         /* No device found, we have to create new shared context. */
 653         MLX5_ASSERT(spawn->max_port);
 654         sh = rte_zmalloc("ethdev shared ib context",
 655                          sizeof(struct mlx5_dev_ctx_shared) +
 656                          spawn->max_port *
 657                          sizeof(struct mlx5_dev_shared_port),
 658                          RTE_CACHE_LINE_SIZE);
 659         if (!sh) {
 660                 DRV_LOG(ERR, "shared context allocation failure");
 661                 rte_errno  = ENOMEM;
 662                 goto exit;
 663         }
 664         err = mlx5_os_open_device(spawn, config, sh);
 665         if (!sh->ctx)
 666                 goto error;
 667         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
 668         if (err) {
 669                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
 670                 goto error;
 671         }
 672         sh->refcnt = 1;
 673         sh->max_port = spawn->max_port;
 674         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
 675                 sizeof(sh->ibdev_name) - 1);
 676         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
 677                 sizeof(sh->ibdev_path) - 1);
 678         /*
 679          * Setting port_id to max unallowed value means
 680          * there is no interrupt subhandler installed for
 681          * the given port index i.
 682          */
 683         for (i = 0; i < sh->max_port; i++) {
 684                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
 685                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
 686         }
 687         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
 688         if (sh->pd == NULL) {
 689                 DRV_LOG(ERR, "PD allocation failure");
 690                 err = ENOMEM;
 691                 goto error;
 692         }
 693         if (sh->devx) {
 694                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
 695                 if (err) {
 696                         DRV_LOG(ERR, "Fail to extract pdn from PD");
 697                         goto error;
 698                 }
 699                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
 700                 if (!sh->td) {
 701                         DRV_LOG(ERR, "TD allocation failure");
 702                         err = ENOMEM;
 703                         goto error;
 704                 }
 705                 tis_attr.transport_domain = sh->td->id;
 706                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
 707                 if (!sh->tis) {
 708                         DRV_LOG(ERR, "TIS allocation failure");
 709                         err = ENOMEM;
 710                         goto error;
 711                 }
 712                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
 713                 if (!sh->tx_uar) {
 714                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
 715                         err = ENOMEM;
 716                         goto error;
 717                 }
 718         }
 719         sh->flow_id_pool = mlx5_flow_id_pool_alloc
 720                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
 721         if (!sh->flow_id_pool) {
 722                 DRV_LOG(ERR, "can't create flow id pool");
 723                 err = ENOMEM;
 724                 goto error;
 725         }
 726 #ifndef RTE_ARCH_64
 727         /* Initialize UAR access locks for 32bit implementations. */
 728         rte_spinlock_init(&sh->uar_lock_cq);
 729         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
 730                 rte_spinlock_init(&sh->uar_lock[i]);
 731 #endif
 732         /*
 733          * Once the device is added to the list of memory event
 734          * callback, its global MR cache table cannot be expanded
 735          * on the fly because of deadlock. If it overflows, lookup
 736          * should be done by searching MR list linearly, which is slow.
 737          *
 738          * At this point the device is not added to the memory
 739          * event list yet, context is just being created.
 740          */
 741         err = mlx5_mr_btree_init(&sh->share_cache.cache,
 742                                  MLX5_MR_BTREE_CACHE_N * 2,
 743                                  spawn->pci_dev->device.numa_node);
 744         if (err) {
 745                 err = rte_errno;
 746                 goto error;
 747         }
 748         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
 749                               &sh->share_cache.dereg_mr_cb);
 750         mlx5_os_dev_shared_handler_install(sh);
 751         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 752         if (!sh->cnt_id_tbl) {
 753                 err = rte_errno;
 754                 goto error;
 755         }
 756         mlx5_flow_aging_init(sh);
 757         mlx5_flow_counters_mng_init(sh);
 758         mlx5_flow_ipool_create(sh, config);
 759         /* Add device to memory callback list. */
 760         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 761         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
 762                          sh, mem_event_cb);
 763         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 764         /* Add context to the global device list. */
 765         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
 766 exit:
 767         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 768         return sh;
 769 error:
 770         pthread_mutex_destroy(&sh->txpp.mutex);
 771         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 772         MLX5_ASSERT(sh);
 773         if (sh->cnt_id_tbl) {
 774                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 775                 sh->cnt_id_tbl = NULL;
 776         }
 777         if (sh->tx_uar) {
 778                 mlx5_glue->devx_free_uar(sh->tx_uar);
 779                 sh->tx_uar = NULL;
 780         }
 781         if (sh->tis)
 782                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 783         if (sh->td)
 784                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 785         if (sh->pd)
 786                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 787         if (sh->ctx)
 788                 claim_zero(mlx5_glue->close_device(sh->ctx));
 789         if (sh->flow_id_pool)
 790                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 791         rte_free(sh);
 792         MLX5_ASSERT(err > 0);
 793         rte_errno = err;
 794         return NULL;
 795 }
 796
 797 /**
 798  * Free shared IB device context. Decrement counter and if zero free
 799  * all allocated resources and close handles.
 800  *
 801  * @param[in] sh
 802  *   Pointer to mlx5_dev_ctx_shared object to free
 803  */
 804 void
 805 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
 806 {
 807         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
 808 #ifdef RTE_LIBRTE_MLX5_DEBUG
 809         /* Check the object presence in the list. */
 810         struct mlx5_dev_ctx_shared *lctx;
 811
 812         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
 813                 if (lctx == sh)
 814                         break;
 815         MLX5_ASSERT(lctx);
 816         if (lctx != sh) {
 817                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
 818                 goto exit;
 819         }
 820 #endif
 821         MLX5_ASSERT(sh);
 822         MLX5_ASSERT(sh->refcnt);
 823         /* Secondary process should not free the shared context. */
 824         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 825         if (--sh->refcnt)
 826                 goto exit;
 827         /* Remove from memory callback device list. */
 828         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
 829         LIST_REMOVE(sh, mem_event_cb);
 830         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
 831         /* Release created Memory Regions. */
 832         mlx5_mr_release_cache(&sh->share_cache);
 833         /* Remove context from the global device list. */
 834         LIST_REMOVE(sh, next);
 835         /*
 836          *  Ensure there is no async event handler installed.
 837          *  Only primary process handles async device events.
 838          **/
 839         mlx5_flow_counters_mng_close(sh);
 840         mlx5_flow_ipool_destroy(sh);
 841         mlx5_os_dev_shared_handler_uninstall(sh);
 842         if (sh->cnt_id_tbl) {
 843                 mlx5_l3t_destroy(sh->cnt_id_tbl);
 844                 sh->cnt_id_tbl = NULL;
 845         }
 846         if (sh->tx_uar) {
 847                 mlx5_glue->devx_free_uar(sh->tx_uar);
 848                 sh->tx_uar = NULL;
 849         }
 850         if (sh->pd)
 851                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
 852         if (sh->tis)
 853                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
 854         if (sh->td)
 855                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
 856         if (sh->ctx)
 857                 claim_zero(mlx5_glue->close_device(sh->ctx));
 858         if (sh->flow_id_pool)
 859                 mlx5_flow_id_pool_release(sh->flow_id_pool);
 860         pthread_mutex_destroy(&sh->txpp.mutex);
 861         rte_free(sh);
 862 exit:
 863         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
 864 }
 865
 866 /**
 867  * Destroy table hash list and all the root entries per domain.
 868  *
 869  * @param[in] priv
 870  *   Pointer to the private device data structure.
 871  */
 872 void
 873 mlx5_free_table_hash_list(struct mlx5_priv *priv)
 874 {
 875         struct mlx5_dev_ctx_shared *sh = priv->sh;
 876         struct mlx5_flow_tbl_data_entry *tbl_data;
 877         union mlx5_flow_tbl_key table_key = {
 878                 {
 879                         .table_id = 0,
 880                         .reserved = 0,
 881                         .domain = 0,
 882                         .direction = 0,
 883                 }
 884         };
 885         struct mlx5_hlist_entry *pos;
 886
 887         if (!sh->flow_tbls)
 888                 return;
 889         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 890         if (pos) {
 891                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 892                                         entry);
 893                 MLX5_ASSERT(tbl_data);
 894                 mlx5_hlist_remove(sh->flow_tbls, pos);
 895                 rte_free(tbl_data);
 896         }
 897         table_key.direction = 1;
 898         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 899         if (pos) {
 900                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 901                                         entry);
 902                 MLX5_ASSERT(tbl_data);
 903                 mlx5_hlist_remove(sh->flow_tbls, pos);
 904                 rte_free(tbl_data);
 905         }
 906         table_key.direction = 0;
 907         table_key.domain = 1;
 908         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
 909         if (pos) {
 910                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
 911                                         entry);
 912                 MLX5_ASSERT(tbl_data);
 913                 mlx5_hlist_remove(sh->flow_tbls, pos);
 914                 rte_free(tbl_data);
 915         }
 916         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
 917 }
 918
 919 /**
 920  * Initialize flow table hash list and create the root tables entry
 921  * for each domain.
 922  *
 923  * @param[in] priv
 924  *   Pointer to the private device data structure.
 925  *
 926  * @return
 927  *   Zero on success, positive error code otherwise.
 928  */
 929 int
 930 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
 931 {
 932         struct mlx5_dev_ctx_shared *sh = priv->sh;
 933         char s[MLX5_HLIST_NAMESIZE];
 934         int err = 0;
 935
 936         MLX5_ASSERT(sh);
 937         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
 938         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
 939         if (!sh->flow_tbls) {
 940                 DRV_LOG(ERR, "flow tables with hash creation failed.");
 941                 err = ENOMEM;
 942                 return err;
 943         }
 944 #ifndef HAVE_MLX5DV_DR
 945         /*
 946          * In case we have not DR support, the zero tables should be created
 947          * because DV expect to see them even if they cannot be created by
 948          * RDMA-CORE.
 949          */
 950         union mlx5_flow_tbl_key table_key = {
 951                 {
 952                         .table_id = 0,
 953                         .reserved = 0,
 954                         .domain = 0,
 955                         .direction = 0,
 956                 }
 957         };
 958         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
 959                                                           sizeof(*tbl_data), 0);
 960
 961         if (!tbl_data) {
 962                 err = ENOMEM;
 963                 goto error;
 964         }
 965         tbl_data->entry.key = table_key.v64;
 966         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 967         if (err)
 968                 goto error;
 969         rte_atomic32_init(&tbl_data->tbl.refcnt);
 970         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 971         table_key.direction = 1;
 972         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 973         if (!tbl_data) {
 974                 err = ENOMEM;
 975                 goto error;
 976         }
 977         tbl_data->entry.key = table_key.v64;
 978         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 979         if (err)
 980                 goto error;
 981         rte_atomic32_init(&tbl_data->tbl.refcnt);
 982         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 983         table_key.direction = 0;
 984         table_key.domain = 1;
 985         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
 986         if (!tbl_data) {
 987                 err = ENOMEM;
 988                 goto error;
 989         }
 990         tbl_data->entry.key = table_key.v64;
 991         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
 992         if (err)
 993                 goto error;
 994         rte_atomic32_init(&tbl_data->tbl.refcnt);
 995         rte_atomic32_inc(&tbl_data->tbl.refcnt);
 996         return err;
 997 error:
 998         mlx5_free_table_hash_list(priv);
 999 #endif /* HAVE_MLX5DV_DR */
1000         return err;
1001 }
1002
1003 /**
1004  * Initialize shared data between primary and secondary process.
1005  *
1006  * A memzone is reserved by primary process and secondary processes attach to
1007  * the memzone.
1008  *
1009  * @return
1010  *   0 on success, a negative errno value otherwise and rte_errno is set.
1011  */
1012 static int
1013 mlx5_init_shared_data(void)
1014 {
1015         const struct rte_memzone *mz;
1016         int ret = 0;
1017
1018         rte_spinlock_lock(&mlx5_shared_data_lock);
1019         if (mlx5_shared_data == NULL) {
1020                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1021                         /* Allocate shared memory. */
1022                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1023                                                  sizeof(*mlx5_shared_data),
1024                                                  SOCKET_ID_ANY, 0);
1025                         if (mz == NULL) {
1026                                 DRV_LOG(ERR,
1027                                         "Cannot allocate mlx5 shared data");
1028                                 ret = -rte_errno;
1029                                 goto error;
1030                         }
1031                         mlx5_shared_data = mz->addr;
1032                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1033                         rte_spinlock_init(&mlx5_shared_data->lock);
1034                 } else {
1035                         /* Lookup allocated shared memory. */
1036                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1037                         if (mz == NULL) {
1038                                 DRV_LOG(ERR,
1039                                         "Cannot attach mlx5 shared data");
1040                                 ret = -rte_errno;
1041                                 goto error;
1042                         }
1043                         mlx5_shared_data = mz->addr;
1044                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1045                 }
1046         }
1047 error:
1048         rte_spinlock_unlock(&mlx5_shared_data_lock);
1049         return ret;
1050 }
1051
1052 /**
1053  * Retrieve integer value from environment variable.
1054  *
1055  * @param[in] name
1056  *   Environment variable name.
1057  *
1058  * @return
1059  *   Integer value, 0 if the variable is not set.
1060  */
1061 int
1062 mlx5_getenv_int(const char *name)
1063 {
1064         const char *val = getenv(name);
1065
1066         if (val == NULL)
1067                 return 0;
1068         return atoi(val);
1069 }
1070
1071 /**
1072  * DPDK callback to add udp tunnel port
1073  *
1074  * @param[in] dev
1075  *   A pointer to eth_dev
1076  * @param[in] udp_tunnel
1077  *   A pointer to udp tunnel
1078  *
1079  * @return
1080  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1081  */
1082 int
1083 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1084                          struct rte_eth_udp_tunnel *udp_tunnel)
1085 {
1086         MLX5_ASSERT(udp_tunnel != NULL);
1087         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1088             udp_tunnel->udp_port == 4789)
1089                 return 0;
1090         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1091             udp_tunnel->udp_port == 4790)
1092                 return 0;
1093         return -ENOTSUP;
1094 }
1095
1096 /**
1097  * Initialize process private data structure.
1098  *
1099  * @param dev
1100  *   Pointer to Ethernet device structure.
1101  *
1102  * @return
1103  *   0 on success, a negative errno value otherwise and rte_errno is set.
1104  */
1105 int
1106 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1107 {
1108         struct mlx5_priv *priv = dev->data->dev_private;
1109         struct mlx5_proc_priv *ppriv;
1110         size_t ppriv_size;
1111
1112         /*
1113          * UAR register table follows the process private structure. BlueFlame
1114          * registers for Tx queues are stored in the table.
1115          */
1116         ppriv_size =
1117                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1118         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1119                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1120         if (!ppriv) {
1121                 rte_errno = ENOMEM;
1122                 return -rte_errno;
1123         }
1124         ppriv->uar_table_sz = ppriv_size;
1125         dev->process_private = ppriv;
1126         return 0;
1127 }
1128
1129 /**
1130  * Un-initialize process private data structure.
1131  *
1132  * @param dev
1133  *   Pointer to Ethernet device structure.
1134  */
1135 static void
1136 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1137 {
1138         if (!dev->process_private)
1139                 return;
1140         rte_free(dev->process_private);
1141         dev->process_private = NULL;
1142 }
1143
1144 /**
1145  * DPDK callback to close the device.
1146  *
1147  * Destroy all queues and objects, free memory.
1148  *
1149  * @param dev
1150  *   Pointer to Ethernet device structure.
1151  */
1152 void
1153 mlx5_dev_close(struct rte_eth_dev *dev)
1154 {
1155         struct mlx5_priv *priv = dev->data->dev_private;
1156         unsigned int i;
1157         int ret;
1158
1159         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1160                 /* Check if process_private released. */
1161                 if (!dev->process_private)
1162                         return;
1163                 mlx5_tx_uar_uninit_secondary(dev);
1164                 mlx5_proc_priv_uninit(dev);
1165                 rte_eth_dev_release_port(dev);
1166                 return;
1167         }
1168         if (!priv->sh)
1169                 return;
1170         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1171                 dev->data->port_id,
1172                 ((priv->sh->ctx != NULL) ?
1173                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1174         /*
1175          * If default mreg copy action is removed at the stop stage,
1176          * the search will return none and nothing will be done anymore.
1177          */
1178         mlx5_flow_stop_default(dev);
1179         mlx5_traffic_disable(dev);
1180         /*
1181          * If all the flows are already flushed in the device stop stage,
1182          * then this will return directly without any action.
1183          */
1184         mlx5_flow_list_flush(dev, &priv->flows, true);
1185         mlx5_flow_meter_flush(dev, NULL);
1186         /* Free the intermediate buffers for flow creation. */
1187         mlx5_flow_free_intermediate(dev);
1188         /* Prevent crashes when queues are still in use. */
1189         dev->rx_pkt_burst = removed_rx_burst;
1190         dev->tx_pkt_burst = removed_tx_burst;
1191         rte_wmb();
1192         /* Disable datapath on secondary process. */
1193         mlx5_mp_req_stop_rxtx(dev);
1194         if (priv->rxqs != NULL) {
1195                 /* XXX race condition if mlx5_rx_burst() is still running. */
1196                 usleep(1000);
1197                 for (i = 0; (i != priv->rxqs_n); ++i)
1198                         mlx5_rxq_release(dev, i);
1199                 priv->rxqs_n = 0;
1200                 priv->rxqs = NULL;
1201         }
1202         if (priv->txqs != NULL) {
1203                 /* XXX race condition if mlx5_tx_burst() is still running. */
1204                 usleep(1000);
1205                 for (i = 0; (i != priv->txqs_n); ++i)
1206                         mlx5_txq_release(dev, i);
1207                 priv->txqs_n = 0;
1208                 priv->txqs = NULL;
1209         }
1210         mlx5_proc_priv_uninit(dev);
1211         if (priv->mreg_cp_tbl)
1212                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1213         mlx5_mprq_free_mp(dev);
1214         mlx5_os_free_shared_dr(priv);
1215         if (priv->rss_conf.rss_key != NULL)
1216                 rte_free(priv->rss_conf.rss_key);
1217         if (priv->reta_idx != NULL)
1218                 rte_free(priv->reta_idx);
1219         if (priv->config.vf)
1220                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1221                                        dev->data->mac_addrs,
1222                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1223         if (priv->nl_socket_route >= 0)
1224                 close(priv->nl_socket_route);
1225         if (priv->nl_socket_rdma >= 0)
1226                 close(priv->nl_socket_rdma);
1227         if (priv->vmwa_context)
1228                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1229         ret = mlx5_hrxq_verify(dev);
1230         if (ret)
1231                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1232                         dev->data->port_id);
1233         ret = mlx5_ind_table_obj_verify(dev);
1234         if (ret)
1235                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1236                         dev->data->port_id);
1237         ret = mlx5_rxq_obj_verify(dev);
1238         if (ret)
1239                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1240                         dev->data->port_id);
1241         ret = mlx5_rxq_verify(dev);
1242         if (ret)
1243                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1244                         dev->data->port_id);
1245         ret = mlx5_txq_obj_verify(dev);
1246         if (ret)
1247                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1248                         dev->data->port_id);
1249         ret = mlx5_txq_verify(dev);
1250         if (ret)
1251                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1252                         dev->data->port_id);
1253         ret = mlx5_flow_verify(dev);
1254         if (ret)
1255                 DRV_LOG(WARNING, "port %u some flows still remain",
1256                         dev->data->port_id);
1257         /*
1258          * Free the shared context in last turn, because the cleanup
1259          * routines above may use some shared fields, like
1260          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1261          * ifindex if Netlink fails.
1262          */
1263         mlx5_free_shared_dev_ctx(priv->sh);
1264         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1265                 unsigned int c = 0;
1266                 uint16_t port_id;
1267
1268                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1269                         struct mlx5_priv *opriv =
1270                                 rte_eth_devices[port_id].data->dev_private;
1271
1272                         if (!opriv ||
1273                             opriv->domain_id != priv->domain_id ||
1274                             &rte_eth_devices[port_id] == dev)
1275                                 continue;
1276                         ++c;
1277                         break;
1278                 }
1279                 if (!c)
1280                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1281         }
1282         memset(priv, 0, sizeof(*priv));
1283         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1284         /*
1285          * Reset mac_addrs to NULL such that it is not freed as part of
1286          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1287          * it is freed when dev_private is freed.
1288          */
1289         dev->data->mac_addrs = NULL;
1290 }
1291
1292 /**
1293  * Verify and store value for device argument.
1294  *
1295  * @param[in] key
1296  *   Key argument to verify.
1297  * @param[in] val
1298  *   Value associated with key.
1299  * @param opaque
1300  *   User data.
1301  *
1302  * @return
1303  *   0 on success, a negative errno value otherwise and rte_errno is set.
1304  */
1305 static int
1306 mlx5_args_check(const char *key, const char *val, void *opaque)
1307 {
1308         struct mlx5_dev_config *config = opaque;
1309         unsigned long mod;
1310         signed long tmp;
1311
1312         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1313         if (!strcmp(MLX5_REPRESENTOR, key))
1314                 return 0;
1315         errno = 0;
1316         tmp = strtol(val, NULL, 0);
1317         if (errno) {
1318                 rte_errno = errno;
1319                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1320                 return -rte_errno;
1321         }
1322         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1323                 /* Negative values are acceptable for some keys only. */
1324                 rte_errno = EINVAL;
1325                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1326                 return -rte_errno;
1327         }
1328         mod = tmp >= 0 ? tmp : -tmp;
1329         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1330                 config->cqe_comp = !!tmp;
1331         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1332                 config->cqe_pad = !!tmp;
1333         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1334                 config->hw_padding = !!tmp;
1335         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1336                 config->mprq.enabled = !!tmp;
1337         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1338                 config->mprq.stride_num_n = tmp;
1339         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1340                 config->mprq.stride_size_n = tmp;
1341         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1342                 config->mprq.max_memcpy_len = tmp;
1343         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1344                 config->mprq.min_rxqs_num = tmp;
1345         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1346                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1347                                  " converted to txq_inline_max", key);
1348                 config->txq_inline_max = tmp;
1349         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1350                 config->txq_inline_max = tmp;
1351         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1352                 config->txq_inline_min = tmp;
1353         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1354                 config->txq_inline_mpw = tmp;
1355         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1356                 config->txqs_inline = tmp;
1357         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1358                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1359         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1360                 config->mps = !!tmp;
1361         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1362                 if (tmp != MLX5_TXDB_CACHED &&
1363                     tmp != MLX5_TXDB_NCACHED &&
1364                     tmp != MLX5_TXDB_HEURISTIC) {
1365                         DRV_LOG(ERR, "invalid Tx doorbell "
1366                                      "mapping parameter");
1367                         rte_errno = EINVAL;
1368                         return -rte_errno;
1369                 }
1370                 config->dbnc = tmp;
1371         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1372                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1373         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1374                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1375                                  " converted to txq_inline_mpw", key);
1376                 config->txq_inline_mpw = tmp;
1377         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1378                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1379         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1380                 if (!mod) {
1381                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1382                         rte_errno = EINVAL;
1383                         return -rte_errno;
1384                 }
1385                 config->tx_pp = tmp;
1386         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1387                 config->tx_skew = tmp;
1388         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1389                 config->rx_vec_en = !!tmp;
1390         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1391                 config->l3_vxlan_en = !!tmp;
1392         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1393                 config->vf_nl_en = !!tmp;
1394         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1395                 config->dv_esw_en = !!tmp;
1396         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1397                 config->dv_flow_en = !!tmp;
1398         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1399                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1400                     tmp != MLX5_XMETA_MODE_META16 &&
1401                     tmp != MLX5_XMETA_MODE_META32) {
1402                         DRV_LOG(ERR, "invalid extensive "
1403                                      "metadata parameter");
1404                         rte_errno = EINVAL;
1405                         return -rte_errno;
1406                 }
1407                 config->dv_xmeta_en = tmp;
1408         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1409                 config->lacp_by_user = !!tmp;
1410         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1411                 config->mr_ext_memseg_en = !!tmp;
1412         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1413                 config->max_dump_files_num = tmp;
1414         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1415                 config->lro.timeout = tmp;
1416         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1417                 DRV_LOG(DEBUG, "class argument is %s.", val);
1418         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1419                 config->log_hp_size = tmp;
1420         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1421                 if (tmp != MLX5_RCM_NONE &&
1422                     tmp != MLX5_RCM_LIGHT &&
1423                     tmp != MLX5_RCM_AGGR) {
1424                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1425                         rte_errno = EINVAL;
1426                         return -rte_errno;
1427                 }
1428                 config->reclaim_mode = tmp;
1429         } else {
1430                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1431                 rte_errno = EINVAL;
1432                 return -rte_errno;
1433         }
1434         return 0;
1435 }
1436
1437 /**
1438  * Parse device parameters.
1439  *
1440  * @param config
1441  *   Pointer to device configuration structure.
1442  * @param devargs
1443  *   Device arguments structure.
1444  *
1445  * @return
1446  *   0 on success, a negative errno value otherwise and rte_errno is set.
1447  */
1448 int
1449 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1450 {
1451         const char **params = (const char *[]){
1452                 MLX5_RXQ_CQE_COMP_EN,
1453                 MLX5_RXQ_CQE_PAD_EN,
1454                 MLX5_RXQ_PKT_PAD_EN,
1455                 MLX5_RX_MPRQ_EN,
1456                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1457                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1458                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1459                 MLX5_RXQS_MIN_MPRQ,
1460                 MLX5_TXQ_INLINE,
1461                 MLX5_TXQ_INLINE_MIN,
1462                 MLX5_TXQ_INLINE_MAX,
1463                 MLX5_TXQ_INLINE_MPW,
1464                 MLX5_TXQS_MIN_INLINE,
1465                 MLX5_TXQS_MAX_VEC,
1466                 MLX5_TXQ_MPW_EN,
1467                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1468                 MLX5_TXQ_MAX_INLINE_LEN,
1469                 MLX5_TX_DB_NC,
1470                 MLX5_TX_PP,
1471                 MLX5_TX_SKEW,
1472                 MLX5_TX_VEC_EN,
1473                 MLX5_RX_VEC_EN,
1474                 MLX5_L3_VXLAN_EN,
1475                 MLX5_VF_NL_EN,
1476                 MLX5_DV_ESW_EN,
1477                 MLX5_DV_FLOW_EN,
1478                 MLX5_DV_XMETA_EN,
1479                 MLX5_LACP_BY_USER,
1480                 MLX5_MR_EXT_MEMSEG_EN,
1481                 MLX5_REPRESENTOR,
1482                 MLX5_MAX_DUMP_FILES_NUM,
1483                 MLX5_LRO_TIMEOUT_USEC,
1484                 MLX5_CLASS_ARG_NAME,
1485                 MLX5_HP_BUF_SIZE,
1486                 MLX5_RECLAIM_MEM,
1487                 NULL,
1488         };
1489         struct rte_kvargs *kvlist;
1490         int ret = 0;
1491         int i;
1492
1493         if (devargs == NULL)
1494                 return 0;
1495         /* Following UGLY cast is done to pass checkpatch. */
1496         kvlist = rte_kvargs_parse(devargs->args, params);
1497         if (kvlist == NULL) {
1498                 rte_errno = EINVAL;
1499                 return -rte_errno;
1500         }
1501         /* Process parameters. */
1502         for (i = 0; (params[i] != NULL); ++i) {
1503                 if (rte_kvargs_count(kvlist, params[i])) {
1504                         ret = rte_kvargs_process(kvlist, params[i],
1505                                                  mlx5_args_check, config);
1506                         if (ret) {
1507                                 rte_errno = EINVAL;
1508                                 rte_kvargs_free(kvlist);
1509                                 return -rte_errno;
1510                         }
1511                 }
1512         }
1513         rte_kvargs_free(kvlist);
1514         return 0;
1515 }
1516
1517 /**
1518  * PMD global initialization.
1519  *
1520  * Independent from individual device, this function initializes global
1521  * per-PMD data structures distinguishing primary and secondary processes.
1522  * Hence, each initialization is called once per a process.
1523  *
1524  * @return
1525  *   0 on success, a negative errno value otherwise and rte_errno is set.
1526  */
1527 int
1528 mlx5_init_once(void)
1529 {
1530         struct mlx5_shared_data *sd;
1531         struct mlx5_local_data *ld = &mlx5_local_data;
1532         int ret = 0;
1533
1534         if (mlx5_init_shared_data())
1535                 return -rte_errno;
1536         sd = mlx5_shared_data;
1537         MLX5_ASSERT(sd);
1538         rte_spinlock_lock(&sd->lock);
1539         switch (rte_eal_process_type()) {
1540         case RTE_PROC_PRIMARY:
1541                 if (sd->init_done)
1542                         break;
1543                 LIST_INIT(&sd->mem_event_cb_list);
1544                 rte_rwlock_init(&sd->mem_event_rwlock);
1545                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1546                                                 mlx5_mr_mem_event_cb, NULL);
1547                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1548                                            mlx5_mp_primary_handle);
1549                 if (ret)
1550                         goto out;
1551                 sd->init_done = true;
1552                 break;
1553         case RTE_PROC_SECONDARY:
1554                 if (ld->init_done)
1555                         break;
1556                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1557                                              mlx5_mp_secondary_handle);
1558                 if (ret)
1559                         goto out;
1560                 ++sd->secondary_cnt;
1561                 ld->init_done = true;
1562                 break;
1563         default:
1564                 break;
1565         }
1566 out:
1567         rte_spinlock_unlock(&sd->lock);
1568         return ret;
1569 }
1570
1571 /**
1572  * Configures the minimal amount of data to inline into WQE
1573  * while sending packets.
1574  *
1575  * - the txq_inline_min has the maximal priority, if this
1576  *   key is specified in devargs
1577  * - if DevX is enabled the inline mode is queried from the
1578  *   device (HCA attributes and NIC vport context if needed).
1579  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1580  *   and none (0 bytes) for other NICs
1581  *
1582  * @param spawn
1583  *   Verbs device parameters (name, port, switch_info) to spawn.
1584  * @param config
1585  *   Device configuration parameters.
1586  */
1587 void
1588 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1589                     struct mlx5_dev_config *config)
1590 {
1591         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1592                 /* Application defines size of inlined data explicitly. */
1593                 switch (spawn->pci_dev->id.device_id) {
1594                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1595                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1596                         if (config->txq_inline_min <
1597                                        (int)MLX5_INLINE_HSIZE_L2) {
1598                                 DRV_LOG(DEBUG,
1599                                         "txq_inline_mix aligned to minimal"
1600                                         " ConnectX-4 required value %d",
1601                                         (int)MLX5_INLINE_HSIZE_L2);
1602                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1603                         }
1604                         break;
1605                 }
1606                 goto exit;
1607         }
1608         if (config->hca_attr.eth_net_offloads) {
1609                 /* We have DevX enabled, inline mode queried successfully. */
1610                 switch (config->hca_attr.wqe_inline_mode) {
1611                 case MLX5_CAP_INLINE_MODE_L2:
1612                         /* outer L2 header must be inlined. */
1613                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1614                         goto exit;
1615                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1616                         /* No inline data are required by NIC. */
1617                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1618                         config->hw_vlan_insert =
1619                                 config->hca_attr.wqe_vlan_insert;
1620                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1621                         goto exit;
1622                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1623                         /* inline mode is defined by NIC vport context. */
1624                         if (!config->hca_attr.eth_virt)
1625                                 break;
1626                         switch (config->hca_attr.vport_inline_mode) {
1627                         case MLX5_INLINE_MODE_NONE:
1628                                 config->txq_inline_min =
1629                                         MLX5_INLINE_HSIZE_NONE;
1630                                 goto exit;
1631                         case MLX5_INLINE_MODE_L2:
1632                                 config->txq_inline_min =
1633                                         MLX5_INLINE_HSIZE_L2;
1634                                 goto exit;
1635                         case MLX5_INLINE_MODE_IP:
1636                                 config->txq_inline_min =
1637                                         MLX5_INLINE_HSIZE_L3;
1638                                 goto exit;
1639                         case MLX5_INLINE_MODE_TCP_UDP:
1640                                 config->txq_inline_min =
1641                                         MLX5_INLINE_HSIZE_L4;
1642                                 goto exit;
1643                         case MLX5_INLINE_MODE_INNER_L2:
1644                                 config->txq_inline_min =
1645                                         MLX5_INLINE_HSIZE_INNER_L2;
1646                                 goto exit;
1647                         case MLX5_INLINE_MODE_INNER_IP:
1648                                 config->txq_inline_min =
1649                                         MLX5_INLINE_HSIZE_INNER_L3;
1650                                 goto exit;
1651                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1652                                 config->txq_inline_min =
1653                                         MLX5_INLINE_HSIZE_INNER_L4;
1654                                 goto exit;
1655                         }
1656                 }
1657         }
1658         /*
1659          * We get here if we are unable to deduce
1660          * inline data size with DevX. Try PCI ID
1661          * to determine old NICs.
1662          */
1663         switch (spawn->pci_dev->id.device_id) {
1664         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1665         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1666         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1667         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1668                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1669                 config->hw_vlan_insert = 0;
1670                 break;
1671         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1672         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1673         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1674         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1675                 /*
1676                  * These NICs support VLAN insertion from WQE and
1677                  * report the wqe_vlan_insert flag. But there is the bug
1678                  * and PFC control may be broken, so disable feature.
1679                  */
1680                 config->hw_vlan_insert = 0;
1681                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1682                 break;
1683         default:
1684                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1685                 break;
1686         }
1687 exit:
1688         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1689 }
1690
1691 /**
1692  * Configures the metadata mask fields in the shared context.
1693  *
1694  * @param [in] dev
1695  *   Pointer to Ethernet device.
1696  */
1697 void
1698 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1699 {
1700         struct mlx5_priv *priv = dev->data->dev_private;
1701         struct mlx5_dev_ctx_shared *sh = priv->sh;
1702         uint32_t meta, mark, reg_c0;
1703
1704         reg_c0 = ~priv->vport_meta_mask;
1705         switch (priv->config.dv_xmeta_en) {
1706         case MLX5_XMETA_MODE_LEGACY:
1707                 meta = UINT32_MAX;
1708                 mark = MLX5_FLOW_MARK_MASK;
1709                 break;
1710         case MLX5_XMETA_MODE_META16:
1711                 meta = reg_c0 >> rte_bsf32(reg_c0);
1712                 mark = MLX5_FLOW_MARK_MASK;
1713                 break;
1714         case MLX5_XMETA_MODE_META32:
1715                 meta = UINT32_MAX;
1716                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1717                 break;
1718         default:
1719                 meta = 0;
1720                 mark = 0;
1721                 MLX5_ASSERT(false);
1722                 break;
1723         }
1724         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1725                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1726                                  sh->dv_mark_mask, mark);
1727         else
1728                 sh->dv_mark_mask = mark;
1729         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1730                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1731                                  sh->dv_meta_mask, meta);
1732         else
1733                 sh->dv_meta_mask = meta;
1734         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1735                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1736                                  sh->dv_meta_mask, reg_c0);
1737         else
1738                 sh->dv_regc0_mask = reg_c0;
1739         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1740         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1741         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1742         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1743 }
1744
1745 int
1746 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1747 {
1748         static const char *const dynf_names[] = {
1749                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1750                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1751                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1752         };
1753         unsigned int i;
1754
1755         if (n < RTE_DIM(dynf_names))
1756                 return -ENOMEM;
1757         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1758                 if (names[i] == NULL)
1759                         return -EINVAL;
1760                 strcpy(names[i], dynf_names[i]);
1761         }
1762         return RTE_DIM(dynf_names);
1763 }
1764
1765 /**
1766  * Comparison callback to sort device data.
1767  *
1768  * This is meant to be used with qsort().
1769  *
1770  * @param a[in]
1771  *   Pointer to pointer to first data object.
1772  * @param b[in]
1773  *   Pointer to pointer to second data object.
1774  *
1775  * @return
1776  *   0 if both objects are equal, less than 0 if the first argument is less
1777  *   than the second, greater than 0 otherwise.
1778  */
1779 int
1780 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1781                               struct mlx5_dev_config *config)
1782 {
1783         struct mlx5_dev_ctx_shared *sh = priv->sh;
1784         struct mlx5_dev_config *sh_conf = NULL;
1785         uint16_t port_id;
1786
1787         MLX5_ASSERT(sh);
1788         /* Nothing to compare for the single/first device. */
1789         if (sh->refcnt == 1)
1790                 return 0;
1791         /* Find the device with shared context. */
1792         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1793                 struct mlx5_priv *opriv =
1794                         rte_eth_devices[port_id].data->dev_private;
1795
1796                 if (opriv && opriv != priv && opriv->sh == sh) {
1797                         sh_conf = &opriv->config;
1798                         break;
1799                 }
1800         }
1801         if (!sh_conf)
1802                 return 0;
1803         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1804                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1805                              " for shared %s context", sh->ibdev_name);
1806                 rte_errno = EINVAL;
1807                 return rte_errno;
1808         }
1809         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1810                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1811                              " for shared %s context", sh->ibdev_name);
1812                 rte_errno = EINVAL;
1813                 return rte_errno;
1814         }
1815         return 0;
1816 }
1817
1818 /**
1819  * Look for the ethernet device belonging to mlx5 driver.
1820  *
1821  * @param[in] port_id
1822  *   port_id to start looking for device.
1823  * @param[in] pci_dev
1824  *   Pointer to the hint PCI device. When device is being probed
1825  *   the its siblings (master and preceding representors might
1826  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1827  *   is not completed yet, for this case match on hint PCI
1828  *   device may be used to detect sibling device.
1829  *
1830  * @return
1831  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1832  */
1833 uint16_t
1834 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1835 {
1836         while (port_id < RTE_MAX_ETHPORTS) {
1837                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1838
1839                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1840                     dev->device &&
1841                     (dev->device == &pci_dev->device ||
1842                      (dev->device->driver &&
1843                      dev->device->driver->name &&
1844                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1845                         break;
1846                 port_id++;
1847         }
1848         if (port_id >= RTE_MAX_ETHPORTS)
1849                 return RTE_MAX_ETHPORTS;
1850         return port_id;
1851 }
1852
1853 /**
1854  * DPDK callback to remove a PCI device.
1855  *
1856  * This function removes all Ethernet devices belong to a given PCI device.
1857  *
1858  * @param[in] pci_dev
1859  *   Pointer to the PCI device.
1860  *
1861  * @return
1862  *   0 on success, the function cannot fail.
1863  */
1864 static int
1865 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1866 {
1867         uint16_t port_id;
1868
1869         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1870                 /*
1871                  * mlx5_dev_close() is not registered to secondary process,
1872                  * call the close function explicitly for secondary process.
1873                  */
1874                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1875                         mlx5_dev_close(&rte_eth_devices[port_id]);
1876                 else
1877                         rte_eth_dev_close(port_id);
1878         }
1879         return 0;
1880 }
1881
1882 static const struct rte_pci_id mlx5_pci_id_map[] = {
1883         {
1884                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1885                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1886         },
1887         {
1888                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1889                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1890         },
1891         {
1892                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1893                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
1894         },
1895         {
1896                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1897                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
1898         },
1899         {
1900                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1901                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
1902         },
1903         {
1904                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1905                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
1906         },
1907         {
1908                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1909                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
1910         },
1911         {
1912                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1913                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
1914         },
1915         {
1916                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1917                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
1918         },
1919         {
1920                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1921                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
1922         },
1923         {
1924                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1925                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
1926         },
1927         {
1928                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1929                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
1930         },
1931         {
1932                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1933                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
1934         },
1935         {
1936                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1937                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
1938         },
1939         {
1940                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1941                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
1942         },
1943         {
1944                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1945                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
1946         },
1947         {
1948                 .vendor_id = 0
1949         }
1950 };
1951
1952 struct rte_pci_driver mlx5_driver = {
1953         .driver = {
1954                 .name = MLX5_DRIVER_NAME
1955         },
1956         .id_table = mlx5_pci_id_map,
1957         .probe = mlx5_os_pci_probe,
1958         .remove = mlx5_pci_remove,
1959         .dma_map = mlx5_dma_map,
1960         .dma_unmap = mlx5_dma_unmap,
1961         .drv_flags = PCI_DRV_FLAGS,
1962 };
1963
1964 /* Initialize driver log type. */
1965 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
1966
1967 /**
1968  * Driver initialization routine.
1969  */
1970 RTE_INIT(rte_mlx5_pmd_init)
1971 {
1972         /* Build the static tables for Verbs conversion. */
1973         mlx5_set_ptype_table();
1974         mlx5_set_cksum_table();
1975         mlx5_set_swp_types_table();
1976         if (mlx5_glue)
1977                 rte_pci_register(&mlx5_driver);
1978 }
1979
1980 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
1981 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
1982 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");