1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
41 #include <mlx5_common_os.h>
42 #include <mlx5_common_mp.h>
44 #include "mlx5_defs.h"
46 #include "mlx5_utils.h"
47 #include "mlx5_rxtx.h"
48 #include "mlx5_autoconf.h"
50 #include "mlx5_flow.h"
51 #include "rte_pmd_mlx5.h"
53 /* Device parameter to enable RX completion queue compression. */
54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
56 /* Device parameter to enable RX completion entry padding to 128B. */
57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
59 /* Device parameter to enable padding Rx packet to cacheline size. */
60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
62 /* Device parameter to enable Multi-Packet Rx queue. */
63 #define MLX5_RX_MPRQ_EN "mprq_en"
65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
77 /* Device parameter to configure inline send. Deprecated, ignored.*/
78 #define MLX5_TXQ_INLINE "txq_inline"
80 /* Device parameter to limit packet size to inline with ordinary SEND. */
81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
83 /* Device parameter to configure minimal data size to inline. */
84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
90 * Device parameter to configure the number of TX queues threshold for
91 * enabling inline send.
93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
96 * Device parameter to configure the number of TX queues threshold for
97 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
101 /* Device parameter to enable multi-packet send WQEs. */
102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
105 * Device parameter to force doorbell register mapping
106 * to non-cahed region eliminating the extra write memory barrier.
108 #define MLX5_TX_DB_NC "tx_db_nc"
111 * Device parameter to include 2 dsegs in the title WQEBB.
112 * Deprecated, ignored.
114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
117 * Device parameter to limit the size of inlining packet.
118 * Deprecated, ignored.
120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
123 * Device parameter to enable Tx scheduling on timestamps
124 * and specify the packet pacing granularity in nanoseconds.
126 #define MLX5_TX_PP "tx_pp"
129 * Device parameter to specify skew in nanoseconds on Tx datapath,
130 * it represents the time between SQ start WQE processing and
131 * appearing actual packet data on the wire.
133 #define MLX5_TX_SKEW "tx_skew"
136 * Device parameter to enable hardware Tx vector.
137 * Deprecated, ignored (no vectorized Tx routines anymore).
139 #define MLX5_TX_VEC_EN "tx_vec_en"
141 /* Device parameter to enable hardware Rx vector. */
142 #define MLX5_RX_VEC_EN "rx_vec_en"
144 /* Allow L3 VXLAN flow creation. */
145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
147 /* Activate DV E-Switch flow steering. */
148 #define MLX5_DV_ESW_EN "dv_esw_en"
150 /* Activate DV flow steering. */
151 #define MLX5_DV_FLOW_EN "dv_flow_en"
153 /* Enable extensive flow metadata support. */
154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
156 /* Device parameter to let the user manage the lacp traffic of bonded device */
157 #define MLX5_LACP_BY_USER "lacp_by_user"
159 /* Activate Netlink support in VF mode. */
160 #define MLX5_VF_NL_EN "vf_nl_en"
162 /* Enable extending memsegs when creating a MR. */
163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
165 /* Select port representors to instantiate. */
166 #define MLX5_REPRESENTOR "representor"
168 /* Device parameter to configure the maximum number of dump files per queue. */
169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
171 /* Configure timeout of LRO session (in microseconds). */
172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
175 * Device parameter to configure the total data buffer size for a single
176 * hairpin queue (logarithm value).
178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
180 /* Flow memory reclaim mode. */
181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
183 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
185 /* Shared memory between primary and secondary processes. */
186 struct mlx5_shared_data *mlx5_shared_data;
188 /* Spinlock for mlx5_shared_data allocation. */
189 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
191 /* Process local data for secondary processes. */
192 static struct mlx5_local_data mlx5_local_data;
194 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
195 LIST_HEAD_INITIALIZER();
196 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
199 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
201 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
207 .malloc = rte_malloc_socket,
209 .type = "mlx5_encap_decap_ipool",
212 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
218 .malloc = rte_malloc_socket,
220 .type = "mlx5_push_vlan_ipool",
223 .size = sizeof(struct mlx5_flow_dv_tag_resource),
229 .malloc = rte_malloc_socket,
231 .type = "mlx5_tag_ipool",
234 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
240 .malloc = rte_malloc_socket,
242 .type = "mlx5_port_id_ipool",
245 .size = sizeof(struct mlx5_flow_tbl_data_entry),
251 .malloc = rte_malloc_socket,
253 .type = "mlx5_jump_ipool",
257 .size = sizeof(struct mlx5_flow_meter),
263 .malloc = rte_malloc_socket,
265 .type = "mlx5_meter_ipool",
268 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
274 .malloc = rte_malloc_socket,
276 .type = "mlx5_mcp_ipool",
279 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
285 .malloc = rte_malloc_socket,
287 .type = "mlx5_hrxq_ipool",
291 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
292 * It set in run time according to PCI function configuration.
300 .malloc = rte_malloc_socket,
302 .type = "mlx5_flow_handle_ipool",
305 .size = sizeof(struct rte_flow),
309 .malloc = rte_malloc_socket,
311 .type = "rte_flow_ipool",
316 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
317 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
319 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
322 * Allocate ID pool structure.
325 * The maximum id can be allocated from the pool.
328 * Pointer to pool object, NULL value otherwise.
330 struct mlx5_flow_id_pool *
331 mlx5_flow_id_pool_alloc(uint32_t max_id)
333 struct mlx5_flow_id_pool *pool;
336 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
337 RTE_CACHE_LINE_SIZE);
339 DRV_LOG(ERR, "can't allocate id pool");
343 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
344 RTE_CACHE_LINE_SIZE);
346 DRV_LOG(ERR, "can't allocate mem for id pool");
350 pool->free_arr = mem;
351 pool->curr = pool->free_arr;
352 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
353 pool->base_index = 0;
354 pool->max_id = max_id;
362 * Release ID pool structure.
365 * Pointer to flow id pool object to free.
368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
370 rte_free(pool->free_arr);
378 * Pointer to flow id pool.
383 * 0 on success, error value otherwise.
386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
388 if (pool->curr == pool->free_arr) {
389 if (pool->base_index == pool->max_id) {
391 DRV_LOG(ERR, "no free id");
394 *id = ++pool->base_index;
397 *id = *(--pool->curr);
405 * Pointer to flow id pool.
410 * 0 on success, error value otherwise.
413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
419 if (pool->curr == pool->last) {
420 size = pool->curr - pool->free_arr;
421 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
422 MLX5_ASSERT(size2 > size);
423 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
425 DRV_LOG(ERR, "can't allocate mem for id pool");
429 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
430 rte_free(pool->free_arr);
431 pool->free_arr = mem;
432 pool->curr = pool->free_arr + size;
433 pool->last = pool->free_arr + size2;
441 * Initialize the shared aging list information per port.
444 * Pointer to mlx5_dev_ctx_shared object.
447 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
450 struct mlx5_age_info *age_info;
452 for (i = 0; i < sh->max_port; i++) {
453 age_info = &sh->port[i].age_info;
455 TAILQ_INIT(&age_info->aged_counters);
456 rte_spinlock_init(&age_info->aged_sl);
457 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
462 * Initialize the counters management structure.
465 * Pointer to mlx5_dev_ctx_shared object to free
468 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
472 memset(&sh->cmng, 0, sizeof(sh->cmng));
473 TAILQ_INIT(&sh->cmng.flow_counters);
474 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
475 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
476 sh->cmng.ccont[i].max_id = -1;
477 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
478 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
479 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
480 TAILQ_INIT(&sh->cmng.ccont[i].counters);
481 rte_spinlock_init(&sh->cmng.ccont[i].csl);
486 * Destroy all the resources allocated for a counter memory management.
489 * Pointer to the memory management structure.
492 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
494 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
496 LIST_REMOVE(mng, next);
497 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
498 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
503 * Close and release all the resources of the counters management.
506 * Pointer to mlx5_dev_ctx_shared object to free.
509 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
511 struct mlx5_counter_stats_mem_mng *mng;
518 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
519 if (rte_errno != EINPROGRESS)
523 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
524 struct mlx5_flow_counter_pool *pool;
525 uint32_t batch = !!(i > 1);
527 if (!sh->cmng.ccont[i].pools)
529 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
531 if (batch && pool->min_dcs)
532 claim_zero(mlx5_devx_cmd_destroy
534 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
535 if (MLX5_POOL_GET_CNT(pool, j)->action)
537 (mlx5_glue->destroy_flow_action
540 if (!batch && MLX5_GET_POOL_CNT_EXT
542 claim_zero(mlx5_devx_cmd_destroy
543 (MLX5_GET_POOL_CNT_EXT
546 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
548 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
550 rte_free(sh->cmng.ccont[i].pools);
552 mng = LIST_FIRST(&sh->cmng.mem_mngs);
554 mlx5_flow_destroy_counter_stat_mem_mng(mng);
555 mng = LIST_FIRST(&sh->cmng.mem_mngs);
557 memset(&sh->cmng, 0, sizeof(sh->cmng));
561 * Initialize the flow resources' indexed mempool.
564 * Pointer to mlx5_dev_ctx_shared object.
566 * Pointer to user dev config.
569 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
570 const struct mlx5_dev_config *config)
573 struct mlx5_indexed_pool_config cfg;
575 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
576 cfg = mlx5_ipool_cfg[i];
581 * Set MLX5_IPOOL_MLX5_FLOW ipool size
582 * according to PCI function flow configuration.
584 case MLX5_IPOOL_MLX5_FLOW:
585 cfg.size = config->dv_flow_en ?
586 sizeof(struct mlx5_flow_handle) :
587 MLX5_FLOW_HANDLE_VERBS_SIZE;
590 if (config->reclaim_mode)
591 cfg.release_mem_en = 1;
592 sh->ipool[i] = mlx5_ipool_create(&cfg);
597 * Release the flow resources' indexed mempool.
600 * Pointer to mlx5_dev_ctx_shared object.
603 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
607 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
608 mlx5_ipool_destroy(sh->ipool[i]);
612 * Check if dynamic flex parser for eCPRI already exists.
615 * Pointer to Ethernet device structure.
618 * true on exists, false on not.
621 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
623 struct mlx5_priv *priv = dev->data->dev_private;
624 struct mlx5_flex_parser_profiles *prf =
625 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
631 * Allocation of a flex parser for eCPRI. Once created, this parser related
632 * resources will be held until the device is closed.
635 * Pointer to Ethernet device structure.
638 * 0 on success, a negative errno value otherwise and rte_errno is set.
641 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
643 struct mlx5_priv *priv = dev->data->dev_private;
644 struct mlx5_flex_parser_profiles *prf =
645 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
646 struct mlx5_devx_graph_node_attr node = {
647 .modify_field_select = 0,
652 if (!priv->config.hca_attr.parse_graph_flex_node) {
653 DRV_LOG(ERR, "Dynamic flex parser is not supported "
654 "for device %s.", priv->dev_data->name);
657 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
658 /* 8 bytes now: 4B common header + 4B message body header. */
659 node.header_length_base_value = 0x8;
660 /* After MAC layer: Ether / VLAN. */
661 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
662 /* Type of compared condition should be 0xAEFE in the L2 layer. */
663 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
664 /* Sample #0: type in common header. */
665 node.sample[0].flow_match_sample_en = 1;
667 node.sample[0].flow_match_sample_offset_mode = 0x0;
668 /* Only the 2nd byte will be used. */
669 node.sample[0].flow_match_sample_field_base_offset = 0x0;
670 /* Sample #1: message payload. */
671 node.sample[1].flow_match_sample_en = 1;
673 node.sample[1].flow_match_sample_offset_mode = 0x0;
675 * Only the first two bytes will be used right now, and its offset will
676 * start after the common header that with the length of a DW(u32).
678 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
679 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
681 DRV_LOG(ERR, "Failed to create flex parser node object.");
682 return (rte_errno == 0) ? -ENODEV : -rte_errno;
685 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
687 DRV_LOG(ERR, "Failed to query sample IDs.");
688 return (rte_errno == 0) ? -ENODEV : -rte_errno;
690 prf->offset[0] = 0x0;
691 prf->offset[1] = sizeof(uint32_t);
692 prf->ids[0] = ids[0];
693 prf->ids[1] = ids[1];
698 * Destroy the flex parser node, including the parser itself, input / output
699 * arcs and DW samples. Resources could be reused then.
702 * Pointer to Ethernet device structure.
705 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
707 struct mlx5_priv *priv = dev->data->dev_private;
708 struct mlx5_flex_parser_profiles *prf =
709 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
712 mlx5_devx_cmd_destroy(prf->obj);
717 * Allocate shared device context. If there is multiport device the
718 * master and representors will share this context, if there is single
719 * port dedicated device, the context will be used by only given
720 * port due to unification.
722 * Routine first searches the context for the specified device name,
723 * if found the shared context assumed and reference counter is incremented.
724 * If no context found the new one is created and initialized with specified
725 * device context and parameters.
728 * Pointer to the device attributes (name, port, etc).
730 * Pointer to device configuration structure.
733 * Pointer to mlx5_dev_ctx_shared object on success,
734 * otherwise NULL and rte_errno is set.
736 struct mlx5_dev_ctx_shared *
737 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
738 const struct mlx5_dev_config *config)
740 struct mlx5_dev_ctx_shared *sh;
743 struct mlx5_devx_tis_attr tis_attr = { 0 };
746 /* Secondary process should not create the shared context. */
747 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
748 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
749 /* Search for IB context by device name. */
750 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
751 if (!strcmp(sh->ibdev_name,
752 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
757 /* No device found, we have to create new shared context. */
758 MLX5_ASSERT(spawn->max_port);
759 sh = rte_zmalloc("ethdev shared ib context",
760 sizeof(struct mlx5_dev_ctx_shared) +
762 sizeof(struct mlx5_dev_shared_port),
763 RTE_CACHE_LINE_SIZE);
765 DRV_LOG(ERR, "shared context allocation failure");
769 err = mlx5_os_open_device(spawn, config, sh);
772 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
774 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
778 sh->max_port = spawn->max_port;
779 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
780 sizeof(sh->ibdev_name) - 1);
781 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
782 sizeof(sh->ibdev_path) - 1);
784 * Setting port_id to max unallowed value means
785 * there is no interrupt subhandler installed for
786 * the given port index i.
788 for (i = 0; i < sh->max_port; i++) {
789 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
790 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
792 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
793 if (sh->pd == NULL) {
794 DRV_LOG(ERR, "PD allocation failure");
799 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
801 DRV_LOG(ERR, "Fail to extract pdn from PD");
804 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
806 DRV_LOG(ERR, "TD allocation failure");
810 tis_attr.transport_domain = sh->td->id;
811 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
813 DRV_LOG(ERR, "TIS allocation failure");
817 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
819 DRV_LOG(ERR, "Failed to allocate DevX UAR.");
824 sh->flow_id_pool = mlx5_flow_id_pool_alloc
825 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
826 if (!sh->flow_id_pool) {
827 DRV_LOG(ERR, "can't create flow id pool");
832 /* Initialize UAR access locks for 32bit implementations. */
833 rte_spinlock_init(&sh->uar_lock_cq);
834 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
835 rte_spinlock_init(&sh->uar_lock[i]);
838 * Once the device is added to the list of memory event
839 * callback, its global MR cache table cannot be expanded
840 * on the fly because of deadlock. If it overflows, lookup
841 * should be done by searching MR list linearly, which is slow.
843 * At this point the device is not added to the memory
844 * event list yet, context is just being created.
846 err = mlx5_mr_btree_init(&sh->share_cache.cache,
847 MLX5_MR_BTREE_CACHE_N * 2,
848 spawn->pci_dev->device.numa_node);
853 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
854 &sh->share_cache.dereg_mr_cb);
855 mlx5_os_dev_shared_handler_install(sh);
856 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
857 if (!sh->cnt_id_tbl) {
861 mlx5_flow_aging_init(sh);
862 mlx5_flow_counters_mng_init(sh);
863 mlx5_flow_ipool_create(sh, config);
864 /* Add device to memory callback list. */
865 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
866 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
868 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
869 /* Add context to the global device list. */
870 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
872 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
875 pthread_mutex_destroy(&sh->txpp.mutex);
876 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
878 if (sh->cnt_id_tbl) {
879 mlx5_l3t_destroy(sh->cnt_id_tbl);
880 sh->cnt_id_tbl = NULL;
883 mlx5_glue->devx_free_uar(sh->tx_uar);
887 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
889 claim_zero(mlx5_devx_cmd_destroy(sh->td));
891 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
893 claim_zero(mlx5_glue->close_device(sh->ctx));
894 if (sh->flow_id_pool)
895 mlx5_flow_id_pool_release(sh->flow_id_pool);
897 MLX5_ASSERT(err > 0);
903 * Free shared IB device context. Decrement counter and if zero free
904 * all allocated resources and close handles.
907 * Pointer to mlx5_dev_ctx_shared object to free
910 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
912 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
913 #ifdef RTE_LIBRTE_MLX5_DEBUG
914 /* Check the object presence in the list. */
915 struct mlx5_dev_ctx_shared *lctx;
917 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
922 DRV_LOG(ERR, "Freeing non-existing shared IB context");
927 MLX5_ASSERT(sh->refcnt);
928 /* Secondary process should not free the shared context. */
929 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
932 /* Remove from memory callback device list. */
933 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
934 LIST_REMOVE(sh, mem_event_cb);
935 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
936 /* Release created Memory Regions. */
937 mlx5_mr_release_cache(&sh->share_cache);
938 /* Remove context from the global device list. */
939 LIST_REMOVE(sh, next);
941 * Ensure there is no async event handler installed.
942 * Only primary process handles async device events.
944 mlx5_flow_counters_mng_close(sh);
945 mlx5_flow_ipool_destroy(sh);
946 mlx5_os_dev_shared_handler_uninstall(sh);
947 if (sh->cnt_id_tbl) {
948 mlx5_l3t_destroy(sh->cnt_id_tbl);
949 sh->cnt_id_tbl = NULL;
952 mlx5_glue->devx_free_uar(sh->tx_uar);
956 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
958 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
960 claim_zero(mlx5_devx_cmd_destroy(sh->td));
962 claim_zero(mlx5_glue->close_device(sh->ctx));
963 if (sh->flow_id_pool)
964 mlx5_flow_id_pool_release(sh->flow_id_pool);
965 pthread_mutex_destroy(&sh->txpp.mutex);
968 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
972 * Destroy table hash list and all the root entries per domain.
975 * Pointer to the private device data structure.
978 mlx5_free_table_hash_list(struct mlx5_priv *priv)
980 struct mlx5_dev_ctx_shared *sh = priv->sh;
981 struct mlx5_flow_tbl_data_entry *tbl_data;
982 union mlx5_flow_tbl_key table_key = {
990 struct mlx5_hlist_entry *pos;
994 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
996 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
998 MLX5_ASSERT(tbl_data);
999 mlx5_hlist_remove(sh->flow_tbls, pos);
1002 table_key.direction = 1;
1003 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1005 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1007 MLX5_ASSERT(tbl_data);
1008 mlx5_hlist_remove(sh->flow_tbls, pos);
1011 table_key.direction = 0;
1012 table_key.domain = 1;
1013 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1015 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1017 MLX5_ASSERT(tbl_data);
1018 mlx5_hlist_remove(sh->flow_tbls, pos);
1021 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1025 * Initialize flow table hash list and create the root tables entry
1029 * Pointer to the private device data structure.
1032 * Zero on success, positive error code otherwise.
1035 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1037 struct mlx5_dev_ctx_shared *sh = priv->sh;
1038 char s[MLX5_HLIST_NAMESIZE];
1042 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1043 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1044 if (!sh->flow_tbls) {
1045 DRV_LOG(ERR, "flow tables with hash creation failed.");
1049 #ifndef HAVE_MLX5DV_DR
1051 * In case we have not DR support, the zero tables should be created
1052 * because DV expect to see them even if they cannot be created by
1055 union mlx5_flow_tbl_key table_key = {
1063 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
1064 sizeof(*tbl_data), 0);
1070 tbl_data->entry.key = table_key.v64;
1071 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1074 rte_atomic32_init(&tbl_data->tbl.refcnt);
1075 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1076 table_key.direction = 1;
1077 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1082 tbl_data->entry.key = table_key.v64;
1083 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1086 rte_atomic32_init(&tbl_data->tbl.refcnt);
1087 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1088 table_key.direction = 0;
1089 table_key.domain = 1;
1090 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1095 tbl_data->entry.key = table_key.v64;
1096 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1099 rte_atomic32_init(&tbl_data->tbl.refcnt);
1100 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1103 mlx5_free_table_hash_list(priv);
1104 #endif /* HAVE_MLX5DV_DR */
1109 * Initialize shared data between primary and secondary process.
1111 * A memzone is reserved by primary process and secondary processes attach to
1115 * 0 on success, a negative errno value otherwise and rte_errno is set.
1118 mlx5_init_shared_data(void)
1120 const struct rte_memzone *mz;
1123 rte_spinlock_lock(&mlx5_shared_data_lock);
1124 if (mlx5_shared_data == NULL) {
1125 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1126 /* Allocate shared memory. */
1127 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1128 sizeof(*mlx5_shared_data),
1132 "Cannot allocate mlx5 shared data");
1136 mlx5_shared_data = mz->addr;
1137 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1138 rte_spinlock_init(&mlx5_shared_data->lock);
1140 /* Lookup allocated shared memory. */
1141 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1144 "Cannot attach mlx5 shared data");
1148 mlx5_shared_data = mz->addr;
1149 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1153 rte_spinlock_unlock(&mlx5_shared_data_lock);
1158 * Retrieve integer value from environment variable.
1161 * Environment variable name.
1164 * Integer value, 0 if the variable is not set.
1167 mlx5_getenv_int(const char *name)
1169 const char *val = getenv(name);
1177 * DPDK callback to add udp tunnel port
1180 * A pointer to eth_dev
1181 * @param[in] udp_tunnel
1182 * A pointer to udp tunnel
1185 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1188 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1189 struct rte_eth_udp_tunnel *udp_tunnel)
1191 MLX5_ASSERT(udp_tunnel != NULL);
1192 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1193 udp_tunnel->udp_port == 4789)
1195 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1196 udp_tunnel->udp_port == 4790)
1202 * Initialize process private data structure.
1205 * Pointer to Ethernet device structure.
1208 * 0 on success, a negative errno value otherwise and rte_errno is set.
1211 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1213 struct mlx5_priv *priv = dev->data->dev_private;
1214 struct mlx5_proc_priv *ppriv;
1218 * UAR register table follows the process private structure. BlueFlame
1219 * registers for Tx queues are stored in the table.
1222 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1223 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1224 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1229 ppriv->uar_table_sz = ppriv_size;
1230 dev->process_private = ppriv;
1235 * Un-initialize process private data structure.
1238 * Pointer to Ethernet device structure.
1241 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1243 if (!dev->process_private)
1245 rte_free(dev->process_private);
1246 dev->process_private = NULL;
1250 * DPDK callback to close the device.
1252 * Destroy all queues and objects, free memory.
1255 * Pointer to Ethernet device structure.
1258 mlx5_dev_close(struct rte_eth_dev *dev)
1260 struct mlx5_priv *priv = dev->data->dev_private;
1264 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1265 /* Check if process_private released. */
1266 if (!dev->process_private)
1268 mlx5_tx_uar_uninit_secondary(dev);
1269 mlx5_proc_priv_uninit(dev);
1270 rte_eth_dev_release_port(dev);
1275 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1277 ((priv->sh->ctx != NULL) ?
1278 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1280 * If default mreg copy action is removed at the stop stage,
1281 * the search will return none and nothing will be done anymore.
1283 mlx5_flow_stop_default(dev);
1284 mlx5_traffic_disable(dev);
1286 * If all the flows are already flushed in the device stop stage,
1287 * then this will return directly without any action.
1289 mlx5_flow_list_flush(dev, &priv->flows, true);
1290 mlx5_flow_meter_flush(dev, NULL);
1291 /* Free the intermediate buffers for flow creation. */
1292 mlx5_flow_free_intermediate(dev);
1293 /* Prevent crashes when queues are still in use. */
1294 dev->rx_pkt_burst = removed_rx_burst;
1295 dev->tx_pkt_burst = removed_tx_burst;
1297 /* Disable datapath on secondary process. */
1298 mlx5_mp_req_stop_rxtx(dev);
1299 /* Free the eCPRI flex parser resource. */
1300 mlx5_flex_parser_ecpri_release(dev);
1301 if (priv->rxqs != NULL) {
1302 /* XXX race condition if mlx5_rx_burst() is still running. */
1304 for (i = 0; (i != priv->rxqs_n); ++i)
1305 mlx5_rxq_release(dev, i);
1309 if (priv->txqs != NULL) {
1310 /* XXX race condition if mlx5_tx_burst() is still running. */
1312 for (i = 0; (i != priv->txqs_n); ++i)
1313 mlx5_txq_release(dev, i);
1317 mlx5_proc_priv_uninit(dev);
1318 if (priv->mreg_cp_tbl)
1319 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1320 mlx5_mprq_free_mp(dev);
1321 mlx5_os_free_shared_dr(priv);
1322 if (priv->rss_conf.rss_key != NULL)
1323 rte_free(priv->rss_conf.rss_key);
1324 if (priv->reta_idx != NULL)
1325 rte_free(priv->reta_idx);
1326 if (priv->config.vf)
1327 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1328 dev->data->mac_addrs,
1329 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1330 if (priv->nl_socket_route >= 0)
1331 close(priv->nl_socket_route);
1332 if (priv->nl_socket_rdma >= 0)
1333 close(priv->nl_socket_rdma);
1334 if (priv->vmwa_context)
1335 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1336 ret = mlx5_hrxq_verify(dev);
1338 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1339 dev->data->port_id);
1340 ret = mlx5_ind_table_obj_verify(dev);
1342 DRV_LOG(WARNING, "port %u some indirection table still remain",
1343 dev->data->port_id);
1344 ret = mlx5_rxq_obj_verify(dev);
1346 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1347 dev->data->port_id);
1348 ret = mlx5_rxq_verify(dev);
1350 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1351 dev->data->port_id);
1352 ret = mlx5_txq_obj_verify(dev);
1354 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1355 dev->data->port_id);
1356 ret = mlx5_txq_verify(dev);
1358 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1359 dev->data->port_id);
1360 ret = mlx5_flow_verify(dev);
1362 DRV_LOG(WARNING, "port %u some flows still remain",
1363 dev->data->port_id);
1365 * Free the shared context in last turn, because the cleanup
1366 * routines above may use some shared fields, like
1367 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1368 * ifindex if Netlink fails.
1370 mlx5_free_shared_dev_ctx(priv->sh);
1371 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1375 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1376 struct mlx5_priv *opriv =
1377 rte_eth_devices[port_id].data->dev_private;
1380 opriv->domain_id != priv->domain_id ||
1381 &rte_eth_devices[port_id] == dev)
1387 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1389 memset(priv, 0, sizeof(*priv));
1390 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1392 * Reset mac_addrs to NULL such that it is not freed as part of
1393 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1394 * it is freed when dev_private is freed.
1396 dev->data->mac_addrs = NULL;
1400 * Verify and store value for device argument.
1403 * Key argument to verify.
1405 * Value associated with key.
1410 * 0 on success, a negative errno value otherwise and rte_errno is set.
1413 mlx5_args_check(const char *key, const char *val, void *opaque)
1415 struct mlx5_dev_config *config = opaque;
1419 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1420 if (!strcmp(MLX5_REPRESENTOR, key))
1423 tmp = strtol(val, NULL, 0);
1426 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1429 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1430 /* Negative values are acceptable for some keys only. */
1432 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1435 mod = tmp >= 0 ? tmp : -tmp;
1436 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1437 config->cqe_comp = !!tmp;
1438 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1439 config->cqe_pad = !!tmp;
1440 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1441 config->hw_padding = !!tmp;
1442 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1443 config->mprq.enabled = !!tmp;
1444 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1445 config->mprq.stride_num_n = tmp;
1446 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1447 config->mprq.stride_size_n = tmp;
1448 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1449 config->mprq.max_memcpy_len = tmp;
1450 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1451 config->mprq.min_rxqs_num = tmp;
1452 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1453 DRV_LOG(WARNING, "%s: deprecated parameter,"
1454 " converted to txq_inline_max", key);
1455 config->txq_inline_max = tmp;
1456 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1457 config->txq_inline_max = tmp;
1458 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1459 config->txq_inline_min = tmp;
1460 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1461 config->txq_inline_mpw = tmp;
1462 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1463 config->txqs_inline = tmp;
1464 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1465 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1466 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1467 config->mps = !!tmp;
1468 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1469 if (tmp != MLX5_TXDB_CACHED &&
1470 tmp != MLX5_TXDB_NCACHED &&
1471 tmp != MLX5_TXDB_HEURISTIC) {
1472 DRV_LOG(ERR, "invalid Tx doorbell "
1473 "mapping parameter");
1478 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1479 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1480 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1481 DRV_LOG(WARNING, "%s: deprecated parameter,"
1482 " converted to txq_inline_mpw", key);
1483 config->txq_inline_mpw = tmp;
1484 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1485 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1486 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1488 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1492 config->tx_pp = tmp;
1493 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1494 config->tx_skew = tmp;
1495 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1496 config->rx_vec_en = !!tmp;
1497 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1498 config->l3_vxlan_en = !!tmp;
1499 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1500 config->vf_nl_en = !!tmp;
1501 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1502 config->dv_esw_en = !!tmp;
1503 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1504 config->dv_flow_en = !!tmp;
1505 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1506 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1507 tmp != MLX5_XMETA_MODE_META16 &&
1508 tmp != MLX5_XMETA_MODE_META32) {
1509 DRV_LOG(ERR, "invalid extensive "
1510 "metadata parameter");
1514 config->dv_xmeta_en = tmp;
1515 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1516 config->lacp_by_user = !!tmp;
1517 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1518 config->mr_ext_memseg_en = !!tmp;
1519 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1520 config->max_dump_files_num = tmp;
1521 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1522 config->lro.timeout = tmp;
1523 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1524 DRV_LOG(DEBUG, "class argument is %s.", val);
1525 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1526 config->log_hp_size = tmp;
1527 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1528 if (tmp != MLX5_RCM_NONE &&
1529 tmp != MLX5_RCM_LIGHT &&
1530 tmp != MLX5_RCM_AGGR) {
1531 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1535 config->reclaim_mode = tmp;
1537 DRV_LOG(WARNING, "%s: unknown parameter", key);
1545 * Parse device parameters.
1548 * Pointer to device configuration structure.
1550 * Device arguments structure.
1553 * 0 on success, a negative errno value otherwise and rte_errno is set.
1556 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1558 const char **params = (const char *[]){
1559 MLX5_RXQ_CQE_COMP_EN,
1560 MLX5_RXQ_CQE_PAD_EN,
1561 MLX5_RXQ_PKT_PAD_EN,
1563 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1564 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1565 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1568 MLX5_TXQ_INLINE_MIN,
1569 MLX5_TXQ_INLINE_MAX,
1570 MLX5_TXQ_INLINE_MPW,
1571 MLX5_TXQS_MIN_INLINE,
1574 MLX5_TXQ_MPW_HDR_DSEG_EN,
1575 MLX5_TXQ_MAX_INLINE_LEN,
1587 MLX5_MR_EXT_MEMSEG_EN,
1589 MLX5_MAX_DUMP_FILES_NUM,
1590 MLX5_LRO_TIMEOUT_USEC,
1591 MLX5_CLASS_ARG_NAME,
1596 struct rte_kvargs *kvlist;
1600 if (devargs == NULL)
1602 /* Following UGLY cast is done to pass checkpatch. */
1603 kvlist = rte_kvargs_parse(devargs->args, params);
1604 if (kvlist == NULL) {
1608 /* Process parameters. */
1609 for (i = 0; (params[i] != NULL); ++i) {
1610 if (rte_kvargs_count(kvlist, params[i])) {
1611 ret = rte_kvargs_process(kvlist, params[i],
1612 mlx5_args_check, config);
1615 rte_kvargs_free(kvlist);
1620 rte_kvargs_free(kvlist);
1625 * PMD global initialization.
1627 * Independent from individual device, this function initializes global
1628 * per-PMD data structures distinguishing primary and secondary processes.
1629 * Hence, each initialization is called once per a process.
1632 * 0 on success, a negative errno value otherwise and rte_errno is set.
1635 mlx5_init_once(void)
1637 struct mlx5_shared_data *sd;
1638 struct mlx5_local_data *ld = &mlx5_local_data;
1641 if (mlx5_init_shared_data())
1643 sd = mlx5_shared_data;
1645 rte_spinlock_lock(&sd->lock);
1646 switch (rte_eal_process_type()) {
1647 case RTE_PROC_PRIMARY:
1650 LIST_INIT(&sd->mem_event_cb_list);
1651 rte_rwlock_init(&sd->mem_event_rwlock);
1652 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1653 mlx5_mr_mem_event_cb, NULL);
1654 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1655 mlx5_mp_primary_handle);
1658 sd->init_done = true;
1660 case RTE_PROC_SECONDARY:
1663 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1664 mlx5_mp_secondary_handle);
1667 ++sd->secondary_cnt;
1668 ld->init_done = true;
1674 rte_spinlock_unlock(&sd->lock);
1679 * Configures the minimal amount of data to inline into WQE
1680 * while sending packets.
1682 * - the txq_inline_min has the maximal priority, if this
1683 * key is specified in devargs
1684 * - if DevX is enabled the inline mode is queried from the
1685 * device (HCA attributes and NIC vport context if needed).
1686 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1687 * and none (0 bytes) for other NICs
1690 * Verbs device parameters (name, port, switch_info) to spawn.
1692 * Device configuration parameters.
1695 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1696 struct mlx5_dev_config *config)
1698 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1699 /* Application defines size of inlined data explicitly. */
1700 switch (spawn->pci_dev->id.device_id) {
1701 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1702 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1703 if (config->txq_inline_min <
1704 (int)MLX5_INLINE_HSIZE_L2) {
1706 "txq_inline_mix aligned to minimal"
1707 " ConnectX-4 required value %d",
1708 (int)MLX5_INLINE_HSIZE_L2);
1709 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1715 if (config->hca_attr.eth_net_offloads) {
1716 /* We have DevX enabled, inline mode queried successfully. */
1717 switch (config->hca_attr.wqe_inline_mode) {
1718 case MLX5_CAP_INLINE_MODE_L2:
1719 /* outer L2 header must be inlined. */
1720 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1722 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1723 /* No inline data are required by NIC. */
1724 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1725 config->hw_vlan_insert =
1726 config->hca_attr.wqe_vlan_insert;
1727 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1729 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1730 /* inline mode is defined by NIC vport context. */
1731 if (!config->hca_attr.eth_virt)
1733 switch (config->hca_attr.vport_inline_mode) {
1734 case MLX5_INLINE_MODE_NONE:
1735 config->txq_inline_min =
1736 MLX5_INLINE_HSIZE_NONE;
1738 case MLX5_INLINE_MODE_L2:
1739 config->txq_inline_min =
1740 MLX5_INLINE_HSIZE_L2;
1742 case MLX5_INLINE_MODE_IP:
1743 config->txq_inline_min =
1744 MLX5_INLINE_HSIZE_L3;
1746 case MLX5_INLINE_MODE_TCP_UDP:
1747 config->txq_inline_min =
1748 MLX5_INLINE_HSIZE_L4;
1750 case MLX5_INLINE_MODE_INNER_L2:
1751 config->txq_inline_min =
1752 MLX5_INLINE_HSIZE_INNER_L2;
1754 case MLX5_INLINE_MODE_INNER_IP:
1755 config->txq_inline_min =
1756 MLX5_INLINE_HSIZE_INNER_L3;
1758 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1759 config->txq_inline_min =
1760 MLX5_INLINE_HSIZE_INNER_L4;
1766 * We get here if we are unable to deduce
1767 * inline data size with DevX. Try PCI ID
1768 * to determine old NICs.
1770 switch (spawn->pci_dev->id.device_id) {
1771 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1772 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1773 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1774 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1775 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1776 config->hw_vlan_insert = 0;
1778 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1779 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1780 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1781 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1783 * These NICs support VLAN insertion from WQE and
1784 * report the wqe_vlan_insert flag. But there is the bug
1785 * and PFC control may be broken, so disable feature.
1787 config->hw_vlan_insert = 0;
1788 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1791 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1795 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1799 * Configures the metadata mask fields in the shared context.
1802 * Pointer to Ethernet device.
1805 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1807 struct mlx5_priv *priv = dev->data->dev_private;
1808 struct mlx5_dev_ctx_shared *sh = priv->sh;
1809 uint32_t meta, mark, reg_c0;
1811 reg_c0 = ~priv->vport_meta_mask;
1812 switch (priv->config.dv_xmeta_en) {
1813 case MLX5_XMETA_MODE_LEGACY:
1815 mark = MLX5_FLOW_MARK_MASK;
1817 case MLX5_XMETA_MODE_META16:
1818 meta = reg_c0 >> rte_bsf32(reg_c0);
1819 mark = MLX5_FLOW_MARK_MASK;
1821 case MLX5_XMETA_MODE_META32:
1823 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1831 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1832 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1833 sh->dv_mark_mask, mark);
1835 sh->dv_mark_mask = mark;
1836 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1837 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1838 sh->dv_meta_mask, meta);
1840 sh->dv_meta_mask = meta;
1841 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1842 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1843 sh->dv_meta_mask, reg_c0);
1845 sh->dv_regc0_mask = reg_c0;
1846 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1847 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1848 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1849 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1853 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1855 static const char *const dynf_names[] = {
1856 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1857 RTE_MBUF_DYNFLAG_METADATA_NAME,
1858 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1862 if (n < RTE_DIM(dynf_names))
1864 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1865 if (names[i] == NULL)
1867 strcpy(names[i], dynf_names[i]);
1869 return RTE_DIM(dynf_names);
1873 * Comparison callback to sort device data.
1875 * This is meant to be used with qsort().
1878 * Pointer to pointer to first data object.
1880 * Pointer to pointer to second data object.
1883 * 0 if both objects are equal, less than 0 if the first argument is less
1884 * than the second, greater than 0 otherwise.
1887 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1888 struct mlx5_dev_config *config)
1890 struct mlx5_dev_ctx_shared *sh = priv->sh;
1891 struct mlx5_dev_config *sh_conf = NULL;
1895 /* Nothing to compare for the single/first device. */
1896 if (sh->refcnt == 1)
1898 /* Find the device with shared context. */
1899 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1900 struct mlx5_priv *opriv =
1901 rte_eth_devices[port_id].data->dev_private;
1903 if (opriv && opriv != priv && opriv->sh == sh) {
1904 sh_conf = &opriv->config;
1910 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1911 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1912 " for shared %s context", sh->ibdev_name);
1916 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1917 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1918 " for shared %s context", sh->ibdev_name);
1926 * Look for the ethernet device belonging to mlx5 driver.
1928 * @param[in] port_id
1929 * port_id to start looking for device.
1930 * @param[in] pci_dev
1931 * Pointer to the hint PCI device. When device is being probed
1932 * the its siblings (master and preceding representors might
1933 * not have assigned driver yet (because the mlx5_os_pci_probe()
1934 * is not completed yet, for this case match on hint PCI
1935 * device may be used to detect sibling device.
1938 * port_id of found device, RTE_MAX_ETHPORT if not found.
1941 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1943 while (port_id < RTE_MAX_ETHPORTS) {
1944 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1946 if (dev->state != RTE_ETH_DEV_UNUSED &&
1948 (dev->device == &pci_dev->device ||
1949 (dev->device->driver &&
1950 dev->device->driver->name &&
1951 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1955 if (port_id >= RTE_MAX_ETHPORTS)
1956 return RTE_MAX_ETHPORTS;
1961 * DPDK callback to remove a PCI device.
1963 * This function removes all Ethernet devices belong to a given PCI device.
1965 * @param[in] pci_dev
1966 * Pointer to the PCI device.
1969 * 0 on success, the function cannot fail.
1972 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1976 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1978 * mlx5_dev_close() is not registered to secondary process,
1979 * call the close function explicitly for secondary process.
1981 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1982 mlx5_dev_close(&rte_eth_devices[port_id]);
1984 rte_eth_dev_close(port_id);
1989 static const struct rte_pci_id mlx5_pci_id_map[] = {
1991 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1995 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1999 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2000 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2003 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2007 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2011 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2012 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2015 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2016 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2019 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2020 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2023 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2024 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2027 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2028 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2031 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2032 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2035 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2036 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2039 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2040 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2043 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2044 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2047 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2048 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2051 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2052 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2059 struct rte_pci_driver mlx5_driver = {
2061 .name = MLX5_DRIVER_NAME
2063 .id_table = mlx5_pci_id_map,
2064 .probe = mlx5_os_pci_probe,
2065 .remove = mlx5_pci_remove,
2066 .dma_map = mlx5_dma_map,
2067 .dma_unmap = mlx5_dma_unmap,
2068 .drv_flags = PCI_DRV_FLAGS,
2071 /* Initialize driver log type. */
2072 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2075 * Driver initialization routine.
2077 RTE_INIT(rte_mlx5_pmd_init)
2079 /* Build the static tables for Verbs conversion. */
2080 mlx5_set_ptype_table();
2081 mlx5_set_cksum_table();
2082 mlx5_set_swp_types_table();
2084 rte_pci_register(&mlx5_driver);
2087 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2088 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2089 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");