net/mlx5: add eCPRI flex parser capacity check
[dpdk.git] / drivers / net / mlx5 / mlx5.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2015 6WIND S.A.
3  * Copyright 2015 Mellanox Technologies, Ltd
4  */
5
6 #include <stddef.h>
7 #include <unistd.h>
8 #include <string.h>
9 #include <stdint.h>
10 #include <stdlib.h>
11 #include <errno.h>
12 #include <net/if.h>
13 #include <sys/mman.h>
14 #include <linux/rtnetlink.h>
15
16 /* Verbs header. */
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
18 #ifdef PEDANTIC
19 #pragma GCC diagnostic ignored "-Wpedantic"
20 #endif
21 #include <infiniband/verbs.h>
22 #ifdef PEDANTIC
23 #pragma GCC diagnostic error "-Wpedantic"
24 #endif
25
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
29 #include <rte_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
37
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
41 #include <mlx5_common_os.h>
42 #include <mlx5_common_mp.h>
43
44 #include "mlx5_defs.h"
45 #include "mlx5.h"
46 #include "mlx5_utils.h"
47 #include "mlx5_rxtx.h"
48 #include "mlx5_autoconf.h"
49 #include "mlx5_mr.h"
50 #include "mlx5_flow.h"
51 #include "rte_pmd_mlx5.h"
52
53 /* Device parameter to enable RX completion queue compression. */
54 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
55
56 /* Device parameter to enable RX completion entry padding to 128B. */
57 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
58
59 /* Device parameter to enable padding Rx packet to cacheline size. */
60 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
61
62 /* Device parameter to enable Multi-Packet Rx queue. */
63 #define MLX5_RX_MPRQ_EN "mprq_en"
64
65 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
66 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
67
68 /* Device parameter to configure log 2 of the stride size for MPRQ. */
69 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
70
71 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
72 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
73
74 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
75 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
76
77 /* Device parameter to configure inline send. Deprecated, ignored.*/
78 #define MLX5_TXQ_INLINE "txq_inline"
79
80 /* Device parameter to limit packet size to inline with ordinary SEND. */
81 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
82
83 /* Device parameter to configure minimal data size to inline. */
84 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
85
86 /* Device parameter to limit packet size to inline with Enhanced MPW. */
87 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
88
89 /*
90  * Device parameter to configure the number of TX queues threshold for
91  * enabling inline send.
92  */
93 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
94
95 /*
96  * Device parameter to configure the number of TX queues threshold for
97  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
98  */
99 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
100
101 /* Device parameter to enable multi-packet send WQEs. */
102 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
103
104 /*
105  * Device parameter to force doorbell register mapping
106  * to non-cahed region eliminating the extra write memory barrier.
107  */
108 #define MLX5_TX_DB_NC "tx_db_nc"
109
110 /*
111  * Device parameter to include 2 dsegs in the title WQEBB.
112  * Deprecated, ignored.
113  */
114 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
115
116 /*
117  * Device parameter to limit the size of inlining packet.
118  * Deprecated, ignored.
119  */
120 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
121
122 /*
123  * Device parameter to enable Tx scheduling on timestamps
124  * and specify the packet pacing granularity in nanoseconds.
125  */
126 #define MLX5_TX_PP "tx_pp"
127
128 /*
129  * Device parameter to specify skew in nanoseconds on Tx datapath,
130  * it represents the time between SQ start WQE processing and
131  * appearing actual packet data on the wire.
132  */
133 #define MLX5_TX_SKEW "tx_skew"
134
135 /*
136  * Device parameter to enable hardware Tx vector.
137  * Deprecated, ignored (no vectorized Tx routines anymore).
138  */
139 #define MLX5_TX_VEC_EN "tx_vec_en"
140
141 /* Device parameter to enable hardware Rx vector. */
142 #define MLX5_RX_VEC_EN "rx_vec_en"
143
144 /* Allow L3 VXLAN flow creation. */
145 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
146
147 /* Activate DV E-Switch flow steering. */
148 #define MLX5_DV_ESW_EN "dv_esw_en"
149
150 /* Activate DV flow steering. */
151 #define MLX5_DV_FLOW_EN "dv_flow_en"
152
153 /* Enable extensive flow metadata support. */
154 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
155
156 /* Device parameter to let the user manage the lacp traffic of bonded device */
157 #define MLX5_LACP_BY_USER "lacp_by_user"
158
159 /* Activate Netlink support in VF mode. */
160 #define MLX5_VF_NL_EN "vf_nl_en"
161
162 /* Enable extending memsegs when creating a MR. */
163 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
164
165 /* Select port representors to instantiate. */
166 #define MLX5_REPRESENTOR "representor"
167
168 /* Device parameter to configure the maximum number of dump files per queue. */
169 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
170
171 /* Configure timeout of LRO session (in microseconds). */
172 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
173
174 /*
175  * Device parameter to configure the total data buffer size for a single
176  * hairpin queue (logarithm value).
177  */
178 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
179
180 /* Flow memory reclaim mode. */
181 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
182
183 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
184
185 /* Shared memory between primary and secondary processes. */
186 struct mlx5_shared_data *mlx5_shared_data;
187
188 /* Spinlock for mlx5_shared_data allocation. */
189 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
190
191 /* Process local data for secondary processes. */
192 static struct mlx5_local_data mlx5_local_data;
193
194 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
195                                                 LIST_HEAD_INITIALIZER();
196 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
197
198 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
199 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
200         {
201                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
202                 .trunk_size = 64,
203                 .grow_trunk = 3,
204                 .grow_shift = 2,
205                 .need_lock = 0,
206                 .release_mem_en = 1,
207                 .malloc = rte_malloc_socket,
208                 .free = rte_free,
209                 .type = "mlx5_encap_decap_ipool",
210         },
211         {
212                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
213                 .trunk_size = 64,
214                 .grow_trunk = 3,
215                 .grow_shift = 2,
216                 .need_lock = 0,
217                 .release_mem_en = 1,
218                 .malloc = rte_malloc_socket,
219                 .free = rte_free,
220                 .type = "mlx5_push_vlan_ipool",
221         },
222         {
223                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
224                 .trunk_size = 64,
225                 .grow_trunk = 3,
226                 .grow_shift = 2,
227                 .need_lock = 0,
228                 .release_mem_en = 1,
229                 .malloc = rte_malloc_socket,
230                 .free = rte_free,
231                 .type = "mlx5_tag_ipool",
232         },
233         {
234                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
235                 .trunk_size = 64,
236                 .grow_trunk = 3,
237                 .grow_shift = 2,
238                 .need_lock = 0,
239                 .release_mem_en = 1,
240                 .malloc = rte_malloc_socket,
241                 .free = rte_free,
242                 .type = "mlx5_port_id_ipool",
243         },
244         {
245                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
246                 .trunk_size = 64,
247                 .grow_trunk = 3,
248                 .grow_shift = 2,
249                 .need_lock = 0,
250                 .release_mem_en = 1,
251                 .malloc = rte_malloc_socket,
252                 .free = rte_free,
253                 .type = "mlx5_jump_ipool",
254         },
255 #endif
256         {
257                 .size = sizeof(struct mlx5_flow_meter),
258                 .trunk_size = 64,
259                 .grow_trunk = 3,
260                 .grow_shift = 2,
261                 .need_lock = 0,
262                 .release_mem_en = 1,
263                 .malloc = rte_malloc_socket,
264                 .free = rte_free,
265                 .type = "mlx5_meter_ipool",
266         },
267         {
268                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
269                 .trunk_size = 64,
270                 .grow_trunk = 3,
271                 .grow_shift = 2,
272                 .need_lock = 0,
273                 .release_mem_en = 1,
274                 .malloc = rte_malloc_socket,
275                 .free = rte_free,
276                 .type = "mlx5_mcp_ipool",
277         },
278         {
279                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
280                 .trunk_size = 64,
281                 .grow_trunk = 3,
282                 .grow_shift = 2,
283                 .need_lock = 0,
284                 .release_mem_en = 1,
285                 .malloc = rte_malloc_socket,
286                 .free = rte_free,
287                 .type = "mlx5_hrxq_ipool",
288         },
289         {
290                 /*
291                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
292                  * It set in run time according to PCI function configuration.
293                  */
294                 .size = 0,
295                 .trunk_size = 64,
296                 .grow_trunk = 3,
297                 .grow_shift = 2,
298                 .need_lock = 0,
299                 .release_mem_en = 1,
300                 .malloc = rte_malloc_socket,
301                 .free = rte_free,
302                 .type = "mlx5_flow_handle_ipool",
303         },
304         {
305                 .size = sizeof(struct rte_flow),
306                 .trunk_size = 4096,
307                 .need_lock = 1,
308                 .release_mem_en = 1,
309                 .malloc = rte_malloc_socket,
310                 .free = rte_free,
311                 .type = "rte_flow_ipool",
312         },
313 };
314
315
316 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
317 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
318
319 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
320
321 /**
322  * Allocate ID pool structure.
323  *
324  * @param[in] max_id
325  *   The maximum id can be allocated from the pool.
326  *
327  * @return
328  *   Pointer to pool object, NULL value otherwise.
329  */
330 struct mlx5_flow_id_pool *
331 mlx5_flow_id_pool_alloc(uint32_t max_id)
332 {
333         struct mlx5_flow_id_pool *pool;
334         void *mem;
335
336         pool = rte_zmalloc("id pool allocation", sizeof(*pool),
337                            RTE_CACHE_LINE_SIZE);
338         if (!pool) {
339                 DRV_LOG(ERR, "can't allocate id pool");
340                 rte_errno  = ENOMEM;
341                 return NULL;
342         }
343         mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
344                           RTE_CACHE_LINE_SIZE);
345         if (!mem) {
346                 DRV_LOG(ERR, "can't allocate mem for id pool");
347                 rte_errno  = ENOMEM;
348                 goto error;
349         }
350         pool->free_arr = mem;
351         pool->curr = pool->free_arr;
352         pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
353         pool->base_index = 0;
354         pool->max_id = max_id;
355         return pool;
356 error:
357         rte_free(pool);
358         return NULL;
359 }
360
361 /**
362  * Release ID pool structure.
363  *
364  * @param[in] pool
365  *   Pointer to flow id pool object to free.
366  */
367 void
368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
369 {
370         rte_free(pool->free_arr);
371         rte_free(pool);
372 }
373
374 /**
375  * Generate ID.
376  *
377  * @param[in] pool
378  *   Pointer to flow id pool.
379  * @param[out] id
380  *   The generated ID.
381  *
382  * @return
383  *   0 on success, error value otherwise.
384  */
385 uint32_t
386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
387 {
388         if (pool->curr == pool->free_arr) {
389                 if (pool->base_index == pool->max_id) {
390                         rte_errno  = ENOMEM;
391                         DRV_LOG(ERR, "no free id");
392                         return -rte_errno;
393                 }
394                 *id = ++pool->base_index;
395                 return 0;
396         }
397         *id = *(--pool->curr);
398         return 0;
399 }
400
401 /**
402  * Release ID.
403  *
404  * @param[in] pool
405  *   Pointer to flow id pool.
406  * @param[out] id
407  *   The generated ID.
408  *
409  * @return
410  *   0 on success, error value otherwise.
411  */
412 uint32_t
413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
414 {
415         uint32_t size;
416         uint32_t size2;
417         void *mem;
418
419         if (pool->curr == pool->last) {
420                 size = pool->curr - pool->free_arr;
421                 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
422                 MLX5_ASSERT(size2 > size);
423                 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
424                 if (!mem) {
425                         DRV_LOG(ERR, "can't allocate mem for id pool");
426                         rte_errno  = ENOMEM;
427                         return -rte_errno;
428                 }
429                 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
430                 rte_free(pool->free_arr);
431                 pool->free_arr = mem;
432                 pool->curr = pool->free_arr + size;
433                 pool->last = pool->free_arr + size2;
434         }
435         *pool->curr = id;
436         pool->curr++;
437         return 0;
438 }
439
440 /**
441  * Initialize the shared aging list information per port.
442  *
443  * @param[in] sh
444  *   Pointer to mlx5_dev_ctx_shared object.
445  */
446 static void
447 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
448 {
449         uint32_t i;
450         struct mlx5_age_info *age_info;
451
452         for (i = 0; i < sh->max_port; i++) {
453                 age_info = &sh->port[i].age_info;
454                 age_info->flags = 0;
455                 TAILQ_INIT(&age_info->aged_counters);
456                 rte_spinlock_init(&age_info->aged_sl);
457                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
458         }
459 }
460
461 /**
462  * Initialize the counters management structure.
463  *
464  * @param[in] sh
465  *   Pointer to mlx5_dev_ctx_shared object to free
466  */
467 static void
468 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
469 {
470         int i;
471
472         memset(&sh->cmng, 0, sizeof(sh->cmng));
473         TAILQ_INIT(&sh->cmng.flow_counters);
474         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
475                 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
476                 sh->cmng.ccont[i].max_id = -1;
477                 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
478                 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
479                 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
480                 TAILQ_INIT(&sh->cmng.ccont[i].counters);
481                 rte_spinlock_init(&sh->cmng.ccont[i].csl);
482         }
483 }
484
485 /**
486  * Destroy all the resources allocated for a counter memory management.
487  *
488  * @param[in] mng
489  *   Pointer to the memory management structure.
490  */
491 static void
492 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
493 {
494         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
495
496         LIST_REMOVE(mng, next);
497         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
498         claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
499         rte_free(mem);
500 }
501
502 /**
503  * Close and release all the resources of the counters management.
504  *
505  * @param[in] sh
506  *   Pointer to mlx5_dev_ctx_shared object to free.
507  */
508 static void
509 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
510 {
511         struct mlx5_counter_stats_mem_mng *mng;
512         int i;
513         int j;
514         int retries = 1024;
515
516         rte_errno = 0;
517         while (--retries) {
518                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
519                 if (rte_errno != EINPROGRESS)
520                         break;
521                 rte_pause();
522         }
523         for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
524                 struct mlx5_flow_counter_pool *pool;
525                 uint32_t batch = !!(i > 1);
526
527                 if (!sh->cmng.ccont[i].pools)
528                         continue;
529                 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
530                 while (pool) {
531                         if (batch && pool->min_dcs)
532                                 claim_zero(mlx5_devx_cmd_destroy
533                                                                (pool->min_dcs));
534                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
535                                 if (MLX5_POOL_GET_CNT(pool, j)->action)
536                                         claim_zero
537                                          (mlx5_glue->destroy_flow_action
538                                           (MLX5_POOL_GET_CNT
539                                           (pool, j)->action));
540                                 if (!batch && MLX5_GET_POOL_CNT_EXT
541                                     (pool, j)->dcs)
542                                         claim_zero(mlx5_devx_cmd_destroy
543                                                    (MLX5_GET_POOL_CNT_EXT
544                                                     (pool, j)->dcs));
545                         }
546                         TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
547                         rte_free(pool);
548                         pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
549                 }
550                 rte_free(sh->cmng.ccont[i].pools);
551         }
552         mng = LIST_FIRST(&sh->cmng.mem_mngs);
553         while (mng) {
554                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
555                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
556         }
557         memset(&sh->cmng, 0, sizeof(sh->cmng));
558 }
559
560 /**
561  * Initialize the flow resources' indexed mempool.
562  *
563  * @param[in] sh
564  *   Pointer to mlx5_dev_ctx_shared object.
565  * @param[in] sh
566  *   Pointer to user dev config.
567  */
568 static void
569 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
570                        const struct mlx5_dev_config *config)
571 {
572         uint8_t i;
573         struct mlx5_indexed_pool_config cfg;
574
575         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
576                 cfg = mlx5_ipool_cfg[i];
577                 switch (i) {
578                 default:
579                         break;
580                 /*
581                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
582                  * according to PCI function flow configuration.
583                  */
584                 case MLX5_IPOOL_MLX5_FLOW:
585                         cfg.size = config->dv_flow_en ?
586                                 sizeof(struct mlx5_flow_handle) :
587                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
588                         break;
589                 }
590                 if (config->reclaim_mode)
591                         cfg.release_mem_en = 1;
592                 sh->ipool[i] = mlx5_ipool_create(&cfg);
593         }
594 }
595
596 /**
597  * Release the flow resources' indexed mempool.
598  *
599  * @param[in] sh
600  *   Pointer to mlx5_dev_ctx_shared object.
601  */
602 static void
603 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
604 {
605         uint8_t i;
606
607         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
608                 mlx5_ipool_destroy(sh->ipool[i]);
609 }
610
611 /*
612  * Check if dynamic flex parser for eCPRI already exists.
613  *
614  * @param dev
615  *   Pointer to Ethernet device structure.
616  *
617  * @return
618  *   true on exists, false on not.
619  */
620 bool
621 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
622 {
623         struct mlx5_priv *priv = dev->data->dev_private;
624         struct mlx5_flex_parser_profiles *prf =
625                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
626
627         return !!prf->obj;
628 }
629
630 /*
631  * Allocation of a flex parser for eCPRI. Once created, this parser related
632  * resources will be held until the device is closed.
633  *
634  * @param dev
635  *   Pointer to Ethernet device structure.
636  *
637  * @return
638  *   0 on success, a negative errno value otherwise and rte_errno is set.
639  */
640 int
641 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
642 {
643         struct mlx5_priv *priv = dev->data->dev_private;
644         struct mlx5_flex_parser_profiles *prf =
645                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
646         struct mlx5_devx_graph_node_attr node = {
647                 .modify_field_select = 0,
648         };
649         uint32_t ids[8];
650         int ret;
651
652         if (!priv->config.hca_attr.parse_graph_flex_node) {
653                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
654                         "for device %s.", priv->dev_data->name);
655                 return -ENOTSUP;
656         }
657         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
658         /* 8 bytes now: 4B common header + 4B message body header. */
659         node.header_length_base_value = 0x8;
660         /* After MAC layer: Ether / VLAN. */
661         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
662         /* Type of compared condition should be 0xAEFE in the L2 layer. */
663         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
664         /* Sample #0: type in common header. */
665         node.sample[0].flow_match_sample_en = 1;
666         /* Fixed offset. */
667         node.sample[0].flow_match_sample_offset_mode = 0x0;
668         /* Only the 2nd byte will be used. */
669         node.sample[0].flow_match_sample_field_base_offset = 0x0;
670         /* Sample #1: message payload. */
671         node.sample[1].flow_match_sample_en = 1;
672         /* Fixed offset. */
673         node.sample[1].flow_match_sample_offset_mode = 0x0;
674         /*
675          * Only the first two bytes will be used right now, and its offset will
676          * start after the common header that with the length of a DW(u32).
677          */
678         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
679         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
680         if (!prf->obj) {
681                 DRV_LOG(ERR, "Failed to create flex parser node object.");
682                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
683         }
684         prf->num = 2;
685         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
686         if (ret) {
687                 DRV_LOG(ERR, "Failed to query sample IDs.");
688                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
689         }
690         prf->offset[0] = 0x0;
691         prf->offset[1] = sizeof(uint32_t);
692         prf->ids[0] = ids[0];
693         prf->ids[1] = ids[1];
694         return 0;
695 }
696
697 /*
698  * Destroy the flex parser node, including the parser itself, input / output
699  * arcs and DW samples. Resources could be reused then.
700  *
701  * @param dev
702  *   Pointer to Ethernet device structure.
703  */
704 static void
705 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
706 {
707         struct mlx5_priv *priv = dev->data->dev_private;
708         struct mlx5_flex_parser_profiles *prf =
709                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
710
711         if (prf->obj)
712                 mlx5_devx_cmd_destroy(prf->obj);
713         prf->obj = NULL;
714 }
715
716 /**
717  * Allocate shared device context. If there is multiport device the
718  * master and representors will share this context, if there is single
719  * port dedicated device, the context will be used by only given
720  * port due to unification.
721  *
722  * Routine first searches the context for the specified device name,
723  * if found the shared context assumed and reference counter is incremented.
724  * If no context found the new one is created and initialized with specified
725  * device context and parameters.
726  *
727  * @param[in] spawn
728  *   Pointer to the device attributes (name, port, etc).
729  * @param[in] config
730  *   Pointer to device configuration structure.
731  *
732  * @return
733  *   Pointer to mlx5_dev_ctx_shared object on success,
734  *   otherwise NULL and rte_errno is set.
735  */
736 struct mlx5_dev_ctx_shared *
737 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
738                            const struct mlx5_dev_config *config)
739 {
740         struct mlx5_dev_ctx_shared *sh;
741         int err = 0;
742         uint32_t i;
743         struct mlx5_devx_tis_attr tis_attr = { 0 };
744
745         MLX5_ASSERT(spawn);
746         /* Secondary process should not create the shared context. */
747         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
748         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
749         /* Search for IB context by device name. */
750         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
751                 if (!strcmp(sh->ibdev_name,
752                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
753                         sh->refcnt++;
754                         goto exit;
755                 }
756         }
757         /* No device found, we have to create new shared context. */
758         MLX5_ASSERT(spawn->max_port);
759         sh = rte_zmalloc("ethdev shared ib context",
760                          sizeof(struct mlx5_dev_ctx_shared) +
761                          spawn->max_port *
762                          sizeof(struct mlx5_dev_shared_port),
763                          RTE_CACHE_LINE_SIZE);
764         if (!sh) {
765                 DRV_LOG(ERR, "shared context allocation failure");
766                 rte_errno  = ENOMEM;
767                 goto exit;
768         }
769         err = mlx5_os_open_device(spawn, config, sh);
770         if (!sh->ctx)
771                 goto error;
772         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
773         if (err) {
774                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
775                 goto error;
776         }
777         sh->refcnt = 1;
778         sh->max_port = spawn->max_port;
779         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
780                 sizeof(sh->ibdev_name) - 1);
781         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
782                 sizeof(sh->ibdev_path) - 1);
783         /*
784          * Setting port_id to max unallowed value means
785          * there is no interrupt subhandler installed for
786          * the given port index i.
787          */
788         for (i = 0; i < sh->max_port; i++) {
789                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
790                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
791         }
792         sh->pd = mlx5_glue->alloc_pd(sh->ctx);
793         if (sh->pd == NULL) {
794                 DRV_LOG(ERR, "PD allocation failure");
795                 err = ENOMEM;
796                 goto error;
797         }
798         if (sh->devx) {
799                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
800                 if (err) {
801                         DRV_LOG(ERR, "Fail to extract pdn from PD");
802                         goto error;
803                 }
804                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
805                 if (!sh->td) {
806                         DRV_LOG(ERR, "TD allocation failure");
807                         err = ENOMEM;
808                         goto error;
809                 }
810                 tis_attr.transport_domain = sh->td->id;
811                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
812                 if (!sh->tis) {
813                         DRV_LOG(ERR, "TIS allocation failure");
814                         err = ENOMEM;
815                         goto error;
816                 }
817                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, 0);
818                 if (!sh->tx_uar) {
819                         DRV_LOG(ERR, "Failed to allocate DevX UAR.");
820                         err = ENOMEM;
821                         goto error;
822                 }
823         }
824         sh->flow_id_pool = mlx5_flow_id_pool_alloc
825                                         ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
826         if (!sh->flow_id_pool) {
827                 DRV_LOG(ERR, "can't create flow id pool");
828                 err = ENOMEM;
829                 goto error;
830         }
831 #ifndef RTE_ARCH_64
832         /* Initialize UAR access locks for 32bit implementations. */
833         rte_spinlock_init(&sh->uar_lock_cq);
834         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
835                 rte_spinlock_init(&sh->uar_lock[i]);
836 #endif
837         /*
838          * Once the device is added to the list of memory event
839          * callback, its global MR cache table cannot be expanded
840          * on the fly because of deadlock. If it overflows, lookup
841          * should be done by searching MR list linearly, which is slow.
842          *
843          * At this point the device is not added to the memory
844          * event list yet, context is just being created.
845          */
846         err = mlx5_mr_btree_init(&sh->share_cache.cache,
847                                  MLX5_MR_BTREE_CACHE_N * 2,
848                                  spawn->pci_dev->device.numa_node);
849         if (err) {
850                 err = rte_errno;
851                 goto error;
852         }
853         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
854                               &sh->share_cache.dereg_mr_cb);
855         mlx5_os_dev_shared_handler_install(sh);
856         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
857         if (!sh->cnt_id_tbl) {
858                 err = rte_errno;
859                 goto error;
860         }
861         mlx5_flow_aging_init(sh);
862         mlx5_flow_counters_mng_init(sh);
863         mlx5_flow_ipool_create(sh, config);
864         /* Add device to memory callback list. */
865         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
866         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
867                          sh, mem_event_cb);
868         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
869         /* Add context to the global device list. */
870         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
871 exit:
872         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
873         return sh;
874 error:
875         pthread_mutex_destroy(&sh->txpp.mutex);
876         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
877         MLX5_ASSERT(sh);
878         if (sh->cnt_id_tbl) {
879                 mlx5_l3t_destroy(sh->cnt_id_tbl);
880                 sh->cnt_id_tbl = NULL;
881         }
882         if (sh->tx_uar) {
883                 mlx5_glue->devx_free_uar(sh->tx_uar);
884                 sh->tx_uar = NULL;
885         }
886         if (sh->tis)
887                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
888         if (sh->td)
889                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
890         if (sh->pd)
891                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
892         if (sh->ctx)
893                 claim_zero(mlx5_glue->close_device(sh->ctx));
894         if (sh->flow_id_pool)
895                 mlx5_flow_id_pool_release(sh->flow_id_pool);
896         rte_free(sh);
897         MLX5_ASSERT(err > 0);
898         rte_errno = err;
899         return NULL;
900 }
901
902 /**
903  * Free shared IB device context. Decrement counter and if zero free
904  * all allocated resources and close handles.
905  *
906  * @param[in] sh
907  *   Pointer to mlx5_dev_ctx_shared object to free
908  */
909 void
910 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
911 {
912         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
913 #ifdef RTE_LIBRTE_MLX5_DEBUG
914         /* Check the object presence in the list. */
915         struct mlx5_dev_ctx_shared *lctx;
916
917         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
918                 if (lctx == sh)
919                         break;
920         MLX5_ASSERT(lctx);
921         if (lctx != sh) {
922                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
923                 goto exit;
924         }
925 #endif
926         MLX5_ASSERT(sh);
927         MLX5_ASSERT(sh->refcnt);
928         /* Secondary process should not free the shared context. */
929         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
930         if (--sh->refcnt)
931                 goto exit;
932         /* Remove from memory callback device list. */
933         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
934         LIST_REMOVE(sh, mem_event_cb);
935         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
936         /* Release created Memory Regions. */
937         mlx5_mr_release_cache(&sh->share_cache);
938         /* Remove context from the global device list. */
939         LIST_REMOVE(sh, next);
940         /*
941          *  Ensure there is no async event handler installed.
942          *  Only primary process handles async device events.
943          **/
944         mlx5_flow_counters_mng_close(sh);
945         mlx5_flow_ipool_destroy(sh);
946         mlx5_os_dev_shared_handler_uninstall(sh);
947         if (sh->cnt_id_tbl) {
948                 mlx5_l3t_destroy(sh->cnt_id_tbl);
949                 sh->cnt_id_tbl = NULL;
950         }
951         if (sh->tx_uar) {
952                 mlx5_glue->devx_free_uar(sh->tx_uar);
953                 sh->tx_uar = NULL;
954         }
955         if (sh->pd)
956                 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
957         if (sh->tis)
958                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
959         if (sh->td)
960                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
961         if (sh->ctx)
962                 claim_zero(mlx5_glue->close_device(sh->ctx));
963         if (sh->flow_id_pool)
964                 mlx5_flow_id_pool_release(sh->flow_id_pool);
965         pthread_mutex_destroy(&sh->txpp.mutex);
966         rte_free(sh);
967 exit:
968         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
969 }
970
971 /**
972  * Destroy table hash list and all the root entries per domain.
973  *
974  * @param[in] priv
975  *   Pointer to the private device data structure.
976  */
977 void
978 mlx5_free_table_hash_list(struct mlx5_priv *priv)
979 {
980         struct mlx5_dev_ctx_shared *sh = priv->sh;
981         struct mlx5_flow_tbl_data_entry *tbl_data;
982         union mlx5_flow_tbl_key table_key = {
983                 {
984                         .table_id = 0,
985                         .reserved = 0,
986                         .domain = 0,
987                         .direction = 0,
988                 }
989         };
990         struct mlx5_hlist_entry *pos;
991
992         if (!sh->flow_tbls)
993                 return;
994         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
995         if (pos) {
996                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
997                                         entry);
998                 MLX5_ASSERT(tbl_data);
999                 mlx5_hlist_remove(sh->flow_tbls, pos);
1000                 rte_free(tbl_data);
1001         }
1002         table_key.direction = 1;
1003         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1004         if (pos) {
1005                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1006                                         entry);
1007                 MLX5_ASSERT(tbl_data);
1008                 mlx5_hlist_remove(sh->flow_tbls, pos);
1009                 rte_free(tbl_data);
1010         }
1011         table_key.direction = 0;
1012         table_key.domain = 1;
1013         pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1014         if (pos) {
1015                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1016                                         entry);
1017                 MLX5_ASSERT(tbl_data);
1018                 mlx5_hlist_remove(sh->flow_tbls, pos);
1019                 rte_free(tbl_data);
1020         }
1021         mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1022 }
1023
1024 /**
1025  * Initialize flow table hash list and create the root tables entry
1026  * for each domain.
1027  *
1028  * @param[in] priv
1029  *   Pointer to the private device data structure.
1030  *
1031  * @return
1032  *   Zero on success, positive error code otherwise.
1033  */
1034 int
1035 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1036 {
1037         struct mlx5_dev_ctx_shared *sh = priv->sh;
1038         char s[MLX5_HLIST_NAMESIZE];
1039         int err = 0;
1040
1041         MLX5_ASSERT(sh);
1042         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1043         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1044         if (!sh->flow_tbls) {
1045                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1046                 err = ENOMEM;
1047                 return err;
1048         }
1049 #ifndef HAVE_MLX5DV_DR
1050         /*
1051          * In case we have not DR support, the zero tables should be created
1052          * because DV expect to see them even if they cannot be created by
1053          * RDMA-CORE.
1054          */
1055         union mlx5_flow_tbl_key table_key = {
1056                 {
1057                         .table_id = 0,
1058                         .reserved = 0,
1059                         .domain = 0,
1060                         .direction = 0,
1061                 }
1062         };
1063         struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
1064                                                           sizeof(*tbl_data), 0);
1065
1066         if (!tbl_data) {
1067                 err = ENOMEM;
1068                 goto error;
1069         }
1070         tbl_data->entry.key = table_key.v64;
1071         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1072         if (err)
1073                 goto error;
1074         rte_atomic32_init(&tbl_data->tbl.refcnt);
1075         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1076         table_key.direction = 1;
1077         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1078         if (!tbl_data) {
1079                 err = ENOMEM;
1080                 goto error;
1081         }
1082         tbl_data->entry.key = table_key.v64;
1083         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1084         if (err)
1085                 goto error;
1086         rte_atomic32_init(&tbl_data->tbl.refcnt);
1087         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1088         table_key.direction = 0;
1089         table_key.domain = 1;
1090         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
1091         if (!tbl_data) {
1092                 err = ENOMEM;
1093                 goto error;
1094         }
1095         tbl_data->entry.key = table_key.v64;
1096         err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1097         if (err)
1098                 goto error;
1099         rte_atomic32_init(&tbl_data->tbl.refcnt);
1100         rte_atomic32_inc(&tbl_data->tbl.refcnt);
1101         return err;
1102 error:
1103         mlx5_free_table_hash_list(priv);
1104 #endif /* HAVE_MLX5DV_DR */
1105         return err;
1106 }
1107
1108 /**
1109  * Initialize shared data between primary and secondary process.
1110  *
1111  * A memzone is reserved by primary process and secondary processes attach to
1112  * the memzone.
1113  *
1114  * @return
1115  *   0 on success, a negative errno value otherwise and rte_errno is set.
1116  */
1117 static int
1118 mlx5_init_shared_data(void)
1119 {
1120         const struct rte_memzone *mz;
1121         int ret = 0;
1122
1123         rte_spinlock_lock(&mlx5_shared_data_lock);
1124         if (mlx5_shared_data == NULL) {
1125                 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1126                         /* Allocate shared memory. */
1127                         mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1128                                                  sizeof(*mlx5_shared_data),
1129                                                  SOCKET_ID_ANY, 0);
1130                         if (mz == NULL) {
1131                                 DRV_LOG(ERR,
1132                                         "Cannot allocate mlx5 shared data");
1133                                 ret = -rte_errno;
1134                                 goto error;
1135                         }
1136                         mlx5_shared_data = mz->addr;
1137                         memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1138                         rte_spinlock_init(&mlx5_shared_data->lock);
1139                 } else {
1140                         /* Lookup allocated shared memory. */
1141                         mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1142                         if (mz == NULL) {
1143                                 DRV_LOG(ERR,
1144                                         "Cannot attach mlx5 shared data");
1145                                 ret = -rte_errno;
1146                                 goto error;
1147                         }
1148                         mlx5_shared_data = mz->addr;
1149                         memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1150                 }
1151         }
1152 error:
1153         rte_spinlock_unlock(&mlx5_shared_data_lock);
1154         return ret;
1155 }
1156
1157 /**
1158  * Retrieve integer value from environment variable.
1159  *
1160  * @param[in] name
1161  *   Environment variable name.
1162  *
1163  * @return
1164  *   Integer value, 0 if the variable is not set.
1165  */
1166 int
1167 mlx5_getenv_int(const char *name)
1168 {
1169         const char *val = getenv(name);
1170
1171         if (val == NULL)
1172                 return 0;
1173         return atoi(val);
1174 }
1175
1176 /**
1177  * DPDK callback to add udp tunnel port
1178  *
1179  * @param[in] dev
1180  *   A pointer to eth_dev
1181  * @param[in] udp_tunnel
1182  *   A pointer to udp tunnel
1183  *
1184  * @return
1185  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1186  */
1187 int
1188 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1189                          struct rte_eth_udp_tunnel *udp_tunnel)
1190 {
1191         MLX5_ASSERT(udp_tunnel != NULL);
1192         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1193             udp_tunnel->udp_port == 4789)
1194                 return 0;
1195         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1196             udp_tunnel->udp_port == 4790)
1197                 return 0;
1198         return -ENOTSUP;
1199 }
1200
1201 /**
1202  * Initialize process private data structure.
1203  *
1204  * @param dev
1205  *   Pointer to Ethernet device structure.
1206  *
1207  * @return
1208  *   0 on success, a negative errno value otherwise and rte_errno is set.
1209  */
1210 int
1211 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1212 {
1213         struct mlx5_priv *priv = dev->data->dev_private;
1214         struct mlx5_proc_priv *ppriv;
1215         size_t ppriv_size;
1216
1217         /*
1218          * UAR register table follows the process private structure. BlueFlame
1219          * registers for Tx queues are stored in the table.
1220          */
1221         ppriv_size =
1222                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1223         ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1224                                   RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1225         if (!ppriv) {
1226                 rte_errno = ENOMEM;
1227                 return -rte_errno;
1228         }
1229         ppriv->uar_table_sz = ppriv_size;
1230         dev->process_private = ppriv;
1231         return 0;
1232 }
1233
1234 /**
1235  * Un-initialize process private data structure.
1236  *
1237  * @param dev
1238  *   Pointer to Ethernet device structure.
1239  */
1240 static void
1241 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1242 {
1243         if (!dev->process_private)
1244                 return;
1245         rte_free(dev->process_private);
1246         dev->process_private = NULL;
1247 }
1248
1249 /**
1250  * DPDK callback to close the device.
1251  *
1252  * Destroy all queues and objects, free memory.
1253  *
1254  * @param dev
1255  *   Pointer to Ethernet device structure.
1256  */
1257 void
1258 mlx5_dev_close(struct rte_eth_dev *dev)
1259 {
1260         struct mlx5_priv *priv = dev->data->dev_private;
1261         unsigned int i;
1262         int ret;
1263
1264         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1265                 /* Check if process_private released. */
1266                 if (!dev->process_private)
1267                         return;
1268                 mlx5_tx_uar_uninit_secondary(dev);
1269                 mlx5_proc_priv_uninit(dev);
1270                 rte_eth_dev_release_port(dev);
1271                 return;
1272         }
1273         if (!priv->sh)
1274                 return;
1275         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1276                 dev->data->port_id,
1277                 ((priv->sh->ctx != NULL) ?
1278                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1279         /*
1280          * If default mreg copy action is removed at the stop stage,
1281          * the search will return none and nothing will be done anymore.
1282          */
1283         mlx5_flow_stop_default(dev);
1284         mlx5_traffic_disable(dev);
1285         /*
1286          * If all the flows are already flushed in the device stop stage,
1287          * then this will return directly without any action.
1288          */
1289         mlx5_flow_list_flush(dev, &priv->flows, true);
1290         mlx5_flow_meter_flush(dev, NULL);
1291         /* Free the intermediate buffers for flow creation. */
1292         mlx5_flow_free_intermediate(dev);
1293         /* Prevent crashes when queues are still in use. */
1294         dev->rx_pkt_burst = removed_rx_burst;
1295         dev->tx_pkt_burst = removed_tx_burst;
1296         rte_wmb();
1297         /* Disable datapath on secondary process. */
1298         mlx5_mp_req_stop_rxtx(dev);
1299         /* Free the eCPRI flex parser resource. */
1300         mlx5_flex_parser_ecpri_release(dev);
1301         if (priv->rxqs != NULL) {
1302                 /* XXX race condition if mlx5_rx_burst() is still running. */
1303                 usleep(1000);
1304                 for (i = 0; (i != priv->rxqs_n); ++i)
1305                         mlx5_rxq_release(dev, i);
1306                 priv->rxqs_n = 0;
1307                 priv->rxqs = NULL;
1308         }
1309         if (priv->txqs != NULL) {
1310                 /* XXX race condition if mlx5_tx_burst() is still running. */
1311                 usleep(1000);
1312                 for (i = 0; (i != priv->txqs_n); ++i)
1313                         mlx5_txq_release(dev, i);
1314                 priv->txqs_n = 0;
1315                 priv->txqs = NULL;
1316         }
1317         mlx5_proc_priv_uninit(dev);
1318         if (priv->mreg_cp_tbl)
1319                 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1320         mlx5_mprq_free_mp(dev);
1321         mlx5_os_free_shared_dr(priv);
1322         if (priv->rss_conf.rss_key != NULL)
1323                 rte_free(priv->rss_conf.rss_key);
1324         if (priv->reta_idx != NULL)
1325                 rte_free(priv->reta_idx);
1326         if (priv->config.vf)
1327                 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1328                                        dev->data->mac_addrs,
1329                                        MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1330         if (priv->nl_socket_route >= 0)
1331                 close(priv->nl_socket_route);
1332         if (priv->nl_socket_rdma >= 0)
1333                 close(priv->nl_socket_rdma);
1334         if (priv->vmwa_context)
1335                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1336         ret = mlx5_hrxq_verify(dev);
1337         if (ret)
1338                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1339                         dev->data->port_id);
1340         ret = mlx5_ind_table_obj_verify(dev);
1341         if (ret)
1342                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1343                         dev->data->port_id);
1344         ret = mlx5_rxq_obj_verify(dev);
1345         if (ret)
1346                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1347                         dev->data->port_id);
1348         ret = mlx5_rxq_verify(dev);
1349         if (ret)
1350                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1351                         dev->data->port_id);
1352         ret = mlx5_txq_obj_verify(dev);
1353         if (ret)
1354                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1355                         dev->data->port_id);
1356         ret = mlx5_txq_verify(dev);
1357         if (ret)
1358                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1359                         dev->data->port_id);
1360         ret = mlx5_flow_verify(dev);
1361         if (ret)
1362                 DRV_LOG(WARNING, "port %u some flows still remain",
1363                         dev->data->port_id);
1364         /*
1365          * Free the shared context in last turn, because the cleanup
1366          * routines above may use some shared fields, like
1367          * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1368          * ifindex if Netlink fails.
1369          */
1370         mlx5_free_shared_dev_ctx(priv->sh);
1371         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1372                 unsigned int c = 0;
1373                 uint16_t port_id;
1374
1375                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1376                         struct mlx5_priv *opriv =
1377                                 rte_eth_devices[port_id].data->dev_private;
1378
1379                         if (!opriv ||
1380                             opriv->domain_id != priv->domain_id ||
1381                             &rte_eth_devices[port_id] == dev)
1382                                 continue;
1383                         ++c;
1384                         break;
1385                 }
1386                 if (!c)
1387                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1388         }
1389         memset(priv, 0, sizeof(*priv));
1390         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1391         /*
1392          * Reset mac_addrs to NULL such that it is not freed as part of
1393          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1394          * it is freed when dev_private is freed.
1395          */
1396         dev->data->mac_addrs = NULL;
1397 }
1398
1399 /**
1400  * Verify and store value for device argument.
1401  *
1402  * @param[in] key
1403  *   Key argument to verify.
1404  * @param[in] val
1405  *   Value associated with key.
1406  * @param opaque
1407  *   User data.
1408  *
1409  * @return
1410  *   0 on success, a negative errno value otherwise and rte_errno is set.
1411  */
1412 static int
1413 mlx5_args_check(const char *key, const char *val, void *opaque)
1414 {
1415         struct mlx5_dev_config *config = opaque;
1416         unsigned long mod;
1417         signed long tmp;
1418
1419         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1420         if (!strcmp(MLX5_REPRESENTOR, key))
1421                 return 0;
1422         errno = 0;
1423         tmp = strtol(val, NULL, 0);
1424         if (errno) {
1425                 rte_errno = errno;
1426                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1427                 return -rte_errno;
1428         }
1429         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1430                 /* Negative values are acceptable for some keys only. */
1431                 rte_errno = EINVAL;
1432                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1433                 return -rte_errno;
1434         }
1435         mod = tmp >= 0 ? tmp : -tmp;
1436         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1437                 config->cqe_comp = !!tmp;
1438         } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1439                 config->cqe_pad = !!tmp;
1440         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1441                 config->hw_padding = !!tmp;
1442         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1443                 config->mprq.enabled = !!tmp;
1444         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1445                 config->mprq.stride_num_n = tmp;
1446         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1447                 config->mprq.stride_size_n = tmp;
1448         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1449                 config->mprq.max_memcpy_len = tmp;
1450         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1451                 config->mprq.min_rxqs_num = tmp;
1452         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1453                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1454                                  " converted to txq_inline_max", key);
1455                 config->txq_inline_max = tmp;
1456         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1457                 config->txq_inline_max = tmp;
1458         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1459                 config->txq_inline_min = tmp;
1460         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1461                 config->txq_inline_mpw = tmp;
1462         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1463                 config->txqs_inline = tmp;
1464         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1465                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1466         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1467                 config->mps = !!tmp;
1468         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1469                 if (tmp != MLX5_TXDB_CACHED &&
1470                     tmp != MLX5_TXDB_NCACHED &&
1471                     tmp != MLX5_TXDB_HEURISTIC) {
1472                         DRV_LOG(ERR, "invalid Tx doorbell "
1473                                      "mapping parameter");
1474                         rte_errno = EINVAL;
1475                         return -rte_errno;
1476                 }
1477                 config->dbnc = tmp;
1478         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1479                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1480         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1481                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1482                                  " converted to txq_inline_mpw", key);
1483                 config->txq_inline_mpw = tmp;
1484         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1485                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1486         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1487                 if (!mod) {
1488                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1489                         rte_errno = EINVAL;
1490                         return -rte_errno;
1491                 }
1492                 config->tx_pp = tmp;
1493         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1494                 config->tx_skew = tmp;
1495         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1496                 config->rx_vec_en = !!tmp;
1497         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1498                 config->l3_vxlan_en = !!tmp;
1499         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1500                 config->vf_nl_en = !!tmp;
1501         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1502                 config->dv_esw_en = !!tmp;
1503         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1504                 config->dv_flow_en = !!tmp;
1505         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1506                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1507                     tmp != MLX5_XMETA_MODE_META16 &&
1508                     tmp != MLX5_XMETA_MODE_META32) {
1509                         DRV_LOG(ERR, "invalid extensive "
1510                                      "metadata parameter");
1511                         rte_errno = EINVAL;
1512                         return -rte_errno;
1513                 }
1514                 config->dv_xmeta_en = tmp;
1515         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1516                 config->lacp_by_user = !!tmp;
1517         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1518                 config->mr_ext_memseg_en = !!tmp;
1519         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1520                 config->max_dump_files_num = tmp;
1521         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1522                 config->lro.timeout = tmp;
1523         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1524                 DRV_LOG(DEBUG, "class argument is %s.", val);
1525         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1526                 config->log_hp_size = tmp;
1527         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1528                 if (tmp != MLX5_RCM_NONE &&
1529                     tmp != MLX5_RCM_LIGHT &&
1530                     tmp != MLX5_RCM_AGGR) {
1531                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1532                         rte_errno = EINVAL;
1533                         return -rte_errno;
1534                 }
1535                 config->reclaim_mode = tmp;
1536         } else {
1537                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1538                 rte_errno = EINVAL;
1539                 return -rte_errno;
1540         }
1541         return 0;
1542 }
1543
1544 /**
1545  * Parse device parameters.
1546  *
1547  * @param config
1548  *   Pointer to device configuration structure.
1549  * @param devargs
1550  *   Device arguments structure.
1551  *
1552  * @return
1553  *   0 on success, a negative errno value otherwise and rte_errno is set.
1554  */
1555 int
1556 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1557 {
1558         const char **params = (const char *[]){
1559                 MLX5_RXQ_CQE_COMP_EN,
1560                 MLX5_RXQ_CQE_PAD_EN,
1561                 MLX5_RXQ_PKT_PAD_EN,
1562                 MLX5_RX_MPRQ_EN,
1563                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1564                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1565                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1566                 MLX5_RXQS_MIN_MPRQ,
1567                 MLX5_TXQ_INLINE,
1568                 MLX5_TXQ_INLINE_MIN,
1569                 MLX5_TXQ_INLINE_MAX,
1570                 MLX5_TXQ_INLINE_MPW,
1571                 MLX5_TXQS_MIN_INLINE,
1572                 MLX5_TXQS_MAX_VEC,
1573                 MLX5_TXQ_MPW_EN,
1574                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1575                 MLX5_TXQ_MAX_INLINE_LEN,
1576                 MLX5_TX_DB_NC,
1577                 MLX5_TX_PP,
1578                 MLX5_TX_SKEW,
1579                 MLX5_TX_VEC_EN,
1580                 MLX5_RX_VEC_EN,
1581                 MLX5_L3_VXLAN_EN,
1582                 MLX5_VF_NL_EN,
1583                 MLX5_DV_ESW_EN,
1584                 MLX5_DV_FLOW_EN,
1585                 MLX5_DV_XMETA_EN,
1586                 MLX5_LACP_BY_USER,
1587                 MLX5_MR_EXT_MEMSEG_EN,
1588                 MLX5_REPRESENTOR,
1589                 MLX5_MAX_DUMP_FILES_NUM,
1590                 MLX5_LRO_TIMEOUT_USEC,
1591                 MLX5_CLASS_ARG_NAME,
1592                 MLX5_HP_BUF_SIZE,
1593                 MLX5_RECLAIM_MEM,
1594                 NULL,
1595         };
1596         struct rte_kvargs *kvlist;
1597         int ret = 0;
1598         int i;
1599
1600         if (devargs == NULL)
1601                 return 0;
1602         /* Following UGLY cast is done to pass checkpatch. */
1603         kvlist = rte_kvargs_parse(devargs->args, params);
1604         if (kvlist == NULL) {
1605                 rte_errno = EINVAL;
1606                 return -rte_errno;
1607         }
1608         /* Process parameters. */
1609         for (i = 0; (params[i] != NULL); ++i) {
1610                 if (rte_kvargs_count(kvlist, params[i])) {
1611                         ret = rte_kvargs_process(kvlist, params[i],
1612                                                  mlx5_args_check, config);
1613                         if (ret) {
1614                                 rte_errno = EINVAL;
1615                                 rte_kvargs_free(kvlist);
1616                                 return -rte_errno;
1617                         }
1618                 }
1619         }
1620         rte_kvargs_free(kvlist);
1621         return 0;
1622 }
1623
1624 /**
1625  * PMD global initialization.
1626  *
1627  * Independent from individual device, this function initializes global
1628  * per-PMD data structures distinguishing primary and secondary processes.
1629  * Hence, each initialization is called once per a process.
1630  *
1631  * @return
1632  *   0 on success, a negative errno value otherwise and rte_errno is set.
1633  */
1634 int
1635 mlx5_init_once(void)
1636 {
1637         struct mlx5_shared_data *sd;
1638         struct mlx5_local_data *ld = &mlx5_local_data;
1639         int ret = 0;
1640
1641         if (mlx5_init_shared_data())
1642                 return -rte_errno;
1643         sd = mlx5_shared_data;
1644         MLX5_ASSERT(sd);
1645         rte_spinlock_lock(&sd->lock);
1646         switch (rte_eal_process_type()) {
1647         case RTE_PROC_PRIMARY:
1648                 if (sd->init_done)
1649                         break;
1650                 LIST_INIT(&sd->mem_event_cb_list);
1651                 rte_rwlock_init(&sd->mem_event_rwlock);
1652                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1653                                                 mlx5_mr_mem_event_cb, NULL);
1654                 ret = mlx5_mp_init_primary(MLX5_MP_NAME,
1655                                            mlx5_mp_primary_handle);
1656                 if (ret)
1657                         goto out;
1658                 sd->init_done = true;
1659                 break;
1660         case RTE_PROC_SECONDARY:
1661                 if (ld->init_done)
1662                         break;
1663                 ret = mlx5_mp_init_secondary(MLX5_MP_NAME,
1664                                              mlx5_mp_secondary_handle);
1665                 if (ret)
1666                         goto out;
1667                 ++sd->secondary_cnt;
1668                 ld->init_done = true;
1669                 break;
1670         default:
1671                 break;
1672         }
1673 out:
1674         rte_spinlock_unlock(&sd->lock);
1675         return ret;
1676 }
1677
1678 /**
1679  * Configures the minimal amount of data to inline into WQE
1680  * while sending packets.
1681  *
1682  * - the txq_inline_min has the maximal priority, if this
1683  *   key is specified in devargs
1684  * - if DevX is enabled the inline mode is queried from the
1685  *   device (HCA attributes and NIC vport context if needed).
1686  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1687  *   and none (0 bytes) for other NICs
1688  *
1689  * @param spawn
1690  *   Verbs device parameters (name, port, switch_info) to spawn.
1691  * @param config
1692  *   Device configuration parameters.
1693  */
1694 void
1695 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1696                     struct mlx5_dev_config *config)
1697 {
1698         if (config->txq_inline_min != MLX5_ARG_UNSET) {
1699                 /* Application defines size of inlined data explicitly. */
1700                 switch (spawn->pci_dev->id.device_id) {
1701                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1702                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1703                         if (config->txq_inline_min <
1704                                        (int)MLX5_INLINE_HSIZE_L2) {
1705                                 DRV_LOG(DEBUG,
1706                                         "txq_inline_mix aligned to minimal"
1707                                         " ConnectX-4 required value %d",
1708                                         (int)MLX5_INLINE_HSIZE_L2);
1709                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1710                         }
1711                         break;
1712                 }
1713                 goto exit;
1714         }
1715         if (config->hca_attr.eth_net_offloads) {
1716                 /* We have DevX enabled, inline mode queried successfully. */
1717                 switch (config->hca_attr.wqe_inline_mode) {
1718                 case MLX5_CAP_INLINE_MODE_L2:
1719                         /* outer L2 header must be inlined. */
1720                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1721                         goto exit;
1722                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1723                         /* No inline data are required by NIC. */
1724                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1725                         config->hw_vlan_insert =
1726                                 config->hca_attr.wqe_vlan_insert;
1727                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1728                         goto exit;
1729                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1730                         /* inline mode is defined by NIC vport context. */
1731                         if (!config->hca_attr.eth_virt)
1732                                 break;
1733                         switch (config->hca_attr.vport_inline_mode) {
1734                         case MLX5_INLINE_MODE_NONE:
1735                                 config->txq_inline_min =
1736                                         MLX5_INLINE_HSIZE_NONE;
1737                                 goto exit;
1738                         case MLX5_INLINE_MODE_L2:
1739                                 config->txq_inline_min =
1740                                         MLX5_INLINE_HSIZE_L2;
1741                                 goto exit;
1742                         case MLX5_INLINE_MODE_IP:
1743                                 config->txq_inline_min =
1744                                         MLX5_INLINE_HSIZE_L3;
1745                                 goto exit;
1746                         case MLX5_INLINE_MODE_TCP_UDP:
1747                                 config->txq_inline_min =
1748                                         MLX5_INLINE_HSIZE_L4;
1749                                 goto exit;
1750                         case MLX5_INLINE_MODE_INNER_L2:
1751                                 config->txq_inline_min =
1752                                         MLX5_INLINE_HSIZE_INNER_L2;
1753                                 goto exit;
1754                         case MLX5_INLINE_MODE_INNER_IP:
1755                                 config->txq_inline_min =
1756                                         MLX5_INLINE_HSIZE_INNER_L3;
1757                                 goto exit;
1758                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
1759                                 config->txq_inline_min =
1760                                         MLX5_INLINE_HSIZE_INNER_L4;
1761                                 goto exit;
1762                         }
1763                 }
1764         }
1765         /*
1766          * We get here if we are unable to deduce
1767          * inline data size with DevX. Try PCI ID
1768          * to determine old NICs.
1769          */
1770         switch (spawn->pci_dev->id.device_id) {
1771         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1772         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1773         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1774         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1775                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1776                 config->hw_vlan_insert = 0;
1777                 break;
1778         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1779         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1780         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1781         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1782                 /*
1783                  * These NICs support VLAN insertion from WQE and
1784                  * report the wqe_vlan_insert flag. But there is the bug
1785                  * and PFC control may be broken, so disable feature.
1786                  */
1787                 config->hw_vlan_insert = 0;
1788                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1789                 break;
1790         default:
1791                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1792                 break;
1793         }
1794 exit:
1795         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1796 }
1797
1798 /**
1799  * Configures the metadata mask fields in the shared context.
1800  *
1801  * @param [in] dev
1802  *   Pointer to Ethernet device.
1803  */
1804 void
1805 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1806 {
1807         struct mlx5_priv *priv = dev->data->dev_private;
1808         struct mlx5_dev_ctx_shared *sh = priv->sh;
1809         uint32_t meta, mark, reg_c0;
1810
1811         reg_c0 = ~priv->vport_meta_mask;
1812         switch (priv->config.dv_xmeta_en) {
1813         case MLX5_XMETA_MODE_LEGACY:
1814                 meta = UINT32_MAX;
1815                 mark = MLX5_FLOW_MARK_MASK;
1816                 break;
1817         case MLX5_XMETA_MODE_META16:
1818                 meta = reg_c0 >> rte_bsf32(reg_c0);
1819                 mark = MLX5_FLOW_MARK_MASK;
1820                 break;
1821         case MLX5_XMETA_MODE_META32:
1822                 meta = UINT32_MAX;
1823                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1824                 break;
1825         default:
1826                 meta = 0;
1827                 mark = 0;
1828                 MLX5_ASSERT(false);
1829                 break;
1830         }
1831         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1832                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1833                                  sh->dv_mark_mask, mark);
1834         else
1835                 sh->dv_mark_mask = mark;
1836         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1837                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1838                                  sh->dv_meta_mask, meta);
1839         else
1840                 sh->dv_meta_mask = meta;
1841         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1842                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1843                                  sh->dv_meta_mask, reg_c0);
1844         else
1845                 sh->dv_regc0_mask = reg_c0;
1846         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1847         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1848         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1849         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1850 }
1851
1852 int
1853 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1854 {
1855         static const char *const dynf_names[] = {
1856                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1857                 RTE_MBUF_DYNFLAG_METADATA_NAME,
1858                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1859         };
1860         unsigned int i;
1861
1862         if (n < RTE_DIM(dynf_names))
1863                 return -ENOMEM;
1864         for (i = 0; i < RTE_DIM(dynf_names); i++) {
1865                 if (names[i] == NULL)
1866                         return -EINVAL;
1867                 strcpy(names[i], dynf_names[i]);
1868         }
1869         return RTE_DIM(dynf_names);
1870 }
1871
1872 /**
1873  * Comparison callback to sort device data.
1874  *
1875  * This is meant to be used with qsort().
1876  *
1877  * @param a[in]
1878  *   Pointer to pointer to first data object.
1879  * @param b[in]
1880  *   Pointer to pointer to second data object.
1881  *
1882  * @return
1883  *   0 if both objects are equal, less than 0 if the first argument is less
1884  *   than the second, greater than 0 otherwise.
1885  */
1886 int
1887 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1888                               struct mlx5_dev_config *config)
1889 {
1890         struct mlx5_dev_ctx_shared *sh = priv->sh;
1891         struct mlx5_dev_config *sh_conf = NULL;
1892         uint16_t port_id;
1893
1894         MLX5_ASSERT(sh);
1895         /* Nothing to compare for the single/first device. */
1896         if (sh->refcnt == 1)
1897                 return 0;
1898         /* Find the device with shared context. */
1899         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1900                 struct mlx5_priv *opriv =
1901                         rte_eth_devices[port_id].data->dev_private;
1902
1903                 if (opriv && opriv != priv && opriv->sh == sh) {
1904                         sh_conf = &opriv->config;
1905                         break;
1906                 }
1907         }
1908         if (!sh_conf)
1909                 return 0;
1910         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1911                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1912                              " for shared %s context", sh->ibdev_name);
1913                 rte_errno = EINVAL;
1914                 return rte_errno;
1915         }
1916         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1917                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1918                              " for shared %s context", sh->ibdev_name);
1919                 rte_errno = EINVAL;
1920                 return rte_errno;
1921         }
1922         return 0;
1923 }
1924
1925 /**
1926  * Look for the ethernet device belonging to mlx5 driver.
1927  *
1928  * @param[in] port_id
1929  *   port_id to start looking for device.
1930  * @param[in] pci_dev
1931  *   Pointer to the hint PCI device. When device is being probed
1932  *   the its siblings (master and preceding representors might
1933  *   not have assigned driver yet (because the mlx5_os_pci_probe()
1934  *   is not completed yet, for this case match on hint PCI
1935  *   device may be used to detect sibling device.
1936  *
1937  * @return
1938  *   port_id of found device, RTE_MAX_ETHPORT if not found.
1939  */
1940 uint16_t
1941 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1942 {
1943         while (port_id < RTE_MAX_ETHPORTS) {
1944                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1945
1946                 if (dev->state != RTE_ETH_DEV_UNUSED &&
1947                     dev->device &&
1948                     (dev->device == &pci_dev->device ||
1949                      (dev->device->driver &&
1950                      dev->device->driver->name &&
1951                      !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1952                         break;
1953                 port_id++;
1954         }
1955         if (port_id >= RTE_MAX_ETHPORTS)
1956                 return RTE_MAX_ETHPORTS;
1957         return port_id;
1958 }
1959
1960 /**
1961  * DPDK callback to remove a PCI device.
1962  *
1963  * This function removes all Ethernet devices belong to a given PCI device.
1964  *
1965  * @param[in] pci_dev
1966  *   Pointer to the PCI device.
1967  *
1968  * @return
1969  *   0 on success, the function cannot fail.
1970  */
1971 static int
1972 mlx5_pci_remove(struct rte_pci_device *pci_dev)
1973 {
1974         uint16_t port_id;
1975
1976         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
1977                 /*
1978                  * mlx5_dev_close() is not registered to secondary process,
1979                  * call the close function explicitly for secondary process.
1980                  */
1981                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
1982                         mlx5_dev_close(&rte_eth_devices[port_id]);
1983                 else
1984                         rte_eth_dev_close(port_id);
1985         }
1986         return 0;
1987 }
1988
1989 static const struct rte_pci_id mlx5_pci_id_map[] = {
1990         {
1991                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1992                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
1993         },
1994         {
1995                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
1996                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
1997         },
1998         {
1999                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2000                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2001         },
2002         {
2003                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2004                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2005         },
2006         {
2007                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2008                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2009         },
2010         {
2011                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2012                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2013         },
2014         {
2015                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2016                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2017         },
2018         {
2019                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2020                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2021         },
2022         {
2023                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2024                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2025         },
2026         {
2027                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2028                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2029         },
2030         {
2031                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2032                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2033         },
2034         {
2035                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2036                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2037         },
2038         {
2039                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2040                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2041         },
2042         {
2043                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2044                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2045         },
2046         {
2047                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2048                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2049         },
2050         {
2051                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2052                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2053         },
2054         {
2055                 .vendor_id = 0
2056         }
2057 };
2058
2059 struct rte_pci_driver mlx5_driver = {
2060         .driver = {
2061                 .name = MLX5_DRIVER_NAME
2062         },
2063         .id_table = mlx5_pci_id_map,
2064         .probe = mlx5_os_pci_probe,
2065         .remove = mlx5_pci_remove,
2066         .dma_map = mlx5_dma_map,
2067         .dma_unmap = mlx5_dma_unmap,
2068         .drv_flags = PCI_DRV_FLAGS,
2069 };
2070
2071 /* Initialize driver log type. */
2072 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2073
2074 /**
2075  * Driver initialization routine.
2076  */
2077 RTE_INIT(rte_mlx5_pmd_init)
2078 {
2079         /* Build the static tables for Verbs conversion. */
2080         mlx5_set_ptype_table();
2081         mlx5_set_cksum_table();
2082         mlx5_set_swp_types_table();
2083         if (mlx5_glue)
2084                 rte_pci_register(&mlx5_driver);
2085 }
2086
2087 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2088 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2089 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");