drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 179 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 180
 181 /* Shared memory between primary and secondary processes. */
 182 struct mlx5_shared_data *mlx5_shared_data;
 183
 184 /** Driver-specific log messages type. */
 185 int mlx5_logtype;
 186
 187 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 188                                                 LIST_HEAD_INITIALIZER();
 189 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 191 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 192         [MLX5_IPOOL_DECAP_ENCAP] = {
 193                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 194                 .trunk_size = 64,
 195                 .grow_trunk = 3,
 196                 .grow_shift = 2,
 197                 .need_lock = 1,
 198                 .release_mem_en = 1,
 199                 .malloc = mlx5_malloc,
 200                 .free = mlx5_free,
 201                 .type = "mlx5_encap_decap_ipool",
 202         },
 203         [MLX5_IPOOL_PUSH_VLAN] = {
 204                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 1,
 209                 .release_mem_en = 1,
 210                 .malloc = mlx5_malloc,
 211                 .free = mlx5_free,
 212                 .type = "mlx5_push_vlan_ipool",
 213         },
 214         [MLX5_IPOOL_TAG] = {
 215                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 1,
 220                 .release_mem_en = 1,
 221                 .malloc = mlx5_malloc,
 222                 .free = mlx5_free,
 223                 .type = "mlx5_tag_ipool",
 224         },
 225         [MLX5_IPOOL_PORT_ID] = {
 226                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 227                 .trunk_size = 64,
 228                 .grow_trunk = 3,
 229                 .grow_shift = 2,
 230                 .need_lock = 1,
 231                 .release_mem_en = 1,
 232                 .malloc = mlx5_malloc,
 233                 .free = mlx5_free,
 234                 .type = "mlx5_port_id_ipool",
 235         },
 236         [MLX5_IPOOL_JUMP] = {
 237                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 238                 .trunk_size = 64,
 239                 .grow_trunk = 3,
 240                 .grow_shift = 2,
 241                 .need_lock = 1,
 242                 .release_mem_en = 1,
 243                 .malloc = mlx5_malloc,
 244                 .free = mlx5_free,
 245                 .type = "mlx5_jump_ipool",
 246         },
 247         [MLX5_IPOOL_SAMPLE] = {
 248                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 249                 .trunk_size = 64,
 250                 .grow_trunk = 3,
 251                 .grow_shift = 2,
 252                 .need_lock = 1,
 253                 .release_mem_en = 1,
 254                 .malloc = mlx5_malloc,
 255                 .free = mlx5_free,
 256                 .type = "mlx5_sample_ipool",
 257         },
 258         [MLX5_IPOOL_DEST_ARRAY] = {
 259                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 260                 .trunk_size = 64,
 261                 .grow_trunk = 3,
 262                 .grow_shift = 2,
 263                 .need_lock = 1,
 264                 .release_mem_en = 1,
 265                 .malloc = mlx5_malloc,
 266                 .free = mlx5_free,
 267                 .type = "mlx5_dest_array_ipool",
 268         },
 269         [MLX5_IPOOL_TUNNEL_ID] = {
 270                 .size = sizeof(struct mlx5_flow_tunnel),
 271                 .trunk_size = MLX5_MAX_TUNNELS,
 272                 .need_lock = 1,
 273                 .release_mem_en = 1,
 274                 .type = "mlx5_tunnel_offload",
 275         },
 276         [MLX5_IPOOL_TNL_TBL_ID] = {
 277                 .size = 0,
 278                 .need_lock = 1,
 279                 .type = "mlx5_flow_tnl_tbl_ipool",
 280         },
 281 #endif
 282         [MLX5_IPOOL_MTR] = {
 283                 /**
 284                  * The ipool index should grow continually from small to big,
 285                  * for meter idx, so not set grow_trunk to avoid meter index
 286                  * not jump continually.
 287                  */
 288                 .size = sizeof(struct mlx5_legacy_flow_meter),
 289                 .trunk_size = 64,
 290                 .need_lock = 1,
 291                 .release_mem_en = 1,
 292                 .malloc = mlx5_malloc,
 293                 .free = mlx5_free,
 294                 .type = "mlx5_meter_ipool",
 295         },
 296         [MLX5_IPOOL_MCP] = {
 297                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 298                 .trunk_size = 64,
 299                 .grow_trunk = 3,
 300                 .grow_shift = 2,
 301                 .need_lock = 1,
 302                 .release_mem_en = 1,
 303                 .malloc = mlx5_malloc,
 304                 .free = mlx5_free,
 305                 .type = "mlx5_mcp_ipool",
 306         },
 307         [MLX5_IPOOL_HRXQ] = {
 308                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 309                 .trunk_size = 64,
 310                 .grow_trunk = 3,
 311                 .grow_shift = 2,
 312                 .need_lock = 1,
 313                 .release_mem_en = 1,
 314                 .malloc = mlx5_malloc,
 315                 .free = mlx5_free,
 316                 .type = "mlx5_hrxq_ipool",
 317         },
 318         [MLX5_IPOOL_MLX5_FLOW] = {
 319                 /*
 320                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 321                  * It set in run time according to PCI function configuration.
 322                  */
 323                 .size = 0,
 324                 .trunk_size = 64,
 325                 .grow_trunk = 3,
 326                 .grow_shift = 2,
 327                 .need_lock = 1,
 328                 .release_mem_en = 1,
 329                 .malloc = mlx5_malloc,
 330                 .free = mlx5_free,
 331                 .type = "mlx5_flow_handle_ipool",
 332         },
 333         [MLX5_IPOOL_RTE_FLOW] = {
 334                 .size = sizeof(struct rte_flow),
 335                 .trunk_size = 4096,
 336                 .need_lock = 1,
 337                 .release_mem_en = 1,
 338                 .malloc = mlx5_malloc,
 339                 .free = mlx5_free,
 340                 .type = "rte_flow_ipool",
 341         },
 342         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 343                 .size = 0,
 344                 .need_lock = 1,
 345                 .type = "mlx5_flow_rss_id_ipool",
 346         },
 347         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 348                 .size = sizeof(struct mlx5_shared_action_rss),
 349                 .trunk_size = 64,
 350                 .grow_trunk = 3,
 351                 .grow_shift = 2,
 352                 .need_lock = 1,
 353                 .release_mem_en = 1,
 354                 .malloc = mlx5_malloc,
 355                 .free = mlx5_free,
 356                 .type = "mlx5_shared_action_rss",
 357         },
 358         [MLX5_IPOOL_MTR_POLICY] = {
 359                 /**
 360                  * The ipool index should grow continually from small to big,
 361                  * for policy idx, so not set grow_trunk to avoid policy index
 362                  * not jump continually.
 363                  */
 364                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 365                 .trunk_size = 64,
 366                 .need_lock = 1,
 367                 .release_mem_en = 1,
 368                 .malloc = mlx5_malloc,
 369                 .free = mlx5_free,
 370                 .type = "mlx5_meter_policy_ipool",
 371         },
 372 };
 373
 374
 375 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 376 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 377
 378 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 379
 380 /**
 381  * Decide whether representor ID is a HPF(host PF) port on BF2.
 382  *
 383  * @param dev
 384  *   Pointer to Ethernet device structure.
 385  *
 386  * @return
 387  *   Non-zero if HPF, otherwise 0.
 388  */
 389 bool
 390 mlx5_is_hpf(struct rte_eth_dev *dev)
 391 {
 392         struct mlx5_priv *priv = dev->data->dev_private;
 393         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 394         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 395
 396         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 397                MLX5_REPRESENTOR_REPR(-1) == repr;
 398 }
 399
 400 /**
 401  * Initialize the ASO aging management structure.
 402  *
 403  * @param[in] sh
 404  *   Pointer to mlx5_dev_ctx_shared object to free
 405  *
 406  * @return
 407  *   0 on success, a negative errno value otherwise and rte_errno is set.
 408  */
 409 int
 410 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 411 {
 412         int err;
 413
 414         if (sh->aso_age_mng)
 415                 return 0;
 416         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 417                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 418         if (!sh->aso_age_mng) {
 419                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 420                 rte_errno = ENOMEM;
 421                 return -ENOMEM;
 422         }
 423         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 424         if (err) {
 425                 mlx5_free(sh->aso_age_mng);
 426                 return -1;
 427         }
 428         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 429         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 430         LIST_INIT(&sh->aso_age_mng->free);
 431         return 0;
 432 }
 433
 434 /**
 435  * Close and release all the resources of the ASO aging management structure.
 436  *
 437  * @param[in] sh
 438  *   Pointer to mlx5_dev_ctx_shared object to free.
 439  */
 440 static void
 441 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 442 {
 443         int i, j;
 444
 445         mlx5_aso_flow_hit_queue_poll_stop(sh);
 446         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 447         if (sh->aso_age_mng->pools) {
 448                 struct mlx5_aso_age_pool *pool;
 449
 450                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 451                         pool = sh->aso_age_mng->pools[i];
 452                         claim_zero(mlx5_devx_cmd_destroy
 453                                                 (pool->flow_hit_aso_obj));
 454                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 455                                 if (pool->actions[j].dr_action)
 456                                         claim_zero
 457                                             (mlx5_flow_os_destroy_flow_action
 458                                               (pool->actions[j].dr_action));
 459                         mlx5_free(pool);
 460                 }
 461                 mlx5_free(sh->aso_age_mng->pools);
 462         }
 463         mlx5_free(sh->aso_age_mng);
 464 }
 465
 466 /**
 467  * Initialize the shared aging list information per port.
 468  *
 469  * @param[in] sh
 470  *   Pointer to mlx5_dev_ctx_shared object.
 471  */
 472 static void
 473 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 474 {
 475         uint32_t i;
 476         struct mlx5_age_info *age_info;
 477
 478         for (i = 0; i < sh->max_port; i++) {
 479                 age_info = &sh->port[i].age_info;
 480                 age_info->flags = 0;
 481                 TAILQ_INIT(&age_info->aged_counters);
 482                 LIST_INIT(&age_info->aged_aso);
 483                 rte_spinlock_init(&age_info->aged_sl);
 484                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 485         }
 486 }
 487
 488 /**
 489  * Initialize the counters management structure.
 490  *
 491  * @param[in] sh
 492  *   Pointer to mlx5_dev_ctx_shared object to free
 493  */
 494 static void
 495 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 496 {
 497         int i;
 498
 499         memset(&sh->cmng, 0, sizeof(sh->cmng));
 500         TAILQ_INIT(&sh->cmng.flow_counters);
 501         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 502         sh->cmng.max_id = -1;
 503         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 504         rte_spinlock_init(&sh->cmng.pool_update_sl);
 505         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 506                 TAILQ_INIT(&sh->cmng.counters[i]);
 507                 rte_spinlock_init(&sh->cmng.csl[i]);
 508         }
 509 }
 510
 511 /**
 512  * Destroy all the resources allocated for a counter memory management.
 513  *
 514  * @param[in] mng
 515  *   Pointer to the memory management structure.
 516  */
 517 static void
 518 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 519 {
 520         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 521
 522         LIST_REMOVE(mng, next);
 523         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 524         claim_zero(mlx5_os_umem_dereg(mng->umem));
 525         mlx5_free(mem);
 526 }
 527
 528 /**
 529  * Close and release all the resources of the counters management.
 530  *
 531  * @param[in] sh
 532  *   Pointer to mlx5_dev_ctx_shared object to free.
 533  */
 534 static void
 535 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 536 {
 537         struct mlx5_counter_stats_mem_mng *mng;
 538         int i, j;
 539         int retries = 1024;
 540
 541         rte_errno = 0;
 542         while (--retries) {
 543                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 544                 if (rte_errno != EINPROGRESS)
 545                         break;
 546                 rte_pause();
 547         }
 548
 549         if (sh->cmng.pools) {
 550                 struct mlx5_flow_counter_pool *pool;
 551                 uint16_t n_valid = sh->cmng.n_valid;
 552                 bool fallback = sh->cmng.counter_fallback;
 553
 554                 for (i = 0; i < n_valid; ++i) {
 555                         pool = sh->cmng.pools[i];
 556                         if (!fallback && pool->min_dcs)
 557                                 claim_zero(mlx5_devx_cmd_destroy
 558                                                                (pool->min_dcs));
 559                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 560                                 struct mlx5_flow_counter *cnt =
 561                                                 MLX5_POOL_GET_CNT(pool, j);
 562
 563                                 if (cnt->action)
 564                                         claim_zero
 565                                          (mlx5_flow_os_destroy_flow_action
 566                                           (cnt->action));
 567                                 if (fallback && MLX5_POOL_GET_CNT
 568                                     (pool, j)->dcs_when_free)
 569                                         claim_zero(mlx5_devx_cmd_destroy
 570                                                    (cnt->dcs_when_free));
 571                         }
 572                         mlx5_free(pool);
 573                 }
 574                 mlx5_free(sh->cmng.pools);
 575         }
 576         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 577         while (mng) {
 578                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 579                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 580         }
 581         memset(&sh->cmng, 0, sizeof(sh->cmng));
 582 }
 583
 584 /**
 585  * Initialize the aso flow meters management structure.
 586  *
 587  * @param[in] sh
 588  *   Pointer to mlx5_dev_ctx_shared object to free
 589  */
 590 int
 591 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 592 {
 593         if (!sh->mtrmng) {
 594                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 595                         sizeof(*sh->mtrmng),
 596                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 597                 if (!sh->mtrmng) {
 598                         DRV_LOG(ERR,
 599                         "meter management allocation was failed.");
 600                         rte_errno = ENOMEM;
 601                         return -ENOMEM;
 602                 }
 603                 if (sh->meter_aso_en) {
 604                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 605                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 606                 }
 607                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 608         }
 609         return 0;
 610 }
 611
 612 /**
 613  * Close and release all the resources of
 614  * the ASO flow meter management structure.
 615  *
 616  * @param[in] sh
 617  *   Pointer to mlx5_dev_ctx_shared object to free.
 618  */
 619 static void
 620 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 621 {
 622         struct mlx5_aso_mtr_pool *mtr_pool;
 623         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 624         uint32_t idx;
 625 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 626         struct mlx5_aso_mtr *aso_mtr;
 627         int i;
 628 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 629
 630         if (sh->meter_aso_en) {
 631                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 632                 idx = mtrmng->pools_mng.n_valid;
 633                 while (idx--) {
 634                         mtr_pool = mtrmng->pools_mng.pools[idx];
 635 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 636                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 637                                 aso_mtr = &mtr_pool->mtrs[i];
 638                                 if (aso_mtr->fm.meter_action)
 639                                         claim_zero
 640                                         (mlx5_glue->destroy_flow_action
 641                                         (aso_mtr->fm.meter_action));
 642                         }
 643 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 644                         claim_zero(mlx5_devx_cmd_destroy
 645                                                 (mtr_pool->devx_obj));
 646                         mtrmng->pools_mng.n_valid--;
 647                         mlx5_free(mtr_pool);
 648                 }
 649                 mlx5_free(sh->mtrmng->pools_mng.pools);
 650         }
 651         mlx5_free(sh->mtrmng);
 652         sh->mtrmng = NULL;
 653 }
 654
 655 /* Send FLOW_AGED event if needed. */
 656 void
 657 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 658 {
 659         struct mlx5_age_info *age_info;
 660         uint32_t i;
 661
 662         for (i = 0; i < sh->max_port; i++) {
 663                 age_info = &sh->port[i].age_info;
 664                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 665                         continue;
 666                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 667                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 668                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 669                         rte_eth_dev_callback_process
 670                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 671                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 672                 }
 673         }
 674 }
 675
 676 /*
 677  * Initialize the ASO connection tracking structure.
 678  *
 679  * @param[in] sh
 680  *   Pointer to mlx5_dev_ctx_shared object.
 681  *
 682  * @return
 683  *   0 on success, a negative errno value otherwise and rte_errno is set.
 684  */
 685 int
 686 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 687 {
 688         int err;
 689
 690         if (sh->ct_mng)
 691                 return 0;
 692         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 693                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 694         if (!sh->ct_mng) {
 695                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 696                 rte_errno = ENOMEM;
 697                 return -rte_errno;
 698         }
 699         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 700         if (err) {
 701                 mlx5_free(sh->ct_mng);
 702                 /* rte_errno should be extracted from the failure. */
 703                 rte_errno = EINVAL;
 704                 return -rte_errno;
 705         }
 706         rte_spinlock_init(&sh->ct_mng->ct_sl);
 707         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 708         LIST_INIT(&sh->ct_mng->free_cts);
 709         return 0;
 710 }
 711
 712 /*
 713  * Close and release all the resources of the
 714  * ASO connection tracking management structure.
 715  *
 716  * @param[in] sh
 717  *   Pointer to mlx5_dev_ctx_shared object to free.
 718  */
 719 static void
 720 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 721 {
 722         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 723         struct mlx5_aso_ct_pool *ct_pool;
 724         struct mlx5_aso_ct_action *ct;
 725         uint32_t idx;
 726         uint32_t val;
 727         uint32_t cnt;
 728         int i;
 729
 730         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 731         idx = mng->next;
 732         while (idx--) {
 733                 cnt = 0;
 734                 ct_pool = mng->pools[idx];
 735                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 736                         ct = &ct_pool->actions[i];
 737                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 738                                                  __ATOMIC_RELAXED);
 739                         MLX5_ASSERT(val == 1);
 740                         if (val > 1)
 741                                 cnt++;
 742 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 743                         if (ct->dr_action_orig)
 744                                 claim_zero(mlx5_glue->destroy_flow_action
 745                                                         (ct->dr_action_orig));
 746                         if (ct->dr_action_rply)
 747                                 claim_zero(mlx5_glue->destroy_flow_action
 748                                                         (ct->dr_action_rply));
 749 #endif
 750                 }
 751                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 752                 if (cnt) {
 753                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 754                                 cnt, i);
 755                 }
 756                 mlx5_free(ct_pool);
 757                 /* in case of failure. */
 758                 mng->next--;
 759         }
 760         mlx5_free(mng->pools);
 761         mlx5_free(mng);
 762         /* Management structure must be cleared to 0s during allocation. */
 763         sh->ct_mng = NULL;
 764 }
 765
 766 /**
 767  * Initialize the flow resources' indexed mempool.
 768  *
 769  * @param[in] sh
 770  *   Pointer to mlx5_dev_ctx_shared object.
 771  * @param[in] config
 772  *   Pointer to user dev config.
 773  */
 774 static void
 775 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 776                        const struct mlx5_dev_config *config)
 777 {
 778         uint8_t i;
 779         struct mlx5_indexed_pool_config cfg;
 780
 781         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 782                 cfg = mlx5_ipool_cfg[i];
 783                 switch (i) {
 784                 default:
 785                         break;
 786                 /*
 787                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 788                  * according to PCI function flow configuration.
 789                  */
 790                 case MLX5_IPOOL_MLX5_FLOW:
 791                         cfg.size = config->dv_flow_en ?
 792                                 sizeof(struct mlx5_flow_handle) :
 793                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 794                         break;
 795                 }
 796                 if (config->reclaim_mode)
 797                         cfg.release_mem_en = 1;
 798                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 799         }
 800 }
 801
 802 /**
 803  * Release the flow resources' indexed mempool.
 804  *
 805  * @param[in] sh
 806  *   Pointer to mlx5_dev_ctx_shared object.
 807  */
 808 static void
 809 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 810 {
 811         uint8_t i;
 812
 813         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 814                 mlx5_ipool_destroy(sh->ipool[i]);
 815 }
 816
 817 /*
 818  * Check if dynamic flex parser for eCPRI already exists.
 819  *
 820  * @param dev
 821  *   Pointer to Ethernet device structure.
 822  *
 823  * @return
 824  *   true on exists, false on not.
 825  */
 826 bool
 827 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 828 {
 829         struct mlx5_priv *priv = dev->data->dev_private;
 830         struct mlx5_flex_parser_profiles *prf =
 831                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 832
 833         return !!prf->obj;
 834 }
 835
 836 /*
 837  * Allocation of a flex parser for eCPRI. Once created, this parser related
 838  * resources will be held until the device is closed.
 839  *
 840  * @param dev
 841  *   Pointer to Ethernet device structure.
 842  *
 843  * @return
 844  *   0 on success, a negative errno value otherwise and rte_errno is set.
 845  */
 846 int
 847 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 848 {
 849         struct mlx5_priv *priv = dev->data->dev_private;
 850         struct mlx5_flex_parser_profiles *prf =
 851                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 852         struct mlx5_devx_graph_node_attr node = {
 853                 .modify_field_select = 0,
 854         };
 855         uint32_t ids[8];
 856         int ret;
 857
 858         if (!priv->config.hca_attr.parse_graph_flex_node) {
 859                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 860                         "for device %s.", priv->dev_data->name);
 861                 return -ENOTSUP;
 862         }
 863         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 864         /* 8 bytes now: 4B common header + 4B message body header. */
 865         node.header_length_base_value = 0x8;
 866         /* After MAC layer: Ether / VLAN. */
 867         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 868         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 869         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 870         /* Sample #0: type in common header. */
 871         node.sample[0].flow_match_sample_en = 1;
 872         /* Fixed offset. */
 873         node.sample[0].flow_match_sample_offset_mode = 0x0;
 874         /* Only the 2nd byte will be used. */
 875         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 876         /* Sample #1: message payload. */
 877         node.sample[1].flow_match_sample_en = 1;
 878         /* Fixed offset. */
 879         node.sample[1].flow_match_sample_offset_mode = 0x0;
 880         /*
 881          * Only the first two bytes will be used right now, and its offset will
 882          * start after the common header that with the length of a DW(u32).
 883          */
 884         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 885         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 886         if (!prf->obj) {
 887                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 888                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 889         }
 890         prf->num = 2;
 891         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 892         if (ret) {
 893                 DRV_LOG(ERR, "Failed to query sample IDs.");
 894                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 895         }
 896         prf->offset[0] = 0x0;
 897         prf->offset[1] = sizeof(uint32_t);
 898         prf->ids[0] = ids[0];
 899         prf->ids[1] = ids[1];
 900         return 0;
 901 }
 902
 903 /*
 904  * Destroy the flex parser node, including the parser itself, input / output
 905  * arcs and DW samples. Resources could be reused then.
 906  *
 907  * @param dev
 908  *   Pointer to Ethernet device structure.
 909  */
 910 static void
 911 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 912 {
 913         struct mlx5_priv *priv = dev->data->dev_private;
 914         struct mlx5_flex_parser_profiles *prf =
 915                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 916
 917         if (prf->obj)
 918                 mlx5_devx_cmd_destroy(prf->obj);
 919         prf->obj = NULL;
 920 }
 921
 922 /*
 923  * Allocate Rx and Tx UARs in robust fashion.
 924  * This routine handles the following UAR allocation issues:
 925  *
 926  *  - tries to allocate the UAR with the most appropriate memory
 927  *    mapping type from the ones supported by the host
 928  *
 929  *  - tries to allocate the UAR with non-NULL base address
 930  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 931  *    UAR base address if UAR was not the first object in the UAR page.
 932  *    It caused the PMD failure and we should try to get another UAR
 933  *    till we get the first one with non-NULL base address returned.
 934  */
 935 static int
 936 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 937                      const struct mlx5_dev_config *config)
 938 {
 939         uint32_t uar_mapping, retry;
 940         int err = 0;
 941         void *base_addr;
 942
 943         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 944 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 945                 /* Control the mapping type according to the settings. */
 946                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 947                               MLX5DV_UAR_ALLOC_TYPE_NC :
 948                               MLX5DV_UAR_ALLOC_TYPE_BF;
 949 #else
 950                 RTE_SET_USED(config);
 951                 /*
 952                  * It seems we have no way to control the memory mapping type
 953                  * for the UAR, the default "Write-Combining" type is supposed.
 954                  * The UAR initialization on queue creation queries the
 955                  * actual mapping type done by Verbs/kernel and setups the
 956                  * PMD datapath accordingly.
 957                  */
 958                 uar_mapping = 0;
 959 #endif
 960                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 961 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 962                 if (!sh->tx_uar &&
 963                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 964                         if (config->dbnc == MLX5_TXDB_CACHED ||
 965                             config->dbnc == MLX5_TXDB_HEURISTIC)
 966                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 967                                                  "is not supported by DevX");
 968                         /*
 969                          * In some environments like virtual machine
 970                          * the Write Combining mapped might be not supported
 971                          * and UAR allocation fails. We try "Non-Cached"
 972                          * mapping for the case. The tx_burst routines take
 973                          * the UAR mapping type into account on UAR setup
 974                          * on queue creation.
 975                          */
 976                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 977                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 978                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 979                                                         (sh->ctx, uar_mapping);
 980                 } else if (!sh->tx_uar &&
 981                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 982                         if (config->dbnc == MLX5_TXDB_NCACHED)
 983                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 984                                                  "is not supported by DevX");
 985                         /*
 986                          * If Verbs/kernel does not support "Non-Cached"
 987                          * try the "Write-Combining".
 988                          */
 989                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 990                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 991                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 992                                                         (sh->ctx, uar_mapping);
 993                 }
 994 #endif
 995                 if (!sh->tx_uar) {
 996                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 997                         err = ENOMEM;
 998                         goto exit;
 999                 }
1000                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1001                 if (base_addr)
1002                         break;
1003                 /*
1004                  * The UARs are allocated by rdma_core within the
1005                  * IB device context, on context closure all UARs
1006                  * will be freed, should be no memory/object leakage.
1007                  */
1008                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1009                 sh->tx_uar = NULL;
1010         }
1011         /* Check whether we finally succeeded with valid UAR allocation. */
1012         if (!sh->tx_uar) {
1013                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1014                 err = ENOMEM;
1015                 goto exit;
1016         }
1017         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1018                 uar_mapping = 0;
1019                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1020                                                         (sh->ctx, uar_mapping);
1021 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1022                 if (!sh->devx_rx_uar &&
1023                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1024                         /*
1025                          * Rx UAR is used to control interrupts only,
1026                          * should be no datapath noticeable impact,
1027                          * can try "Non-Cached" mapping safely.
1028                          */
1029                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1030                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1031                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1032                                                         (sh->ctx, uar_mapping);
1033                 }
1034 #endif
1035                 if (!sh->devx_rx_uar) {
1036                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1037                         err = ENOMEM;
1038                         goto exit;
1039                 }
1040                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1041                 if (base_addr)
1042                         break;
1043                 /*
1044                  * The UARs are allocated by rdma_core within the
1045                  * IB device context, on context closure all UARs
1046                  * will be freed, should be no memory/object leakage.
1047                  */
1048                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1049                 sh->devx_rx_uar = NULL;
1050         }
1051         /* Check whether we finally succeeded with valid UAR allocation. */
1052         if (!sh->devx_rx_uar) {
1053                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1054                 err = ENOMEM;
1055         }
1056 exit:
1057         return err;
1058 }
1059
1060 /**
1061  * Allocate shared device context. If there is multiport device the
1062  * master and representors will share this context, if there is single
1063  * port dedicated device, the context will be used by only given
1064  * port due to unification.
1065  *
1066  * Routine first searches the context for the specified device name,
1067  * if found the shared context assumed and reference counter is incremented.
1068  * If no context found the new one is created and initialized with specified
1069  * device context and parameters.
1070  *
1071  * @param[in] spawn
1072  *   Pointer to the device attributes (name, port, etc).
1073  * @param[in] config
1074  *   Pointer to device configuration structure.
1075  *
1076  * @return
1077  *   Pointer to mlx5_dev_ctx_shared object on success,
1078  *   otherwise NULL and rte_errno is set.
1079  */
1080 struct mlx5_dev_ctx_shared *
1081 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1082                            const struct mlx5_dev_config *config)
1083 {
1084         struct mlx5_dev_ctx_shared *sh;
1085         int err = 0;
1086         uint32_t i;
1087         struct mlx5_devx_tis_attr tis_attr = { 0 };
1088
1089         MLX5_ASSERT(spawn);
1090         /* Secondary process should not create the shared context. */
1091         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1092         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1093         /* Search for IB context by device name. */
1094         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1095                 if (!strcmp(sh->ibdev_name,
1096                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1097                         sh->refcnt++;
1098                         goto exit;
1099                 }
1100         }
1101         /* No device found, we have to create new shared context. */
1102         MLX5_ASSERT(spawn->max_port);
1103         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1104                          sizeof(struct mlx5_dev_ctx_shared) +
1105                          spawn->max_port *
1106                          sizeof(struct mlx5_dev_shared_port),
1107                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1108         if (!sh) {
1109                 DRV_LOG(ERR, "shared context allocation failure");
1110                 rte_errno  = ENOMEM;
1111                 goto exit;
1112         }
1113         if (spawn->bond_info)
1114                 sh->bond = *spawn->bond_info;
1115         err = mlx5_os_open_device(spawn, config, sh);
1116         if (!sh->ctx)
1117                 goto error;
1118         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1119         if (err) {
1120                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1121                 goto error;
1122         }
1123         sh->refcnt = 1;
1124         sh->max_port = spawn->max_port;
1125         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1126                 sizeof(sh->ibdev_name) - 1);
1127         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1128                 sizeof(sh->ibdev_path) - 1);
1129         /*
1130          * Setting port_id to max unallowed value means
1131          * there is no interrupt subhandler installed for
1132          * the given port index i.
1133          */
1134         for (i = 0; i < sh->max_port; i++) {
1135                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1136                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1137         }
1138         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1139         if (sh->pd == NULL) {
1140                 DRV_LOG(ERR, "PD allocation failure");
1141                 err = ENOMEM;
1142                 goto error;
1143         }
1144         if (sh->devx) {
1145                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1146                 if (err) {
1147                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1148                         goto error;
1149                 }
1150                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1151                 if (!sh->td) {
1152                         DRV_LOG(ERR, "TD allocation failure");
1153                         err = ENOMEM;
1154                         goto error;
1155                 }
1156                 tis_attr.transport_domain = sh->td->id;
1157                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1158                 if (!sh->tis) {
1159                         DRV_LOG(ERR, "TIS allocation failure");
1160                         err = ENOMEM;
1161                         goto error;
1162                 }
1163                 err = mlx5_alloc_rxtx_uars(sh, config);
1164                 if (err)
1165                         goto error;
1166                 MLX5_ASSERT(sh->tx_uar);
1167                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1168
1169                 MLX5_ASSERT(sh->devx_rx_uar);
1170                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1171         }
1172 #ifndef RTE_ARCH_64
1173         /* Initialize UAR access locks for 32bit implementations. */
1174         rte_spinlock_init(&sh->uar_lock_cq);
1175         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1176                 rte_spinlock_init(&sh->uar_lock[i]);
1177 #endif
1178         /*
1179          * Once the device is added to the list of memory event
1180          * callback, its global MR cache table cannot be expanded
1181          * on the fly because of deadlock. If it overflows, lookup
1182          * should be done by searching MR list linearly, which is slow.
1183          *
1184          * At this point the device is not added to the memory
1185          * event list yet, context is just being created.
1186          */
1187         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1188                                  MLX5_MR_BTREE_CACHE_N * 2,
1189                                  spawn->pci_dev->device.numa_node);
1190         if (err) {
1191                 err = rte_errno;
1192                 goto error;
1193         }
1194         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1195                               &sh->share_cache.dereg_mr_cb);
1196         mlx5_os_dev_shared_handler_install(sh);
1197         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1198         if (!sh->cnt_id_tbl) {
1199                 err = rte_errno;
1200                 goto error;
1201         }
1202         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1203                 err = mlx5_flow_os_init_workspace_once();
1204                 if (err)
1205                         goto error;
1206         }
1207         mlx5_flow_aging_init(sh);
1208         mlx5_flow_counters_mng_init(sh);
1209         mlx5_flow_ipool_create(sh, config);
1210         /* Add device to memory callback list. */
1211         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1212         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1213                          sh, mem_event_cb);
1214         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1215         /* Add context to the global device list. */
1216         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1217         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1218 exit:
1219         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1220         return sh;
1221 error:
1222         pthread_mutex_destroy(&sh->txpp.mutex);
1223         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1224         MLX5_ASSERT(sh);
1225         if (sh->cnt_id_tbl)
1226                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1227         if (sh->tis)
1228                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1229         if (sh->td)
1230                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1231         if (sh->devx_rx_uar)
1232                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1233         if (sh->tx_uar)
1234                 mlx5_glue->devx_free_uar(sh->tx_uar);
1235         if (sh->pd)
1236                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1237         if (sh->ctx)
1238                 claim_zero(mlx5_glue->close_device(sh->ctx));
1239         mlx5_free(sh);
1240         MLX5_ASSERT(err > 0);
1241         rte_errno = err;
1242         return NULL;
1243 }
1244
1245 /**
1246  * Free shared IB device context. Decrement counter and if zero free
1247  * all allocated resources and close handles.
1248  *
1249  * @param[in] sh
1250  *   Pointer to mlx5_dev_ctx_shared object to free
1251  */
1252 void
1253 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1254 {
1255         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1256 #ifdef RTE_LIBRTE_MLX5_DEBUG
1257         /* Check the object presence in the list. */
1258         struct mlx5_dev_ctx_shared *lctx;
1259
1260         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1261                 if (lctx == sh)
1262                         break;
1263         MLX5_ASSERT(lctx);
1264         if (lctx != sh) {
1265                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1266                 goto exit;
1267         }
1268 #endif
1269         MLX5_ASSERT(sh);
1270         MLX5_ASSERT(sh->refcnt);
1271         /* Secondary process should not free the shared context. */
1272         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1273         if (--sh->refcnt)
1274                 goto exit;
1275         /* Remove from memory callback device list. */
1276         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1277         LIST_REMOVE(sh, mem_event_cb);
1278         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1279         /* Release created Memory Regions. */
1280         mlx5_mr_release_cache(&sh->share_cache);
1281         /* Remove context from the global device list. */
1282         LIST_REMOVE(sh, next);
1283         /* Release flow workspaces objects on the last device. */
1284         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1285                 mlx5_flow_os_release_workspace();
1286         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1287         /*
1288          *  Ensure there is no async event handler installed.
1289          *  Only primary process handles async device events.
1290          **/
1291         mlx5_flow_counters_mng_close(sh);
1292         if (sh->aso_age_mng) {
1293                 mlx5_flow_aso_age_mng_close(sh);
1294                 sh->aso_age_mng = NULL;
1295         }
1296         if (sh->mtrmng)
1297                 mlx5_aso_flow_mtrs_mng_close(sh);
1298         mlx5_flow_ipool_destroy(sh);
1299         mlx5_os_dev_shared_handler_uninstall(sh);
1300         if (sh->cnt_id_tbl) {
1301                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1302                 sh->cnt_id_tbl = NULL;
1303         }
1304         if (sh->tx_uar) {
1305                 mlx5_glue->devx_free_uar(sh->tx_uar);
1306                 sh->tx_uar = NULL;
1307         }
1308         if (sh->pd)
1309                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1310         if (sh->tis)
1311                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1312         if (sh->td)
1313                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1314         if (sh->devx_rx_uar)
1315                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1316         if (sh->ctx)
1317                 claim_zero(mlx5_glue->close_device(sh->ctx));
1318         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1319         pthread_mutex_destroy(&sh->txpp.mutex);
1320         mlx5_free(sh);
1321         return;
1322 exit:
1323         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1324 }
1325
1326 /**
1327  * Destroy table hash list.
1328  *
1329  * @param[in] priv
1330  *   Pointer to the private device data structure.
1331  */
1332 void
1333 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1334 {
1335         struct mlx5_dev_ctx_shared *sh = priv->sh;
1336
1337         if (!sh->flow_tbls)
1338                 return;
1339         mlx5_hlist_destroy(sh->flow_tbls);
1340 }
1341
1342 /**
1343  * Initialize flow table hash list and create the root tables entry
1344  * for each domain.
1345  *
1346  * @param[in] priv
1347  *   Pointer to the private device data structure.
1348  *
1349  * @return
1350  *   Zero on success, positive error code otherwise.
1351  */
1352 int
1353 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1354 {
1355         int err = 0;
1356         /* Tables are only used in DV and DR modes. */
1357 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1358         struct mlx5_dev_ctx_shared *sh = priv->sh;
1359         char s[MLX5_HLIST_NAMESIZE];
1360
1361         MLX5_ASSERT(sh);
1362         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1363         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1364                                           0, 0, flow_dv_tbl_create_cb,
1365                                           flow_dv_tbl_match_cb,
1366                                           flow_dv_tbl_remove_cb);
1367         if (!sh->flow_tbls) {
1368                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1369                 err = ENOMEM;
1370                 return err;
1371         }
1372         sh->flow_tbls->ctx = sh;
1373 #ifndef HAVE_MLX5DV_DR
1374         struct rte_flow_error error;
1375         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1376
1377         /*
1378          * In case we have not DR support, the zero tables should be created
1379          * because DV expect to see them even if they cannot be created by
1380          * RDMA-CORE.
1381          */
1382         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1383                 NULL, 0, 1, 0, &error) ||
1384             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1385                 NULL, 0, 1, 0, &error) ||
1386             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1387                 NULL, 0, 1, 0, &error)) {
1388                 err = ENOMEM;
1389                 goto error;
1390         }
1391         return err;
1392 error:
1393         mlx5_free_table_hash_list(priv);
1394 #endif /* HAVE_MLX5DV_DR */
1395 #endif
1396         return err;
1397 }
1398
1399 /**
1400  * Retrieve integer value from environment variable.
1401  *
1402  * @param[in] name
1403  *   Environment variable name.
1404  *
1405  * @return
1406  *   Integer value, 0 if the variable is not set.
1407  */
1408 int
1409 mlx5_getenv_int(const char *name)
1410 {
1411         const char *val = getenv(name);
1412
1413         if (val == NULL)
1414                 return 0;
1415         return atoi(val);
1416 }
1417
1418 /**
1419  * DPDK callback to add udp tunnel port
1420  *
1421  * @param[in] dev
1422  *   A pointer to eth_dev
1423  * @param[in] udp_tunnel
1424  *   A pointer to udp tunnel
1425  *
1426  * @return
1427  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1428  */
1429 int
1430 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1431                          struct rte_eth_udp_tunnel *udp_tunnel)
1432 {
1433         MLX5_ASSERT(udp_tunnel != NULL);
1434         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1435             udp_tunnel->udp_port == 4789)
1436                 return 0;
1437         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1438             udp_tunnel->udp_port == 4790)
1439                 return 0;
1440         return -ENOTSUP;
1441 }
1442
1443 /**
1444  * Initialize process private data structure.
1445  *
1446  * @param dev
1447  *   Pointer to Ethernet device structure.
1448  *
1449  * @return
1450  *   0 on success, a negative errno value otherwise and rte_errno is set.
1451  */
1452 int
1453 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1454 {
1455         struct mlx5_priv *priv = dev->data->dev_private;
1456         struct mlx5_proc_priv *ppriv;
1457         size_t ppriv_size;
1458
1459         mlx5_proc_priv_uninit(dev);
1460         /*
1461          * UAR register table follows the process private structure. BlueFlame
1462          * registers for Tx queues are stored in the table.
1463          */
1464         ppriv_size =
1465                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1466         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1467                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1468         if (!ppriv) {
1469                 rte_errno = ENOMEM;
1470                 return -rte_errno;
1471         }
1472         ppriv->uar_table_sz = priv->txqs_n;
1473         dev->process_private = ppriv;
1474         return 0;
1475 }
1476
1477 /**
1478  * Un-initialize process private data structure.
1479  *
1480  * @param dev
1481  *   Pointer to Ethernet device structure.
1482  */
1483 void
1484 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1485 {
1486         if (!dev->process_private)
1487                 return;
1488         mlx5_free(dev->process_private);
1489         dev->process_private = NULL;
1490 }
1491
1492 /**
1493  * DPDK callback to close the device.
1494  *
1495  * Destroy all queues and objects, free memory.
1496  *
1497  * @param dev
1498  *   Pointer to Ethernet device structure.
1499  */
1500 int
1501 mlx5_dev_close(struct rte_eth_dev *dev)
1502 {
1503         struct mlx5_priv *priv = dev->data->dev_private;
1504         unsigned int i;
1505         int ret;
1506
1507         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1508                 /* Check if process_private released. */
1509                 if (!dev->process_private)
1510                         return 0;
1511                 mlx5_tx_uar_uninit_secondary(dev);
1512                 mlx5_proc_priv_uninit(dev);
1513                 rte_eth_dev_release_port(dev);
1514                 return 0;
1515         }
1516         if (!priv->sh)
1517                 return 0;
1518         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1519                 dev->data->port_id,
1520                 ((priv->sh->ctx != NULL) ?
1521                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1522         /*
1523          * If default mreg copy action is removed at the stop stage,
1524          * the search will return none and nothing will be done anymore.
1525          */
1526         mlx5_flow_stop_default(dev);
1527         mlx5_traffic_disable(dev);
1528         /*
1529          * If all the flows are already flushed in the device stop stage,
1530          * then this will return directly without any action.
1531          */
1532         mlx5_flow_list_flush(dev, &priv->flows, true);
1533         mlx5_action_handle_flush(dev);
1534         mlx5_flow_meter_flush(dev, NULL);
1535         /* Prevent crashes when queues are still in use. */
1536         dev->rx_pkt_burst = removed_rx_burst;
1537         dev->tx_pkt_burst = removed_tx_burst;
1538         rte_wmb();
1539         /* Disable datapath on secondary process. */
1540         mlx5_mp_os_req_stop_rxtx(dev);
1541         /* Free the eCPRI flex parser resource. */
1542         mlx5_flex_parser_ecpri_release(dev);
1543         if (priv->rxqs != NULL) {
1544                 /* XXX race condition if mlx5_rx_burst() is still running. */
1545                 rte_delay_us_sleep(1000);
1546                 for (i = 0; (i != priv->rxqs_n); ++i)
1547                         mlx5_rxq_release(dev, i);
1548                 priv->rxqs_n = 0;
1549                 priv->rxqs = NULL;
1550         }
1551         if (priv->txqs != NULL) {
1552                 /* XXX race condition if mlx5_tx_burst() is still running. */
1553                 rte_delay_us_sleep(1000);
1554                 for (i = 0; (i != priv->txqs_n); ++i)
1555                         mlx5_txq_release(dev, i);
1556                 priv->txqs_n = 0;
1557                 priv->txqs = NULL;
1558         }
1559         mlx5_proc_priv_uninit(dev);
1560         if (priv->q_counters) {
1561                 mlx5_devx_cmd_destroy(priv->q_counters);
1562                 priv->q_counters = NULL;
1563         }
1564         if (priv->drop_queue.hrxq)
1565                 mlx5_drop_action_destroy(dev);
1566         if (priv->mreg_cp_tbl)
1567                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1568         mlx5_mprq_free_mp(dev);
1569         if (priv->sh->ct_mng)
1570                 mlx5_flow_aso_ct_mng_close(priv->sh);
1571         mlx5_os_free_shared_dr(priv);
1572         if (priv->rss_conf.rss_key != NULL)
1573                 mlx5_free(priv->rss_conf.rss_key);
1574         if (priv->reta_idx != NULL)
1575                 mlx5_free(priv->reta_idx);
1576         if (priv->config.vf)
1577                 mlx5_os_mac_addr_flush(dev);
1578         if (priv->nl_socket_route >= 0)
1579                 close(priv->nl_socket_route);
1580         if (priv->nl_socket_rdma >= 0)
1581                 close(priv->nl_socket_rdma);
1582         if (priv->vmwa_context)
1583                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1584         ret = mlx5_hrxq_verify(dev);
1585         if (ret)
1586                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1587                         dev->data->port_id);
1588         ret = mlx5_ind_table_obj_verify(dev);
1589         if (ret)
1590                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1591                         dev->data->port_id);
1592         ret = mlx5_rxq_obj_verify(dev);
1593         if (ret)
1594                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1595                         dev->data->port_id);
1596         ret = mlx5_rxq_verify(dev);
1597         if (ret)
1598                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1599                         dev->data->port_id);
1600         ret = mlx5_txq_obj_verify(dev);
1601         if (ret)
1602                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1603                         dev->data->port_id);
1604         ret = mlx5_txq_verify(dev);
1605         if (ret)
1606                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1607                         dev->data->port_id);
1608         ret = mlx5_flow_verify(dev);
1609         if (ret)
1610                 DRV_LOG(WARNING, "port %u some flows still remain",
1611                         dev->data->port_id);
1612         mlx5_cache_list_destroy(&priv->hrxqs);
1613         /*
1614          * Free the shared context in last turn, because the cleanup
1615          * routines above may use some shared fields, like
1616          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1617          * ifindex if Netlink fails.
1618          */
1619         mlx5_free_shared_dev_ctx(priv->sh);
1620         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1621                 unsigned int c = 0;
1622                 uint16_t port_id;
1623
1624                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1625                         struct mlx5_priv *opriv =
1626                                 rte_eth_devices[port_id].data->dev_private;
1627
1628                         if (!opriv ||
1629                             opriv->domain_id != priv->domain_id ||
1630                             &rte_eth_devices[port_id] == dev)
1631                                 continue;
1632                         ++c;
1633                         break;
1634                 }
1635                 if (!c)
1636                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1637         }
1638         memset(priv, 0, sizeof(*priv));
1639         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1640         /*
1641          * Reset mac_addrs to NULL such that it is not freed as part of
1642          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1643          * it is freed when dev_private is freed.
1644          */
1645         dev->data->mac_addrs = NULL;
1646         return 0;
1647 }
1648
1649 const struct eth_dev_ops mlx5_dev_ops = {
1650         .dev_configure = mlx5_dev_configure,
1651         .dev_start = mlx5_dev_start,
1652         .dev_stop = mlx5_dev_stop,
1653         .dev_set_link_down = mlx5_set_link_down,
1654         .dev_set_link_up = mlx5_set_link_up,
1655         .dev_close = mlx5_dev_close,
1656         .promiscuous_enable = mlx5_promiscuous_enable,
1657         .promiscuous_disable = mlx5_promiscuous_disable,
1658         .allmulticast_enable = mlx5_allmulticast_enable,
1659         .allmulticast_disable = mlx5_allmulticast_disable,
1660         .link_update = mlx5_link_update,
1661         .stats_get = mlx5_stats_get,
1662         .stats_reset = mlx5_stats_reset,
1663         .xstats_get = mlx5_xstats_get,
1664         .xstats_reset = mlx5_xstats_reset,
1665         .xstats_get_names = mlx5_xstats_get_names,
1666         .fw_version_get = mlx5_fw_version_get,
1667         .dev_infos_get = mlx5_dev_infos_get,
1668         .representor_info_get = mlx5_representor_info_get,
1669         .read_clock = mlx5_txpp_read_clock,
1670         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1671         .vlan_filter_set = mlx5_vlan_filter_set,
1672         .rx_queue_setup = mlx5_rx_queue_setup,
1673         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1674         .tx_queue_setup = mlx5_tx_queue_setup,
1675         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1676         .rx_queue_release = mlx5_rx_queue_release,
1677         .tx_queue_release = mlx5_tx_queue_release,
1678         .rx_queue_start = mlx5_rx_queue_start,
1679         .rx_queue_stop = mlx5_rx_queue_stop,
1680         .tx_queue_start = mlx5_tx_queue_start,
1681         .tx_queue_stop = mlx5_tx_queue_stop,
1682         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1683         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1684         .mac_addr_remove = mlx5_mac_addr_remove,
1685         .mac_addr_add = mlx5_mac_addr_add,
1686         .mac_addr_set = mlx5_mac_addr_set,
1687         .set_mc_addr_list = mlx5_set_mc_addr_list,
1688         .mtu_set = mlx5_dev_set_mtu,
1689         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1690         .vlan_offload_set = mlx5_vlan_offload_set,
1691         .reta_update = mlx5_dev_rss_reta_update,
1692         .reta_query = mlx5_dev_rss_reta_query,
1693         .rss_hash_update = mlx5_rss_hash_update,
1694         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1695         .flow_ops_get = mlx5_flow_ops_get,
1696         .rxq_info_get = mlx5_rxq_info_get,
1697         .txq_info_get = mlx5_txq_info_get,
1698         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1699         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1700         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1701         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1702         .is_removed = mlx5_is_removed,
1703         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1704         .get_module_info = mlx5_get_module_info,
1705         .get_module_eeprom = mlx5_get_module_eeprom,
1706         .hairpin_cap_get = mlx5_hairpin_cap_get,
1707         .mtr_ops_get = mlx5_flow_meter_ops_get,
1708         .hairpin_bind = mlx5_hairpin_bind,
1709         .hairpin_unbind = mlx5_hairpin_unbind,
1710         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1711         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1712         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1713         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1714         .get_monitor_addr = mlx5_get_monitor_addr,
1715 };
1716
1717 /* Available operations from secondary process. */
1718 const struct eth_dev_ops mlx5_dev_sec_ops = {
1719         .stats_get = mlx5_stats_get,
1720         .stats_reset = mlx5_stats_reset,
1721         .xstats_get = mlx5_xstats_get,
1722         .xstats_reset = mlx5_xstats_reset,
1723         .xstats_get_names = mlx5_xstats_get_names,
1724         .fw_version_get = mlx5_fw_version_get,
1725         .dev_infos_get = mlx5_dev_infos_get,
1726         .read_clock = mlx5_txpp_read_clock,
1727         .rx_queue_start = mlx5_rx_queue_start,
1728         .rx_queue_stop = mlx5_rx_queue_stop,
1729         .tx_queue_start = mlx5_tx_queue_start,
1730         .tx_queue_stop = mlx5_tx_queue_stop,
1731         .rxq_info_get = mlx5_rxq_info_get,
1732         .txq_info_get = mlx5_txq_info_get,
1733         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1734         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1735         .get_module_info = mlx5_get_module_info,
1736         .get_module_eeprom = mlx5_get_module_eeprom,
1737 };
1738
1739 /* Available operations in flow isolated mode. */
1740 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1741         .dev_configure = mlx5_dev_configure,
1742         .dev_start = mlx5_dev_start,
1743         .dev_stop = mlx5_dev_stop,
1744         .dev_set_link_down = mlx5_set_link_down,
1745         .dev_set_link_up = mlx5_set_link_up,
1746         .dev_close = mlx5_dev_close,
1747         .promiscuous_enable = mlx5_promiscuous_enable,
1748         .promiscuous_disable = mlx5_promiscuous_disable,
1749         .allmulticast_enable = mlx5_allmulticast_enable,
1750         .allmulticast_disable = mlx5_allmulticast_disable,
1751         .link_update = mlx5_link_update,
1752         .stats_get = mlx5_stats_get,
1753         .stats_reset = mlx5_stats_reset,
1754         .xstats_get = mlx5_xstats_get,
1755         .xstats_reset = mlx5_xstats_reset,
1756         .xstats_get_names = mlx5_xstats_get_names,
1757         .fw_version_get = mlx5_fw_version_get,
1758         .dev_infos_get = mlx5_dev_infos_get,
1759         .read_clock = mlx5_txpp_read_clock,
1760         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1761         .vlan_filter_set = mlx5_vlan_filter_set,
1762         .rx_queue_setup = mlx5_rx_queue_setup,
1763         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1764         .tx_queue_setup = mlx5_tx_queue_setup,
1765         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1766         .rx_queue_release = mlx5_rx_queue_release,
1767         .tx_queue_release = mlx5_tx_queue_release,
1768         .rx_queue_start = mlx5_rx_queue_start,
1769         .rx_queue_stop = mlx5_rx_queue_stop,
1770         .tx_queue_start = mlx5_tx_queue_start,
1771         .tx_queue_stop = mlx5_tx_queue_stop,
1772         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1773         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1774         .mac_addr_remove = mlx5_mac_addr_remove,
1775         .mac_addr_add = mlx5_mac_addr_add,
1776         .mac_addr_set = mlx5_mac_addr_set,
1777         .set_mc_addr_list = mlx5_set_mc_addr_list,
1778         .mtu_set = mlx5_dev_set_mtu,
1779         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1780         .vlan_offload_set = mlx5_vlan_offload_set,
1781         .flow_ops_get = mlx5_flow_ops_get,
1782         .rxq_info_get = mlx5_rxq_info_get,
1783         .txq_info_get = mlx5_txq_info_get,
1784         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1785         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1786         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1787         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1788         .is_removed = mlx5_is_removed,
1789         .get_module_info = mlx5_get_module_info,
1790         .get_module_eeprom = mlx5_get_module_eeprom,
1791         .hairpin_cap_get = mlx5_hairpin_cap_get,
1792         .mtr_ops_get = mlx5_flow_meter_ops_get,
1793         .hairpin_bind = mlx5_hairpin_bind,
1794         .hairpin_unbind = mlx5_hairpin_unbind,
1795         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1796         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1797         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1798         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1799         .get_monitor_addr = mlx5_get_monitor_addr,
1800 };
1801
1802 /**
1803  * Verify and store value for device argument.
1804  *
1805  * @param[in] key
1806  *   Key argument to verify.
1807  * @param[in] val
1808  *   Value associated with key.
1809  * @param opaque
1810  *   User data.
1811  *
1812  * @return
1813  *   0 on success, a negative errno value otherwise and rte_errno is set.
1814  */
1815 static int
1816 mlx5_args_check(const char *key, const char *val, void *opaque)
1817 {
1818         struct mlx5_dev_config *config = opaque;
1819         unsigned long mod;
1820         signed long tmp;
1821
1822         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1823         if (!strcmp(MLX5_REPRESENTOR, key))
1824                 return 0;
1825         errno = 0;
1826         tmp = strtol(val, NULL, 0);
1827         if (errno) {
1828                 rte_errno = errno;
1829                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1830                 return -rte_errno;
1831         }
1832         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1833                 /* Negative values are acceptable for some keys only. */
1834                 rte_errno = EINVAL;
1835                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1836                 return -rte_errno;
1837         }
1838         mod = tmp >= 0 ? tmp : -tmp;
1839         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1840                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1841                         DRV_LOG(ERR, "invalid CQE compression "
1842                                      "format parameter");
1843                         rte_errno = EINVAL;
1844                         return -rte_errno;
1845                 }
1846                 config->cqe_comp = !!tmp;
1847                 config->cqe_comp_fmt = tmp;
1848         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1849                 config->hw_padding = !!tmp;
1850         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1851                 config->mprq.enabled = !!tmp;
1852         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1853                 config->mprq.stride_num_n = tmp;
1854         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1855                 config->mprq.stride_size_n = tmp;
1856         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1857                 config->mprq.max_memcpy_len = tmp;
1858         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1859                 config->mprq.min_rxqs_num = tmp;
1860         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1861                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1862                                  " converted to txq_inline_max", key);
1863                 config->txq_inline_max = tmp;
1864         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1865                 config->txq_inline_max = tmp;
1866         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1867                 config->txq_inline_min = tmp;
1868         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1869                 config->txq_inline_mpw = tmp;
1870         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1871                 config->txqs_inline = tmp;
1872         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1873                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1874         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1875                 config->mps = !!tmp;
1876         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1877                 if (tmp != MLX5_TXDB_CACHED &&
1878                     tmp != MLX5_TXDB_NCACHED &&
1879                     tmp != MLX5_TXDB_HEURISTIC) {
1880                         DRV_LOG(ERR, "invalid Tx doorbell "
1881                                      "mapping parameter");
1882                         rte_errno = EINVAL;
1883                         return -rte_errno;
1884                 }
1885                 config->dbnc = tmp;
1886         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1887                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1888         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1889                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1890                                  " converted to txq_inline_mpw", key);
1891                 config->txq_inline_mpw = tmp;
1892         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1893                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1894         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1895                 if (!mod) {
1896                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1897                         rte_errno = EINVAL;
1898                         return -rte_errno;
1899                 }
1900                 config->tx_pp = tmp;
1901         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1902                 config->tx_skew = tmp;
1903         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1904                 config->rx_vec_en = !!tmp;
1905         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1906                 config->l3_vxlan_en = !!tmp;
1907         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1908                 config->vf_nl_en = !!tmp;
1909         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1910                 config->dv_esw_en = !!tmp;
1911         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1912                 config->dv_flow_en = !!tmp;
1913         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1914                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1915                     tmp != MLX5_XMETA_MODE_META16 &&
1916                     tmp != MLX5_XMETA_MODE_META32 &&
1917                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1918                         DRV_LOG(ERR, "invalid extensive "
1919                                      "metadata parameter");
1920                         rte_errno = EINVAL;
1921                         return -rte_errno;
1922                 }
1923                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1924                         config->dv_xmeta_en = tmp;
1925                 else
1926                         config->dv_miss_info = 1;
1927         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1928                 config->lacp_by_user = !!tmp;
1929         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1930                 config->mr_ext_memseg_en = !!tmp;
1931         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1932                 config->max_dump_files_num = tmp;
1933         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1934                 config->lro.timeout = tmp;
1935         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1936                 DRV_LOG(DEBUG, "class argument is %s.", val);
1937         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1938                 config->log_hp_size = tmp;
1939         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1940                 if (tmp != MLX5_RCM_NONE &&
1941                     tmp != MLX5_RCM_LIGHT &&
1942                     tmp != MLX5_RCM_AGGR) {
1943                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1944                         rte_errno = EINVAL;
1945                         return -rte_errno;
1946                 }
1947                 config->reclaim_mode = tmp;
1948         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1949                 config->sys_mem_en = !!tmp;
1950         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1951                 config->decap_en = !!tmp;
1952         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1953                 config->allow_duplicate_pattern = !!tmp;
1954         } else {
1955                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1956                 rte_errno = EINVAL;
1957                 return -rte_errno;
1958         }
1959         return 0;
1960 }
1961
1962 /**
1963  * Parse device parameters.
1964  *
1965  * @param config
1966  *   Pointer to device configuration structure.
1967  * @param devargs
1968  *   Device arguments structure.
1969  *
1970  * @return
1971  *   0 on success, a negative errno value otherwise and rte_errno is set.
1972  */
1973 int
1974 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1975 {
1976         const char **params = (const char *[]){
1977                 MLX5_RXQ_CQE_COMP_EN,
1978                 MLX5_RXQ_PKT_PAD_EN,
1979                 MLX5_RX_MPRQ_EN,
1980                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1981                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1982                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1983                 MLX5_RXQS_MIN_MPRQ,
1984                 MLX5_TXQ_INLINE,
1985                 MLX5_TXQ_INLINE_MIN,
1986                 MLX5_TXQ_INLINE_MAX,
1987                 MLX5_TXQ_INLINE_MPW,
1988                 MLX5_TXQS_MIN_INLINE,
1989                 MLX5_TXQS_MAX_VEC,
1990                 MLX5_TXQ_MPW_EN,
1991                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1992                 MLX5_TXQ_MAX_INLINE_LEN,
1993                 MLX5_TX_DB_NC,
1994                 MLX5_TX_PP,
1995                 MLX5_TX_SKEW,
1996                 MLX5_TX_VEC_EN,
1997                 MLX5_RX_VEC_EN,
1998                 MLX5_L3_VXLAN_EN,
1999                 MLX5_VF_NL_EN,
2000                 MLX5_DV_ESW_EN,
2001                 MLX5_DV_FLOW_EN,
2002                 MLX5_DV_XMETA_EN,
2003                 MLX5_LACP_BY_USER,
2004                 MLX5_MR_EXT_MEMSEG_EN,
2005                 MLX5_REPRESENTOR,
2006                 MLX5_MAX_DUMP_FILES_NUM,
2007                 MLX5_LRO_TIMEOUT_USEC,
2008                 RTE_DEVARGS_KEY_CLASS,
2009                 MLX5_HP_BUF_SIZE,
2010                 MLX5_RECLAIM_MEM,
2011                 MLX5_SYS_MEM_EN,
2012                 MLX5_DECAP_EN,
2013                 MLX5_ALLOW_DUPLICATE_PATTERN,
2014                 NULL,
2015         };
2016         struct rte_kvargs *kvlist;
2017         int ret = 0;
2018         int i;
2019
2020         if (devargs == NULL)
2021                 return 0;
2022         /* Following UGLY cast is done to pass checkpatch. */
2023         kvlist = rte_kvargs_parse(devargs->args, params);
2024         if (kvlist == NULL) {
2025                 rte_errno = EINVAL;
2026                 return -rte_errno;
2027         }
2028         /* Process parameters. */
2029         for (i = 0; (params[i] != NULL); ++i) {
2030                 if (rte_kvargs_count(kvlist, params[i])) {
2031                         ret = rte_kvargs_process(kvlist, params[i],
2032                                                  mlx5_args_check, config);
2033                         if (ret) {
2034                                 rte_errno = EINVAL;
2035                                 rte_kvargs_free(kvlist);
2036                                 return -rte_errno;
2037                         }
2038                 }
2039         }
2040         rte_kvargs_free(kvlist);
2041         return 0;
2042 }
2043
2044 /**
2045  * Configures the minimal amount of data to inline into WQE
2046  * while sending packets.
2047  *
2048  * - the txq_inline_min has the maximal priority, if this
2049  *   key is specified in devargs
2050  * - if DevX is enabled the inline mode is queried from the
2051  *   device (HCA attributes and NIC vport context if needed).
2052  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2053  *   and none (0 bytes) for other NICs
2054  *
2055  * @param spawn
2056  *   Verbs device parameters (name, port, switch_info) to spawn.
2057  * @param config
2058  *   Device configuration parameters.
2059  */
2060 void
2061 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2062                     struct mlx5_dev_config *config)
2063 {
2064         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2065                 /* Application defines size of inlined data explicitly. */
2066                 switch (spawn->pci_dev->id.device_id) {
2067                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2068                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2069                         if (config->txq_inline_min <
2070                                        (int)MLX5_INLINE_HSIZE_L2) {
2071                                 DRV_LOG(DEBUG,
2072                                         "txq_inline_mix aligned to minimal"
2073                                         " ConnectX-4 required value %d",
2074                                         (int)MLX5_INLINE_HSIZE_L2);
2075                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2076                         }
2077                         break;
2078                 }
2079                 goto exit;
2080         }
2081         if (config->hca_attr.eth_net_offloads) {
2082                 /* We have DevX enabled, inline mode queried successfully. */
2083                 switch (config->hca_attr.wqe_inline_mode) {
2084                 case MLX5_CAP_INLINE_MODE_L2:
2085                         /* outer L2 header must be inlined. */
2086                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2087                         goto exit;
2088                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2089                         /* No inline data are required by NIC. */
2090                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2091                         config->hw_vlan_insert =
2092                                 config->hca_attr.wqe_vlan_insert;
2093                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2094                         goto exit;
2095                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2096                         /* inline mode is defined by NIC vport context. */
2097                         if (!config->hca_attr.eth_virt)
2098                                 break;
2099                         switch (config->hca_attr.vport_inline_mode) {
2100                         case MLX5_INLINE_MODE_NONE:
2101                                 config->txq_inline_min =
2102                                         MLX5_INLINE_HSIZE_NONE;
2103                                 goto exit;
2104                         case MLX5_INLINE_MODE_L2:
2105                                 config->txq_inline_min =
2106                                         MLX5_INLINE_HSIZE_L2;
2107                                 goto exit;
2108                         case MLX5_INLINE_MODE_IP:
2109                                 config->txq_inline_min =
2110                                         MLX5_INLINE_HSIZE_L3;
2111                                 goto exit;
2112                         case MLX5_INLINE_MODE_TCP_UDP:
2113                                 config->txq_inline_min =
2114                                         MLX5_INLINE_HSIZE_L4;
2115                                 goto exit;
2116                         case MLX5_INLINE_MODE_INNER_L2:
2117                                 config->txq_inline_min =
2118                                         MLX5_INLINE_HSIZE_INNER_L2;
2119                                 goto exit;
2120                         case MLX5_INLINE_MODE_INNER_IP:
2121                                 config->txq_inline_min =
2122                                         MLX5_INLINE_HSIZE_INNER_L3;
2123                                 goto exit;
2124                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2125                                 config->txq_inline_min =
2126                                         MLX5_INLINE_HSIZE_INNER_L4;
2127                                 goto exit;
2128                         }
2129                 }
2130         }
2131         /*
2132          * We get here if we are unable to deduce
2133          * inline data size with DevX. Try PCI ID
2134          * to determine old NICs.
2135          */
2136         switch (spawn->pci_dev->id.device_id) {
2137         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2138         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2139         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2140         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2141                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2142                 config->hw_vlan_insert = 0;
2143                 break;
2144         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2145         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2146         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2147         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2148                 /*
2149                  * These NICs support VLAN insertion from WQE and
2150                  * report the wqe_vlan_insert flag. But there is the bug
2151                  * and PFC control may be broken, so disable feature.
2152                  */
2153                 config->hw_vlan_insert = 0;
2154                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2155                 break;
2156         default:
2157                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2158                 break;
2159         }
2160 exit:
2161         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2162 }
2163
2164 /**
2165  * Configures the metadata mask fields in the shared context.
2166  *
2167  * @param [in] dev
2168  *   Pointer to Ethernet device.
2169  */
2170 void
2171 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2172 {
2173         struct mlx5_priv *priv = dev->data->dev_private;
2174         struct mlx5_dev_ctx_shared *sh = priv->sh;
2175         uint32_t meta, mark, reg_c0;
2176
2177         reg_c0 = ~priv->vport_meta_mask;
2178         switch (priv->config.dv_xmeta_en) {
2179         case MLX5_XMETA_MODE_LEGACY:
2180                 meta = UINT32_MAX;
2181                 mark = MLX5_FLOW_MARK_MASK;
2182                 break;
2183         case MLX5_XMETA_MODE_META16:
2184                 meta = reg_c0 >> rte_bsf32(reg_c0);
2185                 mark = MLX5_FLOW_MARK_MASK;
2186                 break;
2187         case MLX5_XMETA_MODE_META32:
2188                 meta = UINT32_MAX;
2189                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2190                 break;
2191         default:
2192                 meta = 0;
2193                 mark = 0;
2194                 MLX5_ASSERT(false);
2195                 break;
2196         }
2197         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2198                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2199                                  sh->dv_mark_mask, mark);
2200         else
2201                 sh->dv_mark_mask = mark;
2202         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2203                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2204                                  sh->dv_meta_mask, meta);
2205         else
2206                 sh->dv_meta_mask = meta;
2207         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2208                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2209                                  sh->dv_meta_mask, reg_c0);
2210         else
2211                 sh->dv_regc0_mask = reg_c0;
2212         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2213         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2214         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2215         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2216 }
2217
2218 int
2219 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2220 {
2221         static const char *const dynf_names[] = {
2222                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2223                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2224                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2225         };
2226         unsigned int i;
2227
2228         if (n < RTE_DIM(dynf_names))
2229                 return -ENOMEM;
2230         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2231                 if (names[i] == NULL)
2232                         return -EINVAL;
2233                 strcpy(names[i], dynf_names[i]);
2234         }
2235         return RTE_DIM(dynf_names);
2236 }
2237
2238 /**
2239  * Comparison callback to sort device data.
2240  *
2241  * This is meant to be used with qsort().
2242  *
2243  * @param a[in]
2244  *   Pointer to pointer to first data object.
2245  * @param b[in]
2246  *   Pointer to pointer to second data object.
2247  *
2248  * @return
2249  *   0 if both objects are equal, less than 0 if the first argument is less
2250  *   than the second, greater than 0 otherwise.
2251  */
2252 int
2253 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2254                               struct mlx5_dev_config *config)
2255 {
2256         struct mlx5_dev_ctx_shared *sh = priv->sh;
2257         struct mlx5_dev_config *sh_conf = NULL;
2258         uint16_t port_id;
2259
2260         MLX5_ASSERT(sh);
2261         /* Nothing to compare for the single/first device. */
2262         if (sh->refcnt == 1)
2263                 return 0;
2264         /* Find the device with shared context. */
2265         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2266                 struct mlx5_priv *opriv =
2267                         rte_eth_devices[port_id].data->dev_private;
2268
2269                 if (opriv && opriv != priv && opriv->sh == sh) {
2270                         sh_conf = &opriv->config;
2271                         break;
2272                 }
2273         }
2274         if (!sh_conf)
2275                 return 0;
2276         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2277                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2278                              " for shared %s context", sh->ibdev_name);
2279                 rte_errno = EINVAL;
2280                 return rte_errno;
2281         }
2282         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2283                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2284                              " for shared %s context", sh->ibdev_name);
2285                 rte_errno = EINVAL;
2286                 return rte_errno;
2287         }
2288         return 0;
2289 }
2290
2291 /**
2292  * Look for the ethernet device belonging to mlx5 driver.
2293  *
2294  * @param[in] port_id
2295  *   port_id to start looking for device.
2296  * @param[in] pci_dev
2297  *   Pointer to the hint PCI device. When device is being probed
2298  *   the its siblings (master and preceding representors might
2299  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2300  *   is not completed yet, for this case match on hint PCI
2301  *   device may be used to detect sibling device.
2302  *
2303  * @return
2304  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2305  */
2306 uint16_t
2307 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2308 {
2309         while (port_id < RTE_MAX_ETHPORTS) {
2310                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2311
2312                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2313                     dev->device &&
2314                     (dev->device == &pci_dev->device ||
2315                      (dev->device->driver &&
2316                      dev->device->driver->name &&
2317                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2318                         break;
2319                 port_id++;
2320         }
2321         if (port_id >= RTE_MAX_ETHPORTS)
2322                 return RTE_MAX_ETHPORTS;
2323         return port_id;
2324 }
2325
2326 /**
2327  * DPDK callback to remove a PCI device.
2328  *
2329  * This function removes all Ethernet devices belong to a given PCI device.
2330  *
2331  * @param[in] pci_dev
2332  *   Pointer to the PCI device.
2333  *
2334  * @return
2335  *   0 on success, the function cannot fail.
2336  */
2337 static int
2338 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2339 {
2340         uint16_t port_id;
2341         int ret = 0;
2342
2343         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2344                 /*
2345                  * mlx5_dev_close() is not registered to secondary process,
2346                  * call the close function explicitly for secondary process.
2347                  */
2348                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2349                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2350                 else
2351                         ret |= rte_eth_dev_close(port_id);
2352         }
2353         return ret == 0 ? 0 : -EIO;
2354 }
2355
2356 static const struct rte_pci_id mlx5_pci_id_map[] = {
2357         {
2358                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2359                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2360         },
2361         {
2362                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2363                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2364         },
2365         {
2366                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2367                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2368         },
2369         {
2370                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2371                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2372         },
2373         {
2374                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2375                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2376         },
2377         {
2378                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2379                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2380         },
2381         {
2382                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2383                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2384         },
2385         {
2386                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2387                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2388         },
2389         {
2390                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2391                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2392         },
2393         {
2394                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2395                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2396         },
2397         {
2398                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2399                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2400         },
2401         {
2402                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2403                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2404         },
2405         {
2406                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2407                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2408         },
2409         {
2410                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2411                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2412         },
2413         {
2414                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2415                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2416         },
2417         {
2418                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2419                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2420         },
2421         {
2422                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2423                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2424         },
2425         {
2426                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2427                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2428         },
2429         {
2430                 .vendor_id = 0
2431         }
2432 };
2433
2434 static struct mlx5_pci_driver mlx5_driver = {
2435         .driver_class = MLX5_CLASS_NET,
2436         .pci_driver = {
2437                 .driver = {
2438                         .name = MLX5_PCI_DRIVER_NAME,
2439                 },
2440                 .id_table = mlx5_pci_id_map,
2441                 .probe = mlx5_os_pci_probe,
2442                 .remove = mlx5_pci_remove,
2443                 .dma_map = mlx5_dma_map,
2444                 .dma_unmap = mlx5_dma_unmap,
2445                 .drv_flags = PCI_DRV_FLAGS,
2446         },
2447 };
2448
2449 /* Initialize driver log type. */
2450 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2451
2452 /**
2453  * Driver initialization routine.
2454  */
2455 RTE_INIT(rte_mlx5_pmd_init)
2456 {
2457         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2458         mlx5_common_init();
2459         /* Build the static tables for Verbs conversion. */
2460         mlx5_set_ptype_table();
2461         mlx5_set_cksum_table();
2462         mlx5_set_swp_types_table();
2463         if (mlx5_glue)
2464                 mlx5_pci_driver_register(&mlx5_driver);
2465 }
2466
2467 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2468 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2469 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");