1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
14 #include <linux/rtnetlink.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
26 #include <rte_malloc.h>
27 #include <rte_ethdev_driver.h>
28 #include <rte_ethdev_pci.h>
30 #include <rte_bus_pci.h>
31 #include <rte_common.h>
32 #include <rte_kvargs.h>
33 #include <rte_rwlock.h>
34 #include <rte_spinlock.h>
35 #include <rte_string_fns.h>
36 #include <rte_alarm.h>
38 #include <mlx5_glue.h>
39 #include <mlx5_devx_cmds.h>
40 #include <mlx5_common.h>
42 #include "mlx5_defs.h"
44 #include "mlx5_utils.h"
45 #include "mlx5_rxtx.h"
46 #include "mlx5_autoconf.h"
48 #include "mlx5_flow.h"
49 #include "rte_pmd_mlx5.h"
51 /* Device parameter to enable RX completion queue compression. */
52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
54 /* Device parameter to enable RX completion entry padding to 128B. */
55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
57 /* Device parameter to enable padding Rx packet to cacheline size. */
58 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
60 /* Device parameter to enable Multi-Packet Rx queue. */
61 #define MLX5_RX_MPRQ_EN "mprq_en"
63 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
64 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
66 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
67 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
69 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
70 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
72 /* Device parameter to configure inline send. Deprecated, ignored.*/
73 #define MLX5_TXQ_INLINE "txq_inline"
75 /* Device parameter to limit packet size to inline with ordinary SEND. */
76 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
78 /* Device parameter to configure minimal data size to inline. */
79 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
81 /* Device parameter to limit packet size to inline with Enhanced MPW. */
82 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
85 * Device parameter to configure the number of TX queues threshold for
86 * enabling inline send.
88 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
91 * Device parameter to configure the number of TX queues threshold for
92 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
94 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
96 /* Device parameter to enable multi-packet send WQEs. */
97 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
100 * Device parameter to force doorbell register mapping
101 * to non-cahed region eliminating the extra write memory barrier.
103 #define MLX5_TX_DB_NC "tx_db_nc"
106 * Device parameter to include 2 dsegs in the title WQEBB.
107 * Deprecated, ignored.
109 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
112 * Device parameter to limit the size of inlining packet.
113 * Deprecated, ignored.
115 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
118 * Device parameter to enable hardware Tx vector.
119 * Deprecated, ignored (no vectorized Tx routines anymore).
121 #define MLX5_TX_VEC_EN "tx_vec_en"
123 /* Device parameter to enable hardware Rx vector. */
124 #define MLX5_RX_VEC_EN "rx_vec_en"
126 /* Allow L3 VXLAN flow creation. */
127 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
129 /* Activate DV E-Switch flow steering. */
130 #define MLX5_DV_ESW_EN "dv_esw_en"
132 /* Activate DV flow steering. */
133 #define MLX5_DV_FLOW_EN "dv_flow_en"
135 /* Enable extensive flow metadata support. */
136 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
138 /* Activate Netlink support in VF mode. */
139 #define MLX5_VF_NL_EN "vf_nl_en"
141 /* Enable extending memsegs when creating a MR. */
142 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
144 /* Select port representors to instantiate. */
145 #define MLX5_REPRESENTOR "representor"
147 /* Device parameter to configure the maximum number of dump files per queue. */
148 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
150 /* Configure timeout of LRO session (in microseconds). */
151 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
153 #ifndef HAVE_IBV_MLX5_MOD_MPW
154 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
155 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
158 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
159 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
162 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
164 /* Shared memory between primary and secondary processes. */
165 struct mlx5_shared_data *mlx5_shared_data;
167 /* Spinlock for mlx5_shared_data allocation. */
168 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
170 /* Process local data for secondary processes. */
171 static struct mlx5_local_data mlx5_local_data;
173 /** Driver-specific log messages type. */
176 /** Data associated with devices to spawn. */
177 struct mlx5_dev_spawn_data {
178 uint32_t ifindex; /**< Network interface index. */
179 uint32_t max_port; /**< IB device maximal port index. */
180 uint32_t ibv_port; /**< IB device physical port index. */
181 int pf_bond; /**< bonding device PF index. < 0 - no bonding */
182 struct mlx5_switch_info info; /**< Switch information. */
183 struct ibv_device *ibv_dev; /**< Associated IB device. */
184 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
185 struct rte_pci_device *pci_dev; /**< Backend PCI device. */
188 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
189 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
191 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
192 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
194 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
195 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192
198 * Allocate ID pool structure.
201 * The maximum id can be allocated from the pool.
204 * Pointer to pool object, NULL value otherwise.
206 struct mlx5_flow_id_pool *
207 mlx5_flow_id_pool_alloc(uint32_t max_id)
209 struct mlx5_flow_id_pool *pool;
212 pool = rte_zmalloc("id pool allocation", sizeof(*pool),
213 RTE_CACHE_LINE_SIZE);
215 DRV_LOG(ERR, "can't allocate id pool");
219 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
220 RTE_CACHE_LINE_SIZE);
222 DRV_LOG(ERR, "can't allocate mem for id pool");
226 pool->free_arr = mem;
227 pool->curr = pool->free_arr;
228 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
229 pool->base_index = 0;
230 pool->max_id = max_id;
238 * Release ID pool structure.
241 * Pointer to flow id pool object to free.
244 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
246 rte_free(pool->free_arr);
254 * Pointer to flow id pool.
259 * 0 on success, error value otherwise.
262 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
264 if (pool->curr == pool->free_arr) {
265 if (pool->base_index == pool->max_id) {
267 DRV_LOG(ERR, "no free id");
270 *id = ++pool->base_index;
273 *id = *(--pool->curr);
281 * Pointer to flow id pool.
286 * 0 on success, error value otherwise.
289 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
295 if (pool->curr == pool->last) {
296 size = pool->curr - pool->free_arr;
297 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
298 MLX5_ASSERT(size2 > size);
299 mem = rte_malloc("", size2 * sizeof(uint32_t), 0);
301 DRV_LOG(ERR, "can't allocate mem for id pool");
305 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
306 rte_free(pool->free_arr);
307 pool->free_arr = mem;
308 pool->curr = pool->free_arr + size;
309 pool->last = pool->free_arr + size2;
317 * Initialize the counters management structure.
320 * Pointer to mlx5_ibv_shared object to free
323 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh)
327 TAILQ_INIT(&sh->cmng.flow_counters);
328 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i)
329 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
333 * Destroy all the resources allocated for a counter memory management.
336 * Pointer to the memory management structure.
339 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
341 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
343 LIST_REMOVE(mng, next);
344 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
345 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
350 * Close and release all the resources of the counters management.
353 * Pointer to mlx5_ibv_shared object to free.
356 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh)
358 struct mlx5_counter_stats_mem_mng *mng;
365 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
366 if (rte_errno != EINPROGRESS)
370 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) {
371 struct mlx5_flow_counter_pool *pool;
372 uint32_t batch = !!(i % 2);
374 if (!sh->cmng.ccont[i].pools)
376 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
381 (mlx5_devx_cmd_destroy(pool->min_dcs));
383 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
384 if (pool->counters_raw[j].action)
386 (mlx5_glue->destroy_flow_action
387 (pool->counters_raw[j].action));
388 if (!batch && pool->counters_raw[j].dcs)
389 claim_zero(mlx5_devx_cmd_destroy
390 (pool->counters_raw[j].dcs));
392 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool,
395 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
397 rte_free(sh->cmng.ccont[i].pools);
399 mng = LIST_FIRST(&sh->cmng.mem_mngs);
401 mlx5_flow_destroy_counter_stat_mem_mng(mng);
402 mng = LIST_FIRST(&sh->cmng.mem_mngs);
404 memset(&sh->cmng, 0, sizeof(sh->cmng));
408 * Extract pdn of PD object using DV API.
411 * Pointer to the verbs PD object.
413 * Pointer to the PD object number variable.
416 * 0 on success, error value otherwise.
418 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
420 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused)
422 struct mlx5dv_obj obj;
423 struct mlx5dv_pd pd_info;
427 obj.pd.out = &pd_info;
428 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
430 DRV_LOG(DEBUG, "Fail to get PD object info");
436 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
439 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config)
444 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
445 /* Get environment variable to store. */
446 env = getenv(MLX5_SHUT_UP_BF);
447 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET;
448 if (config->dbnc == MLX5_ARG_UNSET)
449 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1);
451 setenv(MLX5_SHUT_UP_BF,
452 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1);
457 mlx5_restore_doorbell_mapping_env(int value)
459 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
460 /* Restore the original environment variable state. */
461 if (value == MLX5_ARG_UNSET)
462 unsetenv(MLX5_SHUT_UP_BF);
464 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1);
468 * Allocate shared IB device context. If there is multiport device the
469 * master and representors will share this context, if there is single
470 * port dedicated IB device, the context will be used by only given
471 * port due to unification.
473 * Routine first searches the context for the specified IB device name,
474 * if found the shared context assumed and reference counter is incremented.
475 * If no context found the new one is created and initialized with specified
476 * IB device context and parameters.
479 * Pointer to the IB device attributes (name, port, etc).
481 * Pointer to device configuration structure.
484 * Pointer to mlx5_ibv_shared object on success,
485 * otherwise NULL and rte_errno is set.
487 static struct mlx5_ibv_shared *
488 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn,
489 const struct mlx5_dev_config *config)
491 struct mlx5_ibv_shared *sh;
495 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
496 struct mlx5_devx_tis_attr tis_attr = { 0 };
500 /* Secondary process should not create the shared context. */
501 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
502 pthread_mutex_lock(&mlx5_ibv_list_mutex);
503 /* Search for IB context by device name. */
504 LIST_FOREACH(sh, &mlx5_ibv_list, next) {
505 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
510 /* No device found, we have to create new shared context. */
511 MLX5_ASSERT(spawn->max_port);
512 sh = rte_zmalloc("ethdev shared ib context",
513 sizeof(struct mlx5_ibv_shared) +
515 sizeof(struct mlx5_ibv_shared_port),
516 RTE_CACHE_LINE_SIZE);
518 DRV_LOG(ERR, "shared context allocation failure");
523 * Configure environment variable "MLX5_BF_SHUT_UP"
524 * before the device creation. The rdma_core library
525 * checks the variable at device creation and
526 * stores the result internally.
528 dbmap_env = mlx5_config_doorbell_mapping_env(config);
529 /* Try to open IB device with DV first, then usual Verbs. */
531 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
534 DRV_LOG(DEBUG, "DevX is supported");
535 /* The device is created, no need for environment. */
536 mlx5_restore_doorbell_mapping_env(dbmap_env);
538 /* The environment variable is still configured. */
539 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
540 err = errno ? errno : ENODEV;
542 * The environment variable is not needed anymore,
543 * all device creation attempts are completed.
545 mlx5_restore_doorbell_mapping_env(dbmap_env);
548 DRV_LOG(DEBUG, "DevX is NOT supported");
550 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
552 DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
556 sh->max_port = spawn->max_port;
557 strncpy(sh->ibdev_name, sh->ctx->device->name,
558 sizeof(sh->ibdev_name));
559 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
560 sizeof(sh->ibdev_path));
561 pthread_mutex_init(&sh->intr_mutex, NULL);
563 * Setting port_id to max unallowed value means
564 * there is no interrupt subhandler installed for
565 * the given port index i.
567 for (i = 0; i < sh->max_port; i++) {
568 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
569 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
571 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
572 if (sh->pd == NULL) {
573 DRV_LOG(ERR, "PD allocation failure");
577 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
579 err = mlx5_get_pdn(sh->pd, &sh->pdn);
581 DRV_LOG(ERR, "Fail to extract pdn from PD");
584 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
586 DRV_LOG(ERR, "TD allocation failure");
590 tis_attr.transport_domain = sh->td->id;
591 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
593 DRV_LOG(ERR, "TIS allocation failure");
598 sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX);
599 if (!sh->flow_id_pool) {
600 DRV_LOG(ERR, "can't create flow id pool");
604 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
606 * Once the device is added to the list of memory event
607 * callback, its global MR cache table cannot be expanded
608 * on the fly because of deadlock. If it overflows, lookup
609 * should be done by searching MR list linearly, which is slow.
611 * At this point the device is not added to the memory
612 * event list yet, context is just being created.
614 err = mlx5_mr_btree_init(&sh->mr.cache,
615 MLX5_MR_BTREE_CACHE_N * 2,
616 spawn->pci_dev->device.numa_node);
621 mlx5_flow_counters_mng_init(sh);
622 /* Add device to memory callback list. */
623 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
624 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
626 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
627 /* Add context to the global device list. */
628 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
630 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
633 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
636 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
638 claim_zero(mlx5_devx_cmd_destroy(sh->td));
640 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
642 claim_zero(mlx5_glue->close_device(sh->ctx));
643 if (sh->flow_id_pool)
644 mlx5_flow_id_pool_release(sh->flow_id_pool);
646 MLX5_ASSERT(err > 0);
652 * Free shared IB device context. Decrement counter and if zero free
653 * all allocated resources and close handles.
656 * Pointer to mlx5_ibv_shared object to free
659 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
661 pthread_mutex_lock(&mlx5_ibv_list_mutex);
662 #ifdef RTE_LIBRTE_MLX5_DEBUG
663 /* Check the object presence in the list. */
664 struct mlx5_ibv_shared *lctx;
666 LIST_FOREACH(lctx, &mlx5_ibv_list, next)
671 DRV_LOG(ERR, "Freeing non-existing shared IB context");
676 MLX5_ASSERT(sh->refcnt);
677 /* Secondary process should not free the shared context. */
678 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
681 /* Remove from memory callback device list. */
682 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
683 LIST_REMOVE(sh, mem_event_cb);
684 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
685 /* Release created Memory Regions. */
687 /* Remove context from the global device list. */
688 LIST_REMOVE(sh, next);
690 * Ensure there is no async event handler installed.
691 * Only primary process handles async device events.
693 mlx5_flow_counters_mng_close(sh);
694 MLX5_ASSERT(!sh->intr_cnt);
696 mlx5_intr_callback_unregister
697 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
698 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT
699 if (sh->devx_intr_cnt) {
700 if (sh->intr_handle_devx.fd)
701 rte_intr_callback_unregister(&sh->intr_handle_devx,
702 mlx5_dev_interrupt_handler_devx, sh);
704 mlx5dv_devx_destroy_cmd_comp(sh->devx_comp);
707 pthread_mutex_destroy(&sh->intr_mutex);
709 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
711 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
713 claim_zero(mlx5_devx_cmd_destroy(sh->td));
715 claim_zero(mlx5_glue->close_device(sh->ctx));
716 if (sh->flow_id_pool)
717 mlx5_flow_id_pool_release(sh->flow_id_pool);
720 pthread_mutex_unlock(&mlx5_ibv_list_mutex);
724 * Destroy table hash list and all the root entries per domain.
727 * Pointer to the private device data structure.
730 mlx5_free_table_hash_list(struct mlx5_priv *priv)
732 struct mlx5_ibv_shared *sh = priv->sh;
733 struct mlx5_flow_tbl_data_entry *tbl_data;
734 union mlx5_flow_tbl_key table_key = {
742 struct mlx5_hlist_entry *pos;
746 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
748 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
750 MLX5_ASSERT(tbl_data);
751 mlx5_hlist_remove(sh->flow_tbls, pos);
754 table_key.direction = 1;
755 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
757 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
759 MLX5_ASSERT(tbl_data);
760 mlx5_hlist_remove(sh->flow_tbls, pos);
763 table_key.direction = 0;
764 table_key.domain = 1;
765 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
767 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
769 MLX5_ASSERT(tbl_data);
770 mlx5_hlist_remove(sh->flow_tbls, pos);
773 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
777 * Initialize flow table hash list and create the root tables entry
781 * Pointer to the private device data structure.
784 * Zero on success, positive error code otherwise.
787 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
789 struct mlx5_ibv_shared *sh = priv->sh;
790 char s[MLX5_HLIST_NAMESIZE];
794 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
795 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
796 if (!sh->flow_tbls) {
797 DRV_LOG(ERR, "flow tables with hash creation failed.\n");
801 #ifndef HAVE_MLX5DV_DR
803 * In case we have not DR support, the zero tables should be created
804 * because DV expect to see them even if they cannot be created by
807 union mlx5_flow_tbl_key table_key = {
815 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL,
816 sizeof(*tbl_data), 0);
822 tbl_data->entry.key = table_key.v64;
823 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
826 rte_atomic32_init(&tbl_data->tbl.refcnt);
827 rte_atomic32_inc(&tbl_data->tbl.refcnt);
828 table_key.direction = 1;
829 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
834 tbl_data->entry.key = table_key.v64;
835 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
838 rte_atomic32_init(&tbl_data->tbl.refcnt);
839 rte_atomic32_inc(&tbl_data->tbl.refcnt);
840 table_key.direction = 0;
841 table_key.domain = 1;
842 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
847 tbl_data->entry.key = table_key.v64;
848 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
851 rte_atomic32_init(&tbl_data->tbl.refcnt);
852 rte_atomic32_inc(&tbl_data->tbl.refcnt);
855 mlx5_free_table_hash_list(priv);
856 #endif /* HAVE_MLX5DV_DR */
861 * Initialize DR related data within private structure.
862 * Routine checks the reference counter and does actual
863 * resources creation/initialization only if counter is zero.
866 * Pointer to the private device data structure.
869 * Zero on success, positive error code otherwise.
872 mlx5_alloc_shared_dr(struct mlx5_priv *priv)
874 struct mlx5_ibv_shared *sh = priv->sh;
875 char s[MLX5_HLIST_NAMESIZE];
879 err = mlx5_alloc_table_hash_list(priv);
881 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n",
882 (void *)sh->flow_tbls);
885 /* Create tags hash list table. */
886 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name);
887 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE);
888 if (!sh->tag_table) {
889 DRV_LOG(ERR, "tags with hash creation failed.\n");
893 #ifdef HAVE_MLX5DV_DR
897 /* Shared DV/DR structures is already initialized. */
902 /* Reference counter is zero, we should initialize structures. */
903 domain = mlx5_glue->dr_create_domain(sh->ctx,
904 MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
906 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
910 sh->rx_domain = domain;
911 domain = mlx5_glue->dr_create_domain(sh->ctx,
912 MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
914 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
918 pthread_mutex_init(&sh->dv_mutex, NULL);
919 sh->tx_domain = domain;
920 #ifdef HAVE_MLX5DV_DR_ESWITCH
921 if (priv->config.dv_esw_en) {
922 domain = mlx5_glue->dr_create_domain
923 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
925 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
929 sh->fdb_domain = domain;
930 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
933 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan();
934 #endif /* HAVE_MLX5DV_DR */
939 /* Rollback the created objects. */
941 mlx5_glue->dr_destroy_domain(sh->rx_domain);
942 sh->rx_domain = NULL;
945 mlx5_glue->dr_destroy_domain(sh->tx_domain);
946 sh->tx_domain = NULL;
948 if (sh->fdb_domain) {
949 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
950 sh->fdb_domain = NULL;
952 if (sh->esw_drop_action) {
953 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
954 sh->esw_drop_action = NULL;
956 if (sh->pop_vlan_action) {
957 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
958 sh->pop_vlan_action = NULL;
961 /* tags should be destroyed with flow before. */
962 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
963 sh->tag_table = NULL;
965 mlx5_free_table_hash_list(priv);
970 * Destroy DR related data within private structure.
973 * Pointer to the private device data structure.
976 mlx5_free_shared_dr(struct mlx5_priv *priv)
978 struct mlx5_ibv_shared *sh;
980 if (!priv->dr_shared)
985 #ifdef HAVE_MLX5DV_DR
986 MLX5_ASSERT(sh->dv_refcnt);
987 if (sh->dv_refcnt && --sh->dv_refcnt)
990 mlx5_glue->dr_destroy_domain(sh->rx_domain);
991 sh->rx_domain = NULL;
994 mlx5_glue->dr_destroy_domain(sh->tx_domain);
995 sh->tx_domain = NULL;
997 #ifdef HAVE_MLX5DV_DR_ESWITCH
998 if (sh->fdb_domain) {
999 mlx5_glue->dr_destroy_domain(sh->fdb_domain);
1000 sh->fdb_domain = NULL;
1002 if (sh->esw_drop_action) {
1003 mlx5_glue->destroy_flow_action(sh->esw_drop_action);
1004 sh->esw_drop_action = NULL;
1007 if (sh->pop_vlan_action) {
1008 mlx5_glue->destroy_flow_action(sh->pop_vlan_action);
1009 sh->pop_vlan_action = NULL;
1011 pthread_mutex_destroy(&sh->dv_mutex);
1012 #endif /* HAVE_MLX5DV_DR */
1013 if (sh->tag_table) {
1014 /* tags should be destroyed with flow before. */
1015 mlx5_hlist_destroy(sh->tag_table, NULL, NULL);
1016 sh->tag_table = NULL;
1018 mlx5_free_table_hash_list(priv);
1022 * Initialize shared data between primary and secondary process.
1024 * A memzone is reserved by primary process and secondary processes attach to
1028 * 0 on success, a negative errno value otherwise and rte_errno is set.
1031 mlx5_init_shared_data(void)
1033 const struct rte_memzone *mz;
1036 rte_spinlock_lock(&mlx5_shared_data_lock);
1037 if (mlx5_shared_data == NULL) {
1038 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
1039 /* Allocate shared memory. */
1040 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
1041 sizeof(*mlx5_shared_data),
1045 "Cannot allocate mlx5 shared data");
1049 mlx5_shared_data = mz->addr;
1050 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
1051 rte_spinlock_init(&mlx5_shared_data->lock);
1053 /* Lookup allocated shared memory. */
1054 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
1057 "Cannot attach mlx5 shared data");
1061 mlx5_shared_data = mz->addr;
1062 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
1066 rte_spinlock_unlock(&mlx5_shared_data_lock);
1071 * Retrieve integer value from environment variable.
1074 * Environment variable name.
1077 * Integer value, 0 if the variable is not set.
1080 mlx5_getenv_int(const char *name)
1082 const char *val = getenv(name);
1090 * Verbs callback to allocate a memory. This function should allocate the space
1091 * according to the size provided residing inside a huge page.
1092 * Please note that all allocation must respect the alignment from libmlx5
1093 * (i.e. currently sysconf(_SC_PAGESIZE)).
1096 * The size in bytes of the memory to allocate.
1098 * A pointer to the callback data.
1101 * Allocated buffer, NULL otherwise and rte_errno is set.
1104 mlx5_alloc_verbs_buf(size_t size, void *data)
1106 struct mlx5_priv *priv = data;
1108 size_t alignment = sysconf(_SC_PAGESIZE);
1109 unsigned int socket = SOCKET_ID_ANY;
1111 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
1112 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1114 socket = ctrl->socket;
1115 } else if (priv->verbs_alloc_ctx.type ==
1116 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
1117 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
1119 socket = ctrl->socket;
1121 MLX5_ASSERT(data != NULL);
1122 ret = rte_malloc_socket(__func__, size, alignment, socket);
1129 * Verbs callback to free a memory.
1132 * A pointer to the memory to free.
1134 * A pointer to the callback data.
1137 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
1139 MLX5_ASSERT(data != NULL);
1144 * DPDK callback to add udp tunnel port
1147 * A pointer to eth_dev
1148 * @param[in] udp_tunnel
1149 * A pointer to udp tunnel
1152 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1155 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1156 struct rte_eth_udp_tunnel *udp_tunnel)
1158 MLX5_ASSERT(udp_tunnel != NULL);
1159 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1160 udp_tunnel->udp_port == 4789)
1162 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1163 udp_tunnel->udp_port == 4790)
1169 * Initialize process private data structure.
1172 * Pointer to Ethernet device structure.
1175 * 0 on success, a negative errno value otherwise and rte_errno is set.
1178 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1180 struct mlx5_priv *priv = dev->data->dev_private;
1181 struct mlx5_proc_priv *ppriv;
1185 * UAR register table follows the process private structure. BlueFlame
1186 * registers for Tx queues are stored in the table.
1189 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1190 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
1191 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1196 ppriv->uar_table_sz = ppriv_size;
1197 dev->process_private = ppriv;
1202 * Un-initialize process private data structure.
1205 * Pointer to Ethernet device structure.
1208 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1210 if (!dev->process_private)
1212 rte_free(dev->process_private);
1213 dev->process_private = NULL;
1217 * DPDK callback to close the device.
1219 * Destroy all queues and objects, free memory.
1222 * Pointer to Ethernet device structure.
1225 mlx5_dev_close(struct rte_eth_dev *dev)
1227 struct mlx5_priv *priv = dev->data->dev_private;
1231 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1233 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
1234 /* In case mlx5_dev_stop() has not been called. */
1235 mlx5_dev_interrupt_handler_uninstall(dev);
1236 mlx5_dev_interrupt_handler_devx_uninstall(dev);
1238 * If default mreg copy action is removed at the stop stage,
1239 * the search will return none and nothing will be done anymore.
1241 mlx5_flow_stop_default(dev);
1242 mlx5_traffic_disable(dev);
1244 * If all the flows are already flushed in the device stop stage,
1245 * then this will return directly without any action.
1247 mlx5_flow_list_flush(dev, &priv->flows, true);
1248 mlx5_flow_meter_flush(dev, NULL);
1249 /* Free the intermediate buffers for flow creation. */
1250 mlx5_flow_free_intermediate(dev);
1251 /* Prevent crashes when queues are still in use. */
1252 dev->rx_pkt_burst = removed_rx_burst;
1253 dev->tx_pkt_burst = removed_tx_burst;
1255 /* Disable datapath on secondary process. */
1256 mlx5_mp_req_stop_rxtx(dev);
1257 if (priv->rxqs != NULL) {
1258 /* XXX race condition if mlx5_rx_burst() is still running. */
1260 for (i = 0; (i != priv->rxqs_n); ++i)
1261 mlx5_rxq_release(dev, i);
1265 if (priv->txqs != NULL) {
1266 /* XXX race condition if mlx5_tx_burst() is still running. */
1268 for (i = 0; (i != priv->txqs_n); ++i)
1269 mlx5_txq_release(dev, i);
1273 mlx5_proc_priv_uninit(dev);
1274 if (priv->mreg_cp_tbl)
1275 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1276 mlx5_mprq_free_mp(dev);
1277 mlx5_free_shared_dr(priv);
1278 if (priv->rss_conf.rss_key != NULL)
1279 rte_free(priv->rss_conf.rss_key);
1280 if (priv->reta_idx != NULL)
1281 rte_free(priv->reta_idx);
1282 if (priv->config.vf)
1283 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1284 dev->data->mac_addrs,
1285 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1286 if (priv->nl_socket_route >= 0)
1287 close(priv->nl_socket_route);
1288 if (priv->nl_socket_rdma >= 0)
1289 close(priv->nl_socket_rdma);
1290 if (priv->vmwa_context)
1291 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1294 * Free the shared context in last turn, because the cleanup
1295 * routines above may use some shared fields, like
1296 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1297 * ifindex if Netlink fails.
1299 mlx5_free_shared_ibctx(priv->sh);
1302 ret = mlx5_hrxq_verify(dev);
1304 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1305 dev->data->port_id);
1306 ret = mlx5_ind_table_obj_verify(dev);
1308 DRV_LOG(WARNING, "port %u some indirection table still remain",
1309 dev->data->port_id);
1310 ret = mlx5_rxq_obj_verify(dev);
1312 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1313 dev->data->port_id);
1314 ret = mlx5_rxq_verify(dev);
1316 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1317 dev->data->port_id);
1318 ret = mlx5_txq_obj_verify(dev);
1320 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1321 dev->data->port_id);
1322 ret = mlx5_txq_verify(dev);
1324 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1325 dev->data->port_id);
1326 ret = mlx5_flow_verify(dev);
1328 DRV_LOG(WARNING, "port %u some flows still remain",
1329 dev->data->port_id);
1330 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1334 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1335 struct mlx5_priv *opriv =
1336 rte_eth_devices[port_id].data->dev_private;
1339 opriv->domain_id != priv->domain_id ||
1340 &rte_eth_devices[port_id] == dev)
1346 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1348 memset(priv, 0, sizeof(*priv));
1349 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1351 * Reset mac_addrs to NULL such that it is not freed as part of
1352 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1353 * it is freed when dev_private is freed.
1355 dev->data->mac_addrs = NULL;
1358 const struct eth_dev_ops mlx5_dev_ops = {
1359 .dev_configure = mlx5_dev_configure,
1360 .dev_start = mlx5_dev_start,
1361 .dev_stop = mlx5_dev_stop,
1362 .dev_set_link_down = mlx5_set_link_down,
1363 .dev_set_link_up = mlx5_set_link_up,
1364 .dev_close = mlx5_dev_close,
1365 .promiscuous_enable = mlx5_promiscuous_enable,
1366 .promiscuous_disable = mlx5_promiscuous_disable,
1367 .allmulticast_enable = mlx5_allmulticast_enable,
1368 .allmulticast_disable = mlx5_allmulticast_disable,
1369 .link_update = mlx5_link_update,
1370 .stats_get = mlx5_stats_get,
1371 .stats_reset = mlx5_stats_reset,
1372 .xstats_get = mlx5_xstats_get,
1373 .xstats_reset = mlx5_xstats_reset,
1374 .xstats_get_names = mlx5_xstats_get_names,
1375 .fw_version_get = mlx5_fw_version_get,
1376 .dev_infos_get = mlx5_dev_infos_get,
1377 .read_clock = mlx5_read_clock,
1378 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1379 .vlan_filter_set = mlx5_vlan_filter_set,
1380 .rx_queue_setup = mlx5_rx_queue_setup,
1381 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1382 .tx_queue_setup = mlx5_tx_queue_setup,
1383 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1384 .rx_queue_release = mlx5_rx_queue_release,
1385 .tx_queue_release = mlx5_tx_queue_release,
1386 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1387 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1388 .mac_addr_remove = mlx5_mac_addr_remove,
1389 .mac_addr_add = mlx5_mac_addr_add,
1390 .mac_addr_set = mlx5_mac_addr_set,
1391 .set_mc_addr_list = mlx5_set_mc_addr_list,
1392 .mtu_set = mlx5_dev_set_mtu,
1393 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1394 .vlan_offload_set = mlx5_vlan_offload_set,
1395 .reta_update = mlx5_dev_rss_reta_update,
1396 .reta_query = mlx5_dev_rss_reta_query,
1397 .rss_hash_update = mlx5_rss_hash_update,
1398 .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1399 .filter_ctrl = mlx5_dev_filter_ctrl,
1400 .rx_descriptor_status = mlx5_rx_descriptor_status,
1401 .tx_descriptor_status = mlx5_tx_descriptor_status,
1402 .rxq_info_get = mlx5_rxq_info_get,
1403 .txq_info_get = mlx5_txq_info_get,
1404 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1405 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1406 .rx_queue_count = mlx5_rx_queue_count,
1407 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1408 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1409 .is_removed = mlx5_is_removed,
1410 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add,
1411 .get_module_info = mlx5_get_module_info,
1412 .get_module_eeprom = mlx5_get_module_eeprom,
1413 .hairpin_cap_get = mlx5_hairpin_cap_get,
1414 .mtr_ops_get = mlx5_flow_meter_ops_get,
1417 /* Available operations from secondary process. */
1418 static const struct eth_dev_ops mlx5_dev_sec_ops = {
1419 .stats_get = mlx5_stats_get,
1420 .stats_reset = mlx5_stats_reset,
1421 .xstats_get = mlx5_xstats_get,
1422 .xstats_reset = mlx5_xstats_reset,
1423 .xstats_get_names = mlx5_xstats_get_names,
1424 .fw_version_get = mlx5_fw_version_get,
1425 .dev_infos_get = mlx5_dev_infos_get,
1426 .rx_descriptor_status = mlx5_rx_descriptor_status,
1427 .tx_descriptor_status = mlx5_tx_descriptor_status,
1428 .rxq_info_get = mlx5_rxq_info_get,
1429 .txq_info_get = mlx5_txq_info_get,
1430 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1431 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1432 .get_module_info = mlx5_get_module_info,
1433 .get_module_eeprom = mlx5_get_module_eeprom,
1436 /* Available operations in flow isolated mode. */
1437 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1438 .dev_configure = mlx5_dev_configure,
1439 .dev_start = mlx5_dev_start,
1440 .dev_stop = mlx5_dev_stop,
1441 .dev_set_link_down = mlx5_set_link_down,
1442 .dev_set_link_up = mlx5_set_link_up,
1443 .dev_close = mlx5_dev_close,
1444 .promiscuous_enable = mlx5_promiscuous_enable,
1445 .promiscuous_disable = mlx5_promiscuous_disable,
1446 .allmulticast_enable = mlx5_allmulticast_enable,
1447 .allmulticast_disable = mlx5_allmulticast_disable,
1448 .link_update = mlx5_link_update,
1449 .stats_get = mlx5_stats_get,
1450 .stats_reset = mlx5_stats_reset,
1451 .xstats_get = mlx5_xstats_get,
1452 .xstats_reset = mlx5_xstats_reset,
1453 .xstats_get_names = mlx5_xstats_get_names,
1454 .fw_version_get = mlx5_fw_version_get,
1455 .dev_infos_get = mlx5_dev_infos_get,
1456 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1457 .vlan_filter_set = mlx5_vlan_filter_set,
1458 .rx_queue_setup = mlx5_rx_queue_setup,
1459 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1460 .tx_queue_setup = mlx5_tx_queue_setup,
1461 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1462 .rx_queue_release = mlx5_rx_queue_release,
1463 .tx_queue_release = mlx5_tx_queue_release,
1464 .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1465 .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1466 .mac_addr_remove = mlx5_mac_addr_remove,
1467 .mac_addr_add = mlx5_mac_addr_add,
1468 .mac_addr_set = mlx5_mac_addr_set,
1469 .set_mc_addr_list = mlx5_set_mc_addr_list,
1470 .mtu_set = mlx5_dev_set_mtu,
1471 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1472 .vlan_offload_set = mlx5_vlan_offload_set,
1473 .filter_ctrl = mlx5_dev_filter_ctrl,
1474 .rx_descriptor_status = mlx5_rx_descriptor_status,
1475 .tx_descriptor_status = mlx5_tx_descriptor_status,
1476 .rxq_info_get = mlx5_rxq_info_get,
1477 .txq_info_get = mlx5_txq_info_get,
1478 .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1479 .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1480 .rx_queue_intr_enable = mlx5_rx_intr_enable,
1481 .rx_queue_intr_disable = mlx5_rx_intr_disable,
1482 .is_removed = mlx5_is_removed,
1483 .get_module_info = mlx5_get_module_info,
1484 .get_module_eeprom = mlx5_get_module_eeprom,
1485 .hairpin_cap_get = mlx5_hairpin_cap_get,
1486 .mtr_ops_get = mlx5_flow_meter_ops_get,
1490 * Verify and store value for device argument.
1493 * Key argument to verify.
1495 * Value associated with key.
1500 * 0 on success, a negative errno value otherwise and rte_errno is set.
1503 mlx5_args_check(const char *key, const char *val, void *opaque)
1505 struct mlx5_dev_config *config = opaque;
1508 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1509 if (!strcmp(MLX5_REPRESENTOR, key))
1512 tmp = strtoul(val, NULL, 0);
1515 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1518 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1519 config->cqe_comp = !!tmp;
1520 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1521 config->cqe_pad = !!tmp;
1522 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1523 config->hw_padding = !!tmp;
1524 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1525 config->mprq.enabled = !!tmp;
1526 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1527 config->mprq.stride_num_n = tmp;
1528 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1529 config->mprq.max_memcpy_len = tmp;
1530 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1531 config->mprq.min_rxqs_num = tmp;
1532 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1533 DRV_LOG(WARNING, "%s: deprecated parameter,"
1534 " converted to txq_inline_max", key);
1535 config->txq_inline_max = tmp;
1536 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1537 config->txq_inline_max = tmp;
1538 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1539 config->txq_inline_min = tmp;
1540 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1541 config->txq_inline_mpw = tmp;
1542 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1543 config->txqs_inline = tmp;
1544 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1545 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1546 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1547 config->mps = !!tmp;
1548 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1549 if (tmp != MLX5_TXDB_CACHED &&
1550 tmp != MLX5_TXDB_NCACHED &&
1551 tmp != MLX5_TXDB_HEURISTIC) {
1552 DRV_LOG(ERR, "invalid Tx doorbell "
1553 "mapping parameter");
1558 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1559 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1560 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1561 DRV_LOG(WARNING, "%s: deprecated parameter,"
1562 " converted to txq_inline_mpw", key);
1563 config->txq_inline_mpw = tmp;
1564 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1565 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1566 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1567 config->rx_vec_en = !!tmp;
1568 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1569 config->l3_vxlan_en = !!tmp;
1570 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1571 config->vf_nl_en = !!tmp;
1572 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1573 config->dv_esw_en = !!tmp;
1574 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1575 config->dv_flow_en = !!tmp;
1576 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1577 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1578 tmp != MLX5_XMETA_MODE_META16 &&
1579 tmp != MLX5_XMETA_MODE_META32) {
1580 DRV_LOG(ERR, "invalid extensive "
1581 "metadata parameter");
1585 config->dv_xmeta_en = tmp;
1586 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1587 config->mr_ext_memseg_en = !!tmp;
1588 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1589 config->max_dump_files_num = tmp;
1590 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1591 config->lro.timeout = tmp;
1592 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1593 DRV_LOG(DEBUG, "class argument is %s.", val);
1595 DRV_LOG(WARNING, "%s: unknown parameter", key);
1603 * Parse device parameters.
1606 * Pointer to device configuration structure.
1608 * Device arguments structure.
1611 * 0 on success, a negative errno value otherwise and rte_errno is set.
1614 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1616 const char **params = (const char *[]){
1617 MLX5_RXQ_CQE_COMP_EN,
1618 MLX5_RXQ_CQE_PAD_EN,
1619 MLX5_RXQ_PKT_PAD_EN,
1621 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1622 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1625 MLX5_TXQ_INLINE_MIN,
1626 MLX5_TXQ_INLINE_MAX,
1627 MLX5_TXQ_INLINE_MPW,
1628 MLX5_TXQS_MIN_INLINE,
1631 MLX5_TXQ_MPW_HDR_DSEG_EN,
1632 MLX5_TXQ_MAX_INLINE_LEN,
1641 MLX5_MR_EXT_MEMSEG_EN,
1643 MLX5_MAX_DUMP_FILES_NUM,
1644 MLX5_LRO_TIMEOUT_USEC,
1645 MLX5_CLASS_ARG_NAME,
1648 struct rte_kvargs *kvlist;
1652 if (devargs == NULL)
1654 /* Following UGLY cast is done to pass checkpatch. */
1655 kvlist = rte_kvargs_parse(devargs->args, params);
1656 if (kvlist == NULL) {
1660 /* Process parameters. */
1661 for (i = 0; (params[i] != NULL); ++i) {
1662 if (rte_kvargs_count(kvlist, params[i])) {
1663 ret = rte_kvargs_process(kvlist, params[i],
1664 mlx5_args_check, config);
1667 rte_kvargs_free(kvlist);
1672 rte_kvargs_free(kvlist);
1676 static struct rte_pci_driver mlx5_driver;
1679 * PMD global initialization.
1681 * Independent from individual device, this function initializes global
1682 * per-PMD data structures distinguishing primary and secondary processes.
1683 * Hence, each initialization is called once per a process.
1686 * 0 on success, a negative errno value otherwise and rte_errno is set.
1689 mlx5_init_once(void)
1691 struct mlx5_shared_data *sd;
1692 struct mlx5_local_data *ld = &mlx5_local_data;
1695 if (mlx5_init_shared_data())
1697 sd = mlx5_shared_data;
1699 rte_spinlock_lock(&sd->lock);
1700 switch (rte_eal_process_type()) {
1701 case RTE_PROC_PRIMARY:
1704 LIST_INIT(&sd->mem_event_cb_list);
1705 rte_rwlock_init(&sd->mem_event_rwlock);
1706 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
1707 mlx5_mr_mem_event_cb, NULL);
1708 ret = mlx5_mp_init_primary();
1711 sd->init_done = true;
1713 case RTE_PROC_SECONDARY:
1716 ret = mlx5_mp_init_secondary();
1719 ++sd->secondary_cnt;
1720 ld->init_done = true;
1726 rte_spinlock_unlock(&sd->lock);
1731 * Configures the minimal amount of data to inline into WQE
1732 * while sending packets.
1734 * - the txq_inline_min has the maximal priority, if this
1735 * key is specified in devargs
1736 * - if DevX is enabled the inline mode is queried from the
1737 * device (HCA attributes and NIC vport context if needed).
1738 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1739 * and none (0 bytes) for other NICs
1742 * Verbs device parameters (name, port, switch_info) to spawn.
1744 * Device configuration parameters.
1747 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1748 struct mlx5_dev_config *config)
1750 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1751 /* Application defines size of inlined data explicitly. */
1752 switch (spawn->pci_dev->id.device_id) {
1753 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1754 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1755 if (config->txq_inline_min <
1756 (int)MLX5_INLINE_HSIZE_L2) {
1758 "txq_inline_mix aligned to minimal"
1759 " ConnectX-4 required value %d",
1760 (int)MLX5_INLINE_HSIZE_L2);
1761 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1767 if (config->hca_attr.eth_net_offloads) {
1768 /* We have DevX enabled, inline mode queried successfully. */
1769 switch (config->hca_attr.wqe_inline_mode) {
1770 case MLX5_CAP_INLINE_MODE_L2:
1771 /* outer L2 header must be inlined. */
1772 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1774 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1775 /* No inline data are required by NIC. */
1776 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1777 config->hw_vlan_insert =
1778 config->hca_attr.wqe_vlan_insert;
1779 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1781 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1782 /* inline mode is defined by NIC vport context. */
1783 if (!config->hca_attr.eth_virt)
1785 switch (config->hca_attr.vport_inline_mode) {
1786 case MLX5_INLINE_MODE_NONE:
1787 config->txq_inline_min =
1788 MLX5_INLINE_HSIZE_NONE;
1790 case MLX5_INLINE_MODE_L2:
1791 config->txq_inline_min =
1792 MLX5_INLINE_HSIZE_L2;
1794 case MLX5_INLINE_MODE_IP:
1795 config->txq_inline_min =
1796 MLX5_INLINE_HSIZE_L3;
1798 case MLX5_INLINE_MODE_TCP_UDP:
1799 config->txq_inline_min =
1800 MLX5_INLINE_HSIZE_L4;
1802 case MLX5_INLINE_MODE_INNER_L2:
1803 config->txq_inline_min =
1804 MLX5_INLINE_HSIZE_INNER_L2;
1806 case MLX5_INLINE_MODE_INNER_IP:
1807 config->txq_inline_min =
1808 MLX5_INLINE_HSIZE_INNER_L3;
1810 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1811 config->txq_inline_min =
1812 MLX5_INLINE_HSIZE_INNER_L4;
1818 * We get here if we are unable to deduce
1819 * inline data size with DevX. Try PCI ID
1820 * to determine old NICs.
1822 switch (spawn->pci_dev->id.device_id) {
1823 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1824 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1825 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1826 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1827 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1828 config->hw_vlan_insert = 0;
1830 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1831 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1832 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1833 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1835 * These NICs support VLAN insertion from WQE and
1836 * report the wqe_vlan_insert flag. But there is the bug
1837 * and PFC control may be broken, so disable feature.
1839 config->hw_vlan_insert = 0;
1840 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1843 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1847 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1851 * Configures the metadata mask fields in the shared context.
1854 * Pointer to Ethernet device.
1857 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1859 struct mlx5_priv *priv = dev->data->dev_private;
1860 struct mlx5_ibv_shared *sh = priv->sh;
1861 uint32_t meta, mark, reg_c0;
1863 reg_c0 = ~priv->vport_meta_mask;
1864 switch (priv->config.dv_xmeta_en) {
1865 case MLX5_XMETA_MODE_LEGACY:
1867 mark = MLX5_FLOW_MARK_MASK;
1869 case MLX5_XMETA_MODE_META16:
1870 meta = reg_c0 >> rte_bsf32(reg_c0);
1871 mark = MLX5_FLOW_MARK_MASK;
1873 case MLX5_XMETA_MODE_META32:
1875 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1883 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1884 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1885 sh->dv_mark_mask, mark);
1887 sh->dv_mark_mask = mark;
1888 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1889 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1890 sh->dv_meta_mask, meta);
1892 sh->dv_meta_mask = meta;
1893 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1894 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1895 sh->dv_meta_mask, reg_c0);
1897 sh->dv_regc0_mask = reg_c0;
1898 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1899 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1900 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1901 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1905 * Allocate page of door-bells and register it using DevX API.
1908 * Pointer to Ethernet device.
1911 * Pointer to new page on success, NULL otherwise.
1913 static struct mlx5_devx_dbr_page *
1914 mlx5_alloc_dbr_page(struct rte_eth_dev *dev)
1916 struct mlx5_priv *priv = dev->data->dev_private;
1917 struct mlx5_devx_dbr_page *page;
1919 /* Allocate space for door-bell page and management data. */
1920 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page),
1921 RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1923 DRV_LOG(ERR, "port %u cannot allocate dbr page",
1924 dev->data->port_id);
1927 /* Register allocated memory. */
1928 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs,
1929 MLX5_DBR_PAGE_SIZE, 0);
1931 DRV_LOG(ERR, "port %u cannot umem reg dbr page",
1932 dev->data->port_id);
1940 * Find the next available door-bell, allocate new page if needed.
1943 * Pointer to Ethernet device.
1944 * @param [out] dbr_page
1945 * Door-bell page containing the page data.
1948 * Door-bell address offset on success, a negative error value otherwise.
1951 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page)
1953 struct mlx5_priv *priv = dev->data->dev_private;
1954 struct mlx5_devx_dbr_page *page = NULL;
1957 LIST_FOREACH(page, &priv->dbrpgs, next)
1958 if (page->dbr_count < MLX5_DBR_PER_PAGE)
1960 if (!page) { /* No page with free door-bell exists. */
1961 page = mlx5_alloc_dbr_page(dev);
1962 if (!page) /* Failed to allocate new page. */
1964 LIST_INSERT_HEAD(&priv->dbrpgs, page, next);
1966 /* Loop to find bitmap part with clear bit. */
1968 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX;
1971 /* Find the first clear bit. */
1972 j = rte_bsf64(~page->dbr_bitmap[i]);
1973 MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64));
1974 page->dbr_bitmap[i] |= (1 << j);
1977 return (((i * 64) + j) * sizeof(uint64_t));
1981 * Release a door-bell record.
1984 * Pointer to Ethernet device.
1985 * @param [in] umem_id
1986 * UMEM ID of page containing the door-bell record to release.
1987 * @param [in] offset
1988 * Offset of door-bell record in page.
1991 * 0 on success, a negative error value otherwise.
1994 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset)
1996 struct mlx5_priv *priv = dev->data->dev_private;
1997 struct mlx5_devx_dbr_page *page = NULL;
2000 LIST_FOREACH(page, &priv->dbrpgs, next)
2001 /* Find the page this address belongs to. */
2002 if (page->umem->umem_id == umem_id)
2007 if (!page->dbr_count) {
2008 /* Page not used, free it and remove from list. */
2009 LIST_REMOVE(page, next);
2011 ret = -mlx5_glue->devx_umem_dereg(page->umem);
2014 /* Mark in bitmap that this door-bell is not in use. */
2015 offset /= MLX5_DBR_SIZE;
2016 int i = offset / 64;
2017 int j = offset % 64;
2019 page->dbr_bitmap[i] &= ~(1 << j);
2025 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2027 static const char *const dynf_names[] = {
2028 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2029 RTE_MBUF_DYNFLAG_METADATA_NAME
2033 if (n < RTE_DIM(dynf_names))
2035 for (i = 0; i < RTE_DIM(dynf_names); i++) {
2036 if (names[i] == NULL)
2038 strcpy(names[i], dynf_names[i]);
2040 return RTE_DIM(dynf_names);
2044 * Check sibling device configurations.
2046 * Sibling devices sharing the Infiniband device context
2047 * should have compatible configurations. This regards
2048 * representors and bonding slaves.
2051 * Private device descriptor.
2053 * Configuration of the device is going to be created.
2056 * 0 on success, EINVAL otherwise
2059 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2060 struct mlx5_dev_config *config)
2062 struct mlx5_ibv_shared *sh = priv->sh;
2063 struct mlx5_dev_config *sh_conf = NULL;
2067 /* Nothing to compare for the single/first device. */
2068 if (sh->refcnt == 1)
2070 /* Find the device with shared context. */
2071 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2072 struct mlx5_priv *opriv =
2073 rte_eth_devices[port_id].data->dev_private;
2075 if (opriv && opriv != priv && opriv->sh == sh) {
2076 sh_conf = &opriv->config;
2082 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2083 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2084 " for shared %s context", sh->ibdev_name);
2088 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2089 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2090 " for shared %s context", sh->ibdev_name);
2097 * Spawn an Ethernet device from Verbs information.
2100 * Backing DPDK device.
2102 * Verbs device parameters (name, port, switch_info) to spawn.
2104 * Device configuration parameters.
2107 * A valid Ethernet device object on success, NULL otherwise and rte_errno
2108 * is set. The following errors are defined:
2110 * EBUSY: device is not supposed to be spawned.
2111 * EEXIST: device is already spawned
2113 static struct rte_eth_dev *
2114 mlx5_dev_spawn(struct rte_device *dpdk_dev,
2115 struct mlx5_dev_spawn_data *spawn,
2116 struct mlx5_dev_config config)
2118 const struct mlx5_switch_info *switch_info = &spawn->info;
2119 struct mlx5_ibv_shared *sh = NULL;
2120 struct ibv_port_attr port_attr;
2121 struct mlx5dv_context dv_attr = { .comp_mask = 0 };
2122 struct rte_eth_dev *eth_dev = NULL;
2123 struct mlx5_priv *priv = NULL;
2125 unsigned int hw_padding = 0;
2127 unsigned int cqe_comp;
2128 unsigned int cqe_pad = 0;
2129 unsigned int tunnel_en = 0;
2130 unsigned int mpls_en = 0;
2131 unsigned int swp = 0;
2132 unsigned int mprq = 0;
2133 unsigned int mprq_min_stride_size_n = 0;
2134 unsigned int mprq_max_stride_size_n = 0;
2135 unsigned int mprq_min_stride_num_n = 0;
2136 unsigned int mprq_max_stride_num_n = 0;
2137 struct rte_ether_addr mac;
2138 char name[RTE_ETH_NAME_MAX_LEN];
2139 int own_domain_id = 0;
2142 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2143 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 };
2146 /* Determine if this port representor is supposed to be spawned. */
2147 if (switch_info->representor && dpdk_dev->devargs) {
2148 struct rte_eth_devargs eth_da;
2150 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da);
2153 DRV_LOG(ERR, "failed to process device arguments: %s",
2154 strerror(rte_errno));
2157 for (i = 0; i < eth_da.nb_representor_ports; ++i)
2158 if (eth_da.representor_ports[i] ==
2159 (uint16_t)switch_info->port_name)
2161 if (i == eth_da.nb_representor_ports) {
2166 /* Build device name. */
2167 if (spawn->pf_bond < 0) {
2168 /* Single device. */
2169 if (!switch_info->representor)
2170 strlcpy(name, dpdk_dev->name, sizeof(name));
2172 snprintf(name, sizeof(name), "%s_representor_%u",
2173 dpdk_dev->name, switch_info->port_name);
2175 /* Bonding device. */
2176 if (!switch_info->representor)
2177 snprintf(name, sizeof(name), "%s_%s",
2178 dpdk_dev->name, spawn->ibv_dev->name);
2180 snprintf(name, sizeof(name), "%s_%s_representor_%u",
2181 dpdk_dev->name, spawn->ibv_dev->name,
2182 switch_info->port_name);
2184 /* check if the device is already spawned */
2185 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
2189 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
2190 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
2191 eth_dev = rte_eth_dev_attach_secondary(name);
2192 if (eth_dev == NULL) {
2193 DRV_LOG(ERR, "can not attach rte ethdev");
2197 eth_dev->device = dpdk_dev;
2198 eth_dev->dev_ops = &mlx5_dev_sec_ops;
2199 err = mlx5_proc_priv_init(eth_dev);
2202 /* Receive command fd from primary process */
2203 err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
2206 /* Remap UAR for Tx queues. */
2207 err = mlx5_tx_uar_init_secondary(eth_dev, err);
2211 * Ethdev pointer is still required as input since
2212 * the primary device is not accessible from the
2213 * secondary process.
2215 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
2216 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
2220 * Some parameters ("tx_db_nc" in particularly) are needed in
2221 * advance to create dv/verbs device context. We proceed the
2222 * devargs here to get ones, and later proceed devargs again
2223 * to override some hardware settings.
2225 err = mlx5_args(&config, dpdk_dev->devargs);
2228 DRV_LOG(ERR, "failed to process device arguments: %s",
2229 strerror(rte_errno));
2232 sh = mlx5_alloc_shared_ibctx(spawn, &config);
2235 config.devx = sh->devx;
2236 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR
2237 config.dest_tir = 1;
2239 #ifdef HAVE_IBV_MLX5_MOD_SWP
2240 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
2243 * Multi-packet send is supported by ConnectX-4 Lx PF as well
2244 * as all ConnectX-5 devices.
2246 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2247 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
2249 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2250 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
2252 mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
2253 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
2254 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
2255 DRV_LOG(DEBUG, "enhanced MPW is supported");
2256 mps = MLX5_MPW_ENHANCED;
2258 DRV_LOG(DEBUG, "MPW is supported");
2262 DRV_LOG(DEBUG, "MPW isn't supported");
2263 mps = MLX5_MPW_DISABLED;
2265 #ifdef HAVE_IBV_MLX5_MOD_SWP
2266 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
2267 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
2268 DRV_LOG(DEBUG, "SWP support: %u", swp);
2271 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
2272 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
2273 struct mlx5dv_striding_rq_caps mprq_caps =
2274 dv_attr.striding_rq_caps;
2276 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
2277 mprq_caps.min_single_stride_log_num_of_bytes);
2278 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
2279 mprq_caps.max_single_stride_log_num_of_bytes);
2280 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
2281 mprq_caps.min_single_wqe_log_num_of_strides);
2282 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
2283 mprq_caps.max_single_wqe_log_num_of_strides);
2284 DRV_LOG(DEBUG, "\tsupported_qpts: %d",
2285 mprq_caps.supported_qpts);
2286 DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
2288 mprq_min_stride_size_n =
2289 mprq_caps.min_single_stride_log_num_of_bytes;
2290 mprq_max_stride_size_n =
2291 mprq_caps.max_single_stride_log_num_of_bytes;
2292 mprq_min_stride_num_n =
2293 mprq_caps.min_single_wqe_log_num_of_strides;
2294 mprq_max_stride_num_n =
2295 mprq_caps.max_single_wqe_log_num_of_strides;
2296 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2297 mprq_min_stride_num_n);
2300 if (RTE_CACHE_LINE_SIZE == 128 &&
2301 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
2305 config.cqe_comp = cqe_comp;
2306 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
2307 /* Whether device supports 128B Rx CQE padding. */
2308 cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
2309 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
2311 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
2312 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
2313 tunnel_en = ((dv_attr.tunnel_offloads_caps &
2314 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
2315 (dv_attr.tunnel_offloads_caps &
2316 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) &&
2317 (dv_attr.tunnel_offloads_caps &
2318 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE));
2320 DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
2321 tunnel_en ? "" : "not ");
2324 "tunnel offloading disabled due to old OFED/rdma-core version");
2326 config.tunnel_en = tunnel_en;
2327 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
2328 mpls_en = ((dv_attr.tunnel_offloads_caps &
2329 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
2330 (dv_attr.tunnel_offloads_caps &
2331 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
2332 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
2333 mpls_en ? "" : "not ");
2335 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
2336 " old OFED/rdma-core version or firmware configuration");
2338 config.mpls_en = mpls_en;
2339 /* Check port status. */
2340 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
2342 DRV_LOG(ERR, "port query failed: %s", strerror(err));
2345 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
2346 DRV_LOG(ERR, "port is not configured in Ethernet mode");
2350 if (port_attr.state != IBV_PORT_ACTIVE)
2351 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
2352 mlx5_glue->port_state_str(port_attr.state),
2354 /* Allocate private eth device data. */
2355 priv = rte_zmalloc("ethdev private structure",
2357 RTE_CACHE_LINE_SIZE);
2359 DRV_LOG(ERR, "priv allocation failure");
2364 priv->ibv_port = spawn->ibv_port;
2365 priv->pci_dev = spawn->pci_dev;
2366 priv->mtu = RTE_ETHER_MTU;
2368 /* Initialize UAR access locks for 32bit implementations. */
2369 rte_spinlock_init(&priv->uar_lock_cq);
2370 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
2371 rte_spinlock_init(&priv->uar_lock[i]);
2373 /* Some internal functions rely on Netlink sockets, open them now. */
2374 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
2375 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE);
2376 priv->representor = !!switch_info->representor;
2377 priv->master = !!switch_info->master;
2378 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
2379 priv->vport_meta_tag = 0;
2380 priv->vport_meta_mask = 0;
2381 priv->pf_bond = spawn->pf_bond;
2382 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
2384 * The DevX port query API is implemented. E-Switch may use
2385 * either vport or reg_c[0] metadata register to match on
2386 * vport index. The engaged part of metadata register is
2389 if (switch_info->representor || switch_info->master) {
2390 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |
2391 MLX5DV_DEVX_PORT_MATCH_REG_C_0;
2392 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port,
2396 "can't query devx port %d on device %s",
2397 spawn->ibv_port, spawn->ibv_dev->name);
2398 devx_port.comp_mask = 0;
2401 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {
2402 priv->vport_meta_tag = devx_port.reg_c_0.value;
2403 priv->vport_meta_mask = devx_port.reg_c_0.mask;
2404 if (!priv->vport_meta_mask) {
2405 DRV_LOG(ERR, "vport zero mask for port %d"
2406 " on bonding device %s",
2407 spawn->ibv_port, spawn->ibv_dev->name);
2411 if (priv->vport_meta_tag & ~priv->vport_meta_mask) {
2412 DRV_LOG(ERR, "invalid vport tag for port %d"
2413 " on bonding device %s",
2414 spawn->ibv_port, spawn->ibv_dev->name);
2419 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {
2420 priv->vport_id = devx_port.vport_num;
2421 } else if (spawn->pf_bond >= 0) {
2422 DRV_LOG(ERR, "can't deduce vport index for port %d"
2423 " on bonding device %s",
2424 spawn->ibv_port, spawn->ibv_dev->name);
2428 /* Suppose vport index in compatible way. */
2429 priv->vport_id = switch_info->representor ?
2430 switch_info->port_name + 1 : -1;
2434 * Kernel/rdma_core support single E-Switch per PF configurations
2435 * only and vport_id field contains the vport index for
2436 * associated VF, which is deduced from representor port name.
2437 * For example, let's have the IB device port 10, it has
2438 * attached network device eth0, which has port name attribute
2439 * pf0vf2, we can deduce the VF number as 2, and set vport index
2440 * as 3 (2+1). This assigning schema should be changed if the
2441 * multiple E-Switch instances per PF configurations or/and PCI
2442 * subfunctions are added.
2444 priv->vport_id = switch_info->representor ?
2445 switch_info->port_name + 1 : -1;
2447 /* representor_id field keeps the unmodified VF index. */
2448 priv->representor_id = switch_info->representor ?
2449 switch_info->port_name : -1;
2451 * Look for sibling devices in order to reuse their switch domain
2452 * if any, otherwise allocate one.
2454 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2455 const struct mlx5_priv *opriv =
2456 rte_eth_devices[port_id].data->dev_private;
2459 opriv->sh != priv->sh ||
2461 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
2463 priv->domain_id = opriv->domain_id;
2466 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
2467 err = rte_eth_switch_domain_alloc(&priv->domain_id);
2470 DRV_LOG(ERR, "unable to allocate switch domain: %s",
2471 strerror(rte_errno));
2476 /* Override some values set by hardware configuration. */
2477 mlx5_args(&config, dpdk_dev->devargs);
2478 err = mlx5_dev_check_sibling_config(priv, &config);
2481 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
2482 IBV_DEVICE_RAW_IP_CSUM);
2483 DRV_LOG(DEBUG, "checksum offloading is %ssupported",
2484 (config.hw_csum ? "" : "not "));
2485 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
2486 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
2487 DRV_LOG(DEBUG, "counters are not supported");
2489 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR)
2490 if (config.dv_flow_en) {
2491 DRV_LOG(WARNING, "DV flow is not supported");
2492 config.dv_flow_en = 0;
2495 config.ind_table_max_size =
2496 sh->device_attr.rss_caps.max_rwq_indirection_table_size;
2498 * Remove this check once DPDK supports larger/variable
2499 * indirection tables.
2501 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
2502 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
2503 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
2504 config.ind_table_max_size);
2505 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
2506 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
2507 DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
2508 (config.hw_vlan_strip ? "" : "not "));
2509 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
2510 IBV_RAW_PACKET_CAP_SCATTER_FCS);
2511 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
2512 (config.hw_fcs_strip ? "" : "not "));
2513 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
2514 hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
2515 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
2516 hw_padding = !!(sh->device_attr.device_cap_flags_ex &
2517 IBV_DEVICE_PCI_WRITE_END_PADDING);
2519 if (config.hw_padding && !hw_padding) {
2520 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
2521 config.hw_padding = 0;
2522 } else if (config.hw_padding) {
2523 DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
2525 config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
2526 (sh->device_attr.tso_caps.supported_qpts &
2527 (1 << IBV_QPT_RAW_PACKET)));
2529 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
2531 * MPW is disabled by default, while the Enhanced MPW is enabled
2534 if (config.mps == MLX5_ARG_UNSET)
2535 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
2538 config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
2539 DRV_LOG(INFO, "%sMPS is %s",
2540 config.mps == MLX5_MPW_ENHANCED ? "enhanced " :
2541 config.mps == MLX5_MPW ? "legacy " : "",
2542 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
2543 if (config.cqe_comp && !cqe_comp) {
2544 DRV_LOG(WARNING, "Rx CQE compression isn't supported");
2545 config.cqe_comp = 0;
2547 if (config.cqe_pad && !cqe_pad) {
2548 DRV_LOG(WARNING, "Rx CQE padding isn't supported");
2550 } else if (config.cqe_pad) {
2551 DRV_LOG(INFO, "Rx CQE padding is enabled");
2554 priv->counter_fallback = 0;
2555 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
2560 if (!config.hca_attr.flow_counters_dump)
2561 priv->counter_fallback = 1;
2562 #ifndef HAVE_IBV_DEVX_ASYNC
2563 priv->counter_fallback = 1;
2565 if (priv->counter_fallback)
2566 DRV_LOG(INFO, "Use fall-back DV counter management");
2567 /* Check for LRO support. */
2568 if (config.dest_tir && config.hca_attr.lro_cap &&
2569 config.dv_flow_en) {
2570 /* TBD check tunnel lro caps. */
2571 config.lro.supported = config.hca_attr.lro_cap;
2572 DRV_LOG(DEBUG, "Device supports LRO");
2574 * If LRO timeout is not configured by application,
2575 * use the minimal supported value.
2577 if (!config.lro.timeout)
2578 config.lro.timeout =
2579 config.hca_attr.lro_timer_supported_periods[0];
2580 DRV_LOG(DEBUG, "LRO session timeout set to %d usec",
2581 config.lro.timeout);
2583 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER)
2584 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup &&
2585 config.dv_flow_en) {
2586 uint8_t reg_c_mask =
2587 config.hca_attr.qos.flow_meter_reg_c_ids;
2589 * Meter needs two REG_C's for color match and pre-sfx
2590 * flow match. Here get the REG_C for color match.
2591 * REG_C_0 and REG_C_1 is reserved for metadata feature.
2594 if (__builtin_popcount(reg_c_mask) < 1) {
2596 DRV_LOG(WARNING, "No available register for"
2599 priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
2602 priv->mtr_reg_share =
2603 config.hca_attr.qos.flow_meter_reg_share;
2604 DRV_LOG(DEBUG, "The REG_C meter uses is %d",
2605 priv->mtr_color_reg);
2610 if (config.mprq.enabled && mprq) {
2611 if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
2612 config.mprq.stride_num_n < mprq_min_stride_num_n) {
2613 config.mprq.stride_num_n =
2614 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
2615 mprq_min_stride_num_n);
2617 "the number of strides"
2618 " for Multi-Packet RQ is out of range,"
2619 " setting default value (%u)",
2620 1 << config.mprq.stride_num_n);
2622 config.mprq.min_stride_size_n = mprq_min_stride_size_n;
2623 config.mprq.max_stride_size_n = mprq_max_stride_size_n;
2624 } else if (config.mprq.enabled && !mprq) {
2625 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
2626 config.mprq.enabled = 0;
2628 if (config.max_dump_files_num == 0)
2629 config.max_dump_files_num = 128;
2630 eth_dev = rte_eth_dev_allocate(name);
2631 if (eth_dev == NULL) {
2632 DRV_LOG(ERR, "can not allocate rte ethdev");
2636 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
2637 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2638 if (priv->representor) {
2639 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
2640 eth_dev->data->representor_id = priv->representor_id;
2643 * Store associated network device interface index. This index
2644 * is permanent throughout the lifetime of device. So, we may store
2645 * the ifindex here and use the cached value further.
2647 MLX5_ASSERT(spawn->ifindex);
2648 priv->if_index = spawn->ifindex;
2649 eth_dev->data->dev_private = priv;
2650 priv->dev_data = eth_dev->data;
2651 eth_dev->data->mac_addrs = priv->mac;
2652 eth_dev->device = dpdk_dev;
2653 /* Configure the first MAC address by default. */
2654 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
2656 "port %u cannot get MAC address, is mlx5_en"
2657 " loaded? (errno: %s)",
2658 eth_dev->data->port_id, strerror(rte_errno));
2663 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
2664 eth_dev->data->port_id,
2665 mac.addr_bytes[0], mac.addr_bytes[1],
2666 mac.addr_bytes[2], mac.addr_bytes[3],
2667 mac.addr_bytes[4], mac.addr_bytes[5]);
2668 #ifdef RTE_LIBRTE_MLX5_DEBUG
2670 char ifname[IF_NAMESIZE];
2672 if (mlx5_get_ifname(eth_dev, &ifname) == 0)
2673 DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
2674 eth_dev->data->port_id, ifname);
2676 DRV_LOG(DEBUG, "port %u ifname is unknown",
2677 eth_dev->data->port_id);
2680 /* Get actual MTU if possible. */
2681 err = mlx5_get_mtu(eth_dev, &priv->mtu);
2686 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
2688 /* Initialize burst functions to prevent crashes before link-up. */
2689 eth_dev->rx_pkt_burst = removed_rx_burst;
2690 eth_dev->tx_pkt_burst = removed_tx_burst;
2691 eth_dev->dev_ops = &mlx5_dev_ops;
2692 /* Register MAC address. */
2693 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
2694 if (config.vf && config.vf_nl_en)
2695 mlx5_nl_mac_addr_sync(priv->nl_socket_route,
2696 mlx5_ifindex(eth_dev),
2697 eth_dev->data->mac_addrs,
2698 MLX5_MAX_MAC_ADDRESSES);
2699 TAILQ_INIT(&priv->flows);
2700 TAILQ_INIT(&priv->ctrl_flows);
2701 TAILQ_INIT(&priv->flow_meters);
2702 TAILQ_INIT(&priv->flow_meter_profiles);
2703 /* Hint libmlx5 to use PMD allocator for data plane resources */
2704 struct mlx5dv_ctx_allocators alctr = {
2705 .alloc = &mlx5_alloc_verbs_buf,
2706 .free = &mlx5_free_verbs_buf,
2709 mlx5_glue->dv_set_context_attr(sh->ctx,
2710 MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
2711 (void *)((uintptr_t)&alctr));
2712 /* Bring Ethernet device up. */
2713 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
2714 eth_dev->data->port_id);
2715 mlx5_set_link_up(eth_dev);
2717 * Even though the interrupt handler is not installed yet,
2718 * interrupts will still trigger on the async_fd from
2719 * Verbs context returned by ibv_open_device().
2721 mlx5_link_update(eth_dev, 0);
2722 #ifdef HAVE_MLX5DV_DR_ESWITCH
2723 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
2724 (switch_info->representor || switch_info->master)))
2725 config.dv_esw_en = 0;
2727 config.dv_esw_en = 0;
2729 /* Detect minimal data bytes to inline. */
2730 mlx5_set_min_inline(spawn, &config);
2731 /* Store device configuration on private structure. */
2732 priv->config = config;
2733 /* Create context for virtual machine VLAN workaround. */
2734 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex);
2735 if (config.dv_flow_en) {
2736 err = mlx5_alloc_shared_dr(priv);
2740 * RSS id is shared with meter flow id. Meter flow id can only
2741 * use the 24 MSB of the register.
2743 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >>
2744 MLX5_MTR_COLOR_BITS);
2745 if (!priv->qrss_id_pool) {
2746 DRV_LOG(ERR, "can't create flow id pool");
2751 /* Supported Verbs flow priority number detection. */
2752 err = mlx5_flow_discover_priorities(eth_dev);
2757 priv->config.flow_prio = err;
2758 if (!priv->config.dv_esw_en &&
2759 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2760 DRV_LOG(WARNING, "metadata mode %u is not supported "
2761 "(no E-Switch)", priv->config.dv_xmeta_en);
2762 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY;
2764 mlx5_set_metadata_mask(eth_dev);
2765 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2766 !priv->sh->dv_regc0_mask) {
2767 DRV_LOG(ERR, "metadata mode %u is not supported "
2768 "(no metadata reg_c[0] is available)",
2769 priv->config.dv_xmeta_en);
2774 * Allocate the buffer for flow creating, just once.
2775 * The allocation must be done before any flow creating.
2777 mlx5_flow_alloc_intermediate(eth_dev);
2778 /* Query availibility of metadata reg_c's. */
2779 err = mlx5_flow_discover_mreg_c(eth_dev);
2784 if (!mlx5_flow_ext_mreg_supported(eth_dev)) {
2786 "port %u extensive metadata register is not supported",
2787 eth_dev->data->port_id);
2788 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2789 DRV_LOG(ERR, "metadata mode %u is not supported "
2790 "(no metadata registers available)",
2791 priv->config.dv_xmeta_en);
2796 if (priv->config.dv_flow_en &&
2797 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
2798 mlx5_flow_ext_mreg_supported(eth_dev) &&
2799 priv->sh->dv_regc0_mask) {
2800 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME,
2801 MLX5_FLOW_MREG_HTABLE_SZ);
2802 if (!priv->mreg_cp_tbl) {
2810 if (priv->mreg_cp_tbl)
2811 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
2813 mlx5_free_shared_dr(priv);
2814 if (priv->nl_socket_route >= 0)
2815 close(priv->nl_socket_route);
2816 if (priv->nl_socket_rdma >= 0)
2817 close(priv->nl_socket_rdma);
2818 if (priv->vmwa_context)
2819 mlx5_vlan_vmwa_exit(priv->vmwa_context);
2820 if (priv->qrss_id_pool)
2821 mlx5_flow_id_pool_release(priv->qrss_id_pool);
2823 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
2825 if (eth_dev != NULL)
2826 eth_dev->data->dev_private = NULL;
2828 if (eth_dev != NULL) {
2829 /* mac_addrs must not be freed alone because part of dev_private */
2830 eth_dev->data->mac_addrs = NULL;
2831 rte_eth_dev_release_port(eth_dev);
2834 mlx5_free_shared_ibctx(sh);
2835 MLX5_ASSERT(err > 0);
2841 * Comparison callback to sort device data.
2843 * This is meant to be used with qsort().
2846 * Pointer to pointer to first data object.
2848 * Pointer to pointer to second data object.
2851 * 0 if both objects are equal, less than 0 if the first argument is less
2852 * than the second, greater than 0 otherwise.
2855 mlx5_dev_spawn_data_cmp(const void *a, const void *b)
2857 const struct mlx5_switch_info *si_a =
2858 &((const struct mlx5_dev_spawn_data *)a)->info;
2859 const struct mlx5_switch_info *si_b =
2860 &((const struct mlx5_dev_spawn_data *)b)->info;
2863 /* Master device first. */
2864 ret = si_b->master - si_a->master;
2867 /* Then representor devices. */
2868 ret = si_b->representor - si_a->representor;
2871 /* Unidentified devices come last in no specific order. */
2872 if (!si_a->representor)
2874 /* Order representors by name. */
2875 return si_a->port_name - si_b->port_name;
2879 * Match PCI information for possible slaves of bonding device.
2881 * @param[in] ibv_dev
2882 * Pointer to Infiniband device structure.
2883 * @param[in] pci_dev
2884 * Pointer to PCI device structure to match PCI address.
2885 * @param[in] nl_rdma
2886 * Netlink RDMA group socket handle.
2889 * negative value if no bonding device found, otherwise
2890 * positive index of slave PF in bonding.
2893 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev,
2894 const struct rte_pci_device *pci_dev,
2897 char ifname[IF_NAMESIZE + 1];
2898 unsigned int ifindex;
2904 * Try to get master device name. If something goes
2905 * wrong suppose the lack of kernel support and no
2910 if (!strstr(ibv_dev->name, "bond"))
2912 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name);
2916 * The Master device might not be on the predefined
2917 * port (not on port index 1, it is not garanted),
2918 * we have to scan all Infiniband device port and
2921 for (i = 1; i <= np; ++i) {
2922 /* Check whether Infiniband port is populated. */
2923 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i);
2926 if (!if_indextoname(ifindex, ifname))
2928 /* Try to read bonding slave names from sysfs. */
2930 "/sys/class/net/%s/master/bonding/slaves", ifname);
2931 file = fopen(slaves, "r");
2937 /* Use safe format to check maximal buffer length. */
2938 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE);
2939 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) {
2940 char tmp_str[IF_NAMESIZE + 32];
2941 struct rte_pci_addr pci_addr;
2942 struct mlx5_switch_info info;
2944 /* Process slave interface names in the loop. */
2945 snprintf(tmp_str, sizeof(tmp_str),
2946 "/sys/class/net/%s", ifname);
2947 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) {
2948 DRV_LOG(WARNING, "can not get PCI address"
2949 " for netdev \"%s\"", ifname);
2952 if (pci_dev->addr.domain != pci_addr.domain ||
2953 pci_dev->addr.bus != pci_addr.bus ||
2954 pci_dev->addr.devid != pci_addr.devid ||
2955 pci_dev->addr.function != pci_addr.function)
2957 /* Slave interface PCI address match found. */
2959 snprintf(tmp_str, sizeof(tmp_str),
2960 "/sys/class/net/%s/phys_port_name", ifname);
2961 file = fopen(tmp_str, "rb");
2964 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET;
2965 if (fscanf(file, "%32s", tmp_str) == 1)
2966 mlx5_translate_port_name(tmp_str, &info);
2967 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY ||
2968 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK)
2969 pf = info.port_name;
2978 * DPDK callback to register a PCI device.
2980 * This function spawns Ethernet devices out of a given PCI device.
2982 * @param[in] pci_drv
2983 * PCI driver structure (mlx5_driver).
2984 * @param[in] pci_dev
2985 * PCI device information.
2988 * 0 on success, a negative errno value otherwise and rte_errno is set.
2991 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2992 struct rte_pci_device *pci_dev)
2994 struct ibv_device **ibv_list;
2996 * Number of found IB Devices matching with requested PCI BDF.
2997 * nd != 1 means there are multiple IB devices over the same
2998 * PCI device and we have representors and master.
3000 unsigned int nd = 0;
3002 * Number of found IB device Ports. nd = 1 and np = 1..n means
3003 * we have the single multiport IB device, and there may be
3004 * representors attached to some of found ports.
3006 unsigned int np = 0;
3008 * Number of DPDK ethernet devices to Spawn - either over
3009 * multiple IB devices or multiple ports of single IB device.
3010 * Actually this is the number of iterations to spawn.
3012 unsigned int ns = 0;
3015 * < 0 - no bonding device (single one)
3016 * >= 0 - bonding device (value is slave PF index)
3019 struct mlx5_dev_spawn_data *list = NULL;
3020 struct mlx5_dev_config dev_config;
3023 if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) {
3024 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5"
3028 if (rte_eal_process_type() == RTE_PROC_PRIMARY)
3029 mlx5_pmd_socket_init();
3030 ret = mlx5_init_once();
3032 DRV_LOG(ERR, "unable to init PMD global data: %s",
3033 strerror(rte_errno));
3036 MLX5_ASSERT(pci_drv == &mlx5_driver);
3038 ibv_list = mlx5_glue->get_device_list(&ret);
3040 rte_errno = errno ? errno : ENOSYS;
3041 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
3045 * First scan the list of all Infiniband devices to find
3046 * matching ones, gathering into the list.
3048 struct ibv_device *ibv_match[ret + 1];
3049 int nl_route = mlx5_nl_init(NETLINK_ROUTE);
3050 int nl_rdma = mlx5_nl_init(NETLINK_RDMA);
3054 struct rte_pci_addr pci_addr;
3056 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
3057 bd = mlx5_device_bond_pci_match
3058 (ibv_list[ret], pci_dev, nl_rdma);
3061 * Bonding device detected. Only one match is allowed,
3062 * the bonding is supported over multi-port IB device,
3063 * there should be no matches on representor PCI
3064 * functions or non VF LAG bonding devices with
3065 * specified address.
3069 "multiple PCI match on bonding device"
3070 "\"%s\" found", ibv_list[ret]->name);
3075 DRV_LOG(INFO, "PCI information matches for"
3076 " slave %d bonding device \"%s\"",
3077 bd, ibv_list[ret]->name);
3078 ibv_match[nd++] = ibv_list[ret];
3081 if (mlx5_dev_to_pci_addr
3082 (ibv_list[ret]->ibdev_path, &pci_addr))
3084 if (pci_dev->addr.domain != pci_addr.domain ||
3085 pci_dev->addr.bus != pci_addr.bus ||
3086 pci_dev->addr.devid != pci_addr.devid ||
3087 pci_dev->addr.function != pci_addr.function)
3089 DRV_LOG(INFO, "PCI information matches for device \"%s\"",
3090 ibv_list[ret]->name);
3091 ibv_match[nd++] = ibv_list[ret];
3093 ibv_match[nd] = NULL;
3095 /* No device matches, just complain and bail out. */
3097 "no Verbs device matches PCI device " PCI_PRI_FMT ","
3098 " are kernel drivers loaded?",
3099 pci_dev->addr.domain, pci_dev->addr.bus,
3100 pci_dev->addr.devid, pci_dev->addr.function);
3107 * Found single matching device may have multiple ports.
3108 * Each port may be representor, we have to check the port
3109 * number and check the representors existence.
3112 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
3114 DRV_LOG(WARNING, "can not get IB device \"%s\""
3115 " ports number", ibv_match[0]->name);
3116 if (bd >= 0 && !np) {
3117 DRV_LOG(ERR, "can not get ports"
3118 " for bonding device");
3124 #ifndef HAVE_MLX5DV_DR_DEVX_PORT
3127 * This may happen if there is VF LAG kernel support and
3128 * application is compiled with older rdma_core library.
3131 "No kernel/verbs support for VF LAG bonding found.");
3132 rte_errno = ENOTSUP;
3138 * Now we can determine the maximal
3139 * amount of devices to be spawned.
3141 list = rte_zmalloc("device spawn data",
3142 sizeof(struct mlx5_dev_spawn_data) *
3144 RTE_CACHE_LINE_SIZE);
3146 DRV_LOG(ERR, "spawn data array allocation failure");
3151 if (bd >= 0 || np > 1) {
3153 * Single IB device with multiple ports found,
3154 * it may be E-Switch master device and representors.
3155 * We have to perform identification trough the ports.
3157 MLX5_ASSERT(nl_rdma >= 0);
3158 MLX5_ASSERT(ns == 0);
3159 MLX5_ASSERT(nd == 1);
3161 for (i = 1; i <= np; ++i) {
3162 list[ns].max_port = np;
3163 list[ns].ibv_port = i;
3164 list[ns].ibv_dev = ibv_match[0];
3165 list[ns].eth_dev = NULL;
3166 list[ns].pci_dev = pci_dev;
3167 list[ns].pf_bond = bd;
3168 list[ns].ifindex = mlx5_nl_ifindex
3169 (nl_rdma, list[ns].ibv_dev->name, i);
3170 if (!list[ns].ifindex) {
3172 * No network interface index found for the
3173 * specified port, it means there is no
3174 * representor on this port. It's OK,
3175 * there can be disabled ports, for example
3176 * if sriov_numvfs < sriov_totalvfs.
3182 ret = mlx5_nl_switch_info
3186 if (ret || (!list[ns].info.representor &&
3187 !list[ns].info.master)) {
3189 * We failed to recognize representors with
3190 * Netlink, let's try to perform the task
3193 ret = mlx5_sysfs_switch_info
3197 if (!ret && bd >= 0) {
3198 switch (list[ns].info.name_type) {
3199 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK:
3200 if (list[ns].info.port_name == bd)
3203 case MLX5_PHYS_PORT_NAME_TYPE_PFVF:
3204 if (list[ns].info.pf_num == bd)
3212 if (!ret && (list[ns].info.representor ^
3213 list[ns].info.master))
3218 "unable to recognize master/representors"
3219 " on the IB device with multiple ports");
3226 * The existence of several matching entries (nd > 1) means
3227 * port representors have been instantiated. No existing Verbs
3228 * call nor sysfs entries can tell them apart, this can only
3229 * be done through Netlink calls assuming kernel drivers are
3230 * recent enough to support them.
3232 * In the event of identification failure through Netlink,
3233 * try again through sysfs, then:
3235 * 1. A single IB device matches (nd == 1) with single
3236 * port (np=0/1) and is not a representor, assume
3237 * no switch support.
3239 * 2. Otherwise no safe assumptions can be made;
3240 * complain louder and bail out.
3243 for (i = 0; i != nd; ++i) {
3244 memset(&list[ns].info, 0, sizeof(list[ns].info));
3245 list[ns].max_port = 1;
3246 list[ns].ibv_port = 1;
3247 list[ns].ibv_dev = ibv_match[i];
3248 list[ns].eth_dev = NULL;
3249 list[ns].pci_dev = pci_dev;
3250 list[ns].pf_bond = -1;
3251 list[ns].ifindex = 0;
3253 list[ns].ifindex = mlx5_nl_ifindex
3254 (nl_rdma, list[ns].ibv_dev->name, 1);
3255 if (!list[ns].ifindex) {
3256 char ifname[IF_NAMESIZE];
3259 * Netlink failed, it may happen with old
3260 * ib_core kernel driver (before 4.16).
3261 * We can assume there is old driver because
3262 * here we are processing single ports IB
3263 * devices. Let's try sysfs to retrieve
3264 * the ifindex. The method works for
3265 * master device only.
3269 * Multiple devices found, assume
3270 * representors, can not distinguish
3271 * master/representor and retrieve
3272 * ifindex via sysfs.
3276 ret = mlx5_get_master_ifname
3277 (ibv_match[i]->ibdev_path, &ifname);
3280 if_nametoindex(ifname);
3281 if (!list[ns].ifindex) {
3283 * No network interface index found
3284 * for the specified device, it means
3285 * there it is neither representor
3293 ret = mlx5_nl_switch_info
3297 if (ret || (!list[ns].info.representor &&
3298 !list[ns].info.master)) {
3300 * We failed to recognize representors with
3301 * Netlink, let's try to perform the task
3304 ret = mlx5_sysfs_switch_info
3308 if (!ret && (list[ns].info.representor ^
3309 list[ns].info.master)) {
3311 } else if ((nd == 1) &&
3312 !list[ns].info.representor &&
3313 !list[ns].info.master) {
3315 * Single IB device with
3316 * one physical port and
3317 * attached network device.
3318 * May be SRIOV is not enabled
3319 * or there is no representors.
3321 DRV_LOG(INFO, "no E-Switch support detected");
3328 "unable to recognize master/representors"
3329 " on the multiple IB devices");
3337 * Sort list to probe devices in natural order for users convenience
3338 * (i.e. master first, then representors from lowest to highest ID).
3340 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
3341 /* Default configuration. */
3342 dev_config = (struct mlx5_dev_config){
3344 .mps = MLX5_ARG_UNSET,
3345 .dbnc = MLX5_ARG_UNSET,
3347 .txq_inline_max = MLX5_ARG_UNSET,
3348 .txq_inline_min = MLX5_ARG_UNSET,
3349 .txq_inline_mpw = MLX5_ARG_UNSET,
3350 .txqs_inline = MLX5_ARG_UNSET,
3352 .mr_ext_memseg_en = 1,
3354 .enabled = 0, /* Disabled by default. */
3355 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
3356 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
3357 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
3362 /* Device specific configuration. */
3363 switch (pci_dev->id.device_id) {
3364 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
3365 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
3366 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
3367 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
3368 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF:
3369 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF:
3370 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF:
3376 for (i = 0; i != ns; ++i) {
3379 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
3382 if (!list[i].eth_dev) {
3383 if (rte_errno != EBUSY && rte_errno != EEXIST)
3385 /* Device is disabled or already spawned. Ignore it. */
3388 restore = list[i].eth_dev->data->dev_flags;
3389 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
3390 /* Restore non-PCI flags cleared by the above call. */
3391 list[i].eth_dev->data->dev_flags |= restore;
3392 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev);
3393 rte_eth_dev_probing_finish(list[i].eth_dev);
3397 "probe of PCI device " PCI_PRI_FMT " aborted after"
3398 " encountering an error: %s",
3399 pci_dev->addr.domain, pci_dev->addr.bus,
3400 pci_dev->addr.devid, pci_dev->addr.function,
3401 strerror(rte_errno));
3405 if (!list[i].eth_dev)
3407 mlx5_dev_close(list[i].eth_dev);
3408 /* mac_addrs must not be freed because in dev_private */
3409 list[i].eth_dev->data->mac_addrs = NULL;
3410 claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
3412 /* Restore original error. */
3419 * Do the routine cleanup:
3420 * - close opened Netlink sockets
3421 * - free allocated spawn data array
3422 * - free the Infiniband device list
3430 MLX5_ASSERT(ibv_list);
3431 mlx5_glue->free_device_list(ibv_list);
3436 * Look for the ethernet device belonging to mlx5 driver.
3438 * @param[in] port_id
3439 * port_id to start looking for device.
3440 * @param[in] pci_dev
3441 * Pointer to the hint PCI device. When device is being probed
3442 * the its siblings (master and preceding representors might
3443 * not have assigned driver yet (because the mlx5_pci_probe()
3444 * is not completed yet, for this case match on hint PCI
3445 * device may be used to detect sibling device.
3448 * port_id of found device, RTE_MAX_ETHPORT if not found.
3451 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
3453 while (port_id < RTE_MAX_ETHPORTS) {
3454 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3456 if (dev->state != RTE_ETH_DEV_UNUSED &&
3458 (dev->device == &pci_dev->device ||
3459 (dev->device->driver &&
3460 dev->device->driver->name &&
3461 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
3465 if (port_id >= RTE_MAX_ETHPORTS)
3466 return RTE_MAX_ETHPORTS;
3471 * DPDK callback to remove a PCI device.
3473 * This function removes all Ethernet devices belong to a given PCI device.
3475 * @param[in] pci_dev
3476 * Pointer to the PCI device.
3479 * 0 on success, the function cannot fail.
3482 mlx5_pci_remove(struct rte_pci_device *pci_dev)
3486 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
3487 rte_eth_dev_close(port_id);
3491 static const struct rte_pci_id mlx5_pci_id_map[] = {
3493 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3494 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
3497 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3498 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
3501 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3502 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
3505 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3506 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
3509 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3510 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
3513 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3514 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
3517 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3518 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
3521 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3522 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
3525 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3526 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
3529 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3530 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
3533 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3534 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
3537 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3538 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
3541 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3542 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
3545 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3546 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
3549 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
3550 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
3557 static struct rte_pci_driver mlx5_driver = {
3559 .name = MLX5_DRIVER_NAME
3561 .id_table = mlx5_pci_id_map,
3562 .probe = mlx5_pci_probe,
3563 .remove = mlx5_pci_remove,
3564 .dma_map = mlx5_dma_map,
3565 .dma_unmap = mlx5_dma_unmap,
3566 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
3567 RTE_PCI_DRV_PROBE_AGAIN,
3571 * Driver initialization routine.
3573 RTE_INIT(rte_mlx5_pmd_init)
3575 /* Initialize driver log type. */
3576 mlx5_logtype = rte_log_register("pmd.net.mlx5");
3577 if (mlx5_logtype >= 0)
3578 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
3580 /* Build the static tables for Verbs conversion. */
3581 mlx5_set_ptype_table();
3582 mlx5_set_cksum_table();
3583 mlx5_set_swp_types_table();
3585 rte_pci_register(&mlx5_driver);
3588 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
3589 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
3590 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");