1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
13 #include <linux/rtnetlink.h>
15 #include <rte_malloc.h>
16 #include <rte_ethdev_driver.h>
17 #include <rte_ethdev_pci.h>
19 #include <rte_bus_pci.h>
20 #include <rte_common.h>
21 #include <rte_kvargs.h>
22 #include <rte_rwlock.h>
23 #include <rte_spinlock.h>
24 #include <rte_string_fns.h>
25 #include <rte_alarm.h>
27 #include <mlx5_glue.h>
28 #include <mlx5_devx_cmds.h>
29 #include <mlx5_common.h>
30 #include <mlx5_common_os.h>
31 #include <mlx5_common_mp.h>
32 #include <mlx5_common_pci.h>
33 #include <mlx5_malloc.h>
35 #include "mlx5_defs.h"
37 #include "mlx5_utils.h"
38 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
41 #include "mlx5_flow.h"
42 #include "rte_pmd_mlx5.h"
44 /* Device parameter to enable RX completion queue compression. */
45 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
47 /* Device parameter to enable RX completion entry padding to 128B. */
48 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
50 /* Device parameter to enable padding Rx packet to cacheline size. */
51 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
53 /* Device parameter to enable Multi-Packet Rx queue. */
54 #define MLX5_RX_MPRQ_EN "mprq_en"
56 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
57 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
59 /* Device parameter to configure log 2 of the stride size for MPRQ. */
60 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
62 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
63 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
65 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
66 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
68 /* Device parameter to configure inline send. Deprecated, ignored.*/
69 #define MLX5_TXQ_INLINE "txq_inline"
71 /* Device parameter to limit packet size to inline with ordinary SEND. */
72 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
74 /* Device parameter to configure minimal data size to inline. */
75 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
77 /* Device parameter to limit packet size to inline with Enhanced MPW. */
78 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
81 * Device parameter to configure the number of TX queues threshold for
82 * enabling inline send.
84 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
87 * Device parameter to configure the number of TX queues threshold for
88 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
90 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
92 /* Device parameter to enable multi-packet send WQEs. */
93 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
96 * Device parameter to force doorbell register mapping
97 * to non-cahed region eliminating the extra write memory barrier.
99 #define MLX5_TX_DB_NC "tx_db_nc"
102 * Device parameter to include 2 dsegs in the title WQEBB.
103 * Deprecated, ignored.
105 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
108 * Device parameter to limit the size of inlining packet.
109 * Deprecated, ignored.
111 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
114 * Device parameter to enable Tx scheduling on timestamps
115 * and specify the packet pacing granularity in nanoseconds.
117 #define MLX5_TX_PP "tx_pp"
120 * Device parameter to specify skew in nanoseconds on Tx datapath,
121 * it represents the time between SQ start WQE processing and
122 * appearing actual packet data on the wire.
124 #define MLX5_TX_SKEW "tx_skew"
127 * Device parameter to enable hardware Tx vector.
128 * Deprecated, ignored (no vectorized Tx routines anymore).
130 #define MLX5_TX_VEC_EN "tx_vec_en"
132 /* Device parameter to enable hardware Rx vector. */
133 #define MLX5_RX_VEC_EN "rx_vec_en"
135 /* Allow L3 VXLAN flow creation. */
136 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
138 /* Activate DV E-Switch flow steering. */
139 #define MLX5_DV_ESW_EN "dv_esw_en"
141 /* Activate DV flow steering. */
142 #define MLX5_DV_FLOW_EN "dv_flow_en"
144 /* Enable extensive flow metadata support. */
145 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
147 /* Device parameter to let the user manage the lacp traffic of bonded device */
148 #define MLX5_LACP_BY_USER "lacp_by_user"
150 /* Activate Netlink support in VF mode. */
151 #define MLX5_VF_NL_EN "vf_nl_en"
153 /* Enable extending memsegs when creating a MR. */
154 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
156 /* Select port representors to instantiate. */
157 #define MLX5_REPRESENTOR "representor"
159 /* Device parameter to configure the maximum number of dump files per queue. */
160 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
162 /* Configure timeout of LRO session (in microseconds). */
163 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
166 * Device parameter to configure the total data buffer size for a single
167 * hairpin queue (logarithm value).
169 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
171 /* Flow memory reclaim mode. */
172 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
174 /* The default memory allocator used in PMD. */
175 #define MLX5_SYS_MEM_EN "sys_mem_en"
176 /* Decap will be used or not. */
177 #define MLX5_DECAP_EN "decap_en"
179 /* Shared memory between primary and secondary processes. */
180 struct mlx5_shared_data *mlx5_shared_data;
182 /** Driver-specific log messages type. */
185 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
186 LIST_HEAD_INITIALIZER();
187 static pthread_mutex_t mlx5_dev_ctx_list_mutex = PTHREAD_MUTEX_INITIALIZER;
189 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
190 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
192 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
198 .malloc = mlx5_malloc,
200 .type = "mlx5_encap_decap_ipool",
203 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
209 .malloc = mlx5_malloc,
211 .type = "mlx5_push_vlan_ipool",
214 .size = sizeof(struct mlx5_flow_dv_tag_resource),
220 .malloc = mlx5_malloc,
222 .type = "mlx5_tag_ipool",
225 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
231 .malloc = mlx5_malloc,
233 .type = "mlx5_port_id_ipool",
236 .size = sizeof(struct mlx5_flow_tbl_data_entry),
242 .malloc = mlx5_malloc,
244 .type = "mlx5_jump_ipool",
248 .size = sizeof(struct mlx5_flow_meter),
254 .malloc = mlx5_malloc,
256 .type = "mlx5_meter_ipool",
259 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
265 .malloc = mlx5_malloc,
267 .type = "mlx5_mcp_ipool",
270 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
276 .malloc = mlx5_malloc,
278 .type = "mlx5_hrxq_ipool",
282 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
283 * It set in run time according to PCI function configuration.
291 .malloc = mlx5_malloc,
293 .type = "mlx5_flow_handle_ipool",
296 .size = sizeof(struct rte_flow),
300 .malloc = mlx5_malloc,
302 .type = "rte_flow_ipool",
307 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
308 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
310 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
313 * Allocate ID pool structure.
316 * The maximum id can be allocated from the pool.
319 * Pointer to pool object, NULL value otherwise.
321 struct mlx5_flow_id_pool *
322 mlx5_flow_id_pool_alloc(uint32_t max_id)
324 struct mlx5_flow_id_pool *pool;
327 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool),
328 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
330 DRV_LOG(ERR, "can't allocate id pool");
334 mem = mlx5_malloc(MLX5_MEM_ZERO,
335 MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t),
336 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
338 DRV_LOG(ERR, "can't allocate mem for id pool");
342 pool->free_arr = mem;
343 pool->curr = pool->free_arr;
344 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE;
345 pool->base_index = 0;
346 pool->max_id = max_id;
354 * Release ID pool structure.
357 * Pointer to flow id pool object to free.
360 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool)
362 mlx5_free(pool->free_arr);
370 * Pointer to flow id pool.
375 * 0 on success, error value otherwise.
378 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id)
380 if (pool->curr == pool->free_arr) {
381 if (pool->base_index == pool->max_id) {
383 DRV_LOG(ERR, "no free id");
386 *id = ++pool->base_index;
389 *id = *(--pool->curr);
397 * Pointer to flow id pool.
402 * 0 on success, error value otherwise.
405 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id)
411 if (pool->curr == pool->last) {
412 size = pool->curr - pool->free_arr;
413 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR;
414 MLX5_ASSERT(size2 > size);
415 mem = mlx5_malloc(0, size2 * sizeof(uint32_t), 0,
418 DRV_LOG(ERR, "can't allocate mem for id pool");
422 memcpy(mem, pool->free_arr, size * sizeof(uint32_t));
423 mlx5_free(pool->free_arr);
424 pool->free_arr = mem;
425 pool->curr = pool->free_arr + size;
426 pool->last = pool->free_arr + size2;
434 * Initialize the shared aging list information per port.
437 * Pointer to mlx5_dev_ctx_shared object.
440 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
443 struct mlx5_age_info *age_info;
445 for (i = 0; i < sh->max_port; i++) {
446 age_info = &sh->port[i].age_info;
448 TAILQ_INIT(&age_info->aged_counters);
449 rte_spinlock_init(&age_info->aged_sl);
450 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
455 * Initialize the counters management structure.
458 * Pointer to mlx5_dev_ctx_shared object to free
461 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
465 memset(&sh->cmng, 0, sizeof(sh->cmng));
466 TAILQ_INIT(&sh->cmng.flow_counters);
467 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
468 sh->cmng.ccont[i].min_id = MLX5_CNT_BATCH_OFFSET;
469 sh->cmng.ccont[i].max_id = -1;
470 sh->cmng.ccont[i].last_pool_idx = POOL_IDX_INVALID;
471 TAILQ_INIT(&sh->cmng.ccont[i].pool_list);
472 rte_spinlock_init(&sh->cmng.ccont[i].resize_sl);
473 TAILQ_INIT(&sh->cmng.ccont[i].counters);
474 rte_spinlock_init(&sh->cmng.ccont[i].csl);
479 * Destroy all the resources allocated for a counter memory management.
482 * Pointer to the memory management structure.
485 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
487 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
489 LIST_REMOVE(mng, next);
490 claim_zero(mlx5_devx_cmd_destroy(mng->dm));
491 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem));
496 * Close and release all the resources of the counters management.
499 * Pointer to mlx5_dev_ctx_shared object to free.
502 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
504 struct mlx5_counter_stats_mem_mng *mng;
511 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
512 if (rte_errno != EINPROGRESS)
516 for (i = 0; i < MLX5_CCONT_TYPE_MAX; ++i) {
517 struct mlx5_flow_counter_pool *pool;
518 uint32_t batch = !!(i > 1);
520 if (!sh->cmng.ccont[i].pools)
522 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
524 if (batch && pool->min_dcs)
525 claim_zero(mlx5_devx_cmd_destroy
527 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
528 if (MLX5_POOL_GET_CNT(pool, j)->action)
530 (mlx5_glue->destroy_flow_action
533 if (!batch && MLX5_GET_POOL_CNT_EXT
535 claim_zero(mlx5_devx_cmd_destroy
536 (MLX5_GET_POOL_CNT_EXT
539 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, next);
541 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list);
543 mlx5_free(sh->cmng.ccont[i].pools);
545 mng = LIST_FIRST(&sh->cmng.mem_mngs);
547 mlx5_flow_destroy_counter_stat_mem_mng(mng);
548 mng = LIST_FIRST(&sh->cmng.mem_mngs);
550 memset(&sh->cmng, 0, sizeof(sh->cmng));
554 * Initialize the flow resources' indexed mempool.
557 * Pointer to mlx5_dev_ctx_shared object.
559 * Pointer to user dev config.
562 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
563 const struct mlx5_dev_config *config)
566 struct mlx5_indexed_pool_config cfg;
568 for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
569 cfg = mlx5_ipool_cfg[i];
574 * Set MLX5_IPOOL_MLX5_FLOW ipool size
575 * according to PCI function flow configuration.
577 case MLX5_IPOOL_MLX5_FLOW:
578 cfg.size = config->dv_flow_en ?
579 sizeof(struct mlx5_flow_handle) :
580 MLX5_FLOW_HANDLE_VERBS_SIZE;
583 if (config->reclaim_mode)
584 cfg.release_mem_en = 1;
585 sh->ipool[i] = mlx5_ipool_create(&cfg);
590 * Release the flow resources' indexed mempool.
593 * Pointer to mlx5_dev_ctx_shared object.
596 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
600 for (i = 0; i < MLX5_IPOOL_MAX; ++i)
601 mlx5_ipool_destroy(sh->ipool[i]);
605 * Check if dynamic flex parser for eCPRI already exists.
608 * Pointer to Ethernet device structure.
611 * true on exists, false on not.
614 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
616 struct mlx5_priv *priv = dev->data->dev_private;
617 struct mlx5_flex_parser_profiles *prf =
618 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
624 * Allocation of a flex parser for eCPRI. Once created, this parser related
625 * resources will be held until the device is closed.
628 * Pointer to Ethernet device structure.
631 * 0 on success, a negative errno value otherwise and rte_errno is set.
634 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
636 struct mlx5_priv *priv = dev->data->dev_private;
637 struct mlx5_flex_parser_profiles *prf =
638 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
639 struct mlx5_devx_graph_node_attr node = {
640 .modify_field_select = 0,
645 if (!priv->config.hca_attr.parse_graph_flex_node) {
646 DRV_LOG(ERR, "Dynamic flex parser is not supported "
647 "for device %s.", priv->dev_data->name);
650 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
651 /* 8 bytes now: 4B common header + 4B message body header. */
652 node.header_length_base_value = 0x8;
653 /* After MAC layer: Ether / VLAN. */
654 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
655 /* Type of compared condition should be 0xAEFE in the L2 layer. */
656 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
657 /* Sample #0: type in common header. */
658 node.sample[0].flow_match_sample_en = 1;
660 node.sample[0].flow_match_sample_offset_mode = 0x0;
661 /* Only the 2nd byte will be used. */
662 node.sample[0].flow_match_sample_field_base_offset = 0x0;
663 /* Sample #1: message payload. */
664 node.sample[1].flow_match_sample_en = 1;
666 node.sample[1].flow_match_sample_offset_mode = 0x0;
668 * Only the first two bytes will be used right now, and its offset will
669 * start after the common header that with the length of a DW(u32).
671 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
672 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
674 DRV_LOG(ERR, "Failed to create flex parser node object.");
675 return (rte_errno == 0) ? -ENODEV : -rte_errno;
678 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
680 DRV_LOG(ERR, "Failed to query sample IDs.");
681 return (rte_errno == 0) ? -ENODEV : -rte_errno;
683 prf->offset[0] = 0x0;
684 prf->offset[1] = sizeof(uint32_t);
685 prf->ids[0] = ids[0];
686 prf->ids[1] = ids[1];
691 * Destroy the flex parser node, including the parser itself, input / output
692 * arcs and DW samples. Resources could be reused then.
695 * Pointer to Ethernet device structure.
698 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
700 struct mlx5_priv *priv = dev->data->dev_private;
701 struct mlx5_flex_parser_profiles *prf =
702 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
705 mlx5_devx_cmd_destroy(prf->obj);
710 * Allocate Rx and Tx UARs in robust fashion.
711 * This routine handles the following UAR allocation issues:
713 * - tries to allocate the UAR with the most appropriate memory
714 * mapping type from the ones supported by the host
716 * - tries to allocate the UAR with non-NULL base address
717 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
718 * UAR base address if UAR was not the first object in the UAR page.
719 * It caused the PMD failure and we should try to get another UAR
720 * till we get the first one with non-NULL base address returned.
723 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
724 const struct mlx5_dev_config *config)
726 uint32_t uar_mapping, retry;
729 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
730 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
731 /* Control the mapping type according to the settings. */
732 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
733 MLX5DV_UAR_ALLOC_TYPE_NC :
734 MLX5DV_UAR_ALLOC_TYPE_BF;
736 RTE_SET_USED(config);
738 * It seems we have no way to control the memory mapping type
739 * for the UAR, the default "Write-Combining" type is supposed.
740 * The UAR initialization on queue creation queries the
741 * actual mapping type done by Verbs/kernel and setups the
742 * PMD datapath accordingly.
746 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
747 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
749 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
750 if (config->dbnc == MLX5_TXDB_CACHED ||
751 config->dbnc == MLX5_TXDB_HEURISTIC)
752 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
753 "is not supported by DevX");
755 * In some environments like virtual machine
756 * the Write Combining mapped might be not supported
757 * and UAR allocation fails. We try "Non-Cached"
758 * mapping for the case. The tx_burst routines take
759 * the UAR mapping type into account on UAR setup
762 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)");
763 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
764 sh->tx_uar = mlx5_glue->devx_alloc_uar
765 (sh->ctx, uar_mapping);
766 } else if (!sh->tx_uar &&
767 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
768 if (config->dbnc == MLX5_TXDB_NCACHED)
769 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
770 "is not supported by DevX");
772 * If Verbs/kernel does not support "Non-Cached"
773 * try the "Write-Combining".
775 DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)");
776 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
777 sh->tx_uar = mlx5_glue->devx_alloc_uar
778 (sh->ctx, uar_mapping);
782 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
786 if (sh->tx_uar->base_addr)
789 * The UARs are allocated by rdma_core within the
790 * IB device context, on context closure all UARs
791 * will be freed, should be no memory/object leakage.
793 DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR");
796 /* Check whether we finally succeeded with valid UAR allocation. */
798 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
802 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
804 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
805 (sh->ctx, uar_mapping);
806 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
807 if (!sh->devx_rx_uar &&
808 uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
810 * Rx UAR is used to control interrupts only,
811 * should be no datapath noticeable impact,
812 * can try "Non-Cached" mapping safely.
814 DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)");
815 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
816 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
817 (sh->ctx, uar_mapping);
820 if (!sh->devx_rx_uar) {
821 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
825 if (sh->devx_rx_uar->base_addr)
828 * The UARs are allocated by rdma_core within the
829 * IB device context, on context closure all UARs
830 * will be freed, should be no memory/object leakage.
832 DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR");
833 sh->devx_rx_uar = NULL;
835 /* Check whether we finally succeeded with valid UAR allocation. */
836 if (!sh->devx_rx_uar) {
837 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
845 * Allocate shared device context. If there is multiport device the
846 * master and representors will share this context, if there is single
847 * port dedicated device, the context will be used by only given
848 * port due to unification.
850 * Routine first searches the context for the specified device name,
851 * if found the shared context assumed and reference counter is incremented.
852 * If no context found the new one is created and initialized with specified
853 * device context and parameters.
856 * Pointer to the device attributes (name, port, etc).
858 * Pointer to device configuration structure.
861 * Pointer to mlx5_dev_ctx_shared object on success,
862 * otherwise NULL and rte_errno is set.
864 struct mlx5_dev_ctx_shared *
865 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
866 const struct mlx5_dev_config *config)
868 struct mlx5_dev_ctx_shared *sh;
871 struct mlx5_devx_tis_attr tis_attr = { 0 };
874 /* Secondary process should not create the shared context. */
875 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
876 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
877 /* Search for IB context by device name. */
878 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
879 if (!strcmp(sh->ibdev_name,
880 mlx5_os_get_dev_device_name(spawn->phys_dev))) {
885 /* No device found, we have to create new shared context. */
886 MLX5_ASSERT(spawn->max_port);
887 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
888 sizeof(struct mlx5_dev_ctx_shared) +
890 sizeof(struct mlx5_dev_shared_port),
891 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
893 DRV_LOG(ERR, "shared context allocation failure");
897 err = mlx5_os_open_device(spawn, config, sh);
900 err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
902 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
906 sh->max_port = spawn->max_port;
907 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
908 sizeof(sh->ibdev_name) - 1);
909 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
910 sizeof(sh->ibdev_path) - 1);
912 * Setting port_id to max unallowed value means
913 * there is no interrupt subhandler installed for
914 * the given port index i.
916 for (i = 0; i < sh->max_port; i++) {
917 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
918 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
920 sh->pd = mlx5_glue->alloc_pd(sh->ctx);
921 if (sh->pd == NULL) {
922 DRV_LOG(ERR, "PD allocation failure");
927 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
929 DRV_LOG(ERR, "Fail to extract pdn from PD");
932 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
934 DRV_LOG(ERR, "TD allocation failure");
938 tis_attr.transport_domain = sh->td->id;
939 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
941 DRV_LOG(ERR, "TIS allocation failure");
945 err = mlx5_alloc_rxtx_uars(sh, config);
948 MLX5_ASSERT(sh->tx_uar && sh->tx_uar->base_addr);
949 MLX5_ASSERT(sh->devx_rx_uar && sh->devx_rx_uar->base_addr);
951 sh->flow_id_pool = mlx5_flow_id_pool_alloc
952 ((1 << HAIRPIN_FLOW_ID_BITS) - 1);
953 if (!sh->flow_id_pool) {
954 DRV_LOG(ERR, "can't create flow id pool");
959 /* Initialize UAR access locks for 32bit implementations. */
960 rte_spinlock_init(&sh->uar_lock_cq);
961 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
962 rte_spinlock_init(&sh->uar_lock[i]);
965 * Once the device is added to the list of memory event
966 * callback, its global MR cache table cannot be expanded
967 * on the fly because of deadlock. If it overflows, lookup
968 * should be done by searching MR list linearly, which is slow.
970 * At this point the device is not added to the memory
971 * event list yet, context is just being created.
973 err = mlx5_mr_btree_init(&sh->share_cache.cache,
974 MLX5_MR_BTREE_CACHE_N * 2,
975 spawn->pci_dev->device.numa_node);
980 mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
981 &sh->share_cache.dereg_mr_cb);
982 mlx5_os_dev_shared_handler_install(sh);
983 sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
984 if (!sh->cnt_id_tbl) {
988 mlx5_flow_aging_init(sh);
989 mlx5_flow_counters_mng_init(sh);
990 mlx5_flow_ipool_create(sh, config);
991 /* Add device to memory callback list. */
992 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
993 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
995 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
996 /* Add context to the global device list. */
997 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
999 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1002 pthread_mutex_destroy(&sh->txpp.mutex);
1003 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1006 mlx5_l3t_destroy(sh->cnt_id_tbl);
1008 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1010 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1011 if (sh->devx_rx_uar)
1012 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1014 mlx5_glue->devx_free_uar(sh->tx_uar);
1016 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1018 claim_zero(mlx5_glue->close_device(sh->ctx));
1019 if (sh->flow_id_pool)
1020 mlx5_flow_id_pool_release(sh->flow_id_pool);
1022 MLX5_ASSERT(err > 0);
1028 * Free shared IB device context. Decrement counter and if zero free
1029 * all allocated resources and close handles.
1032 * Pointer to mlx5_dev_ctx_shared object to free
1035 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1037 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1038 #ifdef RTE_LIBRTE_MLX5_DEBUG
1039 /* Check the object presence in the list. */
1040 struct mlx5_dev_ctx_shared *lctx;
1042 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1047 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1052 MLX5_ASSERT(sh->refcnt);
1053 /* Secondary process should not free the shared context. */
1054 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1057 /* Remove from memory callback device list. */
1058 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1059 LIST_REMOVE(sh, mem_event_cb);
1060 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1061 /* Release created Memory Regions. */
1062 mlx5_mr_release_cache(&sh->share_cache);
1063 /* Remove context from the global device list. */
1064 LIST_REMOVE(sh, next);
1065 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1067 * Ensure there is no async event handler installed.
1068 * Only primary process handles async device events.
1070 mlx5_flow_counters_mng_close(sh);
1071 mlx5_flow_ipool_destroy(sh);
1072 mlx5_os_dev_shared_handler_uninstall(sh);
1073 if (sh->cnt_id_tbl) {
1074 mlx5_l3t_destroy(sh->cnt_id_tbl);
1075 sh->cnt_id_tbl = NULL;
1078 mlx5_glue->devx_free_uar(sh->tx_uar);
1082 claim_zero(mlx5_glue->dealloc_pd(sh->pd));
1084 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1086 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1087 if (sh->devx_rx_uar)
1088 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1090 claim_zero(mlx5_glue->close_device(sh->ctx));
1091 if (sh->flow_id_pool)
1092 mlx5_flow_id_pool_release(sh->flow_id_pool);
1093 pthread_mutex_destroy(&sh->txpp.mutex);
1097 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1101 * Destroy table hash list and all the root entries per domain.
1104 * Pointer to the private device data structure.
1107 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1109 struct mlx5_dev_ctx_shared *sh = priv->sh;
1110 struct mlx5_flow_tbl_data_entry *tbl_data;
1111 union mlx5_flow_tbl_key table_key = {
1119 struct mlx5_hlist_entry *pos;
1123 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1125 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1127 MLX5_ASSERT(tbl_data);
1128 mlx5_hlist_remove(sh->flow_tbls, pos);
1129 mlx5_free(tbl_data);
1131 table_key.direction = 1;
1132 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1134 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1136 MLX5_ASSERT(tbl_data);
1137 mlx5_hlist_remove(sh->flow_tbls, pos);
1138 mlx5_free(tbl_data);
1140 table_key.direction = 0;
1141 table_key.domain = 1;
1142 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64);
1144 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
1146 MLX5_ASSERT(tbl_data);
1147 mlx5_hlist_remove(sh->flow_tbls, pos);
1148 mlx5_free(tbl_data);
1150 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL);
1154 * Initialize flow table hash list and create the root tables entry
1158 * Pointer to the private device data structure.
1161 * Zero on success, positive error code otherwise.
1164 mlx5_alloc_table_hash_list(struct mlx5_priv *priv)
1166 struct mlx5_dev_ctx_shared *sh = priv->sh;
1167 char s[MLX5_HLIST_NAMESIZE];
1171 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1172 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE);
1173 if (!sh->flow_tbls) {
1174 DRV_LOG(ERR, "flow tables with hash creation failed.");
1178 #ifndef HAVE_MLX5DV_DR
1180 * In case we have not DR support, the zero tables should be created
1181 * because DV expect to see them even if they cannot be created by
1184 union mlx5_flow_tbl_key table_key = {
1192 struct mlx5_flow_tbl_data_entry *tbl_data = mlx5_malloc(MLX5_MEM_ZERO,
1193 sizeof(*tbl_data), 0,
1200 tbl_data->entry.key = table_key.v64;
1201 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1204 rte_atomic32_init(&tbl_data->tbl.refcnt);
1205 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1206 table_key.direction = 1;
1207 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1213 tbl_data->entry.key = table_key.v64;
1214 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1217 rte_atomic32_init(&tbl_data->tbl.refcnt);
1218 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1219 table_key.direction = 0;
1220 table_key.domain = 1;
1221 tbl_data = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tbl_data), 0,
1227 tbl_data->entry.key = table_key.v64;
1228 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry);
1231 rte_atomic32_init(&tbl_data->tbl.refcnt);
1232 rte_atomic32_inc(&tbl_data->tbl.refcnt);
1235 mlx5_free_table_hash_list(priv);
1236 #endif /* HAVE_MLX5DV_DR */
1241 * Retrieve integer value from environment variable.
1244 * Environment variable name.
1247 * Integer value, 0 if the variable is not set.
1250 mlx5_getenv_int(const char *name)
1252 const char *val = getenv(name);
1260 * DPDK callback to add udp tunnel port
1263 * A pointer to eth_dev
1264 * @param[in] udp_tunnel
1265 * A pointer to udp tunnel
1268 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1271 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1272 struct rte_eth_udp_tunnel *udp_tunnel)
1274 MLX5_ASSERT(udp_tunnel != NULL);
1275 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1276 udp_tunnel->udp_port == 4789)
1278 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1279 udp_tunnel->udp_port == 4790)
1285 * Initialize process private data structure.
1288 * Pointer to Ethernet device structure.
1291 * 0 on success, a negative errno value otherwise and rte_errno is set.
1294 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1296 struct mlx5_priv *priv = dev->data->dev_private;
1297 struct mlx5_proc_priv *ppriv;
1301 * UAR register table follows the process private structure. BlueFlame
1302 * registers for Tx queues are stored in the table.
1305 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1306 ppriv = mlx5_malloc(MLX5_MEM_RTE, ppriv_size, RTE_CACHE_LINE_SIZE,
1307 dev->device->numa_node);
1312 ppriv->uar_table_sz = ppriv_size;
1313 dev->process_private = ppriv;
1318 * Un-initialize process private data structure.
1321 * Pointer to Ethernet device structure.
1324 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1326 if (!dev->process_private)
1328 mlx5_free(dev->process_private);
1329 dev->process_private = NULL;
1333 * DPDK callback to close the device.
1335 * Destroy all queues and objects, free memory.
1338 * Pointer to Ethernet device structure.
1341 mlx5_dev_close(struct rte_eth_dev *dev)
1343 struct mlx5_priv *priv = dev->data->dev_private;
1347 if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1348 /* Check if process_private released. */
1349 if (!dev->process_private)
1351 mlx5_tx_uar_uninit_secondary(dev);
1352 mlx5_proc_priv_uninit(dev);
1353 rte_eth_dev_release_port(dev);
1358 DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1360 ((priv->sh->ctx != NULL) ?
1361 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1363 * If default mreg copy action is removed at the stop stage,
1364 * the search will return none and nothing will be done anymore.
1366 mlx5_flow_stop_default(dev);
1367 mlx5_traffic_disable(dev);
1369 * If all the flows are already flushed in the device stop stage,
1370 * then this will return directly without any action.
1372 mlx5_flow_list_flush(dev, &priv->flows, true);
1373 mlx5_flow_meter_flush(dev, NULL);
1374 /* Free the intermediate buffers for flow creation. */
1375 mlx5_flow_free_intermediate(dev);
1376 /* Prevent crashes when queues are still in use. */
1377 dev->rx_pkt_burst = removed_rx_burst;
1378 dev->tx_pkt_burst = removed_tx_burst;
1380 /* Disable datapath on secondary process. */
1381 mlx5_mp_os_req_stop_rxtx(dev);
1382 /* Free the eCPRI flex parser resource. */
1383 mlx5_flex_parser_ecpri_release(dev);
1384 if (priv->rxqs != NULL) {
1385 /* XXX race condition if mlx5_rx_burst() is still running. */
1387 for (i = 0; (i != priv->rxqs_n); ++i)
1388 mlx5_rxq_release(dev, i);
1392 if (priv->txqs != NULL) {
1393 /* XXX race condition if mlx5_tx_burst() is still running. */
1395 for (i = 0; (i != priv->txqs_n); ++i)
1396 mlx5_txq_release(dev, i);
1400 mlx5_proc_priv_uninit(dev);
1401 if (priv->mreg_cp_tbl)
1402 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL);
1403 mlx5_mprq_free_mp(dev);
1404 mlx5_os_free_shared_dr(priv);
1405 if (priv->rss_conf.rss_key != NULL)
1406 mlx5_free(priv->rss_conf.rss_key);
1407 if (priv->reta_idx != NULL)
1408 mlx5_free(priv->reta_idx);
1409 if (priv->config.vf)
1410 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev),
1411 dev->data->mac_addrs,
1412 MLX5_MAX_MAC_ADDRESSES, priv->mac_own);
1413 if (priv->nl_socket_route >= 0)
1414 close(priv->nl_socket_route);
1415 if (priv->nl_socket_rdma >= 0)
1416 close(priv->nl_socket_rdma);
1417 if (priv->vmwa_context)
1418 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1419 ret = mlx5_hrxq_verify(dev);
1421 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1422 dev->data->port_id);
1423 ret = mlx5_ind_table_obj_verify(dev);
1425 DRV_LOG(WARNING, "port %u some indirection table still remain",
1426 dev->data->port_id);
1427 ret = mlx5_rxq_obj_verify(dev);
1429 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1430 dev->data->port_id);
1431 ret = mlx5_rxq_verify(dev);
1433 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1434 dev->data->port_id);
1435 ret = mlx5_txq_obj_verify(dev);
1437 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1438 dev->data->port_id);
1439 ret = mlx5_txq_verify(dev);
1441 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1442 dev->data->port_id);
1443 ret = mlx5_flow_verify(dev);
1445 DRV_LOG(WARNING, "port %u some flows still remain",
1446 dev->data->port_id);
1448 * Free the shared context in last turn, because the cleanup
1449 * routines above may use some shared fields, like
1450 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
1451 * ifindex if Netlink fails.
1453 mlx5_free_shared_dev_ctx(priv->sh);
1454 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1458 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1459 struct mlx5_priv *opriv =
1460 rte_eth_devices[port_id].data->dev_private;
1463 opriv->domain_id != priv->domain_id ||
1464 &rte_eth_devices[port_id] == dev)
1470 claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1472 memset(priv, 0, sizeof(*priv));
1473 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1475 * Reset mac_addrs to NULL such that it is not freed as part of
1476 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1477 * it is freed when dev_private is freed.
1479 dev->data->mac_addrs = NULL;
1483 * Verify and store value for device argument.
1486 * Key argument to verify.
1488 * Value associated with key.
1493 * 0 on success, a negative errno value otherwise and rte_errno is set.
1496 mlx5_args_check(const char *key, const char *val, void *opaque)
1498 struct mlx5_dev_config *config = opaque;
1502 /* No-op, port representors are processed in mlx5_dev_spawn(). */
1503 if (!strcmp(MLX5_REPRESENTOR, key))
1506 tmp = strtol(val, NULL, 0);
1509 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1512 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1513 /* Negative values are acceptable for some keys only. */
1515 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1518 mod = tmp >= 0 ? tmp : -tmp;
1519 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1520 config->cqe_comp = !!tmp;
1521 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
1522 config->cqe_pad = !!tmp;
1523 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1524 config->hw_padding = !!tmp;
1525 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1526 config->mprq.enabled = !!tmp;
1527 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1528 config->mprq.stride_num_n = tmp;
1529 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1530 config->mprq.stride_size_n = tmp;
1531 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1532 config->mprq.max_memcpy_len = tmp;
1533 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1534 config->mprq.min_rxqs_num = tmp;
1535 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1536 DRV_LOG(WARNING, "%s: deprecated parameter,"
1537 " converted to txq_inline_max", key);
1538 config->txq_inline_max = tmp;
1539 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1540 config->txq_inline_max = tmp;
1541 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1542 config->txq_inline_min = tmp;
1543 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1544 config->txq_inline_mpw = tmp;
1545 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1546 config->txqs_inline = tmp;
1547 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1548 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1549 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1550 config->mps = !!tmp;
1551 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1552 if (tmp != MLX5_TXDB_CACHED &&
1553 tmp != MLX5_TXDB_NCACHED &&
1554 tmp != MLX5_TXDB_HEURISTIC) {
1555 DRV_LOG(ERR, "invalid Tx doorbell "
1556 "mapping parameter");
1561 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1562 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1563 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1564 DRV_LOG(WARNING, "%s: deprecated parameter,"
1565 " converted to txq_inline_mpw", key);
1566 config->txq_inline_mpw = tmp;
1567 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1568 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1569 } else if (strcmp(MLX5_TX_PP, key) == 0) {
1571 DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1575 config->tx_pp = tmp;
1576 } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1577 config->tx_skew = tmp;
1578 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1579 config->rx_vec_en = !!tmp;
1580 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1581 config->l3_vxlan_en = !!tmp;
1582 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1583 config->vf_nl_en = !!tmp;
1584 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1585 config->dv_esw_en = !!tmp;
1586 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1587 config->dv_flow_en = !!tmp;
1588 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1589 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1590 tmp != MLX5_XMETA_MODE_META16 &&
1591 tmp != MLX5_XMETA_MODE_META32) {
1592 DRV_LOG(ERR, "invalid extensive "
1593 "metadata parameter");
1597 config->dv_xmeta_en = tmp;
1598 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1599 config->lacp_by_user = !!tmp;
1600 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1601 config->mr_ext_memseg_en = !!tmp;
1602 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1603 config->max_dump_files_num = tmp;
1604 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1605 config->lro.timeout = tmp;
1606 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1607 DRV_LOG(DEBUG, "class argument is %s.", val);
1608 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1609 config->log_hp_size = tmp;
1610 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1611 if (tmp != MLX5_RCM_NONE &&
1612 tmp != MLX5_RCM_LIGHT &&
1613 tmp != MLX5_RCM_AGGR) {
1614 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1618 config->reclaim_mode = tmp;
1619 } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1620 config->sys_mem_en = !!tmp;
1621 } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1622 config->decap_en = !!tmp;
1624 DRV_LOG(WARNING, "%s: unknown parameter", key);
1632 * Parse device parameters.
1635 * Pointer to device configuration structure.
1637 * Device arguments structure.
1640 * 0 on success, a negative errno value otherwise and rte_errno is set.
1643 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1645 const char **params = (const char *[]){
1646 MLX5_RXQ_CQE_COMP_EN,
1647 MLX5_RXQ_CQE_PAD_EN,
1648 MLX5_RXQ_PKT_PAD_EN,
1650 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1651 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1652 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1655 MLX5_TXQ_INLINE_MIN,
1656 MLX5_TXQ_INLINE_MAX,
1657 MLX5_TXQ_INLINE_MPW,
1658 MLX5_TXQS_MIN_INLINE,
1661 MLX5_TXQ_MPW_HDR_DSEG_EN,
1662 MLX5_TXQ_MAX_INLINE_LEN,
1674 MLX5_MR_EXT_MEMSEG_EN,
1676 MLX5_MAX_DUMP_FILES_NUM,
1677 MLX5_LRO_TIMEOUT_USEC,
1678 MLX5_CLASS_ARG_NAME,
1685 struct rte_kvargs *kvlist;
1689 if (devargs == NULL)
1691 /* Following UGLY cast is done to pass checkpatch. */
1692 kvlist = rte_kvargs_parse(devargs->args, params);
1693 if (kvlist == NULL) {
1697 /* Process parameters. */
1698 for (i = 0; (params[i] != NULL); ++i) {
1699 if (rte_kvargs_count(kvlist, params[i])) {
1700 ret = rte_kvargs_process(kvlist, params[i],
1701 mlx5_args_check, config);
1704 rte_kvargs_free(kvlist);
1709 rte_kvargs_free(kvlist);
1714 * Configures the minimal amount of data to inline into WQE
1715 * while sending packets.
1717 * - the txq_inline_min has the maximal priority, if this
1718 * key is specified in devargs
1719 * - if DevX is enabled the inline mode is queried from the
1720 * device (HCA attributes and NIC vport context if needed).
1721 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
1722 * and none (0 bytes) for other NICs
1725 * Verbs device parameters (name, port, switch_info) to spawn.
1727 * Device configuration parameters.
1730 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
1731 struct mlx5_dev_config *config)
1733 if (config->txq_inline_min != MLX5_ARG_UNSET) {
1734 /* Application defines size of inlined data explicitly. */
1735 switch (spawn->pci_dev->id.device_id) {
1736 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1737 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1738 if (config->txq_inline_min <
1739 (int)MLX5_INLINE_HSIZE_L2) {
1741 "txq_inline_mix aligned to minimal"
1742 " ConnectX-4 required value %d",
1743 (int)MLX5_INLINE_HSIZE_L2);
1744 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1750 if (config->hca_attr.eth_net_offloads) {
1751 /* We have DevX enabled, inline mode queried successfully. */
1752 switch (config->hca_attr.wqe_inline_mode) {
1753 case MLX5_CAP_INLINE_MODE_L2:
1754 /* outer L2 header must be inlined. */
1755 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1757 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
1758 /* No inline data are required by NIC. */
1759 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1760 config->hw_vlan_insert =
1761 config->hca_attr.wqe_vlan_insert;
1762 DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
1764 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
1765 /* inline mode is defined by NIC vport context. */
1766 if (!config->hca_attr.eth_virt)
1768 switch (config->hca_attr.vport_inline_mode) {
1769 case MLX5_INLINE_MODE_NONE:
1770 config->txq_inline_min =
1771 MLX5_INLINE_HSIZE_NONE;
1773 case MLX5_INLINE_MODE_L2:
1774 config->txq_inline_min =
1775 MLX5_INLINE_HSIZE_L2;
1777 case MLX5_INLINE_MODE_IP:
1778 config->txq_inline_min =
1779 MLX5_INLINE_HSIZE_L3;
1781 case MLX5_INLINE_MODE_TCP_UDP:
1782 config->txq_inline_min =
1783 MLX5_INLINE_HSIZE_L4;
1785 case MLX5_INLINE_MODE_INNER_L2:
1786 config->txq_inline_min =
1787 MLX5_INLINE_HSIZE_INNER_L2;
1789 case MLX5_INLINE_MODE_INNER_IP:
1790 config->txq_inline_min =
1791 MLX5_INLINE_HSIZE_INNER_L3;
1793 case MLX5_INLINE_MODE_INNER_TCP_UDP:
1794 config->txq_inline_min =
1795 MLX5_INLINE_HSIZE_INNER_L4;
1801 * We get here if we are unable to deduce
1802 * inline data size with DevX. Try PCI ID
1803 * to determine old NICs.
1805 switch (spawn->pci_dev->id.device_id) {
1806 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
1807 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1808 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
1809 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1810 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
1811 config->hw_vlan_insert = 0;
1813 case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
1814 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1815 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
1816 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1818 * These NICs support VLAN insertion from WQE and
1819 * report the wqe_vlan_insert flag. But there is the bug
1820 * and PFC control may be broken, so disable feature.
1822 config->hw_vlan_insert = 0;
1823 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1826 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
1830 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
1834 * Configures the metadata mask fields in the shared context.
1837 * Pointer to Ethernet device.
1840 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
1842 struct mlx5_priv *priv = dev->data->dev_private;
1843 struct mlx5_dev_ctx_shared *sh = priv->sh;
1844 uint32_t meta, mark, reg_c0;
1846 reg_c0 = ~priv->vport_meta_mask;
1847 switch (priv->config.dv_xmeta_en) {
1848 case MLX5_XMETA_MODE_LEGACY:
1850 mark = MLX5_FLOW_MARK_MASK;
1852 case MLX5_XMETA_MODE_META16:
1853 meta = reg_c0 >> rte_bsf32(reg_c0);
1854 mark = MLX5_FLOW_MARK_MASK;
1856 case MLX5_XMETA_MODE_META32:
1858 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
1866 if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
1867 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
1868 sh->dv_mark_mask, mark);
1870 sh->dv_mark_mask = mark;
1871 if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
1872 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
1873 sh->dv_meta_mask, meta);
1875 sh->dv_meta_mask = meta;
1876 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
1877 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
1878 sh->dv_meta_mask, reg_c0);
1880 sh->dv_regc0_mask = reg_c0;
1881 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
1882 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
1883 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
1884 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
1888 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
1890 static const char *const dynf_names[] = {
1891 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
1892 RTE_MBUF_DYNFLAG_METADATA_NAME,
1893 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
1897 if (n < RTE_DIM(dynf_names))
1899 for (i = 0; i < RTE_DIM(dynf_names); i++) {
1900 if (names[i] == NULL)
1902 strcpy(names[i], dynf_names[i]);
1904 return RTE_DIM(dynf_names);
1908 * Comparison callback to sort device data.
1910 * This is meant to be used with qsort().
1913 * Pointer to pointer to first data object.
1915 * Pointer to pointer to second data object.
1918 * 0 if both objects are equal, less than 0 if the first argument is less
1919 * than the second, greater than 0 otherwise.
1922 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
1923 struct mlx5_dev_config *config)
1925 struct mlx5_dev_ctx_shared *sh = priv->sh;
1926 struct mlx5_dev_config *sh_conf = NULL;
1930 /* Nothing to compare for the single/first device. */
1931 if (sh->refcnt == 1)
1933 /* Find the device with shared context. */
1934 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1935 struct mlx5_priv *opriv =
1936 rte_eth_devices[port_id].data->dev_private;
1938 if (opriv && opriv != priv && opriv->sh == sh) {
1939 sh_conf = &opriv->config;
1945 if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
1946 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
1947 " for shared %s context", sh->ibdev_name);
1951 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
1952 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
1953 " for shared %s context", sh->ibdev_name);
1961 * Look for the ethernet device belonging to mlx5 driver.
1963 * @param[in] port_id
1964 * port_id to start looking for device.
1965 * @param[in] pci_dev
1966 * Pointer to the hint PCI device. When device is being probed
1967 * the its siblings (master and preceding representors might
1968 * not have assigned driver yet (because the mlx5_os_pci_probe()
1969 * is not completed yet, for this case match on hint PCI
1970 * device may be used to detect sibling device.
1973 * port_id of found device, RTE_MAX_ETHPORT if not found.
1976 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
1978 while (port_id < RTE_MAX_ETHPORTS) {
1979 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
1981 if (dev->state != RTE_ETH_DEV_UNUSED &&
1983 (dev->device == &pci_dev->device ||
1984 (dev->device->driver &&
1985 dev->device->driver->name &&
1986 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME))))
1990 if (port_id >= RTE_MAX_ETHPORTS)
1991 return RTE_MAX_ETHPORTS;
1996 * DPDK callback to remove a PCI device.
1998 * This function removes all Ethernet devices belong to a given PCI device.
2000 * @param[in] pci_dev
2001 * Pointer to the PCI device.
2004 * 0 on success, the function cannot fail.
2007 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2011 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2013 * mlx5_dev_close() is not registered to secondary process,
2014 * call the close function explicitly for secondary process.
2016 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2017 mlx5_dev_close(&rte_eth_devices[port_id]);
2019 rte_eth_dev_close(port_id);
2024 static const struct rte_pci_id mlx5_pci_id_map[] = {
2026 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2027 PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2030 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2031 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2034 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2035 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2038 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2039 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2042 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2043 PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2046 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2047 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2050 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2051 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2054 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2055 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2058 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2059 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2062 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2063 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2066 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2067 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2070 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2071 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2074 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2075 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2078 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2079 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF)
2082 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2083 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2086 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2087 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2094 static struct mlx5_pci_driver mlx5_driver = {
2095 .driver_class = MLX5_CLASS_NET,
2098 .name = MLX5_DRIVER_NAME,
2100 .id_table = mlx5_pci_id_map,
2101 .probe = mlx5_os_pci_probe,
2102 .remove = mlx5_pci_remove,
2103 .dma_map = mlx5_dma_map,
2104 .dma_unmap = mlx5_dma_unmap,
2105 .drv_flags = PCI_DRV_FLAGS,
2109 /* Initialize driver log type. */
2110 RTE_LOG_REGISTER(mlx5_logtype, pmd.net.mlx5, NOTICE)
2113 * Driver initialization routine.
2115 RTE_INIT(rte_mlx5_pmd_init)
2118 /* Build the static tables for Verbs conversion. */
2119 mlx5_set_ptype_table();
2120 mlx5_set_cksum_table();
2121 mlx5_set_swp_types_table();
2123 mlx5_pci_driver_register(&mlx5_driver);
2126 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2127 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2128 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");