drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Shared memory between primary and secondary processes. */
 179 struct mlx5_shared_data *mlx5_shared_data;
 180
 181 /** Driver-specific log messages type. */
 182 int mlx5_logtype;
 183
 184 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 185                                                 LIST_HEAD_INITIALIZER();
 186 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 187 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 188 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 189         [MLX5_IPOOL_DECAP_ENCAP] = {
 190                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 191                 .trunk_size = 64,
 192                 .grow_trunk = 3,
 193                 .grow_shift = 2,
 194                 .need_lock = 1,
 195                 .release_mem_en = 1,
 196                 .malloc = mlx5_malloc,
 197                 .free = mlx5_free,
 198                 .type = "mlx5_encap_decap_ipool",
 199         },
 200         [MLX5_IPOOL_PUSH_VLAN] = {
 201                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 202                 .trunk_size = 64,
 203                 .grow_trunk = 3,
 204                 .grow_shift = 2,
 205                 .need_lock = 1,
 206                 .release_mem_en = 1,
 207                 .malloc = mlx5_malloc,
 208                 .free = mlx5_free,
 209                 .type = "mlx5_push_vlan_ipool",
 210         },
 211         [MLX5_IPOOL_TAG] = {
 212                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 213                 .trunk_size = 64,
 214                 .grow_trunk = 3,
 215                 .grow_shift = 2,
 216                 .need_lock = 1,
 217                 .release_mem_en = 1,
 218                 .malloc = mlx5_malloc,
 219                 .free = mlx5_free,
 220                 .type = "mlx5_tag_ipool",
 221         },
 222         [MLX5_IPOOL_PORT_ID] = {
 223                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 224                 .trunk_size = 64,
 225                 .grow_trunk = 3,
 226                 .grow_shift = 2,
 227                 .need_lock = 1,
 228                 .release_mem_en = 1,
 229                 .malloc = mlx5_malloc,
 230                 .free = mlx5_free,
 231                 .type = "mlx5_port_id_ipool",
 232         },
 233         [MLX5_IPOOL_JUMP] = {
 234                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 235                 .trunk_size = 64,
 236                 .grow_trunk = 3,
 237                 .grow_shift = 2,
 238                 .need_lock = 1,
 239                 .release_mem_en = 1,
 240                 .malloc = mlx5_malloc,
 241                 .free = mlx5_free,
 242                 .type = "mlx5_jump_ipool",
 243         },
 244         [MLX5_IPOOL_SAMPLE] = {
 245                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 246                 .trunk_size = 64,
 247                 .grow_trunk = 3,
 248                 .grow_shift = 2,
 249                 .need_lock = 1,
 250                 .release_mem_en = 1,
 251                 .malloc = mlx5_malloc,
 252                 .free = mlx5_free,
 253                 .type = "mlx5_sample_ipool",
 254         },
 255         [MLX5_IPOOL_DEST_ARRAY] = {
 256                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 257                 .trunk_size = 64,
 258                 .grow_trunk = 3,
 259                 .grow_shift = 2,
 260                 .need_lock = 1,
 261                 .release_mem_en = 1,
 262                 .malloc = mlx5_malloc,
 263                 .free = mlx5_free,
 264                 .type = "mlx5_dest_array_ipool",
 265         },
 266         [MLX5_IPOOL_TUNNEL_ID] = {
 267                 .size = sizeof(struct mlx5_flow_tunnel),
 268                 .trunk_size = MLX5_MAX_TUNNELS,
 269                 .need_lock = 1,
 270                 .release_mem_en = 1,
 271                 .type = "mlx5_tunnel_offload",
 272         },
 273         [MLX5_IPOOL_TNL_TBL_ID] = {
 274                 .size = 0,
 275                 .need_lock = 1,
 276                 .type = "mlx5_flow_tnl_tbl_ipool",
 277         },
 278 #endif
 279         [MLX5_IPOOL_MTR] = {
 280                 /**
 281                  * The ipool index should grow continually from small to big,
 282                  * for meter idx, so not set grow_trunk to avoid meter index
 283                  * not jump continually.
 284                  */
 285                 .size = sizeof(struct mlx5_legacy_flow_meter),
 286                 .trunk_size = 64,
 287                 .need_lock = 1,
 288                 .release_mem_en = 1,
 289                 .malloc = mlx5_malloc,
 290                 .free = mlx5_free,
 291                 .type = "mlx5_meter_ipool",
 292         },
 293         [MLX5_IPOOL_MCP] = {
 294                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 295                 .trunk_size = 64,
 296                 .grow_trunk = 3,
 297                 .grow_shift = 2,
 298                 .need_lock = 1,
 299                 .release_mem_en = 1,
 300                 .malloc = mlx5_malloc,
 301                 .free = mlx5_free,
 302                 .type = "mlx5_mcp_ipool",
 303         },
 304         [MLX5_IPOOL_HRXQ] = {
 305                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 306                 .trunk_size = 64,
 307                 .grow_trunk = 3,
 308                 .grow_shift = 2,
 309                 .need_lock = 1,
 310                 .release_mem_en = 1,
 311                 .malloc = mlx5_malloc,
 312                 .free = mlx5_free,
 313                 .type = "mlx5_hrxq_ipool",
 314         },
 315         [MLX5_IPOOL_MLX5_FLOW] = {
 316                 /*
 317                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 318                  * It set in run time according to PCI function configuration.
 319                  */
 320                 .size = 0,
 321                 .trunk_size = 64,
 322                 .grow_trunk = 3,
 323                 .grow_shift = 2,
 324                 .need_lock = 1,
 325                 .release_mem_en = 1,
 326                 .malloc = mlx5_malloc,
 327                 .free = mlx5_free,
 328                 .type = "mlx5_flow_handle_ipool",
 329         },
 330         [MLX5_IPOOL_RTE_FLOW] = {
 331                 .size = sizeof(struct rte_flow),
 332                 .trunk_size = 4096,
 333                 .need_lock = 1,
 334                 .release_mem_en = 1,
 335                 .malloc = mlx5_malloc,
 336                 .free = mlx5_free,
 337                 .type = "rte_flow_ipool",
 338         },
 339         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 340                 .size = 0,
 341                 .need_lock = 1,
 342                 .type = "mlx5_flow_rss_id_ipool",
 343         },
 344         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 345                 .size = sizeof(struct mlx5_shared_action_rss),
 346                 .trunk_size = 64,
 347                 .grow_trunk = 3,
 348                 .grow_shift = 2,
 349                 .need_lock = 1,
 350                 .release_mem_en = 1,
 351                 .malloc = mlx5_malloc,
 352                 .free = mlx5_free,
 353                 .type = "mlx5_shared_action_rss",
 354         },
 355         [MLX5_IPOOL_MTR_POLICY] = {
 356                 /**
 357                  * The ipool index should grow continually from small to big,
 358                  * for policy idx, so not set grow_trunk to avoid policy index
 359                  * not jump continually.
 360                  */
 361                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 362                 .trunk_size = 64,
 363                 .need_lock = 1,
 364                 .release_mem_en = 1,
 365                 .malloc = mlx5_malloc,
 366                 .free = mlx5_free,
 367                 .type = "mlx5_meter_policy_ipool",
 368         },
 369 };
 370
 371
 372 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 373 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 374
 375 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096
 376
 377 /**
 378  * Decide whether representor ID is a HPF(host PF) port on BF2.
 379  *
 380  * @param dev
 381  *   Pointer to Ethernet device structure.
 382  *
 383  * @return
 384  *   Non-zero if HPF, otherwise 0.
 385  */
 386 bool
 387 mlx5_is_hpf(struct rte_eth_dev *dev)
 388 {
 389         struct mlx5_priv *priv = dev->data->dev_private;
 390         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 391         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 392
 393         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 394                MLX5_REPRESENTOR_REPR(-1) == repr;
 395 }
 396
 397 /**
 398  * Initialize the ASO aging management structure.
 399  *
 400  * @param[in] sh
 401  *   Pointer to mlx5_dev_ctx_shared object to free
 402  *
 403  * @return
 404  *   0 on success, a negative errno value otherwise and rte_errno is set.
 405  */
 406 int
 407 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 408 {
 409         int err;
 410
 411         if (sh->aso_age_mng)
 412                 return 0;
 413         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 414                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 415         if (!sh->aso_age_mng) {
 416                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 417                 rte_errno = ENOMEM;
 418                 return -ENOMEM;
 419         }
 420         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 421         if (err) {
 422                 mlx5_free(sh->aso_age_mng);
 423                 return -1;
 424         }
 425         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 426         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 427         LIST_INIT(&sh->aso_age_mng->free);
 428         return 0;
 429 }
 430
 431 /**
 432  * Close and release all the resources of the ASO aging management structure.
 433  *
 434  * @param[in] sh
 435  *   Pointer to mlx5_dev_ctx_shared object to free.
 436  */
 437 static void
 438 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 439 {
 440         int i, j;
 441
 442         mlx5_aso_flow_hit_queue_poll_stop(sh);
 443         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 444         if (sh->aso_age_mng->pools) {
 445                 struct mlx5_aso_age_pool *pool;
 446
 447                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 448                         pool = sh->aso_age_mng->pools[i];
 449                         claim_zero(mlx5_devx_cmd_destroy
 450                                                 (pool->flow_hit_aso_obj));
 451                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 452                                 if (pool->actions[j].dr_action)
 453                                         claim_zero
 454                                             (mlx5_flow_os_destroy_flow_action
 455                                               (pool->actions[j].dr_action));
 456                         mlx5_free(pool);
 457                 }
 458                 mlx5_free(sh->aso_age_mng->pools);
 459         }
 460         mlx5_free(sh->aso_age_mng);
 461 }
 462
 463 /**
 464  * Initialize the shared aging list information per port.
 465  *
 466  * @param[in] sh
 467  *   Pointer to mlx5_dev_ctx_shared object.
 468  */
 469 static void
 470 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 471 {
 472         uint32_t i;
 473         struct mlx5_age_info *age_info;
 474
 475         for (i = 0; i < sh->max_port; i++) {
 476                 age_info = &sh->port[i].age_info;
 477                 age_info->flags = 0;
 478                 TAILQ_INIT(&age_info->aged_counters);
 479                 LIST_INIT(&age_info->aged_aso);
 480                 rte_spinlock_init(&age_info->aged_sl);
 481                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 482         }
 483 }
 484
 485 /**
 486  * Initialize the counters management structure.
 487  *
 488  * @param[in] sh
 489  *   Pointer to mlx5_dev_ctx_shared object to free
 490  */
 491 static void
 492 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 493 {
 494         int i;
 495
 496         memset(&sh->cmng, 0, sizeof(sh->cmng));
 497         TAILQ_INIT(&sh->cmng.flow_counters);
 498         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 499         sh->cmng.max_id = -1;
 500         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 501         rte_spinlock_init(&sh->cmng.pool_update_sl);
 502         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 503                 TAILQ_INIT(&sh->cmng.counters[i]);
 504                 rte_spinlock_init(&sh->cmng.csl[i]);
 505         }
 506 }
 507
 508 /**
 509  * Destroy all the resources allocated for a counter memory management.
 510  *
 511  * @param[in] mng
 512  *   Pointer to the memory management structure.
 513  */
 514 static void
 515 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 516 {
 517         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 518
 519         LIST_REMOVE(mng, next);
 520         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 521         claim_zero(mlx5_os_umem_dereg(mng->umem));
 522         mlx5_free(mem);
 523 }
 524
 525 /**
 526  * Close and release all the resources of the counters management.
 527  *
 528  * @param[in] sh
 529  *   Pointer to mlx5_dev_ctx_shared object to free.
 530  */
 531 static void
 532 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 533 {
 534         struct mlx5_counter_stats_mem_mng *mng;
 535         int i, j;
 536         int retries = 1024;
 537
 538         rte_errno = 0;
 539         while (--retries) {
 540                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 541                 if (rte_errno != EINPROGRESS)
 542                         break;
 543                 rte_pause();
 544         }
 545
 546         if (sh->cmng.pools) {
 547                 struct mlx5_flow_counter_pool *pool;
 548                 uint16_t n_valid = sh->cmng.n_valid;
 549                 bool fallback = sh->cmng.counter_fallback;
 550
 551                 for (i = 0; i < n_valid; ++i) {
 552                         pool = sh->cmng.pools[i];
 553                         if (!fallback && pool->min_dcs)
 554                                 claim_zero(mlx5_devx_cmd_destroy
 555                                                                (pool->min_dcs));
 556                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 557                                 struct mlx5_flow_counter *cnt =
 558                                                 MLX5_POOL_GET_CNT(pool, j);
 559
 560                                 if (cnt->action)
 561                                         claim_zero
 562                                          (mlx5_flow_os_destroy_flow_action
 563                                           (cnt->action));
 564                                 if (fallback && MLX5_POOL_GET_CNT
 565                                     (pool, j)->dcs_when_free)
 566                                         claim_zero(mlx5_devx_cmd_destroy
 567                                                    (cnt->dcs_when_free));
 568                         }
 569                         mlx5_free(pool);
 570                 }
 571                 mlx5_free(sh->cmng.pools);
 572         }
 573         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 574         while (mng) {
 575                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 576                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 577         }
 578         memset(&sh->cmng, 0, sizeof(sh->cmng));
 579 }
 580
 581 /**
 582  * Initialize the aso flow meters management structure.
 583  *
 584  * @param[in] sh
 585  *   Pointer to mlx5_dev_ctx_shared object to free
 586  */
 587 int
 588 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 589 {
 590         if (!sh->mtrmng) {
 591                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 592                         sizeof(*sh->mtrmng),
 593                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 594                 if (!sh->mtrmng) {
 595                         DRV_LOG(ERR,
 596                         "meter management allocation was failed.");
 597                         rte_errno = ENOMEM;
 598                         return -ENOMEM;
 599                 }
 600                 if (sh->meter_aso_en) {
 601                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 602                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 603                         sh->mtrmng->policy_idx_tbl =
 604                                 mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
 605                 }
 606                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 607         }
 608         return 0;
 609 }
 610
 611 /**
 612  * Close and release all the resources of
 613  * the ASO flow meter management structure.
 614  *
 615  * @param[in] sh
 616  *   Pointer to mlx5_dev_ctx_shared object to free.
 617  */
 618 static void
 619 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 620 {
 621         struct mlx5_aso_mtr_pool *mtr_pool;
 622         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 623         uint32_t idx;
 624 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 625         struct mlx5_aso_mtr *aso_mtr;
 626         int i;
 627 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 628
 629         if (sh->meter_aso_en) {
 630                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 631                 idx = mtrmng->pools_mng.n_valid;
 632                 while (idx--) {
 633                         mtr_pool = mtrmng->pools_mng.pools[idx];
 634 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 635                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 636                                 aso_mtr = &mtr_pool->mtrs[i];
 637                                 if (aso_mtr->fm.meter_action)
 638                                         claim_zero
 639                                         (mlx5_glue->destroy_flow_action
 640                                         (aso_mtr->fm.meter_action));
 641                         }
 642 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 643                         claim_zero(mlx5_devx_cmd_destroy
 644                                                 (mtr_pool->devx_obj));
 645                         mtrmng->pools_mng.n_valid--;
 646                         mlx5_free(mtr_pool);
 647                 }
 648                 mlx5_free(sh->mtrmng->pools_mng.pools);
 649         }
 650         mlx5_free(sh->mtrmng);
 651         sh->mtrmng = NULL;
 652 }
 653
 654 /* Send FLOW_AGED event if needed. */
 655 void
 656 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 657 {
 658         struct mlx5_age_info *age_info;
 659         uint32_t i;
 660
 661         for (i = 0; i < sh->max_port; i++) {
 662                 age_info = &sh->port[i].age_info;
 663                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 664                         continue;
 665                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 666                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 667                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 668                         rte_eth_dev_callback_process
 669                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 670                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 671                 }
 672         }
 673 }
 674
 675 /*
 676  * Initialize the ASO connection tracking structure.
 677  *
 678  * @param[in] sh
 679  *   Pointer to mlx5_dev_ctx_shared object.
 680  *
 681  * @return
 682  *   0 on success, a negative errno value otherwise and rte_errno is set.
 683  */
 684 int
 685 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 686 {
 687         int err;
 688
 689         if (sh->ct_mng)
 690                 return 0;
 691         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 692                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 693         if (!sh->ct_mng) {
 694                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 695                 rte_errno = ENOMEM;
 696                 return -rte_errno;
 697         }
 698         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 699         if (err) {
 700                 mlx5_free(sh->ct_mng);
 701                 /* rte_errno should be extracted from the failure. */
 702                 rte_errno = EINVAL;
 703                 return -rte_errno;
 704         }
 705         rte_spinlock_init(&sh->ct_mng->ct_sl);
 706         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 707         LIST_INIT(&sh->ct_mng->free_cts);
 708         return 0;
 709 }
 710
 711 /*
 712  * Close and release all the resources of the
 713  * ASO connection tracking management structure.
 714  *
 715  * @param[in] sh
 716  *   Pointer to mlx5_dev_ctx_shared object to free.
 717  */
 718 static void
 719 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 720 {
 721         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 722         struct mlx5_aso_ct_pool *ct_pool;
 723         struct mlx5_aso_ct_action *ct;
 724         uint32_t idx;
 725         uint32_t val;
 726         uint32_t cnt;
 727         int i;
 728
 729         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 730         idx = mng->next;
 731         while (idx--) {
 732                 cnt = 0;
 733                 ct_pool = mng->pools[idx];
 734                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 735                         ct = &ct_pool->actions[i];
 736                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 737                                                  __ATOMIC_RELAXED);
 738                         MLX5_ASSERT(val == 1);
 739                         if (val > 1)
 740                                 cnt++;
 741 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 742                         if (ct->dr_action_orig)
 743                                 claim_zero(mlx5_glue->destroy_flow_action
 744                                                         (ct->dr_action_orig));
 745                         if (ct->dr_action_rply)
 746                                 claim_zero(mlx5_glue->destroy_flow_action
 747                                                         (ct->dr_action_rply));
 748 #endif
 749                 }
 750                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 751                 if (cnt) {
 752                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 753                                 cnt, i);
 754                 }
 755                 mlx5_free(ct_pool);
 756                 /* in case of failure. */
 757                 mng->next--;
 758         }
 759         mlx5_free(mng->pools);
 760         mlx5_free(mng);
 761         /* Management structure must be cleared to 0s during allocation. */
 762         sh->ct_mng = NULL;
 763 }
 764
 765 /**
 766  * Initialize the flow resources' indexed mempool.
 767  *
 768  * @param[in] sh
 769  *   Pointer to mlx5_dev_ctx_shared object.
 770  * @param[in] config
 771  *   Pointer to user dev config.
 772  */
 773 static void
 774 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 775                        const struct mlx5_dev_config *config)
 776 {
 777         uint8_t i;
 778         struct mlx5_indexed_pool_config cfg;
 779
 780         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 781                 cfg = mlx5_ipool_cfg[i];
 782                 switch (i) {
 783                 default:
 784                         break;
 785                 /*
 786                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 787                  * according to PCI function flow configuration.
 788                  */
 789                 case MLX5_IPOOL_MLX5_FLOW:
 790                         cfg.size = config->dv_flow_en ?
 791                                 sizeof(struct mlx5_flow_handle) :
 792                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 793                         break;
 794                 }
 795                 if (config->reclaim_mode)
 796                         cfg.release_mem_en = 1;
 797                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 798         }
 799 }
 800
 801 /**
 802  * Release the flow resources' indexed mempool.
 803  *
 804  * @param[in] sh
 805  *   Pointer to mlx5_dev_ctx_shared object.
 806  */
 807 static void
 808 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 809 {
 810         uint8_t i;
 811
 812         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 813                 mlx5_ipool_destroy(sh->ipool[i]);
 814 }
 815
 816 /*
 817  * Check if dynamic flex parser for eCPRI already exists.
 818  *
 819  * @param dev
 820  *   Pointer to Ethernet device structure.
 821  *
 822  * @return
 823  *   true on exists, false on not.
 824  */
 825 bool
 826 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 827 {
 828         struct mlx5_priv *priv = dev->data->dev_private;
 829         struct mlx5_flex_parser_profiles *prf =
 830                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 831
 832         return !!prf->obj;
 833 }
 834
 835 /*
 836  * Allocation of a flex parser for eCPRI. Once created, this parser related
 837  * resources will be held until the device is closed.
 838  *
 839  * @param dev
 840  *   Pointer to Ethernet device structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 int
 846 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 847 {
 848         struct mlx5_priv *priv = dev->data->dev_private;
 849         struct mlx5_flex_parser_profiles *prf =
 850                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 851         struct mlx5_devx_graph_node_attr node = {
 852                 .modify_field_select = 0,
 853         };
 854         uint32_t ids[8];
 855         int ret;
 856
 857         if (!priv->config.hca_attr.parse_graph_flex_node) {
 858                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 859                         "for device %s.", priv->dev_data->name);
 860                 return -ENOTSUP;
 861         }
 862         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 863         /* 8 bytes now: 4B common header + 4B message body header. */
 864         node.header_length_base_value = 0x8;
 865         /* After MAC layer: Ether / VLAN. */
 866         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 867         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 868         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 869         /* Sample #0: type in common header. */
 870         node.sample[0].flow_match_sample_en = 1;
 871         /* Fixed offset. */
 872         node.sample[0].flow_match_sample_offset_mode = 0x0;
 873         /* Only the 2nd byte will be used. */
 874         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 875         /* Sample #1: message payload. */
 876         node.sample[1].flow_match_sample_en = 1;
 877         /* Fixed offset. */
 878         node.sample[1].flow_match_sample_offset_mode = 0x0;
 879         /*
 880          * Only the first two bytes will be used right now, and its offset will
 881          * start after the common header that with the length of a DW(u32).
 882          */
 883         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 884         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 885         if (!prf->obj) {
 886                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 887                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 888         }
 889         prf->num = 2;
 890         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 891         if (ret) {
 892                 DRV_LOG(ERR, "Failed to query sample IDs.");
 893                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 894         }
 895         prf->offset[0] = 0x0;
 896         prf->offset[1] = sizeof(uint32_t);
 897         prf->ids[0] = ids[0];
 898         prf->ids[1] = ids[1];
 899         return 0;
 900 }
 901
 902 /*
 903  * Destroy the flex parser node, including the parser itself, input / output
 904  * arcs and DW samples. Resources could be reused then.
 905  *
 906  * @param dev
 907  *   Pointer to Ethernet device structure.
 908  */
 909 static void
 910 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 911 {
 912         struct mlx5_priv *priv = dev->data->dev_private;
 913         struct mlx5_flex_parser_profiles *prf =
 914                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 915
 916         if (prf->obj)
 917                 mlx5_devx_cmd_destroy(prf->obj);
 918         prf->obj = NULL;
 919 }
 920
 921 /*
 922  * Allocate Rx and Tx UARs in robust fashion.
 923  * This routine handles the following UAR allocation issues:
 924  *
 925  *  - tries to allocate the UAR with the most appropriate memory
 926  *    mapping type from the ones supported by the host
 927  *
 928  *  - tries to allocate the UAR with non-NULL base address
 929  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 930  *    UAR base address if UAR was not the first object in the UAR page.
 931  *    It caused the PMD failure and we should try to get another UAR
 932  *    till we get the first one with non-NULL base address returned.
 933  */
 934 static int
 935 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 936                      const struct mlx5_dev_config *config)
 937 {
 938         uint32_t uar_mapping, retry;
 939         int err = 0;
 940         void *base_addr;
 941
 942         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 943 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 944                 /* Control the mapping type according to the settings. */
 945                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 946                               MLX5DV_UAR_ALLOC_TYPE_NC :
 947                               MLX5DV_UAR_ALLOC_TYPE_BF;
 948 #else
 949                 RTE_SET_USED(config);
 950                 /*
 951                  * It seems we have no way to control the memory mapping type
 952                  * for the UAR, the default "Write-Combining" type is supposed.
 953                  * The UAR initialization on queue creation queries the
 954                  * actual mapping type done by Verbs/kernel and setups the
 955                  * PMD datapath accordingly.
 956                  */
 957                 uar_mapping = 0;
 958 #endif
 959                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 960 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 961                 if (!sh->tx_uar &&
 962                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 963                         if (config->dbnc == MLX5_TXDB_CACHED ||
 964                             config->dbnc == MLX5_TXDB_HEURISTIC)
 965                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 966                                                  "is not supported by DevX");
 967                         /*
 968                          * In some environments like virtual machine
 969                          * the Write Combining mapped might be not supported
 970                          * and UAR allocation fails. We try "Non-Cached"
 971                          * mapping for the case. The tx_burst routines take
 972                          * the UAR mapping type into account on UAR setup
 973                          * on queue creation.
 974                          */
 975                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 976                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 977                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 978                                                         (sh->ctx, uar_mapping);
 979                 } else if (!sh->tx_uar &&
 980                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 981                         if (config->dbnc == MLX5_TXDB_NCACHED)
 982                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 983                                                  "is not supported by DevX");
 984                         /*
 985                          * If Verbs/kernel does not support "Non-Cached"
 986                          * try the "Write-Combining".
 987                          */
 988                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 989                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 990                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 991                                                         (sh->ctx, uar_mapping);
 992                 }
 993 #endif
 994                 if (!sh->tx_uar) {
 995                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
 996                         err = ENOMEM;
 997                         goto exit;
 998                 }
 999                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1000                 if (base_addr)
1001                         break;
1002                 /*
1003                  * The UARs are allocated by rdma_core within the
1004                  * IB device context, on context closure all UARs
1005                  * will be freed, should be no memory/object leakage.
1006                  */
1007                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1008                 sh->tx_uar = NULL;
1009         }
1010         /* Check whether we finally succeeded with valid UAR allocation. */
1011         if (!sh->tx_uar) {
1012                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1013                 err = ENOMEM;
1014                 goto exit;
1015         }
1016         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1017                 uar_mapping = 0;
1018                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1019                                                         (sh->ctx, uar_mapping);
1020 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1021                 if (!sh->devx_rx_uar &&
1022                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1023                         /*
1024                          * Rx UAR is used to control interrupts only,
1025                          * should be no datapath noticeable impact,
1026                          * can try "Non-Cached" mapping safely.
1027                          */
1028                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1029                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1030                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1031                                                         (sh->ctx, uar_mapping);
1032                 }
1033 #endif
1034                 if (!sh->devx_rx_uar) {
1035                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1036                         err = ENOMEM;
1037                         goto exit;
1038                 }
1039                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1040                 if (base_addr)
1041                         break;
1042                 /*
1043                  * The UARs are allocated by rdma_core within the
1044                  * IB device context, on context closure all UARs
1045                  * will be freed, should be no memory/object leakage.
1046                  */
1047                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1048                 sh->devx_rx_uar = NULL;
1049         }
1050         /* Check whether we finally succeeded with valid UAR allocation. */
1051         if (!sh->devx_rx_uar) {
1052                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1053                 err = ENOMEM;
1054         }
1055 exit:
1056         return err;
1057 }
1058
1059 /**
1060  * Allocate shared device context. If there is multiport device the
1061  * master and representors will share this context, if there is single
1062  * port dedicated device, the context will be used by only given
1063  * port due to unification.
1064  *
1065  * Routine first searches the context for the specified device name,
1066  * if found the shared context assumed and reference counter is incremented.
1067  * If no context found the new one is created and initialized with specified
1068  * device context and parameters.
1069  *
1070  * @param[in] spawn
1071  *   Pointer to the device attributes (name, port, etc).
1072  * @param[in] config
1073  *   Pointer to device configuration structure.
1074  *
1075  * @return
1076  *   Pointer to mlx5_dev_ctx_shared object on success,
1077  *   otherwise NULL and rte_errno is set.
1078  */
1079 struct mlx5_dev_ctx_shared *
1080 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1081                            const struct mlx5_dev_config *config)
1082 {
1083         struct mlx5_dev_ctx_shared *sh;
1084         int err = 0;
1085         uint32_t i;
1086         struct mlx5_devx_tis_attr tis_attr = { 0 };
1087
1088         MLX5_ASSERT(spawn);
1089         /* Secondary process should not create the shared context. */
1090         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1091         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1092         /* Search for IB context by device name. */
1093         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1094                 if (!strcmp(sh->ibdev_name,
1095                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1096                         sh->refcnt++;
1097                         goto exit;
1098                 }
1099         }
1100         /* No device found, we have to create new shared context. */
1101         MLX5_ASSERT(spawn->max_port);
1102         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1103                          sizeof(struct mlx5_dev_ctx_shared) +
1104                          spawn->max_port *
1105                          sizeof(struct mlx5_dev_shared_port),
1106                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1107         if (!sh) {
1108                 DRV_LOG(ERR, "shared context allocation failure");
1109                 rte_errno  = ENOMEM;
1110                 goto exit;
1111         }
1112         if (spawn->bond_info)
1113                 sh->bond = *spawn->bond_info;
1114         err = mlx5_os_open_device(spawn, config, sh);
1115         if (!sh->ctx)
1116                 goto error;
1117         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1118         if (err) {
1119                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1120                 goto error;
1121         }
1122         sh->refcnt = 1;
1123         sh->max_port = spawn->max_port;
1124         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1125                 sizeof(sh->ibdev_name) - 1);
1126         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1127                 sizeof(sh->ibdev_path) - 1);
1128         /*
1129          * Setting port_id to max unallowed value means
1130          * there is no interrupt subhandler installed for
1131          * the given port index i.
1132          */
1133         for (i = 0; i < sh->max_port; i++) {
1134                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1135                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1136         }
1137         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1138         if (sh->pd == NULL) {
1139                 DRV_LOG(ERR, "PD allocation failure");
1140                 err = ENOMEM;
1141                 goto error;
1142         }
1143         if (sh->devx) {
1144                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1145                 if (err) {
1146                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1147                         goto error;
1148                 }
1149                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1150                 if (!sh->td) {
1151                         DRV_LOG(ERR, "TD allocation failure");
1152                         err = ENOMEM;
1153                         goto error;
1154                 }
1155                 tis_attr.transport_domain = sh->td->id;
1156                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1157                 if (!sh->tis) {
1158                         DRV_LOG(ERR, "TIS allocation failure");
1159                         err = ENOMEM;
1160                         goto error;
1161                 }
1162                 err = mlx5_alloc_rxtx_uars(sh, config);
1163                 if (err)
1164                         goto error;
1165                 MLX5_ASSERT(sh->tx_uar);
1166                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1167
1168                 MLX5_ASSERT(sh->devx_rx_uar);
1169                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1170         }
1171 #ifndef RTE_ARCH_64
1172         /* Initialize UAR access locks for 32bit implementations. */
1173         rte_spinlock_init(&sh->uar_lock_cq);
1174         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1175                 rte_spinlock_init(&sh->uar_lock[i]);
1176 #endif
1177         /*
1178          * Once the device is added to the list of memory event
1179          * callback, its global MR cache table cannot be expanded
1180          * on the fly because of deadlock. If it overflows, lookup
1181          * should be done by searching MR list linearly, which is slow.
1182          *
1183          * At this point the device is not added to the memory
1184          * event list yet, context is just being created.
1185          */
1186         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1187                                  MLX5_MR_BTREE_CACHE_N * 2,
1188                                  spawn->pci_dev->device.numa_node);
1189         if (err) {
1190                 err = rte_errno;
1191                 goto error;
1192         }
1193         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1194                               &sh->share_cache.dereg_mr_cb);
1195         mlx5_os_dev_shared_handler_install(sh);
1196         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1197         if (!sh->cnt_id_tbl) {
1198                 err = rte_errno;
1199                 goto error;
1200         }
1201         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1202                 err = mlx5_flow_os_init_workspace_once();
1203                 if (err)
1204                         goto error;
1205         }
1206         mlx5_flow_aging_init(sh);
1207         mlx5_flow_counters_mng_init(sh);
1208         mlx5_flow_ipool_create(sh, config);
1209         /* Add device to memory callback list. */
1210         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1211         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1212                          sh, mem_event_cb);
1213         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1214         /* Add context to the global device list. */
1215         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1216         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1217 exit:
1218         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1219         return sh;
1220 error:
1221         pthread_mutex_destroy(&sh->txpp.mutex);
1222         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1223         MLX5_ASSERT(sh);
1224         if (sh->cnt_id_tbl)
1225                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1226         if (sh->tis)
1227                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1228         if (sh->td)
1229                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1230         if (sh->devx_rx_uar)
1231                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1232         if (sh->tx_uar)
1233                 mlx5_glue->devx_free_uar(sh->tx_uar);
1234         if (sh->pd)
1235                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1236         if (sh->ctx)
1237                 claim_zero(mlx5_glue->close_device(sh->ctx));
1238         mlx5_free(sh);
1239         MLX5_ASSERT(err > 0);
1240         rte_errno = err;
1241         return NULL;
1242 }
1243
1244 /**
1245  * Free shared IB device context. Decrement counter and if zero free
1246  * all allocated resources and close handles.
1247  *
1248  * @param[in] sh
1249  *   Pointer to mlx5_dev_ctx_shared object to free
1250  */
1251 void
1252 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1253 {
1254         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1255 #ifdef RTE_LIBRTE_MLX5_DEBUG
1256         /* Check the object presence in the list. */
1257         struct mlx5_dev_ctx_shared *lctx;
1258
1259         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1260                 if (lctx == sh)
1261                         break;
1262         MLX5_ASSERT(lctx);
1263         if (lctx != sh) {
1264                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1265                 goto exit;
1266         }
1267 #endif
1268         MLX5_ASSERT(sh);
1269         MLX5_ASSERT(sh->refcnt);
1270         /* Secondary process should not free the shared context. */
1271         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1272         if (--sh->refcnt)
1273                 goto exit;
1274         /* Remove from memory callback device list. */
1275         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1276         LIST_REMOVE(sh, mem_event_cb);
1277         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1278         /* Release created Memory Regions. */
1279         mlx5_mr_release_cache(&sh->share_cache);
1280         /* Remove context from the global device list. */
1281         LIST_REMOVE(sh, next);
1282         /* Release flow workspaces objects on the last device. */
1283         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1284                 mlx5_flow_os_release_workspace();
1285         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1286         /*
1287          *  Ensure there is no async event handler installed.
1288          *  Only primary process handles async device events.
1289          **/
1290         mlx5_flow_counters_mng_close(sh);
1291         if (sh->aso_age_mng) {
1292                 mlx5_flow_aso_age_mng_close(sh);
1293                 sh->aso_age_mng = NULL;
1294         }
1295         if (sh->mtrmng)
1296                 mlx5_aso_flow_mtrs_mng_close(sh);
1297         mlx5_flow_ipool_destroy(sh);
1298         mlx5_os_dev_shared_handler_uninstall(sh);
1299         if (sh->cnt_id_tbl) {
1300                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1301                 sh->cnt_id_tbl = NULL;
1302         }
1303         if (sh->tx_uar) {
1304                 mlx5_glue->devx_free_uar(sh->tx_uar);
1305                 sh->tx_uar = NULL;
1306         }
1307         if (sh->pd)
1308                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1309         if (sh->tis)
1310                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1311         if (sh->td)
1312                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1313         if (sh->devx_rx_uar)
1314                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1315         if (sh->ctx)
1316                 claim_zero(mlx5_glue->close_device(sh->ctx));
1317         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1318         pthread_mutex_destroy(&sh->txpp.mutex);
1319         mlx5_free(sh);
1320         return;
1321 exit:
1322         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1323 }
1324
1325 /**
1326  * Destroy table hash list.
1327  *
1328  * @param[in] priv
1329  *   Pointer to the private device data structure.
1330  */
1331 void
1332 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1333 {
1334         struct mlx5_dev_ctx_shared *sh = priv->sh;
1335
1336         if (!sh->flow_tbls)
1337                 return;
1338         mlx5_hlist_destroy(sh->flow_tbls);
1339 }
1340
1341 /**
1342  * Initialize flow table hash list and create the root tables entry
1343  * for each domain.
1344  *
1345  * @param[in] priv
1346  *   Pointer to the private device data structure.
1347  *
1348  * @return
1349  *   Zero on success, positive error code otherwise.
1350  */
1351 int
1352 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1353 {
1354         int err = 0;
1355         /* Tables are only used in DV and DR modes. */
1356 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1357         struct mlx5_dev_ctx_shared *sh = priv->sh;
1358         char s[MLX5_HLIST_NAMESIZE];
1359
1360         MLX5_ASSERT(sh);
1361         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1362         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1363                                           0, 0, flow_dv_tbl_create_cb,
1364                                           flow_dv_tbl_match_cb,
1365                                           flow_dv_tbl_remove_cb);
1366         if (!sh->flow_tbls) {
1367                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1368                 err = ENOMEM;
1369                 return err;
1370         }
1371         sh->flow_tbls->ctx = sh;
1372 #ifndef HAVE_MLX5DV_DR
1373         struct rte_flow_error error;
1374         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1375
1376         /*
1377          * In case we have not DR support, the zero tables should be created
1378          * because DV expect to see them even if they cannot be created by
1379          * RDMA-CORE.
1380          */
1381         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1382                 NULL, 0, 1, 0, &error) ||
1383             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1384                 NULL, 0, 1, 0, &error) ||
1385             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1386                 NULL, 0, 1, 0, &error)) {
1387                 err = ENOMEM;
1388                 goto error;
1389         }
1390         return err;
1391 error:
1392         mlx5_free_table_hash_list(priv);
1393 #endif /* HAVE_MLX5DV_DR */
1394 #endif
1395         return err;
1396 }
1397
1398 /**
1399  * Retrieve integer value from environment variable.
1400  *
1401  * @param[in] name
1402  *   Environment variable name.
1403  *
1404  * @return
1405  *   Integer value, 0 if the variable is not set.
1406  */
1407 int
1408 mlx5_getenv_int(const char *name)
1409 {
1410         const char *val = getenv(name);
1411
1412         if (val == NULL)
1413                 return 0;
1414         return atoi(val);
1415 }
1416
1417 /**
1418  * DPDK callback to add udp tunnel port
1419  *
1420  * @param[in] dev
1421  *   A pointer to eth_dev
1422  * @param[in] udp_tunnel
1423  *   A pointer to udp tunnel
1424  *
1425  * @return
1426  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1427  */
1428 int
1429 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1430                          struct rte_eth_udp_tunnel *udp_tunnel)
1431 {
1432         MLX5_ASSERT(udp_tunnel != NULL);
1433         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1434             udp_tunnel->udp_port == 4789)
1435                 return 0;
1436         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1437             udp_tunnel->udp_port == 4790)
1438                 return 0;
1439         return -ENOTSUP;
1440 }
1441
1442 /**
1443  * Initialize process private data structure.
1444  *
1445  * @param dev
1446  *   Pointer to Ethernet device structure.
1447  *
1448  * @return
1449  *   0 on success, a negative errno value otherwise and rte_errno is set.
1450  */
1451 int
1452 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1453 {
1454         struct mlx5_priv *priv = dev->data->dev_private;
1455         struct mlx5_proc_priv *ppriv;
1456         size_t ppriv_size;
1457
1458         /*
1459          * UAR register table follows the process private structure. BlueFlame
1460          * registers for Tx queues are stored in the table.
1461          */
1462         ppriv_size =
1463                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1464         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1465                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1466         if (!ppriv) {
1467                 rte_errno = ENOMEM;
1468                 return -rte_errno;
1469         }
1470         ppriv->uar_table_sz = priv->txqs_n;
1471         dev->process_private = ppriv;
1472         return 0;
1473 }
1474
1475 /**
1476  * Un-initialize process private data structure.
1477  *
1478  * @param dev
1479  *   Pointer to Ethernet device structure.
1480  */
1481 void
1482 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1483 {
1484         if (!dev->process_private)
1485                 return;
1486         mlx5_free(dev->process_private);
1487         dev->process_private = NULL;
1488 }
1489
1490 /**
1491  * DPDK callback to close the device.
1492  *
1493  * Destroy all queues and objects, free memory.
1494  *
1495  * @param dev
1496  *   Pointer to Ethernet device structure.
1497  */
1498 int
1499 mlx5_dev_close(struct rte_eth_dev *dev)
1500 {
1501         struct mlx5_priv *priv = dev->data->dev_private;
1502         unsigned int i;
1503         int ret;
1504
1505         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1506                 /* Check if process_private released. */
1507                 if (!dev->process_private)
1508                         return 0;
1509                 mlx5_tx_uar_uninit_secondary(dev);
1510                 mlx5_proc_priv_uninit(dev);
1511                 rte_eth_dev_release_port(dev);
1512                 return 0;
1513         }
1514         if (!priv->sh)
1515                 return 0;
1516         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1517                 dev->data->port_id,
1518                 ((priv->sh->ctx != NULL) ?
1519                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1520         /*
1521          * If default mreg copy action is removed at the stop stage,
1522          * the search will return none and nothing will be done anymore.
1523          */
1524         mlx5_flow_stop_default(dev);
1525         mlx5_traffic_disable(dev);
1526         /*
1527          * If all the flows are already flushed in the device stop stage,
1528          * then this will return directly without any action.
1529          */
1530         mlx5_flow_list_flush(dev, &priv->flows, true);
1531         mlx5_action_handle_flush(dev);
1532         mlx5_flow_meter_flush(dev, NULL);
1533         /* Prevent crashes when queues are still in use. */
1534         dev->rx_pkt_burst = removed_rx_burst;
1535         dev->tx_pkt_burst = removed_tx_burst;
1536         rte_wmb();
1537         /* Disable datapath on secondary process. */
1538         mlx5_mp_os_req_stop_rxtx(dev);
1539         /* Free the eCPRI flex parser resource. */
1540         mlx5_flex_parser_ecpri_release(dev);
1541         if (priv->rxqs != NULL) {
1542                 /* XXX race condition if mlx5_rx_burst() is still running. */
1543                 rte_delay_us_sleep(1000);
1544                 for (i = 0; (i != priv->rxqs_n); ++i)
1545                         mlx5_rxq_release(dev, i);
1546                 priv->rxqs_n = 0;
1547                 priv->rxqs = NULL;
1548         }
1549         if (priv->txqs != NULL) {
1550                 /* XXX race condition if mlx5_tx_burst() is still running. */
1551                 rte_delay_us_sleep(1000);
1552                 for (i = 0; (i != priv->txqs_n); ++i)
1553                         mlx5_txq_release(dev, i);
1554                 priv->txqs_n = 0;
1555                 priv->txqs = NULL;
1556         }
1557         mlx5_proc_priv_uninit(dev);
1558         if (priv->q_counters) {
1559                 mlx5_devx_cmd_destroy(priv->q_counters);
1560                 priv->q_counters = NULL;
1561         }
1562         if (priv->drop_queue.hrxq)
1563                 mlx5_drop_action_destroy(dev);
1564         if (priv->mreg_cp_tbl)
1565                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1566         mlx5_mprq_free_mp(dev);
1567         if (priv->sh->ct_mng)
1568                 mlx5_flow_aso_ct_mng_close(priv->sh);
1569         mlx5_os_free_shared_dr(priv);
1570         if (priv->rss_conf.rss_key != NULL)
1571                 mlx5_free(priv->rss_conf.rss_key);
1572         if (priv->reta_idx != NULL)
1573                 mlx5_free(priv->reta_idx);
1574         if (priv->config.vf)
1575                 mlx5_os_mac_addr_flush(dev);
1576         if (priv->nl_socket_route >= 0)
1577                 close(priv->nl_socket_route);
1578         if (priv->nl_socket_rdma >= 0)
1579                 close(priv->nl_socket_rdma);
1580         if (priv->vmwa_context)
1581                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1582         ret = mlx5_hrxq_verify(dev);
1583         if (ret)
1584                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1585                         dev->data->port_id);
1586         ret = mlx5_ind_table_obj_verify(dev);
1587         if (ret)
1588                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1589                         dev->data->port_id);
1590         ret = mlx5_rxq_obj_verify(dev);
1591         if (ret)
1592                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1593                         dev->data->port_id);
1594         ret = mlx5_rxq_verify(dev);
1595         if (ret)
1596                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1597                         dev->data->port_id);
1598         ret = mlx5_txq_obj_verify(dev);
1599         if (ret)
1600                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1601                         dev->data->port_id);
1602         ret = mlx5_txq_verify(dev);
1603         if (ret)
1604                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1605                         dev->data->port_id);
1606         ret = mlx5_flow_verify(dev);
1607         if (ret)
1608                 DRV_LOG(WARNING, "port %u some flows still remain",
1609                         dev->data->port_id);
1610         mlx5_cache_list_destroy(&priv->hrxqs);
1611         /*
1612          * Free the shared context in last turn, because the cleanup
1613          * routines above may use some shared fields, like
1614          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1615          * ifindex if Netlink fails.
1616          */
1617         mlx5_free_shared_dev_ctx(priv->sh);
1618         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1619                 unsigned int c = 0;
1620                 uint16_t port_id;
1621
1622                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1623                         struct mlx5_priv *opriv =
1624                                 rte_eth_devices[port_id].data->dev_private;
1625
1626                         if (!opriv ||
1627                             opriv->domain_id != priv->domain_id ||
1628                             &rte_eth_devices[port_id] == dev)
1629                                 continue;
1630                         ++c;
1631                         break;
1632                 }
1633                 if (!c)
1634                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1635         }
1636         memset(priv, 0, sizeof(*priv));
1637         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1638         /*
1639          * Reset mac_addrs to NULL such that it is not freed as part of
1640          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1641          * it is freed when dev_private is freed.
1642          */
1643         dev->data->mac_addrs = NULL;
1644         return 0;
1645 }
1646
1647 const struct eth_dev_ops mlx5_dev_ops = {
1648         .dev_configure = mlx5_dev_configure,
1649         .dev_start = mlx5_dev_start,
1650         .dev_stop = mlx5_dev_stop,
1651         .dev_set_link_down = mlx5_set_link_down,
1652         .dev_set_link_up = mlx5_set_link_up,
1653         .dev_close = mlx5_dev_close,
1654         .promiscuous_enable = mlx5_promiscuous_enable,
1655         .promiscuous_disable = mlx5_promiscuous_disable,
1656         .allmulticast_enable = mlx5_allmulticast_enable,
1657         .allmulticast_disable = mlx5_allmulticast_disable,
1658         .link_update = mlx5_link_update,
1659         .stats_get = mlx5_stats_get,
1660         .stats_reset = mlx5_stats_reset,
1661         .xstats_get = mlx5_xstats_get,
1662         .xstats_reset = mlx5_xstats_reset,
1663         .xstats_get_names = mlx5_xstats_get_names,
1664         .fw_version_get = mlx5_fw_version_get,
1665         .dev_infos_get = mlx5_dev_infos_get,
1666         .representor_info_get = mlx5_representor_info_get,
1667         .read_clock = mlx5_txpp_read_clock,
1668         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1669         .vlan_filter_set = mlx5_vlan_filter_set,
1670         .rx_queue_setup = mlx5_rx_queue_setup,
1671         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1672         .tx_queue_setup = mlx5_tx_queue_setup,
1673         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1674         .rx_queue_release = mlx5_rx_queue_release,
1675         .tx_queue_release = mlx5_tx_queue_release,
1676         .rx_queue_start = mlx5_rx_queue_start,
1677         .rx_queue_stop = mlx5_rx_queue_stop,
1678         .tx_queue_start = mlx5_tx_queue_start,
1679         .tx_queue_stop = mlx5_tx_queue_stop,
1680         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1681         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1682         .mac_addr_remove = mlx5_mac_addr_remove,
1683         .mac_addr_add = mlx5_mac_addr_add,
1684         .mac_addr_set = mlx5_mac_addr_set,
1685         .set_mc_addr_list = mlx5_set_mc_addr_list,
1686         .mtu_set = mlx5_dev_set_mtu,
1687         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1688         .vlan_offload_set = mlx5_vlan_offload_set,
1689         .reta_update = mlx5_dev_rss_reta_update,
1690         .reta_query = mlx5_dev_rss_reta_query,
1691         .rss_hash_update = mlx5_rss_hash_update,
1692         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1693         .flow_ops_get = mlx5_flow_ops_get,
1694         .rxq_info_get = mlx5_rxq_info_get,
1695         .txq_info_get = mlx5_txq_info_get,
1696         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1697         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1698         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1699         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1700         .is_removed = mlx5_is_removed,
1701         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1702         .get_module_info = mlx5_get_module_info,
1703         .get_module_eeprom = mlx5_get_module_eeprom,
1704         .hairpin_cap_get = mlx5_hairpin_cap_get,
1705         .mtr_ops_get = mlx5_flow_meter_ops_get,
1706         .hairpin_bind = mlx5_hairpin_bind,
1707         .hairpin_unbind = mlx5_hairpin_unbind,
1708         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1709         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1710         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1711         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1712         .get_monitor_addr = mlx5_get_monitor_addr,
1713 };
1714
1715 /* Available operations from secondary process. */
1716 const struct eth_dev_ops mlx5_dev_sec_ops = {
1717         .stats_get = mlx5_stats_get,
1718         .stats_reset = mlx5_stats_reset,
1719         .xstats_get = mlx5_xstats_get,
1720         .xstats_reset = mlx5_xstats_reset,
1721         .xstats_get_names = mlx5_xstats_get_names,
1722         .fw_version_get = mlx5_fw_version_get,
1723         .dev_infos_get = mlx5_dev_infos_get,
1724         .read_clock = mlx5_txpp_read_clock,
1725         .rx_queue_start = mlx5_rx_queue_start,
1726         .rx_queue_stop = mlx5_rx_queue_stop,
1727         .tx_queue_start = mlx5_tx_queue_start,
1728         .tx_queue_stop = mlx5_tx_queue_stop,
1729         .rxq_info_get = mlx5_rxq_info_get,
1730         .txq_info_get = mlx5_txq_info_get,
1731         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1732         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1733         .get_module_info = mlx5_get_module_info,
1734         .get_module_eeprom = mlx5_get_module_eeprom,
1735 };
1736
1737 /* Available operations in flow isolated mode. */
1738 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1739         .dev_configure = mlx5_dev_configure,
1740         .dev_start = mlx5_dev_start,
1741         .dev_stop = mlx5_dev_stop,
1742         .dev_set_link_down = mlx5_set_link_down,
1743         .dev_set_link_up = mlx5_set_link_up,
1744         .dev_close = mlx5_dev_close,
1745         .promiscuous_enable = mlx5_promiscuous_enable,
1746         .promiscuous_disable = mlx5_promiscuous_disable,
1747         .allmulticast_enable = mlx5_allmulticast_enable,
1748         .allmulticast_disable = mlx5_allmulticast_disable,
1749         .link_update = mlx5_link_update,
1750         .stats_get = mlx5_stats_get,
1751         .stats_reset = mlx5_stats_reset,
1752         .xstats_get = mlx5_xstats_get,
1753         .xstats_reset = mlx5_xstats_reset,
1754         .xstats_get_names = mlx5_xstats_get_names,
1755         .fw_version_get = mlx5_fw_version_get,
1756         .dev_infos_get = mlx5_dev_infos_get,
1757         .read_clock = mlx5_txpp_read_clock,
1758         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1759         .vlan_filter_set = mlx5_vlan_filter_set,
1760         .rx_queue_setup = mlx5_rx_queue_setup,
1761         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1762         .tx_queue_setup = mlx5_tx_queue_setup,
1763         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1764         .rx_queue_release = mlx5_rx_queue_release,
1765         .tx_queue_release = mlx5_tx_queue_release,
1766         .rx_queue_start = mlx5_rx_queue_start,
1767         .rx_queue_stop = mlx5_rx_queue_stop,
1768         .tx_queue_start = mlx5_tx_queue_start,
1769         .tx_queue_stop = mlx5_tx_queue_stop,
1770         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1771         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1772         .mac_addr_remove = mlx5_mac_addr_remove,
1773         .mac_addr_add = mlx5_mac_addr_add,
1774         .mac_addr_set = mlx5_mac_addr_set,
1775         .set_mc_addr_list = mlx5_set_mc_addr_list,
1776         .mtu_set = mlx5_dev_set_mtu,
1777         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1778         .vlan_offload_set = mlx5_vlan_offload_set,
1779         .flow_ops_get = mlx5_flow_ops_get,
1780         .rxq_info_get = mlx5_rxq_info_get,
1781         .txq_info_get = mlx5_txq_info_get,
1782         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1783         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1784         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1785         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1786         .is_removed = mlx5_is_removed,
1787         .get_module_info = mlx5_get_module_info,
1788         .get_module_eeprom = mlx5_get_module_eeprom,
1789         .hairpin_cap_get = mlx5_hairpin_cap_get,
1790         .mtr_ops_get = mlx5_flow_meter_ops_get,
1791         .hairpin_bind = mlx5_hairpin_bind,
1792         .hairpin_unbind = mlx5_hairpin_unbind,
1793         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1794         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1795         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1796         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1797         .get_monitor_addr = mlx5_get_monitor_addr,
1798 };
1799
1800 /**
1801  * Verify and store value for device argument.
1802  *
1803  * @param[in] key
1804  *   Key argument to verify.
1805  * @param[in] val
1806  *   Value associated with key.
1807  * @param opaque
1808  *   User data.
1809  *
1810  * @return
1811  *   0 on success, a negative errno value otherwise and rte_errno is set.
1812  */
1813 static int
1814 mlx5_args_check(const char *key, const char *val, void *opaque)
1815 {
1816         struct mlx5_dev_config *config = opaque;
1817         unsigned long mod;
1818         signed long tmp;
1819
1820         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1821         if (!strcmp(MLX5_REPRESENTOR, key))
1822                 return 0;
1823         errno = 0;
1824         tmp = strtol(val, NULL, 0);
1825         if (errno) {
1826                 rte_errno = errno;
1827                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1828                 return -rte_errno;
1829         }
1830         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1831                 /* Negative values are acceptable for some keys only. */
1832                 rte_errno = EINVAL;
1833                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1834                 return -rte_errno;
1835         }
1836         mod = tmp >= 0 ? tmp : -tmp;
1837         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1838                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1839                         DRV_LOG(ERR, "invalid CQE compression "
1840                                      "format parameter");
1841                         rte_errno = EINVAL;
1842                         return -rte_errno;
1843                 }
1844                 config->cqe_comp = !!tmp;
1845                 config->cqe_comp_fmt = tmp;
1846         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1847                 config->hw_padding = !!tmp;
1848         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1849                 config->mprq.enabled = !!tmp;
1850         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1851                 config->mprq.stride_num_n = tmp;
1852         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1853                 config->mprq.stride_size_n = tmp;
1854         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1855                 config->mprq.max_memcpy_len = tmp;
1856         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1857                 config->mprq.min_rxqs_num = tmp;
1858         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1859                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1860                                  " converted to txq_inline_max", key);
1861                 config->txq_inline_max = tmp;
1862         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1863                 config->txq_inline_max = tmp;
1864         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1865                 config->txq_inline_min = tmp;
1866         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1867                 config->txq_inline_mpw = tmp;
1868         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1869                 config->txqs_inline = tmp;
1870         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1871                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1872         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1873                 config->mps = !!tmp;
1874         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1875                 if (tmp != MLX5_TXDB_CACHED &&
1876                     tmp != MLX5_TXDB_NCACHED &&
1877                     tmp != MLX5_TXDB_HEURISTIC) {
1878                         DRV_LOG(ERR, "invalid Tx doorbell "
1879                                      "mapping parameter");
1880                         rte_errno = EINVAL;
1881                         return -rte_errno;
1882                 }
1883                 config->dbnc = tmp;
1884         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1885                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1886         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1887                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1888                                  " converted to txq_inline_mpw", key);
1889                 config->txq_inline_mpw = tmp;
1890         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1891                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1892         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1893                 if (!mod) {
1894                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1895                         rte_errno = EINVAL;
1896                         return -rte_errno;
1897                 }
1898                 config->tx_pp = tmp;
1899         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1900                 config->tx_skew = tmp;
1901         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1902                 config->rx_vec_en = !!tmp;
1903         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1904                 config->l3_vxlan_en = !!tmp;
1905         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1906                 config->vf_nl_en = !!tmp;
1907         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1908                 config->dv_esw_en = !!tmp;
1909         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1910                 config->dv_flow_en = !!tmp;
1911         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1912                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1913                     tmp != MLX5_XMETA_MODE_META16 &&
1914                     tmp != MLX5_XMETA_MODE_META32 &&
1915                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1916                         DRV_LOG(ERR, "invalid extensive "
1917                                      "metadata parameter");
1918                         rte_errno = EINVAL;
1919                         return -rte_errno;
1920                 }
1921                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1922                         config->dv_xmeta_en = tmp;
1923                 else
1924                         config->dv_miss_info = 1;
1925         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1926                 config->lacp_by_user = !!tmp;
1927         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1928                 config->mr_ext_memseg_en = !!tmp;
1929         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1930                 config->max_dump_files_num = tmp;
1931         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1932                 config->lro.timeout = tmp;
1933         } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) {
1934                 DRV_LOG(DEBUG, "class argument is %s.", val);
1935         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1936                 config->log_hp_size = tmp;
1937         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1938                 if (tmp != MLX5_RCM_NONE &&
1939                     tmp != MLX5_RCM_LIGHT &&
1940                     tmp != MLX5_RCM_AGGR) {
1941                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1942                         rte_errno = EINVAL;
1943                         return -rte_errno;
1944                 }
1945                 config->reclaim_mode = tmp;
1946         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1947                 config->sys_mem_en = !!tmp;
1948         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1949                 config->decap_en = !!tmp;
1950         } else {
1951                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1952                 rte_errno = EINVAL;
1953                 return -rte_errno;
1954         }
1955         return 0;
1956 }
1957
1958 /**
1959  * Parse device parameters.
1960  *
1961  * @param config
1962  *   Pointer to device configuration structure.
1963  * @param devargs
1964  *   Device arguments structure.
1965  *
1966  * @return
1967  *   0 on success, a negative errno value otherwise and rte_errno is set.
1968  */
1969 int
1970 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1971 {
1972         const char **params = (const char *[]){
1973                 MLX5_RXQ_CQE_COMP_EN,
1974                 MLX5_RXQ_PKT_PAD_EN,
1975                 MLX5_RX_MPRQ_EN,
1976                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1977                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1978                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1979                 MLX5_RXQS_MIN_MPRQ,
1980                 MLX5_TXQ_INLINE,
1981                 MLX5_TXQ_INLINE_MIN,
1982                 MLX5_TXQ_INLINE_MAX,
1983                 MLX5_TXQ_INLINE_MPW,
1984                 MLX5_TXQS_MIN_INLINE,
1985                 MLX5_TXQS_MAX_VEC,
1986                 MLX5_TXQ_MPW_EN,
1987                 MLX5_TXQ_MPW_HDR_DSEG_EN,
1988                 MLX5_TXQ_MAX_INLINE_LEN,
1989                 MLX5_TX_DB_NC,
1990                 MLX5_TX_PP,
1991                 MLX5_TX_SKEW,
1992                 MLX5_TX_VEC_EN,
1993                 MLX5_RX_VEC_EN,
1994                 MLX5_L3_VXLAN_EN,
1995                 MLX5_VF_NL_EN,
1996                 MLX5_DV_ESW_EN,
1997                 MLX5_DV_FLOW_EN,
1998                 MLX5_DV_XMETA_EN,
1999                 MLX5_LACP_BY_USER,
2000                 MLX5_MR_EXT_MEMSEG_EN,
2001                 MLX5_REPRESENTOR,
2002                 MLX5_MAX_DUMP_FILES_NUM,
2003                 MLX5_LRO_TIMEOUT_USEC,
2004                 MLX5_CLASS_ARG_NAME,
2005                 MLX5_HP_BUF_SIZE,
2006                 MLX5_RECLAIM_MEM,
2007                 MLX5_SYS_MEM_EN,
2008                 MLX5_DECAP_EN,
2009                 NULL,
2010         };
2011         struct rte_kvargs *kvlist;
2012         int ret = 0;
2013         int i;
2014
2015         if (devargs == NULL)
2016                 return 0;
2017         /* Following UGLY cast is done to pass checkpatch. */
2018         kvlist = rte_kvargs_parse(devargs->args, params);
2019         if (kvlist == NULL) {
2020                 rte_errno = EINVAL;
2021                 return -rte_errno;
2022         }
2023         /* Process parameters. */
2024         for (i = 0; (params[i] != NULL); ++i) {
2025                 if (rte_kvargs_count(kvlist, params[i])) {
2026                         ret = rte_kvargs_process(kvlist, params[i],
2027                                                  mlx5_args_check, config);
2028                         if (ret) {
2029                                 rte_errno = EINVAL;
2030                                 rte_kvargs_free(kvlist);
2031                                 return -rte_errno;
2032                         }
2033                 }
2034         }
2035         rte_kvargs_free(kvlist);
2036         return 0;
2037 }
2038
2039 /**
2040  * Configures the minimal amount of data to inline into WQE
2041  * while sending packets.
2042  *
2043  * - the txq_inline_min has the maximal priority, if this
2044  *   key is specified in devargs
2045  * - if DevX is enabled the inline mode is queried from the
2046  *   device (HCA attributes and NIC vport context if needed).
2047  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2048  *   and none (0 bytes) for other NICs
2049  *
2050  * @param spawn
2051  *   Verbs device parameters (name, port, switch_info) to spawn.
2052  * @param config
2053  *   Device configuration parameters.
2054  */
2055 void
2056 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2057                     struct mlx5_dev_config *config)
2058 {
2059         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2060                 /* Application defines size of inlined data explicitly. */
2061                 switch (spawn->pci_dev->id.device_id) {
2062                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2063                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2064                         if (config->txq_inline_min <
2065                                        (int)MLX5_INLINE_HSIZE_L2) {
2066                                 DRV_LOG(DEBUG,
2067                                         "txq_inline_mix aligned to minimal"
2068                                         " ConnectX-4 required value %d",
2069                                         (int)MLX5_INLINE_HSIZE_L2);
2070                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2071                         }
2072                         break;
2073                 }
2074                 goto exit;
2075         }
2076         if (config->hca_attr.eth_net_offloads) {
2077                 /* We have DevX enabled, inline mode queried successfully. */
2078                 switch (config->hca_attr.wqe_inline_mode) {
2079                 case MLX5_CAP_INLINE_MODE_L2:
2080                         /* outer L2 header must be inlined. */
2081                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2082                         goto exit;
2083                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2084                         /* No inline data are required by NIC. */
2085                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2086                         config->hw_vlan_insert =
2087                                 config->hca_attr.wqe_vlan_insert;
2088                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2089                         goto exit;
2090                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2091                         /* inline mode is defined by NIC vport context. */
2092                         if (!config->hca_attr.eth_virt)
2093                                 break;
2094                         switch (config->hca_attr.vport_inline_mode) {
2095                         case MLX5_INLINE_MODE_NONE:
2096                                 config->txq_inline_min =
2097                                         MLX5_INLINE_HSIZE_NONE;
2098                                 goto exit;
2099                         case MLX5_INLINE_MODE_L2:
2100                                 config->txq_inline_min =
2101                                         MLX5_INLINE_HSIZE_L2;
2102                                 goto exit;
2103                         case MLX5_INLINE_MODE_IP:
2104                                 config->txq_inline_min =
2105                                         MLX5_INLINE_HSIZE_L3;
2106                                 goto exit;
2107                         case MLX5_INLINE_MODE_TCP_UDP:
2108                                 config->txq_inline_min =
2109                                         MLX5_INLINE_HSIZE_L4;
2110                                 goto exit;
2111                         case MLX5_INLINE_MODE_INNER_L2:
2112                                 config->txq_inline_min =
2113                                         MLX5_INLINE_HSIZE_INNER_L2;
2114                                 goto exit;
2115                         case MLX5_INLINE_MODE_INNER_IP:
2116                                 config->txq_inline_min =
2117                                         MLX5_INLINE_HSIZE_INNER_L3;
2118                                 goto exit;
2119                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2120                                 config->txq_inline_min =
2121                                         MLX5_INLINE_HSIZE_INNER_L4;
2122                                 goto exit;
2123                         }
2124                 }
2125         }
2126         /*
2127          * We get here if we are unable to deduce
2128          * inline data size with DevX. Try PCI ID
2129          * to determine old NICs.
2130          */
2131         switch (spawn->pci_dev->id.device_id) {
2132         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2133         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2134         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2135         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2136                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2137                 config->hw_vlan_insert = 0;
2138                 break;
2139         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2140         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2141         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2142         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2143                 /*
2144                  * These NICs support VLAN insertion from WQE and
2145                  * report the wqe_vlan_insert flag. But there is the bug
2146                  * and PFC control may be broken, so disable feature.
2147                  */
2148                 config->hw_vlan_insert = 0;
2149                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2150                 break;
2151         default:
2152                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2153                 break;
2154         }
2155 exit:
2156         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2157 }
2158
2159 /**
2160  * Configures the metadata mask fields in the shared context.
2161  *
2162  * @param [in] dev
2163  *   Pointer to Ethernet device.
2164  */
2165 void
2166 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2167 {
2168         struct mlx5_priv *priv = dev->data->dev_private;
2169         struct mlx5_dev_ctx_shared *sh = priv->sh;
2170         uint32_t meta, mark, reg_c0;
2171
2172         reg_c0 = ~priv->vport_meta_mask;
2173         switch (priv->config.dv_xmeta_en) {
2174         case MLX5_XMETA_MODE_LEGACY:
2175                 meta = UINT32_MAX;
2176                 mark = MLX5_FLOW_MARK_MASK;
2177                 break;
2178         case MLX5_XMETA_MODE_META16:
2179                 meta = reg_c0 >> rte_bsf32(reg_c0);
2180                 mark = MLX5_FLOW_MARK_MASK;
2181                 break;
2182         case MLX5_XMETA_MODE_META32:
2183                 meta = UINT32_MAX;
2184                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2185                 break;
2186         default:
2187                 meta = 0;
2188                 mark = 0;
2189                 MLX5_ASSERT(false);
2190                 break;
2191         }
2192         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2193                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2194                                  sh->dv_mark_mask, mark);
2195         else
2196                 sh->dv_mark_mask = mark;
2197         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2198                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2199                                  sh->dv_meta_mask, meta);
2200         else
2201                 sh->dv_meta_mask = meta;
2202         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2203                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2204                                  sh->dv_meta_mask, reg_c0);
2205         else
2206                 sh->dv_regc0_mask = reg_c0;
2207         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2208         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2209         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2210         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2211 }
2212
2213 int
2214 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2215 {
2216         static const char *const dynf_names[] = {
2217                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2218                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2219                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2220         };
2221         unsigned int i;
2222
2223         if (n < RTE_DIM(dynf_names))
2224                 return -ENOMEM;
2225         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2226                 if (names[i] == NULL)
2227                         return -EINVAL;
2228                 strcpy(names[i], dynf_names[i]);
2229         }
2230         return RTE_DIM(dynf_names);
2231 }
2232
2233 /**
2234  * Comparison callback to sort device data.
2235  *
2236  * This is meant to be used with qsort().
2237  *
2238  * @param a[in]
2239  *   Pointer to pointer to first data object.
2240  * @param b[in]
2241  *   Pointer to pointer to second data object.
2242  *
2243  * @return
2244  *   0 if both objects are equal, less than 0 if the first argument is less
2245  *   than the second, greater than 0 otherwise.
2246  */
2247 int
2248 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2249                               struct mlx5_dev_config *config)
2250 {
2251         struct mlx5_dev_ctx_shared *sh = priv->sh;
2252         struct mlx5_dev_config *sh_conf = NULL;
2253         uint16_t port_id;
2254
2255         MLX5_ASSERT(sh);
2256         /* Nothing to compare for the single/first device. */
2257         if (sh->refcnt == 1)
2258                 return 0;
2259         /* Find the device with shared context. */
2260         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2261                 struct mlx5_priv *opriv =
2262                         rte_eth_devices[port_id].data->dev_private;
2263
2264                 if (opriv && opriv != priv && opriv->sh == sh) {
2265                         sh_conf = &opriv->config;
2266                         break;
2267                 }
2268         }
2269         if (!sh_conf)
2270                 return 0;
2271         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2272                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2273                              " for shared %s context", sh->ibdev_name);
2274                 rte_errno = EINVAL;
2275                 return rte_errno;
2276         }
2277         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2278                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2279                              " for shared %s context", sh->ibdev_name);
2280                 rte_errno = EINVAL;
2281                 return rte_errno;
2282         }
2283         return 0;
2284 }
2285
2286 /**
2287  * Look for the ethernet device belonging to mlx5 driver.
2288  *
2289  * @param[in] port_id
2290  *   port_id to start looking for device.
2291  * @param[in] pci_dev
2292  *   Pointer to the hint PCI device. When device is being probed
2293  *   the its siblings (master and preceding representors might
2294  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2295  *   is not completed yet, for this case match on hint PCI
2296  *   device may be used to detect sibling device.
2297  *
2298  * @return
2299  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2300  */
2301 uint16_t
2302 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2303 {
2304         while (port_id < RTE_MAX_ETHPORTS) {
2305                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2306
2307                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2308                     dev->device &&
2309                     (dev->device == &pci_dev->device ||
2310                      (dev->device->driver &&
2311                      dev->device->driver->name &&
2312                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2313                         break;
2314                 port_id++;
2315         }
2316         if (port_id >= RTE_MAX_ETHPORTS)
2317                 return RTE_MAX_ETHPORTS;
2318         return port_id;
2319 }
2320
2321 /**
2322  * DPDK callback to remove a PCI device.
2323  *
2324  * This function removes all Ethernet devices belong to a given PCI device.
2325  *
2326  * @param[in] pci_dev
2327  *   Pointer to the PCI device.
2328  *
2329  * @return
2330  *   0 on success, the function cannot fail.
2331  */
2332 static int
2333 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2334 {
2335         uint16_t port_id;
2336         int ret = 0;
2337
2338         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2339                 /*
2340                  * mlx5_dev_close() is not registered to secondary process,
2341                  * call the close function explicitly for secondary process.
2342                  */
2343                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2344                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2345                 else
2346                         ret |= rte_eth_dev_close(port_id);
2347         }
2348         return ret == 0 ? 0 : -EIO;
2349 }
2350
2351 static const struct rte_pci_id mlx5_pci_id_map[] = {
2352         {
2353                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2354                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2355         },
2356         {
2357                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2358                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2359         },
2360         {
2361                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2362                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2363         },
2364         {
2365                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2366                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2367         },
2368         {
2369                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2370                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2371         },
2372         {
2373                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2374                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2375         },
2376         {
2377                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2378                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2379         },
2380         {
2381                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2382                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2383         },
2384         {
2385                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2386                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2387         },
2388         {
2389                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2390                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2391         },
2392         {
2393                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2394                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2395         },
2396         {
2397                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2398                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2399         },
2400         {
2401                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2402                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2403         },
2404         {
2405                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2406                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2407         },
2408         {
2409                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2410                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2411         },
2412         {
2413                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2414                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2415         },
2416         {
2417                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2418                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2419         },
2420         {
2421                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2422                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2423         },
2424         {
2425                 .vendor_id = 0
2426         }
2427 };
2428
2429 static struct mlx5_pci_driver mlx5_driver = {
2430         .driver_class = MLX5_CLASS_NET,
2431         .pci_driver = {
2432                 .driver = {
2433                         .name = MLX5_PCI_DRIVER_NAME,
2434                 },
2435                 .id_table = mlx5_pci_id_map,
2436                 .probe = mlx5_os_pci_probe,
2437                 .remove = mlx5_pci_remove,
2438                 .dma_map = mlx5_dma_map,
2439                 .dma_unmap = mlx5_dma_unmap,
2440                 .drv_flags = PCI_DRV_FLAGS,
2441         },
2442 };
2443
2444 /* Initialize driver log type. */
2445 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2446
2447 /**
2448  * Driver initialization routine.
2449  */
2450 RTE_INIT(rte_mlx5_pmd_init)
2451 {
2452         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2453         mlx5_common_init();
2454         /* Build the static tables for Verbs conversion. */
2455         mlx5_set_ptype_table();
2456         mlx5_set_cksum_table();
2457         mlx5_set_swp_types_table();
2458         if (mlx5_glue)
2459                 mlx5_pci_driver_register(&mlx5_driver);
2460 }
2461
2462 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2463 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2464 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");