drivers/net/mlx5/mlx5.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <stddef.h>
   7 #include <unistd.h>
   8 #include <string.h>
   9 #include <stdint.h>
  10 #include <stdlib.h>
  11 #include <errno.h>
  12
  13 #include <rte_malloc.h>
  14 #include <ethdev_driver.h>
  15 #include <ethdev_pci.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_common.h>
  19 #include <rte_kvargs.h>
  20 #include <rte_rwlock.h>
  21 #include <rte_spinlock.h>
  22 #include <rte_string_fns.h>
  23 #include <rte_alarm.h>
  24 #include <rte_cycles.h>
  25
  26 #include <mlx5_glue.h>
  27 #include <mlx5_devx_cmds.h>
  28 #include <mlx5_common.h>
  29 #include <mlx5_common_os.h>
  30 #include <mlx5_common_mp.h>
  31 #include <mlx5_common_pci.h>
  32 #include <mlx5_malloc.h>
  33
  34 #include "mlx5_defs.h"
  35 #include "mlx5.h"
  36 #include "mlx5_utils.h"
  37 #include "mlx5_rxtx.h"
  38 #include "mlx5_rx.h"
  39 #include "mlx5_tx.h"
  40 #include "mlx5_autoconf.h"
  41 #include "mlx5_mr.h"
  42 #include "mlx5_flow.h"
  43 #include "mlx5_flow_os.h"
  44 #include "rte_pmd_mlx5.h"
  45
  46 /* Device parameter to enable RX completion queue compression. */
  47 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
  48
  49 /* Device parameter to enable padding Rx packet to cacheline size. */
  50 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
  51
  52 /* Device parameter to enable Multi-Packet Rx queue. */
  53 #define MLX5_RX_MPRQ_EN "mprq_en"
  54
  55 /* Device parameter to configure log 2 of the number of strides for MPRQ. */
  56 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
  57
  58 /* Device parameter to configure log 2 of the stride size for MPRQ. */
  59 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size"
  60
  61 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
  62 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
  63
  64 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
  65 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
  66
  67 /* Device parameter to configure inline send. Deprecated, ignored.*/
  68 #define MLX5_TXQ_INLINE "txq_inline"
  69
  70 /* Device parameter to limit packet size to inline with ordinary SEND. */
  71 #define MLX5_TXQ_INLINE_MAX "txq_inline_max"
  72
  73 /* Device parameter to configure minimal data size to inline. */
  74 #define MLX5_TXQ_INLINE_MIN "txq_inline_min"
  75
  76 /* Device parameter to limit packet size to inline with Enhanced MPW. */
  77 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw"
  78
  79 /*
  80  * Device parameter to configure the number of TX queues threshold for
  81  * enabling inline send.
  82  */
  83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
  84
  85 /*
  86  * Device parameter to configure the number of TX queues threshold for
  87  * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines).
  88  */
  89 #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
  90
  91 /* Device parameter to enable multi-packet send WQEs. */
  92 #define MLX5_TXQ_MPW_EN "txq_mpw_en"
  93
  94 /*
  95  * Device parameter to force doorbell register mapping
  96  * to non-cahed region eliminating the extra write memory barrier.
  97  */
  98 #define MLX5_TX_DB_NC "tx_db_nc"
  99
 100 /*
 101  * Device parameter to include 2 dsegs in the title WQEBB.
 102  * Deprecated, ignored.
 103  */
 104 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
 105
 106 /*
 107  * Device parameter to limit the size of inlining packet.
 108  * Deprecated, ignored.
 109  */
 110 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
 111
 112 /*
 113  * Device parameter to enable Tx scheduling on timestamps
 114  * and specify the packet pacing granularity in nanoseconds.
 115  */
 116 #define MLX5_TX_PP "tx_pp"
 117
 118 /*
 119  * Device parameter to specify skew in nanoseconds on Tx datapath,
 120  * it represents the time between SQ start WQE processing and
 121  * appearing actual packet data on the wire.
 122  */
 123 #define MLX5_TX_SKEW "tx_skew"
 124
 125 /*
 126  * Device parameter to enable hardware Tx vector.
 127  * Deprecated, ignored (no vectorized Tx routines anymore).
 128  */
 129 #define MLX5_TX_VEC_EN "tx_vec_en"
 130
 131 /* Device parameter to enable hardware Rx vector. */
 132 #define MLX5_RX_VEC_EN "rx_vec_en"
 133
 134 /* Allow L3 VXLAN flow creation. */
 135 #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
 136
 137 /* Activate DV E-Switch flow steering. */
 138 #define MLX5_DV_ESW_EN "dv_esw_en"
 139
 140 /* Activate DV flow steering. */
 141 #define MLX5_DV_FLOW_EN "dv_flow_en"
 142
 143 /* Enable extensive flow metadata support. */
 144 #define MLX5_DV_XMETA_EN "dv_xmeta_en"
 145
 146 /* Device parameter to let the user manage the lacp traffic of bonded device */
 147 #define MLX5_LACP_BY_USER "lacp_by_user"
 148
 149 /* Activate Netlink support in VF mode. */
 150 #define MLX5_VF_NL_EN "vf_nl_en"
 151
 152 /* Enable extending memsegs when creating a MR. */
 153 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
 154
 155 /* Select port representors to instantiate. */
 156 #define MLX5_REPRESENTOR "representor"
 157
 158 /* Device parameter to configure the maximum number of dump files per queue. */
 159 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num"
 160
 161 /* Configure timeout of LRO session (in microseconds). */
 162 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec"
 163
 164 /*
 165  * Device parameter to configure the total data buffer size for a single
 166  * hairpin queue (logarithm value).
 167  */
 168 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz"
 169
 170 /* Flow memory reclaim mode. */
 171 #define MLX5_RECLAIM_MEM "reclaim_mem_mode"
 172
 173 /* The default memory allocator used in PMD. */
 174 #define MLX5_SYS_MEM_EN "sys_mem_en"
 175 /* Decap will be used or not. */
 176 #define MLX5_DECAP_EN "decap_en"
 177
 178 /* Device parameter to configure allow or prevent duplicate rules pattern. */
 179 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern"
 180
 181 /* Shared memory between primary and secondary processes. */
 182 struct mlx5_shared_data *mlx5_shared_data;
 183
 184 /** Driver-specific log messages type. */
 185 int mlx5_logtype;
 186
 187 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list =
 188                                                 LIST_HEAD_INITIALIZER();
 189 static pthread_mutex_t mlx5_dev_ctx_list_mutex;
 190 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = {
 191 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
 192         [MLX5_IPOOL_DECAP_ENCAP] = {
 193                 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource),
 194                 .trunk_size = 64,
 195                 .grow_trunk = 3,
 196                 .grow_shift = 2,
 197                 .need_lock = 1,
 198                 .release_mem_en = 1,
 199                 .malloc = mlx5_malloc,
 200                 .free = mlx5_free,
 201                 .type = "mlx5_encap_decap_ipool",
 202         },
 203         [MLX5_IPOOL_PUSH_VLAN] = {
 204                 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource),
 205                 .trunk_size = 64,
 206                 .grow_trunk = 3,
 207                 .grow_shift = 2,
 208                 .need_lock = 1,
 209                 .release_mem_en = 1,
 210                 .malloc = mlx5_malloc,
 211                 .free = mlx5_free,
 212                 .type = "mlx5_push_vlan_ipool",
 213         },
 214         [MLX5_IPOOL_TAG] = {
 215                 .size = sizeof(struct mlx5_flow_dv_tag_resource),
 216                 .trunk_size = 64,
 217                 .grow_trunk = 3,
 218                 .grow_shift = 2,
 219                 .need_lock = 1,
 220                 .release_mem_en = 1,
 221                 .malloc = mlx5_malloc,
 222                 .free = mlx5_free,
 223                 .type = "mlx5_tag_ipool",
 224         },
 225         [MLX5_IPOOL_PORT_ID] = {
 226                 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource),
 227                 .trunk_size = 64,
 228                 .grow_trunk = 3,
 229                 .grow_shift = 2,
 230                 .need_lock = 1,
 231                 .release_mem_en = 1,
 232                 .malloc = mlx5_malloc,
 233                 .free = mlx5_free,
 234                 .type = "mlx5_port_id_ipool",
 235         },
 236         [MLX5_IPOOL_JUMP] = {
 237                 .size = sizeof(struct mlx5_flow_tbl_data_entry),
 238                 .trunk_size = 64,
 239                 .grow_trunk = 3,
 240                 .grow_shift = 2,
 241                 .need_lock = 1,
 242                 .release_mem_en = 1,
 243                 .malloc = mlx5_malloc,
 244                 .free = mlx5_free,
 245                 .type = "mlx5_jump_ipool",
 246         },
 247         [MLX5_IPOOL_SAMPLE] = {
 248                 .size = sizeof(struct mlx5_flow_dv_sample_resource),
 249                 .trunk_size = 64,
 250                 .grow_trunk = 3,
 251                 .grow_shift = 2,
 252                 .need_lock = 1,
 253                 .release_mem_en = 1,
 254                 .malloc = mlx5_malloc,
 255                 .free = mlx5_free,
 256                 .type = "mlx5_sample_ipool",
 257         },
 258         [MLX5_IPOOL_DEST_ARRAY] = {
 259                 .size = sizeof(struct mlx5_flow_dv_dest_array_resource),
 260                 .trunk_size = 64,
 261                 .grow_trunk = 3,
 262                 .grow_shift = 2,
 263                 .need_lock = 1,
 264                 .release_mem_en = 1,
 265                 .malloc = mlx5_malloc,
 266                 .free = mlx5_free,
 267                 .type = "mlx5_dest_array_ipool",
 268         },
 269         [MLX5_IPOOL_TUNNEL_ID] = {
 270                 .size = sizeof(struct mlx5_flow_tunnel),
 271                 .trunk_size = MLX5_MAX_TUNNELS,
 272                 .need_lock = 1,
 273                 .release_mem_en = 1,
 274                 .type = "mlx5_tunnel_offload",
 275         },
 276         [MLX5_IPOOL_TNL_TBL_ID] = {
 277                 .size = 0,
 278                 .need_lock = 1,
 279                 .type = "mlx5_flow_tnl_tbl_ipool",
 280         },
 281 #endif
 282         [MLX5_IPOOL_MTR] = {
 283                 /**
 284                  * The ipool index should grow continually from small to big,
 285                  * for meter idx, so not set grow_trunk to avoid meter index
 286                  * not jump continually.
 287                  */
 288                 .size = sizeof(struct mlx5_legacy_flow_meter),
 289                 .trunk_size = 64,
 290                 .need_lock = 1,
 291                 .release_mem_en = 1,
 292                 .malloc = mlx5_malloc,
 293                 .free = mlx5_free,
 294                 .type = "mlx5_meter_ipool",
 295         },
 296         [MLX5_IPOOL_MCP] = {
 297                 .size = sizeof(struct mlx5_flow_mreg_copy_resource),
 298                 .trunk_size = 64,
 299                 .grow_trunk = 3,
 300                 .grow_shift = 2,
 301                 .need_lock = 1,
 302                 .release_mem_en = 1,
 303                 .malloc = mlx5_malloc,
 304                 .free = mlx5_free,
 305                 .type = "mlx5_mcp_ipool",
 306         },
 307         [MLX5_IPOOL_HRXQ] = {
 308                 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN),
 309                 .trunk_size = 64,
 310                 .grow_trunk = 3,
 311                 .grow_shift = 2,
 312                 .need_lock = 1,
 313                 .release_mem_en = 1,
 314                 .malloc = mlx5_malloc,
 315                 .free = mlx5_free,
 316                 .type = "mlx5_hrxq_ipool",
 317         },
 318         [MLX5_IPOOL_MLX5_FLOW] = {
 319                 /*
 320                  * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows.
 321                  * It set in run time according to PCI function configuration.
 322                  */
 323                 .size = 0,
 324                 .trunk_size = 64,
 325                 .grow_trunk = 3,
 326                 .grow_shift = 2,
 327                 .need_lock = 1,
 328                 .release_mem_en = 0,
 329                 .per_core_cache = 1 << 19,
 330                 .malloc = mlx5_malloc,
 331                 .free = mlx5_free,
 332                 .type = "mlx5_flow_handle_ipool",
 333         },
 334         [MLX5_IPOOL_RTE_FLOW] = {
 335                 .size = sizeof(struct rte_flow),
 336                 .trunk_size = 4096,
 337                 .need_lock = 1,
 338                 .release_mem_en = 1,
 339                 .malloc = mlx5_malloc,
 340                 .free = mlx5_free,
 341                 .type = "rte_flow_ipool",
 342         },
 343         [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = {
 344                 .size = 0,
 345                 .need_lock = 1,
 346                 .type = "mlx5_flow_rss_id_ipool",
 347         },
 348         [MLX5_IPOOL_RSS_SHARED_ACTIONS] = {
 349                 .size = sizeof(struct mlx5_shared_action_rss),
 350                 .trunk_size = 64,
 351                 .grow_trunk = 3,
 352                 .grow_shift = 2,
 353                 .need_lock = 1,
 354                 .release_mem_en = 1,
 355                 .malloc = mlx5_malloc,
 356                 .free = mlx5_free,
 357                 .type = "mlx5_shared_action_rss",
 358         },
 359         [MLX5_IPOOL_MTR_POLICY] = {
 360                 /**
 361                  * The ipool index should grow continually from small to big,
 362                  * for policy idx, so not set grow_trunk to avoid policy index
 363                  * not jump continually.
 364                  */
 365                 .size = sizeof(struct mlx5_flow_meter_sub_policy),
 366                 .trunk_size = 64,
 367                 .need_lock = 1,
 368                 .release_mem_en = 1,
 369                 .malloc = mlx5_malloc,
 370                 .free = mlx5_free,
 371                 .type = "mlx5_meter_policy_ipool",
 372         },
 373 };
 374
 375
 376 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512
 377 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16
 378
 379 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024
 380
 381 /**
 382  * Decide whether representor ID is a HPF(host PF) port on BF2.
 383  *
 384  * @param dev
 385  *   Pointer to Ethernet device structure.
 386  *
 387  * @return
 388  *   Non-zero if HPF, otherwise 0.
 389  */
 390 bool
 391 mlx5_is_hpf(struct rte_eth_dev *dev)
 392 {
 393         struct mlx5_priv *priv = dev->data->dev_private;
 394         uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id);
 395         int type = MLX5_REPRESENTOR_TYPE(priv->representor_id);
 396
 397         return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF &&
 398                MLX5_REPRESENTOR_REPR(-1) == repr;
 399 }
 400
 401 /**
 402  * Initialize the ASO aging management structure.
 403  *
 404  * @param[in] sh
 405  *   Pointer to mlx5_dev_ctx_shared object to free
 406  *
 407  * @return
 408  *   0 on success, a negative errno value otherwise and rte_errno is set.
 409  */
 410 int
 411 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh)
 412 {
 413         int err;
 414
 415         if (sh->aso_age_mng)
 416                 return 0;
 417         sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng),
 418                                       RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 419         if (!sh->aso_age_mng) {
 420                 DRV_LOG(ERR, "aso_age_mng allocation was failed.");
 421                 rte_errno = ENOMEM;
 422                 return -ENOMEM;
 423         }
 424         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT);
 425         if (err) {
 426                 mlx5_free(sh->aso_age_mng);
 427                 return -1;
 428         }
 429         rte_spinlock_init(&sh->aso_age_mng->resize_sl);
 430         rte_spinlock_init(&sh->aso_age_mng->free_sl);
 431         LIST_INIT(&sh->aso_age_mng->free);
 432         return 0;
 433 }
 434
 435 /**
 436  * Close and release all the resources of the ASO aging management structure.
 437  *
 438  * @param[in] sh
 439  *   Pointer to mlx5_dev_ctx_shared object to free.
 440  */
 441 static void
 442 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh)
 443 {
 444         int i, j;
 445
 446         mlx5_aso_flow_hit_queue_poll_stop(sh);
 447         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT);
 448         if (sh->aso_age_mng->pools) {
 449                 struct mlx5_aso_age_pool *pool;
 450
 451                 for (i = 0; i < sh->aso_age_mng->next; ++i) {
 452                         pool = sh->aso_age_mng->pools[i];
 453                         claim_zero(mlx5_devx_cmd_destroy
 454                                                 (pool->flow_hit_aso_obj));
 455                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j)
 456                                 if (pool->actions[j].dr_action)
 457                                         claim_zero
 458                                             (mlx5_flow_os_destroy_flow_action
 459                                               (pool->actions[j].dr_action));
 460                         mlx5_free(pool);
 461                 }
 462                 mlx5_free(sh->aso_age_mng->pools);
 463         }
 464         mlx5_free(sh->aso_age_mng);
 465 }
 466
 467 /**
 468  * Initialize the shared aging list information per port.
 469  *
 470  * @param[in] sh
 471  *   Pointer to mlx5_dev_ctx_shared object.
 472  */
 473 static void
 474 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh)
 475 {
 476         uint32_t i;
 477         struct mlx5_age_info *age_info;
 478
 479         for (i = 0; i < sh->max_port; i++) {
 480                 age_info = &sh->port[i].age_info;
 481                 age_info->flags = 0;
 482                 TAILQ_INIT(&age_info->aged_counters);
 483                 LIST_INIT(&age_info->aged_aso);
 484                 rte_spinlock_init(&age_info->aged_sl);
 485                 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
 486         }
 487 }
 488
 489 /**
 490  * Initialize the counters management structure.
 491  *
 492  * @param[in] sh
 493  *   Pointer to mlx5_dev_ctx_shared object to free
 494  */
 495 static void
 496 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh)
 497 {
 498         int i;
 499
 500         memset(&sh->cmng, 0, sizeof(sh->cmng));
 501         TAILQ_INIT(&sh->cmng.flow_counters);
 502         sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET;
 503         sh->cmng.max_id = -1;
 504         sh->cmng.last_pool_idx = POOL_IDX_INVALID;
 505         rte_spinlock_init(&sh->cmng.pool_update_sl);
 506         for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) {
 507                 TAILQ_INIT(&sh->cmng.counters[i]);
 508                 rte_spinlock_init(&sh->cmng.csl[i]);
 509         }
 510 }
 511
 512 /**
 513  * Destroy all the resources allocated for a counter memory management.
 514  *
 515  * @param[in] mng
 516  *   Pointer to the memory management structure.
 517  */
 518 static void
 519 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng)
 520 {
 521         uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data;
 522
 523         LIST_REMOVE(mng, next);
 524         claim_zero(mlx5_devx_cmd_destroy(mng->dm));
 525         claim_zero(mlx5_os_umem_dereg(mng->umem));
 526         mlx5_free(mem);
 527 }
 528
 529 /**
 530  * Close and release all the resources of the counters management.
 531  *
 532  * @param[in] sh
 533  *   Pointer to mlx5_dev_ctx_shared object to free.
 534  */
 535 static void
 536 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh)
 537 {
 538         struct mlx5_counter_stats_mem_mng *mng;
 539         int i, j;
 540         int retries = 1024;
 541
 542         rte_errno = 0;
 543         while (--retries) {
 544                 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh);
 545                 if (rte_errno != EINPROGRESS)
 546                         break;
 547                 rte_pause();
 548         }
 549
 550         if (sh->cmng.pools) {
 551                 struct mlx5_flow_counter_pool *pool;
 552                 uint16_t n_valid = sh->cmng.n_valid;
 553                 bool fallback = sh->cmng.counter_fallback;
 554
 555                 for (i = 0; i < n_valid; ++i) {
 556                         pool = sh->cmng.pools[i];
 557                         if (!fallback && pool->min_dcs)
 558                                 claim_zero(mlx5_devx_cmd_destroy
 559                                                                (pool->min_dcs));
 560                         for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) {
 561                                 struct mlx5_flow_counter *cnt =
 562                                                 MLX5_POOL_GET_CNT(pool, j);
 563
 564                                 if (cnt->action)
 565                                         claim_zero
 566                                          (mlx5_flow_os_destroy_flow_action
 567                                           (cnt->action));
 568                                 if (fallback && MLX5_POOL_GET_CNT
 569                                     (pool, j)->dcs_when_free)
 570                                         claim_zero(mlx5_devx_cmd_destroy
 571                                                    (cnt->dcs_when_free));
 572                         }
 573                         mlx5_free(pool);
 574                 }
 575                 mlx5_free(sh->cmng.pools);
 576         }
 577         mng = LIST_FIRST(&sh->cmng.mem_mngs);
 578         while (mng) {
 579                 mlx5_flow_destroy_counter_stat_mem_mng(mng);
 580                 mng = LIST_FIRST(&sh->cmng.mem_mngs);
 581         }
 582         memset(&sh->cmng, 0, sizeof(sh->cmng));
 583 }
 584
 585 /**
 586  * Initialize the aso flow meters management structure.
 587  *
 588  * @param[in] sh
 589  *   Pointer to mlx5_dev_ctx_shared object to free
 590  */
 591 int
 592 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh)
 593 {
 594         if (!sh->mtrmng) {
 595                 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO,
 596                         sizeof(*sh->mtrmng),
 597                         RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 598                 if (!sh->mtrmng) {
 599                         DRV_LOG(ERR,
 600                         "meter management allocation was failed.");
 601                         rte_errno = ENOMEM;
 602                         return -ENOMEM;
 603                 }
 604                 if (sh->meter_aso_en) {
 605                         rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl);
 606                         LIST_INIT(&sh->mtrmng->pools_mng.meters);
 607                 }
 608                 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
 609         }
 610         return 0;
 611 }
 612
 613 /**
 614  * Close and release all the resources of
 615  * the ASO flow meter management structure.
 616  *
 617  * @param[in] sh
 618  *   Pointer to mlx5_dev_ctx_shared object to free.
 619  */
 620 static void
 621 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh)
 622 {
 623         struct mlx5_aso_mtr_pool *mtr_pool;
 624         struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng;
 625         uint32_t idx;
 626 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 627         struct mlx5_aso_mtr *aso_mtr;
 628         int i;
 629 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 630
 631         if (sh->meter_aso_en) {
 632                 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER);
 633                 idx = mtrmng->pools_mng.n_valid;
 634                 while (idx--) {
 635                         mtr_pool = mtrmng->pools_mng.pools[idx];
 636 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
 637                         for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) {
 638                                 aso_mtr = &mtr_pool->mtrs[i];
 639                                 if (aso_mtr->fm.meter_action)
 640                                         claim_zero
 641                                         (mlx5_glue->destroy_flow_action
 642                                         (aso_mtr->fm.meter_action));
 643                         }
 644 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
 645                         claim_zero(mlx5_devx_cmd_destroy
 646                                                 (mtr_pool->devx_obj));
 647                         mtrmng->pools_mng.n_valid--;
 648                         mlx5_free(mtr_pool);
 649                 }
 650                 mlx5_free(sh->mtrmng->pools_mng.pools);
 651         }
 652         mlx5_free(sh->mtrmng);
 653         sh->mtrmng = NULL;
 654 }
 655
 656 /* Send FLOW_AGED event if needed. */
 657 void
 658 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh)
 659 {
 660         struct mlx5_age_info *age_info;
 661         uint32_t i;
 662
 663         for (i = 0; i < sh->max_port; i++) {
 664                 age_info = &sh->port[i].age_info;
 665                 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW))
 666                         continue;
 667                 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW);
 668                 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) {
 669                         MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER);
 670                         rte_eth_dev_callback_process
 671                                 (&rte_eth_devices[sh->port[i].devx_ih_port_id],
 672                                 RTE_ETH_EVENT_FLOW_AGED, NULL);
 673                 }
 674         }
 675 }
 676
 677 /*
 678  * Initialize the ASO connection tracking structure.
 679  *
 680  * @param[in] sh
 681  *   Pointer to mlx5_dev_ctx_shared object.
 682  *
 683  * @return
 684  *   0 on success, a negative errno value otherwise and rte_errno is set.
 685  */
 686 int
 687 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh)
 688 {
 689         int err;
 690
 691         if (sh->ct_mng)
 692                 return 0;
 693         sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng),
 694                                  RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
 695         if (!sh->ct_mng) {
 696                 DRV_LOG(ERR, "ASO CT management allocation failed.");
 697                 rte_errno = ENOMEM;
 698                 return -rte_errno;
 699         }
 700         err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 701         if (err) {
 702                 mlx5_free(sh->ct_mng);
 703                 /* rte_errno should be extracted from the failure. */
 704                 rte_errno = EINVAL;
 705                 return -rte_errno;
 706         }
 707         rte_spinlock_init(&sh->ct_mng->ct_sl);
 708         rte_rwlock_init(&sh->ct_mng->resize_rwl);
 709         LIST_INIT(&sh->ct_mng->free_cts);
 710         return 0;
 711 }
 712
 713 /*
 714  * Close and release all the resources of the
 715  * ASO connection tracking management structure.
 716  *
 717  * @param[in] sh
 718  *   Pointer to mlx5_dev_ctx_shared object to free.
 719  */
 720 static void
 721 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh)
 722 {
 723         struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng;
 724         struct mlx5_aso_ct_pool *ct_pool;
 725         struct mlx5_aso_ct_action *ct;
 726         uint32_t idx;
 727         uint32_t val;
 728         uint32_t cnt;
 729         int i;
 730
 731         mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING);
 732         idx = mng->next;
 733         while (idx--) {
 734                 cnt = 0;
 735                 ct_pool = mng->pools[idx];
 736                 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
 737                         ct = &ct_pool->actions[i];
 738                         val = __atomic_fetch_sub(&ct->refcnt, 1,
 739                                                  __ATOMIC_RELAXED);
 740                         MLX5_ASSERT(val == 1);
 741                         if (val > 1)
 742                                 cnt++;
 743 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
 744                         if (ct->dr_action_orig)
 745                                 claim_zero(mlx5_glue->destroy_flow_action
 746                                                         (ct->dr_action_orig));
 747                         if (ct->dr_action_rply)
 748                                 claim_zero(mlx5_glue->destroy_flow_action
 749                                                         (ct->dr_action_rply));
 750 #endif
 751                 }
 752                 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj));
 753                 if (cnt) {
 754                         DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u",
 755                                 cnt, i);
 756                 }
 757                 mlx5_free(ct_pool);
 758                 /* in case of failure. */
 759                 mng->next--;
 760         }
 761         mlx5_free(mng->pools);
 762         mlx5_free(mng);
 763         /* Management structure must be cleared to 0s during allocation. */
 764         sh->ct_mng = NULL;
 765 }
 766
 767 /**
 768  * Initialize the flow resources' indexed mempool.
 769  *
 770  * @param[in] sh
 771  *   Pointer to mlx5_dev_ctx_shared object.
 772  * @param[in] config
 773  *   Pointer to user dev config.
 774  */
 775 static void
 776 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh,
 777                        const struct mlx5_dev_config *config)
 778 {
 779         uint8_t i;
 780         struct mlx5_indexed_pool_config cfg;
 781
 782         for (i = 0; i < MLX5_IPOOL_MAX; ++i) {
 783                 cfg = mlx5_ipool_cfg[i];
 784                 switch (i) {
 785                 default:
 786                         break;
 787                 /*
 788                  * Set MLX5_IPOOL_MLX5_FLOW ipool size
 789                  * according to PCI function flow configuration.
 790                  */
 791                 case MLX5_IPOOL_MLX5_FLOW:
 792                         cfg.size = config->dv_flow_en ?
 793                                 sizeof(struct mlx5_flow_handle) :
 794                                 MLX5_FLOW_HANDLE_VERBS_SIZE;
 795                         break;
 796                 }
 797                 if (config->reclaim_mode) {
 798                         cfg.release_mem_en = 1;
 799                         cfg.per_core_cache = 0;
 800                 }
 801                 sh->ipool[i] = mlx5_ipool_create(&cfg);
 802         }
 803 }
 804
 805
 806 /**
 807  * Release the flow resources' indexed mempool.
 808  *
 809  * @param[in] sh
 810  *   Pointer to mlx5_dev_ctx_shared object.
 811  */
 812 static void
 813 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh)
 814 {
 815         uint8_t i;
 816
 817         for (i = 0; i < MLX5_IPOOL_MAX; ++i)
 818                 mlx5_ipool_destroy(sh->ipool[i]);
 819         for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i)
 820                 if (sh->mdh_ipools[i])
 821                         mlx5_ipool_destroy(sh->mdh_ipools[i]);
 822 }
 823
 824 /*
 825  * Check if dynamic flex parser for eCPRI already exists.
 826  *
 827  * @param dev
 828  *   Pointer to Ethernet device structure.
 829  *
 830  * @return
 831  *   true on exists, false on not.
 832  */
 833 bool
 834 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev)
 835 {
 836         struct mlx5_priv *priv = dev->data->dev_private;
 837         struct mlx5_flex_parser_profiles *prf =
 838                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 839
 840         return !!prf->obj;
 841 }
 842
 843 /*
 844  * Allocation of a flex parser for eCPRI. Once created, this parser related
 845  * resources will be held until the device is closed.
 846  *
 847  * @param dev
 848  *   Pointer to Ethernet device structure.
 849  *
 850  * @return
 851  *   0 on success, a negative errno value otherwise and rte_errno is set.
 852  */
 853 int
 854 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev)
 855 {
 856         struct mlx5_priv *priv = dev->data->dev_private;
 857         struct mlx5_flex_parser_profiles *prf =
 858                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 859         struct mlx5_devx_graph_node_attr node = {
 860                 .modify_field_select = 0,
 861         };
 862         uint32_t ids[8];
 863         int ret;
 864
 865         if (!priv->config.hca_attr.parse_graph_flex_node) {
 866                 DRV_LOG(ERR, "Dynamic flex parser is not supported "
 867                         "for device %s.", priv->dev_data->name);
 868                 return -ENOTSUP;
 869         }
 870         node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED;
 871         /* 8 bytes now: 4B common header + 4B message body header. */
 872         node.header_length_base_value = 0x8;
 873         /* After MAC layer: Ether / VLAN. */
 874         node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC;
 875         /* Type of compared condition should be 0xAEFE in the L2 layer. */
 876         node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI;
 877         /* Sample #0: type in common header. */
 878         node.sample[0].flow_match_sample_en = 1;
 879         /* Fixed offset. */
 880         node.sample[0].flow_match_sample_offset_mode = 0x0;
 881         /* Only the 2nd byte will be used. */
 882         node.sample[0].flow_match_sample_field_base_offset = 0x0;
 883         /* Sample #1: message payload. */
 884         node.sample[1].flow_match_sample_en = 1;
 885         /* Fixed offset. */
 886         node.sample[1].flow_match_sample_offset_mode = 0x0;
 887         /*
 888          * Only the first two bytes will be used right now, and its offset will
 889          * start after the common header that with the length of a DW(u32).
 890          */
 891         node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t);
 892         prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->ctx, &node);
 893         if (!prf->obj) {
 894                 DRV_LOG(ERR, "Failed to create flex parser node object.");
 895                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 896         }
 897         prf->num = 2;
 898         ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num);
 899         if (ret) {
 900                 DRV_LOG(ERR, "Failed to query sample IDs.");
 901                 return (rte_errno == 0) ? -ENODEV : -rte_errno;
 902         }
 903         prf->offset[0] = 0x0;
 904         prf->offset[1] = sizeof(uint32_t);
 905         prf->ids[0] = ids[0];
 906         prf->ids[1] = ids[1];
 907         return 0;
 908 }
 909
 910 /*
 911  * Destroy the flex parser node, including the parser itself, input / output
 912  * arcs and DW samples. Resources could be reused then.
 913  *
 914  * @param dev
 915  *   Pointer to Ethernet device structure.
 916  */
 917 static void
 918 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev)
 919 {
 920         struct mlx5_priv *priv = dev->data->dev_private;
 921         struct mlx5_flex_parser_profiles *prf =
 922                                 &priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0];
 923
 924         if (prf->obj)
 925                 mlx5_devx_cmd_destroy(prf->obj);
 926         prf->obj = NULL;
 927 }
 928
 929 /*
 930  * Allocate Rx and Tx UARs in robust fashion.
 931  * This routine handles the following UAR allocation issues:
 932  *
 933  *  - tries to allocate the UAR with the most appropriate memory
 934  *    mapping type from the ones supported by the host
 935  *
 936  *  - tries to allocate the UAR with non-NULL base address
 937  *    OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
 938  *    UAR base address if UAR was not the first object in the UAR page.
 939  *    It caused the PMD failure and we should try to get another UAR
 940  *    till we get the first one with non-NULL base address returned.
 941  */
 942 static int
 943 mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,
 944                      const struct mlx5_dev_config *config)
 945 {
 946         uint32_t uar_mapping, retry;
 947         int err = 0;
 948         void *base_addr;
 949
 950         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
 951 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 952                 /* Control the mapping type according to the settings. */
 953                 uar_mapping = (config->dbnc == MLX5_TXDB_NCACHED) ?
 954                               MLX5DV_UAR_ALLOC_TYPE_NC :
 955                               MLX5DV_UAR_ALLOC_TYPE_BF;
 956 #else
 957                 RTE_SET_USED(config);
 958                 /*
 959                  * It seems we have no way to control the memory mapping type
 960                  * for the UAR, the default "Write-Combining" type is supposed.
 961                  * The UAR initialization on queue creation queries the
 962                  * actual mapping type done by Verbs/kernel and setups the
 963                  * PMD datapath accordingly.
 964                  */
 965                 uar_mapping = 0;
 966 #endif
 967                 sh->tx_uar = mlx5_glue->devx_alloc_uar(sh->ctx, uar_mapping);
 968 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
 969                 if (!sh->tx_uar &&
 970                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
 971                         if (config->dbnc == MLX5_TXDB_CACHED ||
 972                             config->dbnc == MLX5_TXDB_HEURISTIC)
 973                                 DRV_LOG(WARNING, "Devarg tx_db_nc setting "
 974                                                  "is not supported by DevX");
 975                         /*
 976                          * In some environments like virtual machine
 977                          * the Write Combining mapped might be not supported
 978                          * and UAR allocation fails. We try "Non-Cached"
 979                          * mapping for the case. The tx_burst routines take
 980                          * the UAR mapping type into account on UAR setup
 981                          * on queue creation.
 982                          */
 983                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)");
 984                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
 985                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 986                                                         (sh->ctx, uar_mapping);
 987                 } else if (!sh->tx_uar &&
 988                            uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
 989                         if (config->dbnc == MLX5_TXDB_NCACHED)
 990                                 DRV_LOG(WARNING, "Devarg tx_db_nc settings "
 991                                                  "is not supported by DevX");
 992                         /*
 993                          * If Verbs/kernel does not support "Non-Cached"
 994                          * try the "Write-Combining".
 995                          */
 996                         DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)");
 997                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
 998                         sh->tx_uar = mlx5_glue->devx_alloc_uar
 999                                                         (sh->ctx, uar_mapping);
1000                 }
1001 #endif
1002                 if (!sh->tx_uar) {
1003                         DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (BF/NC)");
1004                         err = ENOMEM;
1005                         goto exit;
1006                 }
1007                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->tx_uar);
1008                 if (base_addr)
1009                         break;
1010                 /*
1011                  * The UARs are allocated by rdma_core within the
1012                  * IB device context, on context closure all UARs
1013                  * will be freed, should be no memory/object leakage.
1014                  */
1015                 DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR");
1016                 sh->tx_uar = NULL;
1017         }
1018         /* Check whether we finally succeeded with valid UAR allocation. */
1019         if (!sh->tx_uar) {
1020                 DRV_LOG(ERR, "Failed to allocate Tx DevX UAR (NULL base)");
1021                 err = ENOMEM;
1022                 goto exit;
1023         }
1024         for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
1025                 uar_mapping = 0;
1026                 sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1027                                                         (sh->ctx, uar_mapping);
1028 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
1029                 if (!sh->devx_rx_uar &&
1030                     uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
1031                         /*
1032                          * Rx UAR is used to control interrupts only,
1033                          * should be no datapath noticeable impact,
1034                          * can try "Non-Cached" mapping safely.
1035                          */
1036                         DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)");
1037                         uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
1038                         sh->devx_rx_uar = mlx5_glue->devx_alloc_uar
1039                                                         (sh->ctx, uar_mapping);
1040                 }
1041 #endif
1042                 if (!sh->devx_rx_uar) {
1043                         DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (BF/NC)");
1044                         err = ENOMEM;
1045                         goto exit;
1046                 }
1047                 base_addr = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
1048                 if (base_addr)
1049                         break;
1050                 /*
1051                  * The UARs are allocated by rdma_core within the
1052                  * IB device context, on context closure all UARs
1053                  * will be freed, should be no memory/object leakage.
1054                  */
1055                 DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR");
1056                 sh->devx_rx_uar = NULL;
1057         }
1058         /* Check whether we finally succeeded with valid UAR allocation. */
1059         if (!sh->devx_rx_uar) {
1060                 DRV_LOG(ERR, "Failed to allocate Rx DevX UAR (NULL base)");
1061                 err = ENOMEM;
1062         }
1063 exit:
1064         return err;
1065 }
1066
1067 /**
1068  * Allocate shared device context. If there is multiport device the
1069  * master and representors will share this context, if there is single
1070  * port dedicated device, the context will be used by only given
1071  * port due to unification.
1072  *
1073  * Routine first searches the context for the specified device name,
1074  * if found the shared context assumed and reference counter is incremented.
1075  * If no context found the new one is created and initialized with specified
1076  * device context and parameters.
1077  *
1078  * @param[in] spawn
1079  *   Pointer to the device attributes (name, port, etc).
1080  * @param[in] config
1081  *   Pointer to device configuration structure.
1082  *
1083  * @return
1084  *   Pointer to mlx5_dev_ctx_shared object on success,
1085  *   otherwise NULL and rte_errno is set.
1086  */
1087 struct mlx5_dev_ctx_shared *
1088 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn,
1089                            const struct mlx5_dev_config *config)
1090 {
1091         struct mlx5_dev_ctx_shared *sh;
1092         int err = 0;
1093         uint32_t i;
1094         struct mlx5_devx_tis_attr tis_attr = { 0 };
1095
1096         MLX5_ASSERT(spawn);
1097         /* Secondary process should not create the shared context. */
1098         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1099         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1100         /* Search for IB context by device name. */
1101         LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) {
1102                 if (!strcmp(sh->ibdev_name,
1103                         mlx5_os_get_dev_device_name(spawn->phys_dev))) {
1104                         sh->refcnt++;
1105                         goto exit;
1106                 }
1107         }
1108         /* No device found, we have to create new shared context. */
1109         MLX5_ASSERT(spawn->max_port);
1110         sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE,
1111                          sizeof(struct mlx5_dev_ctx_shared) +
1112                          spawn->max_port *
1113                          sizeof(struct mlx5_dev_shared_port),
1114                          RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
1115         if (!sh) {
1116                 DRV_LOG(ERR, "shared context allocation failure");
1117                 rte_errno  = ENOMEM;
1118                 goto exit;
1119         }
1120         if (spawn->bond_info)
1121                 sh->bond = *spawn->bond_info;
1122         err = mlx5_os_open_device(spawn, config, sh);
1123         if (!sh->ctx)
1124                 goto error;
1125         err = mlx5_os_get_dev_attr(sh->ctx, &sh->device_attr);
1126         if (err) {
1127                 DRV_LOG(DEBUG, "mlx5_os_get_dev_attr() failed");
1128                 goto error;
1129         }
1130         sh->refcnt = 1;
1131         sh->max_port = spawn->max_port;
1132         strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->ctx),
1133                 sizeof(sh->ibdev_name) - 1);
1134         strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->ctx),
1135                 sizeof(sh->ibdev_path) - 1);
1136         /*
1137          * Setting port_id to max unallowed value means
1138          * there is no interrupt subhandler installed for
1139          * the given port index i.
1140          */
1141         for (i = 0; i < sh->max_port; i++) {
1142                 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
1143                 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS;
1144         }
1145         sh->pd = mlx5_os_alloc_pd(sh->ctx);
1146         if (sh->pd == NULL) {
1147                 DRV_LOG(ERR, "PD allocation failure");
1148                 err = ENOMEM;
1149                 goto error;
1150         }
1151         if (sh->devx) {
1152                 err = mlx5_os_get_pdn(sh->pd, &sh->pdn);
1153                 if (err) {
1154                         DRV_LOG(ERR, "Fail to extract pdn from PD");
1155                         goto error;
1156                 }
1157                 sh->td = mlx5_devx_cmd_create_td(sh->ctx);
1158                 if (!sh->td) {
1159                         DRV_LOG(ERR, "TD allocation failure");
1160                         err = ENOMEM;
1161                         goto error;
1162                 }
1163                 tis_attr.transport_domain = sh->td->id;
1164                 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr);
1165                 if (!sh->tis) {
1166                         DRV_LOG(ERR, "TIS allocation failure");
1167                         err = ENOMEM;
1168                         goto error;
1169                 }
1170                 err = mlx5_alloc_rxtx_uars(sh, config);
1171                 if (err)
1172                         goto error;
1173                 MLX5_ASSERT(sh->tx_uar);
1174                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar));
1175
1176                 MLX5_ASSERT(sh->devx_rx_uar);
1177                 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar));
1178         }
1179 #ifndef RTE_ARCH_64
1180         /* Initialize UAR access locks for 32bit implementations. */
1181         rte_spinlock_init(&sh->uar_lock_cq);
1182         for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
1183                 rte_spinlock_init(&sh->uar_lock[i]);
1184 #endif
1185         /*
1186          * Once the device is added to the list of memory event
1187          * callback, its global MR cache table cannot be expanded
1188          * on the fly because of deadlock. If it overflows, lookup
1189          * should be done by searching MR list linearly, which is slow.
1190          *
1191          * At this point the device is not added to the memory
1192          * event list yet, context is just being created.
1193          */
1194         err = mlx5_mr_btree_init(&sh->share_cache.cache,
1195                                  MLX5_MR_BTREE_CACHE_N * 2,
1196                                  spawn->pci_dev->device.numa_node);
1197         if (err) {
1198                 err = rte_errno;
1199                 goto error;
1200         }
1201         mlx5_os_set_reg_mr_cb(&sh->share_cache.reg_mr_cb,
1202                               &sh->share_cache.dereg_mr_cb);
1203         mlx5_os_dev_shared_handler_install(sh);
1204         sh->cnt_id_tbl = mlx5_l3t_create(MLX5_L3T_TYPE_DWORD);
1205         if (!sh->cnt_id_tbl) {
1206                 err = rte_errno;
1207                 goto error;
1208         }
1209         if (LIST_EMPTY(&mlx5_dev_ctx_list)) {
1210                 err = mlx5_flow_os_init_workspace_once();
1211                 if (err)
1212                         goto error;
1213         }
1214         mlx5_flow_aging_init(sh);
1215         mlx5_flow_counters_mng_init(sh);
1216         mlx5_flow_ipool_create(sh, config);
1217         /* Add device to memory callback list. */
1218         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1219         LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1220                          sh, mem_event_cb);
1221         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1222         /* Add context to the global device list. */
1223         LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next);
1224         rte_spinlock_init(&sh->geneve_tlv_opt_sl);
1225 exit:
1226         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1227         return sh;
1228 error:
1229         pthread_mutex_destroy(&sh->txpp.mutex);
1230         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1231         MLX5_ASSERT(sh);
1232         if (sh->cnt_id_tbl)
1233                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1234         if (sh->tis)
1235                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1236         if (sh->td)
1237                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1238         if (sh->devx_rx_uar)
1239                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1240         if (sh->tx_uar)
1241                 mlx5_glue->devx_free_uar(sh->tx_uar);
1242         if (sh->pd)
1243                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1244         if (sh->ctx)
1245                 claim_zero(mlx5_glue->close_device(sh->ctx));
1246         mlx5_free(sh);
1247         MLX5_ASSERT(err > 0);
1248         rte_errno = err;
1249         return NULL;
1250 }
1251
1252 /**
1253  * Free shared IB device context. Decrement counter and if zero free
1254  * all allocated resources and close handles.
1255  *
1256  * @param[in] sh
1257  *   Pointer to mlx5_dev_ctx_shared object to free
1258  */
1259 void
1260 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh)
1261 {
1262         pthread_mutex_lock(&mlx5_dev_ctx_list_mutex);
1263 #ifdef RTE_LIBRTE_MLX5_DEBUG
1264         /* Check the object presence in the list. */
1265         struct mlx5_dev_ctx_shared *lctx;
1266
1267         LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next)
1268                 if (lctx == sh)
1269                         break;
1270         MLX5_ASSERT(lctx);
1271         if (lctx != sh) {
1272                 DRV_LOG(ERR, "Freeing non-existing shared IB context");
1273                 goto exit;
1274         }
1275 #endif
1276         MLX5_ASSERT(sh);
1277         MLX5_ASSERT(sh->refcnt);
1278         /* Secondary process should not free the shared context. */
1279         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
1280         if (--sh->refcnt)
1281                 goto exit;
1282         /* Remove from memory callback device list. */
1283         rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1284         LIST_REMOVE(sh, mem_event_cb);
1285         rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1286         /* Release created Memory Regions. */
1287         mlx5_mr_release_cache(&sh->share_cache);
1288         /* Remove context from the global device list. */
1289         LIST_REMOVE(sh, next);
1290         /* Release flow workspaces objects on the last device. */
1291         if (LIST_EMPTY(&mlx5_dev_ctx_list))
1292                 mlx5_flow_os_release_workspace();
1293         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1294         /*
1295          *  Ensure there is no async event handler installed.
1296          *  Only primary process handles async device events.
1297          **/
1298         mlx5_flow_counters_mng_close(sh);
1299         if (sh->aso_age_mng) {
1300                 mlx5_flow_aso_age_mng_close(sh);
1301                 sh->aso_age_mng = NULL;
1302         }
1303         if (sh->mtrmng)
1304                 mlx5_aso_flow_mtrs_mng_close(sh);
1305         mlx5_flow_ipool_destroy(sh);
1306         mlx5_os_dev_shared_handler_uninstall(sh);
1307         if (sh->cnt_id_tbl) {
1308                 mlx5_l3t_destroy(sh->cnt_id_tbl);
1309                 sh->cnt_id_tbl = NULL;
1310         }
1311         if (sh->tx_uar) {
1312                 mlx5_glue->devx_free_uar(sh->tx_uar);
1313                 sh->tx_uar = NULL;
1314         }
1315         if (sh->pd)
1316                 claim_zero(mlx5_os_dealloc_pd(sh->pd));
1317         if (sh->tis)
1318                 claim_zero(mlx5_devx_cmd_destroy(sh->tis));
1319         if (sh->td)
1320                 claim_zero(mlx5_devx_cmd_destroy(sh->td));
1321         if (sh->devx_rx_uar)
1322                 mlx5_glue->devx_free_uar(sh->devx_rx_uar);
1323         if (sh->ctx)
1324                 claim_zero(mlx5_glue->close_device(sh->ctx));
1325         MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL);
1326         pthread_mutex_destroy(&sh->txpp.mutex);
1327         mlx5_free(sh);
1328         return;
1329 exit:
1330         pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex);
1331 }
1332
1333 /**
1334  * Destroy table hash list.
1335  *
1336  * @param[in] priv
1337  *   Pointer to the private device data structure.
1338  */
1339 void
1340 mlx5_free_table_hash_list(struct mlx5_priv *priv)
1341 {
1342         struct mlx5_dev_ctx_shared *sh = priv->sh;
1343
1344         if (!sh->flow_tbls)
1345                 return;
1346         mlx5_hlist_destroy(sh->flow_tbls);
1347 }
1348
1349 /**
1350  * Initialize flow table hash list and create the root tables entry
1351  * for each domain.
1352  *
1353  * @param[in] priv
1354  *   Pointer to the private device data structure.
1355  *
1356  * @return
1357  *   Zero on success, positive error code otherwise.
1358  */
1359 int
1360 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused)
1361 {
1362         int err = 0;
1363         /* Tables are only used in DV and DR modes. */
1364 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
1365         struct mlx5_dev_ctx_shared *sh = priv->sh;
1366         char s[MLX5_NAME_SIZE];
1367
1368         MLX5_ASSERT(sh);
1369         snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name);
1370         sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE,
1371                                           false, true, sh,
1372                                           flow_dv_tbl_create_cb,
1373                                           flow_dv_tbl_match_cb,
1374                                           flow_dv_tbl_remove_cb,
1375                                           flow_dv_tbl_clone_cb,
1376                                           flow_dv_tbl_clone_free_cb);
1377         if (!sh->flow_tbls) {
1378                 DRV_LOG(ERR, "flow tables with hash creation failed.");
1379                 err = ENOMEM;
1380                 return err;
1381         }
1382 #ifndef HAVE_MLX5DV_DR
1383         struct rte_flow_error error;
1384         struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id];
1385
1386         /*
1387          * In case we have not DR support, the zero tables should be created
1388          * because DV expect to see them even if they cannot be created by
1389          * RDMA-CORE.
1390          */
1391         if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0,
1392                 NULL, 0, 1, 0, &error) ||
1393             !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0,
1394                 NULL, 0, 1, 0, &error) ||
1395             !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0,
1396                 NULL, 0, 1, 0, &error)) {
1397                 err = ENOMEM;
1398                 goto error;
1399         }
1400         return err;
1401 error:
1402         mlx5_free_table_hash_list(priv);
1403 #endif /* HAVE_MLX5DV_DR */
1404 #endif
1405         return err;
1406 }
1407
1408 /**
1409  * Retrieve integer value from environment variable.
1410  *
1411  * @param[in] name
1412  *   Environment variable name.
1413  *
1414  * @return
1415  *   Integer value, 0 if the variable is not set.
1416  */
1417 int
1418 mlx5_getenv_int(const char *name)
1419 {
1420         const char *val = getenv(name);
1421
1422         if (val == NULL)
1423                 return 0;
1424         return atoi(val);
1425 }
1426
1427 /**
1428  * DPDK callback to add udp tunnel port
1429  *
1430  * @param[in] dev
1431  *   A pointer to eth_dev
1432  * @param[in] udp_tunnel
1433  *   A pointer to udp tunnel
1434  *
1435  * @return
1436  *   0 on valid udp ports and tunnels, -ENOTSUP otherwise.
1437  */
1438 int
1439 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused,
1440                          struct rte_eth_udp_tunnel *udp_tunnel)
1441 {
1442         MLX5_ASSERT(udp_tunnel != NULL);
1443         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN &&
1444             udp_tunnel->udp_port == 4789)
1445                 return 0;
1446         if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE &&
1447             udp_tunnel->udp_port == 4790)
1448                 return 0;
1449         return -ENOTSUP;
1450 }
1451
1452 /**
1453  * Initialize process private data structure.
1454  *
1455  * @param dev
1456  *   Pointer to Ethernet device structure.
1457  *
1458  * @return
1459  *   0 on success, a negative errno value otherwise and rte_errno is set.
1460  */
1461 int
1462 mlx5_proc_priv_init(struct rte_eth_dev *dev)
1463 {
1464         struct mlx5_priv *priv = dev->data->dev_private;
1465         struct mlx5_proc_priv *ppriv;
1466         size_t ppriv_size;
1467
1468         mlx5_proc_priv_uninit(dev);
1469         /*
1470          * UAR register table follows the process private structure. BlueFlame
1471          * registers for Tx queues are stored in the table.
1472          */
1473         ppriv_size =
1474                 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
1475         ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size,
1476                             RTE_CACHE_LINE_SIZE, dev->device->numa_node);
1477         if (!ppriv) {
1478                 rte_errno = ENOMEM;
1479                 return -rte_errno;
1480         }
1481         ppriv->uar_table_sz = priv->txqs_n;
1482         dev->process_private = ppriv;
1483         return 0;
1484 }
1485
1486 /**
1487  * Un-initialize process private data structure.
1488  *
1489  * @param dev
1490  *   Pointer to Ethernet device structure.
1491  */
1492 void
1493 mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
1494 {
1495         if (!dev->process_private)
1496                 return;
1497         mlx5_free(dev->process_private);
1498         dev->process_private = NULL;
1499 }
1500
1501 /**
1502  * DPDK callback to close the device.
1503  *
1504  * Destroy all queues and objects, free memory.
1505  *
1506  * @param dev
1507  *   Pointer to Ethernet device structure.
1508  */
1509 int
1510 mlx5_dev_close(struct rte_eth_dev *dev)
1511 {
1512         struct mlx5_priv *priv = dev->data->dev_private;
1513         unsigned int i;
1514         int ret;
1515
1516         if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
1517                 /* Check if process_private released. */
1518                 if (!dev->process_private)
1519                         return 0;
1520                 mlx5_tx_uar_uninit_secondary(dev);
1521                 mlx5_proc_priv_uninit(dev);
1522                 rte_eth_dev_release_port(dev);
1523                 return 0;
1524         }
1525         if (!priv->sh)
1526                 return 0;
1527         DRV_LOG(DEBUG, "port %u closing device \"%s\"",
1528                 dev->data->port_id,
1529                 ((priv->sh->ctx != NULL) ?
1530                 mlx5_os_get_ctx_device_name(priv->sh->ctx) : ""));
1531         /*
1532          * If default mreg copy action is removed at the stop stage,
1533          * the search will return none and nothing will be done anymore.
1534          */
1535         mlx5_flow_stop_default(dev);
1536         mlx5_traffic_disable(dev);
1537         /*
1538          * If all the flows are already flushed in the device stop stage,
1539          * then this will return directly without any action.
1540          */
1541         mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true);
1542         mlx5_action_handle_flush(dev);
1543         mlx5_flow_meter_flush(dev, NULL);
1544         /* Prevent crashes when queues are still in use. */
1545         dev->rx_pkt_burst = removed_rx_burst;
1546         dev->tx_pkt_burst = removed_tx_burst;
1547         rte_wmb();
1548         /* Disable datapath on secondary process. */
1549         mlx5_mp_os_req_stop_rxtx(dev);
1550         /* Free the eCPRI flex parser resource. */
1551         mlx5_flex_parser_ecpri_release(dev);
1552         if (priv->rxqs != NULL) {
1553                 /* XXX race condition if mlx5_rx_burst() is still running. */
1554                 rte_delay_us_sleep(1000);
1555                 for (i = 0; (i != priv->rxqs_n); ++i)
1556                         mlx5_rxq_release(dev, i);
1557                 priv->rxqs_n = 0;
1558                 priv->rxqs = NULL;
1559         }
1560         if (priv->txqs != NULL) {
1561                 /* XXX race condition if mlx5_tx_burst() is still running. */
1562                 rte_delay_us_sleep(1000);
1563                 for (i = 0; (i != priv->txqs_n); ++i)
1564                         mlx5_txq_release(dev, i);
1565                 priv->txqs_n = 0;
1566                 priv->txqs = NULL;
1567         }
1568         mlx5_proc_priv_uninit(dev);
1569         if (priv->q_counters) {
1570                 mlx5_devx_cmd_destroy(priv->q_counters);
1571                 priv->q_counters = NULL;
1572         }
1573         if (priv->drop_queue.hrxq)
1574                 mlx5_drop_action_destroy(dev);
1575         if (priv->mreg_cp_tbl)
1576                 mlx5_hlist_destroy(priv->mreg_cp_tbl);
1577         mlx5_mprq_free_mp(dev);
1578         if (priv->sh->ct_mng)
1579                 mlx5_flow_aso_ct_mng_close(priv->sh);
1580         mlx5_os_free_shared_dr(priv);
1581         if (priv->rss_conf.rss_key != NULL)
1582                 mlx5_free(priv->rss_conf.rss_key);
1583         if (priv->reta_idx != NULL)
1584                 mlx5_free(priv->reta_idx);
1585         if (priv->config.vf)
1586                 mlx5_os_mac_addr_flush(dev);
1587         if (priv->nl_socket_route >= 0)
1588                 close(priv->nl_socket_route);
1589         if (priv->nl_socket_rdma >= 0)
1590                 close(priv->nl_socket_rdma);
1591         if (priv->vmwa_context)
1592                 mlx5_vlan_vmwa_exit(priv->vmwa_context);
1593         ret = mlx5_hrxq_verify(dev);
1594         if (ret)
1595                 DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
1596                         dev->data->port_id);
1597         ret = mlx5_ind_table_obj_verify(dev);
1598         if (ret)
1599                 DRV_LOG(WARNING, "port %u some indirection table still remain",
1600                         dev->data->port_id);
1601         ret = mlx5_rxq_obj_verify(dev);
1602         if (ret)
1603                 DRV_LOG(WARNING, "port %u some Rx queue objects still remain",
1604                         dev->data->port_id);
1605         ret = mlx5_rxq_verify(dev);
1606         if (ret)
1607                 DRV_LOG(WARNING, "port %u some Rx queues still remain",
1608                         dev->data->port_id);
1609         ret = mlx5_txq_obj_verify(dev);
1610         if (ret)
1611                 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
1612                         dev->data->port_id);
1613         ret = mlx5_txq_verify(dev);
1614         if (ret)
1615                 DRV_LOG(WARNING, "port %u some Tx queues still remain",
1616                         dev->data->port_id);
1617         ret = mlx5_flow_verify(dev);
1618         if (ret)
1619                 DRV_LOG(WARNING, "port %u some flows still remain",
1620                         dev->data->port_id);
1621         if (priv->hrxqs)
1622                 mlx5_list_destroy(priv->hrxqs);
1623         /*
1624          * Free the shared context in last turn, because the cleanup
1625          * routines above may use some shared fields, like
1626          * mlx5_os_mac_addr_flush() uses ibdev_path for retrieveing
1627          * ifindex if Netlink fails.
1628          */
1629         mlx5_free_shared_dev_ctx(priv->sh);
1630         if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
1631                 unsigned int c = 0;
1632                 uint16_t port_id;
1633
1634                 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
1635                         struct mlx5_priv *opriv =
1636                                 rte_eth_devices[port_id].data->dev_private;
1637
1638                         if (!opriv ||
1639                             opriv->domain_id != priv->domain_id ||
1640                             &rte_eth_devices[port_id] == dev)
1641                                 continue;
1642                         ++c;
1643                         break;
1644                 }
1645                 if (!c)
1646                         claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1647         }
1648         memset(priv, 0, sizeof(*priv));
1649         priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1650         /*
1651          * Reset mac_addrs to NULL such that it is not freed as part of
1652          * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
1653          * it is freed when dev_private is freed.
1654          */
1655         dev->data->mac_addrs = NULL;
1656         return 0;
1657 }
1658
1659 const struct eth_dev_ops mlx5_dev_ops = {
1660         .dev_configure = mlx5_dev_configure,
1661         .dev_start = mlx5_dev_start,
1662         .dev_stop = mlx5_dev_stop,
1663         .dev_set_link_down = mlx5_set_link_down,
1664         .dev_set_link_up = mlx5_set_link_up,
1665         .dev_close = mlx5_dev_close,
1666         .promiscuous_enable = mlx5_promiscuous_enable,
1667         .promiscuous_disable = mlx5_promiscuous_disable,
1668         .allmulticast_enable = mlx5_allmulticast_enable,
1669         .allmulticast_disable = mlx5_allmulticast_disable,
1670         .link_update = mlx5_link_update,
1671         .stats_get = mlx5_stats_get,
1672         .stats_reset = mlx5_stats_reset,
1673         .xstats_get = mlx5_xstats_get,
1674         .xstats_reset = mlx5_xstats_reset,
1675         .xstats_get_names = mlx5_xstats_get_names,
1676         .fw_version_get = mlx5_fw_version_get,
1677         .dev_infos_get = mlx5_dev_infos_get,
1678         .representor_info_get = mlx5_representor_info_get,
1679         .read_clock = mlx5_txpp_read_clock,
1680         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1681         .vlan_filter_set = mlx5_vlan_filter_set,
1682         .rx_queue_setup = mlx5_rx_queue_setup,
1683         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1684         .tx_queue_setup = mlx5_tx_queue_setup,
1685         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1686         .rx_queue_release = mlx5_rx_queue_release,
1687         .tx_queue_release = mlx5_tx_queue_release,
1688         .rx_queue_start = mlx5_rx_queue_start,
1689         .rx_queue_stop = mlx5_rx_queue_stop,
1690         .tx_queue_start = mlx5_tx_queue_start,
1691         .tx_queue_stop = mlx5_tx_queue_stop,
1692         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1693         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1694         .mac_addr_remove = mlx5_mac_addr_remove,
1695         .mac_addr_add = mlx5_mac_addr_add,
1696         .mac_addr_set = mlx5_mac_addr_set,
1697         .set_mc_addr_list = mlx5_set_mc_addr_list,
1698         .mtu_set = mlx5_dev_set_mtu,
1699         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1700         .vlan_offload_set = mlx5_vlan_offload_set,
1701         .reta_update = mlx5_dev_rss_reta_update,
1702         .reta_query = mlx5_dev_rss_reta_query,
1703         .rss_hash_update = mlx5_rss_hash_update,
1704         .rss_hash_conf_get = mlx5_rss_hash_conf_get,
1705         .flow_ops_get = mlx5_flow_ops_get,
1706         .rxq_info_get = mlx5_rxq_info_get,
1707         .txq_info_get = mlx5_txq_info_get,
1708         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1709         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1710         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1711         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1712         .is_removed = mlx5_is_removed,
1713         .udp_tunnel_port_add  = mlx5_udp_tunnel_port_add,
1714         .get_module_info = mlx5_get_module_info,
1715         .get_module_eeprom = mlx5_get_module_eeprom,
1716         .hairpin_cap_get = mlx5_hairpin_cap_get,
1717         .mtr_ops_get = mlx5_flow_meter_ops_get,
1718         .hairpin_bind = mlx5_hairpin_bind,
1719         .hairpin_unbind = mlx5_hairpin_unbind,
1720         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1721         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1722         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1723         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1724         .get_monitor_addr = mlx5_get_monitor_addr,
1725 };
1726
1727 /* Available operations from secondary process. */
1728 const struct eth_dev_ops mlx5_dev_sec_ops = {
1729         .stats_get = mlx5_stats_get,
1730         .stats_reset = mlx5_stats_reset,
1731         .xstats_get = mlx5_xstats_get,
1732         .xstats_reset = mlx5_xstats_reset,
1733         .xstats_get_names = mlx5_xstats_get_names,
1734         .fw_version_get = mlx5_fw_version_get,
1735         .dev_infos_get = mlx5_dev_infos_get,
1736         .read_clock = mlx5_txpp_read_clock,
1737         .rx_queue_start = mlx5_rx_queue_start,
1738         .rx_queue_stop = mlx5_rx_queue_stop,
1739         .tx_queue_start = mlx5_tx_queue_start,
1740         .tx_queue_stop = mlx5_tx_queue_stop,
1741         .rxq_info_get = mlx5_rxq_info_get,
1742         .txq_info_get = mlx5_txq_info_get,
1743         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1744         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1745         .get_module_info = mlx5_get_module_info,
1746         .get_module_eeprom = mlx5_get_module_eeprom,
1747 };
1748
1749 /* Available operations in flow isolated mode. */
1750 const struct eth_dev_ops mlx5_dev_ops_isolate = {
1751         .dev_configure = mlx5_dev_configure,
1752         .dev_start = mlx5_dev_start,
1753         .dev_stop = mlx5_dev_stop,
1754         .dev_set_link_down = mlx5_set_link_down,
1755         .dev_set_link_up = mlx5_set_link_up,
1756         .dev_close = mlx5_dev_close,
1757         .promiscuous_enable = mlx5_promiscuous_enable,
1758         .promiscuous_disable = mlx5_promiscuous_disable,
1759         .allmulticast_enable = mlx5_allmulticast_enable,
1760         .allmulticast_disable = mlx5_allmulticast_disable,
1761         .link_update = mlx5_link_update,
1762         .stats_get = mlx5_stats_get,
1763         .stats_reset = mlx5_stats_reset,
1764         .xstats_get = mlx5_xstats_get,
1765         .xstats_reset = mlx5_xstats_reset,
1766         .xstats_get_names = mlx5_xstats_get_names,
1767         .fw_version_get = mlx5_fw_version_get,
1768         .dev_infos_get = mlx5_dev_infos_get,
1769         .read_clock = mlx5_txpp_read_clock,
1770         .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
1771         .vlan_filter_set = mlx5_vlan_filter_set,
1772         .rx_queue_setup = mlx5_rx_queue_setup,
1773         .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup,
1774         .tx_queue_setup = mlx5_tx_queue_setup,
1775         .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup,
1776         .rx_queue_release = mlx5_rx_queue_release,
1777         .tx_queue_release = mlx5_tx_queue_release,
1778         .rx_queue_start = mlx5_rx_queue_start,
1779         .rx_queue_stop = mlx5_rx_queue_stop,
1780         .tx_queue_start = mlx5_tx_queue_start,
1781         .tx_queue_stop = mlx5_tx_queue_stop,
1782         .flow_ctrl_get = mlx5_dev_get_flow_ctrl,
1783         .flow_ctrl_set = mlx5_dev_set_flow_ctrl,
1784         .mac_addr_remove = mlx5_mac_addr_remove,
1785         .mac_addr_add = mlx5_mac_addr_add,
1786         .mac_addr_set = mlx5_mac_addr_set,
1787         .set_mc_addr_list = mlx5_set_mc_addr_list,
1788         .mtu_set = mlx5_dev_set_mtu,
1789         .vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
1790         .vlan_offload_set = mlx5_vlan_offload_set,
1791         .flow_ops_get = mlx5_flow_ops_get,
1792         .rxq_info_get = mlx5_rxq_info_get,
1793         .txq_info_get = mlx5_txq_info_get,
1794         .rx_burst_mode_get = mlx5_rx_burst_mode_get,
1795         .tx_burst_mode_get = mlx5_tx_burst_mode_get,
1796         .rx_queue_intr_enable = mlx5_rx_intr_enable,
1797         .rx_queue_intr_disable = mlx5_rx_intr_disable,
1798         .is_removed = mlx5_is_removed,
1799         .get_module_info = mlx5_get_module_info,
1800         .get_module_eeprom = mlx5_get_module_eeprom,
1801         .hairpin_cap_get = mlx5_hairpin_cap_get,
1802         .mtr_ops_get = mlx5_flow_meter_ops_get,
1803         .hairpin_bind = mlx5_hairpin_bind,
1804         .hairpin_unbind = mlx5_hairpin_unbind,
1805         .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports,
1806         .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update,
1807         .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind,
1808         .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind,
1809         .get_monitor_addr = mlx5_get_monitor_addr,
1810 };
1811
1812 /**
1813  * Verify and store value for device argument.
1814  *
1815  * @param[in] key
1816  *   Key argument to verify.
1817  * @param[in] val
1818  *   Value associated with key.
1819  * @param opaque
1820  *   User data.
1821  *
1822  * @return
1823  *   0 on success, a negative errno value otherwise and rte_errno is set.
1824  */
1825 static int
1826 mlx5_args_check(const char *key, const char *val, void *opaque)
1827 {
1828         struct mlx5_dev_config *config = opaque;
1829         unsigned long mod;
1830         signed long tmp;
1831
1832         /* No-op, port representors are processed in mlx5_dev_spawn(). */
1833         if (!strcmp(MLX5_REPRESENTOR, key))
1834                 return 0;
1835         errno = 0;
1836         tmp = strtol(val, NULL, 0);
1837         if (errno) {
1838                 rte_errno = errno;
1839                 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
1840                 return -rte_errno;
1841         }
1842         if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) {
1843                 /* Negative values are acceptable for some keys only. */
1844                 rte_errno = EINVAL;
1845                 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val);
1846                 return -rte_errno;
1847         }
1848         mod = tmp >= 0 ? tmp : -tmp;
1849         if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
1850                 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) {
1851                         DRV_LOG(ERR, "invalid CQE compression "
1852                                      "format parameter");
1853                         rte_errno = EINVAL;
1854                         return -rte_errno;
1855                 }
1856                 config->cqe_comp = !!tmp;
1857                 config->cqe_comp_fmt = tmp;
1858         } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
1859                 config->hw_padding = !!tmp;
1860         } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
1861                 config->mprq.enabled = !!tmp;
1862         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
1863                 config->mprq.stride_num_n = tmp;
1864         } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) {
1865                 config->mprq.stride_size_n = tmp;
1866         } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
1867                 config->mprq.max_memcpy_len = tmp;
1868         } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
1869                 config->mprq.min_rxqs_num = tmp;
1870         } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
1871                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1872                                  " converted to txq_inline_max", key);
1873                 config->txq_inline_max = tmp;
1874         } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) {
1875                 config->txq_inline_max = tmp;
1876         } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) {
1877                 config->txq_inline_min = tmp;
1878         } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) {
1879                 config->txq_inline_mpw = tmp;
1880         } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
1881                 config->txqs_inline = tmp;
1882         } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
1883                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1884         } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
1885                 config->mps = !!tmp;
1886         } else if (strcmp(MLX5_TX_DB_NC, key) == 0) {
1887                 if (tmp != MLX5_TXDB_CACHED &&
1888                     tmp != MLX5_TXDB_NCACHED &&
1889                     tmp != MLX5_TXDB_HEURISTIC) {
1890                         DRV_LOG(ERR, "invalid Tx doorbell "
1891                                      "mapping parameter");
1892                         rte_errno = EINVAL;
1893                         return -rte_errno;
1894                 }
1895                 config->dbnc = tmp;
1896         } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
1897                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1898         } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
1899                 DRV_LOG(WARNING, "%s: deprecated parameter,"
1900                                  " converted to txq_inline_mpw", key);
1901                 config->txq_inline_mpw = tmp;
1902         } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
1903                 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key);
1904         } else if (strcmp(MLX5_TX_PP, key) == 0) {
1905                 if (!mod) {
1906                         DRV_LOG(ERR, "Zero Tx packet pacing parameter");
1907                         rte_errno = EINVAL;
1908                         return -rte_errno;
1909                 }
1910                 config->tx_pp = tmp;
1911         } else if (strcmp(MLX5_TX_SKEW, key) == 0) {
1912                 config->tx_skew = tmp;
1913         } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
1914                 config->rx_vec_en = !!tmp;
1915         } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
1916                 config->l3_vxlan_en = !!tmp;
1917         } else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
1918                 config->vf_nl_en = !!tmp;
1919         } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
1920                 config->dv_esw_en = !!tmp;
1921         } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
1922                 config->dv_flow_en = !!tmp;
1923         } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) {
1924                 if (tmp != MLX5_XMETA_MODE_LEGACY &&
1925                     tmp != MLX5_XMETA_MODE_META16 &&
1926                     tmp != MLX5_XMETA_MODE_META32 &&
1927                     tmp != MLX5_XMETA_MODE_MISS_INFO) {
1928                         DRV_LOG(ERR, "invalid extensive "
1929                                      "metadata parameter");
1930                         rte_errno = EINVAL;
1931                         return -rte_errno;
1932                 }
1933                 if (tmp != MLX5_XMETA_MODE_MISS_INFO)
1934                         config->dv_xmeta_en = tmp;
1935                 else
1936                         config->dv_miss_info = 1;
1937         } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) {
1938                 config->lacp_by_user = !!tmp;
1939         } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
1940                 config->mr_ext_memseg_en = !!tmp;
1941         } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) {
1942                 config->max_dump_files_num = tmp;
1943         } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) {
1944                 config->lro.timeout = tmp;
1945         } else if (strcmp(RTE_DEVARGS_KEY_CLASS, key) == 0) {
1946                 DRV_LOG(DEBUG, "class argument is %s.", val);
1947         } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) {
1948                 config->log_hp_size = tmp;
1949         } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) {
1950                 if (tmp != MLX5_RCM_NONE &&
1951                     tmp != MLX5_RCM_LIGHT &&
1952                     tmp != MLX5_RCM_AGGR) {
1953                         DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val);
1954                         rte_errno = EINVAL;
1955                         return -rte_errno;
1956                 }
1957                 config->reclaim_mode = tmp;
1958         } else if (strcmp(MLX5_SYS_MEM_EN, key) == 0) {
1959                 config->sys_mem_en = !!tmp;
1960         } else if (strcmp(MLX5_DECAP_EN, key) == 0) {
1961                 config->decap_en = !!tmp;
1962         } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) {
1963                 config->allow_duplicate_pattern = !!tmp;
1964         } else {
1965                 DRV_LOG(WARNING, "%s: unknown parameter", key);
1966                 rte_errno = EINVAL;
1967                 return -rte_errno;
1968         }
1969         return 0;
1970 }
1971
1972 /**
1973  * Parse device parameters.
1974  *
1975  * @param config
1976  *   Pointer to device configuration structure.
1977  * @param devargs
1978  *   Device arguments structure.
1979  *
1980  * @return
1981  *   0 on success, a negative errno value otherwise and rte_errno is set.
1982  */
1983 int
1984 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
1985 {
1986         const char **params = (const char *[]){
1987                 MLX5_RXQ_CQE_COMP_EN,
1988                 MLX5_RXQ_PKT_PAD_EN,
1989                 MLX5_RX_MPRQ_EN,
1990                 MLX5_RX_MPRQ_LOG_STRIDE_NUM,
1991                 MLX5_RX_MPRQ_LOG_STRIDE_SIZE,
1992                 MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
1993                 MLX5_RXQS_MIN_MPRQ,
1994                 MLX5_TXQ_INLINE,
1995                 MLX5_TXQ_INLINE_MIN,
1996                 MLX5_TXQ_INLINE_MAX,
1997                 MLX5_TXQ_INLINE_MPW,
1998                 MLX5_TXQS_MIN_INLINE,
1999                 MLX5_TXQS_MAX_VEC,
2000                 MLX5_TXQ_MPW_EN,
2001                 MLX5_TXQ_MPW_HDR_DSEG_EN,
2002                 MLX5_TXQ_MAX_INLINE_LEN,
2003                 MLX5_TX_DB_NC,
2004                 MLX5_TX_PP,
2005                 MLX5_TX_SKEW,
2006                 MLX5_TX_VEC_EN,
2007                 MLX5_RX_VEC_EN,
2008                 MLX5_L3_VXLAN_EN,
2009                 MLX5_VF_NL_EN,
2010                 MLX5_DV_ESW_EN,
2011                 MLX5_DV_FLOW_EN,
2012                 MLX5_DV_XMETA_EN,
2013                 MLX5_LACP_BY_USER,
2014                 MLX5_MR_EXT_MEMSEG_EN,
2015                 MLX5_REPRESENTOR,
2016                 MLX5_MAX_DUMP_FILES_NUM,
2017                 MLX5_LRO_TIMEOUT_USEC,
2018                 RTE_DEVARGS_KEY_CLASS,
2019                 MLX5_HP_BUF_SIZE,
2020                 MLX5_RECLAIM_MEM,
2021                 MLX5_SYS_MEM_EN,
2022                 MLX5_DECAP_EN,
2023                 MLX5_ALLOW_DUPLICATE_PATTERN,
2024                 NULL,
2025         };
2026         struct rte_kvargs *kvlist;
2027         int ret = 0;
2028         int i;
2029
2030         if (devargs == NULL)
2031                 return 0;
2032         /* Following UGLY cast is done to pass checkpatch. */
2033         kvlist = rte_kvargs_parse(devargs->args, params);
2034         if (kvlist == NULL) {
2035                 rte_errno = EINVAL;
2036                 return -rte_errno;
2037         }
2038         /* Process parameters. */
2039         for (i = 0; (params[i] != NULL); ++i) {
2040                 if (rte_kvargs_count(kvlist, params[i])) {
2041                         ret = rte_kvargs_process(kvlist, params[i],
2042                                                  mlx5_args_check, config);
2043                         if (ret) {
2044                                 rte_errno = EINVAL;
2045                                 rte_kvargs_free(kvlist);
2046                                 return -rte_errno;
2047                         }
2048                 }
2049         }
2050         rte_kvargs_free(kvlist);
2051         return 0;
2052 }
2053
2054 /**
2055  * Configures the minimal amount of data to inline into WQE
2056  * while sending packets.
2057  *
2058  * - the txq_inline_min has the maximal priority, if this
2059  *   key is specified in devargs
2060  * - if DevX is enabled the inline mode is queried from the
2061  *   device (HCA attributes and NIC vport context if needed).
2062  * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx
2063  *   and none (0 bytes) for other NICs
2064  *
2065  * @param spawn
2066  *   Verbs device parameters (name, port, switch_info) to spawn.
2067  * @param config
2068  *   Device configuration parameters.
2069  */
2070 void
2071 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn,
2072                     struct mlx5_dev_config *config)
2073 {
2074         if (config->txq_inline_min != MLX5_ARG_UNSET) {
2075                 /* Application defines size of inlined data explicitly. */
2076                 switch (spawn->pci_dev->id.device_id) {
2077                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2078                 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2079                         if (config->txq_inline_min <
2080                                        (int)MLX5_INLINE_HSIZE_L2) {
2081                                 DRV_LOG(DEBUG,
2082                                         "txq_inline_mix aligned to minimal"
2083                                         " ConnectX-4 required value %d",
2084                                         (int)MLX5_INLINE_HSIZE_L2);
2085                                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2086                         }
2087                         break;
2088                 }
2089                 goto exit;
2090         }
2091         if (config->hca_attr.eth_net_offloads) {
2092                 /* We have DevX enabled, inline mode queried successfully. */
2093                 switch (config->hca_attr.wqe_inline_mode) {
2094                 case MLX5_CAP_INLINE_MODE_L2:
2095                         /* outer L2 header must be inlined. */
2096                         config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2097                         goto exit;
2098                 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED:
2099                         /* No inline data are required by NIC. */
2100                         config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2101                         config->hw_vlan_insert =
2102                                 config->hca_attr.wqe_vlan_insert;
2103                         DRV_LOG(DEBUG, "Tx VLAN insertion is supported");
2104                         goto exit;
2105                 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT:
2106                         /* inline mode is defined by NIC vport context. */
2107                         if (!config->hca_attr.eth_virt)
2108                                 break;
2109                         switch (config->hca_attr.vport_inline_mode) {
2110                         case MLX5_INLINE_MODE_NONE:
2111                                 config->txq_inline_min =
2112                                         MLX5_INLINE_HSIZE_NONE;
2113                                 goto exit;
2114                         case MLX5_INLINE_MODE_L2:
2115                                 config->txq_inline_min =
2116                                         MLX5_INLINE_HSIZE_L2;
2117                                 goto exit;
2118                         case MLX5_INLINE_MODE_IP:
2119                                 config->txq_inline_min =
2120                                         MLX5_INLINE_HSIZE_L3;
2121                                 goto exit;
2122                         case MLX5_INLINE_MODE_TCP_UDP:
2123                                 config->txq_inline_min =
2124                                         MLX5_INLINE_HSIZE_L4;
2125                                 goto exit;
2126                         case MLX5_INLINE_MODE_INNER_L2:
2127                                 config->txq_inline_min =
2128                                         MLX5_INLINE_HSIZE_INNER_L2;
2129                                 goto exit;
2130                         case MLX5_INLINE_MODE_INNER_IP:
2131                                 config->txq_inline_min =
2132                                         MLX5_INLINE_HSIZE_INNER_L3;
2133                                 goto exit;
2134                         case MLX5_INLINE_MODE_INNER_TCP_UDP:
2135                                 config->txq_inline_min =
2136                                         MLX5_INLINE_HSIZE_INNER_L4;
2137                                 goto exit;
2138                         }
2139                 }
2140         }
2141         /*
2142          * We get here if we are unable to deduce
2143          * inline data size with DevX. Try PCI ID
2144          * to determine old NICs.
2145          */
2146         switch (spawn->pci_dev->id.device_id) {
2147         case PCI_DEVICE_ID_MELLANOX_CONNECTX4:
2148         case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
2149         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX:
2150         case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
2151                 config->txq_inline_min = MLX5_INLINE_HSIZE_L2;
2152                 config->hw_vlan_insert = 0;
2153                 break;
2154         case PCI_DEVICE_ID_MELLANOX_CONNECTX5:
2155         case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
2156         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX:
2157         case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
2158                 /*
2159                  * These NICs support VLAN insertion from WQE and
2160                  * report the wqe_vlan_insert flag. But there is the bug
2161                  * and PFC control may be broken, so disable feature.
2162                  */
2163                 config->hw_vlan_insert = 0;
2164                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2165                 break;
2166         default:
2167                 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE;
2168                 break;
2169         }
2170 exit:
2171         DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min);
2172 }
2173
2174 /**
2175  * Configures the metadata mask fields in the shared context.
2176  *
2177  * @param [in] dev
2178  *   Pointer to Ethernet device.
2179  */
2180 void
2181 mlx5_set_metadata_mask(struct rte_eth_dev *dev)
2182 {
2183         struct mlx5_priv *priv = dev->data->dev_private;
2184         struct mlx5_dev_ctx_shared *sh = priv->sh;
2185         uint32_t meta, mark, reg_c0;
2186
2187         reg_c0 = ~priv->vport_meta_mask;
2188         switch (priv->config.dv_xmeta_en) {
2189         case MLX5_XMETA_MODE_LEGACY:
2190                 meta = UINT32_MAX;
2191                 mark = MLX5_FLOW_MARK_MASK;
2192                 break;
2193         case MLX5_XMETA_MODE_META16:
2194                 meta = reg_c0 >> rte_bsf32(reg_c0);
2195                 mark = MLX5_FLOW_MARK_MASK;
2196                 break;
2197         case MLX5_XMETA_MODE_META32:
2198                 meta = UINT32_MAX;
2199                 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK;
2200                 break;
2201         default:
2202                 meta = 0;
2203                 mark = 0;
2204                 MLX5_ASSERT(false);
2205                 break;
2206         }
2207         if (sh->dv_mark_mask && sh->dv_mark_mask != mark)
2208                 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X",
2209                                  sh->dv_mark_mask, mark);
2210         else
2211                 sh->dv_mark_mask = mark;
2212         if (sh->dv_meta_mask && sh->dv_meta_mask != meta)
2213                 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X",
2214                                  sh->dv_meta_mask, meta);
2215         else
2216                 sh->dv_meta_mask = meta;
2217         if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0)
2218                 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X",
2219                                  sh->dv_meta_mask, reg_c0);
2220         else
2221                 sh->dv_regc0_mask = reg_c0;
2222         DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en);
2223         DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask);
2224         DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask);
2225         DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask);
2226 }
2227
2228 int
2229 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
2230 {
2231         static const char *const dynf_names[] = {
2232                 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE,
2233                 RTE_MBUF_DYNFLAG_METADATA_NAME,
2234                 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME
2235         };
2236         unsigned int i;
2237
2238         if (n < RTE_DIM(dynf_names))
2239                 return -ENOMEM;
2240         for (i = 0; i < RTE_DIM(dynf_names); i++) {
2241                 if (names[i] == NULL)
2242                         return -EINVAL;
2243                 strcpy(names[i], dynf_names[i]);
2244         }
2245         return RTE_DIM(dynf_names);
2246 }
2247
2248 /**
2249  * Comparison callback to sort device data.
2250  *
2251  * This is meant to be used with qsort().
2252  *
2253  * @param a[in]
2254  *   Pointer to pointer to first data object.
2255  * @param b[in]
2256  *   Pointer to pointer to second data object.
2257  *
2258  * @return
2259  *   0 if both objects are equal, less than 0 if the first argument is less
2260  *   than the second, greater than 0 otherwise.
2261  */
2262 int
2263 mlx5_dev_check_sibling_config(struct mlx5_priv *priv,
2264                               struct mlx5_dev_config *config)
2265 {
2266         struct mlx5_dev_ctx_shared *sh = priv->sh;
2267         struct mlx5_dev_config *sh_conf = NULL;
2268         uint16_t port_id;
2269
2270         MLX5_ASSERT(sh);
2271         /* Nothing to compare for the single/first device. */
2272         if (sh->refcnt == 1)
2273                 return 0;
2274         /* Find the device with shared context. */
2275         MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) {
2276                 struct mlx5_priv *opriv =
2277                         rte_eth_devices[port_id].data->dev_private;
2278
2279                 if (opriv && opriv != priv && opriv->sh == sh) {
2280                         sh_conf = &opriv->config;
2281                         break;
2282                 }
2283         }
2284         if (!sh_conf)
2285                 return 0;
2286         if (sh_conf->dv_flow_en ^ config->dv_flow_en) {
2287                 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch"
2288                              " for shared %s context", sh->ibdev_name);
2289                 rte_errno = EINVAL;
2290                 return rte_errno;
2291         }
2292         if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) {
2293                 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch"
2294                              " for shared %s context", sh->ibdev_name);
2295                 rte_errno = EINVAL;
2296                 return rte_errno;
2297         }
2298         return 0;
2299 }
2300
2301 /**
2302  * Look for the ethernet device belonging to mlx5 driver.
2303  *
2304  * @param[in] port_id
2305  *   port_id to start looking for device.
2306  * @param[in] pci_dev
2307  *   Pointer to the hint PCI device. When device is being probed
2308  *   the its siblings (master and preceding representors might
2309  *   not have assigned driver yet (because the mlx5_os_pci_probe()
2310  *   is not completed yet, for this case match on hint PCI
2311  *   device may be used to detect sibling device.
2312  *
2313  * @return
2314  *   port_id of found device, RTE_MAX_ETHPORT if not found.
2315  */
2316 uint16_t
2317 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev)
2318 {
2319         while (port_id < RTE_MAX_ETHPORTS) {
2320                 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
2321
2322                 if (dev->state != RTE_ETH_DEV_UNUSED &&
2323                     dev->device &&
2324                     (dev->device == &pci_dev->device ||
2325                      (dev->device->driver &&
2326                      dev->device->driver->name &&
2327                      !strcmp(dev->device->driver->name, MLX5_PCI_DRIVER_NAME))))
2328                         break;
2329                 port_id++;
2330         }
2331         if (port_id >= RTE_MAX_ETHPORTS)
2332                 return RTE_MAX_ETHPORTS;
2333         return port_id;
2334 }
2335
2336 /**
2337  * DPDK callback to remove a PCI device.
2338  *
2339  * This function removes all Ethernet devices belong to a given PCI device.
2340  *
2341  * @param[in] pci_dev
2342  *   Pointer to the PCI device.
2343  *
2344  * @return
2345  *   0 on success, the function cannot fail.
2346  */
2347 static int
2348 mlx5_pci_remove(struct rte_pci_device *pci_dev)
2349 {
2350         uint16_t port_id;
2351         int ret = 0;
2352
2353         RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) {
2354                 /*
2355                  * mlx5_dev_close() is not registered to secondary process,
2356                  * call the close function explicitly for secondary process.
2357                  */
2358                 if (rte_eal_process_type() == RTE_PROC_SECONDARY)
2359                         ret |= mlx5_dev_close(&rte_eth_devices[port_id]);
2360                 else
2361                         ret |= rte_eth_dev_close(port_id);
2362         }
2363         return ret == 0 ? 0 : -EIO;
2364 }
2365
2366 static const struct rte_pci_id mlx5_pci_id_map[] = {
2367         {
2368                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2369                                PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2370         },
2371         {
2372                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2373                                PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2374         },
2375         {
2376                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2377                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2378         },
2379         {
2380                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2381                                PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2382         },
2383         {
2384                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2385                                PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2386         },
2387         {
2388                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2389                                PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2390         },
2391         {
2392                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2393                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2394         },
2395         {
2396                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2397                                PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2398         },
2399         {
2400                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2401                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2402         },
2403         {
2404                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2405                                PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2406         },
2407         {
2408                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2409                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2410         },
2411         {
2412                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2413                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2414         },
2415         {
2416                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2417                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX)
2418         },
2419         {
2420                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2421                                 PCI_DEVICE_ID_MELLANOX_CONNECTXVF)
2422         },
2423         {
2424                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2425                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
2426         },
2427         {
2428                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2429                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX)
2430         },
2431         {
2432                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2433                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7)
2434         },
2435         {
2436                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2437                                 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF)
2438         },
2439         {
2440                 .vendor_id = 0
2441         }
2442 };
2443
2444 static struct mlx5_pci_driver mlx5_driver = {
2445         .driver_class = MLX5_CLASS_NET,
2446         .pci_driver = {
2447                 .driver = {
2448                         .name = MLX5_PCI_DRIVER_NAME,
2449                 },
2450                 .id_table = mlx5_pci_id_map,
2451                 .probe = mlx5_os_pci_probe,
2452                 .remove = mlx5_pci_remove,
2453                 .dma_map = mlx5_dma_map,
2454                 .dma_unmap = mlx5_dma_unmap,
2455                 .drv_flags = PCI_DRV_FLAGS,
2456         },
2457 };
2458
2459 /* Initialize driver log type. */
2460 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE)
2461
2462 /**
2463  * Driver initialization routine.
2464  */
2465 RTE_INIT(rte_mlx5_pmd_init)
2466 {
2467         pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL);
2468         mlx5_common_init();
2469         /* Build the static tables for Verbs conversion. */
2470         mlx5_set_ptype_table();
2471         mlx5_set_cksum_table();
2472         mlx5_set_swp_types_table();
2473         if (mlx5_glue)
2474                 mlx5_pci_driver_register(&mlx5_driver);
2475 }
2476
2477 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
2478 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
2479 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");