1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
57 /** Switch information returned by mlx5_nl_switch_info(). */
58 struct mlx5_switch_info {
59 uint32_t master:1; /**< Master device. */
60 uint32_t representor:1; /**< Representor device. */
61 int32_t port_name; /**< Representor port name. */
62 uint64_t switch_id; /**< Switch identifier. */
65 LIST_HEAD(mlx5_dev_list, priv);
67 /* Shared memory between primary and secondary processes. */
68 struct mlx5_shared_data {
69 struct mlx5_dev_list mem_event_cb_list;
70 rte_rwlock_t mem_event_rwlock;
73 extern struct mlx5_shared_data *mlx5_shared_data;
75 struct mlx5_xstats_ctrl {
76 /* Number of device stats. */
78 /* Index in the device counters table. */
79 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
80 uint64_t base[MLX5_MAX_XSTATS];
84 TAILQ_HEAD(mlx5_flows, rte_flow);
86 /* Default PMD specific parameter value. */
87 #define MLX5_ARG_UNSET (-1)
90 * Device configuration structure.
92 * Merged configuration from:
94 * - Device capabilities,
95 * - User device parameters disabled features.
97 struct mlx5_dev_config {
98 unsigned int hw_csum:1; /* Checksum offload is supported. */
99 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
100 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
101 unsigned int hw_padding:1; /* End alignment padding is supported. */
102 unsigned int vf:1; /* This is a VF. */
103 unsigned int tunnel_en:1;
104 /* Whether tunnel stateless offloads are supported. */
105 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
106 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */
107 unsigned int cqe_comp:1; /* CQE compression is enabled. */
108 unsigned int tso:1; /* Whether TSO is supported. */
109 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
110 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
111 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
112 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
113 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
114 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
116 unsigned int enabled:1; /* Whether MPRQ is enabled. */
117 unsigned int stride_num_n; /* Number of strides. */
118 unsigned int min_stride_size_n; /* Min size of a stride. */
119 unsigned int max_stride_size_n; /* Max size of a stride. */
120 unsigned int max_memcpy_len;
121 /* Maximum packet size to memcpy Rx packets. */
122 unsigned int min_rxqs_num;
123 /* Rx queue count threshold to enable MPRQ. */
124 } mprq; /* Configurations for Multi-Packet RQ. */
125 int mps; /* Multi-packet send supported mode. */
126 unsigned int flow_prio; /* Number of flow priorities. */
127 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
128 unsigned int ind_table_max_size; /* Maximum indirection table size. */
129 int txq_inline; /* Maximum packet size for inlining. */
130 int txqs_inline; /* Queue number threshold for inlining. */
131 int inline_max_packet_sz; /* Max packet size for inlining. */
135 * Type of objet being allocated.
137 enum mlx5_verbs_alloc_type {
138 MLX5_VERBS_ALLOC_TYPE_NONE,
139 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
140 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
144 * Verbs allocator needs a context to know in the callback which kind of
145 * resources it is allocating.
147 struct mlx5_verbs_alloc_ctx {
148 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
149 const void *obj; /* Pointer to the DPDK object. */
152 LIST_HEAD(mlx5_mr_list, mlx5_mr);
154 /* Flow drop context necessary due to Verbs API. */
156 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
157 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
160 /** DPDK port to network interface index (ifindex) conversion. */
161 struct mlx5_nl_flow_ptoi {
162 uint16_t port_id; /**< DPDK port ID. */
163 unsigned int ifindex; /**< Network interface index. */
169 LIST_ENTRY(priv) mem_event_cb; /* Called by memory event callback. */
170 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
171 struct ibv_context *ctx; /* Verbs context. */
172 struct ibv_device_attr_ex device_attr; /* Device properties. */
173 struct ibv_pd *pd; /* Protection Domain. */
174 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
175 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
176 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
177 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
178 /* Bit-field of MAC addresses owned by the PMD. */
179 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
180 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
181 /* Device properties. */
182 uint16_t mtu; /* Configured MTU. */
183 unsigned int isolated:1; /* Whether isolated mode is enabled. */
184 unsigned int representor:1; /* Device is a port representor. */
185 uint16_t domain_id; /* Switch domain identifier. */
186 int32_t representor_id; /* Port representor identifier. */
188 unsigned int rxqs_n; /* RX queues array size. */
189 unsigned int txqs_n; /* TX queues array size. */
190 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
191 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
192 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
193 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
194 struct rte_intr_handle intr_handle; /* Interrupt handler. */
195 unsigned int (*reta_idx)[]; /* RETA index table. */
196 unsigned int reta_idx_n; /* RETA index size. */
197 struct mlx5_drop drop_queue; /* Flow drop queues. */
198 struct mlx5_flows flows; /* RTE Flow rules. */
199 struct mlx5_flows ctrl_flows; /* Control flow rules. */
200 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
203 uint32_t dev_gen; /* Generation number to flush local caches. */
204 rte_rwlock_t rwlock; /* MR Lock. */
205 struct mlx5_mr_btree cache; /* Global MR cache table. */
206 struct mlx5_mr_list mr_list; /* Registered MR list. */
207 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
209 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
210 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
211 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
212 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
213 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
214 /* Verbs Indirection tables. */
215 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
216 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
217 uint32_t link_speed_capa; /* Link speed capabilities. */
218 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
219 int primary_socket; /* Unix socket for primary process. */
220 void *uar_base; /* Reserved address space for UAR mapping */
221 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */
222 struct mlx5_dev_config config; /* Device configuration. */
223 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
224 /* Context for Verbs allocator. */
225 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
226 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
227 uint32_t nl_sn; /* Netlink message sequence number. */
229 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
230 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
231 /* UAR same-page access control required in 32bit implementations. */
233 struct mnl_socket *mnl_socket; /* Libmnl socket. */
236 #define PORT_ID(priv) ((priv)->dev_data->port_id)
237 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
241 int mlx5_getenv_int(const char *);
245 int mlx5_get_master_ifname(const struct rte_eth_dev *dev,
246 char (*ifname)[IF_NAMESIZE]);
247 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
248 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
249 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr,
251 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
252 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
254 int mlx5_dev_configure(struct rte_eth_dev *dev);
255 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
256 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
257 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
258 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
259 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
260 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
263 struct rte_eth_fc_conf *fc_conf);
264 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
265 struct rte_pci_addr *pci_addr);
266 void mlx5_dev_link_status_handler(void *arg);
267 void mlx5_dev_interrupt_handler(void *arg);
268 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
269 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
270 int mlx5_set_link_down(struct rte_eth_dev *dev);
271 int mlx5_set_link_up(struct rte_eth_dev *dev);
272 int mlx5_is_removed(struct rte_eth_dev *dev);
273 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
274 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
275 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
277 unsigned int port_list_n);
278 int mlx5_sysfs_switch_info(unsigned int ifindex,
279 struct mlx5_switch_info *info);
283 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
284 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
285 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
286 uint32_t index, uint32_t vmdq);
287 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
288 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
289 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
293 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
294 struct rte_eth_rss_conf *rss_conf);
295 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
296 struct rte_eth_rss_conf *rss_conf);
297 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
298 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
299 struct rte_eth_rss_reta_entry64 *reta_conf,
301 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
307 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
308 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
309 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
310 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
314 void mlx5_xstats_init(struct rte_eth_dev *dev);
315 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
316 void mlx5_stats_reset(struct rte_eth_dev *dev);
317 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
319 void mlx5_xstats_reset(struct rte_eth_dev *dev);
320 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
321 struct rte_eth_xstat_name *xstats_names,
326 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
327 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
328 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
332 int mlx5_dev_start(struct rte_eth_dev *dev);
333 void mlx5_dev_stop(struct rte_eth_dev *dev);
334 int mlx5_traffic_enable(struct rte_eth_dev *dev);
335 void mlx5_traffic_disable(struct rte_eth_dev *dev);
336 int mlx5_traffic_restart(struct rte_eth_dev *dev);
340 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
341 void mlx5_flow_print(struct rte_flow *flow);
342 int mlx5_flow_validate(struct rte_eth_dev *dev,
343 const struct rte_flow_attr *attr,
344 const struct rte_flow_item items[],
345 const struct rte_flow_action actions[],
346 struct rte_flow_error *error);
347 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
348 const struct rte_flow_attr *attr,
349 const struct rte_flow_item items[],
350 const struct rte_flow_action actions[],
351 struct rte_flow_error *error);
352 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
353 struct rte_flow_error *error);
354 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
355 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
356 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
357 const struct rte_flow_action *action, void *data,
358 struct rte_flow_error *error);
359 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
360 struct rte_flow_error *error);
361 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
362 enum rte_filter_type filter_type,
363 enum rte_filter_op filter_op,
365 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
366 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
367 int mlx5_flow_verify(struct rte_eth_dev *dev);
368 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
369 struct rte_flow_item_eth *eth_spec,
370 struct rte_flow_item_eth *eth_mask,
371 struct rte_flow_item_vlan *vlan_spec,
372 struct rte_flow_item_vlan *vlan_mask);
373 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
374 struct rte_flow_item_eth *eth_spec,
375 struct rte_flow_item_eth *eth_mask);
376 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
377 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
381 int mlx5_socket_init(struct rte_eth_dev *priv);
382 void mlx5_socket_uninit(struct rte_eth_dev *priv);
383 void mlx5_socket_handle(struct rte_eth_dev *priv);
384 int mlx5_socket_connect(struct rte_eth_dev *priv);
388 int mlx5_nl_init(int protocol);
389 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
391 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
393 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
394 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
395 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
396 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
397 unsigned int mlx5_nl_ifindex(int nl, const char *name);
398 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
399 struct mlx5_switch_info *info);
403 int mlx5_nl_flow_transpose(void *buf,
405 const struct mlx5_nl_flow_ptoi *ptoi,
406 const struct rte_flow_attr *attr,
407 const struct rte_flow_item *pattern,
408 const struct rte_flow_action *actions,
409 struct rte_flow_error *error);
410 void mlx5_nl_flow_brand(void *buf, uint32_t handle);
411 int mlx5_nl_flow_create(struct mnl_socket *nl, void *buf,
412 struct rte_flow_error *error);
413 int mlx5_nl_flow_destroy(struct mnl_socket *nl, void *buf,
414 struct rte_flow_error *error);
415 int mlx5_nl_flow_init(struct mnl_socket *nl, unsigned int ifindex,
416 struct rte_flow_error *error);
417 struct mnl_socket *mlx5_nl_flow_socket_create(void);
418 void mlx5_nl_flow_socket_destroy(struct mnl_socket *nl);
420 #endif /* RTE_PMD_MLX5_H_ */