1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
13 #include <netinet/in.h>
14 #include <sys/queue.h>
17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
19 #pragma GCC diagnostic ignored "-Wpedantic"
21 #include <infiniband/verbs.h>
23 #pragma GCC diagnostic error "-Wpedantic"
27 #include <rte_ether.h>
28 #include <rte_ethdev_driver.h>
29 #include <rte_rwlock.h>
30 #include <rte_interrupts.h>
31 #include <rte_errno.h>
34 #include "mlx5_utils.h"
36 #include "mlx5_rxtx.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
41 PCI_VENDOR_ID_MELLANOX = 0x15b3,
45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013,
46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014,
47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015,
48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016,
49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017,
50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018,
51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019,
52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a,
53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2,
54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3,
55 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b,
56 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c,
59 /* Request types for IPC. */
60 enum mlx5_mp_req_type {
61 MLX5_MP_REQ_VERBS_CMD_FD = 1,
64 /* Pameters for IPC. */
65 struct mlx5_mp_param {
66 enum mlx5_mp_req_type type;
71 /** Request timeout for IPC. */
72 #define MLX5_MP_REQ_TIMEOUT_SEC 5
74 /** Key string for IPC. */
75 #define MLX5_MP_NAME "net_mlx5_mp"
77 /** Switch information returned by mlx5_nl_switch_info(). */
78 struct mlx5_switch_info {
79 uint32_t master:1; /**< Master device. */
80 uint32_t representor:1; /**< Representor device. */
81 uint32_t port_name_new:1; /**< Rep. port name is in new format. */
82 int32_t port_name; /**< Representor port name. */
83 uint64_t switch_id; /**< Switch identifier. */
86 LIST_HEAD(mlx5_dev_list, mlx5_priv);
88 /* Shared memory between primary and secondary processes. */
89 struct mlx5_shared_data {
90 struct mlx5_dev_list mem_event_cb_list;
91 rte_rwlock_t mem_event_rwlock;
94 extern struct mlx5_shared_data *mlx5_shared_data;
96 struct mlx5_counter_ctrl {
97 /* Name of the counter. */
98 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
99 /* Name of the counter on the device table. */
100 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
101 uint32_t ib:1; /**< Nonzero for IB counters. */
104 struct mlx5_xstats_ctrl {
105 /* Number of device stats. */
107 /* Number of device stats identified by PMD. */
108 uint16_t mlx5_stats_n;
109 /* Index in the device counters table. */
110 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
111 uint64_t base[MLX5_MAX_XSTATS];
112 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
115 struct mlx5_stats_ctrl {
116 /* Base for imissed counter. */
117 uint64_t imissed_base;
120 /* devx counter object */
121 struct mlx5_devx_counter_set {
122 struct mlx5dv_devx_obj *obj;
123 int id; /* Flow counter ID */
127 TAILQ_HEAD(mlx5_flows, rte_flow);
129 /* Default PMD specific parameter value. */
130 #define MLX5_ARG_UNSET (-1)
133 * Device configuration structure.
135 * Merged configuration from:
137 * - Device capabilities,
138 * - User device parameters disabled features.
140 struct mlx5_dev_config {
141 unsigned int hw_csum:1; /* Checksum offload is supported. */
142 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
143 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
144 unsigned int hw_padding:1; /* End alignment padding is supported. */
145 unsigned int vf:1; /* This is a VF. */
146 unsigned int tunnel_en:1;
147 /* Whether tunnel stateless offloads are supported. */
148 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
149 unsigned int cqe_comp:1; /* CQE compression is enabled. */
150 unsigned int cqe_pad:1; /* CQE padding is enabled. */
151 unsigned int tso:1; /* Whether TSO is supported. */
152 unsigned int tx_vec_en:1; /* Tx vector is enabled. */
153 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
154 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
155 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
156 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
157 unsigned int dv_flow_en:1; /* Enable DV flow. */
158 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
159 unsigned int devx:1; /* Whether devx interface is available or not. */
161 unsigned int enabled:1; /* Whether MPRQ is enabled. */
162 unsigned int stride_num_n; /* Number of strides. */
163 unsigned int min_stride_size_n; /* Min size of a stride. */
164 unsigned int max_stride_size_n; /* Max size of a stride. */
165 unsigned int max_memcpy_len;
166 /* Maximum packet size to memcpy Rx packets. */
167 unsigned int min_rxqs_num;
168 /* Rx queue count threshold to enable MPRQ. */
169 } mprq; /* Configurations for Multi-Packet RQ. */
170 int mps; /* Multi-packet send supported mode. */
171 unsigned int flow_prio; /* Number of flow priorities. */
172 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
173 unsigned int ind_table_max_size; /* Maximum indirection table size. */
174 int txq_inline; /* Maximum packet size for inlining. */
175 int txqs_inline; /* Queue number threshold for inlining. */
176 int txqs_vec; /* Queue number threshold for vectorized Tx. */
177 int inline_max_packet_sz; /* Max packet size for inlining. */
181 * Type of objet being allocated.
183 enum mlx5_verbs_alloc_type {
184 MLX5_VERBS_ALLOC_TYPE_NONE,
185 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
186 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
190 * Verbs allocator needs a context to know in the callback which kind of
191 * resources it is allocating.
193 struct mlx5_verbs_alloc_ctx {
194 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
195 const void *obj; /* Pointer to the DPDK object. */
198 LIST_HEAD(mlx5_mr_list, mlx5_mr);
200 /* Flow drop context necessary due to Verbs API. */
202 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
203 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */
206 struct mlx5_flow_tcf_context;
208 /* Per port data of shared IB device. */
209 struct mlx5_ibv_shared_port {
212 * Interrupt handler port_id. Used by shared interrupt
213 * handler to find the corresponding rte_eth device
214 * by IB port index. If value is equal or greater
215 * RTE_MAX_ETHPORTS it means there is no subhandler
216 * installed for specified IB port index.
221 * Shared Infiniband device context for Master/Representors
222 * which belong to same IB device with multiple IB ports.
224 struct mlx5_ibv_shared {
225 LIST_ENTRY(mlx5_ibv_shared) next;
227 uint32_t devx:1; /* Opened with DV. */
228 uint32_t max_port; /* Maximal IB device port index. */
229 struct ibv_context *ctx; /* Verbs/DV context. */
230 struct ibv_pd *pd; /* Protection Domain. */
231 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
232 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
233 struct ibv_device_attr_ex device_attr; /* Device properties. */
234 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
235 uint32_t intr_cnt; /* Interrupt handler reference counter. */
236 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
237 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
241 LIST_ENTRY(mlx5_priv) mem_event_cb;
242 /**< Called by memory event callback. */
243 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
244 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
245 uint32_t ibv_port; /* IB device port number. */
246 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
247 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
248 /* Bit-field of MAC addresses owned by the PMD. */
249 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
250 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
251 /* Device properties. */
252 uint16_t mtu; /* Configured MTU. */
253 unsigned int isolated:1; /* Whether isolated mode is enabled. */
254 unsigned int representor:1; /* Device is a port representor. */
255 unsigned int master:1; /* Device is a E-Switch master. */
256 uint16_t domain_id; /* Switch domain identifier. */
257 uint16_t vport_id; /* Associated VF vport index (if any). */
258 int32_t representor_id; /* Port representor identifier. */
260 unsigned int rxqs_n; /* RX queues array size. */
261 unsigned int txqs_n; /* TX queues array size. */
262 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
263 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
264 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
265 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
266 unsigned int (*reta_idx)[]; /* RETA index table. */
267 unsigned int reta_idx_n; /* RETA index size. */
268 struct mlx5_drop drop_queue; /* Flow drop queues. */
269 struct mlx5_flows flows; /* RTE Flow rules. */
270 struct mlx5_flows ctrl_flows; /* Control flow rules. */
271 LIST_HEAD(counters, mlx5_flow_counter) flow_counters;
274 uint32_t dev_gen; /* Generation number to flush local caches. */
275 rte_rwlock_t rwlock; /* MR Lock. */
276 struct mlx5_mr_btree cache; /* Global MR cache table. */
277 struct mlx5_mr_list mr_list; /* Registered MR list. */
278 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
280 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
281 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */
282 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
283 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
284 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */
285 /* Verbs Indirection tables. */
286 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls;
287 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers;
288 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
289 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
290 uint32_t link_speed_capa; /* Link speed capabilities. */
291 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
292 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
293 void *uar_base; /* Reserved address space for UAR mapping */
294 struct mlx5_dev_config config; /* Device configuration. */
295 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
296 /* Context for Verbs allocator. */
297 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
298 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
299 uint32_t nl_sn; /* Netlink message sequence number. */
301 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
302 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
303 /* UAR same-page access control required in 32bit implementations. */
305 struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */
308 #define PORT_ID(priv) ((priv)->dev_data->port_id)
309 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
313 int mlx5_getenv_int(const char *);
317 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
318 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
319 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
320 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
321 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
323 int mlx5_dev_configure(struct rte_eth_dev *dev);
324 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
325 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
326 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
327 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
328 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
329 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
330 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
331 struct rte_eth_fc_conf *fc_conf);
332 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
333 struct rte_eth_fc_conf *fc_conf);
334 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
335 struct rte_pci_addr *pci_addr);
336 void mlx5_dev_link_status_handler(void *arg);
337 void mlx5_dev_interrupt_handler(void *arg);
338 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
339 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
340 int mlx5_set_link_down(struct rte_eth_dev *dev);
341 int mlx5_set_link_up(struct rte_eth_dev *dev);
342 int mlx5_is_removed(struct rte_eth_dev *dev);
343 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
344 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
345 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev,
347 unsigned int port_list_n);
348 int mlx5_sysfs_switch_info(unsigned int ifindex,
349 struct mlx5_switch_info *info);
350 bool mlx5_translate_port_name(const char *port_name_in,
351 struct mlx5_switch_info *port_info_out);
355 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]);
356 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
357 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
358 uint32_t index, uint32_t vmdq);
359 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr);
360 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
361 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr);
365 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
366 struct rte_eth_rss_conf *rss_conf);
367 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
368 struct rte_eth_rss_conf *rss_conf);
369 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
370 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
371 struct rte_eth_rss_reta_entry64 *reta_conf,
373 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
374 struct rte_eth_rss_reta_entry64 *reta_conf,
379 void mlx5_promiscuous_enable(struct rte_eth_dev *dev);
380 void mlx5_promiscuous_disable(struct rte_eth_dev *dev);
381 void mlx5_allmulticast_enable(struct rte_eth_dev *dev);
382 void mlx5_allmulticast_disable(struct rte_eth_dev *dev);
386 void mlx5_stats_init(struct rte_eth_dev *dev);
387 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
388 void mlx5_stats_reset(struct rte_eth_dev *dev);
389 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
391 void mlx5_xstats_reset(struct rte_eth_dev *dev);
392 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
393 struct rte_eth_xstat_name *xstats_names,
398 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
399 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
400 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
404 int mlx5_dev_start(struct rte_eth_dev *dev);
405 void mlx5_dev_stop(struct rte_eth_dev *dev);
406 int mlx5_traffic_enable(struct rte_eth_dev *dev);
407 void mlx5_traffic_disable(struct rte_eth_dev *dev);
408 int mlx5_traffic_restart(struct rte_eth_dev *dev);
412 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
413 void mlx5_flow_print(struct rte_flow *flow);
414 int mlx5_flow_validate(struct rte_eth_dev *dev,
415 const struct rte_flow_attr *attr,
416 const struct rte_flow_item items[],
417 const struct rte_flow_action actions[],
418 struct rte_flow_error *error);
419 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
420 const struct rte_flow_attr *attr,
421 const struct rte_flow_item items[],
422 const struct rte_flow_action actions[],
423 struct rte_flow_error *error);
424 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
425 struct rte_flow_error *error);
426 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list);
427 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
428 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
429 const struct rte_flow_action *action, void *data,
430 struct rte_flow_error *error);
431 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
432 struct rte_flow_error *error);
433 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
434 enum rte_filter_type filter_type,
435 enum rte_filter_op filter_op,
437 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
438 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
439 int mlx5_flow_verify(struct rte_eth_dev *dev);
440 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
441 struct rte_flow_item_eth *eth_spec,
442 struct rte_flow_item_eth *eth_mask,
443 struct rte_flow_item_vlan *vlan_spec,
444 struct rte_flow_item_vlan *vlan_mask);
445 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
446 struct rte_flow_item_eth *eth_spec,
447 struct rte_flow_item_eth *eth_mask);
448 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
449 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
452 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
453 void mlx5_mp_init(void);
457 int mlx5_nl_init(int protocol);
458 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac,
460 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac,
462 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev);
463 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev);
464 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable);
465 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable);
466 unsigned int mlx5_nl_portnum(int nl, const char *name);
467 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex);
468 int mlx5_nl_switch_info(int nl, unsigned int ifindex,
469 struct mlx5_switch_info *info);
471 /* mlx5_devx_cmds.c */
473 int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
474 struct mlx5_devx_counter_set *dcx);
475 int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj);
476 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx,
478 uint64_t *pkts, uint64_t *bytes);
479 #endif /* RTE_PMD_MLX5_H_ */