1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include <mlx5_glue.h>
36 #include <mlx5_devx_cmds.h>
40 #include "mlx5_defs.h"
41 #include "mlx5_utils.h"
43 #include "mlx5_autoconf.h"
45 /* Request types for IPC. */
46 enum mlx5_mp_req_type {
47 MLX5_MP_REQ_VERBS_CMD_FD = 1,
48 MLX5_MP_REQ_CREATE_MR,
49 MLX5_MP_REQ_START_RXTX,
50 MLX5_MP_REQ_STOP_RXTX,
51 MLX5_MP_REQ_QUEUE_STATE_MODIFY,
54 struct mlx5_mp_arg_queue_state_modify {
55 uint8_t is_wq; /* Set if WQ. */
56 uint16_t queue_id; /* DPDK queue ID. */
57 enum ibv_wq_state state; /* WQ requested state. */
60 /* Pameters for IPC. */
61 struct mlx5_mp_param {
62 enum mlx5_mp_req_type type;
67 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */
68 struct mlx5_mp_arg_queue_state_modify state_modify;
69 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */
73 /** Request timeout for IPC. */
74 #define MLX5_MP_REQ_TIMEOUT_SEC 5
76 /** Key string for IPC. */
77 #define MLX5_MP_NAME "net_mlx5_mp"
80 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
82 /* Shared data between primary and secondary processes. */
83 struct mlx5_shared_data {
85 /* Global spinlock for primary and secondary processes. */
86 int init_done; /* Whether primary has done initialization. */
87 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
88 struct mlx5_dev_list mem_event_cb_list;
89 rte_rwlock_t mem_event_rwlock;
92 /* Per-process data structure, not visible to other processes. */
93 struct mlx5_local_data {
94 int init_done; /* Whether a secondary has done initialization. */
97 extern struct mlx5_shared_data *mlx5_shared_data;
99 struct mlx5_counter_ctrl {
100 /* Name of the counter. */
101 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
102 /* Name of the counter on the device table. */
103 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
104 uint32_t ib:1; /**< Nonzero for IB counters. */
107 struct mlx5_xstats_ctrl {
108 /* Number of device stats. */
110 /* Number of device stats identified by PMD. */
111 uint16_t mlx5_stats_n;
112 /* Index in the device counters table. */
113 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
114 uint64_t base[MLX5_MAX_XSTATS];
115 uint64_t xstats[MLX5_MAX_XSTATS];
116 uint64_t hw_stats[MLX5_MAX_XSTATS];
117 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
120 struct mlx5_stats_ctrl {
121 /* Base for imissed counter. */
122 uint64_t imissed_base;
127 TAILQ_HEAD(mlx5_flows, rte_flow);
129 /* Default PMD specific parameter value. */
130 #define MLX5_ARG_UNSET (-1)
132 #define MLX5_LRO_SUPPORTED(dev) \
133 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
135 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
136 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
138 /* Maximal size of aggregated LRO packet. */
139 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
141 /* LRO configurations structure. */
142 struct mlx5_lro_config {
143 uint32_t supported:1; /* Whether LRO is supported. */
144 uint32_t timeout; /* User configuration. */
148 * Device configuration structure.
150 * Merged configuration from:
152 * - Device capabilities,
153 * - User device parameters disabled features.
155 struct mlx5_dev_config {
156 unsigned int hw_csum:1; /* Checksum offload is supported. */
157 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
158 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
159 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
160 unsigned int hw_padding:1; /* End alignment padding is supported. */
161 unsigned int vf:1; /* This is a VF. */
162 unsigned int tunnel_en:1;
163 /* Whether tunnel stateless offloads are supported. */
164 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
165 unsigned int cqe_comp:1; /* CQE compression is enabled. */
166 unsigned int cqe_pad:1; /* CQE padding is enabled. */
167 unsigned int tso:1; /* Whether TSO is supported. */
168 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
169 unsigned int mr_ext_memseg_en:1;
170 /* Whether memseg should be extended for MR creation. */
171 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
172 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
173 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
174 unsigned int dv_flow_en:1; /* Enable DV flow. */
175 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
176 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
177 unsigned int devx:1; /* Whether devx interface is available or not. */
178 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
180 unsigned int enabled:1; /* Whether MPRQ is enabled. */
181 unsigned int stride_num_n; /* Number of strides. */
182 unsigned int stride_size_n; /* Size of a stride. */
183 unsigned int min_stride_size_n; /* Min size of a stride. */
184 unsigned int max_stride_size_n; /* Max size of a stride. */
185 unsigned int max_memcpy_len;
186 /* Maximum packet size to memcpy Rx packets. */
187 unsigned int min_rxqs_num;
188 /* Rx queue count threshold to enable MPRQ. */
189 } mprq; /* Configurations for Multi-Packet RQ. */
190 int mps; /* Multi-packet send supported mode. */
191 int dbnc; /* Skip doorbell register write barrier. */
192 unsigned int flow_prio; /* Number of flow priorities. */
193 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
194 /* Availibility of mreg_c's. */
195 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
196 unsigned int ind_table_max_size; /* Maximum indirection table size. */
197 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
198 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
199 int txqs_inline; /* Queue number threshold for inlining. */
200 int txq_inline_min; /* Minimal amount of data bytes to inline. */
201 int txq_inline_max; /* Max packet size for inlining with SEND. */
202 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
203 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
204 struct mlx5_lro_config lro; /* LRO configuration. */
209 * Type of object being allocated.
211 enum mlx5_verbs_alloc_type {
212 MLX5_VERBS_ALLOC_TYPE_NONE,
213 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
214 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
217 /* Structure for VF VLAN workaround. */
218 struct mlx5_vf_vlan {
224 * Verbs allocator needs a context to know in the callback which kind of
225 * resources it is allocating.
227 struct mlx5_verbs_alloc_ctx {
228 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
229 const void *obj; /* Pointer to the DPDK object. */
232 LIST_HEAD(mlx5_mr_list, mlx5_mr);
234 /* Flow drop context necessary due to Verbs API. */
236 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
237 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
240 #define MLX5_COUNTERS_PER_POOL 512
241 #define MLX5_MAX_PENDING_QUERIES 4
242 #define MLX5_CNT_CONTAINER_RESIZE 64
244 * The pool index and offset of counter in the pool array makes up the
245 * counter index. In case the counter is from pool 0 and offset 0, it
246 * should plus 1 to avoid index 0, since 0 means invalid counter index
249 #define MLX5_MAKE_CNT_IDX(pi, offset) \
250 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
251 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) (&((struct mlx5_flow_counter_ext *) \
252 ((pool) + 1))[((cnt) - (pool)->counters_raw)])
253 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \
254 (&((struct mlx5_flow_counter_ext *) \
255 ((pool) + 1))[offset])
257 struct mlx5_flow_counter_pool;
259 struct flow_counter_stats {
264 /* Generic counters information. */
265 struct mlx5_flow_counter {
266 TAILQ_ENTRY(mlx5_flow_counter) next;
267 /**< Pointer to the next flow counter structure. */
269 uint64_t hits; /**< Reset value of hits packets. */
270 int64_t query_gen; /**< Generation of the last release. */
272 uint64_t bytes; /**< Reset value of bytes. */
273 void *action; /**< Pointer to the dv action. */
276 /* Extend counters information for none batch counters. */
277 struct mlx5_flow_counter_ext {
278 uint32_t shared:1; /**< Share counter ID with other flow rules. */
280 /**< Whether the counter was allocated by batch command. */
281 uint32_t ref_cnt:30; /**< Reference counter. */
282 uint32_t id; /**< User counter ID. */
283 union { /**< Holds the counters for the rule. */
284 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
285 struct ibv_counter_set *cs;
286 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
287 struct ibv_counters *cs;
289 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
294 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
296 /* Generic counter pool structure - query is in pool resolution. */
297 struct mlx5_flow_counter_pool {
298 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
299 struct mlx5_counters counters; /* Free counter list. */
301 struct mlx5_devx_obj *min_dcs;
302 rte_atomic64_t a64_dcs;
304 /* The devx object of the minimum counter ID. */
305 rte_atomic64_t start_query_gen; /* Query start round. */
306 rte_atomic64_t end_query_gen; /* Query end round. */
307 uint32_t index; /* Pool index in container. */
308 rte_spinlock_t sl; /* The pool lock. */
309 struct mlx5_counter_stats_raw *raw;
310 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
311 struct mlx5_flow_counter counters_raw[MLX5_COUNTERS_PER_POOL];
312 /* The pool counters memory. */
315 struct mlx5_counter_stats_raw;
317 /* Memory management structure for group of counter statistics raws. */
318 struct mlx5_counter_stats_mem_mng {
319 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
320 struct mlx5_counter_stats_raw *raws;
321 struct mlx5_devx_obj *dm;
322 struct mlx5dv_devx_umem *umem;
325 /* Raw memory structure for the counter statistics values of a pool. */
326 struct mlx5_counter_stats_raw {
327 LIST_ENTRY(mlx5_counter_stats_raw) next;
329 struct mlx5_counter_stats_mem_mng *mem_mng;
330 volatile struct flow_counter_stats *data;
333 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
335 /* Container structure for counter pools. */
336 struct mlx5_pools_container {
337 rte_atomic16_t n_valid; /* Number of valid pools. */
338 uint16_t n; /* Number of pools. */
339 struct mlx5_counter_pools pool_list; /* Counter pool list. */
340 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
341 struct mlx5_counter_stats_mem_mng *init_mem_mng;
342 /* Hold the memory management for the next allocated pools raws. */
345 /* Counter global management structure. */
346 struct mlx5_flow_counter_mng {
347 uint8_t mhi[2]; /* master \ host container index. */
348 struct mlx5_pools_container ccont[2 * 2];
349 /* 2 containers for single and for batch for double-buffer. */
350 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
351 uint8_t pending_queries;
354 uint8_t query_thread_on;
355 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
356 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
359 /* Per port data of shared IB device. */
360 struct mlx5_ibv_shared_port {
362 uint32_t devx_ih_port_id;
364 * Interrupt handler port_id. Used by shared interrupt
365 * handler to find the corresponding rte_eth device
366 * by IB port index. If value is equal or greater
367 * RTE_MAX_ETHPORTS it means there is no subhandler
368 * installed for specified IB port index.
372 /* Table key of the hash organization. */
373 union mlx5_flow_tbl_key {
375 /* Table ID should be at the lowest address. */
376 uint32_t table_id; /**< ID of the table. */
377 uint16_t reserved; /**< must be zero for comparison. */
378 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
379 uint8_t direction; /**< 1 - egress, 0 - ingress. */
381 uint64_t v64; /**< full 64bits value of key */
384 /* Table structure. */
385 struct mlx5_flow_tbl_resource {
386 void *obj; /**< Pointer to DR table object. */
387 rte_atomic32_t refcnt; /**< Reference counter. */
390 #define MLX5_MAX_TABLES UINT16_MAX
391 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
392 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
393 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
394 /* Reserve the last two tables for metadata register copy. */
395 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
396 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
397 /* Tables for metering splits should be added here. */
398 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
399 #define MLX5_MAX_TABLES_FDB UINT16_MAX
401 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
402 #define MLX5_DBR_SIZE 8
403 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
404 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
406 struct mlx5_devx_dbr_page {
407 /* Door-bell records, must be first member in structure. */
408 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
409 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
410 struct mlx5dv_devx_umem *umem;
411 uint32_t dbr_count; /* Number of door-bell records in use. */
412 /* 1 bit marks matching door-bell is in use. */
413 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
416 /* ID generation structure. */
417 struct mlx5_flow_id_pool {
418 uint32_t *free_arr; /**< Pointer to the a array of free values. */
420 /**< The next index that can be used without any free elements. */
421 uint32_t *curr; /**< Pointer to the index to pop. */
422 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
423 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
427 * Shared Infiniband device context for Master/Representors
428 * which belong to same IB device with multiple IB ports.
430 struct mlx5_ibv_shared {
431 LIST_ENTRY(mlx5_ibv_shared) next;
433 uint32_t devx:1; /* Opened with DV. */
434 uint32_t max_port; /* Maximal IB device port index. */
435 struct ibv_context *ctx; /* Verbs/DV context. */
436 struct ibv_pd *pd; /* Protection Domain. */
437 uint32_t pdn; /* Protection Domain number. */
438 uint32_t tdn; /* Transport Domain number. */
439 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
440 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
441 struct ibv_device_attr_ex device_attr; /* Device properties. */
442 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
443 /**< Called by memory event callback. */
445 uint32_t dev_gen; /* Generation number to flush local caches. */
446 rte_rwlock_t rwlock; /* MR Lock. */
447 struct mlx5_mr_btree cache; /* Global MR cache table. */
448 struct mlx5_mr_list mr_list; /* Registered MR list. */
449 struct mlx5_mr_list mr_free_list; /* Freed MR list. */
451 /* Shared DV/DR flow data section. */
452 pthread_mutex_t dv_mutex; /* DV context mutex. */
453 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
454 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
455 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
456 uint32_t dv_refcnt; /* DV/DR data reference counter. */
457 void *fdb_domain; /* FDB Direct Rules name space handle. */
458 void *rx_domain; /* RX Direct Rules name space handle. */
459 void *tx_domain; /* TX Direct Rules name space handle. */
460 struct mlx5_hlist *flow_tbls;
461 /* Direct Rules tables for FDB, NIC TX+RX */
462 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
463 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
464 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps;
465 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
466 struct mlx5_hlist *tag_table;
467 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource)
468 port_id_action_list; /* List of port ID actions. */
469 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource)
470 push_vlan_action_list; /* List of push VLAN actions. */
471 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
472 /* Shared interrupt handler section. */
473 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
474 uint32_t intr_cnt; /* Interrupt handler reference counter. */
475 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
476 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
477 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
478 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
479 struct mlx5_devx_obj *tis; /* TIS object. */
480 struct mlx5_devx_obj *td; /* Transport domain. */
481 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
482 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
485 /* Per-process private structure. */
486 struct mlx5_proc_priv {
488 /* Size of UAR register table. */
490 /* Table of UAR registers for each process. */
493 /* MTR profile list. */
494 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
496 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
498 #define MLX5_PROC_PRIV(port_id) \
499 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
502 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
503 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
504 uint32_t ibv_port; /* IB device port number. */
505 struct rte_pci_device *pci_dev; /* Backend PCI device. */
506 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
507 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
508 /* Bit-field of MAC addresses owned by the PMD. */
509 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
510 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
511 /* Device properties. */
512 uint16_t mtu; /* Configured MTU. */
513 unsigned int isolated:1; /* Whether isolated mode is enabled. */
514 unsigned int representor:1; /* Device is a port representor. */
515 unsigned int master:1; /* Device is a E-Switch master. */
516 unsigned int dr_shared:1; /* DV/DR data is shared. */
517 unsigned int counter_fallback:1; /* Use counter fallback management. */
518 unsigned int mtr_en:1; /* Whether support meter. */
519 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
520 uint16_t domain_id; /* Switch domain identifier. */
521 uint16_t vport_id; /* Associated VF vport index (if any). */
522 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
523 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
524 int32_t representor_id; /* Port representor identifier. */
525 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
526 unsigned int if_index; /* Associated kernel network device index. */
528 unsigned int rxqs_n; /* RX queues array size. */
529 unsigned int txqs_n; /* TX queues array size. */
530 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
531 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
532 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
533 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
534 unsigned int (*reta_idx)[]; /* RETA index table. */
535 unsigned int reta_idx_n; /* RETA index size. */
536 struct mlx5_drop drop_queue; /* Flow drop queues. */
537 struct mlx5_flows flows; /* RTE Flow rules. */
538 struct mlx5_flows ctrl_flows; /* Control flow rules. */
539 void *inter_flows; /* Intermediate resources for flow creation. */
540 int flow_idx; /* Intermediate device flow index. */
541 int flow_nested_idx; /* Intermediate device flow index, nested. */
542 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
543 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
544 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
545 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
546 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
547 /* Indirection tables. */
548 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
549 /* Pointer to next element. */
550 rte_atomic32_t refcnt; /**< Reference counter. */
551 struct ibv_flow_action *verbs_action;
552 /**< Verbs modify header action object. */
553 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
554 uint8_t max_lro_msg_size;
555 /* Tags resources cache. */
556 uint32_t link_speed_capa; /* Link speed capabilities. */
557 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
558 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
559 struct mlx5_dev_config config; /* Device configuration. */
560 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
561 /* Context for Verbs allocator. */
562 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
563 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
564 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
565 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
566 struct mlx5_flow_id_pool *qrss_id_pool;
567 struct mlx5_hlist *mreg_cp_tbl;
568 /* Hash table of Rx metadata register copy table. */
569 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
570 uint8_t mtr_color_reg; /* Meter color match REG_C. */
571 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
572 struct mlx5_flow_meters flow_meters; /* MTR list. */
574 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
575 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
576 /* UAR same-page access control required in 32bit implementations. */
578 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
579 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
582 #define PORT_ID(priv) ((priv)->dev_data->port_id)
583 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
587 int mlx5_getenv_int(const char *);
588 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
589 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
590 struct mlx5_devx_dbr_page **dbr_page);
591 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
593 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
594 struct rte_eth_udp_tunnel *udp_tunnel);
595 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
597 /* Macro to iterate over all valid ports for mlx5 driver. */
598 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
599 for (port_id = mlx5_eth_find_next(0, pci_dev); \
600 port_id < RTE_MAX_ETHPORTS; \
601 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
605 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
606 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
607 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
608 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
609 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
610 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
612 int mlx5_dev_configure(struct rte_eth_dev *dev);
613 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
614 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
615 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
616 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
617 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
618 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
619 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
620 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
621 struct rte_eth_fc_conf *fc_conf);
622 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
623 struct rte_eth_fc_conf *fc_conf);
624 void mlx5_dev_link_status_handler(void *arg);
625 void mlx5_dev_interrupt_handler(void *arg);
626 void mlx5_dev_interrupt_handler_devx(void *arg);
627 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
628 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
629 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
630 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
631 int mlx5_set_link_down(struct rte_eth_dev *dev);
632 int mlx5_set_link_up(struct rte_eth_dev *dev);
633 int mlx5_is_removed(struct rte_eth_dev *dev);
634 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
635 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
636 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
637 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
638 int mlx5_sysfs_switch_info(unsigned int ifindex,
639 struct mlx5_switch_info *info);
640 void mlx5_sysfs_check_switch_info(bool device_dir,
641 struct mlx5_switch_info *switch_info);
642 void mlx5_translate_port_name(const char *port_name_in,
643 struct mlx5_switch_info *port_info_out);
644 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
645 rte_intr_callback_fn cb_fn, void *cb_arg);
646 int mlx5_get_module_info(struct rte_eth_dev *dev,
647 struct rte_eth_dev_module_info *modinfo);
648 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
649 struct rte_dev_eeprom_info *info);
650 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
651 struct rte_eth_hairpin_cap *cap);
652 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
656 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
657 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
658 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
659 uint32_t index, uint32_t vmdq);
660 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init
661 (struct rte_eth_dev *dev, uint32_t ifindex);
662 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
663 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
664 struct rte_ether_addr *mc_addr_set,
665 uint32_t nb_mc_addr);
669 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
670 struct rte_eth_rss_conf *rss_conf);
671 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
672 struct rte_eth_rss_conf *rss_conf);
673 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
674 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
675 struct rte_eth_rss_reta_entry64 *reta_conf,
677 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
678 struct rte_eth_rss_reta_entry64 *reta_conf,
683 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
684 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
685 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
686 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
690 void mlx5_stats_init(struct rte_eth_dev *dev);
691 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
692 int mlx5_stats_reset(struct rte_eth_dev *dev);
693 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
695 int mlx5_xstats_reset(struct rte_eth_dev *dev);
696 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
697 struct rte_eth_xstat_name *xstats_names,
702 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
703 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
704 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
705 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx);
706 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
707 struct mlx5_vf_vlan *vf_vlan);
708 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
709 struct mlx5_vf_vlan *vf_vlan);
713 int mlx5_dev_start(struct rte_eth_dev *dev);
714 void mlx5_dev_stop(struct rte_eth_dev *dev);
715 int mlx5_traffic_enable(struct rte_eth_dev *dev);
716 void mlx5_traffic_disable(struct rte_eth_dev *dev);
717 int mlx5_traffic_restart(struct rte_eth_dev *dev);
721 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
722 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
723 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
724 void mlx5_flow_print(struct rte_flow *flow);
725 int mlx5_flow_validate(struct rte_eth_dev *dev,
726 const struct rte_flow_attr *attr,
727 const struct rte_flow_item items[],
728 const struct rte_flow_action actions[],
729 struct rte_flow_error *error);
730 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
731 const struct rte_flow_attr *attr,
732 const struct rte_flow_item items[],
733 const struct rte_flow_action actions[],
734 struct rte_flow_error *error);
735 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
736 struct rte_flow_error *error);
737 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list,
739 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
740 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
741 const struct rte_flow_action *action, void *data,
742 struct rte_flow_error *error);
743 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
744 struct rte_flow_error *error);
745 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
746 enum rte_filter_type filter_type,
747 enum rte_filter_op filter_op,
749 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
750 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
751 int mlx5_flow_start_default(struct rte_eth_dev *dev);
752 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
753 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
754 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
755 int mlx5_flow_verify(struct rte_eth_dev *dev);
756 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
757 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
758 struct rte_flow_item_eth *eth_spec,
759 struct rte_flow_item_eth *eth_mask,
760 struct rte_flow_item_vlan *vlan_spec,
761 struct rte_flow_item_vlan *vlan_mask);
762 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
763 struct rte_flow_item_eth *eth_spec,
764 struct rte_flow_item_eth *eth_mask);
765 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
766 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
767 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
768 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
769 uint64_t async_id, int status);
770 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
771 void mlx5_flow_query_alarm(void *arg);
772 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
773 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
774 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
775 bool clear, uint64_t *pkts, uint64_t *bytes);
776 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
777 struct rte_flow_error *error);
780 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
781 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
782 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr);
783 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev);
784 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev,
785 struct mlx5_mp_arg_queue_state_modify *sm);
786 int mlx5_mp_init_primary(void);
787 void mlx5_mp_uninit_primary(void);
788 int mlx5_mp_init_secondary(void);
789 void mlx5_mp_uninit_secondary(void);
793 int mlx5_pmd_socket_init(void);
795 /* mlx5_flow_meter.c */
797 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
798 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
800 struct mlx5_flow_meter *mlx5_flow_meter_attach
801 (struct mlx5_priv *priv,
803 const struct rte_flow_attr *attr,
804 struct rte_flow_error *error);
805 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
807 #endif /* RTE_PMD_MLX5_H_ */