1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include <mlx5_glue.h>
36 #include <mlx5_devx_cmds.h>
39 #include <mlx5_common_mp.h>
40 #include <mlx5_common_mr.h>
42 #include "mlx5_defs.h"
43 #include "mlx5_utils.h"
44 #include "mlx5_autoconf.h"
46 enum mlx5_ipool_index {
47 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
48 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
49 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
50 MLX5_IPOOL_TAG, /* Pool for tag resource. */
51 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
52 MLX5_IPOOL_JUMP, /* Pool for jump resource. */
54 MLX5_IPOOL_MTR, /* Pool for meter resource. */
55 MLX5_IPOOL_MCP, /* Pool for metadata resource. */
56 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */
57 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */
58 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */
63 * There are three reclaim memory mode supported.
64 * 0(none) means no memory reclaim.
65 * 1(light) means only PMD level reclaim.
66 * 2(aggressive) means both PMD and rdma-core level reclaim.
68 enum mlx5_reclaim_mem_mode {
69 MLX5_RCM_NONE, /* Don't reclaim memory. */
70 MLX5_RCM_LIGHT, /* Reclaim PMD level. */
71 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */
74 /* Device attributes used in mlx5 PMD */
75 struct mlx5_dev_attr {
76 uint64_t device_cap_flags_ex;
81 uint32_t raw_packet_caps;
82 uint32_t max_rwq_indirection_table_size;
84 uint32_t tso_supported_qpts;
87 uint32_t sw_parsing_offloads;
88 uint32_t min_single_stride_log_num_of_bytes;
89 uint32_t max_single_stride_log_num_of_bytes;
90 uint32_t min_single_wqe_log_num_of_strides;
91 uint32_t max_single_wqe_log_num_of_strides;
92 uint32_t stride_supported_qpts;
93 uint32_t tunnel_offloads_caps;
97 /** Key string for IPC. */
98 #define MLX5_MP_NAME "net_mlx5_mp"
101 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared);
103 /* Shared data between primary and secondary processes. */
104 struct mlx5_shared_data {
106 /* Global spinlock for primary and secondary processes. */
107 int init_done; /* Whether primary has done initialization. */
108 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
109 struct mlx5_dev_list mem_event_cb_list;
110 rte_rwlock_t mem_event_rwlock;
113 /* Per-process data structure, not visible to other processes. */
114 struct mlx5_local_data {
115 int init_done; /* Whether a secondary has done initialization. */
118 extern struct mlx5_shared_data *mlx5_shared_data;
120 struct mlx5_counter_ctrl {
121 /* Name of the counter. */
122 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
123 /* Name of the counter on the device table. */
124 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
125 uint32_t ib:1; /**< Nonzero for IB counters. */
128 struct mlx5_xstats_ctrl {
129 /* Number of device stats. */
131 /* Number of device stats identified by PMD. */
132 uint16_t mlx5_stats_n;
133 /* Index in the device counters table. */
134 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
135 uint64_t base[MLX5_MAX_XSTATS];
136 uint64_t xstats[MLX5_MAX_XSTATS];
137 uint64_t hw_stats[MLX5_MAX_XSTATS];
138 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
141 struct mlx5_stats_ctrl {
142 /* Base for imissed counter. */
143 uint64_t imissed_base;
147 /* Default PMD specific parameter value. */
148 #define MLX5_ARG_UNSET (-1)
150 #define MLX5_LRO_SUPPORTED(dev) \
151 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
153 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
154 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
156 /* Maximal size of aggregated LRO packet. */
157 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
159 /* LRO configurations structure. */
160 struct mlx5_lro_config {
161 uint32_t supported:1; /* Whether LRO is supported. */
162 uint32_t timeout; /* User configuration. */
166 * Device configuration structure.
168 * Merged configuration from:
170 * - Device capabilities,
171 * - User device parameters disabled features.
173 struct mlx5_dev_config {
174 unsigned int hw_csum:1; /* Checksum offload is supported. */
175 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
176 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
177 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
178 unsigned int hw_padding:1; /* End alignment padding is supported. */
179 unsigned int vf:1; /* This is a VF. */
180 unsigned int tunnel_en:1;
181 /* Whether tunnel stateless offloads are supported. */
182 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
183 unsigned int cqe_comp:1; /* CQE compression is enabled. */
184 unsigned int cqe_pad:1; /* CQE padding is enabled. */
185 unsigned int tso:1; /* Whether TSO is supported. */
186 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
187 unsigned int mr_ext_memseg_en:1;
188 /* Whether memseg should be extended for MR creation. */
189 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
190 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
191 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
192 unsigned int dv_flow_en:1; /* Enable DV flow. */
193 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
194 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
195 unsigned int devx:1; /* Whether devx interface is available or not. */
196 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
197 unsigned int reclaim_mode:2; /* Memory reclaim mode. */
199 unsigned int enabled:1; /* Whether MPRQ is enabled. */
200 unsigned int stride_num_n; /* Number of strides. */
201 unsigned int stride_size_n; /* Size of a stride. */
202 unsigned int min_stride_size_n; /* Min size of a stride. */
203 unsigned int max_stride_size_n; /* Max size of a stride. */
204 unsigned int max_memcpy_len;
205 /* Maximum packet size to memcpy Rx packets. */
206 unsigned int min_rxqs_num;
207 /* Rx queue count threshold to enable MPRQ. */
208 } mprq; /* Configurations for Multi-Packet RQ. */
209 int mps; /* Multi-packet send supported mode. */
210 int dbnc; /* Skip doorbell register write barrier. */
211 unsigned int flow_prio; /* Number of flow priorities. */
212 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
213 /* Availibility of mreg_c's. */
214 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
215 unsigned int ind_table_max_size; /* Maximum indirection table size. */
216 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
217 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
218 int txqs_inline; /* Queue number threshold for inlining. */
219 int txq_inline_min; /* Minimal amount of data bytes to inline. */
220 int txq_inline_max; /* Max packet size for inlining with SEND. */
221 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
222 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
223 struct mlx5_lro_config lro; /* LRO configuration. */
228 * Type of object being allocated.
230 enum mlx5_verbs_alloc_type {
231 MLX5_VERBS_ALLOC_TYPE_NONE,
232 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
233 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
236 /* Structure for VF VLAN workaround. */
237 struct mlx5_vf_vlan {
243 * Verbs allocator needs a context to know in the callback which kind of
244 * resources it is allocating.
246 struct mlx5_verbs_alloc_ctx {
247 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
248 const void *obj; /* Pointer to the DPDK object. */
251 /* Flow drop context necessary due to Verbs API. */
253 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
254 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
257 #define MLX5_COUNTERS_PER_POOL 512
258 #define MLX5_MAX_PENDING_QUERIES 4
259 #define MLX5_CNT_CONTAINER_RESIZE 64
260 #define MLX5_CNT_AGE_OFFSET 0x80000000
261 #define CNT_SIZE (sizeof(struct mlx5_flow_counter))
262 #define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext))
263 #define AGE_SIZE (sizeof(struct mlx5_age_param))
264 #define MLX5_AGING_TIME_DELAY 7
265 #define CNT_POOL_TYPE_EXT (1 << 0)
266 #define CNT_POOL_TYPE_AGE (1 << 1)
267 #define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT)
268 #define IS_AGE_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_AGE)
269 #define MLX_CNT_IS_AGE(counter) ((counter) & MLX5_CNT_AGE_OFFSET ? 1 : 0)
270 #define MLX5_CNT_LEN(pool) \
272 (IS_AGE_POOL(pool) ? AGE_SIZE : 0) + \
273 (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0))
274 #define MLX5_POOL_GET_CNT(pool, index) \
275 ((struct mlx5_flow_counter *) \
276 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool))))
277 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \
278 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \
281 * The pool index and offset of counter in the pool array makes up the
282 * counter index. In case the counter is from pool 0 and offset 0, it
283 * should plus 1 to avoid index 0, since 0 means invalid counter index
286 #define MLX5_MAKE_CNT_IDX(pi, offset) \
287 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
288 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) \
289 ((struct mlx5_flow_counter_ext *)\
290 ((uint8_t *)((cnt) + 1) + \
291 (IS_AGE_POOL(pool) ? AGE_SIZE : 0)))
292 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \
293 MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset)))
294 #define MLX5_CNT_TO_AGE(cnt) \
295 ((struct mlx5_age_param *)((cnt) + 1))
297 struct mlx5_flow_counter_pool;
301 AGE_FREE, /* Initialized state. */
302 AGE_CANDIDATE, /* Counter assigned to flows. */
303 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */
306 #define MLX5_CNT_CONTAINER(sh, batch, age) (&(sh)->cmng.ccont \
307 [(batch) * 2 + (age)])
310 MLX5_CCONT_TYPE_SINGLE,
311 MLX5_CCONT_TYPE_SINGLE_FOR_AGE,
312 MLX5_CCONT_TYPE_BATCH,
313 MLX5_CCONT_TYPE_BATCH_FOR_AGE,
317 /* Counter age parameter. */
318 struct mlx5_age_param {
319 rte_atomic16_t state; /**< Age state. */
320 uint16_t port_id; /**< Port id of the counter. */
321 uint32_t timeout:15; /**< Age timeout in unit of 0.1sec. */
322 uint32_t expire:16; /**< Expire time(0.1sec) in the future. */
323 void *context; /**< Flow counter age context. */
326 struct flow_counter_stats {
331 /* Generic counters information. */
332 struct mlx5_flow_counter {
333 TAILQ_ENTRY(mlx5_flow_counter) next;
334 /**< Pointer to the next flow counter structure. */
336 uint64_t hits; /**< Reset value of hits packets. */
337 int64_t query_gen; /**< Generation of the last release. */
339 uint64_t bytes; /**< Reset value of bytes. */
340 void *action; /**< Pointer to the dv action. */
343 /* Extend counters information for none batch counters. */
344 struct mlx5_flow_counter_ext {
345 uint32_t shared:1; /**< Share counter ID with other flow rules. */
347 /**< Whether the counter was allocated by batch command. */
348 uint32_t ref_cnt:30; /**< Reference counter. */
349 uint32_t id; /**< User counter ID. */
350 union { /**< Holds the counters for the rule. */
351 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
352 struct ibv_counter_set *cs;
353 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
354 struct ibv_counters *cs;
356 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
360 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
362 /* Generic counter pool structure - query is in pool resolution. */
363 struct mlx5_flow_counter_pool {
364 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
365 struct mlx5_counters counters; /* Free counter list. */
367 struct mlx5_devx_obj *min_dcs;
368 rte_atomic64_t a64_dcs;
370 /* The devx object of the minimum counter ID. */
371 rte_atomic64_t start_query_gen; /* Query start round. */
372 rte_atomic64_t end_query_gen; /* Query end round. */
373 uint32_t index; /* Pool index in container. */
374 uint8_t type; /* Memory type behind the counter array. */
375 rte_spinlock_t sl; /* The pool lock. */
376 struct mlx5_counter_stats_raw *raw;
377 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
380 struct mlx5_counter_stats_raw;
382 /* Memory management structure for group of counter statistics raws. */
383 struct mlx5_counter_stats_mem_mng {
384 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
385 struct mlx5_counter_stats_raw *raws;
386 struct mlx5_devx_obj *dm;
387 struct mlx5dv_devx_umem *umem;
390 /* Raw memory structure for the counter statistics values of a pool. */
391 struct mlx5_counter_stats_raw {
392 LIST_ENTRY(mlx5_counter_stats_raw) next;
394 struct mlx5_counter_stats_mem_mng *mem_mng;
395 volatile struct flow_counter_stats *data;
398 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
400 /* Container structure for counter pools. */
401 struct mlx5_pools_container {
402 rte_atomic16_t n_valid; /* Number of valid pools. */
403 uint16_t n; /* Number of pools. */
404 rte_spinlock_t resize_sl; /* The resize lock. */
405 struct mlx5_counter_pools pool_list; /* Counter pool list. */
406 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
407 struct mlx5_counter_stats_mem_mng *mem_mng;
408 /* Hold the memory management for the next allocated pools raws. */
411 /* Counter global management structure. */
412 struct mlx5_flow_counter_mng {
413 struct mlx5_pools_container ccont[MLX5_CCONT_TYPE_MAX];
414 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
415 uint8_t pending_queries;
419 uint8_t query_thread_on;
420 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
421 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
424 #define MLX5_AGE_EVENT_NEW 1
425 #define MLX5_AGE_TRIGGER 2
426 #define MLX5_AGE_SET(age_info, BIT) \
427 ((age_info)->flags |= (1 << (BIT)))
428 #define MLX5_AGE_GET(age_info, BIT) \
429 ((age_info)->flags & (1 << (BIT)))
430 #define GET_PORT_AGE_INFO(priv) \
431 (&((priv)->sh->port[(priv)->ibv_port - 1].age_info))
433 /* Aging information for per port. */
434 struct mlx5_age_info {
435 uint8_t flags; /*Indicate if is new event or need be trigered*/
436 struct mlx5_counters aged_counters; /* Aged flow counter list. */
437 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */
440 /* Per port data of shared IB device. */
441 struct mlx5_ibv_shared_port {
443 uint32_t devx_ih_port_id;
445 * Interrupt handler port_id. Used by shared interrupt
446 * handler to find the corresponding rte_eth device
447 * by IB port index. If value is equal or greater
448 * RTE_MAX_ETHPORTS it means there is no subhandler
449 * installed for specified IB port index.
451 struct mlx5_age_info age_info;
452 /* Aging information for per port. */
455 /* Table key of the hash organization. */
456 union mlx5_flow_tbl_key {
458 /* Table ID should be at the lowest address. */
459 uint32_t table_id; /**< ID of the table. */
460 uint16_t reserved; /**< must be zero for comparison. */
461 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
462 uint8_t direction; /**< 1 - egress, 0 - ingress. */
464 uint64_t v64; /**< full 64bits value of key */
467 /* Table structure. */
468 struct mlx5_flow_tbl_resource {
469 void *obj; /**< Pointer to DR table object. */
470 rte_atomic32_t refcnt; /**< Reference counter. */
473 #define MLX5_MAX_TABLES UINT16_MAX
474 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
475 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
476 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
477 /* Reserve the last two tables for metadata register copy. */
478 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
479 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
480 /* Tables for metering splits should be added here. */
481 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
482 #define MLX5_MAX_TABLES_FDB UINT16_MAX
484 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
485 #define MLX5_DBR_SIZE 8
486 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
487 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
489 struct mlx5_devx_dbr_page {
490 /* Door-bell records, must be first member in structure. */
491 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
492 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
493 struct mlx5dv_devx_umem *umem;
494 uint32_t dbr_count; /* Number of door-bell records in use. */
495 /* 1 bit marks matching door-bell is in use. */
496 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
499 /* ID generation structure. */
500 struct mlx5_flow_id_pool {
501 uint32_t *free_arr; /**< Pointer to the a array of free values. */
503 /**< The next index that can be used without any free elements. */
504 uint32_t *curr; /**< Pointer to the index to pop. */
505 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
506 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
510 * Shared Infiniband device context for Master/Representors
511 * which belong to same IB device with multiple IB ports.
513 struct mlx5_dev_ctx_shared {
514 LIST_ENTRY(mlx5_dev_ctx_shared) next;
516 uint32_t devx:1; /* Opened with DV. */
517 uint32_t max_port; /* Maximal IB device port index. */
518 void *ctx; /* Verbs/DV/DevX context. */
519 void *pd; /* Protection Domain. */
520 uint32_t pdn; /* Protection Domain number. */
521 uint32_t tdn; /* Transport Domain number. */
522 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
523 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
524 struct mlx5_dev_attr device_attr; /* Device properties. */
525 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb;
526 /**< Called by memory event callback. */
527 struct mlx5_mr_share_cache share_cache;
528 /* Shared DV/DR flow data section. */
529 pthread_mutex_t dv_mutex; /* DV context mutex. */
530 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
531 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
532 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
533 uint32_t dv_refcnt; /* DV/DR data reference counter. */
534 void *fdb_domain; /* FDB Direct Rules name space handle. */
535 void *rx_domain; /* RX Direct Rules name space handle. */
536 void *tx_domain; /* TX Direct Rules name space handle. */
537 struct mlx5_hlist *flow_tbls;
538 /* Direct Rules tables for FDB, NIC TX+RX */
539 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
540 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
541 uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */
542 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
543 struct mlx5_hlist *tag_table;
544 uint32_t port_id_action_list; /* List of port ID actions. */
545 uint32_t push_vlan_action_list; /* List of push VLAN actions. */
546 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
547 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
548 /* Memory Pool for mlx5 flow resources. */
549 /* Shared interrupt handler section. */
550 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
551 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
552 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
553 struct mlx5_devx_obj *tis; /* TIS object. */
554 struct mlx5_devx_obj *td; /* Transport domain. */
555 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
556 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
559 /* Per-process private structure. */
560 struct mlx5_proc_priv {
562 /* Size of UAR register table. */
564 /* Table of UAR registers for each process. */
567 /* MTR profile list. */
568 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
570 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
572 #define MLX5_PROC_PRIV(port_id) \
573 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
576 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
577 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */
578 uint32_t ibv_port; /* IB device port number. */
579 struct rte_pci_device *pci_dev; /* Backend PCI device. */
580 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
581 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
582 /* Bit-field of MAC addresses owned by the PMD. */
583 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
584 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
585 /* Device properties. */
586 uint16_t mtu; /* Configured MTU. */
587 unsigned int isolated:1; /* Whether isolated mode is enabled. */
588 unsigned int representor:1; /* Device is a port representor. */
589 unsigned int master:1; /* Device is a E-Switch master. */
590 unsigned int dr_shared:1; /* DV/DR data is shared. */
591 unsigned int counter_fallback:1; /* Use counter fallback management. */
592 unsigned int mtr_en:1; /* Whether support meter. */
593 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
594 uint16_t domain_id; /* Switch domain identifier. */
595 uint16_t vport_id; /* Associated VF vport index (if any). */
596 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
597 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
598 int32_t representor_id; /* Port representor identifier. */
599 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
600 unsigned int if_index; /* Associated kernel network device index. */
602 unsigned int rxqs_n; /* RX queues array size. */
603 unsigned int txqs_n; /* TX queues array size. */
604 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
605 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
606 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
607 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
608 unsigned int (*reta_idx)[]; /* RETA index table. */
609 unsigned int reta_idx_n; /* RETA index size. */
610 struct mlx5_drop drop_queue; /* Flow drop queues. */
611 uint32_t flows; /* RTE Flow rules. */
612 uint32_t ctrl_flows; /* Control flow rules. */
613 void *inter_flows; /* Intermediate resources for flow creation. */
614 void *rss_desc; /* Intermediate rss description resources. */
615 int flow_idx; /* Intermediate device flow index. */
616 int flow_nested_idx; /* Intermediate device flow index, nested. */
617 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
618 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
619 uint32_t hrxqs; /* Verbs Hash Rx queues. */
620 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
621 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
622 /* Indirection tables. */
623 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
624 /* Pointer to next element. */
625 rte_atomic32_t refcnt; /**< Reference counter. */
626 struct ibv_flow_action *verbs_action;
627 /**< Verbs modify header action object. */
628 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
629 uint8_t max_lro_msg_size;
630 /* Tags resources cache. */
631 uint32_t link_speed_capa; /* Link speed capabilities. */
632 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
633 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
634 struct mlx5_dev_config config; /* Device configuration. */
635 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
636 /* Context for Verbs allocator. */
637 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
638 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
639 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
640 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
641 struct mlx5_flow_id_pool *qrss_id_pool;
642 struct mlx5_hlist *mreg_cp_tbl;
643 /* Hash table of Rx metadata register copy table. */
644 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
645 uint8_t mtr_color_reg; /* Meter color match REG_C. */
646 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
647 struct mlx5_flow_meters flow_meters; /* MTR list. */
649 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
650 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
651 /* UAR same-page access control required in 32bit implementations. */
653 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
654 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
655 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
656 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */
659 #define PORT_ID(priv) ((priv)->dev_data->port_id)
660 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
664 int mlx5_getenv_int(const char *);
665 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
666 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
667 struct mlx5_devx_dbr_page **dbr_page);
668 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
670 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
671 struct rte_eth_udp_tunnel *udp_tunnel);
672 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
674 /* Macro to iterate over all valid ports for mlx5 driver. */
675 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
676 for (port_id = mlx5_eth_find_next(0, pci_dev); \
677 port_id < RTE_MAX_ETHPORTS; \
678 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
682 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
683 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
684 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
685 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
686 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
687 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
689 int mlx5_dev_configure(struct rte_eth_dev *dev);
690 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
691 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
692 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
693 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
694 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
695 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
696 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
697 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
698 struct rte_eth_fc_conf *fc_conf);
699 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
700 struct rte_eth_fc_conf *fc_conf);
701 void mlx5_dev_link_status_handler(void *arg);
702 void mlx5_dev_interrupt_handler(void *arg);
703 void mlx5_dev_interrupt_handler_devx(void *arg);
704 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
705 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
706 int mlx5_set_link_down(struct rte_eth_dev *dev);
707 int mlx5_set_link_up(struct rte_eth_dev *dev);
708 int mlx5_is_removed(struct rte_eth_dev *dev);
709 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
710 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
711 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
712 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
713 int mlx5_sysfs_switch_info(unsigned int ifindex,
714 struct mlx5_switch_info *info);
715 void mlx5_sysfs_check_switch_info(bool device_dir,
716 struct mlx5_switch_info *switch_info);
717 void mlx5_translate_port_name(const char *port_name_in,
718 struct mlx5_switch_info *port_info_out);
719 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
720 rte_intr_callback_fn cb_fn, void *cb_arg);
721 int mlx5_get_module_info(struct rte_eth_dev *dev,
722 struct rte_eth_dev_module_info *modinfo);
723 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
724 struct rte_dev_eeprom_info *info);
725 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
726 struct rte_eth_hairpin_cap *cap);
727 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
731 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
732 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
733 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
734 uint32_t index, uint32_t vmdq);
735 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init
736 (struct rte_eth_dev *dev, uint32_t ifindex);
737 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
738 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
739 struct rte_ether_addr *mc_addr_set,
740 uint32_t nb_mc_addr);
744 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
745 struct rte_eth_rss_conf *rss_conf);
746 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
747 struct rte_eth_rss_conf *rss_conf);
748 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
749 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
750 struct rte_eth_rss_reta_entry64 *reta_conf,
752 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
753 struct rte_eth_rss_reta_entry64 *reta_conf,
758 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
759 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
760 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
761 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
765 void mlx5_stats_init(struct rte_eth_dev *dev);
766 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
767 int mlx5_stats_reset(struct rte_eth_dev *dev);
768 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
770 int mlx5_xstats_reset(struct rte_eth_dev *dev);
771 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
772 struct rte_eth_xstat_name *xstats_names,
777 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
778 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
779 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
780 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx);
781 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
782 struct mlx5_vf_vlan *vf_vlan);
783 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
784 struct mlx5_vf_vlan *vf_vlan);
788 int mlx5_dev_start(struct rte_eth_dev *dev);
789 void mlx5_dev_stop(struct rte_eth_dev *dev);
790 int mlx5_traffic_enable(struct rte_eth_dev *dev);
791 void mlx5_traffic_disable(struct rte_eth_dev *dev);
792 int mlx5_traffic_restart(struct rte_eth_dev *dev);
796 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
797 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
798 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
799 void mlx5_flow_print(struct rte_flow *flow);
800 int mlx5_flow_validate(struct rte_eth_dev *dev,
801 const struct rte_flow_attr *attr,
802 const struct rte_flow_item items[],
803 const struct rte_flow_action actions[],
804 struct rte_flow_error *error);
805 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
806 const struct rte_flow_attr *attr,
807 const struct rte_flow_item items[],
808 const struct rte_flow_action actions[],
809 struct rte_flow_error *error);
810 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
811 struct rte_flow_error *error);
812 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active);
813 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
814 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
815 const struct rte_flow_action *action, void *data,
816 struct rte_flow_error *error);
817 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
818 struct rte_flow_error *error);
819 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
820 enum rte_filter_type filter_type,
821 enum rte_filter_op filter_op,
823 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list);
824 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list);
825 int mlx5_flow_start_default(struct rte_eth_dev *dev);
826 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
827 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
828 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
829 int mlx5_flow_verify(struct rte_eth_dev *dev);
830 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
831 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
832 struct rte_flow_item_eth *eth_spec,
833 struct rte_flow_item_eth *eth_mask,
834 struct rte_flow_item_vlan *vlan_spec,
835 struct rte_flow_item_vlan *vlan_mask);
836 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
837 struct rte_flow_item_eth *eth_spec,
838 struct rte_flow_item_eth *eth_mask);
839 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
840 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
841 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
842 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,
843 uint64_t async_id, int status);
844 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);
845 void mlx5_flow_query_alarm(void *arg);
846 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
847 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
848 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
849 bool clear, uint64_t *pkts, uint64_t *bytes);
850 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
851 struct rte_flow_error *error);
852 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev);
853 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts,
854 uint32_t nb_contexts, struct rte_flow_error *error);
857 int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
858 int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
859 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
860 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
864 int mlx5_pmd_socket_init(void);
866 /* mlx5_flow_meter.c */
868 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
869 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
871 struct mlx5_flow_meter *mlx5_flow_meter_attach
872 (struct mlx5_priv *priv,
874 const struct rte_flow_attr *attr,
875 struct rte_flow_error *error);
876 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
879 const char *mlx5_os_get_ctx_device_name(void *ctx);
880 const char *mlx5_os_get_ctx_device_path(void *ctx);
881 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr);
883 #endif /* RTE_PMD_MLX5_H_ */