1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_H_
7 #define RTE_PMD_MLX5_H_
14 #include <netinet/in.h>
15 #include <sys/queue.h>
18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20 #pragma GCC diagnostic ignored "-Wpedantic"
22 #include <infiniband/verbs.h>
24 #pragma GCC diagnostic error "-Wpedantic"
28 #include <rte_ether.h>
29 #include <rte_ethdev_driver.h>
30 #include <rte_rwlock.h>
31 #include <rte_interrupts.h>
32 #include <rte_errno.h>
35 #include <mlx5_glue.h>
36 #include <mlx5_devx_cmds.h>
39 #include <mlx5_common_mp.h>
40 #include <mlx5_common_mr.h>
42 #include "mlx5_defs.h"
43 #include "mlx5_utils.h"
44 #include "mlx5_autoconf.h"
47 enum mlx5_ipool_index {
48 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */
49 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */
50 MLX5_IPOOL_TAG, /* Pool for tag resource. */
51 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */
55 /** Key string for IPC. */
56 #define MLX5_MP_NAME "net_mlx5_mp"
59 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared);
61 /* Shared data between primary and secondary processes. */
62 struct mlx5_shared_data {
64 /* Global spinlock for primary and secondary processes. */
65 int init_done; /* Whether primary has done initialization. */
66 unsigned int secondary_cnt; /* Number of secondary processes init'd. */
67 struct mlx5_dev_list mem_event_cb_list;
68 rte_rwlock_t mem_event_rwlock;
71 /* Per-process data structure, not visible to other processes. */
72 struct mlx5_local_data {
73 int init_done; /* Whether a secondary has done initialization. */
76 extern struct mlx5_shared_data *mlx5_shared_data;
78 struct mlx5_counter_ctrl {
79 /* Name of the counter. */
80 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE];
81 /* Name of the counter on the device table. */
82 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE];
83 uint32_t ib:1; /**< Nonzero for IB counters. */
86 struct mlx5_xstats_ctrl {
87 /* Number of device stats. */
89 /* Number of device stats identified by PMD. */
90 uint16_t mlx5_stats_n;
91 /* Index in the device counters table. */
92 uint16_t dev_table_idx[MLX5_MAX_XSTATS];
93 uint64_t base[MLX5_MAX_XSTATS];
94 uint64_t xstats[MLX5_MAX_XSTATS];
95 uint64_t hw_stats[MLX5_MAX_XSTATS];
96 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS];
99 struct mlx5_stats_ctrl {
100 /* Base for imissed counter. */
101 uint64_t imissed_base;
106 TAILQ_HEAD(mlx5_flows, rte_flow);
108 /* Default PMD specific parameter value. */
109 #define MLX5_ARG_UNSET (-1)
111 #define MLX5_LRO_SUPPORTED(dev) \
112 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported)
114 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */
115 #define MLX5_LRO_SEG_CHUNK_SIZE 256u
117 /* Maximal size of aggregated LRO packet. */
118 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE)
120 /* LRO configurations structure. */
121 struct mlx5_lro_config {
122 uint32_t supported:1; /* Whether LRO is supported. */
123 uint32_t timeout; /* User configuration. */
127 * Device configuration structure.
129 * Merged configuration from:
131 * - Device capabilities,
132 * - User device parameters disabled features.
134 struct mlx5_dev_config {
135 unsigned int hw_csum:1; /* Checksum offload is supported. */
136 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */
137 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */
138 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */
139 unsigned int hw_padding:1; /* End alignment padding is supported. */
140 unsigned int vf:1; /* This is a VF. */
141 unsigned int tunnel_en:1;
142 /* Whether tunnel stateless offloads are supported. */
143 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */
144 unsigned int cqe_comp:1; /* CQE compression is enabled. */
145 unsigned int cqe_pad:1; /* CQE padding is enabled. */
146 unsigned int tso:1; /* Whether TSO is supported. */
147 unsigned int rx_vec_en:1; /* Rx vector is enabled. */
148 unsigned int mr_ext_memseg_en:1;
149 /* Whether memseg should be extended for MR creation. */
150 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */
151 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */
152 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */
153 unsigned int dv_flow_en:1; /* Enable DV flow. */
154 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */
155 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */
156 unsigned int devx:1; /* Whether devx interface is available or not. */
157 unsigned int dest_tir:1; /* Whether advanced DR API is available. */
159 unsigned int enabled:1; /* Whether MPRQ is enabled. */
160 unsigned int stride_num_n; /* Number of strides. */
161 unsigned int stride_size_n; /* Size of a stride. */
162 unsigned int min_stride_size_n; /* Min size of a stride. */
163 unsigned int max_stride_size_n; /* Max size of a stride. */
164 unsigned int max_memcpy_len;
165 /* Maximum packet size to memcpy Rx packets. */
166 unsigned int min_rxqs_num;
167 /* Rx queue count threshold to enable MPRQ. */
168 } mprq; /* Configurations for Multi-Packet RQ. */
169 int mps; /* Multi-packet send supported mode. */
170 int dbnc; /* Skip doorbell register write barrier. */
171 unsigned int flow_prio; /* Number of flow priorities. */
172 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM];
173 /* Availibility of mreg_c's. */
174 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */
175 unsigned int ind_table_max_size; /* Maximum indirection table size. */
176 unsigned int max_dump_files_num; /* Maximum dump files per queue. */
177 unsigned int log_hp_size; /* Single hairpin queue data size in total. */
178 int txqs_inline; /* Queue number threshold for inlining. */
179 int txq_inline_min; /* Minimal amount of data bytes to inline. */
180 int txq_inline_max; /* Max packet size for inlining with SEND. */
181 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */
182 struct mlx5_hca_attr hca_attr; /* HCA attributes. */
183 struct mlx5_lro_config lro; /* LRO configuration. */
188 * Type of object being allocated.
190 enum mlx5_verbs_alloc_type {
191 MLX5_VERBS_ALLOC_TYPE_NONE,
192 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE,
193 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE,
196 /* Structure for VF VLAN workaround. */
197 struct mlx5_vf_vlan {
203 * Verbs allocator needs a context to know in the callback which kind of
204 * resources it is allocating.
206 struct mlx5_verbs_alloc_ctx {
207 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */
208 const void *obj; /* Pointer to the DPDK object. */
211 /* Flow drop context necessary due to Verbs API. */
213 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */
214 struct mlx5_rxq_obj *rxq; /* Rx queue object. */
217 #define MLX5_COUNTERS_PER_POOL 512
218 #define MLX5_MAX_PENDING_QUERIES 4
219 #define MLX5_CNT_CONTAINER_RESIZE 64
221 * The pool index and offset of counter in the pool array makes up the
222 * counter index. In case the counter is from pool 0 and offset 0, it
223 * should plus 1 to avoid index 0, since 0 means invalid counter index
226 #define MLX5_MAKE_CNT_IDX(pi, offset) \
227 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1)
228 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) (&((struct mlx5_flow_counter_ext *) \
229 ((pool) + 1))[((cnt) - (pool)->counters_raw)])
230 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \
231 (&((struct mlx5_flow_counter_ext *) \
232 ((pool) + 1))[offset])
234 struct mlx5_flow_counter_pool;
236 struct flow_counter_stats {
241 /* Generic counters information. */
242 struct mlx5_flow_counter {
243 TAILQ_ENTRY(mlx5_flow_counter) next;
244 /**< Pointer to the next flow counter structure. */
246 uint64_t hits; /**< Reset value of hits packets. */
247 int64_t query_gen; /**< Generation of the last release. */
249 uint64_t bytes; /**< Reset value of bytes. */
250 void *action; /**< Pointer to the dv action. */
253 /* Extend counters information for none batch counters. */
254 struct mlx5_flow_counter_ext {
255 uint32_t shared:1; /**< Share counter ID with other flow rules. */
257 /**< Whether the counter was allocated by batch command. */
258 uint32_t ref_cnt:30; /**< Reference counter. */
259 uint32_t id; /**< User counter ID. */
260 union { /**< Holds the counters for the rule. */
261 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42)
262 struct ibv_counter_set *cs;
263 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
264 struct ibv_counters *cs;
266 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */
271 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter);
273 /* Generic counter pool structure - query is in pool resolution. */
274 struct mlx5_flow_counter_pool {
275 TAILQ_ENTRY(mlx5_flow_counter_pool) next;
276 struct mlx5_counters counters; /* Free counter list. */
278 struct mlx5_devx_obj *min_dcs;
279 rte_atomic64_t a64_dcs;
281 /* The devx object of the minimum counter ID. */
282 rte_atomic64_t start_query_gen; /* Query start round. */
283 rte_atomic64_t end_query_gen; /* Query end round. */
284 uint32_t index; /* Pool index in container. */
285 rte_spinlock_t sl; /* The pool lock. */
286 struct mlx5_counter_stats_raw *raw;
287 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */
288 struct mlx5_flow_counter counters_raw[MLX5_COUNTERS_PER_POOL];
289 /* The pool counters memory. */
292 struct mlx5_counter_stats_raw;
294 /* Memory management structure for group of counter statistics raws. */
295 struct mlx5_counter_stats_mem_mng {
296 LIST_ENTRY(mlx5_counter_stats_mem_mng) next;
297 struct mlx5_counter_stats_raw *raws;
298 struct mlx5_devx_obj *dm;
299 struct mlx5dv_devx_umem *umem;
302 /* Raw memory structure for the counter statistics values of a pool. */
303 struct mlx5_counter_stats_raw {
304 LIST_ENTRY(mlx5_counter_stats_raw) next;
306 struct mlx5_counter_stats_mem_mng *mem_mng;
307 volatile struct flow_counter_stats *data;
310 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool);
312 /* Container structure for counter pools. */
313 struct mlx5_pools_container {
314 rte_atomic16_t n_valid; /* Number of valid pools. */
315 uint16_t n; /* Number of pools. */
316 struct mlx5_counter_pools pool_list; /* Counter pool list. */
317 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */
318 struct mlx5_counter_stats_mem_mng *init_mem_mng;
319 /* Hold the memory management for the next allocated pools raws. */
322 /* Counter global management structure. */
323 struct mlx5_flow_counter_mng {
324 uint8_t mhi[2]; /* master \ host container index. */
325 struct mlx5_pools_container ccont[2 * 2];
326 /* 2 containers for single and for batch for double-buffer. */
327 struct mlx5_counters flow_counters; /* Legacy flow counter list. */
328 uint8_t pending_queries;
331 uint8_t query_thread_on;
332 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs;
333 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws;
336 /* Per port data of shared IB device. */
337 struct mlx5_ibv_shared_port {
339 uint32_t devx_ih_port_id;
341 * Interrupt handler port_id. Used by shared interrupt
342 * handler to find the corresponding rte_eth device
343 * by IB port index. If value is equal or greater
344 * RTE_MAX_ETHPORTS it means there is no subhandler
345 * installed for specified IB port index.
349 /* Table key of the hash organization. */
350 union mlx5_flow_tbl_key {
352 /* Table ID should be at the lowest address. */
353 uint32_t table_id; /**< ID of the table. */
354 uint16_t reserved; /**< must be zero for comparison. */
355 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */
356 uint8_t direction; /**< 1 - egress, 0 - ingress. */
358 uint64_t v64; /**< full 64bits value of key */
361 /* Table structure. */
362 struct mlx5_flow_tbl_resource {
363 void *obj; /**< Pointer to DR table object. */
364 rte_atomic32_t refcnt; /**< Reference counter. */
367 #define MLX5_MAX_TABLES UINT16_MAX
368 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3)
369 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2)
370 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1)
371 /* Reserve the last two tables for metadata register copy. */
372 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1)
373 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2)
374 /* Tables for metering splits should be added here. */
375 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3)
376 #define MLX5_MAX_TABLES_FDB UINT16_MAX
378 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */
379 #define MLX5_DBR_SIZE 8
380 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE)
381 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64)
383 struct mlx5_devx_dbr_page {
384 /* Door-bell records, must be first member in structure. */
385 uint8_t dbrs[MLX5_DBR_PAGE_SIZE];
386 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */
387 struct mlx5dv_devx_umem *umem;
388 uint32_t dbr_count; /* Number of door-bell records in use. */
389 /* 1 bit marks matching door-bell is in use. */
390 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE];
393 /* ID generation structure. */
394 struct mlx5_flow_id_pool {
395 uint32_t *free_arr; /**< Pointer to the a array of free values. */
397 /**< The next index that can be used without any free elements. */
398 uint32_t *curr; /**< Pointer to the index to pop. */
399 uint32_t *last; /**< Pointer to the last element in the empty arrray. */
400 uint32_t max_id; /**< Maximum id can be allocated from the pool. */
404 * Shared Infiniband device context for Master/Representors
405 * which belong to same IB device with multiple IB ports.
407 struct mlx5_ibv_shared {
408 LIST_ENTRY(mlx5_ibv_shared) next;
410 uint32_t devx:1; /* Opened with DV. */
411 uint32_t max_port; /* Maximal IB device port index. */
412 struct ibv_context *ctx; /* Verbs/DV context. */
413 struct ibv_pd *pd; /* Protection Domain. */
414 uint32_t pdn; /* Protection Domain number. */
415 uint32_t tdn; /* Transport Domain number. */
416 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */
417 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */
418 struct ibv_device_attr_ex device_attr; /* Device properties. */
419 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb;
420 /**< Called by memory event callback. */
421 struct mlx5_mr_share_cache share_cache;
422 /* Shared DV/DR flow data section. */
423 pthread_mutex_t dv_mutex; /* DV context mutex. */
424 uint32_t dv_meta_mask; /* flow META metadata supported mask. */
425 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */
426 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */
427 uint32_t dv_refcnt; /* DV/DR data reference counter. */
428 void *fdb_domain; /* FDB Direct Rules name space handle. */
429 void *rx_domain; /* RX Direct Rules name space handle. */
430 void *tx_domain; /* TX Direct Rules name space handle. */
431 struct mlx5_hlist *flow_tbls;
432 /* Direct Rules tables for FDB, NIC TX+RX */
433 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */
434 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */
435 uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */
436 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds;
437 struct mlx5_hlist *tag_table;
438 uint32_t port_id_action_list; /* List of port ID actions. */
439 uint32_t push_vlan_action_list; /* List of push VLAN actions. */
440 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */
441 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX];
442 /* Memory Pool for mlx5 flow resources. */
443 /* Shared interrupt handler section. */
444 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */
445 uint32_t intr_cnt; /* Interrupt handler reference counter. */
446 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */
447 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */
448 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */
449 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */
450 struct mlx5_devx_obj *tis; /* TIS object. */
451 struct mlx5_devx_obj *td; /* Transport domain. */
452 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */
453 struct mlx5_ibv_shared_port port[]; /* per device port data array. */
456 /* Per-process private structure. */
457 struct mlx5_proc_priv {
459 /* Size of UAR register table. */
461 /* Table of UAR registers for each process. */
464 /* MTR profile list. */
465 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile);
467 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter);
469 #define MLX5_PROC_PRIV(port_id) \
470 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private)
473 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */
474 struct mlx5_ibv_shared *sh; /* Shared IB device context. */
475 uint32_t ibv_port; /* IB device port number. */
476 struct rte_pci_device *pci_dev; /* Backend PCI device. */
477 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */
478 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES);
479 /* Bit-field of MAC addresses owned by the PMD. */
480 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */
481 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */
482 /* Device properties. */
483 uint16_t mtu; /* Configured MTU. */
484 unsigned int isolated:1; /* Whether isolated mode is enabled. */
485 unsigned int representor:1; /* Device is a port representor. */
486 unsigned int master:1; /* Device is a E-Switch master. */
487 unsigned int dr_shared:1; /* DV/DR data is shared. */
488 unsigned int counter_fallback:1; /* Use counter fallback management. */
489 unsigned int mtr_en:1; /* Whether support meter. */
490 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */
491 uint16_t domain_id; /* Switch domain identifier. */
492 uint16_t vport_id; /* Associated VF vport index (if any). */
493 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */
494 uint32_t vport_meta_mask; /* Used for vport index field match mask. */
495 int32_t representor_id; /* Port representor identifier. */
496 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */
497 unsigned int if_index; /* Associated kernel network device index. */
499 unsigned int rxqs_n; /* RX queues array size. */
500 unsigned int txqs_n; /* TX queues array size. */
501 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */
502 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */
503 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
504 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */
505 unsigned int (*reta_idx)[]; /* RETA index table. */
506 unsigned int reta_idx_n; /* RETA index size. */
507 struct mlx5_drop drop_queue; /* Flow drop queues. */
508 struct mlx5_flows flows; /* RTE Flow rules. */
509 struct mlx5_flows ctrl_flows; /* Control flow rules. */
510 void *inter_flows; /* Intermediate resources for flow creation. */
511 int flow_idx; /* Intermediate device flow index. */
512 int flow_nested_idx; /* Intermediate device flow index, nested. */
513 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */
514 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */
515 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */
516 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */
517 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */
518 /* Indirection tables. */
519 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls;
520 /* Pointer to next element. */
521 rte_atomic32_t refcnt; /**< Reference counter. */
522 struct ibv_flow_action *verbs_action;
523 /**< Verbs modify header action object. */
524 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
525 uint8_t max_lro_msg_size;
526 /* Tags resources cache. */
527 uint32_t link_speed_capa; /* Link speed capabilities. */
528 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */
529 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */
530 struct mlx5_dev_config config; /* Device configuration. */
531 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx;
532 /* Context for Verbs allocator. */
533 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */
534 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */
535 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */
536 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */
537 struct mlx5_flow_id_pool *qrss_id_pool;
538 struct mlx5_hlist *mreg_cp_tbl;
539 /* Hash table of Rx metadata register copy table. */
540 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */
541 uint8_t mtr_color_reg; /* Meter color match REG_C. */
542 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */
543 struct mlx5_flow_meters flow_meters; /* MTR list. */
545 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */
546 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX];
547 /* UAR same-page access control required in 32bit implementations. */
549 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */
550 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */
551 struct mlx5_mp_id mp_id; /* ID of a multi-process process */
554 #define PORT_ID(priv) ((priv)->dev_data->port_id)
555 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)])
559 int mlx5_getenv_int(const char *);
560 int mlx5_proc_priv_init(struct rte_eth_dev *dev);
561 int64_t mlx5_get_dbr(struct rte_eth_dev *dev,
562 struct mlx5_devx_dbr_page **dbr_page);
563 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id,
565 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev,
566 struct rte_eth_udp_tunnel *udp_tunnel);
567 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev);
569 /* Macro to iterate over all valid ports for mlx5 driver. */
570 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \
571 for (port_id = mlx5_eth_find_next(0, pci_dev); \
572 port_id < RTE_MAX_ETHPORTS; \
573 port_id = mlx5_eth_find_next(port_id + 1, pci_dev))
577 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]);
578 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]);
579 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev);
580 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr);
581 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu);
582 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep,
584 int mlx5_dev_configure(struct rte_eth_dev *dev);
585 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info);
586 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock);
587 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size);
588 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev);
589 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete);
590 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status);
591 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu);
592 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev,
593 struct rte_eth_fc_conf *fc_conf);
594 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev,
595 struct rte_eth_fc_conf *fc_conf);
596 void mlx5_dev_link_status_handler(void *arg);
597 void mlx5_dev_interrupt_handler(void *arg);
598 void mlx5_dev_interrupt_handler_devx(void *arg);
599 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev);
600 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev);
601 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev);
602 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev);
603 int mlx5_set_link_down(struct rte_eth_dev *dev);
604 int mlx5_set_link_up(struct rte_eth_dev *dev);
605 int mlx5_is_removed(struct rte_eth_dev *dev);
606 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev);
607 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev);
608 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid);
609 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev);
610 int mlx5_sysfs_switch_info(unsigned int ifindex,
611 struct mlx5_switch_info *info);
612 void mlx5_sysfs_check_switch_info(bool device_dir,
613 struct mlx5_switch_info *switch_info);
614 void mlx5_translate_port_name(const char *port_name_in,
615 struct mlx5_switch_info *port_info_out);
616 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle,
617 rte_intr_callback_fn cb_fn, void *cb_arg);
618 int mlx5_get_module_info(struct rte_eth_dev *dev,
619 struct rte_eth_dev_module_info *modinfo);
620 int mlx5_get_module_eeprom(struct rte_eth_dev *dev,
621 struct rte_dev_eeprom_info *info);
622 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev,
623 struct rte_eth_hairpin_cap *cap);
624 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev);
628 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]);
629 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index);
630 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac,
631 uint32_t index, uint32_t vmdq);
632 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init
633 (struct rte_eth_dev *dev, uint32_t ifindex);
634 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr);
635 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev,
636 struct rte_ether_addr *mc_addr_set,
637 uint32_t nb_mc_addr);
641 int mlx5_rss_hash_update(struct rte_eth_dev *dev,
642 struct rte_eth_rss_conf *rss_conf);
643 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev,
644 struct rte_eth_rss_conf *rss_conf);
645 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size);
646 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev,
647 struct rte_eth_rss_reta_entry64 *reta_conf,
649 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev,
650 struct rte_eth_rss_reta_entry64 *reta_conf,
655 int mlx5_promiscuous_enable(struct rte_eth_dev *dev);
656 int mlx5_promiscuous_disable(struct rte_eth_dev *dev);
657 int mlx5_allmulticast_enable(struct rte_eth_dev *dev);
658 int mlx5_allmulticast_disable(struct rte_eth_dev *dev);
662 void mlx5_stats_init(struct rte_eth_dev *dev);
663 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats);
664 int mlx5_stats_reset(struct rte_eth_dev *dev);
665 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats,
667 int mlx5_xstats_reset(struct rte_eth_dev *dev);
668 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused,
669 struct rte_eth_xstat_name *xstats_names,
674 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
675 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on);
676 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask);
677 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx);
678 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev,
679 struct mlx5_vf_vlan *vf_vlan);
680 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev,
681 struct mlx5_vf_vlan *vf_vlan);
685 int mlx5_dev_start(struct rte_eth_dev *dev);
686 void mlx5_dev_stop(struct rte_eth_dev *dev);
687 int mlx5_traffic_enable(struct rte_eth_dev *dev);
688 void mlx5_traffic_disable(struct rte_eth_dev *dev);
689 int mlx5_traffic_restart(struct rte_eth_dev *dev);
693 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev);
694 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev);
695 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
696 void mlx5_flow_print(struct rte_flow *flow);
697 int mlx5_flow_validate(struct rte_eth_dev *dev,
698 const struct rte_flow_attr *attr,
699 const struct rte_flow_item items[],
700 const struct rte_flow_action actions[],
701 struct rte_flow_error *error);
702 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev,
703 const struct rte_flow_attr *attr,
704 const struct rte_flow_item items[],
705 const struct rte_flow_action actions[],
706 struct rte_flow_error *error);
707 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow,
708 struct rte_flow_error *error);
709 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list,
711 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error);
712 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow,
713 const struct rte_flow_action *action, void *data,
714 struct rte_flow_error *error);
715 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable,
716 struct rte_flow_error *error);
717 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev,
718 enum rte_filter_type filter_type,
719 enum rte_filter_op filter_op,
721 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list);
722 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list);
723 int mlx5_flow_start_default(struct rte_eth_dev *dev);
724 void mlx5_flow_stop_default(struct rte_eth_dev *dev);
725 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev);
726 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev);
727 int mlx5_flow_verify(struct rte_eth_dev *dev);
728 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);
729 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,
730 struct rte_flow_item_eth *eth_spec,
731 struct rte_flow_item_eth *eth_mask,
732 struct rte_flow_item_vlan *vlan_spec,
733 struct rte_flow_item_vlan *vlan_mask);
734 int mlx5_ctrl_flow(struct rte_eth_dev *dev,
735 struct rte_flow_item_eth *eth_spec,
736 struct rte_flow_item_eth *eth_mask);
737 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);
738 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev);
739 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev);
740 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh,
741 uint64_t async_id, int status);
742 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh);
743 void mlx5_flow_query_alarm(void *arg);
744 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev);
745 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt);
746 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt,
747 bool clear, uint64_t *pkts, uint64_t *bytes);
748 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file,
749 struct rte_flow_error *error);
752 int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
753 int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer);
754 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev);
755 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev);
759 int mlx5_pmd_socket_init(void);
761 /* mlx5_flow_meter.c */
763 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg);
764 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv,
766 struct mlx5_flow_meter *mlx5_flow_meter_attach
767 (struct mlx5_priv *priv,
769 const struct rte_flow_attr *attr,
770 struct rte_flow_error *error);
771 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm);
773 #endif /* RTE_PMD_MLX5_H_ */