1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2020 Mellanox Technologies, Ltd
10 #include <sys/queue.h>
12 #include <rte_malloc.h>
13 #include <rte_common.h>
14 #include <rte_eal_paging.h>
16 #include <mlx5_glue.h>
17 #include <mlx5_devx_cmds.h>
18 #include <mlx5_common_devx.h>
19 #include <mlx5_malloc.h>
22 #include "mlx5_common_os.h"
25 #include "mlx5_utils.h"
26 #include "mlx5_devx.h"
27 #include "mlx5_flow.h"
28 #include "mlx5_flow_os.h"
31 * Modify RQ vlan stripping offload
36 * Enable/disable VLAN stripping.
39 * 0 on success, non-0 otherwise
42 mlx5_rxq_obj_modify_rq_vlan_strip(struct mlx5_rxq_priv *rxq, int on)
44 struct mlx5_devx_modify_rq_attr rq_attr;
46 memset(&rq_attr, 0, sizeof(rq_attr));
47 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
48 rq_attr.state = MLX5_RQC_STATE_RDY;
49 rq_attr.vsd = (on ? 0 : 1);
50 rq_attr.modify_bitmask = MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD;
51 return mlx5_devx_cmd_modify_rq(rxq->devx_rq.rq, &rq_attr);
55 * Modify RQ using DevX API.
60 * Type of change queue state.
63 * 0 on success, a negative errno value otherwise and rte_errno is set.
66 mlx5_devx_modify_rq(struct mlx5_rxq_priv *rxq, uint8_t type)
68 struct mlx5_devx_modify_rq_attr rq_attr;
70 memset(&rq_attr, 0, sizeof(rq_attr));
72 case MLX5_RXQ_MOD_ERR2RST:
73 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
74 rq_attr.state = MLX5_RQC_STATE_RST;
76 case MLX5_RXQ_MOD_RST2RDY:
77 rq_attr.rq_state = MLX5_RQC_STATE_RST;
78 rq_attr.state = MLX5_RQC_STATE_RDY;
80 case MLX5_RXQ_MOD_RDY2ERR:
81 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
82 rq_attr.state = MLX5_RQC_STATE_ERR;
84 case MLX5_RXQ_MOD_RDY2RST:
85 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
86 rq_attr.state = MLX5_RQC_STATE_RST;
91 if (rxq->ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
92 return mlx5_devx_cmd_modify_rq(rxq->ctrl->obj->rq, &rq_attr);
93 return mlx5_devx_cmd_modify_rq(rxq->devx_rq.rq, &rq_attr);
97 * Modify SQ using DevX API.
100 * DevX Tx queue object.
102 * Type of change queue state.
107 * 0 on success, a negative errno value otherwise and rte_errno is set.
110 mlx5_txq_devx_modify(struct mlx5_txq_obj *obj, enum mlx5_txq_modify_type type,
113 struct mlx5_devx_modify_sq_attr msq_attr = { 0 };
116 if (type != MLX5_TXQ_MOD_RST2RDY) {
117 /* Change queue state to reset. */
118 if (type == MLX5_TXQ_MOD_ERR2RDY)
119 msq_attr.sq_state = MLX5_SQC_STATE_ERR;
121 msq_attr.sq_state = MLX5_SQC_STATE_RDY;
122 msq_attr.state = MLX5_SQC_STATE_RST;
123 ret = mlx5_devx_cmd_modify_sq(obj->sq_obj.sq, &msq_attr);
125 DRV_LOG(ERR, "Cannot change the Tx SQ state to RESET"
126 " %s", strerror(errno));
131 if (type != MLX5_TXQ_MOD_RDY2RST) {
132 /* Change queue state to ready. */
133 msq_attr.sq_state = MLX5_SQC_STATE_RST;
134 msq_attr.state = MLX5_SQC_STATE_RDY;
135 ret = mlx5_devx_cmd_modify_sq(obj->sq_obj.sq, &msq_attr);
137 DRV_LOG(ERR, "Cannot change the Tx SQ state to READY"
138 " %s", strerror(errno));
144 * The dev_port variable is relevant only in Verbs API, and there is a
145 * pointer that points to this function and a parallel function in verbs
146 * intermittently, so they should have the same parameters.
153 * Release an Rx DevX queue object.
159 mlx5_rxq_devx_obj_release(struct mlx5_rxq_priv *rxq)
161 struct mlx5_rxq_obj *rxq_obj = rxq->ctrl->obj;
165 if (rxq_obj->rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN) {
166 if (rxq_obj->rq == NULL)
168 mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RDY2RST);
169 claim_zero(mlx5_devx_cmd_destroy(rxq_obj->rq));
171 if (rxq->devx_rq.rq == NULL)
173 mlx5_devx_rq_destroy(&rxq->devx_rq);
174 if (rxq->devx_rq.rmp != NULL && rxq->devx_rq.rmp->ref_cnt > 0)
176 mlx5_devx_cq_destroy(&rxq_obj->cq_obj);
177 memset(&rxq_obj->cq_obj, 0, sizeof(rxq_obj->cq_obj));
178 if (rxq_obj->devx_channel) {
179 mlx5_os_devx_destroy_event_channel
180 (rxq_obj->devx_channel);
181 rxq_obj->devx_channel = NULL;
184 rxq->ctrl->started = false;
188 * Get event for an Rx DevX queue object.
191 * DevX Rx queue object.
194 * 0 on success, a negative errno value otherwise and rte_errno is set.
197 mlx5_rx_devx_get_event(struct mlx5_rxq_obj *rxq_obj)
199 #ifdef HAVE_IBV_DEVX_EVENT
201 struct mlx5dv_devx_async_event_hdr event_resp;
202 uint8_t buf[sizeof(struct mlx5dv_devx_async_event_hdr) + 128];
204 int ret = mlx5_glue->devx_get_event(rxq_obj->devx_channel,
212 if (out.event_resp.cookie != (uint64_t)(uintptr_t)rxq_obj->cq_obj.cq) {
221 #endif /* HAVE_IBV_DEVX_EVENT */
225 * Create a RQ object using DevX.
228 * Pointer to Rx queue.
231 * 0 on success, a negative errno value otherwise and rte_errno is set.
234 mlx5_rxq_create_devx_rq_resources(struct mlx5_rxq_priv *rxq)
236 struct mlx5_priv *priv = rxq->priv;
237 struct mlx5_common_device *cdev = priv->sh->cdev;
238 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
239 struct mlx5_rxq_data *rxq_data = &rxq->ctrl->rxq;
240 struct mlx5_devx_create_rq_attr rq_attr = { 0 };
241 uint16_t log_desc_n = rxq_data->elts_n - rxq_data->sges_n;
242 uint32_t wqe_size, log_wqe_size;
244 /* Fill RQ attributes. */
245 rq_attr.mem_rq_type = MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE;
246 rq_attr.flush_in_error_en = 1;
247 rq_attr.vsd = (rxq_data->vlan_strip) ? 0 : 1;
248 rq_attr.cqn = rxq_ctrl->obj->cq_obj.cq->id;
249 rq_attr.scatter_fcs = (rxq_data->crc_present) ? 1 : 0;
251 mlx5_ts_format_conv(cdev->config.hca_attr.rq_ts_format);
252 /* Fill WQ attributes for this RQ. */
253 if (mlx5_rxq_mprq_enabled(rxq_data)) {
254 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ;
256 * Number of strides in each WQE:
257 * 512*2^single_wqe_log_num_of_strides.
259 rq_attr.wq_attr.single_wqe_log_num_of_strides =
260 rxq_data->strd_num_n -
261 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
262 /* Stride size = (2^single_stride_log_num_of_bytes)*64B. */
263 rq_attr.wq_attr.single_stride_log_num_of_bytes =
264 rxq_data->strd_sz_n -
265 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
266 wqe_size = sizeof(struct mlx5_wqe_mprq);
268 rq_attr.wq_attr.wq_type = MLX5_WQ_TYPE_CYCLIC;
269 wqe_size = sizeof(struct mlx5_wqe_data_seg);
271 log_wqe_size = log2above(wqe_size) + rxq_data->sges_n;
272 wqe_size = 1 << log_wqe_size; /* round up power of two.*/
273 rq_attr.wq_attr.log_wq_stride = log_wqe_size;
274 rq_attr.wq_attr.log_wq_sz = log_desc_n;
275 rq_attr.wq_attr.end_padding_mode = priv->config.hw_padding ?
276 MLX5_WQ_END_PAD_MODE_ALIGN :
277 MLX5_WQ_END_PAD_MODE_NONE;
278 rq_attr.wq_attr.pd = cdev->pdn;
279 rq_attr.counter_set_id = priv->counter_set_id;
280 if (rxq_data->shared) /* Create RMP based RQ. */
281 rxq->devx_rq.rmp = &rxq_ctrl->obj->devx_rmp;
282 /* Create RQ using DevX API. */
283 return mlx5_devx_rq_create(cdev->ctx, &rxq->devx_rq, wqe_size,
284 log_desc_n, &rq_attr, rxq_ctrl->socket);
288 * Create a DevX CQ object for an Rx queue.
291 * Pointer to Rx queue.
294 * 0 on success, a negative errno value otherwise and rte_errno is set.
297 mlx5_rxq_create_devx_cq_resources(struct mlx5_rxq_priv *rxq)
299 struct mlx5_devx_cq *cq_obj = 0;
300 struct mlx5_devx_cq_attr cq_attr = { 0 };
301 struct mlx5_priv *priv = rxq->priv;
302 struct mlx5_dev_ctx_shared *sh = priv->sh;
303 uint16_t port_id = priv->dev_data->port_id;
304 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
305 struct mlx5_rxq_data *rxq_data = &rxq_ctrl->rxq;
306 unsigned int cqe_n = mlx5_rxq_cqe_num(rxq_data);
308 uint16_t event_nums[1] = { 0 };
311 if (rxq_ctrl->started)
313 if (priv->config.cqe_comp && !rxq_data->hw_timestamp &&
315 cq_attr.cqe_comp_en = 1u;
316 rxq_data->mcqe_format = priv->config.cqe_comp_fmt;
317 rxq_data->byte_mask = UINT32_MAX;
318 switch (priv->config.cqe_comp_fmt) {
319 case MLX5_CQE_RESP_FORMAT_HASH:
321 case MLX5_CQE_RESP_FORMAT_CSUM:
323 * Select CSUM miniCQE format only for non-vectorized
324 * MPRQ Rx burst, use HASH miniCQE format for others.
326 if (mlx5_rxq_check_vec_support(rxq_data) < 0 &&
327 mlx5_rxq_mprq_enabled(rxq_data))
328 cq_attr.mini_cqe_res_format =
329 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX;
331 cq_attr.mini_cqe_res_format =
332 MLX5_CQE_RESP_FORMAT_HASH;
333 rxq_data->mcqe_format = cq_attr.mini_cqe_res_format;
335 case MLX5_CQE_RESP_FORMAT_FTAG_STRIDX:
336 rxq_data->byte_mask = MLX5_LEN_WITH_MARK_MASK;
338 case MLX5_CQE_RESP_FORMAT_CSUM_STRIDX:
339 cq_attr.mini_cqe_res_format = priv->config.cqe_comp_fmt;
341 case MLX5_CQE_RESP_FORMAT_L34H_STRIDX:
342 cq_attr.mini_cqe_res_format = 0;
343 cq_attr.mini_cqe_res_format_ext = 1;
347 "Port %u Rx CQE compression is enabled, format %d.",
348 port_id, priv->config.cqe_comp_fmt);
350 * For vectorized Rx, it must not be doubled in order to
351 * make cq_ci and rq_ci aligned.
353 if (mlx5_rxq_check_vec_support(rxq_data) < 0)
355 } else if (priv->config.cqe_comp && rxq_data->hw_timestamp) {
357 "Port %u Rx CQE compression is disabled for HW timestamp.",
359 } else if (priv->config.cqe_comp && rxq_data->lro) {
361 "Port %u Rx CQE compression is disabled for LRO.",
364 cq_attr.uar_page_id = mlx5_os_get_devx_uar_page_id(sh->devx_rx_uar);
365 log_cqe_n = log2above(cqe_n);
366 /* Create CQ using DevX API. */
367 ret = mlx5_devx_cq_create(sh->cdev->ctx, &rxq_ctrl->obj->cq_obj,
368 log_cqe_n, &cq_attr, sh->numa_node);
371 cq_obj = &rxq_ctrl->obj->cq_obj;
372 rxq_data->cqes = (volatile struct mlx5_cqe (*)[])
373 (uintptr_t)cq_obj->cqes;
374 rxq_data->cq_db = cq_obj->db_rec;
375 rxq_data->cq_uar = mlx5_os_get_devx_uar_base_addr(sh->devx_rx_uar);
376 rxq_data->cqe_n = log_cqe_n;
377 rxq_data->cqn = cq_obj->cq->id;
379 if (rxq_ctrl->obj->devx_channel) {
380 ret = mlx5_os_devx_subscribe_devx_event
381 (rxq_ctrl->obj->devx_channel,
385 (uint64_t)(uintptr_t)cq_obj->cq);
387 DRV_LOG(ERR, "Fail to subscribe CQ to event channel.");
389 mlx5_devx_cq_destroy(cq_obj);
390 memset(cq_obj, 0, sizeof(*cq_obj));
399 * Create the Rx hairpin queue object.
402 * Pointer to Rx queue.
405 * 0 on success, a negative errno value otherwise and rte_errno is set.
408 mlx5_rxq_obj_hairpin_new(struct mlx5_rxq_priv *rxq)
410 uint16_t idx = rxq->idx;
411 struct mlx5_priv *priv = rxq->priv;
412 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
413 struct mlx5_devx_create_rq_attr attr = { 0 };
414 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
415 uint32_t max_wq_data;
417 MLX5_ASSERT(rxq != NULL && rxq->ctrl != NULL && tmpl != NULL);
418 tmpl->rxq_ctrl = rxq_ctrl;
420 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
421 /* Jumbo frames > 9KB should be supported, and more packets. */
422 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
423 if (priv->config.log_hp_size > max_wq_data) {
424 DRV_LOG(ERR, "Total data size %u power of 2 is "
425 "too large for hairpin.",
426 priv->config.log_hp_size);
430 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
432 attr.wq_attr.log_hairpin_data_sz =
433 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
434 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
436 /* Set the packets number to the maximum value for performance. */
437 attr.wq_attr.log_hairpin_num_packets =
438 attr.wq_attr.log_hairpin_data_sz -
439 MLX5_HAIRPIN_QUEUE_STRIDE;
440 attr.counter_set_id = priv->counter_set_id;
441 tmpl->rq = mlx5_devx_cmd_create_rq(priv->sh->cdev->ctx, &attr,
445 "Port %u Rx hairpin queue %u can't create rq object.",
446 priv->dev_data->port_id, idx);
450 priv->dev_data->rx_queue_state[idx] = RTE_ETH_QUEUE_STATE_HAIRPIN;
455 * Create the Rx queue DevX object.
458 * Pointer to Rx queue.
461 * 0 on success, a negative errno value otherwise and rte_errno is set.
464 mlx5_rxq_devx_obj_new(struct mlx5_rxq_priv *rxq)
466 struct mlx5_priv *priv = rxq->priv;
467 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
468 struct mlx5_rxq_data *rxq_data = &rxq_ctrl->rxq;
469 struct mlx5_rxq_obj *tmpl = rxq_ctrl->obj;
472 MLX5_ASSERT(rxq_data);
474 if (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
475 return mlx5_rxq_obj_hairpin_new(rxq);
476 tmpl->rxq_ctrl = rxq_ctrl;
477 if (rxq_ctrl->irq && !rxq_ctrl->started) {
479 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA;
481 tmpl->devx_channel = mlx5_os_devx_create_event_channel
482 (priv->sh->cdev->ctx,
484 if (!tmpl->devx_channel) {
486 DRV_LOG(ERR, "Failed to create event channel %d.",
490 tmpl->fd = mlx5_os_get_devx_channel_fd(tmpl->devx_channel);
492 /* Create CQ using DevX API. */
493 ret = mlx5_rxq_create_devx_cq_resources(rxq);
495 DRV_LOG(ERR, "Failed to create CQ.");
498 /* Create RQ using DevX API. */
499 ret = mlx5_rxq_create_devx_rq_resources(rxq);
501 DRV_LOG(ERR, "Port %u Rx queue %u RQ creation failure.",
502 priv->dev_data->port_id, rxq->idx);
506 /* Change queue state to ready. */
507 ret = mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RST2RDY);
510 if (!rxq_data->shared) {
511 rxq_data->wqes = (void *)(uintptr_t)rxq->devx_rq.wq.umem_buf;
512 rxq_data->rq_db = (uint32_t *)(uintptr_t)rxq->devx_rq.wq.db_rec;
513 } else if (!rxq_ctrl->started) {
514 rxq_data->wqes = (void *)(uintptr_t)tmpl->devx_rmp.wq.umem_buf;
516 (uint32_t *)(uintptr_t)tmpl->devx_rmp.wq.db_rec;
518 if (!rxq_ctrl->started) {
519 mlx5_rxq_initialize(rxq_data);
520 rxq_ctrl->wqn = rxq->devx_rq.rq->id;
522 priv->dev_data->rx_queue_state[rxq->idx] = RTE_ETH_QUEUE_STATE_STARTED;
525 ret = rte_errno; /* Save rte_errno before cleanup. */
526 mlx5_rxq_devx_obj_release(rxq);
527 rte_errno = ret; /* Restore rte_errno. */
532 * Prepare RQT attribute structure for DevX RQT API.
535 * Pointer to Ethernet device.
537 * Log of number of queues in the array.
539 * List of RX queue indices or NULL, in which case
540 * the attribute will be filled by drop queue ID.
542 * Size of @p queues array or 0 if it is NULL.
544 * DevX indirection table object.
547 * The RQT attr object initialized, NULL otherwise and rte_errno is set.
549 static struct mlx5_devx_rqt_attr *
550 mlx5_devx_ind_table_create_rqt_attr(struct rte_eth_dev *dev,
551 const unsigned int log_n,
552 const uint16_t *queues,
553 const uint32_t queues_n)
555 struct mlx5_priv *priv = dev->data->dev_private;
556 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
557 const unsigned int rqt_n = 1 << log_n;
560 rqt_attr = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt_attr) +
561 rqt_n * sizeof(uint32_t), 0, SOCKET_ID_ANY);
563 DRV_LOG(ERR, "Port %u cannot allocate RQT resources.",
568 rqt_attr->rqt_max_size = priv->config.ind_table_max_size;
569 rqt_attr->rqt_actual_size = rqt_n;
570 if (queues == NULL) {
571 for (i = 0; i < rqt_n; i++)
572 rqt_attr->rq_list[i] =
573 priv->drop_queue.rxq->devx_rq.rq->id;
576 for (i = 0; i != queues_n; ++i) {
577 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, queues[i]);
579 MLX5_ASSERT(rxq != NULL);
580 if (rxq->ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)
581 rqt_attr->rq_list[i] = rxq->ctrl->obj->rq->id;
583 rqt_attr->rq_list[i] = rxq->devx_rq.rq->id;
586 for (j = 0; i != rqt_n; ++j, ++i)
587 rqt_attr->rq_list[i] = rqt_attr->rq_list[j];
592 * Create RQT using DevX API as a filed of indirection table.
595 * Pointer to Ethernet device.
597 * Log of number of queues in the array.
599 * DevX indirection table object.
602 * 0 on success, a negative errno value otherwise and rte_errno is set.
605 mlx5_devx_ind_table_new(struct rte_eth_dev *dev, const unsigned int log_n,
606 struct mlx5_ind_table_obj *ind_tbl)
608 struct mlx5_priv *priv = dev->data->dev_private;
609 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
610 const uint16_t *queues = dev->data->dev_started ? ind_tbl->queues :
613 MLX5_ASSERT(ind_tbl);
614 rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n, queues,
618 ind_tbl->rqt = mlx5_devx_cmd_create_rqt(priv->sh->cdev->ctx, rqt_attr);
621 DRV_LOG(ERR, "Port %u cannot create DevX RQT.",
630 * Modify RQT using DevX API as a filed of indirection table.
633 * Pointer to Ethernet device.
635 * Log of number of queues in the array.
637 * DevX indirection table object.
640 * 0 on success, a negative errno value otherwise and rte_errno is set.
643 mlx5_devx_ind_table_modify(struct rte_eth_dev *dev, const unsigned int log_n,
644 const uint16_t *queues, const uint32_t queues_n,
645 struct mlx5_ind_table_obj *ind_tbl)
648 struct mlx5_devx_rqt_attr *rqt_attr = NULL;
650 MLX5_ASSERT(ind_tbl);
651 rqt_attr = mlx5_devx_ind_table_create_rqt_attr(dev, log_n,
656 ret = mlx5_devx_cmd_modify_rqt(ind_tbl->rqt, rqt_attr);
659 DRV_LOG(ERR, "Port %u cannot modify DevX RQT.",
665 * Destroy the DevX RQT object.
668 * Indirection table to release.
671 mlx5_devx_ind_table_destroy(struct mlx5_ind_table_obj *ind_tbl)
673 claim_zero(mlx5_devx_cmd_destroy(ind_tbl->rqt));
677 * Set TIR attribute struct with relevant input values.
680 * Pointer to Ethernet device.
682 * RSS key for the Rx hash queue.
683 * @param[in] hash_fields
684 * Verbs protocol hash field to make the RSS on.
686 * Indirection table for TIR. If table queues array is NULL,
687 * a TIR for drop queue is assumed.
690 * @param[out] tir_attr
691 * Parameters structure for TIR creation/modification.
694 * The Verbs/DevX object initialised index, 0 otherwise and rte_errno is set.
697 mlx5_devx_tir_attr_set(struct rte_eth_dev *dev, const uint8_t *rss_key,
698 uint64_t hash_fields,
699 const struct mlx5_ind_table_obj *ind_tbl,
700 int tunnel, struct mlx5_devx_tir_attr *tir_attr)
702 struct mlx5_priv *priv = dev->data->dev_private;
703 enum mlx5_rxq_type rxq_obj_type;
707 /* NULL queues designate drop queue. */
708 if (ind_tbl->queues != NULL) {
709 struct mlx5_rxq_ctrl *rxq_ctrl =
710 mlx5_rxq_ctrl_get(dev, ind_tbl->queues[0]);
711 rxq_obj_type = rxq_ctrl != NULL ? rxq_ctrl->type :
712 MLX5_RXQ_TYPE_STANDARD;
714 /* Enable TIR LRO only if all the queues were configured for. */
715 for (i = 0; i < ind_tbl->queues_n; ++i) {
716 struct mlx5_rxq_data *rxq_i =
717 mlx5_rxq_data_get(dev, ind_tbl->queues[i]);
719 if (rxq_i != NULL && !rxq_i->lro) {
725 rxq_obj_type = priv->drop_queue.rxq->ctrl->type;
727 memset(tir_attr, 0, sizeof(*tir_attr));
728 tir_attr->disp_type = MLX5_TIRC_DISP_TYPE_INDIRECT;
729 tir_attr->rx_hash_fn = MLX5_RX_HASH_FN_TOEPLITZ;
730 tir_attr->tunneled_offload_en = !!tunnel;
731 /* If needed, translate hash_fields bitmap to PRM format. */
733 struct mlx5_rx_hash_field_select *rx_hash_field_select =
734 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
735 hash_fields & IBV_RX_HASH_INNER ?
736 &tir_attr->rx_hash_field_selector_inner :
738 &tir_attr->rx_hash_field_selector_outer;
739 /* 1 bit: 0: IPv4, 1: IPv6. */
740 rx_hash_field_select->l3_prot_type =
741 !!(hash_fields & MLX5_IPV6_IBV_RX_HASH);
742 /* 1 bit: 0: TCP, 1: UDP. */
743 rx_hash_field_select->l4_prot_type =
744 !!(hash_fields & MLX5_UDP_IBV_RX_HASH);
745 /* Bitmask which sets which fields to use in RX Hash. */
746 rx_hash_field_select->selected_fields =
747 ((!!(hash_fields & MLX5_L3_SRC_IBV_RX_HASH)) <<
748 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP) |
749 (!!(hash_fields & MLX5_L3_DST_IBV_RX_HASH)) <<
750 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP |
751 (!!(hash_fields & MLX5_L4_SRC_IBV_RX_HASH)) <<
752 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT |
753 (!!(hash_fields & MLX5_L4_DST_IBV_RX_HASH)) <<
754 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT;
756 if (rxq_obj_type == MLX5_RXQ_TYPE_HAIRPIN)
757 tir_attr->transport_domain = priv->sh->td->id;
759 tir_attr->transport_domain = priv->sh->tdn;
760 memcpy(tir_attr->rx_hash_toeplitz_key, rss_key, MLX5_RSS_HASH_KEY_LEN);
761 tir_attr->indirect_table = ind_tbl->rqt->id;
762 if (dev->data->dev_conf.lpbk_mode)
763 tir_attr->self_lb_block =
764 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
766 tir_attr->lro_timeout_period_usecs = priv->config.lro.timeout;
767 tir_attr->lro_max_msg_sz = priv->max_lro_msg_size;
768 tir_attr->lro_enable_mask =
769 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
770 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO;
775 * Create an Rx Hash queue.
778 * Pointer to Ethernet device.
780 * Pointer to Rx Hash queue.
785 * 0 on success, a negative errno value otherwise and rte_errno is set.
788 mlx5_devx_hrxq_new(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
789 int tunnel __rte_unused)
791 struct mlx5_priv *priv = dev->data->dev_private;
792 struct mlx5_devx_tir_attr tir_attr = {0};
795 mlx5_devx_tir_attr_set(dev, hrxq->rss_key, hrxq->hash_fields,
796 hrxq->ind_table, tunnel, &tir_attr);
797 hrxq->tir = mlx5_devx_cmd_create_tir(priv->sh->cdev->ctx, &tir_attr);
799 DRV_LOG(ERR, "Port %u cannot create DevX TIR.",
804 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
805 if (mlx5_flow_os_create_flow_action_dest_devx_tir(hrxq->tir,
813 err = rte_errno; /* Save rte_errno before cleanup. */
815 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
816 rte_errno = err; /* Restore rte_errno. */
821 * Destroy a DevX TIR object.
824 * Hash Rx queue to release its tir.
827 mlx5_devx_tir_destroy(struct mlx5_hrxq *hrxq)
829 claim_zero(mlx5_devx_cmd_destroy(hrxq->tir));
833 * Modify an Rx Hash queue configuration.
836 * Pointer to Ethernet device.
838 * Hash Rx queue to modify.
840 * RSS key for the Rx hash queue.
842 * Verbs protocol hash field to make the RSS on.
844 * Indirection table for TIR.
847 * 0 on success, a negative errno value otherwise and rte_errno is set.
850 mlx5_devx_hrxq_modify(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq,
851 const uint8_t *rss_key,
852 uint64_t hash_fields,
853 const struct mlx5_ind_table_obj *ind_tbl)
855 struct mlx5_devx_modify_tir_attr modify_tir = {0};
858 * untested for modification fields:
859 * - rx_hash_symmetric not set in hrxq_new(),
860 * - rx_hash_fn set hard-coded in hrxq_new(),
861 * - lro_xxx not set after rxq setup
863 if (ind_tbl != hrxq->ind_table)
864 modify_tir.modify_bitmask |=
865 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE;
866 if (hash_fields != hrxq->hash_fields ||
867 memcmp(hrxq->rss_key, rss_key, MLX5_RSS_HASH_KEY_LEN))
868 modify_tir.modify_bitmask |=
869 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH;
870 mlx5_devx_tir_attr_set(dev, rss_key, hash_fields, ind_tbl,
871 0, /* N/A - tunnel modification unsupported */
873 modify_tir.tirn = hrxq->tir->id;
874 if (mlx5_devx_cmd_modify_tir(hrxq->tir, &modify_tir)) {
875 DRV_LOG(ERR, "port %u cannot modify DevX TIR",
884 * Create a DevX drop Rx queue.
887 * Pointer to Ethernet device.
890 * 0 on success, a negative errno value otherwise and rte_errno is set.
893 mlx5_rxq_devx_obj_drop_create(struct rte_eth_dev *dev)
895 struct mlx5_priv *priv = dev->data->dev_private;
896 int socket_id = dev->device->numa_node;
897 struct mlx5_rxq_priv *rxq;
898 struct mlx5_rxq_ctrl *rxq_ctrl = NULL;
899 struct mlx5_rxq_obj *rxq_obj = NULL;
903 * Initialize dummy control structures.
904 * They are required to hold pointers for cleanup
905 * and are only accessible via drop queue DevX objects.
907 rxq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq), 0, socket_id);
909 DRV_LOG(ERR, "Port %u could not allocate drop queue private",
914 rxq_ctrl = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq_ctrl),
916 if (rxq_ctrl == NULL) {
917 DRV_LOG(ERR, "Port %u could not allocate drop queue control",
922 rxq_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rxq_obj), 0, socket_id);
923 if (rxq_obj == NULL) {
924 DRV_LOG(ERR, "Port %u could not allocate drop queue object",
929 rxq_obj->rxq_ctrl = rxq_ctrl;
930 rxq_ctrl->type = MLX5_RXQ_TYPE_STANDARD;
931 rxq_ctrl->sh = priv->sh;
932 rxq_ctrl->obj = rxq_obj;
933 rxq->ctrl = rxq_ctrl;
935 LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry);
936 /* Create CQ using DevX API. */
937 ret = mlx5_rxq_create_devx_cq_resources(rxq);
939 DRV_LOG(ERR, "Port %u drop queue CQ creation failed.",
943 /* Create RQ using DevX API. */
944 ret = mlx5_rxq_create_devx_rq_resources(rxq);
946 DRV_LOG(ERR, "Port %u drop queue RQ creation failed.",
951 /* Change queue state to ready. */
952 ret = mlx5_devx_modify_rq(rxq, MLX5_RXQ_MOD_RST2RDY);
955 /* Initialize drop queue. */
956 priv->drop_queue.rxq = rxq;
959 ret = rte_errno; /* Save rte_errno before cleanup. */
960 if (rxq != NULL && rxq->devx_rq.rq != NULL)
961 mlx5_devx_rq_destroy(&rxq->devx_rq);
962 if (rxq_obj != NULL) {
963 if (rxq_obj->cq_obj.cq != NULL)
964 mlx5_devx_cq_destroy(&rxq_obj->cq_obj);
965 if (rxq_obj->devx_channel)
966 mlx5_os_devx_destroy_event_channel
967 (rxq_obj->devx_channel);
970 if (rxq_ctrl != NULL)
974 rte_errno = ret; /* Restore rte_errno. */
979 * Release drop Rx queue resources.
982 * Pointer to Ethernet device.
985 mlx5_rxq_devx_obj_drop_release(struct rte_eth_dev *dev)
987 struct mlx5_priv *priv = dev->data->dev_private;
988 struct mlx5_rxq_priv *rxq = priv->drop_queue.rxq;
989 struct mlx5_rxq_ctrl *rxq_ctrl = rxq->ctrl;
991 mlx5_rxq_devx_obj_release(rxq);
992 mlx5_free(rxq_ctrl->obj);
995 priv->drop_queue.rxq = NULL;
999 * Release a drop hash Rx queue.
1002 * Pointer to Ethernet device.
1005 mlx5_devx_drop_action_destroy(struct rte_eth_dev *dev)
1007 struct mlx5_priv *priv = dev->data->dev_private;
1008 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
1010 if (hrxq->tir != NULL)
1011 mlx5_devx_tir_destroy(hrxq);
1012 if (hrxq->ind_table->ind_table != NULL)
1013 mlx5_devx_ind_table_destroy(hrxq->ind_table);
1014 if (priv->drop_queue.rxq->devx_rq.rq != NULL)
1015 mlx5_rxq_devx_obj_drop_release(dev);
1019 * Create a DevX drop action for Rx Hash queue.
1022 * Pointer to Ethernet device.
1025 * 0 on success, a negative errno value otherwise and rte_errno is set.
1028 mlx5_devx_drop_action_create(struct rte_eth_dev *dev)
1030 struct mlx5_priv *priv = dev->data->dev_private;
1031 struct mlx5_hrxq *hrxq = priv->drop_queue.hrxq;
1034 ret = mlx5_rxq_devx_obj_drop_create(dev);
1036 DRV_LOG(ERR, "Cannot create drop RX queue");
1039 /* hrxq->ind_table queues are NULL, drop RX queue ID will be used */
1040 ret = mlx5_devx_ind_table_new(dev, 0, hrxq->ind_table);
1042 DRV_LOG(ERR, "Cannot create drop hash RX queue indirection table");
1045 ret = mlx5_devx_hrxq_new(dev, hrxq, /* tunnel */ false);
1047 DRV_LOG(ERR, "Cannot create drop hash RX queue");
1052 mlx5_devx_drop_action_destroy(dev);
1057 * Select TXQ TIS number.
1060 * Pointer to Ethernet device.
1062 * Queue index in DPDK Tx queue array.
1065 * > 0 on success, a negative errno value otherwise.
1068 mlx5_get_txq_tis_num(struct rte_eth_dev *dev, uint16_t queue_idx)
1070 struct mlx5_priv *priv = dev->data->dev_private;
1073 if (priv->sh->bond.n_port && priv->sh->lag.affinity_mode ==
1074 MLX5_LAG_MODE_TIS) {
1075 tis_idx = (priv->lag_affinity_idx + queue_idx) %
1076 priv->sh->bond.n_port;
1077 DRV_LOG(INFO, "port %d txq %d gets affinity %d and maps to PF %d.",
1078 dev->data->port_id, queue_idx, tis_idx + 1,
1079 priv->sh->lag.tx_remap_affinity[tis_idx]);
1083 MLX5_ASSERT(priv->sh->tis[tis_idx]);
1084 return priv->sh->tis[tis_idx]->id;
1088 * Create the Tx hairpin queue object.
1091 * Pointer to Ethernet device.
1093 * Queue index in DPDK Tx queue array.
1096 * 0 on success, a negative errno value otherwise and rte_errno is set.
1099 mlx5_txq_obj_hairpin_new(struct rte_eth_dev *dev, uint16_t idx)
1101 struct mlx5_priv *priv = dev->data->dev_private;
1102 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1103 struct mlx5_txq_ctrl *txq_ctrl =
1104 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1105 struct mlx5_devx_create_sq_attr attr = { 0 };
1106 struct mlx5_txq_obj *tmpl = txq_ctrl->obj;
1107 uint32_t max_wq_data;
1109 MLX5_ASSERT(txq_data);
1111 tmpl->txq_ctrl = txq_ctrl;
1113 attr.tis_lst_sz = 1;
1114 max_wq_data = priv->config.hca_attr.log_max_hairpin_wq_data_sz;
1115 /* Jumbo frames > 9KB should be supported, and more packets. */
1116 if (priv->config.log_hp_size != (uint32_t)MLX5_ARG_UNSET) {
1117 if (priv->config.log_hp_size > max_wq_data) {
1118 DRV_LOG(ERR, "Total data size %u power of 2 is "
1119 "too large for hairpin.",
1120 priv->config.log_hp_size);
1124 attr.wq_attr.log_hairpin_data_sz = priv->config.log_hp_size;
1126 attr.wq_attr.log_hairpin_data_sz =
1127 (max_wq_data < MLX5_HAIRPIN_JUMBO_LOG_SIZE) ?
1128 max_wq_data : MLX5_HAIRPIN_JUMBO_LOG_SIZE;
1130 /* Set the packets number to the maximum value for performance. */
1131 attr.wq_attr.log_hairpin_num_packets =
1132 attr.wq_attr.log_hairpin_data_sz -
1133 MLX5_HAIRPIN_QUEUE_STRIDE;
1135 attr.tis_num = mlx5_get_txq_tis_num(dev, idx);
1136 tmpl->sq = mlx5_devx_cmd_create_sq(priv->sh->cdev->ctx, &attr);
1139 "Port %u tx hairpin queue %u can't create SQ object.",
1140 dev->data->port_id, idx);
1147 #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)
1149 * Destroy the Tx queue DevX object.
1152 * Txq object to destroy.
1155 mlx5_txq_release_devx_resources(struct mlx5_txq_obj *txq_obj)
1157 mlx5_devx_sq_destroy(&txq_obj->sq_obj);
1158 memset(&txq_obj->sq_obj, 0, sizeof(txq_obj->sq_obj));
1159 mlx5_devx_cq_destroy(&txq_obj->cq_obj);
1160 memset(&txq_obj->cq_obj, 0, sizeof(txq_obj->cq_obj));
1164 * Create a SQ object and its resources using DevX.
1167 * Pointer to Ethernet device.
1169 * Queue index in DPDK Tx queue array.
1170 * @param[in] log_desc_n
1171 * Log of number of descriptors in queue.
1174 * 0 on success, a negative errno value otherwise and rte_errno is set.
1177 mlx5_txq_create_devx_sq_resources(struct rte_eth_dev *dev, uint16_t idx,
1178 uint16_t log_desc_n)
1180 struct mlx5_priv *priv = dev->data->dev_private;
1181 struct mlx5_common_device *cdev = priv->sh->cdev;
1182 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1183 struct mlx5_txq_ctrl *txq_ctrl =
1184 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1185 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1186 struct mlx5_devx_create_sq_attr sq_attr = {
1187 .flush_in_error_en = 1,
1188 .allow_multi_pkt_send_wqe = !!priv->config.mps,
1189 .min_wqe_inline_mode = priv->config.hca_attr.vport_inline_mode,
1190 .allow_swp = !!priv->config.swp,
1191 .cqn = txq_obj->cq_obj.cq->id,
1193 .wq_attr = (struct mlx5_devx_wq_attr){
1196 mlx5_os_get_devx_uar_page_id(priv->sh->tx_uar),
1199 mlx5_ts_format_conv(cdev->config.hca_attr.sq_ts_format),
1200 .tis_num = mlx5_get_txq_tis_num(dev, idx),
1203 /* Create Send Queue object with DevX. */
1204 return mlx5_devx_sq_create(cdev->ctx, &txq_obj->sq_obj,
1205 log_desc_n, &sq_attr, priv->sh->numa_node);
1210 * Create the Tx queue DevX object.
1213 * Pointer to Ethernet device.
1215 * Queue index in DPDK Tx queue array.
1218 * 0 on success, a negative errno value otherwise and rte_errno is set.
1221 mlx5_txq_devx_obj_new(struct rte_eth_dev *dev, uint16_t idx)
1223 struct mlx5_priv *priv = dev->data->dev_private;
1224 struct mlx5_txq_data *txq_data = (*priv->txqs)[idx];
1225 struct mlx5_txq_ctrl *txq_ctrl =
1226 container_of(txq_data, struct mlx5_txq_ctrl, txq);
1228 if (txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN)
1229 return mlx5_txq_obj_hairpin_new(dev, idx);
1230 #if !defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) && defined(HAVE_INFINIBAND_VERBS_H)
1231 DRV_LOG(ERR, "Port %u Tx queue %u cannot create with DevX, no UAR.",
1232 dev->data->port_id, idx);
1236 struct mlx5_dev_ctx_shared *sh = priv->sh;
1237 struct mlx5_txq_obj *txq_obj = txq_ctrl->obj;
1238 struct mlx5_devx_cq_attr cq_attr = {
1239 .uar_page_id = mlx5_os_get_devx_uar_page_id(sh->tx_uar),
1242 uint32_t cqe_n, log_desc_n;
1243 uint32_t wqe_n, wqe_size;
1246 MLX5_ASSERT(txq_data);
1247 MLX5_ASSERT(txq_obj);
1248 txq_obj->txq_ctrl = txq_ctrl;
1250 cqe_n = (1UL << txq_data->elts_n) / MLX5_TX_COMP_THRESH +
1251 1 + MLX5_TX_COMP_THRESH_INLINE_DIV;
1252 log_desc_n = log2above(cqe_n);
1253 cqe_n = 1UL << log_desc_n;
1254 if (cqe_n > UINT16_MAX) {
1255 DRV_LOG(ERR, "Port %u Tx queue %u requests to many CQEs %u.",
1256 dev->data->port_id, txq_data->idx, cqe_n);
1260 /* Create completion queue object with DevX. */
1261 ret = mlx5_devx_cq_create(sh->cdev->ctx, &txq_obj->cq_obj, log_desc_n,
1262 &cq_attr, priv->sh->numa_node);
1264 DRV_LOG(ERR, "Port %u Tx queue %u CQ creation failure.",
1265 dev->data->port_id, idx);
1268 txq_data->cqe_n = log_desc_n;
1269 txq_data->cqe_s = cqe_n;
1270 txq_data->cqe_m = txq_data->cqe_s - 1;
1271 txq_data->cqes = txq_obj->cq_obj.cqes;
1272 txq_data->cq_ci = 0;
1273 txq_data->cq_pi = 0;
1274 txq_data->cq_db = txq_obj->cq_obj.db_rec;
1275 *txq_data->cq_db = 0;
1277 * Adjust the amount of WQEs depending on inline settings.
1278 * The number of descriptors should be enough to handle
1279 * the specified number of packets. If queue is being created
1280 * with Verbs the rdma-core does queue size adjustment
1281 * internally in the mlx5_calc_sq_size(), we do the same
1282 * for the queue being created with DevX at this point.
1284 wqe_size = txq_data->tso_en ?
1285 RTE_ALIGN(txq_ctrl->max_tso_header, MLX5_WSEG_SIZE) : 0;
1286 wqe_size += sizeof(struct mlx5_wqe_cseg) +
1287 sizeof(struct mlx5_wqe_eseg) +
1288 sizeof(struct mlx5_wqe_dseg);
1289 if (txq_data->inlen_send)
1290 wqe_size = RTE_MAX(wqe_size, sizeof(struct mlx5_wqe_cseg) +
1291 sizeof(struct mlx5_wqe_eseg) +
1292 RTE_ALIGN(txq_data->inlen_send +
1295 wqe_size = RTE_ALIGN(wqe_size, MLX5_WQE_SIZE) / MLX5_WQE_SIZE;
1296 /* Create Send Queue object with DevX. */
1297 wqe_n = RTE_MIN((1UL << txq_data->elts_n) * wqe_size,
1298 (uint32_t)priv->sh->device_attr.max_qp_wr);
1299 log_desc_n = log2above(wqe_n);
1300 ret = mlx5_txq_create_devx_sq_resources(dev, idx, log_desc_n);
1302 DRV_LOG(ERR, "Port %u Tx queue %u SQ creation failure.",
1303 dev->data->port_id, idx);
1307 /* Create the Work Queue. */
1308 txq_data->wqe_n = log_desc_n;
1309 txq_data->wqe_s = 1 << txq_data->wqe_n;
1310 txq_data->wqe_m = txq_data->wqe_s - 1;
1311 txq_data->wqes = (struct mlx5_wqe *)(uintptr_t)txq_obj->sq_obj.wqes;
1312 txq_data->wqes_end = txq_data->wqes + txq_data->wqe_s;
1313 txq_data->wqe_ci = 0;
1314 txq_data->wqe_pi = 0;
1315 txq_data->wqe_comp = 0;
1316 txq_data->wqe_thres = txq_data->wqe_s / MLX5_TX_COMP_THRESH_INLINE_DIV;
1317 txq_data->qp_db = &txq_obj->sq_obj.db_rec[MLX5_SND_DBR];
1318 *txq_data->qp_db = 0;
1319 txq_data->qp_num_8s = txq_obj->sq_obj.sq->id << 8;
1320 /* Change Send Queue state to Ready-to-Send. */
1321 ret = mlx5_txq_devx_modify(txq_obj, MLX5_TXQ_MOD_RST2RDY, 0);
1325 "Port %u Tx queue %u SQ state to SQC_STATE_RDY failed.",
1326 dev->data->port_id, idx);
1329 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1331 * If using DevX need to query and store TIS transport domain value.
1332 * This is done once per port.
1333 * Will use this value on Rx, when creating matching TIR.
1336 priv->sh->tdn = priv->sh->td->id;
1338 MLX5_ASSERT(sh->tx_uar);
1339 reg_addr = mlx5_os_get_devx_uar_reg_addr(sh->tx_uar);
1340 MLX5_ASSERT(reg_addr);
1341 txq_ctrl->bf_reg = reg_addr;
1342 txq_ctrl->uar_mmap_offset =
1343 mlx5_os_get_devx_uar_mmap_offset(sh->tx_uar);
1344 txq_uar_init(txq_ctrl);
1345 dev->data->tx_queue_state[idx] = RTE_ETH_QUEUE_STATE_STARTED;
1348 ret = rte_errno; /* Save rte_errno before cleanup. */
1349 mlx5_txq_release_devx_resources(txq_obj);
1350 rte_errno = ret; /* Restore rte_errno. */
1356 * Release an Tx DevX queue object.
1359 * DevX Tx queue object.
1362 mlx5_txq_devx_obj_release(struct mlx5_txq_obj *txq_obj)
1364 MLX5_ASSERT(txq_obj);
1365 if (txq_obj->txq_ctrl->type == MLX5_TXQ_TYPE_HAIRPIN) {
1367 claim_zero(mlx5_devx_cmd_destroy(txq_obj->tis));
1368 #if defined(HAVE_MLX5DV_DEVX_UAR_OFFSET) || !defined(HAVE_INFINIBAND_VERBS_H)
1370 mlx5_txq_release_devx_resources(txq_obj);
1375 struct mlx5_obj_ops devx_obj_ops = {
1376 .rxq_obj_modify_vlan_strip = mlx5_rxq_obj_modify_rq_vlan_strip,
1377 .rxq_obj_new = mlx5_rxq_devx_obj_new,
1378 .rxq_event_get = mlx5_rx_devx_get_event,
1379 .rxq_obj_modify = mlx5_devx_modify_rq,
1380 .rxq_obj_release = mlx5_rxq_devx_obj_release,
1381 .ind_table_new = mlx5_devx_ind_table_new,
1382 .ind_table_modify = mlx5_devx_ind_table_modify,
1383 .ind_table_destroy = mlx5_devx_ind_table_destroy,
1384 .hrxq_new = mlx5_devx_hrxq_new,
1385 .hrxq_destroy = mlx5_devx_tir_destroy,
1386 .hrxq_modify = mlx5_devx_hrxq_modify,
1387 .drop_action_create = mlx5_devx_drop_action_create,
1388 .drop_action_destroy = mlx5_devx_drop_action_destroy,
1389 .txq_obj_new = mlx5_txq_devx_obj_new,
1390 .txq_obj_modify = mlx5_txq_devx_modify,
1391 .txq_obj_release = mlx5_txq_devx_obj_release,
1392 .lb_dummy_queue_create = NULL,
1393 .lb_dummy_queue_release = NULL,