1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
4 #include <rte_flow_driver.h>
5 #include <rte_malloc.h>
13 * Allocate flow counters via devx interface.
16 * ibv contexts returned from mlx5dv_open_device.
18 * Pointer to counters properties structure to be filled by the routine.
20 * Bulk counter numbers in 128 counters units.
23 * Pointer to counter object on success, a negative value otherwise and
26 struct mlx5_devx_obj *
27 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
29 struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
30 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
31 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
37 MLX5_SET(alloc_flow_counter_in, in, opcode,
38 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
39 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
40 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
41 sizeof(in), out, sizeof(out));
43 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
48 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
53 * Query flow counters values.
56 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
58 * Whether hardware should clear the counters after the query or not.
59 * @param[in] n_counters
60 * 0 in case of 1 counter to read, otherwise the counter number to read.
62 * The number of packets that matched the flow.
64 * The number of bytes that matched the flow.
66 * The mkey key for batch query.
68 * The address in the mkey range for batch query.
70 * The completion object for asynchronous batch query.
72 * The ID to be returned in the asynchronous batch query response.
75 * 0 on success, a negative value otherwise.
78 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
79 int clear, uint32_t n_counters,
80 uint64_t *pkts, uint64_t *bytes,
81 uint32_t mkey, void *addr,
82 struct mlx5dv_devx_cmd_comp *cmd_comp,
85 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
86 MLX5_ST_SZ_BYTES(traffic_counter);
87 uint32_t out[out_len];
88 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
92 MLX5_SET(query_flow_counter_in, in, opcode,
93 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
94 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
95 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
96 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
99 MLX5_SET(query_flow_counter_in, in, num_of_counters,
101 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
102 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
103 MLX5_SET64(query_flow_counter_in, in, address,
104 (uint64_t)(uintptr_t)addr);
107 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
110 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
114 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
119 stats = MLX5_ADDR_OF(query_flow_counter_out,
120 out, flow_statistics);
121 *pkts = MLX5_GET64(traffic_counter, stats, packets);
122 *bytes = MLX5_GET64(traffic_counter, stats, octets);
131 * ibv contexts returned from mlx5dv_open_device.
133 * Attributes of the requested mkey.
136 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
139 struct mlx5_devx_obj *
140 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
141 struct mlx5_devx_mkey_attr *attr)
143 uint32_t in[MLX5_ST_SZ_DW(create_mkey_in)] = {0};
144 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
146 struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
148 uint32_t translation_size;
154 pgsize = sysconf(_SC_PAGESIZE);
155 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
156 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
157 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
159 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
160 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
161 MLX5_SET(mkc, mkc, lw, 0x1);
162 MLX5_SET(mkc, mkc, lr, 0x1);
163 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
164 MLX5_SET(mkc, mkc, qpn, 0xffffff);
165 MLX5_SET(mkc, mkc, pd, attr->pd);
166 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
167 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
168 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
169 MLX5_SET64(mkc, mkc, len, attr->size);
170 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
171 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
174 DRV_LOG(ERR, "Can't create mkey - error %d", errno);
179 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
180 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
185 * Get status of devx command response.
186 * Mainly used for asynchronous commands.
189 * The out response buffer.
192 * 0 on success, non-zero value otherwise.
195 mlx5_devx_get_out_command_status(void *out)
201 status = MLX5_GET(query_flow_counter_out, out, status);
203 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
205 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
212 * Destroy any object allocated by a Devx API.
215 * Pointer to a general object.
218 * 0 on success, a negative value otherwise.
221 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
227 ret = mlx5_glue->devx_obj_destroy(obj->obj);
233 * Query NIC vport context.
234 * Fills minimal inline attribute.
237 * ibv contexts returned from mlx5dv_open_device.
241 * Attributes device values.
244 * 0 on success, a negative value otherwise.
247 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
249 struct mlx5_hca_attr *attr)
251 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
252 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
254 int status, syndrome, rc;
256 /* Query NIC vport context to determine inline mode. */
257 MLX5_SET(query_nic_vport_context_in, in, opcode,
258 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
259 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
261 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
262 rc = mlx5_glue->devx_general_cmd(ctx,
267 status = MLX5_GET(query_nic_vport_context_out, out, status);
268 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
270 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
271 "status %x, syndrome = %x",
275 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
277 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
278 min_wqe_inline_mode);
281 rc = (rc > 0) ? -rc : rc;
286 * Query HCA attributes.
287 * Using those attributes we can check on run time if the device
288 * is having the required capabilities.
291 * ibv contexts returned from mlx5dv_open_device.
293 * Attributes device values.
296 * 0 on success, a negative value otherwise.
299 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
300 struct mlx5_hca_attr *attr)
302 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
303 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
305 int status, syndrome, rc;
307 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
308 MLX5_SET(query_hca_cap_in, in, op_mod,
309 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
310 MLX5_HCA_CAP_OPMOD_GET_CUR);
312 rc = mlx5_glue->devx_general_cmd(ctx,
313 in, sizeof(in), out, sizeof(out));
316 status = MLX5_GET(query_hca_cap_out, out, status);
317 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
319 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
320 "status %x, syndrome = %x",
324 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
325 attr->flow_counter_bulk_alloc_bitmap =
326 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
327 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
329 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
330 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
331 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
332 log_max_hairpin_queues);
333 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
334 log_max_hairpin_wq_data_sz);
335 attr->log_max_hairpin_num_packets = MLX5_GET
336 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
337 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
338 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
340 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
341 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
342 flex_parser_protocols);
343 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
345 MLX5_SET(query_hca_cap_in, in, op_mod,
346 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
347 MLX5_HCA_CAP_OPMOD_GET_CUR);
348 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
353 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
354 " status %x, syndrome = %x",
358 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
359 attr->qos.srtcm_sup =
360 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
361 attr->qos.log_max_flow_meter =
362 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
363 attr->qos.flow_meter_reg_c_ids =
364 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
365 attr->qos.flow_meter_reg_share =
366 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
368 if (!attr->eth_net_offloads)
371 /* Query HCA offloads for Ethernet protocol. */
372 memset(in, 0, sizeof(in));
373 memset(out, 0, sizeof(out));
374 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
375 MLX5_SET(query_hca_cap_in, in, op_mod,
376 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
377 MLX5_HCA_CAP_OPMOD_GET_CUR);
379 rc = mlx5_glue->devx_general_cmd(ctx,
383 attr->eth_net_offloads = 0;
386 status = MLX5_GET(query_hca_cap_out, out, status);
387 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
389 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
390 "status %x, syndrome = %x",
392 attr->eth_net_offloads = 0;
395 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
396 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
397 hcattr, wqe_vlan_insert);
398 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
400 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
401 hcattr, tunnel_lro_gre);
402 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
403 hcattr, tunnel_lro_vxlan);
404 attr->lro_max_msg_sz_mode = MLX5_GET
405 (per_protocol_networking_offload_caps,
406 hcattr, lro_max_msg_sz_mode);
407 for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
408 attr->lro_timer_supported_periods[i] =
409 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
410 lro_timer_supported_periods[i]);
412 attr->tunnel_stateless_geneve_rx =
413 MLX5_GET(per_protocol_networking_offload_caps,
414 hcattr, tunnel_stateless_geneve_rx);
415 attr->geneve_max_opt_len =
416 MLX5_GET(per_protocol_networking_offload_caps,
417 hcattr, max_geneve_opt_len);
418 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
419 hcattr, wqe_inline_mode);
420 attr->tunnel_stateless_gtp = MLX5_GET
421 (per_protocol_networking_offload_caps,
422 hcattr, tunnel_stateless_gtp);
423 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
425 if (attr->eth_virt) {
426 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
434 rc = (rc > 0) ? -rc : rc;
439 * Query TIS transport domain from QP verbs object using DevX API.
442 * Pointer to verbs QP returned by ibv_create_qp .
444 * TIS number of TIS to query.
446 * Pointer to TIS transport domain variable, to be set by the routine.
449 * 0 on success, a negative value otherwise.
452 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
455 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
456 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
460 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
461 MLX5_SET(query_tis_in, in, tisn, tis_num);
462 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
464 DRV_LOG(ERR, "Failed to query QP using DevX");
467 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
468 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
473 * Fill WQ data for DevX API command.
474 * Utility function for use when creating DevX objects containing a WQ.
477 * Pointer to WQ context to fill with data.
478 * @param [in] wq_attr
479 * Pointer to WQ attributes structure to fill in WQ context.
482 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
484 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
485 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
486 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
487 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
488 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
489 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
490 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
491 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
492 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
493 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
494 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
495 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
496 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
497 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
498 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
499 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
500 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
501 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
502 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
503 wq_attr->log_hairpin_num_packets);
504 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
505 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
506 wq_attr->single_wqe_log_num_of_strides);
507 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
508 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
509 wq_attr->single_stride_log_num_of_bytes);
510 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
511 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
512 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
516 * Create RQ using DevX API.
519 * ibv_context returned from mlx5dv_open_device.
520 * @param [in] rq_attr
521 * Pointer to create RQ attributes structure.
523 * CPU socket ID for allocations.
526 * The DevX object created, NULL otherwise and rte_errno is set.
528 struct mlx5_devx_obj *
529 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
530 struct mlx5_devx_create_rq_attr *rq_attr,
533 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
534 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
535 void *rq_ctx, *wq_ctx;
536 struct mlx5_devx_wq_attr *wq_attr;
537 struct mlx5_devx_obj *rq = NULL;
539 rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
541 DRV_LOG(ERR, "Failed to allocate RQ data");
545 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
546 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
547 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
548 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
549 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
550 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
551 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
552 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
553 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
554 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
555 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
556 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
557 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
558 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
559 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
560 wq_attr = &rq_attr->wq_attr;
561 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
562 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
565 DRV_LOG(ERR, "Failed to create RQ using DevX");
570 rq->id = MLX5_GET(create_rq_out, out, rqn);
575 * Modify RQ using DevX API.
578 * Pointer to RQ object structure.
579 * @param [in] rq_attr
580 * Pointer to modify RQ attributes structure.
583 * 0 on success, a negative errno value otherwise and rte_errno is set.
586 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
587 struct mlx5_devx_modify_rq_attr *rq_attr)
589 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
590 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
591 void *rq_ctx, *wq_ctx;
594 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
595 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
596 MLX5_SET(modify_rq_in, in, rqn, rq->id);
597 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
598 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
599 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
600 if (rq_attr->modify_bitmask &
601 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
602 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
603 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
604 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
605 if (rq_attr->modify_bitmask &
606 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
607 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
608 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
609 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
610 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
611 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
612 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
614 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
617 DRV_LOG(ERR, "Failed to modify RQ using DevX");
625 * Create TIR using DevX API.
628 * ibv_context returned from mlx5dv_open_device.
629 * @param [in] tir_attr
630 * Pointer to TIR attributes structure.
633 * The DevX object created, NULL otherwise and rte_errno is set.
635 struct mlx5_devx_obj *
636 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
637 struct mlx5_devx_tir_attr *tir_attr)
639 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
640 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
641 void *tir_ctx, *outer, *inner;
642 struct mlx5_devx_obj *tir = NULL;
645 tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
647 DRV_LOG(ERR, "Failed to allocate TIR data");
651 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
652 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
653 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
654 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
655 tir_attr->lro_timeout_period_usecs);
656 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
657 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
658 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
659 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
660 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
661 tir_attr->tunneled_offload_en);
662 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
663 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
664 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
665 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
666 for (i = 0; i < 10; i++) {
667 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
668 tir_attr->rx_hash_toeplitz_key[i]);
670 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
671 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
672 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
673 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
674 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
675 MLX5_SET(rx_hash_field_select, outer, selected_fields,
676 tir_attr->rx_hash_field_selector_outer.selected_fields);
677 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
678 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
679 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
680 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
681 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
682 MLX5_SET(rx_hash_field_select, inner, selected_fields,
683 tir_attr->rx_hash_field_selector_inner.selected_fields);
684 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
687 DRV_LOG(ERR, "Failed to create TIR using DevX");
692 tir->id = MLX5_GET(create_tir_out, out, tirn);
697 * Create RQT using DevX API.
700 * ibv_context returned from mlx5dv_open_device.
701 * @param [in] rqt_attr
702 * Pointer to RQT attributes structure.
705 * The DevX object created, NULL otherwise and rte_errno is set.
707 struct mlx5_devx_obj *
708 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
709 struct mlx5_devx_rqt_attr *rqt_attr)
712 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
713 rqt_attr->rqt_actual_size * sizeof(uint32_t);
714 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
716 struct mlx5_devx_obj *rqt = NULL;
719 in = rte_calloc(__func__, 1, inlen, 0);
721 DRV_LOG(ERR, "Failed to allocate RQT IN data");
725 rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
727 DRV_LOG(ERR, "Failed to allocate RQT data");
732 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
733 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
734 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
735 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
736 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
737 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
738 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
741 DRV_LOG(ERR, "Failed to create RQT using DevX");
746 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
751 * Create SQ using DevX API.
754 * ibv_context returned from mlx5dv_open_device.
755 * @param [in] sq_attr
756 * Pointer to SQ attributes structure.
758 * CPU socket ID for allocations.
761 * The DevX object created, NULL otherwise and rte_errno is set.
763 struct mlx5_devx_obj *
764 mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
765 struct mlx5_devx_create_sq_attr *sq_attr)
767 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
768 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
771 struct mlx5_devx_wq_attr *wq_attr;
772 struct mlx5_devx_obj *sq = NULL;
774 sq = rte_calloc(__func__, 1, sizeof(*sq), 0);
776 DRV_LOG(ERR, "Failed to allocate SQ data");
780 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
781 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
782 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
783 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
784 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
785 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
786 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
787 sq_attr->flush_in_error_en);
788 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
789 sq_attr->min_wqe_inline_mode);
790 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
791 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
792 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
793 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
794 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
795 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
796 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
797 sq_attr->packet_pacing_rate_limit_index);
798 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
799 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
800 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
801 wq_attr = &sq_attr->wq_attr;
802 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
803 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
806 DRV_LOG(ERR, "Failed to create SQ using DevX");
811 sq->id = MLX5_GET(create_sq_out, out, sqn);
816 * Modify SQ using DevX API.
819 * Pointer to SQ object structure.
820 * @param [in] sq_attr
821 * Pointer to SQ attributes structure.
824 * 0 on success, a negative errno value otherwise and rte_errno is set.
827 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
828 struct mlx5_devx_modify_sq_attr *sq_attr)
830 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
831 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
835 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
836 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
837 MLX5_SET(modify_sq_in, in, sqn, sq->id);
838 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
839 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
840 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
841 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
842 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
845 DRV_LOG(ERR, "Failed to modify SQ using DevX");
853 * Create TIS using DevX API.
856 * ibv_context returned from mlx5dv_open_device.
857 * @param [in] tis_attr
858 * Pointer to TIS attributes structure.
861 * The DevX object created, NULL otherwise and rte_errno is set.
863 struct mlx5_devx_obj *
864 mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
865 struct mlx5_devx_tis_attr *tis_attr)
867 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
868 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
869 struct mlx5_devx_obj *tis = NULL;
872 tis = rte_calloc(__func__, 1, sizeof(*tis), 0);
874 DRV_LOG(ERR, "Failed to allocate TIS object");
878 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
879 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
880 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
881 tis_attr->strict_lag_tx_port_affinity);
882 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
883 tis_attr->strict_lag_tx_port_affinity);
884 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
885 MLX5_SET(tisc, tis_ctx, transport_domain,
886 tis_attr->transport_domain);
887 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
890 DRV_LOG(ERR, "Failed to create TIS using DevX");
895 tis->id = MLX5_GET(create_tis_out, out, tisn);
900 * Create transport domain using DevX API.
903 * ibv_context returned from mlx5dv_open_device.
906 * The DevX object created, NULL otherwise and rte_errno is set.
908 struct mlx5_devx_obj *
909 mlx5_devx_cmd_create_td(struct ibv_context *ctx)
911 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
912 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
913 struct mlx5_devx_obj *td = NULL;
915 td = rte_calloc(__func__, 1, sizeof(*td), 0);
917 DRV_LOG(ERR, "Failed to allocate TD object");
921 MLX5_SET(alloc_transport_domain_in, in, opcode,
922 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
923 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
926 DRV_LOG(ERR, "Failed to create TIS using DevX");
931 td->id = MLX5_GET(alloc_transport_domain_out, out,
937 * Dump all flows to file.
940 * Pointer to context.
942 * Pointer to file stream.
945 * 0 on success, a nagative value otherwise.
948 mlx5_devx_cmd_flow_dump(struct mlx5_ibv_shared *sh __rte_unused,
949 FILE *file __rte_unused)
953 #ifdef HAVE_MLX5_DR_FLOW_DUMP
954 if (sh->fdb_domain) {
955 ret = mlx5_glue->dr_dump_domain(file, sh->fdb_domain);
959 assert(sh->rx_domain);
960 ret = mlx5_glue->dr_dump_domain(file, sh->rx_domain);
963 assert(sh->tx_domain);
964 ret = mlx5_glue->dr_dump_domain(file, sh->tx_domain);