1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
15 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
17 #pragma GCC diagnostic ignored "-Wpedantic"
19 #include <infiniband/verbs.h>
21 #pragma GCC diagnostic error "-Wpedantic"
24 #include <rte_atomic.h>
25 #include <rte_alarm.h>
43 /* Private rte flow items. */
44 enum mlx5_rte_flow_item_type {
45 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
46 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
49 /* Private rte flow actions. */
50 enum mlx5_rte_flow_action_type {
51 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
52 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
55 /* Matches on selected register. */
56 struct mlx5_rte_flow_item_tag {
61 /* Modify selected register. */
62 struct mlx5_rte_flow_action_set_tag {
67 /* Pattern outer Layer bits. */
68 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
69 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
70 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
71 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
72 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
73 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
75 /* Pattern inner Layer bits. */
76 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
77 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
78 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
79 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
80 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
81 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
83 /* Pattern tunnel Layer bits. */
84 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
85 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
86 #define MLX5_FLOW_LAYER_GRE (1u << 14)
87 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
88 /* List of tunnel Layer bits continued below. */
90 /* General pattern items bits. */
91 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
92 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
93 #define MLX5_FLOW_ITEM_TAG (1u << 18)
95 /* Pattern MISC bits. */
96 #define MLX5_FLOW_LAYER_ICMP (1u << 19)
97 #define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
98 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
100 /* Pattern tunnel Layer bits (continued). */
101 #define MLX5_FLOW_LAYER_IPIP (1u << 21)
102 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
103 #define MLX5_FLOW_LAYER_NVGRE (1u << 23)
104 #define MLX5_FLOW_LAYER_GENEVE (1u << 24)
107 #define MLX5_FLOW_LAYER_OUTER_L3 \
108 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
109 #define MLX5_FLOW_LAYER_OUTER_L4 \
110 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
111 #define MLX5_FLOW_LAYER_OUTER \
112 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
113 MLX5_FLOW_LAYER_OUTER_L4)
115 /* LRO support mask, i.e. flow contains IPv4/IPv6 and TCP. */
116 #define MLX5_FLOW_LAYER_IPV4_LRO \
117 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
118 #define MLX5_FLOW_LAYER_IPV6_LRO \
119 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_OUTER_L4_TCP)
122 #define MLX5_FLOW_LAYER_TUNNEL \
123 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
124 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
125 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
126 MLX5_FLOW_LAYER_GENEVE)
129 #define MLX5_FLOW_LAYER_INNER_L3 \
130 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
131 #define MLX5_FLOW_LAYER_INNER_L4 \
132 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
133 #define MLX5_FLOW_LAYER_INNER \
134 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
135 MLX5_FLOW_LAYER_INNER_L4)
138 #define MLX5_FLOW_LAYER_L2 \
139 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
140 #define MLX5_FLOW_LAYER_L3_IPV4 \
141 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
142 #define MLX5_FLOW_LAYER_L3_IPV6 \
143 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
144 #define MLX5_FLOW_LAYER_L3 \
145 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
146 #define MLX5_FLOW_LAYER_L4 \
147 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
150 #define MLX5_FLOW_ACTION_DROP (1u << 0)
151 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
152 #define MLX5_FLOW_ACTION_RSS (1u << 2)
153 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
154 #define MLX5_FLOW_ACTION_MARK (1u << 4)
155 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
156 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
157 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
158 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
159 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
160 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
161 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
162 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
163 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
164 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
165 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
166 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
167 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
168 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
169 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
170 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
171 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
172 #define MLX5_FLOW_ACTION_VXLAN_ENCAP (1u << 22)
173 #define MLX5_FLOW_ACTION_VXLAN_DECAP (1u << 23)
174 #define MLX5_FLOW_ACTION_NVGRE_ENCAP (1u << 24)
175 #define MLX5_FLOW_ACTION_NVGRE_DECAP (1u << 25)
176 #define MLX5_FLOW_ACTION_RAW_ENCAP (1u << 26)
177 #define MLX5_FLOW_ACTION_RAW_DECAP (1u << 27)
178 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 28)
179 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 29)
180 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 30)
181 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 31)
182 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 32)
184 #define MLX5_FLOW_FATE_ACTIONS \
185 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
186 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP)
188 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
189 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
190 MLX5_FLOW_ACTION_JUMP)
192 #define MLX5_FLOW_ENCAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_ENCAP | \
193 MLX5_FLOW_ACTION_NVGRE_ENCAP | \
194 MLX5_FLOW_ACTION_RAW_ENCAP | \
195 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
197 #define MLX5_FLOW_DECAP_ACTIONS (MLX5_FLOW_ACTION_VXLAN_DECAP | \
198 MLX5_FLOW_ACTION_NVGRE_DECAP | \
199 MLX5_FLOW_ACTION_RAW_DECAP | \
200 MLX5_FLOW_ACTION_OF_POP_VLAN)
202 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
203 MLX5_FLOW_ACTION_SET_IPV4_DST | \
204 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
205 MLX5_FLOW_ACTION_SET_IPV6_DST | \
206 MLX5_FLOW_ACTION_SET_TP_SRC | \
207 MLX5_FLOW_ACTION_SET_TP_DST | \
208 MLX5_FLOW_ACTION_SET_TTL | \
209 MLX5_FLOW_ACTION_DEC_TTL | \
210 MLX5_FLOW_ACTION_SET_MAC_SRC | \
211 MLX5_FLOW_ACTION_SET_MAC_DST | \
212 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
213 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
214 MLX5_FLOW_ACTION_INC_TCP_ACK | \
215 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
216 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
217 MLX5_FLOW_ACTION_SET_TAG)
219 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
220 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
223 #define IPPROTO_MPLS 137
226 /* UDP port number for MPLS */
227 #define MLX5_UDP_PORT_MPLS 6635
229 /* UDP port numbers for VxLAN. */
230 #define MLX5_UDP_PORT_VXLAN 4789
231 #define MLX5_UDP_PORT_VXLAN_GPE 4790
233 /* UDP port numbers for GENEVE. */
234 #define MLX5_UDP_PORT_GENEVE 6081
236 /* Priority reserved for default flows. */
237 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
240 * Number of sub priorities.
241 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
242 * matching on the NIC (firmware dependent) L4 most have the higher priority
243 * followed by L3 and ending with L2.
245 #define MLX5_PRIORITY_MAP_L2 2
246 #define MLX5_PRIORITY_MAP_L3 1
247 #define MLX5_PRIORITY_MAP_L4 0
248 #define MLX5_PRIORITY_MAP_MAX 3
250 /* Valid layer type for IPV4 RSS. */
251 #define MLX5_IPV4_LAYER_TYPES \
252 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
253 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
254 ETH_RSS_NONFRAG_IPV4_OTHER)
256 /* IBV hash source bits for IPV4. */
257 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
259 /* Valid layer type for IPV6 RSS. */
260 #define MLX5_IPV6_LAYER_TYPES \
261 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
262 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
263 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
265 /* IBV hash source bits for IPV6. */
266 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
269 /* Geneve header first 16Bit */
270 #define MLX5_GENEVE_VER_MASK 0x3
271 #define MLX5_GENEVE_VER_SHIFT 14
272 #define MLX5_GENEVE_VER_VAL(a) \
273 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
274 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
275 #define MLX5_GENEVE_OPTLEN_SHIFT 7
276 #define MLX5_GENEVE_OPTLEN_VAL(a) \
277 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
278 #define MLX5_GENEVE_OAMF_MASK 0x1
279 #define MLX5_GENEVE_OAMF_SHIFT 7
280 #define MLX5_GENEVE_OAMF_VAL(a) \
281 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
282 #define MLX5_GENEVE_CRITO_MASK 0x1
283 #define MLX5_GENEVE_CRITO_SHIFT 6
284 #define MLX5_GENEVE_CRITO_VAL(a) \
285 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
286 #define MLX5_GENEVE_RSVD_MASK 0x3F
287 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
289 * The length of the Geneve options fields, expressed in four byte multiples,
290 * not including the eight byte fixed tunnel.
292 #define MLX5_GENEVE_OPT_LEN_0 14
293 #define MLX5_GENEVE_OPT_LEN_1 63
295 enum mlx5_flow_drv_type {
298 MLX5_FLOW_TYPE_VERBS,
302 /* Matcher PRM representation */
303 struct mlx5_flow_dv_match_params {
305 /**< Size of match value. Do NOT split size and key! */
306 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
307 /**< Matcher value. This value is used as the mask or as a key. */
310 /* Matcher structure. */
311 struct mlx5_flow_dv_matcher {
312 LIST_ENTRY(mlx5_flow_dv_matcher) next;
313 /* Pointer to the next element. */
314 rte_atomic32_t refcnt; /**< Reference counter. */
315 void *matcher_object; /**< Pointer to DV matcher */
316 uint16_t crc; /**< CRC of key. */
317 uint16_t priority; /**< Priority of matcher. */
318 uint8_t egress; /**< Egress matcher. */
319 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
320 uint32_t group; /**< The matcher group. */
321 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
324 #define MLX5_ENCAP_MAX_LEN 132
326 /* Encap/decap resource structure. */
327 struct mlx5_flow_dv_encap_decap_resource {
328 LIST_ENTRY(mlx5_flow_dv_encap_decap_resource) next;
329 /* Pointer to next element. */
330 rte_atomic32_t refcnt; /**< Reference counter. */
332 /**< Verbs encap/decap action object. */
333 uint8_t buf[MLX5_ENCAP_MAX_LEN];
335 uint8_t reformat_type;
337 uint64_t flags; /**< Flags for RDMA API. */
340 /* Tag resource structure. */
341 struct mlx5_flow_dv_tag_resource {
342 LIST_ENTRY(mlx5_flow_dv_tag_resource) next;
343 /* Pointer to next element. */
344 rte_atomic32_t refcnt; /**< Reference counter. */
346 /**< Verbs tag action object. */
347 uint32_t tag; /**< the tag value. */
350 /* Number of modification commands. */
351 #define MLX5_MODIFY_NUM 8
353 /* Modify resource structure */
354 struct mlx5_flow_dv_modify_hdr_resource {
355 LIST_ENTRY(mlx5_flow_dv_modify_hdr_resource) next;
356 /* Pointer to next element. */
357 rte_atomic32_t refcnt; /**< Reference counter. */
358 struct ibv_flow_action *verbs_action;
359 /**< Verbs modify header action object. */
360 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
361 uint32_t actions_num; /**< Number of modification actions. */
362 struct mlx5_modification_cmd actions[MLX5_MODIFY_NUM];
363 /**< Modification actions. */
364 uint64_t flags; /**< Flags for RDMA API. */
367 /* Jump action resource structure. */
368 struct mlx5_flow_dv_jump_tbl_resource {
369 LIST_ENTRY(mlx5_flow_dv_jump_tbl_resource) next;
370 /* Pointer to next element. */
371 rte_atomic32_t refcnt; /**< Reference counter. */
372 void *action; /**< Pointer to the rdma core action. */
373 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
374 struct mlx5_flow_tbl_resource *tbl; /**< The target table. */
377 /* Port ID resource structure. */
378 struct mlx5_flow_dv_port_id_action_resource {
379 LIST_ENTRY(mlx5_flow_dv_port_id_action_resource) next;
380 /* Pointer to next element. */
381 rte_atomic32_t refcnt; /**< Reference counter. */
383 /**< Verbs tag action object. */
384 uint32_t port_id; /**< Port ID value. */
387 /* Push VLAN action resource structure */
388 struct mlx5_flow_dv_push_vlan_action_resource {
389 LIST_ENTRY(mlx5_flow_dv_push_vlan_action_resource) next;
390 /* Pointer to next element. */
391 rte_atomic32_t refcnt; /**< Reference counter. */
392 void *action; /**< Direct verbs action object. */
393 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
394 rte_be32_t vlan_tag; /**< VLAN tag value. */
398 * Max number of actions per DV flow.
399 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
400 * In rdma-core file providers/mlx5/verbs.c
402 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
404 /* DV flows structure. */
405 struct mlx5_flow_dv {
406 uint64_t hash_fields; /**< Fields that participate in the hash. */
407 struct mlx5_hrxq *hrxq; /**< Hash Rx queues. */
409 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
410 struct mlx5_flow_dv_match_params value;
411 /**< Holds the value that the packet is compared to. */
412 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
413 /**< Pointer to encap/decap resource in cache. */
414 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
415 /**< Pointer to modify header resource in cache. */
416 struct ibv_flow *flow; /**< Installed flow. */
417 struct mlx5_flow_dv_jump_tbl_resource *jump;
418 /**< Pointer to the jump action resource. */
419 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
420 /**< Pointer to port ID action resource. */
421 struct mlx5_vf_vlan vf_vlan;
422 /**< Structure for VF VLAN workaround. */
423 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
424 /**< Pointer to push VLAN action resource in cache. */
425 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
426 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS];
429 int actions_n; /**< number of actions. */
432 /* Verbs specification header. */
433 struct ibv_spec_header {
434 enum ibv_flow_spec_type type;
438 /** Handles information leading to a drop fate. */
439 struct mlx5_flow_verbs {
440 LIST_ENTRY(mlx5_flow_verbs) next;
441 unsigned int size; /**< Size of the attribute. */
443 struct ibv_flow_attr *attr;
444 /**< Pointer to the Specification buffer. */
445 uint8_t *specs; /**< Pointer to the specifications. */
447 struct ibv_flow *flow; /**< Verbs flow pointer. */
448 struct mlx5_hrxq *hrxq; /**< Hash Rx queue object. */
449 uint64_t hash_fields; /**< Verbs hash Rx queue hash fields. */
450 struct mlx5_vf_vlan vf_vlan;
451 /**< Structure for VF VLAN workaround. */
454 /** Device flow structure. */
456 LIST_ENTRY(mlx5_flow) next;
457 struct rte_flow *flow; /**< Pointer to the main flow. */
459 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
461 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
462 struct mlx5_flow_dv dv;
464 struct mlx5_flow_verbs verbs;
466 bool external; /**< true if the flow is created external to PMD. */
469 /* Flow structure. */
471 TAILQ_ENTRY(rte_flow) next; /**< Pointer to the next flow structure. */
472 enum mlx5_flow_drv_type drv_type; /**< Driver type. */
473 struct mlx5_flow_counter *counter; /**< Holds flow counter. */
474 struct mlx5_flow_dv_tag_resource *tag_resource;
475 /**< pointer to the tag action. */
476 struct rte_flow_action_rss rss;/**< RSS context. */
477 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
478 uint16_t (*queue)[]; /**< Destination queues to redirect traffic to. */
479 LIST_HEAD(dev_flows, mlx5_flow) dev_flows;
480 /**< Device flows that are part of the flow. */
482 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
483 struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */
484 uint8_t ingress; /**< 1 if the flow is ingress. */
485 uint32_t group; /**< The group index. */
486 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
489 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
490 const struct rte_flow_attr *attr,
491 const struct rte_flow_item items[],
492 const struct rte_flow_action actions[],
494 struct rte_flow_error *error);
495 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
496 (const struct rte_flow_attr *attr, const struct rte_flow_item items[],
497 const struct rte_flow_action actions[], struct rte_flow_error *error);
498 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
499 struct mlx5_flow *dev_flow,
500 const struct rte_flow_attr *attr,
501 const struct rte_flow_item items[],
502 const struct rte_flow_action actions[],
503 struct rte_flow_error *error);
504 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
505 struct rte_flow_error *error);
506 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
507 struct rte_flow *flow);
508 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
509 struct rte_flow *flow);
510 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
511 struct rte_flow *flow,
512 const struct rte_flow_action *actions,
514 struct rte_flow_error *error);
515 struct mlx5_flow_driver_ops {
516 mlx5_flow_validate_t validate;
517 mlx5_flow_prepare_t prepare;
518 mlx5_flow_translate_t translate;
519 mlx5_flow_apply_t apply;
520 mlx5_flow_remove_t remove;
521 mlx5_flow_destroy_t destroy;
522 mlx5_flow_query_t query;
525 #define MLX5_CNT_CONTAINER(sh, batch, thread) (&(sh)->cmng.ccont \
526 [(((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
527 #define MLX5_CNT_CONTAINER_UNUSED(sh, batch, thread) (&(sh)->cmng.ccont \
528 [(~((sh)->cmng.mhi[batch] >> (thread)) & 0x1) * 2 + (batch)])
532 int mlx5_flow_group_to_table(const struct rte_flow_attr *attributes,
533 bool external, uint32_t group, uint32_t *table,
534 struct rte_flow_error *error);
535 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, int tunnel,
536 uint64_t layer_types,
537 uint64_t hash_fields);
538 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
539 uint32_t subpriority);
540 const struct rte_flow_action *mlx5_flow_find_action
541 (const struct rte_flow_action *actions,
542 enum rte_flow_action_type action);
543 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
544 const struct rte_flow_attr *attr,
545 struct rte_flow_error *error);
546 int mlx5_flow_validate_action_drop(uint64_t action_flags,
547 const struct rte_flow_attr *attr,
548 struct rte_flow_error *error);
549 int mlx5_flow_validate_action_flag(uint64_t action_flags,
550 const struct rte_flow_attr *attr,
551 struct rte_flow_error *error);
552 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
553 uint64_t action_flags,
554 const struct rte_flow_attr *attr,
555 struct rte_flow_error *error);
556 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
557 uint64_t action_flags,
558 struct rte_eth_dev *dev,
559 const struct rte_flow_attr *attr,
560 struct rte_flow_error *error);
561 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
562 uint64_t action_flags,
563 struct rte_eth_dev *dev,
564 const struct rte_flow_attr *attr,
566 struct rte_flow_error *error);
567 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
568 const struct rte_flow_attr *attributes,
569 struct rte_flow_error *error);
570 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
572 const uint8_t *nic_mask,
574 struct rte_flow_error *error);
575 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
577 struct rte_flow_error *error);
578 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
580 uint8_t target_protocol,
581 struct rte_flow_error *error);
582 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
584 const struct rte_flow_item *gre_item,
585 struct rte_flow_error *error);
586 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
588 const struct rte_flow_item_ipv4 *acc_mask,
589 struct rte_flow_error *error);
590 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
592 const struct rte_flow_item_ipv6 *acc_mask,
593 struct rte_flow_error *error);
594 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
595 const struct rte_flow_item *item,
598 struct rte_flow_error *error);
599 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
601 uint8_t target_protocol,
602 const struct rte_flow_item_tcp *flow_mask,
603 struct rte_flow_error *error);
604 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
606 uint8_t target_protocol,
607 struct rte_flow_error *error);
608 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
610 struct rte_eth_dev *dev,
611 struct rte_flow_error *error);
612 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
614 struct rte_flow_error *error);
615 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
617 struct rte_eth_dev *dev,
618 struct rte_flow_error *error);
619 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
621 uint8_t target_protocol,
622 struct rte_flow_error *error);
623 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
625 uint8_t target_protocol,
626 struct rte_flow_error *error);
627 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
629 uint8_t target_protocol,
630 struct rte_flow_error *error);
631 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
633 struct rte_eth_dev *dev,
634 struct rte_flow_error *error);
635 #endif /* RTE_PMD_MLX5_FLOW_H_ */