1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_FLOW_H_
6 #define RTE_PMD_MLX5_FLOW_H_
8 #include <netinet/in.h>
14 #include <rte_alarm.h>
17 #include <mlx5_glue.h>
22 /* Private rte flow items. */
23 enum mlx5_rte_flow_item_type {
24 MLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,
25 MLX5_RTE_FLOW_ITEM_TYPE_TAG,
26 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,
27 MLX5_RTE_FLOW_ITEM_TYPE_VLAN,
28 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,
31 /* Private (internal) rte flow actions. */
32 enum mlx5_rte_flow_action_type {
33 MLX5_RTE_FLOW_ACTION_TYPE_END = INT_MIN,
34 MLX5_RTE_FLOW_ACTION_TYPE_TAG,
35 MLX5_RTE_FLOW_ACTION_TYPE_MARK,
36 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG,
37 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS,
38 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET,
41 #define MLX5_SHARED_ACTION_TYPE_OFFSET 30
44 MLX5_SHARED_ACTION_TYPE_RSS,
47 /* Matches on selected register. */
48 struct mlx5_rte_flow_item_tag {
53 /* Modify selected register. */
54 struct mlx5_rte_flow_action_set_tag {
59 struct mlx5_flow_action_copy_mreg {
64 /* Matches on source queue. */
65 struct mlx5_rte_flow_item_tx_queue {
69 /* Feature name to allocate metadata register. */
70 enum mlx5_feature_name {
83 /* Default queue number. */
84 #define MLX5_RSSQ_DEFAULT_NUM 16
86 #define MLX5_FLOW_LAYER_OUTER_L2 (1u << 0)
87 #define MLX5_FLOW_LAYER_OUTER_L3_IPV4 (1u << 1)
88 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6 (1u << 2)
89 #define MLX5_FLOW_LAYER_OUTER_L4_UDP (1u << 3)
90 #define MLX5_FLOW_LAYER_OUTER_L4_TCP (1u << 4)
91 #define MLX5_FLOW_LAYER_OUTER_VLAN (1u << 5)
93 /* Pattern inner Layer bits. */
94 #define MLX5_FLOW_LAYER_INNER_L2 (1u << 6)
95 #define MLX5_FLOW_LAYER_INNER_L3_IPV4 (1u << 7)
96 #define MLX5_FLOW_LAYER_INNER_L3_IPV6 (1u << 8)
97 #define MLX5_FLOW_LAYER_INNER_L4_UDP (1u << 9)
98 #define MLX5_FLOW_LAYER_INNER_L4_TCP (1u << 10)
99 #define MLX5_FLOW_LAYER_INNER_VLAN (1u << 11)
101 /* Pattern tunnel Layer bits. */
102 #define MLX5_FLOW_LAYER_VXLAN (1u << 12)
103 #define MLX5_FLOW_LAYER_VXLAN_GPE (1u << 13)
104 #define MLX5_FLOW_LAYER_GRE (1u << 14)
105 #define MLX5_FLOW_LAYER_MPLS (1u << 15)
106 /* List of tunnel Layer bits continued below. */
108 /* General pattern items bits. */
109 #define MLX5_FLOW_ITEM_METADATA (1u << 16)
110 #define MLX5_FLOW_ITEM_PORT_ID (1u << 17)
111 #define MLX5_FLOW_ITEM_TAG (1u << 18)
112 #define MLX5_FLOW_ITEM_MARK (1u << 19)
114 /* Pattern MISC bits. */
115 #define MLX5_FLOW_LAYER_ICMP (1u << 20)
116 #define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
117 #define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
119 /* Pattern tunnel Layer bits (continued). */
120 #define MLX5_FLOW_LAYER_IPIP (1u << 23)
121 #define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
122 #define MLX5_FLOW_LAYER_NVGRE (1u << 25)
123 #define MLX5_FLOW_LAYER_GENEVE (1u << 26)
126 #define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
128 /* Pattern tunnel Layer bits (continued). */
129 #define MLX5_FLOW_LAYER_GTP (1u << 28)
131 /* Pattern eCPRI Layer bit. */
132 #define MLX5_FLOW_LAYER_ECPRI (UINT64_C(1) << 29)
134 /* IPv6 Fragment Extension Header bit. */
135 #define MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT (1u << 30)
136 #define MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT (1u << 31)
139 #define MLX5_FLOW_LAYER_OUTER_L3 \
140 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)
141 #define MLX5_FLOW_LAYER_OUTER_L4 \
142 (MLX5_FLOW_LAYER_OUTER_L4_UDP | MLX5_FLOW_LAYER_OUTER_L4_TCP)
143 #define MLX5_FLOW_LAYER_OUTER \
144 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_OUTER_L3 | \
145 MLX5_FLOW_LAYER_OUTER_L4)
148 #define MLX5_FLOW_LAYER_TUNNEL \
149 (MLX5_FLOW_LAYER_VXLAN | MLX5_FLOW_LAYER_VXLAN_GPE | \
150 MLX5_FLOW_LAYER_GRE | MLX5_FLOW_LAYER_NVGRE | MLX5_FLOW_LAYER_MPLS | \
151 MLX5_FLOW_LAYER_IPIP | MLX5_FLOW_LAYER_IPV6_ENCAP | \
152 MLX5_FLOW_LAYER_GENEVE | MLX5_FLOW_LAYER_GTP)
155 #define MLX5_FLOW_LAYER_INNER_L3 \
156 (MLX5_FLOW_LAYER_INNER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
157 #define MLX5_FLOW_LAYER_INNER_L4 \
158 (MLX5_FLOW_LAYER_INNER_L4_UDP | MLX5_FLOW_LAYER_INNER_L4_TCP)
159 #define MLX5_FLOW_LAYER_INNER \
160 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3 | \
161 MLX5_FLOW_LAYER_INNER_L4)
164 #define MLX5_FLOW_LAYER_L2 \
165 (MLX5_FLOW_LAYER_OUTER_L2 | MLX5_FLOW_LAYER_INNER_L2)
166 #define MLX5_FLOW_LAYER_L3_IPV4 \
167 (MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_INNER_L3_IPV4)
168 #define MLX5_FLOW_LAYER_L3_IPV6 \
169 (MLX5_FLOW_LAYER_OUTER_L3_IPV6 | MLX5_FLOW_LAYER_INNER_L3_IPV6)
170 #define MLX5_FLOW_LAYER_L3 \
171 (MLX5_FLOW_LAYER_L3_IPV4 | MLX5_FLOW_LAYER_L3_IPV6)
172 #define MLX5_FLOW_LAYER_L4 \
173 (MLX5_FLOW_LAYER_OUTER_L4 | MLX5_FLOW_LAYER_INNER_L4)
176 #define MLX5_FLOW_ACTION_DROP (1u << 0)
177 #define MLX5_FLOW_ACTION_QUEUE (1u << 1)
178 #define MLX5_FLOW_ACTION_RSS (1u << 2)
179 #define MLX5_FLOW_ACTION_FLAG (1u << 3)
180 #define MLX5_FLOW_ACTION_MARK (1u << 4)
181 #define MLX5_FLOW_ACTION_COUNT (1u << 5)
182 #define MLX5_FLOW_ACTION_PORT_ID (1u << 6)
183 #define MLX5_FLOW_ACTION_OF_POP_VLAN (1u << 7)
184 #define MLX5_FLOW_ACTION_OF_PUSH_VLAN (1u << 8)
185 #define MLX5_FLOW_ACTION_OF_SET_VLAN_VID (1u << 9)
186 #define MLX5_FLOW_ACTION_OF_SET_VLAN_PCP (1u << 10)
187 #define MLX5_FLOW_ACTION_SET_IPV4_SRC (1u << 11)
188 #define MLX5_FLOW_ACTION_SET_IPV4_DST (1u << 12)
189 #define MLX5_FLOW_ACTION_SET_IPV6_SRC (1u << 13)
190 #define MLX5_FLOW_ACTION_SET_IPV6_DST (1u << 14)
191 #define MLX5_FLOW_ACTION_SET_TP_SRC (1u << 15)
192 #define MLX5_FLOW_ACTION_SET_TP_DST (1u << 16)
193 #define MLX5_FLOW_ACTION_JUMP (1u << 17)
194 #define MLX5_FLOW_ACTION_SET_TTL (1u << 18)
195 #define MLX5_FLOW_ACTION_DEC_TTL (1u << 19)
196 #define MLX5_FLOW_ACTION_SET_MAC_SRC (1u << 20)
197 #define MLX5_FLOW_ACTION_SET_MAC_DST (1u << 21)
198 #define MLX5_FLOW_ACTION_ENCAP (1u << 22)
199 #define MLX5_FLOW_ACTION_DECAP (1u << 23)
200 #define MLX5_FLOW_ACTION_INC_TCP_SEQ (1u << 24)
201 #define MLX5_FLOW_ACTION_DEC_TCP_SEQ (1u << 25)
202 #define MLX5_FLOW_ACTION_INC_TCP_ACK (1u << 26)
203 #define MLX5_FLOW_ACTION_DEC_TCP_ACK (1u << 27)
204 #define MLX5_FLOW_ACTION_SET_TAG (1ull << 28)
205 #define MLX5_FLOW_ACTION_MARK_EXT (1ull << 29)
206 #define MLX5_FLOW_ACTION_SET_META (1ull << 30)
207 #define MLX5_FLOW_ACTION_METER (1ull << 31)
208 #define MLX5_FLOW_ACTION_SET_IPV4_DSCP (1ull << 32)
209 #define MLX5_FLOW_ACTION_SET_IPV6_DSCP (1ull << 33)
210 #define MLX5_FLOW_ACTION_AGE (1ull << 34)
211 #define MLX5_FLOW_ACTION_DEFAULT_MISS (1ull << 35)
212 #define MLX5_FLOW_ACTION_SAMPLE (1ull << 36)
213 #define MLX5_FLOW_ACTION_TUNNEL_SET (1ull << 37)
214 #define MLX5_FLOW_ACTION_TUNNEL_MATCH (1ull << 38)
216 #define MLX5_FLOW_FATE_ACTIONS \
217 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE | \
218 MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_JUMP | \
219 MLX5_FLOW_ACTION_DEFAULT_MISS)
221 #define MLX5_FLOW_FATE_ESWITCH_ACTIONS \
222 (MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_PORT_ID | \
223 MLX5_FLOW_ACTION_JUMP)
226 #define MLX5_FLOW_MODIFY_HDR_ACTIONS (MLX5_FLOW_ACTION_SET_IPV4_SRC | \
227 MLX5_FLOW_ACTION_SET_IPV4_DST | \
228 MLX5_FLOW_ACTION_SET_IPV6_SRC | \
229 MLX5_FLOW_ACTION_SET_IPV6_DST | \
230 MLX5_FLOW_ACTION_SET_TP_SRC | \
231 MLX5_FLOW_ACTION_SET_TP_DST | \
232 MLX5_FLOW_ACTION_SET_TTL | \
233 MLX5_FLOW_ACTION_DEC_TTL | \
234 MLX5_FLOW_ACTION_SET_MAC_SRC | \
235 MLX5_FLOW_ACTION_SET_MAC_DST | \
236 MLX5_FLOW_ACTION_INC_TCP_SEQ | \
237 MLX5_FLOW_ACTION_DEC_TCP_SEQ | \
238 MLX5_FLOW_ACTION_INC_TCP_ACK | \
239 MLX5_FLOW_ACTION_DEC_TCP_ACK | \
240 MLX5_FLOW_ACTION_OF_SET_VLAN_VID | \
241 MLX5_FLOW_ACTION_SET_TAG | \
242 MLX5_FLOW_ACTION_MARK_EXT | \
243 MLX5_FLOW_ACTION_SET_META | \
244 MLX5_FLOW_ACTION_SET_IPV4_DSCP | \
245 MLX5_FLOW_ACTION_SET_IPV6_DSCP)
247 #define MLX5_FLOW_VLAN_ACTIONS (MLX5_FLOW_ACTION_OF_POP_VLAN | \
248 MLX5_FLOW_ACTION_OF_PUSH_VLAN)
250 #define MLX5_FLOW_XCAP_ACTIONS (MLX5_FLOW_ACTION_ENCAP | MLX5_FLOW_ACTION_DECAP)
253 #define IPPROTO_MPLS 137
256 /* UDP port number for MPLS */
257 #define MLX5_UDP_PORT_MPLS 6635
259 /* UDP port numbers for VxLAN. */
260 #define MLX5_UDP_PORT_VXLAN 4789
261 #define MLX5_UDP_PORT_VXLAN_GPE 4790
263 /* UDP port numbers for GENEVE. */
264 #define MLX5_UDP_PORT_GENEVE 6081
266 /* Priority reserved for default flows. */
267 #define MLX5_FLOW_PRIO_RSVD ((uint32_t)-1)
270 * Number of sub priorities.
271 * For each kind of pattern matching i.e. L2, L3, L4 to have a correct
272 * matching on the NIC (firmware dependent) L4 most have the higher priority
273 * followed by L3 and ending with L2.
275 #define MLX5_PRIORITY_MAP_L2 2
276 #define MLX5_PRIORITY_MAP_L3 1
277 #define MLX5_PRIORITY_MAP_L4 0
278 #define MLX5_PRIORITY_MAP_MAX 3
280 /* Valid layer type for IPV4 RSS. */
281 #define MLX5_IPV4_LAYER_TYPES \
282 (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | \
283 ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_NONFRAG_IPV4_UDP | \
284 ETH_RSS_NONFRAG_IPV4_OTHER)
286 /* IBV hash source bits for IPV4. */
287 #define MLX5_IPV4_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
289 /* Valid layer type for IPV6 RSS. */
290 #define MLX5_IPV6_LAYER_TYPES \
291 (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | ETH_RSS_NONFRAG_IPV6_TCP | \
292 ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_IPV6_EX | ETH_RSS_IPV6_TCP_EX | \
293 ETH_RSS_IPV6_UDP_EX | ETH_RSS_NONFRAG_IPV6_OTHER)
295 /* IBV hash source bits for IPV6. */
296 #define MLX5_IPV6_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
298 /* IBV hash bits for L3 SRC. */
299 #define MLX5_L3_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_SRC_IPV6)
301 /* IBV hash bits for L3 DST. */
302 #define MLX5_L3_DST_IBV_RX_HASH (IBV_RX_HASH_DST_IPV4 | IBV_RX_HASH_DST_IPV6)
304 /* IBV hash bits for TCP. */
305 #define MLX5_TCP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
306 IBV_RX_HASH_DST_PORT_TCP)
308 /* IBV hash bits for UDP. */
309 #define MLX5_UDP_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_UDP | \
310 IBV_RX_HASH_DST_PORT_UDP)
312 /* IBV hash bits for L4 SRC. */
313 #define MLX5_L4_SRC_IBV_RX_HASH (IBV_RX_HASH_SRC_PORT_TCP | \
314 IBV_RX_HASH_SRC_PORT_UDP)
316 /* IBV hash bits for L4 DST. */
317 #define MLX5_L4_DST_IBV_RX_HASH (IBV_RX_HASH_DST_PORT_TCP | \
318 IBV_RX_HASH_DST_PORT_UDP)
320 /* Geneve header first 16Bit */
321 #define MLX5_GENEVE_VER_MASK 0x3
322 #define MLX5_GENEVE_VER_SHIFT 14
323 #define MLX5_GENEVE_VER_VAL(a) \
324 (((a) >> (MLX5_GENEVE_VER_SHIFT)) & (MLX5_GENEVE_VER_MASK))
325 #define MLX5_GENEVE_OPTLEN_MASK 0x3F
326 #define MLX5_GENEVE_OPTLEN_SHIFT 7
327 #define MLX5_GENEVE_OPTLEN_VAL(a) \
328 (((a) >> (MLX5_GENEVE_OPTLEN_SHIFT)) & (MLX5_GENEVE_OPTLEN_MASK))
329 #define MLX5_GENEVE_OAMF_MASK 0x1
330 #define MLX5_GENEVE_OAMF_SHIFT 7
331 #define MLX5_GENEVE_OAMF_VAL(a) \
332 (((a) >> (MLX5_GENEVE_OAMF_SHIFT)) & (MLX5_GENEVE_OAMF_MASK))
333 #define MLX5_GENEVE_CRITO_MASK 0x1
334 #define MLX5_GENEVE_CRITO_SHIFT 6
335 #define MLX5_GENEVE_CRITO_VAL(a) \
336 (((a) >> (MLX5_GENEVE_CRITO_SHIFT)) & (MLX5_GENEVE_CRITO_MASK))
337 #define MLX5_GENEVE_RSVD_MASK 0x3F
338 #define MLX5_GENEVE_RSVD_VAL(a) ((a) & (MLX5_GENEVE_RSVD_MASK))
340 * The length of the Geneve options fields, expressed in four byte multiples,
341 * not including the eight byte fixed tunnel.
343 #define MLX5_GENEVE_OPT_LEN_0 14
344 #define MLX5_GENEVE_OPT_LEN_1 63
346 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
347 sizeof(struct rte_flow_item_ipv4))
349 /* IPv4 fragment_offset field contains relevant data in bits 2 to 15. */
350 #define MLX5_IPV4_FRAG_OFFSET_MASK \
351 (RTE_IPV4_HDR_OFFSET_MASK | RTE_IPV4_HDR_MF_FLAG)
353 /* Specific item's fields can accept a range of values (using spec and last). */
354 #define MLX5_ITEM_RANGE_NOT_ACCEPTED false
355 #define MLX5_ITEM_RANGE_ACCEPTED true
357 /* Software header modify action numbers of a flow. */
358 #define MLX5_ACT_NUM_MDF_IPV4 1
359 #define MLX5_ACT_NUM_MDF_IPV6 4
360 #define MLX5_ACT_NUM_MDF_MAC 2
361 #define MLX5_ACT_NUM_MDF_VID 1
362 #define MLX5_ACT_NUM_MDF_PORT 2
363 #define MLX5_ACT_NUM_MDF_TTL 1
364 #define MLX5_ACT_NUM_DEC_TTL MLX5_ACT_NUM_MDF_TTL
365 #define MLX5_ACT_NUM_MDF_TCPSEQ 1
366 #define MLX5_ACT_NUM_MDF_TCPACK 1
367 #define MLX5_ACT_NUM_SET_REG 1
368 #define MLX5_ACT_NUM_SET_TAG 1
369 #define MLX5_ACT_NUM_CPY_MREG MLX5_ACT_NUM_SET_TAG
370 #define MLX5_ACT_NUM_SET_MARK MLX5_ACT_NUM_SET_TAG
371 #define MLX5_ACT_NUM_SET_META MLX5_ACT_NUM_SET_TAG
372 #define MLX5_ACT_NUM_SET_DSCP 1
374 enum mlx5_flow_drv_type {
377 MLX5_FLOW_TYPE_VERBS,
381 /* Fate action type. */
382 enum mlx5_flow_fate_type {
383 MLX5_FLOW_FATE_NONE, /* Egress flow. */
384 MLX5_FLOW_FATE_QUEUE,
386 MLX5_FLOW_FATE_PORT_ID,
388 MLX5_FLOW_FATE_DEFAULT_MISS,
392 /* Matcher PRM representation */
393 struct mlx5_flow_dv_match_params {
395 /**< Size of match value. Do NOT split size and key! */
396 uint32_t buf[MLX5_ST_SZ_DW(fte_match_param)];
397 /**< Matcher value. This value is used as the mask or as a key. */
400 /* Matcher structure. */
401 struct mlx5_flow_dv_matcher {
402 struct mlx5_cache_entry entry; /**< Pointer to the next element. */
403 struct mlx5_flow_tbl_resource *tbl;
404 /**< Pointer to the table(group) the matcher associated with. */
405 void *matcher_object; /**< Pointer to DV matcher */
406 uint16_t crc; /**< CRC of key. */
407 uint16_t priority; /**< Priority of matcher. */
408 struct mlx5_flow_dv_match_params mask; /**< Matcher mask. */
411 #define MLX5_ENCAP_MAX_LEN 132
413 /* Encap/decap resource key of the hash organization. */
414 union mlx5_flow_encap_decap_key {
416 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
417 uint32_t refmt_type:8; /**< Header reformat type. */
418 uint32_t buf_size:8; /**< Encap buf size. */
419 uint32_t table_level:8; /**< Root table or not. */
420 uint32_t cksum; /**< Encap buf check sum. */
422 uint64_t v64; /**< full 64bits value of key */
425 /* Encap/decap resource structure. */
426 struct mlx5_flow_dv_encap_decap_resource {
427 struct mlx5_hlist_entry entry;
428 /* Pointer to next element. */
429 uint32_t refcnt; /**< Reference counter. */
431 /**< Encap/decap action object. */
432 uint8_t buf[MLX5_ENCAP_MAX_LEN];
434 uint8_t reformat_type;
436 uint64_t flags; /**< Flags for RDMA API. */
437 uint32_t idx; /**< Index for the index memory pool. */
440 /* Tag resource structure. */
441 struct mlx5_flow_dv_tag_resource {
442 struct mlx5_hlist_entry entry;
443 /**< hash list entry for tag resource, tag value as the key. */
445 /**< Tag action object. */
446 uint32_t refcnt; /**< Reference counter. */
447 uint32_t idx; /**< Index for the index memory pool. */
451 * Number of modification commands.
452 * The maximal actions amount in FW is some constant, and it is 16 in the
453 * latest releases. In some old releases, it will be limited to 8.
454 * Since there is no interface to query the capacity, the maximal value should
455 * be used to allow PMD to create the flow. The validation will be done in the
456 * lower driver layer or FW. A failure will be returned if exceeds the maximal
457 * supported actions number on the root table.
458 * On non-root tables, there is no limitation, but 32 is enough right now.
460 #define MLX5_MAX_MODIFY_NUM 32
461 #define MLX5_ROOT_TBL_MODIFY_NUM 16
463 /* Modify resource structure */
464 struct mlx5_flow_dv_modify_hdr_resource {
465 struct mlx5_hlist_entry entry;
466 void *action; /**< Modify header action object. */
467 /* Key area for hash list matching: */
468 uint8_t ft_type; /**< Flow table type, Rx or Tx. */
469 uint32_t actions_num; /**< Number of modification actions. */
470 uint64_t flags; /**< Flags for RDMA API. */
471 struct mlx5_modification_cmd actions[];
472 /**< Modification actions. */
475 /* Modify resource key of the hash organization. */
476 union mlx5_flow_modify_hdr_key {
478 uint32_t ft_type:8; /**< Flow table type, Rx or Tx. */
479 uint32_t actions_num:5; /**< Number of modification actions. */
480 uint32_t group:19; /**< Flow group id. */
481 uint32_t cksum; /**< Actions check sum. */
483 uint64_t v64; /**< full 64bits value of key */
486 /* Jump action resource structure. */
487 struct mlx5_flow_dv_jump_tbl_resource {
488 void *action; /**< Pointer to the rdma core action. */
491 /* Port ID resource structure. */
492 struct mlx5_flow_dv_port_id_action_resource {
493 struct mlx5_cache_entry entry;
494 void *action; /**< Action object. */
495 uint32_t port_id; /**< Port ID value. */
496 uint32_t idx; /**< Indexed pool memory index. */
499 /* Push VLAN action resource structure */
500 struct mlx5_flow_dv_push_vlan_action_resource {
501 struct mlx5_cache_entry entry; /* Cache entry. */
502 void *action; /**< Action object. */
503 uint8_t ft_type; /**< Flow table type, Rx, Tx or FDB. */
504 rte_be32_t vlan_tag; /**< VLAN tag value. */
505 uint32_t idx; /**< Indexed pool memory index. */
508 /* Metadata register copy table entry. */
509 struct mlx5_flow_mreg_copy_resource {
511 * Hash list entry for copy table.
512 * - Key is 32/64-bit MARK action ID.
513 * - MUST be the first entry.
515 struct mlx5_hlist_entry hlist_ent;
516 LIST_ENTRY(mlx5_flow_mreg_copy_resource) next;
517 /* List entry for device flows. */
519 uint32_t rix_flow; /* Built flow for copy. */
522 /* Table tunnel parameter. */
523 struct mlx5_flow_tbl_tunnel_prm {
524 const struct mlx5_flow_tunnel *tunnel;
529 /* Table data structure of the hash organization. */
530 struct mlx5_flow_tbl_data_entry {
531 struct mlx5_hlist_entry entry;
532 /**< hash list entry, 64-bits key inside. */
533 struct mlx5_flow_tbl_resource tbl;
534 /**< flow table resource. */
535 struct mlx5_cache_list matchers;
536 /**< matchers' header associated with the flow table. */
537 struct mlx5_flow_dv_jump_tbl_resource jump;
538 /**< jump resource, at most one for each table created. */
539 uint32_t idx; /**< index for the indexed mempool. */
540 /**< tunnel offload */
541 const struct mlx5_flow_tunnel *tunnel;
544 bool tunnel_offload; /* Tunnel offlod table or not. */
545 bool is_egress; /**< Egress table. */
548 /* Sub rdma-core actions list. */
549 struct mlx5_flow_sub_actions_list {
550 uint32_t actions_num; /**< Number of sample actions. */
551 uint64_t action_flags;
552 void *dr_queue_action;
555 void *dr_port_id_action;
556 void *dr_encap_action;
559 /* Sample sub-actions resource list. */
560 struct mlx5_flow_sub_actions_idx {
561 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
562 uint32_t rix_tag; /**< Index to the tag action. */
564 uint32_t rix_port_id_action; /**< Index to port ID action resource. */
565 uint32_t rix_encap_decap; /**< Index to encap/decap resource. */
568 /* Sample action resource structure. */
569 struct mlx5_flow_dv_sample_resource {
570 struct mlx5_cache_entry entry; /**< Cache entry. */
572 void *verbs_action; /**< Verbs sample action object. */
573 void **sub_actions; /**< Sample sub-action array. */
575 uint32_t idx; /** Sample object index. */
576 uint8_t ft_type; /** Flow Table Type */
577 uint32_t ft_id; /** Flow Table Level */
578 uint32_t ratio; /** Sample Ratio */
579 uint64_t set_action; /** Restore reg_c0 value */
580 void *normal_path_tbl; /** Flow Table pointer */
581 void *default_miss; /** default_miss dr_action. */
582 struct mlx5_flow_sub_actions_idx sample_idx;
583 /**< Action index resources. */
584 struct mlx5_flow_sub_actions_list sample_act;
585 /**< Action resources. */
588 #define MLX5_MAX_DEST_NUM 2
590 /* Destination array action resource structure. */
591 struct mlx5_flow_dv_dest_array_resource {
592 struct mlx5_cache_entry entry; /**< Cache entry. */
593 uint32_t idx; /** Destination array action object index. */
594 uint8_t ft_type; /** Flow Table Type */
595 uint8_t num_of_dest; /**< Number of destination actions. */
596 void *action; /**< Pointer to the rdma core action. */
597 struct mlx5_flow_sub_actions_idx sample_idx[MLX5_MAX_DEST_NUM];
598 /**< Action index resources. */
599 struct mlx5_flow_sub_actions_list sample_act[MLX5_MAX_DEST_NUM];
600 /**< Action resources. */
603 /* Verbs specification header. */
604 struct ibv_spec_header {
605 enum ibv_flow_spec_type type;
609 /* PMD flow priority for tunnel */
610 #define MLX5_TUNNEL_PRIO_GET(rss_desc) \
611 ((rss_desc)->level >= 2 ? MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4)
614 /** Device flow handle structure for DV mode only. */
615 struct mlx5_flow_handle_dv {
617 struct mlx5_flow_dv_matcher *matcher; /**< Cache to matcher. */
618 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr;
619 /**< Pointer to modify header resource in cache. */
620 uint32_t rix_encap_decap;
621 /**< Index to encap/decap resource in cache. */
622 uint32_t rix_push_vlan;
623 /**< Index to push VLAN action resource in cache. */
625 /**< Index to the tag action. */
627 /**< Index to sample action resource in cache. */
628 uint32_t rix_dest_array;
629 /**< Index to destination array resource in cache. */
632 /** Device flow handle structure: used both for creating & destroying. */
633 struct mlx5_flow_handle {
634 SILIST_ENTRY(uint32_t)next;
635 struct mlx5_vf_vlan vf_vlan; /**< Structure for VF VLAN workaround. */
636 /**< Index to next device flow handle. */
638 /**< Bit-fields of present layers, see MLX5_FLOW_LAYER_*. */
639 void *drv_flow; /**< pointer to driver flow object. */
640 uint32_t split_flow_id:28; /**< Sub flow unique match flow id. */
641 uint32_t mark:1; /**< Metadate rxq mark flag. */
642 uint32_t fate_action:3; /**< Fate action type. */
644 uint32_t rix_hrxq; /**< Hash Rx queue object index. */
645 uint32_t rix_jump; /**< Index to the jump action resource. */
646 uint32_t rix_port_id_action;
647 /**< Index to port ID action resource. */
649 /**< Generic value indicates the fate action. */
650 uint32_t rix_default_fate;
651 /**< Indicates default miss fate action. */
653 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
654 struct mlx5_flow_handle_dv dvh;
659 * Size for Verbs device flow handle structure only. Do not use the DV only
660 * structure in Verbs. No DV flows attributes will be accessed.
661 * Macro offsetof() could also be used here.
663 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
664 #define MLX5_FLOW_HANDLE_VERBS_SIZE \
665 (sizeof(struct mlx5_flow_handle) - sizeof(struct mlx5_flow_handle_dv))
667 #define MLX5_FLOW_HANDLE_VERBS_SIZE (sizeof(struct mlx5_flow_handle))
671 * Max number of actions per DV flow.
672 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED
673 * in rdma-core file providers/mlx5/verbs.c.
675 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8
677 /** Device flow structure only for DV flow creation. */
678 struct mlx5_flow_dv_workspace {
679 uint32_t group; /**< The group index. */
680 uint8_t transfer; /**< 1 if the flow is E-Switch flow. */
681 int actions_n; /**< number of actions. */
682 void *actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; /**< Action list. */
683 struct mlx5_flow_dv_encap_decap_resource *encap_decap;
684 /**< Pointer to encap/decap resource in cache. */
685 struct mlx5_flow_dv_push_vlan_action_resource *push_vlan_res;
686 /**< Pointer to push VLAN action resource in cache. */
687 struct mlx5_flow_dv_tag_resource *tag_resource;
688 /**< pointer to the tag action. */
689 struct mlx5_flow_dv_port_id_action_resource *port_id_action;
690 /**< Pointer to port ID action resource. */
691 struct mlx5_flow_dv_jump_tbl_resource *jump;
692 /**< Pointer to the jump action resource. */
693 struct mlx5_flow_dv_match_params value;
694 /**< Holds the value that the packet is compared to. */
695 struct mlx5_flow_dv_sample_resource *sample_res;
696 /**< Pointer to the sample action resource. */
697 struct mlx5_flow_dv_dest_array_resource *dest_array_res;
698 /**< Pointer to the destination array resource. */
702 * Maximal Verbs flow specifications & actions size.
703 * Some elements are mutually exclusive, but enough space should be allocated.
704 * Tunnel cases: 1. Max 2 Ethernet + IP(v6 len > v4 len) + TCP/UDP headers.
705 * 2. One tunnel header (exception: GRE + MPLS),
706 * SPEC length: GRE == tunnel.
707 * Actions: 1. 1 Mark OR Flag.
708 * 2. 1 Drop (if any).
709 * 3. No limitation for counters, but it makes no sense to support too
710 * many counters in a single device flow.
712 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
713 #define MLX5_VERBS_MAX_SPEC_SIZE \
715 (2 * (sizeof(struct ibv_flow_spec_eth) + \
716 sizeof(struct ibv_flow_spec_ipv6) + \
717 sizeof(struct ibv_flow_spec_tcp_udp)) + \
718 sizeof(struct ibv_flow_spec_gre) + \
719 sizeof(struct ibv_flow_spec_mpls)) \
722 #define MLX5_VERBS_MAX_SPEC_SIZE \
724 (2 * (sizeof(struct ibv_flow_spec_eth) + \
725 sizeof(struct ibv_flow_spec_ipv6) + \
726 sizeof(struct ibv_flow_spec_tcp_udp)) + \
727 sizeof(struct ibv_flow_spec_tunnel)) \
731 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) || \
732 defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
733 #define MLX5_VERBS_MAX_ACT_SIZE \
735 sizeof(struct ibv_flow_spec_action_tag) + \
736 sizeof(struct ibv_flow_spec_action_drop) + \
737 sizeof(struct ibv_flow_spec_counter_action) * 4 \
740 #define MLX5_VERBS_MAX_ACT_SIZE \
742 sizeof(struct ibv_flow_spec_action_tag) + \
743 sizeof(struct ibv_flow_spec_action_drop) \
747 #define MLX5_VERBS_MAX_SPEC_ACT_SIZE \
748 (MLX5_VERBS_MAX_SPEC_SIZE + MLX5_VERBS_MAX_ACT_SIZE)
750 /** Device flow structure only for Verbs flow creation. */
751 struct mlx5_flow_verbs_workspace {
752 unsigned int size; /**< Size of the attribute. */
753 struct ibv_flow_attr attr; /**< Verbs flow attribute buffer. */
754 uint8_t specs[MLX5_VERBS_MAX_SPEC_ACT_SIZE];
755 /**< Specifications & actions buffer of verbs flow. */
758 /** Maximal number of device sub-flows supported. */
759 #define MLX5_NUM_MAX_DEV_FLOWS 32
761 /** Device flow structure. */
763 struct rte_flow *flow; /**< Pointer to the main flow. */
764 uint32_t flow_idx; /**< The memory pool index to the main flow. */
765 uint64_t hash_fields; /**< Hash Rx queue hash fields. */
767 /**< Bit-fields of detected actions, see MLX5_FLOW_ACTION_*. */
768 bool external; /**< true if the flow is created external to PMD. */
769 uint8_t ingress; /**< 1 if the flow is ingress. */
771 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
772 struct mlx5_flow_dv_workspace dv;
774 struct mlx5_flow_verbs_workspace verbs;
776 struct mlx5_flow_handle *handle;
777 uint32_t handle_idx; /* Index of the mlx5 flow handle memory. */
778 const struct mlx5_flow_tunnel *tunnel;
781 /* Flow meter state. */
782 #define MLX5_FLOW_METER_DISABLE 0
783 #define MLX5_FLOW_METER_ENABLE 1
785 #define MLX5_MAN_WIDTH 8
786 /* Modify this value if enum rte_mtr_color changes. */
787 #define RTE_MTR_DROPPED RTE_COLORS
789 /* Meter policer statistics */
790 struct mlx5_flow_policer_stats {
791 uint32_t cnt[RTE_COLORS + 1];
792 /**< Color counter, extra for drop. */
794 /**< Statistics mask for the colors. */
797 /* Meter table structure. */
798 struct mlx5_meter_domain_info {
799 struct mlx5_flow_tbl_resource *tbl;
801 struct mlx5_flow_tbl_resource *sfx_tbl;
802 /**< Meter suffix table. */
804 /**< Meter color not match default criteria. */
806 /**< Meter color match criteria. */
808 /**< Meter match action. */
809 void *policer_rules[RTE_MTR_DROPPED + 1];
810 /**< Meter policer for the match. */
813 /* Meter table set for TX RX FDB. */
814 struct mlx5_meter_domains_infos {
816 /**< Table user count. */
817 struct mlx5_meter_domain_info egress;
818 /**< TX meter table. */
819 struct mlx5_meter_domain_info ingress;
820 /**< RX meter table. */
821 struct mlx5_meter_domain_info transfer;
822 /**< FDB meter table. */
824 /**< Drop action as not matched. */
825 void *count_actns[RTE_MTR_DROPPED + 1];
826 /**< Counters for match and unmatched statistics. */
827 uint32_t fmp[MLX5_ST_SZ_DW(flow_meter_parameters)];
828 /**< Flow meter parameter. */
830 /**< Flow meter parameter size. */
832 /**< Flow meter action. */
835 /* Meter parameter structure. */
836 struct mlx5_flow_meter {
837 TAILQ_ENTRY(mlx5_flow_meter) next;
838 /**< Pointer to the next flow meter structure. */
839 uint32_t idx; /* Index to meter object. */
842 struct mlx5_flow_meter_profile *profile;
843 /**< Meter profile parameters. */
845 rte_spinlock_t sl; /**< Meter action spinlock. */
847 /** Policer actions (per meter output color). */
848 enum rte_mtr_policer_action action[RTE_COLORS];
850 /** Set of stats counters to be enabled.
851 * @see enum rte_mtr_stats_type
855 /**< Rule applies to ingress traffic. */
858 /**< Rule applies to egress traffic. */
861 * Instead of simply matching the properties of traffic as it would
862 * appear on a given DPDK port ID, enabling this attribute transfers
863 * a flow rule to the lowest possible level of any device endpoints
864 * found in the pattern.
866 * When supported, this effectively enables an application to
867 * re-route traffic not necessarily intended for it (e.g. coming
868 * from or addressed to different physical ports, VFs or
869 * applications) at the device level.
871 * It complements the behavior of some pattern items such as
872 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them.
874 * When transferring flow rules, ingress and egress attributes keep
875 * their original meaning, as if processing traffic emitted or
876 * received by the application.
879 struct mlx5_meter_domains_infos *mfts;
880 /**< Flow table created for this meter. */
881 struct mlx5_flow_policer_stats policer_stats;
882 /**< Meter policer statistics. */
885 uint32_t active_state:1;
888 /**< Meter shared or not. */
891 /* RFC2697 parameter structure. */
892 struct mlx5_flow_meter_srtcm_rfc2697_prm {
893 /* green_saturation_value = cbs_mantissa * 2^cbs_exponent */
894 uint32_t cbs_exponent:5;
895 uint32_t cbs_mantissa:8;
896 /* cir = 8G * cir_mantissa * 1/(2^cir_exponent) Bytes/Sec */
897 uint32_t cir_exponent:5;
898 uint32_t cir_mantissa:8;
899 /* yellow _saturation_value = ebs_mantissa * 2^ebs_exponent */
900 uint32_t ebs_exponent:5;
901 uint32_t ebs_mantissa:8;
904 /* Flow meter profile structure. */
905 struct mlx5_flow_meter_profile {
906 TAILQ_ENTRY(mlx5_flow_meter_profile) next;
907 /**< Pointer to the next flow meter structure. */
908 uint32_t meter_profile_id; /**< Profile id. */
909 struct rte_mtr_meter_profile profile; /**< Profile detail. */
911 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm;
912 /**< srtcm_rfc2697 struct. */
914 uint32_t ref_cnt; /**< Use count. */
917 #define MLX5_MAX_TUNNELS 256
918 #define MLX5_TNL_MISS_RULE_PRIORITY 3
919 #define MLX5_TNL_MISS_FDB_JUMP_GRP 0x1234faac
922 * When tunnel offload is active, all JUMP group ids are converted
923 * using the same method. That conversion is applied both to tunnel and
924 * regular rule types.
925 * Group ids used in tunnel rules are relative to it's tunnel (!).
926 * Application can create number of steer rules, using the same
927 * tunnel, with different group id in each rule.
928 * Each tunnel stores its groups internally in PMD tunnel object.
929 * Groups used in regular rules do not belong to any tunnel and are stored
933 struct mlx5_flow_tunnel {
934 LIST_ENTRY(mlx5_flow_tunnel) chain;
935 struct rte_flow_tunnel app_tunnel; /** app tunnel copy */
936 uint32_t tunnel_id; /** unique tunnel ID */
938 struct rte_flow_action action;
939 struct rte_flow_item item;
940 struct mlx5_hlist *groups; /** tunnel groups */
943 /** PMD tunnel related context */
944 struct mlx5_flow_tunnel_hub {
945 LIST_HEAD(, mlx5_flow_tunnel) tunnels;
946 rte_spinlock_t sl; /* Tunnel list spinlock. */
947 struct mlx5_hlist *groups; /** non tunnel groups */
950 /* convert jump group to flow table ID in tunnel rules */
951 struct tunnel_tbl_entry {
952 struct mlx5_hlist_entry hash;
956 static inline uint32_t
957 tunnel_id_to_flow_tbl(uint32_t id)
959 return id | (1u << 16);
962 static inline uint32_t
963 tunnel_flow_tbl_to_id(uint32_t flow_tbl)
965 return flow_tbl & ~(1u << 16);
968 union tunnel_tbl_key {
976 static inline struct mlx5_flow_tunnel_hub *
977 mlx5_tunnel_hub(struct rte_eth_dev *dev)
979 struct mlx5_priv *priv = dev->data->dev_private;
980 return priv->sh->tunnel_hub;
984 is_tunnel_offload_active(struct rte_eth_dev *dev)
986 struct mlx5_priv *priv = dev->data->dev_private;
987 return !!priv->config.dv_miss_info;
991 is_flow_tunnel_match_rule(__rte_unused struct rte_eth_dev *dev,
992 __rte_unused const struct rte_flow_attr *attr,
993 __rte_unused const struct rte_flow_item items[],
994 __rte_unused const struct rte_flow_action actions[])
996 return (items[0].type == (typeof(items[0].type))
997 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL);
1001 is_flow_tunnel_steer_rule(__rte_unused struct rte_eth_dev *dev,
1002 __rte_unused const struct rte_flow_attr *attr,
1003 __rte_unused const struct rte_flow_item items[],
1004 __rte_unused const struct rte_flow_action actions[])
1006 return (actions[0].type == (typeof(actions[0].type))
1007 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET);
1010 static inline const struct mlx5_flow_tunnel *
1011 flow_actions_to_tunnel(const struct rte_flow_action actions[])
1013 return actions[0].conf;
1016 static inline const struct mlx5_flow_tunnel *
1017 flow_items_to_tunnel(const struct rte_flow_item items[])
1019 return items[0].spec;
1022 /* Flow structure. */
1024 ILIST_ENTRY(uint32_t)next; /**< Index to the next flow structure. */
1025 uint32_t shared_rss; /** < Shared RSS action ID. */
1026 uint32_t dev_handles;
1027 /**< Device flow handles that are part of the flow. */
1028 uint32_t drv_type:2; /**< Driver type. */
1030 uint32_t meter:16; /**< Holds flow meter id. */
1031 uint32_t rix_mreg_copy;
1032 /**< Index to metadata register copy table resource. */
1033 uint32_t counter; /**< Holds flow counter. */
1034 uint32_t tunnel_id; /**< Tunnel id */
1035 uint32_t age; /**< Holds ASO age bit index. */
1039 * Define list of valid combinations of RX Hash fields
1040 * (see enum ibv_rx_hash_fields).
1042 #define MLX5_RSS_HASH_IPV4 (IBV_RX_HASH_SRC_IPV4 | IBV_RX_HASH_DST_IPV4)
1043 #define MLX5_RSS_HASH_IPV4_TCP \
1044 (MLX5_RSS_HASH_IPV4 | \
1045 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1046 #define MLX5_RSS_HASH_IPV4_UDP \
1047 (MLX5_RSS_HASH_IPV4 | \
1048 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1049 #define MLX5_RSS_HASH_IPV6 (IBV_RX_HASH_SRC_IPV6 | IBV_RX_HASH_DST_IPV6)
1050 #define MLX5_RSS_HASH_IPV6_TCP \
1051 (MLX5_RSS_HASH_IPV6 | \
1052 IBV_RX_HASH_SRC_PORT_TCP | IBV_RX_HASH_SRC_PORT_TCP)
1053 #define MLX5_RSS_HASH_IPV6_UDP \
1054 (MLX5_RSS_HASH_IPV6 | \
1055 IBV_RX_HASH_SRC_PORT_UDP | IBV_RX_HASH_SRC_PORT_UDP)
1056 #define MLX5_RSS_HASH_NONE 0ULL
1058 /* array of valid combinations of RX Hash fields for RSS */
1059 static const uint64_t mlx5_rss_hash_fields[] = {
1061 MLX5_RSS_HASH_IPV4_TCP,
1062 MLX5_RSS_HASH_IPV4_UDP,
1064 MLX5_RSS_HASH_IPV6_TCP,
1065 MLX5_RSS_HASH_IPV6_UDP,
1069 /* Shared RSS action structure */
1070 struct mlx5_shared_action_rss {
1071 ILIST_ENTRY(uint32_t)next; /**< Index to the next RSS structure. */
1072 uint32_t refcnt; /**< Atomically accessed refcnt. */
1073 struct rte_flow_action_rss origin; /**< Original rte RSS action. */
1074 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */
1075 uint16_t *queue; /**< Queue indices to use. */
1076 uint32_t hrxq[MLX5_RSS_HASH_FIELDS_LEN];
1077 /**< Hash RX queue indexes mapped to mlx5_rss_hash_fields */
1078 uint32_t hrxq_tunnel[MLX5_RSS_HASH_FIELDS_LEN];
1079 /**< Hash RX queue indexes for tunneled RSS */
1082 struct rte_flow_shared_action {
1086 /* Thread specific flow workspace intermediate data. */
1087 struct mlx5_flow_workspace {
1088 struct mlx5_flow flows[MLX5_NUM_MAX_DEV_FLOWS];
1089 struct mlx5_flow_rss_desc rss_desc[2];
1090 uint32_t rssq_num[2]; /* Allocated queue num in rss_desc. */
1091 int flow_idx; /* Intermediate device flow index. */
1092 int flow_nested_idx; /* Intermediate device flow index, nested. */
1095 typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,
1096 const struct rte_flow_attr *attr,
1097 const struct rte_flow_item items[],
1098 const struct rte_flow_action actions[],
1101 struct rte_flow_error *error);
1102 typedef struct mlx5_flow *(*mlx5_flow_prepare_t)
1103 (struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
1104 const struct rte_flow_item items[],
1105 const struct rte_flow_action actions[], struct rte_flow_error *error);
1106 typedef int (*mlx5_flow_translate_t)(struct rte_eth_dev *dev,
1107 struct mlx5_flow *dev_flow,
1108 const struct rte_flow_attr *attr,
1109 const struct rte_flow_item items[],
1110 const struct rte_flow_action actions[],
1111 struct rte_flow_error *error);
1112 typedef int (*mlx5_flow_apply_t)(struct rte_eth_dev *dev, struct rte_flow *flow,
1113 struct rte_flow_error *error);
1114 typedef void (*mlx5_flow_remove_t)(struct rte_eth_dev *dev,
1115 struct rte_flow *flow);
1116 typedef void (*mlx5_flow_destroy_t)(struct rte_eth_dev *dev,
1117 struct rte_flow *flow);
1118 typedef int (*mlx5_flow_query_t)(struct rte_eth_dev *dev,
1119 struct rte_flow *flow,
1120 const struct rte_flow_action *actions,
1122 struct rte_flow_error *error);
1123 typedef struct mlx5_meter_domains_infos *(*mlx5_flow_create_mtr_tbls_t)
1124 (struct rte_eth_dev *dev,
1125 const struct mlx5_flow_meter *fm);
1126 typedef int (*mlx5_flow_destroy_mtr_tbls_t)(struct rte_eth_dev *dev,
1127 struct mlx5_meter_domains_infos *tbls);
1128 typedef int (*mlx5_flow_create_policer_rules_t)
1129 (struct rte_eth_dev *dev,
1130 struct mlx5_flow_meter *fm,
1131 const struct rte_flow_attr *attr);
1132 typedef int (*mlx5_flow_destroy_policer_rules_t)
1133 (struct rte_eth_dev *dev,
1134 const struct mlx5_flow_meter *fm,
1135 const struct rte_flow_attr *attr);
1136 typedef uint32_t (*mlx5_flow_counter_alloc_t)
1137 (struct rte_eth_dev *dev);
1138 typedef void (*mlx5_flow_counter_free_t)(struct rte_eth_dev *dev,
1140 typedef int (*mlx5_flow_counter_query_t)(struct rte_eth_dev *dev,
1142 bool clear, uint64_t *pkts,
1144 typedef int (*mlx5_flow_get_aged_flows_t)
1145 (struct rte_eth_dev *dev,
1147 uint32_t nb_contexts,
1148 struct rte_flow_error *error);
1149 typedef int (*mlx5_flow_action_validate_t)
1150 (struct rte_eth_dev *dev,
1151 const struct rte_flow_shared_action_conf *conf,
1152 const struct rte_flow_action *action,
1153 struct rte_flow_error *error);
1154 typedef struct rte_flow_shared_action *(*mlx5_flow_action_create_t)
1155 (struct rte_eth_dev *dev,
1156 const struct rte_flow_shared_action_conf *conf,
1157 const struct rte_flow_action *action,
1158 struct rte_flow_error *error);
1159 typedef int (*mlx5_flow_action_destroy_t)
1160 (struct rte_eth_dev *dev,
1161 struct rte_flow_shared_action *action,
1162 struct rte_flow_error *error);
1163 typedef int (*mlx5_flow_action_update_t)
1164 (struct rte_eth_dev *dev,
1165 struct rte_flow_shared_action *action,
1166 const void *action_conf,
1167 struct rte_flow_error *error);
1168 typedef int (*mlx5_flow_sync_domain_t)
1169 (struct rte_eth_dev *dev,
1172 struct mlx5_flow_driver_ops {
1173 mlx5_flow_validate_t validate;
1174 mlx5_flow_prepare_t prepare;
1175 mlx5_flow_translate_t translate;
1176 mlx5_flow_apply_t apply;
1177 mlx5_flow_remove_t remove;
1178 mlx5_flow_destroy_t destroy;
1179 mlx5_flow_query_t query;
1180 mlx5_flow_create_mtr_tbls_t create_mtr_tbls;
1181 mlx5_flow_destroy_mtr_tbls_t destroy_mtr_tbls;
1182 mlx5_flow_create_policer_rules_t create_policer_rules;
1183 mlx5_flow_destroy_policer_rules_t destroy_policer_rules;
1184 mlx5_flow_counter_alloc_t counter_alloc;
1185 mlx5_flow_counter_free_t counter_free;
1186 mlx5_flow_counter_query_t counter_query;
1187 mlx5_flow_get_aged_flows_t get_aged_flows;
1188 mlx5_flow_action_validate_t action_validate;
1189 mlx5_flow_action_create_t action_create;
1190 mlx5_flow_action_destroy_t action_destroy;
1191 mlx5_flow_action_update_t action_update;
1192 mlx5_flow_sync_domain_t sync_domain;
1197 struct mlx5_flow_workspace *mlx5_flow_get_thread_workspace(void);
1199 struct flow_grp_info {
1200 uint64_t external:1;
1201 uint64_t transfer:1;
1202 uint64_t fdb_def_rule:1;
1203 /* force standard group translation */
1204 uint64_t std_tbl_fix:1;
1208 tunnel_use_standard_attr_group_translate
1209 (struct rte_eth_dev *dev,
1210 const struct mlx5_flow_tunnel *tunnel,
1211 const struct rte_flow_attr *attr,
1212 const struct rte_flow_item items[],
1213 const struct rte_flow_action actions[])
1217 if (!is_tunnel_offload_active(dev))
1218 /* no tunnel offload API */
1222 * OvS will use jump to group 0 in tunnel steer rule.
1223 * If tunnel steer rule starts from group 0 (attr.group == 0)
1224 * that 0 group must be translated with standard method.
1225 * attr.group == 0 in tunnel match rule translated with tunnel
1228 verdict = !attr->group &&
1229 is_flow_tunnel_steer_rule(dev, attr, items, actions);
1232 * non-tunnel group translation uses standard method for
1233 * root group only: attr.group == 0
1235 verdict = !attr->group;
1241 int mlx5_flow_group_to_table(struct rte_eth_dev *dev,
1242 const struct mlx5_flow_tunnel *tunnel,
1243 uint32_t group, uint32_t *table,
1244 struct flow_grp_info flags,
1245 struct rte_flow_error *error);
1246 uint64_t mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc,
1247 int tunnel, uint64_t layer_types,
1248 uint64_t hash_fields);
1249 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev);
1250 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,
1251 uint32_t subpriority);
1252 int mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
1253 enum mlx5_feature_name feature,
1255 struct rte_flow_error *error);
1256 const struct rte_flow_action *mlx5_flow_find_action
1257 (const struct rte_flow_action *actions,
1258 enum rte_flow_action_type action);
1259 int mlx5_validate_action_rss(struct rte_eth_dev *dev,
1260 const struct rte_flow_action *action,
1261 struct rte_flow_error *error);
1262 int mlx5_flow_validate_action_count(struct rte_eth_dev *dev,
1263 const struct rte_flow_attr *attr,
1264 struct rte_flow_error *error);
1265 int mlx5_flow_validate_action_drop(uint64_t action_flags,
1266 const struct rte_flow_attr *attr,
1267 struct rte_flow_error *error);
1268 int mlx5_flow_validate_action_flag(uint64_t action_flags,
1269 const struct rte_flow_attr *attr,
1270 struct rte_flow_error *error);
1271 int mlx5_flow_validate_action_mark(const struct rte_flow_action *action,
1272 uint64_t action_flags,
1273 const struct rte_flow_attr *attr,
1274 struct rte_flow_error *error);
1275 int mlx5_flow_validate_action_queue(const struct rte_flow_action *action,
1276 uint64_t action_flags,
1277 struct rte_eth_dev *dev,
1278 const struct rte_flow_attr *attr,
1279 struct rte_flow_error *error);
1280 int mlx5_flow_validate_action_rss(const struct rte_flow_action *action,
1281 uint64_t action_flags,
1282 struct rte_eth_dev *dev,
1283 const struct rte_flow_attr *attr,
1284 uint64_t item_flags,
1285 struct rte_flow_error *error);
1286 int mlx5_flow_validate_action_default_miss(uint64_t action_flags,
1287 const struct rte_flow_attr *attr,
1288 struct rte_flow_error *error);
1289 int mlx5_flow_validate_attributes(struct rte_eth_dev *dev,
1290 const struct rte_flow_attr *attributes,
1291 struct rte_flow_error *error);
1292 int mlx5_flow_item_acceptable(const struct rte_flow_item *item,
1293 const uint8_t *mask,
1294 const uint8_t *nic_mask,
1296 bool range_accepted,
1297 struct rte_flow_error *error);
1298 int mlx5_flow_validate_item_eth(const struct rte_flow_item *item,
1299 uint64_t item_flags, bool ext_vlan_sup,
1300 struct rte_flow_error *error);
1301 int mlx5_flow_validate_item_gre(const struct rte_flow_item *item,
1302 uint64_t item_flags,
1303 uint8_t target_protocol,
1304 struct rte_flow_error *error);
1305 int mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item,
1306 uint64_t item_flags,
1307 const struct rte_flow_item *gre_item,
1308 struct rte_flow_error *error);
1309 int mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item,
1310 uint64_t item_flags,
1312 uint16_t ether_type,
1313 const struct rte_flow_item_ipv4 *acc_mask,
1314 bool range_accepted,
1315 struct rte_flow_error *error);
1316 int mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item,
1317 uint64_t item_flags,
1319 uint16_t ether_type,
1320 const struct rte_flow_item_ipv6 *acc_mask,
1321 struct rte_flow_error *error);
1322 int mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev,
1323 const struct rte_flow_item *item,
1324 uint64_t item_flags,
1325 uint64_t prev_layer,
1326 struct rte_flow_error *error);
1327 int mlx5_flow_validate_item_tcp(const struct rte_flow_item *item,
1328 uint64_t item_flags,
1329 uint8_t target_protocol,
1330 const struct rte_flow_item_tcp *flow_mask,
1331 struct rte_flow_error *error);
1332 int mlx5_flow_validate_item_udp(const struct rte_flow_item *item,
1333 uint64_t item_flags,
1334 uint8_t target_protocol,
1335 struct rte_flow_error *error);
1336 int mlx5_flow_validate_item_vlan(const struct rte_flow_item *item,
1337 uint64_t item_flags,
1338 struct rte_eth_dev *dev,
1339 struct rte_flow_error *error);
1340 int mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item,
1341 uint64_t item_flags,
1342 struct rte_flow_error *error);
1343 int mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item,
1344 uint64_t item_flags,
1345 struct rte_eth_dev *dev,
1346 struct rte_flow_error *error);
1347 int mlx5_flow_validate_item_icmp(const struct rte_flow_item *item,
1348 uint64_t item_flags,
1349 uint8_t target_protocol,
1350 struct rte_flow_error *error);
1351 int mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item,
1352 uint64_t item_flags,
1353 uint8_t target_protocol,
1354 struct rte_flow_error *error);
1355 int mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item,
1356 uint64_t item_flags,
1357 uint8_t target_protocol,
1358 struct rte_flow_error *error);
1359 int mlx5_flow_validate_item_geneve(const struct rte_flow_item *item,
1360 uint64_t item_flags,
1361 struct rte_eth_dev *dev,
1362 struct rte_flow_error *error);
1363 int mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item,
1364 uint64_t item_flags,
1366 uint16_t ether_type,
1367 const struct rte_flow_item_ecpri *acc_mask,
1368 struct rte_flow_error *error);
1369 struct mlx5_meter_domains_infos *mlx5_flow_create_mtr_tbls
1370 (struct rte_eth_dev *dev,
1371 const struct mlx5_flow_meter *fm);
1372 int mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev,
1373 struct mlx5_meter_domains_infos *tbl);
1374 int mlx5_flow_create_policer_rules(struct rte_eth_dev *dev,
1375 struct mlx5_flow_meter *fm,
1376 const struct rte_flow_attr *attr);
1377 int mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev,
1378 struct mlx5_flow_meter *fm,
1379 const struct rte_flow_attr *attr);
1380 int mlx5_flow_meter_flush(struct rte_eth_dev *dev,
1381 struct rte_mtr_error *error);
1382 int mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev);
1383 int mlx5_shared_action_flush(struct rte_eth_dev *dev);
1384 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id);
1385 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh);
1387 /* Hash list callbacks for flow tables: */
1388 struct mlx5_hlist_entry *flow_dv_tbl_create_cb(struct mlx5_hlist *list,
1389 uint64_t key, void *entry_ctx);
1390 void flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
1391 struct mlx5_hlist_entry *entry);
1392 struct mlx5_flow_tbl_resource *flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
1393 uint32_t table_id, uint8_t egress, uint8_t transfer,
1394 bool external, const struct mlx5_flow_tunnel *tunnel,
1395 uint32_t group_id, uint8_t dummy, struct rte_flow_error *error);
1397 struct mlx5_hlist_entry *flow_dv_tag_create_cb(struct mlx5_hlist *list,
1398 uint64_t key, void *cb_ctx);
1399 void flow_dv_tag_remove_cb(struct mlx5_hlist *list,
1400 struct mlx5_hlist_entry *entry);
1402 int flow_dv_modify_match_cb(struct mlx5_hlist *list,
1403 struct mlx5_hlist_entry *entry,
1404 uint64_t key, void *cb_ctx);
1405 struct mlx5_hlist_entry *flow_dv_modify_create_cb(struct mlx5_hlist *list,
1406 uint64_t key, void *ctx);
1407 void flow_dv_modify_remove_cb(struct mlx5_hlist *list,
1408 struct mlx5_hlist_entry *entry);
1410 struct mlx5_hlist_entry *flow_dv_mreg_create_cb(struct mlx5_hlist *list,
1411 uint64_t key, void *ctx);
1412 void flow_dv_mreg_remove_cb(struct mlx5_hlist *list,
1413 struct mlx5_hlist_entry *entry);
1415 int flow_dv_encap_decap_match_cb(struct mlx5_hlist *list,
1416 struct mlx5_hlist_entry *entry,
1417 uint64_t key, void *cb_ctx);
1418 struct mlx5_hlist_entry *flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
1419 uint64_t key, void *cb_ctx);
1420 void flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
1421 struct mlx5_hlist_entry *entry);
1423 int flow_dv_matcher_match_cb(struct mlx5_cache_list *list,
1424 struct mlx5_cache_entry *entry, void *ctx);
1425 struct mlx5_cache_entry *flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
1426 struct mlx5_cache_entry *entry, void *ctx);
1427 void flow_dv_matcher_remove_cb(struct mlx5_cache_list *list,
1428 struct mlx5_cache_entry *entry);
1430 int flow_dv_port_id_match_cb(struct mlx5_cache_list *list,
1431 struct mlx5_cache_entry *entry, void *cb_ctx);
1432 struct mlx5_cache_entry *flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
1433 struct mlx5_cache_entry *entry, void *cb_ctx);
1434 void flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
1435 struct mlx5_cache_entry *entry);
1437 int flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list,
1438 struct mlx5_cache_entry *entry, void *cb_ctx);
1439 struct mlx5_cache_entry *flow_dv_push_vlan_create_cb
1440 (struct mlx5_cache_list *list,
1441 struct mlx5_cache_entry *entry, void *cb_ctx);
1442 void flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
1443 struct mlx5_cache_entry *entry);
1445 int flow_dv_sample_match_cb(struct mlx5_cache_list *list,
1446 struct mlx5_cache_entry *entry, void *cb_ctx);
1447 struct mlx5_cache_entry *flow_dv_sample_create_cb
1448 (struct mlx5_cache_list *list,
1449 struct mlx5_cache_entry *entry, void *cb_ctx);
1450 void flow_dv_sample_remove_cb(struct mlx5_cache_list *list,
1451 struct mlx5_cache_entry *entry);
1453 int flow_dv_dest_array_match_cb(struct mlx5_cache_list *list,
1454 struct mlx5_cache_entry *entry, void *cb_ctx);
1455 struct mlx5_cache_entry *flow_dv_dest_array_create_cb
1456 (struct mlx5_cache_list *list,
1457 struct mlx5_cache_entry *entry, void *cb_ctx);
1458 void flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list,
1459 struct mlx5_cache_entry *entry);
1460 #endif /* RTE_PMD_MLX5_FLOW_H_ */