drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                         ++dcopy;
 435                 } else {
 436                         MLX5_ASSERT(item->spec);
 437                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 438                                                    field->offset, field->size);
 439                         /* Shift out the trailing masked bits from data. */
 440                         data = (data & mask) >> off_b;
 441                         actions[i].data1 = rte_cpu_to_be_32(data);
 442                 }
 443                 ++i;
 444                 ++field;
 445         } while (field->size);
 446         if (resource->actions_num == i)
 447                 return rte_flow_error_set(error, EINVAL,
 448                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 449                                           "invalid modification flow item");
 450         resource->actions_num = i;
 451         return 0;
 452 }
 453
 454 /**
 455  * Convert modify-header set IPv4 address action to DV specification.
 456  *
 457  * @param[in,out] resource
 458  *   Pointer to the modify-header resource.
 459  * @param[in] action
 460  *   Pointer to action specification.
 461  * @param[out] error
 462  *   Pointer to the error structure.
 463  *
 464  * @return
 465  *   0 on success, a negative errno value otherwise and rte_errno is set.
 466  */
 467 static int
 468 flow_dv_convert_action_modify_ipv4
 469                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 470                          const struct rte_flow_action *action,
 471                          struct rte_flow_error *error)
 472 {
 473         const struct rte_flow_action_set_ipv4 *conf =
 474                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 475         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 476         struct rte_flow_item_ipv4 ipv4;
 477         struct rte_flow_item_ipv4 ipv4_mask;
 478
 479         memset(&ipv4, 0, sizeof(ipv4));
 480         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 481         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 482                 ipv4.hdr.src_addr = conf->ipv4_addr;
 483                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 484         } else {
 485                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 486                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 487         }
 488         item.spec = &ipv4;
 489         item.mask = &ipv4_mask;
 490         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 491                                              MLX5_MODIFICATION_TYPE_SET, error);
 492 }
 493
 494 /**
 495  * Convert modify-header set IPv6 address action to DV specification.
 496  *
 497  * @param[in,out] resource
 498  *   Pointer to the modify-header resource.
 499  * @param[in] action
 500  *   Pointer to action specification.
 501  * @param[out] error
 502  *   Pointer to the error structure.
 503  *
 504  * @return
 505  *   0 on success, a negative errno value otherwise and rte_errno is set.
 506  */
 507 static int
 508 flow_dv_convert_action_modify_ipv6
 509                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 510                          const struct rte_flow_action *action,
 511                          struct rte_flow_error *error)
 512 {
 513         const struct rte_flow_action_set_ipv6 *conf =
 514                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 515         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 516         struct rte_flow_item_ipv6 ipv6;
 517         struct rte_flow_item_ipv6 ipv6_mask;
 518
 519         memset(&ipv6, 0, sizeof(ipv6));
 520         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 521         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 522                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 523                        sizeof(ipv6.hdr.src_addr));
 524                 memcpy(&ipv6_mask.hdr.src_addr,
 525                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 526                        sizeof(ipv6.hdr.src_addr));
 527         } else {
 528                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 529                        sizeof(ipv6.hdr.dst_addr));
 530                 memcpy(&ipv6_mask.hdr.dst_addr,
 531                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 532                        sizeof(ipv6.hdr.dst_addr));
 533         }
 534         item.spec = &ipv6;
 535         item.mask = &ipv6_mask;
 536         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 537                                              MLX5_MODIFICATION_TYPE_SET, error);
 538 }
 539
 540 /**
 541  * Convert modify-header set MAC address action to DV specification.
 542  *
 543  * @param[in,out] resource
 544  *   Pointer to the modify-header resource.
 545  * @param[in] action
 546  *   Pointer to action specification.
 547  * @param[out] error
 548  *   Pointer to the error structure.
 549  *
 550  * @return
 551  *   0 on success, a negative errno value otherwise and rte_errno is set.
 552  */
 553 static int
 554 flow_dv_convert_action_modify_mac
 555                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 556                          const struct rte_flow_action *action,
 557                          struct rte_flow_error *error)
 558 {
 559         const struct rte_flow_action_set_mac *conf =
 560                 (const struct rte_flow_action_set_mac *)(action->conf);
 561         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 562         struct rte_flow_item_eth eth;
 563         struct rte_flow_item_eth eth_mask;
 564
 565         memset(&eth, 0, sizeof(eth));
 566         memset(&eth_mask, 0, sizeof(eth_mask));
 567         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 568                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 569                        sizeof(eth.src.addr_bytes));
 570                 memcpy(&eth_mask.src.addr_bytes,
 571                        &rte_flow_item_eth_mask.src.addr_bytes,
 572                        sizeof(eth_mask.src.addr_bytes));
 573         } else {
 574                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 575                        sizeof(eth.dst.addr_bytes));
 576                 memcpy(&eth_mask.dst.addr_bytes,
 577                        &rte_flow_item_eth_mask.dst.addr_bytes,
 578                        sizeof(eth_mask.dst.addr_bytes));
 579         }
 580         item.spec = &eth;
 581         item.mask = &eth_mask;
 582         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 583                                              MLX5_MODIFICATION_TYPE_SET, error);
 584 }
 585
 586 /**
 587  * Convert modify-header set VLAN VID action to DV specification.
 588  *
 589  * @param[in,out] resource
 590  *   Pointer to the modify-header resource.
 591  * @param[in] action
 592  *   Pointer to action specification.
 593  * @param[out] error
 594  *   Pointer to the error structure.
 595  *
 596  * @return
 597  *   0 on success, a negative errno value otherwise and rte_errno is set.
 598  */
 599 static int
 600 flow_dv_convert_action_modify_vlan_vid
 601                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 602                          const struct rte_flow_action *action,
 603                          struct rte_flow_error *error)
 604 {
 605         const struct rte_flow_action_of_set_vlan_vid *conf =
 606                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 607         int i = resource->actions_num;
 608         struct mlx5_modification_cmd *actions = resource->actions;
 609         struct field_modify_info *field = modify_vlan_out_first_vid;
 610
 611         if (i >= MLX5_MAX_MODIFY_NUM)
 612                 return rte_flow_error_set(error, EINVAL,
 613                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 614                          "too many items to modify");
 615         actions[i] = (struct mlx5_modification_cmd) {
 616                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 617                 .field = field->id,
 618                 .length = field->size,
 619                 .offset = field->offset,
 620         };
 621         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 622         actions[i].data1 = conf->vlan_vid;
 623         actions[i].data1 = actions[i].data1 << 16;
 624         resource->actions_num = ++i;
 625         return 0;
 626 }
 627
 628 /**
 629  * Convert modify-header set TP action to DV specification.
 630  *
 631  * @param[in,out] resource
 632  *   Pointer to the modify-header resource.
 633  * @param[in] action
 634  *   Pointer to action specification.
 635  * @param[in] items
 636  *   Pointer to rte_flow_item objects list.
 637  * @param[in] attr
 638  *   Pointer to flow attributes structure.
 639  * @param[in] dev_flow
 640  *   Pointer to the sub flow.
 641  * @param[in] tunnel_decap
 642  *   Whether action is after tunnel decapsulation.
 643  * @param[out] error
 644  *   Pointer to the error structure.
 645  *
 646  * @return
 647  *   0 on success, a negative errno value otherwise and rte_errno is set.
 648  */
 649 static int
 650 flow_dv_convert_action_modify_tp
 651                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 652                          const struct rte_flow_action *action,
 653                          const struct rte_flow_item *items,
 654                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 655                          bool tunnel_decap, struct rte_flow_error *error)
 656 {
 657         const struct rte_flow_action_set_tp *conf =
 658                 (const struct rte_flow_action_set_tp *)(action->conf);
 659         struct rte_flow_item item;
 660         struct rte_flow_item_udp udp;
 661         struct rte_flow_item_udp udp_mask;
 662         struct rte_flow_item_tcp tcp;
 663         struct rte_flow_item_tcp tcp_mask;
 664         struct field_modify_info *field;
 665
 666         if (!attr->valid)
 667                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 668         if (attr->udp) {
 669                 memset(&udp, 0, sizeof(udp));
 670                 memset(&udp_mask, 0, sizeof(udp_mask));
 671                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 672                         udp.hdr.src_port = conf->port;
 673                         udp_mask.hdr.src_port =
 674                                         rte_flow_item_udp_mask.hdr.src_port;
 675                 } else {
 676                         udp.hdr.dst_port = conf->port;
 677                         udp_mask.hdr.dst_port =
 678                                         rte_flow_item_udp_mask.hdr.dst_port;
 679                 }
 680                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 681                 item.spec = &udp;
 682                 item.mask = &udp_mask;
 683                 field = modify_udp;
 684         } else {
 685                 MLX5_ASSERT(attr->tcp);
 686                 memset(&tcp, 0, sizeof(tcp));
 687                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 688                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 689                         tcp.hdr.src_port = conf->port;
 690                         tcp_mask.hdr.src_port =
 691                                         rte_flow_item_tcp_mask.hdr.src_port;
 692                 } else {
 693                         tcp.hdr.dst_port = conf->port;
 694                         tcp_mask.hdr.dst_port =
 695                                         rte_flow_item_tcp_mask.hdr.dst_port;
 696                 }
 697                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 698                 item.spec = &tcp;
 699                 item.mask = &tcp_mask;
 700                 field = modify_tcp;
 701         }
 702         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 703                                              MLX5_MODIFICATION_TYPE_SET, error);
 704 }
 705
 706 /**
 707  * Convert modify-header set TTL action to DV specification.
 708  *
 709  * @param[in,out] resource
 710  *   Pointer to the modify-header resource.
 711  * @param[in] action
 712  *   Pointer to action specification.
 713  * @param[in] items
 714  *   Pointer to rte_flow_item objects list.
 715  * @param[in] attr
 716  *   Pointer to flow attributes structure.
 717  * @param[in] dev_flow
 718  *   Pointer to the sub flow.
 719  * @param[in] tunnel_decap
 720  *   Whether action is after tunnel decapsulation.
 721  * @param[out] error
 722  *   Pointer to the error structure.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 static int
 728 flow_dv_convert_action_modify_ttl
 729                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 730                          const struct rte_flow_action *action,
 731                          const struct rte_flow_item *items,
 732                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 733                          bool tunnel_decap, struct rte_flow_error *error)
 734 {
 735         const struct rte_flow_action_set_ttl *conf =
 736                 (const struct rte_flow_action_set_ttl *)(action->conf);
 737         struct rte_flow_item item;
 738         struct rte_flow_item_ipv4 ipv4;
 739         struct rte_flow_item_ipv4 ipv4_mask;
 740         struct rte_flow_item_ipv6 ipv6;
 741         struct rte_flow_item_ipv6 ipv6_mask;
 742         struct field_modify_info *field;
 743
 744         if (!attr->valid)
 745                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 746         if (attr->ipv4) {
 747                 memset(&ipv4, 0, sizeof(ipv4));
 748                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 749                 ipv4.hdr.time_to_live = conf->ttl_value;
 750                 ipv4_mask.hdr.time_to_live = 0xFF;
 751                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 752                 item.spec = &ipv4;
 753                 item.mask = &ipv4_mask;
 754                 field = modify_ipv4;
 755         } else {
 756                 MLX5_ASSERT(attr->ipv6);
 757                 memset(&ipv6, 0, sizeof(ipv6));
 758                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 759                 ipv6.hdr.hop_limits = conf->ttl_value;
 760                 ipv6_mask.hdr.hop_limits = 0xFF;
 761                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 762                 item.spec = &ipv6;
 763                 item.mask = &ipv6_mask;
 764                 field = modify_ipv6;
 765         }
 766         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 767                                              MLX5_MODIFICATION_TYPE_SET, error);
 768 }
 769
 770 /**
 771  * Convert modify-header decrement TTL action to DV specification.
 772  *
 773  * @param[in,out] resource
 774  *   Pointer to the modify-header resource.
 775  * @param[in] action
 776  *   Pointer to action specification.
 777  * @param[in] items
 778  *   Pointer to rte_flow_item objects list.
 779  * @param[in] attr
 780  *   Pointer to flow attributes structure.
 781  * @param[in] dev_flow
 782  *   Pointer to the sub flow.
 783  * @param[in] tunnel_decap
 784  *   Whether action is after tunnel decapsulation.
 785  * @param[out] error
 786  *   Pointer to the error structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 static int
 792 flow_dv_convert_action_modify_dec_ttl
 793                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 794                          const struct rte_flow_item *items,
 795                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 796                          bool tunnel_decap, struct rte_flow_error *error)
 797 {
 798         struct rte_flow_item item;
 799         struct rte_flow_item_ipv4 ipv4;
 800         struct rte_flow_item_ipv4 ipv4_mask;
 801         struct rte_flow_item_ipv6 ipv6;
 802         struct rte_flow_item_ipv6 ipv6_mask;
 803         struct field_modify_info *field;
 804
 805         if (!attr->valid)
 806                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 807         if (attr->ipv4) {
 808                 memset(&ipv4, 0, sizeof(ipv4));
 809                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 810                 ipv4.hdr.time_to_live = 0xFF;
 811                 ipv4_mask.hdr.time_to_live = 0xFF;
 812                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 813                 item.spec = &ipv4;
 814                 item.mask = &ipv4_mask;
 815                 field = modify_ipv4;
 816         } else {
 817                 MLX5_ASSERT(attr->ipv6);
 818                 memset(&ipv6, 0, sizeof(ipv6));
 819                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 820                 ipv6.hdr.hop_limits = 0xFF;
 821                 ipv6_mask.hdr.hop_limits = 0xFF;
 822                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 823                 item.spec = &ipv6;
 824                 item.mask = &ipv6_mask;
 825                 field = modify_ipv6;
 826         }
 827         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 828                                              MLX5_MODIFICATION_TYPE_ADD, error);
 829 }
 830
 831 /**
 832  * Convert modify-header increment/decrement TCP Sequence number
 833  * to DV specification.
 834  *
 835  * @param[in,out] resource
 836  *   Pointer to the modify-header resource.
 837  * @param[in] action
 838  *   Pointer to action specification.
 839  * @param[out] error
 840  *   Pointer to the error structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 static int
 846 flow_dv_convert_action_modify_tcp_seq
 847                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 848                          const struct rte_flow_action *action,
 849                          struct rte_flow_error *error)
 850 {
 851         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 852         uint64_t value = rte_be_to_cpu_32(*conf);
 853         struct rte_flow_item item;
 854         struct rte_flow_item_tcp tcp;
 855         struct rte_flow_item_tcp tcp_mask;
 856
 857         memset(&tcp, 0, sizeof(tcp));
 858         memset(&tcp_mask, 0, sizeof(tcp_mask));
 859         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 860                 /*
 861                  * The HW has no decrement operation, only increment operation.
 862                  * To simulate decrement X from Y using increment operation
 863                  * we need to add UINT32_MAX X times to Y.
 864                  * Each adding of UINT32_MAX decrements Y by 1.
 865                  */
 866                 value *= UINT32_MAX;
 867         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 868         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 869         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 870         item.spec = &tcp;
 871         item.mask = &tcp_mask;
 872         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 873                                              MLX5_MODIFICATION_TYPE_ADD, error);
 874 }
 875
 876 /**
 877  * Convert modify-header increment/decrement TCP Acknowledgment number
 878  * to DV specification.
 879  *
 880  * @param[in,out] resource
 881  *   Pointer to the modify-header resource.
 882  * @param[in] action
 883  *   Pointer to action specification.
 884  * @param[out] error
 885  *   Pointer to the error structure.
 886  *
 887  * @return
 888  *   0 on success, a negative errno value otherwise and rte_errno is set.
 889  */
 890 static int
 891 flow_dv_convert_action_modify_tcp_ack
 892                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 893                          const struct rte_flow_action *action,
 894                          struct rte_flow_error *error)
 895 {
 896         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 897         uint64_t value = rte_be_to_cpu_32(*conf);
 898         struct rte_flow_item item;
 899         struct rte_flow_item_tcp tcp;
 900         struct rte_flow_item_tcp tcp_mask;
 901
 902         memset(&tcp, 0, sizeof(tcp));
 903         memset(&tcp_mask, 0, sizeof(tcp_mask));
 904         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 905                 /*
 906                  * The HW has no decrement operation, only increment operation.
 907                  * To simulate decrement X from Y using increment operation
 908                  * we need to add UINT32_MAX X times to Y.
 909                  * Each adding of UINT32_MAX decrements Y by 1.
 910                  */
 911                 value *= UINT32_MAX;
 912         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 913         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 914         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 915         item.spec = &tcp;
 916         item.mask = &tcp_mask;
 917         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 918                                              MLX5_MODIFICATION_TYPE_ADD, error);
 919 }
 920
 921 static enum mlx5_modification_field reg_to_field[] = {
 922         [REG_NON] = MLX5_MODI_OUT_NONE,
 923         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 924         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 925         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 926         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 927         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 928         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 929         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 930         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 931         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 932         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 933 };
 934
 935 /**
 936  * Convert register set to DV specification.
 937  *
 938  * @param[in,out] resource
 939  *   Pointer to the modify-header resource.
 940  * @param[in] action
 941  *   Pointer to action specification.
 942  * @param[out] error
 943  *   Pointer to the error structure.
 944  *
 945  * @return
 946  *   0 on success, a negative errno value otherwise and rte_errno is set.
 947  */
 948 static int
 949 flow_dv_convert_action_set_reg
 950                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 951                          const struct rte_flow_action *action,
 952                          struct rte_flow_error *error)
 953 {
 954         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 955         struct mlx5_modification_cmd *actions = resource->actions;
 956         uint32_t i = resource->actions_num;
 957
 958         if (i >= MLX5_MAX_MODIFY_NUM)
 959                 return rte_flow_error_set(error, EINVAL,
 960                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 961                                           "too many items to modify");
 962         MLX5_ASSERT(conf->id != REG_NON);
 963         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 964         actions[i] = (struct mlx5_modification_cmd) {
 965                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 966                 .field = reg_to_field[conf->id],
 967         };
 968         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 969         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 970         ++i;
 971         resource->actions_num = i;
 972         return 0;
 973 }
 974
 975 /**
 976  * Convert SET_TAG action to DV specification.
 977  *
 978  * @param[in] dev
 979  *   Pointer to the rte_eth_dev structure.
 980  * @param[in,out] resource
 981  *   Pointer to the modify-header resource.
 982  * @param[in] conf
 983  *   Pointer to action specification.
 984  * @param[out] error
 985  *   Pointer to the error structure.
 986  *
 987  * @return
 988  *   0 on success, a negative errno value otherwise and rte_errno is set.
 989  */
 990 static int
 991 flow_dv_convert_action_set_tag
 992                         (struct rte_eth_dev *dev,
 993                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 994                          const struct rte_flow_action_set_tag *conf,
 995                          struct rte_flow_error *error)
 996 {
 997         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 998         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 999         struct rte_flow_item item = {
1000                 .spec = &data,
1001                 .mask = &mask,
1002         };
1003         struct field_modify_info reg_c_x[] = {
1004                 [1] = {0, 0, 0},
1005         };
1006         enum mlx5_modification_field reg_type;
1007         int ret;
1008
1009         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010         if (ret < 0)
1011                 return ret;
1012         MLX5_ASSERT(ret != REG_NON);
1013         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014         reg_type = reg_to_field[ret];
1015         MLX5_ASSERT(reg_type > 0);
1016         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018                                              MLX5_MODIFICATION_TYPE_SET, error);
1019 }
1020
1021 /**
1022  * Convert internal COPY_REG action to DV specification.
1023  *
1024  * @param[in] dev
1025  *   Pointer to the rte_eth_dev structure.
1026  * @param[in,out] res
1027  *   Pointer to the modify-header resource.
1028  * @param[in] action
1029  *   Pointer to action specification.
1030  * @param[out] error
1031  *   Pointer to the error structure.
1032  *
1033  * @return
1034  *   0 on success, a negative errno value otherwise and rte_errno is set.
1035  */
1036 static int
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1039                                  const struct rte_flow_action *action,
1040                                  struct rte_flow_error *error)
1041 {
1042         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044         struct rte_flow_item item = {
1045                 .spec = NULL,
1046                 .mask = &mask,
1047         };
1048         struct field_modify_info reg_src[] = {
1049                 {4, 0, reg_to_field[conf->src]},
1050                 {0, 0, 0},
1051         };
1052         struct field_modify_info reg_dst = {
1053                 .offset = 0,
1054                 .id = reg_to_field[conf->dst],
1055         };
1056         /* Adjust reg_c[0] usage according to reported mask. */
1057         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058                 struct mlx5_priv *priv = dev->data->dev_private;
1059                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060
1061                 MLX5_ASSERT(reg_c0);
1062                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063                 if (conf->dst == REG_C_0) {
1064                         /* Copy to reg_c[0], within mask only. */
1065                         reg_dst.offset = rte_bsf32(reg_c0);
1066                         /*
1067                          * Mask is ignoring the enianness, because
1068                          * there is no conversion in datapath.
1069                          */
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071                         /* Copy from destination lower bits to reg_c[0]. */
1072                         mask = reg_c0 >> reg_dst.offset;
1073 #else
1074                         /* Copy from destination upper bits to reg_c[0]. */
1075                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076                                           rte_fls_u32(reg_c0));
1077 #endif
1078                 } else {
1079                         mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081                         /* Copy from reg_c[0] to destination lower bits. */
1082                         reg_dst.offset = 0;
1083 #else
1084                         /* Copy from reg_c[0] to destination upper bits. */
1085                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086                                          (rte_fls_u32(reg_c0) -
1087                                           rte_bsf32(reg_c0));
1088 #endif
1089                 }
1090         }
1091         return flow_dv_convert_modify_action(&item,
1092                                              reg_src, &reg_dst, res,
1093                                              MLX5_MODIFICATION_TYPE_COPY,
1094                                              error);
1095 }
1096
1097 /**
1098  * Convert MARK action to DV specification. This routine is used
1099  * in extensive metadata only and requires metadata register to be
1100  * handled. In legacy mode hardware tag resource is engaged.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] conf
1105  *   Pointer to MARK action specification.
1106  * @param[in,out] resource
1107  *   Pointer to the modify-header resource.
1108  * @param[out] error
1109  *   Pointer to the error structure.
1110  *
1111  * @return
1112  *   0 on success, a negative errno value otherwise and rte_errno is set.
1113  */
1114 static int
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116                             const struct rte_flow_action_mark *conf,
1117                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1118                             struct rte_flow_error *error)
1119 {
1120         struct mlx5_priv *priv = dev->data->dev_private;
1121         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122                                            priv->sh->dv_mark_mask);
1123         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124         struct rte_flow_item item = {
1125                 .spec = &data,
1126                 .mask = &mask,
1127         };
1128         struct field_modify_info reg_c_x[] = {
1129                 [1] = {0, 0, 0},
1130         };
1131         int reg;
1132
1133         if (!mask)
1134                 return rte_flow_error_set(error, EINVAL,
1135                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136                                           NULL, "zero mark action mask");
1137         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1138         if (reg < 0)
1139                 return reg;
1140         MLX5_ASSERT(reg > 0);
1141         if (reg == REG_C_0) {
1142                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144
1145                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147                 mask = rte_cpu_to_be_32(mask << shl_c0);
1148         }
1149         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151                                              MLX5_MODIFICATION_TYPE_SET, error);
1152 }
1153
1154 /**
1155  * Get metadata register index for specified steering domain.
1156  *
1157  * @param[in] dev
1158  *   Pointer to the rte_eth_dev structure.
1159  * @param[in] attr
1160  *   Attributes of flow to determine steering domain.
1161  * @param[out] error
1162  *   Pointer to the error structure.
1163  *
1164  * @return
1165  *   positive index on success, a negative errno value otherwise
1166  *   and rte_errno is set.
1167  */
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170                          const struct rte_flow_attr *attr,
1171                          struct rte_flow_error *error)
1172 {
1173         int reg =
1174                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1175                                           MLX5_METADATA_FDB :
1176                                             attr->egress ?
1177                                             MLX5_METADATA_TX :
1178                                             MLX5_METADATA_RX, 0, error);
1179         if (reg < 0)
1180                 return rte_flow_error_set(error,
1181                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182                                           NULL, "unavailable "
1183                                           "metadata register");
1184         return reg;
1185 }
1186
1187 /**
1188  * Convert SET_META action to DV specification.
1189  *
1190  * @param[in] dev
1191  *   Pointer to the rte_eth_dev structure.
1192  * @param[in,out] resource
1193  *   Pointer to the modify-header resource.
1194  * @param[in] attr
1195  *   Attributes of flow that includes this item.
1196  * @param[in] conf
1197  *   Pointer to action specification.
1198  * @param[out] error
1199  *   Pointer to the error structure.
1200  *
1201  * @return
1202  *   0 on success, a negative errno value otherwise and rte_errno is set.
1203  */
1204 static int
1205 flow_dv_convert_action_set_meta
1206                         (struct rte_eth_dev *dev,
1207                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1208                          const struct rte_flow_attr *attr,
1209                          const struct rte_flow_action_set_meta *conf,
1210                          struct rte_flow_error *error)
1211 {
1212         uint32_t data = conf->data;
1213         uint32_t mask = conf->mask;
1214         struct rte_flow_item item = {
1215                 .spec = &data,
1216                 .mask = &mask,
1217         };
1218         struct field_modify_info reg_c_x[] = {
1219                 [1] = {0, 0, 0},
1220         };
1221         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1222
1223         if (reg < 0)
1224                 return reg;
1225         MLX5_ASSERT(reg != REG_NON);
1226         /*
1227          * In datapath code there is no endianness
1228          * coversions for perfromance reasons, all
1229          * pattern conversions are done in rte_flow.
1230          */
1231         if (reg == REG_C_0) {
1232                 struct mlx5_priv *priv = dev->data->dev_private;
1233                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234                 uint32_t shl_c0;
1235
1236                 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238                 shl_c0 = rte_bsf32(msk_c0);
1239 #else
1240                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1241 #endif
1242                 mask <<= shl_c0;
1243                 data <<= shl_c0;
1244                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245         }
1246         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247         /* The routine expects parameters in memory as big-endian ones. */
1248         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249                                              MLX5_MODIFICATION_TYPE_SET, error);
1250 }
1251
1252 /**
1253  * Convert modify-header set IPv4 DSCP action to DV specification.
1254  *
1255  * @param[in,out] resource
1256  *   Pointer to the modify-header resource.
1257  * @param[in] action
1258  *   Pointer to action specification.
1259  * @param[out] error
1260  *   Pointer to the error structure.
1261  *
1262  * @return
1263  *   0 on success, a negative errno value otherwise and rte_errno is set.
1264  */
1265 static int
1266 flow_dv_convert_action_modify_ipv4_dscp
1267                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268                          const struct rte_flow_action *action,
1269                          struct rte_flow_error *error)
1270 {
1271         const struct rte_flow_action_set_dscp *conf =
1272                 (const struct rte_flow_action_set_dscp *)(action->conf);
1273         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274         struct rte_flow_item_ipv4 ipv4;
1275         struct rte_flow_item_ipv4 ipv4_mask;
1276
1277         memset(&ipv4, 0, sizeof(ipv4));
1278         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279         ipv4.hdr.type_of_service = conf->dscp;
1280         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281         item.spec = &ipv4;
1282         item.mask = &ipv4_mask;
1283         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284                                              MLX5_MODIFICATION_TYPE_SET, error);
1285 }
1286
1287 /**
1288  * Convert modify-header set IPv6 DSCP action to DV specification.
1289  *
1290  * @param[in,out] resource
1291  *   Pointer to the modify-header resource.
1292  * @param[in] action
1293  *   Pointer to action specification.
1294  * @param[out] error
1295  *   Pointer to the error structure.
1296  *
1297  * @return
1298  *   0 on success, a negative errno value otherwise and rte_errno is set.
1299  */
1300 static int
1301 flow_dv_convert_action_modify_ipv6_dscp
1302                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303                          const struct rte_flow_action *action,
1304                          struct rte_flow_error *error)
1305 {
1306         const struct rte_flow_action_set_dscp *conf =
1307                 (const struct rte_flow_action_set_dscp *)(action->conf);
1308         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309         struct rte_flow_item_ipv6 ipv6;
1310         struct rte_flow_item_ipv6 ipv6_mask;
1311
1312         memset(&ipv6, 0, sizeof(ipv6));
1313         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314         /*
1315          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316          * rdma-core only accept the DSCP bits byte aligned start from
1317          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318          * bits in IPv6 case as rdma-core requires byte aligned value.
1319          */
1320         ipv6.hdr.vtc_flow = conf->dscp;
1321         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322         item.spec = &ipv6;
1323         item.mask = &ipv6_mask;
1324         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325                                              MLX5_MODIFICATION_TYPE_SET, error);
1326 }
1327
1328 static int
1329 mlx5_flow_item_field_width(enum rte_flow_field_id field)
1330 {
1331         switch (field) {
1332         case RTE_FLOW_FIELD_START:
1333                 return 32;
1334         case RTE_FLOW_FIELD_MAC_DST:
1335         case RTE_FLOW_FIELD_MAC_SRC:
1336                 return 48;
1337         case RTE_FLOW_FIELD_VLAN_TYPE:
1338                 return 16;
1339         case RTE_FLOW_FIELD_VLAN_ID:
1340                 return 12;
1341         case RTE_FLOW_FIELD_MAC_TYPE:
1342                 return 16;
1343         case RTE_FLOW_FIELD_IPV4_DSCP:
1344                 return 6;
1345         case RTE_FLOW_FIELD_IPV4_TTL:
1346                 return 8;
1347         case RTE_FLOW_FIELD_IPV4_SRC:
1348         case RTE_FLOW_FIELD_IPV4_DST:
1349                 return 32;
1350         case RTE_FLOW_FIELD_IPV6_DSCP:
1351                 return 6;
1352         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1353                 return 8;
1354         case RTE_FLOW_FIELD_IPV6_SRC:
1355         case RTE_FLOW_FIELD_IPV6_DST:
1356                 return 128;
1357         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1358         case RTE_FLOW_FIELD_TCP_PORT_DST:
1359                 return 16;
1360         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1361         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1362                 return 32;
1363         case RTE_FLOW_FIELD_TCP_FLAGS:
1364                 return 6;
1365         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1366         case RTE_FLOW_FIELD_UDP_PORT_DST:
1367                 return 16;
1368         case RTE_FLOW_FIELD_VXLAN_VNI:
1369         case RTE_FLOW_FIELD_GENEVE_VNI:
1370                 return 24;
1371         case RTE_FLOW_FIELD_GTP_TEID:
1372         case RTE_FLOW_FIELD_TAG:
1373                 return 32;
1374         case RTE_FLOW_FIELD_MARK:
1375                 return 24;
1376         case RTE_FLOW_FIELD_META:
1377                 return 32;
1378         case RTE_FLOW_FIELD_POINTER:
1379         case RTE_FLOW_FIELD_VALUE:
1380                 return 64;
1381         default:
1382                 MLX5_ASSERT(false);
1383         }
1384         return 0;
1385 }
1386
1387 static void
1388 mlx5_flow_field_id_to_modify_info
1389                 (const struct rte_flow_action_modify_data *data,
1390                  struct field_modify_info *info,
1391                  uint32_t *mask, uint32_t *value,
1392                  uint32_t width, uint32_t dst_width,
1393                  struct rte_eth_dev *dev,
1394                  const struct rte_flow_attr *attr,
1395                  struct rte_flow_error *error)
1396 {
1397         uint32_t idx = 0;
1398         uint64_t val = 0;
1399         switch (data->field) {
1400         case RTE_FLOW_FIELD_START:
1401                 /* not supported yet */
1402                 MLX5_ASSERT(false);
1403                 break;
1404         case RTE_FLOW_FIELD_MAC_DST:
1405                 if (mask) {
1406                         if (data->offset < 32) {
1407                                 info[idx] = (struct field_modify_info){4, 0,
1408                                                 MLX5_MODI_OUT_DMAC_47_16};
1409                                 if (width < 32) {
1410                                         mask[idx] =
1411                                                 rte_cpu_to_be_32(0xffffffff >>
1412                                                                  (32 - width));
1413                                         width = 0;
1414                                 } else {
1415                                         mask[idx] = RTE_BE32(0xffffffff);
1416                                         width -= 32;
1417                                 }
1418                                 if (!width)
1419                                         break;
1420                                 ++idx;
1421                         }
1422                         info[idx] = (struct field_modify_info){2, 4 * idx,
1423                                                 MLX5_MODI_OUT_DMAC_15_0};
1424                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1425                 } else {
1426                         if (data->offset < 32)
1427                                 info[idx++] = (struct field_modify_info){4, 0,
1428                                                 MLX5_MODI_OUT_DMAC_47_16};
1429                         info[idx] = (struct field_modify_info){2, 0,
1430                                                 MLX5_MODI_OUT_DMAC_15_0};
1431                 }
1432                 break;
1433         case RTE_FLOW_FIELD_MAC_SRC:
1434                 if (mask) {
1435                         if (data->offset < 32) {
1436                                 info[idx] = (struct field_modify_info){4, 0,
1437                                                 MLX5_MODI_OUT_SMAC_47_16};
1438                                 if (width < 32) {
1439                                         mask[idx] =
1440                                                 rte_cpu_to_be_32(0xffffffff >>
1441                                                                 (32 - width));
1442                                         width = 0;
1443                                 } else {
1444                                         mask[idx] = RTE_BE32(0xffffffff);
1445                                         width -= 32;
1446                                 }
1447                                 if (!width)
1448                                         break;
1449                                 ++idx;
1450                         }
1451                         info[idx] = (struct field_modify_info){2, 4 * idx,
1452                                                 MLX5_MODI_OUT_SMAC_15_0};
1453                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1454                 } else {
1455                         if (data->offset < 32)
1456                                 info[idx++] = (struct field_modify_info){4, 0,
1457                                                 MLX5_MODI_OUT_SMAC_47_16};
1458                         info[idx] = (struct field_modify_info){2, 0,
1459                                                 MLX5_MODI_OUT_SMAC_15_0};
1460                 }
1461                 break;
1462         case RTE_FLOW_FIELD_VLAN_TYPE:
1463                 /* not supported yet */
1464                 break;
1465         case RTE_FLOW_FIELD_VLAN_ID:
1466                 info[idx] = (struct field_modify_info){2, 0,
1467                                         MLX5_MODI_OUT_FIRST_VID};
1468                 if (mask)
1469                         mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1470                 break;
1471         case RTE_FLOW_FIELD_MAC_TYPE:
1472                 info[idx] = (struct field_modify_info){2, 0,
1473                                         MLX5_MODI_OUT_ETHERTYPE};
1474                 if (mask)
1475                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1476                 break;
1477         case RTE_FLOW_FIELD_IPV4_DSCP:
1478                 info[idx] = (struct field_modify_info){1, 0,
1479                                         MLX5_MODI_OUT_IP_DSCP};
1480                 if (mask)
1481                         mask[idx] = 0x3f >> (6 - width);
1482                 break;
1483         case RTE_FLOW_FIELD_IPV4_TTL:
1484                 info[idx] = (struct field_modify_info){1, 0,
1485                                         MLX5_MODI_OUT_IPV4_TTL};
1486                 if (mask)
1487                         mask[idx] = 0xff >> (8 - width);
1488                 break;
1489         case RTE_FLOW_FIELD_IPV4_SRC:
1490                 info[idx] = (struct field_modify_info){4, 0,
1491                                         MLX5_MODI_OUT_SIPV4};
1492                 if (mask)
1493                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1494                                                      (32 - width));
1495                 break;
1496         case RTE_FLOW_FIELD_IPV4_DST:
1497                 info[idx] = (struct field_modify_info){4, 0,
1498                                         MLX5_MODI_OUT_DIPV4};
1499                 if (mask)
1500                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1501                                                      (32 - width));
1502                 break;
1503         case RTE_FLOW_FIELD_IPV6_DSCP:
1504                 info[idx] = (struct field_modify_info){1, 0,
1505                                         MLX5_MODI_OUT_IP_DSCP};
1506                 if (mask)
1507                         mask[idx] = 0x3f >> (6 - width);
1508                 break;
1509         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1510                 info[idx] = (struct field_modify_info){1, 0,
1511                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1512                 if (mask)
1513                         mask[idx] = 0xff >> (8 - width);
1514                 break;
1515         case RTE_FLOW_FIELD_IPV6_SRC:
1516                 if (mask) {
1517                         if (data->offset < 32) {
1518                                 info[idx] = (struct field_modify_info){4,
1519                                                 4 * idx,
1520                                                 MLX5_MODI_OUT_SIPV6_31_0};
1521                                 if (width < 32) {
1522                                         mask[idx] =
1523                                                 rte_cpu_to_be_32(0xffffffff >>
1524                                                                  (32 - width));
1525                                         width = 0;
1526                                 } else {
1527                                         mask[idx] = RTE_BE32(0xffffffff);
1528                                         width -= 32;
1529                                 }
1530                                 if (!width)
1531                                         break;
1532                                 ++idx;
1533                         }
1534                         if (data->offset < 64) {
1535                                 info[idx] = (struct field_modify_info){4,
1536                                                 4 * idx,
1537                                                 MLX5_MODI_OUT_SIPV6_63_32};
1538                                 if (width < 32) {
1539                                         mask[idx] =
1540                                                 rte_cpu_to_be_32(0xffffffff >>
1541                                                                  (32 - width));
1542                                         width = 0;
1543                                 } else {
1544                                         mask[idx] = RTE_BE32(0xffffffff);
1545                                         width -= 32;
1546                                 }
1547                                 if (!width)
1548                                         break;
1549                                 ++idx;
1550                         }
1551                         if (data->offset < 96) {
1552                                 info[idx] = (struct field_modify_info){4,
1553                                                 4 * idx,
1554                                                 MLX5_MODI_OUT_SIPV6_95_64};
1555                                 if (width < 32) {
1556                                         mask[idx] =
1557                                                 rte_cpu_to_be_32(0xffffffff >>
1558                                                                  (32 - width));
1559                                         width = 0;
1560                                 } else {
1561                                         mask[idx] = RTE_BE32(0xffffffff);
1562                                         width -= 32;
1563                                 }
1564                                 if (!width)
1565                                         break;
1566                                 ++idx;
1567                         }
1568                         info[idx] = (struct field_modify_info){4, 4 * idx,
1569                                                 MLX5_MODI_OUT_SIPV6_127_96};
1570                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1571                                                      (32 - width));
1572                 } else {
1573                         if (data->offset < 32)
1574                                 info[idx++] = (struct field_modify_info){4, 0,
1575                                                 MLX5_MODI_OUT_SIPV6_31_0};
1576                         if (data->offset < 64)
1577                                 info[idx++] = (struct field_modify_info){4, 0,
1578                                                 MLX5_MODI_OUT_SIPV6_63_32};
1579                         if (data->offset < 96)
1580                                 info[idx++] = (struct field_modify_info){4, 0,
1581                                                 MLX5_MODI_OUT_SIPV6_95_64};
1582                         if (data->offset < 128)
1583                                 info[idx++] = (struct field_modify_info){4, 0,
1584                                                 MLX5_MODI_OUT_SIPV6_127_96};
1585                 }
1586                 break;
1587         case RTE_FLOW_FIELD_IPV6_DST:
1588                 if (mask) {
1589                         if (data->offset < 32) {
1590                                 info[idx] = (struct field_modify_info){4,
1591                                                 4 * idx,
1592                                                 MLX5_MODI_OUT_DIPV6_31_0};
1593                                 if (width < 32) {
1594                                         mask[idx] =
1595                                                 rte_cpu_to_be_32(0xffffffff >>
1596                                                                  (32 - width));
1597                                         width = 0;
1598                                 } else {
1599                                         mask[idx] = RTE_BE32(0xffffffff);
1600                                         width -= 32;
1601                                 }
1602                                 if (!width)
1603                                         break;
1604                                 ++idx;
1605                         }
1606                         if (data->offset < 64) {
1607                                 info[idx] = (struct field_modify_info){4,
1608                                                 4 * idx,
1609                                                 MLX5_MODI_OUT_DIPV6_63_32};
1610                                 if (width < 32) {
1611                                         mask[idx] =
1612                                                 rte_cpu_to_be_32(0xffffffff >>
1613                                                                  (32 - width));
1614                                         width = 0;
1615                                 } else {
1616                                         mask[idx] = RTE_BE32(0xffffffff);
1617                                         width -= 32;
1618                                 }
1619                                 if (!width)
1620                                         break;
1621                                 ++idx;
1622                         }
1623                         if (data->offset < 96) {
1624                                 info[idx] = (struct field_modify_info){4,
1625                                                 4 * idx,
1626                                                 MLX5_MODI_OUT_DIPV6_95_64};
1627                                 if (width < 32) {
1628                                         mask[idx] =
1629                                                 rte_cpu_to_be_32(0xffffffff >>
1630                                                                  (32 - width));
1631                                         width = 0;
1632                                 } else {
1633                                         mask[idx] = RTE_BE32(0xffffffff);
1634                                         width -= 32;
1635                                 }
1636                                 if (!width)
1637                                         break;
1638                                 ++idx;
1639                         }
1640                         info[idx] = (struct field_modify_info){4, 4 * idx,
1641                                                 MLX5_MODI_OUT_DIPV6_127_96};
1642                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1643                                                      (32 - width));
1644                 } else {
1645                         if (data->offset < 32)
1646                                 info[idx++] = (struct field_modify_info){4, 0,
1647                                                 MLX5_MODI_OUT_DIPV6_31_0};
1648                         if (data->offset < 64)
1649                                 info[idx++] = (struct field_modify_info){4, 0,
1650                                                 MLX5_MODI_OUT_DIPV6_63_32};
1651                         if (data->offset < 96)
1652                                 info[idx++] = (struct field_modify_info){4, 0,
1653                                                 MLX5_MODI_OUT_DIPV6_95_64};
1654                         if (data->offset < 128)
1655                                 info[idx++] = (struct field_modify_info){4, 0,
1656                                                 MLX5_MODI_OUT_DIPV6_127_96};
1657                 }
1658                 break;
1659         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1660                 info[idx] = (struct field_modify_info){2, 0,
1661                                         MLX5_MODI_OUT_TCP_SPORT};
1662                 if (mask)
1663                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1664                 break;
1665         case RTE_FLOW_FIELD_TCP_PORT_DST:
1666                 info[idx] = (struct field_modify_info){2, 0,
1667                                         MLX5_MODI_OUT_TCP_DPORT};
1668                 if (mask)
1669                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1670                 break;
1671         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1672                 info[idx] = (struct field_modify_info){4, 0,
1673                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1674                 if (mask)
1675                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1676                                                      (32 - width));
1677                 break;
1678         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1679                 info[idx] = (struct field_modify_info){4, 0,
1680                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1681                 if (mask)
1682                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1683                                                      (32 - width));
1684                 break;
1685         case RTE_FLOW_FIELD_TCP_FLAGS:
1686                 info[idx] = (struct field_modify_info){1, 0,
1687                                         MLX5_MODI_OUT_TCP_FLAGS};
1688                 if (mask)
1689                         mask[idx] = 0x3f >> (6 - width);
1690                 break;
1691         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1692                 info[idx] = (struct field_modify_info){2, 0,
1693                                         MLX5_MODI_OUT_UDP_SPORT};
1694                 if (mask)
1695                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1696                 break;
1697         case RTE_FLOW_FIELD_UDP_PORT_DST:
1698                 info[idx] = (struct field_modify_info){2, 0,
1699                                         MLX5_MODI_OUT_UDP_DPORT};
1700                 if (mask)
1701                         mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1702                 break;
1703         case RTE_FLOW_FIELD_VXLAN_VNI:
1704                 /* not supported yet */
1705                 break;
1706         case RTE_FLOW_FIELD_GENEVE_VNI:
1707                 /* not supported yet*/
1708                 break;
1709         case RTE_FLOW_FIELD_GTP_TEID:
1710                 info[idx] = (struct field_modify_info){4, 0,
1711                                         MLX5_MODI_GTP_TEID};
1712                 if (mask)
1713                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1714                                                      (32 - width));
1715                 break;
1716         case RTE_FLOW_FIELD_TAG:
1717                 {
1718                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1719                                                    data->level, error);
1720                         if (reg < 0)
1721                                 return;
1722                         MLX5_ASSERT(reg != REG_NON);
1723                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1724                         info[idx] = (struct field_modify_info){4, 0,
1725                                                 reg_to_field[reg]};
1726                         if (mask)
1727                                 mask[idx] =
1728                                         rte_cpu_to_be_32(0xffffffff >>
1729                                                          (32 - width));
1730                 }
1731                 break;
1732         case RTE_FLOW_FIELD_MARK:
1733                 {
1734                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1735                                                        0, error);
1736                         if (reg < 0)
1737                                 return;
1738                         MLX5_ASSERT(reg != REG_NON);
1739                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1740                         info[idx] = (struct field_modify_info){4, 0,
1741                                                 reg_to_field[reg]};
1742                         if (mask)
1743                                 mask[idx] =
1744                                         rte_cpu_to_be_32(0xffffffff >>
1745                                                          (32 - width));
1746                 }
1747                 break;
1748         case RTE_FLOW_FIELD_META:
1749                 {
1750                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1751                         if (reg < 0)
1752                                 return;
1753                         MLX5_ASSERT(reg != REG_NON);
1754                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1755                         info[idx] = (struct field_modify_info){4, 0,
1756                                                 reg_to_field[reg]};
1757                         if (mask)
1758                                 mask[idx] =
1759                                         rte_cpu_to_be_32(0xffffffff >>
1760                                                          (32 - width));
1761                 }
1762                 break;
1763         case RTE_FLOW_FIELD_POINTER:
1764         case RTE_FLOW_FIELD_VALUE:
1765                 if (data->field == RTE_FLOW_FIELD_POINTER)
1766                         memcpy(&val, (void *)(uintptr_t)data->value,
1767                                sizeof(uint64_t));
1768                 else
1769                         val = data->value;
1770                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1771                         if (mask[idx]) {
1772                                 if (dst_width > 16) {
1773                                         value[idx] = rte_cpu_to_be_32(val);
1774                                         val >>= 32;
1775                                 } else if (dst_width > 8) {
1776                                         value[idx] = rte_cpu_to_be_16(val);
1777                                         val >>= 16;
1778                                 } else {
1779                                         value[idx] = (uint8_t)val;
1780                                         val >>= 8;
1781                                 }
1782                                 if (!val)
1783                                         break;
1784                         }
1785                 }
1786                 break;
1787         default:
1788                 MLX5_ASSERT(false);
1789                 break;
1790         }
1791 }
1792
1793 /**
1794  * Convert modify_field action to DV specification.
1795  *
1796  * @param[in] dev
1797  *   Pointer to the rte_eth_dev structure.
1798  * @param[in,out] resource
1799  *   Pointer to the modify-header resource.
1800  * @param[in] action
1801  *   Pointer to action specification.
1802  * @param[in] attr
1803  *   Attributes of flow that includes this item.
1804  * @param[out] error
1805  *   Pointer to the error structure.
1806  *
1807  * @return
1808  *   0 on success, a negative errno value otherwise and rte_errno is set.
1809  */
1810 static int
1811 flow_dv_convert_action_modify_field
1812                         (struct rte_eth_dev *dev,
1813                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1814                          const struct rte_flow_action *action,
1815                          const struct rte_flow_attr *attr,
1816                          struct rte_flow_error *error)
1817 {
1818         const struct rte_flow_action_modify_field *conf =
1819                 (const struct rte_flow_action_modify_field *)(action->conf);
1820         struct rte_flow_item item;
1821         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1822                                                                 {0, 0, 0} };
1823         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1824                                                                 {0, 0, 0} };
1825         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1826         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1827         uint32_t type;
1828         uint32_t dst_width = mlx5_flow_item_field_width(conf->dst.field);
1829
1830         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1831                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1832                 type = MLX5_MODIFICATION_TYPE_SET;
1833                 /** For SET fill the destination field (field) first. */
1834                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1835                         value, conf->width, dst_width, dev, attr, error);
1836                 /** Then copy immediate value from source as per mask. */
1837                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1838                         value, conf->width, dst_width, dev, attr, error);
1839                 item.spec = &value;
1840         } else {
1841                 type = MLX5_MODIFICATION_TYPE_COPY;
1842                 /** For COPY fill the destination field (dcopy) without mask. */
1843                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1844                         value, conf->width, dst_width, dev, attr, error);
1845                 /** Then construct the source field (field) with mask. */
1846                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1847                         value, conf->width, dst_width, dev, attr, error);
1848         }
1849         item.mask = &mask;
1850         return flow_dv_convert_modify_action(&item,
1851                         field, dcopy, resource, type, error);
1852 }
1853
1854 /**
1855  * Validate MARK item.
1856  *
1857  * @param[in] dev
1858  *   Pointer to the rte_eth_dev structure.
1859  * @param[in] item
1860  *   Item specification.
1861  * @param[in] attr
1862  *   Attributes of flow that includes this item.
1863  * @param[out] error
1864  *   Pointer to error structure.
1865  *
1866  * @return
1867  *   0 on success, a negative errno value otherwise and rte_errno is set.
1868  */
1869 static int
1870 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1871                            const struct rte_flow_item *item,
1872                            const struct rte_flow_attr *attr __rte_unused,
1873                            struct rte_flow_error *error)
1874 {
1875         struct mlx5_priv *priv = dev->data->dev_private;
1876         struct mlx5_dev_config *config = &priv->config;
1877         const struct rte_flow_item_mark *spec = item->spec;
1878         const struct rte_flow_item_mark *mask = item->mask;
1879         const struct rte_flow_item_mark nic_mask = {
1880                 .id = priv->sh->dv_mark_mask,
1881         };
1882         int ret;
1883
1884         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1885                 return rte_flow_error_set(error, ENOTSUP,
1886                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1887                                           "extended metadata feature"
1888                                           " isn't enabled");
1889         if (!mlx5_flow_ext_mreg_supported(dev))
1890                 return rte_flow_error_set(error, ENOTSUP,
1891                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1892                                           "extended metadata register"
1893                                           " isn't supported");
1894         if (!nic_mask.id)
1895                 return rte_flow_error_set(error, ENOTSUP,
1896                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1897                                           "extended metadata register"
1898                                           " isn't available");
1899         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1900         if (ret < 0)
1901                 return ret;
1902         if (!spec)
1903                 return rte_flow_error_set(error, EINVAL,
1904                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1905                                           item->spec,
1906                                           "data cannot be empty");
1907         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1908                 return rte_flow_error_set(error, EINVAL,
1909                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1910                                           &spec->id,
1911                                           "mark id exceeds the limit");
1912         if (!mask)
1913                 mask = &nic_mask;
1914         if (!mask->id)
1915                 return rte_flow_error_set(error, EINVAL,
1916                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1917                                         "mask cannot be zero");
1918
1919         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1920                                         (const uint8_t *)&nic_mask,
1921                                         sizeof(struct rte_flow_item_mark),
1922                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1923         if (ret < 0)
1924                 return ret;
1925         return 0;
1926 }
1927
1928 /**
1929  * Validate META item.
1930  *
1931  * @param[in] dev
1932  *   Pointer to the rte_eth_dev structure.
1933  * @param[in] item
1934  *   Item specification.
1935  * @param[in] attr
1936  *   Attributes of flow that includes this item.
1937  * @param[out] error
1938  *   Pointer to error structure.
1939  *
1940  * @return
1941  *   0 on success, a negative errno value otherwise and rte_errno is set.
1942  */
1943 static int
1944 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1945                            const struct rte_flow_item *item,
1946                            const struct rte_flow_attr *attr,
1947                            struct rte_flow_error *error)
1948 {
1949         struct mlx5_priv *priv = dev->data->dev_private;
1950         struct mlx5_dev_config *config = &priv->config;
1951         const struct rte_flow_item_meta *spec = item->spec;
1952         const struct rte_flow_item_meta *mask = item->mask;
1953         struct rte_flow_item_meta nic_mask = {
1954                 .data = UINT32_MAX
1955         };
1956         int reg;
1957         int ret;
1958
1959         if (!spec)
1960                 return rte_flow_error_set(error, EINVAL,
1961                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1962                                           item->spec,
1963                                           "data cannot be empty");
1964         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1965                 if (!mlx5_flow_ext_mreg_supported(dev))
1966                         return rte_flow_error_set(error, ENOTSUP,
1967                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1968                                           "extended metadata register"
1969                                           " isn't supported");
1970                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1971                 if (reg < 0)
1972                         return reg;
1973                 if (reg == REG_NON)
1974                         return rte_flow_error_set(error, ENOTSUP,
1975                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1976                                         "unavalable extended metadata register");
1977                 if (reg == REG_B)
1978                         return rte_flow_error_set(error, ENOTSUP,
1979                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1980                                           "match on reg_b "
1981                                           "isn't supported");
1982                 if (reg != REG_A)
1983                         nic_mask.data = priv->sh->dv_meta_mask;
1984         } else {
1985                 if (attr->transfer)
1986                         return rte_flow_error_set(error, ENOTSUP,
1987                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1988                                         "extended metadata feature "
1989                                         "should be enabled when "
1990                                         "meta item is requested "
1991                                         "with e-switch mode ");
1992                 if (attr->ingress)
1993                         return rte_flow_error_set(error, ENOTSUP,
1994                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1995                                         "match on metadata for ingress "
1996                                         "is not supported in legacy "
1997                                         "metadata mode");
1998         }
1999         if (!mask)
2000                 mask = &rte_flow_item_meta_mask;
2001         if (!mask->data)
2002                 return rte_flow_error_set(error, EINVAL,
2003                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2004                                         "mask cannot be zero");
2005
2006         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2007                                         (const uint8_t *)&nic_mask,
2008                                         sizeof(struct rte_flow_item_meta),
2009                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2010         return ret;
2011 }
2012
2013 /**
2014  * Validate TAG item.
2015  *
2016  * @param[in] dev
2017  *   Pointer to the rte_eth_dev structure.
2018  * @param[in] item
2019  *   Item specification.
2020  * @param[in] attr
2021  *   Attributes of flow that includes this item.
2022  * @param[out] error
2023  *   Pointer to error structure.
2024  *
2025  * @return
2026  *   0 on success, a negative errno value otherwise and rte_errno is set.
2027  */
2028 static int
2029 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2030                           const struct rte_flow_item *item,
2031                           const struct rte_flow_attr *attr __rte_unused,
2032                           struct rte_flow_error *error)
2033 {
2034         const struct rte_flow_item_tag *spec = item->spec;
2035         const struct rte_flow_item_tag *mask = item->mask;
2036         const struct rte_flow_item_tag nic_mask = {
2037                 .data = RTE_BE32(UINT32_MAX),
2038                 .index = 0xff,
2039         };
2040         int ret;
2041
2042         if (!mlx5_flow_ext_mreg_supported(dev))
2043                 return rte_flow_error_set(error, ENOTSUP,
2044                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2045                                           "extensive metadata register"
2046                                           " isn't supported");
2047         if (!spec)
2048                 return rte_flow_error_set(error, EINVAL,
2049                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2050                                           item->spec,
2051                                           "data cannot be empty");
2052         if (!mask)
2053                 mask = &rte_flow_item_tag_mask;
2054         if (!mask->data)
2055                 return rte_flow_error_set(error, EINVAL,
2056                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2057                                         "mask cannot be zero");
2058
2059         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2060                                         (const uint8_t *)&nic_mask,
2061                                         sizeof(struct rte_flow_item_tag),
2062                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2063         if (ret < 0)
2064                 return ret;
2065         if (mask->index != 0xff)
2066                 return rte_flow_error_set(error, EINVAL,
2067                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2068                                           "partial mask for tag index"
2069                                           " is not supported");
2070         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2071         if (ret < 0)
2072                 return ret;
2073         MLX5_ASSERT(ret != REG_NON);
2074         return 0;
2075 }
2076
2077 /**
2078  * Validate vport item.
2079  *
2080  * @param[in] dev
2081  *   Pointer to the rte_eth_dev structure.
2082  * @param[in] item
2083  *   Item specification.
2084  * @param[in] attr
2085  *   Attributes of flow that includes this item.
2086  * @param[in] item_flags
2087  *   Bit-fields that holds the items detected until now.
2088  * @param[out] error
2089  *   Pointer to error structure.
2090  *
2091  * @return
2092  *   0 on success, a negative errno value otherwise and rte_errno is set.
2093  */
2094 static int
2095 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2096                               const struct rte_flow_item *item,
2097                               const struct rte_flow_attr *attr,
2098                               uint64_t item_flags,
2099                               struct rte_flow_error *error)
2100 {
2101         const struct rte_flow_item_port_id *spec = item->spec;
2102         const struct rte_flow_item_port_id *mask = item->mask;
2103         const struct rte_flow_item_port_id switch_mask = {
2104                         .id = 0xffffffff,
2105         };
2106         struct mlx5_priv *esw_priv;
2107         struct mlx5_priv *dev_priv;
2108         int ret;
2109
2110         if (!attr->transfer)
2111                 return rte_flow_error_set(error, EINVAL,
2112                                           RTE_FLOW_ERROR_TYPE_ITEM,
2113                                           NULL,
2114                                           "match on port id is valid only"
2115                                           " when transfer flag is enabled");
2116         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2117                 return rte_flow_error_set(error, ENOTSUP,
2118                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2119                                           "multiple source ports are not"
2120                                           " supported");
2121         if (!mask)
2122                 mask = &switch_mask;
2123         if (mask->id != 0xffffffff)
2124                 return rte_flow_error_set(error, ENOTSUP,
2125                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2126                                            mask,
2127                                            "no support for partial mask on"
2128                                            " \"id\" field");
2129         ret = mlx5_flow_item_acceptable
2130                                 (item, (const uint8_t *)mask,
2131                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2132                                  sizeof(struct rte_flow_item_port_id),
2133                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2134         if (ret)
2135                 return ret;
2136         if (!spec)
2137                 return 0;
2138         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2139         if (!esw_priv)
2140                 return rte_flow_error_set(error, rte_errno,
2141                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2142                                           "failed to obtain E-Switch info for"
2143                                           " port");
2144         dev_priv = mlx5_dev_to_eswitch_info(dev);
2145         if (!dev_priv)
2146                 return rte_flow_error_set(error, rte_errno,
2147                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2148                                           NULL,
2149                                           "failed to obtain E-Switch info");
2150         if (esw_priv->domain_id != dev_priv->domain_id)
2151                 return rte_flow_error_set(error, EINVAL,
2152                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2153                                           "cannot match on a port from a"
2154                                           " different E-Switch");
2155         return 0;
2156 }
2157
2158 /**
2159  * Validate VLAN item.
2160  *
2161  * @param[in] item
2162  *   Item specification.
2163  * @param[in] item_flags
2164  *   Bit-fields that holds the items detected until now.
2165  * @param[in] dev
2166  *   Ethernet device flow is being created on.
2167  * @param[out] error
2168  *   Pointer to error structure.
2169  *
2170  * @return
2171  *   0 on success, a negative errno value otherwise and rte_errno is set.
2172  */
2173 static int
2174 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2175                            uint64_t item_flags,
2176                            struct rte_eth_dev *dev,
2177                            struct rte_flow_error *error)
2178 {
2179         const struct rte_flow_item_vlan *mask = item->mask;
2180         const struct rte_flow_item_vlan nic_mask = {
2181                 .tci = RTE_BE16(UINT16_MAX),
2182                 .inner_type = RTE_BE16(UINT16_MAX),
2183                 .has_more_vlan = 1,
2184         };
2185         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2186         int ret;
2187         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2188                                         MLX5_FLOW_LAYER_INNER_L4) :
2189                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2190                                         MLX5_FLOW_LAYER_OUTER_L4);
2191         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2192                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2193
2194         if (item_flags & vlanm)
2195                 return rte_flow_error_set(error, EINVAL,
2196                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2197                                           "multiple VLAN layers not supported");
2198         else if ((item_flags & l34m) != 0)
2199                 return rte_flow_error_set(error, EINVAL,
2200                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2201                                           "VLAN cannot follow L3/L4 layer");
2202         if (!mask)
2203                 mask = &rte_flow_item_vlan_mask;
2204         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2205                                         (const uint8_t *)&nic_mask,
2206                                         sizeof(struct rte_flow_item_vlan),
2207                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2208         if (ret)
2209                 return ret;
2210         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2211                 struct mlx5_priv *priv = dev->data->dev_private;
2212
2213                 if (priv->vmwa_context) {
2214                         /*
2215                          * Non-NULL context means we have a virtual machine
2216                          * and SR-IOV enabled, we have to create VLAN interface
2217                          * to make hypervisor to setup E-Switch vport
2218                          * context correctly. We avoid creating the multiple
2219                          * VLAN interfaces, so we cannot support VLAN tag mask.
2220                          */
2221                         return rte_flow_error_set(error, EINVAL,
2222                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2223                                                   item,
2224                                                   "VLAN tag mask is not"
2225                                                   " supported in virtual"
2226                                                   " environment");
2227                 }
2228         }
2229         return 0;
2230 }
2231
2232 /*
2233  * GTP flags are contained in 1 byte of the format:
2234  * -------------------------------------------
2235  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2236  * |-----------------------------------------|
2237  * | value | Version | PT | Res | E | S | PN |
2238  * -------------------------------------------
2239  *
2240  * Matching is supported only for GTP flags E, S, PN.
2241  */
2242 #define MLX5_GTP_FLAGS_MASK     0x07
2243
2244 /**
2245  * Validate GTP item.
2246  *
2247  * @param[in] dev
2248  *   Pointer to the rte_eth_dev structure.
2249  * @param[in] item
2250  *   Item specification.
2251  * @param[in] item_flags
2252  *   Bit-fields that holds the items detected until now.
2253  * @param[out] error
2254  *   Pointer to error structure.
2255  *
2256  * @return
2257  *   0 on success, a negative errno value otherwise and rte_errno is set.
2258  */
2259 static int
2260 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2261                           const struct rte_flow_item *item,
2262                           uint64_t item_flags,
2263                           struct rte_flow_error *error)
2264 {
2265         struct mlx5_priv *priv = dev->data->dev_private;
2266         const struct rte_flow_item_gtp *spec = item->spec;
2267         const struct rte_flow_item_gtp *mask = item->mask;
2268         const struct rte_flow_item_gtp nic_mask = {
2269                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2270                 .msg_type = 0xff,
2271                 .teid = RTE_BE32(0xffffffff),
2272         };
2273
2274         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2275                 return rte_flow_error_set(error, ENOTSUP,
2276                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2277                                           "GTP support is not enabled");
2278         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2279                 return rte_flow_error_set(error, ENOTSUP,
2280                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2281                                           "multiple tunnel layers not"
2282                                           " supported");
2283         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2284                 return rte_flow_error_set(error, EINVAL,
2285                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2286                                           "no outer UDP layer found");
2287         if (!mask)
2288                 mask = &rte_flow_item_gtp_mask;
2289         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2290                 return rte_flow_error_set(error, ENOTSUP,
2291                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2292                                           "Match is supported for GTP"
2293                                           " flags only");
2294         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2295                                          (const uint8_t *)&nic_mask,
2296                                          sizeof(struct rte_flow_item_gtp),
2297                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2298 }
2299
2300 /**
2301  * Validate GTP PSC item.
2302  *
2303  * @param[in] item
2304  *   Item specification.
2305  * @param[in] last_item
2306  *   Previous validated item in the pattern items.
2307  * @param[in] gtp_item
2308  *   Previous GTP item specification.
2309  * @param[in] attr
2310  *   Pointer to flow attributes.
2311  * @param[out] error
2312  *   Pointer to error structure.
2313  *
2314  * @return
2315  *   0 on success, a negative errno value otherwise and rte_errno is set.
2316  */
2317 static int
2318 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2319                               uint64_t last_item,
2320                               const struct rte_flow_item *gtp_item,
2321                               const struct rte_flow_attr *attr,
2322                               struct rte_flow_error *error)
2323 {
2324         const struct rte_flow_item_gtp *gtp_spec;
2325         const struct rte_flow_item_gtp *gtp_mask;
2326         const struct rte_flow_item_gtp_psc *spec;
2327         const struct rte_flow_item_gtp_psc *mask;
2328         const struct rte_flow_item_gtp_psc nic_mask = {
2329                 .pdu_type = 0xFF,
2330                 .qfi = 0xFF,
2331         };
2332
2333         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2334                 return rte_flow_error_set
2335                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2336                          "GTP PSC item must be preceded with GTP item");
2337         gtp_spec = gtp_item->spec;
2338         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2339         /* GTP spec and E flag is requested to match zero. */
2340         if (gtp_spec &&
2341                 (gtp_mask->v_pt_rsv_flags &
2342                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2343                 return rte_flow_error_set
2344                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2345                          "GTP E flag must be 1 to match GTP PSC");
2346         /* Check the flow is not created in group zero. */
2347         if (!attr->transfer && !attr->group)
2348                 return rte_flow_error_set
2349                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2350                          "GTP PSC is not supported for group 0");
2351         /* GTP spec is here and E flag is requested to match zero. */
2352         if (!item->spec)
2353                 return 0;
2354         spec = item->spec;
2355         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2356         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2357                 return rte_flow_error_set
2358                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2359                          "PDU type should be smaller than 16");
2360         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2361                                          (const uint8_t *)&nic_mask,
2362                                          sizeof(struct rte_flow_item_gtp_psc),
2363                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2364 }
2365
2366 /**
2367  * Validate IPV4 item.
2368  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2369  * add specific validation of fragment_offset field,
2370  *
2371  * @param[in] item
2372  *   Item specification.
2373  * @param[in] item_flags
2374  *   Bit-fields that holds the items detected until now.
2375  * @param[out] error
2376  *   Pointer to error structure.
2377  *
2378  * @return
2379  *   0 on success, a negative errno value otherwise and rte_errno is set.
2380  */
2381 static int
2382 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2383                            uint64_t item_flags,
2384                            uint64_t last_item,
2385                            uint16_t ether_type,
2386                            struct rte_flow_error *error)
2387 {
2388         int ret;
2389         const struct rte_flow_item_ipv4 *spec = item->spec;
2390         const struct rte_flow_item_ipv4 *last = item->last;
2391         const struct rte_flow_item_ipv4 *mask = item->mask;
2392         rte_be16_t fragment_offset_spec = 0;
2393         rte_be16_t fragment_offset_last = 0;
2394         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2395                 .hdr = {
2396                         .src_addr = RTE_BE32(0xffffffff),
2397                         .dst_addr = RTE_BE32(0xffffffff),
2398                         .type_of_service = 0xff,
2399                         .fragment_offset = RTE_BE16(0xffff),
2400                         .next_proto_id = 0xff,
2401                         .time_to_live = 0xff,
2402                 },
2403         };
2404
2405         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2406                                            ether_type, &nic_ipv4_mask,
2407                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2408         if (ret < 0)
2409                 return ret;
2410         if (spec && mask)
2411                 fragment_offset_spec = spec->hdr.fragment_offset &
2412                                        mask->hdr.fragment_offset;
2413         if (!fragment_offset_spec)
2414                 return 0;
2415         /*
2416          * spec and mask are valid, enforce using full mask to make sure the
2417          * complete value is used correctly.
2418          */
2419         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2420                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2421                 return rte_flow_error_set(error, EINVAL,
2422                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2423                                           item, "must use full mask for"
2424                                           " fragment_offset");
2425         /*
2426          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2427          * indicating this is 1st fragment of fragmented packet.
2428          * This is not yet supported in MLX5, return appropriate error message.
2429          */
2430         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2431                 return rte_flow_error_set(error, ENOTSUP,
2432                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2433                                           "match on first fragment not "
2434                                           "supported");
2435         if (fragment_offset_spec && !last)
2436                 return rte_flow_error_set(error, ENOTSUP,
2437                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2438                                           "specified value not supported");
2439         /* spec and last are valid, validate the specified range. */
2440         fragment_offset_last = last->hdr.fragment_offset &
2441                                mask->hdr.fragment_offset;
2442         /*
2443          * Match on fragment_offset spec 0x2001 and last 0x3fff
2444          * means MF is 1 and frag-offset is > 0.
2445          * This packet is fragment 2nd and onward, excluding last.
2446          * This is not yet supported in MLX5, return appropriate
2447          * error message.
2448          */
2449         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2450             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2451                 return rte_flow_error_set(error, ENOTSUP,
2452                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2453                                           last, "match on following "
2454                                           "fragments not supported");
2455         /*
2456          * Match on fragment_offset spec 0x0001 and last 0x1fff
2457          * means MF is 0 and frag-offset is > 0.
2458          * This packet is last fragment of fragmented packet.
2459          * This is not yet supported in MLX5, return appropriate
2460          * error message.
2461          */
2462         if (fragment_offset_spec == RTE_BE16(1) &&
2463             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2464                 return rte_flow_error_set(error, ENOTSUP,
2465                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2466                                           last, "match on last "
2467                                           "fragment not supported");
2468         /*
2469          * Match on fragment_offset spec 0x0001 and last 0x3fff
2470          * means MF and/or frag-offset is not 0.
2471          * This is a fragmented packet.
2472          * Other range values are invalid and rejected.
2473          */
2474         if (!(fragment_offset_spec == RTE_BE16(1) &&
2475               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2476                 return rte_flow_error_set(error, ENOTSUP,
2477                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2478                                           "specified range not supported");
2479         return 0;
2480 }
2481
2482 /**
2483  * Validate IPV6 fragment extension item.
2484  *
2485  * @param[in] item
2486  *   Item specification.
2487  * @param[in] item_flags
2488  *   Bit-fields that holds the items detected until now.
2489  * @param[out] error
2490  *   Pointer to error structure.
2491  *
2492  * @return
2493  *   0 on success, a negative errno value otherwise and rte_errno is set.
2494  */
2495 static int
2496 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2497                                     uint64_t item_flags,
2498                                     struct rte_flow_error *error)
2499 {
2500         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2501         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2502         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2503         rte_be16_t frag_data_spec = 0;
2504         rte_be16_t frag_data_last = 0;
2505         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2506         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2507                                       MLX5_FLOW_LAYER_OUTER_L4;
2508         int ret = 0;
2509         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2510                 .hdr = {
2511                         .next_header = 0xff,
2512                         .frag_data = RTE_BE16(0xffff),
2513                 },
2514         };
2515
2516         if (item_flags & l4m)
2517                 return rte_flow_error_set(error, EINVAL,
2518                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2519                                           "ipv6 fragment extension item cannot "
2520                                           "follow L4 item.");
2521         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2522             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2523                 return rte_flow_error_set(error, EINVAL,
2524                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2525                                           "ipv6 fragment extension item must "
2526                                           "follow ipv6 item");
2527         if (spec && mask)
2528                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2529         if (!frag_data_spec)
2530                 return 0;
2531         /*
2532          * spec and mask are valid, enforce using full mask to make sure the
2533          * complete value is used correctly.
2534          */
2535         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2536                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2537                 return rte_flow_error_set(error, EINVAL,
2538                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2539                                           item, "must use full mask for"
2540                                           " frag_data");
2541         /*
2542          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2543          * This is 1st fragment of fragmented packet.
2544          */
2545         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2546                 return rte_flow_error_set(error, ENOTSUP,
2547                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2548                                           "match on first fragment not "
2549                                           "supported");
2550         if (frag_data_spec && !last)
2551                 return rte_flow_error_set(error, EINVAL,
2552                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2553                                           "specified value not supported");
2554         ret = mlx5_flow_item_acceptable
2555                                 (item, (const uint8_t *)mask,
2556                                  (const uint8_t *)&nic_mask,
2557                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2558                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2559         if (ret)
2560                 return ret;
2561         /* spec and last are valid, validate the specified range. */
2562         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2563         /*
2564          * Match on frag_data spec 0x0009 and last 0xfff9
2565          * means M is 1 and frag-offset is > 0.
2566          * This packet is fragment 2nd and onward, excluding last.
2567          * This is not yet supported in MLX5, return appropriate
2568          * error message.
2569          */
2570         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2571                                        RTE_IPV6_EHDR_MF_MASK) &&
2572             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2573                 return rte_flow_error_set(error, ENOTSUP,
2574                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2575                                           last, "match on following "
2576                                           "fragments not supported");
2577         /*
2578          * Match on frag_data spec 0x0008 and last 0xfff8
2579          * means M is 0 and frag-offset is > 0.
2580          * This packet is last fragment of fragmented packet.
2581          * This is not yet supported in MLX5, return appropriate
2582          * error message.
2583          */
2584         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2585             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2586                 return rte_flow_error_set(error, ENOTSUP,
2587                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2588                                           last, "match on last "
2589                                           "fragment not supported");
2590         /* Other range values are invalid and rejected. */
2591         return rte_flow_error_set(error, EINVAL,
2592                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2593                                   "specified range not supported");
2594 }
2595
2596 /**
2597  * Validate the pop VLAN action.
2598  *
2599  * @param[in] dev
2600  *   Pointer to the rte_eth_dev structure.
2601  * @param[in] action_flags
2602  *   Holds the actions detected until now.
2603  * @param[in] action
2604  *   Pointer to the pop vlan action.
2605  * @param[in] item_flags
2606  *   The items found in this flow rule.
2607  * @param[in] attr
2608  *   Pointer to flow attributes.
2609  * @param[out] error
2610  *   Pointer to error structure.
2611  *
2612  * @return
2613  *   0 on success, a negative errno value otherwise and rte_errno is set.
2614  */
2615 static int
2616 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2617                                  uint64_t action_flags,
2618                                  const struct rte_flow_action *action,
2619                                  uint64_t item_flags,
2620                                  const struct rte_flow_attr *attr,
2621                                  struct rte_flow_error *error)
2622 {
2623         const struct mlx5_priv *priv = dev->data->dev_private;
2624
2625         (void)action;
2626         (void)attr;
2627         if (!priv->sh->pop_vlan_action)
2628                 return rte_flow_error_set(error, ENOTSUP,
2629                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2630                                           NULL,
2631                                           "pop vlan action is not supported");
2632         if (attr->egress)
2633                 return rte_flow_error_set(error, ENOTSUP,
2634                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2635                                           NULL,
2636                                           "pop vlan action not supported for "
2637                                           "egress");
2638         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2639                 return rte_flow_error_set(error, ENOTSUP,
2640                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2641                                           "no support for multiple VLAN "
2642                                           "actions");
2643         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2644         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2645             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2646                 return rte_flow_error_set(error, ENOTSUP,
2647                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2648                                           NULL,
2649                                           "cannot pop vlan after decap without "
2650                                           "match on inner vlan in the flow");
2651         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2652         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2653             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2654                 return rte_flow_error_set(error, ENOTSUP,
2655                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2656                                           NULL,
2657                                           "cannot pop vlan without a "
2658                                           "match on (outer) vlan in the flow");
2659         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2660                 return rte_flow_error_set(error, EINVAL,
2661                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2662                                           "wrong action order, port_id should "
2663                                           "be after pop VLAN action");
2664         if (!attr->transfer && priv->representor)
2665                 return rte_flow_error_set(error, ENOTSUP,
2666                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2667                                           "pop vlan action for VF representor "
2668                                           "not supported on NIC table");
2669         return 0;
2670 }
2671
2672 /**
2673  * Get VLAN default info from vlan match info.
2674  *
2675  * @param[in] items
2676  *   the list of item specifications.
2677  * @param[out] vlan
2678  *   pointer VLAN info to fill to.
2679  *
2680  * @return
2681  *   0 on success, a negative errno value otherwise and rte_errno is set.
2682  */
2683 static void
2684 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2685                                   struct rte_vlan_hdr *vlan)
2686 {
2687         const struct rte_flow_item_vlan nic_mask = {
2688                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2689                                 MLX5DV_FLOW_VLAN_VID_MASK),
2690                 .inner_type = RTE_BE16(0xffff),
2691         };
2692
2693         if (items == NULL)
2694                 return;
2695         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2696                 int type = items->type;
2697
2698                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2699                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2700                         break;
2701         }
2702         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2703                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2704                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2705
2706                 /* If VLAN item in pattern doesn't contain data, return here. */
2707                 if (!vlan_v)
2708                         return;
2709                 if (!vlan_m)
2710                         vlan_m = &nic_mask;
2711                 /* Only full match values are accepted */
2712                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2713                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2714                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2715                         vlan->vlan_tci |=
2716                                 rte_be_to_cpu_16(vlan_v->tci &
2717                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2718                 }
2719                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2720                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2721                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2722                         vlan->vlan_tci |=
2723                                 rte_be_to_cpu_16(vlan_v->tci &
2724                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2725                 }
2726                 if (vlan_m->inner_type == nic_mask.inner_type)
2727                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2728                                                            vlan_m->inner_type);
2729         }
2730 }
2731
2732 /**
2733  * Validate the push VLAN action.
2734  *
2735  * @param[in] dev
2736  *   Pointer to the rte_eth_dev structure.
2737  * @param[in] action_flags
2738  *   Holds the actions detected until now.
2739  * @param[in] item_flags
2740  *   The items found in this flow rule.
2741  * @param[in] action
2742  *   Pointer to the action structure.
2743  * @param[in] attr
2744  *   Pointer to flow attributes
2745  * @param[out] error
2746  *   Pointer to error structure.
2747  *
2748  * @return
2749  *   0 on success, a negative errno value otherwise and rte_errno is set.
2750  */
2751 static int
2752 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2753                                   uint64_t action_flags,
2754                                   const struct rte_flow_item_vlan *vlan_m,
2755                                   const struct rte_flow_action *action,
2756                                   const struct rte_flow_attr *attr,
2757                                   struct rte_flow_error *error)
2758 {
2759         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2760         const struct mlx5_priv *priv = dev->data->dev_private;
2761
2762         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2763             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2764                 return rte_flow_error_set(error, EINVAL,
2765                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2766                                           "invalid vlan ethertype");
2767         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2768                 return rte_flow_error_set(error, EINVAL,
2769                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2770                                           "wrong action order, port_id should "
2771                                           "be after push VLAN");
2772         if (!attr->transfer && priv->representor)
2773                 return rte_flow_error_set(error, ENOTSUP,
2774                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2775                                           "push vlan action for VF representor "
2776                                           "not supported on NIC table");
2777         if (vlan_m &&
2778             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2779             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2780                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2781             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2782             !(mlx5_flow_find_action
2783                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2784                 return rte_flow_error_set(error, EINVAL,
2785                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2786                                           "not full match mask on VLAN PCP and "
2787                                           "there is no of_set_vlan_pcp action, "
2788                                           "push VLAN action cannot figure out "
2789                                           "PCP value");
2790         if (vlan_m &&
2791             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2792             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2793                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2794             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2795             !(mlx5_flow_find_action
2796                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2797                 return rte_flow_error_set(error, EINVAL,
2798                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2799                                           "not full match mask on VLAN VID and "
2800                                           "there is no of_set_vlan_vid action, "
2801                                           "push VLAN action cannot figure out "
2802                                           "VID value");
2803         (void)attr;
2804         return 0;
2805 }
2806
2807 /**
2808  * Validate the set VLAN PCP.
2809  *
2810  * @param[in] action_flags
2811  *   Holds the actions detected until now.
2812  * @param[in] actions
2813  *   Pointer to the list of actions remaining in the flow rule.
2814  * @param[out] error
2815  *   Pointer to error structure.
2816  *
2817  * @return
2818  *   0 on success, a negative errno value otherwise and rte_errno is set.
2819  */
2820 static int
2821 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2822                                      const struct rte_flow_action actions[],
2823                                      struct rte_flow_error *error)
2824 {
2825         const struct rte_flow_action *action = actions;
2826         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2827
2828         if (conf->vlan_pcp > 7)
2829                 return rte_flow_error_set(error, EINVAL,
2830                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2831                                           "VLAN PCP value is too big");
2832         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2833                 return rte_flow_error_set(error, ENOTSUP,
2834                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2835                                           "set VLAN PCP action must follow "
2836                                           "the push VLAN action");
2837         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2838                 return rte_flow_error_set(error, ENOTSUP,
2839                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2840                                           "Multiple VLAN PCP modification are "
2841                                           "not supported");
2842         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2843                 return rte_flow_error_set(error, EINVAL,
2844                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2845                                           "wrong action order, port_id should "
2846                                           "be after set VLAN PCP");
2847         return 0;
2848 }
2849
2850 /**
2851  * Validate the set VLAN VID.
2852  *
2853  * @param[in] item_flags
2854  *   Holds the items detected in this rule.
2855  * @param[in] action_flags
2856  *   Holds the actions detected until now.
2857  * @param[in] actions
2858  *   Pointer to the list of actions remaining in the flow rule.
2859  * @param[out] error
2860  *   Pointer to error structure.
2861  *
2862  * @return
2863  *   0 on success, a negative errno value otherwise and rte_errno is set.
2864  */
2865 static int
2866 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2867                                      uint64_t action_flags,
2868                                      const struct rte_flow_action actions[],
2869                                      struct rte_flow_error *error)
2870 {
2871         const struct rte_flow_action *action = actions;
2872         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2873
2874         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2875                 return rte_flow_error_set(error, EINVAL,
2876                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2877                                           "VLAN VID value is too big");
2878         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2879             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2880                 return rte_flow_error_set(error, ENOTSUP,
2881                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2882                                           "set VLAN VID action must follow push"
2883                                           " VLAN action or match on VLAN item");
2884         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2885                 return rte_flow_error_set(error, ENOTSUP,
2886                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2887                                           "Multiple VLAN VID modifications are "
2888                                           "not supported");
2889         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2890                 return rte_flow_error_set(error, EINVAL,
2891                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2892                                           "wrong action order, port_id should "
2893                                           "be after set VLAN VID");
2894         return 0;
2895 }
2896
2897 /*
2898  * Validate the FLAG action.
2899  *
2900  * @param[in] dev
2901  *   Pointer to the rte_eth_dev structure.
2902  * @param[in] action_flags
2903  *   Holds the actions detected until now.
2904  * @param[in] attr
2905  *   Pointer to flow attributes
2906  * @param[out] error
2907  *   Pointer to error structure.
2908  *
2909  * @return
2910  *   0 on success, a negative errno value otherwise and rte_errno is set.
2911  */
2912 static int
2913 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2914                              uint64_t action_flags,
2915                              const struct rte_flow_attr *attr,
2916                              struct rte_flow_error *error)
2917 {
2918         struct mlx5_priv *priv = dev->data->dev_private;
2919         struct mlx5_dev_config *config = &priv->config;
2920         int ret;
2921
2922         /* Fall back if no extended metadata register support. */
2923         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2924                 return mlx5_flow_validate_action_flag(action_flags, attr,
2925                                                       error);
2926         /* Extensive metadata mode requires registers. */
2927         if (!mlx5_flow_ext_mreg_supported(dev))
2928                 return rte_flow_error_set(error, ENOTSUP,
2929                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2930                                           "no metadata registers "
2931                                           "to support flag action");
2932         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2933                 return rte_flow_error_set(error, ENOTSUP,
2934                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2935                                           "extended metadata register"
2936                                           " isn't available");
2937         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2938         if (ret < 0)
2939                 return ret;
2940         MLX5_ASSERT(ret > 0);
2941         if (action_flags & MLX5_FLOW_ACTION_MARK)
2942                 return rte_flow_error_set(error, EINVAL,
2943                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2944                                           "can't mark and flag in same flow");
2945         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2946                 return rte_flow_error_set(error, EINVAL,
2947                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2948                                           "can't have 2 flag"
2949                                           " actions in same flow");
2950         return 0;
2951 }
2952
2953 /**
2954  * Validate MARK action.
2955  *
2956  * @param[in] dev
2957  *   Pointer to the rte_eth_dev structure.
2958  * @param[in] action
2959  *   Pointer to action.
2960  * @param[in] action_flags
2961  *   Holds the actions detected until now.
2962  * @param[in] attr
2963  *   Pointer to flow attributes
2964  * @param[out] error
2965  *   Pointer to error structure.
2966  *
2967  * @return
2968  *   0 on success, a negative errno value otherwise and rte_errno is set.
2969  */
2970 static int
2971 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2972                              const struct rte_flow_action *action,
2973                              uint64_t action_flags,
2974                              const struct rte_flow_attr *attr,
2975                              struct rte_flow_error *error)
2976 {
2977         struct mlx5_priv *priv = dev->data->dev_private;
2978         struct mlx5_dev_config *config = &priv->config;
2979         const struct rte_flow_action_mark *mark = action->conf;
2980         int ret;
2981
2982         if (is_tunnel_offload_active(dev))
2983                 return rte_flow_error_set(error, ENOTSUP,
2984                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2985                                           "no mark action "
2986                                           "if tunnel offload active");
2987         /* Fall back if no extended metadata register support. */
2988         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2989                 return mlx5_flow_validate_action_mark(action, action_flags,
2990                                                       attr, error);
2991         /* Extensive metadata mode requires registers. */
2992         if (!mlx5_flow_ext_mreg_supported(dev))
2993                 return rte_flow_error_set(error, ENOTSUP,
2994                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2995                                           "no metadata registers "
2996                                           "to support mark action");
2997         if (!priv->sh->dv_mark_mask)
2998                 return rte_flow_error_set(error, ENOTSUP,
2999                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3000                                           "extended metadata register"
3001                                           " isn't available");
3002         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3003         if (ret < 0)
3004                 return ret;
3005         MLX5_ASSERT(ret > 0);
3006         if (!mark)
3007                 return rte_flow_error_set(error, EINVAL,
3008                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3009                                           "configuration cannot be null");
3010         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3011                 return rte_flow_error_set(error, EINVAL,
3012                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3013                                           &mark->id,
3014                                           "mark id exceeds the limit");
3015         if (action_flags & MLX5_FLOW_ACTION_FLAG)
3016                 return rte_flow_error_set(error, EINVAL,
3017                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3018                                           "can't flag and mark in same flow");
3019         if (action_flags & MLX5_FLOW_ACTION_MARK)
3020                 return rte_flow_error_set(error, EINVAL,
3021                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3022                                           "can't have 2 mark actions in same"
3023                                           " flow");
3024         return 0;
3025 }
3026
3027 /**
3028  * Validate SET_META action.
3029  *
3030  * @param[in] dev
3031  *   Pointer to the rte_eth_dev structure.
3032  * @param[in] action
3033  *   Pointer to the action structure.
3034  * @param[in] action_flags
3035  *   Holds the actions detected until now.
3036  * @param[in] attr
3037  *   Pointer to flow attributes
3038  * @param[out] error
3039  *   Pointer to error structure.
3040  *
3041  * @return
3042  *   0 on success, a negative errno value otherwise and rte_errno is set.
3043  */
3044 static int
3045 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3046                                  const struct rte_flow_action *action,
3047                                  uint64_t action_flags __rte_unused,
3048                                  const struct rte_flow_attr *attr,
3049                                  struct rte_flow_error *error)
3050 {
3051         const struct rte_flow_action_set_meta *conf;
3052         uint32_t nic_mask = UINT32_MAX;
3053         int reg;
3054
3055         if (!mlx5_flow_ext_mreg_supported(dev))
3056                 return rte_flow_error_set(error, ENOTSUP,
3057                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3058                                           "extended metadata register"
3059                                           " isn't supported");
3060         reg = flow_dv_get_metadata_reg(dev, attr, error);
3061         if (reg < 0)
3062                 return reg;
3063         if (reg == REG_NON)
3064                 return rte_flow_error_set(error, ENOTSUP,
3065                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3066                                           "unavalable extended metadata register");
3067         if (reg != REG_A && reg != REG_B) {
3068                 struct mlx5_priv *priv = dev->data->dev_private;
3069
3070                 nic_mask = priv->sh->dv_meta_mask;
3071         }
3072         if (!(action->conf))
3073                 return rte_flow_error_set(error, EINVAL,
3074                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3075                                           "configuration cannot be null");
3076         conf = (const struct rte_flow_action_set_meta *)action->conf;
3077         if (!conf->mask)
3078                 return rte_flow_error_set(error, EINVAL,
3079                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3080                                           "zero mask doesn't have any effect");
3081         if (conf->mask & ~nic_mask)
3082                 return rte_flow_error_set(error, EINVAL,
3083                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3084                                           "meta data must be within reg C0");
3085         return 0;
3086 }
3087
3088 /**
3089  * Validate SET_TAG action.
3090  *
3091  * @param[in] dev
3092  *   Pointer to the rte_eth_dev structure.
3093  * @param[in] action
3094  *   Pointer to the action structure.
3095  * @param[in] action_flags
3096  *   Holds the actions detected until now.
3097  * @param[in] attr
3098  *   Pointer to flow attributes
3099  * @param[out] error
3100  *   Pointer to error structure.
3101  *
3102  * @return
3103  *   0 on success, a negative errno value otherwise and rte_errno is set.
3104  */
3105 static int
3106 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3107                                 const struct rte_flow_action *action,
3108                                 uint64_t action_flags,
3109                                 const struct rte_flow_attr *attr,
3110                                 struct rte_flow_error *error)
3111 {
3112         const struct rte_flow_action_set_tag *conf;
3113         const uint64_t terminal_action_flags =
3114                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3115                 MLX5_FLOW_ACTION_RSS;
3116         int ret;
3117
3118         if (!mlx5_flow_ext_mreg_supported(dev))
3119                 return rte_flow_error_set(error, ENOTSUP,
3120                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3121                                           "extensive metadata register"
3122                                           " isn't supported");
3123         if (!(action->conf))
3124                 return rte_flow_error_set(error, EINVAL,
3125                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3126                                           "configuration cannot be null");
3127         conf = (const struct rte_flow_action_set_tag *)action->conf;
3128         if (!conf->mask)
3129                 return rte_flow_error_set(error, EINVAL,
3130                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3131                                           "zero mask doesn't have any effect");
3132         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3133         if (ret < 0)
3134                 return ret;
3135         if (!attr->transfer && attr->ingress &&
3136             (action_flags & terminal_action_flags))
3137                 return rte_flow_error_set(error, EINVAL,
3138                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3139                                           "set_tag has no effect"
3140                                           " with terminal actions");
3141         return 0;
3142 }
3143
3144 /**
3145  * Validate count action.
3146  *
3147  * @param[in] dev
3148  *   Pointer to rte_eth_dev structure.
3149  * @param[in] action
3150  *   Pointer to the action structure.
3151  * @param[in] action_flags
3152  *   Holds the actions detected until now.
3153  * @param[out] error
3154  *   Pointer to error structure.
3155  *
3156  * @return
3157  *   0 on success, a negative errno value otherwise and rte_errno is set.
3158  */
3159 static int
3160 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3161                               const struct rte_flow_action *action,
3162                               uint64_t action_flags,
3163                               struct rte_flow_error *error)
3164 {
3165         struct mlx5_priv *priv = dev->data->dev_private;
3166         const struct rte_flow_action_count *count;
3167
3168         if (!priv->config.devx)
3169                 goto notsup_err;
3170         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3171                 return rte_flow_error_set(error, EINVAL,
3172                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3173                                           "duplicate count actions set");
3174         count = (const struct rte_flow_action_count *)action->conf;
3175         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3176             !priv->sh->flow_hit_aso_en)
3177                 return rte_flow_error_set(error, EINVAL,
3178                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3179                                           "old age and shared count combination is not supported");
3180 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3181         return 0;
3182 #endif
3183 notsup_err:
3184         return rte_flow_error_set
3185                       (error, ENOTSUP,
3186                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3187                        NULL,
3188                        "count action not supported");
3189 }
3190
3191 /**
3192  * Validate the L2 encap action.
3193  *
3194  * @param[in] dev
3195  *   Pointer to the rte_eth_dev structure.
3196  * @param[in] action_flags
3197  *   Holds the actions detected until now.
3198  * @param[in] action
3199  *   Pointer to the action structure.
3200  * @param[in] attr
3201  *   Pointer to flow attributes.
3202  * @param[out] error
3203  *   Pointer to error structure.
3204  *
3205  * @return
3206  *   0 on success, a negative errno value otherwise and rte_errno is set.
3207  */
3208 static int
3209 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3210                                  uint64_t action_flags,
3211                                  const struct rte_flow_action *action,
3212                                  const struct rte_flow_attr *attr,
3213                                  struct rte_flow_error *error)
3214 {
3215         const struct mlx5_priv *priv = dev->data->dev_private;
3216
3217         if (!(action->conf))
3218                 return rte_flow_error_set(error, EINVAL,
3219                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3220                                           "configuration cannot be null");
3221         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3222                 return rte_flow_error_set(error, EINVAL,
3223                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3224                                           "can only have a single encap action "
3225                                           "in a flow");
3226         if (!attr->transfer && priv->representor)
3227                 return rte_flow_error_set(error, ENOTSUP,
3228                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3229                                           "encap action for VF representor "
3230                                           "not supported on NIC table");
3231         return 0;
3232 }
3233
3234 /**
3235  * Validate a decap action.
3236  *
3237  * @param[in] dev
3238  *   Pointer to the rte_eth_dev structure.
3239  * @param[in] action_flags
3240  *   Holds the actions detected until now.
3241  * @param[in] action
3242  *   Pointer to the action structure.
3243  * @param[in] item_flags
3244  *   Holds the items detected.
3245  * @param[in] attr
3246  *   Pointer to flow attributes
3247  * @param[out] error
3248  *   Pointer to error structure.
3249  *
3250  * @return
3251  *   0 on success, a negative errno value otherwise and rte_errno is set.
3252  */
3253 static int
3254 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3255                               uint64_t action_flags,
3256                               const struct rte_flow_action *action,
3257                               const uint64_t item_flags,
3258                               const struct rte_flow_attr *attr,
3259                               struct rte_flow_error *error)
3260 {
3261         const struct mlx5_priv *priv = dev->data->dev_private;
3262
3263         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3264             !priv->config.decap_en)
3265                 return rte_flow_error_set(error, ENOTSUP,
3266                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3267                                           "decap is not enabled");
3268         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3269                 return rte_flow_error_set(error, ENOTSUP,
3270                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3271                                           action_flags &
3272                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3273                                           "have a single decap action" : "decap "
3274                                           "after encap is not supported");
3275         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3276                 return rte_flow_error_set(error, EINVAL,
3277                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3278                                           "can't have decap action after"
3279                                           " modify action");
3280         if (attr->egress)
3281                 return rte_flow_error_set(error, ENOTSUP,
3282                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3283                                           NULL,
3284                                           "decap action not supported for "
3285                                           "egress");
3286         if (!attr->transfer && priv->representor)
3287                 return rte_flow_error_set(error, ENOTSUP,
3288                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3289                                           "decap action for VF representor "
3290                                           "not supported on NIC table");
3291         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3292             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3293                 return rte_flow_error_set(error, ENOTSUP,
3294                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3295                                 "VXLAN item should be present for VXLAN decap");
3296         return 0;
3297 }
3298
3299 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3300
3301 /**
3302  * Validate the raw encap and decap actions.
3303  *
3304  * @param[in] dev
3305  *   Pointer to the rte_eth_dev structure.
3306  * @param[in] decap
3307  *   Pointer to the decap action.
3308  * @param[in] encap
3309  *   Pointer to the encap action.
3310  * @param[in] attr
3311  *   Pointer to flow attributes
3312  * @param[in/out] action_flags
3313  *   Holds the actions detected until now.
3314  * @param[out] actions_n
3315  *   pointer to the number of actions counter.
3316  * @param[in] action
3317  *   Pointer to the action structure.
3318  * @param[in] item_flags
3319  *   Holds the items detected.
3320  * @param[out] error
3321  *   Pointer to error structure.
3322  *
3323  * @return
3324  *   0 on success, a negative errno value otherwise and rte_errno is set.
3325  */
3326 static int
3327 flow_dv_validate_action_raw_encap_decap
3328         (struct rte_eth_dev *dev,
3329          const struct rte_flow_action_raw_decap *decap,
3330          const struct rte_flow_action_raw_encap *encap,
3331          const struct rte_flow_attr *attr, uint64_t *action_flags,
3332          int *actions_n, const struct rte_flow_action *action,
3333          uint64_t item_flags, struct rte_flow_error *error)
3334 {
3335         const struct mlx5_priv *priv = dev->data->dev_private;
3336         int ret;
3337
3338         if (encap && (!encap->size || !encap->data))
3339                 return rte_flow_error_set(error, EINVAL,
3340                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3341                                           "raw encap data cannot be empty");
3342         if (decap && encap) {
3343                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3344                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3345                         /* L3 encap. */
3346                         decap = NULL;
3347                 else if (encap->size <=
3348                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3349                            decap->size >
3350                            MLX5_ENCAPSULATION_DECISION_SIZE)
3351                         /* L3 decap. */
3352                         encap = NULL;
3353                 else if (encap->size >
3354                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3355                            decap->size >
3356                            MLX5_ENCAPSULATION_DECISION_SIZE)
3357                         /* 2 L2 actions: encap and decap. */
3358                         ;
3359                 else
3360                         return rte_flow_error_set(error,
3361                                 ENOTSUP,
3362                                 RTE_FLOW_ERROR_TYPE_ACTION,
3363                                 NULL, "unsupported too small "
3364                                 "raw decap and too small raw "
3365                                 "encap combination");
3366         }
3367         if (decap) {
3368                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3369                                                     item_flags, attr, error);
3370                 if (ret < 0)
3371                         return ret;
3372                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3373                 ++(*actions_n);
3374         }
3375         if (encap) {
3376                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3377                         return rte_flow_error_set(error, ENOTSUP,
3378                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3379                                                   NULL,
3380                                                   "small raw encap size");
3381                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3382                         return rte_flow_error_set(error, EINVAL,
3383                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3384                                                   NULL,
3385                                                   "more than one encap action");
3386                 if (!attr->transfer && priv->representor)
3387                         return rte_flow_error_set
3388                                         (error, ENOTSUP,
3389                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3390                                          "encap action for VF representor "
3391                                          "not supported on NIC table");
3392                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3393                 ++(*actions_n);
3394         }
3395         return 0;
3396 }
3397
3398 /**
3399  * Match encap_decap resource.
3400  *
3401  * @param list
3402  *   Pointer to the hash list.
3403  * @param entry
3404  *   Pointer to exist resource entry object.
3405  * @param key
3406  *   Key of the new entry.
3407  * @param ctx_cb
3408  *   Pointer to new encap_decap resource.
3409  *
3410  * @return
3411  *   0 on matching, none-zero otherwise.
3412  */
3413 int
3414 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3415                              struct mlx5_hlist_entry *entry,
3416                              uint64_t key __rte_unused, void *cb_ctx)
3417 {
3418         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3419         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3420         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3421
3422         cache_resource = container_of(entry,
3423                                       struct mlx5_flow_dv_encap_decap_resource,
3424                                       entry);
3425         if (resource->reformat_type == cache_resource->reformat_type &&
3426             resource->ft_type == cache_resource->ft_type &&
3427             resource->flags == cache_resource->flags &&
3428             resource->size == cache_resource->size &&
3429             !memcmp((const void *)resource->buf,
3430                     (const void *)cache_resource->buf,
3431                     resource->size))
3432                 return 0;
3433         return -1;
3434 }
3435
3436 /**
3437  * Allocate encap_decap resource.
3438  *
3439  * @param list
3440  *   Pointer to the hash list.
3441  * @param entry
3442  *   Pointer to exist resource entry object.
3443  * @param ctx_cb
3444  *   Pointer to new encap_decap resource.
3445  *
3446  * @return
3447  *   0 on matching, none-zero otherwise.
3448  */
3449 struct mlx5_hlist_entry *
3450 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3451                               uint64_t key __rte_unused,
3452                               void *cb_ctx)
3453 {
3454         struct mlx5_dev_ctx_shared *sh = list->ctx;
3455         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3456         struct mlx5dv_dr_domain *domain;
3457         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3458         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3459         uint32_t idx;
3460         int ret;
3461
3462         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3463                 domain = sh->fdb_domain;
3464         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3465                 domain = sh->rx_domain;
3466         else
3467                 domain = sh->tx_domain;
3468         /* Register new encap/decap resource. */
3469         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3470                                        &idx);
3471         if (!cache_resource) {
3472                 rte_flow_error_set(ctx->error, ENOMEM,
3473                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3474                                    "cannot allocate resource memory");
3475                 return NULL;
3476         }
3477         *cache_resource = *resource;
3478         cache_resource->idx = idx;
3479         ret = mlx5_flow_os_create_flow_action_packet_reformat
3480                                         (sh->ctx, domain, cache_resource,
3481                                          &cache_resource->action);
3482         if (ret) {
3483                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3484                 rte_flow_error_set(ctx->error, ENOMEM,
3485                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3486                                    NULL, "cannot create action");
3487                 return NULL;
3488         }
3489
3490         return &cache_resource->entry;
3491 }
3492
3493 /**
3494  * Find existing encap/decap resource or create and register a new one.
3495  *
3496  * @param[in, out] dev
3497  *   Pointer to rte_eth_dev structure.
3498  * @param[in, out] resource
3499  *   Pointer to encap/decap resource.
3500  * @parm[in, out] dev_flow
3501  *   Pointer to the dev_flow.
3502  * @param[out] error
3503  *   pointer to error structure.
3504  *
3505  * @return
3506  *   0 on success otherwise -errno and errno is set.
3507  */
3508 static int
3509 flow_dv_encap_decap_resource_register
3510                         (struct rte_eth_dev *dev,
3511                          struct mlx5_flow_dv_encap_decap_resource *resource,
3512                          struct mlx5_flow *dev_flow,
3513                          struct rte_flow_error *error)
3514 {
3515         struct mlx5_priv *priv = dev->data->dev_private;
3516         struct mlx5_dev_ctx_shared *sh = priv->sh;
3517         struct mlx5_hlist_entry *entry;
3518         union {
3519                 struct {
3520                         uint32_t ft_type:8;
3521                         uint32_t refmt_type:8;
3522                         /*
3523                          * Header reformat actions can be shared between
3524                          * non-root tables. One bit to indicate non-root
3525                          * table or not.
3526                          */
3527                         uint32_t is_root:1;
3528                         uint32_t reserve:15;
3529                 };
3530                 uint32_t v32;
3531         } encap_decap_key = {
3532                 {
3533                         .ft_type = resource->ft_type,
3534                         .refmt_type = resource->reformat_type,
3535                         .is_root = !!dev_flow->dv.group,
3536                         .reserve = 0,
3537                 }
3538         };
3539         struct mlx5_flow_cb_ctx ctx = {
3540                 .error = error,
3541                 .data = resource,
3542         };
3543         uint64_t key64;
3544
3545         resource->flags = dev_flow->dv.group ? 0 : 1;
3546         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3547                                  sizeof(encap_decap_key.v32), 0);
3548         if (resource->reformat_type !=
3549             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3550             resource->size)
3551                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3552         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3553         if (!entry)
3554                 return -rte_errno;
3555         resource = container_of(entry, typeof(*resource), entry);
3556         dev_flow->dv.encap_decap = resource;
3557         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3558         return 0;
3559 }
3560
3561 /**
3562  * Find existing table jump resource or create and register a new one.
3563  *
3564  * @param[in, out] dev
3565  *   Pointer to rte_eth_dev structure.
3566  * @param[in, out] tbl
3567  *   Pointer to flow table resource.
3568  * @parm[in, out] dev_flow
3569  *   Pointer to the dev_flow.
3570  * @param[out] error
3571  *   pointer to error structure.
3572  *
3573  * @return
3574  *   0 on success otherwise -errno and errno is set.
3575  */
3576 static int
3577 flow_dv_jump_tbl_resource_register
3578                         (struct rte_eth_dev *dev __rte_unused,
3579                          struct mlx5_flow_tbl_resource *tbl,
3580                          struct mlx5_flow *dev_flow,
3581                          struct rte_flow_error *error __rte_unused)
3582 {
3583         struct mlx5_flow_tbl_data_entry *tbl_data =
3584                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3585
3586         MLX5_ASSERT(tbl);
3587         MLX5_ASSERT(tbl_data->jump.action);
3588         dev_flow->handle->rix_jump = tbl_data->idx;
3589         dev_flow->dv.jump = &tbl_data->jump;
3590         return 0;
3591 }
3592
3593 int
3594 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3595                          struct mlx5_cache_entry *entry, void *cb_ctx)
3596 {
3597         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3598         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3599         struct mlx5_flow_dv_port_id_action_resource *res =
3600                         container_of(entry, typeof(*res), entry);
3601
3602         return ref->port_id != res->port_id;
3603 }
3604
3605 struct mlx5_cache_entry *
3606 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3607                           struct mlx5_cache_entry *entry __rte_unused,
3608                           void *cb_ctx)
3609 {
3610         struct mlx5_dev_ctx_shared *sh = list->ctx;
3611         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3612         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3613         struct mlx5_flow_dv_port_id_action_resource *cache;
3614         uint32_t idx;
3615         int ret;
3616
3617         /* Register new port id action resource. */
3618         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3619         if (!cache) {
3620                 rte_flow_error_set(ctx->error, ENOMEM,
3621                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3622                                    "cannot allocate port_id action cache memory");
3623                 return NULL;
3624         }
3625         *cache = *ref;
3626         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3627                                                         ref->port_id,
3628                                                         &cache->action);
3629         if (ret) {
3630                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3631                 rte_flow_error_set(ctx->error, ENOMEM,
3632                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3633                                    "cannot create action");
3634                 return NULL;
3635         }
3636         cache->idx = idx;
3637         return &cache->entry;
3638 }
3639
3640 /**
3641  * Find existing table port ID resource or create and register a new one.
3642  *
3643  * @param[in, out] dev
3644  *   Pointer to rte_eth_dev structure.
3645  * @param[in, out] resource
3646  *   Pointer to port ID action resource.
3647  * @parm[in, out] dev_flow
3648  *   Pointer to the dev_flow.
3649  * @param[out] error
3650  *   pointer to error structure.
3651  *
3652  * @return
3653  *   0 on success otherwise -errno and errno is set.
3654  */
3655 static int
3656 flow_dv_port_id_action_resource_register
3657                         (struct rte_eth_dev *dev,
3658                          struct mlx5_flow_dv_port_id_action_resource *resource,
3659                          struct mlx5_flow *dev_flow,
3660                          struct rte_flow_error *error)
3661 {
3662         struct mlx5_priv *priv = dev->data->dev_private;
3663         struct mlx5_cache_entry *entry;
3664         struct mlx5_flow_dv_port_id_action_resource *cache;
3665         struct mlx5_flow_cb_ctx ctx = {
3666                 .error = error,
3667                 .data = resource,
3668         };
3669
3670         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3671         if (!entry)
3672                 return -rte_errno;
3673         cache = container_of(entry, typeof(*cache), entry);
3674         dev_flow->dv.port_id_action = cache;
3675         dev_flow->handle->rix_port_id_action = cache->idx;
3676         return 0;
3677 }
3678
3679 int
3680 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3681                          struct mlx5_cache_entry *entry, void *cb_ctx)
3682 {
3683         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3684         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3685         struct mlx5_flow_dv_push_vlan_action_resource *res =
3686                         container_of(entry, typeof(*res), entry);
3687
3688         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3689 }
3690
3691 struct mlx5_cache_entry *
3692 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3693                           struct mlx5_cache_entry *entry __rte_unused,
3694                           void *cb_ctx)
3695 {
3696         struct mlx5_dev_ctx_shared *sh = list->ctx;
3697         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3698         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3699         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3700         struct mlx5dv_dr_domain *domain;
3701         uint32_t idx;
3702         int ret;
3703
3704         /* Register new port id action resource. */
3705         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3706         if (!cache) {
3707                 rte_flow_error_set(ctx->error, ENOMEM,
3708                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3709                                    "cannot allocate push_vlan action cache memory");
3710                 return NULL;
3711         }
3712         *cache = *ref;
3713         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3714                 domain = sh->fdb_domain;
3715         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3716                 domain = sh->rx_domain;
3717         else
3718                 domain = sh->tx_domain;
3719         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3720                                                         &cache->action);
3721         if (ret) {
3722                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3723                 rte_flow_error_set(ctx->error, ENOMEM,
3724                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3725                                    "cannot create push vlan action");
3726                 return NULL;
3727         }
3728         cache->idx = idx;
3729         return &cache->entry;
3730 }
3731
3732 /**
3733  * Find existing push vlan resource or create and register a new one.
3734  *
3735  * @param [in, out] dev
3736  *   Pointer to rte_eth_dev structure.
3737  * @param[in, out] resource
3738  *   Pointer to port ID action resource.
3739  * @parm[in, out] dev_flow
3740  *   Pointer to the dev_flow.
3741  * @param[out] error
3742  *   pointer to error structure.
3743  *
3744  * @return
3745  *   0 on success otherwise -errno and errno is set.
3746  */
3747 static int
3748 flow_dv_push_vlan_action_resource_register
3749                        (struct rte_eth_dev *dev,
3750                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3751                         struct mlx5_flow *dev_flow,
3752                         struct rte_flow_error *error)
3753 {
3754         struct mlx5_priv *priv = dev->data->dev_private;
3755         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3756         struct mlx5_cache_entry *entry;
3757         struct mlx5_flow_cb_ctx ctx = {
3758                 .error = error,
3759                 .data = resource,
3760         };
3761
3762         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3763         if (!entry)
3764                 return -rte_errno;
3765         cache = container_of(entry, typeof(*cache), entry);
3766
3767         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3768         dev_flow->dv.push_vlan_res = cache;
3769         return 0;
3770 }
3771
3772 /**
3773  * Get the size of specific rte_flow_item_type hdr size
3774  *
3775  * @param[in] item_type
3776  *   Tested rte_flow_item_type.
3777  *
3778  * @return
3779  *   sizeof struct item_type, 0 if void or irrelevant.
3780  */
3781 static size_t
3782 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3783 {
3784         size_t retval;
3785
3786         switch (item_type) {
3787         case RTE_FLOW_ITEM_TYPE_ETH:
3788                 retval = sizeof(struct rte_ether_hdr);
3789                 break;
3790         case RTE_FLOW_ITEM_TYPE_VLAN:
3791                 retval = sizeof(struct rte_vlan_hdr);
3792                 break;
3793         case RTE_FLOW_ITEM_TYPE_IPV4:
3794                 retval = sizeof(struct rte_ipv4_hdr);
3795                 break;
3796         case RTE_FLOW_ITEM_TYPE_IPV6:
3797                 retval = sizeof(struct rte_ipv6_hdr);
3798                 break;
3799         case RTE_FLOW_ITEM_TYPE_UDP:
3800                 retval = sizeof(struct rte_udp_hdr);
3801                 break;
3802         case RTE_FLOW_ITEM_TYPE_TCP:
3803                 retval = sizeof(struct rte_tcp_hdr);
3804                 break;
3805         case RTE_FLOW_ITEM_TYPE_VXLAN:
3806         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3807                 retval = sizeof(struct rte_vxlan_hdr);
3808                 break;
3809         case RTE_FLOW_ITEM_TYPE_GRE:
3810         case RTE_FLOW_ITEM_TYPE_NVGRE:
3811                 retval = sizeof(struct rte_gre_hdr);
3812                 break;
3813         case RTE_FLOW_ITEM_TYPE_MPLS:
3814                 retval = sizeof(struct rte_mpls_hdr);
3815                 break;
3816         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3817         default:
3818                 retval = 0;
3819                 break;
3820         }
3821         return retval;
3822 }
3823
3824 #define MLX5_ENCAP_IPV4_VERSION         0x40
3825 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3826 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3827 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3828 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3829 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3830 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3831
3832 /**
3833  * Convert the encap action data from list of rte_flow_item to raw buffer
3834  *
3835  * @param[in] items
3836  *   Pointer to rte_flow_item objects list.
3837  * @param[out] buf
3838  *   Pointer to the output buffer.
3839  * @param[out] size
3840  *   Pointer to the output buffer size.
3841  * @param[out] error
3842  *   Pointer to the error structure.
3843  *
3844  * @return
3845  *   0 on success, a negative errno value otherwise and rte_errno is set.
3846  */
3847 static int
3848 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3849                            size_t *size, struct rte_flow_error *error)
3850 {
3851         struct rte_ether_hdr *eth = NULL;
3852         struct rte_vlan_hdr *vlan = NULL;
3853         struct rte_ipv4_hdr *ipv4 = NULL;
3854         struct rte_ipv6_hdr *ipv6 = NULL;
3855         struct rte_udp_hdr *udp = NULL;
3856         struct rte_vxlan_hdr *vxlan = NULL;
3857         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3858         struct rte_gre_hdr *gre = NULL;
3859         size_t len;
3860         size_t temp_size = 0;
3861
3862         if (!items)
3863                 return rte_flow_error_set(error, EINVAL,
3864                                           RTE_FLOW_ERROR_TYPE_ACTION,
3865                                           NULL, "invalid empty data");
3866         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3867                 len = flow_dv_get_item_hdr_len(items->type);
3868                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3869                         return rte_flow_error_set(error, EINVAL,
3870                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3871                                                   (void *)items->type,
3872                                                   "items total size is too big"
3873                                                   " for encap action");
3874                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3875                 switch (items->type) {
3876                 case RTE_FLOW_ITEM_TYPE_ETH:
3877                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3878                         break;
3879                 case RTE_FLOW_ITEM_TYPE_VLAN:
3880                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3881                         if (!eth)
3882                                 return rte_flow_error_set(error, EINVAL,
3883                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3884                                                 (void *)items->type,
3885                                                 "eth header not found");
3886                         if (!eth->ether_type)
3887                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3888                         break;
3889                 case RTE_FLOW_ITEM_TYPE_IPV4:
3890                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3891                         if (!vlan && !eth)
3892                                 return rte_flow_error_set(error, EINVAL,
3893                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3894                                                 (void *)items->type,
3895                                                 "neither eth nor vlan"
3896                                                 " header found");
3897                         if (vlan && !vlan->eth_proto)
3898                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3899                         else if (eth && !eth->ether_type)
3900                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3901                         if (!ipv4->version_ihl)
3902                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3903                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3904                         if (!ipv4->time_to_live)
3905                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3906                         break;
3907                 case RTE_FLOW_ITEM_TYPE_IPV6:
3908                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3909                         if (!vlan && !eth)
3910                                 return rte_flow_error_set(error, EINVAL,
3911                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3912                                                 (void *)items->type,
3913                                                 "neither eth nor vlan"
3914                                                 " header found");
3915                         if (vlan && !vlan->eth_proto)
3916                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3917                         else if (eth && !eth->ether_type)
3918                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3919                         if (!ipv6->vtc_flow)
3920                                 ipv6->vtc_flow =
3921                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3922                         if (!ipv6->hop_limits)
3923                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3924                         break;
3925                 case RTE_FLOW_ITEM_TYPE_UDP:
3926                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3927                         if (!ipv4 && !ipv6)
3928                                 return rte_flow_error_set(error, EINVAL,
3929                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3930                                                 (void *)items->type,
3931                                                 "ip header not found");
3932                         if (ipv4 && !ipv4->next_proto_id)
3933                                 ipv4->next_proto_id = IPPROTO_UDP;
3934                         else if (ipv6 && !ipv6->proto)
3935                                 ipv6->proto = IPPROTO_UDP;
3936                         break;
3937                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3938                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3939                         if (!udp)
3940                                 return rte_flow_error_set(error, EINVAL,
3941                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3942                                                 (void *)items->type,
3943                                                 "udp header not found");
3944                         if (!udp->dst_port)
3945                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3946                         if (!vxlan->vx_flags)
3947                                 vxlan->vx_flags =
3948                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3949                         break;
3950                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3951                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3952                         if (!udp)
3953                                 return rte_flow_error_set(error, EINVAL,
3954                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3955                                                 (void *)items->type,
3956                                                 "udp header not found");
3957                         if (!vxlan_gpe->proto)
3958                                 return rte_flow_error_set(error, EINVAL,
3959                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3960                                                 (void *)items->type,
3961                                                 "next protocol not found");
3962                         if (!udp->dst_port)
3963                                 udp->dst_port =
3964                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3965                         if (!vxlan_gpe->vx_flags)
3966                                 vxlan_gpe->vx_flags =
3967                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3968                         break;
3969                 case RTE_FLOW_ITEM_TYPE_GRE:
3970                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3971                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3972                         if (!gre->proto)
3973                                 return rte_flow_error_set(error, EINVAL,
3974                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3975                                                 (void *)items->type,
3976                                                 "next protocol not found");
3977                         if (!ipv4 && !ipv6)
3978                                 return rte_flow_error_set(error, EINVAL,
3979                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3980                                                 (void *)items->type,
3981                                                 "ip header not found");
3982                         if (ipv4 && !ipv4->next_proto_id)
3983                                 ipv4->next_proto_id = IPPROTO_GRE;
3984                         else if (ipv6 && !ipv6->proto)
3985                                 ipv6->proto = IPPROTO_GRE;
3986                         break;
3987                 case RTE_FLOW_ITEM_TYPE_VOID:
3988                         break;
3989                 default:
3990                         return rte_flow_error_set(error, EINVAL,
3991                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3992                                                   (void *)items->type,
3993                                                   "unsupported item type");
3994                         break;
3995                 }
3996                 temp_size += len;
3997         }
3998         *size = temp_size;
3999         return 0;
4000 }
4001
4002 static int
4003 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4004 {
4005         struct rte_ether_hdr *eth = NULL;
4006         struct rte_vlan_hdr *vlan = NULL;
4007         struct rte_ipv6_hdr *ipv6 = NULL;
4008         struct rte_udp_hdr *udp = NULL;
4009         char *next_hdr;
4010         uint16_t proto;
4011
4012         eth = (struct rte_ether_hdr *)data;
4013         next_hdr = (char *)(eth + 1);
4014         proto = RTE_BE16(eth->ether_type);
4015
4016         /* VLAN skipping */
4017         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4018                 vlan = (struct rte_vlan_hdr *)next_hdr;
4019                 proto = RTE_BE16(vlan->eth_proto);
4020                 next_hdr += sizeof(struct rte_vlan_hdr);
4021         }
4022
4023         /* HW calculates IPv4 csum. no need to proceed */
4024         if (proto == RTE_ETHER_TYPE_IPV4)
4025                 return 0;
4026
4027         /* non IPv4/IPv6 header. not supported */
4028         if (proto != RTE_ETHER_TYPE_IPV6) {
4029                 return rte_flow_error_set(error, ENOTSUP,
4030                                           RTE_FLOW_ERROR_TYPE_ACTION,
4031                                           NULL, "Cannot offload non IPv4/IPv6");
4032         }
4033
4034         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4035
4036         /* ignore non UDP */
4037         if (ipv6->proto != IPPROTO_UDP)
4038                 return 0;
4039
4040         udp = (struct rte_udp_hdr *)(ipv6 + 1);
4041         udp->dgram_cksum = 0;
4042
4043         return 0;
4044 }
4045
4046 /**
4047  * Convert L2 encap action to DV specification.
4048  *
4049  * @param[in] dev
4050  *   Pointer to rte_eth_dev structure.
4051  * @param[in] action
4052  *   Pointer to action structure.
4053  * @param[in, out] dev_flow
4054  *   Pointer to the mlx5_flow.
4055  * @param[in] transfer
4056  *   Mark if the flow is E-Switch flow.
4057  * @param[out] error
4058  *   Pointer to the error structure.
4059  *
4060  * @return
4061  *   0 on success, a negative errno value otherwise and rte_errno is set.
4062  */
4063 static int
4064 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4065                                const struct rte_flow_action *action,
4066                                struct mlx5_flow *dev_flow,
4067                                uint8_t transfer,
4068                                struct rte_flow_error *error)
4069 {
4070         const struct rte_flow_item *encap_data;
4071         const struct rte_flow_action_raw_encap *raw_encap_data;
4072         struct mlx5_flow_dv_encap_decap_resource res = {
4073                 .reformat_type =
4074                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4075                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4076                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4077         };
4078
4079         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4080                 raw_encap_data =
4081                         (const struct rte_flow_action_raw_encap *)action->conf;
4082                 res.size = raw_encap_data->size;
4083                 memcpy(res.buf, raw_encap_data->data, res.size);
4084         } else {
4085                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4086                         encap_data =
4087                                 ((const struct rte_flow_action_vxlan_encap *)
4088                                                 action->conf)->definition;
4089                 else
4090                         encap_data =
4091                                 ((const struct rte_flow_action_nvgre_encap *)
4092                                                 action->conf)->definition;
4093                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4094                                                &res.size, error))
4095                         return -rte_errno;
4096         }
4097         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4098                 return -rte_errno;
4099         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4100                 return rte_flow_error_set(error, EINVAL,
4101                                           RTE_FLOW_ERROR_TYPE_ACTION,
4102                                           NULL, "can't create L2 encap action");
4103         return 0;
4104 }
4105
4106 /**
4107  * Convert L2 decap action to DV specification.
4108  *
4109  * @param[in] dev
4110  *   Pointer to rte_eth_dev structure.
4111  * @param[in, out] dev_flow
4112  *   Pointer to the mlx5_flow.
4113  * @param[in] transfer
4114  *   Mark if the flow is E-Switch flow.
4115  * @param[out] error
4116  *   Pointer to the error structure.
4117  *
4118  * @return
4119  *   0 on success, a negative errno value otherwise and rte_errno is set.
4120  */
4121 static int
4122 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4123                                struct mlx5_flow *dev_flow,
4124                                uint8_t transfer,
4125                                struct rte_flow_error *error)
4126 {
4127         struct mlx5_flow_dv_encap_decap_resource res = {
4128                 .size = 0,
4129                 .reformat_type =
4130                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4131                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4132                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4133         };
4134
4135         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4136                 return rte_flow_error_set(error, EINVAL,
4137                                           RTE_FLOW_ERROR_TYPE_ACTION,
4138                                           NULL, "can't create L2 decap action");
4139         return 0;
4140 }
4141
4142 /**
4143  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4144  *
4145  * @param[in] dev
4146  *   Pointer to rte_eth_dev structure.
4147  * @param[in] action
4148  *   Pointer to action structure.
4149  * @param[in, out] dev_flow
4150  *   Pointer to the mlx5_flow.
4151  * @param[in] attr
4152  *   Pointer to the flow attributes.
4153  * @param[out] error
4154  *   Pointer to the error structure.
4155  *
4156  * @return
4157  *   0 on success, a negative errno value otherwise and rte_errno is set.
4158  */
4159 static int
4160 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4161                                 const struct rte_flow_action *action,
4162                                 struct mlx5_flow *dev_flow,
4163                                 const struct rte_flow_attr *attr,
4164                                 struct rte_flow_error *error)
4165 {
4166         const struct rte_flow_action_raw_encap *encap_data;
4167         struct mlx5_flow_dv_encap_decap_resource res;
4168
4169         memset(&res, 0, sizeof(res));
4170         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4171         res.size = encap_data->size;
4172         memcpy(res.buf, encap_data->data, res.size);
4173         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4174                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4175                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4176         if (attr->transfer)
4177                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4178         else
4179                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4180                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4181         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4182                 return rte_flow_error_set(error, EINVAL,
4183                                           RTE_FLOW_ERROR_TYPE_ACTION,
4184                                           NULL, "can't create encap action");
4185         return 0;
4186 }
4187
4188 /**
4189  * Create action push VLAN.
4190  *
4191  * @param[in] dev
4192  *   Pointer to rte_eth_dev structure.
4193  * @param[in] attr
4194  *   Pointer to the flow attributes.
4195  * @param[in] vlan
4196  *   Pointer to the vlan to push to the Ethernet header.
4197  * @param[in, out] dev_flow
4198  *   Pointer to the mlx5_flow.
4199  * @param[out] error
4200  *   Pointer to the error structure.
4201  *
4202  * @return
4203  *   0 on success, a negative errno value otherwise and rte_errno is set.
4204  */
4205 static int
4206 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4207                                 const struct rte_flow_attr *attr,
4208                                 const struct rte_vlan_hdr *vlan,
4209                                 struct mlx5_flow *dev_flow,
4210                                 struct rte_flow_error *error)
4211 {
4212         struct mlx5_flow_dv_push_vlan_action_resource res;
4213
4214         memset(&res, 0, sizeof(res));
4215         res.vlan_tag =
4216                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4217                                  vlan->vlan_tci);
4218         if (attr->transfer)
4219                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4220         else
4221                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4222                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4223         return flow_dv_push_vlan_action_resource_register
4224                                             (dev, &res, dev_flow, error);
4225 }
4226
4227 /**
4228  * Validate the modify-header actions.
4229  *
4230  * @param[in] action_flags
4231  *   Holds the actions detected until now.
4232  * @param[in] action
4233  *   Pointer to the modify action.
4234  * @param[out] error
4235  *   Pointer to error structure.
4236  *
4237  * @return
4238  *   0 on success, a negative errno value otherwise and rte_errno is set.
4239  */
4240 static int
4241 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4242                                    const struct rte_flow_action *action,
4243                                    struct rte_flow_error *error)
4244 {
4245         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4246                 return rte_flow_error_set(error, EINVAL,
4247                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4248                                           NULL, "action configuration not set");
4249         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4250                 return rte_flow_error_set(error, EINVAL,
4251                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4252                                           "can't have encap action before"
4253                                           " modify action");
4254         return 0;
4255 }
4256
4257 /**
4258  * Validate the modify-header MAC address actions.
4259  *
4260  * @param[in] action_flags
4261  *   Holds the actions detected until now.
4262  * @param[in] action
4263  *   Pointer to the modify action.
4264  * @param[in] item_flags
4265  *   Holds the items detected.
4266  * @param[out] error
4267  *   Pointer to error structure.
4268  *
4269  * @return
4270  *   0 on success, a negative errno value otherwise and rte_errno is set.
4271  */
4272 static int
4273 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4274                                    const struct rte_flow_action *action,
4275                                    const uint64_t item_flags,
4276                                    struct rte_flow_error *error)
4277 {
4278         int ret = 0;
4279
4280         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4281         if (!ret) {
4282                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4283                         return rte_flow_error_set(error, EINVAL,
4284                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4285                                                   NULL,
4286                                                   "no L2 item in pattern");
4287         }
4288         return ret;
4289 }
4290
4291 /**
4292  * Validate the modify-header IPv4 address actions.
4293  *
4294  * @param[in] action_flags
4295  *   Holds the actions detected until now.
4296  * @param[in] action
4297  *   Pointer to the modify action.
4298  * @param[in] item_flags
4299  *   Holds the items detected.
4300  * @param[out] error
4301  *   Pointer to error structure.
4302  *
4303  * @return
4304  *   0 on success, a negative errno value otherwise and rte_errno is set.
4305  */
4306 static int
4307 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4308                                     const struct rte_flow_action *action,
4309                                     const uint64_t item_flags,
4310                                     struct rte_flow_error *error)
4311 {
4312         int ret = 0;
4313         uint64_t layer;
4314
4315         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4316         if (!ret) {
4317                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4318                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4319                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4320                 if (!(item_flags & layer))
4321                         return rte_flow_error_set(error, EINVAL,
4322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4323                                                   NULL,
4324                                                   "no ipv4 item in pattern");
4325         }
4326         return ret;
4327 }
4328
4329 /**
4330  * Validate the modify-header IPv6 address actions.
4331  *
4332  * @param[in] action_flags
4333  *   Holds the actions detected until now.
4334  * @param[in] action
4335  *   Pointer to the modify action.
4336  * @param[in] item_flags
4337  *   Holds the items detected.
4338  * @param[out] error
4339  *   Pointer to error structure.
4340  *
4341  * @return
4342  *   0 on success, a negative errno value otherwise and rte_errno is set.
4343  */
4344 static int
4345 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4346                                     const struct rte_flow_action *action,
4347                                     const uint64_t item_flags,
4348                                     struct rte_flow_error *error)
4349 {
4350         int ret = 0;
4351         uint64_t layer;
4352
4353         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4354         if (!ret) {
4355                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4356                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4357                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4358                 if (!(item_flags & layer))
4359                         return rte_flow_error_set(error, EINVAL,
4360                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4361                                                   NULL,
4362                                                   "no ipv6 item in pattern");
4363         }
4364         return ret;
4365 }
4366
4367 /**
4368  * Validate the modify-header TP actions.
4369  *
4370  * @param[in] action_flags
4371  *   Holds the actions detected until now.
4372  * @param[in] action
4373  *   Pointer to the modify action.
4374  * @param[in] item_flags
4375  *   Holds the items detected.
4376  * @param[out] error
4377  *   Pointer to error structure.
4378  *
4379  * @return
4380  *   0 on success, a negative errno value otherwise and rte_errno is set.
4381  */
4382 static int
4383 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4384                                   const struct rte_flow_action *action,
4385                                   const uint64_t item_flags,
4386                                   struct rte_flow_error *error)
4387 {
4388         int ret = 0;
4389         uint64_t layer;
4390
4391         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4392         if (!ret) {
4393                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4394                                  MLX5_FLOW_LAYER_INNER_L4 :
4395                                  MLX5_FLOW_LAYER_OUTER_L4;
4396                 if (!(item_flags & layer))
4397                         return rte_flow_error_set(error, EINVAL,
4398                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4399                                                   NULL, "no transport layer "
4400                                                   "in pattern");
4401         }
4402         return ret;
4403 }
4404
4405 /**
4406  * Validate the modify-header actions of increment/decrement
4407  * TCP Sequence-number.
4408  *
4409  * @param[in] action_flags
4410  *   Holds the actions detected until now.
4411  * @param[in] action
4412  *   Pointer to the modify action.
4413  * @param[in] item_flags
4414  *   Holds the items detected.
4415  * @param[out] error
4416  *   Pointer to error structure.
4417  *
4418  * @return
4419  *   0 on success, a negative errno value otherwise and rte_errno is set.
4420  */
4421 static int
4422 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4423                                        const struct rte_flow_action *action,
4424                                        const uint64_t item_flags,
4425                                        struct rte_flow_error *error)
4426 {
4427         int ret = 0;
4428         uint64_t layer;
4429
4430         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4431         if (!ret) {
4432                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4433                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4434                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4435                 if (!(item_flags & layer))
4436                         return rte_flow_error_set(error, EINVAL,
4437                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4438                                                   NULL, "no TCP item in"
4439                                                   " pattern");
4440                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4441                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4442                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4443                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4444                         return rte_flow_error_set(error, EINVAL,
4445                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4446                                                   NULL,
4447                                                   "cannot decrease and increase"
4448                                                   " TCP sequence number"
4449                                                   " at the same time");
4450         }
4451         return ret;
4452 }
4453
4454 /**
4455  * Validate the modify-header actions of increment/decrement
4456  * TCP Acknowledgment number.
4457  *
4458  * @param[in] action_flags
4459  *   Holds the actions detected until now.
4460  * @param[in] action
4461  *   Pointer to the modify action.
4462  * @param[in] item_flags
4463  *   Holds the items detected.
4464  * @param[out] error
4465  *   Pointer to error structure.
4466  *
4467  * @return
4468  *   0 on success, a negative errno value otherwise and rte_errno is set.
4469  */
4470 static int
4471 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4472                                        const struct rte_flow_action *action,
4473                                        const uint64_t item_flags,
4474                                        struct rte_flow_error *error)
4475 {
4476         int ret = 0;
4477         uint64_t layer;
4478
4479         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4480         if (!ret) {
4481                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4482                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4483                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4484                 if (!(item_flags & layer))
4485                         return rte_flow_error_set(error, EINVAL,
4486                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4487                                                   NULL, "no TCP item in"
4488                                                   " pattern");
4489                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4490                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4491                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4492                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4493                         return rte_flow_error_set(error, EINVAL,
4494                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4495                                                   NULL,
4496                                                   "cannot decrease and increase"
4497                                                   " TCP acknowledgment number"
4498                                                   " at the same time");
4499         }
4500         return ret;
4501 }
4502
4503 /**
4504  * Validate the modify-header TTL actions.
4505  *
4506  * @param[in] action_flags
4507  *   Holds the actions detected until now.
4508  * @param[in] action
4509  *   Pointer to the modify action.
4510  * @param[in] item_flags
4511  *   Holds the items detected.
4512  * @param[out] error
4513  *   Pointer to error structure.
4514  *
4515  * @return
4516  *   0 on success, a negative errno value otherwise and rte_errno is set.
4517  */
4518 static int
4519 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4520                                    const struct rte_flow_action *action,
4521                                    const uint64_t item_flags,
4522                                    struct rte_flow_error *error)
4523 {
4524         int ret = 0;
4525         uint64_t layer;
4526
4527         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4528         if (!ret) {
4529                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4530                                  MLX5_FLOW_LAYER_INNER_L3 :
4531                                  MLX5_FLOW_LAYER_OUTER_L3;
4532                 if (!(item_flags & layer))
4533                         return rte_flow_error_set(error, EINVAL,
4534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4535                                                   NULL,
4536                                                   "no IP protocol in pattern");
4537         }
4538         return ret;
4539 }
4540
4541 /**
4542  * Validate the generic modify field actions.
4543  * @param[in] dev
4544  *   Pointer to the rte_eth_dev structure.
4545  * @param[in] action_flags
4546  *   Holds the actions detected until now.
4547  * @param[in] action
4548  *   Pointer to the modify action.
4549  * @param[in] attr
4550  *   Pointer to the flow attributes.
4551  * @param[out] error
4552  *   Pointer to error structure.
4553  *
4554  * @return
4555  *   Number of header fields to modify (0 or more) on success,
4556  *   a negative errno value otherwise and rte_errno is set.
4557  */
4558 static int
4559 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4560                                    const uint64_t action_flags,
4561                                    const struct rte_flow_action *action,
4562                                    const struct rte_flow_attr *attr,
4563                                    struct rte_flow_error *error)
4564 {
4565         int ret = 0;
4566         struct mlx5_priv *priv = dev->data->dev_private;
4567         struct mlx5_dev_config *config = &priv->config;
4568         const struct rte_flow_action_modify_field *action_modify_field =
4569                 action->conf;
4570         uint32_t dst_width =
4571                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4572         uint32_t src_width =
4573                 mlx5_flow_item_field_width(action_modify_field->src.field);
4574
4575         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4576         if (ret)
4577                 return ret;
4578
4579         if (action_modify_field->width == 0)
4580                 return rte_flow_error_set(error, EINVAL,
4581                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4582                                 "no bits are requested to be modified");
4583         else if (action_modify_field->width > dst_width ||
4584                  action_modify_field->width > src_width)
4585                 return rte_flow_error_set(error, EINVAL,
4586                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4587                                 "cannot modify more bits than"
4588                                 " the width of a field");
4589         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4590             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4591                 if ((action_modify_field->dst.offset +
4592                      action_modify_field->width > dst_width) ||
4593                     (action_modify_field->dst.offset % 32))
4594                         return rte_flow_error_set(error, EINVAL,
4595                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4596                                         "destination offset is too big"
4597                                         " or not aligned to 4 bytes");
4598                 if (action_modify_field->dst.level &&
4599                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4600                         return rte_flow_error_set(error, ENOTSUP,
4601                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4602                                         "inner header fields modification"
4603                                         " is not supported");
4604         }
4605         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4606             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4607                 if (!attr->transfer && !attr->group)
4608                         return rte_flow_error_set(error, ENOTSUP,
4609                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4610                                         "modify field action is not"
4611                                         " supported for group 0");
4612                 if ((action_modify_field->src.offset +
4613                      action_modify_field->width > src_width) ||
4614                     (action_modify_field->src.offset % 32))
4615                         return rte_flow_error_set(error, EINVAL,
4616                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4617                                         "source offset is too big"
4618                                         " or not aligned to 4 bytes");
4619                 if (action_modify_field->src.level &&
4620                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4621                         return rte_flow_error_set(error, ENOTSUP,
4622                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4623                                         "inner header fields modification"
4624                                         " is not supported");
4625         }
4626         if (action_modify_field->dst.field ==
4627             action_modify_field->src.field)
4628                 return rte_flow_error_set(error, EINVAL,
4629                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4630                                 "source and destination fields"
4631                                 " cannot be the same");
4632         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4633             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4634                 return rte_flow_error_set(error, EINVAL,
4635                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4636                                 "immediate value or a pointer to it"
4637                                 " cannot be used as a destination");
4638         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4639             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4640                 return rte_flow_error_set(error, ENOTSUP,
4641                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4642                                 "modifications of an arbitrary"
4643                                 " place in a packet is not supported");
4644         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4645             action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4646                 return rte_flow_error_set(error, ENOTSUP,
4647                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4648                                 "modifications of the 802.1Q Tag"
4649                                 " Identifier is not supported");
4650         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4651             action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4652                 return rte_flow_error_set(error, ENOTSUP,
4653                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4654                                 "modifications of the VXLAN Network"
4655                                 " Identifier is not supported");
4656         if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4657             action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4658                 return rte_flow_error_set(error, ENOTSUP,
4659                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4660                                 "modifications of the GENEVE Network"
4661                                 " Identifier is not supported");
4662         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4663             action_modify_field->src.field == RTE_FLOW_FIELD_MARK ||
4664             action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4665             action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4666                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4667                     !mlx5_flow_ext_mreg_supported(dev))
4668                         return rte_flow_error_set(error, ENOTSUP,
4669                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4670                                         "cannot modify mark or metadata without"
4671                                         " extended metadata register support");
4672         }
4673         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4674                 return rte_flow_error_set(error, ENOTSUP,
4675                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
4676                                 "add and sub operations"
4677                                 " are not supported");
4678         return (action_modify_field->width / 32) +
4679                !!(action_modify_field->width % 32);
4680 }
4681
4682 /**
4683  * Validate jump action.
4684  *
4685  * @param[in] action
4686  *   Pointer to the jump action.
4687  * @param[in] action_flags
4688  *   Holds the actions detected until now.
4689  * @param[in] attributes
4690  *   Pointer to flow attributes
4691  * @param[in] external
4692  *   Action belongs to flow rule created by request external to PMD.
4693  * @param[out] error
4694  *   Pointer to error structure.
4695  *
4696  * @return
4697  *   0 on success, a negative errno value otherwise and rte_errno is set.
4698  */
4699 static int
4700 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4701                              const struct mlx5_flow_tunnel *tunnel,
4702                              const struct rte_flow_action *action,
4703                              uint64_t action_flags,
4704                              const struct rte_flow_attr *attributes,
4705                              bool external, struct rte_flow_error *error)
4706 {
4707         uint32_t target_group, table;
4708         int ret = 0;
4709         struct flow_grp_info grp_info = {
4710                 .external = !!external,
4711                 .transfer = !!attributes->transfer,
4712                 .fdb_def_rule = 1,
4713                 .std_tbl_fix = 0
4714         };
4715         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4716                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4717                 return rte_flow_error_set(error, EINVAL,
4718                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4719                                           "can't have 2 fate actions in"
4720                                           " same flow");
4721         if (action_flags & MLX5_FLOW_ACTION_METER)
4722                 return rte_flow_error_set(error, ENOTSUP,
4723                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4724                                           "jump with meter not support");
4725         if (!action->conf)
4726                 return rte_flow_error_set(error, EINVAL,
4727                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4728                                           NULL, "action configuration not set");
4729         target_group =
4730                 ((const struct rte_flow_action_jump *)action->conf)->group;
4731         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4732                                        &grp_info, error);
4733         if (ret)
4734                 return ret;
4735         if (attributes->group == target_group &&
4736             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4737                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4738                 return rte_flow_error_set(error, EINVAL,
4739                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4740                                           "target group must be other than"
4741                                           " the current flow group");
4742         return 0;
4743 }
4744
4745 /*
4746  * Validate the port_id action.
4747  *
4748  * @param[in] dev
4749  *   Pointer to rte_eth_dev structure.
4750  * @param[in] action_flags
4751  *   Bit-fields that holds the actions detected until now.
4752  * @param[in] action
4753  *   Port_id RTE action structure.
4754  * @param[in] attr
4755  *   Attributes of flow that includes this action.
4756  * @param[out] error
4757  *   Pointer to error structure.
4758  *
4759  * @return
4760  *   0 on success, a negative errno value otherwise and rte_errno is set.
4761  */
4762 static int
4763 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4764                                 uint64_t action_flags,
4765                                 const struct rte_flow_action *action,
4766                                 const struct rte_flow_attr *attr,
4767                                 struct rte_flow_error *error)
4768 {
4769         const struct rte_flow_action_port_id *port_id;
4770         struct mlx5_priv *act_priv;
4771         struct mlx5_priv *dev_priv;
4772         uint16_t port;
4773
4774         if (!attr->transfer)
4775                 return rte_flow_error_set(error, ENOTSUP,
4776                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4777                                           NULL,
4778                                           "port id action is valid in transfer"
4779                                           " mode only");
4780         if (!action || !action->conf)
4781                 return rte_flow_error_set(error, ENOTSUP,
4782                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4783                                           NULL,
4784                                           "port id action parameters must be"
4785                                           " specified");
4786         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4787                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4788                 return rte_flow_error_set(error, EINVAL,
4789                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4790                                           "can have only one fate actions in"
4791                                           " a flow");
4792         dev_priv = mlx5_dev_to_eswitch_info(dev);
4793         if (!dev_priv)
4794                 return rte_flow_error_set(error, rte_errno,
4795                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4796                                           NULL,
4797                                           "failed to obtain E-Switch info");
4798         port_id = action->conf;
4799         port = port_id->original ? dev->data->port_id : port_id->id;
4800         act_priv = mlx5_port_to_eswitch_info(port, false);
4801         if (!act_priv)
4802                 return rte_flow_error_set
4803                                 (error, rte_errno,
4804                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4805                                  "failed to obtain E-Switch port id for port");
4806         if (act_priv->domain_id != dev_priv->domain_id)
4807                 return rte_flow_error_set
4808                                 (error, EINVAL,
4809                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4810                                  "port does not belong to"
4811                                  " E-Switch being configured");
4812         return 0;
4813 }
4814
4815 /**
4816  * Get the maximum number of modify header actions.
4817  *
4818  * @param dev
4819  *   Pointer to rte_eth_dev structure.
4820  * @param flags
4821  *   Flags bits to check if root level.
4822  *
4823  * @return
4824  *   Max number of modify header actions device can support.
4825  */
4826 static inline unsigned int
4827 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4828                               uint64_t flags)
4829 {
4830         /*
4831          * There's no way to directly query the max capacity from FW.
4832          * The maximal value on root table should be assumed to be supported.
4833          */
4834         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4835                 return MLX5_MAX_MODIFY_NUM;
4836         else
4837                 return MLX5_ROOT_TBL_MODIFY_NUM;
4838 }
4839
4840 /**
4841  * Validate the meter action.
4842  *
4843  * @param[in] dev
4844  *   Pointer to rte_eth_dev structure.
4845  * @param[in] action_flags
4846  *   Bit-fields that holds the actions detected until now.
4847  * @param[in] action
4848  *   Pointer to the meter action.
4849  * @param[in] attr
4850  *   Attributes of flow that includes this action.
4851  * @param[out] error
4852  *   Pointer to error structure.
4853  *
4854  * @return
4855  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4856  */
4857 static int
4858 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4859                                 uint64_t action_flags,
4860                                 const struct rte_flow_action *action,
4861                                 const struct rte_flow_attr *attr,
4862                                 struct rte_flow_error *error)
4863 {
4864         struct mlx5_priv *priv = dev->data->dev_private;
4865         const struct rte_flow_action_meter *am = action->conf;
4866         struct mlx5_flow_meter *fm;
4867
4868         if (!am)
4869                 return rte_flow_error_set(error, EINVAL,
4870                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4871                                           "meter action conf is NULL");
4872
4873         if (action_flags & MLX5_FLOW_ACTION_METER)
4874                 return rte_flow_error_set(error, ENOTSUP,
4875                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4876                                           "meter chaining not support");
4877         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4878                 return rte_flow_error_set(error, ENOTSUP,
4879                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4880                                           "meter with jump not support");
4881         if (!priv->mtr_en)
4882                 return rte_flow_error_set(error, ENOTSUP,
4883                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4884                                           NULL,
4885                                           "meter action not supported");
4886         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4887         if (!fm)
4888                 return rte_flow_error_set(error, EINVAL,
4889                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4890                                           "Meter not found");
4891         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4892               (!fm->ingress && !attr->ingress && attr->egress) ||
4893               (!fm->egress && !attr->egress && attr->ingress))))
4894                 return rte_flow_error_set(error, EINVAL,
4895                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4896                                           "Flow attributes are either invalid "
4897                                           "or have a conflict with current "
4898                                           "meter attributes");
4899         return 0;
4900 }
4901
4902 /**
4903  * Validate the age action.
4904  *
4905  * @param[in] action_flags
4906  *   Holds the actions detected until now.
4907  * @param[in] action
4908  *   Pointer to the age action.
4909  * @param[in] dev
4910  *   Pointer to the Ethernet device structure.
4911  * @param[out] error
4912  *   Pointer to error structure.
4913  *
4914  * @return
4915  *   0 on success, a negative errno value otherwise and rte_errno is set.
4916  */
4917 static int
4918 flow_dv_validate_action_age(uint64_t action_flags,
4919                             const struct rte_flow_action *action,
4920                             struct rte_eth_dev *dev,
4921                             struct rte_flow_error *error)
4922 {
4923         struct mlx5_priv *priv = dev->data->dev_private;
4924         const struct rte_flow_action_age *age = action->conf;
4925
4926         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4927             !priv->sh->aso_age_mng))
4928                 return rte_flow_error_set(error, ENOTSUP,
4929                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4930                                           NULL,
4931                                           "age action not supported");
4932         if (!(action->conf))
4933                 return rte_flow_error_set(error, EINVAL,
4934                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4935                                           "configuration cannot be null");
4936         if (!(age->timeout))
4937                 return rte_flow_error_set(error, EINVAL,
4938                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4939                                           "invalid timeout value 0");
4940         if (action_flags & MLX5_FLOW_ACTION_AGE)
4941                 return rte_flow_error_set(error, EINVAL,
4942                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4943                                           "duplicate age actions set");
4944         return 0;
4945 }
4946
4947 /**
4948  * Validate the modify-header IPv4 DSCP actions.
4949  *
4950  * @param[in] action_flags
4951  *   Holds the actions detected until now.
4952  * @param[in] action
4953  *   Pointer to the modify action.
4954  * @param[in] item_flags
4955  *   Holds the items detected.
4956  * @param[out] error
4957  *   Pointer to error structure.
4958  *
4959  * @return
4960  *   0 on success, a negative errno value otherwise and rte_errno is set.
4961  */
4962 static int
4963 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4964                                          const struct rte_flow_action *action,
4965                                          const uint64_t item_flags,
4966                                          struct rte_flow_error *error)
4967 {
4968         int ret = 0;
4969
4970         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4971         if (!ret) {
4972                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4973                         return rte_flow_error_set(error, EINVAL,
4974                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4975                                                   NULL,
4976                                                   "no ipv4 item in pattern");
4977         }
4978         return ret;
4979 }
4980
4981 /**
4982  * Validate the modify-header IPv6 DSCP actions.
4983  *
4984  * @param[in] action_flags
4985  *   Holds the actions detected until now.
4986  * @param[in] action
4987  *   Pointer to the modify action.
4988  * @param[in] item_flags
4989  *   Holds the items detected.
4990  * @param[out] error
4991  *   Pointer to error structure.
4992  *
4993  * @return
4994  *   0 on success, a negative errno value otherwise and rte_errno is set.
4995  */
4996 static int
4997 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4998                                          const struct rte_flow_action *action,
4999                                          const uint64_t item_flags,
5000                                          struct rte_flow_error *error)
5001 {
5002         int ret = 0;
5003
5004         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5005         if (!ret) {
5006                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5007                         return rte_flow_error_set(error, EINVAL,
5008                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5009                                                   NULL,
5010                                                   "no ipv6 item in pattern");
5011         }
5012         return ret;
5013 }
5014
5015 /**
5016  * Match modify-header resource.
5017  *
5018  * @param list
5019  *   Pointer to the hash list.
5020  * @param entry
5021  *   Pointer to exist resource entry object.
5022  * @param key
5023  *   Key of the new entry.
5024  * @param ctx
5025  *   Pointer to new modify-header resource.
5026  *
5027  * @return
5028  *   0 on matching, non-zero otherwise.
5029  */
5030 int
5031 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5032                         struct mlx5_hlist_entry *entry,
5033                         uint64_t key __rte_unused, void *cb_ctx)
5034 {
5035         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5036         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5037         struct mlx5_flow_dv_modify_hdr_resource *resource =
5038                         container_of(entry, typeof(*resource), entry);
5039         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5040
5041         key_len += ref->actions_num * sizeof(ref->actions[0]);
5042         return ref->actions_num != resource->actions_num ||
5043                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5044 }
5045
5046 struct mlx5_hlist_entry *
5047 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5048                          void *cb_ctx)
5049 {
5050         struct mlx5_dev_ctx_shared *sh = list->ctx;
5051         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5052         struct mlx5dv_dr_domain *ns;
5053         struct mlx5_flow_dv_modify_hdr_resource *entry;
5054         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5055         int ret;
5056         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5057         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5058
5059         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5060                             SOCKET_ID_ANY);
5061         if (!entry) {
5062                 rte_flow_error_set(ctx->error, ENOMEM,
5063                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5064                                    "cannot allocate resource memory");
5065                 return NULL;
5066         }
5067         rte_memcpy(&entry->ft_type,
5068                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5069                    key_len + data_len);
5070         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5071                 ns = sh->fdb_domain;
5072         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5073                 ns = sh->tx_domain;
5074         else
5075                 ns = sh->rx_domain;
5076         ret = mlx5_flow_os_create_flow_action_modify_header
5077                                         (sh->ctx, ns, entry,
5078                                          data_len, &entry->action);
5079         if (ret) {
5080                 mlx5_free(entry);
5081                 rte_flow_error_set(ctx->error, ENOMEM,
5082                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5083                                    NULL, "cannot create modification action");
5084                 return NULL;
5085         }
5086         return &entry->entry;
5087 }
5088
5089 /**
5090  * Validate the sample action.
5091  *
5092  * @param[in, out] action_flags
5093  *   Holds the actions detected until now.
5094  * @param[in] action
5095  *   Pointer to the sample action.
5096  * @param[in] dev
5097  *   Pointer to the Ethernet device structure.
5098  * @param[in] attr
5099  *   Attributes of flow that includes this action.
5100  * @param[in] item_flags
5101  *   Holds the items detected.
5102  * @param[in] rss
5103  *   Pointer to the RSS action.
5104  * @param[out] sample_rss
5105  *   Pointer to the RSS action in sample action list.
5106  * @param[out] count
5107  *   Pointer to the COUNT action in sample action list.
5108  * @param[out] fdb_mirror_limit
5109  *   Pointer to the FDB mirror limitation flag.
5110  * @param[out] error
5111  *   Pointer to error structure.
5112  *
5113  * @return
5114  *   0 on success, a negative errno value otherwise and rte_errno is set.
5115  */
5116 static int
5117 flow_dv_validate_action_sample(uint64_t *action_flags,
5118                                const struct rte_flow_action *action,
5119                                struct rte_eth_dev *dev,
5120                                const struct rte_flow_attr *attr,
5121                                uint64_t item_flags,
5122                                const struct rte_flow_action_rss *rss,
5123                                const struct rte_flow_action_rss **sample_rss,
5124                                const struct rte_flow_action_count **count,
5125                                int *fdb_mirror_limit,
5126                                struct rte_flow_error *error)
5127 {
5128         struct mlx5_priv *priv = dev->data->dev_private;
5129         struct mlx5_dev_config *dev_conf = &priv->config;
5130         const struct rte_flow_action_sample *sample = action->conf;
5131         const struct rte_flow_action *act;
5132         uint64_t sub_action_flags = 0;
5133         uint16_t queue_index = 0xFFFF;
5134         int actions_n = 0;
5135         int ret;
5136
5137         if (!sample)
5138                 return rte_flow_error_set(error, EINVAL,
5139                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5140                                           "configuration cannot be NULL");
5141         if (sample->ratio == 0)
5142                 return rte_flow_error_set(error, EINVAL,
5143                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5144                                           "ratio value starts from 1");
5145         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5146                 return rte_flow_error_set(error, ENOTSUP,
5147                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5148                                           NULL,
5149                                           "sample action not supported");
5150         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5151                 return rte_flow_error_set(error, EINVAL,
5152                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5153                                           "Multiple sample actions not "
5154                                           "supported");
5155         if (*action_flags & MLX5_FLOW_ACTION_METER)
5156                 return rte_flow_error_set(error, EINVAL,
5157                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5158                                           "wrong action order, meter should "
5159                                           "be after sample action");
5160         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5161                 return rte_flow_error_set(error, EINVAL,
5162                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5163                                           "wrong action order, jump should "
5164                                           "be after sample action");
5165         act = sample->actions;
5166         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5167                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5168                         return rte_flow_error_set(error, ENOTSUP,
5169                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5170                                                   act, "too many actions");
5171                 switch (act->type) {
5172                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5173                         ret = mlx5_flow_validate_action_queue(act,
5174                                                               sub_action_flags,
5175                                                               dev,
5176                                                               attr, error);
5177                         if (ret < 0)
5178                                 return ret;
5179                         queue_index = ((const struct rte_flow_action_queue *)
5180                                                         (act->conf))->index;
5181                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5182                         ++actions_n;
5183                         break;
5184                 case RTE_FLOW_ACTION_TYPE_RSS:
5185                         *sample_rss = act->conf;
5186                         ret = mlx5_flow_validate_action_rss(act,
5187                                                             sub_action_flags,
5188                                                             dev, attr,
5189                                                             item_flags,
5190                                                             error);
5191                         if (ret < 0)
5192                                 return ret;
5193                         if (rss && *sample_rss &&
5194                             ((*sample_rss)->level != rss->level ||
5195                             (*sample_rss)->types != rss->types))
5196                                 return rte_flow_error_set(error, ENOTSUP,
5197                                         RTE_FLOW_ERROR_TYPE_ACTION,
5198                                         NULL,
5199                                         "Can't use the different RSS types "
5200                                         "or level in the same flow");
5201                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5202                                 queue_index = (*sample_rss)->queue[0];
5203                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5204                         ++actions_n;
5205                         break;
5206                 case RTE_FLOW_ACTION_TYPE_MARK:
5207                         ret = flow_dv_validate_action_mark(dev, act,
5208                                                            sub_action_flags,
5209                                                            attr, error);
5210                         if (ret < 0)
5211                                 return ret;
5212                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5213                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5214                                                 MLX5_FLOW_ACTION_MARK_EXT;
5215                         else
5216                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5217                         ++actions_n;
5218                         break;
5219                 case RTE_FLOW_ACTION_TYPE_COUNT:
5220                         ret = flow_dv_validate_action_count
5221                                 (dev, act,
5222                                  *action_flags | sub_action_flags,
5223                                  error);
5224                         if (ret < 0)
5225                                 return ret;
5226                         *count = act->conf;
5227                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5228                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5229                         ++actions_n;
5230                         break;
5231                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5232                         ret = flow_dv_validate_action_port_id(dev,
5233                                                               sub_action_flags,
5234                                                               act,
5235                                                               attr,
5236                                                               error);
5237                         if (ret)
5238                                 return ret;
5239                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5240                         ++actions_n;
5241                         break;
5242                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5243                         ret = flow_dv_validate_action_raw_encap_decap
5244                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5245                                  &actions_n, action, item_flags, error);
5246                         if (ret < 0)
5247                                 return ret;
5248                         ++actions_n;
5249                         break;
5250                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5251                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5252                         ret = flow_dv_validate_action_l2_encap(dev,
5253                                                                sub_action_flags,
5254                                                                act, attr,
5255                                                                error);
5256                         if (ret < 0)
5257                                 return ret;
5258                         sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5259                         ++actions_n;
5260                         break;
5261                 default:
5262                         return rte_flow_error_set(error, ENOTSUP,
5263                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5264                                                   NULL,
5265                                                   "Doesn't support optional "
5266                                                   "action");
5267                 }
5268         }
5269         if (attr->ingress && !attr->transfer) {
5270                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5271                                           MLX5_FLOW_ACTION_RSS)))
5272                         return rte_flow_error_set(error, EINVAL,
5273                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5274                                                   NULL,
5275                                                   "Ingress must has a dest "
5276                                                   "QUEUE for Sample");
5277         } else if (attr->egress && !attr->transfer) {
5278                 return rte_flow_error_set(error, ENOTSUP,
5279                                           RTE_FLOW_ERROR_TYPE_ACTION,
5280                                           NULL,
5281                                           "Sample Only support Ingress "
5282                                           "or E-Switch");
5283         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5284                 MLX5_ASSERT(attr->transfer);
5285                 if (sample->ratio > 1)
5286                         return rte_flow_error_set(error, ENOTSUP,
5287                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5288                                                   NULL,
5289                                                   "E-Switch doesn't support "
5290                                                   "any optional action "
5291                                                   "for sampling");
5292                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5293                         return rte_flow_error_set(error, ENOTSUP,
5294                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5295                                                   NULL,
5296                                                   "unsupported action QUEUE");
5297                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5298                         return rte_flow_error_set(error, ENOTSUP,
5299                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5300                                                   NULL,
5301                                                   "unsupported action QUEUE");
5302                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5303                         return rte_flow_error_set(error, EINVAL,
5304                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5305                                                   NULL,
5306                                                   "E-Switch must has a dest "
5307                                                   "port for mirroring");
5308                 if (!priv->config.hca_attr.reg_c_preserve &&
5309                      priv->representor_id != -1)
5310                         *fdb_mirror_limit = 1;
5311         }
5312         /* Continue validation for Xcap actions.*/
5313         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5314             (queue_index == 0xFFFF ||
5315              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5316                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5317                      MLX5_FLOW_XCAP_ACTIONS)
5318                         return rte_flow_error_set(error, ENOTSUP,
5319                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5320                                                   NULL, "encap and decap "
5321                                                   "combination aren't "
5322                                                   "supported");
5323                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5324                                                         MLX5_FLOW_ACTION_ENCAP))
5325                         return rte_flow_error_set(error, ENOTSUP,
5326                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5327                                                   NULL, "encap is not supported"
5328                                                   " for ingress traffic");
5329         }
5330         return 0;
5331 }
5332
5333 /**
5334  * Find existing modify-header resource or create and register a new one.
5335  *
5336  * @param dev[in, out]
5337  *   Pointer to rte_eth_dev structure.
5338  * @param[in, out] resource
5339  *   Pointer to modify-header resource.
5340  * @parm[in, out] dev_flow
5341  *   Pointer to the dev_flow.
5342  * @param[out] error
5343  *   pointer to error structure.
5344  *
5345  * @return
5346  *   0 on success otherwise -errno and errno is set.
5347  */
5348 static int
5349 flow_dv_modify_hdr_resource_register
5350                         (struct rte_eth_dev *dev,
5351                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5352                          struct mlx5_flow *dev_flow,
5353                          struct rte_flow_error *error)
5354 {
5355         struct mlx5_priv *priv = dev->data->dev_private;
5356         struct mlx5_dev_ctx_shared *sh = priv->sh;
5357         uint32_t key_len = sizeof(*resource) -
5358                            offsetof(typeof(*resource), ft_type) +
5359                            resource->actions_num * sizeof(resource->actions[0]);
5360         struct mlx5_hlist_entry *entry;
5361         struct mlx5_flow_cb_ctx ctx = {
5362                 .error = error,
5363                 .data = resource,
5364         };
5365         uint64_t key64;
5366
5367         resource->flags = dev_flow->dv.group ? 0 :
5368                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5369         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5370                                     resource->flags))
5371                 return rte_flow_error_set(error, EOVERFLOW,
5372                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5373                                           "too many modify header items");
5374         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5375         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5376         if (!entry)
5377                 return -rte_errno;
5378         resource = container_of(entry, typeof(*resource), entry);
5379         dev_flow->handle->dvh.modify_hdr = resource;
5380         return 0;
5381 }
5382
5383 /**
5384  * Get DV flow counter by index.
5385  *
5386  * @param[in] dev
5387  *   Pointer to the Ethernet device structure.
5388  * @param[in] idx
5389  *   mlx5 flow counter index in the container.
5390  * @param[out] ppool
5391  *   mlx5 flow counter pool in the container,
5392  *
5393  * @return
5394  *   Pointer to the counter, NULL otherwise.
5395  */
5396 static struct mlx5_flow_counter *
5397 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5398                            uint32_t idx,
5399                            struct mlx5_flow_counter_pool **ppool)
5400 {
5401         struct mlx5_priv *priv = dev->data->dev_private;
5402         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5403         struct mlx5_flow_counter_pool *pool;
5404
5405         /* Decrease to original index and clear shared bit. */
5406         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5407         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5408         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5409         MLX5_ASSERT(pool);
5410         if (ppool)
5411                 *ppool = pool;
5412         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5413 }
5414
5415 /**
5416  * Check the devx counter belongs to the pool.
5417  *
5418  * @param[in] pool
5419  *   Pointer to the counter pool.
5420  * @param[in] id
5421  *   The counter devx ID.
5422  *
5423  * @return
5424  *   True if counter belongs to the pool, false otherwise.
5425  */
5426 static bool
5427 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5428 {
5429         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5430                    MLX5_COUNTERS_PER_POOL;
5431
5432         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5433                 return true;
5434         return false;
5435 }
5436
5437 /**
5438  * Get a pool by devx counter ID.
5439  *
5440  * @param[in] cmng
5441  *   Pointer to the counter management.
5442  * @param[in] id
5443  *   The counter devx ID.
5444  *
5445  * @return
5446  *   The counter pool pointer if exists, NULL otherwise,
5447  */
5448 static struct mlx5_flow_counter_pool *
5449 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5450 {
5451         uint32_t i;
5452         struct mlx5_flow_counter_pool *pool = NULL;
5453
5454         rte_spinlock_lock(&cmng->pool_update_sl);
5455         /* Check last used pool. */
5456         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5457             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5458                 pool = cmng->pools[cmng->last_pool_idx];
5459                 goto out;
5460         }
5461         /* ID out of range means no suitable pool in the container. */
5462         if (id > cmng->max_id || id < cmng->min_id)
5463                 goto out;
5464         /*
5465          * Find the pool from the end of the container, since mostly counter
5466          * ID is sequence increasing, and the last pool should be the needed
5467          * one.
5468          */
5469         i = cmng->n_valid;
5470         while (i--) {
5471                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5472
5473                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5474                         pool = pool_tmp;
5475                         break;
5476                 }
5477         }
5478 out:
5479         rte_spinlock_unlock(&cmng->pool_update_sl);
5480         return pool;
5481 }
5482
5483 /**
5484  * Resize a counter container.
5485  *
5486  * @param[in] dev
5487  *   Pointer to the Ethernet device structure.
5488  *
5489  * @return
5490  *   0 on success, otherwise negative errno value and rte_errno is set.
5491  */
5492 static int
5493 flow_dv_container_resize(struct rte_eth_dev *dev)
5494 {
5495         struct mlx5_priv *priv = dev->data->dev_private;
5496         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5497         void *old_pools = cmng->pools;
5498         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5499         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5500         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5501
5502         if (!pools) {
5503                 rte_errno = ENOMEM;
5504                 return -ENOMEM;
5505         }
5506         if (old_pools)
5507                 memcpy(pools, old_pools, cmng->n *
5508                                        sizeof(struct mlx5_flow_counter_pool *));
5509         cmng->n = resize;
5510         cmng->pools = pools;
5511         if (old_pools)
5512                 mlx5_free(old_pools);
5513         return 0;
5514 }
5515
5516 /**
5517  * Query a devx flow counter.
5518  *
5519  * @param[in] dev
5520  *   Pointer to the Ethernet device structure.
5521  * @param[in] cnt
5522  *   Index to the flow counter.
5523  * @param[out] pkts
5524  *   The statistics value of packets.
5525  * @param[out] bytes
5526  *   The statistics value of bytes.
5527  *
5528  * @return
5529  *   0 on success, otherwise a negative errno value and rte_errno is set.
5530  */
5531 static inline int
5532 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5533                      uint64_t *bytes)
5534 {
5535         struct mlx5_priv *priv = dev->data->dev_private;
5536         struct mlx5_flow_counter_pool *pool = NULL;
5537         struct mlx5_flow_counter *cnt;
5538         int offset;
5539
5540         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5541         MLX5_ASSERT(pool);
5542         if (priv->sh->cmng.counter_fallback)
5543                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5544                                         0, pkts, bytes, 0, NULL, NULL, 0);
5545         rte_spinlock_lock(&pool->sl);
5546         if (!pool->raw) {
5547                 *pkts = 0;
5548                 *bytes = 0;
5549         } else {
5550                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5551                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5552                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5553         }
5554         rte_spinlock_unlock(&pool->sl);
5555         return 0;
5556 }
5557
5558 /**
5559  * Create and initialize a new counter pool.
5560  *
5561  * @param[in] dev
5562  *   Pointer to the Ethernet device structure.
5563  * @param[out] dcs
5564  *   The devX counter handle.
5565  * @param[in] age
5566  *   Whether the pool is for counter that was allocated for aging.
5567  * @param[in/out] cont_cur
5568  *   Pointer to the container pointer, it will be update in pool resize.
5569  *
5570  * @return
5571  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5572  */
5573 static struct mlx5_flow_counter_pool *
5574 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5575                     uint32_t age)
5576 {
5577         struct mlx5_priv *priv = dev->data->dev_private;
5578         struct mlx5_flow_counter_pool *pool;
5579         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5580         bool fallback = priv->sh->cmng.counter_fallback;
5581         uint32_t size = sizeof(*pool);
5582
5583         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5584         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5585         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5586         if (!pool) {
5587                 rte_errno = ENOMEM;
5588                 return NULL;
5589         }
5590         pool->raw = NULL;
5591         pool->is_aged = !!age;
5592         pool->query_gen = 0;
5593         pool->min_dcs = dcs;
5594         rte_spinlock_init(&pool->sl);
5595         rte_spinlock_init(&pool->csl);
5596         TAILQ_INIT(&pool->counters[0]);
5597         TAILQ_INIT(&pool->counters[1]);
5598         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5599         rte_spinlock_lock(&cmng->pool_update_sl);
5600         pool->index = cmng->n_valid;
5601         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5602                 mlx5_free(pool);
5603                 rte_spinlock_unlock(&cmng->pool_update_sl);
5604                 return NULL;
5605         }
5606         cmng->pools[pool->index] = pool;
5607         cmng->n_valid++;
5608         if (unlikely(fallback)) {
5609                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5610
5611                 if (base < cmng->min_id)
5612                         cmng->min_id = base;
5613                 if (base > cmng->max_id)
5614                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5615                 cmng->last_pool_idx = pool->index;
5616         }
5617         rte_spinlock_unlock(&cmng->pool_update_sl);
5618         return pool;
5619 }
5620
5621 /**
5622  * Prepare a new counter and/or a new counter pool.
5623  *
5624  * @param[in] dev
5625  *   Pointer to the Ethernet device structure.
5626  * @param[out] cnt_free
5627  *   Where to put the pointer of a new counter.
5628  * @param[in] age
5629  *   Whether the pool is for counter that was allocated for aging.
5630  *
5631  * @return
5632  *   The counter pool pointer and @p cnt_free is set on success,
5633  *   NULL otherwise and rte_errno is set.
5634  */
5635 static struct mlx5_flow_counter_pool *
5636 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5637                              struct mlx5_flow_counter **cnt_free,
5638                              uint32_t age)
5639 {
5640         struct mlx5_priv *priv = dev->data->dev_private;
5641         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5642         struct mlx5_flow_counter_pool *pool;
5643         struct mlx5_counters tmp_tq;
5644         struct mlx5_devx_obj *dcs = NULL;
5645         struct mlx5_flow_counter *cnt;
5646         enum mlx5_counter_type cnt_type =
5647                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5648         bool fallback = priv->sh->cmng.counter_fallback;
5649         uint32_t i;
5650
5651         if (fallback) {
5652                 /* bulk_bitmap must be 0 for single counter allocation. */
5653                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5654                 if (!dcs)
5655                         return NULL;
5656                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5657                 if (!pool) {
5658                         pool = flow_dv_pool_create(dev, dcs, age);
5659                         if (!pool) {
5660                                 mlx5_devx_cmd_destroy(dcs);
5661                                 return NULL;
5662                         }
5663                 }
5664                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5665                 cnt = MLX5_POOL_GET_CNT(pool, i);
5666                 cnt->pool = pool;
5667                 cnt->dcs_when_free = dcs;
5668                 *cnt_free = cnt;
5669                 return pool;
5670         }
5671         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5672         if (!dcs) {
5673                 rte_errno = ENODATA;
5674                 return NULL;
5675         }
5676         pool = flow_dv_pool_create(dev, dcs, age);
5677         if (!pool) {
5678                 mlx5_devx_cmd_destroy(dcs);
5679                 return NULL;
5680         }
5681         TAILQ_INIT(&tmp_tq);
5682         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5683                 cnt = MLX5_POOL_GET_CNT(pool, i);
5684                 cnt->pool = pool;
5685                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5686         }
5687         rte_spinlock_lock(&cmng->csl[cnt_type]);
5688         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5689         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5690         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5691         (*cnt_free)->pool = pool;
5692         return pool;
5693 }
5694
5695 /**
5696  * Allocate a flow counter.
5697  *
5698  * @param[in] dev
5699  *   Pointer to the Ethernet device structure.
5700  * @param[in] age
5701  *   Whether the counter was allocated for aging.
5702  *
5703  * @return
5704  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5705  */
5706 static uint32_t
5707 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5708 {
5709         struct mlx5_priv *priv = dev->data->dev_private;
5710         struct mlx5_flow_counter_pool *pool = NULL;
5711         struct mlx5_flow_counter *cnt_free = NULL;
5712         bool fallback = priv->sh->cmng.counter_fallback;
5713         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5714         enum mlx5_counter_type cnt_type =
5715                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5716         uint32_t cnt_idx;
5717
5718         if (!priv->config.devx) {
5719                 rte_errno = ENOTSUP;
5720                 return 0;
5721         }
5722         /* Get free counters from container. */
5723         rte_spinlock_lock(&cmng->csl[cnt_type]);
5724         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5725         if (cnt_free)
5726                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5727         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5728         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5729                 goto err;
5730         pool = cnt_free->pool;
5731         if (fallback)
5732                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5733         /* Create a DV counter action only in the first time usage. */
5734         if (!cnt_free->action) {
5735                 uint16_t offset;
5736                 struct mlx5_devx_obj *dcs;
5737                 int ret;
5738
5739                 if (!fallback) {
5740                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5741                         dcs = pool->min_dcs;
5742                 } else {
5743                         offset = 0;
5744                         dcs = cnt_free->dcs_when_free;
5745                 }
5746                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5747                                                             &cnt_free->action);
5748                 if (ret) {
5749                         rte_errno = errno;
5750                         goto err;
5751                 }
5752         }
5753         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5754                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5755         /* Update the counter reset values. */
5756         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5757                                  &cnt_free->bytes))
5758                 goto err;
5759         if (!fallback && !priv->sh->cmng.query_thread_on)
5760                 /* Start the asynchronous batch query by the host thread. */
5761                 mlx5_set_query_alarm(priv->sh);
5762         return cnt_idx;
5763 err:
5764         if (cnt_free) {
5765                 cnt_free->pool = pool;
5766                 if (fallback)
5767                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5768                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5769                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5770                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5771         }
5772         return 0;
5773 }
5774
5775 /**
5776  * Allocate a shared flow counter.
5777  *
5778  * @param[in] ctx
5779  *   Pointer to the shared counter configuration.
5780  * @param[in] data
5781  *   Pointer to save the allocated counter index.
5782  *
5783  * @return
5784  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5785  */
5786
5787 static int32_t
5788 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5789 {
5790         struct mlx5_shared_counter_conf *conf = ctx;
5791         struct rte_eth_dev *dev = conf->dev;
5792         struct mlx5_flow_counter *cnt;
5793
5794         data->dword = flow_dv_counter_alloc(dev, 0);
5795         data->dword |= MLX5_CNT_SHARED_OFFSET;
5796         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5797         cnt->shared_info.id = conf->id;
5798         return 0;
5799 }
5800
5801 /**
5802  * Get a shared flow counter.
5803  *
5804  * @param[in] dev
5805  *   Pointer to the Ethernet device structure.
5806  * @param[in] id
5807  *   Counter identifier.
5808  *
5809  * @return
5810  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5811  */
5812 static uint32_t
5813 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5814 {
5815         struct mlx5_priv *priv = dev->data->dev_private;
5816         struct mlx5_shared_counter_conf conf = {
5817                 .dev = dev,
5818                 .id = id,
5819         };
5820         union mlx5_l3t_data data = {
5821                 .dword = 0,
5822         };
5823
5824         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5825                                flow_dv_counter_alloc_shared_cb, &conf);
5826         return data.dword;
5827 }
5828
5829 /**
5830  * Get age param from counter index.
5831  *
5832  * @param[in] dev
5833  *   Pointer to the Ethernet device structure.
5834  * @param[in] counter
5835  *   Index to the counter handler.
5836  *
5837  * @return
5838  *   The aging parameter specified for the counter index.
5839  */
5840 static struct mlx5_age_param*
5841 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5842                                 uint32_t counter)
5843 {
5844         struct mlx5_flow_counter *cnt;
5845         struct mlx5_flow_counter_pool *pool = NULL;
5846
5847         flow_dv_counter_get_by_idx(dev, counter, &pool);
5848         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5849         cnt = MLX5_POOL_GET_CNT(pool, counter);
5850         return MLX5_CNT_TO_AGE(cnt);
5851 }
5852
5853 /**
5854  * Remove a flow counter from aged counter list.
5855  *
5856  * @param[in] dev
5857  *   Pointer to the Ethernet device structure.
5858  * @param[in] counter
5859  *   Index to the counter handler.
5860  * @param[in] cnt
5861  *   Pointer to the counter handler.
5862  */
5863 static void
5864 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5865                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5866 {
5867         struct mlx5_age_info *age_info;
5868         struct mlx5_age_param *age_param;
5869         struct mlx5_priv *priv = dev->data->dev_private;
5870         uint16_t expected = AGE_CANDIDATE;
5871
5872         age_info = GET_PORT_AGE_INFO(priv);
5873         age_param = flow_dv_counter_idx_get_age(dev, counter);
5874         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5875                                          AGE_FREE, false, __ATOMIC_RELAXED,
5876                                          __ATOMIC_RELAXED)) {
5877                 /**
5878                  * We need the lock even it is age timeout,
5879                  * since counter may still in process.
5880                  */
5881                 rte_spinlock_lock(&age_info->aged_sl);
5882                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5883                 rte_spinlock_unlock(&age_info->aged_sl);
5884                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5885         }
5886 }
5887
5888 /**
5889  * Release a flow counter.
5890  *
5891  * @param[in] dev
5892  *   Pointer to the Ethernet device structure.
5893  * @param[in] counter
5894  *   Index to the counter handler.
5895  */
5896 static void
5897 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5898 {
5899         struct mlx5_priv *priv = dev->data->dev_private;
5900         struct mlx5_flow_counter_pool *pool = NULL;
5901         struct mlx5_flow_counter *cnt;
5902         enum mlx5_counter_type cnt_type;
5903
5904         if (!counter)
5905                 return;
5906         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5907         MLX5_ASSERT(pool);
5908         if (IS_SHARED_CNT(counter) &&
5909             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5910                 return;
5911         if (pool->is_aged)
5912                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5913         cnt->pool = pool;
5914         /*
5915          * Put the counter back to list to be updated in none fallback mode.
5916          * Currently, we are using two list alternately, while one is in query,
5917          * add the freed counter to the other list based on the pool query_gen
5918          * value. After query finishes, add counter the list to the global
5919          * container counter list. The list changes while query starts. In
5920          * this case, lock will not be needed as query callback and release
5921          * function both operate with the different list.
5922          *
5923          */
5924         if (!priv->sh->cmng.counter_fallback) {
5925                 rte_spinlock_lock(&pool->csl);
5926                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5927                 rte_spinlock_unlock(&pool->csl);
5928         } else {
5929                 cnt->dcs_when_free = cnt->dcs_when_active;
5930                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5931                                            MLX5_COUNTER_TYPE_ORIGIN;
5932                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5933                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5934                                   cnt, next);
5935                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5936         }
5937 }
5938
5939 /**
5940  * Verify the @p attributes will be correctly understood by the NIC and store
5941  * them in the @p flow if everything is correct.
5942  *
5943  * @param[in] dev
5944  *   Pointer to dev struct.
5945  * @param[in] attributes
5946  *   Pointer to flow attributes
5947  * @param[in] external
5948  *   This flow rule is created by request external to PMD.
5949  * @param[out] error
5950  *   Pointer to error structure.
5951  *
5952  * @return
5953  *   - 0 on success and non root table.
5954  *   - 1 on success and root table.
5955  *   - a negative errno value otherwise and rte_errno is set.
5956  */
5957 static int
5958 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5959                             const struct mlx5_flow_tunnel *tunnel,
5960                             const struct rte_flow_attr *attributes,
5961                             const struct flow_grp_info *grp_info,
5962                             struct rte_flow_error *error)
5963 {
5964         struct mlx5_priv *priv = dev->data->dev_private;
5965         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5966         int ret = 0;
5967
5968 #ifndef HAVE_MLX5DV_DR
5969         RTE_SET_USED(tunnel);
5970         RTE_SET_USED(grp_info);
5971         if (attributes->group)
5972                 return rte_flow_error_set(error, ENOTSUP,
5973                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5974                                           NULL,
5975                                           "groups are not supported");
5976 #else
5977         uint32_t table = 0;
5978
5979         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5980                                        grp_info, error);
5981         if (ret)
5982                 return ret;
5983         if (!table)
5984                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5985 #endif
5986         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5987             attributes->priority > lowest_priority)
5988                 return rte_flow_error_set(error, ENOTSUP,
5989                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5990                                           NULL,
5991                                           "priority out of range");
5992         if (attributes->transfer) {
5993                 if (!priv->config.dv_esw_en)
5994                         return rte_flow_error_set
5995                                 (error, ENOTSUP,
5996                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5997                                  "E-Switch dr is not supported");
5998                 if (!(priv->representor || priv->master))
5999                         return rte_flow_error_set
6000                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6001                                  NULL, "E-Switch configuration can only be"
6002                                  " done by a master or a representor device");
6003                 if (attributes->egress)
6004                         return rte_flow_error_set
6005                                 (error, ENOTSUP,
6006                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6007                                  "egress is not supported");
6008         }
6009         if (!(attributes->egress ^ attributes->ingress))
6010                 return rte_flow_error_set(error, ENOTSUP,
6011                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6012                                           "must specify exactly one of "
6013                                           "ingress or egress");
6014         return ret;
6015 }
6016
6017 /**
6018  * Internal validation function. For validating both actions and items.
6019  *
6020  * @param[in] dev
6021  *   Pointer to the rte_eth_dev structure.
6022  * @param[in] attr
6023  *   Pointer to the flow attributes.
6024  * @param[in] items
6025  *   Pointer to the list of items.
6026  * @param[in] actions
6027  *   Pointer to the list of actions.
6028  * @param[in] external
6029  *   This flow rule is created by request external to PMD.
6030  * @param[in] hairpin
6031  *   Number of hairpin TX actions, 0 means classic flow.
6032  * @param[out] error
6033  *   Pointer to the error structure.
6034  *
6035  * @return
6036  *   0 on success, a negative errno value otherwise and rte_errno is set.
6037  */
6038 static int
6039 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6040                  const struct rte_flow_item items[],
6041                  const struct rte_flow_action actions[],
6042                  bool external, int hairpin, struct rte_flow_error *error)
6043 {
6044         int ret;
6045         uint64_t action_flags = 0;
6046         uint64_t item_flags = 0;
6047         uint64_t last_item = 0;
6048         uint8_t next_protocol = 0xff;
6049         uint16_t ether_type = 0;
6050         int actions_n = 0;
6051         uint8_t item_ipv6_proto = 0;
6052         int fdb_mirror_limit = 0;
6053         int modify_after_mirror = 0;
6054         const struct rte_flow_item *geneve_item = NULL;
6055         const struct rte_flow_item *gre_item = NULL;
6056         const struct rte_flow_item *gtp_item = NULL;
6057         const struct rte_flow_action_raw_decap *decap;
6058         const struct rte_flow_action_raw_encap *encap;
6059         const struct rte_flow_action_rss *rss = NULL;
6060         const struct rte_flow_action_rss *sample_rss = NULL;
6061         const struct rte_flow_action_count *count = NULL;
6062         const struct rte_flow_action_count *sample_count = NULL;
6063         const struct rte_flow_item_tcp nic_tcp_mask = {
6064                 .hdr = {
6065                         .tcp_flags = 0xFF,
6066                         .src_port = RTE_BE16(UINT16_MAX),
6067                         .dst_port = RTE_BE16(UINT16_MAX),
6068                 }
6069         };
6070         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6071                 .hdr = {
6072                         .src_addr =
6073                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6074                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6075                         .dst_addr =
6076                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6077                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6078                         .vtc_flow = RTE_BE32(0xffffffff),
6079                         .proto = 0xff,
6080                         .hop_limits = 0xff,
6081                 },
6082                 .has_frag_ext = 1,
6083         };
6084         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6085                 .hdr = {
6086                         .common = {
6087                                 .u32 =
6088                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6089                                         .type = 0xFF,
6090                                         }).u32),
6091                         },
6092                         .dummy[0] = 0xffffffff,
6093                 },
6094         };
6095         struct mlx5_priv *priv = dev->data->dev_private;
6096         struct mlx5_dev_config *dev_conf = &priv->config;
6097         uint16_t queue_index = 0xFFFF;
6098         const struct rte_flow_item_vlan *vlan_m = NULL;
6099         uint32_t rw_act_num = 0;
6100         uint64_t is_root;
6101         const struct mlx5_flow_tunnel *tunnel;
6102         struct flow_grp_info grp_info = {
6103                 .external = !!external,
6104                 .transfer = !!attr->transfer,
6105                 .fdb_def_rule = !!priv->fdb_def_rule,
6106         };
6107         const struct rte_eth_hairpin_conf *conf;
6108
6109         if (items == NULL)
6110                 return -1;
6111         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6112                 tunnel = flow_items_to_tunnel(items);
6113                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6114                                 MLX5_FLOW_ACTION_DECAP;
6115         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6116                 tunnel = flow_actions_to_tunnel(actions);
6117                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6118         } else {
6119                 tunnel = NULL;
6120         }
6121         if (tunnel && priv->representor)
6122                 return rte_flow_error_set(error, ENOTSUP,
6123                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6124                                           "decap not supported "
6125                                           "for VF representor");
6126         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6127                                 (dev, tunnel, attr, items, actions);
6128         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6129         if (ret < 0)
6130                 return ret;
6131         is_root = (uint64_t)ret;
6132         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6133                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6134                 int type = items->type;
6135
6136                 if (!mlx5_flow_os_item_supported(type))
6137                         return rte_flow_error_set(error, ENOTSUP,
6138                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6139                                                   NULL, "item not supported");
6140                 switch (type) {
6141                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6142                         if (items[0].type != (typeof(items[0].type))
6143                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6144                                 return rte_flow_error_set
6145                                                 (error, EINVAL,
6146                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6147                                                 NULL, "MLX5 private items "
6148                                                 "must be the first");
6149                         break;
6150                 case RTE_FLOW_ITEM_TYPE_VOID:
6151                         break;
6152                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6153                         ret = flow_dv_validate_item_port_id
6154                                         (dev, items, attr, item_flags, error);
6155                         if (ret < 0)
6156                                 return ret;
6157                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6158                         break;
6159                 case RTE_FLOW_ITEM_TYPE_ETH:
6160                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6161                                                           true, error);
6162                         if (ret < 0)
6163                                 return ret;
6164                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6165                                              MLX5_FLOW_LAYER_OUTER_L2;
6166                         if (items->mask != NULL && items->spec != NULL) {
6167                                 ether_type =
6168                                         ((const struct rte_flow_item_eth *)
6169                                          items->spec)->type;
6170                                 ether_type &=
6171                                         ((const struct rte_flow_item_eth *)
6172                                          items->mask)->type;
6173                                 ether_type = rte_be_to_cpu_16(ether_type);
6174                         } else {
6175                                 ether_type = 0;
6176                         }
6177                         break;
6178                 case RTE_FLOW_ITEM_TYPE_VLAN:
6179                         ret = flow_dv_validate_item_vlan(items, item_flags,
6180                                                          dev, error);
6181                         if (ret < 0)
6182                                 return ret;
6183                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6184                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6185                         if (items->mask != NULL && items->spec != NULL) {
6186                                 ether_type =
6187                                         ((const struct rte_flow_item_vlan *)
6188                                          items->spec)->inner_type;
6189                                 ether_type &=
6190                                         ((const struct rte_flow_item_vlan *)
6191                                          items->mask)->inner_type;
6192                                 ether_type = rte_be_to_cpu_16(ether_type);
6193                         } else {
6194                                 ether_type = 0;
6195                         }
6196                         /* Store outer VLAN mask for of_push_vlan action. */
6197                         if (!tunnel)
6198                                 vlan_m = items->mask;
6199                         break;
6200                 case RTE_FLOW_ITEM_TYPE_IPV4:
6201                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6202                                                   &item_flags, &tunnel);
6203                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6204                                                          last_item, ether_type,
6205                                                          error);
6206                         if (ret < 0)
6207                                 return ret;
6208                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6209                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6210                         if (items->mask != NULL &&
6211                             ((const struct rte_flow_item_ipv4 *)
6212                              items->mask)->hdr.next_proto_id) {
6213                                 next_protocol =
6214                                         ((const struct rte_flow_item_ipv4 *)
6215                                          (items->spec))->hdr.next_proto_id;
6216                                 next_protocol &=
6217                                         ((const struct rte_flow_item_ipv4 *)
6218                                          (items->mask))->hdr.next_proto_id;
6219                         } else {
6220                                 /* Reset for inner layer. */
6221                                 next_protocol = 0xff;
6222                         }
6223                         break;
6224                 case RTE_FLOW_ITEM_TYPE_IPV6:
6225                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6226                                                   &item_flags, &tunnel);
6227                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6228                                                            last_item,
6229                                                            ether_type,
6230                                                            &nic_ipv6_mask,
6231                                                            error);
6232                         if (ret < 0)
6233                                 return ret;
6234                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6235                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6236                         if (items->mask != NULL &&
6237                             ((const struct rte_flow_item_ipv6 *)
6238                              items->mask)->hdr.proto) {
6239                                 item_ipv6_proto =
6240                                         ((const struct rte_flow_item_ipv6 *)
6241                                          items->spec)->hdr.proto;
6242                                 next_protocol =
6243                                         ((const struct rte_flow_item_ipv6 *)
6244                                          items->spec)->hdr.proto;
6245                                 next_protocol &=
6246                                         ((const struct rte_flow_item_ipv6 *)
6247                                          items->mask)->hdr.proto;
6248                         } else {
6249                                 /* Reset for inner layer. */
6250                                 next_protocol = 0xff;
6251                         }
6252                         break;
6253                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6254                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6255                                                                   item_flags,
6256                                                                   error);
6257                         if (ret < 0)
6258                                 return ret;
6259                         last_item = tunnel ?
6260                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6261                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6262                         if (items->mask != NULL &&
6263                             ((const struct rte_flow_item_ipv6_frag_ext *)
6264                              items->mask)->hdr.next_header) {
6265                                 next_protocol =
6266                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6267                                  items->spec)->hdr.next_header;
6268                                 next_protocol &=
6269                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6270                                  items->mask)->hdr.next_header;
6271                         } else {
6272                                 /* Reset for inner layer. */
6273                                 next_protocol = 0xff;
6274                         }
6275                         break;
6276                 case RTE_FLOW_ITEM_TYPE_TCP:
6277                         ret = mlx5_flow_validate_item_tcp
6278                                                 (items, item_flags,
6279                                                  next_protocol,
6280                                                  &nic_tcp_mask,
6281                                                  error);
6282                         if (ret < 0)
6283                                 return ret;
6284                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6285                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6286                         break;
6287                 case RTE_FLOW_ITEM_TYPE_UDP:
6288                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6289                                                           next_protocol,
6290                                                           error);
6291                         if (ret < 0)
6292                                 return ret;
6293                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6294                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6295                         break;
6296                 case RTE_FLOW_ITEM_TYPE_GRE:
6297                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6298                                                           next_protocol, error);
6299                         if (ret < 0)
6300                                 return ret;
6301                         gre_item = items;
6302                         last_item = MLX5_FLOW_LAYER_GRE;
6303                         break;
6304                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6305                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6306                                                             next_protocol,
6307                                                             error);
6308                         if (ret < 0)
6309                                 return ret;
6310                         last_item = MLX5_FLOW_LAYER_NVGRE;
6311                         break;
6312                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6313                         ret = mlx5_flow_validate_item_gre_key
6314                                 (items, item_flags, gre_item, error);
6315                         if (ret < 0)
6316                                 return ret;
6317                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6318                         break;
6319                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6320                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6321                                                             error);
6322                         if (ret < 0)
6323                                 return ret;
6324                         last_item = MLX5_FLOW_LAYER_VXLAN;
6325                         break;
6326                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6327                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6328                                                                 item_flags, dev,
6329                                                                 error);
6330                         if (ret < 0)
6331                                 return ret;
6332                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6333                         break;
6334                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6335                         ret = mlx5_flow_validate_item_geneve(items,
6336                                                              item_flags, dev,
6337                                                              error);
6338                         if (ret < 0)
6339                                 return ret;
6340                         geneve_item = items;
6341                         last_item = MLX5_FLOW_LAYER_GENEVE;
6342                         break;
6343                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6344                         ret = mlx5_flow_validate_item_geneve_opt(items,
6345                                                                  last_item,
6346                                                                  geneve_item,
6347                                                                  dev,
6348                                                                  error);
6349                         if (ret < 0)
6350                                 return ret;
6351                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6352                         break;
6353                 case RTE_FLOW_ITEM_TYPE_MPLS:
6354                         ret = mlx5_flow_validate_item_mpls(dev, items,
6355                                                            item_flags,
6356                                                            last_item, error);
6357                         if (ret < 0)
6358                                 return ret;
6359                         last_item = MLX5_FLOW_LAYER_MPLS;
6360                         break;
6361
6362                 case RTE_FLOW_ITEM_TYPE_MARK:
6363                         ret = flow_dv_validate_item_mark(dev, items, attr,
6364                                                          error);
6365                         if (ret < 0)
6366                                 return ret;
6367                         last_item = MLX5_FLOW_ITEM_MARK;
6368                         break;
6369                 case RTE_FLOW_ITEM_TYPE_META:
6370                         ret = flow_dv_validate_item_meta(dev, items, attr,
6371                                                          error);
6372                         if (ret < 0)
6373                                 return ret;
6374                         last_item = MLX5_FLOW_ITEM_METADATA;
6375                         break;
6376                 case RTE_FLOW_ITEM_TYPE_ICMP:
6377                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6378                                                            next_protocol,
6379                                                            error);
6380                         if (ret < 0)
6381                                 return ret;
6382                         last_item = MLX5_FLOW_LAYER_ICMP;
6383                         break;
6384                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6385                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6386                                                             next_protocol,
6387                                                             error);
6388                         if (ret < 0)
6389                                 return ret;
6390                         item_ipv6_proto = IPPROTO_ICMPV6;
6391                         last_item = MLX5_FLOW_LAYER_ICMP6;
6392                         break;
6393                 case RTE_FLOW_ITEM_TYPE_TAG:
6394                         ret = flow_dv_validate_item_tag(dev, items,
6395                                                         attr, error);
6396                         if (ret < 0)
6397                                 return ret;
6398                         last_item = MLX5_FLOW_ITEM_TAG;
6399                         break;
6400                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6401                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6402                         break;
6403                 case RTE_FLOW_ITEM_TYPE_GTP:
6404                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6405                                                         error);
6406                         if (ret < 0)
6407                                 return ret;
6408                         gtp_item = items;
6409                         last_item = MLX5_FLOW_LAYER_GTP;
6410                         break;
6411                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6412                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6413                                                             gtp_item, attr,
6414                                                             error);
6415                         if (ret < 0)
6416                                 return ret;
6417                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6418                         break;
6419                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6420                         /* Capacity will be checked in the translate stage. */
6421                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6422                                                             last_item,
6423                                                             ether_type,
6424                                                             &nic_ecpri_mask,
6425                                                             error);
6426                         if (ret < 0)
6427                                 return ret;
6428                         last_item = MLX5_FLOW_LAYER_ECPRI;
6429                         break;
6430                 default:
6431                         return rte_flow_error_set(error, ENOTSUP,
6432                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6433                                                   NULL, "item not supported");
6434                 }
6435                 item_flags |= last_item;
6436         }
6437         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6438                 int type = actions->type;
6439
6440                 if (!mlx5_flow_os_action_supported(type))
6441                         return rte_flow_error_set(error, ENOTSUP,
6442                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6443                                                   actions,
6444                                                   "action not supported");
6445                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6446                         return rte_flow_error_set(error, ENOTSUP,
6447                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6448                                                   actions, "too many actions");
6449                 switch (type) {
6450                 case RTE_FLOW_ACTION_TYPE_VOID:
6451                         break;
6452                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6453                         ret = flow_dv_validate_action_port_id(dev,
6454                                                               action_flags,
6455                                                               actions,
6456                                                               attr,
6457                                                               error);
6458                         if (ret)
6459                                 return ret;
6460                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6461                         ++actions_n;
6462                         break;
6463                 case RTE_FLOW_ACTION_TYPE_FLAG:
6464                         ret = flow_dv_validate_action_flag(dev, action_flags,
6465                                                            attr, error);
6466                         if (ret < 0)
6467                                 return ret;
6468                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6469                                 /* Count all modify-header actions as one. */
6470                                 if (!(action_flags &
6471                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6472                                         ++actions_n;
6473                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6474                                                 MLX5_FLOW_ACTION_MARK_EXT;
6475                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6476                                         modify_after_mirror = 1;
6477
6478                         } else {
6479                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6480                                 ++actions_n;
6481                         }
6482                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6483                         break;
6484                 case RTE_FLOW_ACTION_TYPE_MARK:
6485                         ret = flow_dv_validate_action_mark(dev, actions,
6486                                                            action_flags,
6487                                                            attr, error);
6488                         if (ret < 0)
6489                                 return ret;
6490                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6491                                 /* Count all modify-header actions as one. */
6492                                 if (!(action_flags &
6493                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6494                                         ++actions_n;
6495                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6496                                                 MLX5_FLOW_ACTION_MARK_EXT;
6497                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6498                                         modify_after_mirror = 1;
6499                         } else {
6500                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6501                                 ++actions_n;
6502                         }
6503                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6504                         break;
6505                 case RTE_FLOW_ACTION_TYPE_SET_META:
6506                         ret = flow_dv_validate_action_set_meta(dev, actions,
6507                                                                action_flags,
6508                                                                attr, error);
6509                         if (ret < 0)
6510                                 return ret;
6511                         /* Count all modify-header actions as one action. */
6512                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6513                                 ++actions_n;
6514                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6515                                 modify_after_mirror = 1;
6516                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6517                         rw_act_num += MLX5_ACT_NUM_SET_META;
6518                         break;
6519                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6520                         ret = flow_dv_validate_action_set_tag(dev, actions,
6521                                                               action_flags,
6522                                                               attr, error);
6523                         if (ret < 0)
6524                                 return ret;
6525                         /* Count all modify-header actions as one action. */
6526                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6527                                 ++actions_n;
6528                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6529                                 modify_after_mirror = 1;
6530                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6531                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6532                         break;
6533                 case RTE_FLOW_ACTION_TYPE_DROP:
6534                         ret = mlx5_flow_validate_action_drop(action_flags,
6535                                                              attr, error);
6536                         if (ret < 0)
6537                                 return ret;
6538                         action_flags |= MLX5_FLOW_ACTION_DROP;
6539                         ++actions_n;
6540                         break;
6541                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6542                         ret = mlx5_flow_validate_action_queue(actions,
6543                                                               action_flags, dev,
6544                                                               attr, error);
6545                         if (ret < 0)
6546                                 return ret;
6547                         queue_index = ((const struct rte_flow_action_queue *)
6548                                                         (actions->conf))->index;
6549                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6550                         ++actions_n;
6551                         break;
6552                 case RTE_FLOW_ACTION_TYPE_RSS:
6553                         rss = actions->conf;
6554                         ret = mlx5_flow_validate_action_rss(actions,
6555                                                             action_flags, dev,
6556                                                             attr, item_flags,
6557                                                             error);
6558                         if (ret < 0)
6559                                 return ret;
6560                         if (rss && sample_rss &&
6561                             (sample_rss->level != rss->level ||
6562                             sample_rss->types != rss->types))
6563                                 return rte_flow_error_set(error, ENOTSUP,
6564                                         RTE_FLOW_ERROR_TYPE_ACTION,
6565                                         NULL,
6566                                         "Can't use the different RSS types "
6567                                         "or level in the same flow");
6568                         if (rss != NULL && rss->queue_num)
6569                                 queue_index = rss->queue[0];
6570                         action_flags |= MLX5_FLOW_ACTION_RSS;
6571                         ++actions_n;
6572                         break;
6573                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6574                         ret =
6575                         mlx5_flow_validate_action_default_miss(action_flags,
6576                                         attr, error);
6577                         if (ret < 0)
6578                                 return ret;
6579                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6580                         ++actions_n;
6581                         break;
6582                 case RTE_FLOW_ACTION_TYPE_COUNT:
6583                         ret = flow_dv_validate_action_count(dev, actions,
6584                                                             action_flags,
6585                                                             error);
6586                         if (ret < 0)
6587                                 return ret;
6588                         count = actions->conf;
6589                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6590                         ++actions_n;
6591                         break;
6592                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6593                         if (flow_dv_validate_action_pop_vlan(dev,
6594                                                              action_flags,
6595                                                              actions,
6596                                                              item_flags, attr,
6597                                                              error))
6598                                 return -rte_errno;
6599                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6600                         ++actions_n;
6601                         break;
6602                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6603                         ret = flow_dv_validate_action_push_vlan(dev,
6604                                                                 action_flags,
6605                                                                 vlan_m,
6606                                                                 actions, attr,
6607                                                                 error);
6608                         if (ret < 0)
6609                                 return ret;
6610                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6611                         ++actions_n;
6612                         break;
6613                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6614                         ret = flow_dv_validate_action_set_vlan_pcp
6615                                                 (action_flags, actions, error);
6616                         if (ret < 0)
6617                                 return ret;
6618                         /* Count PCP with push_vlan command. */
6619                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6620                         break;
6621                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6622                         ret = flow_dv_validate_action_set_vlan_vid
6623                                                 (item_flags, action_flags,
6624                                                  actions, error);
6625                         if (ret < 0)
6626                                 return ret;
6627                         /* Count VID with push_vlan command. */
6628                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6629                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6630                         break;
6631                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6632                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6633                         ret = flow_dv_validate_action_l2_encap(dev,
6634                                                                action_flags,
6635                                                                actions, attr,
6636                                                                error);
6637                         if (ret < 0)
6638                                 return ret;
6639                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6640                         ++actions_n;
6641                         break;
6642                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6643                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6644                         ret = flow_dv_validate_action_decap(dev, action_flags,
6645                                                             actions, item_flags,
6646                                                             attr, error);
6647                         if (ret < 0)
6648                                 return ret;
6649                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6650                         ++actions_n;
6651                         break;
6652                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6653                         ret = flow_dv_validate_action_raw_encap_decap
6654                                 (dev, NULL, actions->conf, attr, &action_flags,
6655                                  &actions_n, actions, item_flags, error);
6656                         if (ret < 0)
6657                                 return ret;
6658                         break;
6659                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6660                         decap = actions->conf;
6661                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6662                                 ;
6663                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6664                                 encap = NULL;
6665                                 actions--;
6666                         } else {
6667                                 encap = actions->conf;
6668                         }
6669                         ret = flow_dv_validate_action_raw_encap_decap
6670                                            (dev,
6671                                             decap ? decap : &empty_decap, encap,
6672                                             attr, &action_flags, &actions_n,
6673                                             actions, item_flags, error);
6674                         if (ret < 0)
6675                                 return ret;
6676                         break;
6677                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6678                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6679                         ret = flow_dv_validate_action_modify_mac(action_flags,
6680                                                                  actions,
6681                                                                  item_flags,
6682                                                                  error);
6683                         if (ret < 0)
6684                                 return ret;
6685                         /* Count all modify-header actions as one action. */
6686                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6687                                 ++actions_n;
6688                         action_flags |= actions->type ==
6689                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6690                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6691                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6692                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6693                                 modify_after_mirror = 1;
6694                         /*
6695                          * Even if the source and destination MAC addresses have
6696                          * overlap in the header with 4B alignment, the convert
6697                          * function will handle them separately and 4 SW actions
6698                          * will be created. And 2 actions will be added each
6699                          * time no matter how many bytes of address will be set.
6700                          */
6701                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6702                         break;
6703                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6704                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6705                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6706                                                                   actions,
6707                                                                   item_flags,
6708                                                                   error);
6709                         if (ret < 0)
6710                                 return ret;
6711                         /* Count all modify-header actions as one action. */
6712                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6713                                 ++actions_n;
6714                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6715                                 modify_after_mirror = 1;
6716                         action_flags |= actions->type ==
6717                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6718                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6719                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6720                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6721                         break;
6722                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6723                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6724                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6725                                                                   actions,
6726                                                                   item_flags,
6727                                                                   error);
6728                         if (ret < 0)
6729                                 return ret;
6730                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6731                                 return rte_flow_error_set(error, ENOTSUP,
6732                                         RTE_FLOW_ERROR_TYPE_ACTION,
6733                                         actions,
6734                                         "Can't change header "
6735                                         "with ICMPv6 proto");
6736                         /* Count all modify-header actions as one action. */
6737                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6738                                 ++actions_n;
6739                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6740                                 modify_after_mirror = 1;
6741                         action_flags |= actions->type ==
6742                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6743                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6744                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6745                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6746                         break;
6747                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6748                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6749                         ret = flow_dv_validate_action_modify_tp(action_flags,
6750                                                                 actions,
6751                                                                 item_flags,
6752                                                                 error);
6753                         if (ret < 0)
6754                                 return ret;
6755                         /* Count all modify-header actions as one action. */
6756                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6757                                 ++actions_n;
6758                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6759                                 modify_after_mirror = 1;
6760                         action_flags |= actions->type ==
6761                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6762                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6763                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6764                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6765                         break;
6766                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6767                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6768                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6769                                                                  actions,
6770                                                                  item_flags,
6771                                                                  error);
6772                         if (ret < 0)
6773                                 return ret;
6774                         /* Count all modify-header actions as one action. */
6775                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6776                                 ++actions_n;
6777                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6778                                 modify_after_mirror = 1;
6779                         action_flags |= actions->type ==
6780                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6781                                                 MLX5_FLOW_ACTION_SET_TTL :
6782                                                 MLX5_FLOW_ACTION_DEC_TTL;
6783                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6784                         break;
6785                 case RTE_FLOW_ACTION_TYPE_JUMP:
6786                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6787                                                            action_flags,
6788                                                            attr, external,
6789                                                            error);
6790                         if (ret)
6791                                 return ret;
6792                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6793                             fdb_mirror_limit)
6794                                 return rte_flow_error_set(error, EINVAL,
6795                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6796                                                   NULL,
6797                                                   "sample and jump action combination is not supported");
6798                         ++actions_n;
6799                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6800                         break;
6801                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6802                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6803                         ret = flow_dv_validate_action_modify_tcp_seq
6804                                                                 (action_flags,
6805                                                                  actions,
6806                                                                  item_flags,
6807                                                                  error);
6808                         if (ret < 0)
6809                                 return ret;
6810                         /* Count all modify-header actions as one action. */
6811                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6812                                 ++actions_n;
6813                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6814                                 modify_after_mirror = 1;
6815                         action_flags |= actions->type ==
6816                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6817                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6818                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6819                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6820                         break;
6821                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6822                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6823                         ret = flow_dv_validate_action_modify_tcp_ack
6824                                                                 (action_flags,
6825                                                                  actions,
6826                                                                  item_flags,
6827                                                                  error);
6828                         if (ret < 0)
6829                                 return ret;
6830                         /* Count all modify-header actions as one action. */
6831                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6832                                 ++actions_n;
6833                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6834                                 modify_after_mirror = 1;
6835                         action_flags |= actions->type ==
6836                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6837                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6838                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6839                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6840                         break;
6841                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6842                         break;
6843                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6844                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6845                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6846                         break;
6847                 case RTE_FLOW_ACTION_TYPE_METER:
6848                         ret = mlx5_flow_validate_action_meter(dev,
6849                                                               action_flags,
6850                                                               actions, attr,
6851                                                               error);
6852                         if (ret < 0)
6853                                 return ret;
6854                         action_flags |= MLX5_FLOW_ACTION_METER;
6855                         ++actions_n;
6856                         /* Meter action will add one more TAG action. */
6857                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6858                         break;
6859                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6860                         if (!attr->transfer && !attr->group)
6861                                 return rte_flow_error_set(error, ENOTSUP,
6862                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6863                                                                            NULL,
6864                           "Shared ASO age action is not supported for group 0");
6865                         action_flags |= MLX5_FLOW_ACTION_AGE;
6866                         ++actions_n;
6867                         break;
6868                 case RTE_FLOW_ACTION_TYPE_AGE:
6869                         ret = flow_dv_validate_action_age(action_flags,
6870                                                           actions, dev,
6871                                                           error);
6872                         if (ret < 0)
6873                                 return ret;
6874                         /*
6875                          * Validate the regular AGE action (using counter)
6876                          * mutual exclusion with share counter actions.
6877                          */
6878                         if (!priv->sh->flow_hit_aso_en) {
6879                                 if (count && count->shared)
6880                                         return rte_flow_error_set
6881                                                 (error, EINVAL,
6882                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6883                                                 NULL,
6884                                                 "old age and shared count combination is not supported");
6885                                 if (sample_count)
6886                                         return rte_flow_error_set
6887                                                 (error, EINVAL,
6888                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6889                                                 NULL,
6890                                                 "old age action and count must be in the same sub flow");
6891                         }
6892                         action_flags |= MLX5_FLOW_ACTION_AGE;
6893                         ++actions_n;
6894                         break;
6895                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6896                         ret = flow_dv_validate_action_modify_ipv4_dscp
6897                                                          (action_flags,
6898                                                           actions,
6899                                                           item_flags,
6900                                                           error);
6901                         if (ret < 0)
6902                                 return ret;
6903                         /* Count all modify-header actions as one action. */
6904                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6905                                 ++actions_n;
6906                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6907                                 modify_after_mirror = 1;
6908                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6909                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6910                         break;
6911                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6912                         ret = flow_dv_validate_action_modify_ipv6_dscp
6913                                                                 (action_flags,
6914                                                                  actions,
6915                                                                  item_flags,
6916                                                                  error);
6917                         if (ret < 0)
6918                                 return ret;
6919                         /* Count all modify-header actions as one action. */
6920                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6921                                 ++actions_n;
6922                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6923                                 modify_after_mirror = 1;
6924                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6925                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6926                         break;
6927                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6928                         ret = flow_dv_validate_action_sample(&action_flags,
6929                                                              actions, dev,
6930                                                              attr, item_flags,
6931                                                              rss, &sample_rss,
6932                                                              &sample_count,
6933                                                              &fdb_mirror_limit,
6934                                                              error);
6935                         if (ret < 0)
6936                                 return ret;
6937                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6938                         ++actions_n;
6939                         break;
6940                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6941                         if (actions[0].type != (typeof(actions[0].type))
6942                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6943                                 return rte_flow_error_set
6944                                                 (error, EINVAL,
6945                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6946                                                 NULL, "MLX5 private action "
6947                                                 "must be the first");
6948
6949                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6950                         break;
6951                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6952                         ret = flow_dv_validate_action_modify_field(dev,
6953                                                                    action_flags,
6954                                                                    actions,
6955                                                                    attr,
6956                                                                    error);
6957                         if (ret < 0)
6958                                 return ret;
6959                         /* Count all modify-header actions as one action. */
6960                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6961                                 ++actions_n;
6962                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6963                         rw_act_num += ret;
6964                         break;
6965                 default:
6966                         return rte_flow_error_set(error, ENOTSUP,
6967                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6968                                                   actions,
6969                                                   "action not supported");
6970                 }
6971         }
6972         /*
6973          * Validate actions in flow rules
6974          * - Explicit decap action is prohibited by the tunnel offload API.
6975          * - Drop action in tunnel steer rule is prohibited by the API.
6976          * - Application cannot use MARK action because it's value can mask
6977          *   tunnel default miss nitification.
6978          * - JUMP in tunnel match rule has no support in current PMD
6979          *   implementation.
6980          * - TAG & META are reserved for future uses.
6981          */
6982         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6983                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6984                                             MLX5_FLOW_ACTION_MARK     |
6985                                             MLX5_FLOW_ACTION_SET_TAG  |
6986                                             MLX5_FLOW_ACTION_SET_META |
6987                                             MLX5_FLOW_ACTION_DROP;
6988
6989                 if (action_flags & bad_actions_mask)
6990                         return rte_flow_error_set
6991                                         (error, EINVAL,
6992                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6993                                         "Invalid RTE action in tunnel "
6994                                         "set decap rule");
6995                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6996                         return rte_flow_error_set
6997                                         (error, EINVAL,
6998                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6999                                         "tunnel set decap rule must terminate "
7000                                         "with JUMP");
7001                 if (!attr->ingress)
7002                         return rte_flow_error_set
7003                                         (error, EINVAL,
7004                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7005                                         "tunnel flows for ingress traffic only");
7006         }
7007         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7008                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
7009                                             MLX5_FLOW_ACTION_MARK    |
7010                                             MLX5_FLOW_ACTION_SET_TAG |
7011                                             MLX5_FLOW_ACTION_SET_META;
7012
7013                 if (action_flags & bad_actions_mask)
7014                         return rte_flow_error_set
7015                                         (error, EINVAL,
7016                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7017                                         "Invalid RTE action in tunnel "
7018                                         "set match rule");
7019         }
7020         /*
7021          * Validate the drop action mutual exclusion with other actions.
7022          * Drop action is mutually-exclusive with any other action, except for
7023          * Count action.
7024          * Drop action compatibility with tunnel offload was already validated.
7025          */
7026         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7027                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7028         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7029             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7030                 return rte_flow_error_set(error, EINVAL,
7031                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7032                                           "Drop action is mutually-exclusive "
7033                                           "with any other action, except for "
7034                                           "Count action");
7035         /* Eswitch has few restrictions on using items and actions */
7036         if (attr->transfer) {
7037                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7038                     action_flags & MLX5_FLOW_ACTION_FLAG)
7039                         return rte_flow_error_set(error, ENOTSUP,
7040                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7041                                                   NULL,
7042                                                   "unsupported action FLAG");
7043                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7044                     action_flags & MLX5_FLOW_ACTION_MARK)
7045                         return rte_flow_error_set(error, ENOTSUP,
7046                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7047                                                   NULL,
7048                                                   "unsupported action MARK");
7049                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7050                         return rte_flow_error_set(error, ENOTSUP,
7051                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7052                                                   NULL,
7053                                                   "unsupported action QUEUE");
7054                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7055                         return rte_flow_error_set(error, ENOTSUP,
7056                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7057                                                   NULL,
7058                                                   "unsupported action RSS");
7059                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7060                         return rte_flow_error_set(error, EINVAL,
7061                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7062                                                   actions,
7063                                                   "no fate action is found");
7064         } else {
7065                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7066                         return rte_flow_error_set(error, EINVAL,
7067                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7068                                                   actions,
7069                                                   "no fate action is found");
7070         }
7071         /*
7072          * Continue validation for Xcap and VLAN actions.
7073          * If hairpin is working in explicit TX rule mode, there is no actions
7074          * splitting and the validation of hairpin ingress flow should be the
7075          * same as other standard flows.
7076          */
7077         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7078                              MLX5_FLOW_VLAN_ACTIONS)) &&
7079             (queue_index == 0xFFFF ||
7080              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7081              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7082              conf->tx_explicit != 0))) {
7083                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7084                     MLX5_FLOW_XCAP_ACTIONS)
7085                         return rte_flow_error_set(error, ENOTSUP,
7086                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7087                                                   NULL, "encap and decap "
7088                                                   "combination aren't supported");
7089                 if (!attr->transfer && attr->ingress) {
7090                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7091                                 return rte_flow_error_set
7092                                                 (error, ENOTSUP,
7093                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7094                                                  NULL, "encap is not supported"
7095                                                  " for ingress traffic");
7096                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7097                                 return rte_flow_error_set
7098                                                 (error, ENOTSUP,
7099                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7100                                                  NULL, "push VLAN action not "
7101                                                  "supported for ingress");
7102                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7103                                         MLX5_FLOW_VLAN_ACTIONS)
7104                                 return rte_flow_error_set
7105                                                 (error, ENOTSUP,
7106                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7107                                                  NULL, "no support for "
7108                                                  "multiple VLAN actions");
7109                 }
7110         }
7111         /*
7112          * Hairpin flow will add one more TAG action in TX implicit mode.
7113          * In TX explicit mode, there will be no hairpin flow ID.
7114          */
7115         if (hairpin > 0)
7116                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7117         /* extra metadata enabled: one more TAG action will be add. */
7118         if (dev_conf->dv_flow_en &&
7119             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7120             mlx5_flow_ext_mreg_supported(dev))
7121                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7122         if (rw_act_num >
7123                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7124                 return rte_flow_error_set(error, ENOTSUP,
7125                                           RTE_FLOW_ERROR_TYPE_ACTION,
7126                                           NULL, "too many header modify"
7127                                           " actions to support");
7128         }
7129         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7130         if (fdb_mirror_limit && modify_after_mirror)
7131                 return rte_flow_error_set(error, EINVAL,
7132                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7133                                 "sample before modify action is not supported");
7134         return 0;
7135 }
7136
7137 /**
7138  * Internal preparation function. Allocates the DV flow size,
7139  * this size is constant.
7140  *
7141  * @param[in] dev
7142  *   Pointer to the rte_eth_dev structure.
7143  * @param[in] attr
7144  *   Pointer to the flow attributes.
7145  * @param[in] items
7146  *   Pointer to the list of items.
7147  * @param[in] actions
7148  *   Pointer to the list of actions.
7149  * @param[out] error
7150  *   Pointer to the error structure.
7151  *
7152  * @return
7153  *   Pointer to mlx5_flow object on success,
7154  *   otherwise NULL and rte_errno is set.
7155  */
7156 static struct mlx5_flow *
7157 flow_dv_prepare(struct rte_eth_dev *dev,
7158                 const struct rte_flow_attr *attr __rte_unused,
7159                 const struct rte_flow_item items[] __rte_unused,
7160                 const struct rte_flow_action actions[] __rte_unused,
7161                 struct rte_flow_error *error)
7162 {
7163         uint32_t handle_idx = 0;
7164         struct mlx5_flow *dev_flow;
7165         struct mlx5_flow_handle *dev_handle;
7166         struct mlx5_priv *priv = dev->data->dev_private;
7167         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7168
7169         MLX5_ASSERT(wks);
7170         /* In case of corrupting the memory. */
7171         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7172                 rte_flow_error_set(error, ENOSPC,
7173                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7174                                    "not free temporary device flow");
7175                 return NULL;
7176         }
7177         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7178                                    &handle_idx);
7179         if (!dev_handle) {
7180                 rte_flow_error_set(error, ENOMEM,
7181                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7182                                    "not enough memory to create flow handle");
7183                 return NULL;
7184         }
7185         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7186         dev_flow = &wks->flows[wks->flow_idx++];
7187         memset(dev_flow, 0, sizeof(*dev_flow));
7188         dev_flow->handle = dev_handle;
7189         dev_flow->handle_idx = handle_idx;
7190         /*
7191          * In some old rdma-core releases, before continuing, a check of the
7192          * length of matching parameter will be done at first. It needs to use
7193          * the length without misc4 param. If the flow has misc4 support, then
7194          * the length needs to be adjusted accordingly. Each param member is
7195          * aligned with a 64B boundary naturally.
7196          */
7197         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7198                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7199         dev_flow->ingress = attr->ingress;
7200         dev_flow->dv.transfer = attr->transfer;
7201         return dev_flow;
7202 }
7203
7204 #ifdef RTE_LIBRTE_MLX5_DEBUG
7205 /**
7206  * Sanity check for match mask and value. Similar to check_valid_spec() in
7207  * kernel driver. If unmasked bit is present in value, it returns failure.
7208  *
7209  * @param match_mask
7210  *   pointer to match mask buffer.
7211  * @param match_value
7212  *   pointer to match value buffer.
7213  *
7214  * @return
7215  *   0 if valid, -EINVAL otherwise.
7216  */
7217 static int
7218 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7219 {
7220         uint8_t *m = match_mask;
7221         uint8_t *v = match_value;
7222         unsigned int i;
7223
7224         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7225                 if (v[i] & ~m[i]) {
7226                         DRV_LOG(ERR,
7227                                 "match_value differs from match_criteria"
7228                                 " %p[%u] != %p[%u]",
7229                                 match_value, i, match_mask, i);
7230                         return -EINVAL;
7231                 }
7232         }
7233         return 0;
7234 }
7235 #endif
7236
7237 /**
7238  * Add match of ip_version.
7239  *
7240  * @param[in] group
7241  *   Flow group.
7242  * @param[in] headers_v
7243  *   Values header pointer.
7244  * @param[in] headers_m
7245  *   Masks header pointer.
7246  * @param[in] ip_version
7247  *   The IP version to set.
7248  */
7249 static inline void
7250 flow_dv_set_match_ip_version(uint32_t group,
7251                              void *headers_v,
7252                              void *headers_m,
7253                              uint8_t ip_version)
7254 {
7255         if (group == 0)
7256                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7257         else
7258                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7259                          ip_version);
7260         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7261         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7262         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7263 }
7264
7265 /**
7266  * Add Ethernet item to matcher and to the value.
7267  *
7268  * @param[in, out] matcher
7269  *   Flow matcher.
7270  * @param[in, out] key
7271  *   Flow matcher value.
7272  * @param[in] item
7273  *   Flow pattern to translate.
7274  * @param[in] inner
7275  *   Item is inner pattern.
7276  */
7277 static void
7278 flow_dv_translate_item_eth(void *matcher, void *key,
7279                            const struct rte_flow_item *item, int inner,
7280                            uint32_t group)
7281 {
7282         const struct rte_flow_item_eth *eth_m = item->mask;
7283         const struct rte_flow_item_eth *eth_v = item->spec;
7284         const struct rte_flow_item_eth nic_mask = {
7285                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7286                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7287                 .type = RTE_BE16(0xffff),
7288                 .has_vlan = 0,
7289         };
7290         void *hdrs_m;
7291         void *hdrs_v;
7292         char *l24_v;
7293         unsigned int i;
7294
7295         if (!eth_v)
7296                 return;
7297         if (!eth_m)
7298                 eth_m = &nic_mask;
7299         if (inner) {
7300                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7301                                          inner_headers);
7302                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7303         } else {
7304                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7305                                          outer_headers);
7306                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7307         }
7308         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7309                &eth_m->dst, sizeof(eth_m->dst));
7310         /* The value must be in the range of the mask. */
7311         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7312         for (i = 0; i < sizeof(eth_m->dst); ++i)
7313                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7314         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7315                &eth_m->src, sizeof(eth_m->src));
7316         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7317         /* The value must be in the range of the mask. */
7318         for (i = 0; i < sizeof(eth_m->dst); ++i)
7319                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7320         /*
7321          * HW supports match on one Ethertype, the Ethertype following the last
7322          * VLAN tag of the packet (see PRM).
7323          * Set match on ethertype only if ETH header is not followed by VLAN.
7324          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7325          * ethertype, and use ip_version field instead.
7326          * eCPRI over Ether layer will use type value 0xAEFE.
7327          */
7328         if (eth_m->type == 0xFFFF) {
7329                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7330                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7331                 switch (eth_v->type) {
7332                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7333                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7334                         return;
7335                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7336                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7337                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7338                         return;
7339                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7340                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7341                         return;
7342                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7343                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7344                         return;
7345                 default:
7346                         break;
7347                 }
7348         }
7349         if (eth_m->has_vlan) {
7350                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7351                 if (eth_v->has_vlan) {
7352                         /*
7353                          * Here, when also has_more_vlan field in VLAN item is
7354                          * not set, only single-tagged packets will be matched.
7355                          */
7356                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7357                         return;
7358                 }
7359         }
7360         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7361                  rte_be_to_cpu_16(eth_m->type));
7362         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7363         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7364 }
7365
7366 /**
7367  * Add VLAN item to matcher and to the value.
7368  *
7369  * @param[in, out] dev_flow
7370  *   Flow descriptor.
7371  * @param[in, out] matcher
7372  *   Flow matcher.
7373  * @param[in, out] key
7374  *   Flow matcher value.
7375  * @param[in] item
7376  *   Flow pattern to translate.
7377  * @param[in] inner
7378  *   Item is inner pattern.
7379  */
7380 static void
7381 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7382                             void *matcher, void *key,
7383                             const struct rte_flow_item *item,
7384                             int inner, uint32_t group)
7385 {
7386         const struct rte_flow_item_vlan *vlan_m = item->mask;
7387         const struct rte_flow_item_vlan *vlan_v = item->spec;
7388         void *hdrs_m;
7389         void *hdrs_v;
7390         uint16_t tci_m;
7391         uint16_t tci_v;
7392
7393         if (inner) {
7394                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7395                                          inner_headers);
7396                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7397         } else {
7398                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7399                                          outer_headers);
7400                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7401                 /*
7402                  * This is workaround, masks are not supported,
7403                  * and pre-validated.
7404                  */
7405                 if (vlan_v)
7406                         dev_flow->handle->vf_vlan.tag =
7407                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7408         }
7409         /*
7410          * When VLAN item exists in flow, mark packet as tagged,
7411          * even if TCI is not specified.
7412          */
7413         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7414                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7415                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7416         }
7417         if (!vlan_v)
7418                 return;
7419         if (!vlan_m)
7420                 vlan_m = &rte_flow_item_vlan_mask;
7421         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7422         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7423         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7424         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7425         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7426         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7427         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7428         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7429         /*
7430          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7431          * ethertype, and use ip_version field instead.
7432          */
7433         if (vlan_m->inner_type == 0xFFFF) {
7434                 switch (vlan_v->inner_type) {
7435                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7436                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7437                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7438                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7439                         return;
7440                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7441                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7442                         return;
7443                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7444                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7445                         return;
7446                 default:
7447                         break;
7448                 }
7449         }
7450         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7451                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7452                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7453                 /* Only one vlan_tag bit can be set. */
7454                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7455                 return;
7456         }
7457         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7458                  rte_be_to_cpu_16(vlan_m->inner_type));
7459         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7460                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7461 }
7462
7463 /**
7464  * Add IPV4 item to matcher and to the value.
7465  *
7466  * @param[in, out] matcher
7467  *   Flow matcher.
7468  * @param[in, out] key
7469  *   Flow matcher value.
7470  * @param[in] item
7471  *   Flow pattern to translate.
7472  * @param[in] inner
7473  *   Item is inner pattern.
7474  * @param[in] group
7475  *   The group to insert the rule.
7476  */
7477 static void
7478 flow_dv_translate_item_ipv4(void *matcher, void *key,
7479                             const struct rte_flow_item *item,
7480                             int inner, uint32_t group)
7481 {
7482         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7483         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7484         const struct rte_flow_item_ipv4 nic_mask = {
7485                 .hdr = {
7486                         .src_addr = RTE_BE32(0xffffffff),
7487                         .dst_addr = RTE_BE32(0xffffffff),
7488                         .type_of_service = 0xff,
7489                         .next_proto_id = 0xff,
7490                         .time_to_live = 0xff,
7491                 },
7492         };
7493         void *headers_m;
7494         void *headers_v;
7495         char *l24_m;
7496         char *l24_v;
7497         uint8_t tos;
7498
7499         if (inner) {
7500                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7501                                          inner_headers);
7502                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7503         } else {
7504                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7505                                          outer_headers);
7506                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7507         }
7508         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7509         if (!ipv4_v)
7510                 return;
7511         if (!ipv4_m)
7512                 ipv4_m = &nic_mask;
7513         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7514                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7515         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7516                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7517         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7518         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7519         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7520                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7521         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7522                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7523         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7524         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7525         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7526         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7527                  ipv4_m->hdr.type_of_service);
7528         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7529         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7530                  ipv4_m->hdr.type_of_service >> 2);
7531         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7532         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7533                  ipv4_m->hdr.next_proto_id);
7534         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7535                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7536         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7537                  ipv4_m->hdr.time_to_live);
7538         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7539                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7540         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7541                  !!(ipv4_m->hdr.fragment_offset));
7542         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7543                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7544 }
7545
7546 /**
7547  * Add IPV6 item to matcher and to the value.
7548  *
7549  * @param[in, out] matcher
7550  *   Flow matcher.
7551  * @param[in, out] key
7552  *   Flow matcher value.
7553  * @param[in] item
7554  *   Flow pattern to translate.
7555  * @param[in] inner
7556  *   Item is inner pattern.
7557  * @param[in] group
7558  *   The group to insert the rule.
7559  */
7560 static void
7561 flow_dv_translate_item_ipv6(void *matcher, void *key,
7562                             const struct rte_flow_item *item,
7563                             int inner, uint32_t group)
7564 {
7565         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7566         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7567         const struct rte_flow_item_ipv6 nic_mask = {
7568                 .hdr = {
7569                         .src_addr =
7570                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7571                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7572                         .dst_addr =
7573                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7574                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7575                         .vtc_flow = RTE_BE32(0xffffffff),
7576                         .proto = 0xff,
7577                         .hop_limits = 0xff,
7578                 },
7579         };
7580         void *headers_m;
7581         void *headers_v;
7582         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7583         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7584         char *l24_m;
7585         char *l24_v;
7586         uint32_t vtc_m;
7587         uint32_t vtc_v;
7588         int i;
7589         int size;
7590
7591         if (inner) {
7592                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7593                                          inner_headers);
7594                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7595         } else {
7596                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7597                                          outer_headers);
7598                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7599         }
7600         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7601         if (!ipv6_v)
7602                 return;
7603         if (!ipv6_m)
7604                 ipv6_m = &nic_mask;
7605         size = sizeof(ipv6_m->hdr.dst_addr);
7606         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7607                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7608         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7609                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7610         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7611         for (i = 0; i < size; ++i)
7612                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7613         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7614                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7615         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7616                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7617         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7618         for (i = 0; i < size; ++i)
7619                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7620         /* TOS. */
7621         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7622         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7623         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7624         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7625         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7626         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7627         /* Label. */
7628         if (inner) {
7629                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7630                          vtc_m);
7631                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7632                          vtc_v);
7633         } else {
7634                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7635                          vtc_m);
7636                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7637                          vtc_v);
7638         }
7639         /* Protocol. */
7640         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7641                  ipv6_m->hdr.proto);
7642         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7643                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7644         /* Hop limit. */
7645         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7646                  ipv6_m->hdr.hop_limits);
7647         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7648                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7649         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7650                  !!(ipv6_m->has_frag_ext));
7651         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7652                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7653 }
7654
7655 /**
7656  * Add IPV6 fragment extension item to matcher and to the value.
7657  *
7658  * @param[in, out] matcher
7659  *   Flow matcher.
7660  * @param[in, out] key
7661  *   Flow matcher value.
7662  * @param[in] item
7663  *   Flow pattern to translate.
7664  * @param[in] inner
7665  *   Item is inner pattern.
7666  */
7667 static void
7668 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7669                                      const struct rte_flow_item *item,
7670                                      int inner)
7671 {
7672         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7673         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7674         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7675                 .hdr = {
7676                         .next_header = 0xff,
7677                         .frag_data = RTE_BE16(0xffff),
7678                 },
7679         };
7680         void *headers_m;
7681         void *headers_v;
7682
7683         if (inner) {
7684                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7685                                          inner_headers);
7686                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7687         } else {
7688                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7689                                          outer_headers);
7690                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7691         }
7692         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7693         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7694         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7695         if (!ipv6_frag_ext_v)
7696                 return;
7697         if (!ipv6_frag_ext_m)
7698                 ipv6_frag_ext_m = &nic_mask;
7699         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7700                  ipv6_frag_ext_m->hdr.next_header);
7701         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7702                  ipv6_frag_ext_v->hdr.next_header &
7703                  ipv6_frag_ext_m->hdr.next_header);
7704 }
7705
7706 /**
7707  * Add TCP item to matcher and to the value.
7708  *
7709  * @param[in, out] matcher
7710  *   Flow matcher.
7711  * @param[in, out] key
7712  *   Flow matcher value.
7713  * @param[in] item
7714  *   Flow pattern to translate.
7715  * @param[in] inner
7716  *   Item is inner pattern.
7717  */
7718 static void
7719 flow_dv_translate_item_tcp(void *matcher, void *key,
7720                            const struct rte_flow_item *item,
7721                            int inner)
7722 {
7723         const struct rte_flow_item_tcp *tcp_m = item->mask;
7724         const struct rte_flow_item_tcp *tcp_v = item->spec;
7725         void *headers_m;
7726         void *headers_v;
7727
7728         if (inner) {
7729                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7730                                          inner_headers);
7731                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7732         } else {
7733                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7734                                          outer_headers);
7735                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7736         }
7737         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7738         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7739         if (!tcp_v)
7740                 return;
7741         if (!tcp_m)
7742                 tcp_m = &rte_flow_item_tcp_mask;
7743         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7744                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7745         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7746                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7747         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7748                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7749         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7750                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7751         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7752                  tcp_m->hdr.tcp_flags);
7753         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7754                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7755 }
7756
7757 /**
7758  * Add UDP item to matcher and to the value.
7759  *
7760  * @param[in, out] matcher
7761  *   Flow matcher.
7762  * @param[in, out] key
7763  *   Flow matcher value.
7764  * @param[in] item
7765  *   Flow pattern to translate.
7766  * @param[in] inner
7767  *   Item is inner pattern.
7768  */
7769 static void
7770 flow_dv_translate_item_udp(void *matcher, void *key,
7771                            const struct rte_flow_item *item,
7772                            int inner)
7773 {
7774         const struct rte_flow_item_udp *udp_m = item->mask;
7775         const struct rte_flow_item_udp *udp_v = item->spec;
7776         void *headers_m;
7777         void *headers_v;
7778
7779         if (inner) {
7780                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7781                                          inner_headers);
7782                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7783         } else {
7784                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7785                                          outer_headers);
7786                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7787         }
7788         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7789         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7790         if (!udp_v)
7791                 return;
7792         if (!udp_m)
7793                 udp_m = &rte_flow_item_udp_mask;
7794         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7795                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7796         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7797                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7798         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7799                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7800         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7801                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7802 }
7803
7804 /**
7805  * Add GRE optional Key item to matcher and to the value.
7806  *
7807  * @param[in, out] matcher
7808  *   Flow matcher.
7809  * @param[in, out] key
7810  *   Flow matcher value.
7811  * @param[in] item
7812  *   Flow pattern to translate.
7813  * @param[in] inner
7814  *   Item is inner pattern.
7815  */
7816 static void
7817 flow_dv_translate_item_gre_key(void *matcher, void *key,
7818                                    const struct rte_flow_item *item)
7819 {
7820         const rte_be32_t *key_m = item->mask;
7821         const rte_be32_t *key_v = item->spec;
7822         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7823         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7824         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7825
7826         /* GRE K bit must be on and should already be validated */
7827         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7828         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7829         if (!key_v)
7830                 return;
7831         if (!key_m)
7832                 key_m = &gre_key_default_mask;
7833         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7834                  rte_be_to_cpu_32(*key_m) >> 8);
7835         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7836                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7837         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7838                  rte_be_to_cpu_32(*key_m) & 0xFF);
7839         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7840                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7841 }
7842
7843 /**
7844  * Add GRE item to matcher and to the value.
7845  *
7846  * @param[in, out] matcher
7847  *   Flow matcher.
7848  * @param[in, out] key
7849  *   Flow matcher value.
7850  * @param[in] item
7851  *   Flow pattern to translate.
7852  * @param[in] inner
7853  *   Item is inner pattern.
7854  */
7855 static void
7856 flow_dv_translate_item_gre(void *matcher, void *key,
7857                            const struct rte_flow_item *item,
7858                            int inner)
7859 {
7860         const struct rte_flow_item_gre *gre_m = item->mask;
7861         const struct rte_flow_item_gre *gre_v = item->spec;
7862         void *headers_m;
7863         void *headers_v;
7864         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7865         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7866         struct {
7867                 union {
7868                         __extension__
7869                         struct {
7870                                 uint16_t version:3;
7871                                 uint16_t rsvd0:9;
7872                                 uint16_t s_present:1;
7873                                 uint16_t k_present:1;
7874                                 uint16_t rsvd_bit1:1;
7875                                 uint16_t c_present:1;
7876                         };
7877                         uint16_t value;
7878                 };
7879         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7880
7881         if (inner) {
7882                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7883                                          inner_headers);
7884                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7885         } else {
7886                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7887                                          outer_headers);
7888                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7889         }
7890         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7891         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7892         if (!gre_v)
7893                 return;
7894         if (!gre_m)
7895                 gre_m = &rte_flow_item_gre_mask;
7896         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7897                  rte_be_to_cpu_16(gre_m->protocol));
7898         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7899                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7900         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7901         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7902         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7903                  gre_crks_rsvd0_ver_m.c_present);
7904         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7905                  gre_crks_rsvd0_ver_v.c_present &
7906                  gre_crks_rsvd0_ver_m.c_present);
7907         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7908                  gre_crks_rsvd0_ver_m.k_present);
7909         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7910                  gre_crks_rsvd0_ver_v.k_present &
7911                  gre_crks_rsvd0_ver_m.k_present);
7912         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7913                  gre_crks_rsvd0_ver_m.s_present);
7914         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7915                  gre_crks_rsvd0_ver_v.s_present &
7916                  gre_crks_rsvd0_ver_m.s_present);
7917 }
7918
7919 /**
7920  * Add NVGRE item to matcher and to the value.
7921  *
7922  * @param[in, out] matcher
7923  *   Flow matcher.
7924  * @param[in, out] key
7925  *   Flow matcher value.
7926  * @param[in] item
7927  *   Flow pattern to translate.
7928  * @param[in] inner
7929  *   Item is inner pattern.
7930  */
7931 static void
7932 flow_dv_translate_item_nvgre(void *matcher, void *key,
7933                              const struct rte_flow_item *item,
7934                              int inner)
7935 {
7936         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7937         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7938         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7939         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7940         const char *tni_flow_id_m;
7941         const char *tni_flow_id_v;
7942         char *gre_key_m;
7943         char *gre_key_v;
7944         int size;
7945         int i;
7946
7947         /* For NVGRE, GRE header fields must be set with defined values. */
7948         const struct rte_flow_item_gre gre_spec = {
7949                 .c_rsvd0_ver = RTE_BE16(0x2000),
7950                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7951         };
7952         const struct rte_flow_item_gre gre_mask = {
7953                 .c_rsvd0_ver = RTE_BE16(0xB000),
7954                 .protocol = RTE_BE16(UINT16_MAX),
7955         };
7956         const struct rte_flow_item gre_item = {
7957                 .spec = &gre_spec,
7958                 .mask = &gre_mask,
7959                 .last = NULL,
7960         };
7961         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7962         if (!nvgre_v)
7963                 return;
7964         if (!nvgre_m)
7965                 nvgre_m = &rte_flow_item_nvgre_mask;
7966         tni_flow_id_m = (const char *)nvgre_m->tni;
7967         tni_flow_id_v = (const char *)nvgre_v->tni;
7968         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7969         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7970         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7971         memcpy(gre_key_m, tni_flow_id_m, size);
7972         for (i = 0; i < size; ++i)
7973                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7974 }
7975
7976 /**
7977  * Add VXLAN item to matcher and to the value.
7978  *
7979  * @param[in, out] matcher
7980  *   Flow matcher.
7981  * @param[in, out] key
7982  *   Flow matcher value.
7983  * @param[in] item
7984  *   Flow pattern to translate.
7985  * @param[in] inner
7986  *   Item is inner pattern.
7987  */
7988 static void
7989 flow_dv_translate_item_vxlan(void *matcher, void *key,
7990                              const struct rte_flow_item *item,
7991                              int inner)
7992 {
7993         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7994         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7995         void *headers_m;
7996         void *headers_v;
7997         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7998         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7999         char *vni_m;
8000         char *vni_v;
8001         uint16_t dport;
8002         int size;
8003         int i;
8004
8005         if (inner) {
8006                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8007                                          inner_headers);
8008                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8009         } else {
8010                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8011                                          outer_headers);
8012                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8013         }
8014         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8015                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8016         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8017                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8018                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8019         }
8020         if (!vxlan_v)
8021                 return;
8022         if (!vxlan_m)
8023                 vxlan_m = &rte_flow_item_vxlan_mask;
8024         size = sizeof(vxlan_m->vni);
8025         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8026         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8027         memcpy(vni_m, vxlan_m->vni, size);
8028         for (i = 0; i < size; ++i)
8029                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8030 }
8031
8032 /**
8033  * Add VXLAN-GPE item to matcher and to the value.
8034  *
8035  * @param[in, out] matcher
8036  *   Flow matcher.
8037  * @param[in, out] key
8038  *   Flow matcher value.
8039  * @param[in] item
8040  *   Flow pattern to translate.
8041  * @param[in] inner
8042  *   Item is inner pattern.
8043  */
8044
8045 static void
8046 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8047                                  const struct rte_flow_item *item, int inner)
8048 {
8049         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8050         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8051         void *headers_m;
8052         void *headers_v;
8053         void *misc_m =
8054                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8055         void *misc_v =
8056                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8057         char *vni_m;
8058         char *vni_v;
8059         uint16_t dport;
8060         int size;
8061         int i;
8062         uint8_t flags_m = 0xff;
8063         uint8_t flags_v = 0xc;
8064
8065         if (inner) {
8066                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8067                                          inner_headers);
8068                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8069         } else {
8070                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8071                                          outer_headers);
8072                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8073         }
8074         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8075                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8076         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8077                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8078                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8079         }
8080         if (!vxlan_v)
8081                 return;
8082         if (!vxlan_m)
8083                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8084         size = sizeof(vxlan_m->vni);
8085         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8086         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8087         memcpy(vni_m, vxlan_m->vni, size);
8088         for (i = 0; i < size; ++i)
8089                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8090         if (vxlan_m->flags) {
8091                 flags_m = vxlan_m->flags;
8092                 flags_v = vxlan_v->flags;
8093         }
8094         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8095         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8096         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8097                  vxlan_m->protocol);
8098         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8099                  vxlan_v->protocol);
8100 }
8101
8102 /**
8103  * Add Geneve item to matcher and to the value.
8104  *
8105  * @param[in, out] matcher
8106  *   Flow matcher.
8107  * @param[in, out] key
8108  *   Flow matcher value.
8109  * @param[in] item
8110  *   Flow pattern to translate.
8111  * @param[in] inner
8112  *   Item is inner pattern.
8113  */
8114
8115 static void
8116 flow_dv_translate_item_geneve(void *matcher, void *key,
8117                               const struct rte_flow_item *item, int inner)
8118 {
8119         const struct rte_flow_item_geneve *geneve_m = item->mask;
8120         const struct rte_flow_item_geneve *geneve_v = item->spec;
8121         void *headers_m;
8122         void *headers_v;
8123         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8124         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8125         uint16_t dport;
8126         uint16_t gbhdr_m;
8127         uint16_t gbhdr_v;
8128         char *vni_m;
8129         char *vni_v;
8130         size_t size, i;
8131
8132         if (inner) {
8133                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8134                                          inner_headers);
8135                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8136         } else {
8137                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8138                                          outer_headers);
8139                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8140         }
8141         dport = MLX5_UDP_PORT_GENEVE;
8142         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8143                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8144                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8145         }
8146         if (!geneve_v)
8147                 return;
8148         if (!geneve_m)
8149                 geneve_m = &rte_flow_item_geneve_mask;
8150         size = sizeof(geneve_m->vni);
8151         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8152         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8153         memcpy(vni_m, geneve_m->vni, size);
8154         for (i = 0; i < size; ++i)
8155                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8156         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8157                  rte_be_to_cpu_16(geneve_m->protocol));
8158         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8159                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8160         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8161         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8162         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8163                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8164         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8165                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8166         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8167                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8168         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8169                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8170                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8171 }
8172
8173 /**
8174  * Create Geneve TLV option resource.
8175  *
8176  * @param dev[in, out]
8177  *   Pointer to rte_eth_dev structure.
8178  * @param[in, out] tag_be24
8179  *   Tag value in big endian then R-shift 8.
8180  * @parm[in, out] dev_flow
8181  *   Pointer to the dev_flow.
8182  * @param[out] error
8183  *   pointer to error structure.
8184  *
8185  * @return
8186  *   0 on success otherwise -errno and errno is set.
8187  */
8188
8189 int
8190 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8191                                              const struct rte_flow_item *item,
8192                                              struct rte_flow_error *error)
8193 {
8194         struct mlx5_priv *priv = dev->data->dev_private;
8195         struct mlx5_dev_ctx_shared *sh = priv->sh;
8196         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8197                         sh->geneve_tlv_option_resource;
8198         struct mlx5_devx_obj *obj;
8199         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8200         int ret = 0;
8201
8202         if (!geneve_opt_v)
8203                 return -1;
8204         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8205         if (geneve_opt_resource != NULL) {
8206                 if (geneve_opt_resource->option_class ==
8207                         geneve_opt_v->option_class &&
8208                         geneve_opt_resource->option_type ==
8209                         geneve_opt_v->option_type &&
8210                         geneve_opt_resource->length ==
8211                         geneve_opt_v->option_len) {
8212                         /* We already have GENVE TLV option obj allocated. */
8213                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8214                                            __ATOMIC_RELAXED);
8215                 } else {
8216                         ret = rte_flow_error_set(error, ENOMEM,
8217                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8218                                 "Only one GENEVE TLV option supported");
8219                         goto exit;
8220                 }
8221         } else {
8222                 /* Create a GENEVE TLV object and resource. */
8223                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8224                                 geneve_opt_v->option_class,
8225                                 geneve_opt_v->option_type,
8226                                 geneve_opt_v->option_len);
8227                 if (!obj) {
8228                         ret = rte_flow_error_set(error, ENODATA,
8229                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8230                                 "Failed to create GENEVE TLV Devx object");
8231                         goto exit;
8232                 }
8233                 sh->geneve_tlv_option_resource =
8234                                 mlx5_malloc(MLX5_MEM_ZERO,
8235                                                 sizeof(*geneve_opt_resource),
8236                                                 0, SOCKET_ID_ANY);
8237                 if (!sh->geneve_tlv_option_resource) {
8238                         claim_zero(mlx5_devx_cmd_destroy(obj));
8239                         ret = rte_flow_error_set(error, ENOMEM,
8240                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8241                                 "GENEVE TLV object memory allocation failed");
8242                         goto exit;
8243                 }
8244                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8245                 geneve_opt_resource->obj = obj;
8246                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8247                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8248                 geneve_opt_resource->length = geneve_opt_v->option_len;
8249                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8250                                 __ATOMIC_RELAXED);
8251         }
8252 exit:
8253         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8254         return ret;
8255 }
8256
8257 /**
8258  * Add Geneve TLV option item to matcher.
8259  *
8260  * @param[in, out] dev
8261  *   Pointer to rte_eth_dev structure.
8262  * @param[in, out] matcher
8263  *   Flow matcher.
8264  * @param[in, out] key
8265  *   Flow matcher value.
8266  * @param[in] item
8267  *   Flow pattern to translate.
8268  * @param[out] error
8269  *   Pointer to error structure.
8270  */
8271 static int
8272 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8273                                   void *key, const struct rte_flow_item *item,
8274                                   struct rte_flow_error *error)
8275 {
8276         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8277         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8278         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8279         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8280         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8281                         misc_parameters_3);
8282         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8283         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8284         int ret = 0;
8285
8286         if (!geneve_opt_v)
8287                 return -1;
8288         if (!geneve_opt_m)
8289                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8290         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8291                                                            error);
8292         if (ret) {
8293                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8294                 return ret;
8295         }
8296         /*
8297          * Set the option length in GENEVE header if not requested.
8298          * The GENEVE TLV option length is expressed by the option length field
8299          * in the GENEVE header.
8300          * If the option length was not requested but the GENEVE TLV option item
8301          * is present we set the option length field implicitly.
8302          */
8303         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8304                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8305                          MLX5_GENEVE_OPTLEN_MASK);
8306                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8307                          geneve_opt_v->option_len + 1);
8308         }
8309         /* Set the data. */
8310         if (geneve_opt_v->data) {
8311                 memcpy(&opt_data_key, geneve_opt_v->data,
8312                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8313                                 sizeof(opt_data_key)));
8314                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8315                                 sizeof(opt_data_key));
8316                 memcpy(&opt_data_mask, geneve_opt_m->data,
8317                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8318                                 sizeof(opt_data_mask)));
8319                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8320                                 sizeof(opt_data_mask));
8321                 MLX5_SET(fte_match_set_misc3, misc3_m,
8322                                 geneve_tlv_option_0_data,
8323                                 rte_be_to_cpu_32(opt_data_mask));
8324                 MLX5_SET(fte_match_set_misc3, misc3_v,
8325                                 geneve_tlv_option_0_data,
8326                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8327         }
8328         return ret;
8329 }
8330
8331 /**
8332  * Add MPLS item to matcher and to the value.
8333  *
8334  * @param[in, out] matcher
8335  *   Flow matcher.
8336  * @param[in, out] key
8337  *   Flow matcher value.
8338  * @param[in] item
8339  *   Flow pattern to translate.
8340  * @param[in] prev_layer
8341  *   The protocol layer indicated in previous item.
8342  * @param[in] inner
8343  *   Item is inner pattern.
8344  */
8345 static void
8346 flow_dv_translate_item_mpls(void *matcher, void *key,
8347                             const struct rte_flow_item *item,
8348                             uint64_t prev_layer,
8349                             int inner)
8350 {
8351         const uint32_t *in_mpls_m = item->mask;
8352         const uint32_t *in_mpls_v = item->spec;
8353         uint32_t *out_mpls_m = 0;
8354         uint32_t *out_mpls_v = 0;
8355         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8356         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8357         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8358                                      misc_parameters_2);
8359         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8360         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8361         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8362
8363         switch (prev_layer) {
8364         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8365                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8366                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8367                          MLX5_UDP_PORT_MPLS);
8368                 break;
8369         case MLX5_FLOW_LAYER_GRE:
8370                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8371                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8372                          RTE_ETHER_TYPE_MPLS);
8373                 break;
8374         default:
8375                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8376                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8377                          IPPROTO_MPLS);
8378                 break;
8379         }
8380         if (!in_mpls_v)
8381                 return;
8382         if (!in_mpls_m)
8383                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8384         switch (prev_layer) {
8385         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8386                 out_mpls_m =
8387                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8388                                                  outer_first_mpls_over_udp);
8389                 out_mpls_v =
8390                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8391                                                  outer_first_mpls_over_udp);
8392                 break;
8393         case MLX5_FLOW_LAYER_GRE:
8394                 out_mpls_m =
8395                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8396                                                  outer_first_mpls_over_gre);
8397                 out_mpls_v =
8398                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8399                                                  outer_first_mpls_over_gre);
8400                 break;
8401         default:
8402                 /* Inner MPLS not over GRE is not supported. */
8403                 if (!inner) {
8404                         out_mpls_m =
8405                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8406                                                          misc2_m,
8407                                                          outer_first_mpls);
8408                         out_mpls_v =
8409                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8410                                                          misc2_v,
8411                                                          outer_first_mpls);
8412                 }
8413                 break;
8414         }
8415         if (out_mpls_m && out_mpls_v) {
8416                 *out_mpls_m = *in_mpls_m;
8417                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8418         }
8419 }
8420
8421 /**
8422  * Add metadata register item to matcher
8423  *
8424  * @param[in, out] matcher
8425  *   Flow matcher.
8426  * @param[in, out] key
8427  *   Flow matcher value.
8428  * @param[in] reg_type
8429  *   Type of device metadata register
8430  * @param[in] value
8431  *   Register value
8432  * @param[in] mask
8433  *   Register mask
8434  */
8435 static void
8436 flow_dv_match_meta_reg(void *matcher, void *key,
8437                        enum modify_reg reg_type,
8438                        uint32_t data, uint32_t mask)
8439 {
8440         void *misc2_m =
8441                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8442         void *misc2_v =
8443                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8444         uint32_t temp;
8445
8446         data &= mask;
8447         switch (reg_type) {
8448         case REG_A:
8449                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8450                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8451                 break;
8452         case REG_B:
8453                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8454                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8455                 break;
8456         case REG_C_0:
8457                 /*
8458                  * The metadata register C0 field might be divided into
8459                  * source vport index and META item value, we should set
8460                  * this field according to specified mask, not as whole one.
8461                  */
8462                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8463                 temp |= mask;
8464                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8465                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8466                 temp &= ~mask;
8467                 temp |= data;
8468                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8469                 break;
8470         case REG_C_1:
8471                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8472                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8473                 break;
8474         case REG_C_2:
8475                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8476                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8477                 break;
8478         case REG_C_3:
8479                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8480                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8481                 break;
8482         case REG_C_4:
8483                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8484                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8485                 break;
8486         case REG_C_5:
8487                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8488                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8489                 break;
8490         case REG_C_6:
8491                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8492                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8493                 break;
8494         case REG_C_7:
8495                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8496                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8497                 break;
8498         default:
8499                 MLX5_ASSERT(false);
8500                 break;
8501         }
8502 }
8503
8504 /**
8505  * Add MARK item to matcher
8506  *
8507  * @param[in] dev
8508  *   The device to configure through.
8509  * @param[in, out] matcher
8510  *   Flow matcher.
8511  * @param[in, out] key
8512  *   Flow matcher value.
8513  * @param[in] item
8514  *   Flow pattern to translate.
8515  */
8516 static void
8517 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8518                             void *matcher, void *key,
8519                             const struct rte_flow_item *item)
8520 {
8521         struct mlx5_priv *priv = dev->data->dev_private;
8522         const struct rte_flow_item_mark *mark;
8523         uint32_t value;
8524         uint32_t mask;
8525
8526         mark = item->mask ? (const void *)item->mask :
8527                             &rte_flow_item_mark_mask;
8528         mask = mark->id & priv->sh->dv_mark_mask;
8529         mark = (const void *)item->spec;
8530         MLX5_ASSERT(mark);
8531         value = mark->id & priv->sh->dv_mark_mask & mask;
8532         if (mask) {
8533                 enum modify_reg reg;
8534
8535                 /* Get the metadata register index for the mark. */
8536                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8537                 MLX5_ASSERT(reg > 0);
8538                 if (reg == REG_C_0) {
8539                         struct mlx5_priv *priv = dev->data->dev_private;
8540                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8541                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8542
8543                         mask &= msk_c0;
8544                         mask <<= shl_c0;
8545                         value <<= shl_c0;
8546                 }
8547                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8548         }
8549 }
8550
8551 /**
8552  * Add META item to matcher
8553  *
8554  * @param[in] dev
8555  *   The devich to configure through.
8556  * @param[in, out] matcher
8557  *   Flow matcher.
8558  * @param[in, out] key
8559  *   Flow matcher value.
8560  * @param[in] attr
8561  *   Attributes of flow that includes this item.
8562  * @param[in] item
8563  *   Flow pattern to translate.
8564  */
8565 static void
8566 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8567                             void *matcher, void *key,
8568                             const struct rte_flow_attr *attr,
8569                             const struct rte_flow_item *item)
8570 {
8571         const struct rte_flow_item_meta *meta_m;
8572         const struct rte_flow_item_meta *meta_v;
8573
8574         meta_m = (const void *)item->mask;
8575         if (!meta_m)
8576                 meta_m = &rte_flow_item_meta_mask;
8577         meta_v = (const void *)item->spec;
8578         if (meta_v) {
8579                 int reg;
8580                 uint32_t value = meta_v->data;
8581                 uint32_t mask = meta_m->data;
8582
8583                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8584                 if (reg < 0)
8585                         return;
8586                 MLX5_ASSERT(reg != REG_NON);
8587                 /*
8588                  * In datapath code there is no endianness
8589                  * coversions for perfromance reasons, all
8590                  * pattern conversions are done in rte_flow.
8591                  */
8592                 value = rte_cpu_to_be_32(value);
8593                 mask = rte_cpu_to_be_32(mask);
8594                 if (reg == REG_C_0) {
8595                         struct mlx5_priv *priv = dev->data->dev_private;
8596                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8597                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8598 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8599                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8600
8601                         value >>= shr_c0;
8602                         mask >>= shr_c0;
8603 #endif
8604                         value <<= shl_c0;
8605                         mask <<= shl_c0;
8606                         MLX5_ASSERT(msk_c0);
8607                         MLX5_ASSERT(!(~msk_c0 & mask));
8608                 }
8609                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8610         }
8611 }
8612
8613 /**
8614  * Add vport metadata Reg C0 item to matcher
8615  *
8616  * @param[in, out] matcher
8617  *   Flow matcher.
8618  * @param[in, out] key
8619  *   Flow matcher value.
8620  * @param[in] reg
8621  *   Flow pattern to translate.
8622  */
8623 static void
8624 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8625                                   uint32_t value, uint32_t mask)
8626 {
8627         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8628 }
8629
8630 /**
8631  * Add tag item to matcher
8632  *
8633  * @param[in] dev
8634  *   The devich to configure through.
8635  * @param[in, out] matcher
8636  *   Flow matcher.
8637  * @param[in, out] key
8638  *   Flow matcher value.
8639  * @param[in] item
8640  *   Flow pattern to translate.
8641  */
8642 static void
8643 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8644                                 void *matcher, void *key,
8645                                 const struct rte_flow_item *item)
8646 {
8647         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8648         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8649         uint32_t mask, value;
8650
8651         MLX5_ASSERT(tag_v);
8652         value = tag_v->data;
8653         mask = tag_m ? tag_m->data : UINT32_MAX;
8654         if (tag_v->id == REG_C_0) {
8655                 struct mlx5_priv *priv = dev->data->dev_private;
8656                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8657                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8658
8659                 mask &= msk_c0;
8660                 mask <<= shl_c0;
8661                 value <<= shl_c0;
8662         }
8663         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8664 }
8665
8666 /**
8667  * Add TAG item to matcher
8668  *
8669  * @param[in] dev
8670  *   The devich to configure through.
8671  * @param[in, out] matcher
8672  *   Flow matcher.
8673  * @param[in, out] key
8674  *   Flow matcher value.
8675  * @param[in] item
8676  *   Flow pattern to translate.
8677  */
8678 static void
8679 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8680                            void *matcher, void *key,
8681                            const struct rte_flow_item *item)
8682 {
8683         const struct rte_flow_item_tag *tag_v = item->spec;
8684         const struct rte_flow_item_tag *tag_m = item->mask;
8685         enum modify_reg reg;
8686
8687         MLX5_ASSERT(tag_v);
8688         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8689         /* Get the metadata register index for the tag. */
8690         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8691         MLX5_ASSERT(reg > 0);
8692         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8693 }
8694
8695 /**
8696  * Add source vport match to the specified matcher.
8697  *
8698  * @param[in, out] matcher
8699  *   Flow matcher.
8700  * @param[in, out] key
8701  *   Flow matcher value.
8702  * @param[in] port
8703  *   Source vport value to match
8704  * @param[in] mask
8705  *   Mask
8706  */
8707 static void
8708 flow_dv_translate_item_source_vport(void *matcher, void *key,
8709                                     int16_t port, uint16_t mask)
8710 {
8711         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8712         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8713
8714         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8715         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8716 }
8717
8718 /**
8719  * Translate port-id item to eswitch match on  port-id.
8720  *
8721  * @param[in] dev
8722  *   The devich to configure through.
8723  * @param[in, out] matcher
8724  *   Flow matcher.
8725  * @param[in, out] key
8726  *   Flow matcher value.
8727  * @param[in] item
8728  *   Flow pattern to translate.
8729  * @param[in]
8730  *   Flow attributes.
8731  *
8732  * @return
8733  *   0 on success, a negative errno value otherwise.
8734  */
8735 static int
8736 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8737                                void *key, const struct rte_flow_item *item,
8738                                const struct rte_flow_attr *attr)
8739 {
8740         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8741         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8742         struct mlx5_priv *priv;
8743         uint16_t mask, id;
8744
8745         mask = pid_m ? pid_m->id : 0xffff;
8746         id = pid_v ? pid_v->id : dev->data->port_id;
8747         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8748         if (!priv)
8749                 return -rte_errno;
8750         /*
8751          * Translate to vport field or to metadata, depending on mode.
8752          * Kernel can use either misc.source_port or half of C0 metadata
8753          * register.
8754          */
8755         if (priv->vport_meta_mask) {
8756                 /*
8757                  * Provide the hint for SW steering library
8758                  * to insert the flow into ingress domain and
8759                  * save the extra vport match.
8760                  */
8761                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8762                     priv->pf_bond < 0 && attr->transfer)
8763                         flow_dv_translate_item_source_vport
8764                                 (matcher, key, priv->vport_id, mask);
8765                 /*
8766                  * We should always set the vport metadata register,
8767                  * otherwise the SW steering library can drop
8768                  * the rule if wire vport metadata value is not zero,
8769                  * it depends on kernel configuration.
8770                  */
8771                 flow_dv_translate_item_meta_vport(matcher, key,
8772                                                   priv->vport_meta_tag,
8773                                                   priv->vport_meta_mask);
8774         } else {
8775                 flow_dv_translate_item_source_vport(matcher, key,
8776                                                     priv->vport_id, mask);
8777         }
8778         return 0;
8779 }
8780
8781 /**
8782  * Add ICMP6 item to matcher and to the value.
8783  *
8784  * @param[in, out] matcher
8785  *   Flow matcher.
8786  * @param[in, out] key
8787  *   Flow matcher value.
8788  * @param[in] item
8789  *   Flow pattern to translate.
8790  * @param[in] inner
8791  *   Item is inner pattern.
8792  */
8793 static void
8794 flow_dv_translate_item_icmp6(void *matcher, void *key,
8795                               const struct rte_flow_item *item,
8796                               int inner)
8797 {
8798         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8799         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8800         void *headers_m;
8801         void *headers_v;
8802         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8803                                      misc_parameters_3);
8804         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8805         if (inner) {
8806                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8807                                          inner_headers);
8808                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8809         } else {
8810                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8811                                          outer_headers);
8812                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8813         }
8814         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8815         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8816         if (!icmp6_v)
8817                 return;
8818         if (!icmp6_m)
8819                 icmp6_m = &rte_flow_item_icmp6_mask;
8820         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8821         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8822                  icmp6_v->type & icmp6_m->type);
8823         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8824         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8825                  icmp6_v->code & icmp6_m->code);
8826 }
8827
8828 /**
8829  * Add ICMP item to matcher and to the value.
8830  *
8831  * @param[in, out] matcher
8832  *   Flow matcher.
8833  * @param[in, out] key
8834  *   Flow matcher value.
8835  * @param[in] item
8836  *   Flow pattern to translate.
8837  * @param[in] inner
8838  *   Item is inner pattern.
8839  */
8840 static void
8841 flow_dv_translate_item_icmp(void *matcher, void *key,
8842                             const struct rte_flow_item *item,
8843                             int inner)
8844 {
8845         const struct rte_flow_item_icmp *icmp_m = item->mask;
8846         const struct rte_flow_item_icmp *icmp_v = item->spec;
8847         uint32_t icmp_header_data_m = 0;
8848         uint32_t icmp_header_data_v = 0;
8849         void *headers_m;
8850         void *headers_v;
8851         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8852                                      misc_parameters_3);
8853         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8854         if (inner) {
8855                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8856                                          inner_headers);
8857                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8858         } else {
8859                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8860                                          outer_headers);
8861                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8862         }
8863         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8864         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8865         if (!icmp_v)
8866                 return;
8867         if (!icmp_m)
8868                 icmp_m = &rte_flow_item_icmp_mask;
8869         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8870                  icmp_m->hdr.icmp_type);
8871         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8872                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8873         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8874                  icmp_m->hdr.icmp_code);
8875         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8876                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8877         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8878         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8879         if (icmp_header_data_m) {
8880                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8881                 icmp_header_data_v |=
8882                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8883                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8884                          icmp_header_data_m);
8885                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8886                          icmp_header_data_v & icmp_header_data_m);
8887         }
8888 }
8889
8890 /**
8891  * Add GTP item to matcher and to the value.
8892  *
8893  * @param[in, out] matcher
8894  *   Flow matcher.
8895  * @param[in, out] key
8896  *   Flow matcher value.
8897  * @param[in] item
8898  *   Flow pattern to translate.
8899  * @param[in] inner
8900  *   Item is inner pattern.
8901  */
8902 static void
8903 flow_dv_translate_item_gtp(void *matcher, void *key,
8904                            const struct rte_flow_item *item, int inner)
8905 {
8906         const struct rte_flow_item_gtp *gtp_m = item->mask;
8907         const struct rte_flow_item_gtp *gtp_v = item->spec;
8908         void *headers_m;
8909         void *headers_v;
8910         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8911                                      misc_parameters_3);
8912         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8913         uint16_t dport = RTE_GTPU_UDP_PORT;
8914
8915         if (inner) {
8916                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8917                                          inner_headers);
8918                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8919         } else {
8920                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8921                                          outer_headers);
8922                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8923         }
8924         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8925                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8926                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8927         }
8928         if (!gtp_v)
8929                 return;
8930         if (!gtp_m)
8931                 gtp_m = &rte_flow_item_gtp_mask;
8932         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8933                  gtp_m->v_pt_rsv_flags);
8934         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8935                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8936         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8937         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8938                  gtp_v->msg_type & gtp_m->msg_type);
8939         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8940                  rte_be_to_cpu_32(gtp_m->teid));
8941         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8942                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8943 }
8944
8945 /**
8946  * Add GTP PSC item to matcher.
8947  *
8948  * @param[in, out] matcher
8949  *   Flow matcher.
8950  * @param[in, out] key
8951  *   Flow matcher value.
8952  * @param[in] item
8953  *   Flow pattern to translate.
8954  */
8955 static int
8956 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8957                                const struct rte_flow_item *item)
8958 {
8959         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8960         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8961         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8962                         misc_parameters_3);
8963         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8964         union {
8965                 uint32_t w32;
8966                 struct {
8967                         uint16_t seq_num;
8968                         uint8_t npdu_num;
8969                         uint8_t next_ext_header_type;
8970                 };
8971         } dw_2;
8972         uint8_t gtp_flags;
8973
8974         /* Always set E-flag match on one, regardless of GTP item settings. */
8975         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8976         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8977         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8978         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8979         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8980         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8981         /*Set next extension header type. */
8982         dw_2.seq_num = 0;
8983         dw_2.npdu_num = 0;
8984         dw_2.next_ext_header_type = 0xff;
8985         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8986                  rte_cpu_to_be_32(dw_2.w32));
8987         dw_2.seq_num = 0;
8988         dw_2.npdu_num = 0;
8989         dw_2.next_ext_header_type = 0x85;
8990         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8991                  rte_cpu_to_be_32(dw_2.w32));
8992         if (gtp_psc_v) {
8993                 union {
8994                         uint32_t w32;
8995                         struct {
8996                                 uint8_t len;
8997                                 uint8_t type_flags;
8998                                 uint8_t qfi;
8999                                 uint8_t reserved;
9000                         };
9001                 } dw_0;
9002
9003                 /*Set extension header PDU type and Qos. */
9004                 if (!gtp_psc_m)
9005                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9006                 dw_0.w32 = 0;
9007                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
9008                 dw_0.qfi = gtp_psc_m->qfi;
9009                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9010                          rte_cpu_to_be_32(dw_0.w32));
9011                 dw_0.w32 = 0;
9012                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
9013                                                         gtp_psc_m->pdu_type);
9014                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
9015                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9016                          rte_cpu_to_be_32(dw_0.w32));
9017         }
9018         return 0;
9019 }
9020
9021 /**
9022  * Add eCPRI item to matcher and to the value.
9023  *
9024  * @param[in] dev
9025  *   The devich to configure through.
9026  * @param[in, out] matcher
9027  *   Flow matcher.
9028  * @param[in, out] key
9029  *   Flow matcher value.
9030  * @param[in] item
9031  *   Flow pattern to translate.
9032  * @param[in] samples
9033  *   Sample IDs to be used in the matching.
9034  */
9035 static void
9036 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9037                              void *key, const struct rte_flow_item *item)
9038 {
9039         struct mlx5_priv *priv = dev->data->dev_private;
9040         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9041         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9042         struct rte_ecpri_common_hdr common;
9043         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9044                                      misc_parameters_4);
9045         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9046         uint32_t *samples;
9047         void *dw_m;
9048         void *dw_v;
9049
9050         if (!ecpri_v)
9051                 return;
9052         if (!ecpri_m)
9053                 ecpri_m = &rte_flow_item_ecpri_mask;
9054         /*
9055          * Maximal four DW samples are supported in a single matching now.
9056          * Two are used now for a eCPRI matching:
9057          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9058          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9059          *    if any.
9060          */
9061         if (!ecpri_m->hdr.common.u32)
9062                 return;
9063         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9064         /* Need to take the whole DW as the mask to fill the entry. */
9065         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9066                             prog_sample_field_value_0);
9067         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9068                             prog_sample_field_value_0);
9069         /* Already big endian (network order) in the header. */
9070         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9071         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9072         /* Sample#0, used for matching type, offset 0. */
9073         MLX5_SET(fte_match_set_misc4, misc4_m,
9074                  prog_sample_field_id_0, samples[0]);
9075         /* It makes no sense to set the sample ID in the mask field. */
9076         MLX5_SET(fte_match_set_misc4, misc4_v,
9077                  prog_sample_field_id_0, samples[0]);
9078         /*
9079          * Checking if message body part needs to be matched.
9080          * Some wildcard rules only matching type field should be supported.
9081          */
9082         if (ecpri_m->hdr.dummy[0]) {
9083                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9084                 switch (common.type) {
9085                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9086                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9087                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9088                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9089                                             prog_sample_field_value_1);
9090                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9091                                             prog_sample_field_value_1);
9092                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9093                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9094                                             ecpri_m->hdr.dummy[0];
9095                         /* Sample#1, to match message body, offset 4. */
9096                         MLX5_SET(fte_match_set_misc4, misc4_m,
9097                                  prog_sample_field_id_1, samples[1]);
9098                         MLX5_SET(fte_match_set_misc4, misc4_v,
9099                                  prog_sample_field_id_1, samples[1]);
9100                         break;
9101                 default:
9102                         /* Others, do not match any sample ID. */
9103                         break;
9104                 }
9105         }
9106 }
9107
9108 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9109
9110 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9111         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9112                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9113
9114 /**
9115  * Calculate flow matcher enable bitmap.
9116  *
9117  * @param match_criteria
9118  *   Pointer to flow matcher criteria.
9119  *
9120  * @return
9121  *   Bitmap of enabled fields.
9122  */
9123 static uint8_t
9124 flow_dv_matcher_enable(uint32_t *match_criteria)
9125 {
9126         uint8_t match_criteria_enable;
9127
9128         match_criteria_enable =
9129                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9130                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9131         match_criteria_enable |=
9132                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9133                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9134         match_criteria_enable |=
9135                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9136                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9137         match_criteria_enable |=
9138                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9139                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9140         match_criteria_enable |=
9141                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9142                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9143         match_criteria_enable |=
9144                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9145                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9146         return match_criteria_enable;
9147 }
9148
9149 struct mlx5_hlist_entry *
9150 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9151 {
9152         struct mlx5_dev_ctx_shared *sh = list->ctx;
9153         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9154         struct rte_eth_dev *dev = ctx->dev;
9155         struct mlx5_flow_tbl_data_entry *tbl_data;
9156         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9157         struct rte_flow_error *error = ctx->error;
9158         union mlx5_flow_tbl_key key = { .v64 = key64 };
9159         struct mlx5_flow_tbl_resource *tbl;
9160         void *domain;
9161         uint32_t idx = 0;
9162         int ret;
9163
9164         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9165         if (!tbl_data) {
9166                 rte_flow_error_set(error, ENOMEM,
9167                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9168                                    NULL,
9169                                    "cannot allocate flow table data entry");
9170                 return NULL;
9171         }
9172         tbl_data->idx = idx;
9173         tbl_data->tunnel = tt_prm->tunnel;
9174         tbl_data->group_id = tt_prm->group_id;
9175         tbl_data->external = !!tt_prm->external;
9176         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9177         tbl_data->is_egress = !!key.direction;
9178         tbl_data->is_transfer = !!key.domain;
9179         tbl_data->dummy = !!key.dummy;
9180         tbl_data->table_id = key.table_id;
9181         tbl = &tbl_data->tbl;
9182         if (key.dummy)
9183                 return &tbl_data->entry;
9184         if (key.domain)
9185                 domain = sh->fdb_domain;
9186         else if (key.direction)
9187                 domain = sh->tx_domain;
9188         else
9189                 domain = sh->rx_domain;
9190         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9191         if (ret) {
9192                 rte_flow_error_set(error, ENOMEM,
9193                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9194                                    NULL, "cannot create flow table object");
9195                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9196                 return NULL;
9197         }
9198         if (key.table_id) {
9199                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9200                                         (tbl->obj, &tbl_data->jump.action);
9201                 if (ret) {
9202                         rte_flow_error_set(error, ENOMEM,
9203                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9204                                            NULL,
9205                                            "cannot create flow jump action");
9206                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9207                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9208                         return NULL;
9209                 }
9210         }
9211         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9212               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9213               key.table_id);
9214         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9215                              flow_dv_matcher_create_cb,
9216                              flow_dv_matcher_match_cb,
9217                              flow_dv_matcher_remove_cb);
9218         return &tbl_data->entry;
9219 }
9220
9221 int
9222 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9223                      struct mlx5_hlist_entry *entry, uint64_t key64,
9224                      void *cb_ctx __rte_unused)
9225 {
9226         struct mlx5_flow_tbl_data_entry *tbl_data =
9227                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9228         union mlx5_flow_tbl_key key = { .v64 = key64 };
9229
9230         return tbl_data->table_id != key.table_id ||
9231                tbl_data->dummy != key.dummy ||
9232                tbl_data->is_transfer != key.domain ||
9233                tbl_data->is_egress != key.direction;
9234 }
9235
9236 /**
9237  * Get a flow table.
9238  *
9239  * @param[in, out] dev
9240  *   Pointer to rte_eth_dev structure.
9241  * @param[in] table_id
9242  *   Table id to use.
9243  * @param[in] egress
9244  *   Direction of the table.
9245  * @param[in] transfer
9246  *   E-Switch or NIC flow.
9247  * @param[in] dummy
9248  *   Dummy entry for dv API.
9249  * @param[out] error
9250  *   pointer to error structure.
9251  *
9252  * @return
9253  *   Returns tables resource based on the index, NULL in case of failed.
9254  */
9255 struct mlx5_flow_tbl_resource *
9256 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9257                          uint32_t table_id, uint8_t egress,
9258                          uint8_t transfer,
9259                          bool external,
9260                          const struct mlx5_flow_tunnel *tunnel,
9261                          uint32_t group_id, uint8_t dummy,
9262                          struct rte_flow_error *error)
9263 {
9264         struct mlx5_priv *priv = dev->data->dev_private;
9265         union mlx5_flow_tbl_key table_key = {
9266                 {
9267                         .table_id = table_id,
9268                         .dummy = dummy,
9269                         .domain = !!transfer,
9270                         .direction = !!egress,
9271                 }
9272         };
9273         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9274                 .tunnel = tunnel,
9275                 .group_id = group_id,
9276                 .external = external,
9277         };
9278         struct mlx5_flow_cb_ctx ctx = {
9279                 .dev = dev,
9280                 .error = error,
9281                 .data = &tt_prm,
9282         };
9283         struct mlx5_hlist_entry *entry;
9284         struct mlx5_flow_tbl_data_entry *tbl_data;
9285
9286         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9287         if (!entry) {
9288                 rte_flow_error_set(error, ENOMEM,
9289                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9290                                    "cannot get table");
9291                 return NULL;
9292         }
9293         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9294                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9295         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9296         return &tbl_data->tbl;
9297 }
9298
9299 void
9300 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9301                       struct mlx5_hlist_entry *entry)
9302 {
9303         struct mlx5_dev_ctx_shared *sh = list->ctx;
9304         struct mlx5_flow_tbl_data_entry *tbl_data =
9305                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9306
9307         MLX5_ASSERT(entry && sh);
9308         if (tbl_data->jump.action)
9309                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9310         if (tbl_data->tbl.obj)
9311                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9312         if (tbl_data->tunnel_offload && tbl_data->external) {
9313                 struct mlx5_hlist_entry *he;
9314                 struct mlx5_hlist *tunnel_grp_hash;
9315                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9316                 union tunnel_tbl_key tunnel_key = {
9317                         .tunnel_id = tbl_data->tunnel ?
9318                                         tbl_data->tunnel->tunnel_id : 0,
9319                         .group = tbl_data->group_id
9320                 };
9321                 uint32_t table_id = tbl_data->table_id;
9322
9323                 tunnel_grp_hash = tbl_data->tunnel ?
9324                                         tbl_data->tunnel->groups :
9325                                         thub->groups;
9326                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9327                 if (he)
9328                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9329                 DRV_LOG(DEBUG,
9330                         "Table_id %u tunnel %u group %u released.",
9331                         table_id,
9332                         tbl_data->tunnel ?
9333                         tbl_data->tunnel->tunnel_id : 0,
9334                         tbl_data->group_id);
9335         }
9336         mlx5_cache_list_destroy(&tbl_data->matchers);
9337         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9338 }
9339
9340 /**
9341  * Release a flow table.
9342  *
9343  * @param[in] sh
9344  *   Pointer to device shared structure.
9345  * @param[in] tbl
9346  *   Table resource to be released.
9347  *
9348  * @return
9349  *   Returns 0 if table was released, else return 1;
9350  */
9351 static int
9352 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9353                              struct mlx5_flow_tbl_resource *tbl)
9354 {
9355         struct mlx5_flow_tbl_data_entry *tbl_data =
9356                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9357
9358         if (!tbl)
9359                 return 0;
9360         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9361 }
9362
9363 int
9364 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9365                          struct mlx5_cache_entry *entry, void *cb_ctx)
9366 {
9367         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9368         struct mlx5_flow_dv_matcher *ref = ctx->data;
9369         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9370                                                         entry);
9371
9372         return cur->crc != ref->crc ||
9373                cur->priority != ref->priority ||
9374                memcmp((const void *)cur->mask.buf,
9375                       (const void *)ref->mask.buf, ref->mask.size);
9376 }
9377
9378 struct mlx5_cache_entry *
9379 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9380                           struct mlx5_cache_entry *entry __rte_unused,
9381                           void *cb_ctx)
9382 {
9383         struct mlx5_dev_ctx_shared *sh = list->ctx;
9384         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9385         struct mlx5_flow_dv_matcher *ref = ctx->data;
9386         struct mlx5_flow_dv_matcher *cache;
9387         struct mlx5dv_flow_matcher_attr dv_attr = {
9388                 .type = IBV_FLOW_ATTR_NORMAL,
9389                 .match_mask = (void *)&ref->mask,
9390         };
9391         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9392                                                             typeof(*tbl), tbl);
9393         int ret;
9394
9395         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9396         if (!cache) {
9397                 rte_flow_error_set(ctx->error, ENOMEM,
9398                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9399                                    "cannot create matcher");
9400                 return NULL;
9401         }
9402         *cache = *ref;
9403         dv_attr.match_criteria_enable =
9404                 flow_dv_matcher_enable(cache->mask.buf);
9405         dv_attr.priority = ref->priority;
9406         if (tbl->is_egress)
9407                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9408         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9409                                                &cache->matcher_object);
9410         if (ret) {
9411                 mlx5_free(cache);
9412                 rte_flow_error_set(ctx->error, ENOMEM,
9413                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9414                                    "cannot create matcher");
9415                 return NULL;
9416         }
9417         return &cache->entry;
9418 }
9419
9420 /**
9421  * Register the flow matcher.
9422  *
9423  * @param[in, out] dev
9424  *   Pointer to rte_eth_dev structure.
9425  * @param[in, out] matcher
9426  *   Pointer to flow matcher.
9427  * @param[in, out] key
9428  *   Pointer to flow table key.
9429  * @parm[in, out] dev_flow
9430  *   Pointer to the dev_flow.
9431  * @param[out] error
9432  *   pointer to error structure.
9433  *
9434  * @return
9435  *   0 on success otherwise -errno and errno is set.
9436  */
9437 static int
9438 flow_dv_matcher_register(struct rte_eth_dev *dev,
9439                          struct mlx5_flow_dv_matcher *ref,
9440                          union mlx5_flow_tbl_key *key,
9441                          struct mlx5_flow *dev_flow,
9442                          const struct mlx5_flow_tunnel *tunnel,
9443                          uint32_t group_id,
9444                          struct rte_flow_error *error)
9445 {
9446         struct mlx5_cache_entry *entry;
9447         struct mlx5_flow_dv_matcher *cache;
9448         struct mlx5_flow_tbl_resource *tbl;
9449         struct mlx5_flow_tbl_data_entry *tbl_data;
9450         struct mlx5_flow_cb_ctx ctx = {
9451                 .error = error,
9452                 .data = ref,
9453         };
9454
9455         /**
9456          * tunnel offload API requires this registration for cases when
9457          * tunnel match rule was inserted before tunnel set rule.
9458          */
9459         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9460                                        key->direction, key->domain,
9461                                        dev_flow->external, tunnel,
9462                                        group_id, 0, error);
9463         if (!tbl)
9464                 return -rte_errno;      /* No need to refill the error info */
9465         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9466         ref->tbl = tbl;
9467         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9468         if (!entry) {
9469                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9470                 return rte_flow_error_set(error, ENOMEM,
9471                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9472                                           "cannot allocate ref memory");
9473         }
9474         cache = container_of(entry, typeof(*cache), entry);
9475         dev_flow->handle->dvh.matcher = cache;
9476         return 0;
9477 }
9478
9479 struct mlx5_hlist_entry *
9480 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9481 {
9482         struct mlx5_dev_ctx_shared *sh = list->ctx;
9483         struct rte_flow_error *error = ctx;
9484         struct mlx5_flow_dv_tag_resource *entry;
9485         uint32_t idx = 0;
9486         int ret;
9487
9488         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9489         if (!entry) {
9490                 rte_flow_error_set(error, ENOMEM,
9491                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9492                                    "cannot allocate resource memory");
9493                 return NULL;
9494         }
9495         entry->idx = idx;
9496         entry->tag_id = key;
9497         ret = mlx5_flow_os_create_flow_action_tag(key,
9498                                                   &entry->action);
9499         if (ret) {
9500                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9501                 rte_flow_error_set(error, ENOMEM,
9502                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9503                                    NULL, "cannot create action");
9504                 return NULL;
9505         }
9506         return &entry->entry;
9507 }
9508
9509 int
9510 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9511                      struct mlx5_hlist_entry *entry, uint64_t key,
9512                      void *cb_ctx __rte_unused)
9513 {
9514         struct mlx5_flow_dv_tag_resource *tag =
9515                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9516
9517         return key != tag->tag_id;
9518 }
9519
9520 /**
9521  * Find existing tag resource or create and register a new one.
9522  *
9523  * @param dev[in, out]
9524  *   Pointer to rte_eth_dev structure.
9525  * @param[in, out] tag_be24
9526  *   Tag value in big endian then R-shift 8.
9527  * @parm[in, out] dev_flow
9528  *   Pointer to the dev_flow.
9529  * @param[out] error
9530  *   pointer to error structure.
9531  *
9532  * @return
9533  *   0 on success otherwise -errno and errno is set.
9534  */
9535 static int
9536 flow_dv_tag_resource_register
9537                         (struct rte_eth_dev *dev,
9538                          uint32_t tag_be24,
9539                          struct mlx5_flow *dev_flow,
9540                          struct rte_flow_error *error)
9541 {
9542         struct mlx5_priv *priv = dev->data->dev_private;
9543         struct mlx5_flow_dv_tag_resource *cache_resource;
9544         struct mlx5_hlist_entry *entry;
9545
9546         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9547         if (entry) {
9548                 cache_resource = container_of
9549                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9550                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9551                 dev_flow->dv.tag_resource = cache_resource;
9552                 return 0;
9553         }
9554         return -rte_errno;
9555 }
9556
9557 void
9558 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9559                       struct mlx5_hlist_entry *entry)
9560 {
9561         struct mlx5_dev_ctx_shared *sh = list->ctx;
9562         struct mlx5_flow_dv_tag_resource *tag =
9563                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9564
9565         MLX5_ASSERT(tag && sh && tag->action);
9566         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9567         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9568         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9569 }
9570
9571 /**
9572  * Release the tag.
9573  *
9574  * @param dev
9575  *   Pointer to Ethernet device.
9576  * @param tag_idx
9577  *   Tag index.
9578  *
9579  * @return
9580  *   1 while a reference on it exists, 0 when freed.
9581  */
9582 static int
9583 flow_dv_tag_release(struct rte_eth_dev *dev,
9584                     uint32_t tag_idx)
9585 {
9586         struct mlx5_priv *priv = dev->data->dev_private;
9587         struct mlx5_flow_dv_tag_resource *tag;
9588
9589         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9590         if (!tag)
9591                 return 0;
9592         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9593                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9594         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9595 }
9596
9597 /**
9598  * Translate port ID action to vport.
9599  *
9600  * @param[in] dev
9601  *   Pointer to rte_eth_dev structure.
9602  * @param[in] action
9603  *   Pointer to the port ID action.
9604  * @param[out] dst_port_id
9605  *   The target port ID.
9606  * @param[out] error
9607  *   Pointer to the error structure.
9608  *
9609  * @return
9610  *   0 on success, a negative errno value otherwise and rte_errno is set.
9611  */
9612 static int
9613 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9614                                  const struct rte_flow_action *action,
9615                                  uint32_t *dst_port_id,
9616                                  struct rte_flow_error *error)
9617 {
9618         uint32_t port;
9619         struct mlx5_priv *priv;
9620         const struct rte_flow_action_port_id *conf =
9621                         (const struct rte_flow_action_port_id *)action->conf;
9622
9623         port = conf->original ? dev->data->port_id : conf->id;
9624         priv = mlx5_port_to_eswitch_info(port, false);
9625         if (!priv)
9626                 return rte_flow_error_set(error, -rte_errno,
9627                                           RTE_FLOW_ERROR_TYPE_ACTION,
9628                                           NULL,
9629                                           "No eswitch info was found for port");
9630 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9631         /*
9632          * This parameter is transferred to
9633          * mlx5dv_dr_action_create_dest_ib_port().
9634          */
9635         *dst_port_id = priv->dev_port;
9636 #else
9637         /*
9638          * Legacy mode, no LAG configurations is supported.
9639          * This parameter is transferred to
9640          * mlx5dv_dr_action_create_dest_vport().
9641          */
9642         *dst_port_id = priv->vport_id;
9643 #endif
9644         return 0;
9645 }
9646
9647 /**
9648  * Create a counter with aging configuration.
9649  *
9650  * @param[in] dev
9651  *   Pointer to rte_eth_dev structure.
9652  * @param[out] count
9653  *   Pointer to the counter action configuration.
9654  * @param[in] age
9655  *   Pointer to the aging action configuration.
9656  *
9657  * @return
9658  *   Index to flow counter on success, 0 otherwise.
9659  */
9660 static uint32_t
9661 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9662                                 struct mlx5_flow *dev_flow,
9663                                 const struct rte_flow_action_count *count,
9664                                 const struct rte_flow_action_age *age)
9665 {
9666         uint32_t counter;
9667         struct mlx5_age_param *age_param;
9668
9669         if (count && count->shared)
9670                 counter = flow_dv_counter_get_shared(dev, count->id);
9671         else
9672                 counter = flow_dv_counter_alloc(dev, !!age);
9673         if (!counter || age == NULL)
9674                 return counter;
9675         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9676         age_param->context = age->context ? age->context :
9677                 (void *)(uintptr_t)(dev_flow->flow_idx);
9678         age_param->timeout = age->timeout;
9679         age_param->port_id = dev->data->port_id;
9680         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9681         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9682         return counter;
9683 }
9684
9685 /**
9686  * Add Tx queue matcher
9687  *
9688  * @param[in] dev
9689  *   Pointer to the dev struct.
9690  * @param[in, out] matcher
9691  *   Flow matcher.
9692  * @param[in, out] key
9693  *   Flow matcher value.
9694  * @param[in] item
9695  *   Flow pattern to translate.
9696  * @param[in] inner
9697  *   Item is inner pattern.
9698  */
9699 static void
9700 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9701                                 void *matcher, void *key,
9702                                 const struct rte_flow_item *item)
9703 {
9704         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9705         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9706         void *misc_m =
9707                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9708         void *misc_v =
9709                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9710         struct mlx5_txq_ctrl *txq;
9711         uint32_t queue;
9712
9713
9714         queue_m = (const void *)item->mask;
9715         if (!queue_m)
9716                 return;
9717         queue_v = (const void *)item->spec;
9718         if (!queue_v)
9719                 return;
9720         txq = mlx5_txq_get(dev, queue_v->queue);
9721         if (!txq)
9722                 return;
9723         queue = txq->obj->sq->id;
9724         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9725         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9726                  queue & queue_m->queue);
9727         mlx5_txq_release(dev, queue_v->queue);
9728 }
9729
9730 /**
9731  * Set the hash fields according to the @p flow information.
9732  *
9733  * @param[in] dev_flow
9734  *   Pointer to the mlx5_flow.
9735  * @param[in] rss_desc
9736  *   Pointer to the mlx5_flow_rss_desc.
9737  */
9738 static void
9739 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9740                        struct mlx5_flow_rss_desc *rss_desc)
9741 {
9742         uint64_t items = dev_flow->handle->layers;
9743         int rss_inner = 0;
9744         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9745
9746         dev_flow->hash_fields = 0;
9747 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9748         if (rss_desc->level >= 2) {
9749                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9750                 rss_inner = 1;
9751         }
9752 #endif
9753         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9754             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9755                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9756                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9757                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9758                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9759                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9760                         else
9761                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9762                 }
9763         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9764                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9765                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9766                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9767                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9768                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9769                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9770                         else
9771                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9772                 }
9773         }
9774         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9775             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9776                 if (rss_types & ETH_RSS_UDP) {
9777                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9778                                 dev_flow->hash_fields |=
9779                                                 IBV_RX_HASH_SRC_PORT_UDP;
9780                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9781                                 dev_flow->hash_fields |=
9782                                                 IBV_RX_HASH_DST_PORT_UDP;
9783                         else
9784                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9785                 }
9786         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9787                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9788                 if (rss_types & ETH_RSS_TCP) {
9789                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9790                                 dev_flow->hash_fields |=
9791                                                 IBV_RX_HASH_SRC_PORT_TCP;
9792                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9793                                 dev_flow->hash_fields |=
9794                                                 IBV_RX_HASH_DST_PORT_TCP;
9795                         else
9796                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9797                 }
9798         }
9799 }
9800
9801 /**
9802  * Prepare an Rx Hash queue.
9803  *
9804  * @param dev
9805  *   Pointer to Ethernet device.
9806  * @param[in] dev_flow
9807  *   Pointer to the mlx5_flow.
9808  * @param[in] rss_desc
9809  *   Pointer to the mlx5_flow_rss_desc.
9810  * @param[out] hrxq_idx
9811  *   Hash Rx queue index.
9812  *
9813  * @return
9814  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9815  */
9816 static struct mlx5_hrxq *
9817 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9818                      struct mlx5_flow *dev_flow,
9819                      struct mlx5_flow_rss_desc *rss_desc,
9820                      uint32_t *hrxq_idx)
9821 {
9822         struct mlx5_priv *priv = dev->data->dev_private;
9823         struct mlx5_flow_handle *dh = dev_flow->handle;
9824         struct mlx5_hrxq *hrxq;
9825
9826         MLX5_ASSERT(rss_desc->queue_num);
9827         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9828         rss_desc->hash_fields = dev_flow->hash_fields;
9829         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9830         rss_desc->shared_rss = 0;
9831         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9832         if (!*hrxq_idx)
9833                 return NULL;
9834         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9835                               *hrxq_idx);
9836         return hrxq;
9837 }
9838
9839 /**
9840  * Release sample sub action resource.
9841  *
9842  * @param[in, out] dev
9843  *   Pointer to rte_eth_dev structure.
9844  * @param[in] act_res
9845  *   Pointer to sample sub action resource.
9846  */
9847 static void
9848 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9849                                    struct mlx5_flow_sub_actions_idx *act_res)
9850 {
9851         if (act_res->rix_hrxq) {
9852                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9853                 act_res->rix_hrxq = 0;
9854         }
9855         if (act_res->rix_encap_decap) {
9856                 flow_dv_encap_decap_resource_release(dev,
9857                                                      act_res->rix_encap_decap);
9858                 act_res->rix_encap_decap = 0;
9859         }
9860         if (act_res->rix_port_id_action) {
9861                 flow_dv_port_id_action_resource_release(dev,
9862                                                 act_res->rix_port_id_action);
9863                 act_res->rix_port_id_action = 0;
9864         }
9865         if (act_res->rix_tag) {
9866                 flow_dv_tag_release(dev, act_res->rix_tag);
9867                 act_res->rix_tag = 0;
9868         }
9869         if (act_res->rix_jump) {
9870                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9871                 act_res->rix_jump = 0;
9872         }
9873 }
9874
9875 int
9876 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9877                         struct mlx5_cache_entry *entry, void *cb_ctx)
9878 {
9879         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9880         struct rte_eth_dev *dev = ctx->dev;
9881         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9882         struct mlx5_flow_dv_sample_resource *cache_resource =
9883                         container_of(entry, typeof(*cache_resource), entry);
9884
9885         if (resource->ratio == cache_resource->ratio &&
9886             resource->ft_type == cache_resource->ft_type &&
9887             resource->ft_id == cache_resource->ft_id &&
9888             resource->set_action == cache_resource->set_action &&
9889             !memcmp((void *)&resource->sample_act,
9890                     (void *)&cache_resource->sample_act,
9891                     sizeof(struct mlx5_flow_sub_actions_list))) {
9892                 /*
9893                  * Existing sample action should release the prepared
9894                  * sub-actions reference counter.
9895                  */
9896                 flow_dv_sample_sub_actions_release(dev,
9897                                                 &resource->sample_idx);
9898                 return 0;
9899         }
9900         return 1;
9901 }
9902
9903 struct mlx5_cache_entry *
9904 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9905                          struct mlx5_cache_entry *entry __rte_unused,
9906                          void *cb_ctx)
9907 {
9908         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9909         struct rte_eth_dev *dev = ctx->dev;
9910         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9911         void **sample_dv_actions = resource->sub_actions;
9912         struct mlx5_flow_dv_sample_resource *cache_resource;
9913         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9914         struct mlx5_priv *priv = dev->data->dev_private;
9915         struct mlx5_dev_ctx_shared *sh = priv->sh;
9916         struct mlx5_flow_tbl_resource *tbl;
9917         uint32_t idx = 0;
9918         const uint32_t next_ft_step = 1;
9919         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9920         uint8_t is_egress = 0;
9921         uint8_t is_transfer = 0;
9922         struct rte_flow_error *error = ctx->error;
9923
9924         /* Register new sample resource. */
9925         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9926         if (!cache_resource) {
9927                 rte_flow_error_set(error, ENOMEM,
9928                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9929                                           NULL,
9930                                           "cannot allocate resource memory");
9931                 return NULL;
9932         }
9933         *cache_resource = *resource;
9934         /* Create normal path table level */
9935         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9936                 is_transfer = 1;
9937         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9938                 is_egress = 1;
9939         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9940                                         is_egress, is_transfer,
9941                                         true, NULL, 0, 0, error);
9942         if (!tbl) {
9943                 rte_flow_error_set(error, ENOMEM,
9944                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9945                                           NULL,
9946                                           "fail to create normal path table "
9947                                           "for sample");
9948                 goto error;
9949         }
9950         cache_resource->normal_path_tbl = tbl;
9951         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9952                 if (!sh->default_miss_action) {
9953                         rte_flow_error_set(error, ENOMEM,
9954                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9955                                                 NULL,
9956                                                 "default miss action was not "
9957                                                 "created");
9958                         goto error;
9959                 }
9960                 sample_dv_actions[resource->sample_act.actions_num++] =
9961                                                 sh->default_miss_action;
9962         }
9963         /* Create a DR sample action */
9964         sampler_attr.sample_ratio = cache_resource->ratio;
9965         sampler_attr.default_next_table = tbl->obj;
9966         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9967         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9968                                                         &sample_dv_actions[0];
9969         sampler_attr.action = cache_resource->set_action;
9970         if (mlx5_os_flow_dr_create_flow_action_sampler
9971                         (&sampler_attr, &cache_resource->verbs_action)) {
9972                 rte_flow_error_set(error, ENOMEM,
9973                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9974                                         NULL, "cannot create sample action");
9975                 goto error;
9976         }
9977         cache_resource->idx = idx;
9978         cache_resource->dev = dev;
9979         return &cache_resource->entry;
9980 error:
9981         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9982                 flow_dv_sample_sub_actions_release(dev,
9983                                                    &cache_resource->sample_idx);
9984         if (cache_resource->normal_path_tbl)
9985                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9986                                 cache_resource->normal_path_tbl);
9987         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9988         return NULL;
9989
9990 }
9991
9992 /**
9993  * Find existing sample resource or create and register a new one.
9994  *
9995  * @param[in, out] dev
9996  *   Pointer to rte_eth_dev structure.
9997  * @param[in] resource
9998  *   Pointer to sample resource.
9999  * @parm[in, out] dev_flow
10000  *   Pointer to the dev_flow.
10001  * @param[out] error
10002  *   pointer to error structure.
10003  *
10004  * @return
10005  *   0 on success otherwise -errno and errno is set.
10006  */
10007 static int
10008 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
10009                          struct mlx5_flow_dv_sample_resource *resource,
10010                          struct mlx5_flow *dev_flow,
10011                          struct rte_flow_error *error)
10012 {
10013         struct mlx5_flow_dv_sample_resource *cache_resource;
10014         struct mlx5_cache_entry *entry;
10015         struct mlx5_priv *priv = dev->data->dev_private;
10016         struct mlx5_flow_cb_ctx ctx = {
10017                 .dev = dev,
10018                 .error = error,
10019                 .data = resource,
10020         };
10021
10022         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10023         if (!entry)
10024                 return -rte_errno;
10025         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10026         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10027         dev_flow->dv.sample_res = cache_resource;
10028         return 0;
10029 }
10030
10031 int
10032 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10033                             struct mlx5_cache_entry *entry, void *cb_ctx)
10034 {
10035         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10036         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10037         struct rte_eth_dev *dev = ctx->dev;
10038         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10039                         container_of(entry, typeof(*cache_resource), entry);
10040         uint32_t idx = 0;
10041
10042         if (resource->num_of_dest == cache_resource->num_of_dest &&
10043             resource->ft_type == cache_resource->ft_type &&
10044             !memcmp((void *)cache_resource->sample_act,
10045                     (void *)resource->sample_act,
10046                    (resource->num_of_dest *
10047                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10048                 /*
10049                  * Existing sample action should release the prepared
10050                  * sub-actions reference counter.
10051                  */
10052                 for (idx = 0; idx < resource->num_of_dest; idx++)
10053                         flow_dv_sample_sub_actions_release(dev,
10054                                         &resource->sample_idx[idx]);
10055                 return 0;
10056         }
10057         return 1;
10058 }
10059
10060 struct mlx5_cache_entry *
10061 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10062                          struct mlx5_cache_entry *entry __rte_unused,
10063                          void *cb_ctx)
10064 {
10065         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10066         struct rte_eth_dev *dev = ctx->dev;
10067         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10068         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10069         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10070         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10071         struct mlx5_priv *priv = dev->data->dev_private;
10072         struct mlx5_dev_ctx_shared *sh = priv->sh;
10073         struct mlx5_flow_sub_actions_list *sample_act;
10074         struct mlx5dv_dr_domain *domain;
10075         uint32_t idx = 0, res_idx = 0;
10076         struct rte_flow_error *error = ctx->error;
10077         uint64_t action_flags;
10078         int ret;
10079
10080         /* Register new destination array resource. */
10081         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10082                                             &res_idx);
10083         if (!cache_resource) {
10084                 rte_flow_error_set(error, ENOMEM,
10085                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10086                                           NULL,
10087                                           "cannot allocate resource memory");
10088                 return NULL;
10089         }
10090         *cache_resource = *resource;
10091         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10092                 domain = sh->fdb_domain;
10093         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10094                 domain = sh->rx_domain;
10095         else
10096                 domain = sh->tx_domain;
10097         for (idx = 0; idx < resource->num_of_dest; idx++) {
10098                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10099                                  mlx5_malloc(MLX5_MEM_ZERO,
10100                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10101                                  0, SOCKET_ID_ANY);
10102                 if (!dest_attr[idx]) {
10103                         rte_flow_error_set(error, ENOMEM,
10104                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10105                                            NULL,
10106                                            "cannot allocate resource memory");
10107                         goto error;
10108                 }
10109                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10110                 sample_act = &resource->sample_act[idx];
10111                 action_flags = sample_act->action_flags;
10112                 switch (action_flags) {
10113                 case MLX5_FLOW_ACTION_QUEUE:
10114                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10115                         break;
10116                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10117                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10118                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10119                         dest_attr[idx]->dest_reformat->reformat =
10120                                         sample_act->dr_encap_action;
10121                         dest_attr[idx]->dest_reformat->dest =
10122                                         sample_act->dr_port_id_action;
10123                         break;
10124                 case MLX5_FLOW_ACTION_PORT_ID:
10125                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10126                         break;
10127                 case MLX5_FLOW_ACTION_JUMP:
10128                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10129                         break;
10130                 default:
10131                         rte_flow_error_set(error, EINVAL,
10132                                            RTE_FLOW_ERROR_TYPE_ACTION,
10133                                            NULL,
10134                                            "unsupported actions type");
10135                         goto error;
10136                 }
10137         }
10138         /* create a dest array actioin */
10139         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10140                                                 (domain,
10141                                                  cache_resource->num_of_dest,
10142                                                  dest_attr,
10143                                                  &cache_resource->action);
10144         if (ret) {
10145                 rte_flow_error_set(error, ENOMEM,
10146                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10147                                    NULL,
10148                                    "cannot create destination array action");
10149                 goto error;
10150         }
10151         cache_resource->idx = res_idx;
10152         cache_resource->dev = dev;
10153         for (idx = 0; idx < resource->num_of_dest; idx++)
10154                 mlx5_free(dest_attr[idx]);
10155         return &cache_resource->entry;
10156 error:
10157         for (idx = 0; idx < resource->num_of_dest; idx++) {
10158                 flow_dv_sample_sub_actions_release(dev,
10159                                 &cache_resource->sample_idx[idx]);
10160                 if (dest_attr[idx])
10161                         mlx5_free(dest_attr[idx]);
10162         }
10163
10164         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10165         return NULL;
10166 }
10167
10168 /**
10169  * Find existing destination array resource or create and register a new one.
10170  *
10171  * @param[in, out] dev
10172  *   Pointer to rte_eth_dev structure.
10173  * @param[in] resource
10174  *   Pointer to destination array resource.
10175  * @parm[in, out] dev_flow
10176  *   Pointer to the dev_flow.
10177  * @param[out] error
10178  *   pointer to error structure.
10179  *
10180  * @return
10181  *   0 on success otherwise -errno and errno is set.
10182  */
10183 static int
10184 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10185                          struct mlx5_flow_dv_dest_array_resource *resource,
10186                          struct mlx5_flow *dev_flow,
10187                          struct rte_flow_error *error)
10188 {
10189         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10190         struct mlx5_priv *priv = dev->data->dev_private;
10191         struct mlx5_cache_entry *entry;
10192         struct mlx5_flow_cb_ctx ctx = {
10193                 .dev = dev,
10194                 .error = error,
10195                 .data = resource,
10196         };
10197
10198         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10199         if (!entry)
10200                 return -rte_errno;
10201         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10202         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10203         dev_flow->dv.dest_array_res = cache_resource;
10204         return 0;
10205 }
10206
10207 /**
10208  * Convert Sample action to DV specification.
10209  *
10210  * @param[in] dev
10211  *   Pointer to rte_eth_dev structure.
10212  * @param[in] action
10213  *   Pointer to sample action structure.
10214  * @param[in, out] dev_flow
10215  *   Pointer to the mlx5_flow.
10216  * @param[in] attr
10217  *   Pointer to the flow attributes.
10218  * @param[in, out] num_of_dest
10219  *   Pointer to the num of destination.
10220  * @param[in, out] sample_actions
10221  *   Pointer to sample actions list.
10222  * @param[in, out] res
10223  *   Pointer to sample resource.
10224  * @param[out] error
10225  *   Pointer to the error structure.
10226  *
10227  * @return
10228  *   0 on success, a negative errno value otherwise and rte_errno is set.
10229  */
10230 static int
10231 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10232                                 const struct rte_flow_action_sample *action,
10233                                 struct mlx5_flow *dev_flow,
10234                                 const struct rte_flow_attr *attr,
10235                                 uint32_t *num_of_dest,
10236                                 void **sample_actions,
10237                                 struct mlx5_flow_dv_sample_resource *res,
10238                                 struct rte_flow_error *error)
10239 {
10240         struct mlx5_priv *priv = dev->data->dev_private;
10241         const struct rte_flow_action *sub_actions;
10242         struct mlx5_flow_sub_actions_list *sample_act;
10243         struct mlx5_flow_sub_actions_idx *sample_idx;
10244         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10245         struct rte_flow *flow = dev_flow->flow;
10246         struct mlx5_flow_rss_desc *rss_desc;
10247         uint64_t action_flags = 0;
10248
10249         MLX5_ASSERT(wks);
10250         rss_desc = &wks->rss_desc;
10251         sample_act = &res->sample_act;
10252         sample_idx = &res->sample_idx;
10253         res->ratio = action->ratio;
10254         sub_actions = action->actions;
10255         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10256                 int type = sub_actions->type;
10257                 uint32_t pre_rix = 0;
10258                 void *pre_r;
10259                 switch (type) {
10260                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10261                 {
10262                         const struct rte_flow_action_queue *queue;
10263                         struct mlx5_hrxq *hrxq;
10264                         uint32_t hrxq_idx;
10265
10266                         queue = sub_actions->conf;
10267                         rss_desc->queue_num = 1;
10268                         rss_desc->queue[0] = queue->index;
10269                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10270                                                     rss_desc, &hrxq_idx);
10271                         if (!hrxq)
10272                                 return rte_flow_error_set
10273                                         (error, rte_errno,
10274                                          RTE_FLOW_ERROR_TYPE_ACTION,
10275                                          NULL,
10276                                          "cannot create fate queue");
10277                         sample_act->dr_queue_action = hrxq->action;
10278                         sample_idx->rix_hrxq = hrxq_idx;
10279                         sample_actions[sample_act->actions_num++] =
10280                                                 hrxq->action;
10281                         (*num_of_dest)++;
10282                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10283                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10284                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10285                         dev_flow->handle->fate_action =
10286                                         MLX5_FLOW_FATE_QUEUE;
10287                         break;
10288                 }
10289                 case RTE_FLOW_ACTION_TYPE_RSS:
10290                 {
10291                         struct mlx5_hrxq *hrxq;
10292                         uint32_t hrxq_idx;
10293                         const struct rte_flow_action_rss *rss;
10294                         const uint8_t *rss_key;
10295
10296                         rss = sub_actions->conf;
10297                         memcpy(rss_desc->queue, rss->queue,
10298                                rss->queue_num * sizeof(uint16_t));
10299                         rss_desc->queue_num = rss->queue_num;
10300                         /* NULL RSS key indicates default RSS key. */
10301                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10302                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10303                         /*
10304                          * rss->level and rss.types should be set in advance
10305                          * when expanding items for RSS.
10306                          */
10307                         flow_dv_hashfields_set(dev_flow, rss_desc);
10308                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10309                                                     rss_desc, &hrxq_idx);
10310                         if (!hrxq)
10311                                 return rte_flow_error_set
10312                                         (error, rte_errno,
10313                                          RTE_FLOW_ERROR_TYPE_ACTION,
10314                                          NULL,
10315                                          "cannot create fate queue");
10316                         sample_act->dr_queue_action = hrxq->action;
10317                         sample_idx->rix_hrxq = hrxq_idx;
10318                         sample_actions[sample_act->actions_num++] =
10319                                                 hrxq->action;
10320                         (*num_of_dest)++;
10321                         action_flags |= MLX5_FLOW_ACTION_RSS;
10322                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10323                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10324                         dev_flow->handle->fate_action =
10325                                         MLX5_FLOW_FATE_QUEUE;
10326                         break;
10327                 }
10328                 case RTE_FLOW_ACTION_TYPE_MARK:
10329                 {
10330                         uint32_t tag_be = mlx5_flow_mark_set
10331                                 (((const struct rte_flow_action_mark *)
10332                                 (sub_actions->conf))->id);
10333
10334                         dev_flow->handle->mark = 1;
10335                         pre_rix = dev_flow->handle->dvh.rix_tag;
10336                         /* Save the mark resource before sample */
10337                         pre_r = dev_flow->dv.tag_resource;
10338                         if (flow_dv_tag_resource_register(dev, tag_be,
10339                                                   dev_flow, error))
10340                                 return -rte_errno;
10341                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10342                         sample_act->dr_tag_action =
10343                                 dev_flow->dv.tag_resource->action;
10344                         sample_idx->rix_tag =
10345                                 dev_flow->handle->dvh.rix_tag;
10346                         sample_actions[sample_act->actions_num++] =
10347                                                 sample_act->dr_tag_action;
10348                         /* Recover the mark resource after sample */
10349                         dev_flow->dv.tag_resource = pre_r;
10350                         dev_flow->handle->dvh.rix_tag = pre_rix;
10351                         action_flags |= MLX5_FLOW_ACTION_MARK;
10352                         break;
10353                 }
10354                 case RTE_FLOW_ACTION_TYPE_COUNT:
10355                 {
10356                         if (!flow->counter) {
10357                                 flow->counter =
10358                                         flow_dv_translate_create_counter(dev,
10359                                                 dev_flow, sub_actions->conf,
10360                                                 0);
10361                                 if (!flow->counter)
10362                                         return rte_flow_error_set
10363                                                 (error, rte_errno,
10364                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10365                                                 NULL,
10366                                                 "cannot create counter"
10367                                                 " object.");
10368                         }
10369                         sample_act->dr_cnt_action =
10370                                   (flow_dv_counter_get_by_idx(dev,
10371                                   flow->counter, NULL))->action;
10372                         sample_actions[sample_act->actions_num++] =
10373                                                 sample_act->dr_cnt_action;
10374                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10375                         break;
10376                 }
10377                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10378                 {
10379                         struct mlx5_flow_dv_port_id_action_resource
10380                                         port_id_resource;
10381                         uint32_t port_id = 0;
10382
10383                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10384                         /* Save the port id resource before sample */
10385                         pre_rix = dev_flow->handle->rix_port_id_action;
10386                         pre_r = dev_flow->dv.port_id_action;
10387                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10388                                                              &port_id, error))
10389                                 return -rte_errno;
10390                         port_id_resource.port_id = port_id;
10391                         if (flow_dv_port_id_action_resource_register
10392                             (dev, &port_id_resource, dev_flow, error))
10393                                 return -rte_errno;
10394                         sample_act->dr_port_id_action =
10395                                 dev_flow->dv.port_id_action->action;
10396                         sample_idx->rix_port_id_action =
10397                                 dev_flow->handle->rix_port_id_action;
10398                         sample_actions[sample_act->actions_num++] =
10399                                                 sample_act->dr_port_id_action;
10400                         /* Recover the port id resource after sample */
10401                         dev_flow->dv.port_id_action = pre_r;
10402                         dev_flow->handle->rix_port_id_action = pre_rix;
10403                         (*num_of_dest)++;
10404                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10405                         break;
10406                 }
10407                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
10408                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
10409                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10410                         /* Save the encap resource before sample */
10411                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10412                         pre_r = dev_flow->dv.encap_decap;
10413                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10414                                                            dev_flow,
10415                                                            attr->transfer,
10416                                                            error))
10417                                 return -rte_errno;
10418                         sample_act->dr_encap_action =
10419                                 dev_flow->dv.encap_decap->action;
10420                         sample_idx->rix_encap_decap =
10421                                 dev_flow->handle->dvh.rix_encap_decap;
10422                         sample_actions[sample_act->actions_num++] =
10423                                                 sample_act->dr_encap_action;
10424                         /* Recover the encap resource after sample */
10425                         dev_flow->dv.encap_decap = pre_r;
10426                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10427                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10428                         break;
10429                 default:
10430                         return rte_flow_error_set(error, EINVAL,
10431                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10432                                 NULL,
10433                                 "Not support for sampler action");
10434                 }
10435         }
10436         sample_act->action_flags = action_flags;
10437         res->ft_id = dev_flow->dv.group;
10438         if (attr->transfer) {
10439                 union {
10440                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10441                         uint64_t set_action;
10442                 } action_ctx = { .set_action = 0 };
10443
10444                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10445                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10446                          MLX5_MODIFICATION_TYPE_SET);
10447                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10448                          MLX5_MODI_META_REG_C_0);
10449                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10450                          priv->vport_meta_tag);
10451                 res->set_action = action_ctx.set_action;
10452         } else if (attr->ingress) {
10453                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10454         } else {
10455                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10456         }
10457         return 0;
10458 }
10459
10460 /**
10461  * Convert Sample action to DV specification.
10462  *
10463  * @param[in] dev
10464  *   Pointer to rte_eth_dev structure.
10465  * @param[in, out] dev_flow
10466  *   Pointer to the mlx5_flow.
10467  * @param[in] num_of_dest
10468  *   The num of destination.
10469  * @param[in, out] res
10470  *   Pointer to sample resource.
10471  * @param[in, out] mdest_res
10472  *   Pointer to destination array resource.
10473  * @param[in] sample_actions
10474  *   Pointer to sample path actions list.
10475  * @param[in] action_flags
10476  *   Holds the actions detected until now.
10477  * @param[out] error
10478  *   Pointer to the error structure.
10479  *
10480  * @return
10481  *   0 on success, a negative errno value otherwise and rte_errno is set.
10482  */
10483 static int
10484 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10485                              struct mlx5_flow *dev_flow,
10486                              uint32_t num_of_dest,
10487                              struct mlx5_flow_dv_sample_resource *res,
10488                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10489                              void **sample_actions,
10490                              uint64_t action_flags,
10491                              struct rte_flow_error *error)
10492 {
10493         /* update normal path action resource into last index of array */
10494         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10495         struct mlx5_flow_sub_actions_list *sample_act =
10496                                         &mdest_res->sample_act[dest_index];
10497         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10498         struct mlx5_flow_rss_desc *rss_desc;
10499         uint32_t normal_idx = 0;
10500         struct mlx5_hrxq *hrxq;
10501         uint32_t hrxq_idx;
10502
10503         MLX5_ASSERT(wks);
10504         rss_desc = &wks->rss_desc;
10505         if (num_of_dest > 1) {
10506                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10507                         /* Handle QP action for mirroring */
10508                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10509                                                     rss_desc, &hrxq_idx);
10510                         if (!hrxq)
10511                                 return rte_flow_error_set
10512                                      (error, rte_errno,
10513                                       RTE_FLOW_ERROR_TYPE_ACTION,
10514                                       NULL,
10515                                       "cannot create rx queue");
10516                         normal_idx++;
10517                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10518                         sample_act->dr_queue_action = hrxq->action;
10519                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10520                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10521                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10522                 }
10523                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10524                         normal_idx++;
10525                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10526                                 dev_flow->handle->dvh.rix_encap_decap;
10527                         sample_act->dr_encap_action =
10528                                 dev_flow->dv.encap_decap->action;
10529                         dev_flow->handle->dvh.rix_encap_decap = 0;
10530                 }
10531                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10532                         normal_idx++;
10533                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10534                                 dev_flow->handle->rix_port_id_action;
10535                         sample_act->dr_port_id_action =
10536                                 dev_flow->dv.port_id_action->action;
10537                         dev_flow->handle->rix_port_id_action = 0;
10538                 }
10539                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10540                         normal_idx++;
10541                         mdest_res->sample_idx[dest_index].rix_jump =
10542                                 dev_flow->handle->rix_jump;
10543                         sample_act->dr_jump_action =
10544                                 dev_flow->dv.jump->action;
10545                         dev_flow->handle->rix_jump = 0;
10546                 }
10547                 sample_act->actions_num = normal_idx;
10548                 /* update sample action resource into first index of array */
10549                 mdest_res->ft_type = res->ft_type;
10550                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10551                                 sizeof(struct mlx5_flow_sub_actions_idx));
10552                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10553                                 sizeof(struct mlx5_flow_sub_actions_list));
10554                 mdest_res->num_of_dest = num_of_dest;
10555                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10556                                                          dev_flow, error))
10557                         return rte_flow_error_set(error, EINVAL,
10558                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10559                                                   NULL, "can't create sample "
10560                                                   "action");
10561         } else {
10562                 res->sub_actions = sample_actions;
10563                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10564                         return rte_flow_error_set(error, EINVAL,
10565                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10566                                                   NULL,
10567                                                   "can't create sample action");
10568         }
10569         return 0;
10570 }
10571
10572 /**
10573  * Remove an ASO age action from age actions list.
10574  *
10575  * @param[in] dev
10576  *   Pointer to the Ethernet device structure.
10577  * @param[in] age
10578  *   Pointer to the aso age action handler.
10579  */
10580 static void
10581 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10582                                 struct mlx5_aso_age_action *age)
10583 {
10584         struct mlx5_age_info *age_info;
10585         struct mlx5_age_param *age_param = &age->age_params;
10586         struct mlx5_priv *priv = dev->data->dev_private;
10587         uint16_t expected = AGE_CANDIDATE;
10588
10589         age_info = GET_PORT_AGE_INFO(priv);
10590         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10591                                          AGE_FREE, false, __ATOMIC_RELAXED,
10592                                          __ATOMIC_RELAXED)) {
10593                 /**
10594                  * We need the lock even it is age timeout,
10595                  * since age action may still in process.
10596                  */
10597                 rte_spinlock_lock(&age_info->aged_sl);
10598                 LIST_REMOVE(age, next);
10599                 rte_spinlock_unlock(&age_info->aged_sl);
10600                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10601         }
10602 }
10603
10604 /**
10605  * Release an ASO age action.
10606  *
10607  * @param[in] dev
10608  *   Pointer to the Ethernet device structure.
10609  * @param[in] age_idx
10610  *   Index of ASO age action to release.
10611  * @param[in] flow
10612  *   True if the release operation is during flow destroy operation.
10613  *   False if the release operation is during action destroy operation.
10614  *
10615  * @return
10616  *   0 when age action was removed, otherwise the number of references.
10617  */
10618 static int
10619 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10620 {
10621         struct mlx5_priv *priv = dev->data->dev_private;
10622         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10623         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10624         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10625
10626         if (!ret) {
10627                 flow_dv_aso_age_remove_from_age(dev, age);
10628                 rte_spinlock_lock(&mng->free_sl);
10629                 LIST_INSERT_HEAD(&mng->free, age, next);
10630                 rte_spinlock_unlock(&mng->free_sl);
10631         }
10632         return ret;
10633 }
10634
10635 /**
10636  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10637  *
10638  * @param[in] dev
10639  *   Pointer to the Ethernet device structure.
10640  *
10641  * @return
10642  *   0 on success, otherwise negative errno value and rte_errno is set.
10643  */
10644 static int
10645 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10646 {
10647         struct mlx5_priv *priv = dev->data->dev_private;
10648         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10649         void *old_pools = mng->pools;
10650         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10651         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10652         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10653
10654         if (!pools) {
10655                 rte_errno = ENOMEM;
10656                 return -ENOMEM;
10657         }
10658         if (old_pools) {
10659                 memcpy(pools, old_pools,
10660                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10661                 mlx5_free(old_pools);
10662         } else {
10663                 /* First ASO flow hit allocation - starting ASO data-path. */
10664                 int ret = mlx5_aso_queue_start(priv->sh);
10665
10666                 if (ret) {
10667                         mlx5_free(pools);
10668                         return ret;
10669                 }
10670         }
10671         mng->n = resize;
10672         mng->pools = pools;
10673         return 0;
10674 }
10675
10676 /**
10677  * Create and initialize a new ASO aging pool.
10678  *
10679  * @param[in] dev
10680  *   Pointer to the Ethernet device structure.
10681  * @param[out] age_free
10682  *   Where to put the pointer of a new age action.
10683  *
10684  * @return
10685  *   The age actions pool pointer and @p age_free is set on success,
10686  *   NULL otherwise and rte_errno is set.
10687  */
10688 static struct mlx5_aso_age_pool *
10689 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10690                         struct mlx5_aso_age_action **age_free)
10691 {
10692         struct mlx5_priv *priv = dev->data->dev_private;
10693         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10694         struct mlx5_aso_age_pool *pool = NULL;
10695         struct mlx5_devx_obj *obj = NULL;
10696         uint32_t i;
10697
10698         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10699                                                     priv->sh->pdn);
10700         if (!obj) {
10701                 rte_errno = ENODATA;
10702                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10703                 return NULL;
10704         }
10705         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10706         if (!pool) {
10707                 claim_zero(mlx5_devx_cmd_destroy(obj));
10708                 rte_errno = ENOMEM;
10709                 return NULL;
10710         }
10711         pool->flow_hit_aso_obj = obj;
10712         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10713         rte_spinlock_lock(&mng->resize_sl);
10714         pool->index = mng->next;
10715         /* Resize pools array if there is no room for the new pool in it. */
10716         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10717                 claim_zero(mlx5_devx_cmd_destroy(obj));
10718                 mlx5_free(pool);
10719                 rte_spinlock_unlock(&mng->resize_sl);
10720                 return NULL;
10721         }
10722         mng->pools[pool->index] = pool;
10723         mng->next++;
10724         rte_spinlock_unlock(&mng->resize_sl);
10725         /* Assign the first action in the new pool, the rest go to free list. */
10726         *age_free = &pool->actions[0];
10727         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10728                 pool->actions[i].offset = i;
10729                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10730         }
10731         return pool;
10732 }
10733
10734 /**
10735  * Allocate a ASO aging bit.
10736  *
10737  * @param[in] dev
10738  *   Pointer to the Ethernet device structure.
10739  * @param[out] error
10740  *   Pointer to the error structure.
10741  *
10742  * @return
10743  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10744  */
10745 static uint32_t
10746 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10747 {
10748         struct mlx5_priv *priv = dev->data->dev_private;
10749         const struct mlx5_aso_age_pool *pool;
10750         struct mlx5_aso_age_action *age_free = NULL;
10751         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10752
10753         MLX5_ASSERT(mng);
10754         /* Try to get the next free age action bit. */
10755         rte_spinlock_lock(&mng->free_sl);
10756         age_free = LIST_FIRST(&mng->free);
10757         if (age_free) {
10758                 LIST_REMOVE(age_free, next);
10759         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10760                 rte_spinlock_unlock(&mng->free_sl);
10761                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10762                                    NULL, "failed to create ASO age pool");
10763                 return 0; /* 0 is an error. */
10764         }
10765         rte_spinlock_unlock(&mng->free_sl);
10766         pool = container_of
10767           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10768                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10769                                                                        actions);
10770         if (!age_free->dr_action) {
10771                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10772                                                  error);
10773
10774                 if (reg_c < 0) {
10775                         rte_flow_error_set(error, rte_errno,
10776                                            RTE_FLOW_ERROR_TYPE_ACTION,
10777                                            NULL, "failed to get reg_c "
10778                                            "for ASO flow hit");
10779                         return 0; /* 0 is an error. */
10780                 }
10781 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10782                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10783                                 (priv->sh->rx_domain,
10784                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10785                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10786                                  (reg_c - REG_C_0));
10787 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10788                 if (!age_free->dr_action) {
10789                         rte_errno = errno;
10790                         rte_spinlock_lock(&mng->free_sl);
10791                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10792                         rte_spinlock_unlock(&mng->free_sl);
10793                         rte_flow_error_set(error, rte_errno,
10794                                            RTE_FLOW_ERROR_TYPE_ACTION,
10795                                            NULL, "failed to create ASO "
10796                                            "flow hit action");
10797                         return 0; /* 0 is an error. */
10798                 }
10799         }
10800         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10801         return pool->index | ((age_free->offset + 1) << 16);
10802 }
10803
10804 /**
10805  * Create a age action using ASO mechanism.
10806  *
10807  * @param[in] dev
10808  *   Pointer to rte_eth_dev structure.
10809  * @param[in] age
10810  *   Pointer to the aging action configuration.
10811  * @param[out] error
10812  *   Pointer to the error structure.
10813  *
10814  * @return
10815  *   Index to flow counter on success, 0 otherwise.
10816  */
10817 static uint32_t
10818 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10819                                  const struct rte_flow_action_age *age,
10820                                  struct rte_flow_error *error)
10821 {
10822         uint32_t age_idx = 0;
10823         struct mlx5_aso_age_action *aso_age;
10824
10825         age_idx = flow_dv_aso_age_alloc(dev, error);
10826         if (!age_idx)
10827                 return 0;
10828         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10829         aso_age->age_params.context = age->context;
10830         aso_age->age_params.timeout = age->timeout;
10831         aso_age->age_params.port_id = dev->data->port_id;
10832         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10833                          __ATOMIC_RELAXED);
10834         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10835                          __ATOMIC_RELAXED);
10836         return age_idx;
10837 }
10838
10839 /**
10840  * Fill the flow with DV spec, lock free
10841  * (mutex should be acquired by caller).
10842  *
10843  * @param[in] dev
10844  *   Pointer to rte_eth_dev structure.
10845  * @param[in, out] dev_flow
10846  *   Pointer to the sub flow.
10847  * @param[in] attr
10848  *   Pointer to the flow attributes.
10849  * @param[in] items
10850  *   Pointer to the list of items.
10851  * @param[in] actions
10852  *   Pointer to the list of actions.
10853  * @param[out] error
10854  *   Pointer to the error structure.
10855  *
10856  * @return
10857  *   0 on success, a negative errno value otherwise and rte_errno is set.
10858  */
10859 static int
10860 flow_dv_translate(struct rte_eth_dev *dev,
10861                   struct mlx5_flow *dev_flow,
10862                   const struct rte_flow_attr *attr,
10863                   const struct rte_flow_item items[],
10864                   const struct rte_flow_action actions[],
10865                   struct rte_flow_error *error)
10866 {
10867         struct mlx5_priv *priv = dev->data->dev_private;
10868         struct mlx5_dev_config *dev_conf = &priv->config;
10869         struct rte_flow *flow = dev_flow->flow;
10870         struct mlx5_flow_handle *handle = dev_flow->handle;
10871         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10872         struct mlx5_flow_rss_desc *rss_desc;
10873         uint64_t item_flags = 0;
10874         uint64_t last_item = 0;
10875         uint64_t action_flags = 0;
10876         struct mlx5_flow_dv_matcher matcher = {
10877                 .mask = {
10878                         .size = sizeof(matcher.mask.buf) -
10879                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10880                 },
10881         };
10882         int actions_n = 0;
10883         bool actions_end = false;
10884         union {
10885                 struct mlx5_flow_dv_modify_hdr_resource res;
10886                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10887                             sizeof(struct mlx5_modification_cmd) *
10888                             (MLX5_MAX_MODIFY_NUM + 1)];
10889         } mhdr_dummy;
10890         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10891         const struct rte_flow_action_count *count = NULL;
10892         const struct rte_flow_action_age *age = NULL;
10893         union flow_dv_attr flow_attr = { .attr = 0 };
10894         uint32_t tag_be;
10895         union mlx5_flow_tbl_key tbl_key;
10896         uint32_t modify_action_position = UINT32_MAX;
10897         void *match_mask = matcher.mask.buf;
10898         void *match_value = dev_flow->dv.value.buf;
10899         uint8_t next_protocol = 0xff;
10900         struct rte_vlan_hdr vlan = { 0 };
10901         struct mlx5_flow_dv_dest_array_resource mdest_res;
10902         struct mlx5_flow_dv_sample_resource sample_res;
10903         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10904         const struct rte_flow_action_sample *sample = NULL;
10905         struct mlx5_flow_sub_actions_list *sample_act;
10906         uint32_t sample_act_pos = UINT32_MAX;
10907         uint32_t num_of_dest = 0;
10908         int tmp_actions_n = 0;
10909         uint32_t table;
10910         int ret = 0;
10911         const struct mlx5_flow_tunnel *tunnel;
10912         struct flow_grp_info grp_info = {
10913                 .external = !!dev_flow->external,
10914                 .transfer = !!attr->transfer,
10915                 .fdb_def_rule = !!priv->fdb_def_rule,
10916                 .skip_scale = dev_flow->skip_scale &
10917                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10918         };
10919
10920         if (!wks)
10921                 return rte_flow_error_set(error, ENOMEM,
10922                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10923                                           NULL,
10924                                           "failed to push flow workspace");
10925         rss_desc = &wks->rss_desc;
10926         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10927         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10928         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10929                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10930         /* update normal path action resource into last index of array */
10931         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10932         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10933                  flow_items_to_tunnel(items) :
10934                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10935                  flow_actions_to_tunnel(actions) :
10936                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10937         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10938                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10939         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10940                                 (dev, tunnel, attr, items, actions);
10941         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10942                                        &grp_info, error);
10943         if (ret)
10944                 return ret;
10945         dev_flow->dv.group = table;
10946         if (attr->transfer)
10947                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10948         /* number of actions must be set to 0 in case of dirty stack. */
10949         mhdr_res->actions_num = 0;
10950         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10951                 /*
10952                  * do not add decap action if match rule drops packet
10953                  * HW rejects rules with decap & drop
10954                  *
10955                  * if tunnel match rule was inserted before matching tunnel set
10956                  * rule flow table used in the match rule must be registered.
10957                  * current implementation handles that in the
10958                  * flow_dv_match_register() at the function end.
10959                  */
10960                 bool add_decap = true;
10961                 const struct rte_flow_action *ptr = actions;
10962
10963                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10964                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10965                                 add_decap = false;
10966                                 break;
10967                         }
10968                 }
10969                 if (add_decap) {
10970                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10971                                                            attr->transfer,
10972                                                            error))
10973                                 return -rte_errno;
10974                         dev_flow->dv.actions[actions_n++] =
10975                                         dev_flow->dv.encap_decap->action;
10976                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10977                 }
10978         }
10979         for (; !actions_end ; actions++) {
10980                 const struct rte_flow_action_queue *queue;
10981                 const struct rte_flow_action_rss *rss;
10982                 const struct rte_flow_action *action = actions;
10983                 const uint8_t *rss_key;
10984                 const struct rte_flow_action_meter *mtr;
10985                 struct mlx5_flow_tbl_resource *tbl;
10986                 struct mlx5_aso_age_action *age_act;
10987                 uint32_t port_id = 0;
10988                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10989                 int action_type = actions->type;
10990                 const struct rte_flow_action *found_action = NULL;
10991                 struct mlx5_flow_meter *fm = NULL;
10992                 uint32_t jump_group = 0;
10993
10994                 if (!mlx5_flow_os_action_supported(action_type))
10995                         return rte_flow_error_set(error, ENOTSUP,
10996                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10997                                                   actions,
10998                                                   "action not supported");
10999                 switch (action_type) {
11000                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
11001                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
11002                         break;
11003                 case RTE_FLOW_ACTION_TYPE_VOID:
11004                         break;
11005                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11006                         if (flow_dv_translate_action_port_id(dev, action,
11007                                                              &port_id, error))
11008                                 return -rte_errno;
11009                         port_id_resource.port_id = port_id;
11010                         MLX5_ASSERT(!handle->rix_port_id_action);
11011                         if (flow_dv_port_id_action_resource_register
11012                             (dev, &port_id_resource, dev_flow, error))
11013                                 return -rte_errno;
11014                         dev_flow->dv.actions[actions_n++] =
11015                                         dev_flow->dv.port_id_action->action;
11016                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11017                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11018                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11019                         num_of_dest++;
11020                         break;
11021                 case RTE_FLOW_ACTION_TYPE_FLAG:
11022                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11023                         dev_flow->handle->mark = 1;
11024                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11025                                 struct rte_flow_action_mark mark = {
11026                                         .id = MLX5_FLOW_MARK_DEFAULT,
11027                                 };
11028
11029                                 if (flow_dv_convert_action_mark(dev, &mark,
11030                                                                 mhdr_res,
11031                                                                 error))
11032                                         return -rte_errno;
11033                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11034                                 break;
11035                         }
11036                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11037                         /*
11038                          * Only one FLAG or MARK is supported per device flow
11039                          * right now. So the pointer to the tag resource must be
11040                          * zero before the register process.
11041                          */
11042                         MLX5_ASSERT(!handle->dvh.rix_tag);
11043                         if (flow_dv_tag_resource_register(dev, tag_be,
11044                                                           dev_flow, error))
11045                                 return -rte_errno;
11046                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11047                         dev_flow->dv.actions[actions_n++] =
11048                                         dev_flow->dv.tag_resource->action;
11049                         break;
11050                 case RTE_FLOW_ACTION_TYPE_MARK:
11051                         action_flags |= MLX5_FLOW_ACTION_MARK;
11052                         dev_flow->handle->mark = 1;
11053                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11054                                 const struct rte_flow_action_mark *mark =
11055                                         (const struct rte_flow_action_mark *)
11056                                                 actions->conf;
11057
11058                                 if (flow_dv_convert_action_mark(dev, mark,
11059                                                                 mhdr_res,
11060                                                                 error))
11061                                         return -rte_errno;
11062                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11063                                 break;
11064                         }
11065                         /* Fall-through */
11066                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11067                         /* Legacy (non-extensive) MARK action. */
11068                         tag_be = mlx5_flow_mark_set
11069                               (((const struct rte_flow_action_mark *)
11070                                (actions->conf))->id);
11071                         MLX5_ASSERT(!handle->dvh.rix_tag);
11072                         if (flow_dv_tag_resource_register(dev, tag_be,
11073                                                           dev_flow, error))
11074                                 return -rte_errno;
11075                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11076                         dev_flow->dv.actions[actions_n++] =
11077                                         dev_flow->dv.tag_resource->action;
11078                         break;
11079                 case RTE_FLOW_ACTION_TYPE_SET_META:
11080                         if (flow_dv_convert_action_set_meta
11081                                 (dev, mhdr_res, attr,
11082                                  (const struct rte_flow_action_set_meta *)
11083                                   actions->conf, error))
11084                                 return -rte_errno;
11085                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11086                         break;
11087                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11088                         if (flow_dv_convert_action_set_tag
11089                                 (dev, mhdr_res,
11090                                  (const struct rte_flow_action_set_tag *)
11091                                   actions->conf, error))
11092                                 return -rte_errno;
11093                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11094                         break;
11095                 case RTE_FLOW_ACTION_TYPE_DROP:
11096                         action_flags |= MLX5_FLOW_ACTION_DROP;
11097                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11098                         break;
11099                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11100                         queue = actions->conf;
11101                         rss_desc->queue_num = 1;
11102                         rss_desc->queue[0] = queue->index;
11103                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11104                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11105                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11106                         num_of_dest++;
11107                         break;
11108                 case RTE_FLOW_ACTION_TYPE_RSS:
11109                         rss = actions->conf;
11110                         memcpy(rss_desc->queue, rss->queue,
11111                                rss->queue_num * sizeof(uint16_t));
11112                         rss_desc->queue_num = rss->queue_num;
11113                         /* NULL RSS key indicates default RSS key. */
11114                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11115                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11116                         /*
11117                          * rss->level and rss.types should be set in advance
11118                          * when expanding items for RSS.
11119                          */
11120                         action_flags |= MLX5_FLOW_ACTION_RSS;
11121                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11122                                 MLX5_FLOW_FATE_SHARED_RSS :
11123                                 MLX5_FLOW_FATE_QUEUE;
11124                         break;
11125                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11126                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11127                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11128                         __atomic_fetch_add(&age_act->refcnt, 1,
11129                                            __ATOMIC_RELAXED);
11130                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11131                         action_flags |= MLX5_FLOW_ACTION_AGE;
11132                         break;
11133                 case RTE_FLOW_ACTION_TYPE_AGE:
11134                         if (priv->sh->flow_hit_aso_en && attr->group) {
11135                                 /*
11136                                  * Create one shared age action, to be used
11137                                  * by all sub-flows.
11138                                  */
11139                                 if (!flow->age) {
11140                                         flow->age =
11141                                                 flow_dv_translate_create_aso_age
11142                                                         (dev, action->conf,
11143                                                          error);
11144                                         if (!flow->age)
11145                                                 return rte_flow_error_set
11146                                                 (error, rte_errno,
11147                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11148                                                  NULL,
11149                                                  "can't create ASO age action");
11150                                 }
11151                                 dev_flow->dv.actions[actions_n++] =
11152                                           (flow_aso_age_get_by_idx
11153                                                 (dev, flow->age))->dr_action;
11154                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11155                                 break;
11156                         }
11157                         /* Fall-through */
11158                 case RTE_FLOW_ACTION_TYPE_COUNT:
11159                         if (!dev_conf->devx) {
11160                                 return rte_flow_error_set
11161                                               (error, ENOTSUP,
11162                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11163                                                NULL,
11164                                                "count action not supported");
11165                         }
11166                         /* Save information first, will apply later. */
11167                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11168                                 count = action->conf;
11169                         else
11170                                 age = action->conf;
11171                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11172                         break;
11173                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11174                         dev_flow->dv.actions[actions_n++] =
11175                                                 priv->sh->pop_vlan_action;
11176                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11177                         break;
11178                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11179                         if (!(action_flags &
11180                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11181                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11182                         vlan.eth_proto = rte_be_to_cpu_16
11183                              ((((const struct rte_flow_action_of_push_vlan *)
11184                                                    actions->conf)->ethertype));
11185                         found_action = mlx5_flow_find_action
11186                                         (actions + 1,
11187                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11188                         if (found_action)
11189                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11190                         found_action = mlx5_flow_find_action
11191                                         (actions + 1,
11192                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11193                         if (found_action)
11194                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11195                         if (flow_dv_create_action_push_vlan
11196                                             (dev, attr, &vlan, dev_flow, error))
11197                                 return -rte_errno;
11198                         dev_flow->dv.actions[actions_n++] =
11199                                         dev_flow->dv.push_vlan_res->action;
11200                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11201                         break;
11202                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11203                         /* of_vlan_push action handled this action */
11204                         MLX5_ASSERT(action_flags &
11205                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11206                         break;
11207                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11208                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11209                                 break;
11210                         flow_dev_get_vlan_info_from_items(items, &vlan);
11211                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11212                         /* If no VLAN push - this is a modify header action */
11213                         if (flow_dv_convert_action_modify_vlan_vid
11214                                                 (mhdr_res, actions, error))
11215                                 return -rte_errno;
11216                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11217                         break;
11218                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11219                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11220                         if (flow_dv_create_action_l2_encap(dev, actions,
11221                                                            dev_flow,
11222                                                            attr->transfer,
11223                                                            error))
11224                                 return -rte_errno;
11225                         dev_flow->dv.actions[actions_n++] =
11226                                         dev_flow->dv.encap_decap->action;
11227                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11228                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11229                                 sample_act->action_flags |=
11230                                                         MLX5_FLOW_ACTION_ENCAP;
11231                         break;
11232                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11233                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11234                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11235                                                            attr->transfer,
11236                                                            error))
11237                                 return -rte_errno;
11238                         dev_flow->dv.actions[actions_n++] =
11239                                         dev_flow->dv.encap_decap->action;
11240                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11241                         break;
11242                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11243                         /* Handle encap with preceding decap. */
11244                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11245                                 if (flow_dv_create_action_raw_encap
11246                                         (dev, actions, dev_flow, attr, error))
11247                                         return -rte_errno;
11248                                 dev_flow->dv.actions[actions_n++] =
11249                                         dev_flow->dv.encap_decap->action;
11250                         } else {
11251                                 /* Handle encap without preceding decap. */
11252                                 if (flow_dv_create_action_l2_encap
11253                                     (dev, actions, dev_flow, attr->transfer,
11254                                      error))
11255                                         return -rte_errno;
11256                                 dev_flow->dv.actions[actions_n++] =
11257                                         dev_flow->dv.encap_decap->action;
11258                         }
11259                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11260                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11261                                 sample_act->action_flags |=
11262                                                         MLX5_FLOW_ACTION_ENCAP;
11263                         break;
11264                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11265                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11266                                 ;
11267                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11268                                 if (flow_dv_create_action_l2_decap
11269                                     (dev, dev_flow, attr->transfer, error))
11270                                         return -rte_errno;
11271                                 dev_flow->dv.actions[actions_n++] =
11272                                         dev_flow->dv.encap_decap->action;
11273                         }
11274                         /* If decap is followed by encap, handle it at encap. */
11275                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11276                         break;
11277                 case RTE_FLOW_ACTION_TYPE_JUMP:
11278                         jump_group = ((const struct rte_flow_action_jump *)
11279                                                         action->conf)->group;
11280                         grp_info.std_tbl_fix = 0;
11281                         if (dev_flow->skip_scale &
11282                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11283                                 grp_info.skip_scale = 1;
11284                         else
11285                                 grp_info.skip_scale = 0;
11286                         ret = mlx5_flow_group_to_table(dev, tunnel,
11287                                                        jump_group,
11288                                                        &table,
11289                                                        &grp_info, error);
11290                         if (ret)
11291                                 return ret;
11292                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11293                                                        attr->transfer,
11294                                                        !!dev_flow->external,
11295                                                        tunnel, jump_group, 0,
11296                                                        error);
11297                         if (!tbl)
11298                                 return rte_flow_error_set
11299                                                 (error, errno,
11300                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11301                                                  NULL,
11302                                                  "cannot create jump action.");
11303                         if (flow_dv_jump_tbl_resource_register
11304                             (dev, tbl, dev_flow, error)) {
11305                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11306                                 return rte_flow_error_set
11307                                                 (error, errno,
11308                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11309                                                  NULL,
11310                                                  "cannot create jump action.");
11311                         }
11312                         dev_flow->dv.actions[actions_n++] =
11313                                         dev_flow->dv.jump->action;
11314                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11315                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11316                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11317                         num_of_dest++;
11318                         break;
11319                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11320                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11321                         if (flow_dv_convert_action_modify_mac
11322                                         (mhdr_res, actions, error))
11323                                 return -rte_errno;
11324                         action_flags |= actions->type ==
11325                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11326                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11327                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11328                         break;
11329                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11330                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11331                         if (flow_dv_convert_action_modify_ipv4
11332                                         (mhdr_res, actions, error))
11333                                 return -rte_errno;
11334                         action_flags |= actions->type ==
11335                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11336                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11337                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11338                         break;
11339                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11340                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11341                         if (flow_dv_convert_action_modify_ipv6
11342                                         (mhdr_res, actions, error))
11343                                 return -rte_errno;
11344                         action_flags |= actions->type ==
11345                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11346                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11347                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11348                         break;
11349                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11350                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11351                         if (flow_dv_convert_action_modify_tp
11352                                         (mhdr_res, actions, items,
11353                                          &flow_attr, dev_flow, !!(action_flags &
11354                                          MLX5_FLOW_ACTION_DECAP), error))
11355                                 return -rte_errno;
11356                         action_flags |= actions->type ==
11357                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11358                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11359                                         MLX5_FLOW_ACTION_SET_TP_DST;
11360                         break;
11361                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11362                         if (flow_dv_convert_action_modify_dec_ttl
11363                                         (mhdr_res, items, &flow_attr, dev_flow,
11364                                          !!(action_flags &
11365                                          MLX5_FLOW_ACTION_DECAP), error))
11366                                 return -rte_errno;
11367                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11368                         break;
11369                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11370                         if (flow_dv_convert_action_modify_ttl
11371                                         (mhdr_res, actions, items, &flow_attr,
11372                                          dev_flow, !!(action_flags &
11373                                          MLX5_FLOW_ACTION_DECAP), error))
11374                                 return -rte_errno;
11375                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11376                         break;
11377                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11378                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11379                         if (flow_dv_convert_action_modify_tcp_seq
11380                                         (mhdr_res, actions, error))
11381                                 return -rte_errno;
11382                         action_flags |= actions->type ==
11383                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11384                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11385                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11386                         break;
11387
11388                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11389                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11390                         if (flow_dv_convert_action_modify_tcp_ack
11391                                         (mhdr_res, actions, error))
11392                                 return -rte_errno;
11393                         action_flags |= actions->type ==
11394                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11395                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11396                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11397                         break;
11398                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11399                         if (flow_dv_convert_action_set_reg
11400                                         (mhdr_res, actions, error))
11401                                 return -rte_errno;
11402                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11403                         break;
11404                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11405                         if (flow_dv_convert_action_copy_mreg
11406                                         (dev, mhdr_res, actions, error))
11407                                 return -rte_errno;
11408                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11409                         break;
11410                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11411                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11412                         dev_flow->handle->fate_action =
11413                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11414                         break;
11415                 case RTE_FLOW_ACTION_TYPE_METER:
11416                         mtr = actions->conf;
11417                         if (!flow->meter) {
11418                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11419                                                             attr, error);
11420                                 if (!fm)
11421                                         return rte_flow_error_set(error,
11422                                                 rte_errno,
11423                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11424                                                 NULL,
11425                                                 "meter not found "
11426                                                 "or invalid parameters");
11427                                 flow->meter = fm->idx;
11428                         }
11429                         /* Set the meter action. */
11430                         if (!fm) {
11431                                 fm = mlx5_ipool_get(priv->sh->ipool
11432                                                 [MLX5_IPOOL_MTR], flow->meter);
11433                                 if (!fm)
11434                                         return rte_flow_error_set(error,
11435                                                 rte_errno,
11436                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11437                                                 NULL,
11438                                                 "meter not found "
11439                                                 "or invalid parameters");
11440                         }
11441                         dev_flow->dv.actions[actions_n++] =
11442                                 fm->mfts->meter_action;
11443                         action_flags |= MLX5_FLOW_ACTION_METER;
11444                         break;
11445                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11446                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11447                                                               actions, error))
11448                                 return -rte_errno;
11449                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11450                         break;
11451                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11452                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11453                                                               actions, error))
11454                                 return -rte_errno;
11455                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11456                         break;
11457                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11458                         sample_act_pos = actions_n;
11459                         sample = (const struct rte_flow_action_sample *)
11460                                  action->conf;
11461                         actions_n++;
11462                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11463                         /* put encap action into group if work with port id */
11464                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11465                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11466                                 sample_act->action_flags |=
11467                                                         MLX5_FLOW_ACTION_ENCAP;
11468                         break;
11469                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11470                         if (flow_dv_convert_action_modify_field
11471                                         (dev, mhdr_res, actions, attr, error))
11472                                 return -rte_errno;
11473                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11474                         break;
11475                 case RTE_FLOW_ACTION_TYPE_END:
11476                         actions_end = true;
11477                         if (mhdr_res->actions_num) {
11478                                 /* create modify action if needed. */
11479                                 if (flow_dv_modify_hdr_resource_register
11480                                         (dev, mhdr_res, dev_flow, error))
11481                                         return -rte_errno;
11482                                 dev_flow->dv.actions[modify_action_position] =
11483                                         handle->dvh.modify_hdr->action;
11484                         }
11485                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11486                                 /*
11487                                  * Create one count action, to be used
11488                                  * by all sub-flows.
11489                                  */
11490                                 if (!flow->counter) {
11491                                         flow->counter =
11492                                                 flow_dv_translate_create_counter
11493                                                         (dev, dev_flow, count,
11494                                                          age);
11495                                         if (!flow->counter)
11496                                                 return rte_flow_error_set
11497                                                 (error, rte_errno,
11498                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11499                                                  NULL, "cannot create counter"
11500                                                  " object.");
11501                                 }
11502                                 dev_flow->dv.actions[actions_n] =
11503                                           (flow_dv_counter_get_by_idx(dev,
11504                                           flow->counter, NULL))->action;
11505                                 actions_n++;
11506                         }
11507                 default:
11508                         break;
11509                 }
11510                 if (mhdr_res->actions_num &&
11511                     modify_action_position == UINT32_MAX)
11512                         modify_action_position = actions_n++;
11513         }
11514         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11515                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11516                 int item_type = items->type;
11517
11518                 if (!mlx5_flow_os_item_supported(item_type))
11519                         return rte_flow_error_set(error, ENOTSUP,
11520                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11521                                                   NULL, "item not supported");
11522                 switch (item_type) {
11523                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11524                         flow_dv_translate_item_port_id
11525                                 (dev, match_mask, match_value, items, attr);
11526                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11527                         break;
11528                 case RTE_FLOW_ITEM_TYPE_ETH:
11529                         flow_dv_translate_item_eth(match_mask, match_value,
11530                                                    items, tunnel,
11531                                                    dev_flow->dv.group);
11532                         matcher.priority = action_flags &
11533                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11534                                         !dev_flow->external ?
11535                                         MLX5_PRIORITY_MAP_L3 :
11536                                         MLX5_PRIORITY_MAP_L2;
11537                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11538                                              MLX5_FLOW_LAYER_OUTER_L2;
11539                         break;
11540                 case RTE_FLOW_ITEM_TYPE_VLAN:
11541                         flow_dv_translate_item_vlan(dev_flow,
11542                                                     match_mask, match_value,
11543                                                     items, tunnel,
11544                                                     dev_flow->dv.group);
11545                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11546                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11547                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11548                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11549                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11550                         break;
11551                 case RTE_FLOW_ITEM_TYPE_IPV4:
11552                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11553                                                   &item_flags, &tunnel);
11554                         flow_dv_translate_item_ipv4(match_mask, match_value,
11555                                                     items, tunnel,
11556                                                     dev_flow->dv.group);
11557                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11558                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11559                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11560                         if (items->mask != NULL &&
11561                             ((const struct rte_flow_item_ipv4 *)
11562                              items->mask)->hdr.next_proto_id) {
11563                                 next_protocol =
11564                                         ((const struct rte_flow_item_ipv4 *)
11565                                          (items->spec))->hdr.next_proto_id;
11566                                 next_protocol &=
11567                                         ((const struct rte_flow_item_ipv4 *)
11568                                          (items->mask))->hdr.next_proto_id;
11569                         } else {
11570                                 /* Reset for inner layer. */
11571                                 next_protocol = 0xff;
11572                         }
11573                         break;
11574                 case RTE_FLOW_ITEM_TYPE_IPV6:
11575                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11576                                                   &item_flags, &tunnel);
11577                         flow_dv_translate_item_ipv6(match_mask, match_value,
11578                                                     items, tunnel,
11579                                                     dev_flow->dv.group);
11580                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11581                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11582                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11583                         if (items->mask != NULL &&
11584                             ((const struct rte_flow_item_ipv6 *)
11585                              items->mask)->hdr.proto) {
11586                                 next_protocol =
11587                                         ((const struct rte_flow_item_ipv6 *)
11588                                          items->spec)->hdr.proto;
11589                                 next_protocol &=
11590                                         ((const struct rte_flow_item_ipv6 *)
11591                                          items->mask)->hdr.proto;
11592                         } else {
11593                                 /* Reset for inner layer. */
11594                                 next_protocol = 0xff;
11595                         }
11596                         break;
11597                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11598                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11599                                                              match_value,
11600                                                              items, tunnel);
11601                         last_item = tunnel ?
11602                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11603                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11604                         if (items->mask != NULL &&
11605                             ((const struct rte_flow_item_ipv6_frag_ext *)
11606                              items->mask)->hdr.next_header) {
11607                                 next_protocol =
11608                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11609                                  items->spec)->hdr.next_header;
11610                                 next_protocol &=
11611                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11612                                  items->mask)->hdr.next_header;
11613                         } else {
11614                                 /* Reset for inner layer. */
11615                                 next_protocol = 0xff;
11616                         }
11617                         break;
11618                 case RTE_FLOW_ITEM_TYPE_TCP:
11619                         flow_dv_translate_item_tcp(match_mask, match_value,
11620                                                    items, tunnel);
11621                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11622                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11623                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11624                         break;
11625                 case RTE_FLOW_ITEM_TYPE_UDP:
11626                         flow_dv_translate_item_udp(match_mask, match_value,
11627                                                    items, tunnel);
11628                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11629                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11630                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11631                         break;
11632                 case RTE_FLOW_ITEM_TYPE_GRE:
11633                         flow_dv_translate_item_gre(match_mask, match_value,
11634                                                    items, tunnel);
11635                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11636                         last_item = MLX5_FLOW_LAYER_GRE;
11637                         break;
11638                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11639                         flow_dv_translate_item_gre_key(match_mask,
11640                                                        match_value, items);
11641                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11642                         break;
11643                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11644                         flow_dv_translate_item_nvgre(match_mask, match_value,
11645                                                      items, tunnel);
11646                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11647                         last_item = MLX5_FLOW_LAYER_GRE;
11648                         break;
11649                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11650                         flow_dv_translate_item_vxlan(match_mask, match_value,
11651                                                      items, tunnel);
11652                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11653                         last_item = MLX5_FLOW_LAYER_VXLAN;
11654                         break;
11655                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11656                         flow_dv_translate_item_vxlan_gpe(match_mask,
11657                                                          match_value, items,
11658                                                          tunnel);
11659                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11660                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11661                         break;
11662                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11663                         flow_dv_translate_item_geneve(match_mask, match_value,
11664                                                       items, tunnel);
11665                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11666                         last_item = MLX5_FLOW_LAYER_GENEVE;
11667                         break;
11668                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11669                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11670                                                           match_value,
11671                                                           items, error);
11672                         if (ret)
11673                                 return rte_flow_error_set(error, -ret,
11674                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11675                                         "cannot create GENEVE TLV option");
11676                         flow->geneve_tlv_option = 1;
11677                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11678                         break;
11679                 case RTE_FLOW_ITEM_TYPE_MPLS:
11680                         flow_dv_translate_item_mpls(match_mask, match_value,
11681                                                     items, last_item, tunnel);
11682                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11683                         last_item = MLX5_FLOW_LAYER_MPLS;
11684                         break;
11685                 case RTE_FLOW_ITEM_TYPE_MARK:
11686                         flow_dv_translate_item_mark(dev, match_mask,
11687                                                     match_value, items);
11688                         last_item = MLX5_FLOW_ITEM_MARK;
11689                         break;
11690                 case RTE_FLOW_ITEM_TYPE_META:
11691                         flow_dv_translate_item_meta(dev, match_mask,
11692                                                     match_value, attr, items);
11693                         last_item = MLX5_FLOW_ITEM_METADATA;
11694                         break;
11695                 case RTE_FLOW_ITEM_TYPE_ICMP:
11696                         flow_dv_translate_item_icmp(match_mask, match_value,
11697                                                     items, tunnel);
11698                         last_item = MLX5_FLOW_LAYER_ICMP;
11699                         break;
11700                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11701                         flow_dv_translate_item_icmp6(match_mask, match_value,
11702                                                       items, tunnel);
11703                         last_item = MLX5_FLOW_LAYER_ICMP6;
11704                         break;
11705                 case RTE_FLOW_ITEM_TYPE_TAG:
11706                         flow_dv_translate_item_tag(dev, match_mask,
11707                                                    match_value, items);
11708                         last_item = MLX5_FLOW_ITEM_TAG;
11709                         break;
11710                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11711                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11712                                                         match_value, items);
11713                         last_item = MLX5_FLOW_ITEM_TAG;
11714                         break;
11715                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11716                         flow_dv_translate_item_tx_queue(dev, match_mask,
11717                                                         match_value,
11718                                                         items);
11719                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11720                         break;
11721                 case RTE_FLOW_ITEM_TYPE_GTP:
11722                         flow_dv_translate_item_gtp(match_mask, match_value,
11723                                                    items, tunnel);
11724                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11725                         last_item = MLX5_FLOW_LAYER_GTP;
11726                         break;
11727                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11728                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11729                                                           match_value,
11730                                                           items);
11731                         if (ret)
11732                                 return rte_flow_error_set(error, -ret,
11733                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11734                                         "cannot create GTP PSC item");
11735                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11736                         break;
11737                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11738                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11739                                 /* Create it only the first time to be used. */
11740                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11741                                 if (ret)
11742                                         return rte_flow_error_set
11743                                                 (error, -ret,
11744                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11745                                                 NULL,
11746                                                 "cannot create eCPRI parser");
11747                         }
11748                         /* Adjust the length matcher and device flow value. */
11749                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11750                         dev_flow->dv.value.size =
11751                                         MLX5_ST_SZ_BYTES(fte_match_param);
11752                         flow_dv_translate_item_ecpri(dev, match_mask,
11753                                                      match_value, items);
11754                         /* No other protocol should follow eCPRI layer. */
11755                         last_item = MLX5_FLOW_LAYER_ECPRI;
11756                         break;
11757                 default:
11758                         break;
11759                 }
11760                 item_flags |= last_item;
11761         }
11762         /*
11763          * When E-Switch mode is enabled, we have two cases where we need to
11764          * set the source port manually.
11765          * The first one, is in case of Nic steering rule, and the second is
11766          * E-Switch rule where no port_id item was found. In both cases
11767          * the source port is set according the current port in use.
11768          */
11769         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11770             (priv->representor || priv->master)) {
11771                 if (flow_dv_translate_item_port_id(dev, match_mask,
11772                                                    match_value, NULL, attr))
11773                         return -rte_errno;
11774         }
11775 #ifdef RTE_LIBRTE_MLX5_DEBUG
11776         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11777                                               dev_flow->dv.value.buf));
11778 #endif
11779         /*
11780          * Layers may be already initialized from prefix flow if this dev_flow
11781          * is the suffix flow.
11782          */
11783         handle->layers |= item_flags;
11784         if (action_flags & MLX5_FLOW_ACTION_RSS)
11785                 flow_dv_hashfields_set(dev_flow, rss_desc);
11786         /* If has RSS action in the sample action, the Sample/Mirror resource
11787          * should be registered after the hash filed be update.
11788          */
11789         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11790                 ret = flow_dv_translate_action_sample(dev,
11791                                                       sample,
11792                                                       dev_flow, attr,
11793                                                       &num_of_dest,
11794                                                       sample_actions,
11795                                                       &sample_res,
11796                                                       error);
11797                 if (ret < 0)
11798                         return ret;
11799                 ret = flow_dv_create_action_sample(dev,
11800                                                    dev_flow,
11801                                                    num_of_dest,
11802                                                    &sample_res,
11803                                                    &mdest_res,
11804                                                    sample_actions,
11805                                                    action_flags,
11806                                                    error);
11807                 if (ret < 0)
11808                         return rte_flow_error_set
11809                                                 (error, rte_errno,
11810                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11811                                                 NULL,
11812                                                 "cannot create sample action");
11813                 if (num_of_dest > 1) {
11814                         dev_flow->dv.actions[sample_act_pos] =
11815                         dev_flow->dv.dest_array_res->action;
11816                 } else {
11817                         dev_flow->dv.actions[sample_act_pos] =
11818                         dev_flow->dv.sample_res->verbs_action;
11819                 }
11820         }
11821         /*
11822          * For multiple destination (sample action with ratio=1), the encap
11823          * action and port id action will be combined into group action.
11824          * So need remove the original these actions in the flow and only
11825          * use the sample action instead of.
11826          */
11827         if (num_of_dest > 1 &&
11828             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11829                 int i;
11830                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11831
11832                 for (i = 0; i < actions_n; i++) {
11833                         if ((sample_act->dr_encap_action &&
11834                                 sample_act->dr_encap_action ==
11835                                 dev_flow->dv.actions[i]) ||
11836                                 (sample_act->dr_port_id_action &&
11837                                 sample_act->dr_port_id_action ==
11838                                 dev_flow->dv.actions[i]) ||
11839                                 (sample_act->dr_jump_action &&
11840                                 sample_act->dr_jump_action ==
11841                                 dev_flow->dv.actions[i]))
11842                                 continue;
11843                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11844                 }
11845                 memcpy((void *)dev_flow->dv.actions,
11846                                 (void *)temp_actions,
11847                                 tmp_actions_n * sizeof(void *));
11848                 actions_n = tmp_actions_n;
11849         }
11850         dev_flow->dv.actions_n = actions_n;
11851         dev_flow->act_flags = action_flags;
11852         /* Register matcher. */
11853         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11854                                     matcher.mask.size);
11855         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11856                                         matcher.priority);
11857         /* reserved field no needs to be set to 0 here. */
11858         tbl_key.domain = attr->transfer;
11859         tbl_key.direction = attr->egress;
11860         tbl_key.table_id = dev_flow->dv.group;
11861         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11862                                      tunnel, attr->group, error))
11863                 return -rte_errno;
11864         return 0;
11865 }
11866
11867 /**
11868  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11869  * and tunnel.
11870  *
11871  * @param[in, out] action
11872  *   Shred RSS action holding hash RX queue objects.
11873  * @param[in] hash_fields
11874  *   Defines combination of packet fields to participate in RX hash.
11875  * @param[in] tunnel
11876  *   Tunnel type
11877  * @param[in] hrxq_idx
11878  *   Hash RX queue index to set.
11879  *
11880  * @return
11881  *   0 on success, otherwise negative errno value.
11882  */
11883 static int
11884 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11885                               const uint64_t hash_fields,
11886                               uint32_t hrxq_idx)
11887 {
11888         uint32_t *hrxqs = action->hrxq;
11889
11890         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11891         case MLX5_RSS_HASH_IPV4:
11892                 /* fall-through. */
11893         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11894                 /* fall-through. */
11895         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11896                 hrxqs[0] = hrxq_idx;
11897                 return 0;
11898         case MLX5_RSS_HASH_IPV4_TCP:
11899                 /* fall-through. */
11900         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11901                 /* fall-through. */
11902         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11903                 hrxqs[1] = hrxq_idx;
11904                 return 0;
11905         case MLX5_RSS_HASH_IPV4_UDP:
11906                 /* fall-through. */
11907         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11908                 /* fall-through. */
11909         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11910                 hrxqs[2] = hrxq_idx;
11911                 return 0;
11912         case MLX5_RSS_HASH_IPV6:
11913                 /* fall-through. */
11914         case MLX5_RSS_HASH_IPV6_DST_ONLY:
11915                 /* fall-through. */
11916         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11917                 hrxqs[3] = hrxq_idx;
11918                 return 0;
11919         case MLX5_RSS_HASH_IPV6_TCP:
11920                 /* fall-through. */
11921         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11922                 /* fall-through. */
11923         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11924                 hrxqs[4] = hrxq_idx;
11925                 return 0;
11926         case MLX5_RSS_HASH_IPV6_UDP:
11927                 /* fall-through. */
11928         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
11929                 /* fall-through. */
11930         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
11931                 hrxqs[5] = hrxq_idx;
11932                 return 0;
11933         case MLX5_RSS_HASH_NONE:
11934                 hrxqs[6] = hrxq_idx;
11935                 return 0;
11936         default:
11937                 return -1;
11938         }
11939 }
11940
11941 /**
11942  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11943  * and tunnel.
11944  *
11945  * @param[in] dev
11946  *   Pointer to the Ethernet device structure.
11947  * @param[in] idx
11948  *   Shared RSS action ID holding hash RX queue objects.
11949  * @param[in] hash_fields
11950  *   Defines combination of packet fields to participate in RX hash.
11951  * @param[in] tunnel
11952  *   Tunnel type
11953  *
11954  * @return
11955  *   Valid hash RX queue index, otherwise 0.
11956  */
11957 static uint32_t
11958 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11959                                  const uint64_t hash_fields)
11960 {
11961         struct mlx5_priv *priv = dev->data->dev_private;
11962         struct mlx5_shared_action_rss *shared_rss =
11963             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11964         const uint32_t *hrxqs = shared_rss->hrxq;
11965
11966         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11967         case MLX5_RSS_HASH_IPV4:
11968                 /* fall-through. */
11969         case MLX5_RSS_HASH_IPV4_DST_ONLY:
11970                 /* fall-through. */
11971         case MLX5_RSS_HASH_IPV4_SRC_ONLY:
11972                 return hrxqs[0];
11973         case MLX5_RSS_HASH_IPV4_TCP:
11974                 /* fall-through. */
11975         case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
11976                 /* fall-through. */
11977         case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
11978                 return hrxqs[1];
11979         case MLX5_RSS_HASH_IPV4_UDP:
11980                 /* fall-through. */
11981         case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
11982                 /* fall-through. */
11983         case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
11984                 return hrxqs[2];
11985         case MLX5_RSS_HASH_IPV6:
11986                 /* fall-through. */
11987         case MLX5_RSS_HASH_IPV6_DST_ONLY:
11988                 /* fall-through. */
11989         case MLX5_RSS_HASH_IPV6_SRC_ONLY:
11990                 return hrxqs[3];
11991         case MLX5_RSS_HASH_IPV6_TCP:
11992                 /* fall-through. */
11993         case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
11994                 /* fall-through. */
11995         case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
11996                 return hrxqs[4];
11997         case MLX5_RSS_HASH_IPV6_UDP:
11998                 /* fall-through. */
11999         case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
12000                 /* fall-through. */
12001         case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
12002                 return hrxqs[5];
12003         case MLX5_RSS_HASH_NONE:
12004                 return hrxqs[6];
12005         default:
12006                 return 0;
12007         }
12008
12009 }
12010
12011 /**
12012  * Apply the flow to the NIC, lock free,
12013  * (mutex should be acquired by caller).
12014  *
12015  * @param[in] dev
12016  *   Pointer to the Ethernet device structure.
12017  * @param[in, out] flow
12018  *   Pointer to flow structure.
12019  * @param[out] error
12020  *   Pointer to error structure.
12021  *
12022  * @return
12023  *   0 on success, a negative errno value otherwise and rte_errno is set.
12024  */
12025 static int
12026 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
12027               struct rte_flow_error *error)
12028 {
12029         struct mlx5_flow_dv_workspace *dv;
12030         struct mlx5_flow_handle *dh;
12031         struct mlx5_flow_handle_dv *dv_h;
12032         struct mlx5_flow *dev_flow;
12033         struct mlx5_priv *priv = dev->data->dev_private;
12034         uint32_t handle_idx;
12035         int n;
12036         int err;
12037         int idx;
12038         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12039         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
12040
12041         MLX5_ASSERT(wks);
12042         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
12043                 dev_flow = &wks->flows[idx];
12044                 dv = &dev_flow->dv;
12045                 dh = dev_flow->handle;
12046                 dv_h = &dh->dvh;
12047                 n = dv->actions_n;
12048                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
12049                         if (dv->transfer) {
12050                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12051                                 dv->actions[n++] = priv->sh->dr_drop_action;
12052                         } else {
12053 #ifdef HAVE_MLX5DV_DR
12054                                 /* DR supports drop action placeholder. */
12055                                 MLX5_ASSERT(priv->sh->dr_drop_action);
12056                                 dv->actions[n++] = priv->sh->dr_drop_action;
12057 #else
12058                                 /* For DV we use the explicit drop queue. */
12059                                 MLX5_ASSERT(priv->drop_queue.hrxq);
12060                                 dv->actions[n++] =
12061                                                 priv->drop_queue.hrxq->action;
12062 #endif
12063                         }
12064                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12065                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12066                         struct mlx5_hrxq *hrxq;
12067                         uint32_t hrxq_idx;
12068
12069                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12070                                                     &hrxq_idx);
12071                         if (!hrxq) {
12072                                 rte_flow_error_set
12073                                         (error, rte_errno,
12074                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12075                                          "cannot get hash queue");
12076                                 goto error;
12077                         }
12078                         dh->rix_hrxq = hrxq_idx;
12079                         dv->actions[n++] = hrxq->action;
12080                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12081                         struct mlx5_hrxq *hrxq = NULL;
12082                         uint32_t hrxq_idx;
12083
12084                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12085                                                 rss_desc->shared_rss,
12086                                                 dev_flow->hash_fields);
12087                         if (hrxq_idx)
12088                                 hrxq = mlx5_ipool_get
12089                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12090                                          hrxq_idx);
12091                         if (!hrxq) {
12092                                 rte_flow_error_set
12093                                         (error, rte_errno,
12094                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12095                                          "cannot get hash queue");
12096                                 goto error;
12097                         }
12098                         dh->rix_srss = rss_desc->shared_rss;
12099                         dv->actions[n++] = hrxq->action;
12100                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12101                         if (!priv->sh->default_miss_action) {
12102                                 rte_flow_error_set
12103                                         (error, rte_errno,
12104                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12105                                          "default miss action not be created.");
12106                                 goto error;
12107                         }
12108                         dv->actions[n++] = priv->sh->default_miss_action;
12109                 }
12110                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12111                                                (void *)&dv->value, n,
12112                                                dv->actions, &dh->drv_flow);
12113                 if (err) {
12114                         rte_flow_error_set(error, errno,
12115                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12116                                            NULL,
12117                                            "hardware refuses to create flow");
12118                         goto error;
12119                 }
12120                 if (priv->vmwa_context &&
12121                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12122                         /*
12123                          * The rule contains the VLAN pattern.
12124                          * For VF we are going to create VLAN
12125                          * interface to make hypervisor set correct
12126                          * e-Switch vport context.
12127                          */
12128                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12129                 }
12130         }
12131         return 0;
12132 error:
12133         err = rte_errno; /* Save rte_errno before cleanup. */
12134         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12135                        handle_idx, dh, next) {
12136                 /* hrxq is union, don't clear it if the flag is not set. */
12137                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12138                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12139                         dh->rix_hrxq = 0;
12140                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12141                         dh->rix_srss = 0;
12142                 }
12143                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12144                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12145         }
12146         rte_errno = err; /* Restore rte_errno. */
12147         return -rte_errno;
12148 }
12149
12150 void
12151 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12152                           struct mlx5_cache_entry *entry)
12153 {
12154         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12155                                                           entry);
12156
12157         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12158         mlx5_free(cache);
12159 }
12160
12161 /**
12162  * Release the flow matcher.
12163  *
12164  * @param dev
12165  *   Pointer to Ethernet device.
12166  * @param port_id
12167  *   Index to port ID action resource.
12168  *
12169  * @return
12170  *   1 while a reference on it exists, 0 when freed.
12171  */
12172 static int
12173 flow_dv_matcher_release(struct rte_eth_dev *dev,
12174                         struct mlx5_flow_handle *handle)
12175 {
12176         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12177         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12178                                                             typeof(*tbl), tbl);
12179         int ret;
12180
12181         MLX5_ASSERT(matcher->matcher_object);
12182         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12183         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12184         return ret;
12185 }
12186
12187 /**
12188  * Release encap_decap resource.
12189  *
12190  * @param list
12191  *   Pointer to the hash list.
12192  * @param entry
12193  *   Pointer to exist resource entry object.
12194  */
12195 void
12196 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12197                               struct mlx5_hlist_entry *entry)
12198 {
12199         struct mlx5_dev_ctx_shared *sh = list->ctx;
12200         struct mlx5_flow_dv_encap_decap_resource *res =
12201                 container_of(entry, typeof(*res), entry);
12202
12203         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12204         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12205 }
12206
12207 /**
12208  * Release an encap/decap resource.
12209  *
12210  * @param dev
12211  *   Pointer to Ethernet device.
12212  * @param encap_decap_idx
12213  *   Index of encap decap resource.
12214  *
12215  * @return
12216  *   1 while a reference on it exists, 0 when freed.
12217  */
12218 static int
12219 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12220                                      uint32_t encap_decap_idx)
12221 {
12222         struct mlx5_priv *priv = dev->data->dev_private;
12223         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12224
12225         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12226                                         encap_decap_idx);
12227         if (!cache_resource)
12228                 return 0;
12229         MLX5_ASSERT(cache_resource->action);
12230         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12231                                      &cache_resource->entry);
12232 }
12233
12234 /**
12235  * Release an jump to table action resource.
12236  *
12237  * @param dev
12238  *   Pointer to Ethernet device.
12239  * @param rix_jump
12240  *   Index to the jump action resource.
12241  *
12242  * @return
12243  *   1 while a reference on it exists, 0 when freed.
12244  */
12245 static int
12246 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12247                                   uint32_t rix_jump)
12248 {
12249         struct mlx5_priv *priv = dev->data->dev_private;
12250         struct mlx5_flow_tbl_data_entry *tbl_data;
12251
12252         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12253                                   rix_jump);
12254         if (!tbl_data)
12255                 return 0;
12256         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12257 }
12258
12259 void
12260 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12261                          struct mlx5_hlist_entry *entry)
12262 {
12263         struct mlx5_flow_dv_modify_hdr_resource *res =
12264                 container_of(entry, typeof(*res), entry);
12265
12266         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12267         mlx5_free(entry);
12268 }
12269
12270 /**
12271  * Release a modify-header resource.
12272  *
12273  * @param dev
12274  *   Pointer to Ethernet device.
12275  * @param handle
12276  *   Pointer to mlx5_flow_handle.
12277  *
12278  * @return
12279  *   1 while a reference on it exists, 0 when freed.
12280  */
12281 static int
12282 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12283                                     struct mlx5_flow_handle *handle)
12284 {
12285         struct mlx5_priv *priv = dev->data->dev_private;
12286         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12287
12288         MLX5_ASSERT(entry->action);
12289         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12290 }
12291
12292 void
12293 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12294                           struct mlx5_cache_entry *entry)
12295 {
12296         struct mlx5_dev_ctx_shared *sh = list->ctx;
12297         struct mlx5_flow_dv_port_id_action_resource *cache =
12298                         container_of(entry, typeof(*cache), entry);
12299
12300         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12301         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12302 }
12303
12304 /**
12305  * Release port ID action resource.
12306  *
12307  * @param dev
12308  *   Pointer to Ethernet device.
12309  * @param handle
12310  *   Pointer to mlx5_flow_handle.
12311  *
12312  * @return
12313  *   1 while a reference on it exists, 0 when freed.
12314  */
12315 static int
12316 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12317                                         uint32_t port_id)
12318 {
12319         struct mlx5_priv *priv = dev->data->dev_private;
12320         struct mlx5_flow_dv_port_id_action_resource *cache;
12321
12322         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12323         if (!cache)
12324                 return 0;
12325         MLX5_ASSERT(cache->action);
12326         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12327                                      &cache->entry);
12328 }
12329
12330 /**
12331  * Release shared RSS action resource.
12332  *
12333  * @param dev
12334  *   Pointer to Ethernet device.
12335  * @param srss
12336  *   Shared RSS action index.
12337  */
12338 static void
12339 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12340 {
12341         struct mlx5_priv *priv = dev->data->dev_private;
12342         struct mlx5_shared_action_rss *shared_rss;
12343
12344         shared_rss = mlx5_ipool_get
12345                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12346         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12347 }
12348
12349 void
12350 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12351                             struct mlx5_cache_entry *entry)
12352 {
12353         struct mlx5_dev_ctx_shared *sh = list->ctx;
12354         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12355                         container_of(entry, typeof(*cache), entry);
12356
12357         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12358         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12359 }
12360
12361 /**
12362  * Release push vlan action resource.
12363  *
12364  * @param dev
12365  *   Pointer to Ethernet device.
12366  * @param handle
12367  *   Pointer to mlx5_flow_handle.
12368  *
12369  * @return
12370  *   1 while a reference on it exists, 0 when freed.
12371  */
12372 static int
12373 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12374                                           struct mlx5_flow_handle *handle)
12375 {
12376         struct mlx5_priv *priv = dev->data->dev_private;
12377         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12378         uint32_t idx = handle->dvh.rix_push_vlan;
12379
12380         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12381         if (!cache)
12382                 return 0;
12383         MLX5_ASSERT(cache->action);
12384         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12385                                      &cache->entry);
12386 }
12387
12388 /**
12389  * Release the fate resource.
12390  *
12391  * @param dev
12392  *   Pointer to Ethernet device.
12393  * @param handle
12394  *   Pointer to mlx5_flow_handle.
12395  */
12396 static void
12397 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12398                                struct mlx5_flow_handle *handle)
12399 {
12400         if (!handle->rix_fate)
12401                 return;
12402         switch (handle->fate_action) {
12403         case MLX5_FLOW_FATE_QUEUE:
12404                 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
12405                         mlx5_hrxq_release(dev, handle->rix_hrxq);
12406                 break;
12407         case MLX5_FLOW_FATE_JUMP:
12408                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12409                 break;
12410         case MLX5_FLOW_FATE_PORT_ID:
12411                 flow_dv_port_id_action_resource_release(dev,
12412                                 handle->rix_port_id_action);
12413                 break;
12414         default:
12415                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12416                 break;
12417         }
12418         handle->rix_fate = 0;
12419 }
12420
12421 void
12422 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12423                          struct mlx5_cache_entry *entry)
12424 {
12425         struct mlx5_flow_dv_sample_resource *cache_resource =
12426                         container_of(entry, typeof(*cache_resource), entry);
12427         struct rte_eth_dev *dev = cache_resource->dev;
12428         struct mlx5_priv *priv = dev->data->dev_private;
12429
12430         if (cache_resource->verbs_action)
12431                 claim_zero(mlx5_flow_os_destroy_flow_action
12432                                 (cache_resource->verbs_action));
12433         if (cache_resource->normal_path_tbl)
12434                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12435                         cache_resource->normal_path_tbl);
12436         flow_dv_sample_sub_actions_release(dev,
12437                                 &cache_resource->sample_idx);
12438         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12439                         cache_resource->idx);
12440         DRV_LOG(DEBUG, "sample resource %p: removed",
12441                 (void *)cache_resource);
12442 }
12443
12444 /**
12445  * Release an sample resource.
12446  *
12447  * @param dev
12448  *   Pointer to Ethernet device.
12449  * @param handle
12450  *   Pointer to mlx5_flow_handle.
12451  *
12452  * @return
12453  *   1 while a reference on it exists, 0 when freed.
12454  */
12455 static int
12456 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12457                                      struct mlx5_flow_handle *handle)
12458 {
12459         struct mlx5_priv *priv = dev->data->dev_private;
12460         struct mlx5_flow_dv_sample_resource *cache_resource;
12461
12462         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12463                          handle->dvh.rix_sample);
12464         if (!cache_resource)
12465                 return 0;
12466         MLX5_ASSERT(cache_resource->verbs_action);
12467         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12468                                      &cache_resource->entry);
12469 }
12470
12471 void
12472 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12473                              struct mlx5_cache_entry *entry)
12474 {
12475         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12476                         container_of(entry, typeof(*cache_resource), entry);
12477         struct rte_eth_dev *dev = cache_resource->dev;
12478         struct mlx5_priv *priv = dev->data->dev_private;
12479         uint32_t i = 0;
12480
12481         MLX5_ASSERT(cache_resource->action);
12482         if (cache_resource->action)
12483                 claim_zero(mlx5_flow_os_destroy_flow_action
12484                                         (cache_resource->action));
12485         for (; i < cache_resource->num_of_dest; i++)
12486                 flow_dv_sample_sub_actions_release(dev,
12487                                 &cache_resource->sample_idx[i]);
12488         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12489                         cache_resource->idx);
12490         DRV_LOG(DEBUG, "destination array resource %p: removed",
12491                 (void *)cache_resource);
12492 }
12493
12494 /**
12495  * Release an destination array resource.
12496  *
12497  * @param dev
12498  *   Pointer to Ethernet device.
12499  * @param handle
12500  *   Pointer to mlx5_flow_handle.
12501  *
12502  * @return
12503  *   1 while a reference on it exists, 0 when freed.
12504  */
12505 static int
12506 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12507                                     struct mlx5_flow_handle *handle)
12508 {
12509         struct mlx5_priv *priv = dev->data->dev_private;
12510         struct mlx5_flow_dv_dest_array_resource *cache;
12511
12512         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12513                                handle->dvh.rix_dest_array);
12514         if (!cache)
12515                 return 0;
12516         MLX5_ASSERT(cache->action);
12517         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12518                                      &cache->entry);
12519 }
12520
12521 static void
12522 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12523 {
12524         struct mlx5_priv *priv = dev->data->dev_private;
12525         struct mlx5_dev_ctx_shared *sh = priv->sh;
12526         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12527                                 sh->geneve_tlv_option_resource;
12528         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12529         if (geneve_opt_resource) {
12530                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12531                                          __ATOMIC_RELAXED))) {
12532                         claim_zero(mlx5_devx_cmd_destroy
12533                                         (geneve_opt_resource->obj));
12534                         mlx5_free(sh->geneve_tlv_option_resource);
12535                         sh->geneve_tlv_option_resource = NULL;
12536                 }
12537         }
12538         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12539 }
12540
12541 /**
12542  * Remove the flow from the NIC but keeps it in memory.
12543  * Lock free, (mutex should be acquired by caller).
12544  *
12545  * @param[in] dev
12546  *   Pointer to Ethernet device.
12547  * @param[in, out] flow
12548  *   Pointer to flow structure.
12549  */
12550 static void
12551 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12552 {
12553         struct mlx5_flow_handle *dh;
12554         uint32_t handle_idx;
12555         struct mlx5_priv *priv = dev->data->dev_private;
12556
12557         if (!flow)
12558                 return;
12559         handle_idx = flow->dev_handles;
12560         while (handle_idx) {
12561                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12562                                     handle_idx);
12563                 if (!dh)
12564                         return;
12565                 if (dh->drv_flow) {
12566                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12567                         dh->drv_flow = NULL;
12568                 }
12569                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12570                         flow_dv_fate_resource_release(dev, dh);
12571                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12572                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12573                 handle_idx = dh->next.next;
12574         }
12575 }
12576
12577 /**
12578  * Remove the flow from the NIC and the memory.
12579  * Lock free, (mutex should be acquired by caller).
12580  *
12581  * @param[in] dev
12582  *   Pointer to the Ethernet device structure.
12583  * @param[in, out] flow
12584  *   Pointer to flow structure.
12585  */
12586 static void
12587 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12588 {
12589         struct mlx5_flow_handle *dev_handle;
12590         struct mlx5_priv *priv = dev->data->dev_private;
12591         uint32_t srss = 0;
12592
12593         if (!flow)
12594                 return;
12595         flow_dv_remove(dev, flow);
12596         if (flow->counter) {
12597                 flow_dv_counter_free(dev, flow->counter);
12598                 flow->counter = 0;
12599         }
12600         if (flow->meter) {
12601                 struct mlx5_flow_meter *fm;
12602
12603                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12604                                     flow->meter);
12605                 if (fm)
12606                         mlx5_flow_meter_detach(fm);
12607                 flow->meter = 0;
12608         }
12609         if (flow->age)
12610                 flow_dv_aso_age_release(dev, flow->age);
12611         if (flow->geneve_tlv_option) {
12612                 flow_dv_geneve_tlv_option_resource_release(dev);
12613                 flow->geneve_tlv_option = 0;
12614         }
12615         while (flow->dev_handles) {
12616                 uint32_t tmp_idx = flow->dev_handles;
12617
12618                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12619                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12620                 if (!dev_handle)
12621                         return;
12622                 flow->dev_handles = dev_handle->next.next;
12623                 if (dev_handle->dvh.matcher)
12624                         flow_dv_matcher_release(dev, dev_handle);
12625                 if (dev_handle->dvh.rix_sample)
12626                         flow_dv_sample_resource_release(dev, dev_handle);
12627                 if (dev_handle->dvh.rix_dest_array)
12628                         flow_dv_dest_array_resource_release(dev, dev_handle);
12629                 if (dev_handle->dvh.rix_encap_decap)
12630                         flow_dv_encap_decap_resource_release(dev,
12631                                 dev_handle->dvh.rix_encap_decap);
12632                 if (dev_handle->dvh.modify_hdr)
12633                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12634                 if (dev_handle->dvh.rix_push_vlan)
12635                         flow_dv_push_vlan_action_resource_release(dev,
12636                                                                   dev_handle);
12637                 if (dev_handle->dvh.rix_tag)
12638                         flow_dv_tag_release(dev,
12639                                             dev_handle->dvh.rix_tag);
12640                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12641                         flow_dv_fate_resource_release(dev, dev_handle);
12642                 else if (!srss)
12643                         srss = dev_handle->rix_srss;
12644                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12645                            tmp_idx);
12646         }
12647         if (srss)
12648                 flow_dv_shared_rss_action_release(dev, srss);
12649 }
12650
12651 /**
12652  * Release array of hash RX queue objects.
12653  * Helper function.
12654  *
12655  * @param[in] dev
12656  *   Pointer to the Ethernet device structure.
12657  * @param[in, out] hrxqs
12658  *   Array of hash RX queue objects.
12659  *
12660  * @return
12661  *   Total number of references to hash RX queue objects in *hrxqs* array
12662  *   after this operation.
12663  */
12664 static int
12665 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12666                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12667 {
12668         size_t i;
12669         int remaining = 0;
12670
12671         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12672                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12673
12674                 if (!ret)
12675                         (*hrxqs)[i] = 0;
12676                 remaining += ret;
12677         }
12678         return remaining;
12679 }
12680
12681 /**
12682  * Release all hash RX queue objects representing shared RSS action.
12683  *
12684  * @param[in] dev
12685  *   Pointer to the Ethernet device structure.
12686  * @param[in, out] action
12687  *   Shared RSS action to remove hash RX queue objects from.
12688  *
12689  * @return
12690  *   Total number of references to hash RX queue objects stored in *action*
12691  *   after this operation.
12692  *   Expected to be 0 if no external references held.
12693  */
12694 static int
12695 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12696                                  struct mlx5_shared_action_rss *shared_rss)
12697 {
12698         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
12699 }
12700
12701 /**
12702  * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
12703  * user input.
12704  *
12705  * Only one hash value is available for one L3+L4 combination:
12706  * for example:
12707  * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
12708  * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
12709  * same slot in mlx5_rss_hash_fields.
12710  *
12711  * @param[in] rss
12712  *   Pointer to the shared action RSS conf.
12713  * @param[in, out] hash_field
12714  *   hash_field variable needed to be adjusted.
12715  *
12716  * @return
12717  *   void
12718  */
12719 static void
12720 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
12721                                      uint64_t *hash_field)
12722 {
12723         uint64_t rss_types = rss->origin.types;
12724
12725         switch (*hash_field & ~IBV_RX_HASH_INNER) {
12726         case MLX5_RSS_HASH_IPV4:
12727                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
12728                         *hash_field &= ~MLX5_RSS_HASH_IPV4;
12729                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12730                                 *hash_field |= IBV_RX_HASH_DST_IPV4;
12731                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12732                                 *hash_field |= IBV_RX_HASH_SRC_IPV4;
12733                         else
12734                                 *hash_field |= MLX5_RSS_HASH_IPV4;
12735                 }
12736                 return;
12737         case MLX5_RSS_HASH_IPV6:
12738                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
12739                         *hash_field &= ~MLX5_RSS_HASH_IPV6;
12740                         if (rss_types & ETH_RSS_L3_DST_ONLY)
12741                                 *hash_field |= IBV_RX_HASH_DST_IPV6;
12742                         else if (rss_types & ETH_RSS_L3_SRC_ONLY)
12743                                 *hash_field |= IBV_RX_HASH_SRC_IPV6;
12744                         else
12745                                 *hash_field |= MLX5_RSS_HASH_IPV6;
12746                 }
12747                 return;
12748         case MLX5_RSS_HASH_IPV4_UDP:
12749                 /* fall-through. */
12750         case MLX5_RSS_HASH_IPV6_UDP:
12751                 if (rss_types & ETH_RSS_UDP) {
12752                         *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
12753                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12754                                 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
12755                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12756                                 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
12757                         else
12758                                 *hash_field |= MLX5_UDP_IBV_RX_HASH;
12759                 }
12760                 return;
12761         case MLX5_RSS_HASH_IPV4_TCP:
12762                 /* fall-through. */
12763         case MLX5_RSS_HASH_IPV6_TCP:
12764                 if (rss_types & ETH_RSS_TCP) {
12765                         *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
12766                         if (rss_types & ETH_RSS_L4_DST_ONLY)
12767                                 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
12768                         else if (rss_types & ETH_RSS_L4_SRC_ONLY)
12769                                 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
12770                         else
12771                                 *hash_field |= MLX5_TCP_IBV_RX_HASH;
12772                 }
12773                 return;
12774         default:
12775                 return;
12776         }
12777 }
12778
12779 /**
12780  * Setup shared RSS action.
12781  * Prepare set of hash RX queue objects sufficient to handle all valid
12782  * hash_fields combinations (see enum ibv_rx_hash_fields).
12783  *
12784  * @param[in] dev
12785  *   Pointer to the Ethernet device structure.
12786  * @param[in] action_idx
12787  *   Shared RSS action ipool index.
12788  * @param[in, out] action
12789  *   Partially initialized shared RSS action.
12790  * @param[out] error
12791  *   Perform verbose error reporting if not NULL. Initialized in case of
12792  *   error only.
12793  *
12794  * @return
12795  *   0 on success, otherwise negative errno value.
12796  */
12797 static int
12798 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12799                            uint32_t action_idx,
12800                            struct mlx5_shared_action_rss *shared_rss,
12801                            struct rte_flow_error *error)
12802 {
12803         struct mlx5_flow_rss_desc rss_desc = { 0 };
12804         size_t i;
12805         int err;
12806
12807         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12808                 return rte_flow_error_set(error, rte_errno,
12809                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12810                                           "cannot setup indirection table");
12811         }
12812         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12813         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12814         rss_desc.const_q = shared_rss->origin.queue;
12815         rss_desc.queue_num = shared_rss->origin.queue_num;
12816         /* Set non-zero value to indicate a shared RSS. */
12817         rss_desc.shared_rss = action_idx;
12818         rss_desc.ind_tbl = shared_rss->ind_tbl;
12819         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12820                 uint32_t hrxq_idx;
12821                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12822                 int tunnel = 0;
12823
12824                 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
12825                 if (shared_rss->origin.level > 1) {
12826                         hash_fields |= IBV_RX_HASH_INNER;
12827                         tunnel = 1;
12828                 }
12829                 rss_desc.tunnel = tunnel;
12830                 rss_desc.hash_fields = hash_fields;
12831                 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12832                 if (!hrxq_idx) {
12833                         rte_flow_error_set
12834                                 (error, rte_errno,
12835                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12836                                  "cannot get hash queue");
12837                         goto error_hrxq_new;
12838                 }
12839                 err = __flow_dv_action_rss_hrxq_set
12840                         (shared_rss, hash_fields, hrxq_idx);
12841                 MLX5_ASSERT(!err);
12842         }
12843         return 0;
12844 error_hrxq_new:
12845         err = rte_errno;
12846         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12847         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12848                 shared_rss->ind_tbl = NULL;
12849         rte_errno = err;
12850         return -rte_errno;
12851 }
12852
12853 /**
12854  * Create shared RSS action.
12855  *
12856  * @param[in] dev
12857  *   Pointer to the Ethernet device structure.
12858  * @param[in] conf
12859  *   Shared action configuration.
12860  * @param[in] rss
12861  *   RSS action specification used to create shared action.
12862  * @param[out] error
12863  *   Perform verbose error reporting if not NULL. Initialized in case of
12864  *   error only.
12865  *
12866  * @return
12867  *   A valid shared action ID in case of success, 0 otherwise and
12868  *   rte_errno is set.
12869  */
12870 static uint32_t
12871 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12872                             const struct rte_flow_shared_action_conf *conf,
12873                             const struct rte_flow_action_rss *rss,
12874                             struct rte_flow_error *error)
12875 {
12876         struct mlx5_priv *priv = dev->data->dev_private;
12877         struct mlx5_shared_action_rss *shared_rss = NULL;
12878         void *queue = NULL;
12879         struct rte_flow_action_rss *origin;
12880         const uint8_t *rss_key;
12881         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12882         uint32_t idx;
12883
12884         RTE_SET_USED(conf);
12885         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12886                             0, SOCKET_ID_ANY);
12887         shared_rss = mlx5_ipool_zmalloc
12888                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12889         if (!shared_rss || !queue) {
12890                 rte_flow_error_set(error, ENOMEM,
12891                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12892                                    "cannot allocate resource memory");
12893                 goto error_rss_init;
12894         }
12895         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12896                 rte_flow_error_set(error, E2BIG,
12897                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12898                                    "rss action number out of range");
12899                 goto error_rss_init;
12900         }
12901         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12902                                           sizeof(*shared_rss->ind_tbl),
12903                                           0, SOCKET_ID_ANY);
12904         if (!shared_rss->ind_tbl) {
12905                 rte_flow_error_set(error, ENOMEM,
12906                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12907                                    "cannot allocate resource memory");
12908                 goto error_rss_init;
12909         }
12910         memcpy(queue, rss->queue, queue_size);
12911         shared_rss->ind_tbl->queues = queue;
12912         shared_rss->ind_tbl->queues_n = rss->queue_num;
12913         origin = &shared_rss->origin;
12914         origin->func = rss->func;
12915         origin->level = rss->level;
12916         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12917         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12918         /* NULL RSS key indicates default RSS key. */
12919         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12920         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12921         origin->key = &shared_rss->key[0];
12922         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12923         origin->queue = queue;
12924         origin->queue_num = rss->queue_num;
12925         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12926                 goto error_rss_init;
12927         rte_spinlock_init(&shared_rss->action_rss_sl);
12928         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12929         rte_spinlock_lock(&priv->shared_act_sl);
12930         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12931                      &priv->rss_shared_actions, idx, shared_rss, next);
12932         rte_spinlock_unlock(&priv->shared_act_sl);
12933         return idx;
12934 error_rss_init:
12935         if (shared_rss) {
12936                 if (shared_rss->ind_tbl)
12937                         mlx5_free(shared_rss->ind_tbl);
12938                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12939                                 idx);
12940         }
12941         if (queue)
12942                 mlx5_free(queue);
12943         return 0;
12944 }
12945
12946 /**
12947  * Destroy the shared RSS action.
12948  * Release related hash RX queue objects.
12949  *
12950  * @param[in] dev
12951  *   Pointer to the Ethernet device structure.
12952  * @param[in] idx
12953  *   The shared RSS action object ID to be removed.
12954  * @param[out] error
12955  *   Perform verbose error reporting if not NULL. Initialized in case of
12956  *   error only.
12957  *
12958  * @return
12959  *   0 on success, otherwise negative errno value.
12960  */
12961 static int
12962 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12963                              struct rte_flow_error *error)
12964 {
12965         struct mlx5_priv *priv = dev->data->dev_private;
12966         struct mlx5_shared_action_rss *shared_rss =
12967             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12968         uint32_t old_refcnt = 1;
12969         int remaining;
12970         uint16_t *queue = NULL;
12971
12972         if (!shared_rss)
12973                 return rte_flow_error_set(error, EINVAL,
12974                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12975                                           "invalid shared action");
12976         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12977         if (remaining)
12978                 return rte_flow_error_set(error, EBUSY,
12979                                           RTE_FLOW_ERROR_TYPE_ACTION,
12980                                           NULL,
12981                                           "shared rss hrxq has references");
12982         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12983                                          0, 0, __ATOMIC_ACQUIRE,
12984                                          __ATOMIC_RELAXED))
12985                 return rte_flow_error_set(error, EBUSY,
12986                                           RTE_FLOW_ERROR_TYPE_ACTION,
12987                                           NULL,
12988                                           "shared rss has references");
12989         queue = shared_rss->ind_tbl->queues;
12990         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12991         if (remaining)
12992                 return rte_flow_error_set(error, EBUSY,
12993                                           RTE_FLOW_ERROR_TYPE_ACTION,
12994                                           NULL,
12995                                           "shared rss indirection table has"
12996                                           " references");
12997         mlx5_free(queue);
12998         rte_spinlock_lock(&priv->shared_act_sl);
12999         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13000                      &priv->rss_shared_actions, idx, shared_rss, next);
13001         rte_spinlock_unlock(&priv->shared_act_sl);
13002         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
13003                         idx);
13004         return 0;
13005 }
13006
13007 /**
13008  * Create shared action, lock free,
13009  * (mutex should be acquired by caller).
13010  * Dispatcher for action type specific call.
13011  *
13012  * @param[in] dev
13013  *   Pointer to the Ethernet device structure.
13014  * @param[in] conf
13015  *   Shared action configuration.
13016  * @param[in] action
13017  *   Action specification used to create shared action.
13018  * @param[out] error
13019  *   Perform verbose error reporting if not NULL. Initialized in case of
13020  *   error only.
13021  *
13022  * @return
13023  *   A valid shared action handle in case of success, NULL otherwise and
13024  *   rte_errno is set.
13025  */
13026 static struct rte_flow_shared_action *
13027 flow_dv_action_create(struct rte_eth_dev *dev,
13028                       const struct rte_flow_shared_action_conf *conf,
13029                       const struct rte_flow_action *action,
13030                       struct rte_flow_error *err)
13031 {
13032         uint32_t idx = 0;
13033         uint32_t ret = 0;
13034
13035         switch (action->type) {
13036         case RTE_FLOW_ACTION_TYPE_RSS:
13037                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
13038                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
13039                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13040                 break;
13041         case RTE_FLOW_ACTION_TYPE_AGE:
13042                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
13043                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
13044                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
13045                 if (ret) {
13046                         struct mlx5_aso_age_action *aso_age =
13047                                               flow_aso_age_get_by_idx(dev, ret);
13048
13049                         if (!aso_age->age_params.context)
13050                                 aso_age->age_params.context =
13051                                                          (void *)(uintptr_t)idx;
13052                 }
13053                 break;
13054         default:
13055                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
13056                                    NULL, "action type not supported");
13057                 break;
13058         }
13059         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
13060 }
13061
13062 /**
13063  * Destroy the shared action.
13064  * Release action related resources on the NIC and the memory.
13065  * Lock free, (mutex should be acquired by caller).
13066  * Dispatcher for action type specific call.
13067  *
13068  * @param[in] dev
13069  *   Pointer to the Ethernet device structure.
13070  * @param[in] action
13071  *   The shared action object to be removed.
13072  * @param[out] error
13073  *   Perform verbose error reporting if not NULL. Initialized in case of
13074  *   error only.
13075  *
13076  * @return
13077  *   0 on success, otherwise negative errno value.
13078  */
13079 static int
13080 flow_dv_action_destroy(struct rte_eth_dev *dev,
13081                        struct rte_flow_shared_action *action,
13082                        struct rte_flow_error *error)
13083 {
13084         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13085         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13086         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13087         int ret;
13088
13089         switch (type) {
13090         case MLX5_SHARED_ACTION_TYPE_RSS:
13091                 return __flow_dv_action_rss_release(dev, idx, error);
13092         case MLX5_SHARED_ACTION_TYPE_AGE:
13093                 ret = flow_dv_aso_age_release(dev, idx);
13094                 if (ret)
13095                         /*
13096                          * In this case, the last flow has a reference will
13097                          * actually release the age action.
13098                          */
13099                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
13100                                 " released with references %d.", idx, ret);
13101                 return 0;
13102         default:
13103                 return rte_flow_error_set(error, ENOTSUP,
13104                                           RTE_FLOW_ERROR_TYPE_ACTION,
13105                                           NULL,
13106                                           "action type not supported");
13107         }
13108 }
13109
13110 /**
13111  * Updates in place shared RSS action configuration.
13112  *
13113  * @param[in] dev
13114  *   Pointer to the Ethernet device structure.
13115  * @param[in] idx
13116  *   The shared RSS action object ID to be updated.
13117  * @param[in] action_conf
13118  *   RSS action specification used to modify *shared_rss*.
13119  * @param[out] error
13120  *   Perform verbose error reporting if not NULL. Initialized in case of
13121  *   error only.
13122  *
13123  * @return
13124  *   0 on success, otherwise negative errno value.
13125  * @note: currently only support update of RSS queues.
13126  */
13127 static int
13128 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
13129                             const struct rte_flow_action_rss *action_conf,
13130                             struct rte_flow_error *error)
13131 {
13132         struct mlx5_priv *priv = dev->data->dev_private;
13133         struct mlx5_shared_action_rss *shared_rss =
13134             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13135         int ret = 0;
13136         void *queue = NULL;
13137         uint16_t *queue_old = NULL;
13138         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
13139
13140         if (!shared_rss)
13141                 return rte_flow_error_set(error, EINVAL,
13142                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13143                                           "invalid shared action to update");
13144         if (priv->obj_ops.ind_table_modify == NULL)
13145                 return rte_flow_error_set(error, ENOTSUP,
13146                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13147                                           "cannot modify indirection table");
13148         queue = mlx5_malloc(MLX5_MEM_ZERO,
13149                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13150                             0, SOCKET_ID_ANY);
13151         if (!queue)
13152                 return rte_flow_error_set(error, ENOMEM,
13153                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13154                                           NULL,
13155                                           "cannot allocate resource memory");
13156         memcpy(queue, action_conf->queue, queue_size);
13157         MLX5_ASSERT(shared_rss->ind_tbl);
13158         rte_spinlock_lock(&shared_rss->action_rss_sl);
13159         queue_old = shared_rss->ind_tbl->queues;
13160         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13161                                         queue, action_conf->queue_num, true);
13162         if (ret) {
13163                 mlx5_free(queue);
13164                 ret = rte_flow_error_set(error, rte_errno,
13165                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13166                                           "cannot update indirection table");
13167         } else {
13168                 mlx5_free(queue_old);
13169                 shared_rss->origin.queue = queue;
13170                 shared_rss->origin.queue_num = action_conf->queue_num;
13171         }
13172         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13173         return ret;
13174 }
13175
13176 /**
13177  * Updates in place shared action configuration, lock free,
13178  * (mutex should be acquired by caller).
13179  *
13180  * @param[in] dev
13181  *   Pointer to the Ethernet device structure.
13182  * @param[in] action
13183  *   The shared action object to be updated.
13184  * @param[in] action_conf
13185  *   Action specification used to modify *action*.
13186  *   *action_conf* should be of type correlating with type of the *action*,
13187  *   otherwise considered as invalid.
13188  * @param[out] error
13189  *   Perform verbose error reporting if not NULL. Initialized in case of
13190  *   error only.
13191  *
13192  * @return
13193  *   0 on success, otherwise negative errno value.
13194  */
13195 static int
13196 flow_dv_action_update(struct rte_eth_dev *dev,
13197                         struct rte_flow_shared_action *action,
13198                         const void *action_conf,
13199                         struct rte_flow_error *err)
13200 {
13201         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13202         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13203         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13204
13205         switch (type) {
13206         case MLX5_SHARED_ACTION_TYPE_RSS:
13207                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13208         default:
13209                 return rte_flow_error_set(err, ENOTSUP,
13210                                           RTE_FLOW_ERROR_TYPE_ACTION,
13211                                           NULL,
13212                                           "action type update not supported");
13213         }
13214 }
13215
13216 static int
13217 flow_dv_action_query(struct rte_eth_dev *dev,
13218                      const struct rte_flow_shared_action *action, void *data,
13219                      struct rte_flow_error *error)
13220 {
13221         struct mlx5_age_param *age_param;
13222         struct rte_flow_query_age *resp;
13223         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13224         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13225         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13226
13227         switch (type) {
13228         case MLX5_SHARED_ACTION_TYPE_AGE:
13229                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13230                 resp = data;
13231                 resp->aged = __atomic_load_n(&age_param->state,
13232                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13233                                                                           1 : 0;
13234                 resp->sec_since_last_hit_valid = !resp->aged;
13235                 if (resp->sec_since_last_hit_valid)
13236                         resp->sec_since_last_hit = __atomic_load_n
13237                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13238                 return 0;
13239         default:
13240                 return rte_flow_error_set(error, ENOTSUP,
13241                                           RTE_FLOW_ERROR_TYPE_ACTION,
13242                                           NULL,
13243                                           "action type query not supported");
13244         }
13245 }
13246
13247 /**
13248  * Query a dv flow  rule for its statistics via devx.
13249  *
13250  * @param[in] dev
13251  *   Pointer to Ethernet device.
13252  * @param[in] flow
13253  *   Pointer to the sub flow.
13254  * @param[out] data
13255  *   data retrieved by the query.
13256  * @param[out] error
13257  *   Perform verbose error reporting if not NULL.
13258  *
13259  * @return
13260  *   0 on success, a negative errno value otherwise and rte_errno is set.
13261  */
13262 static int
13263 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13264                     void *data, struct rte_flow_error *error)
13265 {
13266         struct mlx5_priv *priv = dev->data->dev_private;
13267         struct rte_flow_query_count *qc = data;
13268
13269         if (!priv->config.devx)
13270                 return rte_flow_error_set(error, ENOTSUP,
13271                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13272                                           NULL,
13273                                           "counters are not supported");
13274         if (flow->counter) {
13275                 uint64_t pkts, bytes;
13276                 struct mlx5_flow_counter *cnt;
13277
13278                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13279                                                  NULL);
13280                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13281                                                &bytes);
13282
13283                 if (err)
13284                         return rte_flow_error_set(error, -err,
13285                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13286                                         NULL, "cannot read counters");
13287                 qc->hits_set = 1;
13288                 qc->bytes_set = 1;
13289                 qc->hits = pkts - cnt->hits;
13290                 qc->bytes = bytes - cnt->bytes;
13291                 if (qc->reset) {
13292                         cnt->hits = pkts;
13293                         cnt->bytes = bytes;
13294                 }
13295                 return 0;
13296         }
13297         return rte_flow_error_set(error, EINVAL,
13298                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13299                                   NULL,
13300                                   "counters are not available");
13301 }
13302
13303 /**
13304  * Query a flow rule AGE action for aging information.
13305  *
13306  * @param[in] dev
13307  *   Pointer to Ethernet device.
13308  * @param[in] flow
13309  *   Pointer to the sub flow.
13310  * @param[out] data
13311  *   data retrieved by the query.
13312  * @param[out] error
13313  *   Perform verbose error reporting if not NULL.
13314  *
13315  * @return
13316  *   0 on success, a negative errno value otherwise and rte_errno is set.
13317  */
13318 static int
13319 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13320                   void *data, struct rte_flow_error *error)
13321 {
13322         struct rte_flow_query_age *resp = data;
13323         struct mlx5_age_param *age_param;
13324
13325         if (flow->age) {
13326                 struct mlx5_aso_age_action *act =
13327                                      flow_aso_age_get_by_idx(dev, flow->age);
13328
13329                 age_param = &act->age_params;
13330         } else if (flow->counter) {
13331                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13332
13333                 if (!age_param || !age_param->timeout)
13334                         return rte_flow_error_set
13335                                         (error, EINVAL,
13336                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13337                                          NULL, "cannot read age data");
13338         } else {
13339                 return rte_flow_error_set(error, EINVAL,
13340                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13341                                           NULL, "age data not available");
13342         }
13343         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13344                                      AGE_TMOUT ? 1 : 0;
13345         resp->sec_since_last_hit_valid = !resp->aged;
13346         if (resp->sec_since_last_hit_valid)
13347                 resp->sec_since_last_hit = __atomic_load_n
13348                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13349         return 0;
13350 }
13351
13352 /**
13353  * Query a flow.
13354  *
13355  * @see rte_flow_query()
13356  * @see rte_flow_ops
13357  */
13358 static int
13359 flow_dv_query(struct rte_eth_dev *dev,
13360               struct rte_flow *flow __rte_unused,
13361               const struct rte_flow_action *actions __rte_unused,
13362               void *data __rte_unused,
13363               struct rte_flow_error *error __rte_unused)
13364 {
13365         int ret = -EINVAL;
13366
13367         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13368                 switch (actions->type) {
13369                 case RTE_FLOW_ACTION_TYPE_VOID:
13370                         break;
13371                 case RTE_FLOW_ACTION_TYPE_COUNT:
13372                         ret = flow_dv_query_count(dev, flow, data, error);
13373                         break;
13374                 case RTE_FLOW_ACTION_TYPE_AGE:
13375                         ret = flow_dv_query_age(dev, flow, data, error);
13376                         break;
13377                 default:
13378                         return rte_flow_error_set(error, ENOTSUP,
13379                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13380                                                   actions,
13381                                                   "action not supported");
13382                 }
13383         }
13384         return ret;
13385 }
13386
13387 /**
13388  * Destroy the meter table set.
13389  * Lock free, (mutex should be acquired by caller).
13390  *
13391  * @param[in] dev
13392  *   Pointer to Ethernet device.
13393  * @param[in] tbl
13394  *   Pointer to the meter table set.
13395  *
13396  * @return
13397  *   Always 0.
13398  */
13399 static int
13400 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13401                         struct mlx5_meter_domains_infos *tbl)
13402 {
13403         struct mlx5_priv *priv = dev->data->dev_private;
13404         struct mlx5_meter_domains_infos *mtd =
13405                                 (struct mlx5_meter_domains_infos *)tbl;
13406
13407         if (!mtd || !priv->config.dv_flow_en)
13408                 return 0;
13409         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13410                 claim_zero(mlx5_flow_os_destroy_flow
13411                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13412         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13413                 claim_zero(mlx5_flow_os_destroy_flow
13414                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13415         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13416                 claim_zero(mlx5_flow_os_destroy_flow
13417                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13418         if (mtd->egress.color_matcher)
13419                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13420                            (mtd->egress.color_matcher));
13421         if (mtd->egress.any_matcher)
13422                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13423                            (mtd->egress.any_matcher));
13424         if (mtd->egress.tbl)
13425                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13426         if (mtd->egress.sfx_tbl)
13427                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13428         if (mtd->ingress.color_matcher)
13429                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13430                            (mtd->ingress.color_matcher));
13431         if (mtd->ingress.any_matcher)
13432                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13433                            (mtd->ingress.any_matcher));
13434         if (mtd->ingress.tbl)
13435                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13436         if (mtd->ingress.sfx_tbl)
13437                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13438                                              mtd->ingress.sfx_tbl);
13439         if (mtd->transfer.color_matcher)
13440                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13441                            (mtd->transfer.color_matcher));
13442         if (mtd->transfer.any_matcher)
13443                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13444                            (mtd->transfer.any_matcher));
13445         if (mtd->transfer.tbl)
13446                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13447         if (mtd->transfer.sfx_tbl)
13448                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13449                                              mtd->transfer.sfx_tbl);
13450         if (mtd->drop_actn)
13451                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13452         mlx5_free(mtd);
13453         return 0;
13454 }
13455
13456 /* Number of meter flow actions, count and jump or count and drop. */
13457 #define METER_ACTIONS 2
13458
13459 /**
13460  * Create specify domain meter table and suffix table.
13461  *
13462  * @param[in] dev
13463  *   Pointer to Ethernet device.
13464  * @param[in,out] mtb
13465  *   Pointer to DV meter table set.
13466  * @param[in] egress
13467  *   Table attribute.
13468  * @param[in] transfer
13469  *   Table attribute.
13470  * @param[in] color_reg_c_idx
13471  *   Reg C index for color match.
13472  *
13473  * @return
13474  *   0 on success, -1 otherwise and rte_errno is set.
13475  */
13476 static int
13477 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13478                            struct mlx5_meter_domains_infos *mtb,
13479                            uint8_t egress, uint8_t transfer,
13480                            uint32_t color_reg_c_idx)
13481 {
13482         struct mlx5_priv *priv = dev->data->dev_private;
13483         struct mlx5_dev_ctx_shared *sh = priv->sh;
13484         struct mlx5_flow_dv_match_params mask = {
13485                 .size = sizeof(mask.buf),
13486         };
13487         struct mlx5_flow_dv_match_params value = {
13488                 .size = sizeof(value.buf),
13489         };
13490         struct mlx5dv_flow_matcher_attr dv_attr = {
13491                 .type = IBV_FLOW_ATTR_NORMAL,
13492                 .priority = 0,
13493                 .match_criteria_enable = 0,
13494                 .match_mask = (void *)&mask,
13495         };
13496         void *actions[METER_ACTIONS];
13497         struct mlx5_meter_domain_info *dtb;
13498         struct rte_flow_error error;
13499         int i = 0;
13500         int ret;
13501
13502         if (transfer)
13503                 dtb = &mtb->transfer;
13504         else if (egress)
13505                 dtb = &mtb->egress;
13506         else
13507                 dtb = &mtb->ingress;
13508         /* Create the meter table with METER level. */
13509         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13510                                             egress, transfer, false, NULL, 0,
13511                                             0, &error);
13512         if (!dtb->tbl) {
13513                 DRV_LOG(ERR, "Failed to create meter policer table.");
13514                 return -1;
13515         }
13516         /* Create the meter suffix table with SUFFIX level. */
13517         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13518                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13519                                             egress, transfer, false, NULL, 0,
13520                                             0, &error);
13521         if (!dtb->sfx_tbl) {
13522                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13523                 return -1;
13524         }
13525         /* Create matchers, Any and Color. */
13526         dv_attr.priority = 3;
13527         dv_attr.match_criteria_enable = 0;
13528         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13529                                                &dtb->any_matcher);
13530         if (ret) {
13531                 DRV_LOG(ERR, "Failed to create meter"
13532                              " policer default matcher.");
13533                 goto error_exit;
13534         }
13535         dv_attr.priority = 0;
13536         dv_attr.match_criteria_enable =
13537                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13538         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13539                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13540         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13541                                                &dtb->color_matcher);
13542         if (ret) {
13543                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13544                 goto error_exit;
13545         }
13546         if (mtb->count_actns[RTE_MTR_DROPPED])
13547                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13548         actions[i++] = mtb->drop_actn;
13549         /* Default rule: lowest priority, match any, actions: drop. */
13550         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13551                                        actions,
13552                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
13553         if (ret) {
13554                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13555                 goto error_exit;
13556         }
13557         return 0;
13558 error_exit:
13559         return -1;
13560 }
13561
13562 /**
13563  * Create the needed meter and suffix tables.
13564  * Lock free, (mutex should be acquired by caller).
13565  *
13566  * @param[in] dev
13567  *   Pointer to Ethernet device.
13568  * @param[in] fm
13569  *   Pointer to the flow meter.
13570  *
13571  * @return
13572  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13573  */
13574 static struct mlx5_meter_domains_infos *
13575 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13576                        const struct mlx5_flow_meter *fm)
13577 {
13578         struct mlx5_priv *priv = dev->data->dev_private;
13579         struct mlx5_meter_domains_infos *mtb;
13580         int ret;
13581         int i;
13582
13583         if (!priv->mtr_en) {
13584                 rte_errno = ENOTSUP;
13585                 return NULL;
13586         }
13587         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13588         if (!mtb) {
13589                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13590                 return NULL;
13591         }
13592         /* Create meter count actions */
13593         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13594                 struct mlx5_flow_counter *cnt;
13595                 if (!fm->policer_stats.cnt[i])
13596                         continue;
13597                 cnt = flow_dv_counter_get_by_idx(dev,
13598                       fm->policer_stats.cnt[i], NULL);
13599                 mtb->count_actns[i] = cnt->action;
13600         }
13601         /* Create drop action. */
13602         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13603         if (ret) {
13604                 DRV_LOG(ERR, "Failed to create drop action.");
13605                 goto error_exit;
13606         }
13607         /* Egress meter table. */
13608         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13609         if (ret) {
13610                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13611                 goto error_exit;
13612         }
13613         /* Ingress meter table. */
13614         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13615         if (ret) {
13616                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13617                 goto error_exit;
13618         }
13619         /* FDB meter table. */
13620         if (priv->config.dv_esw_en) {
13621                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13622                                                  priv->mtr_color_reg);
13623                 if (ret) {
13624                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13625                         goto error_exit;
13626                 }
13627         }
13628         return mtb;
13629 error_exit:
13630         flow_dv_destroy_mtr_tbl(dev, mtb);
13631         return NULL;
13632 }
13633
13634 /**
13635  * Destroy domain policer rule.
13636  *
13637  * @param[in] dt
13638  *   Pointer to domain table.
13639  */
13640 static void
13641 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13642 {
13643         int i;
13644
13645         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13646                 if (dt->policer_rules[i]) {
13647                         claim_zero(mlx5_flow_os_destroy_flow
13648                                    (dt->policer_rules[i]));
13649                         dt->policer_rules[i] = NULL;
13650                 }
13651         }
13652         if (dt->jump_actn) {
13653                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13654                 dt->jump_actn = NULL;
13655         }
13656 }
13657
13658 /**
13659  * Destroy policer rules.
13660  *
13661  * @param[in] dev
13662  *   Pointer to Ethernet device.
13663  * @param[in] fm
13664  *   Pointer to flow meter structure.
13665  * @param[in] attr
13666  *   Pointer to flow attributes.
13667  *
13668  * @return
13669  *   Always 0.
13670  */
13671 static int
13672 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13673                               const struct mlx5_flow_meter *fm,
13674                               const struct rte_flow_attr *attr)
13675 {
13676         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13677
13678         if (!mtb)
13679                 return 0;
13680         if (attr->egress)
13681                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13682         if (attr->ingress)
13683                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13684         if (attr->transfer)
13685                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13686         return 0;
13687 }
13688
13689 /**
13690  * Create specify domain meter policer rule.
13691  *
13692  * @param[in] fm
13693  *   Pointer to flow meter structure.
13694  * @param[in] mtb
13695  *   Pointer to DV meter table set.
13696  * @param[in] mtr_reg_c
13697  *   Color match REG_C.
13698  *
13699  * @return
13700  *   0 on success, -1 otherwise.
13701  */
13702 static int
13703 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13704                                     struct mlx5_meter_domain_info *dtb,
13705                                     uint8_t mtr_reg_c)
13706 {
13707         struct mlx5_flow_dv_match_params matcher = {
13708                 .size = sizeof(matcher.buf),
13709         };
13710         struct mlx5_flow_dv_match_params value = {
13711                 .size = sizeof(value.buf),
13712         };
13713         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13714         void *actions[METER_ACTIONS];
13715         int i;
13716         int ret = 0;
13717
13718         /* Create jump action. */
13719         if (!dtb->jump_actn)
13720                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13721                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13722         if (ret) {
13723                 DRV_LOG(ERR, "Failed to create policer jump action.");
13724                 goto error;
13725         }
13726         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13727                 int j = 0;
13728
13729                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13730                                        rte_col_2_mlx5_col(i), UINT8_MAX);
13731                 if (mtb->count_actns[i])
13732                         actions[j++] = mtb->count_actns[i];
13733                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13734                         actions[j++] = mtb->drop_actn;
13735                 else
13736                         actions[j++] = dtb->jump_actn;
13737                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13738                                                (void *)&value, j, actions,
13739                                                &dtb->policer_rules[i]);
13740                 if (ret) {
13741                         DRV_LOG(ERR, "Failed to create policer rule.");
13742                         goto error;
13743                 }
13744         }
13745         return 0;
13746 error:
13747         rte_errno = errno;
13748         return -1;
13749 }
13750
13751 /**
13752  * Create policer rules.
13753  *
13754  * @param[in] dev
13755  *   Pointer to Ethernet device.
13756  * @param[in] fm
13757  *   Pointer to flow meter structure.
13758  * @param[in] attr
13759  *   Pointer to flow attributes.
13760  *
13761  * @return
13762  *   0 on success, -1 otherwise.
13763  */
13764 static int
13765 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13766                              struct mlx5_flow_meter *fm,
13767                              const struct rte_flow_attr *attr)
13768 {
13769         struct mlx5_priv *priv = dev->data->dev_private;
13770         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13771         int ret;
13772
13773         if (attr->egress) {
13774                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13775                                                 priv->mtr_color_reg);
13776                 if (ret) {
13777                         DRV_LOG(ERR, "Failed to create egress policer.");
13778                         goto error;
13779                 }
13780         }
13781         if (attr->ingress) {
13782                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13783                                                 priv->mtr_color_reg);
13784                 if (ret) {
13785                         DRV_LOG(ERR, "Failed to create ingress policer.");
13786                         goto error;
13787                 }
13788         }
13789         if (attr->transfer) {
13790                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13791                                                 priv->mtr_color_reg);
13792                 if (ret) {
13793                         DRV_LOG(ERR, "Failed to create transfer policer.");
13794                         goto error;
13795                 }
13796         }
13797         return 0;
13798 error:
13799         flow_dv_destroy_policer_rules(dev, fm, attr);
13800         return -1;
13801 }
13802
13803 /**
13804  * Validate the batch counter support in root table.
13805  *
13806  * Create a simple flow with invalid counter and drop action on root table to
13807  * validate if batch counter with offset on root table is supported or not.
13808  *
13809  * @param[in] dev
13810  *   Pointer to rte_eth_dev structure.
13811  *
13812  * @return
13813  *   0 on success, a negative errno value otherwise and rte_errno is set.
13814  */
13815 int
13816 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13817 {
13818         struct mlx5_priv *priv = dev->data->dev_private;
13819         struct mlx5_dev_ctx_shared *sh = priv->sh;
13820         struct mlx5_flow_dv_match_params mask = {
13821                 .size = sizeof(mask.buf),
13822         };
13823         struct mlx5_flow_dv_match_params value = {
13824                 .size = sizeof(value.buf),
13825         };
13826         struct mlx5dv_flow_matcher_attr dv_attr = {
13827                 .type = IBV_FLOW_ATTR_NORMAL,
13828                 .priority = 0,
13829                 .match_criteria_enable = 0,
13830                 .match_mask = (void *)&mask,
13831         };
13832         void *actions[2] = { 0 };
13833         struct mlx5_flow_tbl_resource *tbl = NULL;
13834         struct mlx5_devx_obj *dcs = NULL;
13835         void *matcher = NULL;
13836         void *flow = NULL;
13837         int ret = -1;
13838
13839         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13840         if (!tbl)
13841                 goto err;
13842         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13843         if (!dcs)
13844                 goto err;
13845         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13846                                                     &actions[0]);
13847         if (ret)
13848                 goto err;
13849         actions[1] = sh->dr_drop_action ? sh->dr_drop_action :
13850                                           priv->drop_queue.hrxq->action;
13851         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13852         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13853                                                &matcher);
13854         if (ret)
13855                 goto err;
13856         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13857                                        actions, &flow);
13858 err:
13859         /*
13860          * If batch counter with offset is not supported, the driver will not
13861          * validate the invalid offset value, flow create should success.
13862          * In this case, it means batch counter is not supported in root table.
13863          *
13864          * Otherwise, if flow create is failed, counter offset is supported.
13865          */
13866         if (flow) {
13867                 DRV_LOG(INFO, "Batch counter is not supported in root "
13868                               "table. Switch to fallback mode.");
13869                 rte_errno = ENOTSUP;
13870                 ret = -rte_errno;
13871                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13872         } else {
13873                 /* Check matcher to make sure validate fail at flow create. */
13874                 if (!matcher || (matcher && errno != EINVAL))
13875                         DRV_LOG(ERR, "Unexpected error in counter offset "
13876                                      "support detection");
13877                 ret = 0;
13878         }
13879         if (actions[0])
13880                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13881         if (matcher)
13882                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13883         if (tbl)
13884                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13885         if (dcs)
13886                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13887         return ret;
13888 }
13889
13890 /**
13891  * Query a devx counter.
13892  *
13893  * @param[in] dev
13894  *   Pointer to the Ethernet device structure.
13895  * @param[in] cnt
13896  *   Index to the flow counter.
13897  * @param[in] clear
13898  *   Set to clear the counter statistics.
13899  * @param[out] pkts
13900  *   The statistics value of packets.
13901  * @param[out] bytes
13902  *   The statistics value of bytes.
13903  *
13904  * @return
13905  *   0 on success, otherwise return -1.
13906  */
13907 static int
13908 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13909                       uint64_t *pkts, uint64_t *bytes)
13910 {
13911         struct mlx5_priv *priv = dev->data->dev_private;
13912         struct mlx5_flow_counter *cnt;
13913         uint64_t inn_pkts, inn_bytes;
13914         int ret;
13915
13916         if (!priv->config.devx)
13917                 return -1;
13918
13919         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13920         if (ret)
13921                 return -1;
13922         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13923         *pkts = inn_pkts - cnt->hits;
13924         *bytes = inn_bytes - cnt->bytes;
13925         if (clear) {
13926                 cnt->hits = inn_pkts;
13927                 cnt->bytes = inn_bytes;
13928         }
13929         return 0;
13930 }
13931
13932 /**
13933  * Get aged-out flows.
13934  *
13935  * @param[in] dev
13936  *   Pointer to the Ethernet device structure.
13937  * @param[in] context
13938  *   The address of an array of pointers to the aged-out flows contexts.
13939  * @param[in] nb_contexts
13940  *   The length of context array pointers.
13941  * @param[out] error
13942  *   Perform verbose error reporting if not NULL. Initialized in case of
13943  *   error only.
13944  *
13945  * @return
13946  *   how many contexts get in success, otherwise negative errno value.
13947  *   if nb_contexts is 0, return the amount of all aged contexts.
13948  *   if nb_contexts is not 0 , return the amount of aged flows reported
13949  *   in the context array.
13950  * @note: only stub for now
13951  */
13952 static int
13953 flow_get_aged_flows(struct rte_eth_dev *dev,
13954                     void **context,
13955                     uint32_t nb_contexts,
13956                     struct rte_flow_error *error)
13957 {
13958         struct mlx5_priv *priv = dev->data->dev_private;
13959         struct mlx5_age_info *age_info;
13960         struct mlx5_age_param *age_param;
13961         struct mlx5_flow_counter *counter;
13962         struct mlx5_aso_age_action *act;
13963         int nb_flows = 0;
13964
13965         if (nb_contexts && !context)
13966                 return rte_flow_error_set(error, EINVAL,
13967                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13968                                           NULL, "empty context");
13969         age_info = GET_PORT_AGE_INFO(priv);
13970         rte_spinlock_lock(&age_info->aged_sl);
13971         LIST_FOREACH(act, &age_info->aged_aso, next) {
13972                 nb_flows++;
13973                 if (nb_contexts) {
13974                         context[nb_flows - 1] =
13975                                                 act->age_params.context;
13976                         if (!(--nb_contexts))
13977                                 break;
13978                 }
13979         }
13980         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13981                 nb_flows++;
13982                 if (nb_contexts) {
13983                         age_param = MLX5_CNT_TO_AGE(counter);
13984                         context[nb_flows - 1] = age_param->context;
13985                         if (!(--nb_contexts))
13986                                 break;
13987                 }
13988         }
13989         rte_spinlock_unlock(&age_info->aged_sl);
13990         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13991         return nb_flows;
13992 }
13993
13994 /*
13995  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13996  */
13997 static uint32_t
13998 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13999 {
14000         return flow_dv_counter_alloc(dev, 0);
14001 }
14002
14003 /**
14004  * Validate shared action.
14005  * Dispatcher for action type specific validation.
14006  *
14007  * @param[in] dev
14008  *   Pointer to the Ethernet device structure.
14009  * @param[in] conf
14010  *   Shared action configuration.
14011  * @param[in] action
14012  *   The shared action object to validate.
14013  * @param[out] error
14014  *   Perform verbose error reporting if not NULL. Initialized in case of
14015  *   error only.
14016  *
14017  * @return
14018  *   0 on success, otherwise negative errno value.
14019  */
14020 static int
14021 flow_dv_action_validate(struct rte_eth_dev *dev,
14022                         const struct rte_flow_shared_action_conf *conf,
14023                         const struct rte_flow_action *action,
14024                         struct rte_flow_error *err)
14025 {
14026         struct mlx5_priv *priv = dev->data->dev_private;
14027
14028         RTE_SET_USED(conf);
14029         switch (action->type) {
14030         case RTE_FLOW_ACTION_TYPE_RSS:
14031                 /*
14032                  * priv->obj_ops is set according to driver capabilities.
14033                  * When DevX capabilities are
14034                  * sufficient, it is set to devx_obj_ops.
14035                  * Otherwise, it is set to ibv_obj_ops.
14036                  * ibv_obj_ops doesn't support ind_table_modify operation.
14037                  * In this case the shared RSS action can't be used.
14038                  */
14039                 if (priv->obj_ops.ind_table_modify == NULL)
14040                         return rte_flow_error_set
14041                                         (err, ENOTSUP,
14042                                          RTE_FLOW_ERROR_TYPE_ACTION,
14043                                          NULL,
14044                                          "shared RSS action not supported");
14045                 return mlx5_validate_action_rss(dev, action, err);
14046         case RTE_FLOW_ACTION_TYPE_AGE:
14047                 if (!priv->sh->aso_age_mng)
14048                         return rte_flow_error_set(err, ENOTSUP,
14049                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14050                                                 NULL,
14051                                              "shared age action not supported");
14052                 return flow_dv_validate_action_age(0, action, dev, err);
14053         default:
14054                 return rte_flow_error_set(err, ENOTSUP,
14055                                           RTE_FLOW_ERROR_TYPE_ACTION,
14056                                           NULL,
14057                                           "action type not supported");
14058         }
14059 }
14060
14061 static int
14062 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
14063 {
14064         struct mlx5_priv *priv = dev->data->dev_private;
14065         int ret = 0;
14066
14067         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
14068                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
14069                                                 flags);
14070                 if (ret != 0)
14071                         return ret;
14072         }
14073         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
14074                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
14075                 if (ret != 0)
14076                         return ret;
14077         }
14078         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
14079                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
14080                 if (ret != 0)
14081                         return ret;
14082         }
14083         return 0;
14084 }
14085
14086 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
14087         .validate = flow_dv_validate,
14088         .prepare = flow_dv_prepare,
14089         .translate = flow_dv_translate,
14090         .apply = flow_dv_apply,
14091         .remove = flow_dv_remove,
14092         .destroy = flow_dv_destroy,
14093         .query = flow_dv_query,
14094         .create_mtr_tbls = flow_dv_create_mtr_tbl,
14095         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
14096         .create_policer_rules = flow_dv_create_policer_rules,
14097         .destroy_policer_rules = flow_dv_destroy_policer_rules,
14098         .counter_alloc = flow_dv_counter_allocate,
14099         .counter_free = flow_dv_counter_free,
14100         .counter_query = flow_dv_counter_query,
14101         .get_aged_flows = flow_get_aged_flows,
14102         .action_validate = flow_dv_action_validate,
14103         .action_create = flow_dv_action_create,
14104         .action_destroy = flow_dv_action_destroy,
14105         .action_update = flow_dv_action_update,
14106         .action_query = flow_dv_action_query,
14107         .sync_domain = flow_dv_sync_domain,
14108 };
14109
14110 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
14111