drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                       uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84
  85 /**
  86  * Initialize flow attributes structure according to flow items' types.
  87  *
  88  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  89  * mode. For tunnel mode, the items to be modified are the outermost ones.
  90  *
  91  * @param[in] item
  92  *   Pointer to item specification.
  93  * @param[out] attr
  94  *   Pointer to flow attributes structure.
  95  * @param[in] dev_flow
  96  *   Pointer to the sub flow.
  97  * @param[in] tunnel_decap
  98  *   Whether action is after tunnel decapsulation.
  99  */
 100 static void
 101 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 102                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 103 {
 104         uint64_t layers = dev_flow->handle->layers;
 105
 106         /*
 107          * If layers is already initialized, it means this dev_flow is the
 108          * suffix flow, the layers flags is set by the prefix flow. Need to
 109          * use the layer flags from prefix flow as the suffix flow may not
 110          * have the user defined items as the flow is split.
 111          */
 112         if (layers) {
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 114                         attr->ipv4 = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 116                         attr->ipv6 = 1;
 117                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 118                         attr->tcp = 1;
 119                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 120                         attr->udp = 1;
 121                 attr->valid = 1;
 122                 return;
 123         }
 124         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 125                 uint8_t next_protocol = 0xff;
 126                 switch (item->type) {
 127                 case RTE_FLOW_ITEM_TYPE_GRE:
 128                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 129                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 130                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 131                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 132                 case RTE_FLOW_ITEM_TYPE_MPLS:
 133                         if (tunnel_decap)
 134                                 attr->attr = 0;
 135                         break;
 136                 case RTE_FLOW_ITEM_TYPE_IPV4:
 137                         if (!attr->ipv6)
 138                                 attr->ipv4 = 1;
 139                         if (item->mask != NULL &&
 140                             ((const struct rte_flow_item_ipv4 *)
 141                             item->mask)->hdr.next_proto_id)
 142                                 next_protocol =
 143                                     ((const struct rte_flow_item_ipv4 *)
 144                                       (item->spec))->hdr.next_proto_id &
 145                                     ((const struct rte_flow_item_ipv4 *)
 146                                       (item->mask))->hdr.next_proto_id;
 147                         if ((next_protocol == IPPROTO_IPIP ||
 148                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 149                                 attr->attr = 0;
 150                         break;
 151                 case RTE_FLOW_ITEM_TYPE_IPV6:
 152                         if (!attr->ipv4)
 153                                 attr->ipv6 = 1;
 154                         if (item->mask != NULL &&
 155                             ((const struct rte_flow_item_ipv6 *)
 156                             item->mask)->hdr.proto)
 157                                 next_protocol =
 158                                     ((const struct rte_flow_item_ipv6 *)
 159                                       (item->spec))->hdr.proto &
 160                                     ((const struct rte_flow_item_ipv6 *)
 161                                       (item->mask))->hdr.proto;
 162                         if ((next_protocol == IPPROTO_IPIP ||
 163                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 164                                 attr->attr = 0;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_UDP:
 167                         if (!attr->tcp)
 168                                 attr->udp = 1;
 169                         break;
 170                 case RTE_FLOW_ITEM_TYPE_TCP:
 171                         if (!attr->udp)
 172                                 attr->tcp = 1;
 173                         break;
 174                 default:
 175                         break;
 176                 }
 177         }
 178         attr->valid = 1;
 179 }
 180
 181 /**
 182  * Convert rte_mtr_color to mlx5 color.
 183  *
 184  * @param[in] rcol
 185  *   rte_mtr_color.
 186  *
 187  * @return
 188  *   mlx5 color.
 189  */
 190 static int
 191 rte_col_2_mlx5_col(enum rte_color rcol)
 192 {
 193         switch (rcol) {
 194         case RTE_COLOR_GREEN:
 195                 return MLX5_FLOW_COLOR_GREEN;
 196         case RTE_COLOR_YELLOW:
 197                 return MLX5_FLOW_COLOR_YELLOW;
 198         case RTE_COLOR_RED:
 199                 return MLX5_FLOW_COLOR_RED;
 200         default:
 201                 break;
 202         }
 203         return MLX5_FLOW_COLOR_UNDEFINED;
 204 }
 205
 206 struct field_modify_info {
 207         uint32_t size; /* Size of field in protocol header, in bytes. */
 208         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 209         enum mlx5_modification_field id;
 210 };
 211
 212 struct field_modify_info modify_eth[] = {
 213         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 214         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 215         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 216         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 217         {0, 0, 0},
 218 };
 219
 220 struct field_modify_info modify_vlan_out_first_vid[] = {
 221         /* Size in bits !!! */
 222         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_ipv4[] = {
 227         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 228         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 229         {4, 12, MLX5_MODI_OUT_SIPV4},
 230         {4, 16, MLX5_MODI_OUT_DIPV4},
 231         {0, 0, 0},
 232 };
 233
 234 struct field_modify_info modify_ipv6[] = {
 235         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 236         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 237         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 238         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 239         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 240         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 241         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 242         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 243         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 244         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 245         {0, 0, 0},
 246 };
 247
 248 struct field_modify_info modify_udp[] = {
 249         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 250         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_tcp[] = {
 255         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 257         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 258         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 259         {0, 0, 0},
 260 };
 261
 262 static void
 263 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 264                           uint8_t next_protocol, uint64_t *item_flags,
 265                           int *tunnel)
 266 {
 267         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 268                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 269         if (next_protocol == IPPROTO_IPIP) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 271                 *tunnel = 1;
 272         }
 273         if (next_protocol == IPPROTO_IPV6) {
 274                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 275                 *tunnel = 1;
 276         }
 277 }
 278
 279 /**
 280  * Acquire the synchronizing object to protect multithreaded access
 281  * to shared dv context. Lock occurs only if context is actually
 282  * shared, i.e. we have multiport IB device and representors are
 283  * created.
 284  *
 285  * @param[in] dev
 286  *   Pointer to the rte_eth_dev structure.
 287  */
 288 static void
 289 flow_dv_shared_lock(struct rte_eth_dev *dev)
 290 {
 291         struct mlx5_priv *priv = dev->data->dev_private;
 292         struct mlx5_dev_ctx_shared *sh = priv->sh;
 293
 294         if (sh->refcnt > 1) {
 295                 int ret;
 296
 297                 ret = pthread_mutex_lock(&sh->dv_mutex);
 298                 MLX5_ASSERT(!ret);
 299                 (void)ret;
 300         }
 301 }
 302
 303 static void
 304 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 305 {
 306         struct mlx5_priv *priv = dev->data->dev_private;
 307         struct mlx5_dev_ctx_shared *sh = priv->sh;
 308
 309         if (sh->refcnt > 1) {
 310                 int ret;
 311
 312                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 313                 MLX5_ASSERT(!ret);
 314                 (void)ret;
 315         }
 316 }
 317
 318 /* Update VLAN's VID/PCP based on input rte_flow_action.
 319  *
 320  * @param[in] action
 321  *   Pointer to struct rte_flow_action.
 322  * @param[out] vlan
 323  *   Pointer to struct rte_vlan_hdr.
 324  */
 325 static void
 326 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 327                          struct rte_vlan_hdr *vlan)
 328 {
 329         uint16_t vlan_tci;
 330         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 331                 vlan_tci =
 332                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 333                                                action->conf)->vlan_pcp;
 334                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 335                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 336                 vlan->vlan_tci |= vlan_tci;
 337         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 338                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 339                 vlan->vlan_tci |= rte_be_to_cpu_16
 340                     (((const struct rte_flow_action_of_set_vlan_vid *)
 341                                              action->conf)->vlan_vid);
 342         }
 343 }
 344
 345 /**
 346  * Fetch 1, 2, 3 or 4 byte field from the byte array
 347  * and return as unsigned integer in host-endian format.
 348  *
 349  * @param[in] data
 350  *   Pointer to data array.
 351  * @param[in] size
 352  *   Size of field to extract.
 353  *
 354  * @return
 355  *   converted field in host endian format.
 356  */
 357 static inline uint32_t
 358 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 359 {
 360         uint32_t ret;
 361
 362         switch (size) {
 363         case 1:
 364                 ret = *data;
 365                 break;
 366         case 2:
 367                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 368                 break;
 369         case 3:
 370                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 371                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 372                 break;
 373         case 4:
 374                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 375                 break;
 376         default:
 377                 MLX5_ASSERT(false);
 378                 ret = 0;
 379                 break;
 380         }
 381         return ret;
 382 }
 383
 384 /**
 385  * Convert modify-header action to DV specification.
 386  *
 387  * Data length of each action is determined by provided field description
 388  * and the item mask. Data bit offset and width of each action is determined
 389  * by provided item mask.
 390  *
 391  * @param[in] item
 392  *   Pointer to item specification.
 393  * @param[in] field
 394  *   Pointer to field modification information.
 395  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 396  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 397  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 398  * @param[in] dcopy
 399  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 400  *   Negative offset value sets the same offset as source offset.
 401  *   size field is ignored, value is taken from source field.
 402  * @param[in,out] resource
 403  *   Pointer to the modify-header resource.
 404  * @param[in] type
 405  *   Type of modification.
 406  * @param[out] error
 407  *   Pointer to the error structure.
 408  *
 409  * @return
 410  *   0 on success, a negative errno value otherwise and rte_errno is set.
 411  */
 412 static int
 413 flow_dv_convert_modify_action(struct rte_flow_item *item,
 414                               struct field_modify_info *field,
 415                               struct field_modify_info *dcopy,
 416                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 417                               uint32_t type, struct rte_flow_error *error)
 418 {
 419         uint32_t i = resource->actions_num;
 420         struct mlx5_modification_cmd *actions = resource->actions;
 421
 422         /*
 423          * The item and mask are provided in big-endian format.
 424          * The fields should be presented as in big-endian format either.
 425          * Mask must be always present, it defines the actual field width.
 426          */
 427         MLX5_ASSERT(item->mask);
 428         MLX5_ASSERT(field->size);
 429         do {
 430                 unsigned int size_b;
 431                 unsigned int off_b;
 432                 uint32_t mask;
 433                 uint32_t data;
 434
 435                 if (i >= MLX5_MAX_MODIFY_NUM)
 436                         return rte_flow_error_set(error, EINVAL,
 437                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 438                                  "too many items to modify");
 439                 /* Fetch variable byte size mask from the array. */
 440                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 441                                            field->offset, field->size);
 442                 if (!mask) {
 443                         ++field;
 444                         continue;
 445                 }
 446                 /* Deduce actual data width in bits from mask value. */
 447                 off_b = rte_bsf32(mask);
 448                 size_b = sizeof(uint32_t) * CHAR_BIT -
 449                          off_b - __builtin_clz(mask);
 450                 MLX5_ASSERT(size_b);
 451                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 452                 actions[i] = (struct mlx5_modification_cmd) {
 453                         .action_type = type,
 454                         .field = field->id,
 455                         .offset = off_b,
 456                         .length = size_b,
 457                 };
 458                 /* Convert entire record to expected big-endian format. */
 459                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 460                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 461                         MLX5_ASSERT(dcopy);
 462                         actions[i].dst_field = dcopy->id;
 463                         actions[i].dst_offset =
 464                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 465                         /* Convert entire record to big-endian format. */
 466                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 467                 } else {
 468                         MLX5_ASSERT(item->spec);
 469                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 470                                                    field->offset, field->size);
 471                         /* Shift out the trailing masked bits from data. */
 472                         data = (data & mask) >> off_b;
 473                         actions[i].data1 = rte_cpu_to_be_32(data);
 474                 }
 475                 ++i;
 476                 ++field;
 477         } while (field->size);
 478         if (resource->actions_num == i)
 479                 return rte_flow_error_set(error, EINVAL,
 480                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 481                                           "invalid modification flow item");
 482         resource->actions_num = i;
 483         return 0;
 484 }
 485
 486 /**
 487  * Convert modify-header set IPv4 address action to DV specification.
 488  *
 489  * @param[in,out] resource
 490  *   Pointer to the modify-header resource.
 491  * @param[in] action
 492  *   Pointer to action specification.
 493  * @param[out] error
 494  *   Pointer to the error structure.
 495  *
 496  * @return
 497  *   0 on success, a negative errno value otherwise and rte_errno is set.
 498  */
 499 static int
 500 flow_dv_convert_action_modify_ipv4
 501                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 502                          const struct rte_flow_action *action,
 503                          struct rte_flow_error *error)
 504 {
 505         const struct rte_flow_action_set_ipv4 *conf =
 506                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 507         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 508         struct rte_flow_item_ipv4 ipv4;
 509         struct rte_flow_item_ipv4 ipv4_mask;
 510
 511         memset(&ipv4, 0, sizeof(ipv4));
 512         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 513         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 514                 ipv4.hdr.src_addr = conf->ipv4_addr;
 515                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 516         } else {
 517                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 518                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 519         }
 520         item.spec = &ipv4;
 521         item.mask = &ipv4_mask;
 522         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 523                                              MLX5_MODIFICATION_TYPE_SET, error);
 524 }
 525
 526 /**
 527  * Convert modify-header set IPv6 address action to DV specification.
 528  *
 529  * @param[in,out] resource
 530  *   Pointer to the modify-header resource.
 531  * @param[in] action
 532  *   Pointer to action specification.
 533  * @param[out] error
 534  *   Pointer to the error structure.
 535  *
 536  * @return
 537  *   0 on success, a negative errno value otherwise and rte_errno is set.
 538  */
 539 static int
 540 flow_dv_convert_action_modify_ipv6
 541                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 542                          const struct rte_flow_action *action,
 543                          struct rte_flow_error *error)
 544 {
 545         const struct rte_flow_action_set_ipv6 *conf =
 546                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 547         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 548         struct rte_flow_item_ipv6 ipv6;
 549         struct rte_flow_item_ipv6 ipv6_mask;
 550
 551         memset(&ipv6, 0, sizeof(ipv6));
 552         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 553         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 554                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 555                        sizeof(ipv6.hdr.src_addr));
 556                 memcpy(&ipv6_mask.hdr.src_addr,
 557                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 558                        sizeof(ipv6.hdr.src_addr));
 559         } else {
 560                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 561                        sizeof(ipv6.hdr.dst_addr));
 562                 memcpy(&ipv6_mask.hdr.dst_addr,
 563                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 564                        sizeof(ipv6.hdr.dst_addr));
 565         }
 566         item.spec = &ipv6;
 567         item.mask = &ipv6_mask;
 568         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 569                                              MLX5_MODIFICATION_TYPE_SET, error);
 570 }
 571
 572 /**
 573  * Convert modify-header set MAC address action to DV specification.
 574  *
 575  * @param[in,out] resource
 576  *   Pointer to the modify-header resource.
 577  * @param[in] action
 578  *   Pointer to action specification.
 579  * @param[out] error
 580  *   Pointer to the error structure.
 581  *
 582  * @return
 583  *   0 on success, a negative errno value otherwise and rte_errno is set.
 584  */
 585 static int
 586 flow_dv_convert_action_modify_mac
 587                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 588                          const struct rte_flow_action *action,
 589                          struct rte_flow_error *error)
 590 {
 591         const struct rte_flow_action_set_mac *conf =
 592                 (const struct rte_flow_action_set_mac *)(action->conf);
 593         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 594         struct rte_flow_item_eth eth;
 595         struct rte_flow_item_eth eth_mask;
 596
 597         memset(&eth, 0, sizeof(eth));
 598         memset(&eth_mask, 0, sizeof(eth_mask));
 599         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 600                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 601                        sizeof(eth.src.addr_bytes));
 602                 memcpy(&eth_mask.src.addr_bytes,
 603                        &rte_flow_item_eth_mask.src.addr_bytes,
 604                        sizeof(eth_mask.src.addr_bytes));
 605         } else {
 606                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 607                        sizeof(eth.dst.addr_bytes));
 608                 memcpy(&eth_mask.dst.addr_bytes,
 609                        &rte_flow_item_eth_mask.dst.addr_bytes,
 610                        sizeof(eth_mask.dst.addr_bytes));
 611         }
 612         item.spec = &eth;
 613         item.mask = &eth_mask;
 614         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 615                                              MLX5_MODIFICATION_TYPE_SET, error);
 616 }
 617
 618 /**
 619  * Convert modify-header set VLAN VID action to DV specification.
 620  *
 621  * @param[in,out] resource
 622  *   Pointer to the modify-header resource.
 623  * @param[in] action
 624  *   Pointer to action specification.
 625  * @param[out] error
 626  *   Pointer to the error structure.
 627  *
 628  * @return
 629  *   0 on success, a negative errno value otherwise and rte_errno is set.
 630  */
 631 static int
 632 flow_dv_convert_action_modify_vlan_vid
 633                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 634                          const struct rte_flow_action *action,
 635                          struct rte_flow_error *error)
 636 {
 637         const struct rte_flow_action_of_set_vlan_vid *conf =
 638                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 639         int i = resource->actions_num;
 640         struct mlx5_modification_cmd *actions = resource->actions;
 641         struct field_modify_info *field = modify_vlan_out_first_vid;
 642
 643         if (i >= MLX5_MAX_MODIFY_NUM)
 644                 return rte_flow_error_set(error, EINVAL,
 645                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 646                          "too many items to modify");
 647         actions[i] = (struct mlx5_modification_cmd) {
 648                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 649                 .field = field->id,
 650                 .length = field->size,
 651                 .offset = field->offset,
 652         };
 653         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 654         actions[i].data1 = conf->vlan_vid;
 655         actions[i].data1 = actions[i].data1 << 16;
 656         resource->actions_num = ++i;
 657         return 0;
 658 }
 659
 660 /**
 661  * Convert modify-header set TP action to DV specification.
 662  *
 663  * @param[in,out] resource
 664  *   Pointer to the modify-header resource.
 665  * @param[in] action
 666  *   Pointer to action specification.
 667  * @param[in] items
 668  *   Pointer to rte_flow_item objects list.
 669  * @param[in] attr
 670  *   Pointer to flow attributes structure.
 671  * @param[in] dev_flow
 672  *   Pointer to the sub flow.
 673  * @param[in] tunnel_decap
 674  *   Whether action is after tunnel decapsulation.
 675  * @param[out] error
 676  *   Pointer to the error structure.
 677  *
 678  * @return
 679  *   0 on success, a negative errno value otherwise and rte_errno is set.
 680  */
 681 static int
 682 flow_dv_convert_action_modify_tp
 683                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 684                          const struct rte_flow_action *action,
 685                          const struct rte_flow_item *items,
 686                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 687                          bool tunnel_decap, struct rte_flow_error *error)
 688 {
 689         const struct rte_flow_action_set_tp *conf =
 690                 (const struct rte_flow_action_set_tp *)(action->conf);
 691         struct rte_flow_item item;
 692         struct rte_flow_item_udp udp;
 693         struct rte_flow_item_udp udp_mask;
 694         struct rte_flow_item_tcp tcp;
 695         struct rte_flow_item_tcp tcp_mask;
 696         struct field_modify_info *field;
 697
 698         if (!attr->valid)
 699                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 700         if (attr->udp) {
 701                 memset(&udp, 0, sizeof(udp));
 702                 memset(&udp_mask, 0, sizeof(udp_mask));
 703                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 704                         udp.hdr.src_port = conf->port;
 705                         udp_mask.hdr.src_port =
 706                                         rte_flow_item_udp_mask.hdr.src_port;
 707                 } else {
 708                         udp.hdr.dst_port = conf->port;
 709                         udp_mask.hdr.dst_port =
 710                                         rte_flow_item_udp_mask.hdr.dst_port;
 711                 }
 712                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 713                 item.spec = &udp;
 714                 item.mask = &udp_mask;
 715                 field = modify_udp;
 716         } else {
 717                 MLX5_ASSERT(attr->tcp);
 718                 memset(&tcp, 0, sizeof(tcp));
 719                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 720                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 721                         tcp.hdr.src_port = conf->port;
 722                         tcp_mask.hdr.src_port =
 723                                         rte_flow_item_tcp_mask.hdr.src_port;
 724                 } else {
 725                         tcp.hdr.dst_port = conf->port;
 726                         tcp_mask.hdr.dst_port =
 727                                         rte_flow_item_tcp_mask.hdr.dst_port;
 728                 }
 729                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 730                 item.spec = &tcp;
 731                 item.mask = &tcp_mask;
 732                 field = modify_tcp;
 733         }
 734         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 735                                              MLX5_MODIFICATION_TYPE_SET, error);
 736 }
 737
 738 /**
 739  * Convert modify-header set TTL action to DV specification.
 740  *
 741  * @param[in,out] resource
 742  *   Pointer to the modify-header resource.
 743  * @param[in] action
 744  *   Pointer to action specification.
 745  * @param[in] items
 746  *   Pointer to rte_flow_item objects list.
 747  * @param[in] attr
 748  *   Pointer to flow attributes structure.
 749  * @param[in] dev_flow
 750  *   Pointer to the sub flow.
 751  * @param[in] tunnel_decap
 752  *   Whether action is after tunnel decapsulation.
 753  * @param[out] error
 754  *   Pointer to the error structure.
 755  *
 756  * @return
 757  *   0 on success, a negative errno value otherwise and rte_errno is set.
 758  */
 759 static int
 760 flow_dv_convert_action_modify_ttl
 761                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 762                          const struct rte_flow_action *action,
 763                          const struct rte_flow_item *items,
 764                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 765                          bool tunnel_decap, struct rte_flow_error *error)
 766 {
 767         const struct rte_flow_action_set_ttl *conf =
 768                 (const struct rte_flow_action_set_ttl *)(action->conf);
 769         struct rte_flow_item item;
 770         struct rte_flow_item_ipv4 ipv4;
 771         struct rte_flow_item_ipv4 ipv4_mask;
 772         struct rte_flow_item_ipv6 ipv6;
 773         struct rte_flow_item_ipv6 ipv6_mask;
 774         struct field_modify_info *field;
 775
 776         if (!attr->valid)
 777                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 778         if (attr->ipv4) {
 779                 memset(&ipv4, 0, sizeof(ipv4));
 780                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 781                 ipv4.hdr.time_to_live = conf->ttl_value;
 782                 ipv4_mask.hdr.time_to_live = 0xFF;
 783                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 784                 item.spec = &ipv4;
 785                 item.mask = &ipv4_mask;
 786                 field = modify_ipv4;
 787         } else {
 788                 MLX5_ASSERT(attr->ipv6);
 789                 memset(&ipv6, 0, sizeof(ipv6));
 790                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 791                 ipv6.hdr.hop_limits = conf->ttl_value;
 792                 ipv6_mask.hdr.hop_limits = 0xFF;
 793                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 794                 item.spec = &ipv6;
 795                 item.mask = &ipv6_mask;
 796                 field = modify_ipv6;
 797         }
 798         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 799                                              MLX5_MODIFICATION_TYPE_SET, error);
 800 }
 801
 802 /**
 803  * Convert modify-header decrement TTL action to DV specification.
 804  *
 805  * @param[in,out] resource
 806  *   Pointer to the modify-header resource.
 807  * @param[in] action
 808  *   Pointer to action specification.
 809  * @param[in] items
 810  *   Pointer to rte_flow_item objects list.
 811  * @param[in] attr
 812  *   Pointer to flow attributes structure.
 813  * @param[in] dev_flow
 814  *   Pointer to the sub flow.
 815  * @param[in] tunnel_decap
 816  *   Whether action is after tunnel decapsulation.
 817  * @param[out] error
 818  *   Pointer to the error structure.
 819  *
 820  * @return
 821  *   0 on success, a negative errno value otherwise and rte_errno is set.
 822  */
 823 static int
 824 flow_dv_convert_action_modify_dec_ttl
 825                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 826                          const struct rte_flow_item *items,
 827                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 828                          bool tunnel_decap, struct rte_flow_error *error)
 829 {
 830         struct rte_flow_item item;
 831         struct rte_flow_item_ipv4 ipv4;
 832         struct rte_flow_item_ipv4 ipv4_mask;
 833         struct rte_flow_item_ipv6 ipv6;
 834         struct rte_flow_item_ipv6 ipv6_mask;
 835         struct field_modify_info *field;
 836
 837         if (!attr->valid)
 838                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 839         if (attr->ipv4) {
 840                 memset(&ipv4, 0, sizeof(ipv4));
 841                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 842                 ipv4.hdr.time_to_live = 0xFF;
 843                 ipv4_mask.hdr.time_to_live = 0xFF;
 844                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 845                 item.spec = &ipv4;
 846                 item.mask = &ipv4_mask;
 847                 field = modify_ipv4;
 848         } else {
 849                 MLX5_ASSERT(attr->ipv6);
 850                 memset(&ipv6, 0, sizeof(ipv6));
 851                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 852                 ipv6.hdr.hop_limits = 0xFF;
 853                 ipv6_mask.hdr.hop_limits = 0xFF;
 854                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 855                 item.spec = &ipv6;
 856                 item.mask = &ipv6_mask;
 857                 field = modify_ipv6;
 858         }
 859         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 860                                              MLX5_MODIFICATION_TYPE_ADD, error);
 861 }
 862
 863 /**
 864  * Convert modify-header increment/decrement TCP Sequence number
 865  * to DV specification.
 866  *
 867  * @param[in,out] resource
 868  *   Pointer to the modify-header resource.
 869  * @param[in] action
 870  *   Pointer to action specification.
 871  * @param[out] error
 872  *   Pointer to the error structure.
 873  *
 874  * @return
 875  *   0 on success, a negative errno value otherwise and rte_errno is set.
 876  */
 877 static int
 878 flow_dv_convert_action_modify_tcp_seq
 879                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 880                          const struct rte_flow_action *action,
 881                          struct rte_flow_error *error)
 882 {
 883         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 884         uint64_t value = rte_be_to_cpu_32(*conf);
 885         struct rte_flow_item item;
 886         struct rte_flow_item_tcp tcp;
 887         struct rte_flow_item_tcp tcp_mask;
 888
 889         memset(&tcp, 0, sizeof(tcp));
 890         memset(&tcp_mask, 0, sizeof(tcp_mask));
 891         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 892                 /*
 893                  * The HW has no decrement operation, only increment operation.
 894                  * To simulate decrement X from Y using increment operation
 895                  * we need to add UINT32_MAX X times to Y.
 896                  * Each adding of UINT32_MAX decrements Y by 1.
 897                  */
 898                 value *= UINT32_MAX;
 899         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 900         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 901         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 902         item.spec = &tcp;
 903         item.mask = &tcp_mask;
 904         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 905                                              MLX5_MODIFICATION_TYPE_ADD, error);
 906 }
 907
 908 /**
 909  * Convert modify-header increment/decrement TCP Acknowledgment number
 910  * to DV specification.
 911  *
 912  * @param[in,out] resource
 913  *   Pointer to the modify-header resource.
 914  * @param[in] action
 915  *   Pointer to action specification.
 916  * @param[out] error
 917  *   Pointer to the error structure.
 918  *
 919  * @return
 920  *   0 on success, a negative errno value otherwise and rte_errno is set.
 921  */
 922 static int
 923 flow_dv_convert_action_modify_tcp_ack
 924                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 925                          const struct rte_flow_action *action,
 926                          struct rte_flow_error *error)
 927 {
 928         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 929         uint64_t value = rte_be_to_cpu_32(*conf);
 930         struct rte_flow_item item;
 931         struct rte_flow_item_tcp tcp;
 932         struct rte_flow_item_tcp tcp_mask;
 933
 934         memset(&tcp, 0, sizeof(tcp));
 935         memset(&tcp_mask, 0, sizeof(tcp_mask));
 936         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 937                 /*
 938                  * The HW has no decrement operation, only increment operation.
 939                  * To simulate decrement X from Y using increment operation
 940                  * we need to add UINT32_MAX X times to Y.
 941                  * Each adding of UINT32_MAX decrements Y by 1.
 942                  */
 943                 value *= UINT32_MAX;
 944         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 945         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 946         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 947         item.spec = &tcp;
 948         item.mask = &tcp_mask;
 949         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 950                                              MLX5_MODIFICATION_TYPE_ADD, error);
 951 }
 952
 953 static enum mlx5_modification_field reg_to_field[] = {
 954         [REG_NON] = MLX5_MODI_OUT_NONE,
 955         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 956         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 957         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 958         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 959         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 960         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 961         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 962         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 963         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 964         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 965 };
 966
 967 /**
 968  * Convert register set to DV specification.
 969  *
 970  * @param[in,out] resource
 971  *   Pointer to the modify-header resource.
 972  * @param[in] action
 973  *   Pointer to action specification.
 974  * @param[out] error
 975  *   Pointer to the error structure.
 976  *
 977  * @return
 978  *   0 on success, a negative errno value otherwise and rte_errno is set.
 979  */
 980 static int
 981 flow_dv_convert_action_set_reg
 982                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 983                          const struct rte_flow_action *action,
 984                          struct rte_flow_error *error)
 985 {
 986         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 987         struct mlx5_modification_cmd *actions = resource->actions;
 988         uint32_t i = resource->actions_num;
 989
 990         if (i >= MLX5_MAX_MODIFY_NUM)
 991                 return rte_flow_error_set(error, EINVAL,
 992                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 993                                           "too many items to modify");
 994         MLX5_ASSERT(conf->id != REG_NON);
 995         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 996         actions[i] = (struct mlx5_modification_cmd) {
 997                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 998                 .field = reg_to_field[conf->id],
 999         };
1000         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1001         actions[i].data1 = rte_cpu_to_be_32(conf->data);
1002         ++i;
1003         resource->actions_num = i;
1004         return 0;
1005 }
1006
1007 /**
1008  * Convert SET_TAG action to DV specification.
1009  *
1010  * @param[in] dev
1011  *   Pointer to the rte_eth_dev structure.
1012  * @param[in,out] resource
1013  *   Pointer to the modify-header resource.
1014  * @param[in] conf
1015  *   Pointer to action specification.
1016  * @param[out] error
1017  *   Pointer to the error structure.
1018  *
1019  * @return
1020  *   0 on success, a negative errno value otherwise and rte_errno is set.
1021  */
1022 static int
1023 flow_dv_convert_action_set_tag
1024                         (struct rte_eth_dev *dev,
1025                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1026                          const struct rte_flow_action_set_tag *conf,
1027                          struct rte_flow_error *error)
1028 {
1029         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1030         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1031         struct rte_flow_item item = {
1032                 .spec = &data,
1033                 .mask = &mask,
1034         };
1035         struct field_modify_info reg_c_x[] = {
1036                 [1] = {0, 0, 0},
1037         };
1038         enum mlx5_modification_field reg_type;
1039         int ret;
1040
1041         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1042         if (ret < 0)
1043                 return ret;
1044         MLX5_ASSERT(ret != REG_NON);
1045         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1046         reg_type = reg_to_field[ret];
1047         MLX5_ASSERT(reg_type > 0);
1048         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1049         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1050                                              MLX5_MODIFICATION_TYPE_SET, error);
1051 }
1052
1053 /**
1054  * Convert internal COPY_REG action to DV specification.
1055  *
1056  * @param[in] dev
1057  *   Pointer to the rte_eth_dev structure.
1058  * @param[in,out] res
1059  *   Pointer to the modify-header resource.
1060  * @param[in] action
1061  *   Pointer to action specification.
1062  * @param[out] error
1063  *   Pointer to the error structure.
1064  *
1065  * @return
1066  *   0 on success, a negative errno value otherwise and rte_errno is set.
1067  */
1068 static int
1069 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1070                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1071                                  const struct rte_flow_action *action,
1072                                  struct rte_flow_error *error)
1073 {
1074         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1075         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1076         struct rte_flow_item item = {
1077                 .spec = NULL,
1078                 .mask = &mask,
1079         };
1080         struct field_modify_info reg_src[] = {
1081                 {4, 0, reg_to_field[conf->src]},
1082                 {0, 0, 0},
1083         };
1084         struct field_modify_info reg_dst = {
1085                 .offset = 0,
1086                 .id = reg_to_field[conf->dst],
1087         };
1088         /* Adjust reg_c[0] usage according to reported mask. */
1089         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1090                 struct mlx5_priv *priv = dev->data->dev_private;
1091                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1092
1093                 MLX5_ASSERT(reg_c0);
1094                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1095                 if (conf->dst == REG_C_0) {
1096                         /* Copy to reg_c[0], within mask only. */
1097                         reg_dst.offset = rte_bsf32(reg_c0);
1098                         /*
1099                          * Mask is ignoring the enianness, because
1100                          * there is no conversion in datapath.
1101                          */
1102 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1103                         /* Copy from destination lower bits to reg_c[0]. */
1104                         mask = reg_c0 >> reg_dst.offset;
1105 #else
1106                         /* Copy from destination upper bits to reg_c[0]. */
1107                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1108                                           rte_fls_u32(reg_c0));
1109 #endif
1110                 } else {
1111                         mask = rte_cpu_to_be_32(reg_c0);
1112 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1113                         /* Copy from reg_c[0] to destination lower bits. */
1114                         reg_dst.offset = 0;
1115 #else
1116                         /* Copy from reg_c[0] to destination upper bits. */
1117                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1118                                          (rte_fls_u32(reg_c0) -
1119                                           rte_bsf32(reg_c0));
1120 #endif
1121                 }
1122         }
1123         return flow_dv_convert_modify_action(&item,
1124                                              reg_src, &reg_dst, res,
1125                                              MLX5_MODIFICATION_TYPE_COPY,
1126                                              error);
1127 }
1128
1129 /**
1130  * Convert MARK action to DV specification. This routine is used
1131  * in extensive metadata only and requires metadata register to be
1132  * handled. In legacy mode hardware tag resource is engaged.
1133  *
1134  * @param[in] dev
1135  *   Pointer to the rte_eth_dev structure.
1136  * @param[in] conf
1137  *   Pointer to MARK action specification.
1138  * @param[in,out] resource
1139  *   Pointer to the modify-header resource.
1140  * @param[out] error
1141  *   Pointer to the error structure.
1142  *
1143  * @return
1144  *   0 on success, a negative errno value otherwise and rte_errno is set.
1145  */
1146 static int
1147 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1148                             const struct rte_flow_action_mark *conf,
1149                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1150                             struct rte_flow_error *error)
1151 {
1152         struct mlx5_priv *priv = dev->data->dev_private;
1153         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1154                                            priv->sh->dv_mark_mask);
1155         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1156         struct rte_flow_item item = {
1157                 .spec = &data,
1158                 .mask = &mask,
1159         };
1160         struct field_modify_info reg_c_x[] = {
1161                 [1] = {0, 0, 0},
1162         };
1163         int reg;
1164
1165         if (!mask)
1166                 return rte_flow_error_set(error, EINVAL,
1167                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1168                                           NULL, "zero mark action mask");
1169         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1170         if (reg < 0)
1171                 return reg;
1172         MLX5_ASSERT(reg > 0);
1173         if (reg == REG_C_0) {
1174                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1175                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1176
1177                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1178                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1179                 mask = rte_cpu_to_be_32(mask << shl_c0);
1180         }
1181         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1182         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1183                                              MLX5_MODIFICATION_TYPE_SET, error);
1184 }
1185
1186 /**
1187  * Get metadata register index for specified steering domain.
1188  *
1189  * @param[in] dev
1190  *   Pointer to the rte_eth_dev structure.
1191  * @param[in] attr
1192  *   Attributes of flow to determine steering domain.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   positive index on success, a negative errno value otherwise
1198  *   and rte_errno is set.
1199  */
1200 static enum modify_reg
1201 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1202                          const struct rte_flow_attr *attr,
1203                          struct rte_flow_error *error)
1204 {
1205         int reg =
1206                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1207                                           MLX5_METADATA_FDB :
1208                                             attr->egress ?
1209                                             MLX5_METADATA_TX :
1210                                             MLX5_METADATA_RX, 0, error);
1211         if (reg < 0)
1212                 return rte_flow_error_set(error,
1213                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1214                                           NULL, "unavailable "
1215                                           "metadata register");
1216         return reg;
1217 }
1218
1219 /**
1220  * Convert SET_META action to DV specification.
1221  *
1222  * @param[in] dev
1223  *   Pointer to the rte_eth_dev structure.
1224  * @param[in,out] resource
1225  *   Pointer to the modify-header resource.
1226  * @param[in] attr
1227  *   Attributes of flow that includes this item.
1228  * @param[in] conf
1229  *   Pointer to action specification.
1230  * @param[out] error
1231  *   Pointer to the error structure.
1232  *
1233  * @return
1234  *   0 on success, a negative errno value otherwise and rte_errno is set.
1235  */
1236 static int
1237 flow_dv_convert_action_set_meta
1238                         (struct rte_eth_dev *dev,
1239                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1240                          const struct rte_flow_attr *attr,
1241                          const struct rte_flow_action_set_meta *conf,
1242                          struct rte_flow_error *error)
1243 {
1244         uint32_t data = conf->data;
1245         uint32_t mask = conf->mask;
1246         struct rte_flow_item item = {
1247                 .spec = &data,
1248                 .mask = &mask,
1249         };
1250         struct field_modify_info reg_c_x[] = {
1251                 [1] = {0, 0, 0},
1252         };
1253         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1254
1255         if (reg < 0)
1256                 return reg;
1257         /*
1258          * In datapath code there is no endianness
1259          * coversions for perfromance reasons, all
1260          * pattern conversions are done in rte_flow.
1261          */
1262         if (reg == REG_C_0) {
1263                 struct mlx5_priv *priv = dev->data->dev_private;
1264                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1265                 uint32_t shl_c0;
1266
1267                 MLX5_ASSERT(msk_c0);
1268 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1269                 shl_c0 = rte_bsf32(msk_c0);
1270 #else
1271                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1272 #endif
1273                 mask <<= shl_c0;
1274                 data <<= shl_c0;
1275                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1276         }
1277         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1278         /* The routine expects parameters in memory as big-endian ones. */
1279         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1280                                              MLX5_MODIFICATION_TYPE_SET, error);
1281 }
1282
1283 /**
1284  * Convert modify-header set IPv4 DSCP action to DV specification.
1285  *
1286  * @param[in,out] resource
1287  *   Pointer to the modify-header resource.
1288  * @param[in] action
1289  *   Pointer to action specification.
1290  * @param[out] error
1291  *   Pointer to the error structure.
1292  *
1293  * @return
1294  *   0 on success, a negative errno value otherwise and rte_errno is set.
1295  */
1296 static int
1297 flow_dv_convert_action_modify_ipv4_dscp
1298                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1299                          const struct rte_flow_action *action,
1300                          struct rte_flow_error *error)
1301 {
1302         const struct rte_flow_action_set_dscp *conf =
1303                 (const struct rte_flow_action_set_dscp *)(action->conf);
1304         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1305         struct rte_flow_item_ipv4 ipv4;
1306         struct rte_flow_item_ipv4 ipv4_mask;
1307
1308         memset(&ipv4, 0, sizeof(ipv4));
1309         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1310         ipv4.hdr.type_of_service = conf->dscp;
1311         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1312         item.spec = &ipv4;
1313         item.mask = &ipv4_mask;
1314         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1315                                              MLX5_MODIFICATION_TYPE_SET, error);
1316 }
1317
1318 /**
1319  * Convert modify-header set IPv6 DSCP action to DV specification.
1320  *
1321  * @param[in,out] resource
1322  *   Pointer to the modify-header resource.
1323  * @param[in] action
1324  *   Pointer to action specification.
1325  * @param[out] error
1326  *   Pointer to the error structure.
1327  *
1328  * @return
1329  *   0 on success, a negative errno value otherwise and rte_errno is set.
1330  */
1331 static int
1332 flow_dv_convert_action_modify_ipv6_dscp
1333                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1334                          const struct rte_flow_action *action,
1335                          struct rte_flow_error *error)
1336 {
1337         const struct rte_flow_action_set_dscp *conf =
1338                 (const struct rte_flow_action_set_dscp *)(action->conf);
1339         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1340         struct rte_flow_item_ipv6 ipv6;
1341         struct rte_flow_item_ipv6 ipv6_mask;
1342
1343         memset(&ipv6, 0, sizeof(ipv6));
1344         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1345         /*
1346          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1347          * rdma-core only accept the DSCP bits byte aligned start from
1348          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1349          * bits in IPv6 case as rdma-core requires byte aligned value.
1350          */
1351         ipv6.hdr.vtc_flow = conf->dscp;
1352         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1353         item.spec = &ipv6;
1354         item.mask = &ipv6_mask;
1355         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1356                                              MLX5_MODIFICATION_TYPE_SET, error);
1357 }
1358
1359 /**
1360  * Validate MARK item.
1361  *
1362  * @param[in] dev
1363  *   Pointer to the rte_eth_dev structure.
1364  * @param[in] item
1365  *   Item specification.
1366  * @param[in] attr
1367  *   Attributes of flow that includes this item.
1368  * @param[out] error
1369  *   Pointer to error structure.
1370  *
1371  * @return
1372  *   0 on success, a negative errno value otherwise and rte_errno is set.
1373  */
1374 static int
1375 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1376                            const struct rte_flow_item *item,
1377                            const struct rte_flow_attr *attr __rte_unused,
1378                            struct rte_flow_error *error)
1379 {
1380         struct mlx5_priv *priv = dev->data->dev_private;
1381         struct mlx5_dev_config *config = &priv->config;
1382         const struct rte_flow_item_mark *spec = item->spec;
1383         const struct rte_flow_item_mark *mask = item->mask;
1384         const struct rte_flow_item_mark nic_mask = {
1385                 .id = priv->sh->dv_mark_mask,
1386         };
1387         int ret;
1388
1389         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1390                 return rte_flow_error_set(error, ENOTSUP,
1391                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1392                                           "extended metadata feature"
1393                                           " isn't enabled");
1394         if (!mlx5_flow_ext_mreg_supported(dev))
1395                 return rte_flow_error_set(error, ENOTSUP,
1396                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1397                                           "extended metadata register"
1398                                           " isn't supported");
1399         if (!nic_mask.id)
1400                 return rte_flow_error_set(error, ENOTSUP,
1401                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1402                                           "extended metadata register"
1403                                           " isn't available");
1404         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1405         if (ret < 0)
1406                 return ret;
1407         if (!spec)
1408                 return rte_flow_error_set(error, EINVAL,
1409                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1410                                           item->spec,
1411                                           "data cannot be empty");
1412         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1413                 return rte_flow_error_set(error, EINVAL,
1414                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1415                                           &spec->id,
1416                                           "mark id exceeds the limit");
1417         if (!mask)
1418                 mask = &nic_mask;
1419         if (!mask->id)
1420                 return rte_flow_error_set(error, EINVAL,
1421                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1422                                         "mask cannot be zero");
1423
1424         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1425                                         (const uint8_t *)&nic_mask,
1426                                         sizeof(struct rte_flow_item_mark),
1427                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1428         if (ret < 0)
1429                 return ret;
1430         return 0;
1431 }
1432
1433 /**
1434  * Validate META item.
1435  *
1436  * @param[in] dev
1437  *   Pointer to the rte_eth_dev structure.
1438  * @param[in] item
1439  *   Item specification.
1440  * @param[in] attr
1441  *   Attributes of flow that includes this item.
1442  * @param[out] error
1443  *   Pointer to error structure.
1444  *
1445  * @return
1446  *   0 on success, a negative errno value otherwise and rte_errno is set.
1447  */
1448 static int
1449 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1450                            const struct rte_flow_item *item,
1451                            const struct rte_flow_attr *attr,
1452                            struct rte_flow_error *error)
1453 {
1454         struct mlx5_priv *priv = dev->data->dev_private;
1455         struct mlx5_dev_config *config = &priv->config;
1456         const struct rte_flow_item_meta *spec = item->spec;
1457         const struct rte_flow_item_meta *mask = item->mask;
1458         struct rte_flow_item_meta nic_mask = {
1459                 .data = UINT32_MAX
1460         };
1461         int reg;
1462         int ret;
1463
1464         if (!spec)
1465                 return rte_flow_error_set(error, EINVAL,
1466                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1467                                           item->spec,
1468                                           "data cannot be empty");
1469         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1470                 if (!mlx5_flow_ext_mreg_supported(dev))
1471                         return rte_flow_error_set(error, ENOTSUP,
1472                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1473                                           "extended metadata register"
1474                                           " isn't supported");
1475                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1476                 if (reg < 0)
1477                         return reg;
1478                 if (reg == REG_B)
1479                         return rte_flow_error_set(error, ENOTSUP,
1480                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1481                                           "match on reg_b "
1482                                           "isn't supported");
1483                 if (reg != REG_A)
1484                         nic_mask.data = priv->sh->dv_meta_mask;
1485         } else if (attr->transfer) {
1486                 return rte_flow_error_set(error, ENOTSUP,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1488                                         "extended metadata feature "
1489                                         "should be enabled when "
1490                                         "meta item is requested "
1491                                         "with e-switch mode ");
1492         }
1493         if (!mask)
1494                 mask = &rte_flow_item_meta_mask;
1495         if (!mask->data)
1496                 return rte_flow_error_set(error, EINVAL,
1497                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1498                                         "mask cannot be zero");
1499
1500         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1501                                         (const uint8_t *)&nic_mask,
1502                                         sizeof(struct rte_flow_item_meta),
1503                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1504         return ret;
1505 }
1506
1507 /**
1508  * Validate TAG item.
1509  *
1510  * @param[in] dev
1511  *   Pointer to the rte_eth_dev structure.
1512  * @param[in] item
1513  *   Item specification.
1514  * @param[in] attr
1515  *   Attributes of flow that includes this item.
1516  * @param[out] error
1517  *   Pointer to error structure.
1518  *
1519  * @return
1520  *   0 on success, a negative errno value otherwise and rte_errno is set.
1521  */
1522 static int
1523 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1524                           const struct rte_flow_item *item,
1525                           const struct rte_flow_attr *attr __rte_unused,
1526                           struct rte_flow_error *error)
1527 {
1528         const struct rte_flow_item_tag *spec = item->spec;
1529         const struct rte_flow_item_tag *mask = item->mask;
1530         const struct rte_flow_item_tag nic_mask = {
1531                 .data = RTE_BE32(UINT32_MAX),
1532                 .index = 0xff,
1533         };
1534         int ret;
1535
1536         if (!mlx5_flow_ext_mreg_supported(dev))
1537                 return rte_flow_error_set(error, ENOTSUP,
1538                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1539                                           "extensive metadata register"
1540                                           " isn't supported");
1541         if (!spec)
1542                 return rte_flow_error_set(error, EINVAL,
1543                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1544                                           item->spec,
1545                                           "data cannot be empty");
1546         if (!mask)
1547                 mask = &rte_flow_item_tag_mask;
1548         if (!mask->data)
1549                 return rte_flow_error_set(error, EINVAL,
1550                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551                                         "mask cannot be zero");
1552
1553         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1554                                         (const uint8_t *)&nic_mask,
1555                                         sizeof(struct rte_flow_item_tag),
1556                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1557         if (ret < 0)
1558                 return ret;
1559         if (mask->index != 0xff)
1560                 return rte_flow_error_set(error, EINVAL,
1561                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1562                                           "partial mask for tag index"
1563                                           " is not supported");
1564         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1565         if (ret < 0)
1566                 return ret;
1567         MLX5_ASSERT(ret != REG_NON);
1568         return 0;
1569 }
1570
1571 /**
1572  * Validate vport item.
1573  *
1574  * @param[in] dev
1575  *   Pointer to the rte_eth_dev structure.
1576  * @param[in] item
1577  *   Item specification.
1578  * @param[in] attr
1579  *   Attributes of flow that includes this item.
1580  * @param[in] item_flags
1581  *   Bit-fields that holds the items detected until now.
1582  * @param[out] error
1583  *   Pointer to error structure.
1584  *
1585  * @return
1586  *   0 on success, a negative errno value otherwise and rte_errno is set.
1587  */
1588 static int
1589 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1590                               const struct rte_flow_item *item,
1591                               const struct rte_flow_attr *attr,
1592                               uint64_t item_flags,
1593                               struct rte_flow_error *error)
1594 {
1595         const struct rte_flow_item_port_id *spec = item->spec;
1596         const struct rte_flow_item_port_id *mask = item->mask;
1597         const struct rte_flow_item_port_id switch_mask = {
1598                         .id = 0xffffffff,
1599         };
1600         struct mlx5_priv *esw_priv;
1601         struct mlx5_priv *dev_priv;
1602         int ret;
1603
1604         if (!attr->transfer)
1605                 return rte_flow_error_set(error, EINVAL,
1606                                           RTE_FLOW_ERROR_TYPE_ITEM,
1607                                           NULL,
1608                                           "match on port id is valid only"
1609                                           " when transfer flag is enabled");
1610         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1611                 return rte_flow_error_set(error, ENOTSUP,
1612                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1613                                           "multiple source ports are not"
1614                                           " supported");
1615         if (!mask)
1616                 mask = &switch_mask;
1617         if (mask->id != 0xffffffff)
1618                 return rte_flow_error_set(error, ENOTSUP,
1619                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1620                                            mask,
1621                                            "no support for partial mask on"
1622                                            " \"id\" field");
1623         ret = mlx5_flow_item_acceptable
1624                                 (item, (const uint8_t *)mask,
1625                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1626                                  sizeof(struct rte_flow_item_port_id),
1627                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1628         if (ret)
1629                 return ret;
1630         if (!spec)
1631                 return 0;
1632         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1633         if (!esw_priv)
1634                 return rte_flow_error_set(error, rte_errno,
1635                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636                                           "failed to obtain E-Switch info for"
1637                                           " port");
1638         dev_priv = mlx5_dev_to_eswitch_info(dev);
1639         if (!dev_priv)
1640                 return rte_flow_error_set(error, rte_errno,
1641                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1642                                           NULL,
1643                                           "failed to obtain E-Switch info");
1644         if (esw_priv->domain_id != dev_priv->domain_id)
1645                 return rte_flow_error_set(error, EINVAL,
1646                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1647                                           "cannot match on a port from a"
1648                                           " different E-Switch");
1649         return 0;
1650 }
1651
1652 /**
1653  * Validate VLAN item.
1654  *
1655  * @param[in] item
1656  *   Item specification.
1657  * @param[in] item_flags
1658  *   Bit-fields that holds the items detected until now.
1659  * @param[in] dev
1660  *   Ethernet device flow is being created on.
1661  * @param[out] error
1662  *   Pointer to error structure.
1663  *
1664  * @return
1665  *   0 on success, a negative errno value otherwise and rte_errno is set.
1666  */
1667 static int
1668 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1669                            uint64_t item_flags,
1670                            struct rte_eth_dev *dev,
1671                            struct rte_flow_error *error)
1672 {
1673         const struct rte_flow_item_vlan *mask = item->mask;
1674         const struct rte_flow_item_vlan nic_mask = {
1675                 .tci = RTE_BE16(UINT16_MAX),
1676                 .inner_type = RTE_BE16(UINT16_MAX),
1677                 .has_more_vlan = 1,
1678         };
1679         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1680         int ret;
1681         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1682                                         MLX5_FLOW_LAYER_INNER_L4) :
1683                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1684                                         MLX5_FLOW_LAYER_OUTER_L4);
1685         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1686                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1687
1688         if (item_flags & vlanm)
1689                 return rte_flow_error_set(error, EINVAL,
1690                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1691                                           "multiple VLAN layers not supported");
1692         else if ((item_flags & l34m) != 0)
1693                 return rte_flow_error_set(error, EINVAL,
1694                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1695                                           "VLAN cannot follow L3/L4 layer");
1696         if (!mask)
1697                 mask = &rte_flow_item_vlan_mask;
1698         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1699                                         (const uint8_t *)&nic_mask,
1700                                         sizeof(struct rte_flow_item_vlan),
1701                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1702         if (ret)
1703                 return ret;
1704         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1705                 struct mlx5_priv *priv = dev->data->dev_private;
1706
1707                 if (priv->vmwa_context) {
1708                         /*
1709                          * Non-NULL context means we have a virtual machine
1710                          * and SR-IOV enabled, we have to create VLAN interface
1711                          * to make hypervisor to setup E-Switch vport
1712                          * context correctly. We avoid creating the multiple
1713                          * VLAN interfaces, so we cannot support VLAN tag mask.
1714                          */
1715                         return rte_flow_error_set(error, EINVAL,
1716                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1717                                                   item,
1718                                                   "VLAN tag mask is not"
1719                                                   " supported in virtual"
1720                                                   " environment");
1721                 }
1722         }
1723         return 0;
1724 }
1725
1726 /*
1727  * GTP flags are contained in 1 byte of the format:
1728  * -------------------------------------------
1729  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1730  * |-----------------------------------------|
1731  * | value | Version | PT | Res | E | S | PN |
1732  * -------------------------------------------
1733  *
1734  * Matching is supported only for GTP flags E, S, PN.
1735  */
1736 #define MLX5_GTP_FLAGS_MASK     0x07
1737
1738 /**
1739  * Validate GTP item.
1740  *
1741  * @param[in] dev
1742  *   Pointer to the rte_eth_dev structure.
1743  * @param[in] item
1744  *   Item specification.
1745  * @param[in] item_flags
1746  *   Bit-fields that holds the items detected until now.
1747  * @param[out] error
1748  *   Pointer to error structure.
1749  *
1750  * @return
1751  *   0 on success, a negative errno value otherwise and rte_errno is set.
1752  */
1753 static int
1754 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1755                           const struct rte_flow_item *item,
1756                           uint64_t item_flags,
1757                           struct rte_flow_error *error)
1758 {
1759         struct mlx5_priv *priv = dev->data->dev_private;
1760         const struct rte_flow_item_gtp *spec = item->spec;
1761         const struct rte_flow_item_gtp *mask = item->mask;
1762         const struct rte_flow_item_gtp nic_mask = {
1763                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1764                 .msg_type = 0xff,
1765                 .teid = RTE_BE32(0xffffffff),
1766         };
1767
1768         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1769                 return rte_flow_error_set(error, ENOTSUP,
1770                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1771                                           "GTP support is not enabled");
1772         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "multiple tunnel layers not"
1776                                           " supported");
1777         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1778                 return rte_flow_error_set(error, EINVAL,
1779                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1780                                           "no outer UDP layer found");
1781         if (!mask)
1782                 mask = &rte_flow_item_gtp_mask;
1783         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1784                 return rte_flow_error_set(error, ENOTSUP,
1785                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1786                                           "Match is supported for GTP"
1787                                           " flags only");
1788         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1789                                          (const uint8_t *)&nic_mask,
1790                                          sizeof(struct rte_flow_item_gtp),
1791                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1792 }
1793
1794 /**
1795  * Validate IPV4 item.
1796  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1797  * add specific validation of fragment_offset field,
1798  *
1799  * @param[in] item
1800  *   Item specification.
1801  * @param[in] item_flags
1802  *   Bit-fields that holds the items detected until now.
1803  * @param[out] error
1804  *   Pointer to error structure.
1805  *
1806  * @return
1807  *   0 on success, a negative errno value otherwise and rte_errno is set.
1808  */
1809 static int
1810 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1811                            uint64_t item_flags,
1812                            uint64_t last_item,
1813                            uint16_t ether_type,
1814                            struct rte_flow_error *error)
1815 {
1816         int ret;
1817         const struct rte_flow_item_ipv4 *spec = item->spec;
1818         const struct rte_flow_item_ipv4 *last = item->last;
1819         const struct rte_flow_item_ipv4 *mask = item->mask;
1820         rte_be16_t fragment_offset_spec = 0;
1821         rte_be16_t fragment_offset_last = 0;
1822         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1823                 .hdr = {
1824                         .src_addr = RTE_BE32(0xffffffff),
1825                         .dst_addr = RTE_BE32(0xffffffff),
1826                         .type_of_service = 0xff,
1827                         .fragment_offset = RTE_BE16(0xffff),
1828                         .next_proto_id = 0xff,
1829                         .time_to_live = 0xff,
1830                 },
1831         };
1832
1833         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1834                                            ether_type, &nic_ipv4_mask,
1835                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1836         if (ret < 0)
1837                 return ret;
1838         if (spec && mask)
1839                 fragment_offset_spec = spec->hdr.fragment_offset &
1840                                        mask->hdr.fragment_offset;
1841         if (!fragment_offset_spec)
1842                 return 0;
1843         /*
1844          * spec and mask are valid, enforce using full mask to make sure the
1845          * complete value is used correctly.
1846          */
1847         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1848                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1849                 return rte_flow_error_set(error, EINVAL,
1850                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1851                                           item, "must use full mask for"
1852                                           " fragment_offset");
1853         /*
1854          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1855          * indicating this is 1st fragment of fragmented packet.
1856          * This is not yet supported in MLX5, return appropriate error message.
1857          */
1858         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1859                 return rte_flow_error_set(error, ENOTSUP,
1860                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1861                                           "match on first fragment not "
1862                                           "supported");
1863         if (fragment_offset_spec && !last)
1864                 return rte_flow_error_set(error, ENOTSUP,
1865                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1866                                           "specified value not supported");
1867         /* spec and last are valid, validate the specified range. */
1868         fragment_offset_last = last->hdr.fragment_offset &
1869                                mask->hdr.fragment_offset;
1870         /*
1871          * Match on fragment_offset spec 0x2001 and last 0x3fff
1872          * means MF is 1 and frag-offset is > 0.
1873          * This packet is fragment 2nd and onward, excluding last.
1874          * This is not yet supported in MLX5, return appropriate
1875          * error message.
1876          */
1877         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1878             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1879                 return rte_flow_error_set(error, ENOTSUP,
1880                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1881                                           last, "match on following "
1882                                           "fragments not supported");
1883         /*
1884          * Match on fragment_offset spec 0x0001 and last 0x1fff
1885          * means MF is 0 and frag-offset is > 0.
1886          * This packet is last fragment of fragmented packet.
1887          * This is not yet supported in MLX5, return appropriate
1888          * error message.
1889          */
1890         if (fragment_offset_spec == RTE_BE16(1) &&
1891             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1892                 return rte_flow_error_set(error, ENOTSUP,
1893                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1894                                           last, "match on last "
1895                                           "fragment not supported");
1896         /*
1897          * Match on fragment_offset spec 0x0001 and last 0x3fff
1898          * means MF and/or frag-offset is not 0.
1899          * This is a fragmented packet.
1900          * Other range values are invalid and rejected.
1901          */
1902         if (!(fragment_offset_spec == RTE_BE16(1) &&
1903               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1904                 return rte_flow_error_set(error, ENOTSUP,
1905                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1906                                           "specified range not supported");
1907         return 0;
1908 }
1909
1910 /**
1911  * Validate IPV6 fragment extension item.
1912  *
1913  * @param[in] item
1914  *   Item specification.
1915  * @param[in] item_flags
1916  *   Bit-fields that holds the items detected until now.
1917  * @param[out] error
1918  *   Pointer to error structure.
1919  *
1920  * @return
1921  *   0 on success, a negative errno value otherwise and rte_errno is set.
1922  */
1923 static int
1924 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1925                                     uint64_t item_flags,
1926                                     struct rte_flow_error *error)
1927 {
1928         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1929         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1930         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1931         rte_be16_t frag_data_spec = 0;
1932         rte_be16_t frag_data_last = 0;
1933         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1934         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1935                                       MLX5_FLOW_LAYER_OUTER_L4;
1936         int ret = 0;
1937         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1938                 .hdr = {
1939                         .next_header = 0xff,
1940                         .frag_data = RTE_BE16(0xffff),
1941                 },
1942         };
1943
1944         if (item_flags & l4m)
1945                 return rte_flow_error_set(error, EINVAL,
1946                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1947                                           "ipv6 fragment extension item cannot "
1948                                           "follow L4 item.");
1949         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1950             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1951                 return rte_flow_error_set(error, EINVAL,
1952                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1953                                           "ipv6 fragment extension item must "
1954                                           "follow ipv6 item");
1955         if (spec && mask)
1956                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1957         if (!frag_data_spec)
1958                 return 0;
1959         /*
1960          * spec and mask are valid, enforce using full mask to make sure the
1961          * complete value is used correctly.
1962          */
1963         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1964                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1965                 return rte_flow_error_set(error, EINVAL,
1966                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1967                                           item, "must use full mask for"
1968                                           " frag_data");
1969         /*
1970          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1971          * This is 1st fragment of fragmented packet.
1972          */
1973         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1974                 return rte_flow_error_set(error, ENOTSUP,
1975                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1976                                           "match on first fragment not "
1977                                           "supported");
1978         if (frag_data_spec && !last)
1979                 return rte_flow_error_set(error, EINVAL,
1980                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1981                                           "specified value not supported");
1982         ret = mlx5_flow_item_acceptable
1983                                 (item, (const uint8_t *)mask,
1984                                  (const uint8_t *)&nic_mask,
1985                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
1986                                  MLX5_ITEM_RANGE_ACCEPTED, error);
1987         if (ret)
1988                 return ret;
1989         /* spec and last are valid, validate the specified range. */
1990         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1991         /*
1992          * Match on frag_data spec 0x0009 and last 0xfff9
1993          * means M is 1 and frag-offset is > 0.
1994          * This packet is fragment 2nd and onward, excluding last.
1995          * This is not yet supported in MLX5, return appropriate
1996          * error message.
1997          */
1998         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
1999                                        RTE_IPV6_EHDR_MF_MASK) &&
2000             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2001                 return rte_flow_error_set(error, ENOTSUP,
2002                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2003                                           last, "match on following "
2004                                           "fragments not supported");
2005         /*
2006          * Match on frag_data spec 0x0008 and last 0xfff8
2007          * means M is 0 and frag-offset is > 0.
2008          * This packet is last fragment of fragmented packet.
2009          * This is not yet supported in MLX5, return appropriate
2010          * error message.
2011          */
2012         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2013             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2014                 return rte_flow_error_set(error, ENOTSUP,
2015                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2016                                           last, "match on last "
2017                                           "fragment not supported");
2018         /* Other range values are invalid and rejected. */
2019         return rte_flow_error_set(error, EINVAL,
2020                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2021                                   "specified range not supported");
2022 }
2023
2024 /**
2025  * Validate the pop VLAN action.
2026  *
2027  * @param[in] dev
2028  *   Pointer to the rte_eth_dev structure.
2029  * @param[in] action_flags
2030  *   Holds the actions detected until now.
2031  * @param[in] action
2032  *   Pointer to the pop vlan action.
2033  * @param[in] item_flags
2034  *   The items found in this flow rule.
2035  * @param[in] attr
2036  *   Pointer to flow attributes.
2037  * @param[out] error
2038  *   Pointer to error structure.
2039  *
2040  * @return
2041  *   0 on success, a negative errno value otherwise and rte_errno is set.
2042  */
2043 static int
2044 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2045                                  uint64_t action_flags,
2046                                  const struct rte_flow_action *action,
2047                                  uint64_t item_flags,
2048                                  const struct rte_flow_attr *attr,
2049                                  struct rte_flow_error *error)
2050 {
2051         const struct mlx5_priv *priv = dev->data->dev_private;
2052
2053         (void)action;
2054         (void)attr;
2055         if (!priv->sh->pop_vlan_action)
2056                 return rte_flow_error_set(error, ENOTSUP,
2057                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2058                                           NULL,
2059                                           "pop vlan action is not supported");
2060         if (attr->egress)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2063                                           NULL,
2064                                           "pop vlan action not supported for "
2065                                           "egress");
2066         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2067                 return rte_flow_error_set(error, ENOTSUP,
2068                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2069                                           "no support for multiple VLAN "
2070                                           "actions");
2071         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2072         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2073             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2074                 return rte_flow_error_set(error, ENOTSUP,
2075                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2076                                           NULL,
2077                                           "cannot pop vlan after decap without "
2078                                           "match on inner vlan in the flow");
2079         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2080         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2081             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2082                 return rte_flow_error_set(error, ENOTSUP,
2083                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2084                                           NULL,
2085                                           "cannot pop vlan without a "
2086                                           "match on (outer) vlan in the flow");
2087         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2088                 return rte_flow_error_set(error, EINVAL,
2089                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2090                                           "wrong action order, port_id should "
2091                                           "be after pop VLAN action");
2092         if (!attr->transfer && priv->representor)
2093                 return rte_flow_error_set(error, ENOTSUP,
2094                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2095                                           "pop vlan action for VF representor "
2096                                           "not supported on NIC table");
2097         return 0;
2098 }
2099
2100 /**
2101  * Get VLAN default info from vlan match info.
2102  *
2103  * @param[in] items
2104  *   the list of item specifications.
2105  * @param[out] vlan
2106  *   pointer VLAN info to fill to.
2107  *
2108  * @return
2109  *   0 on success, a negative errno value otherwise and rte_errno is set.
2110  */
2111 static void
2112 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2113                                   struct rte_vlan_hdr *vlan)
2114 {
2115         const struct rte_flow_item_vlan nic_mask = {
2116                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2117                                 MLX5DV_FLOW_VLAN_VID_MASK),
2118                 .inner_type = RTE_BE16(0xffff),
2119         };
2120
2121         if (items == NULL)
2122                 return;
2123         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2124                 int type = items->type;
2125
2126                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2127                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2128                         break;
2129         }
2130         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2131                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2132                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2133
2134                 /* If VLAN item in pattern doesn't contain data, return here. */
2135                 if (!vlan_v)
2136                         return;
2137                 if (!vlan_m)
2138                         vlan_m = &nic_mask;
2139                 /* Only full match values are accepted */
2140                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2141                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2142                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2143                         vlan->vlan_tci |=
2144                                 rte_be_to_cpu_16(vlan_v->tci &
2145                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2146                 }
2147                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2148                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2149                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2150                         vlan->vlan_tci |=
2151                                 rte_be_to_cpu_16(vlan_v->tci &
2152                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2153                 }
2154                 if (vlan_m->inner_type == nic_mask.inner_type)
2155                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2156                                                            vlan_m->inner_type);
2157         }
2158 }
2159
2160 /**
2161  * Validate the push VLAN action.
2162  *
2163  * @param[in] dev
2164  *   Pointer to the rte_eth_dev structure.
2165  * @param[in] action_flags
2166  *   Holds the actions detected until now.
2167  * @param[in] item_flags
2168  *   The items found in this flow rule.
2169  * @param[in] action
2170  *   Pointer to the action structure.
2171  * @param[in] attr
2172  *   Pointer to flow attributes
2173  * @param[out] error
2174  *   Pointer to error structure.
2175  *
2176  * @return
2177  *   0 on success, a negative errno value otherwise and rte_errno is set.
2178  */
2179 static int
2180 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2181                                   uint64_t action_flags,
2182                                   const struct rte_flow_item_vlan *vlan_m,
2183                                   const struct rte_flow_action *action,
2184                                   const struct rte_flow_attr *attr,
2185                                   struct rte_flow_error *error)
2186 {
2187         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2188         const struct mlx5_priv *priv = dev->data->dev_private;
2189
2190         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2191             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2192                 return rte_flow_error_set(error, EINVAL,
2193                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2194                                           "invalid vlan ethertype");
2195         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2196                 return rte_flow_error_set(error, EINVAL,
2197                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2198                                           "wrong action order, port_id should "
2199                                           "be after push VLAN");
2200         if (!attr->transfer && priv->representor)
2201                 return rte_flow_error_set(error, ENOTSUP,
2202                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2203                                           "push vlan action for VF representor "
2204                                           "not supported on NIC table");
2205         if (vlan_m &&
2206             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2207             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2208                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2209             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2210             !(mlx5_flow_find_action
2211                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2212                 return rte_flow_error_set(error, EINVAL,
2213                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2214                                           "not full match mask on VLAN PCP and "
2215                                           "there is no of_set_vlan_pcp action, "
2216                                           "push VLAN action cannot figure out "
2217                                           "PCP value");
2218         if (vlan_m &&
2219             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2220             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2221                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2222             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2223             !(mlx5_flow_find_action
2224                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2225                 return rte_flow_error_set(error, EINVAL,
2226                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2227                                           "not full match mask on VLAN VID and "
2228                                           "there is no of_set_vlan_vid action, "
2229                                           "push VLAN action cannot figure out "
2230                                           "VID value");
2231         (void)attr;
2232         return 0;
2233 }
2234
2235 /**
2236  * Validate the set VLAN PCP.
2237  *
2238  * @param[in] action_flags
2239  *   Holds the actions detected until now.
2240  * @param[in] actions
2241  *   Pointer to the list of actions remaining in the flow rule.
2242  * @param[out] error
2243  *   Pointer to error structure.
2244  *
2245  * @return
2246  *   0 on success, a negative errno value otherwise and rte_errno is set.
2247  */
2248 static int
2249 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2250                                      const struct rte_flow_action actions[],
2251                                      struct rte_flow_error *error)
2252 {
2253         const struct rte_flow_action *action = actions;
2254         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2255
2256         if (conf->vlan_pcp > 7)
2257                 return rte_flow_error_set(error, EINVAL,
2258                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2259                                           "VLAN PCP value is too big");
2260         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2261                 return rte_flow_error_set(error, ENOTSUP,
2262                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2263                                           "set VLAN PCP action must follow "
2264                                           "the push VLAN action");
2265         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2266                 return rte_flow_error_set(error, ENOTSUP,
2267                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2268                                           "Multiple VLAN PCP modification are "
2269                                           "not supported");
2270         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2271                 return rte_flow_error_set(error, EINVAL,
2272                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2273                                           "wrong action order, port_id should "
2274                                           "be after set VLAN PCP");
2275         return 0;
2276 }
2277
2278 /**
2279  * Validate the set VLAN VID.
2280  *
2281  * @param[in] item_flags
2282  *   Holds the items detected in this rule.
2283  * @param[in] action_flags
2284  *   Holds the actions detected until now.
2285  * @param[in] actions
2286  *   Pointer to the list of actions remaining in the flow rule.
2287  * @param[out] error
2288  *   Pointer to error structure.
2289  *
2290  * @return
2291  *   0 on success, a negative errno value otherwise and rte_errno is set.
2292  */
2293 static int
2294 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2295                                      uint64_t action_flags,
2296                                      const struct rte_flow_action actions[],
2297                                      struct rte_flow_error *error)
2298 {
2299         const struct rte_flow_action *action = actions;
2300         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2301
2302         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2303                 return rte_flow_error_set(error, EINVAL,
2304                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2305                                           "VLAN VID value is too big");
2306         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2307             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2308                 return rte_flow_error_set(error, ENOTSUP,
2309                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2310                                           "set VLAN VID action must follow push"
2311                                           " VLAN action or match on VLAN item");
2312         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2313                 return rte_flow_error_set(error, ENOTSUP,
2314                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2315                                           "Multiple VLAN VID modifications are "
2316                                           "not supported");
2317         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2318                 return rte_flow_error_set(error, EINVAL,
2319                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2320                                           "wrong action order, port_id should "
2321                                           "be after set VLAN VID");
2322         return 0;
2323 }
2324
2325 /*
2326  * Validate the FLAG action.
2327  *
2328  * @param[in] dev
2329  *   Pointer to the rte_eth_dev structure.
2330  * @param[in] action_flags
2331  *   Holds the actions detected until now.
2332  * @param[in] attr
2333  *   Pointer to flow attributes
2334  * @param[out] error
2335  *   Pointer to error structure.
2336  *
2337  * @return
2338  *   0 on success, a negative errno value otherwise and rte_errno is set.
2339  */
2340 static int
2341 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2342                              uint64_t action_flags,
2343                              const struct rte_flow_attr *attr,
2344                              struct rte_flow_error *error)
2345 {
2346         struct mlx5_priv *priv = dev->data->dev_private;
2347         struct mlx5_dev_config *config = &priv->config;
2348         int ret;
2349
2350         /* Fall back if no extended metadata register support. */
2351         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2352                 return mlx5_flow_validate_action_flag(action_flags, attr,
2353                                                       error);
2354         /* Extensive metadata mode requires registers. */
2355         if (!mlx5_flow_ext_mreg_supported(dev))
2356                 return rte_flow_error_set(error, ENOTSUP,
2357                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2358                                           "no metadata registers "
2359                                           "to support flag action");
2360         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2361                 return rte_flow_error_set(error, ENOTSUP,
2362                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2363                                           "extended metadata register"
2364                                           " isn't available");
2365         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2366         if (ret < 0)
2367                 return ret;
2368         MLX5_ASSERT(ret > 0);
2369         if (action_flags & MLX5_FLOW_ACTION_MARK)
2370                 return rte_flow_error_set(error, EINVAL,
2371                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2372                                           "can't mark and flag in same flow");
2373         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2374                 return rte_flow_error_set(error, EINVAL,
2375                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2376                                           "can't have 2 flag"
2377                                           " actions in same flow");
2378         return 0;
2379 }
2380
2381 /**
2382  * Validate MARK action.
2383  *
2384  * @param[in] dev
2385  *   Pointer to the rte_eth_dev structure.
2386  * @param[in] action
2387  *   Pointer to action.
2388  * @param[in] action_flags
2389  *   Holds the actions detected until now.
2390  * @param[in] attr
2391  *   Pointer to flow attributes
2392  * @param[out] error
2393  *   Pointer to error structure.
2394  *
2395  * @return
2396  *   0 on success, a negative errno value otherwise and rte_errno is set.
2397  */
2398 static int
2399 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2400                              const struct rte_flow_action *action,
2401                              uint64_t action_flags,
2402                              const struct rte_flow_attr *attr,
2403                              struct rte_flow_error *error)
2404 {
2405         struct mlx5_priv *priv = dev->data->dev_private;
2406         struct mlx5_dev_config *config = &priv->config;
2407         const struct rte_flow_action_mark *mark = action->conf;
2408         int ret;
2409
2410         /* Fall back if no extended metadata register support. */
2411         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2412                 return mlx5_flow_validate_action_mark(action, action_flags,
2413                                                       attr, error);
2414         /* Extensive metadata mode requires registers. */
2415         if (!mlx5_flow_ext_mreg_supported(dev))
2416                 return rte_flow_error_set(error, ENOTSUP,
2417                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2418                                           "no metadata registers "
2419                                           "to support mark action");
2420         if (!priv->sh->dv_mark_mask)
2421                 return rte_flow_error_set(error, ENOTSUP,
2422                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2423                                           "extended metadata register"
2424                                           " isn't available");
2425         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2426         if (ret < 0)
2427                 return ret;
2428         MLX5_ASSERT(ret > 0);
2429         if (!mark)
2430                 return rte_flow_error_set(error, EINVAL,
2431                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2432                                           "configuration cannot be null");
2433         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2434                 return rte_flow_error_set(error, EINVAL,
2435                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2436                                           &mark->id,
2437                                           "mark id exceeds the limit");
2438         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2439                 return rte_flow_error_set(error, EINVAL,
2440                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2441                                           "can't flag and mark in same flow");
2442         if (action_flags & MLX5_FLOW_ACTION_MARK)
2443                 return rte_flow_error_set(error, EINVAL,
2444                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2445                                           "can't have 2 mark actions in same"
2446                                           " flow");
2447         return 0;
2448 }
2449
2450 /**
2451  * Validate SET_META action.
2452  *
2453  * @param[in] dev
2454  *   Pointer to the rte_eth_dev structure.
2455  * @param[in] action
2456  *   Pointer to the action structure.
2457  * @param[in] action_flags
2458  *   Holds the actions detected until now.
2459  * @param[in] attr
2460  *   Pointer to flow attributes
2461  * @param[out] error
2462  *   Pointer to error structure.
2463  *
2464  * @return
2465  *   0 on success, a negative errno value otherwise and rte_errno is set.
2466  */
2467 static int
2468 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2469                                  const struct rte_flow_action *action,
2470                                  uint64_t action_flags __rte_unused,
2471                                  const struct rte_flow_attr *attr,
2472                                  struct rte_flow_error *error)
2473 {
2474         const struct rte_flow_action_set_meta *conf;
2475         uint32_t nic_mask = UINT32_MAX;
2476         int reg;
2477
2478         if (!mlx5_flow_ext_mreg_supported(dev))
2479                 return rte_flow_error_set(error, ENOTSUP,
2480                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2481                                           "extended metadata register"
2482                                           " isn't supported");
2483         reg = flow_dv_get_metadata_reg(dev, attr, error);
2484         if (reg < 0)
2485                 return reg;
2486         if (reg != REG_A && reg != REG_B) {
2487                 struct mlx5_priv *priv = dev->data->dev_private;
2488
2489                 nic_mask = priv->sh->dv_meta_mask;
2490         }
2491         if (!(action->conf))
2492                 return rte_flow_error_set(error, EINVAL,
2493                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2494                                           "configuration cannot be null");
2495         conf = (const struct rte_flow_action_set_meta *)action->conf;
2496         if (!conf->mask)
2497                 return rte_flow_error_set(error, EINVAL,
2498                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2499                                           "zero mask doesn't have any effect");
2500         if (conf->mask & ~nic_mask)
2501                 return rte_flow_error_set(error, EINVAL,
2502                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2503                                           "meta data must be within reg C0");
2504         return 0;
2505 }
2506
2507 /**
2508  * Validate SET_TAG action.
2509  *
2510  * @param[in] dev
2511  *   Pointer to the rte_eth_dev structure.
2512  * @param[in] action
2513  *   Pointer to the action structure.
2514  * @param[in] action_flags
2515  *   Holds the actions detected until now.
2516  * @param[in] attr
2517  *   Pointer to flow attributes
2518  * @param[out] error
2519  *   Pointer to error structure.
2520  *
2521  * @return
2522  *   0 on success, a negative errno value otherwise and rte_errno is set.
2523  */
2524 static int
2525 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2526                                 const struct rte_flow_action *action,
2527                                 uint64_t action_flags,
2528                                 const struct rte_flow_attr *attr,
2529                                 struct rte_flow_error *error)
2530 {
2531         const struct rte_flow_action_set_tag *conf;
2532         const uint64_t terminal_action_flags =
2533                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2534                 MLX5_FLOW_ACTION_RSS;
2535         int ret;
2536
2537         if (!mlx5_flow_ext_mreg_supported(dev))
2538                 return rte_flow_error_set(error, ENOTSUP,
2539                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2540                                           "extensive metadata register"
2541                                           " isn't supported");
2542         if (!(action->conf))
2543                 return rte_flow_error_set(error, EINVAL,
2544                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2545                                           "configuration cannot be null");
2546         conf = (const struct rte_flow_action_set_tag *)action->conf;
2547         if (!conf->mask)
2548                 return rte_flow_error_set(error, EINVAL,
2549                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2550                                           "zero mask doesn't have any effect");
2551         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2552         if (ret < 0)
2553                 return ret;
2554         if (!attr->transfer && attr->ingress &&
2555             (action_flags & terminal_action_flags))
2556                 return rte_flow_error_set(error, EINVAL,
2557                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2558                                           "set_tag has no effect"
2559                                           " with terminal actions");
2560         return 0;
2561 }
2562
2563 /**
2564  * Validate count action.
2565  *
2566  * @param[in] dev
2567  *   Pointer to rte_eth_dev structure.
2568  * @param[out] error
2569  *   Pointer to error structure.
2570  *
2571  * @return
2572  *   0 on success, a negative errno value otherwise and rte_errno is set.
2573  */
2574 static int
2575 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2576                               struct rte_flow_error *error)
2577 {
2578         struct mlx5_priv *priv = dev->data->dev_private;
2579
2580         if (!priv->config.devx)
2581                 goto notsup_err;
2582 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2583         return 0;
2584 #endif
2585 notsup_err:
2586         return rte_flow_error_set
2587                       (error, ENOTSUP,
2588                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2589                        NULL,
2590                        "count action not supported");
2591 }
2592
2593 /**
2594  * Validate the L2 encap action.
2595  *
2596  * @param[in] dev
2597  *   Pointer to the rte_eth_dev structure.
2598  * @param[in] action_flags
2599  *   Holds the actions detected until now.
2600  * @param[in] action
2601  *   Pointer to the action structure.
2602  * @param[in] attr
2603  *   Pointer to flow attributes.
2604  * @param[out] error
2605  *   Pointer to error structure.
2606  *
2607  * @return
2608  *   0 on success, a negative errno value otherwise and rte_errno is set.
2609  */
2610 static int
2611 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2612                                  uint64_t action_flags,
2613                                  const struct rte_flow_action *action,
2614                                  const struct rte_flow_attr *attr,
2615                                  struct rte_flow_error *error)
2616 {
2617         const struct mlx5_priv *priv = dev->data->dev_private;
2618
2619         if (!(action->conf))
2620                 return rte_flow_error_set(error, EINVAL,
2621                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2622                                           "configuration cannot be null");
2623         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2624                 return rte_flow_error_set(error, EINVAL,
2625                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2626                                           "can only have a single encap action "
2627                                           "in a flow");
2628         if (!attr->transfer && priv->representor)
2629                 return rte_flow_error_set(error, ENOTSUP,
2630                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2631                                           "encap action for VF representor "
2632                                           "not supported on NIC table");
2633         return 0;
2634 }
2635
2636 /**
2637  * Validate a decap action.
2638  *
2639  * @param[in] dev
2640  *   Pointer to the rte_eth_dev structure.
2641  * @param[in] action_flags
2642  *   Holds the actions detected until now.
2643  * @param[in] attr
2644  *   Pointer to flow attributes
2645  * @param[out] error
2646  *   Pointer to error structure.
2647  *
2648  * @return
2649  *   0 on success, a negative errno value otherwise and rte_errno is set.
2650  */
2651 static int
2652 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2653                               uint64_t action_flags,
2654                               const struct rte_flow_attr *attr,
2655                               struct rte_flow_error *error)
2656 {
2657         const struct mlx5_priv *priv = dev->data->dev_private;
2658
2659         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2660             !priv->config.decap_en)
2661                 return rte_flow_error_set(error, ENOTSUP,
2662                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2663                                           "decap is not enabled");
2664         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2665                 return rte_flow_error_set(error, ENOTSUP,
2666                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2667                                           action_flags &
2668                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2669                                           "have a single decap action" : "decap "
2670                                           "after encap is not supported");
2671         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2672                 return rte_flow_error_set(error, EINVAL,
2673                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2674                                           "can't have decap action after"
2675                                           " modify action");
2676         if (attr->egress)
2677                 return rte_flow_error_set(error, ENOTSUP,
2678                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2679                                           NULL,
2680                                           "decap action not supported for "
2681                                           "egress");
2682         if (!attr->transfer && priv->representor)
2683                 return rte_flow_error_set(error, ENOTSUP,
2684                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2685                                           "decap action for VF representor "
2686                                           "not supported on NIC table");
2687         return 0;
2688 }
2689
2690 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2691
2692 /**
2693  * Validate the raw encap and decap actions.
2694  *
2695  * @param[in] dev
2696  *   Pointer to the rte_eth_dev structure.
2697  * @param[in] decap
2698  *   Pointer to the decap action.
2699  * @param[in] encap
2700  *   Pointer to the encap action.
2701  * @param[in] attr
2702  *   Pointer to flow attributes
2703  * @param[in/out] action_flags
2704  *   Holds the actions detected until now.
2705  * @param[out] actions_n
2706  *   pointer to the number of actions counter.
2707  * @param[out] error
2708  *   Pointer to error structure.
2709  *
2710  * @return
2711  *   0 on success, a negative errno value otherwise and rte_errno is set.
2712  */
2713 static int
2714 flow_dv_validate_action_raw_encap_decap
2715         (struct rte_eth_dev *dev,
2716          const struct rte_flow_action_raw_decap *decap,
2717          const struct rte_flow_action_raw_encap *encap,
2718          const struct rte_flow_attr *attr, uint64_t *action_flags,
2719          int *actions_n, struct rte_flow_error *error)
2720 {
2721         const struct mlx5_priv *priv = dev->data->dev_private;
2722         int ret;
2723
2724         if (encap && (!encap->size || !encap->data))
2725                 return rte_flow_error_set(error, EINVAL,
2726                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2727                                           "raw encap data cannot be empty");
2728         if (decap && encap) {
2729                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2730                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2731                         /* L3 encap. */
2732                         decap = NULL;
2733                 else if (encap->size <=
2734                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2735                            decap->size >
2736                            MLX5_ENCAPSULATION_DECISION_SIZE)
2737                         /* L3 decap. */
2738                         encap = NULL;
2739                 else if (encap->size >
2740                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2741                            decap->size >
2742                            MLX5_ENCAPSULATION_DECISION_SIZE)
2743                         /* 2 L2 actions: encap and decap. */
2744                         ;
2745                 else
2746                         return rte_flow_error_set(error,
2747                                 ENOTSUP,
2748                                 RTE_FLOW_ERROR_TYPE_ACTION,
2749                                 NULL, "unsupported too small "
2750                                 "raw decap and too small raw "
2751                                 "encap combination");
2752         }
2753         if (decap) {
2754                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2755                                                     error);
2756                 if (ret < 0)
2757                         return ret;
2758                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2759                 ++(*actions_n);
2760         }
2761         if (encap) {
2762                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2763                         return rte_flow_error_set(error, ENOTSUP,
2764                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2765                                                   NULL,
2766                                                   "small raw encap size");
2767                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2768                         return rte_flow_error_set(error, EINVAL,
2769                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2770                                                   NULL,
2771                                                   "more than one encap action");
2772                 if (!attr->transfer && priv->representor)
2773                         return rte_flow_error_set
2774                                         (error, ENOTSUP,
2775                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2776                                          "encap action for VF representor "
2777                                          "not supported on NIC table");
2778                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2779                 ++(*actions_n);
2780         }
2781         return 0;
2782 }
2783
2784 /**
2785  * Match encap_decap resource.
2786  *
2787  * @param entry
2788  *   Pointer to exist resource entry object.
2789  * @param ctx
2790  *   Pointer to new encap_decap resource.
2791  *
2792  * @return
2793  *   0 on matching, -1 otherwise.
2794  */
2795 static int
2796 flow_dv_encap_decap_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
2797 {
2798         struct mlx5_flow_dv_encap_decap_resource *resource;
2799         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2800
2801         resource = (struct mlx5_flow_dv_encap_decap_resource *)ctx;
2802         cache_resource = container_of(entry,
2803                                       struct mlx5_flow_dv_encap_decap_resource,
2804                                       entry);
2805         if (resource->entry.key == cache_resource->entry.key &&
2806             resource->reformat_type == cache_resource->reformat_type &&
2807             resource->ft_type == cache_resource->ft_type &&
2808             resource->flags == cache_resource->flags &&
2809             resource->size == cache_resource->size &&
2810             !memcmp((const void *)resource->buf,
2811                     (const void *)cache_resource->buf,
2812                     resource->size))
2813                 return 0;
2814         return -1;
2815 }
2816
2817 /**
2818  * Find existing encap/decap resource or create and register a new one.
2819  *
2820  * @param[in, out] dev
2821  *   Pointer to rte_eth_dev structure.
2822  * @param[in, out] resource
2823  *   Pointer to encap/decap resource.
2824  * @parm[in, out] dev_flow
2825  *   Pointer to the dev_flow.
2826  * @param[out] error
2827  *   pointer to error structure.
2828  *
2829  * @return
2830  *   0 on success otherwise -errno and errno is set.
2831  */
2832 static int
2833 flow_dv_encap_decap_resource_register
2834                         (struct rte_eth_dev *dev,
2835                          struct mlx5_flow_dv_encap_decap_resource *resource,
2836                          struct mlx5_flow *dev_flow,
2837                          struct rte_flow_error *error)
2838 {
2839         struct mlx5_priv *priv = dev->data->dev_private;
2840         struct mlx5_dev_ctx_shared *sh = priv->sh;
2841         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2842         struct mlx5dv_dr_domain *domain;
2843         struct mlx5_hlist_entry *entry;
2844         union mlx5_flow_encap_decap_key encap_decap_key = {
2845                 {
2846                         .ft_type = resource->ft_type,
2847                         .refmt_type = resource->reformat_type,
2848                         .buf_size = resource->size,
2849                         .table_level = !!dev_flow->dv.group,
2850                         .cksum = 0,
2851                 }
2852         };
2853         int ret;
2854
2855         resource->flags = dev_flow->dv.group ? 0 : 1;
2856         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2857                 domain = sh->fdb_domain;
2858         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2859                 domain = sh->rx_domain;
2860         else
2861                 domain = sh->tx_domain;
2862         encap_decap_key.cksum = __rte_raw_cksum(resource->buf,
2863                                                 resource->size, 0);
2864         resource->entry.key = encap_decap_key.v64;
2865         /* Lookup a matching resource from cache. */
2866         entry = mlx5_hlist_lookup_ex(sh->encaps_decaps, resource->entry.key,
2867                                      flow_dv_encap_decap_resource_match,
2868                                      (void *)resource);
2869         if (entry) {
2870                 cache_resource = container_of(entry,
2871                         struct mlx5_flow_dv_encap_decap_resource, entry);
2872                 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2873                         (void *)cache_resource,
2874                         __atomic_load_n(&cache_resource->refcnt,
2875                                         __ATOMIC_RELAXED));
2876                 __atomic_fetch_add(&cache_resource->refcnt, 1,
2877                                    __ATOMIC_RELAXED);
2878                 dev_flow->handle->dvh.rix_encap_decap = cache_resource->idx;
2879                 dev_flow->dv.encap_decap = cache_resource;
2880                 return 0;
2881         }
2882         /* Register new encap/decap resource. */
2883         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2884                                        &dev_flow->handle->dvh.rix_encap_decap);
2885         if (!cache_resource)
2886                 return rte_flow_error_set(error, ENOMEM,
2887                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2888                                           "cannot allocate resource memory");
2889         *cache_resource = *resource;
2890         cache_resource->idx = dev_flow->handle->dvh.rix_encap_decap;
2891         ret = mlx5_flow_os_create_flow_action_packet_reformat
2892                                         (sh->ctx, domain, cache_resource,
2893                                          &cache_resource->action);
2894         if (ret) {
2895                 mlx5_free(cache_resource);
2896                 return rte_flow_error_set(error, ENOMEM,
2897                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2898                                           NULL, "cannot create action");
2899         }
2900         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
2901         if (mlx5_hlist_insert_ex(sh->encaps_decaps, &cache_resource->entry,
2902                                  flow_dv_encap_decap_resource_match,
2903                                  (void *)cache_resource)) {
2904                 claim_zero(mlx5_flow_os_destroy_flow_action
2905                                                 (cache_resource->action));
2906                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2907                                 cache_resource->idx);
2908                 return rte_flow_error_set(error, EEXIST,
2909                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2910                                           NULL, "action exist");
2911         }
2912         dev_flow->dv.encap_decap = cache_resource;
2913         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2914                 (void *)cache_resource,
2915                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
2916         return 0;
2917 }
2918
2919 /**
2920  * Find existing table jump resource or create and register a new one.
2921  *
2922  * @param[in, out] dev
2923  *   Pointer to rte_eth_dev structure.
2924  * @param[in, out] tbl
2925  *   Pointer to flow table resource.
2926  * @parm[in, out] dev_flow
2927  *   Pointer to the dev_flow.
2928  * @param[out] error
2929  *   pointer to error structure.
2930  *
2931  * @return
2932  *   0 on success otherwise -errno and errno is set.
2933  */
2934 static int
2935 flow_dv_jump_tbl_resource_register
2936                         (struct rte_eth_dev *dev __rte_unused,
2937                          struct mlx5_flow_tbl_resource *tbl,
2938                          struct mlx5_flow *dev_flow,
2939                          struct rte_flow_error *error __rte_unused)
2940 {
2941         struct mlx5_flow_tbl_data_entry *tbl_data =
2942                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2943
2944         MLX5_ASSERT(tbl);
2945         MLX5_ASSERT(tbl_data->jump.action);
2946         dev_flow->handle->rix_jump = tbl_data->idx;
2947         dev_flow->dv.jump = &tbl_data->jump;
2948         return 0;
2949 }
2950
2951 /**
2952  * Find existing table port ID resource or create and register a new one.
2953  *
2954  * @param[in, out] dev
2955  *   Pointer to rte_eth_dev structure.
2956  * @param[in, out] resource
2957  *   Pointer to port ID action resource.
2958  * @parm[in, out] dev_flow
2959  *   Pointer to the dev_flow.
2960  * @param[out] error
2961  *   pointer to error structure.
2962  *
2963  * @return
2964  *   0 on success otherwise -errno and errno is set.
2965  */
2966 static int
2967 flow_dv_port_id_action_resource_register
2968                         (struct rte_eth_dev *dev,
2969                          struct mlx5_flow_dv_port_id_action_resource *resource,
2970                          struct mlx5_flow *dev_flow,
2971                          struct rte_flow_error *error)
2972 {
2973         struct mlx5_priv *priv = dev->data->dev_private;
2974         struct mlx5_dev_ctx_shared *sh = priv->sh;
2975         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2976         uint32_t idx = 0;
2977         int ret;
2978
2979         /* Lookup a matching resource from cache. */
2980         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2981                       idx, cache_resource, next) {
2982                 if (resource->port_id == cache_resource->port_id) {
2983                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2984                                 "refcnt %d++",
2985                                 (void *)cache_resource,
2986                                 __atomic_load_n(&cache_resource->refcnt,
2987                                                 __ATOMIC_RELAXED));
2988                         __atomic_fetch_add(&cache_resource->refcnt, 1,
2989                                            __ATOMIC_RELAXED);
2990                         dev_flow->handle->rix_port_id_action = idx;
2991                         dev_flow->dv.port_id_action = cache_resource;
2992                         return 0;
2993                 }
2994         }
2995         /* Register new port id action resource. */
2996         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2997                                        &dev_flow->handle->rix_port_id_action);
2998         if (!cache_resource)
2999                 return rte_flow_error_set(error, ENOMEM,
3000                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3001                                           "cannot allocate resource memory");
3002         *cache_resource = *resource;
3003         ret = mlx5_flow_os_create_flow_action_dest_port
3004                                 (priv->sh->fdb_domain, resource->port_id,
3005                                  &cache_resource->action);
3006         if (ret) {
3007                 mlx5_free(cache_resource);
3008                 return rte_flow_error_set(error, ENOMEM,
3009                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3010                                           NULL, "cannot create action");
3011         }
3012         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
3013         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
3014                      dev_flow->handle->rix_port_id_action, cache_resource,
3015                      next);
3016         dev_flow->dv.port_id_action = cache_resource;
3017         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
3018                 (void *)cache_resource,
3019                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
3020         return 0;
3021 }
3022
3023 /**
3024  * Find existing push vlan resource or create and register a new one.
3025  *
3026  * @param [in, out] dev
3027  *   Pointer to rte_eth_dev structure.
3028  * @param[in, out] resource
3029  *   Pointer to port ID action resource.
3030  * @parm[in, out] dev_flow
3031  *   Pointer to the dev_flow.
3032  * @param[out] error
3033  *   pointer to error structure.
3034  *
3035  * @return
3036  *   0 on success otherwise -errno and errno is set.
3037  */
3038 static int
3039 flow_dv_push_vlan_action_resource_register
3040                        (struct rte_eth_dev *dev,
3041                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3042                         struct mlx5_flow *dev_flow,
3043                         struct rte_flow_error *error)
3044 {
3045         struct mlx5_priv *priv = dev->data->dev_private;
3046         struct mlx5_dev_ctx_shared *sh = priv->sh;
3047         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
3048         struct mlx5dv_dr_domain *domain;
3049         uint32_t idx = 0;
3050         int ret;
3051
3052         /* Lookup a matching resource from cache. */
3053         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3054                       sh->push_vlan_action_list, idx, cache_resource, next) {
3055                 if (resource->vlan_tag == cache_resource->vlan_tag &&
3056                     resource->ft_type == cache_resource->ft_type) {
3057                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
3058                                 "refcnt %d++",
3059                                 (void *)cache_resource,
3060                                 __atomic_load_n(&cache_resource->refcnt,
3061                                                 __ATOMIC_RELAXED));
3062                         __atomic_fetch_add(&cache_resource->refcnt, 1,
3063                                            __ATOMIC_RELAXED);
3064                         dev_flow->handle->dvh.rix_push_vlan = idx;
3065                         dev_flow->dv.push_vlan_res = cache_resource;
3066                         return 0;
3067                 }
3068         }
3069         /* Register new push_vlan action resource. */
3070         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3071                                        &dev_flow->handle->dvh.rix_push_vlan);
3072         if (!cache_resource)
3073                 return rte_flow_error_set(error, ENOMEM,
3074                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3075                                           "cannot allocate resource memory");
3076         *cache_resource = *resource;
3077         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3078                 domain = sh->fdb_domain;
3079         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3080                 domain = sh->rx_domain;
3081         else
3082                 domain = sh->tx_domain;
3083         ret = mlx5_flow_os_create_flow_action_push_vlan
3084                                         (domain, resource->vlan_tag,
3085                                          &cache_resource->action);
3086         if (ret) {
3087                 mlx5_free(cache_resource);
3088                 return rte_flow_error_set(error, ENOMEM,
3089                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3090                                           NULL, "cannot create action");
3091         }
3092         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
3093         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3094                      &sh->push_vlan_action_list,
3095                      dev_flow->handle->dvh.rix_push_vlan,
3096                      cache_resource, next);
3097         dev_flow->dv.push_vlan_res = cache_resource;
3098         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
3099                 (void *)cache_resource,
3100                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
3101         return 0;
3102 }
3103 /**
3104  * Get the size of specific rte_flow_item_type hdr size
3105  *
3106  * @param[in] item_type
3107  *   Tested rte_flow_item_type.
3108  *
3109  * @return
3110  *   sizeof struct item_type, 0 if void or irrelevant.
3111  */
3112 static size_t
3113 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3114 {
3115         size_t retval;
3116
3117         switch (item_type) {
3118         case RTE_FLOW_ITEM_TYPE_ETH:
3119                 retval = sizeof(struct rte_ether_hdr);
3120                 break;
3121         case RTE_FLOW_ITEM_TYPE_VLAN:
3122                 retval = sizeof(struct rte_vlan_hdr);
3123                 break;
3124         case RTE_FLOW_ITEM_TYPE_IPV4:
3125                 retval = sizeof(struct rte_ipv4_hdr);
3126                 break;
3127         case RTE_FLOW_ITEM_TYPE_IPV6:
3128                 retval = sizeof(struct rte_ipv6_hdr);
3129                 break;
3130         case RTE_FLOW_ITEM_TYPE_UDP:
3131                 retval = sizeof(struct rte_udp_hdr);
3132                 break;
3133         case RTE_FLOW_ITEM_TYPE_TCP:
3134                 retval = sizeof(struct rte_tcp_hdr);
3135                 break;
3136         case RTE_FLOW_ITEM_TYPE_VXLAN:
3137         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3138                 retval = sizeof(struct rte_vxlan_hdr);
3139                 break;
3140         case RTE_FLOW_ITEM_TYPE_GRE:
3141         case RTE_FLOW_ITEM_TYPE_NVGRE:
3142                 retval = sizeof(struct rte_gre_hdr);
3143                 break;
3144         case RTE_FLOW_ITEM_TYPE_MPLS:
3145                 retval = sizeof(struct rte_mpls_hdr);
3146                 break;
3147         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3148         default:
3149                 retval = 0;
3150                 break;
3151         }
3152         return retval;
3153 }
3154
3155 #define MLX5_ENCAP_IPV4_VERSION         0x40
3156 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3157 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3158 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3159 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3160 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3161 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3162
3163 /**
3164  * Convert the encap action data from list of rte_flow_item to raw buffer
3165  *
3166  * @param[in] items
3167  *   Pointer to rte_flow_item objects list.
3168  * @param[out] buf
3169  *   Pointer to the output buffer.
3170  * @param[out] size
3171  *   Pointer to the output buffer size.
3172  * @param[out] error
3173  *   Pointer to the error structure.
3174  *
3175  * @return
3176  *   0 on success, a negative errno value otherwise and rte_errno is set.
3177  */
3178 static int
3179 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3180                            size_t *size, struct rte_flow_error *error)
3181 {
3182         struct rte_ether_hdr *eth = NULL;
3183         struct rte_vlan_hdr *vlan = NULL;
3184         struct rte_ipv4_hdr *ipv4 = NULL;
3185         struct rte_ipv6_hdr *ipv6 = NULL;
3186         struct rte_udp_hdr *udp = NULL;
3187         struct rte_vxlan_hdr *vxlan = NULL;
3188         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3189         struct rte_gre_hdr *gre = NULL;
3190         size_t len;
3191         size_t temp_size = 0;
3192
3193         if (!items)
3194                 return rte_flow_error_set(error, EINVAL,
3195                                           RTE_FLOW_ERROR_TYPE_ACTION,
3196                                           NULL, "invalid empty data");
3197         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3198                 len = flow_dv_get_item_hdr_len(items->type);
3199                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3200                         return rte_flow_error_set(error, EINVAL,
3201                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3202                                                   (void *)items->type,
3203                                                   "items total size is too big"
3204                                                   " for encap action");
3205                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3206                 switch (items->type) {
3207                 case RTE_FLOW_ITEM_TYPE_ETH:
3208                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3209                         break;
3210                 case RTE_FLOW_ITEM_TYPE_VLAN:
3211                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3212                         if (!eth)
3213                                 return rte_flow_error_set(error, EINVAL,
3214                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3215                                                 (void *)items->type,
3216                                                 "eth header not found");
3217                         if (!eth->ether_type)
3218                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3219                         break;
3220                 case RTE_FLOW_ITEM_TYPE_IPV4:
3221                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3222                         if (!vlan && !eth)
3223                                 return rte_flow_error_set(error, EINVAL,
3224                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3225                                                 (void *)items->type,
3226                                                 "neither eth nor vlan"
3227                                                 " header found");
3228                         if (vlan && !vlan->eth_proto)
3229                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3230                         else if (eth && !eth->ether_type)
3231                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3232                         if (!ipv4->version_ihl)
3233                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3234                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3235                         if (!ipv4->time_to_live)
3236                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3237                         break;
3238                 case RTE_FLOW_ITEM_TYPE_IPV6:
3239                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3240                         if (!vlan && !eth)
3241                                 return rte_flow_error_set(error, EINVAL,
3242                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3243                                                 (void *)items->type,
3244                                                 "neither eth nor vlan"
3245                                                 " header found");
3246                         if (vlan && !vlan->eth_proto)
3247                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3248                         else if (eth && !eth->ether_type)
3249                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3250                         if (!ipv6->vtc_flow)
3251                                 ipv6->vtc_flow =
3252                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3253                         if (!ipv6->hop_limits)
3254                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3255                         break;
3256                 case RTE_FLOW_ITEM_TYPE_UDP:
3257                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3258                         if (!ipv4 && !ipv6)
3259                                 return rte_flow_error_set(error, EINVAL,
3260                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3261                                                 (void *)items->type,
3262                                                 "ip header not found");
3263                         if (ipv4 && !ipv4->next_proto_id)
3264                                 ipv4->next_proto_id = IPPROTO_UDP;
3265                         else if (ipv6 && !ipv6->proto)
3266                                 ipv6->proto = IPPROTO_UDP;
3267                         break;
3268                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3269                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3270                         if (!udp)
3271                                 return rte_flow_error_set(error, EINVAL,
3272                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3273                                                 (void *)items->type,
3274                                                 "udp header not found");
3275                         if (!udp->dst_port)
3276                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3277                         if (!vxlan->vx_flags)
3278                                 vxlan->vx_flags =
3279                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3280                         break;
3281                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3282                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3283                         if (!udp)
3284                                 return rte_flow_error_set(error, EINVAL,
3285                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3286                                                 (void *)items->type,
3287                                                 "udp header not found");
3288                         if (!vxlan_gpe->proto)
3289                                 return rte_flow_error_set(error, EINVAL,
3290                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3291                                                 (void *)items->type,
3292                                                 "next protocol not found");
3293                         if (!udp->dst_port)
3294                                 udp->dst_port =
3295                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3296                         if (!vxlan_gpe->vx_flags)
3297                                 vxlan_gpe->vx_flags =
3298                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3299                         break;
3300                 case RTE_FLOW_ITEM_TYPE_GRE:
3301                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3302                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3303                         if (!gre->proto)
3304                                 return rte_flow_error_set(error, EINVAL,
3305                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3306                                                 (void *)items->type,
3307                                                 "next protocol not found");
3308                         if (!ipv4 && !ipv6)
3309                                 return rte_flow_error_set(error, EINVAL,
3310                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3311                                                 (void *)items->type,
3312                                                 "ip header not found");
3313                         if (ipv4 && !ipv4->next_proto_id)
3314                                 ipv4->next_proto_id = IPPROTO_GRE;
3315                         else if (ipv6 && !ipv6->proto)
3316                                 ipv6->proto = IPPROTO_GRE;
3317                         break;
3318                 case RTE_FLOW_ITEM_TYPE_VOID:
3319                         break;
3320                 default:
3321                         return rte_flow_error_set(error, EINVAL,
3322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3323                                                   (void *)items->type,
3324                                                   "unsupported item type");
3325                         break;
3326                 }
3327                 temp_size += len;
3328         }
3329         *size = temp_size;
3330         return 0;
3331 }
3332
3333 static int
3334 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3335 {
3336         struct rte_ether_hdr *eth = NULL;
3337         struct rte_vlan_hdr *vlan = NULL;
3338         struct rte_ipv6_hdr *ipv6 = NULL;
3339         struct rte_udp_hdr *udp = NULL;
3340         char *next_hdr;
3341         uint16_t proto;
3342
3343         eth = (struct rte_ether_hdr *)data;
3344         next_hdr = (char *)(eth + 1);
3345         proto = RTE_BE16(eth->ether_type);
3346
3347         /* VLAN skipping */
3348         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3349                 vlan = (struct rte_vlan_hdr *)next_hdr;
3350                 proto = RTE_BE16(vlan->eth_proto);
3351                 next_hdr += sizeof(struct rte_vlan_hdr);
3352         }
3353
3354         /* HW calculates IPv4 csum. no need to proceed */
3355         if (proto == RTE_ETHER_TYPE_IPV4)
3356                 return 0;
3357
3358         /* non IPv4/IPv6 header. not supported */
3359         if (proto != RTE_ETHER_TYPE_IPV6) {
3360                 return rte_flow_error_set(error, ENOTSUP,
3361                                           RTE_FLOW_ERROR_TYPE_ACTION,
3362                                           NULL, "Cannot offload non IPv4/IPv6");
3363         }
3364
3365         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3366
3367         /* ignore non UDP */
3368         if (ipv6->proto != IPPROTO_UDP)
3369                 return 0;
3370
3371         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3372         udp->dgram_cksum = 0;
3373
3374         return 0;
3375 }
3376
3377 /**
3378  * Convert L2 encap action to DV specification.
3379  *
3380  * @param[in] dev
3381  *   Pointer to rte_eth_dev structure.
3382  * @param[in] action
3383  *   Pointer to action structure.
3384  * @param[in, out] dev_flow
3385  *   Pointer to the mlx5_flow.
3386  * @param[in] transfer
3387  *   Mark if the flow is E-Switch flow.
3388  * @param[out] error
3389  *   Pointer to the error structure.
3390  *
3391  * @return
3392  *   0 on success, a negative errno value otherwise and rte_errno is set.
3393  */
3394 static int
3395 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3396                                const struct rte_flow_action *action,
3397                                struct mlx5_flow *dev_flow,
3398                                uint8_t transfer,
3399                                struct rte_flow_error *error)
3400 {
3401         const struct rte_flow_item *encap_data;
3402         const struct rte_flow_action_raw_encap *raw_encap_data;
3403         struct mlx5_flow_dv_encap_decap_resource res = {
3404                 .reformat_type =
3405                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3406                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3407                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3408         };
3409
3410         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3411                 raw_encap_data =
3412                         (const struct rte_flow_action_raw_encap *)action->conf;
3413                 res.size = raw_encap_data->size;
3414                 memcpy(res.buf, raw_encap_data->data, res.size);
3415         } else {
3416                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3417                         encap_data =
3418                                 ((const struct rte_flow_action_vxlan_encap *)
3419                                                 action->conf)->definition;
3420                 else
3421                         encap_data =
3422                                 ((const struct rte_flow_action_nvgre_encap *)
3423                                                 action->conf)->definition;
3424                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3425                                                &res.size, error))
3426                         return -rte_errno;
3427         }
3428         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3429                 return -rte_errno;
3430         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3431                 return rte_flow_error_set(error, EINVAL,
3432                                           RTE_FLOW_ERROR_TYPE_ACTION,
3433                                           NULL, "can't create L2 encap action");
3434         return 0;
3435 }
3436
3437 /**
3438  * Convert L2 decap action to DV specification.
3439  *
3440  * @param[in] dev
3441  *   Pointer to rte_eth_dev structure.
3442  * @param[in, out] dev_flow
3443  *   Pointer to the mlx5_flow.
3444  * @param[in] transfer
3445  *   Mark if the flow is E-Switch flow.
3446  * @param[out] error
3447  *   Pointer to the error structure.
3448  *
3449  * @return
3450  *   0 on success, a negative errno value otherwise and rte_errno is set.
3451  */
3452 static int
3453 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3454                                struct mlx5_flow *dev_flow,
3455                                uint8_t transfer,
3456                                struct rte_flow_error *error)
3457 {
3458         struct mlx5_flow_dv_encap_decap_resource res = {
3459                 .size = 0,
3460                 .reformat_type =
3461                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3462                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3463                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3464         };
3465
3466         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3467                 return rte_flow_error_set(error, EINVAL,
3468                                           RTE_FLOW_ERROR_TYPE_ACTION,
3469                                           NULL, "can't create L2 decap action");
3470         return 0;
3471 }
3472
3473 /**
3474  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3475  *
3476  * @param[in] dev
3477  *   Pointer to rte_eth_dev structure.
3478  * @param[in] action
3479  *   Pointer to action structure.
3480  * @param[in, out] dev_flow
3481  *   Pointer to the mlx5_flow.
3482  * @param[in] attr
3483  *   Pointer to the flow attributes.
3484  * @param[out] error
3485  *   Pointer to the error structure.
3486  *
3487  * @return
3488  *   0 on success, a negative errno value otherwise and rte_errno is set.
3489  */
3490 static int
3491 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3492                                 const struct rte_flow_action *action,
3493                                 struct mlx5_flow *dev_flow,
3494                                 const struct rte_flow_attr *attr,
3495                                 struct rte_flow_error *error)
3496 {
3497         const struct rte_flow_action_raw_encap *encap_data;
3498         struct mlx5_flow_dv_encap_decap_resource res;
3499
3500         memset(&res, 0, sizeof(res));
3501         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3502         res.size = encap_data->size;
3503         memcpy(res.buf, encap_data->data, res.size);
3504         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3505                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3506                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3507         if (attr->transfer)
3508                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3509         else
3510                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3511                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3512         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3513                 return rte_flow_error_set(error, EINVAL,
3514                                           RTE_FLOW_ERROR_TYPE_ACTION,
3515                                           NULL, "can't create encap action");
3516         return 0;
3517 }
3518
3519 /**
3520  * Create action push VLAN.
3521  *
3522  * @param[in] dev
3523  *   Pointer to rte_eth_dev structure.
3524  * @param[in] attr
3525  *   Pointer to the flow attributes.
3526  * @param[in] vlan
3527  *   Pointer to the vlan to push to the Ethernet header.
3528  * @param[in, out] dev_flow
3529  *   Pointer to the mlx5_flow.
3530  * @param[out] error
3531  *   Pointer to the error structure.
3532  *
3533  * @return
3534  *   0 on success, a negative errno value otherwise and rte_errno is set.
3535  */
3536 static int
3537 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3538                                 const struct rte_flow_attr *attr,
3539                                 const struct rte_vlan_hdr *vlan,
3540                                 struct mlx5_flow *dev_flow,
3541                                 struct rte_flow_error *error)
3542 {
3543         struct mlx5_flow_dv_push_vlan_action_resource res;
3544
3545         memset(&res, 0, sizeof(res));
3546         res.vlan_tag =
3547                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3548                                  vlan->vlan_tci);
3549         if (attr->transfer)
3550                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3551         else
3552                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3553                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3554         return flow_dv_push_vlan_action_resource_register
3555                                             (dev, &res, dev_flow, error);
3556 }
3557
3558 static int fdb_mirror;
3559
3560 /**
3561  * Validate the modify-header actions.
3562  *
3563  * @param[in] action_flags
3564  *   Holds the actions detected until now.
3565  * @param[in] action
3566  *   Pointer to the modify action.
3567  * @param[out] error
3568  *   Pointer to error structure.
3569  *
3570  * @return
3571  *   0 on success, a negative errno value otherwise and rte_errno is set.
3572  */
3573 static int
3574 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3575                                    const struct rte_flow_action *action,
3576                                    struct rte_flow_error *error)
3577 {
3578         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3579                 return rte_flow_error_set(error, EINVAL,
3580                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3581                                           NULL, "action configuration not set");
3582         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3583                 return rte_flow_error_set(error, EINVAL,
3584                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3585                                           "can't have encap action before"
3586                                           " modify action");
3587         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3588                 return rte_flow_error_set(error, EINVAL,
3589                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3590                                           "can't support sample action before"
3591                                           " modify action for E-Switch"
3592                                           " mirroring");
3593         return 0;
3594 }
3595
3596 /**
3597  * Validate the modify-header MAC address actions.
3598  *
3599  * @param[in] action_flags
3600  *   Holds the actions detected until now.
3601  * @param[in] action
3602  *   Pointer to the modify action.
3603  * @param[in] item_flags
3604  *   Holds the items detected.
3605  * @param[out] error
3606  *   Pointer to error structure.
3607  *
3608  * @return
3609  *   0 on success, a negative errno value otherwise and rte_errno is set.
3610  */
3611 static int
3612 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3613                                    const struct rte_flow_action *action,
3614                                    const uint64_t item_flags,
3615                                    struct rte_flow_error *error)
3616 {
3617         int ret = 0;
3618
3619         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3620         if (!ret) {
3621                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3622                         return rte_flow_error_set(error, EINVAL,
3623                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3624                                                   NULL,
3625                                                   "no L2 item in pattern");
3626         }
3627         return ret;
3628 }
3629
3630 /**
3631  * Validate the modify-header IPv4 address actions.
3632  *
3633  * @param[in] action_flags
3634  *   Holds the actions detected until now.
3635  * @param[in] action
3636  *   Pointer to the modify action.
3637  * @param[in] item_flags
3638  *   Holds the items detected.
3639  * @param[out] error
3640  *   Pointer to error structure.
3641  *
3642  * @return
3643  *   0 on success, a negative errno value otherwise and rte_errno is set.
3644  */
3645 static int
3646 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3647                                     const struct rte_flow_action *action,
3648                                     const uint64_t item_flags,
3649                                     struct rte_flow_error *error)
3650 {
3651         int ret = 0;
3652         uint64_t layer;
3653
3654         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3655         if (!ret) {
3656                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3657                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3658                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3659                 if (!(item_flags & layer))
3660                         return rte_flow_error_set(error, EINVAL,
3661                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3662                                                   NULL,
3663                                                   "no ipv4 item in pattern");
3664         }
3665         return ret;
3666 }
3667
3668 /**
3669  * Validate the modify-header IPv6 address actions.
3670  *
3671  * @param[in] action_flags
3672  *   Holds the actions detected until now.
3673  * @param[in] action
3674  *   Pointer to the modify action.
3675  * @param[in] item_flags
3676  *   Holds the items detected.
3677  * @param[out] error
3678  *   Pointer to error structure.
3679  *
3680  * @return
3681  *   0 on success, a negative errno value otherwise and rte_errno is set.
3682  */
3683 static int
3684 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3685                                     const struct rte_flow_action *action,
3686                                     const uint64_t item_flags,
3687                                     struct rte_flow_error *error)
3688 {
3689         int ret = 0;
3690         uint64_t layer;
3691
3692         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3693         if (!ret) {
3694                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3695                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3696                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3697                 if (!(item_flags & layer))
3698                         return rte_flow_error_set(error, EINVAL,
3699                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3700                                                   NULL,
3701                                                   "no ipv6 item in pattern");
3702         }
3703         return ret;
3704 }
3705
3706 /**
3707  * Validate the modify-header TP actions.
3708  *
3709  * @param[in] action_flags
3710  *   Holds the actions detected until now.
3711  * @param[in] action
3712  *   Pointer to the modify action.
3713  * @param[in] item_flags
3714  *   Holds the items detected.
3715  * @param[out] error
3716  *   Pointer to error structure.
3717  *
3718  * @return
3719  *   0 on success, a negative errno value otherwise and rte_errno is set.
3720  */
3721 static int
3722 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3723                                   const struct rte_flow_action *action,
3724                                   const uint64_t item_flags,
3725                                   struct rte_flow_error *error)
3726 {
3727         int ret = 0;
3728         uint64_t layer;
3729
3730         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3731         if (!ret) {
3732                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3733                                  MLX5_FLOW_LAYER_INNER_L4 :
3734                                  MLX5_FLOW_LAYER_OUTER_L4;
3735                 if (!(item_flags & layer))
3736                         return rte_flow_error_set(error, EINVAL,
3737                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3738                                                   NULL, "no transport layer "
3739                                                   "in pattern");
3740         }
3741         return ret;
3742 }
3743
3744 /**
3745  * Validate the modify-header actions of increment/decrement
3746  * TCP Sequence-number.
3747  *
3748  * @param[in] action_flags
3749  *   Holds the actions detected until now.
3750  * @param[in] action
3751  *   Pointer to the modify action.
3752  * @param[in] item_flags
3753  *   Holds the items detected.
3754  * @param[out] error
3755  *   Pointer to error structure.
3756  *
3757  * @return
3758  *   0 on success, a negative errno value otherwise and rte_errno is set.
3759  */
3760 static int
3761 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3762                                        const struct rte_flow_action *action,
3763                                        const uint64_t item_flags,
3764                                        struct rte_flow_error *error)
3765 {
3766         int ret = 0;
3767         uint64_t layer;
3768
3769         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3770         if (!ret) {
3771                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3772                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3773                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3774                 if (!(item_flags & layer))
3775                         return rte_flow_error_set(error, EINVAL,
3776                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3777                                                   NULL, "no TCP item in"
3778                                                   " pattern");
3779                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3780                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3781                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3782                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3783                         return rte_flow_error_set(error, EINVAL,
3784                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3785                                                   NULL,
3786                                                   "cannot decrease and increase"
3787                                                   " TCP sequence number"
3788                                                   " at the same time");
3789         }
3790         return ret;
3791 }
3792
3793 /**
3794  * Validate the modify-header actions of increment/decrement
3795  * TCP Acknowledgment number.
3796  *
3797  * @param[in] action_flags
3798  *   Holds the actions detected until now.
3799  * @param[in] action
3800  *   Pointer to the modify action.
3801  * @param[in] item_flags
3802  *   Holds the items detected.
3803  * @param[out] error
3804  *   Pointer to error structure.
3805  *
3806  * @return
3807  *   0 on success, a negative errno value otherwise and rte_errno is set.
3808  */
3809 static int
3810 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3811                                        const struct rte_flow_action *action,
3812                                        const uint64_t item_flags,
3813                                        struct rte_flow_error *error)
3814 {
3815         int ret = 0;
3816         uint64_t layer;
3817
3818         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3819         if (!ret) {
3820                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3821                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3822                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3823                 if (!(item_flags & layer))
3824                         return rte_flow_error_set(error, EINVAL,
3825                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3826                                                   NULL, "no TCP item in"
3827                                                   " pattern");
3828                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3829                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3830                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3831                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3832                         return rte_flow_error_set(error, EINVAL,
3833                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3834                                                   NULL,
3835                                                   "cannot decrease and increase"
3836                                                   " TCP acknowledgment number"
3837                                                   " at the same time");
3838         }
3839         return ret;
3840 }
3841
3842 /**
3843  * Validate the modify-header TTL actions.
3844  *
3845  * @param[in] action_flags
3846  *   Holds the actions detected until now.
3847  * @param[in] action
3848  *   Pointer to the modify action.
3849  * @param[in] item_flags
3850  *   Holds the items detected.
3851  * @param[out] error
3852  *   Pointer to error structure.
3853  *
3854  * @return
3855  *   0 on success, a negative errno value otherwise and rte_errno is set.
3856  */
3857 static int
3858 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3859                                    const struct rte_flow_action *action,
3860                                    const uint64_t item_flags,
3861                                    struct rte_flow_error *error)
3862 {
3863         int ret = 0;
3864         uint64_t layer;
3865
3866         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3867         if (!ret) {
3868                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3869                                  MLX5_FLOW_LAYER_INNER_L3 :
3870                                  MLX5_FLOW_LAYER_OUTER_L3;
3871                 if (!(item_flags & layer))
3872                         return rte_flow_error_set(error, EINVAL,
3873                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                   NULL,
3875                                                   "no IP protocol in pattern");
3876         }
3877         return ret;
3878 }
3879
3880 /**
3881  * Validate jump action.
3882  *
3883  * @param[in] action
3884  *   Pointer to the jump action.
3885  * @param[in] action_flags
3886  *   Holds the actions detected until now.
3887  * @param[in] attributes
3888  *   Pointer to flow attributes
3889  * @param[in] external
3890  *   Action belongs to flow rule created by request external to PMD.
3891  * @param[out] error
3892  *   Pointer to error structure.
3893  *
3894  * @return
3895  *   0 on success, a negative errno value otherwise and rte_errno is set.
3896  */
3897 static int
3898 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3899                              const struct mlx5_flow_tunnel *tunnel,
3900                              const struct rte_flow_action *action,
3901                              uint64_t action_flags,
3902                              const struct rte_flow_attr *attributes,
3903                              bool external, struct rte_flow_error *error)
3904 {
3905         uint32_t target_group, table;
3906         int ret = 0;
3907         struct flow_grp_info grp_info = {
3908                 .external = !!external,
3909                 .transfer = !!attributes->transfer,
3910                 .fdb_def_rule = 1,
3911                 .std_tbl_fix = 0
3912         };
3913         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3914                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3915                 return rte_flow_error_set(error, EINVAL,
3916                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3917                                           "can't have 2 fate actions in"
3918                                           " same flow");
3919         if (action_flags & MLX5_FLOW_ACTION_METER)
3920                 return rte_flow_error_set(error, ENOTSUP,
3921                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3922                                           "jump with meter not support");
3923         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3924                 return rte_flow_error_set(error, EINVAL,
3925                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3926                                           "E-Switch mirroring can't support"
3927                                           " Sample action and jump action in"
3928                                           " same flow now");
3929         if (!action->conf)
3930                 return rte_flow_error_set(error, EINVAL,
3931                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3932                                           NULL, "action configuration not set");
3933         target_group =
3934                 ((const struct rte_flow_action_jump *)action->conf)->group;
3935         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3936                                        grp_info, error);
3937         if (ret)
3938                 return ret;
3939         if (attributes->group == target_group &&
3940             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3941                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3942                 return rte_flow_error_set(error, EINVAL,
3943                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3944                                           "target group must be other than"
3945                                           " the current flow group");
3946         return 0;
3947 }
3948
3949 /*
3950  * Validate the port_id action.
3951  *
3952  * @param[in] dev
3953  *   Pointer to rte_eth_dev structure.
3954  * @param[in] action_flags
3955  *   Bit-fields that holds the actions detected until now.
3956  * @param[in] action
3957  *   Port_id RTE action structure.
3958  * @param[in] attr
3959  *   Attributes of flow that includes this action.
3960  * @param[out] error
3961  *   Pointer to error structure.
3962  *
3963  * @return
3964  *   0 on success, a negative errno value otherwise and rte_errno is set.
3965  */
3966 static int
3967 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3968                                 uint64_t action_flags,
3969                                 const struct rte_flow_action *action,
3970                                 const struct rte_flow_attr *attr,
3971                                 struct rte_flow_error *error)
3972 {
3973         const struct rte_flow_action_port_id *port_id;
3974         struct mlx5_priv *act_priv;
3975         struct mlx5_priv *dev_priv;
3976         uint16_t port;
3977
3978         if (!attr->transfer)
3979                 return rte_flow_error_set(error, ENOTSUP,
3980                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3981                                           NULL,
3982                                           "port id action is valid in transfer"
3983                                           " mode only");
3984         if (!action || !action->conf)
3985                 return rte_flow_error_set(error, ENOTSUP,
3986                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3987                                           NULL,
3988                                           "port id action parameters must be"
3989                                           " specified");
3990         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3991                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3992                 return rte_flow_error_set(error, EINVAL,
3993                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3994                                           "can have only one fate actions in"
3995                                           " a flow");
3996         dev_priv = mlx5_dev_to_eswitch_info(dev);
3997         if (!dev_priv)
3998                 return rte_flow_error_set(error, rte_errno,
3999                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4000                                           NULL,
4001                                           "failed to obtain E-Switch info");
4002         port_id = action->conf;
4003         port = port_id->original ? dev->data->port_id : port_id->id;
4004         act_priv = mlx5_port_to_eswitch_info(port, false);
4005         if (!act_priv)
4006                 return rte_flow_error_set
4007                                 (error, rte_errno,
4008                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4009                                  "failed to obtain E-Switch port id for port");
4010         if (act_priv->domain_id != dev_priv->domain_id)
4011                 return rte_flow_error_set
4012                                 (error, EINVAL,
4013                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4014                                  "port does not belong to"
4015                                  " E-Switch being configured");
4016         return 0;
4017 }
4018
4019 /**
4020  * Get the maximum number of modify header actions.
4021  *
4022  * @param dev
4023  *   Pointer to rte_eth_dev structure.
4024  * @param flags
4025  *   Flags bits to check if root level.
4026  *
4027  * @return
4028  *   Max number of modify header actions device can support.
4029  */
4030 static inline unsigned int
4031 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4032                               uint64_t flags)
4033 {
4034         /*
4035          * There's no way to directly query the max capacity from FW.
4036          * The maximal value on root table should be assumed to be supported.
4037          */
4038         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4039                 return MLX5_MAX_MODIFY_NUM;
4040         else
4041                 return MLX5_ROOT_TBL_MODIFY_NUM;
4042 }
4043
4044 /**
4045  * Validate the meter action.
4046  *
4047  * @param[in] dev
4048  *   Pointer to rte_eth_dev structure.
4049  * @param[in] action_flags
4050  *   Bit-fields that holds the actions detected until now.
4051  * @param[in] action
4052  *   Pointer to the meter action.
4053  * @param[in] attr
4054  *   Attributes of flow that includes this action.
4055  * @param[out] error
4056  *   Pointer to error structure.
4057  *
4058  * @return
4059  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4060  */
4061 static int
4062 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4063                                 uint64_t action_flags,
4064                                 const struct rte_flow_action *action,
4065                                 const struct rte_flow_attr *attr,
4066                                 struct rte_flow_error *error)
4067 {
4068         struct mlx5_priv *priv = dev->data->dev_private;
4069         const struct rte_flow_action_meter *am = action->conf;
4070         struct mlx5_flow_meter *fm;
4071
4072         if (!am)
4073                 return rte_flow_error_set(error, EINVAL,
4074                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4075                                           "meter action conf is NULL");
4076
4077         if (action_flags & MLX5_FLOW_ACTION_METER)
4078                 return rte_flow_error_set(error, ENOTSUP,
4079                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4080                                           "meter chaining not support");
4081         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4082                 return rte_flow_error_set(error, ENOTSUP,
4083                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4084                                           "meter with jump not support");
4085         if (!priv->mtr_en)
4086                 return rte_flow_error_set(error, ENOTSUP,
4087                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4088                                           NULL,
4089                                           "meter action not supported");
4090         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4091         if (!fm)
4092                 return rte_flow_error_set(error, EINVAL,
4093                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4094                                           "Meter not found");
4095         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4096               (!fm->ingress && !attr->ingress && attr->egress) ||
4097               (!fm->egress && !attr->egress && attr->ingress))))
4098                 return rte_flow_error_set(error, EINVAL,
4099                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4100                                           "Flow attributes are either invalid "
4101                                           "or have a conflict with current "
4102                                           "meter attributes");
4103         return 0;
4104 }
4105
4106 /**
4107  * Validate the age action.
4108  *
4109  * @param[in] action_flags
4110  *   Holds the actions detected until now.
4111  * @param[in] action
4112  *   Pointer to the age action.
4113  * @param[in] dev
4114  *   Pointer to the Ethernet device structure.
4115  * @param[out] error
4116  *   Pointer to error structure.
4117  *
4118  * @return
4119  *   0 on success, a negative errno value otherwise and rte_errno is set.
4120  */
4121 static int
4122 flow_dv_validate_action_age(uint64_t action_flags,
4123                             const struct rte_flow_action *action,
4124                             struct rte_eth_dev *dev,
4125                             struct rte_flow_error *error)
4126 {
4127         struct mlx5_priv *priv = dev->data->dev_private;
4128         const struct rte_flow_action_age *age = action->conf;
4129
4130         if (!priv->config.devx || priv->sh->cmng.counter_fallback)
4131                 return rte_flow_error_set(error, ENOTSUP,
4132                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4133                                           NULL,
4134                                           "age action not supported");
4135         if (!(action->conf))
4136                 return rte_flow_error_set(error, EINVAL,
4137                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4138                                           "configuration cannot be null");
4139         if (!(age->timeout))
4140                 return rte_flow_error_set(error, EINVAL,
4141                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4142                                           "invalid timeout value 0");
4143         if (action_flags & MLX5_FLOW_ACTION_AGE)
4144                 return rte_flow_error_set(error, EINVAL,
4145                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4146                                           "duplicate age actions set");
4147         return 0;
4148 }
4149
4150 /**
4151  * Validate the modify-header IPv4 DSCP actions.
4152  *
4153  * @param[in] action_flags
4154  *   Holds the actions detected until now.
4155  * @param[in] action
4156  *   Pointer to the modify action.
4157  * @param[in] item_flags
4158  *   Holds the items detected.
4159  * @param[out] error
4160  *   Pointer to error structure.
4161  *
4162  * @return
4163  *   0 on success, a negative errno value otherwise and rte_errno is set.
4164  */
4165 static int
4166 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4167                                          const struct rte_flow_action *action,
4168                                          const uint64_t item_flags,
4169                                          struct rte_flow_error *error)
4170 {
4171         int ret = 0;
4172
4173         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4174         if (!ret) {
4175                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4176                         return rte_flow_error_set(error, EINVAL,
4177                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4178                                                   NULL,
4179                                                   "no ipv4 item in pattern");
4180         }
4181         return ret;
4182 }
4183
4184 /**
4185  * Validate the modify-header IPv6 DSCP actions.
4186  *
4187  * @param[in] action_flags
4188  *   Holds the actions detected until now.
4189  * @param[in] action
4190  *   Pointer to the modify action.
4191  * @param[in] item_flags
4192  *   Holds the items detected.
4193  * @param[out] error
4194  *   Pointer to error structure.
4195  *
4196  * @return
4197  *   0 on success, a negative errno value otherwise and rte_errno is set.
4198  */
4199 static int
4200 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4201                                          const struct rte_flow_action *action,
4202                                          const uint64_t item_flags,
4203                                          struct rte_flow_error *error)
4204 {
4205         int ret = 0;
4206
4207         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4208         if (!ret) {
4209                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4210                         return rte_flow_error_set(error, EINVAL,
4211                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4212                                                   NULL,
4213                                                   "no ipv6 item in pattern");
4214         }
4215         return ret;
4216 }
4217
4218 /**
4219  * Match modify-header resource.
4220  *
4221  * @param entry
4222  *   Pointer to exist resource entry object.
4223  * @param ctx
4224  *   Pointer to new modify-header resource.
4225  *
4226  * @return
4227  *   0 on matching, -1 otherwise.
4228  */
4229 static int
4230 flow_dv_modify_hdr_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
4231 {
4232         struct mlx5_flow_dv_modify_hdr_resource *resource;
4233         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4234         uint32_t actions_len;
4235
4236         resource = (struct mlx5_flow_dv_modify_hdr_resource *)ctx;
4237         cache_resource = container_of(entry,
4238                                       struct mlx5_flow_dv_modify_hdr_resource,
4239                                       entry);
4240         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4241         if (resource->entry.key == cache_resource->entry.key &&
4242             resource->ft_type == cache_resource->ft_type &&
4243             resource->actions_num == cache_resource->actions_num &&
4244             resource->flags == cache_resource->flags &&
4245             !memcmp((const void *)resource->actions,
4246                     (const void *)cache_resource->actions,
4247                     actions_len))
4248                 return 0;
4249         return -1;
4250 }
4251
4252 /**
4253  * Validate the sample action.
4254  *
4255  * @param[in] action_flags
4256  *   Holds the actions detected until now.
4257  * @param[in] action
4258  *   Pointer to the sample action.
4259  * @param[in] dev
4260  *   Pointer to the Ethernet device structure.
4261  * @param[in] attr
4262  *   Attributes of flow that includes this action.
4263  * @param[out] error
4264  *   Pointer to error structure.
4265  *
4266  * @return
4267  *   0 on success, a negative errno value otherwise and rte_errno is set.
4268  */
4269 static int
4270 flow_dv_validate_action_sample(uint64_t action_flags,
4271                                const struct rte_flow_action *action,
4272                                struct rte_eth_dev *dev,
4273                                const struct rte_flow_attr *attr,
4274                                struct rte_flow_error *error)
4275 {
4276         struct mlx5_priv *priv = dev->data->dev_private;
4277         struct mlx5_dev_config *dev_conf = &priv->config;
4278         const struct rte_flow_action_sample *sample = action->conf;
4279         const struct rte_flow_action *act;
4280         uint64_t sub_action_flags = 0;
4281         uint16_t queue_index = 0xFFFF;
4282         int actions_n = 0;
4283         int ret;
4284         fdb_mirror = 0;
4285
4286         if (!sample)
4287                 return rte_flow_error_set(error, EINVAL,
4288                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4289                                           "configuration cannot be NULL");
4290         if (sample->ratio == 0)
4291                 return rte_flow_error_set(error, EINVAL,
4292                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4293                                           "ratio value starts from 1");
4294         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4295                 return rte_flow_error_set(error, ENOTSUP,
4296                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4297                                           NULL,
4298                                           "sample action not supported");
4299         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4300                 return rte_flow_error_set(error, EINVAL,
4301                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4302                                           "Multiple sample actions not "
4303                                           "supported");
4304         if (action_flags & MLX5_FLOW_ACTION_METER)
4305                 return rte_flow_error_set(error, EINVAL,
4306                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4307                                           "wrong action order, meter should "
4308                                           "be after sample action");
4309         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4310                 return rte_flow_error_set(error, EINVAL,
4311                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4312                                           "wrong action order, jump should "
4313                                           "be after sample action");
4314         act = sample->actions;
4315         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4316                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4317                         return rte_flow_error_set(error, ENOTSUP,
4318                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4319                                                   act, "too many actions");
4320                 switch (act->type) {
4321                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4322                         ret = mlx5_flow_validate_action_queue(act,
4323                                                               sub_action_flags,
4324                                                               dev,
4325                                                               attr, error);
4326                         if (ret < 0)
4327                                 return ret;
4328                         queue_index = ((const struct rte_flow_action_queue *)
4329                                                         (act->conf))->index;
4330                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4331                         ++actions_n;
4332                         break;
4333                 case RTE_FLOW_ACTION_TYPE_MARK:
4334                         ret = flow_dv_validate_action_mark(dev, act,
4335                                                            sub_action_flags,
4336                                                            attr, error);
4337                         if (ret < 0)
4338                                 return ret;
4339                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4340                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4341                                                 MLX5_FLOW_ACTION_MARK_EXT;
4342                         else
4343                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4344                         ++actions_n;
4345                         break;
4346                 case RTE_FLOW_ACTION_TYPE_COUNT:
4347                         ret = flow_dv_validate_action_count(dev, error);
4348                         if (ret < 0)
4349                                 return ret;
4350                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4351                         ++actions_n;
4352                         break;
4353                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4354                         ret = flow_dv_validate_action_port_id(dev,
4355                                                               sub_action_flags,
4356                                                               act,
4357                                                               attr,
4358                                                               error);
4359                         if (ret)
4360                                 return ret;
4361                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4362                         ++actions_n;
4363                         break;
4364                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4365                         ret = flow_dv_validate_action_raw_encap_decap
4366                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4367                                  &actions_n, error);
4368                         if (ret < 0)
4369                                 return ret;
4370                         ++actions_n;
4371                         break;
4372                 default:
4373                         return rte_flow_error_set(error, ENOTSUP,
4374                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4375                                                   NULL,
4376                                                   "Doesn't support optional "
4377                                                   "action");
4378                 }
4379         }
4380         if (attr->ingress && !attr->transfer) {
4381                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4382                         return rte_flow_error_set(error, EINVAL,
4383                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4384                                                   NULL,
4385                                                   "Ingress must has a dest "
4386                                                   "QUEUE for Sample");
4387         } else if (attr->egress && !attr->transfer) {
4388                 return rte_flow_error_set(error, ENOTSUP,
4389                                           RTE_FLOW_ERROR_TYPE_ACTION,
4390                                           NULL,
4391                                           "Sample Only support Ingress "
4392                                           "or E-Switch");
4393         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4394                 MLX5_ASSERT(attr->transfer);
4395                 if (sample->ratio > 1)
4396                         return rte_flow_error_set(error, ENOTSUP,
4397                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4398                                                   NULL,
4399                                                   "E-Switch doesn't support "
4400                                                   "any optional action "
4401                                                   "for sampling");
4402                 fdb_mirror = 1;
4403                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4404                         return rte_flow_error_set(error, ENOTSUP,
4405                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4406                                                   NULL,
4407                                                   "unsupported action QUEUE");
4408                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4409                         return rte_flow_error_set(error, EINVAL,
4410                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4411                                                   NULL,
4412                                                   "E-Switch must has a dest "
4413                                                   "port for mirroring");
4414         }
4415         /* Continue validation for Xcap actions.*/
4416         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4417             (queue_index == 0xFFFF ||
4418              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4419                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4420                      MLX5_FLOW_XCAP_ACTIONS)
4421                         return rte_flow_error_set(error, ENOTSUP,
4422                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4423                                                   NULL, "encap and decap "
4424                                                   "combination aren't "
4425                                                   "supported");
4426                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4427                                                         MLX5_FLOW_ACTION_ENCAP))
4428                         return rte_flow_error_set(error, ENOTSUP,
4429                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4430                                                   NULL, "encap is not supported"
4431                                                   " for ingress traffic");
4432         }
4433         return 0;
4434 }
4435
4436 /**
4437  * Find existing modify-header resource or create and register a new one.
4438  *
4439  * @param dev[in, out]
4440  *   Pointer to rte_eth_dev structure.
4441  * @param[in, out] resource
4442  *   Pointer to modify-header resource.
4443  * @parm[in, out] dev_flow
4444  *   Pointer to the dev_flow.
4445  * @param[out] error
4446  *   pointer to error structure.
4447  *
4448  * @return
4449  *   0 on success otherwise -errno and errno is set.
4450  */
4451 static int
4452 flow_dv_modify_hdr_resource_register
4453                         (struct rte_eth_dev *dev,
4454                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4455                          struct mlx5_flow *dev_flow,
4456                          struct rte_flow_error *error)
4457 {
4458         struct mlx5_priv *priv = dev->data->dev_private;
4459         struct mlx5_dev_ctx_shared *sh = priv->sh;
4460         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4461         struct mlx5dv_dr_domain *ns;
4462         uint32_t actions_len;
4463         struct mlx5_hlist_entry *entry;
4464         union mlx5_flow_modify_hdr_key hdr_mod_key = {
4465                 {
4466                         .ft_type = resource->ft_type,
4467                         .actions_num = resource->actions_num,
4468                         .group = dev_flow->dv.group,
4469                         .cksum = 0,
4470                 }
4471         };
4472         int ret;
4473
4474         resource->flags = dev_flow->dv.group ? 0 :
4475                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4476         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4477                                     resource->flags))
4478                 return rte_flow_error_set(error, EOVERFLOW,
4479                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4480                                           "too many modify header items");
4481         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4482                 ns = sh->fdb_domain;
4483         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4484                 ns = sh->tx_domain;
4485         else
4486                 ns = sh->rx_domain;
4487         /* Lookup a matching resource from cache. */
4488         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4489         hdr_mod_key.cksum = __rte_raw_cksum(resource->actions, actions_len, 0);
4490         resource->entry.key = hdr_mod_key.v64;
4491         entry = mlx5_hlist_lookup_ex(sh->modify_cmds, resource->entry.key,
4492                                      flow_dv_modify_hdr_resource_match,
4493                                      (void *)resource);
4494         if (entry) {
4495                 cache_resource = container_of(entry,
4496                                         struct mlx5_flow_dv_modify_hdr_resource,
4497                                         entry);
4498                 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4499                         (void *)cache_resource,
4500                         __atomic_load_n(&cache_resource->refcnt,
4501                                         __ATOMIC_RELAXED));
4502                 __atomic_fetch_add(&cache_resource->refcnt, 1,
4503                                    __ATOMIC_RELAXED);
4504                 dev_flow->handle->dvh.modify_hdr = cache_resource;
4505                 return 0;
4506
4507         }
4508         /* Register new modify-header resource. */
4509         cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4510                                     sizeof(*cache_resource) + actions_len, 0,
4511                                     SOCKET_ID_ANY);
4512         if (!cache_resource)
4513                 return rte_flow_error_set(error, ENOMEM,
4514                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4515                                           "cannot allocate resource memory");
4516         *cache_resource = *resource;
4517         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4518         ret = mlx5_flow_os_create_flow_action_modify_header
4519                                         (sh->ctx, ns, cache_resource,
4520                                          actions_len, &cache_resource->action);
4521         if (ret) {
4522                 mlx5_free(cache_resource);
4523                 return rte_flow_error_set(error, ENOMEM,
4524                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4525                                           NULL, "cannot create action");
4526         }
4527         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
4528         if (mlx5_hlist_insert_ex(sh->modify_cmds, &cache_resource->entry,
4529                                  flow_dv_modify_hdr_resource_match,
4530                                  (void *)cache_resource)) {
4531                 claim_zero(mlx5_flow_os_destroy_flow_action
4532                                                 (cache_resource->action));
4533                 mlx5_free(cache_resource);
4534                 return rte_flow_error_set(error, EEXIST,
4535                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4536                                           NULL, "action exist");
4537         }
4538         dev_flow->handle->dvh.modify_hdr = cache_resource;
4539         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4540                 (void *)cache_resource,
4541                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
4542         return 0;
4543 }
4544
4545 /**
4546  * Get DV flow counter by index.
4547  *
4548  * @param[in] dev
4549  *   Pointer to the Ethernet device structure.
4550  * @param[in] idx
4551  *   mlx5 flow counter index in the container.
4552  * @param[out] ppool
4553  *   mlx5 flow counter pool in the container,
4554  *
4555  * @return
4556  *   Pointer to the counter, NULL otherwise.
4557  */
4558 static struct mlx5_flow_counter *
4559 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4560                            uint32_t idx,
4561                            struct mlx5_flow_counter_pool **ppool)
4562 {
4563         struct mlx5_priv *priv = dev->data->dev_private;
4564         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4565         struct mlx5_flow_counter_pool *pool;
4566
4567         /* Decrease to original index and clear shared bit. */
4568         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4569         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4570         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4571         MLX5_ASSERT(pool);
4572         if (ppool)
4573                 *ppool = pool;
4574         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4575 }
4576
4577 /**
4578  * Check the devx counter belongs to the pool.
4579  *
4580  * @param[in] pool
4581  *   Pointer to the counter pool.
4582  * @param[in] id
4583  *   The counter devx ID.
4584  *
4585  * @return
4586  *   True if counter belongs to the pool, false otherwise.
4587  */
4588 static bool
4589 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4590 {
4591         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4592                    MLX5_COUNTERS_PER_POOL;
4593
4594         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4595                 return true;
4596         return false;
4597 }
4598
4599 /**
4600  * Get a pool by devx counter ID.
4601  *
4602  * @param[in] cmng
4603  *   Pointer to the counter management.
4604  * @param[in] id
4605  *   The counter devx ID.
4606  *
4607  * @return
4608  *   The counter pool pointer if exists, NULL otherwise,
4609  */
4610 static struct mlx5_flow_counter_pool *
4611 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4612 {
4613         uint32_t i;
4614         struct mlx5_flow_counter_pool *pool = NULL;
4615
4616         rte_spinlock_lock(&cmng->pool_update_sl);
4617         /* Check last used pool. */
4618         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4619             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4620                 pool = cmng->pools[cmng->last_pool_idx];
4621                 goto out;
4622         }
4623         /* ID out of range means no suitable pool in the container. */
4624         if (id > cmng->max_id || id < cmng->min_id)
4625                 goto out;
4626         /*
4627          * Find the pool from the end of the container, since mostly counter
4628          * ID is sequence increasing, and the last pool should be the needed
4629          * one.
4630          */
4631         i = cmng->n_valid;
4632         while (i--) {
4633                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4634
4635                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4636                         pool = pool_tmp;
4637                         break;
4638                 }
4639         }
4640 out:
4641         rte_spinlock_unlock(&cmng->pool_update_sl);
4642         return pool;
4643 }
4644
4645 /**
4646  * Resize a counter container.
4647  *
4648  * @param[in] dev
4649  *   Pointer to the Ethernet device structure.
4650  *
4651  * @return
4652  *   0 on success, otherwise negative errno value and rte_errno is set.
4653  */
4654 static int
4655 flow_dv_container_resize(struct rte_eth_dev *dev)
4656 {
4657         struct mlx5_priv *priv = dev->data->dev_private;
4658         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4659         void *old_pools = cmng->pools;
4660         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4661         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4662         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4663
4664         if (!pools) {
4665                 rte_errno = ENOMEM;
4666                 return -ENOMEM;
4667         }
4668         if (old_pools)
4669                 memcpy(pools, old_pools, cmng->n *
4670                                        sizeof(struct mlx5_flow_counter_pool *));
4671         cmng->n = resize;
4672         cmng->pools = pools;
4673         if (old_pools)
4674                 mlx5_free(old_pools);
4675         return 0;
4676 }
4677
4678 /**
4679  * Query a devx flow counter.
4680  *
4681  * @param[in] dev
4682  *   Pointer to the Ethernet device structure.
4683  * @param[in] cnt
4684  *   Index to the flow counter.
4685  * @param[out] pkts
4686  *   The statistics value of packets.
4687  * @param[out] bytes
4688  *   The statistics value of bytes.
4689  *
4690  * @return
4691  *   0 on success, otherwise a negative errno value and rte_errno is set.
4692  */
4693 static inline int
4694 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4695                      uint64_t *bytes)
4696 {
4697         struct mlx5_priv *priv = dev->data->dev_private;
4698         struct mlx5_flow_counter_pool *pool = NULL;
4699         struct mlx5_flow_counter *cnt;
4700         int offset;
4701
4702         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4703         MLX5_ASSERT(pool);
4704         if (priv->sh->cmng.counter_fallback)
4705                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4706                                         0, pkts, bytes, 0, NULL, NULL, 0);
4707         rte_spinlock_lock(&pool->sl);
4708         if (!pool->raw) {
4709                 *pkts = 0;
4710                 *bytes = 0;
4711         } else {
4712                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4713                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4714                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4715         }
4716         rte_spinlock_unlock(&pool->sl);
4717         return 0;
4718 }
4719
4720 /**
4721  * Create and initialize a new counter pool.
4722  *
4723  * @param[in] dev
4724  *   Pointer to the Ethernet device structure.
4725  * @param[out] dcs
4726  *   The devX counter handle.
4727  * @param[in] age
4728  *   Whether the pool is for counter that was allocated for aging.
4729  * @param[in/out] cont_cur
4730  *   Pointer to the container pointer, it will be update in pool resize.
4731  *
4732  * @return
4733  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4734  */
4735 static struct mlx5_flow_counter_pool *
4736 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4737                     uint32_t age)
4738 {
4739         struct mlx5_priv *priv = dev->data->dev_private;
4740         struct mlx5_flow_counter_pool *pool;
4741         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4742         bool fallback = priv->sh->cmng.counter_fallback;
4743         uint32_t size = sizeof(*pool);
4744
4745         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4746         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4747         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4748         if (!pool) {
4749                 rte_errno = ENOMEM;
4750                 return NULL;
4751         }
4752         pool->raw = NULL;
4753         pool->is_aged = !!age;
4754         pool->query_gen = 0;
4755         pool->min_dcs = dcs;
4756         rte_spinlock_init(&pool->sl);
4757         rte_spinlock_init(&pool->csl);
4758         TAILQ_INIT(&pool->counters[0]);
4759         TAILQ_INIT(&pool->counters[1]);
4760         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4761         rte_spinlock_lock(&cmng->pool_update_sl);
4762         pool->index = cmng->n_valid;
4763         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4764                 mlx5_free(pool);
4765                 rte_spinlock_unlock(&cmng->pool_update_sl);
4766                 return NULL;
4767         }
4768         cmng->pools[pool->index] = pool;
4769         cmng->n_valid++;
4770         if (unlikely(fallback)) {
4771                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4772
4773                 if (base < cmng->min_id)
4774                         cmng->min_id = base;
4775                 if (base > cmng->max_id)
4776                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4777                 cmng->last_pool_idx = pool->index;
4778         }
4779         rte_spinlock_unlock(&cmng->pool_update_sl);
4780         return pool;
4781 }
4782
4783 /**
4784  * Prepare a new counter and/or a new counter pool.
4785  *
4786  * @param[in] dev
4787  *   Pointer to the Ethernet device structure.
4788  * @param[out] cnt_free
4789  *   Where to put the pointer of a new counter.
4790  * @param[in] age
4791  *   Whether the pool is for counter that was allocated for aging.
4792  *
4793  * @return
4794  *   The counter pool pointer and @p cnt_free is set on success,
4795  *   NULL otherwise and rte_errno is set.
4796  */
4797 static struct mlx5_flow_counter_pool *
4798 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4799                              struct mlx5_flow_counter **cnt_free,
4800                              uint32_t age)
4801 {
4802         struct mlx5_priv *priv = dev->data->dev_private;
4803         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4804         struct mlx5_flow_counter_pool *pool;
4805         struct mlx5_counters tmp_tq;
4806         struct mlx5_devx_obj *dcs = NULL;
4807         struct mlx5_flow_counter *cnt;
4808         enum mlx5_counter_type cnt_type =
4809                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4810         bool fallback = priv->sh->cmng.counter_fallback;
4811         uint32_t i;
4812
4813         if (fallback) {
4814                 /* bulk_bitmap must be 0 for single counter allocation. */
4815                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4816                 if (!dcs)
4817                         return NULL;
4818                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4819                 if (!pool) {
4820                         pool = flow_dv_pool_create(dev, dcs, age);
4821                         if (!pool) {
4822                                 mlx5_devx_cmd_destroy(dcs);
4823                                 return NULL;
4824                         }
4825                 }
4826                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4827                 cnt = MLX5_POOL_GET_CNT(pool, i);
4828                 cnt->pool = pool;
4829                 cnt->dcs_when_free = dcs;
4830                 *cnt_free = cnt;
4831                 return pool;
4832         }
4833         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4834         if (!dcs) {
4835                 rte_errno = ENODATA;
4836                 return NULL;
4837         }
4838         pool = flow_dv_pool_create(dev, dcs, age);
4839         if (!pool) {
4840                 mlx5_devx_cmd_destroy(dcs);
4841                 return NULL;
4842         }
4843         TAILQ_INIT(&tmp_tq);
4844         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4845                 cnt = MLX5_POOL_GET_CNT(pool, i);
4846                 cnt->pool = pool;
4847                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4848         }
4849         rte_spinlock_lock(&cmng->csl[cnt_type]);
4850         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4851         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4852         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4853         (*cnt_free)->pool = pool;
4854         return pool;
4855 }
4856
4857 /**
4858  * Allocate a flow counter.
4859  *
4860  * @param[in] dev
4861  *   Pointer to the Ethernet device structure.
4862  * @param[in] age
4863  *   Whether the counter was allocated for aging.
4864  *
4865  * @return
4866  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4867  */
4868 static uint32_t
4869 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4870 {
4871         struct mlx5_priv *priv = dev->data->dev_private;
4872         struct mlx5_flow_counter_pool *pool = NULL;
4873         struct mlx5_flow_counter *cnt_free = NULL;
4874         bool fallback = priv->sh->cmng.counter_fallback;
4875         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4876         enum mlx5_counter_type cnt_type =
4877                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4878         uint32_t cnt_idx;
4879
4880         if (!priv->config.devx) {
4881                 rte_errno = ENOTSUP;
4882                 return 0;
4883         }
4884         /* Get free counters from container. */
4885         rte_spinlock_lock(&cmng->csl[cnt_type]);
4886         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4887         if (cnt_free)
4888                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4889         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4890         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4891                 goto err;
4892         pool = cnt_free->pool;
4893         if (fallback)
4894                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4895         /* Create a DV counter action only in the first time usage. */
4896         if (!cnt_free->action) {
4897                 uint16_t offset;
4898                 struct mlx5_devx_obj *dcs;
4899                 int ret;
4900
4901                 if (!fallback) {
4902                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4903                         dcs = pool->min_dcs;
4904                 } else {
4905                         offset = 0;
4906                         dcs = cnt_free->dcs_when_free;
4907                 }
4908                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4909                                                             &cnt_free->action);
4910                 if (ret) {
4911                         rte_errno = errno;
4912                         goto err;
4913                 }
4914         }
4915         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4916                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4917         /* Update the counter reset values. */
4918         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4919                                  &cnt_free->bytes))
4920                 goto err;
4921         if (!fallback && !priv->sh->cmng.query_thread_on)
4922                 /* Start the asynchronous batch query by the host thread. */
4923                 mlx5_set_query_alarm(priv->sh);
4924         return cnt_idx;
4925 err:
4926         if (cnt_free) {
4927                 cnt_free->pool = pool;
4928                 if (fallback)
4929                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4930                 rte_spinlock_lock(&cmng->csl[cnt_type]);
4931                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4932                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4933         }
4934         return 0;
4935 }
4936
4937 /**
4938  * Allocate a shared flow counter.
4939  *
4940  * @param[in] ctx
4941  *   Pointer to the shared counter configuration.
4942  * @param[in] data
4943  *   Pointer to save the allocated counter index.
4944  *
4945  * @return
4946  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4947  */
4948
4949 static int32_t
4950 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
4951 {
4952         struct mlx5_shared_counter_conf *conf = ctx;
4953         struct rte_eth_dev *dev = conf->dev;
4954         struct mlx5_flow_counter *cnt;
4955
4956         data->dword = flow_dv_counter_alloc(dev, 0);
4957         data->dword |= MLX5_CNT_SHARED_OFFSET;
4958         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
4959         cnt->shared_info.id = conf->id;
4960         return 0;
4961 }
4962
4963 /**
4964  * Get a shared flow counter.
4965  *
4966  * @param[in] dev
4967  *   Pointer to the Ethernet device structure.
4968  * @param[in] id
4969  *   Counter identifier.
4970  *
4971  * @return
4972  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4973  */
4974 static uint32_t
4975 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
4976 {
4977         struct mlx5_priv *priv = dev->data->dev_private;
4978         struct mlx5_shared_counter_conf conf = {
4979                 .dev = dev,
4980                 .id = id,
4981         };
4982         union mlx5_l3t_data data = {
4983                 .dword = 0,
4984         };
4985
4986         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
4987                                flow_dv_counter_alloc_shared_cb, &conf);
4988         return data.dword;
4989 }
4990
4991 /**
4992  * Get age param from counter index.
4993  *
4994  * @param[in] dev
4995  *   Pointer to the Ethernet device structure.
4996  * @param[in] counter
4997  *   Index to the counter handler.
4998  *
4999  * @return
5000  *   The aging parameter specified for the counter index.
5001  */
5002 static struct mlx5_age_param*
5003 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5004                                 uint32_t counter)
5005 {
5006         struct mlx5_flow_counter *cnt;
5007         struct mlx5_flow_counter_pool *pool = NULL;
5008
5009         flow_dv_counter_get_by_idx(dev, counter, &pool);
5010         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5011         cnt = MLX5_POOL_GET_CNT(pool, counter);
5012         return MLX5_CNT_TO_AGE(cnt);
5013 }
5014
5015 /**
5016  * Remove a flow counter from aged counter list.
5017  *
5018  * @param[in] dev
5019  *   Pointer to the Ethernet device structure.
5020  * @param[in] counter
5021  *   Index to the counter handler.
5022  * @param[in] cnt
5023  *   Pointer to the counter handler.
5024  */
5025 static void
5026 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5027                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5028 {
5029         struct mlx5_age_info *age_info;
5030         struct mlx5_age_param *age_param;
5031         struct mlx5_priv *priv = dev->data->dev_private;
5032         uint16_t expected = AGE_CANDIDATE;
5033
5034         age_info = GET_PORT_AGE_INFO(priv);
5035         age_param = flow_dv_counter_idx_get_age(dev, counter);
5036         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5037                                          AGE_FREE, false, __ATOMIC_RELAXED,
5038                                          __ATOMIC_RELAXED)) {
5039                 /**
5040                  * We need the lock even it is age timeout,
5041                  * since counter may still in process.
5042                  */
5043                 rte_spinlock_lock(&age_info->aged_sl);
5044                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5045                 rte_spinlock_unlock(&age_info->aged_sl);
5046                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5047         }
5048 }
5049
5050 /**
5051  * Release a flow counter.
5052  *
5053  * @param[in] dev
5054  *   Pointer to the Ethernet device structure.
5055  * @param[in] counter
5056  *   Index to the counter handler.
5057  */
5058 static void
5059 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
5060 {
5061         struct mlx5_priv *priv = dev->data->dev_private;
5062         struct mlx5_flow_counter_pool *pool = NULL;
5063         struct mlx5_flow_counter *cnt;
5064         enum mlx5_counter_type cnt_type;
5065
5066         if (!counter)
5067                 return;
5068         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5069         MLX5_ASSERT(pool);
5070         if (IS_SHARED_CNT(counter) &&
5071             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5072                 return;
5073         if (pool->is_aged)
5074                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5075         cnt->pool = pool;
5076         /*
5077          * Put the counter back to list to be updated in none fallback mode.
5078          * Currently, we are using two list alternately, while one is in query,
5079          * add the freed counter to the other list based on the pool query_gen
5080          * value. After query finishes, add counter the list to the global
5081          * container counter list. The list changes while query starts. In
5082          * this case, lock will not be needed as query callback and release
5083          * function both operate with the different list.
5084          *
5085          */
5086         if (!priv->sh->cmng.counter_fallback) {
5087                 rte_spinlock_lock(&pool->csl);
5088                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5089                 rte_spinlock_unlock(&pool->csl);
5090         } else {
5091                 cnt->dcs_when_free = cnt->dcs_when_active;
5092                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5093                                            MLX5_COUNTER_TYPE_ORIGIN;
5094                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5095                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5096                                   cnt, next);
5097                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5098         }
5099 }
5100
5101 /**
5102  * Verify the @p attributes will be correctly understood by the NIC and store
5103  * them in the @p flow if everything is correct.
5104  *
5105  * @param[in] dev
5106  *   Pointer to dev struct.
5107  * @param[in] attributes
5108  *   Pointer to flow attributes
5109  * @param[in] external
5110  *   This flow rule is created by request external to PMD.
5111  * @param[out] error
5112  *   Pointer to error structure.
5113  *
5114  * @return
5115  *   - 0 on success and non root table.
5116  *   - 1 on success and root table.
5117  *   - a negative errno value otherwise and rte_errno is set.
5118  */
5119 static int
5120 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5121                             const struct mlx5_flow_tunnel *tunnel,
5122                             const struct rte_flow_attr *attributes,
5123                             struct flow_grp_info grp_info,
5124                             struct rte_flow_error *error)
5125 {
5126         struct mlx5_priv *priv = dev->data->dev_private;
5127         uint32_t priority_max = priv->config.flow_prio - 1;
5128         int ret = 0;
5129
5130 #ifndef HAVE_MLX5DV_DR
5131         RTE_SET_USED(tunnel);
5132         RTE_SET_USED(grp_info);
5133         if (attributes->group)
5134                 return rte_flow_error_set(error, ENOTSUP,
5135                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5136                                           NULL,
5137                                           "groups are not supported");
5138 #else
5139         uint32_t table = 0;
5140
5141         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5142                                        grp_info, error);
5143         if (ret)
5144                 return ret;
5145         if (!table)
5146                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5147 #endif
5148         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5149             attributes->priority >= priority_max)
5150                 return rte_flow_error_set(error, ENOTSUP,
5151                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5152                                           NULL,
5153                                           "priority out of range");
5154         if (attributes->transfer) {
5155                 if (!priv->config.dv_esw_en)
5156                         return rte_flow_error_set
5157                                 (error, ENOTSUP,
5158                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5159                                  "E-Switch dr is not supported");
5160                 if (!(priv->representor || priv->master))
5161                         return rte_flow_error_set
5162                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5163                                  NULL, "E-Switch configuration can only be"
5164                                  " done by a master or a representor device");
5165                 if (attributes->egress)
5166                         return rte_flow_error_set
5167                                 (error, ENOTSUP,
5168                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5169                                  "egress is not supported");
5170         }
5171         if (!(attributes->egress ^ attributes->ingress))
5172                 return rte_flow_error_set(error, ENOTSUP,
5173                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5174                                           "must specify exactly one of "
5175                                           "ingress or egress");
5176         return ret;
5177 }
5178
5179 /**
5180  * Internal validation function. For validating both actions and items.
5181  *
5182  * @param[in] dev
5183  *   Pointer to the rte_eth_dev structure.
5184  * @param[in] attr
5185  *   Pointer to the flow attributes.
5186  * @param[in] items
5187  *   Pointer to the list of items.
5188  * @param[in] actions
5189  *   Pointer to the list of actions.
5190  * @param[in] external
5191  *   This flow rule is created by request external to PMD.
5192  * @param[in] hairpin
5193  *   Number of hairpin TX actions, 0 means classic flow.
5194  * @param[out] error
5195  *   Pointer to the error structure.
5196  *
5197  * @return
5198  *   0 on success, a negative errno value otherwise and rte_errno is set.
5199  */
5200 static int
5201 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5202                  const struct rte_flow_item items[],
5203                  const struct rte_flow_action actions[],
5204                  bool external, int hairpin, struct rte_flow_error *error)
5205 {
5206         int ret;
5207         uint64_t action_flags = 0;
5208         uint64_t item_flags = 0;
5209         uint64_t last_item = 0;
5210         uint8_t next_protocol = 0xff;
5211         uint16_t ether_type = 0;
5212         int actions_n = 0;
5213         uint8_t item_ipv6_proto = 0;
5214         const struct rte_flow_item *gre_item = NULL;
5215         const struct rte_flow_action_raw_decap *decap;
5216         const struct rte_flow_action_raw_encap *encap;
5217         const struct rte_flow_action_rss *rss;
5218         const struct rte_flow_item_tcp nic_tcp_mask = {
5219                 .hdr = {
5220                         .tcp_flags = 0xFF,
5221                         .src_port = RTE_BE16(UINT16_MAX),
5222                         .dst_port = RTE_BE16(UINT16_MAX),
5223                 }
5224         };
5225         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5226                 .hdr = {
5227                         .src_addr =
5228                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5229                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5230                         .dst_addr =
5231                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5232                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5233                         .vtc_flow = RTE_BE32(0xffffffff),
5234                         .proto = 0xff,
5235                         .hop_limits = 0xff,
5236                 },
5237                 .has_frag_ext = 1,
5238         };
5239         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5240                 .hdr = {
5241                         .common = {
5242                                 .u32 =
5243                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5244                                         .type = 0xFF,
5245                                         }).u32),
5246                         },
5247                         .dummy[0] = 0xffffffff,
5248                 },
5249         };
5250         struct mlx5_priv *priv = dev->data->dev_private;
5251         struct mlx5_dev_config *dev_conf = &priv->config;
5252         uint16_t queue_index = 0xFFFF;
5253         const struct rte_flow_item_vlan *vlan_m = NULL;
5254         int16_t rw_act_num = 0;
5255         uint64_t is_root;
5256         const struct mlx5_flow_tunnel *tunnel;
5257         struct flow_grp_info grp_info = {
5258                 .external = !!external,
5259                 .transfer = !!attr->transfer,
5260                 .fdb_def_rule = !!priv->fdb_def_rule,
5261         };
5262         const struct rte_eth_hairpin_conf *conf;
5263
5264         if (items == NULL)
5265                 return -1;
5266         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5267                 tunnel = flow_items_to_tunnel(items);
5268                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5269                                 MLX5_FLOW_ACTION_DECAP;
5270         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5271                 tunnel = flow_actions_to_tunnel(actions);
5272                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5273         } else {
5274                 tunnel = NULL;
5275         }
5276         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5277                                 (dev, tunnel, attr, items, actions);
5278         ret = flow_dv_validate_attributes(dev, tunnel, attr, grp_info, error);
5279         if (ret < 0)
5280                 return ret;
5281         is_root = (uint64_t)ret;
5282         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5283                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5284                 int type = items->type;
5285
5286                 if (!mlx5_flow_os_item_supported(type))
5287                         return rte_flow_error_set(error, ENOTSUP,
5288                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5289                                                   NULL, "item not supported");
5290                 switch (type) {
5291                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5292                         if (items[0].type != (typeof(items[0].type))
5293                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5294                                 return rte_flow_error_set
5295                                                 (error, EINVAL,
5296                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5297                                                 NULL, "MLX5 private items "
5298                                                 "must be the first");
5299                         break;
5300                 case RTE_FLOW_ITEM_TYPE_VOID:
5301                         break;
5302                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5303                         ret = flow_dv_validate_item_port_id
5304                                         (dev, items, attr, item_flags, error);
5305                         if (ret < 0)
5306                                 return ret;
5307                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5308                         break;
5309                 case RTE_FLOW_ITEM_TYPE_ETH:
5310                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5311                                                           true, error);
5312                         if (ret < 0)
5313                                 return ret;
5314                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5315                                              MLX5_FLOW_LAYER_OUTER_L2;
5316                         if (items->mask != NULL && items->spec != NULL) {
5317                                 ether_type =
5318                                         ((const struct rte_flow_item_eth *)
5319                                          items->spec)->type;
5320                                 ether_type &=
5321                                         ((const struct rte_flow_item_eth *)
5322                                          items->mask)->type;
5323                                 ether_type = rte_be_to_cpu_16(ether_type);
5324                         } else {
5325                                 ether_type = 0;
5326                         }
5327                         break;
5328                 case RTE_FLOW_ITEM_TYPE_VLAN:
5329                         ret = flow_dv_validate_item_vlan(items, item_flags,
5330                                                          dev, error);
5331                         if (ret < 0)
5332                                 return ret;
5333                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5334                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5335                         if (items->mask != NULL && items->spec != NULL) {
5336                                 ether_type =
5337                                         ((const struct rte_flow_item_vlan *)
5338                                          items->spec)->inner_type;
5339                                 ether_type &=
5340                                         ((const struct rte_flow_item_vlan *)
5341                                          items->mask)->inner_type;
5342                                 ether_type = rte_be_to_cpu_16(ether_type);
5343                         } else {
5344                                 ether_type = 0;
5345                         }
5346                         /* Store outer VLAN mask for of_push_vlan action. */
5347                         if (!tunnel)
5348                                 vlan_m = items->mask;
5349                         break;
5350                 case RTE_FLOW_ITEM_TYPE_IPV4:
5351                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5352                                                   &item_flags, &tunnel);
5353                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5354                                                          last_item, ether_type,
5355                                                          error);
5356                         if (ret < 0)
5357                                 return ret;
5358                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5359                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5360                         if (items->mask != NULL &&
5361                             ((const struct rte_flow_item_ipv4 *)
5362                              items->mask)->hdr.next_proto_id) {
5363                                 next_protocol =
5364                                         ((const struct rte_flow_item_ipv4 *)
5365                                          (items->spec))->hdr.next_proto_id;
5366                                 next_protocol &=
5367                                         ((const struct rte_flow_item_ipv4 *)
5368                                          (items->mask))->hdr.next_proto_id;
5369                         } else {
5370                                 /* Reset for inner layer. */
5371                                 next_protocol = 0xff;
5372                         }
5373                         break;
5374                 case RTE_FLOW_ITEM_TYPE_IPV6:
5375                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5376                                                   &item_flags, &tunnel);
5377                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5378                                                            last_item,
5379                                                            ether_type,
5380                                                            &nic_ipv6_mask,
5381                                                            error);
5382                         if (ret < 0)
5383                                 return ret;
5384                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5385                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5386                         if (items->mask != NULL &&
5387                             ((const struct rte_flow_item_ipv6 *)
5388                              items->mask)->hdr.proto) {
5389                                 item_ipv6_proto =
5390                                         ((const struct rte_flow_item_ipv6 *)
5391                                          items->spec)->hdr.proto;
5392                                 next_protocol =
5393                                         ((const struct rte_flow_item_ipv6 *)
5394                                          items->spec)->hdr.proto;
5395                                 next_protocol &=
5396                                         ((const struct rte_flow_item_ipv6 *)
5397                                          items->mask)->hdr.proto;
5398                         } else {
5399                                 /* Reset for inner layer. */
5400                                 next_protocol = 0xff;
5401                         }
5402                         break;
5403                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5404                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5405                                                                   item_flags,
5406                                                                   error);
5407                         if (ret < 0)
5408                                 return ret;
5409                         last_item = tunnel ?
5410                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5411                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5412                         if (items->mask != NULL &&
5413                             ((const struct rte_flow_item_ipv6_frag_ext *)
5414                              items->mask)->hdr.next_header) {
5415                                 next_protocol =
5416                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5417                                  items->spec)->hdr.next_header;
5418                                 next_protocol &=
5419                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5420                                  items->mask)->hdr.next_header;
5421                         } else {
5422                                 /* Reset for inner layer. */
5423                                 next_protocol = 0xff;
5424                         }
5425                         break;
5426                 case RTE_FLOW_ITEM_TYPE_TCP:
5427                         ret = mlx5_flow_validate_item_tcp
5428                                                 (items, item_flags,
5429                                                  next_protocol,
5430                                                  &nic_tcp_mask,
5431                                                  error);
5432                         if (ret < 0)
5433                                 return ret;
5434                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5435                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5436                         break;
5437                 case RTE_FLOW_ITEM_TYPE_UDP:
5438                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5439                                                           next_protocol,
5440                                                           error);
5441                         if (ret < 0)
5442                                 return ret;
5443                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5444                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5445                         break;
5446                 case RTE_FLOW_ITEM_TYPE_GRE:
5447                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5448                                                           next_protocol, error);
5449                         if (ret < 0)
5450                                 return ret;
5451                         gre_item = items;
5452                         last_item = MLX5_FLOW_LAYER_GRE;
5453                         break;
5454                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5455                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5456                                                             next_protocol,
5457                                                             error);
5458                         if (ret < 0)
5459                                 return ret;
5460                         last_item = MLX5_FLOW_LAYER_NVGRE;
5461                         break;
5462                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5463                         ret = mlx5_flow_validate_item_gre_key
5464                                 (items, item_flags, gre_item, error);
5465                         if (ret < 0)
5466                                 return ret;
5467                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5468                         break;
5469                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5470                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5471                                                             error);
5472                         if (ret < 0)
5473                                 return ret;
5474                         last_item = MLX5_FLOW_LAYER_VXLAN;
5475                         break;
5476                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5477                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5478                                                                 item_flags, dev,
5479                                                                 error);
5480                         if (ret < 0)
5481                                 return ret;
5482                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5483                         break;
5484                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5485                         ret = mlx5_flow_validate_item_geneve(items,
5486                                                              item_flags, dev,
5487                                                              error);
5488                         if (ret < 0)
5489                                 return ret;
5490                         last_item = MLX5_FLOW_LAYER_GENEVE;
5491                         break;
5492                 case RTE_FLOW_ITEM_TYPE_MPLS:
5493                         ret = mlx5_flow_validate_item_mpls(dev, items,
5494                                                            item_flags,
5495                                                            last_item, error);
5496                         if (ret < 0)
5497                                 return ret;
5498                         last_item = MLX5_FLOW_LAYER_MPLS;
5499                         break;
5500
5501                 case RTE_FLOW_ITEM_TYPE_MARK:
5502                         ret = flow_dv_validate_item_mark(dev, items, attr,
5503                                                          error);
5504                         if (ret < 0)
5505                                 return ret;
5506                         last_item = MLX5_FLOW_ITEM_MARK;
5507                         break;
5508                 case RTE_FLOW_ITEM_TYPE_META:
5509                         ret = flow_dv_validate_item_meta(dev, items, attr,
5510                                                          error);
5511                         if (ret < 0)
5512                                 return ret;
5513                         last_item = MLX5_FLOW_ITEM_METADATA;
5514                         break;
5515                 case RTE_FLOW_ITEM_TYPE_ICMP:
5516                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5517                                                            next_protocol,
5518                                                            error);
5519                         if (ret < 0)
5520                                 return ret;
5521                         last_item = MLX5_FLOW_LAYER_ICMP;
5522                         break;
5523                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5524                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5525                                                             next_protocol,
5526                                                             error);
5527                         if (ret < 0)
5528                                 return ret;
5529                         item_ipv6_proto = IPPROTO_ICMPV6;
5530                         last_item = MLX5_FLOW_LAYER_ICMP6;
5531                         break;
5532                 case RTE_FLOW_ITEM_TYPE_TAG:
5533                         ret = flow_dv_validate_item_tag(dev, items,
5534                                                         attr, error);
5535                         if (ret < 0)
5536                                 return ret;
5537                         last_item = MLX5_FLOW_ITEM_TAG;
5538                         break;
5539                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5540                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5541                         break;
5542                 case RTE_FLOW_ITEM_TYPE_GTP:
5543                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5544                                                         error);
5545                         if (ret < 0)
5546                                 return ret;
5547                         last_item = MLX5_FLOW_LAYER_GTP;
5548                         break;
5549                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5550                         /* Capacity will be checked in the translate stage. */
5551                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5552                                                             last_item,
5553                                                             ether_type,
5554                                                             &nic_ecpri_mask,
5555                                                             error);
5556                         if (ret < 0)
5557                                 return ret;
5558                         last_item = MLX5_FLOW_LAYER_ECPRI;
5559                         break;
5560                 default:
5561                         return rte_flow_error_set(error, ENOTSUP,
5562                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5563                                                   NULL, "item not supported");
5564                 }
5565                 item_flags |= last_item;
5566         }
5567         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5568                 int type = actions->type;
5569
5570                 if (!mlx5_flow_os_action_supported(type))
5571                         return rte_flow_error_set(error, ENOTSUP,
5572                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5573                                                   actions,
5574                                                   "action not supported");
5575                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5576                         return rte_flow_error_set(error, ENOTSUP,
5577                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5578                                                   actions, "too many actions");
5579                 switch (type) {
5580                 case RTE_FLOW_ACTION_TYPE_VOID:
5581                         break;
5582                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5583                         ret = flow_dv_validate_action_port_id(dev,
5584                                                               action_flags,
5585                                                               actions,
5586                                                               attr,
5587                                                               error);
5588                         if (ret)
5589                                 return ret;
5590                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5591                         ++actions_n;
5592                         break;
5593                 case RTE_FLOW_ACTION_TYPE_FLAG:
5594                         ret = flow_dv_validate_action_flag(dev, action_flags,
5595                                                            attr, error);
5596                         if (ret < 0)
5597                                 return ret;
5598                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5599                                 /* Count all modify-header actions as one. */
5600                                 if (!(action_flags &
5601                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5602                                         ++actions_n;
5603                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5604                                                 MLX5_FLOW_ACTION_MARK_EXT;
5605                         } else {
5606                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5607                                 ++actions_n;
5608                         }
5609                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5610                         break;
5611                 case RTE_FLOW_ACTION_TYPE_MARK:
5612                         ret = flow_dv_validate_action_mark(dev, actions,
5613                                                            action_flags,
5614                                                            attr, error);
5615                         if (ret < 0)
5616                                 return ret;
5617                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5618                                 /* Count all modify-header actions as one. */
5619                                 if (!(action_flags &
5620                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5621                                         ++actions_n;
5622                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5623                                                 MLX5_FLOW_ACTION_MARK_EXT;
5624                         } else {
5625                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5626                                 ++actions_n;
5627                         }
5628                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5629                         break;
5630                 case RTE_FLOW_ACTION_TYPE_SET_META:
5631                         ret = flow_dv_validate_action_set_meta(dev, actions,
5632                                                                action_flags,
5633                                                                attr, error);
5634                         if (ret < 0)
5635                                 return ret;
5636                         /* Count all modify-header actions as one action. */
5637                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5638                                 ++actions_n;
5639                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5640                         rw_act_num += MLX5_ACT_NUM_SET_META;
5641                         break;
5642                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5643                         ret = flow_dv_validate_action_set_tag(dev, actions,
5644                                                               action_flags,
5645                                                               attr, error);
5646                         if (ret < 0)
5647                                 return ret;
5648                         /* Count all modify-header actions as one action. */
5649                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5650                                 ++actions_n;
5651                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5652                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5653                         break;
5654                 case RTE_FLOW_ACTION_TYPE_DROP:
5655                         ret = mlx5_flow_validate_action_drop(action_flags,
5656                                                              attr, error);
5657                         if (ret < 0)
5658                                 return ret;
5659                         action_flags |= MLX5_FLOW_ACTION_DROP;
5660                         ++actions_n;
5661                         break;
5662                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5663                         ret = mlx5_flow_validate_action_queue(actions,
5664                                                               action_flags, dev,
5665                                                               attr, error);
5666                         if (ret < 0)
5667                                 return ret;
5668                         queue_index = ((const struct rte_flow_action_queue *)
5669                                                         (actions->conf))->index;
5670                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5671                         ++actions_n;
5672                         break;
5673                 case RTE_FLOW_ACTION_TYPE_RSS:
5674                         rss = actions->conf;
5675                         ret = mlx5_flow_validate_action_rss(actions,
5676                                                             action_flags, dev,
5677                                                             attr, item_flags,
5678                                                             error);
5679                         if (ret < 0)
5680                                 return ret;
5681                         if (rss != NULL && rss->queue_num)
5682                                 queue_index = rss->queue[0];
5683                         action_flags |= MLX5_FLOW_ACTION_RSS;
5684                         ++actions_n;
5685                         break;
5686                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5687                         ret =
5688                         mlx5_flow_validate_action_default_miss(action_flags,
5689                                         attr, error);
5690                         if (ret < 0)
5691                                 return ret;
5692                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5693                         ++actions_n;
5694                         break;
5695                 case RTE_FLOW_ACTION_TYPE_COUNT:
5696                         ret = flow_dv_validate_action_count(dev, error);
5697                         if (ret < 0)
5698                                 return ret;
5699                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5700                         ++actions_n;
5701                         break;
5702                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5703                         if (flow_dv_validate_action_pop_vlan(dev,
5704                                                              action_flags,
5705                                                              actions,
5706                                                              item_flags, attr,
5707                                                              error))
5708                                 return -rte_errno;
5709                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5710                         ++actions_n;
5711                         break;
5712                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5713                         ret = flow_dv_validate_action_push_vlan(dev,
5714                                                                 action_flags,
5715                                                                 vlan_m,
5716                                                                 actions, attr,
5717                                                                 error);
5718                         if (ret < 0)
5719                                 return ret;
5720                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5721                         ++actions_n;
5722                         break;
5723                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5724                         ret = flow_dv_validate_action_set_vlan_pcp
5725                                                 (action_flags, actions, error);
5726                         if (ret < 0)
5727                                 return ret;
5728                         /* Count PCP with push_vlan command. */
5729                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5730                         break;
5731                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5732                         ret = flow_dv_validate_action_set_vlan_vid
5733                                                 (item_flags, action_flags,
5734                                                  actions, error);
5735                         if (ret < 0)
5736                                 return ret;
5737                         /* Count VID with push_vlan command. */
5738                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5739                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5740                         break;
5741                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5742                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5743                         ret = flow_dv_validate_action_l2_encap(dev,
5744                                                                action_flags,
5745                                                                actions, attr,
5746                                                                error);
5747                         if (ret < 0)
5748                                 return ret;
5749                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5750                         ++actions_n;
5751                         break;
5752                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5753                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5754                         ret = flow_dv_validate_action_decap(dev, action_flags,
5755                                                             attr, error);
5756                         if (ret < 0)
5757                                 return ret;
5758                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5759                         ++actions_n;
5760                         break;
5761                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5762                         ret = flow_dv_validate_action_raw_encap_decap
5763                                 (dev, NULL, actions->conf, attr, &action_flags,
5764                                  &actions_n, error);
5765                         if (ret < 0)
5766                                 return ret;
5767                         break;
5768                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5769                         decap = actions->conf;
5770                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5771                                 ;
5772                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5773                                 encap = NULL;
5774                                 actions--;
5775                         } else {
5776                                 encap = actions->conf;
5777                         }
5778                         ret = flow_dv_validate_action_raw_encap_decap
5779                                            (dev,
5780                                             decap ? decap : &empty_decap, encap,
5781                                             attr, &action_flags, &actions_n,
5782                                             error);
5783                         if (ret < 0)
5784                                 return ret;
5785                         break;
5786                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5787                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5788                         ret = flow_dv_validate_action_modify_mac(action_flags,
5789                                                                  actions,
5790                                                                  item_flags,
5791                                                                  error);
5792                         if (ret < 0)
5793                                 return ret;
5794                         /* Count all modify-header actions as one action. */
5795                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5796                                 ++actions_n;
5797                         action_flags |= actions->type ==
5798                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5799                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5800                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5801                         /*
5802                          * Even if the source and destination MAC addresses have
5803                          * overlap in the header with 4B alignment, the convert
5804                          * function will handle them separately and 4 SW actions
5805                          * will be created. And 2 actions will be added each
5806                          * time no matter how many bytes of address will be set.
5807                          */
5808                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5809                         break;
5810                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5811                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5812                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5813                                                                   actions,
5814                                                                   item_flags,
5815                                                                   error);
5816                         if (ret < 0)
5817                                 return ret;
5818                         /* Count all modify-header actions as one action. */
5819                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5820                                 ++actions_n;
5821                         action_flags |= actions->type ==
5822                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5823                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5824                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5825                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5826                         break;
5827                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5828                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5829                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5830                                                                   actions,
5831                                                                   item_flags,
5832                                                                   error);
5833                         if (ret < 0)
5834                                 return ret;
5835                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5836                                 return rte_flow_error_set(error, ENOTSUP,
5837                                         RTE_FLOW_ERROR_TYPE_ACTION,
5838                                         actions,
5839                                         "Can't change header "
5840                                         "with ICMPv6 proto");
5841                         /* Count all modify-header actions as one action. */
5842                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5843                                 ++actions_n;
5844                         action_flags |= actions->type ==
5845                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5846                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5847                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5848                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5849                         break;
5850                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5851                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5852                         ret = flow_dv_validate_action_modify_tp(action_flags,
5853                                                                 actions,
5854                                                                 item_flags,
5855                                                                 error);
5856                         if (ret < 0)
5857                                 return ret;
5858                         /* Count all modify-header actions as one action. */
5859                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5860                                 ++actions_n;
5861                         action_flags |= actions->type ==
5862                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5863                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5864                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5865                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5866                         break;
5867                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5868                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5869                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5870                                                                  actions,
5871                                                                  item_flags,
5872                                                                  error);
5873                         if (ret < 0)
5874                                 return ret;
5875                         /* Count all modify-header actions as one action. */
5876                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5877                                 ++actions_n;
5878                         action_flags |= actions->type ==
5879                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5880                                                 MLX5_FLOW_ACTION_SET_TTL :
5881                                                 MLX5_FLOW_ACTION_DEC_TTL;
5882                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5883                         break;
5884                 case RTE_FLOW_ACTION_TYPE_JUMP:
5885                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5886                                                            action_flags,
5887                                                            attr, external,
5888                                                            error);
5889                         if (ret)
5890                                 return ret;
5891                         ++actions_n;
5892                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5893                         break;
5894                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5895                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5896                         ret = flow_dv_validate_action_modify_tcp_seq
5897                                                                 (action_flags,
5898                                                                  actions,
5899                                                                  item_flags,
5900                                                                  error);
5901                         if (ret < 0)
5902                                 return ret;
5903                         /* Count all modify-header actions as one action. */
5904                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5905                                 ++actions_n;
5906                         action_flags |= actions->type ==
5907                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5908                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5909                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5910                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5911                         break;
5912                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5913                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5914                         ret = flow_dv_validate_action_modify_tcp_ack
5915                                                                 (action_flags,
5916                                                                  actions,
5917                                                                  item_flags,
5918                                                                  error);
5919                         if (ret < 0)
5920                                 return ret;
5921                         /* Count all modify-header actions as one action. */
5922                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5923                                 ++actions_n;
5924                         action_flags |= actions->type ==
5925                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5926                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5927                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5928                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5929                         break;
5930                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5931                         break;
5932                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5933                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5934                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5935                         break;
5936                 case RTE_FLOW_ACTION_TYPE_METER:
5937                         ret = mlx5_flow_validate_action_meter(dev,
5938                                                               action_flags,
5939                                                               actions, attr,
5940                                                               error);
5941                         if (ret < 0)
5942                                 return ret;
5943                         action_flags |= MLX5_FLOW_ACTION_METER;
5944                         ++actions_n;
5945                         /* Meter action will add one more TAG action. */
5946                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5947                         break;
5948                 case RTE_FLOW_ACTION_TYPE_AGE:
5949                         ret = flow_dv_validate_action_age(action_flags,
5950                                                           actions, dev,
5951                                                           error);
5952                         if (ret < 0)
5953                                 return ret;
5954                         action_flags |= MLX5_FLOW_ACTION_AGE;
5955                         ++actions_n;
5956                         break;
5957                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5958                         ret = flow_dv_validate_action_modify_ipv4_dscp
5959                                                          (action_flags,
5960                                                           actions,
5961                                                           item_flags,
5962                                                           error);
5963                         if (ret < 0)
5964                                 return ret;
5965                         /* Count all modify-header actions as one action. */
5966                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5967                                 ++actions_n;
5968                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5969                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5970                         break;
5971                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5972                         ret = flow_dv_validate_action_modify_ipv6_dscp
5973                                                                 (action_flags,
5974                                                                  actions,
5975                                                                  item_flags,
5976                                                                  error);
5977                         if (ret < 0)
5978                                 return ret;
5979                         /* Count all modify-header actions as one action. */
5980                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5981                                 ++actions_n;
5982                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5983                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5984                         break;
5985                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
5986                         ret = flow_dv_validate_action_sample(action_flags,
5987                                                              actions, dev,
5988                                                              attr, error);
5989                         if (ret < 0)
5990                                 return ret;
5991                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
5992                         ++actions_n;
5993                         break;
5994                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
5995                         if (actions[0].type != (typeof(actions[0].type))
5996                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
5997                                 return rte_flow_error_set
5998                                                 (error, EINVAL,
5999                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6000                                                 NULL, "MLX5 private action "
6001                                                 "must be the first");
6002
6003                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6004                         break;
6005                 default:
6006                         return rte_flow_error_set(error, ENOTSUP,
6007                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6008                                                   actions,
6009                                                   "action not supported");
6010                 }
6011         }
6012         /*
6013          * Validate actions in flow rules
6014          * - Explicit decap action is prohibited by the tunnel offload API.
6015          * - Drop action in tunnel steer rule is prohibited by the API.
6016          * - Application cannot use MARK action because it's value can mask
6017          *   tunnel default miss nitification.
6018          * - JUMP in tunnel match rule has no support in current PMD
6019          *   implementation.
6020          * - TAG & META are reserved for future uses.
6021          */
6022         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6023                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6024                                             MLX5_FLOW_ACTION_MARK     |
6025                                             MLX5_FLOW_ACTION_SET_TAG  |
6026                                             MLX5_FLOW_ACTION_SET_META |
6027                                             MLX5_FLOW_ACTION_DROP;
6028
6029                 if (action_flags & bad_actions_mask)
6030                         return rte_flow_error_set
6031                                         (error, EINVAL,
6032                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6033                                         "Invalid RTE action in tunnel "
6034                                         "set decap rule");
6035                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6036                         return rte_flow_error_set
6037                                         (error, EINVAL,
6038                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6039                                         "tunnel set decap rule must terminate "
6040                                         "with JUMP");
6041                 if (!attr->ingress)
6042                         return rte_flow_error_set
6043                                         (error, EINVAL,
6044                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6045                                         "tunnel flows for ingress traffic only");
6046         }
6047         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6048                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6049                                             MLX5_FLOW_ACTION_MARK    |
6050                                             MLX5_FLOW_ACTION_SET_TAG |
6051                                             MLX5_FLOW_ACTION_SET_META;
6052
6053                 if (action_flags & bad_actions_mask)
6054                         return rte_flow_error_set
6055                                         (error, EINVAL,
6056                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6057                                         "Invalid RTE action in tunnel "
6058                                         "set match rule");
6059         }
6060         /*
6061          * Validate the drop action mutual exclusion with other actions.
6062          * Drop action is mutually-exclusive with any other action, except for
6063          * Count action.
6064          */
6065         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6066             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6067                 return rte_flow_error_set(error, EINVAL,
6068                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6069                                           "Drop action is mutually-exclusive "
6070                                           "with any other action, except for "
6071                                           "Count action");
6072         /* Eswitch has few restrictions on using items and actions */
6073         if (attr->transfer) {
6074                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6075                     action_flags & MLX5_FLOW_ACTION_FLAG)
6076                         return rte_flow_error_set(error, ENOTSUP,
6077                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6078                                                   NULL,
6079                                                   "unsupported action FLAG");
6080                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6081                     action_flags & MLX5_FLOW_ACTION_MARK)
6082                         return rte_flow_error_set(error, ENOTSUP,
6083                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6084                                                   NULL,
6085                                                   "unsupported action MARK");
6086                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6087                         return rte_flow_error_set(error, ENOTSUP,
6088                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6089                                                   NULL,
6090                                                   "unsupported action QUEUE");
6091                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6092                         return rte_flow_error_set(error, ENOTSUP,
6093                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6094                                                   NULL,
6095                                                   "unsupported action RSS");
6096                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6097                         return rte_flow_error_set(error, EINVAL,
6098                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6099                                                   actions,
6100                                                   "no fate action is found");
6101         } else {
6102                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6103                         return rte_flow_error_set(error, EINVAL,
6104                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6105                                                   actions,
6106                                                   "no fate action is found");
6107         }
6108         /*
6109          * Continue validation for Xcap and VLAN actions.
6110          * If hairpin is working in explicit TX rule mode, there is no actions
6111          * splitting and the validation of hairpin ingress flow should be the
6112          * same as other standard flows.
6113          */
6114         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6115                              MLX5_FLOW_VLAN_ACTIONS)) &&
6116             (queue_index == 0xFFFF ||
6117              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6118              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6119              conf->tx_explicit != 0))) {
6120                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6121                     MLX5_FLOW_XCAP_ACTIONS)
6122                         return rte_flow_error_set(error, ENOTSUP,
6123                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6124                                                   NULL, "encap and decap "
6125                                                   "combination aren't supported");
6126                 if (!attr->transfer && attr->ingress) {
6127                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6128                                 return rte_flow_error_set
6129                                                 (error, ENOTSUP,
6130                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6131                                                  NULL, "encap is not supported"
6132                                                  " for ingress traffic");
6133                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6134                                 return rte_flow_error_set
6135                                                 (error, ENOTSUP,
6136                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6137                                                  NULL, "push VLAN action not "
6138                                                  "supported for ingress");
6139                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6140                                         MLX5_FLOW_VLAN_ACTIONS)
6141                                 return rte_flow_error_set
6142                                                 (error, ENOTSUP,
6143                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6144                                                  NULL, "no support for "
6145                                                  "multiple VLAN actions");
6146                 }
6147         }
6148         /*
6149          * Hairpin flow will add one more TAG action in TX implicit mode.
6150          * In TX explicit mode, there will be no hairpin flow ID.
6151          */
6152         if (hairpin > 0)
6153                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6154         /* extra metadata enabled: one more TAG action will be add. */
6155         if (dev_conf->dv_flow_en &&
6156             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6157             mlx5_flow_ext_mreg_supported(dev))
6158                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6159         if ((uint32_t)rw_act_num >
6160                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6161                 return rte_flow_error_set(error, ENOTSUP,
6162                                           RTE_FLOW_ERROR_TYPE_ACTION,
6163                                           NULL, "too many header modify"
6164                                           " actions to support");
6165         }
6166         return 0;
6167 }
6168
6169 /**
6170  * Internal preparation function. Allocates the DV flow size,
6171  * this size is constant.
6172  *
6173  * @param[in] dev
6174  *   Pointer to the rte_eth_dev structure.
6175  * @param[in] attr
6176  *   Pointer to the flow attributes.
6177  * @param[in] items
6178  *   Pointer to the list of items.
6179  * @param[in] actions
6180  *   Pointer to the list of actions.
6181  * @param[out] error
6182  *   Pointer to the error structure.
6183  *
6184  * @return
6185  *   Pointer to mlx5_flow object on success,
6186  *   otherwise NULL and rte_errno is set.
6187  */
6188 static struct mlx5_flow *
6189 flow_dv_prepare(struct rte_eth_dev *dev,
6190                 const struct rte_flow_attr *attr __rte_unused,
6191                 const struct rte_flow_item items[] __rte_unused,
6192                 const struct rte_flow_action actions[] __rte_unused,
6193                 struct rte_flow_error *error)
6194 {
6195         uint32_t handle_idx = 0;
6196         struct mlx5_flow *dev_flow;
6197         struct mlx5_flow_handle *dev_handle;
6198         struct mlx5_priv *priv = dev->data->dev_private;
6199         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6200
6201         MLX5_ASSERT(wks);
6202         /* In case of corrupting the memory. */
6203         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6204                 rte_flow_error_set(error, ENOSPC,
6205                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6206                                    "not free temporary device flow");
6207                 return NULL;
6208         }
6209         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6210                                    &handle_idx);
6211         if (!dev_handle) {
6212                 rte_flow_error_set(error, ENOMEM,
6213                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6214                                    "not enough memory to create flow handle");
6215                 return NULL;
6216         }
6217         MLX5_ASSERT(wks->flow_idx + 1 < RTE_DIM(wks->flows));
6218         dev_flow = &wks->flows[wks->flow_idx++];
6219         dev_flow->handle = dev_handle;
6220         dev_flow->handle_idx = handle_idx;
6221         /*
6222          * In some old rdma-core releases, before continuing, a check of the
6223          * length of matching parameter will be done at first. It needs to use
6224          * the length without misc4 param. If the flow has misc4 support, then
6225          * the length needs to be adjusted accordingly. Each param member is
6226          * aligned with a 64B boundary naturally.
6227          */
6228         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6229                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6230         /*
6231          * The matching value needs to be cleared to 0 before using. In the
6232          * past, it will be automatically cleared when using rte_*alloc
6233          * API. The time consumption will be almost the same as before.
6234          */
6235         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6236         dev_flow->ingress = attr->ingress;
6237         dev_flow->dv.transfer = attr->transfer;
6238         return dev_flow;
6239 }
6240
6241 #ifdef RTE_LIBRTE_MLX5_DEBUG
6242 /**
6243  * Sanity check for match mask and value. Similar to check_valid_spec() in
6244  * kernel driver. If unmasked bit is present in value, it returns failure.
6245  *
6246  * @param match_mask
6247  *   pointer to match mask buffer.
6248  * @param match_value
6249  *   pointer to match value buffer.
6250  *
6251  * @return
6252  *   0 if valid, -EINVAL otherwise.
6253  */
6254 static int
6255 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6256 {
6257         uint8_t *m = match_mask;
6258         uint8_t *v = match_value;
6259         unsigned int i;
6260
6261         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6262                 if (v[i] & ~m[i]) {
6263                         DRV_LOG(ERR,
6264                                 "match_value differs from match_criteria"
6265                                 " %p[%u] != %p[%u]",
6266                                 match_value, i, match_mask, i);
6267                         return -EINVAL;
6268                 }
6269         }
6270         return 0;
6271 }
6272 #endif
6273
6274 /**
6275  * Add match of ip_version.
6276  *
6277  * @param[in] group
6278  *   Flow group.
6279  * @param[in] headers_v
6280  *   Values header pointer.
6281  * @param[in] headers_m
6282  *   Masks header pointer.
6283  * @param[in] ip_version
6284  *   The IP version to set.
6285  */
6286 static inline void
6287 flow_dv_set_match_ip_version(uint32_t group,
6288                              void *headers_v,
6289                              void *headers_m,
6290                              uint8_t ip_version)
6291 {
6292         if (group == 0)
6293                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6294         else
6295                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6296                          ip_version);
6297         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6298         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6299         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6300 }
6301
6302 /**
6303  * Add Ethernet item to matcher and to the value.
6304  *
6305  * @param[in, out] matcher
6306  *   Flow matcher.
6307  * @param[in, out] key
6308  *   Flow matcher value.
6309  * @param[in] item
6310  *   Flow pattern to translate.
6311  * @param[in] inner
6312  *   Item is inner pattern.
6313  */
6314 static void
6315 flow_dv_translate_item_eth(void *matcher, void *key,
6316                            const struct rte_flow_item *item, int inner,
6317                            uint32_t group)
6318 {
6319         const struct rte_flow_item_eth *eth_m = item->mask;
6320         const struct rte_flow_item_eth *eth_v = item->spec;
6321         const struct rte_flow_item_eth nic_mask = {
6322                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6323                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6324                 .type = RTE_BE16(0xffff),
6325                 .has_vlan = 0,
6326         };
6327         void *hdrs_m;
6328         void *hdrs_v;
6329         char *l24_v;
6330         unsigned int i;
6331
6332         if (!eth_v)
6333                 return;
6334         if (!eth_m)
6335                 eth_m = &nic_mask;
6336         if (inner) {
6337                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6338                                          inner_headers);
6339                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6340         } else {
6341                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6342                                          outer_headers);
6343                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6344         }
6345         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6346                &eth_m->dst, sizeof(eth_m->dst));
6347         /* The value must be in the range of the mask. */
6348         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6349         for (i = 0; i < sizeof(eth_m->dst); ++i)
6350                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6351         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6352                &eth_m->src, sizeof(eth_m->src));
6353         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6354         /* The value must be in the range of the mask. */
6355         for (i = 0; i < sizeof(eth_m->dst); ++i)
6356                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6357         /*
6358          * HW supports match on one Ethertype, the Ethertype following the last
6359          * VLAN tag of the packet (see PRM).
6360          * Set match on ethertype only if ETH header is not followed by VLAN.
6361          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6362          * ethertype, and use ip_version field instead.
6363          * eCPRI over Ether layer will use type value 0xAEFE.
6364          */
6365         if (eth_m->type == 0xFFFF) {
6366                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6367                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6368                 switch (eth_v->type) {
6369                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6370                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6371                         return;
6372                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6373                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6374                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6375                         return;
6376                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6377                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6378                         return;
6379                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6380                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6381                         return;
6382                 default:
6383                         break;
6384                 }
6385         }
6386         if (eth_m->has_vlan) {
6387                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6388                 if (eth_v->has_vlan) {
6389                         /*
6390                          * Here, when also has_more_vlan field in VLAN item is
6391                          * not set, only single-tagged packets will be matched.
6392                          */
6393                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6394                         return;
6395                 }
6396         }
6397         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6398                  rte_be_to_cpu_16(eth_m->type));
6399         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6400         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6401 }
6402
6403 /**
6404  * Add VLAN item to matcher and to the value.
6405  *
6406  * @param[in, out] dev_flow
6407  *   Flow descriptor.
6408  * @param[in, out] matcher
6409  *   Flow matcher.
6410  * @param[in, out] key
6411  *   Flow matcher value.
6412  * @param[in] item
6413  *   Flow pattern to translate.
6414  * @param[in] inner
6415  *   Item is inner pattern.
6416  */
6417 static void
6418 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6419                             void *matcher, void *key,
6420                             const struct rte_flow_item *item,
6421                             int inner, uint32_t group)
6422 {
6423         const struct rte_flow_item_vlan *vlan_m = item->mask;
6424         const struct rte_flow_item_vlan *vlan_v = item->spec;
6425         void *hdrs_m;
6426         void *hdrs_v;
6427         uint16_t tci_m;
6428         uint16_t tci_v;
6429
6430         if (inner) {
6431                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6432                                          inner_headers);
6433                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6434         } else {
6435                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6436                                          outer_headers);
6437                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6438                 /*
6439                  * This is workaround, masks are not supported,
6440                  * and pre-validated.
6441                  */
6442                 if (vlan_v)
6443                         dev_flow->handle->vf_vlan.tag =
6444                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6445         }
6446         /*
6447          * When VLAN item exists in flow, mark packet as tagged,
6448          * even if TCI is not specified.
6449          */
6450         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6451                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6452                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6453         }
6454         if (!vlan_v)
6455                 return;
6456         if (!vlan_m)
6457                 vlan_m = &rte_flow_item_vlan_mask;
6458         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6459         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6460         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6461         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6462         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6463         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6464         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6465         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6466         /*
6467          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6468          * ethertype, and use ip_version field instead.
6469          */
6470         if (vlan_m->inner_type == 0xFFFF) {
6471                 switch (vlan_v->inner_type) {
6472                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6473                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6474                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6475                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6476                         return;
6477                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6478                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6479                         return;
6480                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6481                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6482                         return;
6483                 default:
6484                         break;
6485                 }
6486         }
6487         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6488                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6489                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6490                 /* Only one vlan_tag bit can be set. */
6491                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6492                 return;
6493         }
6494         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6495                  rte_be_to_cpu_16(vlan_m->inner_type));
6496         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6497                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6498 }
6499
6500 /**
6501  * Add IPV4 item to matcher and to the value.
6502  *
6503  * @param[in, out] matcher
6504  *   Flow matcher.
6505  * @param[in, out] key
6506  *   Flow matcher value.
6507  * @param[in] item
6508  *   Flow pattern to translate.
6509  * @param[in] inner
6510  *   Item is inner pattern.
6511  * @param[in] group
6512  *   The group to insert the rule.
6513  */
6514 static void
6515 flow_dv_translate_item_ipv4(void *matcher, void *key,
6516                             const struct rte_flow_item *item,
6517                             int inner, uint32_t group)
6518 {
6519         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6520         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6521         const struct rte_flow_item_ipv4 nic_mask = {
6522                 .hdr = {
6523                         .src_addr = RTE_BE32(0xffffffff),
6524                         .dst_addr = RTE_BE32(0xffffffff),
6525                         .type_of_service = 0xff,
6526                         .next_proto_id = 0xff,
6527                         .time_to_live = 0xff,
6528                 },
6529         };
6530         void *headers_m;
6531         void *headers_v;
6532         char *l24_m;
6533         char *l24_v;
6534         uint8_t tos;
6535
6536         if (inner) {
6537                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6538                                          inner_headers);
6539                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6540         } else {
6541                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6542                                          outer_headers);
6543                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6544         }
6545         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6546         if (!ipv4_v)
6547                 return;
6548         if (!ipv4_m)
6549                 ipv4_m = &nic_mask;
6550         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6551                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6552         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6553                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6554         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6555         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6556         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6557                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6558         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6559                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6560         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6561         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6562         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6563         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6564                  ipv4_m->hdr.type_of_service);
6565         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6566         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6567                  ipv4_m->hdr.type_of_service >> 2);
6568         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6569         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6570                  ipv4_m->hdr.next_proto_id);
6571         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6572                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6573         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6574                  ipv4_m->hdr.time_to_live);
6575         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6576                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6577         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6578                  !!(ipv4_m->hdr.fragment_offset));
6579         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6580                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6581 }
6582
6583 /**
6584  * Add IPV6 item to matcher and to the value.
6585  *
6586  * @param[in, out] matcher
6587  *   Flow matcher.
6588  * @param[in, out] key
6589  *   Flow matcher value.
6590  * @param[in] item
6591  *   Flow pattern to translate.
6592  * @param[in] inner
6593  *   Item is inner pattern.
6594  * @param[in] group
6595  *   The group to insert the rule.
6596  */
6597 static void
6598 flow_dv_translate_item_ipv6(void *matcher, void *key,
6599                             const struct rte_flow_item *item,
6600                             int inner, uint32_t group)
6601 {
6602         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6603         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6604         const struct rte_flow_item_ipv6 nic_mask = {
6605                 .hdr = {
6606                         .src_addr =
6607                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6608                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6609                         .dst_addr =
6610                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6611                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6612                         .vtc_flow = RTE_BE32(0xffffffff),
6613                         .proto = 0xff,
6614                         .hop_limits = 0xff,
6615                 },
6616         };
6617         void *headers_m;
6618         void *headers_v;
6619         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6620         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6621         char *l24_m;
6622         char *l24_v;
6623         uint32_t vtc_m;
6624         uint32_t vtc_v;
6625         int i;
6626         int size;
6627
6628         if (inner) {
6629                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6630                                          inner_headers);
6631                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6632         } else {
6633                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6634                                          outer_headers);
6635                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6636         }
6637         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6638         if (!ipv6_v)
6639                 return;
6640         if (!ipv6_m)
6641                 ipv6_m = &nic_mask;
6642         size = sizeof(ipv6_m->hdr.dst_addr);
6643         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6644                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6645         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6646                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6647         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6648         for (i = 0; i < size; ++i)
6649                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6650         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6651                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6652         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6653                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6654         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6655         for (i = 0; i < size; ++i)
6656                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6657         /* TOS. */
6658         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6659         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6660         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6661         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6662         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6663         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6664         /* Label. */
6665         if (inner) {
6666                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6667                          vtc_m);
6668                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6669                          vtc_v);
6670         } else {
6671                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6672                          vtc_m);
6673                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6674                          vtc_v);
6675         }
6676         /* Protocol. */
6677         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6678                  ipv6_m->hdr.proto);
6679         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6680                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6681         /* Hop limit. */
6682         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6683                  ipv6_m->hdr.hop_limits);
6684         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6685                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6686         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6687                  !!(ipv6_m->has_frag_ext));
6688         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6689                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6690 }
6691
6692 /**
6693  * Add IPV6 fragment extension item to matcher and to the value.
6694  *
6695  * @param[in, out] matcher
6696  *   Flow matcher.
6697  * @param[in, out] key
6698  *   Flow matcher value.
6699  * @param[in] item
6700  *   Flow pattern to translate.
6701  * @param[in] inner
6702  *   Item is inner pattern.
6703  */
6704 static void
6705 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6706                                      const struct rte_flow_item *item,
6707                                      int inner)
6708 {
6709         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6710         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6711         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6712                 .hdr = {
6713                         .next_header = 0xff,
6714                         .frag_data = RTE_BE16(0xffff),
6715                 },
6716         };
6717         void *headers_m;
6718         void *headers_v;
6719
6720         if (inner) {
6721                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6722                                          inner_headers);
6723                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6724         } else {
6725                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6726                                          outer_headers);
6727                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6728         }
6729         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6730         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6731         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6732         if (!ipv6_frag_ext_v)
6733                 return;
6734         if (!ipv6_frag_ext_m)
6735                 ipv6_frag_ext_m = &nic_mask;
6736         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6737                  ipv6_frag_ext_m->hdr.next_header);
6738         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6739                  ipv6_frag_ext_v->hdr.next_header &
6740                  ipv6_frag_ext_m->hdr.next_header);
6741 }
6742
6743 /**
6744  * Add TCP item to matcher and to the value.
6745  *
6746  * @param[in, out] matcher
6747  *   Flow matcher.
6748  * @param[in, out] key
6749  *   Flow matcher value.
6750  * @param[in] item
6751  *   Flow pattern to translate.
6752  * @param[in] inner
6753  *   Item is inner pattern.
6754  */
6755 static void
6756 flow_dv_translate_item_tcp(void *matcher, void *key,
6757                            const struct rte_flow_item *item,
6758                            int inner)
6759 {
6760         const struct rte_flow_item_tcp *tcp_m = item->mask;
6761         const struct rte_flow_item_tcp *tcp_v = item->spec;
6762         void *headers_m;
6763         void *headers_v;
6764
6765         if (inner) {
6766                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6767                                          inner_headers);
6768                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6769         } else {
6770                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6771                                          outer_headers);
6772                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6773         }
6774         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6775         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6776         if (!tcp_v)
6777                 return;
6778         if (!tcp_m)
6779                 tcp_m = &rte_flow_item_tcp_mask;
6780         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6781                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6782         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6783                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6784         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6785                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6786         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6787                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6788         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6789                  tcp_m->hdr.tcp_flags);
6790         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6791                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6792 }
6793
6794 /**
6795  * Add UDP item to matcher and to the value.
6796  *
6797  * @param[in, out] matcher
6798  *   Flow matcher.
6799  * @param[in, out] key
6800  *   Flow matcher value.
6801  * @param[in] item
6802  *   Flow pattern to translate.
6803  * @param[in] inner
6804  *   Item is inner pattern.
6805  */
6806 static void
6807 flow_dv_translate_item_udp(void *matcher, void *key,
6808                            const struct rte_flow_item *item,
6809                            int inner)
6810 {
6811         const struct rte_flow_item_udp *udp_m = item->mask;
6812         const struct rte_flow_item_udp *udp_v = item->spec;
6813         void *headers_m;
6814         void *headers_v;
6815
6816         if (inner) {
6817                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6818                                          inner_headers);
6819                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6820         } else {
6821                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6822                                          outer_headers);
6823                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6824         }
6825         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6826         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6827         if (!udp_v)
6828                 return;
6829         if (!udp_m)
6830                 udp_m = &rte_flow_item_udp_mask;
6831         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6832                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6833         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6834                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6835         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6836                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6837         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6838                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6839 }
6840
6841 /**
6842  * Add GRE optional Key item to matcher and to the value.
6843  *
6844  * @param[in, out] matcher
6845  *   Flow matcher.
6846  * @param[in, out] key
6847  *   Flow matcher value.
6848  * @param[in] item
6849  *   Flow pattern to translate.
6850  * @param[in] inner
6851  *   Item is inner pattern.
6852  */
6853 static void
6854 flow_dv_translate_item_gre_key(void *matcher, void *key,
6855                                    const struct rte_flow_item *item)
6856 {
6857         const rte_be32_t *key_m = item->mask;
6858         const rte_be32_t *key_v = item->spec;
6859         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6860         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6861         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6862
6863         /* GRE K bit must be on and should already be validated */
6864         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6865         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6866         if (!key_v)
6867                 return;
6868         if (!key_m)
6869                 key_m = &gre_key_default_mask;
6870         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6871                  rte_be_to_cpu_32(*key_m) >> 8);
6872         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6873                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6874         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6875                  rte_be_to_cpu_32(*key_m) & 0xFF);
6876         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6877                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6878 }
6879
6880 /**
6881  * Add GRE item to matcher and to the value.
6882  *
6883  * @param[in, out] matcher
6884  *   Flow matcher.
6885  * @param[in, out] key
6886  *   Flow matcher value.
6887  * @param[in] item
6888  *   Flow pattern to translate.
6889  * @param[in] inner
6890  *   Item is inner pattern.
6891  */
6892 static void
6893 flow_dv_translate_item_gre(void *matcher, void *key,
6894                            const struct rte_flow_item *item,
6895                            int inner)
6896 {
6897         const struct rte_flow_item_gre *gre_m = item->mask;
6898         const struct rte_flow_item_gre *gre_v = item->spec;
6899         void *headers_m;
6900         void *headers_v;
6901         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6902         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6903         struct {
6904                 union {
6905                         __extension__
6906                         struct {
6907                                 uint16_t version:3;
6908                                 uint16_t rsvd0:9;
6909                                 uint16_t s_present:1;
6910                                 uint16_t k_present:1;
6911                                 uint16_t rsvd_bit1:1;
6912                                 uint16_t c_present:1;
6913                         };
6914                         uint16_t value;
6915                 };
6916         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6917
6918         if (inner) {
6919                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6920                                          inner_headers);
6921                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6922         } else {
6923                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6924                                          outer_headers);
6925                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6926         }
6927         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6928         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6929         if (!gre_v)
6930                 return;
6931         if (!gre_m)
6932                 gre_m = &rte_flow_item_gre_mask;
6933         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6934                  rte_be_to_cpu_16(gre_m->protocol));
6935         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6936                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6937         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6938         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6939         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6940                  gre_crks_rsvd0_ver_m.c_present);
6941         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6942                  gre_crks_rsvd0_ver_v.c_present &
6943                  gre_crks_rsvd0_ver_m.c_present);
6944         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6945                  gre_crks_rsvd0_ver_m.k_present);
6946         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6947                  gre_crks_rsvd0_ver_v.k_present &
6948                  gre_crks_rsvd0_ver_m.k_present);
6949         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6950                  gre_crks_rsvd0_ver_m.s_present);
6951         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6952                  gre_crks_rsvd0_ver_v.s_present &
6953                  gre_crks_rsvd0_ver_m.s_present);
6954 }
6955
6956 /**
6957  * Add NVGRE item to matcher and to the value.
6958  *
6959  * @param[in, out] matcher
6960  *   Flow matcher.
6961  * @param[in, out] key
6962  *   Flow matcher value.
6963  * @param[in] item
6964  *   Flow pattern to translate.
6965  * @param[in] inner
6966  *   Item is inner pattern.
6967  */
6968 static void
6969 flow_dv_translate_item_nvgre(void *matcher, void *key,
6970                              const struct rte_flow_item *item,
6971                              int inner)
6972 {
6973         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6974         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6975         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6976         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6977         const char *tni_flow_id_m;
6978         const char *tni_flow_id_v;
6979         char *gre_key_m;
6980         char *gre_key_v;
6981         int size;
6982         int i;
6983
6984         /* For NVGRE, GRE header fields must be set with defined values. */
6985         const struct rte_flow_item_gre gre_spec = {
6986                 .c_rsvd0_ver = RTE_BE16(0x2000),
6987                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6988         };
6989         const struct rte_flow_item_gre gre_mask = {
6990                 .c_rsvd0_ver = RTE_BE16(0xB000),
6991                 .protocol = RTE_BE16(UINT16_MAX),
6992         };
6993         const struct rte_flow_item gre_item = {
6994                 .spec = &gre_spec,
6995                 .mask = &gre_mask,
6996                 .last = NULL,
6997         };
6998         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6999         if (!nvgre_v)
7000                 return;
7001         if (!nvgre_m)
7002                 nvgre_m = &rte_flow_item_nvgre_mask;
7003         tni_flow_id_m = (const char *)nvgre_m->tni;
7004         tni_flow_id_v = (const char *)nvgre_v->tni;
7005         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7006         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7007         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7008         memcpy(gre_key_m, tni_flow_id_m, size);
7009         for (i = 0; i < size; ++i)
7010                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7011 }
7012
7013 /**
7014  * Add VXLAN item to matcher and to the value.
7015  *
7016  * @param[in, out] matcher
7017  *   Flow matcher.
7018  * @param[in, out] key
7019  *   Flow matcher value.
7020  * @param[in] item
7021  *   Flow pattern to translate.
7022  * @param[in] inner
7023  *   Item is inner pattern.
7024  */
7025 static void
7026 flow_dv_translate_item_vxlan(void *matcher, void *key,
7027                              const struct rte_flow_item *item,
7028                              int inner)
7029 {
7030         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7031         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7032         void *headers_m;
7033         void *headers_v;
7034         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7035         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7036         char *vni_m;
7037         char *vni_v;
7038         uint16_t dport;
7039         int size;
7040         int i;
7041
7042         if (inner) {
7043                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7044                                          inner_headers);
7045                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7046         } else {
7047                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7048                                          outer_headers);
7049                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7050         }
7051         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7052                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7053         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7054                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7055                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7056         }
7057         if (!vxlan_v)
7058                 return;
7059         if (!vxlan_m)
7060                 vxlan_m = &rte_flow_item_vxlan_mask;
7061         size = sizeof(vxlan_m->vni);
7062         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7063         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7064         memcpy(vni_m, vxlan_m->vni, size);
7065         for (i = 0; i < size; ++i)
7066                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7067 }
7068
7069 /**
7070  * Add VXLAN-GPE item to matcher and to the value.
7071  *
7072  * @param[in, out] matcher
7073  *   Flow matcher.
7074  * @param[in, out] key
7075  *   Flow matcher value.
7076  * @param[in] item
7077  *   Flow pattern to translate.
7078  * @param[in] inner
7079  *   Item is inner pattern.
7080  */
7081
7082 static void
7083 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7084                                  const struct rte_flow_item *item, int inner)
7085 {
7086         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7087         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7088         void *headers_m;
7089         void *headers_v;
7090         void *misc_m =
7091                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7092         void *misc_v =
7093                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7094         char *vni_m;
7095         char *vni_v;
7096         uint16_t dport;
7097         int size;
7098         int i;
7099         uint8_t flags_m = 0xff;
7100         uint8_t flags_v = 0xc;
7101
7102         if (inner) {
7103                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7104                                          inner_headers);
7105                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7106         } else {
7107                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7108                                          outer_headers);
7109                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7110         }
7111         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7112                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7113         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7114                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7115                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7116         }
7117         if (!vxlan_v)
7118                 return;
7119         if (!vxlan_m)
7120                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7121         size = sizeof(vxlan_m->vni);
7122         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7123         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7124         memcpy(vni_m, vxlan_m->vni, size);
7125         for (i = 0; i < size; ++i)
7126                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7127         if (vxlan_m->flags) {
7128                 flags_m = vxlan_m->flags;
7129                 flags_v = vxlan_v->flags;
7130         }
7131         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7132         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7133         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7134                  vxlan_m->protocol);
7135         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7136                  vxlan_v->protocol);
7137 }
7138
7139 /**
7140  * Add Geneve item to matcher and to the value.
7141  *
7142  * @param[in, out] matcher
7143  *   Flow matcher.
7144  * @param[in, out] key
7145  *   Flow matcher value.
7146  * @param[in] item
7147  *   Flow pattern to translate.
7148  * @param[in] inner
7149  *   Item is inner pattern.
7150  */
7151
7152 static void
7153 flow_dv_translate_item_geneve(void *matcher, void *key,
7154                               const struct rte_flow_item *item, int inner)
7155 {
7156         const struct rte_flow_item_geneve *geneve_m = item->mask;
7157         const struct rte_flow_item_geneve *geneve_v = item->spec;
7158         void *headers_m;
7159         void *headers_v;
7160         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7161         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7162         uint16_t dport;
7163         uint16_t gbhdr_m;
7164         uint16_t gbhdr_v;
7165         char *vni_m;
7166         char *vni_v;
7167         size_t size, i;
7168
7169         if (inner) {
7170                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7171                                          inner_headers);
7172                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7173         } else {
7174                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7175                                          outer_headers);
7176                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7177         }
7178         dport = MLX5_UDP_PORT_GENEVE;
7179         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7180                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7181                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7182         }
7183         if (!geneve_v)
7184                 return;
7185         if (!geneve_m)
7186                 geneve_m = &rte_flow_item_geneve_mask;
7187         size = sizeof(geneve_m->vni);
7188         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7189         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7190         memcpy(vni_m, geneve_m->vni, size);
7191         for (i = 0; i < size; ++i)
7192                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7193         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7194                  rte_be_to_cpu_16(geneve_m->protocol));
7195         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7196                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7197         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7198         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7199         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7200                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7201         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7202                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7203         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7204                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7205         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7206                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7207                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7208 }
7209
7210 /**
7211  * Add MPLS item to matcher and to the value.
7212  *
7213  * @param[in, out] matcher
7214  *   Flow matcher.
7215  * @param[in, out] key
7216  *   Flow matcher value.
7217  * @param[in] item
7218  *   Flow pattern to translate.
7219  * @param[in] prev_layer
7220  *   The protocol layer indicated in previous item.
7221  * @param[in] inner
7222  *   Item is inner pattern.
7223  */
7224 static void
7225 flow_dv_translate_item_mpls(void *matcher, void *key,
7226                             const struct rte_flow_item *item,
7227                             uint64_t prev_layer,
7228                             int inner)
7229 {
7230         const uint32_t *in_mpls_m = item->mask;
7231         const uint32_t *in_mpls_v = item->spec;
7232         uint32_t *out_mpls_m = 0;
7233         uint32_t *out_mpls_v = 0;
7234         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7235         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7236         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7237                                      misc_parameters_2);
7238         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7239         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7240         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7241
7242         switch (prev_layer) {
7243         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7244                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7245                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7246                          MLX5_UDP_PORT_MPLS);
7247                 break;
7248         case MLX5_FLOW_LAYER_GRE:
7249                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7250                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7251                          RTE_ETHER_TYPE_MPLS);
7252                 break;
7253         default:
7254                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7255                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7256                          IPPROTO_MPLS);
7257                 break;
7258         }
7259         if (!in_mpls_v)
7260                 return;
7261         if (!in_mpls_m)
7262                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7263         switch (prev_layer) {
7264         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7265                 out_mpls_m =
7266                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7267                                                  outer_first_mpls_over_udp);
7268                 out_mpls_v =
7269                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7270                                                  outer_first_mpls_over_udp);
7271                 break;
7272         case MLX5_FLOW_LAYER_GRE:
7273                 out_mpls_m =
7274                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7275                                                  outer_first_mpls_over_gre);
7276                 out_mpls_v =
7277                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7278                                                  outer_first_mpls_over_gre);
7279                 break;
7280         default:
7281                 /* Inner MPLS not over GRE is not supported. */
7282                 if (!inner) {
7283                         out_mpls_m =
7284                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7285                                                          misc2_m,
7286                                                          outer_first_mpls);
7287                         out_mpls_v =
7288                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7289                                                          misc2_v,
7290                                                          outer_first_mpls);
7291                 }
7292                 break;
7293         }
7294         if (out_mpls_m && out_mpls_v) {
7295                 *out_mpls_m = *in_mpls_m;
7296                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7297         }
7298 }
7299
7300 /**
7301  * Add metadata register item to matcher
7302  *
7303  * @param[in, out] matcher
7304  *   Flow matcher.
7305  * @param[in, out] key
7306  *   Flow matcher value.
7307  * @param[in] reg_type
7308  *   Type of device metadata register
7309  * @param[in] value
7310  *   Register value
7311  * @param[in] mask
7312  *   Register mask
7313  */
7314 static void
7315 flow_dv_match_meta_reg(void *matcher, void *key,
7316                        enum modify_reg reg_type,
7317                        uint32_t data, uint32_t mask)
7318 {
7319         void *misc2_m =
7320                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7321         void *misc2_v =
7322                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7323         uint32_t temp;
7324
7325         data &= mask;
7326         switch (reg_type) {
7327         case REG_A:
7328                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7329                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7330                 break;
7331         case REG_B:
7332                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7333                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7334                 break;
7335         case REG_C_0:
7336                 /*
7337                  * The metadata register C0 field might be divided into
7338                  * source vport index and META item value, we should set
7339                  * this field according to specified mask, not as whole one.
7340                  */
7341                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7342                 temp |= mask;
7343                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7344                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7345                 temp &= ~mask;
7346                 temp |= data;
7347                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7348                 break;
7349         case REG_C_1:
7350                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7351                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7352                 break;
7353         case REG_C_2:
7354                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7355                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7356                 break;
7357         case REG_C_3:
7358                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7359                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7360                 break;
7361         case REG_C_4:
7362                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7363                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7364                 break;
7365         case REG_C_5:
7366                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7367                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7368                 break;
7369         case REG_C_6:
7370                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7371                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7372                 break;
7373         case REG_C_7:
7374                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7375                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7376                 break;
7377         default:
7378                 MLX5_ASSERT(false);
7379                 break;
7380         }
7381 }
7382
7383 /**
7384  * Add MARK item to matcher
7385  *
7386  * @param[in] dev
7387  *   The device to configure through.
7388  * @param[in, out] matcher
7389  *   Flow matcher.
7390  * @param[in, out] key
7391  *   Flow matcher value.
7392  * @param[in] item
7393  *   Flow pattern to translate.
7394  */
7395 static void
7396 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7397                             void *matcher, void *key,
7398                             const struct rte_flow_item *item)
7399 {
7400         struct mlx5_priv *priv = dev->data->dev_private;
7401         const struct rte_flow_item_mark *mark;
7402         uint32_t value;
7403         uint32_t mask;
7404
7405         mark = item->mask ? (const void *)item->mask :
7406                             &rte_flow_item_mark_mask;
7407         mask = mark->id & priv->sh->dv_mark_mask;
7408         mark = (const void *)item->spec;
7409         MLX5_ASSERT(mark);
7410         value = mark->id & priv->sh->dv_mark_mask & mask;
7411         if (mask) {
7412                 enum modify_reg reg;
7413
7414                 /* Get the metadata register index for the mark. */
7415                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7416                 MLX5_ASSERT(reg > 0);
7417                 if (reg == REG_C_0) {
7418                         struct mlx5_priv *priv = dev->data->dev_private;
7419                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7420                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7421
7422                         mask &= msk_c0;
7423                         mask <<= shl_c0;
7424                         value <<= shl_c0;
7425                 }
7426                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7427         }
7428 }
7429
7430 /**
7431  * Add META item to matcher
7432  *
7433  * @param[in] dev
7434  *   The devich to configure through.
7435  * @param[in, out] matcher
7436  *   Flow matcher.
7437  * @param[in, out] key
7438  *   Flow matcher value.
7439  * @param[in] attr
7440  *   Attributes of flow that includes this item.
7441  * @param[in] item
7442  *   Flow pattern to translate.
7443  */
7444 static void
7445 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7446                             void *matcher, void *key,
7447                             const struct rte_flow_attr *attr,
7448                             const struct rte_flow_item *item)
7449 {
7450         const struct rte_flow_item_meta *meta_m;
7451         const struct rte_flow_item_meta *meta_v;
7452
7453         meta_m = (const void *)item->mask;
7454         if (!meta_m)
7455                 meta_m = &rte_flow_item_meta_mask;
7456         meta_v = (const void *)item->spec;
7457         if (meta_v) {
7458                 int reg;
7459                 uint32_t value = meta_v->data;
7460                 uint32_t mask = meta_m->data;
7461
7462                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7463                 if (reg < 0)
7464                         return;
7465                 /*
7466                  * In datapath code there is no endianness
7467                  * coversions for perfromance reasons, all
7468                  * pattern conversions are done in rte_flow.
7469                  */
7470                 value = rte_cpu_to_be_32(value);
7471                 mask = rte_cpu_to_be_32(mask);
7472                 if (reg == REG_C_0) {
7473                         struct mlx5_priv *priv = dev->data->dev_private;
7474                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7475                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7476 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7477                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7478
7479                         value >>= shr_c0;
7480                         mask >>= shr_c0;
7481 #endif
7482                         value <<= shl_c0;
7483                         mask <<= shl_c0;
7484                         MLX5_ASSERT(msk_c0);
7485                         MLX5_ASSERT(!(~msk_c0 & mask));
7486                 }
7487                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7488         }
7489 }
7490
7491 /**
7492  * Add vport metadata Reg C0 item to matcher
7493  *
7494  * @param[in, out] matcher
7495  *   Flow matcher.
7496  * @param[in, out] key
7497  *   Flow matcher value.
7498  * @param[in] reg
7499  *   Flow pattern to translate.
7500  */
7501 static void
7502 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7503                                   uint32_t value, uint32_t mask)
7504 {
7505         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7506 }
7507
7508 /**
7509  * Add tag item to matcher
7510  *
7511  * @param[in] dev
7512  *   The devich to configure through.
7513  * @param[in, out] matcher
7514  *   Flow matcher.
7515  * @param[in, out] key
7516  *   Flow matcher value.
7517  * @param[in] item
7518  *   Flow pattern to translate.
7519  */
7520 static void
7521 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7522                                 void *matcher, void *key,
7523                                 const struct rte_flow_item *item)
7524 {
7525         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7526         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7527         uint32_t mask, value;
7528
7529         MLX5_ASSERT(tag_v);
7530         value = tag_v->data;
7531         mask = tag_m ? tag_m->data : UINT32_MAX;
7532         if (tag_v->id == REG_C_0) {
7533                 struct mlx5_priv *priv = dev->data->dev_private;
7534                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7535                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7536
7537                 mask &= msk_c0;
7538                 mask <<= shl_c0;
7539                 value <<= shl_c0;
7540         }
7541         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7542 }
7543
7544 /**
7545  * Add TAG item to matcher
7546  *
7547  * @param[in] dev
7548  *   The devich to configure through.
7549  * @param[in, out] matcher
7550  *   Flow matcher.
7551  * @param[in, out] key
7552  *   Flow matcher value.
7553  * @param[in] item
7554  *   Flow pattern to translate.
7555  */
7556 static void
7557 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7558                            void *matcher, void *key,
7559                            const struct rte_flow_item *item)
7560 {
7561         const struct rte_flow_item_tag *tag_v = item->spec;
7562         const struct rte_flow_item_tag *tag_m = item->mask;
7563         enum modify_reg reg;
7564
7565         MLX5_ASSERT(tag_v);
7566         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7567         /* Get the metadata register index for the tag. */
7568         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7569         MLX5_ASSERT(reg > 0);
7570         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7571 }
7572
7573 /**
7574  * Add source vport match to the specified matcher.
7575  *
7576  * @param[in, out] matcher
7577  *   Flow matcher.
7578  * @param[in, out] key
7579  *   Flow matcher value.
7580  * @param[in] port
7581  *   Source vport value to match
7582  * @param[in] mask
7583  *   Mask
7584  */
7585 static void
7586 flow_dv_translate_item_source_vport(void *matcher, void *key,
7587                                     int16_t port, uint16_t mask)
7588 {
7589         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7590         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7591
7592         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7593         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7594 }
7595
7596 /**
7597  * Translate port-id item to eswitch match on  port-id.
7598  *
7599  * @param[in] dev
7600  *   The devich to configure through.
7601  * @param[in, out] matcher
7602  *   Flow matcher.
7603  * @param[in, out] key
7604  *   Flow matcher value.
7605  * @param[in] item
7606  *   Flow pattern to translate.
7607  *
7608  * @return
7609  *   0 on success, a negative errno value otherwise.
7610  */
7611 static int
7612 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7613                                void *key, const struct rte_flow_item *item)
7614 {
7615         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7616         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7617         struct mlx5_priv *priv;
7618         uint16_t mask, id;
7619
7620         mask = pid_m ? pid_m->id : 0xffff;
7621         id = pid_v ? pid_v->id : dev->data->port_id;
7622         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7623         if (!priv)
7624                 return -rte_errno;
7625         /* Translate to vport field or to metadata, depending on mode. */
7626         if (priv->vport_meta_mask)
7627                 flow_dv_translate_item_meta_vport(matcher, key,
7628                                                   priv->vport_meta_tag,
7629                                                   priv->vport_meta_mask);
7630         else
7631                 flow_dv_translate_item_source_vport(matcher, key,
7632                                                     priv->vport_id, mask);
7633         return 0;
7634 }
7635
7636 /**
7637  * Add ICMP6 item to matcher and to the value.
7638  *
7639  * @param[in, out] matcher
7640  *   Flow matcher.
7641  * @param[in, out] key
7642  *   Flow matcher value.
7643  * @param[in] item
7644  *   Flow pattern to translate.
7645  * @param[in] inner
7646  *   Item is inner pattern.
7647  */
7648 static void
7649 flow_dv_translate_item_icmp6(void *matcher, void *key,
7650                               const struct rte_flow_item *item,
7651                               int inner)
7652 {
7653         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7654         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7655         void *headers_m;
7656         void *headers_v;
7657         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7658                                      misc_parameters_3);
7659         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7660         if (inner) {
7661                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7662                                          inner_headers);
7663                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7664         } else {
7665                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7666                                          outer_headers);
7667                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7668         }
7669         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7670         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7671         if (!icmp6_v)
7672                 return;
7673         if (!icmp6_m)
7674                 icmp6_m = &rte_flow_item_icmp6_mask;
7675         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7676         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7677                  icmp6_v->type & icmp6_m->type);
7678         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7679         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7680                  icmp6_v->code & icmp6_m->code);
7681 }
7682
7683 /**
7684  * Add ICMP item to matcher and to the value.
7685  *
7686  * @param[in, out] matcher
7687  *   Flow matcher.
7688  * @param[in, out] key
7689  *   Flow matcher value.
7690  * @param[in] item
7691  *   Flow pattern to translate.
7692  * @param[in] inner
7693  *   Item is inner pattern.
7694  */
7695 static void
7696 flow_dv_translate_item_icmp(void *matcher, void *key,
7697                             const struct rte_flow_item *item,
7698                             int inner)
7699 {
7700         const struct rte_flow_item_icmp *icmp_m = item->mask;
7701         const struct rte_flow_item_icmp *icmp_v = item->spec;
7702         uint32_t icmp_header_data_m = 0;
7703         uint32_t icmp_header_data_v = 0;
7704         void *headers_m;
7705         void *headers_v;
7706         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7707                                      misc_parameters_3);
7708         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7709         if (inner) {
7710                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7711                                          inner_headers);
7712                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7713         } else {
7714                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7715                                          outer_headers);
7716                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7717         }
7718         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7719         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7720         if (!icmp_v)
7721                 return;
7722         if (!icmp_m)
7723                 icmp_m = &rte_flow_item_icmp_mask;
7724         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7725                  icmp_m->hdr.icmp_type);
7726         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7727                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7728         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7729                  icmp_m->hdr.icmp_code);
7730         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7731                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7732         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7733         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7734         if (icmp_header_data_m) {
7735                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7736                 icmp_header_data_v |=
7737                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7738                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7739                          icmp_header_data_m);
7740                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7741                          icmp_header_data_v & icmp_header_data_m);
7742         }
7743 }
7744
7745 /**
7746  * Add GTP item to matcher and to the value.
7747  *
7748  * @param[in, out] matcher
7749  *   Flow matcher.
7750  * @param[in, out] key
7751  *   Flow matcher value.
7752  * @param[in] item
7753  *   Flow pattern to translate.
7754  * @param[in] inner
7755  *   Item is inner pattern.
7756  */
7757 static void
7758 flow_dv_translate_item_gtp(void *matcher, void *key,
7759                            const struct rte_flow_item *item, int inner)
7760 {
7761         const struct rte_flow_item_gtp *gtp_m = item->mask;
7762         const struct rte_flow_item_gtp *gtp_v = item->spec;
7763         void *headers_m;
7764         void *headers_v;
7765         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7766                                      misc_parameters_3);
7767         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7768         uint16_t dport = RTE_GTPU_UDP_PORT;
7769
7770         if (inner) {
7771                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7772                                          inner_headers);
7773                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7774         } else {
7775                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7776                                          outer_headers);
7777                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7778         }
7779         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7780                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7781                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7782         }
7783         if (!gtp_v)
7784                 return;
7785         if (!gtp_m)
7786                 gtp_m = &rte_flow_item_gtp_mask;
7787         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7788                  gtp_m->v_pt_rsv_flags);
7789         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7790                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7791         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7792         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7793                  gtp_v->msg_type & gtp_m->msg_type);
7794         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7795                  rte_be_to_cpu_32(gtp_m->teid));
7796         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7797                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7798 }
7799
7800 /**
7801  * Add eCPRI item to matcher and to the value.
7802  *
7803  * @param[in] dev
7804  *   The devich to configure through.
7805  * @param[in, out] matcher
7806  *   Flow matcher.
7807  * @param[in, out] key
7808  *   Flow matcher value.
7809  * @param[in] item
7810  *   Flow pattern to translate.
7811  * @param[in] samples
7812  *   Sample IDs to be used in the matching.
7813  */
7814 static void
7815 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7816                              void *key, const struct rte_flow_item *item)
7817 {
7818         struct mlx5_priv *priv = dev->data->dev_private;
7819         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7820         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7821         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7822                                      misc_parameters_4);
7823         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7824         uint32_t *samples;
7825         void *dw_m;
7826         void *dw_v;
7827
7828         if (!ecpri_v)
7829                 return;
7830         if (!ecpri_m)
7831                 ecpri_m = &rte_flow_item_ecpri_mask;
7832         /*
7833          * Maximal four DW samples are supported in a single matching now.
7834          * Two are used now for a eCPRI matching:
7835          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7836          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7837          *    if any.
7838          */
7839         if (!ecpri_m->hdr.common.u32)
7840                 return;
7841         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7842         /* Need to take the whole DW as the mask to fill the entry. */
7843         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7844                             prog_sample_field_value_0);
7845         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7846                             prog_sample_field_value_0);
7847         /* Already big endian (network order) in the header. */
7848         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7849         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7850         /* Sample#0, used for matching type, offset 0. */
7851         MLX5_SET(fte_match_set_misc4, misc4_m,
7852                  prog_sample_field_id_0, samples[0]);
7853         /* It makes no sense to set the sample ID in the mask field. */
7854         MLX5_SET(fte_match_set_misc4, misc4_v,
7855                  prog_sample_field_id_0, samples[0]);
7856         /*
7857          * Checking if message body part needs to be matched.
7858          * Some wildcard rules only matching type field should be supported.
7859          */
7860         if (ecpri_m->hdr.dummy[0]) {
7861                 switch (ecpri_v->hdr.common.type) {
7862                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7863                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7864                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7865                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7866                                             prog_sample_field_value_1);
7867                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7868                                             prog_sample_field_value_1);
7869                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7870                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7871                         /* Sample#1, to match message body, offset 4. */
7872                         MLX5_SET(fte_match_set_misc4, misc4_m,
7873                                  prog_sample_field_id_1, samples[1]);
7874                         MLX5_SET(fte_match_set_misc4, misc4_v,
7875                                  prog_sample_field_id_1, samples[1]);
7876                         break;
7877                 default:
7878                         /* Others, do not match any sample ID. */
7879                         break;
7880                 }
7881         }
7882 }
7883
7884 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7885
7886 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7887         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7888                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7889
7890 /**
7891  * Calculate flow matcher enable bitmap.
7892  *
7893  * @param match_criteria
7894  *   Pointer to flow matcher criteria.
7895  *
7896  * @return
7897  *   Bitmap of enabled fields.
7898  */
7899 static uint8_t
7900 flow_dv_matcher_enable(uint32_t *match_criteria)
7901 {
7902         uint8_t match_criteria_enable;
7903
7904         match_criteria_enable =
7905                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7906                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7907         match_criteria_enable |=
7908                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7909                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7910         match_criteria_enable |=
7911                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7912                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7913         match_criteria_enable |=
7914                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7915                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7916         match_criteria_enable |=
7917                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7918                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7919         match_criteria_enable |=
7920                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7921                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7922         return match_criteria_enable;
7923 }
7924
7925
7926 /**
7927  * Get a flow table.
7928  *
7929  * @param[in, out] dev
7930  *   Pointer to rte_eth_dev structure.
7931  * @param[in] table_id
7932  *   Table id to use.
7933  * @param[in] egress
7934  *   Direction of the table.
7935  * @param[in] transfer
7936  *   E-Switch or NIC flow.
7937  * @param[out] error
7938  *   pointer to error structure.
7939  *
7940  * @return
7941  *   Returns tables resource based on the index, NULL in case of failed.
7942  */
7943 static struct mlx5_flow_tbl_resource *
7944 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7945                          uint32_t table_id, uint8_t egress,
7946                          uint8_t transfer,
7947                          bool external,
7948                          const struct mlx5_flow_tunnel *tunnel,
7949                          uint32_t group_id,
7950                          struct rte_flow_error *error)
7951 {
7952         struct mlx5_priv *priv = dev->data->dev_private;
7953         struct mlx5_dev_ctx_shared *sh = priv->sh;
7954         struct mlx5_flow_tbl_resource *tbl;
7955         union mlx5_flow_tbl_key table_key = {
7956                 {
7957                         .table_id = table_id,
7958                         .reserved = 0,
7959                         .domain = !!transfer,
7960                         .direction = !!egress,
7961                 }
7962         };
7963         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7964                                                          table_key.v64, NULL);
7965         struct mlx5_flow_tbl_data_entry *tbl_data;
7966         uint32_t idx = 0;
7967         int ret;
7968         void *domain;
7969
7970         if (pos) {
7971                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7972                                         entry);
7973                 tbl = &tbl_data->tbl;
7974                 __atomic_fetch_add(&tbl->refcnt, 1, __ATOMIC_RELAXED);
7975                 return tbl;
7976         }
7977         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7978         if (!tbl_data) {
7979                 rte_flow_error_set(error, ENOMEM,
7980                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7981                                    NULL,
7982                                    "cannot allocate flow table data entry");
7983                 return NULL;
7984         }
7985         tbl_data->idx = idx;
7986         tbl_data->tunnel = tunnel;
7987         tbl_data->group_id = group_id;
7988         tbl_data->external = external;
7989         tbl = &tbl_data->tbl;
7990         pos = &tbl_data->entry;
7991         if (transfer)
7992                 domain = sh->fdb_domain;
7993         else if (egress)
7994                 domain = sh->tx_domain;
7995         else
7996                 domain = sh->rx_domain;
7997         ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7998         if (ret) {
7999                 rte_flow_error_set(error, ENOMEM,
8000                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8001                                    NULL, "cannot create flow table object");
8002                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8003                 return NULL;
8004         }
8005         /*
8006          * No multi-threads now, but still better to initialize the reference
8007          * count before insert it into the hash list.
8008          */
8009         __atomic_store_n(&tbl->refcnt, 0, __ATOMIC_RELAXED);
8010
8011         if (table_id) {
8012                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8013                                         (tbl->obj, &tbl_data->jump.action);
8014                 if (ret) {
8015                         rte_flow_error_set(error, ENOMEM,
8016                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8017                                            NULL,
8018                                            "cannot create flow jump action");
8019                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8020                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8021                         return NULL;
8022                 }
8023         }
8024         pos->key = table_key.v64;
8025         ret = !mlx5_hlist_insert(sh->flow_tbls, pos);
8026         if (ret < 0) {
8027                 rte_flow_error_set(error, -ret,
8028                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8029                                    "cannot insert flow table data entry");
8030                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8031                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8032         }
8033         __atomic_fetch_add(&tbl->refcnt, 1, __ATOMIC_RELAXED);
8034         return tbl;
8035 }
8036
8037 /**
8038  * Release a flow table.
8039  *
8040  * @param[in] dev
8041  *   Pointer to rte_eth_dev structure.
8042  * @param[in] tbl
8043  *   Table resource to be released.
8044  *
8045  * @return
8046  *   Returns 0 if table was released, else return 1;
8047  */
8048 static int
8049 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
8050                              struct mlx5_flow_tbl_resource *tbl)
8051 {
8052         struct mlx5_priv *priv = dev->data->dev_private;
8053         struct mlx5_dev_ctx_shared *sh = priv->sh;
8054         struct mlx5_flow_tbl_data_entry *tbl_data =
8055                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8056
8057         if (!tbl)
8058                 return 0;
8059         if (__atomic_sub_fetch(&tbl->refcnt, 1, __ATOMIC_RELAXED) == 0) {
8060                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
8061
8062                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8063                 tbl->obj = NULL;
8064                 if (is_tunnel_offload_active(dev) && tbl_data->external) {
8065                         struct mlx5_hlist_entry *he;
8066                         struct mlx5_hlist *tunnel_grp_hash;
8067                         struct mlx5_flow_tunnel_hub *thub =
8068                                                         mlx5_tunnel_hub(dev);
8069                         union tunnel_tbl_key tunnel_key = {
8070                                 .tunnel_id = tbl_data->tunnel ?
8071                                                 tbl_data->tunnel->tunnel_id : 0,
8072                                 .group = tbl_data->group_id
8073                         };
8074                         union mlx5_flow_tbl_key table_key = {
8075                                 .v64 = pos->key
8076                         };
8077                         uint32_t table_id = table_key.table_id;
8078
8079                         tunnel_grp_hash = tbl_data->tunnel ?
8080                                                 tbl_data->tunnel->groups :
8081                                                 thub->groups;
8082                         he = mlx5_hlist_lookup(tunnel_grp_hash,
8083                                                tunnel_key.val, NULL);
8084                         if (he) {
8085                                 struct tunnel_tbl_entry *tte;
8086                                 tte = container_of(he, typeof(*tte), hash);
8087                                 MLX5_ASSERT(tte->flow_table == table_id);
8088                                 mlx5_hlist_remove(tunnel_grp_hash, he);
8089                                 mlx5_free(tte);
8090                         }
8091                         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TNL_TBL_ID],
8092                                         tunnel_flow_tbl_to_id(table_id));
8093                         DRV_LOG(DEBUG,
8094                                 "port %u release table_id %#x tunnel %u group %u",
8095                                 dev->data->port_id, table_id,
8096                                 tbl_data->tunnel ?
8097                                 tbl_data->tunnel->tunnel_id : 0,
8098                                 tbl_data->group_id);
8099                 }
8100                 /* remove the entry from the hash list and free memory. */
8101                 mlx5_hlist_remove(sh->flow_tbls, pos);
8102                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
8103                                 tbl_data->idx);
8104                 return 0;
8105         }
8106         return 1;
8107 }
8108
8109 /**
8110  * Register the flow matcher.
8111  *
8112  * @param[in, out] dev
8113  *   Pointer to rte_eth_dev structure.
8114  * @param[in, out] matcher
8115  *   Pointer to flow matcher.
8116  * @param[in, out] key
8117  *   Pointer to flow table key.
8118  * @parm[in, out] dev_flow
8119  *   Pointer to the dev_flow.
8120  * @param[out] error
8121  *   pointer to error structure.
8122  *
8123  * @return
8124  *   0 on success otherwise -errno and errno is set.
8125  */
8126 static int
8127 flow_dv_matcher_register(struct rte_eth_dev *dev,
8128                          struct mlx5_flow_dv_matcher *matcher,
8129                          union mlx5_flow_tbl_key *key,
8130                          struct mlx5_flow *dev_flow,
8131                          struct rte_flow_error *error)
8132 {
8133         struct mlx5_priv *priv = dev->data->dev_private;
8134         struct mlx5_dev_ctx_shared *sh = priv->sh;
8135         struct mlx5_flow_dv_matcher *cache_matcher;
8136         struct mlx5dv_flow_matcher_attr dv_attr = {
8137                 .type = IBV_FLOW_ATTR_NORMAL,
8138                 .match_mask = (void *)&matcher->mask,
8139         };
8140         struct mlx5_flow_tbl_resource *tbl;
8141         struct mlx5_flow_tbl_data_entry *tbl_data;
8142         int ret;
8143
8144         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
8145                                        key->domain, false, NULL, 0, error);
8146         if (!tbl)
8147                 return -rte_errno;      /* No need to refill the error info */
8148         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8149         /* Lookup from cache. */
8150         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
8151                 if (matcher->crc == cache_matcher->crc &&
8152                     matcher->priority == cache_matcher->priority &&
8153                     !memcmp((const void *)matcher->mask.buf,
8154                             (const void *)cache_matcher->mask.buf,
8155                             cache_matcher->mask.size)) {
8156                         DRV_LOG(DEBUG,
8157                                 "%s group %u priority %hd use %s "
8158                                 "matcher %p: refcnt %d++",
8159                                 key->domain ? "FDB" : "NIC", key->table_id,
8160                                 cache_matcher->priority,
8161                                 key->direction ? "tx" : "rx",
8162                                 (void *)cache_matcher,
8163                                 __atomic_load_n(&cache_matcher->refcnt,
8164                                                 __ATOMIC_RELAXED));
8165                         __atomic_fetch_add(&cache_matcher->refcnt, 1,
8166                                            __ATOMIC_RELAXED);
8167                         dev_flow->handle->dvh.matcher = cache_matcher;
8168                         /* old matcher should not make the table ref++. */
8169                         flow_dv_tbl_resource_release(dev, tbl);
8170                         return 0;
8171                 }
8172         }
8173         /* Register new matcher. */
8174         cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
8175                                     SOCKET_ID_ANY);
8176         if (!cache_matcher) {
8177                 flow_dv_tbl_resource_release(dev, tbl);
8178                 return rte_flow_error_set(error, ENOMEM,
8179                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8180                                           "cannot allocate matcher memory");
8181         }
8182         *cache_matcher = *matcher;
8183         dv_attr.match_criteria_enable =
8184                 flow_dv_matcher_enable(cache_matcher->mask.buf);
8185         dv_attr.priority = matcher->priority;
8186         if (key->direction)
8187                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8188         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
8189                                                &cache_matcher->matcher_object);
8190         if (ret) {
8191                 mlx5_free(cache_matcher);
8192 #ifdef HAVE_MLX5DV_DR
8193                 flow_dv_tbl_resource_release(dev, tbl);
8194 #endif
8195                 return rte_flow_error_set(error, ENOMEM,
8196                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8197                                           NULL, "cannot create matcher");
8198         }
8199         /* Save the table information */
8200         cache_matcher->tbl = tbl;
8201         /* only matcher ref++, table ref++ already done above in get API. */
8202         __atomic_store_n(&cache_matcher->refcnt, 1, __ATOMIC_RELAXED);
8203         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
8204         dev_flow->handle->dvh.matcher = cache_matcher;
8205         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
8206                 key->domain ? "FDB" : "NIC", key->table_id,
8207                 cache_matcher->priority,
8208                 key->direction ? "tx" : "rx", (void *)cache_matcher,
8209                 __atomic_load_n(&cache_matcher->refcnt, __ATOMIC_RELAXED));
8210         return 0;
8211 }
8212
8213 /**
8214  * Find existing tag resource or create and register a new one.
8215  *
8216  * @param dev[in, out]
8217  *   Pointer to rte_eth_dev structure.
8218  * @param[in, out] tag_be24
8219  *   Tag value in big endian then R-shift 8.
8220  * @parm[in, out] dev_flow
8221  *   Pointer to the dev_flow.
8222  * @param[out] error
8223  *   pointer to error structure.
8224  *
8225  * @return
8226  *   0 on success otherwise -errno and errno is set.
8227  */
8228 static int
8229 flow_dv_tag_resource_register
8230                         (struct rte_eth_dev *dev,
8231                          uint32_t tag_be24,
8232                          struct mlx5_flow *dev_flow,
8233                          struct rte_flow_error *error)
8234 {
8235         struct mlx5_priv *priv = dev->data->dev_private;
8236         struct mlx5_dev_ctx_shared *sh = priv->sh;
8237         struct mlx5_flow_dv_tag_resource *cache_resource;
8238         struct mlx5_hlist_entry *entry;
8239         int ret;
8240
8241         /* Lookup a matching resource from cache. */
8242         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24, NULL);
8243         if (entry) {
8244                 cache_resource = container_of
8245                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8246                 __atomic_fetch_add(&cache_resource->refcnt, 1,
8247                                    __ATOMIC_RELAXED);
8248                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8249                 dev_flow->dv.tag_resource = cache_resource;
8250                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
8251                         (void *)cache_resource,
8252                         __atomic_load_n(&cache_resource->refcnt,
8253                                         __ATOMIC_RELAXED));
8254                 return 0;
8255         }
8256         /* Register new resource. */
8257         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
8258                                        &dev_flow->handle->dvh.rix_tag);
8259         if (!cache_resource)
8260                 return rte_flow_error_set(error, ENOMEM,
8261                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8262                                           "cannot allocate resource memory");
8263         cache_resource->entry.key = (uint64_t)tag_be24;
8264         ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
8265                                                   &cache_resource->action);
8266         if (ret) {
8267                 mlx5_free(cache_resource);
8268                 return rte_flow_error_set(error, ENOMEM,
8269                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8270                                           NULL, "cannot create action");
8271         }
8272         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8273         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
8274                 mlx5_flow_os_destroy_flow_action(cache_resource->action);
8275                 mlx5_free(cache_resource);
8276                 return rte_flow_error_set(error, EEXIST,
8277                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8278                                           NULL, "cannot insert tag");
8279         }
8280         dev_flow->dv.tag_resource = cache_resource;
8281         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
8282                 (void *)cache_resource,
8283                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8284         return 0;
8285 }
8286
8287 /**
8288  * Release the tag.
8289  *
8290  * @param dev
8291  *   Pointer to Ethernet device.
8292  * @param tag_idx
8293  *   Tag index.
8294  *
8295  * @return
8296  *   1 while a reference on it exists, 0 when freed.
8297  */
8298 static int
8299 flow_dv_tag_release(struct rte_eth_dev *dev,
8300                     uint32_t tag_idx)
8301 {
8302         struct mlx5_priv *priv = dev->data->dev_private;
8303         struct mlx5_dev_ctx_shared *sh = priv->sh;
8304         struct mlx5_flow_dv_tag_resource *tag;
8305
8306         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8307         if (!tag)
8308                 return 0;
8309         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8310                 dev->data->port_id, (void *)tag,
8311                 __atomic_load_n(&tag->refcnt, __ATOMIC_RELAXED));
8312         if (__atomic_sub_fetch(&tag->refcnt, 1, __ATOMIC_RELAXED) == 0) {
8313                 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8314                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
8315                 DRV_LOG(DEBUG, "port %u tag %p: removed",
8316                         dev->data->port_id, (void *)tag);
8317                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8318                 return 0;
8319         }
8320         return 1;
8321 }
8322
8323 /**
8324  * Translate port ID action to vport.
8325  *
8326  * @param[in] dev
8327  *   Pointer to rte_eth_dev structure.
8328  * @param[in] action
8329  *   Pointer to the port ID action.
8330  * @param[out] dst_port_id
8331  *   The target port ID.
8332  * @param[out] error
8333  *   Pointer to the error structure.
8334  *
8335  * @return
8336  *   0 on success, a negative errno value otherwise and rte_errno is set.
8337  */
8338 static int
8339 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8340                                  const struct rte_flow_action *action,
8341                                  uint32_t *dst_port_id,
8342                                  struct rte_flow_error *error)
8343 {
8344         uint32_t port;
8345         struct mlx5_priv *priv;
8346         const struct rte_flow_action_port_id *conf =
8347                         (const struct rte_flow_action_port_id *)action->conf;
8348
8349         port = conf->original ? dev->data->port_id : conf->id;
8350         priv = mlx5_port_to_eswitch_info(port, false);
8351         if (!priv)
8352                 return rte_flow_error_set(error, -rte_errno,
8353                                           RTE_FLOW_ERROR_TYPE_ACTION,
8354                                           NULL,
8355                                           "No eswitch info was found for port");
8356 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8357         /*
8358          * This parameter is transferred to
8359          * mlx5dv_dr_action_create_dest_ib_port().
8360          */
8361         *dst_port_id = priv->dev_port;
8362 #else
8363         /*
8364          * Legacy mode, no LAG configurations is supported.
8365          * This parameter is transferred to
8366          * mlx5dv_dr_action_create_dest_vport().
8367          */
8368         *dst_port_id = priv->vport_id;
8369 #endif
8370         return 0;
8371 }
8372
8373 /**
8374  * Create a counter with aging configuration.
8375  *
8376  * @param[in] dev
8377  *   Pointer to rte_eth_dev structure.
8378  * @param[out] count
8379  *   Pointer to the counter action configuration.
8380  * @param[in] age
8381  *   Pointer to the aging action configuration.
8382  *
8383  * @return
8384  *   Index to flow counter on success, 0 otherwise.
8385  */
8386 static uint32_t
8387 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8388                                 struct mlx5_flow *dev_flow,
8389                                 const struct rte_flow_action_count *count,
8390                                 const struct rte_flow_action_age *age)
8391 {
8392         uint32_t counter;
8393         struct mlx5_age_param *age_param;
8394
8395         if (count && count->shared)
8396                 counter = flow_dv_counter_get_shared(dev, count->id);
8397         else
8398                 counter = flow_dv_counter_alloc(dev, !!age);
8399         if (!counter || age == NULL)
8400                 return counter;
8401         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8402         age_param->context = age->context ? age->context :
8403                 (void *)(uintptr_t)(dev_flow->flow_idx);
8404         age_param->timeout = age->timeout;
8405         age_param->port_id = dev->data->port_id;
8406         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8407         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8408         return counter;
8409 }
8410 /**
8411  * Add Tx queue matcher
8412  *
8413  * @param[in] dev
8414  *   Pointer to the dev struct.
8415  * @param[in, out] matcher
8416  *   Flow matcher.
8417  * @param[in, out] key
8418  *   Flow matcher value.
8419  * @param[in] item
8420  *   Flow pattern to translate.
8421  * @param[in] inner
8422  *   Item is inner pattern.
8423  */
8424 static void
8425 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8426                                 void *matcher, void *key,
8427                                 const struct rte_flow_item *item)
8428 {
8429         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8430         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8431         void *misc_m =
8432                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8433         void *misc_v =
8434                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8435         struct mlx5_txq_ctrl *txq;
8436         uint32_t queue;
8437
8438
8439         queue_m = (const void *)item->mask;
8440         if (!queue_m)
8441                 return;
8442         queue_v = (const void *)item->spec;
8443         if (!queue_v)
8444                 return;
8445         txq = mlx5_txq_get(dev, queue_v->queue);
8446         if (!txq)
8447                 return;
8448         queue = txq->obj->sq->id;
8449         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8450         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8451                  queue & queue_m->queue);
8452         mlx5_txq_release(dev, queue_v->queue);
8453 }
8454
8455 /**
8456  * Set the hash fields according to the @p flow information.
8457  *
8458  * @param[in] dev_flow
8459  *   Pointer to the mlx5_flow.
8460  * @param[in] rss_desc
8461  *   Pointer to the mlx5_flow_rss_desc.
8462  */
8463 static void
8464 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8465                        struct mlx5_flow_rss_desc *rss_desc)
8466 {
8467         uint64_t items = dev_flow->handle->layers;
8468         int rss_inner = 0;
8469         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8470
8471         dev_flow->hash_fields = 0;
8472 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8473         if (rss_desc->level >= 2) {
8474                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8475                 rss_inner = 1;
8476         }
8477 #endif
8478         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8479             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8480                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8481                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8482                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8483                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8484                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8485                         else
8486                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8487                 }
8488         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8489                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8490                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8491                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8492                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8493                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8494                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8495                         else
8496                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8497                 }
8498         }
8499         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8500             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8501                 if (rss_types & ETH_RSS_UDP) {
8502                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8503                                 dev_flow->hash_fields |=
8504                                                 IBV_RX_HASH_SRC_PORT_UDP;
8505                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8506                                 dev_flow->hash_fields |=
8507                                                 IBV_RX_HASH_DST_PORT_UDP;
8508                         else
8509                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8510                 }
8511         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8512                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8513                 if (rss_types & ETH_RSS_TCP) {
8514                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8515                                 dev_flow->hash_fields |=
8516                                                 IBV_RX_HASH_SRC_PORT_TCP;
8517                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8518                                 dev_flow->hash_fields |=
8519                                                 IBV_RX_HASH_DST_PORT_TCP;
8520                         else
8521                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8522                 }
8523         }
8524 }
8525
8526 /**
8527  * Create an Rx Hash queue.
8528  *
8529  * @param dev
8530  *   Pointer to Ethernet device.
8531  * @param[in] dev_flow
8532  *   Pointer to the mlx5_flow.
8533  * @param[in] rss_desc
8534  *   Pointer to the mlx5_flow_rss_desc.
8535  * @param[out] hrxq_idx
8536  *   Hash Rx queue index.
8537  *
8538  * @return
8539  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8540  */
8541 static struct mlx5_hrxq *
8542 flow_dv_handle_rx_queue(struct rte_eth_dev *dev,
8543                         struct mlx5_flow *dev_flow,
8544                         struct mlx5_flow_rss_desc *rss_desc,
8545                         uint32_t *hrxq_idx)
8546 {
8547         struct mlx5_priv *priv = dev->data->dev_private;
8548         struct mlx5_flow_handle *dh = dev_flow->handle;
8549         struct mlx5_hrxq *hrxq;
8550
8551         MLX5_ASSERT(rss_desc->queue_num);
8552         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8553                                   dev_flow->hash_fields,
8554                                   rss_desc->queue, rss_desc->queue_num);
8555         if (!*hrxq_idx) {
8556                 *hrxq_idx = mlx5_hrxq_new
8557                                 (dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8558                                  dev_flow->hash_fields,
8559                                  rss_desc->queue, rss_desc->queue_num,
8560                                  !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL),
8561                                  false);
8562                 if (!*hrxq_idx)
8563                         return NULL;
8564         }
8565         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8566                               *hrxq_idx);
8567         return hrxq;
8568 }
8569
8570 /**
8571  * Find existing sample resource or create and register a new one.
8572  *
8573  * @param[in, out] dev
8574  *   Pointer to rte_eth_dev structure.
8575  * @param[in] attr
8576  *   Attributes of flow that includes this item.
8577  * @param[in] resource
8578  *   Pointer to sample resource.
8579  * @parm[in, out] dev_flow
8580  *   Pointer to the dev_flow.
8581  * @param[in, out] sample_dv_actions
8582  *   Pointer to sample actions list.
8583  * @param[out] error
8584  *   pointer to error structure.
8585  *
8586  * @return
8587  *   0 on success otherwise -errno and errno is set.
8588  */
8589 static int
8590 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8591                          const struct rte_flow_attr *attr,
8592                          struct mlx5_flow_dv_sample_resource *resource,
8593                          struct mlx5_flow *dev_flow,
8594                          void **sample_dv_actions,
8595                          struct rte_flow_error *error)
8596 {
8597         struct mlx5_flow_dv_sample_resource *cache_resource;
8598         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8599         struct mlx5_priv *priv = dev->data->dev_private;
8600         struct mlx5_dev_ctx_shared *sh = priv->sh;
8601         struct mlx5_flow_tbl_resource *tbl;
8602         uint32_t idx = 0;
8603         const uint32_t next_ft_step = 1;
8604         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8605
8606         /* Lookup a matching resource from cache. */
8607         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_SAMPLE], sh->sample_action_list,
8608                       idx, cache_resource, next) {
8609                 if (resource->ratio == cache_resource->ratio &&
8610                     resource->ft_type == cache_resource->ft_type &&
8611                     resource->ft_id == cache_resource->ft_id &&
8612                     resource->set_action == cache_resource->set_action &&
8613                     !memcmp((void *)&resource->sample_act,
8614                             (void *)&cache_resource->sample_act,
8615                             sizeof(struct mlx5_flow_sub_actions_list))) {
8616                         DRV_LOG(DEBUG, "sample resource %p: refcnt %d++",
8617                                 (void *)cache_resource,
8618                                 __atomic_load_n(&cache_resource->refcnt,
8619                                                 __ATOMIC_RELAXED));
8620                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8621                                            __ATOMIC_RELAXED);
8622                         dev_flow->handle->dvh.rix_sample = idx;
8623                         dev_flow->dv.sample_res = cache_resource;
8624                         return 0;
8625                 }
8626         }
8627         /* Register new sample resource. */
8628         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE],
8629                                        &dev_flow->handle->dvh.rix_sample);
8630         if (!cache_resource)
8631                 return rte_flow_error_set(error, ENOMEM,
8632                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8633                                           NULL,
8634                                           "cannot allocate resource memory");
8635         *cache_resource = *resource;
8636         /* Create normal path table level */
8637         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8638                                         attr->egress, attr->transfer,
8639                                         dev_flow->external, NULL, 0, error);
8640         if (!tbl) {
8641                 rte_flow_error_set(error, ENOMEM,
8642                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8643                                           NULL,
8644                                           "fail to create normal path table "
8645                                           "for sample");
8646                 goto error;
8647         }
8648         cache_resource->normal_path_tbl = tbl;
8649         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8650                 cache_resource->default_miss =
8651                                 mlx5_glue->dr_create_flow_action_default_miss();
8652                 if (!cache_resource->default_miss) {
8653                         rte_flow_error_set(error, ENOMEM,
8654                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8655                                                 NULL,
8656                                                 "cannot create default miss "
8657                                                 "action");
8658                         goto error;
8659                 }
8660                 sample_dv_actions[resource->sample_act.actions_num++] =
8661                                                 cache_resource->default_miss;
8662         }
8663         /* Create a DR sample action */
8664         sampler_attr.sample_ratio = cache_resource->ratio;
8665         sampler_attr.default_next_table = tbl->obj;
8666         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8667         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8668                                                         &sample_dv_actions[0];
8669         sampler_attr.action = cache_resource->set_action;
8670         cache_resource->verbs_action =
8671                 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8672         if (!cache_resource->verbs_action) {
8673                 rte_flow_error_set(error, ENOMEM,
8674                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8675                                         NULL, "cannot create sample action");
8676                 goto error;
8677         }
8678         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8679         ILIST_INSERT(sh->ipool[MLX5_IPOOL_SAMPLE], &sh->sample_action_list,
8680                      dev_flow->handle->dvh.rix_sample, cache_resource,
8681                      next);
8682         dev_flow->dv.sample_res = cache_resource;
8683         DRV_LOG(DEBUG, "new sample resource %p: refcnt %d++",
8684                 (void *)cache_resource,
8685                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8686         return 0;
8687 error:
8688         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8689                 if (cache_resource->default_miss)
8690                         claim_zero(mlx5_glue->destroy_flow_action
8691                                 (cache_resource->default_miss));
8692         } else {
8693                 if (cache_resource->sample_idx.rix_hrxq &&
8694                     !mlx5_hrxq_release(dev,
8695                                 cache_resource->sample_idx.rix_hrxq))
8696                         cache_resource->sample_idx.rix_hrxq = 0;
8697                 if (cache_resource->sample_idx.rix_tag &&
8698                     !flow_dv_tag_release(dev,
8699                                 cache_resource->sample_idx.rix_tag))
8700                         cache_resource->sample_idx.rix_tag = 0;
8701                 if (cache_resource->sample_idx.cnt) {
8702                         flow_dv_counter_release(dev,
8703                                 cache_resource->sample_idx.cnt);
8704                         cache_resource->sample_idx.cnt = 0;
8705                 }
8706         }
8707         if (cache_resource->normal_path_tbl)
8708                 flow_dv_tbl_resource_release(dev,
8709                                 cache_resource->normal_path_tbl);
8710         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE],
8711                                 dev_flow->handle->dvh.rix_sample);
8712         dev_flow->handle->dvh.rix_sample = 0;
8713         return -rte_errno;
8714 }
8715
8716 /**
8717  * Find existing destination array resource or create and register a new one.
8718  *
8719  * @param[in, out] dev
8720  *   Pointer to rte_eth_dev structure.
8721  * @param[in] attr
8722  *   Attributes of flow that includes this item.
8723  * @param[in] resource
8724  *   Pointer to destination array resource.
8725  * @parm[in, out] dev_flow
8726  *   Pointer to the dev_flow.
8727  * @param[out] error
8728  *   pointer to error structure.
8729  *
8730  * @return
8731  *   0 on success otherwise -errno and errno is set.
8732  */
8733 static int
8734 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
8735                          const struct rte_flow_attr *attr,
8736                          struct mlx5_flow_dv_dest_array_resource *resource,
8737                          struct mlx5_flow *dev_flow,
8738                          struct rte_flow_error *error)
8739 {
8740         struct mlx5_flow_dv_dest_array_resource *cache_resource;
8741         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8742         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8743         struct mlx5_priv *priv = dev->data->dev_private;
8744         struct mlx5_dev_ctx_shared *sh = priv->sh;
8745         struct mlx5_flow_sub_actions_list *sample_act;
8746         struct mlx5dv_dr_domain *domain;
8747         uint32_t idx = 0;
8748
8749         /* Lookup a matching resource from cache. */
8750         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8751                       sh->dest_array_list,
8752                       idx, cache_resource, next) {
8753                 if (resource->num_of_dest == cache_resource->num_of_dest &&
8754                     resource->ft_type == cache_resource->ft_type &&
8755                     !memcmp((void *)cache_resource->sample_act,
8756                             (void *)resource->sample_act,
8757                            (resource->num_of_dest *
8758                            sizeof(struct mlx5_flow_sub_actions_list)))) {
8759                         DRV_LOG(DEBUG, "dest array resource %p: refcnt %d++",
8760                                 (void *)cache_resource,
8761                                 __atomic_load_n(&cache_resource->refcnt,
8762                                                 __ATOMIC_RELAXED));
8763                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8764                                            __ATOMIC_RELAXED);
8765                         dev_flow->handle->dvh.rix_dest_array = idx;
8766                         dev_flow->dv.dest_array_res = cache_resource;
8767                         return 0;
8768                 }
8769         }
8770         /* Register new destination array resource. */
8771         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8772                                        &dev_flow->handle->dvh.rix_dest_array);
8773         if (!cache_resource)
8774                 return rte_flow_error_set(error, ENOMEM,
8775                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8776                                           NULL,
8777                                           "cannot allocate resource memory");
8778         *cache_resource = *resource;
8779         if (attr->transfer)
8780                 domain = sh->fdb_domain;
8781         else if (attr->ingress)
8782                 domain = sh->rx_domain;
8783         else
8784                 domain = sh->tx_domain;
8785         for (idx = 0; idx < resource->num_of_dest; idx++) {
8786                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8787                                  mlx5_malloc(MLX5_MEM_ZERO,
8788                                  sizeof(struct mlx5dv_dr_action_dest_attr),
8789                                  0, SOCKET_ID_ANY);
8790                 if (!dest_attr[idx]) {
8791                         rte_flow_error_set(error, ENOMEM,
8792                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8793                                            NULL,
8794                                            "cannot allocate resource memory");
8795                         goto error;
8796                 }
8797                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8798                 sample_act = &resource->sample_act[idx];
8799                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8800                         dest_attr[idx]->dest = sample_act->dr_queue_action;
8801                 } else if (sample_act->action_flags ==
8802                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8803                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8804                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8805                         dest_attr[idx]->dest_reformat->reformat =
8806                                         sample_act->dr_encap_action;
8807                         dest_attr[idx]->dest_reformat->dest =
8808                                         sample_act->dr_port_id_action;
8809                 } else if (sample_act->action_flags ==
8810                            MLX5_FLOW_ACTION_PORT_ID) {
8811                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
8812                 }
8813         }
8814         /* create a dest array actioin */
8815         cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8816                                                 (domain,
8817                                                  cache_resource->num_of_dest,
8818                                                  dest_attr);
8819         if (!cache_resource->action) {
8820                 rte_flow_error_set(error, ENOMEM,
8821                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8822                                    NULL,
8823                                    "cannot create destination array action");
8824                 goto error;
8825         }
8826         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8827         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8828                      &sh->dest_array_list,
8829                      dev_flow->handle->dvh.rix_dest_array, cache_resource,
8830                      next);
8831         dev_flow->dv.dest_array_res = cache_resource;
8832         DRV_LOG(DEBUG, "new destination array resource %p: refcnt %d++",
8833                 (void *)cache_resource,
8834                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8835         for (idx = 0; idx < resource->num_of_dest; idx++)
8836                 mlx5_free(dest_attr[idx]);
8837         return 0;
8838 error:
8839         for (idx = 0; idx < resource->num_of_dest; idx++) {
8840                 struct mlx5_flow_sub_actions_idx *act_res =
8841                                         &cache_resource->sample_idx[idx];
8842                 if (act_res->rix_hrxq &&
8843                     !mlx5_hrxq_release(dev,
8844                                 act_res->rix_hrxq))
8845                         act_res->rix_hrxq = 0;
8846                 if (act_res->rix_encap_decap &&
8847                         !flow_dv_encap_decap_resource_release(dev,
8848                                 act_res->rix_encap_decap))
8849                         act_res->rix_encap_decap = 0;
8850                 if (act_res->rix_port_id_action &&
8851                         !flow_dv_port_id_action_resource_release(dev,
8852                                 act_res->rix_port_id_action))
8853                         act_res->rix_port_id_action = 0;
8854                 if (dest_attr[idx])
8855                         mlx5_free(dest_attr[idx]);
8856         }
8857
8858         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8859                                 dev_flow->handle->dvh.rix_dest_array);
8860         dev_flow->handle->dvh.rix_dest_array = 0;
8861         return -rte_errno;
8862 }
8863
8864 /**
8865  * Convert Sample action to DV specification.
8866  *
8867  * @param[in] dev
8868  *   Pointer to rte_eth_dev structure.
8869  * @param[in] action
8870  *   Pointer to action structure.
8871  * @param[in, out] dev_flow
8872  *   Pointer to the mlx5_flow.
8873  * @param[in] attr
8874  *   Pointer to the flow attributes.
8875  * @param[in, out] num_of_dest
8876  *   Pointer to the num of destination.
8877  * @param[in, out] sample_actions
8878  *   Pointer to sample actions list.
8879  * @param[in, out] res
8880  *   Pointer to sample resource.
8881  * @param[out] error
8882  *   Pointer to the error structure.
8883  *
8884  * @return
8885  *   0 on success, a negative errno value otherwise and rte_errno is set.
8886  */
8887 static int
8888 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
8889                                 const struct rte_flow_action *action,
8890                                 struct mlx5_flow *dev_flow,
8891                                 const struct rte_flow_attr *attr,
8892                                 uint32_t *num_of_dest,
8893                                 void **sample_actions,
8894                                 struct mlx5_flow_dv_sample_resource *res,
8895                                 struct rte_flow_error *error)
8896 {
8897         struct mlx5_priv *priv = dev->data->dev_private;
8898         const struct rte_flow_action_sample *sample_action;
8899         const struct rte_flow_action *sub_actions;
8900         const struct rte_flow_action_queue *queue;
8901         struct mlx5_flow_sub_actions_list *sample_act;
8902         struct mlx5_flow_sub_actions_idx *sample_idx;
8903         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8904         struct mlx5_flow_rss_desc *rss_desc;
8905         uint64_t action_flags = 0;
8906
8907         MLX5_ASSERT(wks);
8908         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
8909         sample_act = &res->sample_act;
8910         sample_idx = &res->sample_idx;
8911         sample_action = (const struct rte_flow_action_sample *)action->conf;
8912         res->ratio = sample_action->ratio;
8913         sub_actions = sample_action->actions;
8914         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
8915                 int type = sub_actions->type;
8916                 uint32_t pre_rix = 0;
8917                 void *pre_r;
8918                 switch (type) {
8919                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8920                 {
8921                         struct mlx5_hrxq *hrxq;
8922                         uint32_t hrxq_idx;
8923
8924                         queue = sub_actions->conf;
8925                         rss_desc->queue_num = 1;
8926                         rss_desc->queue[0] = queue->index;
8927                         hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
8928                                         rss_desc, &hrxq_idx);
8929                         if (!hrxq)
8930                                 return rte_flow_error_set
8931                                         (error, rte_errno,
8932                                          RTE_FLOW_ERROR_TYPE_ACTION,
8933                                          NULL,
8934                                          "cannot create fate queue");
8935                         sample_act->dr_queue_action = hrxq->action;
8936                         sample_idx->rix_hrxq = hrxq_idx;
8937                         sample_actions[sample_act->actions_num++] =
8938                                                 hrxq->action;
8939                         (*num_of_dest)++;
8940                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8941                         if (action_flags & MLX5_FLOW_ACTION_MARK)
8942                                 dev_flow->handle->rix_hrxq = hrxq_idx;
8943                         dev_flow->handle->fate_action =
8944                                         MLX5_FLOW_FATE_QUEUE;
8945                         break;
8946                 }
8947                 case RTE_FLOW_ACTION_TYPE_MARK:
8948                 {
8949                         uint32_t tag_be = mlx5_flow_mark_set
8950                                 (((const struct rte_flow_action_mark *)
8951                                 (sub_actions->conf))->id);
8952
8953                         dev_flow->handle->mark = 1;
8954                         pre_rix = dev_flow->handle->dvh.rix_tag;
8955                         /* Save the mark resource before sample */
8956                         pre_r = dev_flow->dv.tag_resource;
8957                         if (flow_dv_tag_resource_register(dev, tag_be,
8958                                                   dev_flow, error))
8959                                 return -rte_errno;
8960                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8961                         sample_act->dr_tag_action =
8962                                 dev_flow->dv.tag_resource->action;
8963                         sample_idx->rix_tag =
8964                                 dev_flow->handle->dvh.rix_tag;
8965                         sample_actions[sample_act->actions_num++] =
8966                                                 sample_act->dr_tag_action;
8967                         /* Recover the mark resource after sample */
8968                         dev_flow->dv.tag_resource = pre_r;
8969                         dev_flow->handle->dvh.rix_tag = pre_rix;
8970                         action_flags |= MLX5_FLOW_ACTION_MARK;
8971                         break;
8972                 }
8973                 case RTE_FLOW_ACTION_TYPE_COUNT:
8974                 {
8975                         uint32_t counter;
8976
8977                         counter = flow_dv_translate_create_counter(dev,
8978                                         dev_flow, sub_actions->conf, 0);
8979                         if (!counter)
8980                                 return rte_flow_error_set
8981                                                 (error, rte_errno,
8982                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8983                                                  NULL,
8984                                                  "cannot create counter"
8985                                                  " object.");
8986                         sample_idx->cnt = counter;
8987                         sample_act->dr_cnt_action =
8988                                   (flow_dv_counter_get_by_idx(dev,
8989                                   counter, NULL))->action;
8990                         sample_actions[sample_act->actions_num++] =
8991                                                 sample_act->dr_cnt_action;
8992                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8993                         break;
8994                 }
8995                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8996                 {
8997                         struct mlx5_flow_dv_port_id_action_resource
8998                                         port_id_resource;
8999                         uint32_t port_id = 0;
9000
9001                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9002                         /* Save the port id resource before sample */
9003                         pre_rix = dev_flow->handle->rix_port_id_action;
9004                         pre_r = dev_flow->dv.port_id_action;
9005                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9006                                                              &port_id, error))
9007                                 return -rte_errno;
9008                         port_id_resource.port_id = port_id;
9009                         if (flow_dv_port_id_action_resource_register
9010                             (dev, &port_id_resource, dev_flow, error))
9011                                 return -rte_errno;
9012                         sample_act->dr_port_id_action =
9013                                 dev_flow->dv.port_id_action->action;
9014                         sample_idx->rix_port_id_action =
9015                                 dev_flow->handle->rix_port_id_action;
9016                         sample_actions[sample_act->actions_num++] =
9017                                                 sample_act->dr_port_id_action;
9018                         /* Recover the port id resource after sample */
9019                         dev_flow->dv.port_id_action = pre_r;
9020                         dev_flow->handle->rix_port_id_action = pre_rix;
9021                         (*num_of_dest)++;
9022                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9023                         break;
9024                 }
9025                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9026                         /* Save the encap resource before sample */
9027                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9028                         pre_r = dev_flow->dv.encap_decap;
9029                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9030                                                            dev_flow,
9031                                                            attr->transfer,
9032                                                            error))
9033                                 return -rte_errno;
9034                         sample_act->dr_encap_action =
9035                                 dev_flow->dv.encap_decap->action;
9036                         sample_idx->rix_encap_decap =
9037                                 dev_flow->handle->dvh.rix_encap_decap;
9038                         sample_actions[sample_act->actions_num++] =
9039                                                 sample_act->dr_encap_action;
9040                         /* Recover the encap resource after sample */
9041                         dev_flow->dv.encap_decap = pre_r;
9042                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9043                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9044                         break;
9045                 default:
9046                         return rte_flow_error_set(error, EINVAL,
9047                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9048                                 NULL,
9049                                 "Not support for sampler action");
9050                 }
9051         }
9052         sample_act->action_flags = action_flags;
9053         res->ft_id = dev_flow->dv.group;
9054         if (attr->transfer) {
9055                 union {
9056                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9057                         uint64_t set_action;
9058                 } action_ctx = { .set_action = 0 };
9059
9060                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9061                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9062                          MLX5_MODIFICATION_TYPE_SET);
9063                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9064                          MLX5_MODI_META_REG_C_0);
9065                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9066                          priv->vport_meta_tag);
9067                 res->set_action = action_ctx.set_action;
9068         } else if (attr->ingress) {
9069                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9070         }
9071         return 0;
9072 }
9073
9074 /**
9075  * Convert Sample action to DV specification.
9076  *
9077  * @param[in] dev
9078  *   Pointer to rte_eth_dev structure.
9079  * @param[in, out] dev_flow
9080  *   Pointer to the mlx5_flow.
9081  * @param[in] attr
9082  *   Pointer to the flow attributes.
9083  * @param[in] num_of_dest
9084  *   The num of destination.
9085  * @param[in, out] res
9086  *   Pointer to sample resource.
9087  * @param[in, out] mdest_res
9088  *   Pointer to destination array resource.
9089  * @param[in] sample_actions
9090  *   Pointer to sample path actions list.
9091  * @param[in] action_flags
9092  *   Holds the actions detected until now.
9093  * @param[out] error
9094  *   Pointer to the error structure.
9095  *
9096  * @return
9097  *   0 on success, a negative errno value otherwise and rte_errno is set.
9098  */
9099 static int
9100 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9101                              struct mlx5_flow *dev_flow,
9102                              const struct rte_flow_attr *attr,
9103                              uint32_t num_of_dest,
9104                              struct mlx5_flow_dv_sample_resource *res,
9105                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9106                              void **sample_actions,
9107                              uint64_t action_flags,
9108                              struct rte_flow_error *error)
9109 {
9110         /* update normal path action resource into last index of array */
9111         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9112         struct mlx5_flow_sub_actions_list *sample_act =
9113                                         &mdest_res->sample_act[dest_index];
9114         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9115         struct mlx5_flow_rss_desc *rss_desc;
9116         uint32_t normal_idx = 0;
9117         struct mlx5_hrxq *hrxq;
9118         uint32_t hrxq_idx;
9119
9120         MLX5_ASSERT(wks);
9121         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
9122         if (num_of_dest > 1) {
9123                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9124                         /* Handle QP action for mirroring */
9125                         hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
9126                                                        rss_desc, &hrxq_idx);
9127                         if (!hrxq)
9128                                 return rte_flow_error_set
9129                                      (error, rte_errno,
9130                                       RTE_FLOW_ERROR_TYPE_ACTION,
9131                                       NULL,
9132                                       "cannot create rx queue");
9133                         normal_idx++;
9134                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9135                         sample_act->dr_queue_action = hrxq->action;
9136                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9137                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9138                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9139                 }
9140                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9141                         normal_idx++;
9142                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9143                                 dev_flow->handle->dvh.rix_encap_decap;
9144                         sample_act->dr_encap_action =
9145                                 dev_flow->dv.encap_decap->action;
9146                 }
9147                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9148                         normal_idx++;
9149                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9150                                 dev_flow->handle->rix_port_id_action;
9151                         sample_act->dr_port_id_action =
9152                                 dev_flow->dv.port_id_action->action;
9153                 }
9154                 sample_act->actions_num = normal_idx;
9155                 /* update sample action resource into first index of array */
9156                 mdest_res->ft_type = res->ft_type;
9157                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9158                                 sizeof(struct mlx5_flow_sub_actions_idx));
9159                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9160                                 sizeof(struct mlx5_flow_sub_actions_list));
9161                 mdest_res->num_of_dest = num_of_dest;
9162                 if (flow_dv_dest_array_resource_register(dev, attr, mdest_res,
9163                                                          dev_flow, error))
9164                         return rte_flow_error_set(error, EINVAL,
9165                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9166                                                   NULL, "can't create sample "
9167                                                   "action");
9168         } else {
9169                 if (flow_dv_sample_resource_register(dev, attr, res, dev_flow,
9170                                                      sample_actions, error))
9171                         return rte_flow_error_set(error, EINVAL,
9172                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9173                                                   NULL,
9174                                                   "can't create sample action");
9175         }
9176         return 0;
9177 }
9178
9179 /**
9180  * Fill the flow with DV spec, lock free
9181  * (mutex should be acquired by caller).
9182  *
9183  * @param[in] dev
9184  *   Pointer to rte_eth_dev structure.
9185  * @param[in, out] dev_flow
9186  *   Pointer to the sub flow.
9187  * @param[in] attr
9188  *   Pointer to the flow attributes.
9189  * @param[in] items
9190  *   Pointer to the list of items.
9191  * @param[in] actions
9192  *   Pointer to the list of actions.
9193  * @param[out] error
9194  *   Pointer to the error structure.
9195  *
9196  * @return
9197  *   0 on success, a negative errno value otherwise and rte_errno is set.
9198  */
9199 static int
9200 __flow_dv_translate(struct rte_eth_dev *dev,
9201                     struct mlx5_flow *dev_flow,
9202                     const struct rte_flow_attr *attr,
9203                     const struct rte_flow_item items[],
9204                     const struct rte_flow_action actions[],
9205                     struct rte_flow_error *error)
9206 {
9207         struct mlx5_priv *priv = dev->data->dev_private;
9208         struct mlx5_dev_config *dev_conf = &priv->config;
9209         struct rte_flow *flow = dev_flow->flow;
9210         struct mlx5_flow_handle *handle = dev_flow->handle;
9211         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9212         struct mlx5_flow_rss_desc *rss_desc;
9213         uint64_t item_flags = 0;
9214         uint64_t last_item = 0;
9215         uint64_t action_flags = 0;
9216         uint64_t priority = attr->priority;
9217         struct mlx5_flow_dv_matcher matcher = {
9218                 .mask = {
9219                         .size = sizeof(matcher.mask.buf) -
9220                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9221                 },
9222         };
9223         int actions_n = 0;
9224         bool actions_end = false;
9225         union {
9226                 struct mlx5_flow_dv_modify_hdr_resource res;
9227                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9228                             sizeof(struct mlx5_modification_cmd) *
9229                             (MLX5_MAX_MODIFY_NUM + 1)];
9230         } mhdr_dummy;
9231         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9232         const struct rte_flow_action_count *count = NULL;
9233         const struct rte_flow_action_age *age = NULL;
9234         union flow_dv_attr flow_attr = { .attr = 0 };
9235         uint32_t tag_be;
9236         union mlx5_flow_tbl_key tbl_key;
9237         uint32_t modify_action_position = UINT32_MAX;
9238         void *match_mask = matcher.mask.buf;
9239         void *match_value = dev_flow->dv.value.buf;
9240         uint8_t next_protocol = 0xff;
9241         struct rte_vlan_hdr vlan = { 0 };
9242         struct mlx5_flow_dv_dest_array_resource mdest_res;
9243         struct mlx5_flow_dv_sample_resource sample_res;
9244         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9245         struct mlx5_flow_sub_actions_list *sample_act;
9246         uint32_t sample_act_pos = UINT32_MAX;
9247         uint32_t num_of_dest = 0;
9248         int tmp_actions_n = 0;
9249         uint32_t table;
9250         int ret = 0;
9251         const struct mlx5_flow_tunnel *tunnel;
9252         struct flow_grp_info grp_info = {
9253                 .external = !!dev_flow->external,
9254                 .transfer = !!attr->transfer,
9255                 .fdb_def_rule = !!priv->fdb_def_rule,
9256         };
9257
9258         MLX5_ASSERT(wks);
9259         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
9260         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9261         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9262         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9263                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9264         /* update normal path action resource into last index of array */
9265         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9266         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9267                  flow_items_to_tunnel(items) :
9268                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9269                  flow_actions_to_tunnel(actions) :
9270                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9271         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9272                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9273         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9274                                 (dev, tunnel, attr, items, actions);
9275         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9276                                        grp_info, error);
9277         if (ret)
9278                 return ret;
9279         dev_flow->dv.group = table;
9280         if (attr->transfer)
9281                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9282         if (priority == MLX5_FLOW_PRIO_RSVD)
9283                 priority = dev_conf->flow_prio - 1;
9284         /* number of actions must be set to 0 in case of dirty stack. */
9285         mhdr_res->actions_num = 0;
9286         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9287                 /*
9288                  * do not add decap action if match rule drops packet
9289                  * HW rejects rules with decap & drop
9290                  */
9291                 bool add_decap = true;
9292                 const struct rte_flow_action *ptr = actions;
9293                 struct mlx5_flow_tbl_resource *tbl;
9294
9295                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9296                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9297                                 add_decap = false;
9298                                 break;
9299                         }
9300                 }
9301                 if (add_decap) {
9302                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9303                                                            attr->transfer,
9304                                                            error))
9305                                 return -rte_errno;
9306                         dev_flow->dv.actions[actions_n++] =
9307                                         dev_flow->dv.encap_decap->action;
9308                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9309                 }
9310                 /*
9311                  * bind table_id with <group, table> for tunnel match rule.
9312                  * Tunnel set rule establishes that bind in JUMP action handler.
9313                  * Required for scenario when application creates tunnel match
9314                  * rule before tunnel set rule.
9315                  */
9316                 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9317                                                attr->transfer,
9318                                                !!dev_flow->external, tunnel,
9319                                                attr->group, error);
9320                 if (!tbl)
9321                         return rte_flow_error_set
9322                                (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
9323                                actions, "cannot register tunnel group");
9324         }
9325         for (; !actions_end ; actions++) {
9326                 const struct rte_flow_action_queue *queue;
9327                 const struct rte_flow_action_rss *rss;
9328                 const struct rte_flow_action *action = actions;
9329                 const uint8_t *rss_key;
9330                 const struct rte_flow_action_meter *mtr;
9331                 struct mlx5_flow_tbl_resource *tbl;
9332                 uint32_t port_id = 0;
9333                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9334                 int action_type = actions->type;
9335                 const struct rte_flow_action *found_action = NULL;
9336                 struct mlx5_flow_meter *fm = NULL;
9337                 uint32_t jump_group = 0;
9338
9339                 if (!mlx5_flow_os_action_supported(action_type))
9340                         return rte_flow_error_set(error, ENOTSUP,
9341                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9342                                                   actions,
9343                                                   "action not supported");
9344                 switch (action_type) {
9345                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9346                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9347                         break;
9348                 case RTE_FLOW_ACTION_TYPE_VOID:
9349                         break;
9350                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9351                         if (flow_dv_translate_action_port_id(dev, action,
9352                                                              &port_id, error))
9353                                 return -rte_errno;
9354                         port_id_resource.port_id = port_id;
9355                         MLX5_ASSERT(!handle->rix_port_id_action);
9356                         if (flow_dv_port_id_action_resource_register
9357                             (dev, &port_id_resource, dev_flow, error))
9358                                 return -rte_errno;
9359                         dev_flow->dv.actions[actions_n++] =
9360                                         dev_flow->dv.port_id_action->action;
9361                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9362                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9363                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9364                         num_of_dest++;
9365                         break;
9366                 case RTE_FLOW_ACTION_TYPE_FLAG:
9367                         action_flags |= MLX5_FLOW_ACTION_FLAG;
9368                         dev_flow->handle->mark = 1;
9369                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9370                                 struct rte_flow_action_mark mark = {
9371                                         .id = MLX5_FLOW_MARK_DEFAULT,
9372                                 };
9373
9374                                 if (flow_dv_convert_action_mark(dev, &mark,
9375                                                                 mhdr_res,
9376                                                                 error))
9377                                         return -rte_errno;
9378                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9379                                 break;
9380                         }
9381                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9382                         /*
9383                          * Only one FLAG or MARK is supported per device flow
9384                          * right now. So the pointer to the tag resource must be
9385                          * zero before the register process.
9386                          */
9387                         MLX5_ASSERT(!handle->dvh.rix_tag);
9388                         if (flow_dv_tag_resource_register(dev, tag_be,
9389                                                           dev_flow, error))
9390                                 return -rte_errno;
9391                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9392                         dev_flow->dv.actions[actions_n++] =
9393                                         dev_flow->dv.tag_resource->action;
9394                         break;
9395                 case RTE_FLOW_ACTION_TYPE_MARK:
9396                         action_flags |= MLX5_FLOW_ACTION_MARK;
9397                         dev_flow->handle->mark = 1;
9398                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9399                                 const struct rte_flow_action_mark *mark =
9400                                         (const struct rte_flow_action_mark *)
9401                                                 actions->conf;
9402
9403                                 if (flow_dv_convert_action_mark(dev, mark,
9404                                                                 mhdr_res,
9405                                                                 error))
9406                                         return -rte_errno;
9407                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9408                                 break;
9409                         }
9410                         /* Fall-through */
9411                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9412                         /* Legacy (non-extensive) MARK action. */
9413                         tag_be = mlx5_flow_mark_set
9414                               (((const struct rte_flow_action_mark *)
9415                                (actions->conf))->id);
9416                         MLX5_ASSERT(!handle->dvh.rix_tag);
9417                         if (flow_dv_tag_resource_register(dev, tag_be,
9418                                                           dev_flow, error))
9419                                 return -rte_errno;
9420                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9421                         dev_flow->dv.actions[actions_n++] =
9422                                         dev_flow->dv.tag_resource->action;
9423                         break;
9424                 case RTE_FLOW_ACTION_TYPE_SET_META:
9425                         if (flow_dv_convert_action_set_meta
9426                                 (dev, mhdr_res, attr,
9427                                  (const struct rte_flow_action_set_meta *)
9428                                   actions->conf, error))
9429                                 return -rte_errno;
9430                         action_flags |= MLX5_FLOW_ACTION_SET_META;
9431                         break;
9432                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9433                         if (flow_dv_convert_action_set_tag
9434                                 (dev, mhdr_res,
9435                                  (const struct rte_flow_action_set_tag *)
9436                                   actions->conf, error))
9437                                 return -rte_errno;
9438                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9439                         break;
9440                 case RTE_FLOW_ACTION_TYPE_DROP:
9441                         action_flags |= MLX5_FLOW_ACTION_DROP;
9442                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9443                         break;
9444                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9445                         queue = actions->conf;
9446                         rss_desc->queue_num = 1;
9447                         rss_desc->queue[0] = queue->index;
9448                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9449                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9450                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9451                         num_of_dest++;
9452                         break;
9453                 case RTE_FLOW_ACTION_TYPE_RSS:
9454                         rss = actions->conf;
9455                         memcpy(rss_desc->queue, rss->queue,
9456                                rss->queue_num * sizeof(uint16_t));
9457                         rss_desc->queue_num = rss->queue_num;
9458                         /* NULL RSS key indicates default RSS key. */
9459                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9460                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9461                         /*
9462                          * rss->level and rss.types should be set in advance
9463                          * when expanding items for RSS.
9464                          */
9465                         action_flags |= MLX5_FLOW_ACTION_RSS;
9466                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9467                         break;
9468                 case RTE_FLOW_ACTION_TYPE_AGE:
9469                 case RTE_FLOW_ACTION_TYPE_COUNT:
9470                         if (!dev_conf->devx) {
9471                                 return rte_flow_error_set
9472                                               (error, ENOTSUP,
9473                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9474                                                NULL,
9475                                                "count action not supported");
9476                         }
9477                         /* Save information first, will apply later. */
9478                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9479                                 count = action->conf;
9480                         else
9481                                 age = action->conf;
9482                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9483                         break;
9484                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9485                         dev_flow->dv.actions[actions_n++] =
9486                                                 priv->sh->pop_vlan_action;
9487                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9488                         break;
9489                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9490                         if (!(action_flags &
9491                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9492                                 flow_dev_get_vlan_info_from_items(items, &vlan);
9493                         vlan.eth_proto = rte_be_to_cpu_16
9494                              ((((const struct rte_flow_action_of_push_vlan *)
9495                                                    actions->conf)->ethertype));
9496                         found_action = mlx5_flow_find_action
9497                                         (actions + 1,
9498                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9499                         if (found_action)
9500                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9501                         found_action = mlx5_flow_find_action
9502                                         (actions + 1,
9503                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9504                         if (found_action)
9505                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9506                         if (flow_dv_create_action_push_vlan
9507                                             (dev, attr, &vlan, dev_flow, error))
9508                                 return -rte_errno;
9509                         dev_flow->dv.actions[actions_n++] =
9510                                         dev_flow->dv.push_vlan_res->action;
9511                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9512                         break;
9513                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9514                         /* of_vlan_push action handled this action */
9515                         MLX5_ASSERT(action_flags &
9516                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9517                         break;
9518                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9519                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9520                                 break;
9521                         flow_dev_get_vlan_info_from_items(items, &vlan);
9522                         mlx5_update_vlan_vid_pcp(actions, &vlan);
9523                         /* If no VLAN push - this is a modify header action */
9524                         if (flow_dv_convert_action_modify_vlan_vid
9525                                                 (mhdr_res, actions, error))
9526                                 return -rte_errno;
9527                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
9528                         break;
9529                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
9530                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
9531                         if (flow_dv_create_action_l2_encap(dev, actions,
9532                                                            dev_flow,
9533                                                            attr->transfer,
9534                                                            error))
9535                                 return -rte_errno;
9536                         dev_flow->dv.actions[actions_n++] =
9537                                         dev_flow->dv.encap_decap->action;
9538                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9539                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9540                                 sample_act->action_flags |=
9541                                                         MLX5_FLOW_ACTION_ENCAP;
9542                         break;
9543                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
9544                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
9545                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9546                                                            attr->transfer,
9547                                                            error))
9548                                 return -rte_errno;
9549                         dev_flow->dv.actions[actions_n++] =
9550                                         dev_flow->dv.encap_decap->action;
9551                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9552                         break;
9553                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9554                         /* Handle encap with preceding decap. */
9555                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
9556                                 if (flow_dv_create_action_raw_encap
9557                                         (dev, actions, dev_flow, attr, error))
9558                                         return -rte_errno;
9559                                 dev_flow->dv.actions[actions_n++] =
9560                                         dev_flow->dv.encap_decap->action;
9561                         } else {
9562                                 /* Handle encap without preceding decap. */
9563                                 if (flow_dv_create_action_l2_encap
9564                                     (dev, actions, dev_flow, attr->transfer,
9565                                      error))
9566                                         return -rte_errno;
9567                                 dev_flow->dv.actions[actions_n++] =
9568                                         dev_flow->dv.encap_decap->action;
9569                         }
9570                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9571                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9572                                 sample_act->action_flags |=
9573                                                         MLX5_FLOW_ACTION_ENCAP;
9574                         break;
9575                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
9576                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
9577                                 ;
9578                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
9579                                 if (flow_dv_create_action_l2_decap
9580                                     (dev, dev_flow, attr->transfer, error))
9581                                         return -rte_errno;
9582                                 dev_flow->dv.actions[actions_n++] =
9583                                         dev_flow->dv.encap_decap->action;
9584                         }
9585                         /* If decap is followed by encap, handle it at encap. */
9586                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9587                         break;
9588                 case RTE_FLOW_ACTION_TYPE_JUMP:
9589                         jump_group = ((const struct rte_flow_action_jump *)
9590                                                         action->conf)->group;
9591                         grp_info.std_tbl_fix = 0;
9592                         ret = mlx5_flow_group_to_table(dev, tunnel,
9593                                                        jump_group,
9594                                                        &table,
9595                                                        grp_info, error);
9596                         if (ret)
9597                                 return ret;
9598                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9599                                                        attr->transfer,
9600                                                        !!dev_flow->external,
9601                                                        tunnel, jump_group,
9602                                                        error);
9603                         if (!tbl)
9604                                 return rte_flow_error_set
9605                                                 (error, errno,
9606                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9607                                                  NULL,
9608                                                  "cannot create jump action.");
9609                         if (flow_dv_jump_tbl_resource_register
9610                             (dev, tbl, dev_flow, error)) {
9611                                 flow_dv_tbl_resource_release(dev, tbl);
9612                                 return rte_flow_error_set
9613                                                 (error, errno,
9614                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9615                                                  NULL,
9616                                                  "cannot create jump action.");
9617                         }
9618                         dev_flow->dv.actions[actions_n++] =
9619                                         dev_flow->dv.jump->action;
9620                         action_flags |= MLX5_FLOW_ACTION_JUMP;
9621                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
9622                         break;
9623                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
9624                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
9625                         if (flow_dv_convert_action_modify_mac
9626                                         (mhdr_res, actions, error))
9627                                 return -rte_errno;
9628                         action_flags |= actions->type ==
9629                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
9630                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
9631                                         MLX5_FLOW_ACTION_SET_MAC_DST;
9632                         break;
9633                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
9634                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
9635                         if (flow_dv_convert_action_modify_ipv4
9636                                         (mhdr_res, actions, error))
9637                                 return -rte_errno;
9638                         action_flags |= actions->type ==
9639                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
9640                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
9641                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
9642                         break;
9643                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
9644                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
9645                         if (flow_dv_convert_action_modify_ipv6
9646                                         (mhdr_res, actions, error))
9647                                 return -rte_errno;
9648                         action_flags |= actions->type ==
9649                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
9650                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
9651                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
9652                         break;
9653                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
9654                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
9655                         if (flow_dv_convert_action_modify_tp
9656                                         (mhdr_res, actions, items,
9657                                          &flow_attr, dev_flow, !!(action_flags &
9658                                          MLX5_FLOW_ACTION_DECAP), error))
9659                                 return -rte_errno;
9660                         action_flags |= actions->type ==
9661                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
9662                                         MLX5_FLOW_ACTION_SET_TP_SRC :
9663                                         MLX5_FLOW_ACTION_SET_TP_DST;
9664                         break;
9665                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
9666                         if (flow_dv_convert_action_modify_dec_ttl
9667                                         (mhdr_res, items, &flow_attr, dev_flow,
9668                                          !!(action_flags &
9669                                          MLX5_FLOW_ACTION_DECAP), error))
9670                                 return -rte_errno;
9671                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
9672                         break;
9673                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
9674                         if (flow_dv_convert_action_modify_ttl
9675                                         (mhdr_res, actions, items, &flow_attr,
9676                                          dev_flow, !!(action_flags &
9677                                          MLX5_FLOW_ACTION_DECAP), error))
9678                                 return -rte_errno;
9679                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
9680                         break;
9681                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
9682                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
9683                         if (flow_dv_convert_action_modify_tcp_seq
9684                                         (mhdr_res, actions, error))
9685                                 return -rte_errno;
9686                         action_flags |= actions->type ==
9687                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
9688                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
9689                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
9690                         break;
9691
9692                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
9693                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
9694                         if (flow_dv_convert_action_modify_tcp_ack
9695                                         (mhdr_res, actions, error))
9696                                 return -rte_errno;
9697                         action_flags |= actions->type ==
9698                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
9699                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
9700                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
9701                         break;
9702                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
9703                         if (flow_dv_convert_action_set_reg
9704                                         (mhdr_res, actions, error))
9705                                 return -rte_errno;
9706                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9707                         break;
9708                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
9709                         if (flow_dv_convert_action_copy_mreg
9710                                         (dev, mhdr_res, actions, error))
9711                                 return -rte_errno;
9712                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9713                         break;
9714                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
9715                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
9716                         dev_flow->handle->fate_action =
9717                                         MLX5_FLOW_FATE_DEFAULT_MISS;
9718                         break;
9719                 case RTE_FLOW_ACTION_TYPE_METER:
9720                         mtr = actions->conf;
9721                         if (!flow->meter) {
9722                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
9723                                                             attr, error);
9724                                 if (!fm)
9725                                         return rte_flow_error_set(error,
9726                                                 rte_errno,
9727                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9728                                                 NULL,
9729                                                 "meter not found "
9730                                                 "or invalid parameters");
9731                                 flow->meter = fm->idx;
9732                         }
9733                         /* Set the meter action. */
9734                         if (!fm) {
9735                                 fm = mlx5_ipool_get(priv->sh->ipool
9736                                                 [MLX5_IPOOL_MTR], flow->meter);
9737                                 if (!fm)
9738                                         return rte_flow_error_set(error,
9739                                                 rte_errno,
9740                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9741                                                 NULL,
9742                                                 "meter not found "
9743                                                 "or invalid parameters");
9744                         }
9745                         dev_flow->dv.actions[actions_n++] =
9746                                 fm->mfts->meter_action;
9747                         action_flags |= MLX5_FLOW_ACTION_METER;
9748                         break;
9749                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
9750                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
9751                                                               actions, error))
9752                                 return -rte_errno;
9753                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
9754                         break;
9755                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
9756                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
9757                                                               actions, error))
9758                                 return -rte_errno;
9759                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
9760                         break;
9761                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
9762                         sample_act_pos = actions_n;
9763                         ret = flow_dv_translate_action_sample(dev,
9764                                                               actions,
9765                                                               dev_flow, attr,
9766                                                               &num_of_dest,
9767                                                               sample_actions,
9768                                                               &sample_res,
9769                                                               error);
9770                         if (ret < 0)
9771                                 return ret;
9772                         actions_n++;
9773                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
9774                         /* put encap action into group if work with port id */
9775                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
9776                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
9777                                 sample_act->action_flags |=
9778                                                         MLX5_FLOW_ACTION_ENCAP;
9779                         break;
9780                 case RTE_FLOW_ACTION_TYPE_END:
9781                         actions_end = true;
9782                         if (mhdr_res->actions_num) {
9783                                 /* create modify action if needed. */
9784                                 if (flow_dv_modify_hdr_resource_register
9785                                         (dev, mhdr_res, dev_flow, error))
9786                                         return -rte_errno;
9787                                 dev_flow->dv.actions[modify_action_position] =
9788                                         handle->dvh.modify_hdr->action;
9789                         }
9790                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
9791                                 flow->counter =
9792                                         flow_dv_translate_create_counter(dev,
9793                                                 dev_flow, count, age);
9794
9795                                 if (!flow->counter)
9796                                         return rte_flow_error_set
9797                                                 (error, rte_errno,
9798                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9799                                                 NULL,
9800                                                 "cannot create counter"
9801                                                 " object.");
9802                                 dev_flow->dv.actions[actions_n] =
9803                                           (flow_dv_counter_get_by_idx(dev,
9804                                           flow->counter, NULL))->action;
9805                                 actions_n++;
9806                         }
9807                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
9808                                 ret = flow_dv_create_action_sample(dev,
9809                                                           dev_flow, attr,
9810                                                           num_of_dest,
9811                                                           &sample_res,
9812                                                           &mdest_res,
9813                                                           sample_actions,
9814                                                           action_flags,
9815                                                           error);
9816                                 if (ret < 0)
9817                                         return rte_flow_error_set
9818                                                 (error, rte_errno,
9819                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9820                                                 NULL,
9821                                                 "cannot create sample action");
9822                                 if (num_of_dest > 1) {
9823                                         dev_flow->dv.actions[sample_act_pos] =
9824                                         dev_flow->dv.dest_array_res->action;
9825                                 } else {
9826                                         dev_flow->dv.actions[sample_act_pos] =
9827                                         dev_flow->dv.sample_res->verbs_action;
9828                                 }
9829                         }
9830                         break;
9831                 default:
9832                         break;
9833                 }
9834                 if (mhdr_res->actions_num &&
9835                     modify_action_position == UINT32_MAX)
9836                         modify_action_position = actions_n++;
9837         }
9838         /*
9839          * For multiple destination (sample action with ratio=1), the encap
9840          * action and port id action will be combined into group action.
9841          * So need remove the original these actions in the flow and only
9842          * use the sample action instead of.
9843          */
9844         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
9845                 int i;
9846                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9847
9848                 for (i = 0; i < actions_n; i++) {
9849                         if ((sample_act->dr_encap_action &&
9850                                 sample_act->dr_encap_action ==
9851                                 dev_flow->dv.actions[i]) ||
9852                                 (sample_act->dr_port_id_action &&
9853                                 sample_act->dr_port_id_action ==
9854                                 dev_flow->dv.actions[i]))
9855                                 continue;
9856                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
9857                 }
9858                 memcpy((void *)dev_flow->dv.actions,
9859                                 (void *)temp_actions,
9860                                 tmp_actions_n * sizeof(void *));
9861                 actions_n = tmp_actions_n;
9862         }
9863         dev_flow->dv.actions_n = actions_n;
9864         dev_flow->act_flags = action_flags;
9865         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
9866                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
9867                 int item_type = items->type;
9868
9869                 if (!mlx5_flow_os_item_supported(item_type))
9870                         return rte_flow_error_set(error, ENOTSUP,
9871                                                   RTE_FLOW_ERROR_TYPE_ITEM,
9872                                                   NULL, "item not supported");
9873                 switch (item_type) {
9874                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
9875                         flow_dv_translate_item_port_id(dev, match_mask,
9876                                                        match_value, items);
9877                         last_item = MLX5_FLOW_ITEM_PORT_ID;
9878                         break;
9879                 case RTE_FLOW_ITEM_TYPE_ETH:
9880                         flow_dv_translate_item_eth(match_mask, match_value,
9881                                                    items, tunnel,
9882                                                    dev_flow->dv.group);
9883                         matcher.priority = action_flags &
9884                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
9885                                         !dev_flow->external ?
9886                                         MLX5_PRIORITY_MAP_L3 :
9887                                         MLX5_PRIORITY_MAP_L2;
9888                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
9889                                              MLX5_FLOW_LAYER_OUTER_L2;
9890                         break;
9891                 case RTE_FLOW_ITEM_TYPE_VLAN:
9892                         flow_dv_translate_item_vlan(dev_flow,
9893                                                     match_mask, match_value,
9894                                                     items, tunnel,
9895                                                     dev_flow->dv.group);
9896                         matcher.priority = MLX5_PRIORITY_MAP_L2;
9897                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
9898                                               MLX5_FLOW_LAYER_INNER_VLAN) :
9899                                              (MLX5_FLOW_LAYER_OUTER_L2 |
9900                                               MLX5_FLOW_LAYER_OUTER_VLAN);
9901                         break;
9902                 case RTE_FLOW_ITEM_TYPE_IPV4:
9903                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9904                                                   &item_flags, &tunnel);
9905                         flow_dv_translate_item_ipv4(match_mask, match_value,
9906                                                     items, tunnel,
9907                                                     dev_flow->dv.group);
9908                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9909                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
9910                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
9911                         if (items->mask != NULL &&
9912                             ((const struct rte_flow_item_ipv4 *)
9913                              items->mask)->hdr.next_proto_id) {
9914                                 next_protocol =
9915                                         ((const struct rte_flow_item_ipv4 *)
9916                                          (items->spec))->hdr.next_proto_id;
9917                                 next_protocol &=
9918                                         ((const struct rte_flow_item_ipv4 *)
9919                                          (items->mask))->hdr.next_proto_id;
9920                         } else {
9921                                 /* Reset for inner layer. */
9922                                 next_protocol = 0xff;
9923                         }
9924                         break;
9925                 case RTE_FLOW_ITEM_TYPE_IPV6:
9926                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9927                                                   &item_flags, &tunnel);
9928                         flow_dv_translate_item_ipv6(match_mask, match_value,
9929                                                     items, tunnel,
9930                                                     dev_flow->dv.group);
9931                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9932                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
9933                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
9934                         if (items->mask != NULL &&
9935                             ((const struct rte_flow_item_ipv6 *)
9936                              items->mask)->hdr.proto) {
9937                                 next_protocol =
9938                                         ((const struct rte_flow_item_ipv6 *)
9939                                          items->spec)->hdr.proto;
9940                                 next_protocol &=
9941                                         ((const struct rte_flow_item_ipv6 *)
9942                                          items->mask)->hdr.proto;
9943                         } else {
9944                                 /* Reset for inner layer. */
9945                                 next_protocol = 0xff;
9946                         }
9947                         break;
9948                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
9949                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
9950                                                              match_value,
9951                                                              items, tunnel);
9952                         last_item = tunnel ?
9953                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
9954                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
9955                         if (items->mask != NULL &&
9956                             ((const struct rte_flow_item_ipv6_frag_ext *)
9957                              items->mask)->hdr.next_header) {
9958                                 next_protocol =
9959                                 ((const struct rte_flow_item_ipv6_frag_ext *)
9960                                  items->spec)->hdr.next_header;
9961                                 next_protocol &=
9962                                 ((const struct rte_flow_item_ipv6_frag_ext *)
9963                                  items->mask)->hdr.next_header;
9964                         } else {
9965                                 /* Reset for inner layer. */
9966                                 next_protocol = 0xff;
9967                         }
9968                         break;
9969                 case RTE_FLOW_ITEM_TYPE_TCP:
9970                         flow_dv_translate_item_tcp(match_mask, match_value,
9971                                                    items, tunnel);
9972                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9973                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
9974                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
9975                         break;
9976                 case RTE_FLOW_ITEM_TYPE_UDP:
9977                         flow_dv_translate_item_udp(match_mask, match_value,
9978                                                    items, tunnel);
9979                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9980                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
9981                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
9982                         break;
9983                 case RTE_FLOW_ITEM_TYPE_GRE:
9984                         flow_dv_translate_item_gre(match_mask, match_value,
9985                                                    items, tunnel);
9986                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9987                         last_item = MLX5_FLOW_LAYER_GRE;
9988                         break;
9989                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
9990                         flow_dv_translate_item_gre_key(match_mask,
9991                                                        match_value, items);
9992                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
9993                         break;
9994                 case RTE_FLOW_ITEM_TYPE_NVGRE:
9995                         flow_dv_translate_item_nvgre(match_mask, match_value,
9996                                                      items, tunnel);
9997                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9998                         last_item = MLX5_FLOW_LAYER_GRE;
9999                         break;
10000                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10001                         flow_dv_translate_item_vxlan(match_mask, match_value,
10002                                                      items, tunnel);
10003                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10004                         last_item = MLX5_FLOW_LAYER_VXLAN;
10005                         break;
10006                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10007                         flow_dv_translate_item_vxlan_gpe(match_mask,
10008                                                          match_value, items,
10009                                                          tunnel);
10010                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10011                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10012                         break;
10013                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10014                         flow_dv_translate_item_geneve(match_mask, match_value,
10015                                                       items, tunnel);
10016                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10017                         last_item = MLX5_FLOW_LAYER_GENEVE;
10018                         break;
10019                 case RTE_FLOW_ITEM_TYPE_MPLS:
10020                         flow_dv_translate_item_mpls(match_mask, match_value,
10021                                                     items, last_item, tunnel);
10022                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10023                         last_item = MLX5_FLOW_LAYER_MPLS;
10024                         break;
10025                 case RTE_FLOW_ITEM_TYPE_MARK:
10026                         flow_dv_translate_item_mark(dev, match_mask,
10027                                                     match_value, items);
10028                         last_item = MLX5_FLOW_ITEM_MARK;
10029                         break;
10030                 case RTE_FLOW_ITEM_TYPE_META:
10031                         flow_dv_translate_item_meta(dev, match_mask,
10032                                                     match_value, attr, items);
10033                         last_item = MLX5_FLOW_ITEM_METADATA;
10034                         break;
10035                 case RTE_FLOW_ITEM_TYPE_ICMP:
10036                         flow_dv_translate_item_icmp(match_mask, match_value,
10037                                                     items, tunnel);
10038                         last_item = MLX5_FLOW_LAYER_ICMP;
10039                         break;
10040                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10041                         flow_dv_translate_item_icmp6(match_mask, match_value,
10042                                                       items, tunnel);
10043                         last_item = MLX5_FLOW_LAYER_ICMP6;
10044                         break;
10045                 case RTE_FLOW_ITEM_TYPE_TAG:
10046                         flow_dv_translate_item_tag(dev, match_mask,
10047                                                    match_value, items);
10048                         last_item = MLX5_FLOW_ITEM_TAG;
10049                         break;
10050                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10051                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10052                                                         match_value, items);
10053                         last_item = MLX5_FLOW_ITEM_TAG;
10054                         break;
10055                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10056                         flow_dv_translate_item_tx_queue(dev, match_mask,
10057                                                         match_value,
10058                                                         items);
10059                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10060                         break;
10061                 case RTE_FLOW_ITEM_TYPE_GTP:
10062                         flow_dv_translate_item_gtp(match_mask, match_value,
10063                                                    items, tunnel);
10064                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10065                         last_item = MLX5_FLOW_LAYER_GTP;
10066                         break;
10067                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10068                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10069                                 /* Create it only the first time to be used. */
10070                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10071                                 if (ret)
10072                                         return rte_flow_error_set
10073                                                 (error, -ret,
10074                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10075                                                 NULL,
10076                                                 "cannot create eCPRI parser");
10077                         }
10078                         /* Adjust the length matcher and device flow value. */
10079                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10080                         dev_flow->dv.value.size =
10081                                         MLX5_ST_SZ_BYTES(fte_match_param);
10082                         flow_dv_translate_item_ecpri(dev, match_mask,
10083                                                      match_value, items);
10084                         /* No other protocol should follow eCPRI layer. */
10085                         last_item = MLX5_FLOW_LAYER_ECPRI;
10086                         break;
10087                 default:
10088                         break;
10089                 }
10090                 item_flags |= last_item;
10091         }
10092         /*
10093          * When E-Switch mode is enabled, we have two cases where we need to
10094          * set the source port manually.
10095          * The first one, is in case of Nic steering rule, and the second is
10096          * E-Switch rule where no port_id item was found. In both cases
10097          * the source port is set according the current port in use.
10098          */
10099         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10100             (priv->representor || priv->master)) {
10101                 if (flow_dv_translate_item_port_id(dev, match_mask,
10102                                                    match_value, NULL))
10103                         return -rte_errno;
10104         }
10105 #ifdef RTE_LIBRTE_MLX5_DEBUG
10106         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10107                                               dev_flow->dv.value.buf));
10108 #endif
10109         /*
10110          * Layers may be already initialized from prefix flow if this dev_flow
10111          * is the suffix flow.
10112          */
10113         handle->layers |= item_flags;
10114         if (action_flags & MLX5_FLOW_ACTION_RSS)
10115                 flow_dv_hashfields_set(dev_flow, rss_desc);
10116         /* Register matcher. */
10117         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10118                                     matcher.mask.size);
10119         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
10120                                                      matcher.priority);
10121         /* reserved field no needs to be set to 0 here. */
10122         tbl_key.domain = attr->transfer;
10123         tbl_key.direction = attr->egress;
10124         tbl_key.table_id = dev_flow->dv.group;
10125         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
10126                 return -rte_errno;
10127         return 0;
10128 }
10129
10130 /**
10131  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10132  * and tunnel.
10133  *
10134  * @param[in, out] action
10135  *   Shred RSS action holding hash RX queue objects.
10136  * @param[in] hash_fields
10137  *   Defines combination of packet fields to participate in RX hash.
10138  * @param[in] tunnel
10139  *   Tunnel type
10140  * @param[in] hrxq_idx
10141  *   Hash RX queue index to set.
10142  *
10143  * @return
10144  *   0 on success, otherwise negative errno value.
10145  */
10146 static int
10147 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10148                               const uint64_t hash_fields,
10149                               const int tunnel,
10150                               uint32_t hrxq_idx)
10151 {
10152         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10153
10154         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10155         case MLX5_RSS_HASH_IPV4:
10156                 hrxqs[0] = hrxq_idx;
10157                 return 0;
10158         case MLX5_RSS_HASH_IPV4_TCP:
10159                 hrxqs[1] = hrxq_idx;
10160                 return 0;
10161         case MLX5_RSS_HASH_IPV4_UDP:
10162                 hrxqs[2] = hrxq_idx;
10163                 return 0;
10164         case MLX5_RSS_HASH_IPV6:
10165                 hrxqs[3] = hrxq_idx;
10166                 return 0;
10167         case MLX5_RSS_HASH_IPV6_TCP:
10168                 hrxqs[4] = hrxq_idx;
10169                 return 0;
10170         case MLX5_RSS_HASH_IPV6_UDP:
10171                 hrxqs[5] = hrxq_idx;
10172                 return 0;
10173         case MLX5_RSS_HASH_NONE:
10174                 hrxqs[6] = hrxq_idx;
10175                 return 0;
10176         default:
10177                 return -1;
10178         }
10179 }
10180
10181 /**
10182  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10183  * and tunnel.
10184  *
10185  * @param[in] action
10186  *   Shred RSS action holding hash RX queue objects.
10187  * @param[in] hash_fields
10188  *   Defines combination of packet fields to participate in RX hash.
10189  * @param[in] tunnel
10190  *   Tunnel type
10191  *
10192  * @return
10193  *   Valid hash RX queue index, otherwise 0.
10194  */
10195 static uint32_t
10196 __flow_dv_action_rss_hrxq_lookup(const struct mlx5_shared_action_rss *action,
10197                                  const uint64_t hash_fields,
10198                                  const int tunnel)
10199 {
10200         const uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10201
10202         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10203         case MLX5_RSS_HASH_IPV4:
10204                 return hrxqs[0];
10205         case MLX5_RSS_HASH_IPV4_TCP:
10206                 return hrxqs[1];
10207         case MLX5_RSS_HASH_IPV4_UDP:
10208                 return hrxqs[2];
10209         case MLX5_RSS_HASH_IPV6:
10210                 return hrxqs[3];
10211         case MLX5_RSS_HASH_IPV6_TCP:
10212                 return hrxqs[4];
10213         case MLX5_RSS_HASH_IPV6_UDP:
10214                 return hrxqs[5];
10215         case MLX5_RSS_HASH_NONE:
10216                 return hrxqs[6];
10217         default:
10218                 return 0;
10219         }
10220 }
10221
10222 /**
10223  * Retrieves hash RX queue suitable for the *flow*.
10224  * If shared action configured for *flow* suitable hash RX queue will be
10225  * retrieved from attached shared action.
10226  *
10227  * @param[in] flow
10228  *   Shred RSS action holding hash RX queue objects.
10229  * @param[in] dev_flow
10230  *   Pointer to the sub flow.
10231  * @param[out] hrxq
10232  *   Pointer to retrieved hash RX queue object.
10233  *
10234  * @return
10235  *   Valid hash RX queue index, otherwise 0 and rte_errno is set.
10236  */
10237 static uint32_t
10238 __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct rte_flow *flow,
10239                            struct mlx5_flow *dev_flow,
10240                            struct mlx5_hrxq **hrxq)
10241 {
10242         struct mlx5_priv *priv = dev->data->dev_private;
10243         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10244         uint32_t hrxq_idx;
10245
10246         if (flow->shared_rss) {
10247                 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
10248                                 (flow->shared_rss, dev_flow->hash_fields,
10249                                  !!(dev_flow->handle->layers &
10250                                     MLX5_FLOW_LAYER_TUNNEL));
10251                 if (hrxq_idx) {
10252                         *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10253                                                hrxq_idx);
10254                         __atomic_fetch_add(&(*hrxq)->refcnt, 1,
10255                                            __ATOMIC_RELAXED);
10256                 }
10257         } else {
10258                 struct mlx5_flow_rss_desc *rss_desc =
10259                                 &wks->rss_desc[!!wks->flow_nested_idx];
10260
10261                 MLX5_ASSERT(rss_desc->queue_num);
10262                 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
10263                                          MLX5_RSS_HASH_KEY_LEN,
10264                                          dev_flow->hash_fields,
10265                                          rss_desc->queue, rss_desc->queue_num);
10266                 if (!hrxq_idx) {
10267                         hrxq_idx = mlx5_hrxq_new(dev,
10268                                                  rss_desc->key,
10269                                                  MLX5_RSS_HASH_KEY_LEN,
10270                                                  dev_flow->hash_fields,
10271                                                  rss_desc->queue,
10272                                                  rss_desc->queue_num,
10273                                                  !!(dev_flow->handle->layers &
10274                                                  MLX5_FLOW_LAYER_TUNNEL),
10275                                                  false);
10276                 }
10277                 *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10278                                        hrxq_idx);
10279         }
10280         return hrxq_idx;
10281 }
10282
10283 /**
10284  * Apply the flow to the NIC, lock free,
10285  * (mutex should be acquired by caller).
10286  *
10287  * @param[in] dev
10288  *   Pointer to the Ethernet device structure.
10289  * @param[in, out] flow
10290  *   Pointer to flow structure.
10291  * @param[out] error
10292  *   Pointer to error structure.
10293  *
10294  * @return
10295  *   0 on success, a negative errno value otherwise and rte_errno is set.
10296  */
10297 static int
10298 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10299                 struct rte_flow_error *error)
10300 {
10301         struct mlx5_flow_dv_workspace *dv;
10302         struct mlx5_flow_handle *dh;
10303         struct mlx5_flow_handle_dv *dv_h;
10304         struct mlx5_flow *dev_flow;
10305         struct mlx5_priv *priv = dev->data->dev_private;
10306         uint32_t handle_idx;
10307         int n;
10308         int err;
10309         int idx;
10310         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10311
10312         MLX5_ASSERT(wks);
10313         for (idx = wks->flow_idx - 1; idx >= wks->flow_nested_idx; idx--) {
10314                 dev_flow = &wks->flows[idx];
10315                 dv = &dev_flow->dv;
10316                 dh = dev_flow->handle;
10317                 dv_h = &dh->dvh;
10318                 n = dv->actions_n;
10319                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10320                         if (dv->transfer) {
10321                                 dv->actions[n++] = priv->sh->esw_drop_action;
10322                         } else {
10323                                 MLX5_ASSERT(priv->drop_queue.hrxq);
10324                                 dv->actions[n++] =
10325                                                 priv->drop_queue.hrxq->action;
10326                         }
10327                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10328                            !dv_h->rix_sample && !dv_h->rix_dest_array) {
10329                         struct mlx5_hrxq *hrxq = NULL;
10330                         uint32_t hrxq_idx = __flow_dv_rss_get_hrxq
10331                                                 (dev, flow, dev_flow, &hrxq);
10332
10333                         if (!hrxq) {
10334                                 rte_flow_error_set
10335                                         (error, rte_errno,
10336                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10337                                          "cannot get hash queue");
10338                                 goto error;
10339                         }
10340                         dh->rix_hrxq = hrxq_idx;
10341                         dv->actions[n++] = hrxq->action;
10342                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10343                         if (!priv->sh->default_miss_action) {
10344                                 rte_flow_error_set
10345                                         (error, rte_errno,
10346                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10347                                          "default miss action not be created.");
10348                                 goto error;
10349                         }
10350                         dv->actions[n++] = priv->sh->default_miss_action;
10351                 }
10352                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10353                                                (void *)&dv->value, n,
10354                                                dv->actions, &dh->drv_flow);
10355                 if (err) {
10356                         rte_flow_error_set(error, errno,
10357                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10358                                            NULL,
10359                                            "hardware refuses to create flow");
10360                         goto error;
10361                 }
10362                 if (priv->vmwa_context &&
10363                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
10364                         /*
10365                          * The rule contains the VLAN pattern.
10366                          * For VF we are going to create VLAN
10367                          * interface to make hypervisor set correct
10368                          * e-Switch vport context.
10369                          */
10370                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10371                 }
10372         }
10373         return 0;
10374 error:
10375         err = rte_errno; /* Save rte_errno before cleanup. */
10376         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10377                        handle_idx, dh, next) {
10378                 /* hrxq is union, don't clear it if the flag is not set. */
10379                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
10380                         mlx5_hrxq_release(dev, dh->rix_hrxq);
10381                         dh->rix_hrxq = 0;
10382                 }
10383                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10384                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10385         }
10386         rte_errno = err; /* Restore rte_errno. */
10387         return -rte_errno;
10388 }
10389
10390 /**
10391  * Release the flow matcher.
10392  *
10393  * @param dev
10394  *   Pointer to Ethernet device.
10395  * @param handle
10396  *   Pointer to mlx5_flow_handle.
10397  *
10398  * @return
10399  *   1 while a reference on it exists, 0 when freed.
10400  */
10401 static int
10402 flow_dv_matcher_release(struct rte_eth_dev *dev,
10403                         struct mlx5_flow_handle *handle)
10404 {
10405         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10406
10407         MLX5_ASSERT(matcher->matcher_object);
10408         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
10409                 dev->data->port_id, (void *)matcher,
10410                 __atomic_load_n(&matcher->refcnt, __ATOMIC_RELAXED));
10411         if (__atomic_sub_fetch(&matcher->refcnt, 1, __ATOMIC_RELAXED) == 0) {
10412                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10413                            (matcher->matcher_object));
10414                 LIST_REMOVE(matcher, next);
10415                 /* table ref-- in release interface. */
10416                 flow_dv_tbl_resource_release(dev, matcher->tbl);
10417                 mlx5_free(matcher);
10418                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
10419                         dev->data->port_id, (void *)matcher);
10420                 return 0;
10421         }
10422         return 1;
10423 }
10424
10425 /**
10426  * Release an encap/decap resource.
10427  *
10428  * @param dev
10429  *   Pointer to Ethernet device.
10430  * @param encap_decap_idx
10431  *   Index of encap decap resource.
10432  *
10433  * @return
10434  *   1 while a reference on it exists, 0 when freed.
10435  */
10436 static int
10437 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10438                                      uint32_t encap_decap_idx)
10439 {
10440         struct mlx5_priv *priv = dev->data->dev_private;
10441         uint32_t idx = encap_decap_idx;
10442         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10443
10444         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10445                          idx);
10446         if (!cache_resource)
10447                 return 0;
10448         MLX5_ASSERT(cache_resource->action);
10449         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
10450                 (void *)cache_resource,
10451                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10452         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10453                                __ATOMIC_RELAXED) == 0) {
10454                 claim_zero(mlx5_flow_os_destroy_flow_action
10455                                                 (cache_resource->action));
10456                 mlx5_hlist_remove(priv->sh->encaps_decaps,
10457                                   &cache_resource->entry);
10458                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
10459                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
10460                         (void *)cache_resource);
10461                 return 0;
10462         }
10463         return 1;
10464 }
10465
10466 /**
10467  * Release an jump to table action resource.
10468  *
10469  * @param dev
10470  *   Pointer to Ethernet device.
10471  * @param handle
10472  *   Pointer to mlx5_flow_handle.
10473  *
10474  * @return
10475  *   1 while a reference on it exists, 0 when freed.
10476  */
10477 static int
10478 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10479                                   struct mlx5_flow_handle *handle)
10480 {
10481         struct mlx5_priv *priv = dev->data->dev_private;
10482         struct mlx5_flow_tbl_data_entry *tbl_data;
10483
10484         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10485                              handle->rix_jump);
10486         if (!tbl_data)
10487                 return 0;
10488         return flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
10489 }
10490
10491 /**
10492  * Release a modify-header resource.
10493  *
10494  * @param dev
10495  *   Pointer to Ethernet device.
10496  * @param handle
10497  *   Pointer to mlx5_flow_handle.
10498  *
10499  * @return
10500  *   1 while a reference on it exists, 0 when freed.
10501  */
10502 static int
10503 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10504                                     struct mlx5_flow_handle *handle)
10505 {
10506         struct mlx5_priv *priv = dev->data->dev_private;
10507         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
10508                                                         handle->dvh.modify_hdr;
10509
10510         MLX5_ASSERT(cache_resource->action);
10511         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
10512                 (void *)cache_resource,
10513                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10514         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10515                                 __ATOMIC_RELAXED) == 0) {
10516                 claim_zero(mlx5_flow_os_destroy_flow_action
10517                                                 (cache_resource->action));
10518                 mlx5_hlist_remove(priv->sh->modify_cmds,
10519                                   &cache_resource->entry);
10520                 mlx5_free(cache_resource);
10521                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
10522                         (void *)cache_resource);
10523                 return 0;
10524         }
10525         return 1;
10526 }
10527
10528 /**
10529  * Release port ID action resource.
10530  *
10531  * @param dev
10532  *   Pointer to Ethernet device.
10533  * @param handle
10534  *   Pointer to mlx5_flow_handle.
10535  *
10536  * @return
10537  *   1 while a reference on it exists, 0 when freed.
10538  */
10539 static int
10540 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
10541                                         uint32_t port_id)
10542 {
10543         struct mlx5_priv *priv = dev->data->dev_private;
10544         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
10545         uint32_t idx = port_id;
10546
10547         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10548                                         idx);
10549         if (!cache_resource)
10550                 return 0;
10551         MLX5_ASSERT(cache_resource->action);
10552         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
10553                 (void *)cache_resource,
10554                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10555         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10556                                __ATOMIC_RELAXED) == 0) {
10557                 claim_zero(mlx5_flow_os_destroy_flow_action
10558                                                 (cache_resource->action));
10559                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10560                              &priv->sh->port_id_action_list, idx,
10561                              cache_resource, next);
10562                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
10563                 DRV_LOG(DEBUG, "port id action resource %p: removed",
10564                         (void *)cache_resource);
10565                 return 0;
10566         }
10567         return 1;
10568 }
10569
10570 /**
10571  * Release push vlan action resource.
10572  *
10573  * @param dev
10574  *   Pointer to Ethernet device.
10575  * @param handle
10576  *   Pointer to mlx5_flow_handle.
10577  *
10578  * @return
10579  *   1 while a reference on it exists, 0 when freed.
10580  */
10581 static int
10582 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
10583                                           struct mlx5_flow_handle *handle)
10584 {
10585         struct mlx5_priv *priv = dev->data->dev_private;
10586         uint32_t idx = handle->dvh.rix_push_vlan;
10587         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
10588
10589         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10590                                         idx);
10591         if (!cache_resource)
10592                 return 0;
10593         MLX5_ASSERT(cache_resource->action);
10594         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
10595                 (void *)cache_resource,
10596                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10597         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10598                                __ATOMIC_RELAXED) == 0) {
10599                 claim_zero(mlx5_flow_os_destroy_flow_action
10600                                                 (cache_resource->action));
10601                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10602                              &priv->sh->push_vlan_action_list, idx,
10603                              cache_resource, next);
10604                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
10605                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
10606                         (void *)cache_resource);
10607                 return 0;
10608         }
10609         return 1;
10610 }
10611
10612 /**
10613  * Release the fate resource.
10614  *
10615  * @param dev
10616  *   Pointer to Ethernet device.
10617  * @param handle
10618  *   Pointer to mlx5_flow_handle.
10619  */
10620 static void
10621 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
10622                                struct mlx5_flow_handle *handle)
10623 {
10624         if (!handle->rix_fate)
10625                 return;
10626         switch (handle->fate_action) {
10627         case MLX5_FLOW_FATE_QUEUE:
10628                 mlx5_hrxq_release(dev, handle->rix_hrxq);
10629                 break;
10630         case MLX5_FLOW_FATE_JUMP:
10631                 flow_dv_jump_tbl_resource_release(dev, handle);
10632                 break;
10633         case MLX5_FLOW_FATE_PORT_ID:
10634                 flow_dv_port_id_action_resource_release(dev,
10635                                 handle->rix_port_id_action);
10636                 break;
10637         default:
10638                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
10639                 break;
10640         }
10641         handle->rix_fate = 0;
10642 }
10643
10644 /**
10645  * Release an sample resource.
10646  *
10647  * @param dev
10648  *   Pointer to Ethernet device.
10649  * @param handle
10650  *   Pointer to mlx5_flow_handle.
10651  *
10652  * @return
10653  *   1 while a reference on it exists, 0 when freed.
10654  */
10655 static int
10656 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
10657                                      struct mlx5_flow_handle *handle)
10658 {
10659         struct mlx5_priv *priv = dev->data->dev_private;
10660         uint32_t idx = handle->dvh.rix_sample;
10661         struct mlx5_flow_dv_sample_resource *cache_resource;
10662
10663         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10664                          idx);
10665         if (!cache_resource)
10666                 return 0;
10667         MLX5_ASSERT(cache_resource->verbs_action);
10668         DRV_LOG(DEBUG, "sample resource %p: refcnt %d--",
10669                 (void *)cache_resource,
10670                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10671         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10672                                __ATOMIC_RELAXED) == 0) {
10673                 if (cache_resource->verbs_action)
10674                         claim_zero(mlx5_glue->destroy_flow_action
10675                                         (cache_resource->verbs_action));
10676                 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10677                         if (cache_resource->default_miss)
10678                                 claim_zero(mlx5_glue->destroy_flow_action
10679                                   (cache_resource->default_miss));
10680                 }
10681                 if (cache_resource->normal_path_tbl)
10682                         flow_dv_tbl_resource_release(dev,
10683                                 cache_resource->normal_path_tbl);
10684         }
10685         if (cache_resource->sample_idx.rix_hrxq &&
10686                 !mlx5_hrxq_release(dev,
10687                         cache_resource->sample_idx.rix_hrxq))
10688                 cache_resource->sample_idx.rix_hrxq = 0;
10689         if (cache_resource->sample_idx.rix_tag &&
10690                 !flow_dv_tag_release(dev,
10691                         cache_resource->sample_idx.rix_tag))
10692                 cache_resource->sample_idx.rix_tag = 0;
10693         if (cache_resource->sample_idx.cnt) {
10694                 flow_dv_counter_release(dev,
10695                         cache_resource->sample_idx.cnt);
10696                 cache_resource->sample_idx.cnt = 0;
10697         }
10698         if (!__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED)) {
10699                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10700                              &priv->sh->sample_action_list, idx,
10701                              cache_resource, next);
10702                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10703                 DRV_LOG(DEBUG, "sample resource %p: removed",
10704                         (void *)cache_resource);
10705                 return 0;
10706         }
10707         return 1;
10708 }
10709
10710 /**
10711  * Release an destination array resource.
10712  *
10713  * @param dev
10714  *   Pointer to Ethernet device.
10715  * @param handle
10716  *   Pointer to mlx5_flow_handle.
10717  *
10718  * @return
10719  *   1 while a reference on it exists, 0 when freed.
10720  */
10721 static int
10722 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
10723                                      struct mlx5_flow_handle *handle)
10724 {
10725         struct mlx5_priv *priv = dev->data->dev_private;
10726         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10727         struct mlx5_flow_sub_actions_idx *mdest_act_res;
10728         uint32_t idx = handle->dvh.rix_dest_array;
10729         uint32_t i = 0;
10730
10731         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10732                          idx);
10733         if (!cache_resource)
10734                 return 0;
10735         MLX5_ASSERT(cache_resource->action);
10736         DRV_LOG(DEBUG, "destination array resource %p: refcnt %d--",
10737                 (void *)cache_resource,
10738                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10739         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10740                                __ATOMIC_RELAXED) == 0) {
10741                 if (cache_resource->action)
10742                         claim_zero(mlx5_glue->destroy_flow_action
10743                                                 (cache_resource->action));
10744                 for (; i < cache_resource->num_of_dest; i++) {
10745                         mdest_act_res = &cache_resource->sample_idx[i];
10746                         if (mdest_act_res->rix_hrxq) {
10747                                 mlx5_hrxq_release(dev,
10748                                         mdest_act_res->rix_hrxq);
10749                                 mdest_act_res->rix_hrxq = 0;
10750                         }
10751                         if (mdest_act_res->rix_encap_decap) {
10752                                 flow_dv_encap_decap_resource_release(dev,
10753                                         mdest_act_res->rix_encap_decap);
10754                                 mdest_act_res->rix_encap_decap = 0;
10755                         }
10756                         if (mdest_act_res->rix_port_id_action) {
10757                                 flow_dv_port_id_action_resource_release(dev,
10758                                         mdest_act_res->rix_port_id_action);
10759                                 mdest_act_res->rix_port_id_action = 0;
10760                         }
10761                         if (mdest_act_res->rix_tag) {
10762                                 flow_dv_tag_release(dev,
10763                                         mdest_act_res->rix_tag);
10764                                 mdest_act_res->rix_tag = 0;
10765                         }
10766                 }
10767                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10768                              &priv->sh->dest_array_list, idx,
10769                              cache_resource, next);
10770                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], idx);
10771                 DRV_LOG(DEBUG, "destination array resource %p: removed",
10772                         (void *)cache_resource);
10773                 return 0;
10774         }
10775         return 1;
10776 }
10777
10778 /**
10779  * Remove the flow from the NIC but keeps it in memory.
10780  * Lock free, (mutex should be acquired by caller).
10781  *
10782  * @param[in] dev
10783  *   Pointer to Ethernet device.
10784  * @param[in, out] flow
10785  *   Pointer to flow structure.
10786  */
10787 static void
10788 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10789 {
10790         struct mlx5_flow_handle *dh;
10791         uint32_t handle_idx;
10792         struct mlx5_priv *priv = dev->data->dev_private;
10793
10794         if (!flow)
10795                 return;
10796         handle_idx = flow->dev_handles;
10797         while (handle_idx) {
10798                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10799                                     handle_idx);
10800                 if (!dh)
10801                         return;
10802                 if (dh->drv_flow) {
10803                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
10804                         dh->drv_flow = NULL;
10805                 }
10806                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
10807                         flow_dv_fate_resource_release(dev, dh);
10808                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10809                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10810                 handle_idx = dh->next.next;
10811         }
10812 }
10813
10814 /**
10815  * Remove the flow from the NIC and the memory.
10816  * Lock free, (mutex should be acquired by caller).
10817  *
10818  * @param[in] dev
10819  *   Pointer to the Ethernet device structure.
10820  * @param[in, out] flow
10821  *   Pointer to flow structure.
10822  */
10823 static void
10824 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10825 {
10826         struct rte_flow_shared_action *shared;
10827         struct mlx5_flow_handle *dev_handle;
10828         struct mlx5_priv *priv = dev->data->dev_private;
10829
10830         if (!flow)
10831                 return;
10832         __flow_dv_remove(dev, flow);
10833         shared = mlx5_flow_get_shared_rss(flow);
10834         if (shared)
10835                 __atomic_sub_fetch(&shared->refcnt, 1, __ATOMIC_RELAXED);
10836         if (flow->counter) {
10837                 flow_dv_counter_release(dev, flow->counter);
10838                 flow->counter = 0;
10839         }
10840         if (flow->meter) {
10841                 struct mlx5_flow_meter *fm;
10842
10843                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
10844                                     flow->meter);
10845                 if (fm)
10846                         mlx5_flow_meter_detach(fm);
10847                 flow->meter = 0;
10848         }
10849         while (flow->dev_handles) {
10850                 uint32_t tmp_idx = flow->dev_handles;
10851
10852                 dev_handle = mlx5_ipool_get(priv->sh->ipool
10853                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
10854                 if (!dev_handle)
10855                         return;
10856                 flow->dev_handles = dev_handle->next.next;
10857                 if (dev_handle->dvh.matcher)
10858                         flow_dv_matcher_release(dev, dev_handle);
10859                 if (dev_handle->dvh.rix_sample)
10860                         flow_dv_sample_resource_release(dev, dev_handle);
10861                 if (dev_handle->dvh.rix_dest_array)
10862                         flow_dv_dest_array_resource_release(dev, dev_handle);
10863                 if (dev_handle->dvh.rix_encap_decap)
10864                         flow_dv_encap_decap_resource_release(dev,
10865                                 dev_handle->dvh.rix_encap_decap);
10866                 if (dev_handle->dvh.modify_hdr)
10867                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
10868                 if (dev_handle->dvh.rix_push_vlan)
10869                         flow_dv_push_vlan_action_resource_release(dev,
10870                                                                   dev_handle);
10871                 if (dev_handle->dvh.rix_tag)
10872                         flow_dv_tag_release(dev,
10873                                             dev_handle->dvh.rix_tag);
10874                 flow_dv_fate_resource_release(dev, dev_handle);
10875                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10876                            tmp_idx);
10877         }
10878 }
10879
10880 /**
10881  * Release array of hash RX queue objects.
10882  * Helper function.
10883  *
10884  * @param[in] dev
10885  *   Pointer to the Ethernet device structure.
10886  * @param[in, out] hrxqs
10887  *   Array of hash RX queue objects.
10888  *
10889  * @return
10890  *   Total number of references to hash RX queue objects in *hrxqs* array
10891  *   after this operation.
10892  */
10893 static int
10894 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
10895                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
10896 {
10897         size_t i;
10898         int remaining = 0;
10899
10900         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
10901                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
10902
10903                 if (!ret)
10904                         (*hrxqs)[i] = 0;
10905                 remaining += ret;
10906         }
10907         return remaining;
10908 }
10909
10910 /**
10911  * Release all hash RX queue objects representing shared RSS action.
10912  *
10913  * @param[in] dev
10914  *   Pointer to the Ethernet device structure.
10915  * @param[in, out] action
10916  *   Shared RSS action to remove hash RX queue objects from.
10917  *
10918  * @return
10919  *   Total number of references to hash RX queue objects stored in *action*
10920  *   after this operation.
10921  *   Expected to be 0 if no external references held.
10922  */
10923 static int
10924 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
10925                                  struct mlx5_shared_action_rss *action)
10926 {
10927         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
10928                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
10929 }
10930
10931 /**
10932  * Setup shared RSS action.
10933  * Prepare set of hash RX queue objects sufficient to handle all valid
10934  * hash_fields combinations (see enum ibv_rx_hash_fields).
10935  *
10936  * @param[in] dev
10937  *   Pointer to the Ethernet device structure.
10938  * @param[in, out] action
10939  *   Partially initialized shared RSS action.
10940  * @param[out] error
10941  *   Perform verbose error reporting if not NULL. Initialized in case of
10942  *   error only.
10943  *
10944  * @return
10945  *   0 on success, otherwise negative errno value.
10946  */
10947 static int
10948 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
10949                         struct mlx5_shared_action_rss *action,
10950                         struct rte_flow_error *error)
10951 {
10952         size_t i;
10953         int err;
10954
10955         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
10956                 uint32_t hrxq_idx;
10957                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
10958                 int tunnel;
10959
10960                 for (tunnel = 0; tunnel < 2; tunnel++) {
10961                         hrxq_idx = mlx5_hrxq_new(dev, action->origin.key,
10962                                         MLX5_RSS_HASH_KEY_LEN,
10963                                         hash_fields,
10964                                         action->origin.queue,
10965                                         action->origin.queue_num,
10966                                         tunnel, true);
10967                         if (!hrxq_idx) {
10968                                 rte_flow_error_set
10969                                         (error, rte_errno,
10970                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10971                                          "cannot get hash queue");
10972                                 goto error_hrxq_new;
10973                         }
10974                         err = __flow_dv_action_rss_hrxq_set
10975                                 (action, hash_fields, tunnel, hrxq_idx);
10976                         MLX5_ASSERT(!err);
10977                 }
10978         }
10979         return 0;
10980 error_hrxq_new:
10981         err = rte_errno;
10982         __flow_dv_action_rss_hrxqs_release(dev, action);
10983         rte_errno = err;
10984         return -rte_errno;
10985 }
10986
10987 /**
10988  * Create shared RSS action.
10989  *
10990  * @param[in] dev
10991  *   Pointer to the Ethernet device structure.
10992  * @param[in] conf
10993  *   Shared action configuration.
10994  * @param[in] rss
10995  *   RSS action specification used to create shared action.
10996  * @param[out] error
10997  *   Perform verbose error reporting if not NULL. Initialized in case of
10998  *   error only.
10999  *
11000  * @return
11001  *   A valid shared action handle in case of success, NULL otherwise and
11002  *   rte_errno is set.
11003  */
11004 static struct rte_flow_shared_action *
11005 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11006                             const struct rte_flow_shared_action_conf *conf,
11007                             const struct rte_flow_action_rss *rss,
11008                             struct rte_flow_error *error)
11009 {
11010         struct rte_flow_shared_action *shared_action = NULL;
11011         void *queue = NULL;
11012         struct mlx5_shared_action_rss *shared_rss;
11013         struct rte_flow_action_rss *origin;
11014         const uint8_t *rss_key;
11015         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11016
11017         RTE_SET_USED(conf);
11018         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11019                             0, SOCKET_ID_ANY);
11020         shared_action = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*shared_action), 0,
11021                                     SOCKET_ID_ANY);
11022         if (!shared_action || !queue) {
11023                 rte_flow_error_set(error, ENOMEM,
11024                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11025                                    "cannot allocate resource memory");
11026                 goto error_rss_init;
11027         }
11028         shared_rss = &shared_action->rss;
11029         shared_rss->queue = queue;
11030         origin = &shared_rss->origin;
11031         origin->func = rss->func;
11032         origin->level = rss->level;
11033         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11034         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11035         /* NULL RSS key indicates default RSS key. */
11036         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11037         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11038         origin->key = &shared_rss->key[0];
11039         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11040         memcpy(shared_rss->queue, rss->queue, queue_size);
11041         origin->queue = shared_rss->queue;
11042         origin->queue_num = rss->queue_num;
11043         if (__flow_dv_action_rss_setup(dev, shared_rss, error))
11044                 goto error_rss_init;
11045         shared_action->type = MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS;
11046         return shared_action;
11047 error_rss_init:
11048         mlx5_free(shared_action);
11049         mlx5_free(queue);
11050         return NULL;
11051 }
11052
11053 /**
11054  * Destroy the shared RSS action.
11055  * Release related hash RX queue objects.
11056  *
11057  * @param[in] dev
11058  *   Pointer to the Ethernet device structure.
11059  * @param[in] shared_rss
11060  *   The shared RSS action object to be removed.
11061  * @param[out] error
11062  *   Perform verbose error reporting if not NULL. Initialized in case of
11063  *   error only.
11064  *
11065  * @return
11066  *   0 on success, otherwise negative errno value.
11067  */
11068 static int
11069 __flow_dv_action_rss_release(struct rte_eth_dev *dev,
11070                          struct mlx5_shared_action_rss *shared_rss,
11071                          struct rte_flow_error *error)
11072 {
11073         struct rte_flow_shared_action *shared_action = NULL;
11074         uint32_t old_refcnt = 1;
11075         int remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11076
11077         if (remaining) {
11078                 return rte_flow_error_set(error, ETOOMANYREFS,
11079                                           RTE_FLOW_ERROR_TYPE_ACTION,
11080                                           NULL,
11081                                           "shared rss hrxq has references");
11082         }
11083         shared_action = container_of(shared_rss,
11084                                      struct rte_flow_shared_action, rss);
11085         if (!__atomic_compare_exchange_n(&shared_action->refcnt, &old_refcnt,
11086                                          0, 0,
11087                                          __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {
11088                 return rte_flow_error_set(error, ETOOMANYREFS,
11089                                           RTE_FLOW_ERROR_TYPE_ACTION,
11090                                           NULL,
11091                                           "shared rss has references");
11092         }
11093         rte_free(shared_rss->queue);
11094         return 0;
11095 }
11096
11097 /**
11098  * Create shared action, lock free,
11099  * (mutex should be acquired by caller).
11100  * Dispatcher for action type specific call.
11101  *
11102  * @param[in] dev
11103  *   Pointer to the Ethernet device structure.
11104  * @param[in] conf
11105  *   Shared action configuration.
11106  * @param[in] action
11107  *   Action specification used to create shared action.
11108  * @param[out] error
11109  *   Perform verbose error reporting if not NULL. Initialized in case of
11110  *   error only.
11111  *
11112  * @return
11113  *   A valid shared action handle in case of success, NULL otherwise and
11114  *   rte_errno is set.
11115  */
11116 static struct rte_flow_shared_action *
11117 __flow_dv_action_create(struct rte_eth_dev *dev,
11118                         const struct rte_flow_shared_action_conf *conf,
11119                         const struct rte_flow_action *action,
11120                         struct rte_flow_error *error)
11121 {
11122         struct rte_flow_shared_action *shared_action = NULL;
11123         struct mlx5_priv *priv = dev->data->dev_private;
11124
11125         switch (action->type) {
11126         case RTE_FLOW_ACTION_TYPE_RSS:
11127                 shared_action = __flow_dv_action_rss_create(dev, conf,
11128                                                             action->conf,
11129                                                             error);
11130                 break;
11131         default:
11132                 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11133                                    NULL, "action type not supported");
11134                 break;
11135         }
11136         if (shared_action) {
11137                 __atomic_add_fetch(&shared_action->refcnt, 1,
11138                                    __ATOMIC_RELAXED);
11139                 LIST_INSERT_HEAD(&priv->shared_actions, shared_action, next);
11140         }
11141         return shared_action;
11142 }
11143
11144 /**
11145  * Destroy the shared action.
11146  * Release action related resources on the NIC and the memory.
11147  * Lock free, (mutex should be acquired by caller).
11148  * Dispatcher for action type specific call.
11149  *
11150  * @param[in] dev
11151  *   Pointer to the Ethernet device structure.
11152  * @param[in] action
11153  *   The shared action object to be removed.
11154  * @param[out] error
11155  *   Perform verbose error reporting if not NULL. Initialized in case of
11156  *   error only.
11157  *
11158  * @return
11159  *   0 on success, otherwise negative errno value.
11160  */
11161 static int
11162 __flow_dv_action_destroy(struct rte_eth_dev *dev,
11163                          struct rte_flow_shared_action *action,
11164                          struct rte_flow_error *error)
11165 {
11166         int ret;
11167
11168         switch (action->type) {
11169         case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11170                 ret = __flow_dv_action_rss_release(dev, &action->rss, error);
11171                 break;
11172         default:
11173                 return rte_flow_error_set(error, ENOTSUP,
11174                                           RTE_FLOW_ERROR_TYPE_ACTION,
11175                                           NULL,
11176                                           "action type not supported");
11177         }
11178         if (ret)
11179                 return ret;
11180         LIST_REMOVE(action, next);
11181         rte_free(action);
11182         return 0;
11183 }
11184
11185 /**
11186  * Updates in place shared RSS action configuration.
11187  *
11188  * @param[in] dev
11189  *   Pointer to the Ethernet device structure.
11190  * @param[in] shared_rss
11191  *   The shared RSS action object to be updated.
11192  * @param[in] action_conf
11193  *   RSS action specification used to modify *shared_rss*.
11194  * @param[out] error
11195  *   Perform verbose error reporting if not NULL. Initialized in case of
11196  *   error only.
11197  *
11198  * @return
11199  *   0 on success, otherwise negative errno value.
11200  * @note: currently only support update of RSS queues.
11201  */
11202 static int
11203 __flow_dv_action_rss_update(struct rte_eth_dev *dev,
11204                             struct mlx5_shared_action_rss *shared_rss,
11205                             const struct rte_flow_action_rss *action_conf,
11206                             struct rte_flow_error *error)
11207 {
11208         size_t i;
11209         int ret;
11210         void *queue = NULL;
11211         const uint8_t *rss_key;
11212         uint32_t rss_key_len;
11213         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11214
11215         queue = mlx5_malloc(MLX5_MEM_ZERO,
11216                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11217                             0, SOCKET_ID_ANY);
11218         if (!queue)
11219                 return rte_flow_error_set(error, ENOMEM,
11220                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11221                                           NULL,
11222                                           "cannot allocate resource memory");
11223         if (action_conf->key) {
11224                 rss_key = action_conf->key;
11225                 rss_key_len = action_conf->key_len;
11226         } else {
11227                 rss_key = rss_hash_default_key;
11228                 rss_key_len = MLX5_RSS_HASH_KEY_LEN;
11229         }
11230         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11231                 uint32_t hrxq_idx;
11232                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11233                 int tunnel;
11234
11235                 for (tunnel = 0; tunnel < 2; tunnel++) {
11236                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup
11237                                         (shared_rss, hash_fields, tunnel);
11238                         MLX5_ASSERT(hrxq_idx);
11239                         ret = mlx5_hrxq_modify
11240                                 (dev, hrxq_idx,
11241                                  rss_key, rss_key_len,
11242                                  hash_fields,
11243                                  action_conf->queue, action_conf->queue_num);
11244                         if (ret) {
11245                                 mlx5_free(queue);
11246                                 return rte_flow_error_set
11247                                         (error, rte_errno,
11248                                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11249                                          "cannot update hash queue");
11250                         }
11251                 }
11252         }
11253         mlx5_free(shared_rss->queue);
11254         shared_rss->queue = queue;
11255         memcpy(shared_rss->queue, action_conf->queue, queue_size);
11256         shared_rss->origin.queue = shared_rss->queue;
11257         shared_rss->origin.queue_num = action_conf->queue_num;
11258         return 0;
11259 }
11260
11261 /**
11262  * Updates in place shared action configuration, lock free,
11263  * (mutex should be acquired by caller).
11264  *
11265  * @param[in] dev
11266  *   Pointer to the Ethernet device structure.
11267  * @param[in] action
11268  *   The shared action object to be updated.
11269  * @param[in] action_conf
11270  *   Action specification used to modify *action*.
11271  *   *action_conf* should be of type correlating with type of the *action*,
11272  *   otherwise considered as invalid.
11273  * @param[out] error
11274  *   Perform verbose error reporting if not NULL. Initialized in case of
11275  *   error only.
11276  *
11277  * @return
11278  *   0 on success, otherwise negative errno value.
11279  */
11280 static int
11281 __flow_dv_action_update(struct rte_eth_dev *dev,
11282                         struct rte_flow_shared_action *action,
11283                         const void *action_conf,
11284                         struct rte_flow_error *error)
11285 {
11286         switch (action->type) {
11287         case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11288                 return __flow_dv_action_rss_update(dev, &action->rss,
11289                                                    action_conf, error);
11290         default:
11291                 return rte_flow_error_set(error, ENOTSUP,
11292                                           RTE_FLOW_ERROR_TYPE_ACTION,
11293                                           NULL,
11294                                           "action type not supported");
11295         }
11296 }
11297 /**
11298  * Query a dv flow  rule for its statistics via devx.
11299  *
11300  * @param[in] dev
11301  *   Pointer to Ethernet device.
11302  * @param[in] flow
11303  *   Pointer to the sub flow.
11304  * @param[out] data
11305  *   data retrieved by the query.
11306  * @param[out] error
11307  *   Perform verbose error reporting if not NULL.
11308  *
11309  * @return
11310  *   0 on success, a negative errno value otherwise and rte_errno is set.
11311  */
11312 static int
11313 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11314                     void *data, struct rte_flow_error *error)
11315 {
11316         struct mlx5_priv *priv = dev->data->dev_private;
11317         struct rte_flow_query_count *qc = data;
11318
11319         if (!priv->config.devx)
11320                 return rte_flow_error_set(error, ENOTSUP,
11321                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11322                                           NULL,
11323                                           "counters are not supported");
11324         if (flow->counter) {
11325                 uint64_t pkts, bytes;
11326                 struct mlx5_flow_counter *cnt;
11327
11328                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11329                                                  NULL);
11330                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11331                                                &bytes);
11332
11333                 if (err)
11334                         return rte_flow_error_set(error, -err,
11335                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11336                                         NULL, "cannot read counters");
11337                 qc->hits_set = 1;
11338                 qc->bytes_set = 1;
11339                 qc->hits = pkts - cnt->hits;
11340                 qc->bytes = bytes - cnt->bytes;
11341                 if (qc->reset) {
11342                         cnt->hits = pkts;
11343                         cnt->bytes = bytes;
11344                 }
11345                 return 0;
11346         }
11347         return rte_flow_error_set(error, EINVAL,
11348                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11349                                   NULL,
11350                                   "counters are not available");
11351 }
11352
11353 /**
11354  * Query a flow rule AGE action for aging information.
11355  *
11356  * @param[in] dev
11357  *   Pointer to Ethernet device.
11358  * @param[in] flow
11359  *   Pointer to the sub flow.
11360  * @param[out] data
11361  *   data retrieved by the query.
11362  * @param[out] error
11363  *   Perform verbose error reporting if not NULL.
11364  *
11365  * @return
11366  *   0 on success, a negative errno value otherwise and rte_errno is set.
11367  */
11368 static int
11369 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11370                   void *data, struct rte_flow_error *error)
11371 {
11372         struct rte_flow_query_age *resp = data;
11373
11374         if (flow->counter) {
11375                 struct mlx5_age_param *age_param =
11376                                 flow_dv_counter_idx_get_age(dev, flow->counter);
11377
11378                 if (!age_param || !age_param->timeout)
11379                         return rte_flow_error_set
11380                                         (error, EINVAL,
11381                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11382                                          NULL, "cannot read age data");
11383                 resp->aged = __atomic_load_n(&age_param->state,
11384                                              __ATOMIC_RELAXED) ==
11385                                                         AGE_TMOUT ? 1 : 0;
11386                 resp->sec_since_last_hit_valid = !resp->aged;
11387                 if (resp->sec_since_last_hit_valid)
11388                         resp->sec_since_last_hit =
11389                                 __atomic_load_n(&age_param->sec_since_last_hit,
11390                                                 __ATOMIC_RELAXED);
11391                 return 0;
11392         }
11393         return rte_flow_error_set(error, EINVAL,
11394                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11395                                   NULL,
11396                                   "age data not available");
11397 }
11398
11399 /**
11400  * Query a flow.
11401  *
11402  * @see rte_flow_query()
11403  * @see rte_flow_ops
11404  */
11405 static int
11406 flow_dv_query(struct rte_eth_dev *dev,
11407               struct rte_flow *flow __rte_unused,
11408               const struct rte_flow_action *actions __rte_unused,
11409               void *data __rte_unused,
11410               struct rte_flow_error *error __rte_unused)
11411 {
11412         int ret = -EINVAL;
11413
11414         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11415                 switch (actions->type) {
11416                 case RTE_FLOW_ACTION_TYPE_VOID:
11417                         break;
11418                 case RTE_FLOW_ACTION_TYPE_COUNT:
11419                         ret = flow_dv_query_count(dev, flow, data, error);
11420                         break;
11421                 case RTE_FLOW_ACTION_TYPE_AGE:
11422                         ret = flow_dv_query_age(dev, flow, data, error);
11423                         break;
11424                 default:
11425                         return rte_flow_error_set(error, ENOTSUP,
11426                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11427                                                   actions,
11428                                                   "action not supported");
11429                 }
11430         }
11431         return ret;
11432 }
11433
11434 /**
11435  * Destroy the meter table set.
11436  * Lock free, (mutex should be acquired by caller).
11437  *
11438  * @param[in] dev
11439  *   Pointer to Ethernet device.
11440  * @param[in] tbl
11441  *   Pointer to the meter table set.
11442  *
11443  * @return
11444  *   Always 0.
11445  */
11446 static int
11447 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11448                         struct mlx5_meter_domains_infos *tbl)
11449 {
11450         struct mlx5_priv *priv = dev->data->dev_private;
11451         struct mlx5_meter_domains_infos *mtd =
11452                                 (struct mlx5_meter_domains_infos *)tbl;
11453
11454         if (!mtd || !priv->config.dv_flow_en)
11455                 return 0;
11456         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11457                 claim_zero(mlx5_flow_os_destroy_flow
11458                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11459         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11460                 claim_zero(mlx5_flow_os_destroy_flow
11461                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11462         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11463                 claim_zero(mlx5_flow_os_destroy_flow
11464                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
11465         if (mtd->egress.color_matcher)
11466                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11467                            (mtd->egress.color_matcher));
11468         if (mtd->egress.any_matcher)
11469                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11470                            (mtd->egress.any_matcher));
11471         if (mtd->egress.tbl)
11472                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
11473         if (mtd->egress.sfx_tbl)
11474                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
11475         if (mtd->ingress.color_matcher)
11476                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11477                            (mtd->ingress.color_matcher));
11478         if (mtd->ingress.any_matcher)
11479                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11480                            (mtd->ingress.any_matcher));
11481         if (mtd->ingress.tbl)
11482                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
11483         if (mtd->ingress.sfx_tbl)
11484                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
11485         if (mtd->transfer.color_matcher)
11486                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11487                            (mtd->transfer.color_matcher));
11488         if (mtd->transfer.any_matcher)
11489                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11490                            (mtd->transfer.any_matcher));
11491         if (mtd->transfer.tbl)
11492                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
11493         if (mtd->transfer.sfx_tbl)
11494                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
11495         if (mtd->drop_actn)
11496                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
11497         mlx5_free(mtd);
11498         return 0;
11499 }
11500
11501 /* Number of meter flow actions, count and jump or count and drop. */
11502 #define METER_ACTIONS 2
11503
11504 /**
11505  * Create specify domain meter table and suffix table.
11506  *
11507  * @param[in] dev
11508  *   Pointer to Ethernet device.
11509  * @param[in,out] mtb
11510  *   Pointer to DV meter table set.
11511  * @param[in] egress
11512  *   Table attribute.
11513  * @param[in] transfer
11514  *   Table attribute.
11515  * @param[in] color_reg_c_idx
11516  *   Reg C index for color match.
11517  *
11518  * @return
11519  *   0 on success, -1 otherwise and rte_errno is set.
11520  */
11521 static int
11522 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
11523                            struct mlx5_meter_domains_infos *mtb,
11524                            uint8_t egress, uint8_t transfer,
11525                            uint32_t color_reg_c_idx)
11526 {
11527         struct mlx5_priv *priv = dev->data->dev_private;
11528         struct mlx5_dev_ctx_shared *sh = priv->sh;
11529         struct mlx5_flow_dv_match_params mask = {
11530                 .size = sizeof(mask.buf),
11531         };
11532         struct mlx5_flow_dv_match_params value = {
11533                 .size = sizeof(value.buf),
11534         };
11535         struct mlx5dv_flow_matcher_attr dv_attr = {
11536                 .type = IBV_FLOW_ATTR_NORMAL,
11537                 .priority = 0,
11538                 .match_criteria_enable = 0,
11539                 .match_mask = (void *)&mask,
11540         };
11541         void *actions[METER_ACTIONS];
11542         struct mlx5_meter_domain_info *dtb;
11543         struct rte_flow_error error;
11544         int i = 0;
11545         int ret;
11546
11547         if (transfer)
11548                 dtb = &mtb->transfer;
11549         else if (egress)
11550                 dtb = &mtb->egress;
11551         else
11552                 dtb = &mtb->ingress;
11553         /* Create the meter table with METER level. */
11554         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
11555                                             egress, transfer, false, NULL, 0,
11556                                             &error);
11557         if (!dtb->tbl) {
11558                 DRV_LOG(ERR, "Failed to create meter policer table.");
11559                 return -1;
11560         }
11561         /* Create the meter suffix table with SUFFIX level. */
11562         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
11563                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
11564                                             egress, transfer, false, NULL, 0,
11565                                             &error);
11566         if (!dtb->sfx_tbl) {
11567                 DRV_LOG(ERR, "Failed to create meter suffix table.");
11568                 return -1;
11569         }
11570         /* Create matchers, Any and Color. */
11571         dv_attr.priority = 3;
11572         dv_attr.match_criteria_enable = 0;
11573         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11574                                                &dtb->any_matcher);
11575         if (ret) {
11576                 DRV_LOG(ERR, "Failed to create meter"
11577                              " policer default matcher.");
11578                 goto error_exit;
11579         }
11580         dv_attr.priority = 0;
11581         dv_attr.match_criteria_enable =
11582                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
11583         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
11584                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
11585         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11586                                                &dtb->color_matcher);
11587         if (ret) {
11588                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
11589                 goto error_exit;
11590         }
11591         if (mtb->count_actns[RTE_MTR_DROPPED])
11592                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
11593         actions[i++] = mtb->drop_actn;
11594         /* Default rule: lowest priority, match any, actions: drop. */
11595         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
11596                                        actions,
11597                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
11598         if (ret) {
11599                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
11600                 goto error_exit;
11601         }
11602         return 0;
11603 error_exit:
11604         return -1;
11605 }
11606
11607 /**
11608  * Create the needed meter and suffix tables.
11609  * Lock free, (mutex should be acquired by caller).
11610  *
11611  * @param[in] dev
11612  *   Pointer to Ethernet device.
11613  * @param[in] fm
11614  *   Pointer to the flow meter.
11615  *
11616  * @return
11617  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
11618  */
11619 static struct mlx5_meter_domains_infos *
11620 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
11621                        const struct mlx5_flow_meter *fm)
11622 {
11623         struct mlx5_priv *priv = dev->data->dev_private;
11624         struct mlx5_meter_domains_infos *mtb;
11625         int ret;
11626         int i;
11627
11628         if (!priv->mtr_en) {
11629                 rte_errno = ENOTSUP;
11630                 return NULL;
11631         }
11632         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
11633         if (!mtb) {
11634                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
11635                 return NULL;
11636         }
11637         /* Create meter count actions */
11638         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
11639                 struct mlx5_flow_counter *cnt;
11640                 if (!fm->policer_stats.cnt[i])
11641                         continue;
11642                 cnt = flow_dv_counter_get_by_idx(dev,
11643                       fm->policer_stats.cnt[i], NULL);
11644                 mtb->count_actns[i] = cnt->action;
11645         }
11646         /* Create drop action. */
11647         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
11648         if (ret) {
11649                 DRV_LOG(ERR, "Failed to create drop action.");
11650                 goto error_exit;
11651         }
11652         /* Egress meter table. */
11653         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
11654         if (ret) {
11655                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
11656                 goto error_exit;
11657         }
11658         /* Ingress meter table. */
11659         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
11660         if (ret) {
11661                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
11662                 goto error_exit;
11663         }
11664         /* FDB meter table. */
11665         if (priv->config.dv_esw_en) {
11666                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
11667                                                  priv->mtr_color_reg);
11668                 if (ret) {
11669                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
11670                         goto error_exit;
11671                 }
11672         }
11673         return mtb;
11674 error_exit:
11675         flow_dv_destroy_mtr_tbl(dev, mtb);
11676         return NULL;
11677 }
11678
11679 /**
11680  * Destroy domain policer rule.
11681  *
11682  * @param[in] dt
11683  *   Pointer to domain table.
11684  */
11685 static void
11686 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
11687 {
11688         int i;
11689
11690         for (i = 0; i < RTE_MTR_DROPPED; i++) {
11691                 if (dt->policer_rules[i]) {
11692                         claim_zero(mlx5_flow_os_destroy_flow
11693                                    (dt->policer_rules[i]));
11694                         dt->policer_rules[i] = NULL;
11695                 }
11696         }
11697         if (dt->jump_actn) {
11698                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
11699                 dt->jump_actn = NULL;
11700         }
11701 }
11702
11703 /**
11704  * Destroy policer rules.
11705  *
11706  * @param[in] dev
11707  *   Pointer to Ethernet device.
11708  * @param[in] fm
11709  *   Pointer to flow meter structure.
11710  * @param[in] attr
11711  *   Pointer to flow attributes.
11712  *
11713  * @return
11714  *   Always 0.
11715  */
11716 static int
11717 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
11718                               const struct mlx5_flow_meter *fm,
11719                               const struct rte_flow_attr *attr)
11720 {
11721         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
11722
11723         if (!mtb)
11724                 return 0;
11725         if (attr->egress)
11726                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
11727         if (attr->ingress)
11728                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
11729         if (attr->transfer)
11730                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
11731         return 0;
11732 }
11733
11734 /**
11735  * Create specify domain meter policer rule.
11736  *
11737  * @param[in] fm
11738  *   Pointer to flow meter structure.
11739  * @param[in] mtb
11740  *   Pointer to DV meter table set.
11741  * @param[in] mtr_reg_c
11742  *   Color match REG_C.
11743  *
11744  * @return
11745  *   0 on success, -1 otherwise.
11746  */
11747 static int
11748 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
11749                                     struct mlx5_meter_domain_info *dtb,
11750                                     uint8_t mtr_reg_c)
11751 {
11752         struct mlx5_flow_dv_match_params matcher = {
11753                 .size = sizeof(matcher.buf),
11754         };
11755         struct mlx5_flow_dv_match_params value = {
11756                 .size = sizeof(value.buf),
11757         };
11758         struct mlx5_meter_domains_infos *mtb = fm->mfts;
11759         void *actions[METER_ACTIONS];
11760         int i;
11761         int ret = 0;
11762
11763         /* Create jump action. */
11764         if (!dtb->jump_actn)
11765                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11766                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
11767         if (ret) {
11768                 DRV_LOG(ERR, "Failed to create policer jump action.");
11769                 goto error;
11770         }
11771         for (i = 0; i < RTE_MTR_DROPPED; i++) {
11772                 int j = 0;
11773
11774                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
11775                                        rte_col_2_mlx5_col(i), UINT8_MAX);
11776                 if (mtb->count_actns[i])
11777                         actions[j++] = mtb->count_actns[i];
11778                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
11779                         actions[j++] = mtb->drop_actn;
11780                 else
11781                         actions[j++] = dtb->jump_actn;
11782                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
11783                                                (void *)&value, j, actions,
11784                                                &dtb->policer_rules[i]);
11785                 if (ret) {
11786                         DRV_LOG(ERR, "Failed to create policer rule.");
11787                         goto error;
11788                 }
11789         }
11790         return 0;
11791 error:
11792         rte_errno = errno;
11793         return -1;
11794 }
11795
11796 /**
11797  * Create policer rules.
11798  *
11799  * @param[in] dev
11800  *   Pointer to Ethernet device.
11801  * @param[in] fm
11802  *   Pointer to flow meter structure.
11803  * @param[in] attr
11804  *   Pointer to flow attributes.
11805  *
11806  * @return
11807  *   0 on success, -1 otherwise.
11808  */
11809 static int
11810 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
11811                              struct mlx5_flow_meter *fm,
11812                              const struct rte_flow_attr *attr)
11813 {
11814         struct mlx5_priv *priv = dev->data->dev_private;
11815         struct mlx5_meter_domains_infos *mtb = fm->mfts;
11816         int ret;
11817
11818         if (attr->egress) {
11819                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
11820                                                 priv->mtr_color_reg);
11821                 if (ret) {
11822                         DRV_LOG(ERR, "Failed to create egress policer.");
11823                         goto error;
11824                 }
11825         }
11826         if (attr->ingress) {
11827                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
11828                                                 priv->mtr_color_reg);
11829                 if (ret) {
11830                         DRV_LOG(ERR, "Failed to create ingress policer.");
11831                         goto error;
11832                 }
11833         }
11834         if (attr->transfer) {
11835                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
11836                                                 priv->mtr_color_reg);
11837                 if (ret) {
11838                         DRV_LOG(ERR, "Failed to create transfer policer.");
11839                         goto error;
11840                 }
11841         }
11842         return 0;
11843 error:
11844         flow_dv_destroy_policer_rules(dev, fm, attr);
11845         return -1;
11846 }
11847
11848 /**
11849  * Validate the batch counter support in root table.
11850  *
11851  * Create a simple flow with invalid counter and drop action on root table to
11852  * validate if batch counter with offset on root table is supported or not.
11853  *
11854  * @param[in] dev
11855  *   Pointer to rte_eth_dev structure.
11856  *
11857  * @return
11858  *   0 on success, a negative errno value otherwise and rte_errno is set.
11859  */
11860 int
11861 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
11862 {
11863         struct mlx5_priv *priv = dev->data->dev_private;
11864         struct mlx5_dev_ctx_shared *sh = priv->sh;
11865         struct mlx5_flow_dv_match_params mask = {
11866                 .size = sizeof(mask.buf),
11867         };
11868         struct mlx5_flow_dv_match_params value = {
11869                 .size = sizeof(value.buf),
11870         };
11871         struct mlx5dv_flow_matcher_attr dv_attr = {
11872                 .type = IBV_FLOW_ATTR_NORMAL,
11873                 .priority = 0,
11874                 .match_criteria_enable = 0,
11875                 .match_mask = (void *)&mask,
11876         };
11877         void *actions[2] = { 0 };
11878         struct mlx5_flow_tbl_resource *tbl = NULL, *dest_tbl = NULL;
11879         struct mlx5_devx_obj *dcs = NULL;
11880         void *matcher = NULL;
11881         void *flow = NULL;
11882         int i, ret = -1;
11883
11884         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, NULL);
11885         if (!tbl)
11886                 goto err;
11887         dest_tbl = flow_dv_tbl_resource_get(dev, 1, 0, 0, false, NULL, 0, NULL);
11888         if (!dest_tbl)
11889                 goto err;
11890         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
11891         if (!dcs)
11892                 goto err;
11893         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
11894                                                     &actions[0]);
11895         if (ret)
11896                 goto err;
11897         ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11898                                 (dest_tbl->obj, &actions[1]);
11899         if (ret)
11900                 goto err;
11901         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
11902         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
11903                                                &matcher);
11904         if (ret)
11905                 goto err;
11906         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
11907                                        actions, &flow);
11908 err:
11909         /*
11910          * If batch counter with offset is not supported, the driver will not
11911          * validate the invalid offset value, flow create should success.
11912          * In this case, it means batch counter is not supported in root table.
11913          *
11914          * Otherwise, if flow create is failed, counter offset is supported.
11915          */
11916         if (flow) {
11917                 DRV_LOG(INFO, "Batch counter is not supported in root "
11918                               "table. Switch to fallback mode.");
11919                 rte_errno = ENOTSUP;
11920                 ret = -rte_errno;
11921                 claim_zero(mlx5_flow_os_destroy_flow(flow));
11922         } else {
11923                 /* Check matcher to make sure validate fail at flow create. */
11924                 if (!matcher || (matcher && errno != EINVAL))
11925                         DRV_LOG(ERR, "Unexpected error in counter offset "
11926                                      "support detection");
11927                 ret = 0;
11928         }
11929         for (i = 0; i < 2; i++) {
11930                 if (actions[i])
11931                         claim_zero(mlx5_flow_os_destroy_flow_action
11932                                    (actions[i]));
11933         }
11934         if (matcher)
11935                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
11936         if (tbl)
11937                 flow_dv_tbl_resource_release(dev, tbl);
11938         if (dest_tbl)
11939                 flow_dv_tbl_resource_release(dev, dest_tbl);
11940         if (dcs)
11941                 claim_zero(mlx5_devx_cmd_destroy(dcs));
11942         return ret;
11943 }
11944
11945 /**
11946  * Query a devx counter.
11947  *
11948  * @param[in] dev
11949  *   Pointer to the Ethernet device structure.
11950  * @param[in] cnt
11951  *   Index to the flow counter.
11952  * @param[in] clear
11953  *   Set to clear the counter statistics.
11954  * @param[out] pkts
11955  *   The statistics value of packets.
11956  * @param[out] bytes
11957  *   The statistics value of bytes.
11958  *
11959  * @return
11960  *   0 on success, otherwise return -1.
11961  */
11962 static int
11963 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
11964                       uint64_t *pkts, uint64_t *bytes)
11965 {
11966         struct mlx5_priv *priv = dev->data->dev_private;
11967         struct mlx5_flow_counter *cnt;
11968         uint64_t inn_pkts, inn_bytes;
11969         int ret;
11970
11971         if (!priv->config.devx)
11972                 return -1;
11973
11974         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
11975         if (ret)
11976                 return -1;
11977         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
11978         *pkts = inn_pkts - cnt->hits;
11979         *bytes = inn_bytes - cnt->bytes;
11980         if (clear) {
11981                 cnt->hits = inn_pkts;
11982                 cnt->bytes = inn_bytes;
11983         }
11984         return 0;
11985 }
11986
11987 /**
11988  * Get aged-out flows.
11989  *
11990  * @param[in] dev
11991  *   Pointer to the Ethernet device structure.
11992  * @param[in] context
11993  *   The address of an array of pointers to the aged-out flows contexts.
11994  * @param[in] nb_contexts
11995  *   The length of context array pointers.
11996  * @param[out] error
11997  *   Perform verbose error reporting if not NULL. Initialized in case of
11998  *   error only.
11999  *
12000  * @return
12001  *   how many contexts get in success, otherwise negative errno value.
12002  *   if nb_contexts is 0, return the amount of all aged contexts.
12003  *   if nb_contexts is not 0 , return the amount of aged flows reported
12004  *   in the context array.
12005  * @note: only stub for now
12006  */
12007 static int
12008 flow_get_aged_flows(struct rte_eth_dev *dev,
12009                     void **context,
12010                     uint32_t nb_contexts,
12011                     struct rte_flow_error *error)
12012 {
12013         struct mlx5_priv *priv = dev->data->dev_private;
12014         struct mlx5_age_info *age_info;
12015         struct mlx5_age_param *age_param;
12016         struct mlx5_flow_counter *counter;
12017         int nb_flows = 0;
12018
12019         if (nb_contexts && !context)
12020                 return rte_flow_error_set(error, EINVAL,
12021                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12022                                           NULL,
12023                                           "Should assign at least one flow or"
12024                                           " context to get if nb_contexts != 0");
12025         age_info = GET_PORT_AGE_INFO(priv);
12026         rte_spinlock_lock(&age_info->aged_sl);
12027         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12028                 nb_flows++;
12029                 if (nb_contexts) {
12030                         age_param = MLX5_CNT_TO_AGE(counter);
12031                         context[nb_flows - 1] = age_param->context;
12032                         if (!(--nb_contexts))
12033                                 break;
12034                 }
12035         }
12036         rte_spinlock_unlock(&age_info->aged_sl);
12037         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12038         return nb_flows;
12039 }
12040
12041 /*
12042  * Mutex-protected thunk to lock-free  __flow_dv_translate().
12043  */
12044 static int
12045 flow_dv_translate(struct rte_eth_dev *dev,
12046                   struct mlx5_flow *dev_flow,
12047                   const struct rte_flow_attr *attr,
12048                   const struct rte_flow_item items[],
12049                   const struct rte_flow_action actions[],
12050                   struct rte_flow_error *error)
12051 {
12052         int ret;
12053
12054         flow_dv_shared_lock(dev);
12055         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
12056         flow_dv_shared_unlock(dev);
12057         return ret;
12058 }
12059
12060 /*
12061  * Mutex-protected thunk to lock-free  __flow_dv_apply().
12062  */
12063 static int
12064 flow_dv_apply(struct rte_eth_dev *dev,
12065               struct rte_flow *flow,
12066               struct rte_flow_error *error)
12067 {
12068         int ret;
12069
12070         flow_dv_shared_lock(dev);
12071         ret = __flow_dv_apply(dev, flow, error);
12072         flow_dv_shared_unlock(dev);
12073         return ret;
12074 }
12075
12076 /*
12077  * Mutex-protected thunk to lock-free __flow_dv_remove().
12078  */
12079 static void
12080 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12081 {
12082         flow_dv_shared_lock(dev);
12083         __flow_dv_remove(dev, flow);
12084         flow_dv_shared_unlock(dev);
12085 }
12086
12087 /*
12088  * Mutex-protected thunk to lock-free __flow_dv_destroy().
12089  */
12090 static void
12091 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12092 {
12093         flow_dv_shared_lock(dev);
12094         __flow_dv_destroy(dev, flow);
12095         flow_dv_shared_unlock(dev);
12096 }
12097
12098 /*
12099  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12100  */
12101 static uint32_t
12102 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12103 {
12104         uint32_t cnt;
12105
12106         flow_dv_shared_lock(dev);
12107         cnt = flow_dv_counter_alloc(dev, 0);
12108         flow_dv_shared_unlock(dev);
12109         return cnt;
12110 }
12111
12112 /*
12113  * Mutex-protected thunk to lock-free flow_dv_counter_release().
12114  */
12115 static void
12116 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
12117 {
12118         flow_dv_shared_lock(dev);
12119         flow_dv_counter_release(dev, cnt);
12120         flow_dv_shared_unlock(dev);
12121 }
12122
12123 /**
12124  * Validate shared action.
12125  * Dispatcher for action type specific validation.
12126  *
12127  * @param[in] dev
12128  *   Pointer to the Ethernet device structure.
12129  * @param[in] conf
12130  *   Shared action configuration.
12131  * @param[in] action
12132  *   The shared action object to validate.
12133  * @param[out] error
12134  *   Perform verbose error reporting if not NULL. Initialized in case of
12135  *   error only.
12136  *
12137  * @return
12138  *   0 on success, otherwise negative errno value.
12139  */
12140 static int
12141 flow_dv_action_validate(struct rte_eth_dev *dev,
12142                         const struct rte_flow_shared_action_conf *conf,
12143                         const struct rte_flow_action *action,
12144                         struct rte_flow_error *error)
12145 {
12146         RTE_SET_USED(conf);
12147         switch (action->type) {
12148         case RTE_FLOW_ACTION_TYPE_RSS:
12149                 return mlx5_validate_action_rss(dev, action, error);
12150         default:
12151                 return rte_flow_error_set(error, ENOTSUP,
12152                                           RTE_FLOW_ERROR_TYPE_ACTION,
12153                                           NULL,
12154                                           "action type not supported");
12155         }
12156 }
12157
12158 /*
12159  * Mutex-protected thunk to lock-free  __flow_dv_action_create().
12160  */
12161 static struct rte_flow_shared_action *
12162 flow_dv_action_create(struct rte_eth_dev *dev,
12163                       const struct rte_flow_shared_action_conf *conf,
12164                       const struct rte_flow_action *action,
12165                       struct rte_flow_error *error)
12166 {
12167         struct rte_flow_shared_action *shared_action = NULL;
12168
12169         flow_dv_shared_lock(dev);
12170         shared_action = __flow_dv_action_create(dev, conf, action, error);
12171         flow_dv_shared_unlock(dev);
12172         return shared_action;
12173 }
12174
12175 /*
12176  * Mutex-protected thunk to lock-free  __flow_dv_action_destroy().
12177  */
12178 static int
12179 flow_dv_action_destroy(struct rte_eth_dev *dev,
12180                        struct rte_flow_shared_action *action,
12181                        struct rte_flow_error *error)
12182 {
12183         int ret;
12184
12185         flow_dv_shared_lock(dev);
12186         ret = __flow_dv_action_destroy(dev, action, error);
12187         flow_dv_shared_unlock(dev);
12188         return ret;
12189 }
12190
12191 /*
12192  * Mutex-protected thunk to lock-free  __flow_dv_action_update().
12193  */
12194 static int
12195 flow_dv_action_update(struct rte_eth_dev *dev,
12196                       struct rte_flow_shared_action *action,
12197                       const void *action_conf,
12198                       struct rte_flow_error *error)
12199 {
12200         int ret;
12201
12202         flow_dv_shared_lock(dev);
12203         ret = __flow_dv_action_update(dev, action, action_conf,
12204                                       error);
12205         flow_dv_shared_unlock(dev);
12206         return ret;
12207 }
12208
12209 static int
12210 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12211 {
12212         struct mlx5_priv *priv = dev->data->dev_private;
12213         int ret = 0;
12214
12215         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12216                 ret = mlx5_glue->dr_sync_domain(priv->sh->rx_domain,
12217                                                 flags);
12218                 if (ret != 0)
12219                         return ret;
12220         }
12221         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12222                 ret = mlx5_glue->dr_sync_domain(priv->sh->tx_domain, flags);
12223                 if (ret != 0)
12224                         return ret;
12225         }
12226         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12227                 ret = mlx5_glue->dr_sync_domain(priv->sh->fdb_domain, flags);
12228                 if (ret != 0)
12229                         return ret;
12230         }
12231         return 0;
12232 }
12233
12234 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12235         .validate = flow_dv_validate,
12236         .prepare = flow_dv_prepare,
12237         .translate = flow_dv_translate,
12238         .apply = flow_dv_apply,
12239         .remove = flow_dv_remove,
12240         .destroy = flow_dv_destroy,
12241         .query = flow_dv_query,
12242         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12243         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12244         .create_policer_rules = flow_dv_create_policer_rules,
12245         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12246         .counter_alloc = flow_dv_counter_allocate,
12247         .counter_free = flow_dv_counter_free,
12248         .counter_query = flow_dv_counter_query,
12249         .get_aged_flows = flow_get_aged_flows,
12250         .action_validate = flow_dv_action_validate,
12251         .action_create = flow_dv_action_create,
12252         .action_destroy = flow_dv_action_destroy,
12253         .action_update = flow_dv_action_update,
12254         .sync_domain = flow_dv_sync_domain,
12255 };
12256
12257 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12258