drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30 #include <rte_gtp.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34 #include <mlx5_prm.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_flow.h"
  39 #include "mlx5_rxtx.h"
  40
  41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  42
  43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  45 #endif
  46
  47 #ifndef HAVE_MLX5DV_DR_ESWITCH
  48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  50 #endif
  51 #endif
  52
  53 #ifndef HAVE_MLX5DV_DR
  54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  55 #endif
  56
  57 /* VLAN header definitions */
  58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  63
  64 union flow_dv_attr {
  65         struct {
  66                 uint32_t valid:1;
  67                 uint32_t ipv4:1;
  68                 uint32_t ipv6:1;
  69                 uint32_t tcp:1;
  70                 uint32_t udp:1;
  71                 uint32_t reserved:27;
  72         };
  73         uint32_t attr;
  74 };
  75
  76 static int
  77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  78                              struct mlx5_flow_tbl_resource *tbl);
  79
  80 /**
  81  * Initialize flow attributes structure according to flow items' types.
  82  *
  83  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  84  * mode. For tunnel mode, the items to be modified are the outermost ones.
  85  *
  86  * @param[in] item
  87  *   Pointer to item specification.
  88  * @param[out] attr
  89  *   Pointer to flow attributes structure.
  90  * @param[in] dev_flow
  91  *   Pointer to the sub flow.
  92  * @param[in] tunnel_decap
  93  *   Whether action is after tunnel decapsulation.
  94  */
  95 static void
  96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  97                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  98 {
  99         uint64_t layers = dev_flow->handle->layers;
 100
 101         /*
 102          * If layers is already initialized, it means this dev_flow is the
 103          * suffix flow, the layers flags is set by the prefix flow. Need to
 104          * use the layer flags from prefix flow as the suffix flow may not
 105          * have the user defined items as the flow is split.
 106          */
 107         if (layers) {
 108                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 109                         attr->ipv4 = 1;
 110                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 111                         attr->ipv6 = 1;
 112                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 113                         attr->tcp = 1;
 114                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 115                         attr->udp = 1;
 116                 attr->valid = 1;
 117                 return;
 118         }
 119         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 120                 uint8_t next_protocol = 0xff;
 121                 switch (item->type) {
 122                 case RTE_FLOW_ITEM_TYPE_GRE:
 123                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 124                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 126                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 127                 case RTE_FLOW_ITEM_TYPE_MPLS:
 128                         if (tunnel_decap)
 129                                 attr->attr = 0;
 130                         break;
 131                 case RTE_FLOW_ITEM_TYPE_IPV4:
 132                         if (!attr->ipv6)
 133                                 attr->ipv4 = 1;
 134                         if (item->mask != NULL &&
 135                             ((const struct rte_flow_item_ipv4 *)
 136                             item->mask)->hdr.next_proto_id)
 137                                 next_protocol =
 138                                     ((const struct rte_flow_item_ipv4 *)
 139                                       (item->spec))->hdr.next_proto_id &
 140                                     ((const struct rte_flow_item_ipv4 *)
 141                                       (item->mask))->hdr.next_proto_id;
 142                         if ((next_protocol == IPPROTO_IPIP ||
 143                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 144                                 attr->attr = 0;
 145                         break;
 146                 case RTE_FLOW_ITEM_TYPE_IPV6:
 147                         if (!attr->ipv4)
 148                                 attr->ipv6 = 1;
 149                         if (item->mask != NULL &&
 150                             ((const struct rte_flow_item_ipv6 *)
 151                             item->mask)->hdr.proto)
 152                                 next_protocol =
 153                                     ((const struct rte_flow_item_ipv6 *)
 154                                       (item->spec))->hdr.proto &
 155                                     ((const struct rte_flow_item_ipv6 *)
 156                                       (item->mask))->hdr.proto;
 157                         if ((next_protocol == IPPROTO_IPIP ||
 158                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 159                                 attr->attr = 0;
 160                         break;
 161                 case RTE_FLOW_ITEM_TYPE_UDP:
 162                         if (!attr->tcp)
 163                                 attr->udp = 1;
 164                         break;
 165                 case RTE_FLOW_ITEM_TYPE_TCP:
 166                         if (!attr->udp)
 167                                 attr->tcp = 1;
 168                         break;
 169                 default:
 170                         break;
 171                 }
 172         }
 173         attr->valid = 1;
 174 }
 175
 176 /**
 177  * Convert rte_mtr_color to mlx5 color.
 178  *
 179  * @param[in] rcol
 180  *   rte_mtr_color.
 181  *
 182  * @return
 183  *   mlx5 color.
 184  */
 185 static int
 186 rte_col_2_mlx5_col(enum rte_color rcol)
 187 {
 188         switch (rcol) {
 189         case RTE_COLOR_GREEN:
 190                 return MLX5_FLOW_COLOR_GREEN;
 191         case RTE_COLOR_YELLOW:
 192                 return MLX5_FLOW_COLOR_YELLOW;
 193         case RTE_COLOR_RED:
 194                 return MLX5_FLOW_COLOR_RED;
 195         default:
 196                 break;
 197         }
 198         return MLX5_FLOW_COLOR_UNDEFINED;
 199 }
 200
 201 struct field_modify_info {
 202         uint32_t size; /* Size of field in protocol header, in bytes. */
 203         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 204         enum mlx5_modification_field id;
 205 };
 206
 207 struct field_modify_info modify_eth[] = {
 208         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 209         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 210         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 211         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 212         {0, 0, 0},
 213 };
 214
 215 struct field_modify_info modify_vlan_out_first_vid[] = {
 216         /* Size in bits !!! */
 217         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 218         {0, 0, 0},
 219 };
 220
 221 struct field_modify_info modify_ipv4[] = {
 222         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 223         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 224         {4, 12, MLX5_MODI_OUT_SIPV4},
 225         {4, 16, MLX5_MODI_OUT_DIPV4},
 226         {0, 0, 0},
 227 };
 228
 229 struct field_modify_info modify_ipv6[] = {
 230         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 231         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 232         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 233         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 234         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 235         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 236         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 237         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 238         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 239         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 240         {0, 0, 0},
 241 };
 242
 243 struct field_modify_info modify_udp[] = {
 244         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 245         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 246         {0, 0, 0},
 247 };
 248
 249 struct field_modify_info modify_tcp[] = {
 250         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 251         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 252         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 253         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 254         {0, 0, 0},
 255 };
 256
 257 static void
 258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 259                           uint8_t next_protocol, uint64_t *item_flags,
 260                           int *tunnel)
 261 {
 262         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 263                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 264         if (next_protocol == IPPROTO_IPIP) {
 265                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 266                 *tunnel = 1;
 267         }
 268         if (next_protocol == IPPROTO_IPV6) {
 269                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 270                 *tunnel = 1;
 271         }
 272 }
 273
 274 /**
 275  * Acquire the synchronizing object to protect multithreaded access
 276  * to shared dv context. Lock occurs only if context is actually
 277  * shared, i.e. we have multiport IB device and representors are
 278  * created.
 279  *
 280  * @param[in] dev
 281  *   Pointer to the rte_eth_dev structure.
 282  */
 283 static void
 284 flow_dv_shared_lock(struct rte_eth_dev *dev)
 285 {
 286         struct mlx5_priv *priv = dev->data->dev_private;
 287         struct mlx5_ibv_shared *sh = priv->sh;
 288
 289         if (sh->dv_refcnt > 1) {
 290                 int ret;
 291
 292                 ret = pthread_mutex_lock(&sh->dv_mutex);
 293                 MLX5_ASSERT(!ret);
 294                 (void)ret;
 295         }
 296 }
 297
 298 static void
 299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 300 {
 301         struct mlx5_priv *priv = dev->data->dev_private;
 302         struct mlx5_ibv_shared *sh = priv->sh;
 303
 304         if (sh->dv_refcnt > 1) {
 305                 int ret;
 306
 307                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 308                 MLX5_ASSERT(!ret);
 309                 (void)ret;
 310         }
 311 }
 312
 313 /* Update VLAN's VID/PCP based on input rte_flow_action.
 314  *
 315  * @param[in] action
 316  *   Pointer to struct rte_flow_action.
 317  * @param[out] vlan
 318  *   Pointer to struct rte_vlan_hdr.
 319  */
 320 static void
 321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 322                          struct rte_vlan_hdr *vlan)
 323 {
 324         uint16_t vlan_tci;
 325         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 326                 vlan_tci =
 327                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 328                                                action->conf)->vlan_pcp;
 329                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 330                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 331                 vlan->vlan_tci |= vlan_tci;
 332         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 333                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 334                 vlan->vlan_tci |= rte_be_to_cpu_16
 335                     (((const struct rte_flow_action_of_set_vlan_vid *)
 336                                              action->conf)->vlan_vid);
 337         }
 338 }
 339
 340 /**
 341  * Fetch 1, 2, 3 or 4 byte field from the byte array
 342  * and return as unsigned integer in host-endian format.
 343  *
 344  * @param[in] data
 345  *   Pointer to data array.
 346  * @param[in] size
 347  *   Size of field to extract.
 348  *
 349  * @return
 350  *   converted field in host endian format.
 351  */
 352 static inline uint32_t
 353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 354 {
 355         uint32_t ret;
 356
 357         switch (size) {
 358         case 1:
 359                 ret = *data;
 360                 break;
 361         case 2:
 362                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 363                 break;
 364         case 3:
 365                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 366                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 367                 break;
 368         case 4:
 369                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 370                 break;
 371         default:
 372                 MLX5_ASSERT(false);
 373                 ret = 0;
 374                 break;
 375         }
 376         return ret;
 377 }
 378
 379 /**
 380  * Convert modify-header action to DV specification.
 381  *
 382  * Data length of each action is determined by provided field description
 383  * and the item mask. Data bit offset and width of each action is determined
 384  * by provided item mask.
 385  *
 386  * @param[in] item
 387  *   Pointer to item specification.
 388  * @param[in] field
 389  *   Pointer to field modification information.
 390  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 391  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 393  * @param[in] dcopy
 394  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 395  *   Negative offset value sets the same offset as source offset.
 396  *   size field is ignored, value is taken from source field.
 397  * @param[in,out] resource
 398  *   Pointer to the modify-header resource.
 399  * @param[in] type
 400  *   Type of modification.
 401  * @param[out] error
 402  *   Pointer to the error structure.
 403  *
 404  * @return
 405  *   0 on success, a negative errno value otherwise and rte_errno is set.
 406  */
 407 static int
 408 flow_dv_convert_modify_action(struct rte_flow_item *item,
 409                               struct field_modify_info *field,
 410                               struct field_modify_info *dcopy,
 411                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 412                               uint32_t type, struct rte_flow_error *error)
 413 {
 414         uint32_t i = resource->actions_num;
 415         struct mlx5_modification_cmd *actions = resource->actions;
 416
 417         /*
 418          * The item and mask are provided in big-endian format.
 419          * The fields should be presented as in big-endian format either.
 420          * Mask must be always present, it defines the actual field width.
 421          */
 422         MLX5_ASSERT(item->mask);
 423         MLX5_ASSERT(field->size);
 424         do {
 425                 unsigned int size_b;
 426                 unsigned int off_b;
 427                 uint32_t mask;
 428                 uint32_t data;
 429
 430                 if (i >= MLX5_MAX_MODIFY_NUM)
 431                         return rte_flow_error_set(error, EINVAL,
 432                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 433                                  "too many items to modify");
 434                 /* Fetch variable byte size mask from the array. */
 435                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 436                                            field->offset, field->size);
 437                 MLX5_ASSERT(mask);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /**
1643  * Validate GTP item.
1644  *
1645  * @param[in] dev
1646  *   Pointer to the rte_eth_dev structure.
1647  * @param[in] item
1648  *   Item specification.
1649  * @param[in] item_flags
1650  *   Bit-fields that holds the items detected until now.
1651  * @param[out] error
1652  *   Pointer to error structure.
1653  *
1654  * @return
1655  *   0 on success, a negative errno value otherwise and rte_errno is set.
1656  */
1657 static int
1658 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1659                           const struct rte_flow_item *item,
1660                           uint64_t item_flags,
1661                           struct rte_flow_error *error)
1662 {
1663         struct mlx5_priv *priv = dev->data->dev_private;
1664         const struct rte_flow_item_gtp *mask = item->mask;
1665         const struct rte_flow_item_gtp nic_mask = {
1666                 .msg_type = 0xff,
1667                 .teid = RTE_BE32(0xffffffff),
1668         };
1669
1670         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1671                 return rte_flow_error_set(error, ENOTSUP,
1672                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1673                                           "GTP support is not enabled");
1674         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1675                 return rte_flow_error_set(error, ENOTSUP,
1676                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1677                                           "multiple tunnel layers not"
1678                                           " supported");
1679         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1680                 return rte_flow_error_set(error, EINVAL,
1681                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1682                                           "no outer UDP layer found");
1683         if (!mask)
1684                 mask = &rte_flow_item_gtp_mask;
1685         return mlx5_flow_item_acceptable
1686                 (item, (const uint8_t *)mask,
1687                  (const uint8_t *)&nic_mask,
1688                  sizeof(struct rte_flow_item_gtp),
1689                  error);
1690 }
1691
1692 /**
1693  * Validate the pop VLAN action.
1694  *
1695  * @param[in] dev
1696  *   Pointer to the rte_eth_dev structure.
1697  * @param[in] action_flags
1698  *   Holds the actions detected until now.
1699  * @param[in] action
1700  *   Pointer to the pop vlan action.
1701  * @param[in] item_flags
1702  *   The items found in this flow rule.
1703  * @param[in] attr
1704  *   Pointer to flow attributes.
1705  * @param[out] error
1706  *   Pointer to error structure.
1707  *
1708  * @return
1709  *   0 on success, a negative errno value otherwise and rte_errno is set.
1710  */
1711 static int
1712 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1713                                  uint64_t action_flags,
1714                                  const struct rte_flow_action *action,
1715                                  uint64_t item_flags,
1716                                  const struct rte_flow_attr *attr,
1717                                  struct rte_flow_error *error)
1718 {
1719         const struct mlx5_priv *priv = dev->data->dev_private;
1720
1721         (void)action;
1722         (void)attr;
1723         if (!priv->sh->pop_vlan_action)
1724                 return rte_flow_error_set(error, ENOTSUP,
1725                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1726                                           NULL,
1727                                           "pop vlan action is not supported");
1728         if (attr->egress)
1729                 return rte_flow_error_set(error, ENOTSUP,
1730                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1731                                           NULL,
1732                                           "pop vlan action not supported for "
1733                                           "egress");
1734         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1735                 return rte_flow_error_set(error, ENOTSUP,
1736                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1737                                           "no support for multiple VLAN "
1738                                           "actions");
1739         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1740                 return rte_flow_error_set(error, ENOTSUP,
1741                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1742                                           NULL,
1743                                           "cannot pop vlan without a "
1744                                           "match on (outer) vlan in the flow");
1745         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1746                 return rte_flow_error_set(error, EINVAL,
1747                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1748                                           "wrong action order, port_id should "
1749                                           "be after pop VLAN action");
1750         if (!attr->transfer && priv->representor)
1751                 return rte_flow_error_set(error, ENOTSUP,
1752                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1753                                           "pop vlan action for VF representor "
1754                                           "not supported on NIC table");
1755         return 0;
1756 }
1757
1758 /**
1759  * Get VLAN default info from vlan match info.
1760  *
1761  * @param[in] items
1762  *   the list of item specifications.
1763  * @param[out] vlan
1764  *   pointer VLAN info to fill to.
1765  *
1766  * @return
1767  *   0 on success, a negative errno value otherwise and rte_errno is set.
1768  */
1769 static void
1770 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1771                                   struct rte_vlan_hdr *vlan)
1772 {
1773         const struct rte_flow_item_vlan nic_mask = {
1774                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1775                                 MLX5DV_FLOW_VLAN_VID_MASK),
1776                 .inner_type = RTE_BE16(0xffff),
1777         };
1778
1779         if (items == NULL)
1780                 return;
1781         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1782                 int type = items->type;
1783
1784                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1785                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1786                         break;
1787         }
1788         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1789                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1790                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1791
1792                 if (!vlan_m)
1793                         vlan_m = &nic_mask;
1794                 /* Only full match values are accepted */
1795                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1796                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1797                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1798                         vlan->vlan_tci |=
1799                                 rte_be_to_cpu_16(vlan_v->tci &
1800                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1801                 }
1802                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1803                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1804                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1805                         vlan->vlan_tci |=
1806                                 rte_be_to_cpu_16(vlan_v->tci &
1807                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1808                 }
1809                 if (vlan_m->inner_type == nic_mask.inner_type)
1810                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1811                                                            vlan_m->inner_type);
1812         }
1813 }
1814
1815 /**
1816  * Validate the push VLAN action.
1817  *
1818  * @param[in] dev
1819  *   Pointer to the rte_eth_dev structure.
1820  * @param[in] action_flags
1821  *   Holds the actions detected until now.
1822  * @param[in] item_flags
1823  *   The items found in this flow rule.
1824  * @param[in] action
1825  *   Pointer to the action structure.
1826  * @param[in] attr
1827  *   Pointer to flow attributes
1828  * @param[out] error
1829  *   Pointer to error structure.
1830  *
1831  * @return
1832  *   0 on success, a negative errno value otherwise and rte_errno is set.
1833  */
1834 static int
1835 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1836                                   uint64_t action_flags,
1837                                   const struct rte_flow_item_vlan *vlan_m,
1838                                   const struct rte_flow_action *action,
1839                                   const struct rte_flow_attr *attr,
1840                                   struct rte_flow_error *error)
1841 {
1842         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1843         const struct mlx5_priv *priv = dev->data->dev_private;
1844
1845         if (!attr->transfer && attr->ingress)
1846                 return rte_flow_error_set(error, ENOTSUP,
1847                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1848                                           NULL,
1849                                           "push VLAN action not supported for "
1850                                           "ingress");
1851         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1852             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1853                 return rte_flow_error_set(error, EINVAL,
1854                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1855                                           "invalid vlan ethertype");
1856         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1857                 return rte_flow_error_set(error, ENOTSUP,
1858                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1859                                           "no support for multiple VLAN "
1860                                           "actions");
1861         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1862                 return rte_flow_error_set(error, EINVAL,
1863                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1864                                           "wrong action order, port_id should "
1865                                           "be after push VLAN");
1866         if (!attr->transfer && priv->representor)
1867                 return rte_flow_error_set(error, ENOTSUP,
1868                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1869                                           "push vlan action for VF representor "
1870                                           "not supported on NIC table");
1871         if (vlan_m &&
1872             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1873             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1874                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1875             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1876             !(mlx5_flow_find_action
1877                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1878                 return rte_flow_error_set(error, EINVAL,
1879                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1880                                           "not full match mask on VLAN PCP and "
1881                                           "there is no of_set_vlan_pcp action, "
1882                                           "push VLAN action cannot figure out "
1883                                           "PCP value");
1884         if (vlan_m &&
1885             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1886             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1887                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1888             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1889             !(mlx5_flow_find_action
1890                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1891                 return rte_flow_error_set(error, EINVAL,
1892                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1893                                           "not full match mask on VLAN VID and "
1894                                           "there is no of_set_vlan_vid action, "
1895                                           "push VLAN action cannot figure out "
1896                                           "VID value");
1897         (void)attr;
1898         return 0;
1899 }
1900
1901 /**
1902  * Validate the set VLAN PCP.
1903  *
1904  * @param[in] action_flags
1905  *   Holds the actions detected until now.
1906  * @param[in] actions
1907  *   Pointer to the list of actions remaining in the flow rule.
1908  * @param[out] error
1909  *   Pointer to error structure.
1910  *
1911  * @return
1912  *   0 on success, a negative errno value otherwise and rte_errno is set.
1913  */
1914 static int
1915 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1916                                      const struct rte_flow_action actions[],
1917                                      struct rte_flow_error *error)
1918 {
1919         const struct rte_flow_action *action = actions;
1920         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1921
1922         if (conf->vlan_pcp > 7)
1923                 return rte_flow_error_set(error, EINVAL,
1924                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1925                                           "VLAN PCP value is too big");
1926         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1927                 return rte_flow_error_set(error, ENOTSUP,
1928                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1929                                           "set VLAN PCP action must follow "
1930                                           "the push VLAN action");
1931         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1932                 return rte_flow_error_set(error, ENOTSUP,
1933                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1934                                           "Multiple VLAN PCP modification are "
1935                                           "not supported");
1936         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1937                 return rte_flow_error_set(error, EINVAL,
1938                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1939                                           "wrong action order, port_id should "
1940                                           "be after set VLAN PCP");
1941         return 0;
1942 }
1943
1944 /**
1945  * Validate the set VLAN VID.
1946  *
1947  * @param[in] item_flags
1948  *   Holds the items detected in this rule.
1949  * @param[in] action_flags
1950  *   Holds the actions detected until now.
1951  * @param[in] actions
1952  *   Pointer to the list of actions remaining in the flow rule.
1953  * @param[out] error
1954  *   Pointer to error structure.
1955  *
1956  * @return
1957  *   0 on success, a negative errno value otherwise and rte_errno is set.
1958  */
1959 static int
1960 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1961                                      uint64_t action_flags,
1962                                      const struct rte_flow_action actions[],
1963                                      struct rte_flow_error *error)
1964 {
1965         const struct rte_flow_action *action = actions;
1966         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1967
1968         if (conf->vlan_vid > RTE_BE16(0xFFE))
1969                 return rte_flow_error_set(error, EINVAL,
1970                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1971                                           "VLAN VID value is too big");
1972         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1973             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1974                 return rte_flow_error_set(error, ENOTSUP,
1975                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1976                                           "set VLAN VID action must follow push"
1977                                           " VLAN action or match on VLAN item");
1978         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1979                 return rte_flow_error_set(error, ENOTSUP,
1980                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1981                                           "Multiple VLAN VID modifications are "
1982                                           "not supported");
1983         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1984                 return rte_flow_error_set(error, EINVAL,
1985                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1986                                           "wrong action order, port_id should "
1987                                           "be after set VLAN VID");
1988         return 0;
1989 }
1990
1991 /*
1992  * Validate the FLAG action.
1993  *
1994  * @param[in] dev
1995  *   Pointer to the rte_eth_dev structure.
1996  * @param[in] action_flags
1997  *   Holds the actions detected until now.
1998  * @param[in] attr
1999  *   Pointer to flow attributes
2000  * @param[out] error
2001  *   Pointer to error structure.
2002  *
2003  * @return
2004  *   0 on success, a negative errno value otherwise and rte_errno is set.
2005  */
2006 static int
2007 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2008                              uint64_t action_flags,
2009                              const struct rte_flow_attr *attr,
2010                              struct rte_flow_error *error)
2011 {
2012         struct mlx5_priv *priv = dev->data->dev_private;
2013         struct mlx5_dev_config *config = &priv->config;
2014         int ret;
2015
2016         /* Fall back if no extended metadata register support. */
2017         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2018                 return mlx5_flow_validate_action_flag(action_flags, attr,
2019                                                       error);
2020         /* Extensive metadata mode requires registers. */
2021         if (!mlx5_flow_ext_mreg_supported(dev))
2022                 return rte_flow_error_set(error, ENOTSUP,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2024                                           "no metadata registers "
2025                                           "to support flag action");
2026         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2027                 return rte_flow_error_set(error, ENOTSUP,
2028                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2029                                           "extended metadata register"
2030                                           " isn't available");
2031         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2032         if (ret < 0)
2033                 return ret;
2034         MLX5_ASSERT(ret > 0);
2035         if (action_flags & MLX5_FLOW_ACTION_MARK)
2036                 return rte_flow_error_set(error, EINVAL,
2037                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2038                                           "can't mark and flag in same flow");
2039         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2040                 return rte_flow_error_set(error, EINVAL,
2041                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2042                                           "can't have 2 flag"
2043                                           " actions in same flow");
2044         return 0;
2045 }
2046
2047 /**
2048  * Validate MARK action.
2049  *
2050  * @param[in] dev
2051  *   Pointer to the rte_eth_dev structure.
2052  * @param[in] action
2053  *   Pointer to action.
2054  * @param[in] action_flags
2055  *   Holds the actions detected until now.
2056  * @param[in] attr
2057  *   Pointer to flow attributes
2058  * @param[out] error
2059  *   Pointer to error structure.
2060  *
2061  * @return
2062  *   0 on success, a negative errno value otherwise and rte_errno is set.
2063  */
2064 static int
2065 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2066                              const struct rte_flow_action *action,
2067                              uint64_t action_flags,
2068                              const struct rte_flow_attr *attr,
2069                              struct rte_flow_error *error)
2070 {
2071         struct mlx5_priv *priv = dev->data->dev_private;
2072         struct mlx5_dev_config *config = &priv->config;
2073         const struct rte_flow_action_mark *mark = action->conf;
2074         int ret;
2075
2076         /* Fall back if no extended metadata register support. */
2077         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2078                 return mlx5_flow_validate_action_mark(action, action_flags,
2079                                                       attr, error);
2080         /* Extensive metadata mode requires registers. */
2081         if (!mlx5_flow_ext_mreg_supported(dev))
2082                 return rte_flow_error_set(error, ENOTSUP,
2083                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2084                                           "no metadata registers "
2085                                           "to support mark action");
2086         if (!priv->sh->dv_mark_mask)
2087                 return rte_flow_error_set(error, ENOTSUP,
2088                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2089                                           "extended metadata register"
2090                                           " isn't available");
2091         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2092         if (ret < 0)
2093                 return ret;
2094         MLX5_ASSERT(ret > 0);
2095         if (!mark)
2096                 return rte_flow_error_set(error, EINVAL,
2097                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2098                                           "configuration cannot be null");
2099         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2100                 return rte_flow_error_set(error, EINVAL,
2101                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2102                                           &mark->id,
2103                                           "mark id exceeds the limit");
2104         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2105                 return rte_flow_error_set(error, EINVAL,
2106                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2107                                           "can't flag and mark in same flow");
2108         if (action_flags & MLX5_FLOW_ACTION_MARK)
2109                 return rte_flow_error_set(error, EINVAL,
2110                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2111                                           "can't have 2 mark actions in same"
2112                                           " flow");
2113         return 0;
2114 }
2115
2116 /**
2117  * Validate SET_META action.
2118  *
2119  * @param[in] dev
2120  *   Pointer to the rte_eth_dev structure.
2121  * @param[in] action
2122  *   Pointer to the action structure.
2123  * @param[in] action_flags
2124  *   Holds the actions detected until now.
2125  * @param[in] attr
2126  *   Pointer to flow attributes
2127  * @param[out] error
2128  *   Pointer to error structure.
2129  *
2130  * @return
2131  *   0 on success, a negative errno value otherwise and rte_errno is set.
2132  */
2133 static int
2134 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2135                                  const struct rte_flow_action *action,
2136                                  uint64_t action_flags __rte_unused,
2137                                  const struct rte_flow_attr *attr,
2138                                  struct rte_flow_error *error)
2139 {
2140         const struct rte_flow_action_set_meta *conf;
2141         uint32_t nic_mask = UINT32_MAX;
2142         int reg;
2143
2144         if (!mlx5_flow_ext_mreg_supported(dev))
2145                 return rte_flow_error_set(error, ENOTSUP,
2146                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2147                                           "extended metadata register"
2148                                           " isn't supported");
2149         reg = flow_dv_get_metadata_reg(dev, attr, error);
2150         if (reg < 0)
2151                 return reg;
2152         if (reg != REG_A && reg != REG_B) {
2153                 struct mlx5_priv *priv = dev->data->dev_private;
2154
2155                 nic_mask = priv->sh->dv_meta_mask;
2156         }
2157         if (!(action->conf))
2158                 return rte_flow_error_set(error, EINVAL,
2159                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2160                                           "configuration cannot be null");
2161         conf = (const struct rte_flow_action_set_meta *)action->conf;
2162         if (!conf->mask)
2163                 return rte_flow_error_set(error, EINVAL,
2164                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2165                                           "zero mask doesn't have any effect");
2166         if (conf->mask & ~nic_mask)
2167                 return rte_flow_error_set(error, EINVAL,
2168                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2169                                           "meta data must be within reg C0");
2170         return 0;
2171 }
2172
2173 /**
2174  * Validate SET_TAG action.
2175  *
2176  * @param[in] dev
2177  *   Pointer to the rte_eth_dev structure.
2178  * @param[in] action
2179  *   Pointer to the action structure.
2180  * @param[in] action_flags
2181  *   Holds the actions detected until now.
2182  * @param[in] attr
2183  *   Pointer to flow attributes
2184  * @param[out] error
2185  *   Pointer to error structure.
2186  *
2187  * @return
2188  *   0 on success, a negative errno value otherwise and rte_errno is set.
2189  */
2190 static int
2191 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2192                                 const struct rte_flow_action *action,
2193                                 uint64_t action_flags,
2194                                 const struct rte_flow_attr *attr,
2195                                 struct rte_flow_error *error)
2196 {
2197         const struct rte_flow_action_set_tag *conf;
2198         const uint64_t terminal_action_flags =
2199                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2200                 MLX5_FLOW_ACTION_RSS;
2201         int ret;
2202
2203         if (!mlx5_flow_ext_mreg_supported(dev))
2204                 return rte_flow_error_set(error, ENOTSUP,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2206                                           "extensive metadata register"
2207                                           " isn't supported");
2208         if (!(action->conf))
2209                 return rte_flow_error_set(error, EINVAL,
2210                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2211                                           "configuration cannot be null");
2212         conf = (const struct rte_flow_action_set_tag *)action->conf;
2213         if (!conf->mask)
2214                 return rte_flow_error_set(error, EINVAL,
2215                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2216                                           "zero mask doesn't have any effect");
2217         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2218         if (ret < 0)
2219                 return ret;
2220         if (!attr->transfer && attr->ingress &&
2221             (action_flags & terminal_action_flags))
2222                 return rte_flow_error_set(error, EINVAL,
2223                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2224                                           "set_tag has no effect"
2225                                           " with terminal actions");
2226         return 0;
2227 }
2228
2229 /**
2230  * Validate count action.
2231  *
2232  * @param[in] dev
2233  *   Pointer to rte_eth_dev structure.
2234  * @param[out] error
2235  *   Pointer to error structure.
2236  *
2237  * @return
2238  *   0 on success, a negative errno value otherwise and rte_errno is set.
2239  */
2240 static int
2241 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2242                               struct rte_flow_error *error)
2243 {
2244         struct mlx5_priv *priv = dev->data->dev_private;
2245
2246         if (!priv->config.devx)
2247                 goto notsup_err;
2248 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2249         return 0;
2250 #endif
2251 notsup_err:
2252         return rte_flow_error_set
2253                       (error, ENOTSUP,
2254                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2255                        NULL,
2256                        "count action not supported");
2257 }
2258
2259 /**
2260  * Validate the L2 encap action.
2261  *
2262  * @param[in] dev
2263  *   Pointer to the rte_eth_dev structure.
2264  * @param[in] action_flags
2265  *   Holds the actions detected until now.
2266  * @param[in] action
2267  *   Pointer to the action structure.
2268  * @param[in] attr
2269  *   Pointer to flow attributes.
2270  * @param[out] error
2271  *   Pointer to error structure.
2272  *
2273  * @return
2274  *   0 on success, a negative errno value otherwise and rte_errno is set.
2275  */
2276 static int
2277 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2278                                  uint64_t action_flags,
2279                                  const struct rte_flow_action *action,
2280                                  const struct rte_flow_attr *attr,
2281                                  struct rte_flow_error *error)
2282 {
2283         const struct mlx5_priv *priv = dev->data->dev_private;
2284
2285         if (!(action->conf))
2286                 return rte_flow_error_set(error, EINVAL,
2287                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2288                                           "configuration cannot be null");
2289         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2290                 return rte_flow_error_set(error, EINVAL,
2291                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2292                                           "can only have a single encap action "
2293                                           "in a flow");
2294         if (!attr->transfer && priv->representor)
2295                 return rte_flow_error_set(error, ENOTSUP,
2296                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2297                                           "encap action for VF representor "
2298                                           "not supported on NIC table");
2299         return 0;
2300 }
2301
2302 /**
2303  * Validate a decap action.
2304  *
2305  * @param[in] dev
2306  *   Pointer to the rte_eth_dev structure.
2307  * @param[in] action_flags
2308  *   Holds the actions detected until now.
2309  * @param[in] attr
2310  *   Pointer to flow attributes
2311  * @param[out] error
2312  *   Pointer to error structure.
2313  *
2314  * @return
2315  *   0 on success, a negative errno value otherwise and rte_errno is set.
2316  */
2317 static int
2318 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2319                               uint64_t action_flags,
2320                               const struct rte_flow_attr *attr,
2321                               struct rte_flow_error *error)
2322 {
2323         const struct mlx5_priv *priv = dev->data->dev_private;
2324
2325         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2326                 return rte_flow_error_set(error, ENOTSUP,
2327                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2328                                           action_flags &
2329                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2330                                           "have a single decap action" : "decap "
2331                                           "after encap is not supported");
2332         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2333                 return rte_flow_error_set(error, EINVAL,
2334                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2335                                           "can't have decap action after"
2336                                           " modify action");
2337         if (attr->egress)
2338                 return rte_flow_error_set(error, ENOTSUP,
2339                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2340                                           NULL,
2341                                           "decap action not supported for "
2342                                           "egress");
2343         if (!attr->transfer && priv->representor)
2344                 return rte_flow_error_set(error, ENOTSUP,
2345                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2346                                           "decap action for VF representor "
2347                                           "not supported on NIC table");
2348         return 0;
2349 }
2350
2351 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2352
2353 /**
2354  * Validate the raw encap and decap actions.
2355  *
2356  * @param[in] dev
2357  *   Pointer to the rte_eth_dev structure.
2358  * @param[in] decap
2359  *   Pointer to the decap action.
2360  * @param[in] encap
2361  *   Pointer to the encap action.
2362  * @param[in] attr
2363  *   Pointer to flow attributes
2364  * @param[in/out] action_flags
2365  *   Holds the actions detected until now.
2366  * @param[out] actions_n
2367  *   pointer to the number of actions counter.
2368  * @param[out] error
2369  *   Pointer to error structure.
2370  *
2371  * @return
2372  *   0 on success, a negative errno value otherwise and rte_errno is set.
2373  */
2374 static int
2375 flow_dv_validate_action_raw_encap_decap
2376         (struct rte_eth_dev *dev,
2377          const struct rte_flow_action_raw_decap *decap,
2378          const struct rte_flow_action_raw_encap *encap,
2379          const struct rte_flow_attr *attr, uint64_t *action_flags,
2380          int *actions_n, struct rte_flow_error *error)
2381 {
2382         const struct mlx5_priv *priv = dev->data->dev_private;
2383         int ret;
2384
2385         if (encap && (!encap->size || !encap->data))
2386                 return rte_flow_error_set(error, EINVAL,
2387                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2388                                           "raw encap data cannot be empty");
2389         if (decap && encap) {
2390                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2391                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2392                         /* L3 encap. */
2393                         decap = NULL;
2394                 else if (encap->size <=
2395                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2396                            decap->size >
2397                            MLX5_ENCAPSULATION_DECISION_SIZE)
2398                         /* L3 decap. */
2399                         encap = NULL;
2400                 else if (encap->size >
2401                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2402                            decap->size >
2403                            MLX5_ENCAPSULATION_DECISION_SIZE)
2404                         /* 2 L2 actions: encap and decap. */
2405                         ;
2406                 else
2407                         return rte_flow_error_set(error,
2408                                 ENOTSUP,
2409                                 RTE_FLOW_ERROR_TYPE_ACTION,
2410                                 NULL, "unsupported too small "
2411                                 "raw decap and too small raw "
2412                                 "encap combination");
2413         }
2414         if (decap) {
2415                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2416                                                     error);
2417                 if (ret < 0)
2418                         return ret;
2419                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2420                 ++(*actions_n);
2421         }
2422         if (encap) {
2423                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2424                         return rte_flow_error_set(error, ENOTSUP,
2425                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2426                                                   NULL,
2427                                                   "small raw encap size");
2428                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2429                         return rte_flow_error_set(error, EINVAL,
2430                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2431                                                   NULL,
2432                                                   "more than one encap action");
2433                 if (!attr->transfer && priv->representor)
2434                         return rte_flow_error_set
2435                                         (error, ENOTSUP,
2436                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2437                                          "encap action for VF representor "
2438                                          "not supported on NIC table");
2439                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2440                 ++(*actions_n);
2441         }
2442         return 0;
2443 }
2444
2445 /**
2446  * Find existing encap/decap resource or create and register a new one.
2447  *
2448  * @param[in, out] dev
2449  *   Pointer to rte_eth_dev structure.
2450  * @param[in, out] resource
2451  *   Pointer to encap/decap resource.
2452  * @parm[in, out] dev_flow
2453  *   Pointer to the dev_flow.
2454  * @param[out] error
2455  *   pointer to error structure.
2456  *
2457  * @return
2458  *   0 on success otherwise -errno and errno is set.
2459  */
2460 static int
2461 flow_dv_encap_decap_resource_register
2462                         (struct rte_eth_dev *dev,
2463                          struct mlx5_flow_dv_encap_decap_resource *resource,
2464                          struct mlx5_flow *dev_flow,
2465                          struct rte_flow_error *error)
2466 {
2467         struct mlx5_priv *priv = dev->data->dev_private;
2468         struct mlx5_ibv_shared *sh = priv->sh;
2469         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2470         struct mlx5dv_dr_domain *domain;
2471         uint32_t idx = 0;
2472
2473         resource->flags = dev_flow->dv.group ? 0 : 1;
2474         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2475                 domain = sh->fdb_domain;
2476         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2477                 domain = sh->rx_domain;
2478         else
2479                 domain = sh->tx_domain;
2480         /* Lookup a matching resource from cache. */
2481         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2482                       cache_resource, next) {
2483                 if (resource->reformat_type == cache_resource->reformat_type &&
2484                     resource->ft_type == cache_resource->ft_type &&
2485                     resource->flags == cache_resource->flags &&
2486                     resource->size == cache_resource->size &&
2487                     !memcmp((const void *)resource->buf,
2488                             (const void *)cache_resource->buf,
2489                             resource->size)) {
2490                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2491                                 (void *)cache_resource,
2492                                 rte_atomic32_read(&cache_resource->refcnt));
2493                         rte_atomic32_inc(&cache_resource->refcnt);
2494                         dev_flow->handle->dvh.rix_encap_decap = idx;
2495                         dev_flow->dv.encap_decap = cache_resource;
2496                         return 0;
2497                 }
2498         }
2499         /* Register new encap/decap resource. */
2500         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2501                                        &dev_flow->handle->dvh.rix_encap_decap);
2502         if (!cache_resource)
2503                 return rte_flow_error_set(error, ENOMEM,
2504                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2505                                           "cannot allocate resource memory");
2506         *cache_resource = *resource;
2507         cache_resource->verbs_action =
2508                 mlx5_glue->dv_create_flow_action_packet_reformat
2509                         (sh->ctx, cache_resource->reformat_type,
2510                          cache_resource->ft_type, domain, cache_resource->flags,
2511                          cache_resource->size,
2512                          (cache_resource->size ? cache_resource->buf : NULL));
2513         if (!cache_resource->verbs_action) {
2514                 rte_free(cache_resource);
2515                 return rte_flow_error_set(error, ENOMEM,
2516                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2517                                           NULL, "cannot create action");
2518         }
2519         rte_atomic32_init(&cache_resource->refcnt);
2520         rte_atomic32_inc(&cache_resource->refcnt);
2521         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2522                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2523                      next);
2524         dev_flow->dv.encap_decap = cache_resource;
2525         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2526                 (void *)cache_resource,
2527                 rte_atomic32_read(&cache_resource->refcnt));
2528         return 0;
2529 }
2530
2531 /**
2532  * Find existing table jump resource or create and register a new one.
2533  *
2534  * @param[in, out] dev
2535  *   Pointer to rte_eth_dev structure.
2536  * @param[in, out] tbl
2537  *   Pointer to flow table resource.
2538  * @parm[in, out] dev_flow
2539  *   Pointer to the dev_flow.
2540  * @param[out] error
2541  *   pointer to error structure.
2542  *
2543  * @return
2544  *   0 on success otherwise -errno and errno is set.
2545  */
2546 static int
2547 flow_dv_jump_tbl_resource_register
2548                         (struct rte_eth_dev *dev __rte_unused,
2549                          struct mlx5_flow_tbl_resource *tbl,
2550                          struct mlx5_flow *dev_flow,
2551                          struct rte_flow_error *error)
2552 {
2553         struct mlx5_flow_tbl_data_entry *tbl_data =
2554                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2555         int cnt;
2556
2557         MLX5_ASSERT(tbl);
2558         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2559         if (!cnt) {
2560                 tbl_data->jump.action =
2561                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2562                         (tbl->obj);
2563                 if (!tbl_data->jump.action)
2564                         return rte_flow_error_set(error, ENOMEM,
2565                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2566                                         NULL, "cannot create jump action");
2567                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2568                         (void *)&tbl_data->jump, cnt);
2569         } else {
2570                 /* old jump should not make the table ref++. */
2571                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2572                 MLX5_ASSERT(tbl_data->jump.action);
2573                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2574                         (void *)&tbl_data->jump, cnt);
2575         }
2576         rte_atomic32_inc(&tbl_data->jump.refcnt);
2577         dev_flow->handle->rix_jump = tbl_data->idx;
2578         dev_flow->dv.jump = &tbl_data->jump;
2579         return 0;
2580 }
2581
2582 /**
2583  * Find existing table port ID resource or create and register a new one.
2584  *
2585  * @param[in, out] dev
2586  *   Pointer to rte_eth_dev structure.
2587  * @param[in, out] resource
2588  *   Pointer to port ID action resource.
2589  * @parm[in, out] dev_flow
2590  *   Pointer to the dev_flow.
2591  * @param[out] error
2592  *   pointer to error structure.
2593  *
2594  * @return
2595  *   0 on success otherwise -errno and errno is set.
2596  */
2597 static int
2598 flow_dv_port_id_action_resource_register
2599                         (struct rte_eth_dev *dev,
2600                          struct mlx5_flow_dv_port_id_action_resource *resource,
2601                          struct mlx5_flow *dev_flow,
2602                          struct rte_flow_error *error)
2603 {
2604         struct mlx5_priv *priv = dev->data->dev_private;
2605         struct mlx5_ibv_shared *sh = priv->sh;
2606         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2607         uint32_t idx = 0;
2608
2609         /* Lookup a matching resource from cache. */
2610         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2611                       idx, cache_resource, next) {
2612                 if (resource->port_id == cache_resource->port_id) {
2613                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2614                                 "refcnt %d++",
2615                                 (void *)cache_resource,
2616                                 rte_atomic32_read(&cache_resource->refcnt));
2617                         rte_atomic32_inc(&cache_resource->refcnt);
2618                         dev_flow->handle->rix_port_id_action = idx;
2619                         dev_flow->dv.port_id_action = cache_resource;
2620                         return 0;
2621                 }
2622         }
2623         /* Register new port id action resource. */
2624         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2625                                        &dev_flow->handle->rix_port_id_action);
2626         if (!cache_resource)
2627                 return rte_flow_error_set(error, ENOMEM,
2628                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2629                                           "cannot allocate resource memory");
2630         *cache_resource = *resource;
2631         /*
2632          * Depending on rdma_core version the glue routine calls
2633          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2634          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2635          */
2636         cache_resource->action =
2637                 mlx5_glue->dr_create_flow_action_dest_port
2638                         (priv->sh->fdb_domain, resource->port_id);
2639         if (!cache_resource->action) {
2640                 rte_free(cache_resource);
2641                 return rte_flow_error_set(error, ENOMEM,
2642                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2643                                           NULL, "cannot create action");
2644         }
2645         rte_atomic32_init(&cache_resource->refcnt);
2646         rte_atomic32_inc(&cache_resource->refcnt);
2647         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2648                      dev_flow->handle->rix_port_id_action, cache_resource,
2649                      next);
2650         dev_flow->dv.port_id_action = cache_resource;
2651         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2652                 (void *)cache_resource,
2653                 rte_atomic32_read(&cache_resource->refcnt));
2654         return 0;
2655 }
2656
2657 /**
2658  * Find existing push vlan resource or create and register a new one.
2659  *
2660  * @param [in, out] dev
2661  *   Pointer to rte_eth_dev structure.
2662  * @param[in, out] resource
2663  *   Pointer to port ID action resource.
2664  * @parm[in, out] dev_flow
2665  *   Pointer to the dev_flow.
2666  * @param[out] error
2667  *   pointer to error structure.
2668  *
2669  * @return
2670  *   0 on success otherwise -errno and errno is set.
2671  */
2672 static int
2673 flow_dv_push_vlan_action_resource_register
2674                        (struct rte_eth_dev *dev,
2675                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2676                         struct mlx5_flow *dev_flow,
2677                         struct rte_flow_error *error)
2678 {
2679         struct mlx5_priv *priv = dev->data->dev_private;
2680         struct mlx5_ibv_shared *sh = priv->sh;
2681         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2682         struct mlx5dv_dr_domain *domain;
2683         uint32_t idx = 0;
2684
2685         /* Lookup a matching resource from cache. */
2686         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2687                       sh->push_vlan_action_list, idx, cache_resource, next) {
2688                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2689                     resource->ft_type == cache_resource->ft_type) {
2690                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2691                                 "refcnt %d++",
2692                                 (void *)cache_resource,
2693                                 rte_atomic32_read(&cache_resource->refcnt));
2694                         rte_atomic32_inc(&cache_resource->refcnt);
2695                         dev_flow->handle->dvh.rix_push_vlan = idx;
2696                         dev_flow->dv.push_vlan_res = cache_resource;
2697                         return 0;
2698                 }
2699         }
2700         /* Register new push_vlan action resource. */
2701         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2702                                        &dev_flow->handle->dvh.rix_push_vlan);
2703         if (!cache_resource)
2704                 return rte_flow_error_set(error, ENOMEM,
2705                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2706                                           "cannot allocate resource memory");
2707         *cache_resource = *resource;
2708         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2709                 domain = sh->fdb_domain;
2710         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2711                 domain = sh->rx_domain;
2712         else
2713                 domain = sh->tx_domain;
2714         cache_resource->action =
2715                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2716                                                            resource->vlan_tag);
2717         if (!cache_resource->action) {
2718                 rte_free(cache_resource);
2719                 return rte_flow_error_set(error, ENOMEM,
2720                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2721                                           NULL, "cannot create action");
2722         }
2723         rte_atomic32_init(&cache_resource->refcnt);
2724         rte_atomic32_inc(&cache_resource->refcnt);
2725         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2726                      &sh->push_vlan_action_list,
2727                      dev_flow->handle->dvh.rix_push_vlan,
2728                      cache_resource, next);
2729         dev_flow->dv.push_vlan_res = cache_resource;
2730         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2731                 (void *)cache_resource,
2732                 rte_atomic32_read(&cache_resource->refcnt));
2733         return 0;
2734 }
2735 /**
2736  * Get the size of specific rte_flow_item_type
2737  *
2738  * @param[in] item_type
2739  *   Tested rte_flow_item_type.
2740  *
2741  * @return
2742  *   sizeof struct item_type, 0 if void or irrelevant.
2743  */
2744 static size_t
2745 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2746 {
2747         size_t retval;
2748
2749         switch (item_type) {
2750         case RTE_FLOW_ITEM_TYPE_ETH:
2751                 retval = sizeof(struct rte_flow_item_eth);
2752                 break;
2753         case RTE_FLOW_ITEM_TYPE_VLAN:
2754                 retval = sizeof(struct rte_flow_item_vlan);
2755                 break;
2756         case RTE_FLOW_ITEM_TYPE_IPV4:
2757                 retval = sizeof(struct rte_flow_item_ipv4);
2758                 break;
2759         case RTE_FLOW_ITEM_TYPE_IPV6:
2760                 retval = sizeof(struct rte_flow_item_ipv6);
2761                 break;
2762         case RTE_FLOW_ITEM_TYPE_UDP:
2763                 retval = sizeof(struct rte_flow_item_udp);
2764                 break;
2765         case RTE_FLOW_ITEM_TYPE_TCP:
2766                 retval = sizeof(struct rte_flow_item_tcp);
2767                 break;
2768         case RTE_FLOW_ITEM_TYPE_VXLAN:
2769                 retval = sizeof(struct rte_flow_item_vxlan);
2770                 break;
2771         case RTE_FLOW_ITEM_TYPE_GRE:
2772                 retval = sizeof(struct rte_flow_item_gre);
2773                 break;
2774         case RTE_FLOW_ITEM_TYPE_NVGRE:
2775                 retval = sizeof(struct rte_flow_item_nvgre);
2776                 break;
2777         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2778                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2779                 break;
2780         case RTE_FLOW_ITEM_TYPE_MPLS:
2781                 retval = sizeof(struct rte_flow_item_mpls);
2782                 break;
2783         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2784         default:
2785                 retval = 0;
2786                 break;
2787         }
2788         return retval;
2789 }
2790
2791 #define MLX5_ENCAP_IPV4_VERSION         0x40
2792 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2793 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2794 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2795 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2796 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2797 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2798
2799 /**
2800  * Convert the encap action data from list of rte_flow_item to raw buffer
2801  *
2802  * @param[in] items
2803  *   Pointer to rte_flow_item objects list.
2804  * @param[out] buf
2805  *   Pointer to the output buffer.
2806  * @param[out] size
2807  *   Pointer to the output buffer size.
2808  * @param[out] error
2809  *   Pointer to the error structure.
2810  *
2811  * @return
2812  *   0 on success, a negative errno value otherwise and rte_errno is set.
2813  */
2814 static int
2815 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2816                            size_t *size, struct rte_flow_error *error)
2817 {
2818         struct rte_ether_hdr *eth = NULL;
2819         struct rte_vlan_hdr *vlan = NULL;
2820         struct rte_ipv4_hdr *ipv4 = NULL;
2821         struct rte_ipv6_hdr *ipv6 = NULL;
2822         struct rte_udp_hdr *udp = NULL;
2823         struct rte_vxlan_hdr *vxlan = NULL;
2824         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2825         struct rte_gre_hdr *gre = NULL;
2826         size_t len;
2827         size_t temp_size = 0;
2828
2829         if (!items)
2830                 return rte_flow_error_set(error, EINVAL,
2831                                           RTE_FLOW_ERROR_TYPE_ACTION,
2832                                           NULL, "invalid empty data");
2833         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2834                 len = flow_dv_get_item_len(items->type);
2835                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2836                         return rte_flow_error_set(error, EINVAL,
2837                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2838                                                   (void *)items->type,
2839                                                   "items total size is too big"
2840                                                   " for encap action");
2841                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2842                 switch (items->type) {
2843                 case RTE_FLOW_ITEM_TYPE_ETH:
2844                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2845                         break;
2846                 case RTE_FLOW_ITEM_TYPE_VLAN:
2847                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2848                         if (!eth)
2849                                 return rte_flow_error_set(error, EINVAL,
2850                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2851                                                 (void *)items->type,
2852                                                 "eth header not found");
2853                         if (!eth->ether_type)
2854                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2855                         break;
2856                 case RTE_FLOW_ITEM_TYPE_IPV4:
2857                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2858                         if (!vlan && !eth)
2859                                 return rte_flow_error_set(error, EINVAL,
2860                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2861                                                 (void *)items->type,
2862                                                 "neither eth nor vlan"
2863                                                 " header found");
2864                         if (vlan && !vlan->eth_proto)
2865                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2866                         else if (eth && !eth->ether_type)
2867                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2868                         if (!ipv4->version_ihl)
2869                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2870                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2871                         if (!ipv4->time_to_live)
2872                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2873                         break;
2874                 case RTE_FLOW_ITEM_TYPE_IPV6:
2875                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2876                         if (!vlan && !eth)
2877                                 return rte_flow_error_set(error, EINVAL,
2878                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2879                                                 (void *)items->type,
2880                                                 "neither eth nor vlan"
2881                                                 " header found");
2882                         if (vlan && !vlan->eth_proto)
2883                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2884                         else if (eth && !eth->ether_type)
2885                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2886                         if (!ipv6->vtc_flow)
2887                                 ipv6->vtc_flow =
2888                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2889                         if (!ipv6->hop_limits)
2890                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2891                         break;
2892                 case RTE_FLOW_ITEM_TYPE_UDP:
2893                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2894                         if (!ipv4 && !ipv6)
2895                                 return rte_flow_error_set(error, EINVAL,
2896                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2897                                                 (void *)items->type,
2898                                                 "ip header not found");
2899                         if (ipv4 && !ipv4->next_proto_id)
2900                                 ipv4->next_proto_id = IPPROTO_UDP;
2901                         else if (ipv6 && !ipv6->proto)
2902                                 ipv6->proto = IPPROTO_UDP;
2903                         break;
2904                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2905                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2906                         if (!udp)
2907                                 return rte_flow_error_set(error, EINVAL,
2908                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2909                                                 (void *)items->type,
2910                                                 "udp header not found");
2911                         if (!udp->dst_port)
2912                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2913                         if (!vxlan->vx_flags)
2914                                 vxlan->vx_flags =
2915                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2916                         break;
2917                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2918                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2919                         if (!udp)
2920                                 return rte_flow_error_set(error, EINVAL,
2921                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2922                                                 (void *)items->type,
2923                                                 "udp header not found");
2924                         if (!vxlan_gpe->proto)
2925                                 return rte_flow_error_set(error, EINVAL,
2926                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2927                                                 (void *)items->type,
2928                                                 "next protocol not found");
2929                         if (!udp->dst_port)
2930                                 udp->dst_port =
2931                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2932                         if (!vxlan_gpe->vx_flags)
2933                                 vxlan_gpe->vx_flags =
2934                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2935                         break;
2936                 case RTE_FLOW_ITEM_TYPE_GRE:
2937                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2938                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2939                         if (!gre->proto)
2940                                 return rte_flow_error_set(error, EINVAL,
2941                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2942                                                 (void *)items->type,
2943                                                 "next protocol not found");
2944                         if (!ipv4 && !ipv6)
2945                                 return rte_flow_error_set(error, EINVAL,
2946                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2947                                                 (void *)items->type,
2948                                                 "ip header not found");
2949                         if (ipv4 && !ipv4->next_proto_id)
2950                                 ipv4->next_proto_id = IPPROTO_GRE;
2951                         else if (ipv6 && !ipv6->proto)
2952                                 ipv6->proto = IPPROTO_GRE;
2953                         break;
2954                 case RTE_FLOW_ITEM_TYPE_VOID:
2955                         break;
2956                 default:
2957                         return rte_flow_error_set(error, EINVAL,
2958                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2959                                                   (void *)items->type,
2960                                                   "unsupported item type");
2961                         break;
2962                 }
2963                 temp_size += len;
2964         }
2965         *size = temp_size;
2966         return 0;
2967 }
2968
2969 static int
2970 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2971 {
2972         struct rte_ether_hdr *eth = NULL;
2973         struct rte_vlan_hdr *vlan = NULL;
2974         struct rte_ipv6_hdr *ipv6 = NULL;
2975         struct rte_udp_hdr *udp = NULL;
2976         char *next_hdr;
2977         uint16_t proto;
2978
2979         eth = (struct rte_ether_hdr *)data;
2980         next_hdr = (char *)(eth + 1);
2981         proto = RTE_BE16(eth->ether_type);
2982
2983         /* VLAN skipping */
2984         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2985                 vlan = (struct rte_vlan_hdr *)next_hdr;
2986                 proto = RTE_BE16(vlan->eth_proto);
2987                 next_hdr += sizeof(struct rte_vlan_hdr);
2988         }
2989
2990         /* HW calculates IPv4 csum. no need to proceed */
2991         if (proto == RTE_ETHER_TYPE_IPV4)
2992                 return 0;
2993
2994         /* non IPv4/IPv6 header. not supported */
2995         if (proto != RTE_ETHER_TYPE_IPV6) {
2996                 return rte_flow_error_set(error, ENOTSUP,
2997                                           RTE_FLOW_ERROR_TYPE_ACTION,
2998                                           NULL, "Cannot offload non IPv4/IPv6");
2999         }
3000
3001         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3002
3003         /* ignore non UDP */
3004         if (ipv6->proto != IPPROTO_UDP)
3005                 return 0;
3006
3007         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3008         udp->dgram_cksum = 0;
3009
3010         return 0;
3011 }
3012
3013 /**
3014  * Convert L2 encap action to DV specification.
3015  *
3016  * @param[in] dev
3017  *   Pointer to rte_eth_dev structure.
3018  * @param[in] action
3019  *   Pointer to action structure.
3020  * @param[in, out] dev_flow
3021  *   Pointer to the mlx5_flow.
3022  * @param[in] transfer
3023  *   Mark if the flow is E-Switch flow.
3024  * @param[out] error
3025  *   Pointer to the error structure.
3026  *
3027  * @return
3028  *   0 on success, a negative errno value otherwise and rte_errno is set.
3029  */
3030 static int
3031 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3032                                const struct rte_flow_action *action,
3033                                struct mlx5_flow *dev_flow,
3034                                uint8_t transfer,
3035                                struct rte_flow_error *error)
3036 {
3037         const struct rte_flow_item *encap_data;
3038         const struct rte_flow_action_raw_encap *raw_encap_data;
3039         struct mlx5_flow_dv_encap_decap_resource res = {
3040                 .reformat_type =
3041                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3042                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3043                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3044         };
3045
3046         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3047                 raw_encap_data =
3048                         (const struct rte_flow_action_raw_encap *)action->conf;
3049                 res.size = raw_encap_data->size;
3050                 memcpy(res.buf, raw_encap_data->data, res.size);
3051         } else {
3052                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3053                         encap_data =
3054                                 ((const struct rte_flow_action_vxlan_encap *)
3055                                                 action->conf)->definition;
3056                 else
3057                         encap_data =
3058                                 ((const struct rte_flow_action_nvgre_encap *)
3059                                                 action->conf)->definition;
3060                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3061                                                &res.size, error))
3062                         return -rte_errno;
3063         }
3064         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3065                 return -rte_errno;
3066         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3067                 return rte_flow_error_set(error, EINVAL,
3068                                           RTE_FLOW_ERROR_TYPE_ACTION,
3069                                           NULL, "can't create L2 encap action");
3070         return 0;
3071 }
3072
3073 /**
3074  * Convert L2 decap action to DV specification.
3075  *
3076  * @param[in] dev
3077  *   Pointer to rte_eth_dev structure.
3078  * @param[in, out] dev_flow
3079  *   Pointer to the mlx5_flow.
3080  * @param[in] transfer
3081  *   Mark if the flow is E-Switch flow.
3082  * @param[out] error
3083  *   Pointer to the error structure.
3084  *
3085  * @return
3086  *   0 on success, a negative errno value otherwise and rte_errno is set.
3087  */
3088 static int
3089 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3090                                struct mlx5_flow *dev_flow,
3091                                uint8_t transfer,
3092                                struct rte_flow_error *error)
3093 {
3094         struct mlx5_flow_dv_encap_decap_resource res = {
3095                 .size = 0,
3096                 .reformat_type =
3097                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3098                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3099                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3100         };
3101
3102         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3103                 return rte_flow_error_set(error, EINVAL,
3104                                           RTE_FLOW_ERROR_TYPE_ACTION,
3105                                           NULL, "can't create L2 decap action");
3106         return 0;
3107 }
3108
3109 /**
3110  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3111  *
3112  * @param[in] dev
3113  *   Pointer to rte_eth_dev structure.
3114  * @param[in] action
3115  *   Pointer to action structure.
3116  * @param[in, out] dev_flow
3117  *   Pointer to the mlx5_flow.
3118  * @param[in] attr
3119  *   Pointer to the flow attributes.
3120  * @param[out] error
3121  *   Pointer to the error structure.
3122  *
3123  * @return
3124  *   0 on success, a negative errno value otherwise and rte_errno is set.
3125  */
3126 static int
3127 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3128                                 const struct rte_flow_action *action,
3129                                 struct mlx5_flow *dev_flow,
3130                                 const struct rte_flow_attr *attr,
3131                                 struct rte_flow_error *error)
3132 {
3133         const struct rte_flow_action_raw_encap *encap_data;
3134         struct mlx5_flow_dv_encap_decap_resource res;
3135
3136         memset(&res, 0, sizeof(res));
3137         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3138         res.size = encap_data->size;
3139         memcpy(res.buf, encap_data->data, res.size);
3140         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3141                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3142                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3143         if (attr->transfer)
3144                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3145         else
3146                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3147                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3148         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3149                 return rte_flow_error_set(error, EINVAL,
3150                                           RTE_FLOW_ERROR_TYPE_ACTION,
3151                                           NULL, "can't create encap action");
3152         return 0;
3153 }
3154
3155 /**
3156  * Create action push VLAN.
3157  *
3158  * @param[in] dev
3159  *   Pointer to rte_eth_dev structure.
3160  * @param[in] attr
3161  *   Pointer to the flow attributes.
3162  * @param[in] vlan
3163  *   Pointer to the vlan to push to the Ethernet header.
3164  * @param[in, out] dev_flow
3165  *   Pointer to the mlx5_flow.
3166  * @param[out] error
3167  *   Pointer to the error structure.
3168  *
3169  * @return
3170  *   0 on success, a negative errno value otherwise and rte_errno is set.
3171  */
3172 static int
3173 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3174                                 const struct rte_flow_attr *attr,
3175                                 const struct rte_vlan_hdr *vlan,
3176                                 struct mlx5_flow *dev_flow,
3177                                 struct rte_flow_error *error)
3178 {
3179         struct mlx5_flow_dv_push_vlan_action_resource res;
3180
3181         memset(&res, 0, sizeof(res));
3182         res.vlan_tag =
3183                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3184                                  vlan->vlan_tci);
3185         if (attr->transfer)
3186                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3187         else
3188                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3189                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3190         return flow_dv_push_vlan_action_resource_register
3191                                             (dev, &res, dev_flow, error);
3192 }
3193
3194 /**
3195  * Validate the modify-header actions.
3196  *
3197  * @param[in] action_flags
3198  *   Holds the actions detected until now.
3199  * @param[in] action
3200  *   Pointer to the modify action.
3201  * @param[out] error
3202  *   Pointer to error structure.
3203  *
3204  * @return
3205  *   0 on success, a negative errno value otherwise and rte_errno is set.
3206  */
3207 static int
3208 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3209                                    const struct rte_flow_action *action,
3210                                    struct rte_flow_error *error)
3211 {
3212         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3213                 return rte_flow_error_set(error, EINVAL,
3214                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3215                                           NULL, "action configuration not set");
3216         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3217                 return rte_flow_error_set(error, EINVAL,
3218                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3219                                           "can't have encap action before"
3220                                           " modify action");
3221         return 0;
3222 }
3223
3224 /**
3225  * Validate the modify-header MAC address actions.
3226  *
3227  * @param[in] action_flags
3228  *   Holds the actions detected until now.
3229  * @param[in] action
3230  *   Pointer to the modify action.
3231  * @param[in] item_flags
3232  *   Holds the items detected.
3233  * @param[out] error
3234  *   Pointer to error structure.
3235  *
3236  * @return
3237  *   0 on success, a negative errno value otherwise and rte_errno is set.
3238  */
3239 static int
3240 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3241                                    const struct rte_flow_action *action,
3242                                    const uint64_t item_flags,
3243                                    struct rte_flow_error *error)
3244 {
3245         int ret = 0;
3246
3247         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3248         if (!ret) {
3249                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3250                         return rte_flow_error_set(error, EINVAL,
3251                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3252                                                   NULL,
3253                                                   "no L2 item in pattern");
3254         }
3255         return ret;
3256 }
3257
3258 /**
3259  * Validate the modify-header IPv4 address actions.
3260  *
3261  * @param[in] action_flags
3262  *   Holds the actions detected until now.
3263  * @param[in] action
3264  *   Pointer to the modify action.
3265  * @param[in] item_flags
3266  *   Holds the items detected.
3267  * @param[out] error
3268  *   Pointer to error structure.
3269  *
3270  * @return
3271  *   0 on success, a negative errno value otherwise and rte_errno is set.
3272  */
3273 static int
3274 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3275                                     const struct rte_flow_action *action,
3276                                     const uint64_t item_flags,
3277                                     struct rte_flow_error *error)
3278 {
3279         int ret = 0;
3280         uint64_t layer;
3281
3282         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3283         if (!ret) {
3284                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3285                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3286                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3287                 if (!(item_flags & layer))
3288                         return rte_flow_error_set(error, EINVAL,
3289                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3290                                                   NULL,
3291                                                   "no ipv4 item in pattern");
3292         }
3293         return ret;
3294 }
3295
3296 /**
3297  * Validate the modify-header IPv6 address actions.
3298  *
3299  * @param[in] action_flags
3300  *   Holds the actions detected until now.
3301  * @param[in] action
3302  *   Pointer to the modify action.
3303  * @param[in] item_flags
3304  *   Holds the items detected.
3305  * @param[out] error
3306  *   Pointer to error structure.
3307  *
3308  * @return
3309  *   0 on success, a negative errno value otherwise and rte_errno is set.
3310  */
3311 static int
3312 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3313                                     const struct rte_flow_action *action,
3314                                     const uint64_t item_flags,
3315                                     struct rte_flow_error *error)
3316 {
3317         int ret = 0;
3318         uint64_t layer;
3319
3320         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3321         if (!ret) {
3322                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3323                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3324                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3325                 if (!(item_flags & layer))
3326                         return rte_flow_error_set(error, EINVAL,
3327                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3328                                                   NULL,
3329                                                   "no ipv6 item in pattern");
3330         }
3331         return ret;
3332 }
3333
3334 /**
3335  * Validate the modify-header TP actions.
3336  *
3337  * @param[in] action_flags
3338  *   Holds the actions detected until now.
3339  * @param[in] action
3340  *   Pointer to the modify action.
3341  * @param[in] item_flags
3342  *   Holds the items detected.
3343  * @param[out] error
3344  *   Pointer to error structure.
3345  *
3346  * @return
3347  *   0 on success, a negative errno value otherwise and rte_errno is set.
3348  */
3349 static int
3350 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3351                                   const struct rte_flow_action *action,
3352                                   const uint64_t item_flags,
3353                                   struct rte_flow_error *error)
3354 {
3355         int ret = 0;
3356         uint64_t layer;
3357
3358         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3359         if (!ret) {
3360                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3361                                  MLX5_FLOW_LAYER_INNER_L4 :
3362                                  MLX5_FLOW_LAYER_OUTER_L4;
3363                 if (!(item_flags & layer))
3364                         return rte_flow_error_set(error, EINVAL,
3365                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3366                                                   NULL, "no transport layer "
3367                                                   "in pattern");
3368         }
3369         return ret;
3370 }
3371
3372 /**
3373  * Validate the modify-header actions of increment/decrement
3374  * TCP Sequence-number.
3375  *
3376  * @param[in] action_flags
3377  *   Holds the actions detected until now.
3378  * @param[in] action
3379  *   Pointer to the modify action.
3380  * @param[in] item_flags
3381  *   Holds the items detected.
3382  * @param[out] error
3383  *   Pointer to error structure.
3384  *
3385  * @return
3386  *   0 on success, a negative errno value otherwise and rte_errno is set.
3387  */
3388 static int
3389 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3390                                        const struct rte_flow_action *action,
3391                                        const uint64_t item_flags,
3392                                        struct rte_flow_error *error)
3393 {
3394         int ret = 0;
3395         uint64_t layer;
3396
3397         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3398         if (!ret) {
3399                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3400                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3401                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3402                 if (!(item_flags & layer))
3403                         return rte_flow_error_set(error, EINVAL,
3404                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3405                                                   NULL, "no TCP item in"
3406                                                   " pattern");
3407                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3408                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3409                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3410                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3411                         return rte_flow_error_set(error, EINVAL,
3412                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3413                                                   NULL,
3414                                                   "cannot decrease and increase"
3415                                                   " TCP sequence number"
3416                                                   " at the same time");
3417         }
3418         return ret;
3419 }
3420
3421 /**
3422  * Validate the modify-header actions of increment/decrement
3423  * TCP Acknowledgment number.
3424  *
3425  * @param[in] action_flags
3426  *   Holds the actions detected until now.
3427  * @param[in] action
3428  *   Pointer to the modify action.
3429  * @param[in] item_flags
3430  *   Holds the items detected.
3431  * @param[out] error
3432  *   Pointer to error structure.
3433  *
3434  * @return
3435  *   0 on success, a negative errno value otherwise and rte_errno is set.
3436  */
3437 static int
3438 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3439                                        const struct rte_flow_action *action,
3440                                        const uint64_t item_flags,
3441                                        struct rte_flow_error *error)
3442 {
3443         int ret = 0;
3444         uint64_t layer;
3445
3446         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3447         if (!ret) {
3448                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3449                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3450                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3451                 if (!(item_flags & layer))
3452                         return rte_flow_error_set(error, EINVAL,
3453                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3454                                                   NULL, "no TCP item in"
3455                                                   " pattern");
3456                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3457                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3458                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3459                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3460                         return rte_flow_error_set(error, EINVAL,
3461                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3462                                                   NULL,
3463                                                   "cannot decrease and increase"
3464                                                   " TCP acknowledgment number"
3465                                                   " at the same time");
3466         }
3467         return ret;
3468 }
3469
3470 /**
3471  * Validate the modify-header TTL actions.
3472  *
3473  * @param[in] action_flags
3474  *   Holds the actions detected until now.
3475  * @param[in] action
3476  *   Pointer to the modify action.
3477  * @param[in] item_flags
3478  *   Holds the items detected.
3479  * @param[out] error
3480  *   Pointer to error structure.
3481  *
3482  * @return
3483  *   0 on success, a negative errno value otherwise and rte_errno is set.
3484  */
3485 static int
3486 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3487                                    const struct rte_flow_action *action,
3488                                    const uint64_t item_flags,
3489                                    struct rte_flow_error *error)
3490 {
3491         int ret = 0;
3492         uint64_t layer;
3493
3494         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3495         if (!ret) {
3496                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3497                                  MLX5_FLOW_LAYER_INNER_L3 :
3498                                  MLX5_FLOW_LAYER_OUTER_L3;
3499                 if (!(item_flags & layer))
3500                         return rte_flow_error_set(error, EINVAL,
3501                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3502                                                   NULL,
3503                                                   "no IP protocol in pattern");
3504         }
3505         return ret;
3506 }
3507
3508 /**
3509  * Validate jump action.
3510  *
3511  * @param[in] action
3512  *   Pointer to the jump action.
3513  * @param[in] action_flags
3514  *   Holds the actions detected until now.
3515  * @param[in] attributes
3516  *   Pointer to flow attributes
3517  * @param[in] external
3518  *   Action belongs to flow rule created by request external to PMD.
3519  * @param[out] error
3520  *   Pointer to error structure.
3521  *
3522  * @return
3523  *   0 on success, a negative errno value otherwise and rte_errno is set.
3524  */
3525 static int
3526 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3527                              uint64_t action_flags,
3528                              const struct rte_flow_attr *attributes,
3529                              bool external, struct rte_flow_error *error)
3530 {
3531         uint32_t target_group, table;
3532         int ret = 0;
3533
3534         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3535                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3536                 return rte_flow_error_set(error, EINVAL,
3537                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3538                                           "can't have 2 fate actions in"
3539                                           " same flow");
3540         if (action_flags & MLX5_FLOW_ACTION_METER)
3541                 return rte_flow_error_set(error, ENOTSUP,
3542                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3543                                           "jump with meter not support");
3544         if (!action->conf)
3545                 return rte_flow_error_set(error, EINVAL,
3546                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3547                                           NULL, "action configuration not set");
3548         target_group =
3549                 ((const struct rte_flow_action_jump *)action->conf)->group;
3550         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3551                                        true, &table, error);
3552         if (ret)
3553                 return ret;
3554         if (attributes->group == target_group)
3555                 return rte_flow_error_set(error, EINVAL,
3556                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3557                                           "target group must be other than"
3558                                           " the current flow group");
3559         return 0;
3560 }
3561
3562 /*
3563  * Validate the port_id action.
3564  *
3565  * @param[in] dev
3566  *   Pointer to rte_eth_dev structure.
3567  * @param[in] action_flags
3568  *   Bit-fields that holds the actions detected until now.
3569  * @param[in] action
3570  *   Port_id RTE action structure.
3571  * @param[in] attr
3572  *   Attributes of flow that includes this action.
3573  * @param[out] error
3574  *   Pointer to error structure.
3575  *
3576  * @return
3577  *   0 on success, a negative errno value otherwise and rte_errno is set.
3578  */
3579 static int
3580 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3581                                 uint64_t action_flags,
3582                                 const struct rte_flow_action *action,
3583                                 const struct rte_flow_attr *attr,
3584                                 struct rte_flow_error *error)
3585 {
3586         const struct rte_flow_action_port_id *port_id;
3587         struct mlx5_priv *act_priv;
3588         struct mlx5_priv *dev_priv;
3589         uint16_t port;
3590
3591         if (!attr->transfer)
3592                 return rte_flow_error_set(error, ENOTSUP,
3593                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3594                                           NULL,
3595                                           "port id action is valid in transfer"
3596                                           " mode only");
3597         if (!action || !action->conf)
3598                 return rte_flow_error_set(error, ENOTSUP,
3599                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3600                                           NULL,
3601                                           "port id action parameters must be"
3602                                           " specified");
3603         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3604                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3605                 return rte_flow_error_set(error, EINVAL,
3606                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3607                                           "can have only one fate actions in"
3608                                           " a flow");
3609         dev_priv = mlx5_dev_to_eswitch_info(dev);
3610         if (!dev_priv)
3611                 return rte_flow_error_set(error, rte_errno,
3612                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3613                                           NULL,
3614                                           "failed to obtain E-Switch info");
3615         port_id = action->conf;
3616         port = port_id->original ? dev->data->port_id : port_id->id;
3617         act_priv = mlx5_port_to_eswitch_info(port, false);
3618         if (!act_priv)
3619                 return rte_flow_error_set
3620                                 (error, rte_errno,
3621                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3622                                  "failed to obtain E-Switch port id for port");
3623         if (act_priv->domain_id != dev_priv->domain_id)
3624                 return rte_flow_error_set
3625                                 (error, EINVAL,
3626                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3627                                  "port does not belong to"
3628                                  " E-Switch being configured");
3629         return 0;
3630 }
3631
3632 /**
3633  * Get the maximum number of modify header actions.
3634  *
3635  * @param dev
3636  *   Pointer to rte_eth_dev structure.
3637  * @param flags
3638  *   Flags bits to check if root level.
3639  *
3640  * @return
3641  *   Max number of modify header actions device can support.
3642  */
3643 static inline unsigned int
3644 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3645                               uint64_t flags)
3646 {
3647         /*
3648          * There's no way to directly query the max capacity from FW.
3649          * The maximal value on root table should be assumed to be supported.
3650          */
3651         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3652                 return MLX5_MAX_MODIFY_NUM;
3653         else
3654                 return MLX5_ROOT_TBL_MODIFY_NUM;
3655 }
3656
3657 /**
3658  * Validate the meter action.
3659  *
3660  * @param[in] dev
3661  *   Pointer to rte_eth_dev structure.
3662  * @param[in] action_flags
3663  *   Bit-fields that holds the actions detected until now.
3664  * @param[in] action
3665  *   Pointer to the meter action.
3666  * @param[in] attr
3667  *   Attributes of flow that includes this action.
3668  * @param[out] error
3669  *   Pointer to error structure.
3670  *
3671  * @return
3672  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3673  */
3674 static int
3675 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3676                                 uint64_t action_flags,
3677                                 const struct rte_flow_action *action,
3678                                 const struct rte_flow_attr *attr,
3679                                 struct rte_flow_error *error)
3680 {
3681         struct mlx5_priv *priv = dev->data->dev_private;
3682         const struct rte_flow_action_meter *am = action->conf;
3683         struct mlx5_flow_meter *fm;
3684
3685         if (!am)
3686                 return rte_flow_error_set(error, EINVAL,
3687                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3688                                           "meter action conf is NULL");
3689
3690         if (action_flags & MLX5_FLOW_ACTION_METER)
3691                 return rte_flow_error_set(error, ENOTSUP,
3692                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3693                                           "meter chaining not support");
3694         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3695                 return rte_flow_error_set(error, ENOTSUP,
3696                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3697                                           "meter with jump not support");
3698         if (!priv->mtr_en)
3699                 return rte_flow_error_set(error, ENOTSUP,
3700                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3701                                           NULL,
3702                                           "meter action not supported");
3703         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3704         if (!fm)
3705                 return rte_flow_error_set(error, EINVAL,
3706                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3707                                           "Meter not found");
3708         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3709               (!fm->ingress && !attr->ingress && attr->egress) ||
3710               (!fm->egress && !attr->egress && attr->ingress))))
3711                 return rte_flow_error_set(error, EINVAL,
3712                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3713                                           "Flow attributes are either invalid "
3714                                           "or have a conflict with current "
3715                                           "meter attributes");
3716         return 0;
3717 }
3718
3719 /**
3720  * Validate the modify-header IPv4 DSCP actions.
3721  *
3722  * @param[in] action_flags
3723  *   Holds the actions detected until now.
3724  * @param[in] action
3725  *   Pointer to the modify action.
3726  * @param[in] item_flags
3727  *   Holds the items detected.
3728  * @param[out] error
3729  *   Pointer to error structure.
3730  *
3731  * @return
3732  *   0 on success, a negative errno value otherwise and rte_errno is set.
3733  */
3734 static int
3735 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3736                                          const struct rte_flow_action *action,
3737                                          const uint64_t item_flags,
3738                                          struct rte_flow_error *error)
3739 {
3740         int ret = 0;
3741
3742         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3743         if (!ret) {
3744                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3745                         return rte_flow_error_set(error, EINVAL,
3746                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3747                                                   NULL,
3748                                                   "no ipv4 item in pattern");
3749         }
3750         return ret;
3751 }
3752
3753 /**
3754  * Validate the modify-header IPv6 DSCP actions.
3755  *
3756  * @param[in] action_flags
3757  *   Holds the actions detected until now.
3758  * @param[in] action
3759  *   Pointer to the modify action.
3760  * @param[in] item_flags
3761  *   Holds the items detected.
3762  * @param[out] error
3763  *   Pointer to error structure.
3764  *
3765  * @return
3766  *   0 on success, a negative errno value otherwise and rte_errno is set.
3767  */
3768 static int
3769 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3770                                          const struct rte_flow_action *action,
3771                                          const uint64_t item_flags,
3772                                          struct rte_flow_error *error)
3773 {
3774         int ret = 0;
3775
3776         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3777         if (!ret) {
3778                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3779                         return rte_flow_error_set(error, EINVAL,
3780                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3781                                                   NULL,
3782                                                   "no ipv6 item in pattern");
3783         }
3784         return ret;
3785 }
3786
3787 /**
3788  * Find existing modify-header resource or create and register a new one.
3789  *
3790  * @param dev[in, out]
3791  *   Pointer to rte_eth_dev structure.
3792  * @param[in, out] resource
3793  *   Pointer to modify-header resource.
3794  * @parm[in, out] dev_flow
3795  *   Pointer to the dev_flow.
3796  * @param[out] error
3797  *   pointer to error structure.
3798  *
3799  * @return
3800  *   0 on success otherwise -errno and errno is set.
3801  */
3802 static int
3803 flow_dv_modify_hdr_resource_register
3804                         (struct rte_eth_dev *dev,
3805                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3806                          struct mlx5_flow *dev_flow,
3807                          struct rte_flow_error *error)
3808 {
3809         struct mlx5_priv *priv = dev->data->dev_private;
3810         struct mlx5_ibv_shared *sh = priv->sh;
3811         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3812         struct mlx5dv_dr_domain *ns;
3813         uint32_t actions_len;
3814
3815         resource->flags = dev_flow->dv.group ? 0 :
3816                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3817         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3818                                     resource->flags))
3819                 return rte_flow_error_set(error, EOVERFLOW,
3820                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3821                                           "too many modify header items");
3822         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3823                 ns = sh->fdb_domain;
3824         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3825                 ns = sh->tx_domain;
3826         else
3827                 ns = sh->rx_domain;
3828         /* Lookup a matching resource from cache. */
3829         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3830         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3831                 if (resource->ft_type == cache_resource->ft_type &&
3832                     resource->actions_num == cache_resource->actions_num &&
3833                     resource->flags == cache_resource->flags &&
3834                     !memcmp((const void *)resource->actions,
3835                             (const void *)cache_resource->actions,
3836                             actions_len)) {
3837                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3838                                 (void *)cache_resource,
3839                                 rte_atomic32_read(&cache_resource->refcnt));
3840                         rte_atomic32_inc(&cache_resource->refcnt);
3841                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3842                         return 0;
3843                 }
3844         }
3845         /* Register new modify-header resource. */
3846         cache_resource = rte_calloc(__func__, 1,
3847                                     sizeof(*cache_resource) + actions_len, 0);
3848         if (!cache_resource)
3849                 return rte_flow_error_set(error, ENOMEM,
3850                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3851                                           "cannot allocate resource memory");
3852         *cache_resource = *resource;
3853         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3854         cache_resource->verbs_action =
3855                 mlx5_glue->dv_create_flow_action_modify_header
3856                                         (sh->ctx, cache_resource->ft_type, ns,
3857                                          cache_resource->flags, actions_len,
3858                                          (uint64_t *)cache_resource->actions);
3859         if (!cache_resource->verbs_action) {
3860                 rte_free(cache_resource);
3861                 return rte_flow_error_set(error, ENOMEM,
3862                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3863                                           NULL, "cannot create action");
3864         }
3865         rte_atomic32_init(&cache_resource->refcnt);
3866         rte_atomic32_inc(&cache_resource->refcnt);
3867         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3868         dev_flow->handle->dvh.modify_hdr = cache_resource;
3869         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3870                 (void *)cache_resource,
3871                 rte_atomic32_read(&cache_resource->refcnt));
3872         return 0;
3873 }
3874
3875 /**
3876  * Get DV flow counter by index.
3877  *
3878  * @param[in] dev
3879  *   Pointer to the Ethernet device structure.
3880  * @param[in] idx
3881  *   mlx5 flow counter index in the container.
3882  * @param[out] ppool
3883  *   mlx5 flow counter pool in the container,
3884  *
3885  * @return
3886  *   Pointer to the counter, NULL otherwise.
3887  */
3888 static struct mlx5_flow_counter *
3889 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3890                            uint32_t idx,
3891                            struct mlx5_flow_counter_pool **ppool)
3892 {
3893         struct mlx5_priv *priv = dev->data->dev_private;
3894         struct mlx5_pools_container *cont;
3895         struct mlx5_flow_counter_pool *pool;
3896         uint32_t batch = 0;
3897
3898         idx--;
3899         if (idx >= MLX5_CNT_BATCH_OFFSET) {
3900                 idx -= MLX5_CNT_BATCH_OFFSET;
3901                 batch = 1;
3902         }
3903         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3904         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3905         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3906         MLX5_ASSERT(pool);
3907         if (ppool)
3908                 *ppool = pool;
3909         return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3910 }
3911
3912 /**
3913  * Get a pool by devx counter ID.
3914  *
3915  * @param[in] cont
3916  *   Pointer to the counter container.
3917  * @param[in] id
3918  *   The counter devx ID.
3919  *
3920  * @return
3921  *   The counter pool pointer if exists, NULL otherwise,
3922  */
3923 static struct mlx5_flow_counter_pool *
3924 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3925 {
3926         uint32_t i;
3927         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3928
3929         for (i = 0; i < n_valid; i++) {
3930                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3931                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3932                            MLX5_COUNTERS_PER_POOL;
3933
3934                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3935                         /*
3936                          * Move the pool to the head, as counter allocate
3937                          * always gets the first pool in the container.
3938                          */
3939                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
3940                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3941                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3942                         }
3943                         return pool;
3944                 }
3945         }
3946         return NULL;
3947 }
3948
3949 /**
3950  * Allocate a new memory for the counter values wrapped by all the needed
3951  * management.
3952  *
3953  * @param[in] dev
3954  *   Pointer to the Ethernet device structure.
3955  * @param[in] raws_n
3956  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3957  *
3958  * @return
3959  *   The new memory management pointer on success, otherwise NULL and rte_errno
3960  *   is set.
3961  */
3962 static struct mlx5_counter_stats_mem_mng *
3963 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3964 {
3965         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3966                                         (dev->data->dev_private))->sh;
3967         struct mlx5_devx_mkey_attr mkey_attr;
3968         struct mlx5_counter_stats_mem_mng *mem_mng;
3969         volatile struct flow_counter_stats *raw_data;
3970         int size = (sizeof(struct flow_counter_stats) *
3971                         MLX5_COUNTERS_PER_POOL +
3972                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3973                         sizeof(struct mlx5_counter_stats_mem_mng);
3974         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3975         int i;
3976
3977         if (!mem) {
3978                 rte_errno = ENOMEM;
3979                 return NULL;
3980         }
3981         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3982         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3983         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3984                                                  IBV_ACCESS_LOCAL_WRITE);
3985         if (!mem_mng->umem) {
3986                 rte_errno = errno;
3987                 rte_free(mem);
3988                 return NULL;
3989         }
3990         mkey_attr.addr = (uintptr_t)mem;
3991         mkey_attr.size = size;
3992         mkey_attr.umem_id = mem_mng->umem->umem_id;
3993         mkey_attr.pd = sh->pdn;
3994         mkey_attr.log_entity_size = 0;
3995         mkey_attr.pg_access = 0;
3996         mkey_attr.klm_array = NULL;
3997         mkey_attr.klm_num = 0;
3998         mkey_attr.relaxed_ordering = 1;
3999         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4000         if (!mem_mng->dm) {
4001                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4002                 rte_errno = errno;
4003                 rte_free(mem);
4004                 return NULL;
4005         }
4006         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4007         raw_data = (volatile struct flow_counter_stats *)mem;
4008         for (i = 0; i < raws_n; ++i) {
4009                 mem_mng->raws[i].mem_mng = mem_mng;
4010                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4011         }
4012         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4013         return mem_mng;
4014 }
4015
4016 /**
4017  * Resize a counter container.
4018  *
4019  * @param[in] dev
4020  *   Pointer to the Ethernet device structure.
4021  * @param[in] batch
4022  *   Whether the pool is for counter that was allocated by batch command.
4023  *
4024  * @return
4025  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4026  */
4027 static struct mlx5_pools_container *
4028 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4029 {
4030         struct mlx5_priv *priv = dev->data->dev_private;
4031         struct mlx5_pools_container *cont =
4032                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4033         struct mlx5_pools_container *new_cont =
4034                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4035         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4036         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4037         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4038         int i;
4039
4040         /* Fallback mode has no background thread. Skip the check. */
4041         if (!priv->counter_fallback &&
4042             cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4043                 /* The last resize still hasn't detected by the host thread. */
4044                 rte_errno = EAGAIN;
4045                 return NULL;
4046         }
4047         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4048         if (!new_cont->pools) {
4049                 rte_errno = ENOMEM;
4050                 return NULL;
4051         }
4052         if (cont->n)
4053                 memcpy(new_cont->pools, cont->pools, cont->n *
4054                        sizeof(struct mlx5_flow_counter_pool *));
4055         /*
4056          * Fallback mode query the counter directly, no background query
4057          * resources are needed.
4058          */
4059         if (!priv->counter_fallback) {
4060                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4061                         MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4062                 if (!mem_mng) {
4063                         rte_free(new_cont->pools);
4064                         return NULL;
4065                 }
4066                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4067                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4068                                          mem_mng->raws +
4069                                          MLX5_CNT_CONTAINER_RESIZE +
4070                                          i, next);
4071         } else {
4072                 /*
4073                  * Release the old container pools directly as no background
4074                  * thread helps that.
4075                  */
4076                 rte_free(cont->pools);
4077         }
4078         new_cont->n = resize;
4079         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4080         TAILQ_INIT(&new_cont->pool_list);
4081         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4082         new_cont->init_mem_mng = mem_mng;
4083         rte_cio_wmb();
4084          /* Flip the master container. */
4085         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4086         return new_cont;
4087 }
4088
4089 /**
4090  * Query a devx flow counter.
4091  *
4092  * @param[in] dev
4093  *   Pointer to the Ethernet device structure.
4094  * @param[in] cnt
4095  *   Index to the flow counter.
4096  * @param[out] pkts
4097  *   The statistics value of packets.
4098  * @param[out] bytes
4099  *   The statistics value of bytes.
4100  *
4101  * @return
4102  *   0 on success, otherwise a negative errno value and rte_errno is set.
4103  */
4104 static inline int
4105 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4106                      uint64_t *bytes)
4107 {
4108         struct mlx5_priv *priv = dev->data->dev_private;
4109         struct mlx5_flow_counter_pool *pool = NULL;
4110         struct mlx5_flow_counter *cnt;
4111         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4112         int offset;
4113
4114         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4115         MLX5_ASSERT(pool);
4116         if (counter < MLX5_CNT_BATCH_OFFSET) {
4117                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4118                 if (priv->counter_fallback)
4119                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4120                                         0, pkts, bytes, 0, NULL, NULL, 0);
4121         }
4122
4123         rte_spinlock_lock(&pool->sl);
4124         /*
4125          * The single counters allocation may allocate smaller ID than the
4126          * current allocated in parallel to the host reading.
4127          * In this case the new counter values must be reported as 0.
4128          */
4129         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4130                 *pkts = 0;
4131                 *bytes = 0;
4132         } else {
4133                 offset = cnt - &pool->counters_raw[0];
4134                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4135                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4136         }
4137         rte_spinlock_unlock(&pool->sl);
4138         return 0;
4139 }
4140
4141 /**
4142  * Create and initialize a new counter pool.
4143  *
4144  * @param[in] dev
4145  *   Pointer to the Ethernet device structure.
4146  * @param[out] dcs
4147  *   The devX counter handle.
4148  * @param[in] batch
4149  *   Whether the pool is for counter that was allocated by batch command.
4150  * @param[in/out] cont_cur
4151  *   Pointer to the container pointer, it will be update in pool resize.
4152  *
4153  * @return
4154  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4155  */
4156 static struct mlx5_pools_container *
4157 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4158                     uint32_t batch)
4159 {
4160         struct mlx5_priv *priv = dev->data->dev_private;
4161         struct mlx5_flow_counter_pool *pool;
4162         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4163                                                                0);
4164         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4165         uint32_t size;
4166
4167         if (cont->n == n_valid) {
4168                 cont = flow_dv_container_resize(dev, batch);
4169                 if (!cont)
4170                         return NULL;
4171         }
4172         size = sizeof(*pool);
4173         if (!batch)
4174                 size += MLX5_COUNTERS_PER_POOL *
4175                         sizeof(struct mlx5_flow_counter_ext);
4176         pool = rte_calloc(__func__, 1, size, 0);
4177         if (!pool) {
4178                 rte_errno = ENOMEM;
4179                 return NULL;
4180         }
4181         pool->min_dcs = dcs;
4182         if (!priv->counter_fallback)
4183                 pool->raw = cont->init_mem_mng->raws + n_valid %
4184                                                      MLX5_CNT_CONTAINER_RESIZE;
4185         pool->raw_hw = NULL;
4186         rte_spinlock_init(&pool->sl);
4187         /*
4188          * The generation of the new allocated counters in this pool is 0, 2 in
4189          * the pool generation makes all the counters valid for allocation.
4190          * The start and end query generation protect the counters be released
4191          * between the query and update gap period will not be reallocated
4192          * without the last query finished and stats updated to the memory.
4193          */
4194         rte_atomic64_set(&pool->start_query_gen, 0x2);
4195         /*
4196          * There's no background query thread for fallback mode, set the
4197          * end_query_gen to the maximum value since no need to wait for
4198          * statistics update.
4199          */
4200         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4201                          INT64_MAX : 0x2);
4202         TAILQ_INIT(&pool->counters);
4203         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4204         pool->index = n_valid;
4205         cont->pools[n_valid] = pool;
4206         /* Pool initialization must be updated before host thread access. */
4207         rte_cio_wmb();
4208         rte_atomic16_add(&cont->n_valid, 1);
4209         return cont;
4210 }
4211
4212 /**
4213  * Prepare a new counter and/or a new counter pool.
4214  *
4215  * @param[in] dev
4216  *   Pointer to the Ethernet device structure.
4217  * @param[out] cnt_free
4218  *   Where to put the pointer of a new counter.
4219  * @param[in] batch
4220  *   Whether the pool is for counter that was allocated by batch command.
4221  *
4222  * @return
4223  *   The counter container pointer and @p cnt_free is set on success,
4224  *   NULL otherwise and rte_errno is set.
4225  */
4226 static struct mlx5_pools_container *
4227 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4228                              struct mlx5_flow_counter **cnt_free,
4229                              uint32_t batch)
4230 {
4231         struct mlx5_priv *priv = dev->data->dev_private;
4232         struct mlx5_pools_container *cont;
4233         struct mlx5_flow_counter_pool *pool;
4234         struct mlx5_devx_obj *dcs = NULL;
4235         struct mlx5_flow_counter *cnt;
4236         uint32_t i;
4237
4238         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4239         if (!batch) {
4240                 /* bulk_bitmap must be 0 for single counter allocation. */
4241                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4242                 if (!dcs)
4243                         return NULL;
4244                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4245                 if (!pool) {
4246                         cont = flow_dv_pool_create(dev, dcs, batch);
4247                         if (!cont) {
4248                                 mlx5_devx_cmd_destroy(dcs);
4249                                 return NULL;
4250                         }
4251                         pool = TAILQ_FIRST(&cont->pool_list);
4252                 } else if (dcs->id < pool->min_dcs->id) {
4253                         rte_atomic64_set(&pool->a64_dcs,
4254                                          (int64_t)(uintptr_t)dcs);
4255                 }
4256                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4257                 cnt = &pool->counters_raw[i];
4258                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4259                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4260                 *cnt_free = cnt;
4261                 return cont;
4262         }
4263         /* bulk_bitmap is in 128 counters units. */
4264         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4265                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4266         if (!dcs) {
4267                 rte_errno = ENODATA;
4268                 return NULL;
4269         }
4270         cont = flow_dv_pool_create(dev, dcs, batch);
4271         if (!cont) {
4272                 mlx5_devx_cmd_destroy(dcs);
4273                 return NULL;
4274         }
4275         pool = TAILQ_FIRST(&cont->pool_list);
4276         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4277                 cnt = &pool->counters_raw[i];
4278                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4279         }
4280         *cnt_free = &pool->counters_raw[0];
4281         return cont;
4282 }
4283
4284 /**
4285  * Search for existed shared counter.
4286  *
4287  * @param[in] cont
4288  *   Pointer to the relevant counter pool container.
4289  * @param[in] id
4290  *   The shared counter ID to search.
4291  * @param[out] ppool
4292  *   mlx5 flow counter pool in the container,
4293  *
4294  * @return
4295  *   NULL if not existed, otherwise pointer to the shared extend counter.
4296  */
4297 static struct mlx5_flow_counter_ext *
4298 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4299                               struct mlx5_flow_counter_pool **ppool)
4300 {
4301         static struct mlx5_flow_counter_ext *cnt;
4302         struct mlx5_flow_counter_pool *pool;
4303         uint32_t i;
4304         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4305
4306         for (i = 0; i < n_valid; i++) {
4307                 pool = cont->pools[i];
4308                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4309                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4310                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4311                                 if (ppool)
4312                                         *ppool = cont->pools[i];
4313                                 return cnt;
4314                         }
4315                 }
4316         }
4317         return NULL;
4318 }
4319
4320 /**
4321  * Allocate a flow counter.
4322  *
4323  * @param[in] dev
4324  *   Pointer to the Ethernet device structure.
4325  * @param[in] shared
4326  *   Indicate if this counter is shared with other flows.
4327  * @param[in] id
4328  *   Counter identifier.
4329  * @param[in] group
4330  *   Counter flow group.
4331  *
4332  * @return
4333  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4334  */
4335 static uint32_t
4336 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4337                       uint16_t group)
4338 {
4339         struct mlx5_priv *priv = dev->data->dev_private;
4340         struct mlx5_flow_counter_pool *pool = NULL;
4341         struct mlx5_flow_counter *cnt_free = NULL;
4342         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4343         /*
4344          * Currently group 0 flow counter cannot be assigned to a flow if it is
4345          * not the first one in the batch counter allocation, so it is better
4346          * to allocate counters one by one for these flows in a separate
4347          * container.
4348          * A counter can be shared between different groups so need to take
4349          * shared counters from the single container.
4350          */
4351         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4352         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4353                                                                0);
4354         uint32_t cnt_idx;
4355
4356         if (!priv->config.devx) {
4357                 rte_errno = ENOTSUP;
4358                 return 0;
4359         }
4360         if (shared) {
4361                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4362                 if (cnt_ext) {
4363                         if (cnt_ext->ref_cnt + 1 == 0) {
4364                                 rte_errno = E2BIG;
4365                                 return 0;
4366                         }
4367                         cnt_ext->ref_cnt++;
4368                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4369                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4370                                   + 1;
4371                         return cnt_idx;
4372                 }
4373         }
4374         /* Pools which has a free counters are in the start. */
4375         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4376                 /*
4377                  * The free counter reset values must be updated between the
4378                  * counter release to the counter allocation, so, at least one
4379                  * query must be done in this time. ensure it by saving the
4380                  * query generation in the release time.
4381                  * The free list is sorted according to the generation - so if
4382                  * the first one is not updated, all the others are not
4383                  * updated too.
4384                  */
4385                 cnt_free = TAILQ_FIRST(&pool->counters);
4386                 if (cnt_free && cnt_free->query_gen <
4387                     rte_atomic64_read(&pool->end_query_gen))
4388                         break;
4389                 cnt_free = NULL;
4390         }
4391         if (!cnt_free) {
4392                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4393                 if (!cont)
4394                         return 0;
4395                 pool = TAILQ_FIRST(&cont->pool_list);
4396         }
4397         if (!batch)
4398                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4399         /* Create a DV counter action only in the first time usage. */
4400         if (!cnt_free->action) {
4401                 uint16_t offset;
4402                 struct mlx5_devx_obj *dcs;
4403
4404                 if (batch) {
4405                         offset = cnt_free - &pool->counters_raw[0];
4406                         dcs = pool->min_dcs;
4407                 } else {
4408                         offset = 0;
4409                         dcs = cnt_ext->dcs;
4410                 }
4411                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4412                                         (dcs->obj, offset);
4413                 if (!cnt_free->action) {
4414                         rte_errno = errno;
4415                         return 0;
4416                 }
4417         }
4418         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4419                                     (cnt_free - pool->counters_raw));
4420         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4421         /* Update the counter reset values. */
4422         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4423                                  &cnt_free->bytes))
4424                 return 0;
4425         if (cnt_ext) {
4426                 cnt_ext->shared = shared;
4427                 cnt_ext->ref_cnt = 1;
4428                 cnt_ext->id = id;
4429         }
4430         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4431                 /* Start the asynchronous batch query by the host thread. */
4432                 mlx5_set_query_alarm(priv->sh);
4433         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4434         if (TAILQ_EMPTY(&pool->counters)) {
4435                 /* Move the pool to the end of the container pool list. */
4436                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4437                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4438         }
4439         return cnt_idx;
4440 }
4441
4442 /**
4443  * Release a flow counter.
4444  *
4445  * @param[in] dev
4446  *   Pointer to the Ethernet device structure.
4447  * @param[in] counter
4448  *   Index to the counter handler.
4449  */
4450 static void
4451 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4452 {
4453         struct mlx5_flow_counter_pool *pool = NULL;
4454         struct mlx5_flow_counter *cnt;
4455         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4456
4457         if (!counter)
4458                 return;
4459         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4460         MLX5_ASSERT(pool);
4461         if (counter < MLX5_CNT_BATCH_OFFSET) {
4462                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4463                 if (cnt_ext && --cnt_ext->ref_cnt)
4464                         return;
4465         }
4466         /* Put the counter in the end - the last updated one. */
4467         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4468         /*
4469          * Counters released between query trigger and handler need
4470          * to wait the next round of query. Since the packets arrive
4471          * in the gap period will not be taken into account to the
4472          * old counter.
4473          */
4474         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4475 }
4476
4477 /**
4478  * Verify the @p attributes will be correctly understood by the NIC and store
4479  * them in the @p flow if everything is correct.
4480  *
4481  * @param[in] dev
4482  *   Pointer to dev struct.
4483  * @param[in] attributes
4484  *   Pointer to flow attributes
4485  * @param[in] external
4486  *   This flow rule is created by request external to PMD.
4487  * @param[out] error
4488  *   Pointer to error structure.
4489  *
4490  * @return
4491  *   - 0 on success and non root table.
4492  *   - 1 on success and root table.
4493  *   - a negative errno value otherwise and rte_errno is set.
4494  */
4495 static int
4496 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4497                             const struct rte_flow_attr *attributes,
4498                             bool external __rte_unused,
4499                             struct rte_flow_error *error)
4500 {
4501         struct mlx5_priv *priv = dev->data->dev_private;
4502         uint32_t priority_max = priv->config.flow_prio - 1;
4503         int ret = 0;
4504
4505 #ifndef HAVE_MLX5DV_DR
4506         if (attributes->group)
4507                 return rte_flow_error_set(error, ENOTSUP,
4508                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4509                                           NULL,
4510                                           "groups are not supported");
4511 #else
4512         uint32_t table = 0;
4513
4514         ret = mlx5_flow_group_to_table(attributes, external,
4515                                        attributes->group, !!priv->fdb_def_rule,
4516                                        &table, error);
4517         if (ret)
4518                 return ret;
4519         if (!table)
4520                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4521 #endif
4522         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4523             attributes->priority >= priority_max)
4524                 return rte_flow_error_set(error, ENOTSUP,
4525                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4526                                           NULL,
4527                                           "priority out of range");
4528         if (attributes->transfer) {
4529                 if (!priv->config.dv_esw_en)
4530                         return rte_flow_error_set
4531                                 (error, ENOTSUP,
4532                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4533                                  "E-Switch dr is not supported");
4534                 if (!(priv->representor || priv->master))
4535                         return rte_flow_error_set
4536                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4537                                  NULL, "E-Switch configuration can only be"
4538                                  " done by a master or a representor device");
4539                 if (attributes->egress)
4540                         return rte_flow_error_set
4541                                 (error, ENOTSUP,
4542                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4543                                  "egress is not supported");
4544         }
4545         if (!(attributes->egress ^ attributes->ingress))
4546                 return rte_flow_error_set(error, ENOTSUP,
4547                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4548                                           "must specify exactly one of "
4549                                           "ingress or egress");
4550         return ret;
4551 }
4552
4553 /**
4554  * Internal validation function. For validating both actions and items.
4555  *
4556  * @param[in] dev
4557  *   Pointer to the rte_eth_dev structure.
4558  * @param[in] attr
4559  *   Pointer to the flow attributes.
4560  * @param[in] items
4561  *   Pointer to the list of items.
4562  * @param[in] actions
4563  *   Pointer to the list of actions.
4564  * @param[in] external
4565  *   This flow rule is created by request external to PMD.
4566  * @param[in] hairpin
4567  *   Number of hairpin TX actions, 0 means classic flow.
4568  * @param[out] error
4569  *   Pointer to the error structure.
4570  *
4571  * @return
4572  *   0 on success, a negative errno value otherwise and rte_errno is set.
4573  */
4574 static int
4575 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4576                  const struct rte_flow_item items[],
4577                  const struct rte_flow_action actions[],
4578                  bool external, int hairpin, struct rte_flow_error *error)
4579 {
4580         int ret;
4581         uint64_t action_flags = 0;
4582         uint64_t item_flags = 0;
4583         uint64_t last_item = 0;
4584         uint8_t next_protocol = 0xff;
4585         uint16_t ether_type = 0;
4586         int actions_n = 0;
4587         uint8_t item_ipv6_proto = 0;
4588         const struct rte_flow_item *gre_item = NULL;
4589         const struct rte_flow_action_raw_decap *decap;
4590         const struct rte_flow_action_raw_encap *encap;
4591         const struct rte_flow_action_rss *rss;
4592         const struct rte_flow_item_tcp nic_tcp_mask = {
4593                 .hdr = {
4594                         .tcp_flags = 0xFF,
4595                         .src_port = RTE_BE16(UINT16_MAX),
4596                         .dst_port = RTE_BE16(UINT16_MAX),
4597                 }
4598         };
4599         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4600                 .hdr = {
4601                         .src_addr = RTE_BE32(0xffffffff),
4602                         .dst_addr = RTE_BE32(0xffffffff),
4603                         .type_of_service = 0xff,
4604                         .next_proto_id = 0xff,
4605                         .time_to_live = 0xff,
4606                 },
4607         };
4608         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4609                 .hdr = {
4610                         .src_addr =
4611                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4612                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4613                         .dst_addr =
4614                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4615                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4616                         .vtc_flow = RTE_BE32(0xffffffff),
4617                         .proto = 0xff,
4618                         .hop_limits = 0xff,
4619                 },
4620         };
4621         struct mlx5_priv *priv = dev->data->dev_private;
4622         struct mlx5_dev_config *dev_conf = &priv->config;
4623         uint16_t queue_index = 0xFFFF;
4624         const struct rte_flow_item_vlan *vlan_m = NULL;
4625         int16_t rw_act_num = 0;
4626         uint64_t is_root;
4627
4628         if (items == NULL)
4629                 return -1;
4630         ret = flow_dv_validate_attributes(dev, attr, external, error);
4631         if (ret < 0)
4632                 return ret;
4633         is_root = (uint64_t)ret;
4634         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4635                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4636                 int type = items->type;
4637
4638                 switch (type) {
4639                 case RTE_FLOW_ITEM_TYPE_VOID:
4640                         break;
4641                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4642                         ret = flow_dv_validate_item_port_id
4643                                         (dev, items, attr, item_flags, error);
4644                         if (ret < 0)
4645                                 return ret;
4646                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4647                         break;
4648                 case RTE_FLOW_ITEM_TYPE_ETH:
4649                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4650                                                           error);
4651                         if (ret < 0)
4652                                 return ret;
4653                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4654                                              MLX5_FLOW_LAYER_OUTER_L2;
4655                         if (items->mask != NULL && items->spec != NULL) {
4656                                 ether_type =
4657                                         ((const struct rte_flow_item_eth *)
4658                                          items->spec)->type;
4659                                 ether_type &=
4660                                         ((const struct rte_flow_item_eth *)
4661                                          items->mask)->type;
4662                                 ether_type = rte_be_to_cpu_16(ether_type);
4663                         } else {
4664                                 ether_type = 0;
4665                         }
4666                         break;
4667                 case RTE_FLOW_ITEM_TYPE_VLAN:
4668                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4669                                                            dev, error);
4670                         if (ret < 0)
4671                                 return ret;
4672                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4673                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4674                         if (items->mask != NULL && items->spec != NULL) {
4675                                 ether_type =
4676                                         ((const struct rte_flow_item_vlan *)
4677                                          items->spec)->inner_type;
4678                                 ether_type &=
4679                                         ((const struct rte_flow_item_vlan *)
4680                                          items->mask)->inner_type;
4681                                 ether_type = rte_be_to_cpu_16(ether_type);
4682                         } else {
4683                                 ether_type = 0;
4684                         }
4685                         /* Store outer VLAN mask for of_push_vlan action. */
4686                         if (!tunnel)
4687                                 vlan_m = items->mask;
4688                         break;
4689                 case RTE_FLOW_ITEM_TYPE_IPV4:
4690                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4691                                                   &item_flags, &tunnel);
4692                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4693                                                            last_item,
4694                                                            ether_type,
4695                                                            &nic_ipv4_mask,
4696                                                            error);
4697                         if (ret < 0)
4698                                 return ret;
4699                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4700                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4701                         if (items->mask != NULL &&
4702                             ((const struct rte_flow_item_ipv4 *)
4703                              items->mask)->hdr.next_proto_id) {
4704                                 next_protocol =
4705                                         ((const struct rte_flow_item_ipv4 *)
4706                                          (items->spec))->hdr.next_proto_id;
4707                                 next_protocol &=
4708                                         ((const struct rte_flow_item_ipv4 *)
4709                                          (items->mask))->hdr.next_proto_id;
4710                         } else {
4711                                 /* Reset for inner layer. */
4712                                 next_protocol = 0xff;
4713                         }
4714                         break;
4715                 case RTE_FLOW_ITEM_TYPE_IPV6:
4716                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4717                                                   &item_flags, &tunnel);
4718                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4719                                                            last_item,
4720                                                            ether_type,
4721                                                            &nic_ipv6_mask,
4722                                                            error);
4723                         if (ret < 0)
4724                                 return ret;
4725                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4726                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4727                         if (items->mask != NULL &&
4728                             ((const struct rte_flow_item_ipv6 *)
4729                              items->mask)->hdr.proto) {
4730                                 item_ipv6_proto =
4731                                         ((const struct rte_flow_item_ipv6 *)
4732                                          items->spec)->hdr.proto;
4733                                 next_protocol =
4734                                         ((const struct rte_flow_item_ipv6 *)
4735                                          items->spec)->hdr.proto;
4736                                 next_protocol &=
4737                                         ((const struct rte_flow_item_ipv6 *)
4738                                          items->mask)->hdr.proto;
4739                         } else {
4740                                 /* Reset for inner layer. */
4741                                 next_protocol = 0xff;
4742                         }
4743                         break;
4744                 case RTE_FLOW_ITEM_TYPE_TCP:
4745                         ret = mlx5_flow_validate_item_tcp
4746                                                 (items, item_flags,
4747                                                  next_protocol,
4748                                                  &nic_tcp_mask,
4749                                                  error);
4750                         if (ret < 0)
4751                                 return ret;
4752                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4753                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4754                         break;
4755                 case RTE_FLOW_ITEM_TYPE_UDP:
4756                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4757                                                           next_protocol,
4758                                                           error);
4759                         if (ret < 0)
4760                                 return ret;
4761                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4762                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4763                         break;
4764                 case RTE_FLOW_ITEM_TYPE_GRE:
4765                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4766                                                           next_protocol, error);
4767                         if (ret < 0)
4768                                 return ret;
4769                         gre_item = items;
4770                         last_item = MLX5_FLOW_LAYER_GRE;
4771                         break;
4772                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4773                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4774                                                             next_protocol,
4775                                                             error);
4776                         if (ret < 0)
4777                                 return ret;
4778                         last_item = MLX5_FLOW_LAYER_NVGRE;
4779                         break;
4780                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4781                         ret = mlx5_flow_validate_item_gre_key
4782                                 (items, item_flags, gre_item, error);
4783                         if (ret < 0)
4784                                 return ret;
4785                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4786                         break;
4787                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4788                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4789                                                             error);
4790                         if (ret < 0)
4791                                 return ret;
4792                         last_item = MLX5_FLOW_LAYER_VXLAN;
4793                         break;
4794                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4795                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4796                                                                 item_flags, dev,
4797                                                                 error);
4798                         if (ret < 0)
4799                                 return ret;
4800                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4801                         break;
4802                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4803                         ret = mlx5_flow_validate_item_geneve(items,
4804                                                              item_flags, dev,
4805                                                              error);
4806                         if (ret < 0)
4807                                 return ret;
4808                         last_item = MLX5_FLOW_LAYER_GENEVE;
4809                         break;
4810                 case RTE_FLOW_ITEM_TYPE_MPLS:
4811                         ret = mlx5_flow_validate_item_mpls(dev, items,
4812                                                            item_flags,
4813                                                            last_item, error);
4814                         if (ret < 0)
4815                                 return ret;
4816                         last_item = MLX5_FLOW_LAYER_MPLS;
4817                         break;
4818
4819                 case RTE_FLOW_ITEM_TYPE_MARK:
4820                         ret = flow_dv_validate_item_mark(dev, items, attr,
4821                                                          error);
4822                         if (ret < 0)
4823                                 return ret;
4824                         last_item = MLX5_FLOW_ITEM_MARK;
4825                         break;
4826                 case RTE_FLOW_ITEM_TYPE_META:
4827                         ret = flow_dv_validate_item_meta(dev, items, attr,
4828                                                          error);
4829                         if (ret < 0)
4830                                 return ret;
4831                         last_item = MLX5_FLOW_ITEM_METADATA;
4832                         break;
4833                 case RTE_FLOW_ITEM_TYPE_ICMP:
4834                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4835                                                            next_protocol,
4836                                                            error);
4837                         if (ret < 0)
4838                                 return ret;
4839                         last_item = MLX5_FLOW_LAYER_ICMP;
4840                         break;
4841                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4842                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4843                                                             next_protocol,
4844                                                             error);
4845                         if (ret < 0)
4846                                 return ret;
4847                         item_ipv6_proto = IPPROTO_ICMPV6;
4848                         last_item = MLX5_FLOW_LAYER_ICMP6;
4849                         break;
4850                 case RTE_FLOW_ITEM_TYPE_TAG:
4851                         ret = flow_dv_validate_item_tag(dev, items,
4852                                                         attr, error);
4853                         if (ret < 0)
4854                                 return ret;
4855                         last_item = MLX5_FLOW_ITEM_TAG;
4856                         break;
4857                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4858                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4859                         break;
4860                 case RTE_FLOW_ITEM_TYPE_GTP:
4861                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4862                                                         error);
4863                         if (ret < 0)
4864                                 return ret;
4865                         last_item = MLX5_FLOW_LAYER_GTP;
4866                         break;
4867                 default:
4868                         return rte_flow_error_set(error, ENOTSUP,
4869                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4870                                                   NULL, "item not supported");
4871                 }
4872                 item_flags |= last_item;
4873         }
4874         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4875                 int type = actions->type;
4876                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4877                         return rte_flow_error_set(error, ENOTSUP,
4878                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4879                                                   actions, "too many actions");
4880                 switch (type) {
4881                 case RTE_FLOW_ACTION_TYPE_VOID:
4882                         break;
4883                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4884                         ret = flow_dv_validate_action_port_id(dev,
4885                                                               action_flags,
4886                                                               actions,
4887                                                               attr,
4888                                                               error);
4889                         if (ret)
4890                                 return ret;
4891                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4892                         ++actions_n;
4893                         break;
4894                 case RTE_FLOW_ACTION_TYPE_FLAG:
4895                         ret = flow_dv_validate_action_flag(dev, action_flags,
4896                                                            attr, error);
4897                         if (ret < 0)
4898                                 return ret;
4899                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4900                                 /* Count all modify-header actions as one. */
4901                                 if (!(action_flags &
4902                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4903                                         ++actions_n;
4904                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4905                                                 MLX5_FLOW_ACTION_MARK_EXT;
4906                         } else {
4907                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4908                                 ++actions_n;
4909                         }
4910                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
4911                         break;
4912                 case RTE_FLOW_ACTION_TYPE_MARK:
4913                         ret = flow_dv_validate_action_mark(dev, actions,
4914                                                            action_flags,
4915                                                            attr, error);
4916                         if (ret < 0)
4917                                 return ret;
4918                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4919                                 /* Count all modify-header actions as one. */
4920                                 if (!(action_flags &
4921                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4922                                         ++actions_n;
4923                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4924                                                 MLX5_FLOW_ACTION_MARK_EXT;
4925                         } else {
4926                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4927                                 ++actions_n;
4928                         }
4929                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
4930                         break;
4931                 case RTE_FLOW_ACTION_TYPE_SET_META:
4932                         ret = flow_dv_validate_action_set_meta(dev, actions,
4933                                                                action_flags,
4934                                                                attr, error);
4935                         if (ret < 0)
4936                                 return ret;
4937                         /* Count all modify-header actions as one action. */
4938                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4939                                 ++actions_n;
4940                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4941                         rw_act_num += MLX5_ACT_NUM_SET_META;
4942                         break;
4943                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4944                         ret = flow_dv_validate_action_set_tag(dev, actions,
4945                                                               action_flags,
4946                                                               attr, error);
4947                         if (ret < 0)
4948                                 return ret;
4949                         /* Count all modify-header actions as one action. */
4950                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4951                                 ++actions_n;
4952                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4953                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
4954                         break;
4955                 case RTE_FLOW_ACTION_TYPE_DROP:
4956                         ret = mlx5_flow_validate_action_drop(action_flags,
4957                                                              attr, error);
4958                         if (ret < 0)
4959                                 return ret;
4960                         action_flags |= MLX5_FLOW_ACTION_DROP;
4961                         ++actions_n;
4962                         break;
4963                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4964                         ret = mlx5_flow_validate_action_queue(actions,
4965                                                               action_flags, dev,
4966                                                               attr, error);
4967                         if (ret < 0)
4968                                 return ret;
4969                         queue_index = ((const struct rte_flow_action_queue *)
4970                                                         (actions->conf))->index;
4971                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
4972                         ++actions_n;
4973                         break;
4974                 case RTE_FLOW_ACTION_TYPE_RSS:
4975                         rss = actions->conf;
4976                         ret = mlx5_flow_validate_action_rss(actions,
4977                                                             action_flags, dev,
4978                                                             attr, item_flags,
4979                                                             error);
4980                         if (ret < 0)
4981                                 return ret;
4982                         if (rss != NULL && rss->queue_num)
4983                                 queue_index = rss->queue[0];
4984                         action_flags |= MLX5_FLOW_ACTION_RSS;
4985                         ++actions_n;
4986                         break;
4987                 case RTE_FLOW_ACTION_TYPE_COUNT:
4988                         ret = flow_dv_validate_action_count(dev, error);
4989                         if (ret < 0)
4990                                 return ret;
4991                         action_flags |= MLX5_FLOW_ACTION_COUNT;
4992                         ++actions_n;
4993                         break;
4994                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4995                         if (flow_dv_validate_action_pop_vlan(dev,
4996                                                              action_flags,
4997                                                              actions,
4998                                                              item_flags, attr,
4999                                                              error))
5000                                 return -rte_errno;
5001                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5002                         ++actions_n;
5003                         break;
5004                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5005                         ret = flow_dv_validate_action_push_vlan(dev,
5006                                                                 action_flags,
5007                                                                 vlan_m,
5008                                                                 actions, attr,
5009                                                                 error);
5010                         if (ret < 0)
5011                                 return ret;
5012                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5013                         ++actions_n;
5014                         break;
5015                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5016                         ret = flow_dv_validate_action_set_vlan_pcp
5017                                                 (action_flags, actions, error);
5018                         if (ret < 0)
5019                                 return ret;
5020                         /* Count PCP with push_vlan command. */
5021                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5022                         break;
5023                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5024                         ret = flow_dv_validate_action_set_vlan_vid
5025                                                 (item_flags, action_flags,
5026                                                  actions, error);
5027                         if (ret < 0)
5028                                 return ret;
5029                         /* Count VID with push_vlan command. */
5030                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5031                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5032                         break;
5033                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5034                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5035                         ret = flow_dv_validate_action_l2_encap(dev,
5036                                                                action_flags,
5037                                                                actions, attr,
5038                                                                error);
5039                         if (ret < 0)
5040                                 return ret;
5041                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5042                         ++actions_n;
5043                         break;
5044                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5045                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5046                         ret = flow_dv_validate_action_decap(dev, action_flags,
5047                                                             attr, error);
5048                         if (ret < 0)
5049                                 return ret;
5050                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5051                         ++actions_n;
5052                         break;
5053                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5054                         ret = flow_dv_validate_action_raw_encap_decap
5055                                 (dev, NULL, actions->conf, attr, &action_flags,
5056                                  &actions_n, error);
5057                         if (ret < 0)
5058                                 return ret;
5059                         break;
5060                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5061                         decap = actions->conf;
5062                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5063                                 ;
5064                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5065                                 encap = NULL;
5066                                 actions--;
5067                         } else {
5068                                 encap = actions->conf;
5069                         }
5070                         ret = flow_dv_validate_action_raw_encap_decap
5071                                            (dev,
5072                                             decap ? decap : &empty_decap, encap,
5073                                             attr, &action_flags, &actions_n,
5074                                             error);
5075                         if (ret < 0)
5076                                 return ret;
5077                         break;
5078                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5079                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5080                         ret = flow_dv_validate_action_modify_mac(action_flags,
5081                                                                  actions,
5082                                                                  item_flags,
5083                                                                  error);
5084                         if (ret < 0)
5085                                 return ret;
5086                         /* Count all modify-header actions as one action. */
5087                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5088                                 ++actions_n;
5089                         action_flags |= actions->type ==
5090                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5091                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5092                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5093                         /*
5094                          * Even if the source and destination MAC addresses have
5095                          * overlap in the header with 4B alignment, the convert
5096                          * function will handle them separately and 4 SW actions
5097                          * will be created. And 2 actions will be added each
5098                          * time no matter how many bytes of address will be set.
5099                          */
5100                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5101                         break;
5102                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5103                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5104                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5105                                                                   actions,
5106                                                                   item_flags,
5107                                                                   error);
5108                         if (ret < 0)
5109                                 return ret;
5110                         /* Count all modify-header actions as one action. */
5111                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5112                                 ++actions_n;
5113                         action_flags |= actions->type ==
5114                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5115                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5116                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5117                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5118                         break;
5119                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5120                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5121                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5122                                                                   actions,
5123                                                                   item_flags,
5124                                                                   error);
5125                         if (ret < 0)
5126                                 return ret;
5127                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5128                                 return rte_flow_error_set(error, ENOTSUP,
5129                                         RTE_FLOW_ERROR_TYPE_ACTION,
5130                                         actions,
5131                                         "Can't change header "
5132                                         "with ICMPv6 proto");
5133                         /* Count all modify-header actions as one action. */
5134                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5135                                 ++actions_n;
5136                         action_flags |= actions->type ==
5137                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5138                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5139                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5140                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5141                         break;
5142                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5143                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5144                         ret = flow_dv_validate_action_modify_tp(action_flags,
5145                                                                 actions,
5146                                                                 item_flags,
5147                                                                 error);
5148                         if (ret < 0)
5149                                 return ret;
5150                         /* Count all modify-header actions as one action. */
5151                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5152                                 ++actions_n;
5153                         action_flags |= actions->type ==
5154                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5155                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5156                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5157                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5158                         break;
5159                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5160                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5161                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5162                                                                  actions,
5163                                                                  item_flags,
5164                                                                  error);
5165                         if (ret < 0)
5166                                 return ret;
5167                         /* Count all modify-header actions as one action. */
5168                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5169                                 ++actions_n;
5170                         action_flags |= actions->type ==
5171                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5172                                                 MLX5_FLOW_ACTION_SET_TTL :
5173                                                 MLX5_FLOW_ACTION_DEC_TTL;
5174                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5175                         break;
5176                 case RTE_FLOW_ACTION_TYPE_JUMP:
5177                         ret = flow_dv_validate_action_jump(actions,
5178                                                            action_flags,
5179                                                            attr, external,
5180                                                            error);
5181                         if (ret)
5182                                 return ret;
5183                         ++actions_n;
5184                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5185                         break;
5186                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5187                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5188                         ret = flow_dv_validate_action_modify_tcp_seq
5189                                                                 (action_flags,
5190                                                                  actions,
5191                                                                  item_flags,
5192                                                                  error);
5193                         if (ret < 0)
5194                                 return ret;
5195                         /* Count all modify-header actions as one action. */
5196                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5197                                 ++actions_n;
5198                         action_flags |= actions->type ==
5199                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5200                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5201                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5202                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5203                         break;
5204                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5205                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5206                         ret = flow_dv_validate_action_modify_tcp_ack
5207                                                                 (action_flags,
5208                                                                  actions,
5209                                                                  item_flags,
5210                                                                  error);
5211                         if (ret < 0)
5212                                 return ret;
5213                         /* Count all modify-header actions as one action. */
5214                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5215                                 ++actions_n;
5216                         action_flags |= actions->type ==
5217                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5218                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5219                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5220                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5221                         break;
5222                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5223                         break;
5224                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5225                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5226                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5227                         break;
5228                 case RTE_FLOW_ACTION_TYPE_METER:
5229                         ret = mlx5_flow_validate_action_meter(dev,
5230                                                               action_flags,
5231                                                               actions, attr,
5232                                                               error);
5233                         if (ret < 0)
5234                                 return ret;
5235                         action_flags |= MLX5_FLOW_ACTION_METER;
5236                         ++actions_n;
5237                         /* Meter action will add one more TAG action. */
5238                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5239                         break;
5240                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5241                         ret = flow_dv_validate_action_modify_ipv4_dscp
5242                                                          (action_flags,
5243                                                           actions,
5244                                                           item_flags,
5245                                                           error);
5246                         if (ret < 0)
5247                                 return ret;
5248                         /* Count all modify-header actions as one action. */
5249                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5250                                 ++actions_n;
5251                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5252                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5253                         break;
5254                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5255                         ret = flow_dv_validate_action_modify_ipv6_dscp
5256                                                                 (action_flags,
5257                                                                  actions,
5258                                                                  item_flags,
5259                                                                  error);
5260                         if (ret < 0)
5261                                 return ret;
5262                         /* Count all modify-header actions as one action. */
5263                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5264                                 ++actions_n;
5265                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5266                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5267                         break;
5268                 default:
5269                         return rte_flow_error_set(error, ENOTSUP,
5270                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5271                                                   actions,
5272                                                   "action not supported");
5273                 }
5274         }
5275         /*
5276          * Validate the drop action mutual exclusion with other actions.
5277          * Drop action is mutually-exclusive with any other action, except for
5278          * Count action.
5279          */
5280         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5281             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5282                 return rte_flow_error_set(error, EINVAL,
5283                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5284                                           "Drop action is mutually-exclusive "
5285                                           "with any other action, except for "
5286                                           "Count action");
5287         /* Eswitch has few restrictions on using items and actions */
5288         if (attr->transfer) {
5289                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5290                     action_flags & MLX5_FLOW_ACTION_FLAG)
5291                         return rte_flow_error_set(error, ENOTSUP,
5292                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5293                                                   NULL,
5294                                                   "unsupported action FLAG");
5295                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5296                     action_flags & MLX5_FLOW_ACTION_MARK)
5297                         return rte_flow_error_set(error, ENOTSUP,
5298                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5299                                                   NULL,
5300                                                   "unsupported action MARK");
5301                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5302                         return rte_flow_error_set(error, ENOTSUP,
5303                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5304                                                   NULL,
5305                                                   "unsupported action QUEUE");
5306                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5307                         return rte_flow_error_set(error, ENOTSUP,
5308                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5309                                                   NULL,
5310                                                   "unsupported action RSS");
5311                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5312                         return rte_flow_error_set(error, EINVAL,
5313                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5314                                                   actions,
5315                                                   "no fate action is found");
5316         } else {
5317                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5318                         return rte_flow_error_set(error, EINVAL,
5319                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5320                                                   actions,
5321                                                   "no fate action is found");
5322         }
5323         /* Continue validation for Xcap actions.*/
5324         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5325             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5326                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5327                     MLX5_FLOW_XCAP_ACTIONS)
5328                         return rte_flow_error_set(error, ENOTSUP,
5329                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5330                                                   NULL, "encap and decap "
5331                                                   "combination aren't supported");
5332                 if (!attr->transfer && attr->ingress && (action_flags &
5333                                                         MLX5_FLOW_ACTION_ENCAP))
5334                         return rte_flow_error_set(error, ENOTSUP,
5335                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5336                                                   NULL, "encap is not supported"
5337                                                   " for ingress traffic");
5338         }
5339         /* Hairpin flow will add one more TAG action. */
5340         if (hairpin > 0)
5341                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5342         /* extra metadata enabled: one more TAG action will be add. */
5343         if (dev_conf->dv_flow_en &&
5344             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5345             mlx5_flow_ext_mreg_supported(dev))
5346                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5347         if ((uint32_t)rw_act_num >
5348                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5349                 return rte_flow_error_set(error, ENOTSUP,
5350                                           RTE_FLOW_ERROR_TYPE_ACTION,
5351                                           NULL, "too many header modify"
5352                                           " actions to support");
5353         }
5354         return 0;
5355 }
5356
5357 /**
5358  * Internal preparation function. Allocates the DV flow size,
5359  * this size is constant.
5360  *
5361  * @param[in] dev
5362  *   Pointer to the rte_eth_dev structure.
5363  * @param[in] attr
5364  *   Pointer to the flow attributes.
5365  * @param[in] items
5366  *   Pointer to the list of items.
5367  * @param[in] actions
5368  *   Pointer to the list of actions.
5369  * @param[out] error
5370  *   Pointer to the error structure.
5371  *
5372  * @return
5373  *   Pointer to mlx5_flow object on success,
5374  *   otherwise NULL and rte_errno is set.
5375  */
5376 static struct mlx5_flow *
5377 flow_dv_prepare(struct rte_eth_dev *dev,
5378                 const struct rte_flow_attr *attr __rte_unused,
5379                 const struct rte_flow_item items[] __rte_unused,
5380                 const struct rte_flow_action actions[] __rte_unused,
5381                 struct rte_flow_error *error)
5382 {
5383         uint32_t handle_idx = 0;
5384         struct mlx5_flow *dev_flow;
5385         struct mlx5_flow_handle *dev_handle;
5386         struct mlx5_priv *priv = dev->data->dev_private;
5387
5388         /* In case of corrupting the memory. */
5389         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5390                 rte_flow_error_set(error, ENOSPC,
5391                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5392                                    "not free temporary device flow");
5393                 return NULL;
5394         }
5395         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5396                                    &handle_idx);
5397         if (!dev_handle) {
5398                 rte_flow_error_set(error, ENOMEM,
5399                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5400                                    "not enough memory to create flow handle");
5401                 return NULL;
5402         }
5403         /* No multi-thread supporting. */
5404         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5405         dev_flow->handle = dev_handle;
5406         dev_flow->handle_idx = handle_idx;
5407         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5408         /*
5409          * The matching value needs to be cleared to 0 before using. In the
5410          * past, it will be automatically cleared when using rte_*alloc
5411          * API. The time consumption will be almost the same as before.
5412          */
5413         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5414         dev_flow->ingress = attr->ingress;
5415         dev_flow->dv.transfer = attr->transfer;
5416         return dev_flow;
5417 }
5418
5419 #ifdef RTE_LIBRTE_MLX5_DEBUG
5420 /**
5421  * Sanity check for match mask and value. Similar to check_valid_spec() in
5422  * kernel driver. If unmasked bit is present in value, it returns failure.
5423  *
5424  * @param match_mask
5425  *   pointer to match mask buffer.
5426  * @param match_value
5427  *   pointer to match value buffer.
5428  *
5429  * @return
5430  *   0 if valid, -EINVAL otherwise.
5431  */
5432 static int
5433 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5434 {
5435         uint8_t *m = match_mask;
5436         uint8_t *v = match_value;
5437         unsigned int i;
5438
5439         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5440                 if (v[i] & ~m[i]) {
5441                         DRV_LOG(ERR,
5442                                 "match_value differs from match_criteria"
5443                                 " %p[%u] != %p[%u]",
5444                                 match_value, i, match_mask, i);
5445                         return -EINVAL;
5446                 }
5447         }
5448         return 0;
5449 }
5450 #endif
5451
5452 /**
5453  * Add Ethernet item to matcher and to the value.
5454  *
5455  * @param[in, out] matcher
5456  *   Flow matcher.
5457  * @param[in, out] key
5458  *   Flow matcher value.
5459  * @param[in] item
5460  *   Flow pattern to translate.
5461  * @param[in] inner
5462  *   Item is inner pattern.
5463  */
5464 static void
5465 flow_dv_translate_item_eth(void *matcher, void *key,
5466                            const struct rte_flow_item *item, int inner)
5467 {
5468         const struct rte_flow_item_eth *eth_m = item->mask;
5469         const struct rte_flow_item_eth *eth_v = item->spec;
5470         const struct rte_flow_item_eth nic_mask = {
5471                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5472                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5473                 .type = RTE_BE16(0xffff),
5474         };
5475         void *headers_m;
5476         void *headers_v;
5477         char *l24_v;
5478         unsigned int i;
5479
5480         if (!eth_v)
5481                 return;
5482         if (!eth_m)
5483                 eth_m = &nic_mask;
5484         if (inner) {
5485                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5486                                          inner_headers);
5487                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5488         } else {
5489                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5490                                          outer_headers);
5491                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5492         }
5493         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5494                &eth_m->dst, sizeof(eth_m->dst));
5495         /* The value must be in the range of the mask. */
5496         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5497         for (i = 0; i < sizeof(eth_m->dst); ++i)
5498                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5499         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5500                &eth_m->src, sizeof(eth_m->src));
5501         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5502         /* The value must be in the range of the mask. */
5503         for (i = 0; i < sizeof(eth_m->dst); ++i)
5504                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5505         if (eth_v->type) {
5506                 /* When ethertype is present set mask for tagged VLAN. */
5507                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5508                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5509                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5510                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5511                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5512                                  1);
5513                         /* Return here to avoid setting match on ethertype. */
5514                         return;
5515                 }
5516         }
5517         /*
5518          * HW supports match on one Ethertype, the Ethertype following the last
5519          * VLAN tag of the packet (see PRM).
5520          * Set match on ethertype only if ETH header is not followed by VLAN.
5521          */
5522         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5523                  rte_be_to_cpu_16(eth_m->type));
5524         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5525         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5526 }
5527
5528 /**
5529  * Add VLAN item to matcher and to the value.
5530  *
5531  * @param[in, out] dev_flow
5532  *   Flow descriptor.
5533  * @param[in, out] matcher
5534  *   Flow matcher.
5535  * @param[in, out] key
5536  *   Flow matcher value.
5537  * @param[in] item
5538  *   Flow pattern to translate.
5539  * @param[in] inner
5540  *   Item is inner pattern.
5541  */
5542 static void
5543 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5544                             void *matcher, void *key,
5545                             const struct rte_flow_item *item,
5546                             int inner)
5547 {
5548         const struct rte_flow_item_vlan *vlan_m = item->mask;
5549         const struct rte_flow_item_vlan *vlan_v = item->spec;
5550         void *headers_m;
5551         void *headers_v;
5552         uint16_t tci_m;
5553         uint16_t tci_v;
5554
5555         if (!vlan_v)
5556                 return;
5557         if (!vlan_m)
5558                 vlan_m = &rte_flow_item_vlan_mask;
5559         if (inner) {
5560                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5561                                          inner_headers);
5562                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5563         } else {
5564                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5565                                          outer_headers);
5566                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5567                 /*
5568                  * This is workaround, masks are not supported,
5569                  * and pre-validated.
5570                  */
5571                 dev_flow->handle->vf_vlan.tag =
5572                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5573         }
5574         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5575         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5576         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5577         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5578         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5579         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5580         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5581         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5582         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5583         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5584         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5585                  rte_be_to_cpu_16(vlan_m->inner_type));
5586         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5587                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5588 }
5589
5590 /**
5591  * Add IPV4 item to matcher and to the value.
5592  *
5593  * @param[in, out] matcher
5594  *   Flow matcher.
5595  * @param[in, out] key
5596  *   Flow matcher value.
5597  * @param[in] item
5598  *   Flow pattern to translate.
5599  * @param[in] item_flags
5600  *   Bit-fields that holds the items detected until now.
5601  * @param[in] inner
5602  *   Item is inner pattern.
5603  * @param[in] group
5604  *   The group to insert the rule.
5605  */
5606 static void
5607 flow_dv_translate_item_ipv4(void *matcher, void *key,
5608                             const struct rte_flow_item *item,
5609                             const uint64_t item_flags,
5610                             int inner, uint32_t group)
5611 {
5612         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5613         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5614         const struct rte_flow_item_ipv4 nic_mask = {
5615                 .hdr = {
5616                         .src_addr = RTE_BE32(0xffffffff),
5617                         .dst_addr = RTE_BE32(0xffffffff),
5618                         .type_of_service = 0xff,
5619                         .next_proto_id = 0xff,
5620                         .time_to_live = 0xff,
5621                 },
5622         };
5623         void *headers_m;
5624         void *headers_v;
5625         char *l24_m;
5626         char *l24_v;
5627         uint8_t tos;
5628
5629         if (inner) {
5630                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5631                                          inner_headers);
5632                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5633         } else {
5634                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5635                                          outer_headers);
5636                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5637         }
5638         if (group == 0)
5639                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5640         else
5641                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5642         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5643         /*
5644          * On outer header (which must contains L2), or inner header with L2,
5645          * set cvlan_tag mask bit to mark this packet as untagged.
5646          * This should be done even if item->spec is empty.
5647          */
5648         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5649                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5650         if (!ipv4_v)
5651                 return;
5652         if (!ipv4_m)
5653                 ipv4_m = &nic_mask;
5654         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5655                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5656         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5657                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5658         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5659         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5660         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5661                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5662         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5663                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5664         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5665         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5666         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5667         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5668                  ipv4_m->hdr.type_of_service);
5669         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5670         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5671                  ipv4_m->hdr.type_of_service >> 2);
5672         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5673         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5674                  ipv4_m->hdr.next_proto_id);
5675         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5676                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5677         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5678                  ipv4_m->hdr.time_to_live);
5679         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5680                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5681 }
5682
5683 /**
5684  * Add IPV6 item to matcher and to the value.
5685  *
5686  * @param[in, out] matcher
5687  *   Flow matcher.
5688  * @param[in, out] key
5689  *   Flow matcher value.
5690  * @param[in] item
5691  *   Flow pattern to translate.
5692  * @param[in] item_flags
5693  *   Bit-fields that holds the items detected until now.
5694  * @param[in] inner
5695  *   Item is inner pattern.
5696  * @param[in] group
5697  *   The group to insert the rule.
5698  */
5699 static void
5700 flow_dv_translate_item_ipv6(void *matcher, void *key,
5701                             const struct rte_flow_item *item,
5702                             const uint64_t item_flags,
5703                             int inner, uint32_t group)
5704 {
5705         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5706         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5707         const struct rte_flow_item_ipv6 nic_mask = {
5708                 .hdr = {
5709                         .src_addr =
5710                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5711                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5712                         .dst_addr =
5713                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5714                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5715                         .vtc_flow = RTE_BE32(0xffffffff),
5716                         .proto = 0xff,
5717                         .hop_limits = 0xff,
5718                 },
5719         };
5720         void *headers_m;
5721         void *headers_v;
5722         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5723         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5724         char *l24_m;
5725         char *l24_v;
5726         uint32_t vtc_m;
5727         uint32_t vtc_v;
5728         int i;
5729         int size;
5730
5731         if (inner) {
5732                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5733                                          inner_headers);
5734                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5735         } else {
5736                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5737                                          outer_headers);
5738                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5739         }
5740         if (group == 0)
5741                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5742         else
5743                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5744         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5745         /*
5746          * On outer header (which must contains L2), or inner header with L2,
5747          * set cvlan_tag mask bit to mark this packet as untagged.
5748          * This should be done even if item->spec is empty.
5749          */
5750         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5751                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5752         if (!ipv6_v)
5753                 return;
5754         if (!ipv6_m)
5755                 ipv6_m = &nic_mask;
5756         size = sizeof(ipv6_m->hdr.dst_addr);
5757         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5758                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5759         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5760                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5761         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5762         for (i = 0; i < size; ++i)
5763                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5764         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5765                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5766         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5767                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5768         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5769         for (i = 0; i < size; ++i)
5770                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5771         /* TOS. */
5772         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5773         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5774         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5775         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5776         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5777         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5778         /* Label. */
5779         if (inner) {
5780                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5781                          vtc_m);
5782                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5783                          vtc_v);
5784         } else {
5785                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5786                          vtc_m);
5787                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5788                          vtc_v);
5789         }
5790         /* Protocol. */
5791         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5792                  ipv6_m->hdr.proto);
5793         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5794                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5795         /* Hop limit. */
5796         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5797                  ipv6_m->hdr.hop_limits);
5798         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5799                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5800 }
5801
5802 /**
5803  * Add TCP item to matcher and to the value.
5804  *
5805  * @param[in, out] matcher
5806  *   Flow matcher.
5807  * @param[in, out] key
5808  *   Flow matcher value.
5809  * @param[in] item
5810  *   Flow pattern to translate.
5811  * @param[in] inner
5812  *   Item is inner pattern.
5813  */
5814 static void
5815 flow_dv_translate_item_tcp(void *matcher, void *key,
5816                            const struct rte_flow_item *item,
5817                            int inner)
5818 {
5819         const struct rte_flow_item_tcp *tcp_m = item->mask;
5820         const struct rte_flow_item_tcp *tcp_v = item->spec;
5821         void *headers_m;
5822         void *headers_v;
5823
5824         if (inner) {
5825                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5826                                          inner_headers);
5827                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5828         } else {
5829                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5830                                          outer_headers);
5831                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5832         }
5833         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5834         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5835         if (!tcp_v)
5836                 return;
5837         if (!tcp_m)
5838                 tcp_m = &rte_flow_item_tcp_mask;
5839         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5840                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5841         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5842                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5843         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5844                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5845         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5846                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5847         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5848                  tcp_m->hdr.tcp_flags);
5849         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5850                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5851 }
5852
5853 /**
5854  * Add UDP item to matcher and to the value.
5855  *
5856  * @param[in, out] matcher
5857  *   Flow matcher.
5858  * @param[in, out] key
5859  *   Flow matcher value.
5860  * @param[in] item
5861  *   Flow pattern to translate.
5862  * @param[in] inner
5863  *   Item is inner pattern.
5864  */
5865 static void
5866 flow_dv_translate_item_udp(void *matcher, void *key,
5867                            const struct rte_flow_item *item,
5868                            int inner)
5869 {
5870         const struct rte_flow_item_udp *udp_m = item->mask;
5871         const struct rte_flow_item_udp *udp_v = item->spec;
5872         void *headers_m;
5873         void *headers_v;
5874
5875         if (inner) {
5876                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5877                                          inner_headers);
5878                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5879         } else {
5880                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5881                                          outer_headers);
5882                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5883         }
5884         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5885         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5886         if (!udp_v)
5887                 return;
5888         if (!udp_m)
5889                 udp_m = &rte_flow_item_udp_mask;
5890         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5891                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5892         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5893                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5894         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5895                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5896         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5897                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5898 }
5899
5900 /**
5901  * Add GRE optional Key item to matcher and to the value.
5902  *
5903  * @param[in, out] matcher
5904  *   Flow matcher.
5905  * @param[in, out] key
5906  *   Flow matcher value.
5907  * @param[in] item
5908  *   Flow pattern to translate.
5909  * @param[in] inner
5910  *   Item is inner pattern.
5911  */
5912 static void
5913 flow_dv_translate_item_gre_key(void *matcher, void *key,
5914                                    const struct rte_flow_item *item)
5915 {
5916         const rte_be32_t *key_m = item->mask;
5917         const rte_be32_t *key_v = item->spec;
5918         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5919         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5920         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5921
5922         /* GRE K bit must be on and should already be validated */
5923         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5924         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5925         if (!key_v)
5926                 return;
5927         if (!key_m)
5928                 key_m = &gre_key_default_mask;
5929         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5930                  rte_be_to_cpu_32(*key_m) >> 8);
5931         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5932                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5933         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5934                  rte_be_to_cpu_32(*key_m) & 0xFF);
5935         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5936                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5937 }
5938
5939 /**
5940  * Add GRE item to matcher and to the value.
5941  *
5942  * @param[in, out] matcher
5943  *   Flow matcher.
5944  * @param[in, out] key
5945  *   Flow matcher value.
5946  * @param[in] item
5947  *   Flow pattern to translate.
5948  * @param[in] inner
5949  *   Item is inner pattern.
5950  */
5951 static void
5952 flow_dv_translate_item_gre(void *matcher, void *key,
5953                            const struct rte_flow_item *item,
5954                            int inner)
5955 {
5956         const struct rte_flow_item_gre *gre_m = item->mask;
5957         const struct rte_flow_item_gre *gre_v = item->spec;
5958         void *headers_m;
5959         void *headers_v;
5960         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5961         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5962         struct {
5963                 union {
5964                         __extension__
5965                         struct {
5966                                 uint16_t version:3;
5967                                 uint16_t rsvd0:9;
5968                                 uint16_t s_present:1;
5969                                 uint16_t k_present:1;
5970                                 uint16_t rsvd_bit1:1;
5971                                 uint16_t c_present:1;
5972                         };
5973                         uint16_t value;
5974                 };
5975         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5976
5977         if (inner) {
5978                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5979                                          inner_headers);
5980                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5981         } else {
5982                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5983                                          outer_headers);
5984                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5985         }
5986         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5987         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5988         if (!gre_v)
5989                 return;
5990         if (!gre_m)
5991                 gre_m = &rte_flow_item_gre_mask;
5992         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5993                  rte_be_to_cpu_16(gre_m->protocol));
5994         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5995                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5996         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5997         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5998         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5999                  gre_crks_rsvd0_ver_m.c_present);
6000         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6001                  gre_crks_rsvd0_ver_v.c_present &
6002                  gre_crks_rsvd0_ver_m.c_present);
6003         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6004                  gre_crks_rsvd0_ver_m.k_present);
6005         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6006                  gre_crks_rsvd0_ver_v.k_present &
6007                  gre_crks_rsvd0_ver_m.k_present);
6008         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6009                  gre_crks_rsvd0_ver_m.s_present);
6010         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6011                  gre_crks_rsvd0_ver_v.s_present &
6012                  gre_crks_rsvd0_ver_m.s_present);
6013 }
6014
6015 /**
6016  * Add NVGRE item to matcher and to the value.
6017  *
6018  * @param[in, out] matcher
6019  *   Flow matcher.
6020  * @param[in, out] key
6021  *   Flow matcher value.
6022  * @param[in] item
6023  *   Flow pattern to translate.
6024  * @param[in] inner
6025  *   Item is inner pattern.
6026  */
6027 static void
6028 flow_dv_translate_item_nvgre(void *matcher, void *key,
6029                              const struct rte_flow_item *item,
6030                              int inner)
6031 {
6032         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6033         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6034         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6035         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6036         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6037         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6038         char *gre_key_m;
6039         char *gre_key_v;
6040         int size;
6041         int i;
6042
6043         /* For NVGRE, GRE header fields must be set with defined values. */
6044         const struct rte_flow_item_gre gre_spec = {
6045                 .c_rsvd0_ver = RTE_BE16(0x2000),
6046                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6047         };
6048         const struct rte_flow_item_gre gre_mask = {
6049                 .c_rsvd0_ver = RTE_BE16(0xB000),
6050                 .protocol = RTE_BE16(UINT16_MAX),
6051         };
6052         const struct rte_flow_item gre_item = {
6053                 .spec = &gre_spec,
6054                 .mask = &gre_mask,
6055                 .last = NULL,
6056         };
6057         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6058         if (!nvgre_v)
6059                 return;
6060         if (!nvgre_m)
6061                 nvgre_m = &rte_flow_item_nvgre_mask;
6062         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6063         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6064         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6065         memcpy(gre_key_m, tni_flow_id_m, size);
6066         for (i = 0; i < size; ++i)
6067                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6068 }
6069
6070 /**
6071  * Add VXLAN item to matcher and to the value.
6072  *
6073  * @param[in, out] matcher
6074  *   Flow matcher.
6075  * @param[in, out] key
6076  *   Flow matcher value.
6077  * @param[in] item
6078  *   Flow pattern to translate.
6079  * @param[in] inner
6080  *   Item is inner pattern.
6081  */
6082 static void
6083 flow_dv_translate_item_vxlan(void *matcher, void *key,
6084                              const struct rte_flow_item *item,
6085                              int inner)
6086 {
6087         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6088         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6089         void *headers_m;
6090         void *headers_v;
6091         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6092         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6093         char *vni_m;
6094         char *vni_v;
6095         uint16_t dport;
6096         int size;
6097         int i;
6098
6099         if (inner) {
6100                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6101                                          inner_headers);
6102                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6103         } else {
6104                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6105                                          outer_headers);
6106                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6107         }
6108         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6109                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6110         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6111                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6112                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6113         }
6114         if (!vxlan_v)
6115                 return;
6116         if (!vxlan_m)
6117                 vxlan_m = &rte_flow_item_vxlan_mask;
6118         size = sizeof(vxlan_m->vni);
6119         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6120         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6121         memcpy(vni_m, vxlan_m->vni, size);
6122         for (i = 0; i < size; ++i)
6123                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6124 }
6125
6126 /**
6127  * Add VXLAN-GPE item to matcher and to the value.
6128  *
6129  * @param[in, out] matcher
6130  *   Flow matcher.
6131  * @param[in, out] key
6132  *   Flow matcher value.
6133  * @param[in] item
6134  *   Flow pattern to translate.
6135  * @param[in] inner
6136  *   Item is inner pattern.
6137  */
6138
6139 static void
6140 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6141                                  const struct rte_flow_item *item, int inner)
6142 {
6143         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6144         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6145         void *headers_m;
6146         void *headers_v;
6147         void *misc_m =
6148                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6149         void *misc_v =
6150                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6151         char *vni_m;
6152         char *vni_v;
6153         uint16_t dport;
6154         int size;
6155         int i;
6156         uint8_t flags_m = 0xff;
6157         uint8_t flags_v = 0xc;
6158
6159         if (inner) {
6160                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6161                                          inner_headers);
6162                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6163         } else {
6164                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6165                                          outer_headers);
6166                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6167         }
6168         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6169                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6170         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6171                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6172                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6173         }
6174         if (!vxlan_v)
6175                 return;
6176         if (!vxlan_m)
6177                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6178         size = sizeof(vxlan_m->vni);
6179         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6180         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6181         memcpy(vni_m, vxlan_m->vni, size);
6182         for (i = 0; i < size; ++i)
6183                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6184         if (vxlan_m->flags) {
6185                 flags_m = vxlan_m->flags;
6186                 flags_v = vxlan_v->flags;
6187         }
6188         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6189         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6190         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6191                  vxlan_m->protocol);
6192         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6193                  vxlan_v->protocol);
6194 }
6195
6196 /**
6197  * Add Geneve item to matcher and to the value.
6198  *
6199  * @param[in, out] matcher
6200  *   Flow matcher.
6201  * @param[in, out] key
6202  *   Flow matcher value.
6203  * @param[in] item
6204  *   Flow pattern to translate.
6205  * @param[in] inner
6206  *   Item is inner pattern.
6207  */
6208
6209 static void
6210 flow_dv_translate_item_geneve(void *matcher, void *key,
6211                               const struct rte_flow_item *item, int inner)
6212 {
6213         const struct rte_flow_item_geneve *geneve_m = item->mask;
6214         const struct rte_flow_item_geneve *geneve_v = item->spec;
6215         void *headers_m;
6216         void *headers_v;
6217         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6218         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6219         uint16_t dport;
6220         uint16_t gbhdr_m;
6221         uint16_t gbhdr_v;
6222         char *vni_m;
6223         char *vni_v;
6224         size_t size, i;
6225
6226         if (inner) {
6227                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6228                                          inner_headers);
6229                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6230         } else {
6231                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6232                                          outer_headers);
6233                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6234         }
6235         dport = MLX5_UDP_PORT_GENEVE;
6236         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6237                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6238                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6239         }
6240         if (!geneve_v)
6241                 return;
6242         if (!geneve_m)
6243                 geneve_m = &rte_flow_item_geneve_mask;
6244         size = sizeof(geneve_m->vni);
6245         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6246         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6247         memcpy(vni_m, geneve_m->vni, size);
6248         for (i = 0; i < size; ++i)
6249                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6250         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6251                  rte_be_to_cpu_16(geneve_m->protocol));
6252         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6253                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6254         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6255         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6256         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6257                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6258         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6259                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6260         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6261                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6262         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6263                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6264                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6265 }
6266
6267 /**
6268  * Add MPLS item to matcher and to the value.
6269  *
6270  * @param[in, out] matcher
6271  *   Flow matcher.
6272  * @param[in, out] key
6273  *   Flow matcher value.
6274  * @param[in] item
6275  *   Flow pattern to translate.
6276  * @param[in] prev_layer
6277  *   The protocol layer indicated in previous item.
6278  * @param[in] inner
6279  *   Item is inner pattern.
6280  */
6281 static void
6282 flow_dv_translate_item_mpls(void *matcher, void *key,
6283                             const struct rte_flow_item *item,
6284                             uint64_t prev_layer,
6285                             int inner)
6286 {
6287         const uint32_t *in_mpls_m = item->mask;
6288         const uint32_t *in_mpls_v = item->spec;
6289         uint32_t *out_mpls_m = 0;
6290         uint32_t *out_mpls_v = 0;
6291         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6292         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6293         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6294                                      misc_parameters_2);
6295         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6296         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6297         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6298
6299         switch (prev_layer) {
6300         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6301                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6302                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6303                          MLX5_UDP_PORT_MPLS);
6304                 break;
6305         case MLX5_FLOW_LAYER_GRE:
6306                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6307                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6308                          RTE_ETHER_TYPE_MPLS);
6309                 break;
6310         default:
6311                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6312                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6313                          IPPROTO_MPLS);
6314                 break;
6315         }
6316         if (!in_mpls_v)
6317                 return;
6318         if (!in_mpls_m)
6319                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6320         switch (prev_layer) {
6321         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6322                 out_mpls_m =
6323                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6324                                                  outer_first_mpls_over_udp);
6325                 out_mpls_v =
6326                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6327                                                  outer_first_mpls_over_udp);
6328                 break;
6329         case MLX5_FLOW_LAYER_GRE:
6330                 out_mpls_m =
6331                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6332                                                  outer_first_mpls_over_gre);
6333                 out_mpls_v =
6334                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6335                                                  outer_first_mpls_over_gre);
6336                 break;
6337         default:
6338                 /* Inner MPLS not over GRE is not supported. */
6339                 if (!inner) {
6340                         out_mpls_m =
6341                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6342                                                          misc2_m,
6343                                                          outer_first_mpls);
6344                         out_mpls_v =
6345                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6346                                                          misc2_v,
6347                                                          outer_first_mpls);
6348                 }
6349                 break;
6350         }
6351         if (out_mpls_m && out_mpls_v) {
6352                 *out_mpls_m = *in_mpls_m;
6353                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6354         }
6355 }
6356
6357 /**
6358  * Add metadata register item to matcher
6359  *
6360  * @param[in, out] matcher
6361  *   Flow matcher.
6362  * @param[in, out] key
6363  *   Flow matcher value.
6364  * @param[in] reg_type
6365  *   Type of device metadata register
6366  * @param[in] value
6367  *   Register value
6368  * @param[in] mask
6369  *   Register mask
6370  */
6371 static void
6372 flow_dv_match_meta_reg(void *matcher, void *key,
6373                        enum modify_reg reg_type,
6374                        uint32_t data, uint32_t mask)
6375 {
6376         void *misc2_m =
6377                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6378         void *misc2_v =
6379                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6380         uint32_t temp;
6381
6382         data &= mask;
6383         switch (reg_type) {
6384         case REG_A:
6385                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6386                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6387                 break;
6388         case REG_B:
6389                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6390                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6391                 break;
6392         case REG_C_0:
6393                 /*
6394                  * The metadata register C0 field might be divided into
6395                  * source vport index and META item value, we should set
6396                  * this field according to specified mask, not as whole one.
6397                  */
6398                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6399                 temp |= mask;
6400                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6401                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6402                 temp &= ~mask;
6403                 temp |= data;
6404                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6405                 break;
6406         case REG_C_1:
6407                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6408                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6409                 break;
6410         case REG_C_2:
6411                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6412                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6413                 break;
6414         case REG_C_3:
6415                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6416                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6417                 break;
6418         case REG_C_4:
6419                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6420                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6421                 break;
6422         case REG_C_5:
6423                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6424                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6425                 break;
6426         case REG_C_6:
6427                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6428                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6429                 break;
6430         case REG_C_7:
6431                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6432                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6433                 break;
6434         default:
6435                 MLX5_ASSERT(false);
6436                 break;
6437         }
6438 }
6439
6440 /**
6441  * Add MARK item to matcher
6442  *
6443  * @param[in] dev
6444  *   The device to configure through.
6445  * @param[in, out] matcher
6446  *   Flow matcher.
6447  * @param[in, out] key
6448  *   Flow matcher value.
6449  * @param[in] item
6450  *   Flow pattern to translate.
6451  */
6452 static void
6453 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6454                             void *matcher, void *key,
6455                             const struct rte_flow_item *item)
6456 {
6457         struct mlx5_priv *priv = dev->data->dev_private;
6458         const struct rte_flow_item_mark *mark;
6459         uint32_t value;
6460         uint32_t mask;
6461
6462         mark = item->mask ? (const void *)item->mask :
6463                             &rte_flow_item_mark_mask;
6464         mask = mark->id & priv->sh->dv_mark_mask;
6465         mark = (const void *)item->spec;
6466         MLX5_ASSERT(mark);
6467         value = mark->id & priv->sh->dv_mark_mask & mask;
6468         if (mask) {
6469                 enum modify_reg reg;
6470
6471                 /* Get the metadata register index for the mark. */
6472                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6473                 MLX5_ASSERT(reg > 0);
6474                 if (reg == REG_C_0) {
6475                         struct mlx5_priv *priv = dev->data->dev_private;
6476                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6477                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6478
6479                         mask &= msk_c0;
6480                         mask <<= shl_c0;
6481                         value <<= shl_c0;
6482                 }
6483                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6484         }
6485 }
6486
6487 /**
6488  * Add META item to matcher
6489  *
6490  * @param[in] dev
6491  *   The devich to configure through.
6492  * @param[in, out] matcher
6493  *   Flow matcher.
6494  * @param[in, out] key
6495  *   Flow matcher value.
6496  * @param[in] attr
6497  *   Attributes of flow that includes this item.
6498  * @param[in] item
6499  *   Flow pattern to translate.
6500  */
6501 static void
6502 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6503                             void *matcher, void *key,
6504                             const struct rte_flow_attr *attr,
6505                             const struct rte_flow_item *item)
6506 {
6507         const struct rte_flow_item_meta *meta_m;
6508         const struct rte_flow_item_meta *meta_v;
6509
6510         meta_m = (const void *)item->mask;
6511         if (!meta_m)
6512                 meta_m = &rte_flow_item_meta_mask;
6513         meta_v = (const void *)item->spec;
6514         if (meta_v) {
6515                 int reg;
6516                 uint32_t value = meta_v->data;
6517                 uint32_t mask = meta_m->data;
6518
6519                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6520                 if (reg < 0)
6521                         return;
6522                 /*
6523                  * In datapath code there is no endianness
6524                  * coversions for perfromance reasons, all
6525                  * pattern conversions are done in rte_flow.
6526                  */
6527                 value = rte_cpu_to_be_32(value);
6528                 mask = rte_cpu_to_be_32(mask);
6529                 if (reg == REG_C_0) {
6530                         struct mlx5_priv *priv = dev->data->dev_private;
6531                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6532                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6533 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6534                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6535
6536                         value >>= shr_c0;
6537                         mask >>= shr_c0;
6538 #endif
6539                         value <<= shl_c0;
6540                         mask <<= shl_c0;
6541                         MLX5_ASSERT(msk_c0);
6542                         MLX5_ASSERT(!(~msk_c0 & mask));
6543                 }
6544                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6545         }
6546 }
6547
6548 /**
6549  * Add vport metadata Reg C0 item to matcher
6550  *
6551  * @param[in, out] matcher
6552  *   Flow matcher.
6553  * @param[in, out] key
6554  *   Flow matcher value.
6555  * @param[in] reg
6556  *   Flow pattern to translate.
6557  */
6558 static void
6559 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6560                                   uint32_t value, uint32_t mask)
6561 {
6562         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6563 }
6564
6565 /**
6566  * Add tag item to matcher
6567  *
6568  * @param[in] dev
6569  *   The devich to configure through.
6570  * @param[in, out] matcher
6571  *   Flow matcher.
6572  * @param[in, out] key
6573  *   Flow matcher value.
6574  * @param[in] item
6575  *   Flow pattern to translate.
6576  */
6577 static void
6578 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6579                                 void *matcher, void *key,
6580                                 const struct rte_flow_item *item)
6581 {
6582         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6583         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6584         uint32_t mask, value;
6585
6586         MLX5_ASSERT(tag_v);
6587         value = tag_v->data;
6588         mask = tag_m ? tag_m->data : UINT32_MAX;
6589         if (tag_v->id == REG_C_0) {
6590                 struct mlx5_priv *priv = dev->data->dev_private;
6591                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6592                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6593
6594                 mask &= msk_c0;
6595                 mask <<= shl_c0;
6596                 value <<= shl_c0;
6597         }
6598         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6599 }
6600
6601 /**
6602  * Add TAG item to matcher
6603  *
6604  * @param[in] dev
6605  *   The devich to configure through.
6606  * @param[in, out] matcher
6607  *   Flow matcher.
6608  * @param[in, out] key
6609  *   Flow matcher value.
6610  * @param[in] item
6611  *   Flow pattern to translate.
6612  */
6613 static void
6614 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6615                            void *matcher, void *key,
6616                            const struct rte_flow_item *item)
6617 {
6618         const struct rte_flow_item_tag *tag_v = item->spec;
6619         const struct rte_flow_item_tag *tag_m = item->mask;
6620         enum modify_reg reg;
6621
6622         MLX5_ASSERT(tag_v);
6623         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6624         /* Get the metadata register index for the tag. */
6625         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6626         MLX5_ASSERT(reg > 0);
6627         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6628 }
6629
6630 /**
6631  * Add source vport match to the specified matcher.
6632  *
6633  * @param[in, out] matcher
6634  *   Flow matcher.
6635  * @param[in, out] key
6636  *   Flow matcher value.
6637  * @param[in] port
6638  *   Source vport value to match
6639  * @param[in] mask
6640  *   Mask
6641  */
6642 static void
6643 flow_dv_translate_item_source_vport(void *matcher, void *key,
6644                                     int16_t port, uint16_t mask)
6645 {
6646         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6647         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6648
6649         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6650         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6651 }
6652
6653 /**
6654  * Translate port-id item to eswitch match on  port-id.
6655  *
6656  * @param[in] dev
6657  *   The devich to configure through.
6658  * @param[in, out] matcher
6659  *   Flow matcher.
6660  * @param[in, out] key
6661  *   Flow matcher value.
6662  * @param[in] item
6663  *   Flow pattern to translate.
6664  *
6665  * @return
6666  *   0 on success, a negative errno value otherwise.
6667  */
6668 static int
6669 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6670                                void *key, const struct rte_flow_item *item)
6671 {
6672         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6673         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6674         struct mlx5_priv *priv;
6675         uint16_t mask, id;
6676
6677         mask = pid_m ? pid_m->id : 0xffff;
6678         id = pid_v ? pid_v->id : dev->data->port_id;
6679         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6680         if (!priv)
6681                 return -rte_errno;
6682         /* Translate to vport field or to metadata, depending on mode. */
6683         if (priv->vport_meta_mask)
6684                 flow_dv_translate_item_meta_vport(matcher, key,
6685                                                   priv->vport_meta_tag,
6686                                                   priv->vport_meta_mask);
6687         else
6688                 flow_dv_translate_item_source_vport(matcher, key,
6689                                                     priv->vport_id, mask);
6690         return 0;
6691 }
6692
6693 /**
6694  * Add ICMP6 item to matcher and to the value.
6695  *
6696  * @param[in, out] matcher
6697  *   Flow matcher.
6698  * @param[in, out] key
6699  *   Flow matcher value.
6700  * @param[in] item
6701  *   Flow pattern to translate.
6702  * @param[in] inner
6703  *   Item is inner pattern.
6704  */
6705 static void
6706 flow_dv_translate_item_icmp6(void *matcher, void *key,
6707                               const struct rte_flow_item *item,
6708                               int inner)
6709 {
6710         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6711         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6712         void *headers_m;
6713         void *headers_v;
6714         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6715                                      misc_parameters_3);
6716         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6717         if (inner) {
6718                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6719                                          inner_headers);
6720                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6721         } else {
6722                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6723                                          outer_headers);
6724                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6725         }
6726         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6727         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6728         if (!icmp6_v)
6729                 return;
6730         if (!icmp6_m)
6731                 icmp6_m = &rte_flow_item_icmp6_mask;
6732         /*
6733          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6734          * If only the protocol is specified, no need to match the frag.
6735          */
6736         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6737         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6738         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6739         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6740                  icmp6_v->type & icmp6_m->type);
6741         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6742         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6743                  icmp6_v->code & icmp6_m->code);
6744 }
6745
6746 /**
6747  * Add ICMP item to matcher and to the value.
6748  *
6749  * @param[in, out] matcher
6750  *   Flow matcher.
6751  * @param[in, out] key
6752  *   Flow matcher value.
6753  * @param[in] item
6754  *   Flow pattern to translate.
6755  * @param[in] inner
6756  *   Item is inner pattern.
6757  */
6758 static void
6759 flow_dv_translate_item_icmp(void *matcher, void *key,
6760                             const struct rte_flow_item *item,
6761                             int inner)
6762 {
6763         const struct rte_flow_item_icmp *icmp_m = item->mask;
6764         const struct rte_flow_item_icmp *icmp_v = item->spec;
6765         void *headers_m;
6766         void *headers_v;
6767         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6768                                      misc_parameters_3);
6769         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6770         if (inner) {
6771                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6772                                          inner_headers);
6773                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6774         } else {
6775                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6776                                          outer_headers);
6777                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6778         }
6779         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6780         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6781         if (!icmp_v)
6782                 return;
6783         if (!icmp_m)
6784                 icmp_m = &rte_flow_item_icmp_mask;
6785         /*
6786          * Force flow only to match the non-fragmented IPv4 ICMP packets.
6787          * If only the protocol is specified, no need to match the frag.
6788          */
6789         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6790         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6791         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6792                  icmp_m->hdr.icmp_type);
6793         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6794                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6795         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6796                  icmp_m->hdr.icmp_code);
6797         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6798                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6799 }
6800
6801 /**
6802  * Add GTP item to matcher and to the value.
6803  *
6804  * @param[in, out] matcher
6805  *   Flow matcher.
6806  * @param[in, out] key
6807  *   Flow matcher value.
6808  * @param[in] item
6809  *   Flow pattern to translate.
6810  * @param[in] inner
6811  *   Item is inner pattern.
6812  */
6813 static void
6814 flow_dv_translate_item_gtp(void *matcher, void *key,
6815                            const struct rte_flow_item *item, int inner)
6816 {
6817         const struct rte_flow_item_gtp *gtp_m = item->mask;
6818         const struct rte_flow_item_gtp *gtp_v = item->spec;
6819         void *headers_m;
6820         void *headers_v;
6821         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6822                                      misc_parameters_3);
6823         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6824         uint16_t dport = RTE_GTPU_UDP_PORT;
6825
6826         if (inner) {
6827                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6828                                          inner_headers);
6829                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6830         } else {
6831                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6832                                          outer_headers);
6833                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6834         }
6835         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6836                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6837                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6838         }
6839         if (!gtp_v)
6840                 return;
6841         if (!gtp_m)
6842                 gtp_m = &rte_flow_item_gtp_mask;
6843         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6844         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6845                  gtp_v->msg_type & gtp_m->msg_type);
6846         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6847                  rte_be_to_cpu_32(gtp_m->teid));
6848         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6849                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6850 }
6851
6852 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6853
6854 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6855         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6856                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6857
6858 /**
6859  * Calculate flow matcher enable bitmap.
6860  *
6861  * @param match_criteria
6862  *   Pointer to flow matcher criteria.
6863  *
6864  * @return
6865  *   Bitmap of enabled fields.
6866  */
6867 static uint8_t
6868 flow_dv_matcher_enable(uint32_t *match_criteria)
6869 {
6870         uint8_t match_criteria_enable;
6871
6872         match_criteria_enable =
6873                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6874                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6875         match_criteria_enable |=
6876                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6877                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6878         match_criteria_enable |=
6879                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6880                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6881         match_criteria_enable |=
6882                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6883                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6884         match_criteria_enable |=
6885                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6886                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6887         return match_criteria_enable;
6888 }
6889
6890
6891 /**
6892  * Get a flow table.
6893  *
6894  * @param[in, out] dev
6895  *   Pointer to rte_eth_dev structure.
6896  * @param[in] table_id
6897  *   Table id to use.
6898  * @param[in] egress
6899  *   Direction of the table.
6900  * @param[in] transfer
6901  *   E-Switch or NIC flow.
6902  * @param[out] error
6903  *   pointer to error structure.
6904  *
6905  * @return
6906  *   Returns tables resource based on the index, NULL in case of failed.
6907  */
6908 static struct mlx5_flow_tbl_resource *
6909 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6910                          uint32_t table_id, uint8_t egress,
6911                          uint8_t transfer,
6912                          struct rte_flow_error *error)
6913 {
6914         struct mlx5_priv *priv = dev->data->dev_private;
6915         struct mlx5_ibv_shared *sh = priv->sh;
6916         struct mlx5_flow_tbl_resource *tbl;
6917         union mlx5_flow_tbl_key table_key = {
6918                 {
6919                         .table_id = table_id,
6920                         .reserved = 0,
6921                         .domain = !!transfer,
6922                         .direction = !!egress,
6923                 }
6924         };
6925         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6926                                                          table_key.v64);
6927         struct mlx5_flow_tbl_data_entry *tbl_data;
6928         uint32_t idx = 0;
6929         int ret;
6930         void *domain;
6931
6932         if (pos) {
6933                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6934                                         entry);
6935                 tbl = &tbl_data->tbl;
6936                 rte_atomic32_inc(&tbl->refcnt);
6937                 return tbl;
6938         }
6939         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
6940         if (!tbl_data) {
6941                 rte_flow_error_set(error, ENOMEM,
6942                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6943                                    NULL,
6944                                    "cannot allocate flow table data entry");
6945                 return NULL;
6946         }
6947         tbl_data->idx = idx;
6948         tbl = &tbl_data->tbl;
6949         pos = &tbl_data->entry;
6950         if (transfer)
6951                 domain = sh->fdb_domain;
6952         else if (egress)
6953                 domain = sh->tx_domain;
6954         else
6955                 domain = sh->rx_domain;
6956         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6957         if (!tbl->obj) {
6958                 rte_flow_error_set(error, ENOMEM,
6959                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6960                                    NULL, "cannot create flow table object");
6961                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6962                 return NULL;
6963         }
6964         /*
6965          * No multi-threads now, but still better to initialize the reference
6966          * count before insert it into the hash list.
6967          */
6968         rte_atomic32_init(&tbl->refcnt);
6969         /* Jump action reference count is initialized here. */
6970         rte_atomic32_init(&tbl_data->jump.refcnt);
6971         pos->key = table_key.v64;
6972         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6973         if (ret < 0) {
6974                 rte_flow_error_set(error, -ret,
6975                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6976                                    "cannot insert flow table data entry");
6977                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6978                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6979         }
6980         rte_atomic32_inc(&tbl->refcnt);
6981         return tbl;
6982 }
6983
6984 /**
6985  * Release a flow table.
6986  *
6987  * @param[in] dev
6988  *   Pointer to rte_eth_dev structure.
6989  * @param[in] tbl
6990  *   Table resource to be released.
6991  *
6992  * @return
6993  *   Returns 0 if table was released, else return 1;
6994  */
6995 static int
6996 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6997                              struct mlx5_flow_tbl_resource *tbl)
6998 {
6999         struct mlx5_priv *priv = dev->data->dev_private;
7000         struct mlx5_ibv_shared *sh = priv->sh;
7001         struct mlx5_flow_tbl_data_entry *tbl_data =
7002                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7003
7004         if (!tbl)
7005                 return 0;
7006         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7007                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7008
7009                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7010                 tbl->obj = NULL;
7011                 /* remove the entry from the hash list and free memory. */
7012                 mlx5_hlist_remove(sh->flow_tbls, pos);
7013                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7014                                 tbl_data->idx);
7015                 return 0;
7016         }
7017         return 1;
7018 }
7019
7020 /**
7021  * Register the flow matcher.
7022  *
7023  * @param[in, out] dev
7024  *   Pointer to rte_eth_dev structure.
7025  * @param[in, out] matcher
7026  *   Pointer to flow matcher.
7027  * @param[in, out] key
7028  *   Pointer to flow table key.
7029  * @parm[in, out] dev_flow
7030  *   Pointer to the dev_flow.
7031  * @param[out] error
7032  *   pointer to error structure.
7033  *
7034  * @return
7035  *   0 on success otherwise -errno and errno is set.
7036  */
7037 static int
7038 flow_dv_matcher_register(struct rte_eth_dev *dev,
7039                          struct mlx5_flow_dv_matcher *matcher,
7040                          union mlx5_flow_tbl_key *key,
7041                          struct mlx5_flow *dev_flow,
7042                          struct rte_flow_error *error)
7043 {
7044         struct mlx5_priv *priv = dev->data->dev_private;
7045         struct mlx5_ibv_shared *sh = priv->sh;
7046         struct mlx5_flow_dv_matcher *cache_matcher;
7047         struct mlx5dv_flow_matcher_attr dv_attr = {
7048                 .type = IBV_FLOW_ATTR_NORMAL,
7049                 .match_mask = (void *)&matcher->mask,
7050         };
7051         struct mlx5_flow_tbl_resource *tbl;
7052         struct mlx5_flow_tbl_data_entry *tbl_data;
7053
7054         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7055                                        key->domain, error);
7056         if (!tbl)
7057                 return -rte_errno;      /* No need to refill the error info */
7058         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7059         /* Lookup from cache. */
7060         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7061                 if (matcher->crc == cache_matcher->crc &&
7062                     matcher->priority == cache_matcher->priority &&
7063                     !memcmp((const void *)matcher->mask.buf,
7064                             (const void *)cache_matcher->mask.buf,
7065                             cache_matcher->mask.size)) {
7066                         DRV_LOG(DEBUG,
7067                                 "%s group %u priority %hd use %s "
7068                                 "matcher %p: refcnt %d++",
7069                                 key->domain ? "FDB" : "NIC", key->table_id,
7070                                 cache_matcher->priority,
7071                                 key->direction ? "tx" : "rx",
7072                                 (void *)cache_matcher,
7073                                 rte_atomic32_read(&cache_matcher->refcnt));
7074                         rte_atomic32_inc(&cache_matcher->refcnt);
7075                         dev_flow->handle->dvh.matcher = cache_matcher;
7076                         /* old matcher should not make the table ref++. */
7077                         flow_dv_tbl_resource_release(dev, tbl);
7078                         return 0;
7079                 }
7080         }
7081         /* Register new matcher. */
7082         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7083         if (!cache_matcher) {
7084                 flow_dv_tbl_resource_release(dev, tbl);
7085                 return rte_flow_error_set(error, ENOMEM,
7086                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7087                                           "cannot allocate matcher memory");
7088         }
7089         *cache_matcher = *matcher;
7090         dv_attr.match_criteria_enable =
7091                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7092         dv_attr.priority = matcher->priority;
7093         if (key->direction)
7094                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7095         cache_matcher->matcher_object =
7096                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7097         if (!cache_matcher->matcher_object) {
7098                 rte_free(cache_matcher);
7099 #ifdef HAVE_MLX5DV_DR
7100                 flow_dv_tbl_resource_release(dev, tbl);
7101 #endif
7102                 return rte_flow_error_set(error, ENOMEM,
7103                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7104                                           NULL, "cannot create matcher");
7105         }
7106         /* Save the table information */
7107         cache_matcher->tbl = tbl;
7108         rte_atomic32_init(&cache_matcher->refcnt);
7109         /* only matcher ref++, table ref++ already done above in get API. */
7110         rte_atomic32_inc(&cache_matcher->refcnt);
7111         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7112         dev_flow->handle->dvh.matcher = cache_matcher;
7113         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7114                 key->domain ? "FDB" : "NIC", key->table_id,
7115                 cache_matcher->priority,
7116                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7117                 rte_atomic32_read(&cache_matcher->refcnt));
7118         return 0;
7119 }
7120
7121 /**
7122  * Find existing tag resource or create and register a new one.
7123  *
7124  * @param dev[in, out]
7125  *   Pointer to rte_eth_dev structure.
7126  * @param[in, out] tag_be24
7127  *   Tag value in big endian then R-shift 8.
7128  * @parm[in, out] dev_flow
7129  *   Pointer to the dev_flow.
7130  * @param[out] error
7131  *   pointer to error structure.
7132  *
7133  * @return
7134  *   0 on success otherwise -errno and errno is set.
7135  */
7136 static int
7137 flow_dv_tag_resource_register
7138                         (struct rte_eth_dev *dev,
7139                          uint32_t tag_be24,
7140                          struct mlx5_flow *dev_flow,
7141                          struct rte_flow_error *error)
7142 {
7143         struct mlx5_priv *priv = dev->data->dev_private;
7144         struct mlx5_ibv_shared *sh = priv->sh;
7145         struct mlx5_flow_dv_tag_resource *cache_resource;
7146         struct mlx5_hlist_entry *entry;
7147
7148         /* Lookup a matching resource from cache. */
7149         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7150         if (entry) {
7151                 cache_resource = container_of
7152                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7153                 rte_atomic32_inc(&cache_resource->refcnt);
7154                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7155                 dev_flow->dv.tag_resource = cache_resource;
7156                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7157                         (void *)cache_resource,
7158                         rte_atomic32_read(&cache_resource->refcnt));
7159                 return 0;
7160         }
7161         /* Register new resource. */
7162         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7163                                        &dev_flow->handle->dvh.rix_tag);
7164         if (!cache_resource)
7165                 return rte_flow_error_set(error, ENOMEM,
7166                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7167                                           "cannot allocate resource memory");
7168         cache_resource->entry.key = (uint64_t)tag_be24;
7169         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7170         if (!cache_resource->action) {
7171                 rte_free(cache_resource);
7172                 return rte_flow_error_set(error, ENOMEM,
7173                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7174                                           NULL, "cannot create action");
7175         }
7176         rte_atomic32_init(&cache_resource->refcnt);
7177         rte_atomic32_inc(&cache_resource->refcnt);
7178         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7179                 mlx5_glue->destroy_flow_action(cache_resource->action);
7180                 rte_free(cache_resource);
7181                 return rte_flow_error_set(error, EEXIST,
7182                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7183                                           NULL, "cannot insert tag");
7184         }
7185         dev_flow->dv.tag_resource = cache_resource;
7186         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7187                 (void *)cache_resource,
7188                 rte_atomic32_read(&cache_resource->refcnt));
7189         return 0;
7190 }
7191
7192 /**
7193  * Release the tag.
7194  *
7195  * @param dev
7196  *   Pointer to Ethernet device.
7197  * @param tag_idx
7198  *   Tag index.
7199  *
7200  * @return
7201  *   1 while a reference on it exists, 0 when freed.
7202  */
7203 static int
7204 flow_dv_tag_release(struct rte_eth_dev *dev,
7205                     uint32_t tag_idx)
7206 {
7207         struct mlx5_priv *priv = dev->data->dev_private;
7208         struct mlx5_ibv_shared *sh = priv->sh;
7209         struct mlx5_flow_dv_tag_resource *tag;
7210
7211         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7212         if (!tag)
7213                 return 0;
7214         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7215                 dev->data->port_id, (void *)tag,
7216                 rte_atomic32_read(&tag->refcnt));
7217         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7218                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7219                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7220                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7221                         dev->data->port_id, (void *)tag);
7222                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7223                 return 0;
7224         }
7225         return 1;
7226 }
7227
7228 /**
7229  * Translate port ID action to vport.
7230  *
7231  * @param[in] dev
7232  *   Pointer to rte_eth_dev structure.
7233  * @param[in] action
7234  *   Pointer to the port ID action.
7235  * @param[out] dst_port_id
7236  *   The target port ID.
7237  * @param[out] error
7238  *   Pointer to the error structure.
7239  *
7240  * @return
7241  *   0 on success, a negative errno value otherwise and rte_errno is set.
7242  */
7243 static int
7244 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7245                                  const struct rte_flow_action *action,
7246                                  uint32_t *dst_port_id,
7247                                  struct rte_flow_error *error)
7248 {
7249         uint32_t port;
7250         struct mlx5_priv *priv;
7251         const struct rte_flow_action_port_id *conf =
7252                         (const struct rte_flow_action_port_id *)action->conf;
7253
7254         port = conf->original ? dev->data->port_id : conf->id;
7255         priv = mlx5_port_to_eswitch_info(port, false);
7256         if (!priv)
7257                 return rte_flow_error_set(error, -rte_errno,
7258                                           RTE_FLOW_ERROR_TYPE_ACTION,
7259                                           NULL,
7260                                           "No eswitch info was found for port");
7261 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7262         /*
7263          * This parameter is transferred to
7264          * mlx5dv_dr_action_create_dest_ib_port().
7265          */
7266         *dst_port_id = priv->ibv_port;
7267 #else
7268         /*
7269          * Legacy mode, no LAG configurations is supported.
7270          * This parameter is transferred to
7271          * mlx5dv_dr_action_create_dest_vport().
7272          */
7273         *dst_port_id = priv->vport_id;
7274 #endif
7275         return 0;
7276 }
7277
7278 /**
7279  * Add Tx queue matcher
7280  *
7281  * @param[in] dev
7282  *   Pointer to the dev struct.
7283  * @param[in, out] matcher
7284  *   Flow matcher.
7285  * @param[in, out] key
7286  *   Flow matcher value.
7287  * @param[in] item
7288  *   Flow pattern to translate.
7289  * @param[in] inner
7290  *   Item is inner pattern.
7291  */
7292 static void
7293 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7294                                 void *matcher, void *key,
7295                                 const struct rte_flow_item *item)
7296 {
7297         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7298         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7299         void *misc_m =
7300                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7301         void *misc_v =
7302                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7303         struct mlx5_txq_ctrl *txq;
7304         uint32_t queue;
7305
7306
7307         queue_m = (const void *)item->mask;
7308         if (!queue_m)
7309                 return;
7310         queue_v = (const void *)item->spec;
7311         if (!queue_v)
7312                 return;
7313         txq = mlx5_txq_get(dev, queue_v->queue);
7314         if (!txq)
7315                 return;
7316         queue = txq->obj->sq->id;
7317         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7318         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7319                  queue & queue_m->queue);
7320         mlx5_txq_release(dev, queue_v->queue);
7321 }
7322
7323 /**
7324  * Set the hash fields according to the @p flow information.
7325  *
7326  * @param[in] dev_flow
7327  *   Pointer to the mlx5_flow.
7328  * @param[in] rss_desc
7329  *   Pointer to the mlx5_flow_rss_desc.
7330  */
7331 static void
7332 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7333                        struct mlx5_flow_rss_desc *rss_desc)
7334 {
7335         uint64_t items = dev_flow->handle->layers;
7336         int rss_inner = 0;
7337         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7338
7339         dev_flow->hash_fields = 0;
7340 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7341         if (rss_desc->level >= 2) {
7342                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7343                 rss_inner = 1;
7344         }
7345 #endif
7346         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7347             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7348                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7349                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7350                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7351                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7352                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7353                         else
7354                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7355                 }
7356         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7357                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7358                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7359                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7360                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7361                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7362                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7363                         else
7364                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7365                 }
7366         }
7367         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7368             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7369                 if (rss_types & ETH_RSS_UDP) {
7370                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7371                                 dev_flow->hash_fields |=
7372                                                 IBV_RX_HASH_SRC_PORT_UDP;
7373                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7374                                 dev_flow->hash_fields |=
7375                                                 IBV_RX_HASH_DST_PORT_UDP;
7376                         else
7377                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7378                 }
7379         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7380                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7381                 if (rss_types & ETH_RSS_TCP) {
7382                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7383                                 dev_flow->hash_fields |=
7384                                                 IBV_RX_HASH_SRC_PORT_TCP;
7385                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7386                                 dev_flow->hash_fields |=
7387                                                 IBV_RX_HASH_DST_PORT_TCP;
7388                         else
7389                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7390                 }
7391         }
7392 }
7393
7394 /**
7395  * Fill the flow with DV spec, lock free
7396  * (mutex should be acquired by caller).
7397  *
7398  * @param[in] dev
7399  *   Pointer to rte_eth_dev structure.
7400  * @param[in, out] dev_flow
7401  *   Pointer to the sub flow.
7402  * @param[in] attr
7403  *   Pointer to the flow attributes.
7404  * @param[in] items
7405  *   Pointer to the list of items.
7406  * @param[in] actions
7407  *   Pointer to the list of actions.
7408  * @param[out] error
7409  *   Pointer to the error structure.
7410  *
7411  * @return
7412  *   0 on success, a negative errno value otherwise and rte_errno is set.
7413  */
7414 static int
7415 __flow_dv_translate(struct rte_eth_dev *dev,
7416                     struct mlx5_flow *dev_flow,
7417                     const struct rte_flow_attr *attr,
7418                     const struct rte_flow_item items[],
7419                     const struct rte_flow_action actions[],
7420                     struct rte_flow_error *error)
7421 {
7422         struct mlx5_priv *priv = dev->data->dev_private;
7423         struct mlx5_dev_config *dev_conf = &priv->config;
7424         struct rte_flow *flow = dev_flow->flow;
7425         struct mlx5_flow_handle *handle = dev_flow->handle;
7426         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7427                                               priv->rss_desc)
7428                                               [!!priv->flow_nested_idx];
7429         uint64_t item_flags = 0;
7430         uint64_t last_item = 0;
7431         uint64_t action_flags = 0;
7432         uint64_t priority = attr->priority;
7433         struct mlx5_flow_dv_matcher matcher = {
7434                 .mask = {
7435                         .size = sizeof(matcher.mask.buf),
7436                 },
7437         };
7438         int actions_n = 0;
7439         bool actions_end = false;
7440         union {
7441                 struct mlx5_flow_dv_modify_hdr_resource res;
7442                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7443                             sizeof(struct mlx5_modification_cmd) *
7444                             (MLX5_MAX_MODIFY_NUM + 1)];
7445         } mhdr_dummy;
7446         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7447         union flow_dv_attr flow_attr = { .attr = 0 };
7448         uint32_t tag_be;
7449         union mlx5_flow_tbl_key tbl_key;
7450         uint32_t modify_action_position = UINT32_MAX;
7451         void *match_mask = matcher.mask.buf;
7452         void *match_value = dev_flow->dv.value.buf;
7453         uint8_t next_protocol = 0xff;
7454         struct rte_vlan_hdr vlan = { 0 };
7455         uint32_t table;
7456         int ret = 0;
7457
7458         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7459                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7460         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7461                                        !!priv->fdb_def_rule, &table, error);
7462         if (ret)
7463                 return ret;
7464         dev_flow->dv.group = table;
7465         if (attr->transfer)
7466                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7467         if (priority == MLX5_FLOW_PRIO_RSVD)
7468                 priority = dev_conf->flow_prio - 1;
7469         /* number of actions must be set to 0 in case of dirty stack. */
7470         mhdr_res->actions_num = 0;
7471         for (; !actions_end ; actions++) {
7472                 const struct rte_flow_action_queue *queue;
7473                 const struct rte_flow_action_rss *rss;
7474                 const struct rte_flow_action *action = actions;
7475                 const struct rte_flow_action_count *count = action->conf;
7476                 const uint8_t *rss_key;
7477                 const struct rte_flow_action_jump *jump_data;
7478                 const struct rte_flow_action_meter *mtr;
7479                 struct mlx5_flow_tbl_resource *tbl;
7480                 uint32_t port_id = 0;
7481                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7482                 int action_type = actions->type;
7483                 const struct rte_flow_action *found_action = NULL;
7484                 struct mlx5_flow_meter *fm = NULL;
7485
7486                 switch (action_type) {
7487                 case RTE_FLOW_ACTION_TYPE_VOID:
7488                         break;
7489                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7490                         if (flow_dv_translate_action_port_id(dev, action,
7491                                                              &port_id, error))
7492                                 return -rte_errno;
7493                         memset(&port_id_resource, 0, sizeof(port_id_resource));
7494                         port_id_resource.port_id = port_id;
7495                         if (flow_dv_port_id_action_resource_register
7496                             (dev, &port_id_resource, dev_flow, error))
7497                                 return -rte_errno;
7498                         MLX5_ASSERT(!handle->rix_port_id_action);
7499                         dev_flow->dv.actions[actions_n++] =
7500                                         dev_flow->dv.port_id_action->action;
7501                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7502                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7503                         break;
7504                 case RTE_FLOW_ACTION_TYPE_FLAG:
7505                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7506                         dev_flow->handle->mark = 1;
7507                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7508                                 struct rte_flow_action_mark mark = {
7509                                         .id = MLX5_FLOW_MARK_DEFAULT,
7510                                 };
7511
7512                                 if (flow_dv_convert_action_mark(dev, &mark,
7513                                                                 mhdr_res,
7514                                                                 error))
7515                                         return -rte_errno;
7516                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7517                                 break;
7518                         }
7519                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7520                         /*
7521                          * Only one FLAG or MARK is supported per device flow
7522                          * right now. So the pointer to the tag resource must be
7523                          * zero before the register process.
7524                          */
7525                         MLX5_ASSERT(!handle->dvh.rix_tag);
7526                         if (flow_dv_tag_resource_register(dev, tag_be,
7527                                                           dev_flow, error))
7528                                 return -rte_errno;
7529                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7530                         dev_flow->dv.actions[actions_n++] =
7531                                         dev_flow->dv.tag_resource->action;
7532                         break;
7533                 case RTE_FLOW_ACTION_TYPE_MARK:
7534                         action_flags |= MLX5_FLOW_ACTION_MARK;
7535                         dev_flow->handle->mark = 1;
7536                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7537                                 const struct rte_flow_action_mark *mark =
7538                                         (const struct rte_flow_action_mark *)
7539                                                 actions->conf;
7540
7541                                 if (flow_dv_convert_action_mark(dev, mark,
7542                                                                 mhdr_res,
7543                                                                 error))
7544                                         return -rte_errno;
7545                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7546                                 break;
7547                         }
7548                         /* Fall-through */
7549                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7550                         /* Legacy (non-extensive) MARK action. */
7551                         tag_be = mlx5_flow_mark_set
7552                               (((const struct rte_flow_action_mark *)
7553                                (actions->conf))->id);
7554                         MLX5_ASSERT(!handle->dvh.rix_tag);
7555                         if (flow_dv_tag_resource_register(dev, tag_be,
7556                                                           dev_flow, error))
7557                                 return -rte_errno;
7558                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7559                         dev_flow->dv.actions[actions_n++] =
7560                                         dev_flow->dv.tag_resource->action;
7561                         break;
7562                 case RTE_FLOW_ACTION_TYPE_SET_META:
7563                         if (flow_dv_convert_action_set_meta
7564                                 (dev, mhdr_res, attr,
7565                                  (const struct rte_flow_action_set_meta *)
7566                                   actions->conf, error))
7567                                 return -rte_errno;
7568                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7569                         break;
7570                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7571                         if (flow_dv_convert_action_set_tag
7572                                 (dev, mhdr_res,
7573                                  (const struct rte_flow_action_set_tag *)
7574                                   actions->conf, error))
7575                                 return -rte_errno;
7576                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7577                         break;
7578                 case RTE_FLOW_ACTION_TYPE_DROP:
7579                         action_flags |= MLX5_FLOW_ACTION_DROP;
7580                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7581                         break;
7582                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7583                         queue = actions->conf;
7584                         rss_desc->queue_num = 1;
7585                         rss_desc->queue[0] = queue->index;
7586                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7587                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7588                         break;
7589                 case RTE_FLOW_ACTION_TYPE_RSS:
7590                         rss = actions->conf;
7591                         memcpy(rss_desc->queue, rss->queue,
7592                                rss->queue_num * sizeof(uint16_t));
7593                         rss_desc->queue_num = rss->queue_num;
7594                         /* NULL RSS key indicates default RSS key. */
7595                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7596                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7597                         /*
7598                          * rss->level and rss.types should be set in advance
7599                          * when expanding items for RSS.
7600                          */
7601                         action_flags |= MLX5_FLOW_ACTION_RSS;
7602                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7603                         break;
7604                 case RTE_FLOW_ACTION_TYPE_COUNT:
7605                         if (!dev_conf->devx) {
7606                                 rte_errno = ENOTSUP;
7607                                 goto cnt_err;
7608                         }
7609                         flow->counter = flow_dv_counter_alloc(dev,
7610                                                         count->shared,
7611                                                         count->id,
7612                                                         dev_flow->dv.group);
7613                         if (!flow->counter)
7614                                 goto cnt_err;
7615                         dev_flow->dv.actions[actions_n++] =
7616                                   (flow_dv_counter_get_by_idx(dev,
7617                                   flow->counter, NULL))->action;
7618                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7619                         break;
7620 cnt_err:
7621                         if (rte_errno == ENOTSUP)
7622                                 return rte_flow_error_set
7623                                               (error, ENOTSUP,
7624                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7625                                                NULL,
7626                                                "count action not supported");
7627                         else
7628                                 return rte_flow_error_set
7629                                                 (error, rte_errno,
7630                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7631                                                  action,
7632                                                  "cannot create counter"
7633                                                   " object.");
7634                         break;
7635                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7636                         dev_flow->dv.actions[actions_n++] =
7637                                                 priv->sh->pop_vlan_action;
7638                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7639                         break;
7640                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7641                         if (!(action_flags &
7642                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7643                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7644                         vlan.eth_proto = rte_be_to_cpu_16
7645                              ((((const struct rte_flow_action_of_push_vlan *)
7646                                                    actions->conf)->ethertype));
7647                         found_action = mlx5_flow_find_action
7648                                         (actions + 1,
7649                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7650                         if (found_action)
7651                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7652                         found_action = mlx5_flow_find_action
7653                                         (actions + 1,
7654                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7655                         if (found_action)
7656                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7657                         if (flow_dv_create_action_push_vlan
7658                                             (dev, attr, &vlan, dev_flow, error))
7659                                 return -rte_errno;
7660                         dev_flow->dv.actions[actions_n++] =
7661                                         dev_flow->dv.push_vlan_res->action;
7662                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7663                         break;
7664                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7665                         /* of_vlan_push action handled this action */
7666                         MLX5_ASSERT(action_flags &
7667                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7668                         break;
7669                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7670                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7671                                 break;
7672                         flow_dev_get_vlan_info_from_items(items, &vlan);
7673                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7674                         /* If no VLAN push - this is a modify header action */
7675                         if (flow_dv_convert_action_modify_vlan_vid
7676                                                 (mhdr_res, actions, error))
7677                                 return -rte_errno;
7678                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7679                         break;
7680                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7681                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7682                         if (flow_dv_create_action_l2_encap(dev, actions,
7683                                                            dev_flow,
7684                                                            attr->transfer,
7685                                                            error))
7686                                 return -rte_errno;
7687                         dev_flow->dv.actions[actions_n++] =
7688                                         dev_flow->dv.encap_decap->verbs_action;
7689                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7690                         break;
7691                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7692                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7693                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7694                                                            attr->transfer,
7695                                                            error))
7696                                 return -rte_errno;
7697                         dev_flow->dv.actions[actions_n++] =
7698                                         dev_flow->dv.encap_decap->verbs_action;
7699                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7700                         break;
7701                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7702                         /* Handle encap with preceding decap. */
7703                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7704                                 if (flow_dv_create_action_raw_encap
7705                                         (dev, actions, dev_flow, attr, error))
7706                                         return -rte_errno;
7707                                 dev_flow->dv.actions[actions_n++] =
7708                                         dev_flow->dv.encap_decap->verbs_action;
7709                         } else {
7710                                 /* Handle encap without preceding decap. */
7711                                 if (flow_dv_create_action_l2_encap
7712                                     (dev, actions, dev_flow, attr->transfer,
7713                                      error))
7714                                         return -rte_errno;
7715                                 dev_flow->dv.actions[actions_n++] =
7716                                         dev_flow->dv.encap_decap->verbs_action;
7717                         }
7718                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7719                         break;
7720                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7721                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7722                                 ;
7723                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7724                                 if (flow_dv_create_action_l2_decap
7725                                     (dev, dev_flow, attr->transfer, error))
7726                                         return -rte_errno;
7727                                 dev_flow->dv.actions[actions_n++] =
7728                                         dev_flow->dv.encap_decap->verbs_action;
7729                         }
7730                         /* If decap is followed by encap, handle it at encap. */
7731                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7732                         break;
7733                 case RTE_FLOW_ACTION_TYPE_JUMP:
7734                         jump_data = action->conf;
7735                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7736                                                        jump_data->group,
7737                                                        !!priv->fdb_def_rule,
7738                                                        &table, error);
7739                         if (ret)
7740                                 return ret;
7741                         tbl = flow_dv_tbl_resource_get(dev, table,
7742                                                        attr->egress,
7743                                                        attr->transfer, error);
7744                         if (!tbl)
7745                                 return rte_flow_error_set
7746                                                 (error, errno,
7747                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7748                                                  NULL,
7749                                                  "cannot create jump action.");
7750                         if (flow_dv_jump_tbl_resource_register
7751                             (dev, tbl, dev_flow, error)) {
7752                                 flow_dv_tbl_resource_release(dev, tbl);
7753                                 return rte_flow_error_set
7754                                                 (error, errno,
7755                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7756                                                  NULL,
7757                                                  "cannot create jump action.");
7758                         }
7759                         dev_flow->dv.actions[actions_n++] =
7760                                         dev_flow->dv.jump->action;
7761                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7762                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
7763                         break;
7764                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7765                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7766                         if (flow_dv_convert_action_modify_mac
7767                                         (mhdr_res, actions, error))
7768                                 return -rte_errno;
7769                         action_flags |= actions->type ==
7770                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7771                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7772                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7773                         break;
7774                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7775                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7776                         if (flow_dv_convert_action_modify_ipv4
7777                                         (mhdr_res, actions, error))
7778                                 return -rte_errno;
7779                         action_flags |= actions->type ==
7780                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7781                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7782                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7783                         break;
7784                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7785                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7786                         if (flow_dv_convert_action_modify_ipv6
7787                                         (mhdr_res, actions, error))
7788                                 return -rte_errno;
7789                         action_flags |= actions->type ==
7790                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7791                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
7792                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
7793                         break;
7794                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7795                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7796                         if (flow_dv_convert_action_modify_tp
7797                                         (mhdr_res, actions, items,
7798                                          &flow_attr, dev_flow, !!(action_flags &
7799                                          MLX5_FLOW_ACTION_DECAP), error))
7800                                 return -rte_errno;
7801                         action_flags |= actions->type ==
7802                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7803                                         MLX5_FLOW_ACTION_SET_TP_SRC :
7804                                         MLX5_FLOW_ACTION_SET_TP_DST;
7805                         break;
7806                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7807                         if (flow_dv_convert_action_modify_dec_ttl
7808                                         (mhdr_res, items, &flow_attr, dev_flow,
7809                                          !!(action_flags &
7810                                          MLX5_FLOW_ACTION_DECAP), error))
7811                                 return -rte_errno;
7812                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7813                         break;
7814                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7815                         if (flow_dv_convert_action_modify_ttl
7816                                         (mhdr_res, actions, items, &flow_attr,
7817                                          dev_flow, !!(action_flags &
7818                                          MLX5_FLOW_ACTION_DECAP), error))
7819                                 return -rte_errno;
7820                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7821                         break;
7822                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7823                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7824                         if (flow_dv_convert_action_modify_tcp_seq
7825                                         (mhdr_res, actions, error))
7826                                 return -rte_errno;
7827                         action_flags |= actions->type ==
7828                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7829                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
7830                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7831                         break;
7832
7833                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7834                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7835                         if (flow_dv_convert_action_modify_tcp_ack
7836                                         (mhdr_res, actions, error))
7837                                 return -rte_errno;
7838                         action_flags |= actions->type ==
7839                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7840                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
7841                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
7842                         break;
7843                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7844                         if (flow_dv_convert_action_set_reg
7845                                         (mhdr_res, actions, error))
7846                                 return -rte_errno;
7847                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7848                         break;
7849                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7850                         if (flow_dv_convert_action_copy_mreg
7851                                         (dev, mhdr_res, actions, error))
7852                                 return -rte_errno;
7853                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7854                         break;
7855                 case RTE_FLOW_ACTION_TYPE_METER:
7856                         mtr = actions->conf;
7857                         if (!flow->meter) {
7858                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
7859                                                             attr, error);
7860                                 if (!fm)
7861                                         return rte_flow_error_set(error,
7862                                                 rte_errno,
7863                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7864                                                 NULL,
7865                                                 "meter not found "
7866                                                 "or invalid parameters");
7867                                 flow->meter = fm->idx;
7868                         }
7869                         /* Set the meter action. */
7870                         if (!fm) {
7871                                 fm = mlx5_ipool_get(priv->sh->ipool
7872                                                 [MLX5_IPOOL_MTR], flow->meter);
7873                                 if (!fm)
7874                                         return rte_flow_error_set(error,
7875                                                 rte_errno,
7876                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7877                                                 NULL,
7878                                                 "meter not found "
7879                                                 "or invalid parameters");
7880                         }
7881                         dev_flow->dv.actions[actions_n++] =
7882                                 fm->mfts->meter_action;
7883                         action_flags |= MLX5_FLOW_ACTION_METER;
7884                         break;
7885                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7886                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7887                                                               actions, error))
7888                                 return -rte_errno;
7889                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7890                         break;
7891                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7892                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7893                                                               actions, error))
7894                                 return -rte_errno;
7895                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7896                         break;
7897                 case RTE_FLOW_ACTION_TYPE_END:
7898                         actions_end = true;
7899                         if (mhdr_res->actions_num) {
7900                                 /* create modify action if needed. */
7901                                 if (flow_dv_modify_hdr_resource_register
7902                                         (dev, mhdr_res, dev_flow, error))
7903                                         return -rte_errno;
7904                                 dev_flow->dv.actions[modify_action_position] =
7905                                         handle->dvh.modify_hdr->verbs_action;
7906                         }
7907                         break;
7908                 default:
7909                         break;
7910                 }
7911                 if (mhdr_res->actions_num &&
7912                     modify_action_position == UINT32_MAX)
7913                         modify_action_position = actions_n++;
7914         }
7915         dev_flow->dv.actions_n = actions_n;
7916         dev_flow->act_flags = action_flags;
7917         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7918                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7919                 int item_type = items->type;
7920
7921                 switch (item_type) {
7922                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7923                         flow_dv_translate_item_port_id(dev, match_mask,
7924                                                        match_value, items);
7925                         last_item = MLX5_FLOW_ITEM_PORT_ID;
7926                         break;
7927                 case RTE_FLOW_ITEM_TYPE_ETH:
7928                         flow_dv_translate_item_eth(match_mask, match_value,
7929                                                    items, tunnel);
7930                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7931                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7932                                              MLX5_FLOW_LAYER_OUTER_L2;
7933                         break;
7934                 case RTE_FLOW_ITEM_TYPE_VLAN:
7935                         flow_dv_translate_item_vlan(dev_flow,
7936                                                     match_mask, match_value,
7937                                                     items, tunnel);
7938                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7939                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7940                                               MLX5_FLOW_LAYER_INNER_VLAN) :
7941                                              (MLX5_FLOW_LAYER_OUTER_L2 |
7942                                               MLX5_FLOW_LAYER_OUTER_VLAN);
7943                         break;
7944                 case RTE_FLOW_ITEM_TYPE_IPV4:
7945                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7946                                                   &item_flags, &tunnel);
7947                         flow_dv_translate_item_ipv4(match_mask, match_value,
7948                                                     items, item_flags, tunnel,
7949                                                     dev_flow->dv.group);
7950                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7951                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7952                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7953                         if (items->mask != NULL &&
7954                             ((const struct rte_flow_item_ipv4 *)
7955                              items->mask)->hdr.next_proto_id) {
7956                                 next_protocol =
7957                                         ((const struct rte_flow_item_ipv4 *)
7958                                          (items->spec))->hdr.next_proto_id;
7959                                 next_protocol &=
7960                                         ((const struct rte_flow_item_ipv4 *)
7961                                          (items->mask))->hdr.next_proto_id;
7962                         } else {
7963                                 /* Reset for inner layer. */
7964                                 next_protocol = 0xff;
7965                         }
7966                         break;
7967                 case RTE_FLOW_ITEM_TYPE_IPV6:
7968                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7969                                                   &item_flags, &tunnel);
7970                         flow_dv_translate_item_ipv6(match_mask, match_value,
7971                                                     items, item_flags, tunnel,
7972                                                     dev_flow->dv.group);
7973                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7974                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7975                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7976                         if (items->mask != NULL &&
7977                             ((const struct rte_flow_item_ipv6 *)
7978                              items->mask)->hdr.proto) {
7979                                 next_protocol =
7980                                         ((const struct rte_flow_item_ipv6 *)
7981                                          items->spec)->hdr.proto;
7982                                 next_protocol &=
7983                                         ((const struct rte_flow_item_ipv6 *)
7984                                          items->mask)->hdr.proto;
7985                         } else {
7986                                 /* Reset for inner layer. */
7987                                 next_protocol = 0xff;
7988                         }
7989                         break;
7990                 case RTE_FLOW_ITEM_TYPE_TCP:
7991                         flow_dv_translate_item_tcp(match_mask, match_value,
7992                                                    items, tunnel);
7993                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7994                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7995                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
7996                         break;
7997                 case RTE_FLOW_ITEM_TYPE_UDP:
7998                         flow_dv_translate_item_udp(match_mask, match_value,
7999                                                    items, tunnel);
8000                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8001                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8002                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8003                         break;
8004                 case RTE_FLOW_ITEM_TYPE_GRE:
8005                         flow_dv_translate_item_gre(match_mask, match_value,
8006                                                    items, tunnel);
8007                         matcher.priority = rss_desc->level >= 2 ?
8008                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8009                         last_item = MLX5_FLOW_LAYER_GRE;
8010                         break;
8011                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8012                         flow_dv_translate_item_gre_key(match_mask,
8013                                                        match_value, items);
8014                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8015                         break;
8016                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8017                         flow_dv_translate_item_nvgre(match_mask, match_value,
8018                                                      items, tunnel);
8019                         matcher.priority = rss_desc->level >= 2 ?
8020                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8021                         last_item = MLX5_FLOW_LAYER_GRE;
8022                         break;
8023                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8024                         flow_dv_translate_item_vxlan(match_mask, match_value,
8025                                                      items, tunnel);
8026                         matcher.priority = rss_desc->level >= 2 ?
8027                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8028                         last_item = MLX5_FLOW_LAYER_VXLAN;
8029                         break;
8030                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8031                         flow_dv_translate_item_vxlan_gpe(match_mask,
8032                                                          match_value, items,
8033                                                          tunnel);
8034                         matcher.priority = rss_desc->level >= 2 ?
8035                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8036                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8037                         break;
8038                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8039                         flow_dv_translate_item_geneve(match_mask, match_value,
8040                                                       items, tunnel);
8041                         matcher.priority = rss_desc->level >= 2 ?
8042                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8043                         last_item = MLX5_FLOW_LAYER_GENEVE;
8044                         break;
8045                 case RTE_FLOW_ITEM_TYPE_MPLS:
8046                         flow_dv_translate_item_mpls(match_mask, match_value,
8047                                                     items, last_item, tunnel);
8048                         matcher.priority = rss_desc->level >= 2 ?
8049                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8050                         last_item = MLX5_FLOW_LAYER_MPLS;
8051                         break;
8052                 case RTE_FLOW_ITEM_TYPE_MARK:
8053                         flow_dv_translate_item_mark(dev, match_mask,
8054                                                     match_value, items);
8055                         last_item = MLX5_FLOW_ITEM_MARK;
8056                         break;
8057                 case RTE_FLOW_ITEM_TYPE_META:
8058                         flow_dv_translate_item_meta(dev, match_mask,
8059                                                     match_value, attr, items);
8060                         last_item = MLX5_FLOW_ITEM_METADATA;
8061                         break;
8062                 case RTE_FLOW_ITEM_TYPE_ICMP:
8063                         flow_dv_translate_item_icmp(match_mask, match_value,
8064                                                     items, tunnel);
8065                         last_item = MLX5_FLOW_LAYER_ICMP;
8066                         break;
8067                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8068                         flow_dv_translate_item_icmp6(match_mask, match_value,
8069                                                       items, tunnel);
8070                         last_item = MLX5_FLOW_LAYER_ICMP6;
8071                         break;
8072                 case RTE_FLOW_ITEM_TYPE_TAG:
8073                         flow_dv_translate_item_tag(dev, match_mask,
8074                                                    match_value, items);
8075                         last_item = MLX5_FLOW_ITEM_TAG;
8076                         break;
8077                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8078                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8079                                                         match_value, items);
8080                         last_item = MLX5_FLOW_ITEM_TAG;
8081                         break;
8082                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8083                         flow_dv_translate_item_tx_queue(dev, match_mask,
8084                                                         match_value,
8085                                                         items);
8086                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8087                         break;
8088                 case RTE_FLOW_ITEM_TYPE_GTP:
8089                         flow_dv_translate_item_gtp(match_mask, match_value,
8090                                                    items, tunnel);
8091                         matcher.priority = rss_desc->level >= 2 ?
8092                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8093                         last_item = MLX5_FLOW_LAYER_GTP;
8094                         break;
8095                 default:
8096                         break;
8097                 }
8098                 item_flags |= last_item;
8099         }
8100         /*
8101          * When E-Switch mode is enabled, we have two cases where we need to
8102          * set the source port manually.
8103          * The first one, is in case of Nic steering rule, and the second is
8104          * E-Switch rule where no port_id item was found. In both cases
8105          * the source port is set according the current port in use.
8106          */
8107         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8108             (priv->representor || priv->master)) {
8109                 if (flow_dv_translate_item_port_id(dev, match_mask,
8110                                                    match_value, NULL))
8111                         return -rte_errno;
8112         }
8113 #ifdef RTE_LIBRTE_MLX5_DEBUG
8114         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8115                                               dev_flow->dv.value.buf));
8116 #endif
8117         /*
8118          * Layers may be already initialized from prefix flow if this dev_flow
8119          * is the suffix flow.
8120          */
8121         handle->layers |= item_flags;
8122         if (action_flags & MLX5_FLOW_ACTION_RSS)
8123                 flow_dv_hashfields_set(dev_flow, rss_desc);
8124         /* Register matcher. */
8125         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8126                                     matcher.mask.size);
8127         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8128                                                      matcher.priority);
8129         /* reserved field no needs to be set to 0 here. */
8130         tbl_key.domain = attr->transfer;
8131         tbl_key.direction = attr->egress;
8132         tbl_key.table_id = dev_flow->dv.group;
8133         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8134                 return -rte_errno;
8135         return 0;
8136 }
8137
8138 /**
8139  * Apply the flow to the NIC, lock free,
8140  * (mutex should be acquired by caller).
8141  *
8142  * @param[in] dev
8143  *   Pointer to the Ethernet device structure.
8144  * @param[in, out] flow
8145  *   Pointer to flow structure.
8146  * @param[out] error
8147  *   Pointer to error structure.
8148  *
8149  * @return
8150  *   0 on success, a negative errno value otherwise and rte_errno is set.
8151  */
8152 static int
8153 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8154                 struct rte_flow_error *error)
8155 {
8156         struct mlx5_flow_dv_workspace *dv;
8157         struct mlx5_flow_handle *dh;
8158         struct mlx5_flow_handle_dv *dv_h;
8159         struct mlx5_flow *dev_flow;
8160         struct mlx5_priv *priv = dev->data->dev_private;
8161         uint32_t handle_idx;
8162         int n;
8163         int err;
8164         int idx;
8165
8166         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8167                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8168                 dv = &dev_flow->dv;
8169                 dh = dev_flow->handle;
8170                 dv_h = &dh->dvh;
8171                 n = dv->actions_n;
8172                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8173                         if (dv->transfer) {
8174                                 dv->actions[n++] = priv->sh->esw_drop_action;
8175                         } else {
8176                                 struct mlx5_hrxq *drop_hrxq;
8177                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8178                                 if (!drop_hrxq) {
8179                                         rte_flow_error_set
8180                                                 (error, errno,
8181                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8182                                                  NULL,
8183                                                  "cannot get drop hash queue");
8184                                         goto error;
8185                                 }
8186                                 /*
8187                                  * Drop queues will be released by the specify
8188                                  * mlx5_hrxq_drop_release() function. Assign
8189                                  * the special index to hrxq to mark the queue
8190                                  * has been allocated.
8191                                  */
8192                                 dh->rix_hrxq = UINT32_MAX;
8193                                 dv->actions[n++] = drop_hrxq->action;
8194                         }
8195                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8196                         struct mlx5_hrxq *hrxq;
8197                         uint32_t hrxq_idx;
8198                         struct mlx5_flow_rss_desc *rss_desc =
8199                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8200                                 [!!priv->flow_nested_idx];
8201
8202                         MLX5_ASSERT(rss_desc->queue_num);
8203                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8204                                                  MLX5_RSS_HASH_KEY_LEN,
8205                                                  dev_flow->hash_fields,
8206                                                  rss_desc->queue,
8207                                                  rss_desc->queue_num);
8208                         if (!hrxq_idx) {
8209                                 hrxq_idx = mlx5_hrxq_new
8210                                                 (dev, rss_desc->key,
8211                                                 MLX5_RSS_HASH_KEY_LEN,
8212                                                 dev_flow->hash_fields,
8213                                                 rss_desc->queue,
8214                                                 rss_desc->queue_num,
8215                                                 !!(dh->layers &
8216                                                 MLX5_FLOW_LAYER_TUNNEL));
8217                         }
8218                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8219                                               hrxq_idx);
8220                         if (!hrxq) {
8221                                 rte_flow_error_set
8222                                         (error, rte_errno,
8223                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8224                                          "cannot get hash queue");
8225                                 goto error;
8226                         }
8227                         dh->rix_hrxq = hrxq_idx;
8228                         dv->actions[n++] = hrxq->action;
8229                 }
8230                 dh->ib_flow =
8231                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8232                                                   (void *)&dv->value, n,
8233                                                   dv->actions);
8234                 if (!dh->ib_flow) {
8235                         rte_flow_error_set(error, errno,
8236                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8237                                            NULL,
8238                                            "hardware refuses to create flow");
8239                         goto error;
8240                 }
8241                 if (priv->vmwa_context &&
8242                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8243                         /*
8244                          * The rule contains the VLAN pattern.
8245                          * For VF we are going to create VLAN
8246                          * interface to make hypervisor set correct
8247                          * e-Switch vport context.
8248                          */
8249                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8250                 }
8251         }
8252         return 0;
8253 error:
8254         err = rte_errno; /* Save rte_errno before cleanup. */
8255         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8256                        handle_idx, dh, next) {
8257                 /* hrxq is union, don't clear it if the flag is not set. */
8258                 if (dh->rix_hrxq) {
8259                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8260                                 mlx5_hrxq_drop_release(dev);
8261                                 dh->rix_hrxq = 0;
8262                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8263                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8264                                 dh->rix_hrxq = 0;
8265                         }
8266                 }
8267                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8268                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8269         }
8270         rte_errno = err; /* Restore rte_errno. */
8271         return -rte_errno;
8272 }
8273
8274 /**
8275  * Release the flow matcher.
8276  *
8277  * @param dev
8278  *   Pointer to Ethernet device.
8279  * @param handle
8280  *   Pointer to mlx5_flow_handle.
8281  *
8282  * @return
8283  *   1 while a reference on it exists, 0 when freed.
8284  */
8285 static int
8286 flow_dv_matcher_release(struct rte_eth_dev *dev,
8287                         struct mlx5_flow_handle *handle)
8288 {
8289         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8290
8291         MLX5_ASSERT(matcher->matcher_object);
8292         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8293                 dev->data->port_id, (void *)matcher,
8294                 rte_atomic32_read(&matcher->refcnt));
8295         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8296                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8297                            (matcher->matcher_object));
8298                 LIST_REMOVE(matcher, next);
8299                 /* table ref-- in release interface. */
8300                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8301                 rte_free(matcher);
8302                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8303                         dev->data->port_id, (void *)matcher);
8304                 return 0;
8305         }
8306         return 1;
8307 }
8308
8309 /**
8310  * Release an encap/decap resource.
8311  *
8312  * @param dev
8313  *   Pointer to Ethernet device.
8314  * @param handle
8315  *   Pointer to mlx5_flow_handle.
8316  *
8317  * @return
8318  *   1 while a reference on it exists, 0 when freed.
8319  */
8320 static int
8321 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8322                                      struct mlx5_flow_handle *handle)
8323 {
8324         struct mlx5_priv *priv = dev->data->dev_private;
8325         uint32_t idx = handle->dvh.rix_encap_decap;
8326         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8327
8328         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8329                          idx);
8330         if (!cache_resource)
8331                 return 0;
8332         MLX5_ASSERT(cache_resource->verbs_action);
8333         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8334                 (void *)cache_resource,
8335                 rte_atomic32_read(&cache_resource->refcnt));
8336         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8337                 claim_zero(mlx5_glue->destroy_flow_action
8338                                 (cache_resource->verbs_action));
8339                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8340                              &priv->sh->encaps_decaps, idx,
8341                              cache_resource, next);
8342                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8343                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8344                         (void *)cache_resource);
8345                 return 0;
8346         }
8347         return 1;
8348 }
8349
8350 /**
8351  * Release an jump to table action resource.
8352  *
8353  * @param dev
8354  *   Pointer to Ethernet device.
8355  * @param handle
8356  *   Pointer to mlx5_flow_handle.
8357  *
8358  * @return
8359  *   1 while a reference on it exists, 0 when freed.
8360  */
8361 static int
8362 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8363                                   struct mlx5_flow_handle *handle)
8364 {
8365         struct mlx5_priv *priv = dev->data->dev_private;
8366         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8367         struct mlx5_flow_tbl_data_entry *tbl_data;
8368
8369         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8370                              handle->rix_jump);
8371         if (!tbl_data)
8372                 return 0;
8373         cache_resource = &tbl_data->jump;
8374         MLX5_ASSERT(cache_resource->action);
8375         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8376                 (void *)cache_resource,
8377                 rte_atomic32_read(&cache_resource->refcnt));
8378         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8379                 claim_zero(mlx5_glue->destroy_flow_action
8380                                 (cache_resource->action));
8381                 /* jump action memory free is inside the table release. */
8382                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8383                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8384                         (void *)cache_resource);
8385                 return 0;
8386         }
8387         return 1;
8388 }
8389
8390 /**
8391  * Release a modify-header resource.
8392  *
8393  * @param handle
8394  *   Pointer to mlx5_flow_handle.
8395  *
8396  * @return
8397  *   1 while a reference on it exists, 0 when freed.
8398  */
8399 static int
8400 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8401 {
8402         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8403                                                         handle->dvh.modify_hdr;
8404
8405         MLX5_ASSERT(cache_resource->verbs_action);
8406         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8407                 (void *)cache_resource,
8408                 rte_atomic32_read(&cache_resource->refcnt));
8409         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8410                 claim_zero(mlx5_glue->destroy_flow_action
8411                                 (cache_resource->verbs_action));
8412                 LIST_REMOVE(cache_resource, next);
8413                 rte_free(cache_resource);
8414                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8415                         (void *)cache_resource);
8416                 return 0;
8417         }
8418         return 1;
8419 }
8420
8421 /**
8422  * Release port ID action resource.
8423  *
8424  * @param dev
8425  *   Pointer to Ethernet device.
8426  * @param handle
8427  *   Pointer to mlx5_flow_handle.
8428  *
8429  * @return
8430  *   1 while a reference on it exists, 0 when freed.
8431  */
8432 static int
8433 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8434                                         struct mlx5_flow_handle *handle)
8435 {
8436         struct mlx5_priv *priv = dev->data->dev_private;
8437         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8438         uint32_t idx = handle->rix_port_id_action;
8439
8440         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8441                                         idx);
8442         if (!cache_resource)
8443                 return 0;
8444         MLX5_ASSERT(cache_resource->action);
8445         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8446                 (void *)cache_resource,
8447                 rte_atomic32_read(&cache_resource->refcnt));
8448         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8449                 claim_zero(mlx5_glue->destroy_flow_action
8450                                 (cache_resource->action));
8451                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8452                              &priv->sh->port_id_action_list, idx,
8453                              cache_resource, next);
8454                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8455                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8456                         (void *)cache_resource);
8457                 return 0;
8458         }
8459         return 1;
8460 }
8461
8462 /**
8463  * Release push vlan action resource.
8464  *
8465  * @param dev
8466  *   Pointer to Ethernet device.
8467  * @param handle
8468  *   Pointer to mlx5_flow_handle.
8469  *
8470  * @return
8471  *   1 while a reference on it exists, 0 when freed.
8472  */
8473 static int
8474 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8475                                           struct mlx5_flow_handle *handle)
8476 {
8477         struct mlx5_priv *priv = dev->data->dev_private;
8478         uint32_t idx = handle->dvh.rix_push_vlan;
8479         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8480
8481         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8482                                         idx);
8483         if (!cache_resource)
8484                 return 0;
8485         MLX5_ASSERT(cache_resource->action);
8486         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8487                 (void *)cache_resource,
8488                 rte_atomic32_read(&cache_resource->refcnt));
8489         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8490                 claim_zero(mlx5_glue->destroy_flow_action
8491                                 (cache_resource->action));
8492                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8493                              &priv->sh->push_vlan_action_list, idx,
8494                              cache_resource, next);
8495                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8496                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8497                         (void *)cache_resource);
8498                 return 0;
8499         }
8500         return 1;
8501 }
8502
8503 /**
8504  * Release the fate resource.
8505  *
8506  * @param dev
8507  *   Pointer to Ethernet device.
8508  * @param handle
8509  *   Pointer to mlx5_flow_handle.
8510  */
8511 static void
8512 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8513                                struct mlx5_flow_handle *handle)
8514 {
8515         if (!handle->rix_fate)
8516                 return;
8517         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8518                 mlx5_hrxq_drop_release(dev);
8519         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8520                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8521         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8522                 flow_dv_jump_tbl_resource_release(dev, handle);
8523         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8524                 flow_dv_port_id_action_resource_release(dev, handle);
8525         else
8526                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8527         handle->rix_fate = 0;
8528 }
8529
8530 /**
8531  * Remove the flow from the NIC but keeps it in memory.
8532  * Lock free, (mutex should be acquired by caller).
8533  *
8534  * @param[in] dev
8535  *   Pointer to Ethernet device.
8536  * @param[in, out] flow
8537  *   Pointer to flow structure.
8538  */
8539 static void
8540 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8541 {
8542         struct mlx5_flow_handle *dh;
8543         uint32_t handle_idx;
8544         struct mlx5_priv *priv = dev->data->dev_private;
8545
8546         if (!flow)
8547                 return;
8548         handle_idx = flow->dev_handles;
8549         while (handle_idx) {
8550                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8551                                     handle_idx);
8552                 if (!dh)
8553                         return;
8554                 if (dh->ib_flow) {
8555                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8556                         dh->ib_flow = NULL;
8557                 }
8558                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8559                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8560                         flow_dv_fate_resource_release(dev, dh);
8561                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8562                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8563                 handle_idx = dh->next.next;
8564         }
8565 }
8566
8567 /**
8568  * Remove the flow from the NIC and the memory.
8569  * Lock free, (mutex should be acquired by caller).
8570  *
8571  * @param[in] dev
8572  *   Pointer to the Ethernet device structure.
8573  * @param[in, out] flow
8574  *   Pointer to flow structure.
8575  */
8576 static void
8577 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8578 {
8579         struct mlx5_flow_handle *dev_handle;
8580         struct mlx5_priv *priv = dev->data->dev_private;
8581
8582         if (!flow)
8583                 return;
8584         __flow_dv_remove(dev, flow);
8585         if (flow->counter) {
8586                 flow_dv_counter_release(dev, flow->counter);
8587                 flow->counter = 0;
8588         }
8589         if (flow->meter) {
8590                 struct mlx5_flow_meter *fm;
8591
8592                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8593                                     flow->meter);
8594                 if (fm)
8595                         mlx5_flow_meter_detach(fm);
8596                 flow->meter = 0;
8597         }
8598         while (flow->dev_handles) {
8599                 uint32_t tmp_idx = flow->dev_handles;
8600
8601                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8602                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8603                 if (!dev_handle)
8604                         return;
8605                 flow->dev_handles = dev_handle->next.next;
8606                 if (dev_handle->dvh.matcher)
8607                         flow_dv_matcher_release(dev, dev_handle);
8608                 if (dev_handle->dvh.rix_encap_decap)
8609                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8610                 if (dev_handle->dvh.modify_hdr)
8611                         flow_dv_modify_hdr_resource_release(dev_handle);
8612                 if (dev_handle->dvh.rix_push_vlan)
8613                         flow_dv_push_vlan_action_resource_release(dev,
8614                                                                   dev_handle);
8615                 if (dev_handle->dvh.rix_tag)
8616                         flow_dv_tag_release(dev,
8617                                             dev_handle->dvh.rix_tag);
8618                 flow_dv_fate_resource_release(dev, dev_handle);
8619                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8620                            tmp_idx);
8621         }
8622 }
8623
8624 /**
8625  * Query a dv flow  rule for its statistics via devx.
8626  *
8627  * @param[in] dev
8628  *   Pointer to Ethernet device.
8629  * @param[in] flow
8630  *   Pointer to the sub flow.
8631  * @param[out] data
8632  *   data retrieved by the query.
8633  * @param[out] error
8634  *   Perform verbose error reporting if not NULL.
8635  *
8636  * @return
8637  *   0 on success, a negative errno value otherwise and rte_errno is set.
8638  */
8639 static int
8640 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8641                     void *data, struct rte_flow_error *error)
8642 {
8643         struct mlx5_priv *priv = dev->data->dev_private;
8644         struct rte_flow_query_count *qc = data;
8645
8646         if (!priv->config.devx)
8647                 return rte_flow_error_set(error, ENOTSUP,
8648                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8649                                           NULL,
8650                                           "counters are not supported");
8651         if (flow->counter) {
8652                 uint64_t pkts, bytes;
8653                 struct mlx5_flow_counter *cnt;
8654
8655                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8656                                                  NULL);
8657                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8658                                                &bytes);
8659
8660                 if (err)
8661                         return rte_flow_error_set(error, -err,
8662                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8663                                         NULL, "cannot read counters");
8664                 qc->hits_set = 1;
8665                 qc->bytes_set = 1;
8666                 qc->hits = pkts - cnt->hits;
8667                 qc->bytes = bytes - cnt->bytes;
8668                 if (qc->reset) {
8669                         cnt->hits = pkts;
8670                         cnt->bytes = bytes;
8671                 }
8672                 return 0;
8673         }
8674         return rte_flow_error_set(error, EINVAL,
8675                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8676                                   NULL,
8677                                   "counters are not available");
8678 }
8679
8680 /**
8681  * Query a flow.
8682  *
8683  * @see rte_flow_query()
8684  * @see rte_flow_ops
8685  */
8686 static int
8687 flow_dv_query(struct rte_eth_dev *dev,
8688               struct rte_flow *flow __rte_unused,
8689               const struct rte_flow_action *actions __rte_unused,
8690               void *data __rte_unused,
8691               struct rte_flow_error *error __rte_unused)
8692 {
8693         int ret = -EINVAL;
8694
8695         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8696                 switch (actions->type) {
8697                 case RTE_FLOW_ACTION_TYPE_VOID:
8698                         break;
8699                 case RTE_FLOW_ACTION_TYPE_COUNT:
8700                         ret = flow_dv_query_count(dev, flow, data, error);
8701                         break;
8702                 default:
8703                         return rte_flow_error_set(error, ENOTSUP,
8704                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8705                                                   actions,
8706                                                   "action not supported");
8707                 }
8708         }
8709         return ret;
8710 }
8711
8712 /**
8713  * Destroy the meter table set.
8714  * Lock free, (mutex should be acquired by caller).
8715  *
8716  * @param[in] dev
8717  *   Pointer to Ethernet device.
8718  * @param[in] tbl
8719  *   Pointer to the meter table set.
8720  *
8721  * @return
8722  *   Always 0.
8723  */
8724 static int
8725 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8726                         struct mlx5_meter_domains_infos *tbl)
8727 {
8728         struct mlx5_priv *priv = dev->data->dev_private;
8729         struct mlx5_meter_domains_infos *mtd =
8730                                 (struct mlx5_meter_domains_infos *)tbl;
8731
8732         if (!mtd || !priv->config.dv_flow_en)
8733                 return 0;
8734         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8735                 claim_zero(mlx5_glue->dv_destroy_flow
8736                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8737         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8738                 claim_zero(mlx5_glue->dv_destroy_flow
8739                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8740         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8741                 claim_zero(mlx5_glue->dv_destroy_flow
8742                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8743         if (mtd->egress.color_matcher)
8744                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8745                           (mtd->egress.color_matcher));
8746         if (mtd->egress.any_matcher)
8747                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8748                           (mtd->egress.any_matcher));
8749         if (mtd->egress.tbl)
8750                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
8751         if (mtd->egress.sfx_tbl)
8752                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
8753         if (mtd->ingress.color_matcher)
8754                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8755                           (mtd->ingress.color_matcher));
8756         if (mtd->ingress.any_matcher)
8757                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8758                           (mtd->ingress.any_matcher));
8759         if (mtd->ingress.tbl)
8760                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
8761         if (mtd->ingress.sfx_tbl)
8762                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
8763         if (mtd->transfer.color_matcher)
8764                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8765                           (mtd->transfer.color_matcher));
8766         if (mtd->transfer.any_matcher)
8767                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8768                           (mtd->transfer.any_matcher));
8769         if (mtd->transfer.tbl)
8770                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
8771         if (mtd->transfer.sfx_tbl)
8772                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
8773         if (mtd->drop_actn)
8774                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8775         rte_free(mtd);
8776         return 0;
8777 }
8778
8779 /* Number of meter flow actions, count and jump or count and drop. */
8780 #define METER_ACTIONS 2
8781
8782 /**
8783  * Create specify domain meter table and suffix table.
8784  *
8785  * @param[in] dev
8786  *   Pointer to Ethernet device.
8787  * @param[in,out] mtb
8788  *   Pointer to DV meter table set.
8789  * @param[in] egress
8790  *   Table attribute.
8791  * @param[in] transfer
8792  *   Table attribute.
8793  * @param[in] color_reg_c_idx
8794  *   Reg C index for color match.
8795  *
8796  * @return
8797  *   0 on success, -1 otherwise and rte_errno is set.
8798  */
8799 static int
8800 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8801                            struct mlx5_meter_domains_infos *mtb,
8802                            uint8_t egress, uint8_t transfer,
8803                            uint32_t color_reg_c_idx)
8804 {
8805         struct mlx5_priv *priv = dev->data->dev_private;
8806         struct mlx5_ibv_shared *sh = priv->sh;
8807         struct mlx5_flow_dv_match_params mask = {
8808                 .size = sizeof(mask.buf),
8809         };
8810         struct mlx5_flow_dv_match_params value = {
8811                 .size = sizeof(value.buf),
8812         };
8813         struct mlx5dv_flow_matcher_attr dv_attr = {
8814                 .type = IBV_FLOW_ATTR_NORMAL,
8815                 .priority = 0,
8816                 .match_criteria_enable = 0,
8817                 .match_mask = (void *)&mask,
8818         };
8819         void *actions[METER_ACTIONS];
8820         struct mlx5_meter_domain_info *dtb;
8821         struct rte_flow_error error;
8822         int i = 0;
8823
8824         if (transfer)
8825                 dtb = &mtb->transfer;
8826         else if (egress)
8827                 dtb = &mtb->egress;
8828         else
8829                 dtb = &mtb->ingress;
8830         /* Create the meter table with METER level. */
8831         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8832                                             egress, transfer, &error);
8833         if (!dtb->tbl) {
8834                 DRV_LOG(ERR, "Failed to create meter policer table.");
8835                 return -1;
8836         }
8837         /* Create the meter suffix table with SUFFIX level. */
8838         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8839                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8840                                             egress, transfer, &error);
8841         if (!dtb->sfx_tbl) {
8842                 DRV_LOG(ERR, "Failed to create meter suffix table.");
8843                 return -1;
8844         }
8845         /* Create matchers, Any and Color. */
8846         dv_attr.priority = 3;
8847         dv_attr.match_criteria_enable = 0;
8848         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8849                                                              &dv_attr,
8850                                                              dtb->tbl->obj);
8851         if (!dtb->any_matcher) {
8852                 DRV_LOG(ERR, "Failed to create meter"
8853                              " policer default matcher.");
8854                 goto error_exit;
8855         }
8856         dv_attr.priority = 0;
8857         dv_attr.match_criteria_enable =
8858                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8859         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8860                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8861         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8862                                                                &dv_attr,
8863                                                                dtb->tbl->obj);
8864         if (!dtb->color_matcher) {
8865                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8866                 goto error_exit;
8867         }
8868         if (mtb->count_actns[RTE_MTR_DROPPED])
8869                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8870         actions[i++] = mtb->drop_actn;
8871         /* Default rule: lowest priority, match any, actions: drop. */
8872         dtb->policer_rules[RTE_MTR_DROPPED] =
8873                         mlx5_glue->dv_create_flow(dtb->any_matcher,
8874                                                  (void *)&value, i, actions);
8875         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8876                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8877                 goto error_exit;
8878         }
8879         return 0;
8880 error_exit:
8881         return -1;
8882 }
8883
8884 /**
8885  * Create the needed meter and suffix tables.
8886  * Lock free, (mutex should be acquired by caller).
8887  *
8888  * @param[in] dev
8889  *   Pointer to Ethernet device.
8890  * @param[in] fm
8891  *   Pointer to the flow meter.
8892  *
8893  * @return
8894  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
8895  */
8896 static struct mlx5_meter_domains_infos *
8897 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8898                        const struct mlx5_flow_meter *fm)
8899 {
8900         struct mlx5_priv *priv = dev->data->dev_private;
8901         struct mlx5_meter_domains_infos *mtb;
8902         int ret;
8903         int i;
8904
8905         if (!priv->mtr_en) {
8906                 rte_errno = ENOTSUP;
8907                 return NULL;
8908         }
8909         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8910         if (!mtb) {
8911                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8912                 return NULL;
8913         }
8914         /* Create meter count actions */
8915         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8916                 struct mlx5_flow_counter *cnt;
8917                 if (!fm->policer_stats.cnt[i])
8918                         continue;
8919                 cnt = flow_dv_counter_get_by_idx(dev,
8920                       fm->policer_stats.cnt[i], NULL);
8921                 mtb->count_actns[i] = cnt->action;
8922         }
8923         /* Create drop action. */
8924         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8925         if (!mtb->drop_actn) {
8926                 DRV_LOG(ERR, "Failed to create drop action.");
8927                 goto error_exit;
8928         }
8929         /* Egress meter table. */
8930         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8931         if (ret) {
8932                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8933                 goto error_exit;
8934         }
8935         /* Ingress meter table. */
8936         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8937         if (ret) {
8938                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8939                 goto error_exit;
8940         }
8941         /* FDB meter table. */
8942         if (priv->config.dv_esw_en) {
8943                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8944                                                  priv->mtr_color_reg);
8945                 if (ret) {
8946                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8947                         goto error_exit;
8948                 }
8949         }
8950         return mtb;
8951 error_exit:
8952         flow_dv_destroy_mtr_tbl(dev, mtb);
8953         return NULL;
8954 }
8955
8956 /**
8957  * Destroy domain policer rule.
8958  *
8959  * @param[in] dt
8960  *   Pointer to domain table.
8961  */
8962 static void
8963 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8964 {
8965         int i;
8966
8967         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8968                 if (dt->policer_rules[i]) {
8969                         claim_zero(mlx5_glue->dv_destroy_flow
8970                                   (dt->policer_rules[i]));
8971                         dt->policer_rules[i] = NULL;
8972                 }
8973         }
8974         if (dt->jump_actn) {
8975                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8976                 dt->jump_actn = NULL;
8977         }
8978 }
8979
8980 /**
8981  * Destroy policer rules.
8982  *
8983  * @param[in] dev
8984  *   Pointer to Ethernet device.
8985  * @param[in] fm
8986  *   Pointer to flow meter structure.
8987  * @param[in] attr
8988  *   Pointer to flow attributes.
8989  *
8990  * @return
8991  *   Always 0.
8992  */
8993 static int
8994 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8995                               const struct mlx5_flow_meter *fm,
8996                               const struct rte_flow_attr *attr)
8997 {
8998         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8999
9000         if (!mtb)
9001                 return 0;
9002         if (attr->egress)
9003                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9004         if (attr->ingress)
9005                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9006         if (attr->transfer)
9007                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9008         return 0;
9009 }
9010
9011 /**
9012  * Create specify domain meter policer rule.
9013  *
9014  * @param[in] fm
9015  *   Pointer to flow meter structure.
9016  * @param[in] mtb
9017  *   Pointer to DV meter table set.
9018  * @param[in] mtr_reg_c
9019  *   Color match REG_C.
9020  *
9021  * @return
9022  *   0 on success, -1 otherwise.
9023  */
9024 static int
9025 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9026                                     struct mlx5_meter_domain_info *dtb,
9027                                     uint8_t mtr_reg_c)
9028 {
9029         struct mlx5_flow_dv_match_params matcher = {
9030                 .size = sizeof(matcher.buf),
9031         };
9032         struct mlx5_flow_dv_match_params value = {
9033                 .size = sizeof(value.buf),
9034         };
9035         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9036         void *actions[METER_ACTIONS];
9037         int i;
9038
9039         /* Create jump action. */
9040         if (!dtb->jump_actn)
9041                 dtb->jump_actn =
9042                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9043                                                         (dtb->sfx_tbl->obj);
9044         if (!dtb->jump_actn) {
9045                 DRV_LOG(ERR, "Failed to create policer jump action.");
9046                 goto error;
9047         }
9048         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9049                 int j = 0;
9050
9051                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9052                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9053                 if (mtb->count_actns[i])
9054                         actions[j++] = mtb->count_actns[i];
9055                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9056                         actions[j++] = mtb->drop_actn;
9057                 else
9058                         actions[j++] = dtb->jump_actn;
9059                 dtb->policer_rules[i] =
9060                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9061                                                  (void *)&value,
9062                                                   j, actions);
9063                 if (!dtb->policer_rules[i]) {
9064                         DRV_LOG(ERR, "Failed to create policer rule.");
9065                         goto error;
9066                 }
9067         }
9068         return 0;
9069 error:
9070         rte_errno = errno;
9071         return -1;
9072 }
9073
9074 /**
9075  * Create policer rules.
9076  *
9077  * @param[in] dev
9078  *   Pointer to Ethernet device.
9079  * @param[in] fm
9080  *   Pointer to flow meter structure.
9081  * @param[in] attr
9082  *   Pointer to flow attributes.
9083  *
9084  * @return
9085  *   0 on success, -1 otherwise.
9086  */
9087 static int
9088 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9089                              struct mlx5_flow_meter *fm,
9090                              const struct rte_flow_attr *attr)
9091 {
9092         struct mlx5_priv *priv = dev->data->dev_private;
9093         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9094         int ret;
9095
9096         if (attr->egress) {
9097                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9098                                                 priv->mtr_color_reg);
9099                 if (ret) {
9100                         DRV_LOG(ERR, "Failed to create egress policer.");
9101                         goto error;
9102                 }
9103         }
9104         if (attr->ingress) {
9105                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9106                                                 priv->mtr_color_reg);
9107                 if (ret) {
9108                         DRV_LOG(ERR, "Failed to create ingress policer.");
9109                         goto error;
9110                 }
9111         }
9112         if (attr->transfer) {
9113                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9114                                                 priv->mtr_color_reg);
9115                 if (ret) {
9116                         DRV_LOG(ERR, "Failed to create transfer policer.");
9117                         goto error;
9118                 }
9119         }
9120         return 0;
9121 error:
9122         flow_dv_destroy_policer_rules(dev, fm, attr);
9123         return -1;
9124 }
9125
9126 /**
9127  * Query a devx counter.
9128  *
9129  * @param[in] dev
9130  *   Pointer to the Ethernet device structure.
9131  * @param[in] cnt
9132  *   Index to the flow counter.
9133  * @param[in] clear
9134  *   Set to clear the counter statistics.
9135  * @param[out] pkts
9136  *   The statistics value of packets.
9137  * @param[out] bytes
9138  *   The statistics value of bytes.
9139  *
9140  * @return
9141  *   0 on success, otherwise return -1.
9142  */
9143 static int
9144 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9145                       uint64_t *pkts, uint64_t *bytes)
9146 {
9147         struct mlx5_priv *priv = dev->data->dev_private;
9148         struct mlx5_flow_counter *cnt;
9149         uint64_t inn_pkts, inn_bytes;
9150         int ret;
9151
9152         if (!priv->config.devx)
9153                 return -1;
9154
9155         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9156         if (ret)
9157                 return -1;
9158         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9159         *pkts = inn_pkts - cnt->hits;
9160         *bytes = inn_bytes - cnt->bytes;
9161         if (clear) {
9162                 cnt->hits = inn_pkts;
9163                 cnt->bytes = inn_bytes;
9164         }
9165         return 0;
9166 }
9167
9168 /*
9169  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9170  */
9171 static int
9172 flow_dv_translate(struct rte_eth_dev *dev,
9173                   struct mlx5_flow *dev_flow,
9174                   const struct rte_flow_attr *attr,
9175                   const struct rte_flow_item items[],
9176                   const struct rte_flow_action actions[],
9177                   struct rte_flow_error *error)
9178 {
9179         int ret;
9180
9181         flow_dv_shared_lock(dev);
9182         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9183         flow_dv_shared_unlock(dev);
9184         return ret;
9185 }
9186
9187 /*
9188  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9189  */
9190 static int
9191 flow_dv_apply(struct rte_eth_dev *dev,
9192               struct rte_flow *flow,
9193               struct rte_flow_error *error)
9194 {
9195         int ret;
9196
9197         flow_dv_shared_lock(dev);
9198         ret = __flow_dv_apply(dev, flow, error);
9199         flow_dv_shared_unlock(dev);
9200         return ret;
9201 }
9202
9203 /*
9204  * Mutex-protected thunk to lock-free __flow_dv_remove().
9205  */
9206 static void
9207 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9208 {
9209         flow_dv_shared_lock(dev);
9210         __flow_dv_remove(dev, flow);
9211         flow_dv_shared_unlock(dev);
9212 }
9213
9214 /*
9215  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9216  */
9217 static void
9218 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9219 {
9220         flow_dv_shared_lock(dev);
9221         __flow_dv_destroy(dev, flow);
9222         flow_dv_shared_unlock(dev);
9223 }
9224
9225 /*
9226  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9227  */
9228 static uint32_t
9229 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9230 {
9231         uint32_t cnt;
9232
9233         flow_dv_shared_lock(dev);
9234         cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9235         flow_dv_shared_unlock(dev);
9236         return cnt;
9237 }
9238
9239 /*
9240  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9241  */
9242 static void
9243 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9244 {
9245         flow_dv_shared_lock(dev);
9246         flow_dv_counter_release(dev, cnt);
9247         flow_dv_shared_unlock(dev);
9248 }
9249
9250 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9251         .validate = flow_dv_validate,
9252         .prepare = flow_dv_prepare,
9253         .translate = flow_dv_translate,
9254         .apply = flow_dv_apply,
9255         .remove = flow_dv_remove,
9256         .destroy = flow_dv_destroy,
9257         .query = flow_dv_query,
9258         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9259         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9260         .create_policer_rules = flow_dv_create_policer_rules,
9261         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9262         .counter_alloc = flow_dv_counter_allocate,
9263         .counter_free = flow_dv_counter_free,
9264         .counter_query = flow_dv_counter_query,
9265 };
9266
9267 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */