1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_bus_pci.h>
21 #include <rte_vxlan.h>
23 #include <rte_eal_paging.h>
26 #include <rte_mtr_driver.h>
27 #include <rte_tailq.h>
29 #include <mlx5_glue.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_malloc.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_common_os.h"
37 #include "mlx5_flow.h"
38 #include "mlx5_flow_os.h"
41 #include "rte_pmd_mlx5.h"
43 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
45 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
46 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
49 #ifndef HAVE_MLX5DV_DR_ESWITCH
50 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
51 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
55 #ifndef HAVE_MLX5DV_DR
56 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
80 struct mlx5_flow_tbl_resource *tbl);
83 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
84 uint32_t encap_decap_idx);
87 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
90 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
93 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
96 static inline uint16_t
97 mlx5_translate_tunnel_etypes(uint64_t pattern_flags)
99 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
100 return RTE_ETHER_TYPE_TEB;
101 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
102 return RTE_ETHER_TYPE_IPV4;
103 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
104 return RTE_ETHER_TYPE_IPV6;
105 else if (pattern_flags & MLX5_FLOW_LAYER_MPLS)
106 return RTE_ETHER_TYPE_MPLS;
111 flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
113 struct mlx5_priv *priv = dev->data->dev_private;
115 if (priv->pci_dev == NULL)
117 switch (priv->pci_dev->id.device_id) {
118 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
119 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
120 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
121 return (int16_t)0xfffe;
128 * Initialize flow attributes structure according to flow items' types.
130 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
131 * mode. For tunnel mode, the items to be modified are the outermost ones.
134 * Pointer to item specification.
136 * Pointer to flow attributes structure.
137 * @param[in] dev_flow
138 * Pointer to the sub flow.
139 * @param[in] tunnel_decap
140 * Whether action is after tunnel decapsulation.
143 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
144 struct mlx5_flow *dev_flow, bool tunnel_decap)
146 uint64_t layers = dev_flow->handle->layers;
149 * If layers is already initialized, it means this dev_flow is the
150 * suffix flow, the layers flags is set by the prefix flow. Need to
151 * use the layer flags from prefix flow as the suffix flow may not
152 * have the user defined items as the flow is split.
155 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
157 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
159 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
161 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
166 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
167 uint8_t next_protocol = 0xff;
168 switch (item->type) {
169 case RTE_FLOW_ITEM_TYPE_GRE:
170 case RTE_FLOW_ITEM_TYPE_NVGRE:
171 case RTE_FLOW_ITEM_TYPE_VXLAN:
172 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
173 case RTE_FLOW_ITEM_TYPE_GENEVE:
174 case RTE_FLOW_ITEM_TYPE_MPLS:
178 case RTE_FLOW_ITEM_TYPE_IPV4:
181 if (item->mask != NULL &&
182 ((const struct rte_flow_item_ipv4 *)
183 item->mask)->hdr.next_proto_id)
185 ((const struct rte_flow_item_ipv4 *)
186 (item->spec))->hdr.next_proto_id &
187 ((const struct rte_flow_item_ipv4 *)
188 (item->mask))->hdr.next_proto_id;
189 if ((next_protocol == IPPROTO_IPIP ||
190 next_protocol == IPPROTO_IPV6) && tunnel_decap)
193 case RTE_FLOW_ITEM_TYPE_IPV6:
196 if (item->mask != NULL &&
197 ((const struct rte_flow_item_ipv6 *)
198 item->mask)->hdr.proto)
200 ((const struct rte_flow_item_ipv6 *)
201 (item->spec))->hdr.proto &
202 ((const struct rte_flow_item_ipv6 *)
203 (item->mask))->hdr.proto;
204 if ((next_protocol == IPPROTO_IPIP ||
205 next_protocol == IPPROTO_IPV6) && tunnel_decap)
208 case RTE_FLOW_ITEM_TYPE_UDP:
212 case RTE_FLOW_ITEM_TYPE_TCP:
224 * Convert rte_mtr_color to mlx5 color.
233 rte_col_2_mlx5_col(enum rte_color rcol)
236 case RTE_COLOR_GREEN:
237 return MLX5_FLOW_COLOR_GREEN;
238 case RTE_COLOR_YELLOW:
239 return MLX5_FLOW_COLOR_YELLOW;
241 return MLX5_FLOW_COLOR_RED;
245 return MLX5_FLOW_COLOR_UNDEFINED;
248 struct field_modify_info {
249 uint32_t size; /* Size of field in protocol header, in bytes. */
250 uint32_t offset; /* Offset of field in protocol header, in bytes. */
251 enum mlx5_modification_field id;
254 struct field_modify_info modify_eth[] = {
255 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
256 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
257 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
258 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
262 struct field_modify_info modify_vlan_out_first_vid[] = {
263 /* Size in bits !!! */
264 {12, 0, MLX5_MODI_OUT_FIRST_VID},
268 struct field_modify_info modify_ipv4[] = {
269 {1, 1, MLX5_MODI_OUT_IP_DSCP},
270 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
271 {4, 12, MLX5_MODI_OUT_SIPV4},
272 {4, 16, MLX5_MODI_OUT_DIPV4},
276 struct field_modify_info modify_ipv6[] = {
277 {1, 0, MLX5_MODI_OUT_IP_DSCP},
278 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
279 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
280 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
281 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
282 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
283 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
284 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
285 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
286 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
290 struct field_modify_info modify_udp[] = {
291 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
292 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
296 struct field_modify_info modify_tcp[] = {
297 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
298 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
299 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
300 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
305 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
306 uint8_t next_protocol, uint64_t *item_flags,
309 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
310 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
311 if (next_protocol == IPPROTO_IPIP) {
312 *item_flags |= MLX5_FLOW_LAYER_IPIP;
315 if (next_protocol == IPPROTO_IPV6) {
316 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
321 static inline struct mlx5_hlist *
322 flow_dv_hlist_prepare(struct mlx5_dev_ctx_shared *sh, struct mlx5_hlist **phl,
323 const char *name, uint32_t size, bool direct_key,
324 bool lcores_share, void *ctx,
325 mlx5_list_create_cb cb_create,
326 mlx5_list_match_cb cb_match,
327 mlx5_list_remove_cb cb_remove,
328 mlx5_list_clone_cb cb_clone,
329 mlx5_list_clone_free_cb cb_clone_free)
331 struct mlx5_hlist *hl;
332 struct mlx5_hlist *expected = NULL;
333 char s[MLX5_NAME_SIZE];
335 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
338 snprintf(s, sizeof(s), "%s_%s", sh->ibdev_name, name);
339 hl = mlx5_hlist_create(s, size, direct_key, lcores_share,
340 ctx, cb_create, cb_match, cb_remove, cb_clone,
343 DRV_LOG(ERR, "%s hash creation failed", name);
347 if (!__atomic_compare_exchange_n(phl, &expected, hl, false,
350 mlx5_hlist_destroy(hl);
351 hl = __atomic_load_n(phl, __ATOMIC_SEQ_CST);
356 /* Update VLAN's VID/PCP based on input rte_flow_action.
359 * Pointer to struct rte_flow_action.
361 * Pointer to struct rte_vlan_hdr.
364 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
365 struct rte_vlan_hdr *vlan)
368 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
370 ((const struct rte_flow_action_of_set_vlan_pcp *)
371 action->conf)->vlan_pcp;
372 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
373 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
374 vlan->vlan_tci |= vlan_tci;
375 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
376 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
377 vlan->vlan_tci |= rte_be_to_cpu_16
378 (((const struct rte_flow_action_of_set_vlan_vid *)
379 action->conf)->vlan_vid);
384 * Fetch 1, 2, 3 or 4 byte field from the byte array
385 * and return as unsigned integer in host-endian format.
388 * Pointer to data array.
390 * Size of field to extract.
393 * converted field in host endian format.
395 static inline uint32_t
396 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
405 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
408 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
409 ret = (ret << 8) | *(data + sizeof(uint16_t));
412 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
423 * Convert modify-header action to DV specification.
425 * Data length of each action is determined by provided field description
426 * and the item mask. Data bit offset and width of each action is determined
427 * by provided item mask.
430 * Pointer to item specification.
432 * Pointer to field modification information.
433 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
434 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
435 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
437 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
438 * Negative offset value sets the same offset as source offset.
439 * size field is ignored, value is taken from source field.
440 * @param[in,out] resource
441 * Pointer to the modify-header resource.
443 * Type of modification.
445 * Pointer to the error structure.
448 * 0 on success, a negative errno value otherwise and rte_errno is set.
451 flow_dv_convert_modify_action(struct rte_flow_item *item,
452 struct field_modify_info *field,
453 struct field_modify_info *dcopy,
454 struct mlx5_flow_dv_modify_hdr_resource *resource,
455 uint32_t type, struct rte_flow_error *error)
457 uint32_t i = resource->actions_num;
458 struct mlx5_modification_cmd *actions = resource->actions;
459 uint32_t carry_b = 0;
462 * The item and mask are provided in big-endian format.
463 * The fields should be presented as in big-endian format either.
464 * Mask must be always present, it defines the actual field width.
466 MLX5_ASSERT(item->mask);
467 MLX5_ASSERT(field->size);
473 bool next_field = true;
474 bool next_dcopy = true;
476 if (i >= MLX5_MAX_MODIFY_NUM)
477 return rte_flow_error_set(error, EINVAL,
478 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
479 "too many items to modify");
480 /* Fetch variable byte size mask from the array. */
481 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
482 field->offset, field->size);
487 /* Deduce actual data width in bits from mask value. */
488 off_b = rte_bsf32(mask) + carry_b;
489 size_b = sizeof(uint32_t) * CHAR_BIT -
490 off_b - __builtin_clz(mask);
492 actions[i] = (struct mlx5_modification_cmd) {
496 .length = (size_b == sizeof(uint32_t) * CHAR_BIT) ?
499 if (type == MLX5_MODIFICATION_TYPE_COPY) {
501 actions[i].dst_field = dcopy->id;
502 actions[i].dst_offset =
503 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
504 /* Convert entire record to big-endian format. */
505 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
507 * Destination field overflow. Copy leftovers of
508 * a source field to the next destination field.
511 if ((size_b > dcopy->size * CHAR_BIT - dcopy->offset) &&
514 dcopy->size * CHAR_BIT - dcopy->offset;
515 carry_b = actions[i].length;
519 * Not enough bits in a source filed to fill a
520 * destination field. Switch to the next source.
522 if ((size_b < dcopy->size * CHAR_BIT - dcopy->offset) &&
523 (size_b == field->size * CHAR_BIT - off_b)) {
525 field->size * CHAR_BIT - off_b;
526 dcopy->offset += actions[i].length;
532 MLX5_ASSERT(item->spec);
533 data = flow_dv_fetch_field((const uint8_t *)item->spec +
534 field->offset, field->size);
535 /* Shift out the trailing masked bits from data. */
536 data = (data & mask) >> off_b;
537 actions[i].data1 = rte_cpu_to_be_32(data);
539 /* Convert entire record to expected big-endian format. */
540 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
544 } while (field->size);
545 if (resource->actions_num == i)
546 return rte_flow_error_set(error, EINVAL,
547 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
548 "invalid modification flow item");
549 resource->actions_num = i;
554 * Convert modify-header set IPv4 address action to DV specification.
556 * @param[in,out] resource
557 * Pointer to the modify-header resource.
559 * Pointer to action specification.
561 * Pointer to the error structure.
564 * 0 on success, a negative errno value otherwise and rte_errno is set.
567 flow_dv_convert_action_modify_ipv4
568 (struct mlx5_flow_dv_modify_hdr_resource *resource,
569 const struct rte_flow_action *action,
570 struct rte_flow_error *error)
572 const struct rte_flow_action_set_ipv4 *conf =
573 (const struct rte_flow_action_set_ipv4 *)(action->conf);
574 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
575 struct rte_flow_item_ipv4 ipv4;
576 struct rte_flow_item_ipv4 ipv4_mask;
578 memset(&ipv4, 0, sizeof(ipv4));
579 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
580 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
581 ipv4.hdr.src_addr = conf->ipv4_addr;
582 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
584 ipv4.hdr.dst_addr = conf->ipv4_addr;
585 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
588 item.mask = &ipv4_mask;
589 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
590 MLX5_MODIFICATION_TYPE_SET, error);
594 * Convert modify-header set IPv6 address action to DV specification.
596 * @param[in,out] resource
597 * Pointer to the modify-header resource.
599 * Pointer to action specification.
601 * Pointer to the error structure.
604 * 0 on success, a negative errno value otherwise and rte_errno is set.
607 flow_dv_convert_action_modify_ipv6
608 (struct mlx5_flow_dv_modify_hdr_resource *resource,
609 const struct rte_flow_action *action,
610 struct rte_flow_error *error)
612 const struct rte_flow_action_set_ipv6 *conf =
613 (const struct rte_flow_action_set_ipv6 *)(action->conf);
614 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
615 struct rte_flow_item_ipv6 ipv6;
616 struct rte_flow_item_ipv6 ipv6_mask;
618 memset(&ipv6, 0, sizeof(ipv6));
619 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
620 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
621 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
622 sizeof(ipv6.hdr.src_addr));
623 memcpy(&ipv6_mask.hdr.src_addr,
624 &rte_flow_item_ipv6_mask.hdr.src_addr,
625 sizeof(ipv6.hdr.src_addr));
627 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
628 sizeof(ipv6.hdr.dst_addr));
629 memcpy(&ipv6_mask.hdr.dst_addr,
630 &rte_flow_item_ipv6_mask.hdr.dst_addr,
631 sizeof(ipv6.hdr.dst_addr));
634 item.mask = &ipv6_mask;
635 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
636 MLX5_MODIFICATION_TYPE_SET, error);
640 * Convert modify-header set MAC address action to DV specification.
642 * @param[in,out] resource
643 * Pointer to the modify-header resource.
645 * Pointer to action specification.
647 * Pointer to the error structure.
650 * 0 on success, a negative errno value otherwise and rte_errno is set.
653 flow_dv_convert_action_modify_mac
654 (struct mlx5_flow_dv_modify_hdr_resource *resource,
655 const struct rte_flow_action *action,
656 struct rte_flow_error *error)
658 const struct rte_flow_action_set_mac *conf =
659 (const struct rte_flow_action_set_mac *)(action->conf);
660 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
661 struct rte_flow_item_eth eth;
662 struct rte_flow_item_eth eth_mask;
664 memset(ð, 0, sizeof(eth));
665 memset(ð_mask, 0, sizeof(eth_mask));
666 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
667 memcpy(ð.src.addr_bytes, &conf->mac_addr,
668 sizeof(eth.src.addr_bytes));
669 memcpy(ð_mask.src.addr_bytes,
670 &rte_flow_item_eth_mask.src.addr_bytes,
671 sizeof(eth_mask.src.addr_bytes));
673 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
674 sizeof(eth.dst.addr_bytes));
675 memcpy(ð_mask.dst.addr_bytes,
676 &rte_flow_item_eth_mask.dst.addr_bytes,
677 sizeof(eth_mask.dst.addr_bytes));
680 item.mask = ð_mask;
681 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
682 MLX5_MODIFICATION_TYPE_SET, error);
686 * Convert modify-header set VLAN VID action to DV specification.
688 * @param[in,out] resource
689 * Pointer to the modify-header resource.
691 * Pointer to action specification.
693 * Pointer to the error structure.
696 * 0 on success, a negative errno value otherwise and rte_errno is set.
699 flow_dv_convert_action_modify_vlan_vid
700 (struct mlx5_flow_dv_modify_hdr_resource *resource,
701 const struct rte_flow_action *action,
702 struct rte_flow_error *error)
704 const struct rte_flow_action_of_set_vlan_vid *conf =
705 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
706 int i = resource->actions_num;
707 struct mlx5_modification_cmd *actions = resource->actions;
708 struct field_modify_info *field = modify_vlan_out_first_vid;
710 if (i >= MLX5_MAX_MODIFY_NUM)
711 return rte_flow_error_set(error, EINVAL,
712 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
713 "too many items to modify");
714 actions[i] = (struct mlx5_modification_cmd) {
715 .action_type = MLX5_MODIFICATION_TYPE_SET,
717 .length = field->size,
718 .offset = field->offset,
720 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
721 actions[i].data1 = conf->vlan_vid;
722 actions[i].data1 = actions[i].data1 << 16;
723 resource->actions_num = ++i;
728 * Convert modify-header set TP action to DV specification.
730 * @param[in,out] resource
731 * Pointer to the modify-header resource.
733 * Pointer to action specification.
735 * Pointer to rte_flow_item objects list.
737 * Pointer to flow attributes structure.
738 * @param[in] dev_flow
739 * Pointer to the sub flow.
740 * @param[in] tunnel_decap
741 * Whether action is after tunnel decapsulation.
743 * Pointer to the error structure.
746 * 0 on success, a negative errno value otherwise and rte_errno is set.
749 flow_dv_convert_action_modify_tp
750 (struct mlx5_flow_dv_modify_hdr_resource *resource,
751 const struct rte_flow_action *action,
752 const struct rte_flow_item *items,
753 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
754 bool tunnel_decap, struct rte_flow_error *error)
756 const struct rte_flow_action_set_tp *conf =
757 (const struct rte_flow_action_set_tp *)(action->conf);
758 struct rte_flow_item item;
759 struct rte_flow_item_udp udp;
760 struct rte_flow_item_udp udp_mask;
761 struct rte_flow_item_tcp tcp;
762 struct rte_flow_item_tcp tcp_mask;
763 struct field_modify_info *field;
766 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
768 memset(&udp, 0, sizeof(udp));
769 memset(&udp_mask, 0, sizeof(udp_mask));
770 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
771 udp.hdr.src_port = conf->port;
772 udp_mask.hdr.src_port =
773 rte_flow_item_udp_mask.hdr.src_port;
775 udp.hdr.dst_port = conf->port;
776 udp_mask.hdr.dst_port =
777 rte_flow_item_udp_mask.hdr.dst_port;
779 item.type = RTE_FLOW_ITEM_TYPE_UDP;
781 item.mask = &udp_mask;
784 MLX5_ASSERT(attr->tcp);
785 memset(&tcp, 0, sizeof(tcp));
786 memset(&tcp_mask, 0, sizeof(tcp_mask));
787 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
788 tcp.hdr.src_port = conf->port;
789 tcp_mask.hdr.src_port =
790 rte_flow_item_tcp_mask.hdr.src_port;
792 tcp.hdr.dst_port = conf->port;
793 tcp_mask.hdr.dst_port =
794 rte_flow_item_tcp_mask.hdr.dst_port;
796 item.type = RTE_FLOW_ITEM_TYPE_TCP;
798 item.mask = &tcp_mask;
801 return flow_dv_convert_modify_action(&item, field, NULL, resource,
802 MLX5_MODIFICATION_TYPE_SET, error);
806 * Convert modify-header set TTL action to DV specification.
808 * @param[in,out] resource
809 * Pointer to the modify-header resource.
811 * Pointer to action specification.
813 * Pointer to rte_flow_item objects list.
815 * Pointer to flow attributes structure.
816 * @param[in] dev_flow
817 * Pointer to the sub flow.
818 * @param[in] tunnel_decap
819 * Whether action is after tunnel decapsulation.
821 * Pointer to the error structure.
824 * 0 on success, a negative errno value otherwise and rte_errno is set.
827 flow_dv_convert_action_modify_ttl
828 (struct mlx5_flow_dv_modify_hdr_resource *resource,
829 const struct rte_flow_action *action,
830 const struct rte_flow_item *items,
831 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
832 bool tunnel_decap, struct rte_flow_error *error)
834 const struct rte_flow_action_set_ttl *conf =
835 (const struct rte_flow_action_set_ttl *)(action->conf);
836 struct rte_flow_item item;
837 struct rte_flow_item_ipv4 ipv4;
838 struct rte_flow_item_ipv4 ipv4_mask;
839 struct rte_flow_item_ipv6 ipv6;
840 struct rte_flow_item_ipv6 ipv6_mask;
841 struct field_modify_info *field;
844 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
846 memset(&ipv4, 0, sizeof(ipv4));
847 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
848 ipv4.hdr.time_to_live = conf->ttl_value;
849 ipv4_mask.hdr.time_to_live = 0xFF;
850 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
852 item.mask = &ipv4_mask;
855 MLX5_ASSERT(attr->ipv6);
856 memset(&ipv6, 0, sizeof(ipv6));
857 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
858 ipv6.hdr.hop_limits = conf->ttl_value;
859 ipv6_mask.hdr.hop_limits = 0xFF;
860 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
862 item.mask = &ipv6_mask;
865 return flow_dv_convert_modify_action(&item, field, NULL, resource,
866 MLX5_MODIFICATION_TYPE_SET, error);
870 * Convert modify-header decrement TTL action to DV specification.
872 * @param[in,out] resource
873 * Pointer to the modify-header resource.
875 * Pointer to action specification.
877 * Pointer to rte_flow_item objects list.
879 * Pointer to flow attributes structure.
880 * @param[in] dev_flow
881 * Pointer to the sub flow.
882 * @param[in] tunnel_decap
883 * Whether action is after tunnel decapsulation.
885 * Pointer to the error structure.
888 * 0 on success, a negative errno value otherwise and rte_errno is set.
891 flow_dv_convert_action_modify_dec_ttl
892 (struct mlx5_flow_dv_modify_hdr_resource *resource,
893 const struct rte_flow_item *items,
894 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
895 bool tunnel_decap, struct rte_flow_error *error)
897 struct rte_flow_item item;
898 struct rte_flow_item_ipv4 ipv4;
899 struct rte_flow_item_ipv4 ipv4_mask;
900 struct rte_flow_item_ipv6 ipv6;
901 struct rte_flow_item_ipv6 ipv6_mask;
902 struct field_modify_info *field;
905 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
907 memset(&ipv4, 0, sizeof(ipv4));
908 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
909 ipv4.hdr.time_to_live = 0xFF;
910 ipv4_mask.hdr.time_to_live = 0xFF;
911 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
913 item.mask = &ipv4_mask;
916 MLX5_ASSERT(attr->ipv6);
917 memset(&ipv6, 0, sizeof(ipv6));
918 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
919 ipv6.hdr.hop_limits = 0xFF;
920 ipv6_mask.hdr.hop_limits = 0xFF;
921 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
923 item.mask = &ipv6_mask;
926 return flow_dv_convert_modify_action(&item, field, NULL, resource,
927 MLX5_MODIFICATION_TYPE_ADD, error);
931 * Convert modify-header increment/decrement TCP Sequence number
932 * to DV specification.
934 * @param[in,out] resource
935 * Pointer to the modify-header resource.
937 * Pointer to action specification.
939 * Pointer to the error structure.
942 * 0 on success, a negative errno value otherwise and rte_errno is set.
945 flow_dv_convert_action_modify_tcp_seq
946 (struct mlx5_flow_dv_modify_hdr_resource *resource,
947 const struct rte_flow_action *action,
948 struct rte_flow_error *error)
950 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
951 uint64_t value = rte_be_to_cpu_32(*conf);
952 struct rte_flow_item item;
953 struct rte_flow_item_tcp tcp;
954 struct rte_flow_item_tcp tcp_mask;
956 memset(&tcp, 0, sizeof(tcp));
957 memset(&tcp_mask, 0, sizeof(tcp_mask));
958 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
960 * The HW has no decrement operation, only increment operation.
961 * To simulate decrement X from Y using increment operation
962 * we need to add UINT32_MAX X times to Y.
963 * Each adding of UINT32_MAX decrements Y by 1.
966 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
967 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
968 item.type = RTE_FLOW_ITEM_TYPE_TCP;
970 item.mask = &tcp_mask;
971 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
972 MLX5_MODIFICATION_TYPE_ADD, error);
976 * Convert modify-header increment/decrement TCP Acknowledgment number
977 * to DV specification.
979 * @param[in,out] resource
980 * Pointer to the modify-header resource.
982 * Pointer to action specification.
984 * Pointer to the error structure.
987 * 0 on success, a negative errno value otherwise and rte_errno is set.
990 flow_dv_convert_action_modify_tcp_ack
991 (struct mlx5_flow_dv_modify_hdr_resource *resource,
992 const struct rte_flow_action *action,
993 struct rte_flow_error *error)
995 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
996 uint64_t value = rte_be_to_cpu_32(*conf);
997 struct rte_flow_item item;
998 struct rte_flow_item_tcp tcp;
999 struct rte_flow_item_tcp tcp_mask;
1001 memset(&tcp, 0, sizeof(tcp));
1002 memset(&tcp_mask, 0, sizeof(tcp_mask));
1003 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
1005 * The HW has no decrement operation, only increment operation.
1006 * To simulate decrement X from Y using increment operation
1007 * we need to add UINT32_MAX X times to Y.
1008 * Each adding of UINT32_MAX decrements Y by 1.
1010 value *= UINT32_MAX;
1011 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
1012 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
1013 item.type = RTE_FLOW_ITEM_TYPE_TCP;
1015 item.mask = &tcp_mask;
1016 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
1017 MLX5_MODIFICATION_TYPE_ADD, error);
1020 static enum mlx5_modification_field reg_to_field[] = {
1021 [REG_NON] = MLX5_MODI_OUT_NONE,
1022 [REG_A] = MLX5_MODI_META_DATA_REG_A,
1023 [REG_B] = MLX5_MODI_META_DATA_REG_B,
1024 [REG_C_0] = MLX5_MODI_META_REG_C_0,
1025 [REG_C_1] = MLX5_MODI_META_REG_C_1,
1026 [REG_C_2] = MLX5_MODI_META_REG_C_2,
1027 [REG_C_3] = MLX5_MODI_META_REG_C_3,
1028 [REG_C_4] = MLX5_MODI_META_REG_C_4,
1029 [REG_C_5] = MLX5_MODI_META_REG_C_5,
1030 [REG_C_6] = MLX5_MODI_META_REG_C_6,
1031 [REG_C_7] = MLX5_MODI_META_REG_C_7,
1035 * Convert register set to DV specification.
1037 * @param[in,out] resource
1038 * Pointer to the modify-header resource.
1040 * Pointer to action specification.
1042 * Pointer to the error structure.
1045 * 0 on success, a negative errno value otherwise and rte_errno is set.
1048 flow_dv_convert_action_set_reg
1049 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1050 const struct rte_flow_action *action,
1051 struct rte_flow_error *error)
1053 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
1054 struct mlx5_modification_cmd *actions = resource->actions;
1055 uint32_t i = resource->actions_num;
1057 if (i >= MLX5_MAX_MODIFY_NUM)
1058 return rte_flow_error_set(error, EINVAL,
1059 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1060 "too many items to modify");
1061 MLX5_ASSERT(conf->id != REG_NON);
1062 MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
1063 actions[i] = (struct mlx5_modification_cmd) {
1064 .action_type = MLX5_MODIFICATION_TYPE_SET,
1065 .field = reg_to_field[conf->id],
1066 .offset = conf->offset,
1067 .length = conf->length,
1069 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1070 actions[i].data1 = rte_cpu_to_be_32(conf->data);
1072 resource->actions_num = i;
1077 * Convert SET_TAG action to DV specification.
1080 * Pointer to the rte_eth_dev structure.
1081 * @param[in,out] resource
1082 * Pointer to the modify-header resource.
1084 * Pointer to action specification.
1086 * Pointer to the error structure.
1089 * 0 on success, a negative errno value otherwise and rte_errno is set.
1092 flow_dv_convert_action_set_tag
1093 (struct rte_eth_dev *dev,
1094 struct mlx5_flow_dv_modify_hdr_resource *resource,
1095 const struct rte_flow_action_set_tag *conf,
1096 struct rte_flow_error *error)
1098 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1099 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1100 struct rte_flow_item item = {
1104 struct field_modify_info reg_c_x[] = {
1107 enum mlx5_modification_field reg_type;
1110 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1113 MLX5_ASSERT(ret != REG_NON);
1114 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1115 reg_type = reg_to_field[ret];
1116 MLX5_ASSERT(reg_type > 0);
1117 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1118 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1119 MLX5_MODIFICATION_TYPE_SET, error);
1123 * Convert internal COPY_REG action to DV specification.
1126 * Pointer to the rte_eth_dev structure.
1127 * @param[in,out] res
1128 * Pointer to the modify-header resource.
1130 * Pointer to action specification.
1132 * Pointer to the error structure.
1135 * 0 on success, a negative errno value otherwise and rte_errno is set.
1138 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1139 struct mlx5_flow_dv_modify_hdr_resource *res,
1140 const struct rte_flow_action *action,
1141 struct rte_flow_error *error)
1143 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1144 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1145 struct rte_flow_item item = {
1149 struct field_modify_info reg_src[] = {
1150 {4, 0, reg_to_field[conf->src]},
1153 struct field_modify_info reg_dst = {
1155 .id = reg_to_field[conf->dst],
1157 /* Adjust reg_c[0] usage according to reported mask. */
1158 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1159 struct mlx5_priv *priv = dev->data->dev_private;
1160 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1162 MLX5_ASSERT(reg_c0);
1163 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1164 if (conf->dst == REG_C_0) {
1165 /* Copy to reg_c[0], within mask only. */
1166 reg_dst.offset = rte_bsf32(reg_c0);
1167 mask = rte_cpu_to_be_32(reg_c0 >> reg_dst.offset);
1170 mask = rte_cpu_to_be_32(reg_c0);
1173 return flow_dv_convert_modify_action(&item,
1174 reg_src, ®_dst, res,
1175 MLX5_MODIFICATION_TYPE_COPY,
1180 * Convert MARK action to DV specification. This routine is used
1181 * in extensive metadata only and requires metadata register to be
1182 * handled. In legacy mode hardware tag resource is engaged.
1185 * Pointer to the rte_eth_dev structure.
1187 * Pointer to MARK action specification.
1188 * @param[in,out] resource
1189 * Pointer to the modify-header resource.
1191 * Pointer to the error structure.
1194 * 0 on success, a negative errno value otherwise and rte_errno is set.
1197 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1198 const struct rte_flow_action_mark *conf,
1199 struct mlx5_flow_dv_modify_hdr_resource *resource,
1200 struct rte_flow_error *error)
1202 struct mlx5_priv *priv = dev->data->dev_private;
1203 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1204 priv->sh->dv_mark_mask);
1205 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1206 struct rte_flow_item item = {
1210 struct field_modify_info reg_c_x[] = {
1216 return rte_flow_error_set(error, EINVAL,
1217 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1218 NULL, "zero mark action mask");
1219 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1222 MLX5_ASSERT(reg > 0);
1223 if (reg == REG_C_0) {
1224 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1225 uint32_t shl_c0 = rte_bsf32(msk_c0);
1227 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1228 mask = rte_cpu_to_be_32(mask) & msk_c0;
1229 mask = rte_cpu_to_be_32(mask << shl_c0);
1231 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1232 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1233 MLX5_MODIFICATION_TYPE_SET, error);
1237 * Get metadata register index for specified steering domain.
1240 * Pointer to the rte_eth_dev structure.
1242 * Attributes of flow to determine steering domain.
1244 * Pointer to the error structure.
1247 * positive index on success, a negative errno value otherwise
1248 * and rte_errno is set.
1250 static enum modify_reg
1251 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1252 const struct rte_flow_attr *attr,
1253 struct rte_flow_error *error)
1256 mlx5_flow_get_reg_id(dev, attr->transfer ?
1260 MLX5_METADATA_RX, 0, error);
1262 return rte_flow_error_set(error,
1263 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1264 NULL, "unavailable "
1265 "metadata register");
1270 * Convert SET_META action to DV specification.
1273 * Pointer to the rte_eth_dev structure.
1274 * @param[in,out] resource
1275 * Pointer to the modify-header resource.
1277 * Attributes of flow that includes this item.
1279 * Pointer to action specification.
1281 * Pointer to the error structure.
1284 * 0 on success, a negative errno value otherwise and rte_errno is set.
1287 flow_dv_convert_action_set_meta
1288 (struct rte_eth_dev *dev,
1289 struct mlx5_flow_dv_modify_hdr_resource *resource,
1290 const struct rte_flow_attr *attr,
1291 const struct rte_flow_action_set_meta *conf,
1292 struct rte_flow_error *error)
1294 uint32_t mask = rte_cpu_to_be_32(conf->mask);
1295 uint32_t data = rte_cpu_to_be_32(conf->data) & mask;
1296 struct rte_flow_item item = {
1300 struct field_modify_info reg_c_x[] = {
1303 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1307 MLX5_ASSERT(reg != REG_NON);
1308 if (reg == REG_C_0) {
1309 struct mlx5_priv *priv = dev->data->dev_private;
1310 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1311 uint32_t shl_c0 = rte_bsf32(msk_c0);
1313 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1314 mask = rte_cpu_to_be_32(mask) & msk_c0;
1315 mask = rte_cpu_to_be_32(mask << shl_c0);
1317 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1318 /* The routine expects parameters in memory as big-endian ones. */
1319 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1320 MLX5_MODIFICATION_TYPE_SET, error);
1324 * Convert modify-header set IPv4 DSCP action to DV specification.
1326 * @param[in,out] resource
1327 * Pointer to the modify-header resource.
1329 * Pointer to action specification.
1331 * Pointer to the error structure.
1334 * 0 on success, a negative errno value otherwise and rte_errno is set.
1337 flow_dv_convert_action_modify_ipv4_dscp
1338 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1339 const struct rte_flow_action *action,
1340 struct rte_flow_error *error)
1342 const struct rte_flow_action_set_dscp *conf =
1343 (const struct rte_flow_action_set_dscp *)(action->conf);
1344 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1345 struct rte_flow_item_ipv4 ipv4;
1346 struct rte_flow_item_ipv4 ipv4_mask;
1348 memset(&ipv4, 0, sizeof(ipv4));
1349 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1350 ipv4.hdr.type_of_service = conf->dscp;
1351 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1353 item.mask = &ipv4_mask;
1354 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1355 MLX5_MODIFICATION_TYPE_SET, error);
1359 * Convert modify-header set IPv6 DSCP action to DV specification.
1361 * @param[in,out] resource
1362 * Pointer to the modify-header resource.
1364 * Pointer to action specification.
1366 * Pointer to the error structure.
1369 * 0 on success, a negative errno value otherwise and rte_errno is set.
1372 flow_dv_convert_action_modify_ipv6_dscp
1373 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1374 const struct rte_flow_action *action,
1375 struct rte_flow_error *error)
1377 const struct rte_flow_action_set_dscp *conf =
1378 (const struct rte_flow_action_set_dscp *)(action->conf);
1379 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1380 struct rte_flow_item_ipv6 ipv6;
1381 struct rte_flow_item_ipv6 ipv6_mask;
1383 memset(&ipv6, 0, sizeof(ipv6));
1384 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1386 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1387 * rdma-core only accept the DSCP bits byte aligned start from
1388 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1389 * bits in IPv6 case as rdma-core requires byte aligned value.
1391 ipv6.hdr.vtc_flow = conf->dscp;
1392 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1394 item.mask = &ipv6_mask;
1395 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1396 MLX5_MODIFICATION_TYPE_SET, error);
1400 mlx5_flow_item_field_width(struct rte_eth_dev *dev,
1401 enum rte_flow_field_id field, int inherit,
1402 const struct rte_flow_attr *attr,
1403 struct rte_flow_error *error)
1405 struct mlx5_priv *priv = dev->data->dev_private;
1408 case RTE_FLOW_FIELD_START:
1410 case RTE_FLOW_FIELD_MAC_DST:
1411 case RTE_FLOW_FIELD_MAC_SRC:
1413 case RTE_FLOW_FIELD_VLAN_TYPE:
1415 case RTE_FLOW_FIELD_VLAN_ID:
1417 case RTE_FLOW_FIELD_MAC_TYPE:
1419 case RTE_FLOW_FIELD_IPV4_DSCP:
1421 case RTE_FLOW_FIELD_IPV4_TTL:
1423 case RTE_FLOW_FIELD_IPV4_SRC:
1424 case RTE_FLOW_FIELD_IPV4_DST:
1426 case RTE_FLOW_FIELD_IPV6_DSCP:
1428 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1430 case RTE_FLOW_FIELD_IPV6_SRC:
1431 case RTE_FLOW_FIELD_IPV6_DST:
1433 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1434 case RTE_FLOW_FIELD_TCP_PORT_DST:
1436 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1437 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1439 case RTE_FLOW_FIELD_TCP_FLAGS:
1441 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1442 case RTE_FLOW_FIELD_UDP_PORT_DST:
1444 case RTE_FLOW_FIELD_VXLAN_VNI:
1445 case RTE_FLOW_FIELD_GENEVE_VNI:
1447 case RTE_FLOW_FIELD_GTP_TEID:
1448 case RTE_FLOW_FIELD_TAG:
1450 case RTE_FLOW_FIELD_MARK:
1451 return __builtin_popcount(priv->sh->dv_mark_mask);
1452 case RTE_FLOW_FIELD_META:
1453 return (flow_dv_get_metadata_reg(dev, attr, error) == REG_C_0) ?
1454 __builtin_popcount(priv->sh->dv_meta_mask) : 32;
1455 case RTE_FLOW_FIELD_POINTER:
1456 case RTE_FLOW_FIELD_VALUE:
1457 return inherit < 0 ? 0 : inherit;
1465 mlx5_flow_field_id_to_modify_info
1466 (const struct rte_flow_action_modify_data *data,
1467 struct field_modify_info *info, uint32_t *mask,
1468 uint32_t width, uint32_t *shift, struct rte_eth_dev *dev,
1469 const struct rte_flow_attr *attr, struct rte_flow_error *error)
1471 struct mlx5_priv *priv = dev->data->dev_private;
1475 switch (data->field) {
1476 case RTE_FLOW_FIELD_START:
1477 /* not supported yet */
1480 case RTE_FLOW_FIELD_MAC_DST:
1481 off = data->offset > 16 ? data->offset - 16 : 0;
1483 if (data->offset < 16) {
1484 info[idx] = (struct field_modify_info){2, 4,
1485 MLX5_MODI_OUT_DMAC_15_0};
1487 mask[1] = rte_cpu_to_be_16(0xffff >>
1491 mask[1] = RTE_BE16(0xffff);
1498 info[idx] = (struct field_modify_info){4, 0,
1499 MLX5_MODI_OUT_DMAC_47_16};
1500 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1501 (32 - width)) << off);
1503 if (data->offset < 16)
1504 info[idx++] = (struct field_modify_info){2, 0,
1505 MLX5_MODI_OUT_DMAC_15_0};
1506 info[idx] = (struct field_modify_info){4, 0,
1507 MLX5_MODI_OUT_DMAC_47_16};
1510 case RTE_FLOW_FIELD_MAC_SRC:
1511 off = data->offset > 16 ? data->offset - 16 : 0;
1513 if (data->offset < 16) {
1514 info[idx] = (struct field_modify_info){2, 4,
1515 MLX5_MODI_OUT_SMAC_15_0};
1517 mask[1] = rte_cpu_to_be_16(0xffff >>
1521 mask[1] = RTE_BE16(0xffff);
1528 info[idx] = (struct field_modify_info){4, 0,
1529 MLX5_MODI_OUT_SMAC_47_16};
1530 mask[0] = rte_cpu_to_be_32((0xffffffff >>
1531 (32 - width)) << off);
1533 if (data->offset < 16)
1534 info[idx++] = (struct field_modify_info){2, 0,
1535 MLX5_MODI_OUT_SMAC_15_0};
1536 info[idx] = (struct field_modify_info){4, 0,
1537 MLX5_MODI_OUT_SMAC_47_16};
1540 case RTE_FLOW_FIELD_VLAN_TYPE:
1541 /* not supported yet */
1543 case RTE_FLOW_FIELD_VLAN_ID:
1544 info[idx] = (struct field_modify_info){2, 0,
1545 MLX5_MODI_OUT_FIRST_VID};
1547 mask[idx] = rte_cpu_to_be_16(0x0fff >> (12 - width));
1549 case RTE_FLOW_FIELD_MAC_TYPE:
1550 info[idx] = (struct field_modify_info){2, 0,
1551 MLX5_MODI_OUT_ETHERTYPE};
1553 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1555 case RTE_FLOW_FIELD_IPV4_DSCP:
1556 info[idx] = (struct field_modify_info){1, 0,
1557 MLX5_MODI_OUT_IP_DSCP};
1559 mask[idx] = 0x3f >> (6 - width);
1561 case RTE_FLOW_FIELD_IPV4_TTL:
1562 info[idx] = (struct field_modify_info){1, 0,
1563 MLX5_MODI_OUT_IPV4_TTL};
1565 mask[idx] = 0xff >> (8 - width);
1567 case RTE_FLOW_FIELD_IPV4_SRC:
1568 info[idx] = (struct field_modify_info){4, 0,
1569 MLX5_MODI_OUT_SIPV4};
1571 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1574 case RTE_FLOW_FIELD_IPV4_DST:
1575 info[idx] = (struct field_modify_info){4, 0,
1576 MLX5_MODI_OUT_DIPV4};
1578 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1581 case RTE_FLOW_FIELD_IPV6_DSCP:
1582 info[idx] = (struct field_modify_info){1, 0,
1583 MLX5_MODI_OUT_IP_DSCP};
1585 mask[idx] = 0x3f >> (6 - width);
1587 case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1588 info[idx] = (struct field_modify_info){1, 0,
1589 MLX5_MODI_OUT_IPV6_HOPLIMIT};
1591 mask[idx] = 0xff >> (8 - width);
1593 case RTE_FLOW_FIELD_IPV6_SRC:
1595 if (data->offset < 32) {
1596 info[idx] = (struct field_modify_info){4, 12,
1597 MLX5_MODI_OUT_SIPV6_31_0};
1600 rte_cpu_to_be_32(0xffffffff >>
1604 mask[3] = RTE_BE32(0xffffffff);
1611 if (data->offset < 64) {
1612 info[idx] = (struct field_modify_info){4, 8,
1613 MLX5_MODI_OUT_SIPV6_63_32};
1616 rte_cpu_to_be_32(0xffffffff >>
1620 mask[2] = RTE_BE32(0xffffffff);
1627 if (data->offset < 96) {
1628 info[idx] = (struct field_modify_info){4, 4,
1629 MLX5_MODI_OUT_SIPV6_95_64};
1632 rte_cpu_to_be_32(0xffffffff >>
1636 mask[1] = RTE_BE32(0xffffffff);
1643 info[idx] = (struct field_modify_info){4, 0,
1644 MLX5_MODI_OUT_SIPV6_127_96};
1645 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1647 if (data->offset < 32)
1648 info[idx++] = (struct field_modify_info){4, 0,
1649 MLX5_MODI_OUT_SIPV6_31_0};
1650 if (data->offset < 64)
1651 info[idx++] = (struct field_modify_info){4, 0,
1652 MLX5_MODI_OUT_SIPV6_63_32};
1653 if (data->offset < 96)
1654 info[idx++] = (struct field_modify_info){4, 0,
1655 MLX5_MODI_OUT_SIPV6_95_64};
1656 if (data->offset < 128)
1657 info[idx++] = (struct field_modify_info){4, 0,
1658 MLX5_MODI_OUT_SIPV6_127_96};
1661 case RTE_FLOW_FIELD_IPV6_DST:
1663 if (data->offset < 32) {
1664 info[idx] = (struct field_modify_info){4, 12,
1665 MLX5_MODI_OUT_DIPV6_31_0};
1668 rte_cpu_to_be_32(0xffffffff >>
1672 mask[3] = RTE_BE32(0xffffffff);
1679 if (data->offset < 64) {
1680 info[idx] = (struct field_modify_info){4, 8,
1681 MLX5_MODI_OUT_DIPV6_63_32};
1684 rte_cpu_to_be_32(0xffffffff >>
1688 mask[2] = RTE_BE32(0xffffffff);
1695 if (data->offset < 96) {
1696 info[idx] = (struct field_modify_info){4, 4,
1697 MLX5_MODI_OUT_DIPV6_95_64};
1700 rte_cpu_to_be_32(0xffffffff >>
1704 mask[1] = RTE_BE32(0xffffffff);
1711 info[idx] = (struct field_modify_info){4, 0,
1712 MLX5_MODI_OUT_DIPV6_127_96};
1713 mask[0] = rte_cpu_to_be_32(0xffffffff >> (32 - width));
1715 if (data->offset < 32)
1716 info[idx++] = (struct field_modify_info){4, 0,
1717 MLX5_MODI_OUT_DIPV6_31_0};
1718 if (data->offset < 64)
1719 info[idx++] = (struct field_modify_info){4, 0,
1720 MLX5_MODI_OUT_DIPV6_63_32};
1721 if (data->offset < 96)
1722 info[idx++] = (struct field_modify_info){4, 0,
1723 MLX5_MODI_OUT_DIPV6_95_64};
1724 if (data->offset < 128)
1725 info[idx++] = (struct field_modify_info){4, 0,
1726 MLX5_MODI_OUT_DIPV6_127_96};
1729 case RTE_FLOW_FIELD_TCP_PORT_SRC:
1730 info[idx] = (struct field_modify_info){2, 0,
1731 MLX5_MODI_OUT_TCP_SPORT};
1733 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1735 case RTE_FLOW_FIELD_TCP_PORT_DST:
1736 info[idx] = (struct field_modify_info){2, 0,
1737 MLX5_MODI_OUT_TCP_DPORT};
1739 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1741 case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1742 info[idx] = (struct field_modify_info){4, 0,
1743 MLX5_MODI_OUT_TCP_SEQ_NUM};
1745 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1748 case RTE_FLOW_FIELD_TCP_ACK_NUM:
1749 info[idx] = (struct field_modify_info){4, 0,
1750 MLX5_MODI_OUT_TCP_ACK_NUM};
1752 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1755 case RTE_FLOW_FIELD_TCP_FLAGS:
1756 info[idx] = (struct field_modify_info){2, 0,
1757 MLX5_MODI_OUT_TCP_FLAGS};
1759 mask[idx] = rte_cpu_to_be_16(0x1ff >> (9 - width));
1761 case RTE_FLOW_FIELD_UDP_PORT_SRC:
1762 info[idx] = (struct field_modify_info){2, 0,
1763 MLX5_MODI_OUT_UDP_SPORT};
1765 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1767 case RTE_FLOW_FIELD_UDP_PORT_DST:
1768 info[idx] = (struct field_modify_info){2, 0,
1769 MLX5_MODI_OUT_UDP_DPORT};
1771 mask[idx] = rte_cpu_to_be_16(0xffff >> (16 - width));
1773 case RTE_FLOW_FIELD_VXLAN_VNI:
1774 /* not supported yet */
1776 case RTE_FLOW_FIELD_GENEVE_VNI:
1777 /* not supported yet*/
1779 case RTE_FLOW_FIELD_GTP_TEID:
1780 info[idx] = (struct field_modify_info){4, 0,
1781 MLX5_MODI_GTP_TEID};
1783 mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1786 case RTE_FLOW_FIELD_TAG:
1788 int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1789 data->level, error);
1792 MLX5_ASSERT(reg != REG_NON);
1793 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1794 info[idx] = (struct field_modify_info){4, 0,
1798 rte_cpu_to_be_32(0xffffffff >>
1802 case RTE_FLOW_FIELD_MARK:
1804 uint32_t mark_mask = priv->sh->dv_mark_mask;
1805 uint32_t mark_count = __builtin_popcount(mark_mask);
1806 int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1810 MLX5_ASSERT(reg != REG_NON);
1811 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1812 info[idx] = (struct field_modify_info){4, 0,
1815 mask[idx] = rte_cpu_to_be_32((mark_mask >>
1816 (mark_count - width)) & mark_mask);
1819 case RTE_FLOW_FIELD_META:
1821 uint32_t meta_mask = priv->sh->dv_meta_mask;
1822 uint32_t meta_count = __builtin_popcount(meta_mask);
1824 rte_cpu_to_be_32(priv->sh->dv_regc0_mask);
1825 uint32_t shl_c0 = rte_bsf32(msk_c0);
1826 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1829 MLX5_ASSERT(reg != REG_NON);
1830 MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1833 info[idx] = (struct field_modify_info){4, 0,
1836 mask[idx] = rte_cpu_to_be_32((meta_mask >>
1837 (meta_count - width)) & meta_mask);
1840 case RTE_FLOW_FIELD_POINTER:
1841 case RTE_FLOW_FIELD_VALUE:
1849 * Convert modify_field action to DV specification.
1852 * Pointer to the rte_eth_dev structure.
1853 * @param[in,out] resource
1854 * Pointer to the modify-header resource.
1856 * Pointer to action specification.
1858 * Attributes of flow that includes this item.
1860 * Pointer to the error structure.
1863 * 0 on success, a negative errno value otherwise and rte_errno is set.
1866 flow_dv_convert_action_modify_field
1867 (struct rte_eth_dev *dev,
1868 struct mlx5_flow_dv_modify_hdr_resource *resource,
1869 const struct rte_flow_action *action,
1870 const struct rte_flow_attr *attr,
1871 struct rte_flow_error *error)
1873 const struct rte_flow_action_modify_field *conf =
1874 (const struct rte_flow_action_modify_field *)(action->conf);
1875 struct rte_flow_item item = {
1879 struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1881 struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1883 uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1887 if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1888 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1889 type = MLX5_MODIFICATION_TYPE_SET;
1890 /** For SET fill the destination field (field) first. */
1891 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1892 conf->width, &shift, dev,
1894 item.spec = conf->src.field == RTE_FLOW_FIELD_POINTER ?
1895 (void *)(uintptr_t)conf->src.pvalue :
1896 (void *)(uintptr_t)&conf->src.value;
1898 type = MLX5_MODIFICATION_TYPE_COPY;
1899 /** For COPY fill the destination field (dcopy) without mask. */
1900 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1901 conf->width, &shift, dev,
1903 /** Then construct the source field (field) with mask. */
1904 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1905 conf->width, &shift,
1909 return flow_dv_convert_modify_action(&item,
1910 field, dcopy, resource, type, error);
1914 * Validate MARK item.
1917 * Pointer to the rte_eth_dev structure.
1919 * Item specification.
1921 * Attributes of flow that includes this item.
1923 * Pointer to error structure.
1926 * 0 on success, a negative errno value otherwise and rte_errno is set.
1929 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1930 const struct rte_flow_item *item,
1931 const struct rte_flow_attr *attr __rte_unused,
1932 struct rte_flow_error *error)
1934 struct mlx5_priv *priv = dev->data->dev_private;
1935 struct mlx5_dev_config *config = &priv->config;
1936 const struct rte_flow_item_mark *spec = item->spec;
1937 const struct rte_flow_item_mark *mask = item->mask;
1938 const struct rte_flow_item_mark nic_mask = {
1939 .id = priv->sh->dv_mark_mask,
1943 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1944 return rte_flow_error_set(error, ENOTSUP,
1945 RTE_FLOW_ERROR_TYPE_ITEM, item,
1946 "extended metadata feature"
1948 if (!mlx5_flow_ext_mreg_supported(dev))
1949 return rte_flow_error_set(error, ENOTSUP,
1950 RTE_FLOW_ERROR_TYPE_ITEM, item,
1951 "extended metadata register"
1952 " isn't supported");
1954 return rte_flow_error_set(error, ENOTSUP,
1955 RTE_FLOW_ERROR_TYPE_ITEM, item,
1956 "extended metadata register"
1957 " isn't available");
1958 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1962 return rte_flow_error_set(error, EINVAL,
1963 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1965 "data cannot be empty");
1966 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1970 "mark id exceeds the limit");
1974 return rte_flow_error_set(error, EINVAL,
1975 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1976 "mask cannot be zero");
1978 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1979 (const uint8_t *)&nic_mask,
1980 sizeof(struct rte_flow_item_mark),
1981 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1988 * Validate META item.
1991 * Pointer to the rte_eth_dev structure.
1993 * Item specification.
1995 * Attributes of flow that includes this item.
1997 * Pointer to error structure.
2000 * 0 on success, a negative errno value otherwise and rte_errno is set.
2003 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
2004 const struct rte_flow_item *item,
2005 const struct rte_flow_attr *attr,
2006 struct rte_flow_error *error)
2008 struct mlx5_priv *priv = dev->data->dev_private;
2009 struct mlx5_dev_config *config = &priv->config;
2010 const struct rte_flow_item_meta *spec = item->spec;
2011 const struct rte_flow_item_meta *mask = item->mask;
2012 struct rte_flow_item_meta nic_mask = {
2019 return rte_flow_error_set(error, EINVAL,
2020 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2022 "data cannot be empty");
2023 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
2024 if (!mlx5_flow_ext_mreg_supported(dev))
2025 return rte_flow_error_set(error, ENOTSUP,
2026 RTE_FLOW_ERROR_TYPE_ITEM, item,
2027 "extended metadata register"
2028 " isn't supported");
2029 reg = flow_dv_get_metadata_reg(dev, attr, error);
2033 return rte_flow_error_set(error, ENOTSUP,
2034 RTE_FLOW_ERROR_TYPE_ITEM, item,
2035 "unavalable extended metadata register");
2037 return rte_flow_error_set(error, ENOTSUP,
2038 RTE_FLOW_ERROR_TYPE_ITEM, item,
2042 nic_mask.data = priv->sh->dv_meta_mask;
2045 return rte_flow_error_set(error, ENOTSUP,
2046 RTE_FLOW_ERROR_TYPE_ITEM, item,
2047 "extended metadata feature "
2048 "should be enabled when "
2049 "meta item is requested "
2050 "with e-switch mode ");
2052 return rte_flow_error_set(error, ENOTSUP,
2053 RTE_FLOW_ERROR_TYPE_ITEM, item,
2054 "match on metadata for ingress "
2055 "is not supported in legacy "
2059 mask = &rte_flow_item_meta_mask;
2061 return rte_flow_error_set(error, EINVAL,
2062 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2063 "mask cannot be zero");
2065 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2066 (const uint8_t *)&nic_mask,
2067 sizeof(struct rte_flow_item_meta),
2068 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2073 * Validate TAG item.
2076 * Pointer to the rte_eth_dev structure.
2078 * Item specification.
2080 * Attributes of flow that includes this item.
2082 * Pointer to error structure.
2085 * 0 on success, a negative errno value otherwise and rte_errno is set.
2088 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
2089 const struct rte_flow_item *item,
2090 const struct rte_flow_attr *attr __rte_unused,
2091 struct rte_flow_error *error)
2093 const struct rte_flow_item_tag *spec = item->spec;
2094 const struct rte_flow_item_tag *mask = item->mask;
2095 const struct rte_flow_item_tag nic_mask = {
2096 .data = RTE_BE32(UINT32_MAX),
2101 if (!mlx5_flow_ext_mreg_supported(dev))
2102 return rte_flow_error_set(error, ENOTSUP,
2103 RTE_FLOW_ERROR_TYPE_ITEM, item,
2104 "extensive metadata register"
2105 " isn't supported");
2107 return rte_flow_error_set(error, EINVAL,
2108 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
2110 "data cannot be empty");
2112 mask = &rte_flow_item_tag_mask;
2114 return rte_flow_error_set(error, EINVAL,
2115 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2116 "mask cannot be zero");
2118 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2119 (const uint8_t *)&nic_mask,
2120 sizeof(struct rte_flow_item_tag),
2121 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2124 if (mask->index != 0xff)
2125 return rte_flow_error_set(error, EINVAL,
2126 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2127 "partial mask for tag index"
2128 " is not supported");
2129 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2132 MLX5_ASSERT(ret != REG_NON);
2137 * Validate vport item.
2140 * Pointer to the rte_eth_dev structure.
2142 * Item specification.
2144 * Attributes of flow that includes this item.
2145 * @param[in] item_flags
2146 * Bit-fields that holds the items detected until now.
2148 * Pointer to error structure.
2151 * 0 on success, a negative errno value otherwise and rte_errno is set.
2154 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2155 const struct rte_flow_item *item,
2156 const struct rte_flow_attr *attr,
2157 uint64_t item_flags,
2158 struct rte_flow_error *error)
2160 const struct rte_flow_item_port_id *spec = item->spec;
2161 const struct rte_flow_item_port_id *mask = item->mask;
2162 const struct rte_flow_item_port_id switch_mask = {
2165 struct mlx5_priv *esw_priv;
2166 struct mlx5_priv *dev_priv;
2169 if (!attr->transfer)
2170 return rte_flow_error_set(error, EINVAL,
2171 RTE_FLOW_ERROR_TYPE_ITEM,
2173 "match on port id is valid only"
2174 " when transfer flag is enabled");
2175 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2176 return rte_flow_error_set(error, ENOTSUP,
2177 RTE_FLOW_ERROR_TYPE_ITEM, item,
2178 "multiple source ports are not"
2181 mask = &switch_mask;
2182 if (mask->id != 0xffffffff)
2183 return rte_flow_error_set(error, ENOTSUP,
2184 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2186 "no support for partial mask on"
2188 ret = mlx5_flow_item_acceptable
2189 (item, (const uint8_t *)mask,
2190 (const uint8_t *)&rte_flow_item_port_id_mask,
2191 sizeof(struct rte_flow_item_port_id),
2192 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2197 if (spec->id == MLX5_PORT_ESW_MGR)
2199 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2201 return rte_flow_error_set(error, rte_errno,
2202 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2203 "failed to obtain E-Switch info for"
2205 dev_priv = mlx5_dev_to_eswitch_info(dev);
2207 return rte_flow_error_set(error, rte_errno,
2208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2210 "failed to obtain E-Switch info");
2211 if (esw_priv->domain_id != dev_priv->domain_id)
2212 return rte_flow_error_set(error, EINVAL,
2213 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2214 "cannot match on a port from a"
2215 " different E-Switch");
2220 * Validate VLAN item.
2223 * Item specification.
2224 * @param[in] item_flags
2225 * Bit-fields that holds the items detected until now.
2227 * Ethernet device flow is being created on.
2229 * Pointer to error structure.
2232 * 0 on success, a negative errno value otherwise and rte_errno is set.
2235 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2236 uint64_t item_flags,
2237 struct rte_eth_dev *dev,
2238 struct rte_flow_error *error)
2240 const struct rte_flow_item_vlan *mask = item->mask;
2241 const struct rte_flow_item_vlan nic_mask = {
2242 .tci = RTE_BE16(UINT16_MAX),
2243 .inner_type = RTE_BE16(UINT16_MAX),
2246 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2248 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2249 MLX5_FLOW_LAYER_INNER_L4) :
2250 (MLX5_FLOW_LAYER_OUTER_L3 |
2251 MLX5_FLOW_LAYER_OUTER_L4);
2252 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2253 MLX5_FLOW_LAYER_OUTER_VLAN;
2255 if (item_flags & vlanm)
2256 return rte_flow_error_set(error, EINVAL,
2257 RTE_FLOW_ERROR_TYPE_ITEM, item,
2258 "multiple VLAN layers not supported");
2259 else if ((item_flags & l34m) != 0)
2260 return rte_flow_error_set(error, EINVAL,
2261 RTE_FLOW_ERROR_TYPE_ITEM, item,
2262 "VLAN cannot follow L3/L4 layer");
2264 mask = &rte_flow_item_vlan_mask;
2265 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2266 (const uint8_t *)&nic_mask,
2267 sizeof(struct rte_flow_item_vlan),
2268 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2271 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2272 struct mlx5_priv *priv = dev->data->dev_private;
2274 if (priv->vmwa_context) {
2276 * Non-NULL context means we have a virtual machine
2277 * and SR-IOV enabled, we have to create VLAN interface
2278 * to make hypervisor to setup E-Switch vport
2279 * context correctly. We avoid creating the multiple
2280 * VLAN interfaces, so we cannot support VLAN tag mask.
2282 return rte_flow_error_set(error, EINVAL,
2283 RTE_FLOW_ERROR_TYPE_ITEM,
2285 "VLAN tag mask is not"
2286 " supported in virtual"
2294 * GTP flags are contained in 1 byte of the format:
2295 * -------------------------------------------
2296 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
2297 * |-----------------------------------------|
2298 * | value | Version | PT | Res | E | S | PN |
2299 * -------------------------------------------
2301 * Matching is supported only for GTP flags E, S, PN.
2303 #define MLX5_GTP_FLAGS_MASK 0x07
2306 * Validate GTP item.
2309 * Pointer to the rte_eth_dev structure.
2311 * Item specification.
2312 * @param[in] item_flags
2313 * Bit-fields that holds the items detected until now.
2315 * Pointer to error structure.
2318 * 0 on success, a negative errno value otherwise and rte_errno is set.
2321 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2322 const struct rte_flow_item *item,
2323 uint64_t item_flags,
2324 struct rte_flow_error *error)
2326 struct mlx5_priv *priv = dev->data->dev_private;
2327 const struct rte_flow_item_gtp *spec = item->spec;
2328 const struct rte_flow_item_gtp *mask = item->mask;
2329 const struct rte_flow_item_gtp nic_mask = {
2330 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2332 .teid = RTE_BE32(0xffffffff),
2335 if (!priv->config.hca_attr.tunnel_stateless_gtp)
2336 return rte_flow_error_set(error, ENOTSUP,
2337 RTE_FLOW_ERROR_TYPE_ITEM, item,
2338 "GTP support is not enabled");
2339 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2340 return rte_flow_error_set(error, ENOTSUP,
2341 RTE_FLOW_ERROR_TYPE_ITEM, item,
2342 "multiple tunnel layers not"
2344 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2345 return rte_flow_error_set(error, EINVAL,
2346 RTE_FLOW_ERROR_TYPE_ITEM, item,
2347 "no outer UDP layer found");
2349 mask = &rte_flow_item_gtp_mask;
2350 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2351 return rte_flow_error_set(error, ENOTSUP,
2352 RTE_FLOW_ERROR_TYPE_ITEM, item,
2353 "Match is supported for GTP"
2355 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2356 (const uint8_t *)&nic_mask,
2357 sizeof(struct rte_flow_item_gtp),
2358 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2362 * Validate GTP PSC item.
2365 * Item specification.
2366 * @param[in] last_item
2367 * Previous validated item in the pattern items.
2368 * @param[in] gtp_item
2369 * Previous GTP item specification.
2371 * Pointer to flow attributes.
2373 * Pointer to error structure.
2376 * 0 on success, a negative errno value otherwise and rte_errno is set.
2379 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2381 const struct rte_flow_item *gtp_item,
2382 const struct rte_flow_attr *attr,
2383 struct rte_flow_error *error)
2385 const struct rte_flow_item_gtp *gtp_spec;
2386 const struct rte_flow_item_gtp *gtp_mask;
2387 const struct rte_flow_item_gtp_psc *mask;
2388 const struct rte_flow_item_gtp_psc nic_mask = {
2393 if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2394 return rte_flow_error_set
2395 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2396 "GTP PSC item must be preceded with GTP item");
2397 gtp_spec = gtp_item->spec;
2398 gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2399 /* GTP spec and E flag is requested to match zero. */
2401 (gtp_mask->v_pt_rsv_flags &
2402 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2403 return rte_flow_error_set
2404 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2405 "GTP E flag must be 1 to match GTP PSC");
2406 /* Check the flow is not created in group zero. */
2407 if (!attr->transfer && !attr->group)
2408 return rte_flow_error_set
2409 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2410 "GTP PSC is not supported for group 0");
2411 /* GTP spec is here and E flag is requested to match zero. */
2414 mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2415 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2416 (const uint8_t *)&nic_mask,
2417 sizeof(struct rte_flow_item_gtp_psc),
2418 MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2422 * Validate IPV4 item.
2423 * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2424 * add specific validation of fragment_offset field,
2427 * Item specification.
2428 * @param[in] item_flags
2429 * Bit-fields that holds the items detected until now.
2431 * Pointer to error structure.
2434 * 0 on success, a negative errno value otherwise and rte_errno is set.
2437 flow_dv_validate_item_ipv4(struct rte_eth_dev *dev,
2438 const struct rte_flow_item *item,
2439 uint64_t item_flags, uint64_t last_item,
2440 uint16_t ether_type, struct rte_flow_error *error)
2443 struct mlx5_priv *priv = dev->data->dev_private;
2444 const struct rte_flow_item_ipv4 *spec = item->spec;
2445 const struct rte_flow_item_ipv4 *last = item->last;
2446 const struct rte_flow_item_ipv4 *mask = item->mask;
2447 rte_be16_t fragment_offset_spec = 0;
2448 rte_be16_t fragment_offset_last = 0;
2449 struct rte_flow_item_ipv4 nic_ipv4_mask = {
2451 .src_addr = RTE_BE32(0xffffffff),
2452 .dst_addr = RTE_BE32(0xffffffff),
2453 .type_of_service = 0xff,
2454 .fragment_offset = RTE_BE16(0xffff),
2455 .next_proto_id = 0xff,
2456 .time_to_live = 0xff,
2460 if (mask && (mask->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK)) {
2461 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2462 bool ihl_cap = !tunnel ? priv->config.hca_attr.outer_ipv4_ihl :
2463 priv->config.hca_attr.inner_ipv4_ihl;
2465 return rte_flow_error_set(error, ENOTSUP,
2466 RTE_FLOW_ERROR_TYPE_ITEM,
2468 "IPV4 ihl offload not supported");
2469 nic_ipv4_mask.hdr.version_ihl = mask->hdr.version_ihl;
2471 ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2472 ether_type, &nic_ipv4_mask,
2473 MLX5_ITEM_RANGE_ACCEPTED, error);
2477 fragment_offset_spec = spec->hdr.fragment_offset &
2478 mask->hdr.fragment_offset;
2479 if (!fragment_offset_spec)
2482 * spec and mask are valid, enforce using full mask to make sure the
2483 * complete value is used correctly.
2485 if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2486 != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2487 return rte_flow_error_set(error, EINVAL,
2488 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2489 item, "must use full mask for"
2490 " fragment_offset");
2492 * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2493 * indicating this is 1st fragment of fragmented packet.
2494 * This is not yet supported in MLX5, return appropriate error message.
2496 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2497 return rte_flow_error_set(error, ENOTSUP,
2498 RTE_FLOW_ERROR_TYPE_ITEM, item,
2499 "match on first fragment not "
2501 if (fragment_offset_spec && !last)
2502 return rte_flow_error_set(error, ENOTSUP,
2503 RTE_FLOW_ERROR_TYPE_ITEM, item,
2504 "specified value not supported");
2505 /* spec and last are valid, validate the specified range. */
2506 fragment_offset_last = last->hdr.fragment_offset &
2507 mask->hdr.fragment_offset;
2509 * Match on fragment_offset spec 0x2001 and last 0x3fff
2510 * means MF is 1 and frag-offset is > 0.
2511 * This packet is fragment 2nd and onward, excluding last.
2512 * This is not yet supported in MLX5, return appropriate
2515 if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2516 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2517 return rte_flow_error_set(error, ENOTSUP,
2518 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519 last, "match on following "
2520 "fragments not supported");
2522 * Match on fragment_offset spec 0x0001 and last 0x1fff
2523 * means MF is 0 and frag-offset is > 0.
2524 * This packet is last fragment of fragmented packet.
2525 * This is not yet supported in MLX5, return appropriate
2528 if (fragment_offset_spec == RTE_BE16(1) &&
2529 fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2530 return rte_flow_error_set(error, ENOTSUP,
2531 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532 last, "match on last "
2533 "fragment not supported");
2535 * Match on fragment_offset spec 0x0001 and last 0x3fff
2536 * means MF and/or frag-offset is not 0.
2537 * This is a fragmented packet.
2538 * Other range values are invalid and rejected.
2540 if (!(fragment_offset_spec == RTE_BE16(1) &&
2541 fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2542 return rte_flow_error_set(error, ENOTSUP,
2543 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2544 "specified range not supported");
2549 * Validate IPV6 fragment extension item.
2552 * Item specification.
2553 * @param[in] item_flags
2554 * Bit-fields that holds the items detected until now.
2556 * Pointer to error structure.
2559 * 0 on success, a negative errno value otherwise and rte_errno is set.
2562 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2563 uint64_t item_flags,
2564 struct rte_flow_error *error)
2566 const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2567 const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2568 const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2569 rte_be16_t frag_data_spec = 0;
2570 rte_be16_t frag_data_last = 0;
2571 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2572 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2573 MLX5_FLOW_LAYER_OUTER_L4;
2575 struct rte_flow_item_ipv6_frag_ext nic_mask = {
2577 .next_header = 0xff,
2578 .frag_data = RTE_BE16(0xffff),
2582 if (item_flags & l4m)
2583 return rte_flow_error_set(error, EINVAL,
2584 RTE_FLOW_ERROR_TYPE_ITEM, item,
2585 "ipv6 fragment extension item cannot "
2587 if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2588 (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2589 return rte_flow_error_set(error, EINVAL,
2590 RTE_FLOW_ERROR_TYPE_ITEM, item,
2591 "ipv6 fragment extension item must "
2592 "follow ipv6 item");
2594 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2595 if (!frag_data_spec)
2598 * spec and mask are valid, enforce using full mask to make sure the
2599 * complete value is used correctly.
2601 if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2602 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2603 return rte_flow_error_set(error, EINVAL,
2604 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2605 item, "must use full mask for"
2608 * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2609 * This is 1st fragment of fragmented packet.
2611 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2612 return rte_flow_error_set(error, ENOTSUP,
2613 RTE_FLOW_ERROR_TYPE_ITEM, item,
2614 "match on first fragment not "
2616 if (frag_data_spec && !last)
2617 return rte_flow_error_set(error, EINVAL,
2618 RTE_FLOW_ERROR_TYPE_ITEM, item,
2619 "specified value not supported");
2620 ret = mlx5_flow_item_acceptable
2621 (item, (const uint8_t *)mask,
2622 (const uint8_t *)&nic_mask,
2623 sizeof(struct rte_flow_item_ipv6_frag_ext),
2624 MLX5_ITEM_RANGE_ACCEPTED, error);
2627 /* spec and last are valid, validate the specified range. */
2628 frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2630 * Match on frag_data spec 0x0009 and last 0xfff9
2631 * means M is 1 and frag-offset is > 0.
2632 * This packet is fragment 2nd and onward, excluding last.
2633 * This is not yet supported in MLX5, return appropriate
2636 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2637 RTE_IPV6_EHDR_MF_MASK) &&
2638 frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2639 return rte_flow_error_set(error, ENOTSUP,
2640 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2641 last, "match on following "
2642 "fragments not supported");
2644 * Match on frag_data spec 0x0008 and last 0xfff8
2645 * means M is 0 and frag-offset is > 0.
2646 * This packet is last fragment of fragmented packet.
2647 * This is not yet supported in MLX5, return appropriate
2650 if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2651 frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2652 return rte_flow_error_set(error, ENOTSUP,
2653 RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2654 last, "match on last "
2655 "fragment not supported");
2656 /* Other range values are invalid and rejected. */
2657 return rte_flow_error_set(error, EINVAL,
2658 RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2659 "specified range not supported");
2663 * Validate ASO CT item.
2666 * Pointer to the rte_eth_dev structure.
2668 * Item specification.
2669 * @param[in] item_flags
2670 * Pointer to bit-fields that holds the items detected until now.
2672 * Pointer to error structure.
2675 * 0 on success, a negative errno value otherwise and rte_errno is set.
2678 flow_dv_validate_item_aso_ct(struct rte_eth_dev *dev,
2679 const struct rte_flow_item *item,
2680 uint64_t *item_flags,
2681 struct rte_flow_error *error)
2683 const struct rte_flow_item_conntrack *spec = item->spec;
2684 const struct rte_flow_item_conntrack *mask = item->mask;
2688 if (*item_flags & MLX5_FLOW_LAYER_ASO_CT)
2689 return rte_flow_error_set(error, EINVAL,
2690 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2691 "Only one CT is supported");
2693 mask = &rte_flow_item_conntrack_mask;
2694 flags = spec->flags & mask->flags;
2695 if ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID) &&
2696 ((flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID) ||
2697 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD) ||
2698 (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)))
2699 return rte_flow_error_set(error, EINVAL,
2700 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
2701 "Conflict status bits");
2702 /* State change also needs to be considered. */
2703 *item_flags |= MLX5_FLOW_LAYER_ASO_CT;
2708 * Validate the pop VLAN action.
2711 * Pointer to the rte_eth_dev structure.
2712 * @param[in] action_flags
2713 * Holds the actions detected until now.
2715 * Pointer to the pop vlan action.
2716 * @param[in] item_flags
2717 * The items found in this flow rule.
2719 * Pointer to flow attributes.
2721 * Pointer to error structure.
2724 * 0 on success, a negative errno value otherwise and rte_errno is set.
2727 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2728 uint64_t action_flags,
2729 const struct rte_flow_action *action,
2730 uint64_t item_flags,
2731 const struct rte_flow_attr *attr,
2732 struct rte_flow_error *error)
2734 const struct mlx5_priv *priv = dev->data->dev_private;
2735 struct mlx5_dev_ctx_shared *sh = priv->sh;
2736 bool direction_error = false;
2738 if (!priv->sh->pop_vlan_action)
2739 return rte_flow_error_set(error, ENOTSUP,
2740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2742 "pop vlan action is not supported");
2743 /* Pop VLAN is not supported in egress except for CX6 FDB mode. */
2744 if (attr->transfer) {
2745 bool fdb_tx = priv->representor_id != UINT16_MAX;
2746 bool is_cx5 = sh->steering_format_version ==
2747 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2749 if (fdb_tx && is_cx5)
2750 direction_error = true;
2751 } else if (attr->egress) {
2752 direction_error = true;
2754 if (direction_error)
2755 return rte_flow_error_set(error, ENOTSUP,
2756 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2758 "pop vlan action not supported for egress");
2759 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2760 return rte_flow_error_set(error, ENOTSUP,
2761 RTE_FLOW_ERROR_TYPE_ACTION, action,
2762 "no support for multiple VLAN "
2764 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2765 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2766 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2767 return rte_flow_error_set(error, ENOTSUP,
2768 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2770 "cannot pop vlan after decap without "
2771 "match on inner vlan in the flow");
2772 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2773 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2774 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2775 return rte_flow_error_set(error, ENOTSUP,
2776 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2778 "cannot pop vlan without a "
2779 "match on (outer) vlan in the flow");
2780 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2781 return rte_flow_error_set(error, EINVAL,
2782 RTE_FLOW_ERROR_TYPE_ACTION, action,
2783 "wrong action order, port_id should "
2784 "be after pop VLAN action");
2785 if (!attr->transfer && priv->representor)
2786 return rte_flow_error_set(error, ENOTSUP,
2787 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2788 "pop vlan action for VF representor "
2789 "not supported on NIC table");
2794 * Get VLAN default info from vlan match info.
2797 * the list of item specifications.
2799 * pointer VLAN info to fill to.
2802 * 0 on success, a negative errno value otherwise and rte_errno is set.
2805 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2806 struct rte_vlan_hdr *vlan)
2808 const struct rte_flow_item_vlan nic_mask = {
2809 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2810 MLX5DV_FLOW_VLAN_VID_MASK),
2811 .inner_type = RTE_BE16(0xffff),
2816 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2817 int type = items->type;
2819 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2820 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2823 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2824 const struct rte_flow_item_vlan *vlan_m = items->mask;
2825 const struct rte_flow_item_vlan *vlan_v = items->spec;
2827 /* If VLAN item in pattern doesn't contain data, return here. */
2832 /* Only full match values are accepted */
2833 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2834 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2835 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2837 rte_be_to_cpu_16(vlan_v->tci &
2838 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2840 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2841 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2842 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2844 rte_be_to_cpu_16(vlan_v->tci &
2845 MLX5DV_FLOW_VLAN_VID_MASK_BE);
2847 if (vlan_m->inner_type == nic_mask.inner_type)
2848 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2849 vlan_m->inner_type);
2854 * Validate the push VLAN action.
2857 * Pointer to the rte_eth_dev structure.
2858 * @param[in] action_flags
2859 * Holds the actions detected until now.
2860 * @param[in] item_flags
2861 * The items found in this flow rule.
2863 * Pointer to the action structure.
2865 * Pointer to flow attributes
2867 * Pointer to error structure.
2870 * 0 on success, a negative errno value otherwise and rte_errno is set.
2873 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2874 uint64_t action_flags,
2875 const struct rte_flow_item_vlan *vlan_m,
2876 const struct rte_flow_action *action,
2877 const struct rte_flow_attr *attr,
2878 struct rte_flow_error *error)
2880 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2881 const struct mlx5_priv *priv = dev->data->dev_private;
2882 struct mlx5_dev_ctx_shared *sh = priv->sh;
2883 bool direction_error = false;
2885 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2886 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2887 return rte_flow_error_set(error, EINVAL,
2888 RTE_FLOW_ERROR_TYPE_ACTION, action,
2889 "invalid vlan ethertype");
2890 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2891 return rte_flow_error_set(error, EINVAL,
2892 RTE_FLOW_ERROR_TYPE_ACTION, action,
2893 "wrong action order, port_id should "
2894 "be after push VLAN");
2895 /* Push VLAN is not supported in ingress except for CX6 FDB mode. */
2896 if (attr->transfer) {
2897 bool fdb_tx = priv->representor_id != UINT16_MAX;
2898 bool is_cx5 = sh->steering_format_version ==
2899 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5;
2901 if (!fdb_tx && is_cx5)
2902 direction_error = true;
2903 } else if (attr->ingress) {
2904 direction_error = true;
2906 if (direction_error)
2907 return rte_flow_error_set(error, ENOTSUP,
2908 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2910 "push vlan action not supported for ingress");
2911 if (!attr->transfer && priv->representor)
2912 return rte_flow_error_set(error, ENOTSUP,
2913 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2914 "push vlan action for VF representor "
2915 "not supported on NIC table");
2917 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2918 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2919 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2920 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2921 !(mlx5_flow_find_action
2922 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2923 return rte_flow_error_set(error, EINVAL,
2924 RTE_FLOW_ERROR_TYPE_ACTION, action,
2925 "not full match mask on VLAN PCP and "
2926 "there is no of_set_vlan_pcp action, "
2927 "push VLAN action cannot figure out "
2930 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2931 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2932 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2933 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2934 !(mlx5_flow_find_action
2935 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2936 return rte_flow_error_set(error, EINVAL,
2937 RTE_FLOW_ERROR_TYPE_ACTION, action,
2938 "not full match mask on VLAN VID and "
2939 "there is no of_set_vlan_vid action, "
2940 "push VLAN action cannot figure out "
2947 * Validate the set VLAN PCP.
2949 * @param[in] action_flags
2950 * Holds the actions detected until now.
2951 * @param[in] actions
2952 * Pointer to the list of actions remaining in the flow rule.
2954 * Pointer to error structure.
2957 * 0 on success, a negative errno value otherwise and rte_errno is set.
2960 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2961 const struct rte_flow_action actions[],
2962 struct rte_flow_error *error)
2964 const struct rte_flow_action *action = actions;
2965 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2967 if (conf->vlan_pcp > 7)
2968 return rte_flow_error_set(error, EINVAL,
2969 RTE_FLOW_ERROR_TYPE_ACTION, action,
2970 "VLAN PCP value is too big");
2971 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2972 return rte_flow_error_set(error, ENOTSUP,
2973 RTE_FLOW_ERROR_TYPE_ACTION, action,
2974 "set VLAN PCP action must follow "
2975 "the push VLAN action");
2976 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2977 return rte_flow_error_set(error, ENOTSUP,
2978 RTE_FLOW_ERROR_TYPE_ACTION, action,
2979 "Multiple VLAN PCP modification are "
2981 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2982 return rte_flow_error_set(error, EINVAL,
2983 RTE_FLOW_ERROR_TYPE_ACTION, action,
2984 "wrong action order, port_id should "
2985 "be after set VLAN PCP");
2990 * Validate the set VLAN VID.
2992 * @param[in] item_flags
2993 * Holds the items detected in this rule.
2994 * @param[in] action_flags
2995 * Holds the actions detected until now.
2996 * @param[in] actions
2997 * Pointer to the list of actions remaining in the flow rule.
2999 * Pointer to error structure.
3002 * 0 on success, a negative errno value otherwise and rte_errno is set.
3005 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
3006 uint64_t action_flags,
3007 const struct rte_flow_action actions[],
3008 struct rte_flow_error *error)
3010 const struct rte_flow_action *action = actions;
3011 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
3013 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
3014 return rte_flow_error_set(error, EINVAL,
3015 RTE_FLOW_ERROR_TYPE_ACTION, action,
3016 "VLAN VID value is too big");
3017 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
3018 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
3019 return rte_flow_error_set(error, ENOTSUP,
3020 RTE_FLOW_ERROR_TYPE_ACTION, action,
3021 "set VLAN VID action must follow push"
3022 " VLAN action or match on VLAN item");
3023 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
3024 return rte_flow_error_set(error, ENOTSUP,
3025 RTE_FLOW_ERROR_TYPE_ACTION, action,
3026 "Multiple VLAN VID modifications are "
3028 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
3029 return rte_flow_error_set(error, EINVAL,
3030 RTE_FLOW_ERROR_TYPE_ACTION, action,
3031 "wrong action order, port_id should "
3032 "be after set VLAN VID");
3037 * Validate the FLAG action.
3040 * Pointer to the rte_eth_dev structure.
3041 * @param[in] action_flags
3042 * Holds the actions detected until now.
3044 * Pointer to flow attributes
3046 * Pointer to error structure.
3049 * 0 on success, a negative errno value otherwise and rte_errno is set.
3052 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
3053 uint64_t action_flags,
3054 const struct rte_flow_attr *attr,
3055 struct rte_flow_error *error)
3057 struct mlx5_priv *priv = dev->data->dev_private;
3058 struct mlx5_dev_config *config = &priv->config;
3061 /* Fall back if no extended metadata register support. */
3062 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3063 return mlx5_flow_validate_action_flag(action_flags, attr,
3065 /* Extensive metadata mode requires registers. */
3066 if (!mlx5_flow_ext_mreg_supported(dev))
3067 return rte_flow_error_set(error, ENOTSUP,
3068 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3069 "no metadata registers "
3070 "to support flag action");
3071 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
3072 return rte_flow_error_set(error, ENOTSUP,
3073 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3074 "extended metadata register"
3075 " isn't available");
3076 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3079 MLX5_ASSERT(ret > 0);
3080 if (action_flags & MLX5_FLOW_ACTION_MARK)
3081 return rte_flow_error_set(error, EINVAL,
3082 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3083 "can't mark and flag in same flow");
3084 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3088 " actions in same flow");
3093 * Validate MARK action.
3096 * Pointer to the rte_eth_dev structure.
3098 * Pointer to action.
3099 * @param[in] action_flags
3100 * Holds the actions detected until now.
3102 * Pointer to flow attributes
3104 * Pointer to error structure.
3107 * 0 on success, a negative errno value otherwise and rte_errno is set.
3110 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
3111 const struct rte_flow_action *action,
3112 uint64_t action_flags,
3113 const struct rte_flow_attr *attr,
3114 struct rte_flow_error *error)
3116 struct mlx5_priv *priv = dev->data->dev_private;
3117 struct mlx5_dev_config *config = &priv->config;
3118 const struct rte_flow_action_mark *mark = action->conf;
3121 if (is_tunnel_offload_active(dev))
3122 return rte_flow_error_set(error, ENOTSUP,
3123 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3125 "if tunnel offload active");
3126 /* Fall back if no extended metadata register support. */
3127 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
3128 return mlx5_flow_validate_action_mark(action, action_flags,
3130 /* Extensive metadata mode requires registers. */
3131 if (!mlx5_flow_ext_mreg_supported(dev))
3132 return rte_flow_error_set(error, ENOTSUP,
3133 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3134 "no metadata registers "
3135 "to support mark action");
3136 if (!priv->sh->dv_mark_mask)
3137 return rte_flow_error_set(error, ENOTSUP,
3138 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3139 "extended metadata register"
3140 " isn't available");
3141 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
3144 MLX5_ASSERT(ret > 0);
3146 return rte_flow_error_set(error, EINVAL,
3147 RTE_FLOW_ERROR_TYPE_ACTION, action,
3148 "configuration cannot be null");
3149 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
3150 return rte_flow_error_set(error, EINVAL,
3151 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3153 "mark id exceeds the limit");
3154 if (action_flags & MLX5_FLOW_ACTION_FLAG)
3155 return rte_flow_error_set(error, EINVAL,
3156 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3157 "can't flag and mark in same flow");
3158 if (action_flags & MLX5_FLOW_ACTION_MARK)
3159 return rte_flow_error_set(error, EINVAL,
3160 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3161 "can't have 2 mark actions in same"
3167 * Validate SET_META action.
3170 * Pointer to the rte_eth_dev structure.
3172 * Pointer to the action structure.
3173 * @param[in] action_flags
3174 * Holds the actions detected until now.
3176 * Pointer to flow attributes
3178 * Pointer to error structure.
3181 * 0 on success, a negative errno value otherwise and rte_errno is set.
3184 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
3185 const struct rte_flow_action *action,
3186 uint64_t action_flags __rte_unused,
3187 const struct rte_flow_attr *attr,
3188 struct rte_flow_error *error)
3190 struct mlx5_priv *priv = dev->data->dev_private;
3191 struct mlx5_dev_config *config = &priv->config;
3192 const struct rte_flow_action_set_meta *conf;
3193 uint32_t nic_mask = UINT32_MAX;
3196 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
3197 !mlx5_flow_ext_mreg_supported(dev))
3198 return rte_flow_error_set(error, ENOTSUP,
3199 RTE_FLOW_ERROR_TYPE_ACTION, action,
3200 "extended metadata register"
3201 " isn't supported");
3202 reg = flow_dv_get_metadata_reg(dev, attr, error);
3206 return rte_flow_error_set(error, ENOTSUP,
3207 RTE_FLOW_ERROR_TYPE_ACTION, action,
3208 "unavalable extended metadata register");
3209 if (reg != REG_A && reg != REG_B) {
3210 struct mlx5_priv *priv = dev->data->dev_private;
3212 nic_mask = priv->sh->dv_meta_mask;
3214 if (!(action->conf))
3215 return rte_flow_error_set(error, EINVAL,
3216 RTE_FLOW_ERROR_TYPE_ACTION, action,
3217 "configuration cannot be null");
3218 conf = (const struct rte_flow_action_set_meta *)action->conf;
3220 return rte_flow_error_set(error, EINVAL,
3221 RTE_FLOW_ERROR_TYPE_ACTION, action,
3222 "zero mask doesn't have any effect");
3223 if (conf->mask & ~nic_mask)
3224 return rte_flow_error_set(error, EINVAL,
3225 RTE_FLOW_ERROR_TYPE_ACTION, action,
3226 "meta data must be within reg C0");
3231 * Validate SET_TAG action.
3234 * Pointer to the rte_eth_dev structure.
3236 * Pointer to the action structure.
3237 * @param[in] action_flags
3238 * Holds the actions detected until now.
3240 * Pointer to flow attributes
3242 * Pointer to error structure.
3245 * 0 on success, a negative errno value otherwise and rte_errno is set.
3248 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3249 const struct rte_flow_action *action,
3250 uint64_t action_flags,
3251 const struct rte_flow_attr *attr,
3252 struct rte_flow_error *error)
3254 const struct rte_flow_action_set_tag *conf;
3255 const uint64_t terminal_action_flags =
3256 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3257 MLX5_FLOW_ACTION_RSS;
3260 if (!mlx5_flow_ext_mreg_supported(dev))
3261 return rte_flow_error_set(error, ENOTSUP,
3262 RTE_FLOW_ERROR_TYPE_ACTION, action,
3263 "extensive metadata register"
3264 " isn't supported");
3265 if (!(action->conf))
3266 return rte_flow_error_set(error, EINVAL,
3267 RTE_FLOW_ERROR_TYPE_ACTION, action,
3268 "configuration cannot be null");
3269 conf = (const struct rte_flow_action_set_tag *)action->conf;
3271 return rte_flow_error_set(error, EINVAL,
3272 RTE_FLOW_ERROR_TYPE_ACTION, action,
3273 "zero mask doesn't have any effect");
3274 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3277 if (!attr->transfer && attr->ingress &&
3278 (action_flags & terminal_action_flags))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION, action,
3281 "set_tag has no effect"
3282 " with terminal actions");
3287 * Validate count action.
3290 * Pointer to rte_eth_dev structure.
3292 * Indicator if action is shared.
3293 * @param[in] action_flags
3294 * Holds the actions detected until now.
3296 * Pointer to error structure.
3299 * 0 on success, a negative errno value otherwise and rte_errno is set.
3302 flow_dv_validate_action_count(struct rte_eth_dev *dev, bool shared,
3303 uint64_t action_flags,
3304 struct rte_flow_error *error)
3306 struct mlx5_priv *priv = dev->data->dev_private;
3308 if (!priv->sh->devx)
3310 if (action_flags & MLX5_FLOW_ACTION_COUNT)
3311 return rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3313 "duplicate count actions set");
3314 if (shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3315 !priv->sh->flow_hit_aso_en)
3316 return rte_flow_error_set(error, EINVAL,
3317 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3318 "old age and shared count combination is not supported");
3319 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3323 return rte_flow_error_set
3325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3327 "count action not supported");
3331 * Validate the L2 encap action.
3334 * Pointer to the rte_eth_dev structure.
3335 * @param[in] action_flags
3336 * Holds the actions detected until now.
3338 * Pointer to the action structure.
3340 * Pointer to flow attributes.
3342 * Pointer to error structure.
3345 * 0 on success, a negative errno value otherwise and rte_errno is set.
3348 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3349 uint64_t action_flags,
3350 const struct rte_flow_action *action,
3351 const struct rte_flow_attr *attr,
3352 struct rte_flow_error *error)
3354 const struct mlx5_priv *priv = dev->data->dev_private;
3356 if (!(action->conf))
3357 return rte_flow_error_set(error, EINVAL,
3358 RTE_FLOW_ERROR_TYPE_ACTION, action,
3359 "configuration cannot be null");
3360 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3361 return rte_flow_error_set(error, EINVAL,
3362 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3363 "can only have a single encap action "
3365 if (!attr->transfer && priv->representor)
3366 return rte_flow_error_set(error, ENOTSUP,
3367 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3368 "encap action for VF representor "
3369 "not supported on NIC table");
3374 * Validate a decap action.
3377 * Pointer to the rte_eth_dev structure.
3378 * @param[in] action_flags
3379 * Holds the actions detected until now.
3381 * Pointer to the action structure.
3382 * @param[in] item_flags
3383 * Holds the items detected.
3385 * Pointer to flow attributes
3387 * Pointer to error structure.
3390 * 0 on success, a negative errno value otherwise and rte_errno is set.
3393 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3394 uint64_t action_flags,
3395 const struct rte_flow_action *action,
3396 const uint64_t item_flags,
3397 const struct rte_flow_attr *attr,
3398 struct rte_flow_error *error)
3400 const struct mlx5_priv *priv = dev->data->dev_private;
3402 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3403 !priv->config.decap_en)
3404 return rte_flow_error_set(error, ENOTSUP,
3405 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3406 "decap is not enabled");
3407 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3408 return rte_flow_error_set(error, ENOTSUP,
3409 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3411 MLX5_FLOW_ACTION_DECAP ? "can only "
3412 "have a single decap action" : "decap "
3413 "after encap is not supported");
3414 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3415 return rte_flow_error_set(error, EINVAL,
3416 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3417 "can't have decap action after"
3420 return rte_flow_error_set(error, ENOTSUP,
3421 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3423 "decap action not supported for "
3425 if (!attr->transfer && priv->representor)
3426 return rte_flow_error_set(error, ENOTSUP,
3427 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3428 "decap action for VF representor "
3429 "not supported on NIC table");
3430 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3431 !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3432 return rte_flow_error_set(error, ENOTSUP,
3433 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3434 "VXLAN item should be present for VXLAN decap");
3438 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3441 * Validate the raw encap and decap actions.
3444 * Pointer to the rte_eth_dev structure.
3446 * Pointer to the decap action.
3448 * Pointer to the encap action.
3450 * Pointer to flow attributes
3451 * @param[in/out] action_flags
3452 * Holds the actions detected until now.
3453 * @param[out] actions_n
3454 * pointer to the number of actions counter.
3456 * Pointer to the action structure.
3457 * @param[in] item_flags
3458 * Holds the items detected.
3460 * Pointer to error structure.
3463 * 0 on success, a negative errno value otherwise and rte_errno is set.
3466 flow_dv_validate_action_raw_encap_decap
3467 (struct rte_eth_dev *dev,
3468 const struct rte_flow_action_raw_decap *decap,
3469 const struct rte_flow_action_raw_encap *encap,
3470 const struct rte_flow_attr *attr, uint64_t *action_flags,
3471 int *actions_n, const struct rte_flow_action *action,
3472 uint64_t item_flags, struct rte_flow_error *error)
3474 const struct mlx5_priv *priv = dev->data->dev_private;
3477 if (encap && (!encap->size || !encap->data))
3478 return rte_flow_error_set(error, EINVAL,
3479 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3480 "raw encap data cannot be empty");
3481 if (decap && encap) {
3482 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3483 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3486 else if (encap->size <=
3487 MLX5_ENCAPSULATION_DECISION_SIZE &&
3489 MLX5_ENCAPSULATION_DECISION_SIZE)
3492 else if (encap->size >
3493 MLX5_ENCAPSULATION_DECISION_SIZE &&
3495 MLX5_ENCAPSULATION_DECISION_SIZE)
3496 /* 2 L2 actions: encap and decap. */
3499 return rte_flow_error_set(error,
3501 RTE_FLOW_ERROR_TYPE_ACTION,
3502 NULL, "unsupported too small "
3503 "raw decap and too small raw "
3504 "encap combination");
3507 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3508 item_flags, attr, error);
3511 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3515 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3516 return rte_flow_error_set(error, ENOTSUP,
3517 RTE_FLOW_ERROR_TYPE_ACTION,
3519 "small raw encap size");
3520 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3521 return rte_flow_error_set(error, EINVAL,
3522 RTE_FLOW_ERROR_TYPE_ACTION,
3524 "more than one encap action");
3525 if (!attr->transfer && priv->representor)
3526 return rte_flow_error_set
3528 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3529 "encap action for VF representor "
3530 "not supported on NIC table");
3531 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3538 * Validate the ASO CT action.
3541 * Pointer to the rte_eth_dev structure.
3542 * @param[in] action_flags
3543 * Holds the actions detected until now.
3544 * @param[in] item_flags
3545 * The items found in this flow rule.
3547 * Pointer to flow attributes.
3549 * Pointer to error structure.
3552 * 0 on success, a negative errno value otherwise and rte_errno is set.
3555 flow_dv_validate_action_aso_ct(struct rte_eth_dev *dev,
3556 uint64_t action_flags,
3557 uint64_t item_flags,
3558 const struct rte_flow_attr *attr,
3559 struct rte_flow_error *error)
3563 if (attr->group == 0 && !attr->transfer)
3564 return rte_flow_error_set(error, ENOTSUP,
3565 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3567 "Only support non-root table");
3568 if (action_flags & MLX5_FLOW_FATE_ACTIONS)
3569 return rte_flow_error_set(error, ENOTSUP,
3570 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3571 "CT cannot follow a fate action");
3572 if ((action_flags & MLX5_FLOW_ACTION_METER) ||
3573 (action_flags & MLX5_FLOW_ACTION_AGE))
3574 return rte_flow_error_set(error, EINVAL,
3575 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3576 "Only one ASO action is supported");
3577 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3578 return rte_flow_error_set(error, EINVAL,
3579 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3580 "Encap cannot exist before CT");
3581 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3584 "Not a outer TCP packet");
3589 flow_dv_encap_decap_match_cb(void *tool_ctx __rte_unused,
3590 struct mlx5_list_entry *entry, void *cb_ctx)
3592 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3593 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3594 struct mlx5_flow_dv_encap_decap_resource *resource;
3596 resource = container_of(entry, struct mlx5_flow_dv_encap_decap_resource,
3598 if (resource->reformat_type == ctx_resource->reformat_type &&
3599 resource->ft_type == ctx_resource->ft_type &&
3600 resource->flags == ctx_resource->flags &&
3601 resource->size == ctx_resource->size &&
3602 !memcmp((const void *)resource->buf,
3603 (const void *)ctx_resource->buf,
3609 struct mlx5_list_entry *
3610 flow_dv_encap_decap_create_cb(void *tool_ctx, void *cb_ctx)
3612 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3613 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3614 struct mlx5dv_dr_domain *domain;
3615 struct mlx5_flow_dv_encap_decap_resource *ctx_resource = ctx->data;
3616 struct mlx5_flow_dv_encap_decap_resource *resource;
3620 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3621 domain = sh->fdb_domain;
3622 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3623 domain = sh->rx_domain;
3625 domain = sh->tx_domain;
3626 /* Register new encap/decap resource. */
3627 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &idx);
3629 rte_flow_error_set(ctx->error, ENOMEM,
3630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3631 "cannot allocate resource memory");
3634 *resource = *ctx_resource;
3635 resource->idx = idx;
3636 ret = mlx5_flow_os_create_flow_action_packet_reformat(sh->cdev->ctx,
3640 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3641 rte_flow_error_set(ctx->error, ENOMEM,
3642 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3643 NULL, "cannot create action");
3647 return &resource->entry;
3650 struct mlx5_list_entry *
3651 flow_dv_encap_decap_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
3654 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3655 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3656 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3659 cache_resource = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3661 if (!cache_resource) {
3662 rte_flow_error_set(ctx->error, ENOMEM,
3663 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3664 "cannot allocate resource memory");
3667 memcpy(cache_resource, oentry, sizeof(*cache_resource));
3668 cache_resource->idx = idx;
3669 return &cache_resource->entry;
3673 flow_dv_encap_decap_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3675 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3676 struct mlx5_flow_dv_encap_decap_resource *res =
3677 container_of(entry, typeof(*res), entry);
3679 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
3683 * Find existing encap/decap resource or create and register a new one.
3685 * @param[in, out] dev
3686 * Pointer to rte_eth_dev structure.
3687 * @param[in, out] resource
3688 * Pointer to encap/decap resource.
3689 * @parm[in, out] dev_flow
3690 * Pointer to the dev_flow.
3692 * pointer to error structure.
3695 * 0 on success otherwise -errno and errno is set.
3698 flow_dv_encap_decap_resource_register
3699 (struct rte_eth_dev *dev,
3700 struct mlx5_flow_dv_encap_decap_resource *resource,
3701 struct mlx5_flow *dev_flow,
3702 struct rte_flow_error *error)
3704 struct mlx5_priv *priv = dev->data->dev_private;
3705 struct mlx5_dev_ctx_shared *sh = priv->sh;
3706 struct mlx5_list_entry *entry;
3710 uint32_t refmt_type:8;
3712 * Header reformat actions can be shared between
3713 * non-root tables. One bit to indicate non-root
3717 uint32_t reserve:15;
3720 } encap_decap_key = {
3722 .ft_type = resource->ft_type,
3723 .refmt_type = resource->reformat_type,
3724 .is_root = !!dev_flow->dv.group,
3728 struct mlx5_flow_cb_ctx ctx = {
3732 struct mlx5_hlist *encaps_decaps;
3735 encaps_decaps = flow_dv_hlist_prepare(sh, &sh->encaps_decaps,
3737 MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ,
3739 flow_dv_encap_decap_create_cb,
3740 flow_dv_encap_decap_match_cb,
3741 flow_dv_encap_decap_remove_cb,
3742 flow_dv_encap_decap_clone_cb,
3743 flow_dv_encap_decap_clone_free_cb);
3744 if (unlikely(!encaps_decaps))
3746 resource->flags = dev_flow->dv.group ? 0 : 1;
3747 key64 = __rte_raw_cksum(&encap_decap_key.v32,
3748 sizeof(encap_decap_key.v32), 0);
3749 if (resource->reformat_type !=
3750 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3752 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3753 entry = mlx5_hlist_register(encaps_decaps, key64, &ctx);
3756 resource = container_of(entry, typeof(*resource), entry);
3757 dev_flow->dv.encap_decap = resource;
3758 dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3763 * Find existing table jump resource or create and register a new one.
3765 * @param[in, out] dev
3766 * Pointer to rte_eth_dev structure.
3767 * @param[in, out] tbl
3768 * Pointer to flow table resource.
3769 * @parm[in, out] dev_flow
3770 * Pointer to the dev_flow.
3772 * pointer to error structure.
3775 * 0 on success otherwise -errno and errno is set.
3778 flow_dv_jump_tbl_resource_register
3779 (struct rte_eth_dev *dev __rte_unused,
3780 struct mlx5_flow_tbl_resource *tbl,
3781 struct mlx5_flow *dev_flow,
3782 struct rte_flow_error *error __rte_unused)
3784 struct mlx5_flow_tbl_data_entry *tbl_data =
3785 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3788 MLX5_ASSERT(tbl_data->jump.action);
3789 dev_flow->handle->rix_jump = tbl_data->idx;
3790 dev_flow->dv.jump = &tbl_data->jump;
3795 flow_dv_port_id_match_cb(void *tool_ctx __rte_unused,
3796 struct mlx5_list_entry *entry, void *cb_ctx)
3798 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3799 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3800 struct mlx5_flow_dv_port_id_action_resource *res =
3801 container_of(entry, typeof(*res), entry);
3803 return ref->port_id != res->port_id;
3806 struct mlx5_list_entry *
3807 flow_dv_port_id_create_cb(void *tool_ctx, void *cb_ctx)
3809 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3810 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3811 struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3812 struct mlx5_flow_dv_port_id_action_resource *resource;
3816 /* Register new port id action resource. */
3817 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3819 rte_flow_error_set(ctx->error, ENOMEM,
3820 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3821 "cannot allocate port_id action memory");
3825 ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3829 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3830 rte_flow_error_set(ctx->error, ENOMEM,
3831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3832 "cannot create action");
3835 resource->idx = idx;
3836 return &resource->entry;
3839 struct mlx5_list_entry *
3840 flow_dv_port_id_clone_cb(void *tool_ctx,
3841 struct mlx5_list_entry *entry __rte_unused,
3844 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3845 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3846 struct mlx5_flow_dv_port_id_action_resource *resource;
3849 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3851 rte_flow_error_set(ctx->error, ENOMEM,
3852 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3853 "cannot allocate port_id action memory");
3856 memcpy(resource, entry, sizeof(*resource));
3857 resource->idx = idx;
3858 return &resource->entry;
3862 flow_dv_port_id_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3864 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3865 struct mlx5_flow_dv_port_id_action_resource *resource =
3866 container_of(entry, typeof(*resource), entry);
3868 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
3872 * Find existing table port ID resource or create and register a new one.
3874 * @param[in, out] dev
3875 * Pointer to rte_eth_dev structure.
3876 * @param[in, out] ref
3877 * Pointer to port ID action resource reference.
3878 * @parm[in, out] dev_flow
3879 * Pointer to the dev_flow.
3881 * pointer to error structure.
3884 * 0 on success otherwise -errno and errno is set.
3887 flow_dv_port_id_action_resource_register
3888 (struct rte_eth_dev *dev,
3889 struct mlx5_flow_dv_port_id_action_resource *ref,
3890 struct mlx5_flow *dev_flow,
3891 struct rte_flow_error *error)
3893 struct mlx5_priv *priv = dev->data->dev_private;
3894 struct mlx5_list_entry *entry;
3895 struct mlx5_flow_dv_port_id_action_resource *resource;
3896 struct mlx5_flow_cb_ctx ctx = {
3901 entry = mlx5_list_register(priv->sh->port_id_action_list, &ctx);
3904 resource = container_of(entry, typeof(*resource), entry);
3905 dev_flow->dv.port_id_action = resource;
3906 dev_flow->handle->rix_port_id_action = resource->idx;
3911 flow_dv_push_vlan_match_cb(void *tool_ctx __rte_unused,
3912 struct mlx5_list_entry *entry, void *cb_ctx)
3914 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3915 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3916 struct mlx5_flow_dv_push_vlan_action_resource *res =
3917 container_of(entry, typeof(*res), entry);
3919 return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3922 struct mlx5_list_entry *
3923 flow_dv_push_vlan_create_cb(void *tool_ctx, void *cb_ctx)
3925 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3926 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3927 struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3928 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3929 struct mlx5dv_dr_domain *domain;
3933 /* Register new port id action resource. */
3934 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3936 rte_flow_error_set(ctx->error, ENOMEM,
3937 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3938 "cannot allocate push_vlan action memory");
3942 if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3943 domain = sh->fdb_domain;
3944 else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3945 domain = sh->rx_domain;
3947 domain = sh->tx_domain;
3948 ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3951 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3952 rte_flow_error_set(ctx->error, ENOMEM,
3953 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3954 "cannot create push vlan action");
3957 resource->idx = idx;
3958 return &resource->entry;
3961 struct mlx5_list_entry *
3962 flow_dv_push_vlan_clone_cb(void *tool_ctx,
3963 struct mlx5_list_entry *entry __rte_unused,
3966 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3967 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3968 struct mlx5_flow_dv_push_vlan_action_resource *resource;
3971 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3973 rte_flow_error_set(ctx->error, ENOMEM,
3974 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3975 "cannot allocate push_vlan action memory");
3978 memcpy(resource, entry, sizeof(*resource));
3979 resource->idx = idx;
3980 return &resource->entry;
3984 flow_dv_push_vlan_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
3986 struct mlx5_dev_ctx_shared *sh = tool_ctx;
3987 struct mlx5_flow_dv_push_vlan_action_resource *resource =
3988 container_of(entry, typeof(*resource), entry);
3990 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
3994 * Find existing push vlan resource or create and register a new one.
3996 * @param [in, out] dev
3997 * Pointer to rte_eth_dev structure.
3998 * @param[in, out] ref
3999 * Pointer to port ID action resource reference.
4000 * @parm[in, out] dev_flow
4001 * Pointer to the dev_flow.
4003 * pointer to error structure.
4006 * 0 on success otherwise -errno and errno is set.
4009 flow_dv_push_vlan_action_resource_register
4010 (struct rte_eth_dev *dev,
4011 struct mlx5_flow_dv_push_vlan_action_resource *ref,
4012 struct mlx5_flow *dev_flow,
4013 struct rte_flow_error *error)
4015 struct mlx5_priv *priv = dev->data->dev_private;
4016 struct mlx5_flow_dv_push_vlan_action_resource *resource;
4017 struct mlx5_list_entry *entry;
4018 struct mlx5_flow_cb_ctx ctx = {
4023 entry = mlx5_list_register(priv->sh->push_vlan_action_list, &ctx);
4026 resource = container_of(entry, typeof(*resource), entry);
4028 dev_flow->handle->dvh.rix_push_vlan = resource->idx;
4029 dev_flow->dv.push_vlan_res = resource;
4034 * Get the size of specific rte_flow_item_type hdr size
4036 * @param[in] item_type
4037 * Tested rte_flow_item_type.
4040 * sizeof struct item_type, 0 if void or irrelevant.
4043 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
4047 switch (item_type) {
4048 case RTE_FLOW_ITEM_TYPE_ETH:
4049 retval = sizeof(struct rte_ether_hdr);
4051 case RTE_FLOW_ITEM_TYPE_VLAN:
4052 retval = sizeof(struct rte_vlan_hdr);
4054 case RTE_FLOW_ITEM_TYPE_IPV4:
4055 retval = sizeof(struct rte_ipv4_hdr);
4057 case RTE_FLOW_ITEM_TYPE_IPV6:
4058 retval = sizeof(struct rte_ipv6_hdr);
4060 case RTE_FLOW_ITEM_TYPE_UDP:
4061 retval = sizeof(struct rte_udp_hdr);
4063 case RTE_FLOW_ITEM_TYPE_TCP:
4064 retval = sizeof(struct rte_tcp_hdr);
4066 case RTE_FLOW_ITEM_TYPE_VXLAN:
4067 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4068 retval = sizeof(struct rte_vxlan_hdr);
4070 case RTE_FLOW_ITEM_TYPE_GRE:
4071 case RTE_FLOW_ITEM_TYPE_NVGRE:
4072 retval = sizeof(struct rte_gre_hdr);
4074 case RTE_FLOW_ITEM_TYPE_MPLS:
4075 retval = sizeof(struct rte_mpls_hdr);
4077 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
4085 #define MLX5_ENCAP_IPV4_VERSION 0x40
4086 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
4087 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
4088 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
4089 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
4090 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
4091 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
4094 * Convert the encap action data from list of rte_flow_item to raw buffer
4097 * Pointer to rte_flow_item objects list.
4099 * Pointer to the output buffer.
4101 * Pointer to the output buffer size.
4103 * Pointer to the error structure.
4106 * 0 on success, a negative errno value otherwise and rte_errno is set.
4109 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
4110 size_t *size, struct rte_flow_error *error)
4112 struct rte_ether_hdr *eth = NULL;
4113 struct rte_vlan_hdr *vlan = NULL;
4114 struct rte_ipv4_hdr *ipv4 = NULL;
4115 struct rte_ipv6_hdr *ipv6 = NULL;
4116 struct rte_udp_hdr *udp = NULL;
4117 struct rte_vxlan_hdr *vxlan = NULL;
4118 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
4119 struct rte_gre_hdr *gre = NULL;
4121 size_t temp_size = 0;
4124 return rte_flow_error_set(error, EINVAL,
4125 RTE_FLOW_ERROR_TYPE_ACTION,
4126 NULL, "invalid empty data");
4127 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4128 len = flow_dv_get_item_hdr_len(items->type);
4129 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
4130 return rte_flow_error_set(error, EINVAL,
4131 RTE_FLOW_ERROR_TYPE_ACTION,
4132 (void *)items->type,
4133 "items total size is too big"
4134 " for encap action");
4135 rte_memcpy((void *)&buf[temp_size], items->spec, len);
4136 switch (items->type) {
4137 case RTE_FLOW_ITEM_TYPE_ETH:
4138 eth = (struct rte_ether_hdr *)&buf[temp_size];
4140 case RTE_FLOW_ITEM_TYPE_VLAN:
4141 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
4143 return rte_flow_error_set(error, EINVAL,
4144 RTE_FLOW_ERROR_TYPE_ACTION,
4145 (void *)items->type,
4146 "eth header not found");
4147 if (!eth->ether_type)
4148 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
4150 case RTE_FLOW_ITEM_TYPE_IPV4:
4151 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
4153 return rte_flow_error_set(error, EINVAL,
4154 RTE_FLOW_ERROR_TYPE_ACTION,
4155 (void *)items->type,
4156 "neither eth nor vlan"
4158 if (vlan && !vlan->eth_proto)
4159 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4160 else if (eth && !eth->ether_type)
4161 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
4162 if (!ipv4->version_ihl)
4163 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
4164 MLX5_ENCAP_IPV4_IHL_MIN;
4165 if (!ipv4->time_to_live)
4166 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
4168 case RTE_FLOW_ITEM_TYPE_IPV6:
4169 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
4171 return rte_flow_error_set(error, EINVAL,
4172 RTE_FLOW_ERROR_TYPE_ACTION,
4173 (void *)items->type,
4174 "neither eth nor vlan"
4176 if (vlan && !vlan->eth_proto)
4177 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4178 else if (eth && !eth->ether_type)
4179 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
4180 if (!ipv6->vtc_flow)
4182 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
4183 if (!ipv6->hop_limits)
4184 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
4186 case RTE_FLOW_ITEM_TYPE_UDP:
4187 udp = (struct rte_udp_hdr *)&buf[temp_size];
4189 return rte_flow_error_set(error, EINVAL,
4190 RTE_FLOW_ERROR_TYPE_ACTION,
4191 (void *)items->type,
4192 "ip header not found");
4193 if (ipv4 && !ipv4->next_proto_id)
4194 ipv4->next_proto_id = IPPROTO_UDP;
4195 else if (ipv6 && !ipv6->proto)
4196 ipv6->proto = IPPROTO_UDP;
4198 case RTE_FLOW_ITEM_TYPE_VXLAN:
4199 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
4201 return rte_flow_error_set(error, EINVAL,
4202 RTE_FLOW_ERROR_TYPE_ACTION,
4203 (void *)items->type,
4204 "udp header not found");
4206 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
4207 if (!vxlan->vx_flags)
4209 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
4211 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4212 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
4214 return rte_flow_error_set(error, EINVAL,
4215 RTE_FLOW_ERROR_TYPE_ACTION,
4216 (void *)items->type,
4217 "udp header not found");
4218 if (!vxlan_gpe->proto)
4219 return rte_flow_error_set(error, EINVAL,
4220 RTE_FLOW_ERROR_TYPE_ACTION,
4221 (void *)items->type,
4222 "next protocol not found");
4225 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
4226 if (!vxlan_gpe->vx_flags)
4227 vxlan_gpe->vx_flags =
4228 MLX5_ENCAP_VXLAN_GPE_FLAGS;
4230 case RTE_FLOW_ITEM_TYPE_GRE:
4231 case RTE_FLOW_ITEM_TYPE_NVGRE:
4232 gre = (struct rte_gre_hdr *)&buf[temp_size];
4234 return rte_flow_error_set(error, EINVAL,
4235 RTE_FLOW_ERROR_TYPE_ACTION,
4236 (void *)items->type,
4237 "next protocol not found");
4239 return rte_flow_error_set(error, EINVAL,
4240 RTE_FLOW_ERROR_TYPE_ACTION,
4241 (void *)items->type,
4242 "ip header not found");
4243 if (ipv4 && !ipv4->next_proto_id)
4244 ipv4->next_proto_id = IPPROTO_GRE;
4245 else if (ipv6 && !ipv6->proto)
4246 ipv6->proto = IPPROTO_GRE;
4248 case RTE_FLOW_ITEM_TYPE_VOID:
4251 return rte_flow_error_set(error, EINVAL,
4252 RTE_FLOW_ERROR_TYPE_ACTION,
4253 (void *)items->type,
4254 "unsupported item type");
4264 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
4266 struct rte_ether_hdr *eth = NULL;
4267 struct rte_vlan_hdr *vlan = NULL;
4268 struct rte_ipv6_hdr *ipv6 = NULL;
4269 struct rte_udp_hdr *udp = NULL;
4273 eth = (struct rte_ether_hdr *)data;
4274 next_hdr = (char *)(eth + 1);
4275 proto = RTE_BE16(eth->ether_type);
4278 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
4279 vlan = (struct rte_vlan_hdr *)next_hdr;
4280 proto = RTE_BE16(vlan->eth_proto);
4281 next_hdr += sizeof(struct rte_vlan_hdr);
4284 /* HW calculates IPv4 csum. no need to proceed */
4285 if (proto == RTE_ETHER_TYPE_IPV4)
4288 /* non IPv4/IPv6 header. not supported */
4289 if (proto != RTE_ETHER_TYPE_IPV6) {
4290 return rte_flow_error_set(error, ENOTSUP,
4291 RTE_FLOW_ERROR_TYPE_ACTION,
4292 NULL, "Cannot offload non IPv4/IPv6");
4295 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
4297 /* ignore non UDP */
4298 if (ipv6->proto != IPPROTO_UDP)
4301 udp = (struct rte_udp_hdr *)(ipv6 + 1);
4302 udp->dgram_cksum = 0;
4308 * Convert L2 encap action to DV specification.
4311 * Pointer to rte_eth_dev structure.
4313 * Pointer to action structure.
4314 * @param[in, out] dev_flow
4315 * Pointer to the mlx5_flow.
4316 * @param[in] transfer
4317 * Mark if the flow is E-Switch flow.
4319 * Pointer to the error structure.
4322 * 0 on success, a negative errno value otherwise and rte_errno is set.
4325 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4326 const struct rte_flow_action *action,
4327 struct mlx5_flow *dev_flow,
4329 struct rte_flow_error *error)
4331 const struct rte_flow_item *encap_data;
4332 const struct rte_flow_action_raw_encap *raw_encap_data;
4333 struct mlx5_flow_dv_encap_decap_resource res = {
4335 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4336 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4337 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4340 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4342 (const struct rte_flow_action_raw_encap *)action->conf;
4343 res.size = raw_encap_data->size;
4344 memcpy(res.buf, raw_encap_data->data, res.size);
4346 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4348 ((const struct rte_flow_action_vxlan_encap *)
4349 action->conf)->definition;
4352 ((const struct rte_flow_action_nvgre_encap *)
4353 action->conf)->definition;
4354 if (flow_dv_convert_encap_data(encap_data, res.buf,
4358 if (flow_dv_zero_encap_udp_csum(res.buf, error))
4360 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4361 return rte_flow_error_set(error, EINVAL,
4362 RTE_FLOW_ERROR_TYPE_ACTION,
4363 NULL, "can't create L2 encap action");
4368 * Convert L2 decap action to DV specification.
4371 * Pointer to rte_eth_dev structure.
4372 * @param[in, out] dev_flow
4373 * Pointer to the mlx5_flow.
4374 * @param[in] transfer
4375 * Mark if the flow is E-Switch flow.
4377 * Pointer to the error structure.
4380 * 0 on success, a negative errno value otherwise and rte_errno is set.
4383 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4384 struct mlx5_flow *dev_flow,
4386 struct rte_flow_error *error)
4388 struct mlx5_flow_dv_encap_decap_resource res = {
4391 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4392 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4393 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4396 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4397 return rte_flow_error_set(error, EINVAL,
4398 RTE_FLOW_ERROR_TYPE_ACTION,
4399 NULL, "can't create L2 decap action");
4404 * Convert raw decap/encap (L3 tunnel) action to DV specification.
4407 * Pointer to rte_eth_dev structure.
4409 * Pointer to action structure.
4410 * @param[in, out] dev_flow
4411 * Pointer to the mlx5_flow.
4413 * Pointer to the flow attributes.
4415 * Pointer to the error structure.
4418 * 0 on success, a negative errno value otherwise and rte_errno is set.
4421 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4422 const struct rte_flow_action *action,
4423 struct mlx5_flow *dev_flow,
4424 const struct rte_flow_attr *attr,
4425 struct rte_flow_error *error)
4427 const struct rte_flow_action_raw_encap *encap_data;
4428 struct mlx5_flow_dv_encap_decap_resource res;
4430 memset(&res, 0, sizeof(res));
4431 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4432 res.size = encap_data->size;
4433 memcpy(res.buf, encap_data->data, res.size);
4434 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4435 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4436 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4438 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4440 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4441 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4442 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4443 return rte_flow_error_set(error, EINVAL,
4444 RTE_FLOW_ERROR_TYPE_ACTION,
4445 NULL, "can't create encap action");
4450 * Create action push VLAN.
4453 * Pointer to rte_eth_dev structure.
4455 * Pointer to the flow attributes.
4457 * Pointer to the vlan to push to the Ethernet header.
4458 * @param[in, out] dev_flow
4459 * Pointer to the mlx5_flow.
4461 * Pointer to the error structure.
4464 * 0 on success, a negative errno value otherwise and rte_errno is set.
4467 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4468 const struct rte_flow_attr *attr,
4469 const struct rte_vlan_hdr *vlan,
4470 struct mlx5_flow *dev_flow,
4471 struct rte_flow_error *error)
4473 struct mlx5_flow_dv_push_vlan_action_resource res;
4475 memset(&res, 0, sizeof(res));
4477 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4480 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4482 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4483 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4484 return flow_dv_push_vlan_action_resource_register
4485 (dev, &res, dev_flow, error);
4489 * Validate the modify-header actions.
4491 * @param[in] action_flags
4492 * Holds the actions detected until now.
4494 * Pointer to the modify action.
4496 * Pointer to error structure.
4499 * 0 on success, a negative errno value otherwise and rte_errno is set.
4502 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4503 const struct rte_flow_action *action,
4504 struct rte_flow_error *error)
4506 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4507 return rte_flow_error_set(error, EINVAL,
4508 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4509 NULL, "action configuration not set");
4510 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4511 return rte_flow_error_set(error, EINVAL,
4512 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4513 "can't have encap action before"
4519 * Validate the modify-header MAC address actions.
4521 * @param[in] action_flags
4522 * Holds the actions detected until now.
4524 * Pointer to the modify action.
4525 * @param[in] item_flags
4526 * Holds the items detected.
4528 * Pointer to error structure.
4531 * 0 on success, a negative errno value otherwise and rte_errno is set.
4534 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4535 const struct rte_flow_action *action,
4536 const uint64_t item_flags,
4537 struct rte_flow_error *error)
4541 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4543 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4544 return rte_flow_error_set(error, EINVAL,
4545 RTE_FLOW_ERROR_TYPE_ACTION,
4547 "no L2 item in pattern");
4553 * Validate the modify-header IPv4 address actions.
4555 * @param[in] action_flags
4556 * Holds the actions detected until now.
4558 * Pointer to the modify action.
4559 * @param[in] item_flags
4560 * Holds the items detected.
4562 * Pointer to error structure.
4565 * 0 on success, a negative errno value otherwise and rte_errno is set.
4568 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4569 const struct rte_flow_action *action,
4570 const uint64_t item_flags,
4571 struct rte_flow_error *error)
4576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4578 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4579 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4580 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4581 if (!(item_flags & layer))
4582 return rte_flow_error_set(error, EINVAL,
4583 RTE_FLOW_ERROR_TYPE_ACTION,
4585 "no ipv4 item in pattern");
4591 * Validate the modify-header IPv6 address actions.
4593 * @param[in] action_flags
4594 * Holds the actions detected until now.
4596 * Pointer to the modify action.
4597 * @param[in] item_flags
4598 * Holds the items detected.
4600 * Pointer to error structure.
4603 * 0 on success, a negative errno value otherwise and rte_errno is set.
4606 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4607 const struct rte_flow_action *action,
4608 const uint64_t item_flags,
4609 struct rte_flow_error *error)
4614 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4616 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4617 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4618 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4619 if (!(item_flags & layer))
4620 return rte_flow_error_set(error, EINVAL,
4621 RTE_FLOW_ERROR_TYPE_ACTION,
4623 "no ipv6 item in pattern");
4629 * Validate the modify-header TP actions.
4631 * @param[in] action_flags
4632 * Holds the actions detected until now.
4634 * Pointer to the modify action.
4635 * @param[in] item_flags
4636 * Holds the items detected.
4638 * Pointer to error structure.
4641 * 0 on success, a negative errno value otherwise and rte_errno is set.
4644 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4645 const struct rte_flow_action *action,
4646 const uint64_t item_flags,
4647 struct rte_flow_error *error)
4652 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4654 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4655 MLX5_FLOW_LAYER_INNER_L4 :
4656 MLX5_FLOW_LAYER_OUTER_L4;
4657 if (!(item_flags & layer))
4658 return rte_flow_error_set(error, EINVAL,
4659 RTE_FLOW_ERROR_TYPE_ACTION,
4660 NULL, "no transport layer "
4667 * Validate the modify-header actions of increment/decrement
4668 * TCP Sequence-number.
4670 * @param[in] action_flags
4671 * Holds the actions detected until now.
4673 * Pointer to the modify action.
4674 * @param[in] item_flags
4675 * Holds the items detected.
4677 * Pointer to error structure.
4680 * 0 on success, a negative errno value otherwise and rte_errno is set.
4683 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4684 const struct rte_flow_action *action,
4685 const uint64_t item_flags,
4686 struct rte_flow_error *error)
4691 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4693 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4694 MLX5_FLOW_LAYER_INNER_L4_TCP :
4695 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4696 if (!(item_flags & layer))
4697 return rte_flow_error_set(error, EINVAL,
4698 RTE_FLOW_ERROR_TYPE_ACTION,
4699 NULL, "no TCP item in"
4701 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4702 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4703 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4704 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4705 return rte_flow_error_set(error, EINVAL,
4706 RTE_FLOW_ERROR_TYPE_ACTION,
4708 "cannot decrease and increase"
4709 " TCP sequence number"
4710 " at the same time");
4716 * Validate the modify-header actions of increment/decrement
4717 * TCP Acknowledgment number.
4719 * @param[in] action_flags
4720 * Holds the actions detected until now.
4722 * Pointer to the modify action.
4723 * @param[in] item_flags
4724 * Holds the items detected.
4726 * Pointer to error structure.
4729 * 0 on success, a negative errno value otherwise and rte_errno is set.
4732 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4733 const struct rte_flow_action *action,
4734 const uint64_t item_flags,
4735 struct rte_flow_error *error)
4740 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4742 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4743 MLX5_FLOW_LAYER_INNER_L4_TCP :
4744 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4745 if (!(item_flags & layer))
4746 return rte_flow_error_set(error, EINVAL,
4747 RTE_FLOW_ERROR_TYPE_ACTION,
4748 NULL, "no TCP item in"
4750 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4751 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4752 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4753 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4754 return rte_flow_error_set(error, EINVAL,
4755 RTE_FLOW_ERROR_TYPE_ACTION,
4757 "cannot decrease and increase"
4758 " TCP acknowledgment number"
4759 " at the same time");
4765 * Validate the modify-header TTL actions.
4767 * @param[in] action_flags
4768 * Holds the actions detected until now.
4770 * Pointer to the modify action.
4771 * @param[in] item_flags
4772 * Holds the items detected.
4774 * Pointer to error structure.
4777 * 0 on success, a negative errno value otherwise and rte_errno is set.
4780 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4781 const struct rte_flow_action *action,
4782 const uint64_t item_flags,
4783 struct rte_flow_error *error)
4788 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4790 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4791 MLX5_FLOW_LAYER_INNER_L3 :
4792 MLX5_FLOW_LAYER_OUTER_L3;
4793 if (!(item_flags & layer))
4794 return rte_flow_error_set(error, EINVAL,
4795 RTE_FLOW_ERROR_TYPE_ACTION,
4797 "no IP protocol in pattern");
4803 * Validate the generic modify field actions.
4805 * Pointer to the rte_eth_dev structure.
4806 * @param[in] action_flags
4807 * Holds the actions detected until now.
4809 * Pointer to the modify action.
4811 * Pointer to the flow attributes.
4813 * Pointer to error structure.
4816 * Number of header fields to modify (0 or more) on success,
4817 * a negative errno value otherwise and rte_errno is set.
4820 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4821 const uint64_t action_flags,
4822 const struct rte_flow_action *action,
4823 const struct rte_flow_attr *attr,
4824 struct rte_flow_error *error)
4827 struct mlx5_priv *priv = dev->data->dev_private;
4828 struct mlx5_dev_config *config = &priv->config;
4829 const struct rte_flow_action_modify_field *action_modify_field =
4831 uint32_t dst_width = mlx5_flow_item_field_width(dev,
4832 action_modify_field->dst.field,
4834 uint32_t src_width = mlx5_flow_item_field_width(dev,
4835 action_modify_field->src.field,
4836 dst_width, attr, error);
4838 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4842 if (action_modify_field->width == 0)
4843 return rte_flow_error_set(error, EINVAL,
4844 RTE_FLOW_ERROR_TYPE_ACTION, action,
4845 "no bits are requested to be modified");
4846 else if (action_modify_field->width > dst_width ||
4847 action_modify_field->width > src_width)
4848 return rte_flow_error_set(error, EINVAL,
4849 RTE_FLOW_ERROR_TYPE_ACTION, action,
4850 "cannot modify more bits than"
4851 " the width of a field");
4852 if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4853 action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4854 if ((action_modify_field->dst.offset +
4855 action_modify_field->width > dst_width) ||
4856 (action_modify_field->dst.offset % 32))
4857 return rte_flow_error_set(error, EINVAL,
4858 RTE_FLOW_ERROR_TYPE_ACTION, action,
4859 "destination offset is too big"
4860 " or not aligned to 4 bytes");
4861 if (action_modify_field->dst.level &&
4862 action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4863 return rte_flow_error_set(error, ENOTSUP,
4864 RTE_FLOW_ERROR_TYPE_ACTION, action,
4865 "inner header fields modification"
4866 " is not supported");
4868 if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4869 action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4870 if (!attr->transfer && !attr->group)
4871 return rte_flow_error_set(error, ENOTSUP,
4872 RTE_FLOW_ERROR_TYPE_ACTION, action,
4873 "modify field action is not"
4874 " supported for group 0");
4875 if ((action_modify_field->src.offset +
4876 action_modify_field->width > src_width) ||
4877 (action_modify_field->src.offset % 32))
4878 return rte_flow_error_set(error, EINVAL,
4879 RTE_FLOW_ERROR_TYPE_ACTION, action,
4880 "source offset is too big"
4881 " or not aligned to 4 bytes");
4882 if (action_modify_field->src.level &&
4883 action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4884 return rte_flow_error_set(error, ENOTSUP,
4885 RTE_FLOW_ERROR_TYPE_ACTION, action,
4886 "inner header fields modification"
4887 " is not supported");
4889 if ((action_modify_field->dst.field ==
4890 action_modify_field->src.field) &&
4891 (action_modify_field->dst.level ==
4892 action_modify_field->src.level))
4893 return rte_flow_error_set(error, EINVAL,
4894 RTE_FLOW_ERROR_TYPE_ACTION, action,
4895 "source and destination fields"
4896 " cannot be the same");
4897 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4898 action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER ||
4899 action_modify_field->dst.field == RTE_FLOW_FIELD_MARK)
4900 return rte_flow_error_set(error, EINVAL,
4901 RTE_FLOW_ERROR_TYPE_ACTION, action,
4902 "mark, immediate value or a pointer to it"
4903 " cannot be used as a destination");
4904 if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4905 action_modify_field->src.field == RTE_FLOW_FIELD_START)
4906 return rte_flow_error_set(error, ENOTSUP,
4907 RTE_FLOW_ERROR_TYPE_ACTION, action,
4908 "modifications of an arbitrary"
4909 " place in a packet is not supported");
4910 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VLAN_TYPE ||
4911 action_modify_field->src.field == RTE_FLOW_FIELD_VLAN_TYPE)
4912 return rte_flow_error_set(error, ENOTSUP,
4913 RTE_FLOW_ERROR_TYPE_ACTION, action,
4914 "modifications of the 802.1Q Tag"
4915 " Identifier is not supported");
4916 if (action_modify_field->dst.field == RTE_FLOW_FIELD_VXLAN_VNI ||
4917 action_modify_field->src.field == RTE_FLOW_FIELD_VXLAN_VNI)
4918 return rte_flow_error_set(error, ENOTSUP,
4919 RTE_FLOW_ERROR_TYPE_ACTION, action,
4920 "modifications of the VXLAN Network"
4921 " Identifier is not supported");
4922 if (action_modify_field->dst.field == RTE_FLOW_FIELD_GENEVE_VNI ||
4923 action_modify_field->src.field == RTE_FLOW_FIELD_GENEVE_VNI)
4924 return rte_flow_error_set(error, ENOTSUP,
4925 RTE_FLOW_ERROR_TYPE_ACTION, action,
4926 "modifications of the GENEVE Network"
4927 " Identifier is not supported");
4928 if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4929 action_modify_field->src.field == RTE_FLOW_FIELD_MARK)
4930 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4931 !mlx5_flow_ext_mreg_supported(dev))
4932 return rte_flow_error_set(error, ENOTSUP,
4933 RTE_FLOW_ERROR_TYPE_ACTION, action,
4934 "cannot modify mark in legacy mode"
4935 " or without extensive registers");
4936 if (action_modify_field->dst.field == RTE_FLOW_FIELD_META ||
4937 action_modify_field->src.field == RTE_FLOW_FIELD_META) {
4938 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
4939 !mlx5_flow_ext_mreg_supported(dev))
4940 return rte_flow_error_set(error, ENOTSUP,
4941 RTE_FLOW_ERROR_TYPE_ACTION, action,
4942 "cannot modify meta without"
4943 " extensive registers support");
4944 ret = flow_dv_get_metadata_reg(dev, attr, error);
4945 if (ret < 0 || ret == REG_NON)
4946 return rte_flow_error_set(error, ENOTSUP,
4947 RTE_FLOW_ERROR_TYPE_ACTION, action,
4948 "cannot modify meta without"
4949 " extensive registers available");
4951 if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4952 return rte_flow_error_set(error, ENOTSUP,
4953 RTE_FLOW_ERROR_TYPE_ACTION, action,
4954 "add and sub operations"
4955 " are not supported");
4956 return (action_modify_field->width / 32) +
4957 !!(action_modify_field->width % 32);
4961 * Validate jump action.
4964 * Pointer to the jump action.
4965 * @param[in] action_flags
4966 * Holds the actions detected until now.
4967 * @param[in] attributes
4968 * Pointer to flow attributes
4969 * @param[in] external
4970 * Action belongs to flow rule created by request external to PMD.
4972 * Pointer to error structure.
4975 * 0 on success, a negative errno value otherwise and rte_errno is set.
4978 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4979 const struct mlx5_flow_tunnel *tunnel,
4980 const struct rte_flow_action *action,
4981 uint64_t action_flags,
4982 const struct rte_flow_attr *attributes,
4983 bool external, struct rte_flow_error *error)
4985 uint32_t target_group, table;
4987 struct flow_grp_info grp_info = {
4988 .external = !!external,
4989 .transfer = !!attributes->transfer,
4993 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4994 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4995 return rte_flow_error_set(error, EINVAL,
4996 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4997 "can't have 2 fate actions in"
5000 return rte_flow_error_set(error, EINVAL,
5001 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5002 NULL, "action configuration not set");
5004 ((const struct rte_flow_action_jump *)action->conf)->group;
5005 ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
5009 if (attributes->group == target_group &&
5010 !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
5011 MLX5_FLOW_ACTION_TUNNEL_MATCH)))
5012 return rte_flow_error_set(error, EINVAL,
5013 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5014 "target group must be other than"
5015 " the current flow group");
5020 * Validate action PORT_ID / REPRESENTED_PORT.
5023 * Pointer to rte_eth_dev structure.
5024 * @param[in] action_flags
5025 * Bit-fields that holds the actions detected until now.
5027 * PORT_ID / REPRESENTED_PORT action structure.
5029 * Attributes of flow that includes this action.
5031 * Pointer to error structure.
5034 * 0 on success, a negative errno value otherwise and rte_errno is set.
5037 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
5038 uint64_t action_flags,
5039 const struct rte_flow_action *action,
5040 const struct rte_flow_attr *attr,
5041 struct rte_flow_error *error)
5043 const struct rte_flow_action_port_id *port_id;
5044 const struct rte_flow_action_ethdev *ethdev;
5045 struct mlx5_priv *act_priv;
5046 struct mlx5_priv *dev_priv;
5049 if (!attr->transfer)
5050 return rte_flow_error_set(error, ENOTSUP,
5051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5053 "port action is valid in transfer"
5055 if (!action || !action->conf)
5056 return rte_flow_error_set(error, ENOTSUP,
5057 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
5059 "port action parameters must be"
5061 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
5062 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5063 return rte_flow_error_set(error, EINVAL,
5064 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5065 "can have only one fate actions in"
5067 dev_priv = mlx5_dev_to_eswitch_info(dev);
5069 return rte_flow_error_set(error, rte_errno,
5070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5072 "failed to obtain E-Switch info");
5073 switch (action->type) {
5074 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5075 port_id = action->conf;
5076 port = port_id->original ? dev->data->port_id : port_id->id;
5078 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5079 ethdev = action->conf;
5080 port = ethdev->port_id;
5084 return rte_flow_error_set
5086 RTE_FLOW_ERROR_TYPE_ACTION, action,
5087 "unknown E-Switch action");
5089 act_priv = mlx5_port_to_eswitch_info(port, false);
5091 return rte_flow_error_set
5093 RTE_FLOW_ERROR_TYPE_ACTION_CONF, action->conf,
5094 "failed to obtain E-Switch port id for port");
5095 if (act_priv->domain_id != dev_priv->domain_id)
5096 return rte_flow_error_set
5098 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5099 "port does not belong to"
5100 " E-Switch being configured");
5105 * Get the maximum number of modify header actions.
5108 * Pointer to rte_eth_dev structure.
5110 * Whether action is on root table.
5113 * Max number of modify header actions device can support.
5115 static inline unsigned int
5116 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
5120 * There's no way to directly query the max capacity from FW.
5121 * The maximal value on root table should be assumed to be supported.
5124 return MLX5_MAX_MODIFY_NUM;
5126 return MLX5_ROOT_TBL_MODIFY_NUM;
5130 * Validate the meter action.
5133 * Pointer to rte_eth_dev structure.
5134 * @param[in] action_flags
5135 * Bit-fields that holds the actions detected until now.
5136 * @param[in] item_flags
5137 * Holds the items detected.
5139 * Pointer to the meter action.
5141 * Attributes of flow that includes this action.
5142 * @param[in] port_id_item
5143 * Pointer to item indicating port id.
5145 * Pointer to error structure.
5148 * 0 on success, a negative errno value otherwise and rte_ernno is set.
5151 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
5152 uint64_t action_flags, uint64_t item_flags,
5153 const struct rte_flow_action *action,
5154 const struct rte_flow_attr *attr,
5155 const struct rte_flow_item *port_id_item,
5157 struct rte_flow_error *error)
5159 struct mlx5_priv *priv = dev->data->dev_private;
5160 const struct rte_flow_action_meter *am = action->conf;
5161 struct mlx5_flow_meter_info *fm;
5162 struct mlx5_flow_meter_policy *mtr_policy;
5163 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
5166 return rte_flow_error_set(error, EINVAL,
5167 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5168 "meter action conf is NULL");
5170 if (action_flags & MLX5_FLOW_ACTION_METER)
5171 return rte_flow_error_set(error, ENOTSUP,
5172 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5173 "meter chaining not support");
5174 if (action_flags & MLX5_FLOW_ACTION_JUMP)
5175 return rte_flow_error_set(error, ENOTSUP,
5176 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5177 "meter with jump not support");
5179 return rte_flow_error_set(error, ENOTSUP,
5180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5182 "meter action not supported");
5183 fm = mlx5_flow_meter_find(priv, am->mtr_id, NULL);
5185 return rte_flow_error_set(error, EINVAL,
5186 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5188 /* aso meter can always be shared by different domains */
5189 if (fm->ref_cnt && !priv->sh->meter_aso_en &&
5190 !(fm->transfer == attr->transfer ||
5191 (!fm->ingress && !attr->ingress && attr->egress) ||
5192 (!fm->egress && !attr->egress && attr->ingress)))
5193 return rte_flow_error_set(error, EINVAL,
5194 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5195 "Flow attributes domain are either invalid "
5196 "or have a domain conflict with current "
5197 "meter attributes");
5198 if (fm->def_policy) {
5199 if (!((attr->transfer &&
5200 mtrmng->def_policy[MLX5_MTR_DOMAIN_TRANSFER]) ||
5202 mtrmng->def_policy[MLX5_MTR_DOMAIN_EGRESS]) ||
5204 mtrmng->def_policy[MLX5_MTR_DOMAIN_INGRESS])))
5205 return rte_flow_error_set(error, EINVAL,
5206 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5207 "Flow attributes domain "
5208 "have a conflict with current "
5209 "meter domain attributes");
5212 mtr_policy = mlx5_flow_meter_policy_find(dev,
5213 fm->policy_id, NULL);
5215 return rte_flow_error_set(error, EINVAL,
5216 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5217 "Invalid policy id for meter ");
5218 if (!((attr->transfer && mtr_policy->transfer) ||
5219 (attr->egress && mtr_policy->egress) ||
5220 (attr->ingress && mtr_policy->ingress)))
5221 return rte_flow_error_set(error, EINVAL,
5222 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5223 "Flow attributes domain "
5224 "have a conflict with current "
5225 "meter domain attributes");
5226 if (attr->transfer && mtr_policy->dev) {
5228 * When policy has fate action of port_id,
5229 * the flow should have the same src port as policy.
5231 struct mlx5_priv *policy_port_priv =
5232 mtr_policy->dev->data->dev_private;
5233 int32_t flow_src_port = priv->representor_id;
5236 const struct rte_flow_item_port_id *spec =
5238 struct mlx5_priv *port_priv =
5239 mlx5_port_to_eswitch_info(spec->id,
5242 return rte_flow_error_set(error,
5244 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5246 "Failed to get port info.");
5247 flow_src_port = port_priv->representor_id;
5249 if (flow_src_port != policy_port_priv->representor_id)
5250 return rte_flow_error_set(error,
5252 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
5254 "Flow and meter policy "
5255 "have different src port.");
5256 } else if (mtr_policy->is_rss) {
5257 struct mlx5_flow_meter_policy *fp;
5258 struct mlx5_meter_policy_action_container *acg;
5259 struct mlx5_meter_policy_action_container *acy;
5260 const struct rte_flow_action *rss_act;
5263 fp = mlx5_flow_meter_hierarchy_get_final_policy(dev,
5266 return rte_flow_error_set(error, EINVAL,
5267 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5268 "Unable to get the final "
5269 "policy in the hierarchy");
5270 acg = &fp->act_cnt[RTE_COLOR_GREEN];
5271 acy = &fp->act_cnt[RTE_COLOR_YELLOW];
5272 MLX5_ASSERT(acg->fate_action ==
5273 MLX5_FLOW_FATE_SHARED_RSS ||
5275 MLX5_FLOW_FATE_SHARED_RSS);
5276 if (acg->fate_action == MLX5_FLOW_FATE_SHARED_RSS)
5280 ret = mlx5_flow_validate_action_rss(rss_act,
5281 action_flags, dev, attr,
5286 *def_policy = false;
5292 * Validate the age action.
5294 * @param[in] action_flags
5295 * Holds the actions detected until now.
5297 * Pointer to the age action.
5299 * Pointer to the Ethernet device structure.
5301 * Pointer to error structure.
5304 * 0 on success, a negative errno value otherwise and rte_errno is set.
5307 flow_dv_validate_action_age(uint64_t action_flags,
5308 const struct rte_flow_action *action,
5309 struct rte_eth_dev *dev,
5310 struct rte_flow_error *error)
5312 struct mlx5_priv *priv = dev->data->dev_private;
5313 const struct rte_flow_action_age *age = action->conf;
5315 if (!priv->sh->devx || (priv->sh->cmng.counter_fallback &&
5316 !priv->sh->aso_age_mng))
5317 return rte_flow_error_set(error, ENOTSUP,
5318 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5320 "age action not supported");
5321 if (!(action->conf))
5322 return rte_flow_error_set(error, EINVAL,
5323 RTE_FLOW_ERROR_TYPE_ACTION, action,
5324 "configuration cannot be null");
5325 if (!(age->timeout))
5326 return rte_flow_error_set(error, EINVAL,
5327 RTE_FLOW_ERROR_TYPE_ACTION, action,
5328 "invalid timeout value 0");
5329 if (action_flags & MLX5_FLOW_ACTION_AGE)
5330 return rte_flow_error_set(error, EINVAL,
5331 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5332 "duplicate age actions set");
5337 * Validate the modify-header IPv4 DSCP actions.
5339 * @param[in] action_flags
5340 * Holds the actions detected until now.
5342 * Pointer to the modify action.
5343 * @param[in] item_flags
5344 * Holds the items detected.
5346 * Pointer to error structure.
5349 * 0 on success, a negative errno value otherwise and rte_errno is set.
5352 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
5353 const struct rte_flow_action *action,
5354 const uint64_t item_flags,
5355 struct rte_flow_error *error)
5359 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5361 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
5362 return rte_flow_error_set(error, EINVAL,
5363 RTE_FLOW_ERROR_TYPE_ACTION,
5365 "no ipv4 item in pattern");
5371 * Validate the modify-header IPv6 DSCP actions.
5373 * @param[in] action_flags
5374 * Holds the actions detected until now.
5376 * Pointer to the modify action.
5377 * @param[in] item_flags
5378 * Holds the items detected.
5380 * Pointer to error structure.
5383 * 0 on success, a negative errno value otherwise and rte_errno is set.
5386 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
5387 const struct rte_flow_action *action,
5388 const uint64_t item_flags,
5389 struct rte_flow_error *error)
5393 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
5395 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
5396 return rte_flow_error_set(error, EINVAL,
5397 RTE_FLOW_ERROR_TYPE_ACTION,
5399 "no ipv6 item in pattern");
5405 flow_dv_modify_match_cb(void *tool_ctx __rte_unused,
5406 struct mlx5_list_entry *entry, void *cb_ctx)
5408 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5409 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5410 struct mlx5_flow_dv_modify_hdr_resource *resource =
5411 container_of(entry, typeof(*resource), entry);
5412 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5414 key_len += ref->actions_num * sizeof(ref->actions[0]);
5415 return ref->actions_num != resource->actions_num ||
5416 memcmp(&ref->ft_type, &resource->ft_type, key_len);
5419 static struct mlx5_indexed_pool *
5420 flow_dv_modify_ipool_get(struct mlx5_dev_ctx_shared *sh, uint8_t index)
5422 struct mlx5_indexed_pool *ipool = __atomic_load_n
5423 (&sh->mdh_ipools[index], __ATOMIC_SEQ_CST);
5426 struct mlx5_indexed_pool *expected = NULL;
5427 struct mlx5_indexed_pool_config cfg =
5428 (struct mlx5_indexed_pool_config) {
5429 .size = sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
5431 sizeof(struct mlx5_modification_cmd),
5436 .release_mem_en = !!sh->reclaim_mode,
5437 .per_core_cache = sh->reclaim_mode ? 0 : (1 << 16),
5438 .malloc = mlx5_malloc,
5440 .type = "mlx5_modify_action_resource",
5443 cfg.size = RTE_ALIGN(cfg.size, sizeof(ipool));
5444 ipool = mlx5_ipool_create(&cfg);
5447 if (!__atomic_compare_exchange_n(&sh->mdh_ipools[index],
5448 &expected, ipool, false,
5450 __ATOMIC_SEQ_CST)) {
5451 mlx5_ipool_destroy(ipool);
5452 ipool = __atomic_load_n(&sh->mdh_ipools[index],
5459 struct mlx5_list_entry *
5460 flow_dv_modify_create_cb(void *tool_ctx, void *cb_ctx)
5462 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5463 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5464 struct mlx5dv_dr_domain *ns;
5465 struct mlx5_flow_dv_modify_hdr_resource *entry;
5466 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5467 struct mlx5_indexed_pool *ipool = flow_dv_modify_ipool_get(sh,
5468 ref->actions_num - 1);
5470 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5471 uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5474 if (unlikely(!ipool)) {
5475 rte_flow_error_set(ctx->error, ENOMEM,
5476 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5477 NULL, "cannot allocate modify ipool");
5480 entry = mlx5_ipool_zmalloc(ipool, &idx);
5482 rte_flow_error_set(ctx->error, ENOMEM,
5483 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5484 "cannot allocate resource memory");
5487 rte_memcpy(&entry->ft_type,
5488 RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5489 key_len + data_len);
5490 if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5491 ns = sh->fdb_domain;
5492 else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5496 ret = mlx5_flow_os_create_flow_action_modify_header
5497 (sh->cdev->ctx, ns, entry,
5498 data_len, &entry->action);
5500 mlx5_ipool_free(sh->mdh_ipools[ref->actions_num - 1], idx);
5501 rte_flow_error_set(ctx->error, ENOMEM,
5502 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5503 NULL, "cannot create modification action");
5507 return &entry->entry;
5510 struct mlx5_list_entry *
5511 flow_dv_modify_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
5514 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5515 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5516 struct mlx5_flow_dv_modify_hdr_resource *entry;
5517 struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5518 uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5521 entry = mlx5_ipool_malloc(sh->mdh_ipools[ref->actions_num - 1],
5524 rte_flow_error_set(ctx->error, ENOMEM,
5525 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5526 "cannot allocate resource memory");
5529 memcpy(entry, oentry, sizeof(*entry) + data_len);
5531 return &entry->entry;
5535 flow_dv_modify_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
5537 struct mlx5_dev_ctx_shared *sh = tool_ctx;
5538 struct mlx5_flow_dv_modify_hdr_resource *res =
5539 container_of(entry, typeof(*res), entry);
5541 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
5545 * Validate the sample action.
5547 * @param[in, out] action_flags
5548 * Holds the actions detected until now.
5550 * Pointer to the sample action.
5552 * Pointer to the Ethernet device structure.
5554 * Attributes of flow that includes this action.
5555 * @param[in] item_flags
5556 * Holds the items detected.
5558 * Pointer to the RSS action.
5559 * @param[out] sample_rss
5560 * Pointer to the RSS action in sample action list.
5562 * Pointer to the COUNT action in sample action list.
5563 * @param[out] fdb_mirror_limit
5564 * Pointer to the FDB mirror limitation flag.
5566 * Pointer to error structure.
5569 * 0 on success, a negative errno value otherwise and rte_errno is set.
5572 flow_dv_validate_action_sample(uint64_t *action_flags,
5573 const struct rte_flow_action *action,
5574 struct rte_eth_dev *dev,
5575 const struct rte_flow_attr *attr,
5576 uint64_t item_flags,
5577 const struct rte_flow_action_rss *rss,
5578 const struct rte_flow_action_rss **sample_rss,
5579 const struct rte_flow_action_count **count,
5580 int *fdb_mirror_limit,
5581 struct rte_flow_error *error)
5583 struct mlx5_priv *priv = dev->data->dev_private;
5584 struct mlx5_dev_config *dev_conf = &priv->config;
5585 const struct rte_flow_action_sample *sample = action->conf;
5586 const struct rte_flow_action *act;
5587 uint64_t sub_action_flags = 0;
5588 uint16_t queue_index = 0xFFFF;
5593 return rte_flow_error_set(error, EINVAL,
5594 RTE_FLOW_ERROR_TYPE_ACTION, action,
5595 "configuration cannot be NULL");
5596 if (sample->ratio == 0)
5597 return rte_flow_error_set(error, EINVAL,
5598 RTE_FLOW_ERROR_TYPE_ACTION, action,
5599 "ratio value starts from 1");
5600 if (!priv->sh->devx || (sample->ratio > 0 && !priv->sampler_en))
5601 return rte_flow_error_set(error, ENOTSUP,
5602 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5604 "sample action not supported");
5605 if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5606 return rte_flow_error_set(error, EINVAL,
5607 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5608 "Multiple sample actions not "
5610 if (*action_flags & MLX5_FLOW_ACTION_METER)
5611 return rte_flow_error_set(error, EINVAL,
5612 RTE_FLOW_ERROR_TYPE_ACTION, action,
5613 "wrong action order, meter should "
5614 "be after sample action");
5615 if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5616 return rte_flow_error_set(error, EINVAL,
5617 RTE_FLOW_ERROR_TYPE_ACTION, action,
5618 "wrong action order, jump should "
5619 "be after sample action");
5620 if (*action_flags & MLX5_FLOW_ACTION_CT)
5621 return rte_flow_error_set(error, EINVAL,
5622 RTE_FLOW_ERROR_TYPE_ACTION, action,
5623 "Sample after CT not supported");
5624 act = sample->actions;
5625 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5626 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5627 return rte_flow_error_set(error, ENOTSUP,
5628 RTE_FLOW_ERROR_TYPE_ACTION,
5629 act, "too many actions");
5630 switch (act->type) {
5631 case RTE_FLOW_ACTION_TYPE_QUEUE:
5632 ret = mlx5_flow_validate_action_queue(act,
5638 queue_index = ((const struct rte_flow_action_queue *)
5639 (act->conf))->index;
5640 sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5643 case RTE_FLOW_ACTION_TYPE_RSS:
5644 *sample_rss = act->conf;
5645 ret = mlx5_flow_validate_action_rss(act,
5652 if (rss && *sample_rss &&
5653 ((*sample_rss)->level != rss->level ||
5654 (*sample_rss)->types != rss->types))
5655 return rte_flow_error_set(error, ENOTSUP,
5656 RTE_FLOW_ERROR_TYPE_ACTION,
5658 "Can't use the different RSS types "
5659 "or level in the same flow");
5660 if (*sample_rss != NULL && (*sample_rss)->queue_num)
5661 queue_index = (*sample_rss)->queue[0];
5662 sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5665 case RTE_FLOW_ACTION_TYPE_MARK:
5666 ret = flow_dv_validate_action_mark(dev, act,
5671 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5672 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5673 MLX5_FLOW_ACTION_MARK_EXT;
5675 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5678 case RTE_FLOW_ACTION_TYPE_COUNT:
5679 ret = flow_dv_validate_action_count
5680 (dev, false, *action_flags | sub_action_flags,
5685 sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5686 *action_flags |= MLX5_FLOW_ACTION_COUNT;
5689 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5690 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
5691 ret = flow_dv_validate_action_port_id(dev,
5698 sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5701 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5702 ret = flow_dv_validate_action_raw_encap_decap
5703 (dev, NULL, act->conf, attr, &sub_action_flags,
5704 &actions_n, action, item_flags, error);
5709 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5710 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5711 ret = flow_dv_validate_action_l2_encap(dev,
5717 sub_action_flags |= MLX5_FLOW_ACTION_ENCAP;
5721 return rte_flow_error_set(error, ENOTSUP,
5722 RTE_FLOW_ERROR_TYPE_ACTION,
5724 "Doesn't support optional "
5728 if (attr->ingress && !attr->transfer) {
5729 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5730 MLX5_FLOW_ACTION_RSS)))
5731 return rte_flow_error_set(error, EINVAL,
5732 RTE_FLOW_ERROR_TYPE_ACTION,
5734 "Ingress must has a dest "
5735 "QUEUE for Sample");
5736 } else if (attr->egress && !attr->transfer) {
5737 return rte_flow_error_set(error, ENOTSUP,
5738 RTE_FLOW_ERROR_TYPE_ACTION,
5740 "Sample Only support Ingress "
5742 } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5743 MLX5_ASSERT(attr->transfer);
5744 if (sample->ratio > 1)
5745 return rte_flow_error_set(error, ENOTSUP,
5746 RTE_FLOW_ERROR_TYPE_ACTION,
5748 "E-Switch doesn't support "
5749 "any optional action "
5751 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5752 return rte_flow_error_set(error, ENOTSUP,
5753 RTE_FLOW_ERROR_TYPE_ACTION,
5755 "unsupported action QUEUE");
5756 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5757 return rte_flow_error_set(error, ENOTSUP,
5758 RTE_FLOW_ERROR_TYPE_ACTION,
5760 "unsupported action QUEUE");
5761 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5762 return rte_flow_error_set(error, EINVAL,
5763 RTE_FLOW_ERROR_TYPE_ACTION,
5765 "E-Switch must has a dest "
5766 "port for mirroring");
5767 if (!priv->config.hca_attr.reg_c_preserve &&
5768 priv->representor_id != UINT16_MAX)
5769 *fdb_mirror_limit = 1;
5771 /* Continue validation for Xcap actions.*/
5772 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5773 (queue_index == 0xFFFF ||
5774 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5775 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5776 MLX5_FLOW_XCAP_ACTIONS)
5777 return rte_flow_error_set(error, ENOTSUP,
5778 RTE_FLOW_ERROR_TYPE_ACTION,
5779 NULL, "encap and decap "
5780 "combination aren't "
5782 if (!attr->transfer && attr->ingress && (sub_action_flags &
5783 MLX5_FLOW_ACTION_ENCAP))
5784 return rte_flow_error_set(error, ENOTSUP,
5785 RTE_FLOW_ERROR_TYPE_ACTION,
5786 NULL, "encap is not supported"
5787 " for ingress traffic");
5793 * Find existing modify-header resource or create and register a new one.
5795 * @param dev[in, out]
5796 * Pointer to rte_eth_dev structure.
5797 * @param[in, out] resource
5798 * Pointer to modify-header resource.
5799 * @parm[in, out] dev_flow
5800 * Pointer to the dev_flow.
5802 * pointer to error structure.
5805 * 0 on success otherwise -errno and errno is set.
5808 flow_dv_modify_hdr_resource_register
5809 (struct rte_eth_dev *dev,
5810 struct mlx5_flow_dv_modify_hdr_resource *resource,
5811 struct mlx5_flow *dev_flow,
5812 struct rte_flow_error *error)
5814 struct mlx5_priv *priv = dev->data->dev_private;
5815 struct mlx5_dev_ctx_shared *sh = priv->sh;
5816 uint32_t key_len = sizeof(*resource) -
5817 offsetof(typeof(*resource), ft_type) +
5818 resource->actions_num * sizeof(resource->actions[0]);
5819 struct mlx5_list_entry *entry;
5820 struct mlx5_flow_cb_ctx ctx = {
5824 struct mlx5_hlist *modify_cmds;
5827 modify_cmds = flow_dv_hlist_prepare(sh, &sh->modify_cmds,
5829 MLX5_FLOW_HDR_MODIFY_HTABLE_SZ,
5831 flow_dv_modify_create_cb,
5832 flow_dv_modify_match_cb,
5833 flow_dv_modify_remove_cb,
5834 flow_dv_modify_clone_cb,
5835 flow_dv_modify_clone_free_cb);
5836 if (unlikely(!modify_cmds))
5838 resource->root = !dev_flow->dv.group;
5839 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5841 return rte_flow_error_set(error, EOVERFLOW,
5842 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5843 "too many modify header items");
5844 key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5845 entry = mlx5_hlist_register(modify_cmds, key64, &ctx);
5848 resource = container_of(entry, typeof(*resource), entry);
5849 dev_flow->handle->dvh.modify_hdr = resource;
5854 * Get DV flow counter by index.
5857 * Pointer to the Ethernet device structure.
5859 * mlx5 flow counter index in the container.
5861 * mlx5 flow counter pool in the container.
5864 * Pointer to the counter, NULL otherwise.
5866 static struct mlx5_flow_counter *
5867 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5869 struct mlx5_flow_counter_pool **ppool)
5871 struct mlx5_priv *priv = dev->data->dev_private;
5872 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5873 struct mlx5_flow_counter_pool *pool;
5875 /* Decrease to original index and clear shared bit. */
5876 idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5877 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5878 pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5882 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5886 * Check the devx counter belongs to the pool.
5889 * Pointer to the counter pool.
5891 * The counter devx ID.
5894 * True if counter belongs to the pool, false otherwise.
5897 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5899 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5900 MLX5_COUNTERS_PER_POOL;
5902 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5908 * Get a pool by devx counter ID.
5911 * Pointer to the counter management.
5913 * The counter devx ID.
5916 * The counter pool pointer if exists, NULL otherwise,
5918 static struct mlx5_flow_counter_pool *
5919 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5922 struct mlx5_flow_counter_pool *pool = NULL;
5924 rte_spinlock_lock(&cmng->pool_update_sl);
5925 /* Check last used pool. */
5926 if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5927 flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5928 pool = cmng->pools[cmng->last_pool_idx];
5931 /* ID out of range means no suitable pool in the container. */
5932 if (id > cmng->max_id || id < cmng->min_id)
5935 * Find the pool from the end of the container, since mostly counter
5936 * ID is sequence increasing, and the last pool should be the needed
5941 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5943 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5949 rte_spinlock_unlock(&cmng->pool_update_sl);
5954 * Resize a counter container.
5957 * Pointer to the Ethernet device structure.
5960 * 0 on success, otherwise negative errno value and rte_errno is set.
5963 flow_dv_container_resize(struct rte_eth_dev *dev)
5965 struct mlx5_priv *priv = dev->data->dev_private;
5966 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5967 void *old_pools = cmng->pools;
5968 uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5969 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5970 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5977 memcpy(pools, old_pools, cmng->n *
5978 sizeof(struct mlx5_flow_counter_pool *));
5980 cmng->pools = pools;
5982 mlx5_free(old_pools);
5987 * Query a devx flow counter.
5990 * Pointer to the Ethernet device structure.
5991 * @param[in] counter
5992 * Index to the flow counter.
5994 * The statistics value of packets.
5996 * The statistics value of bytes.
5999 * 0 on success, otherwise a negative errno value and rte_errno is set.
6002 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
6005 struct mlx5_priv *priv = dev->data->dev_private;
6006 struct mlx5_flow_counter_pool *pool = NULL;
6007 struct mlx5_flow_counter *cnt;
6010 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6012 if (priv->sh->cmng.counter_fallback)
6013 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
6014 0, pkts, bytes, 0, NULL, NULL, 0);
6015 rte_spinlock_lock(&pool->sl);
6020 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
6021 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
6022 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
6024 rte_spinlock_unlock(&pool->sl);
6029 * Create and initialize a new counter pool.
6032 * Pointer to the Ethernet device structure.
6034 * The devX counter handle.
6036 * Whether the pool is for counter that was allocated for aging.
6037 * @param[in/out] cont_cur
6038 * Pointer to the container pointer, it will be update in pool resize.
6041 * The pool container pointer on success, NULL otherwise and rte_errno is set.
6043 static struct mlx5_flow_counter_pool *
6044 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
6047 struct mlx5_priv *priv = dev->data->dev_private;
6048 struct mlx5_flow_counter_pool *pool;
6049 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6050 bool fallback = priv->sh->cmng.counter_fallback;
6051 uint32_t size = sizeof(*pool);
6053 size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
6054 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
6055 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
6061 pool->is_aged = !!age;
6062 pool->query_gen = 0;
6063 pool->min_dcs = dcs;
6064 rte_spinlock_init(&pool->sl);
6065 rte_spinlock_init(&pool->csl);
6066 TAILQ_INIT(&pool->counters[0]);
6067 TAILQ_INIT(&pool->counters[1]);
6068 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
6069 rte_spinlock_lock(&cmng->pool_update_sl);
6070 pool->index = cmng->n_valid;
6071 if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
6073 rte_spinlock_unlock(&cmng->pool_update_sl);
6076 cmng->pools[pool->index] = pool;
6078 if (unlikely(fallback)) {
6079 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
6081 if (base < cmng->min_id)
6082 cmng->min_id = base;
6083 if (base > cmng->max_id)
6084 cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
6085 cmng->last_pool_idx = pool->index;
6087 rte_spinlock_unlock(&cmng->pool_update_sl);
6092 * Prepare a new counter and/or a new counter pool.
6095 * Pointer to the Ethernet device structure.
6096 * @param[out] cnt_free
6097 * Where to put the pointer of a new counter.
6099 * Whether the pool is for counter that was allocated for aging.
6102 * The counter pool pointer and @p cnt_free is set on success,
6103 * NULL otherwise and rte_errno is set.
6105 static struct mlx5_flow_counter_pool *
6106 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
6107 struct mlx5_flow_counter **cnt_free,
6110 struct mlx5_priv *priv = dev->data->dev_private;
6111 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6112 struct mlx5_flow_counter_pool *pool;
6113 struct mlx5_counters tmp_tq;
6114 struct mlx5_devx_obj *dcs = NULL;
6115 struct mlx5_flow_counter *cnt;
6116 enum mlx5_counter_type cnt_type =
6117 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6118 bool fallback = priv->sh->cmng.counter_fallback;
6122 /* bulk_bitmap must be 0 for single counter allocation. */
6123 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0);
6126 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
6128 pool = flow_dv_pool_create(dev, dcs, age);
6130 mlx5_devx_cmd_destroy(dcs);
6134 i = dcs->id % MLX5_COUNTERS_PER_POOL;
6135 cnt = MLX5_POOL_GET_CNT(pool, i);
6137 cnt->dcs_when_free = dcs;
6141 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
6143 rte_errno = ENODATA;
6146 pool = flow_dv_pool_create(dev, dcs, age);
6148 mlx5_devx_cmd_destroy(dcs);
6151 TAILQ_INIT(&tmp_tq);
6152 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
6153 cnt = MLX5_POOL_GET_CNT(pool, i);
6155 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
6157 rte_spinlock_lock(&cmng->csl[cnt_type]);
6158 TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
6159 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6160 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
6161 (*cnt_free)->pool = pool;
6166 * Allocate a flow counter.
6169 * Pointer to the Ethernet device structure.
6171 * Whether the counter was allocated for aging.
6174 * Index to flow counter on success, 0 otherwise and rte_errno is set.
6177 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
6179 struct mlx5_priv *priv = dev->data->dev_private;
6180 struct mlx5_flow_counter_pool *pool = NULL;
6181 struct mlx5_flow_counter *cnt_free = NULL;
6182 bool fallback = priv->sh->cmng.counter_fallback;
6183 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
6184 enum mlx5_counter_type cnt_type =
6185 age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
6188 if (!priv->sh->devx) {
6189 rte_errno = ENOTSUP;
6192 /* Get free counters from container. */
6193 rte_spinlock_lock(&cmng->csl[cnt_type]);
6194 cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
6196 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
6197 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6198 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
6200 pool = cnt_free->pool;
6202 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
6203 /* Create a DV counter action only in the first time usage. */
6204 if (!cnt_free->action) {
6206 struct mlx5_devx_obj *dcs;
6210 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
6211 dcs = pool->min_dcs;
6214 dcs = cnt_free->dcs_when_free;
6216 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
6223 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
6224 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
6225 /* Update the counter reset values. */
6226 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
6229 if (!fallback && !priv->sh->cmng.query_thread_on)
6230 /* Start the asynchronous batch query by the host thread. */
6231 mlx5_set_query_alarm(priv->sh);
6233 * When the count action isn't shared (by ID), shared_info field is
6234 * used for indirect action API's refcnt.
6235 * When the counter action is not shared neither by ID nor by indirect
6236 * action API, shared info must be 1.
6238 cnt_free->shared_info.refcnt = 1;
6242 cnt_free->pool = pool;
6244 cnt_free->dcs_when_free = cnt_free->dcs_when_active;
6245 rte_spinlock_lock(&cmng->csl[cnt_type]);
6246 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
6247 rte_spinlock_unlock(&cmng->csl[cnt_type]);
6253 * Get age param from counter index.
6256 * Pointer to the Ethernet device structure.
6257 * @param[in] counter
6258 * Index to the counter handler.
6261 * The aging parameter specified for the counter index.
6263 static struct mlx5_age_param*
6264 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
6267 struct mlx5_flow_counter *cnt;
6268 struct mlx5_flow_counter_pool *pool = NULL;
6270 flow_dv_counter_get_by_idx(dev, counter, &pool);
6271 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
6272 cnt = MLX5_POOL_GET_CNT(pool, counter);
6273 return MLX5_CNT_TO_AGE(cnt);
6277 * Remove a flow counter from aged counter list.
6280 * Pointer to the Ethernet device structure.
6281 * @param[in] counter
6282 * Index to the counter handler.
6284 * Pointer to the counter handler.
6287 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
6288 uint32_t counter, struct mlx5_flow_counter *cnt)
6290 struct mlx5_age_info *age_info;
6291 struct mlx5_age_param *age_param;
6292 struct mlx5_priv *priv = dev->data->dev_private;
6293 uint16_t expected = AGE_CANDIDATE;
6295 age_info = GET_PORT_AGE_INFO(priv);
6296 age_param = flow_dv_counter_idx_get_age(dev, counter);
6297 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
6298 AGE_FREE, false, __ATOMIC_RELAXED,
6299 __ATOMIC_RELAXED)) {
6301 * We need the lock even it is age timeout,
6302 * since counter may still in process.
6304 rte_spinlock_lock(&age_info->aged_sl);
6305 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
6306 rte_spinlock_unlock(&age_info->aged_sl);
6307 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
6312 * Release a flow counter.
6315 * Pointer to the Ethernet device structure.
6316 * @param[in] counter
6317 * Index to the counter handler.
6320 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
6322 struct mlx5_priv *priv = dev->data->dev_private;
6323 struct mlx5_flow_counter_pool *pool = NULL;
6324 struct mlx5_flow_counter *cnt;
6325 enum mlx5_counter_type cnt_type;
6329 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
6331 if (pool->is_aged) {
6332 flow_dv_counter_remove_from_age(dev, counter, cnt);
6335 * If the counter action is shared by indirect action API,
6336 * the atomic function reduces its references counter.
6337 * If after the reduction the action is still referenced, the
6338 * function returns here and does not release it.
6339 * When the counter action is not shared by
6340 * indirect action API, shared info is 1 before the reduction,
6341 * so this condition is failed and function doesn't return here.
6343 if (__atomic_sub_fetch(&cnt->shared_info.refcnt, 1,
6349 * Put the counter back to list to be updated in none fallback mode.
6350 * Currently, we are using two list alternately, while one is in query,
6351 * add the freed counter to the other list based on the pool query_gen
6352 * value. After query finishes, add counter the list to the global
6353 * container counter list. The list changes while query starts. In
6354 * this case, lock will not be needed as query callback and release
6355 * function both operate with the different list.
6357 if (!priv->sh->cmng.counter_fallback) {
6358 rte_spinlock_lock(&pool->csl);
6359 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
6360 rte_spinlock_unlock(&pool->csl);
6362 cnt->dcs_when_free = cnt->dcs_when_active;
6363 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
6364 MLX5_COUNTER_TYPE_ORIGIN;
6365 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
6366 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
6368 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
6373 * Resize a meter id container.
6376 * Pointer to the Ethernet device structure.
6379 * 0 on success, otherwise negative errno value and rte_errno is set.
6382 flow_dv_mtr_container_resize(struct rte_eth_dev *dev)
6384 struct mlx5_priv *priv = dev->data->dev_private;
6385 struct mlx5_aso_mtr_pools_mng *pools_mng =
6386 &priv->sh->mtrmng->pools_mng;
6387 void *old_pools = pools_mng->pools;
6388 uint32_t resize = pools_mng->n + MLX5_MTRS_CONTAINER_RESIZE;
6389 uint32_t mem_size = sizeof(struct mlx5_aso_mtr_pool *) * resize;
6390 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
6397 if (mlx5_aso_queue_init(priv->sh, ASO_OPC_MOD_POLICER)) {
6402 memcpy(pools, old_pools, pools_mng->n *
6403 sizeof(struct mlx5_aso_mtr_pool *));
6404 pools_mng->n = resize;
6405 pools_mng->pools = pools;
6407 mlx5_free(old_pools);
6412 * Prepare a new meter and/or a new meter pool.
6415 * Pointer to the Ethernet device structure.
6416 * @param[out] mtr_free
6417 * Where to put the pointer of a new meter.g.
6420 * The meter pool pointer and @mtr_free is set on success,
6421 * NULL otherwise and rte_errno is set.
6423 static struct mlx5_aso_mtr_pool *
6424 flow_dv_mtr_pool_create(struct rte_eth_dev *dev, struct mlx5_aso_mtr **mtr_free)
6426 struct mlx5_priv *priv = dev->data->dev_private;
6427 struct mlx5_aso_mtr_pools_mng *pools_mng = &priv->sh->mtrmng->pools_mng;
6428 struct mlx5_aso_mtr_pool *pool = NULL;
6429 struct mlx5_devx_obj *dcs = NULL;
6431 uint32_t log_obj_size;
6433 log_obj_size = rte_log2_u32(MLX5_ASO_MTRS_PER_POOL >> 1);
6434 dcs = mlx5_devx_cmd_create_flow_meter_aso_obj(priv->sh->cdev->ctx,
6435 priv->sh->cdev->pdn,
6438 rte_errno = ENODATA;
6441 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
6444 claim_zero(mlx5_devx_cmd_destroy(dcs));
6447 pool->devx_obj = dcs;
6448 rte_rwlock_write_lock(&pools_mng->resize_mtrwl);
6449 pool->index = pools_mng->n_valid;
6450 if (pool->index == pools_mng->n && flow_dv_mtr_container_resize(dev)) {
6452 claim_zero(mlx5_devx_cmd_destroy(dcs));
6453 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6456 pools_mng->pools[pool->index] = pool;
6457 pools_mng->n_valid++;
6458 rte_rwlock_write_unlock(&pools_mng->resize_mtrwl);
6459 for (i = 1; i < MLX5_ASO_MTRS_PER_POOL; ++i) {
6460 pool->mtrs[i].offset = i;
6461 LIST_INSERT_HEAD(&pools_mng->meters, &pool->mtrs[i], next);
6463 pool->mtrs[0].offset = 0;
6464 *mtr_free = &pool->mtrs[0];
6469 * Release a flow meter into pool.
6472 * Pointer to the Ethernet device structure.
6473 * @param[in] mtr_idx
6474 * Index to aso flow meter.
6477 flow_dv_aso_mtr_release_to_pool(struct rte_eth_dev *dev, uint32_t mtr_idx)
6479 struct mlx5_priv *priv = dev->data->dev_private;
6480 struct mlx5_aso_mtr_pools_mng *pools_mng =
6481 &priv->sh->mtrmng->pools_mng;
6482 struct mlx5_aso_mtr *aso_mtr = mlx5_aso_meter_by_idx(priv, mtr_idx);
6484 MLX5_ASSERT(aso_mtr);
6485 rte_spinlock_lock(&pools_mng->mtrsl);
6486 memset(&aso_mtr->fm, 0, sizeof(struct mlx5_flow_meter_info));
6487 aso_mtr->state = ASO_METER_FREE;
6488 LIST_INSERT_HEAD(&pools_mng->meters, aso_mtr, next);
6489 rte_spinlock_unlock(&pools_mng->mtrsl);
6493 * Allocate a aso flow meter.
6496 * Pointer to the Ethernet device structure.
6499 * Index to aso flow meter on success, 0 otherwise and rte_errno is set.
6502 flow_dv_mtr_alloc(struct rte_eth_dev *dev)
6504 struct mlx5_priv *priv = dev->data->dev_private;
6505 struct mlx5_aso_mtr *mtr_free = NULL;
6506 struct mlx5_aso_mtr_pools_mng *pools_mng =
6507 &priv->sh->mtrmng->pools_mng;
6508 struct mlx5_aso_mtr_pool *pool;
6509 uint32_t mtr_idx = 0;
6511 if (!priv->sh->devx) {
6512 rte_errno = ENOTSUP;
6515 /* Allocate the flow meter memory. */
6516 /* Get free meters from management. */
6517 rte_spinlock_lock(&pools_mng->mtrsl);
6518 mtr_free = LIST_FIRST(&pools_mng->meters);
6520 LIST_REMOVE(mtr_free, next);
6521 if (!mtr_free && !flow_dv_mtr_pool_create(dev, &mtr_free)) {
6522 rte_spinlock_unlock(&pools_mng->mtrsl);
6525 mtr_free->state = ASO_METER_WAIT;
6526 rte_spinlock_unlock(&pools_mng->mtrsl);
6527 pool = container_of(mtr_free,
6528 struct mlx5_aso_mtr_pool,
6529 mtrs[mtr_free->offset]);
6530 mtr_idx = MLX5_MAKE_MTR_IDX(pool->index, mtr_free->offset);
6531 if (!mtr_free->fm.meter_action) {
6532 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
6533 struct rte_flow_error error;
6536 reg_id = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &error);
6537 mtr_free->fm.meter_action =
6538 mlx5_glue->dv_create_flow_action_aso
6539 (priv->sh->rx_domain,
6540 pool->devx_obj->obj,
6542 (1 << MLX5_FLOW_COLOR_GREEN),
6544 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
6545 if (!mtr_free->fm.meter_action) {
6546 flow_dv_aso_mtr_release_to_pool(dev, mtr_idx);
6554 * Verify the @p attributes will be correctly understood by the NIC and store
6555 * them in the @p flow if everything is correct.
6558 * Pointer to dev struct.
6559 * @param[in] attributes
6560 * Pointer to flow attributes
6561 * @param[in] external
6562 * This flow rule is created by request external to PMD.
6564 * Pointer to error structure.
6567 * - 0 on success and non root table.
6568 * - 1 on success and root table.
6569 * - a negative errno value otherwise and rte_errno is set.
6572 flow_dv_validate_attributes(struct rte_eth_dev *dev,
6573 const struct mlx5_flow_tunnel *tunnel,
6574 const struct rte_flow_attr *attributes,
6575 const struct flow_grp_info *grp_info,
6576 struct rte_flow_error *error)
6578 struct mlx5_priv *priv = dev->data->dev_private;
6579 uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
6582 #ifndef HAVE_MLX5DV_DR
6583 RTE_SET_USED(tunnel);
6584 RTE_SET_USED(grp_info);
6585 if (attributes->group)
6586 return rte_flow_error_set(error, ENOTSUP,
6587 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
6589 "groups are not supported");
6593 ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
6598 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
6600 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
6601 attributes->priority > lowest_priority)
6602 return rte_flow_error_set(error, ENOTSUP,
6603 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
6605 "priority out of range");
6606 if (attributes->transfer) {
6607 if (!priv->config.dv_esw_en)
6608 return rte_flow_error_set
6610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6611 "E-Switch dr is not supported");
6612 if (!(priv->representor || priv->master))
6613 return rte_flow_error_set
6614 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6615 NULL, "E-Switch configuration can only be"
6616 " done by a master or a representor device");
6617 if (attributes->egress)
6618 return rte_flow_error_set
6620 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
6621 "egress is not supported");
6623 if (!(attributes->egress ^ attributes->ingress))
6624 return rte_flow_error_set(error, ENOTSUP,
6625 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
6626 "must specify exactly one of "
6627 "ingress or egress");
6632 validate_integrity_bits(const struct rte_flow_item_integrity *mask,
6633 int64_t pattern_flags, uint64_t l3_flags,
6634 uint64_t l4_flags, uint64_t ip4_flag,
6635 struct rte_flow_error *error)
6637 if (mask->l3_ok && !(pattern_flags & l3_flags))
6638 return rte_flow_error_set(error, EINVAL,
6639 RTE_FLOW_ERROR_TYPE_ITEM,
6640 NULL, "missing L3 protocol");
6642 if (mask->ipv4_csum_ok && !(pattern_flags & ip4_flag))
6643 return rte_flow_error_set(error, EINVAL,
6644 RTE_FLOW_ERROR_TYPE_ITEM,
6645 NULL, "missing IPv4 protocol");
6647 if ((mask->l4_ok || mask->l4_csum_ok) && !(pattern_flags & l4_flags))
6648 return rte_flow_error_set(error, EINVAL,
6649 RTE_FLOW_ERROR_TYPE_ITEM,
6650 NULL, "missing L4 protocol");
6656 flow_dv_validate_item_integrity_post(const struct
6657 rte_flow_item *integrity_items[2],
6658 int64_t pattern_flags,
6659 struct rte_flow_error *error)
6661 const struct rte_flow_item_integrity *mask;
6664 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
6665 mask = (typeof(mask))integrity_items[0]->mask;
6666 ret = validate_integrity_bits(mask, pattern_flags,
6667 MLX5_FLOW_LAYER_OUTER_L3,
6668 MLX5_FLOW_LAYER_OUTER_L4,
6669 MLX5_FLOW_LAYER_OUTER_L3_IPV4,
6674 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
6675 mask = (typeof(mask))integrity_items[1]->mask;
6676 ret = validate_integrity_bits(mask, pattern_flags,
6677 MLX5_FLOW_LAYER_INNER_L3,
6678 MLX5_FLOW_LAYER_INNER_L4,
6679 MLX5_FLOW_LAYER_INNER_L3_IPV4,
6688 flow_dv_validate_item_integrity(struct rte_eth_dev *dev,
6689 const struct rte_flow_item *integrity_item,
6690 uint64_t pattern_flags, uint64_t *last_item,
6691 const struct rte_flow_item *integrity_items[2],
6692 struct rte_flow_error *error)
6694 struct mlx5_priv *priv = dev->data->dev_private;
6695 const struct rte_flow_item_integrity *mask = (typeof(mask))
6696 integrity_item->mask;
6697 const struct rte_flow_item_integrity *spec = (typeof(spec))
6698 integrity_item->spec;
6700 if (!priv->config.hca_attr.pkt_integrity_match)
6701 return rte_flow_error_set(error, ENOTSUP,
6702 RTE_FLOW_ERROR_TYPE_ITEM,
6704 "packet integrity integrity_item not supported");
6706 return rte_flow_error_set(error, ENOTSUP,
6707 RTE_FLOW_ERROR_TYPE_ITEM,
6709 "no spec for integrity item");
6711 mask = &rte_flow_item_integrity_mask;
6712 if (!mlx5_validate_integrity_item(mask))
6713 return rte_flow_error_set(error, ENOTSUP,
6714 RTE_FLOW_ERROR_TYPE_ITEM,
6716 "unsupported integrity filter");
6717 if (spec->level > 1) {
6718 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY)
6719 return rte_flow_error_set
6721 RTE_FLOW_ERROR_TYPE_ITEM,
6722 NULL, "multiple inner integrity items not supported");
6723 integrity_items[1] = integrity_item;
6724 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
6726 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY)
6727 return rte_flow_error_set
6729 RTE_FLOW_ERROR_TYPE_ITEM,
6730 NULL, "multiple outer integrity items not supported");
6731 integrity_items[0] = integrity_item;
6732 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
6738 flow_dv_validate_item_flex(struct rte_eth_dev *dev,
6739 const struct rte_flow_item *item,
6740 uint64_t item_flags,
6741 uint64_t *last_item,
6743 struct rte_flow_error *error)
6745 const struct rte_flow_item_flex *flow_spec = item->spec;
6746 const struct rte_flow_item_flex *flow_mask = item->mask;
6747 struct mlx5_flex_item *flex;
6750 return rte_flow_error_set(error, EINVAL,
6751 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6752 "flex flow item spec cannot be NULL");
6754 return rte_flow_error_set(error, EINVAL,
6755 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6756 "flex flow item mask cannot be NULL");
6758 return rte_flow_error_set(error, ENOTSUP,
6759 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6760 "flex flow item last not supported");
6761 if (mlx5_flex_acquire_index(dev, flow_spec->handle, false) < 0)
6762 return rte_flow_error_set(error, EINVAL,
6763 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
6764 "invalid flex flow item handle");
6765 flex = (struct mlx5_flex_item *)flow_spec->handle;
6766 switch (flex->tunnel_mode) {
6767 case FLEX_TUNNEL_MODE_SINGLE:
6769 (MLX5_FLOW_ITEM_OUTER_FLEX | MLX5_FLOW_ITEM_INNER_FLEX))
6770 rte_flow_error_set(error, EINVAL,
6771 RTE_FLOW_ERROR_TYPE_ITEM,
6772 NULL, "multiple flex items not supported");
6774 case FLEX_TUNNEL_MODE_OUTER:
6776 rte_flow_error_set(error, EINVAL,
6777 RTE_FLOW_ERROR_TYPE_ITEM,
6778 NULL, "inner flex item was not configured");
6779 if (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX)
6780 rte_flow_error_set(error, ENOTSUP,
6781 RTE_FLOW_ERROR_TYPE_ITEM,
6782 NULL, "multiple flex items not supported");
6784 case FLEX_TUNNEL_MODE_INNER:
6786 rte_flow_error_set(error, EINVAL,
6787 RTE_FLOW_ERROR_TYPE_ITEM,
6788 NULL, "outer flex item was not configured");
6789 if (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)
6790 rte_flow_error_set(error, EINVAL,
6791 RTE_FLOW_ERROR_TYPE_ITEM,
6792 NULL, "multiple flex items not supported");
6794 case FLEX_TUNNEL_MODE_MULTI:
6795 if ((is_inner && (item_flags & MLX5_FLOW_ITEM_INNER_FLEX)) ||
6796 (!is_inner && (item_flags & MLX5_FLOW_ITEM_OUTER_FLEX))) {
6797 rte_flow_error_set(error, EINVAL,
6798 RTE_FLOW_ERROR_TYPE_ITEM,
6799 NULL, "multiple flex items not supported");
6802 case FLEX_TUNNEL_MODE_TUNNEL:
6803 if (is_inner || (item_flags & MLX5_FLOW_ITEM_FLEX_TUNNEL))
6804 rte_flow_error_set(error, EINVAL,
6805 RTE_FLOW_ERROR_TYPE_ITEM,
6806 NULL, "multiple flex tunnel items not supported");
6809 rte_flow_error_set(error, EINVAL,
6810 RTE_FLOW_ERROR_TYPE_ITEM,
6811 NULL, "invalid flex item configuration");
6813 *last_item = flex->tunnel_mode == FLEX_TUNNEL_MODE_TUNNEL ?
6814 MLX5_FLOW_ITEM_FLEX_TUNNEL : is_inner ?
6815 MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
6820 * Internal validation function. For validating both actions and items.
6823 * Pointer to the rte_eth_dev structure.
6825 * Pointer to the flow attributes.
6827 * Pointer to the list of items.
6828 * @param[in] actions
6829 * Pointer to the list of actions.
6830 * @param[in] external
6831 * This flow rule is created by request external to PMD.
6832 * @param[in] hairpin
6833 * Number of hairpin TX actions, 0 means classic flow.
6835 * Pointer to the error structure.
6838 * 0 on success, a negative errno value otherwise and rte_errno is set.
6841 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6842 const struct rte_flow_item items[],
6843 const struct rte_flow_action actions[],
6844 bool external, int hairpin, struct rte_flow_error *error)
6847 uint64_t action_flags = 0;
6848 uint64_t item_flags = 0;
6849 uint64_t last_item = 0;
6850 uint8_t next_protocol = 0xff;
6851 uint16_t ether_type = 0;
6853 uint8_t item_ipv6_proto = 0;
6854 int fdb_mirror_limit = 0;
6855 int modify_after_mirror = 0;
6856 const struct rte_flow_item *geneve_item = NULL;
6857 const struct rte_flow_item *gre_item = NULL;
6858 const struct rte_flow_item *gtp_item = NULL;
6859 const struct rte_flow_action_raw_decap *decap;
6860 const struct rte_flow_action_raw_encap *encap;
6861 const struct rte_flow_action_rss *rss = NULL;
6862 const struct rte_flow_action_rss *sample_rss = NULL;
6863 const struct rte_flow_action_count *sample_count = NULL;
6864 const struct rte_flow_item_tcp nic_tcp_mask = {
6867 .src_port = RTE_BE16(UINT16_MAX),
6868 .dst_port = RTE_BE16(UINT16_MAX),
6871 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6874 "\xff\xff\xff\xff\xff\xff\xff\xff"
6875 "\xff\xff\xff\xff\xff\xff\xff\xff",
6877 "\xff\xff\xff\xff\xff\xff\xff\xff"
6878 "\xff\xff\xff\xff\xff\xff\xff\xff",
6879 .vtc_flow = RTE_BE32(0xffffffff),
6885 const struct rte_flow_item_ecpri nic_ecpri_mask = {
6889 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6893 .dummy[0] = 0xffffffff,
6896 struct mlx5_priv *priv = dev->data->dev_private;
6897 struct mlx5_dev_config *dev_conf = &priv->config;
6898 uint16_t queue_index = 0xFFFF;
6899 const struct rte_flow_item_vlan *vlan_m = NULL;
6900 uint32_t rw_act_num = 0;
6902 const struct mlx5_flow_tunnel *tunnel;
6903 enum mlx5_tof_rule_type tof_rule_type;
6904 struct flow_grp_info grp_info = {
6905 .external = !!external,
6906 .transfer = !!attr->transfer,
6907 .fdb_def_rule = !!priv->fdb_def_rule,
6908 .std_tbl_fix = true,
6910 const struct rte_eth_hairpin_conf *conf;
6911 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
6912 const struct rte_flow_item *port_id_item = NULL;
6913 bool def_policy = false;
6914 uint16_t udp_dport = 0;
6918 tunnel = is_tunnel_offload_active(dev) ?
6919 mlx5_get_tof(items, actions, &tof_rule_type) : NULL;
6921 if (!priv->config.dv_flow_en)
6922 return rte_flow_error_set
6924 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6925 NULL, "tunnel offload requires DV flow interface");
6926 if (priv->representor)
6927 return rte_flow_error_set
6929 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6930 NULL, "decap not supported for VF representor");
6931 if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_SET_RULE)
6932 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6933 else if (tof_rule_type == MLX5_TUNNEL_OFFLOAD_MATCH_RULE)
6934 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6935 MLX5_FLOW_ACTION_DECAP;
6936 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6937 (dev, attr, tunnel, tof_rule_type);
6939 ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6942 is_root = (uint64_t)ret;
6943 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6944 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6945 int type = items->type;
6947 if (!mlx5_flow_os_item_supported(type))
6948 return rte_flow_error_set(error, ENOTSUP,
6949 RTE_FLOW_ERROR_TYPE_ITEM,
6950 NULL, "item not supported");
6952 case RTE_FLOW_ITEM_TYPE_VOID:
6954 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6955 ret = flow_dv_validate_item_port_id
6956 (dev, items, attr, item_flags, error);
6959 last_item = MLX5_FLOW_ITEM_PORT_ID;
6960 port_id_item = items;
6962 case RTE_FLOW_ITEM_TYPE_ETH:
6963 ret = mlx5_flow_validate_item_eth(items, item_flags,
6967 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6968 MLX5_FLOW_LAYER_OUTER_L2;
6969 if (items->mask != NULL && items->spec != NULL) {
6971 ((const struct rte_flow_item_eth *)
6974 ((const struct rte_flow_item_eth *)
6976 ether_type = rte_be_to_cpu_16(ether_type);
6981 case RTE_FLOW_ITEM_TYPE_VLAN:
6982 ret = flow_dv_validate_item_vlan(items, item_flags,
6986 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6987 MLX5_FLOW_LAYER_OUTER_VLAN;
6988 if (items->mask != NULL && items->spec != NULL) {
6990 ((const struct rte_flow_item_vlan *)
6991 items->spec)->inner_type;
6993 ((const struct rte_flow_item_vlan *)
6994 items->mask)->inner_type;
6995 ether_type = rte_be_to_cpu_16(ether_type);
6999 /* Store outer VLAN mask for of_push_vlan action. */
7001 vlan_m = items->mask;
7003 case RTE_FLOW_ITEM_TYPE_IPV4:
7004 mlx5_flow_tunnel_ip_check(items, next_protocol,
7005 &item_flags, &tunnel);
7006 ret = flow_dv_validate_item_ipv4(dev, items, item_flags,
7007 last_item, ether_type,
7011 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7012 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7013 if (items->mask != NULL &&
7014 ((const struct rte_flow_item_ipv4 *)
7015 items->mask)->hdr.next_proto_id) {
7017 ((const struct rte_flow_item_ipv4 *)
7018 (items->spec))->hdr.next_proto_id;
7020 ((const struct rte_flow_item_ipv4 *)
7021 (items->mask))->hdr.next_proto_id;
7023 /* Reset for inner layer. */
7024 next_protocol = 0xff;
7027 case RTE_FLOW_ITEM_TYPE_IPV6:
7028 mlx5_flow_tunnel_ip_check(items, next_protocol,
7029 &item_flags, &tunnel);
7030 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
7037 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7038 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7039 if (items->mask != NULL &&
7040 ((const struct rte_flow_item_ipv6 *)
7041 items->mask)->hdr.proto) {
7043 ((const struct rte_flow_item_ipv6 *)
7044 items->spec)->hdr.proto;
7046 ((const struct rte_flow_item_ipv6 *)
7047 items->spec)->hdr.proto;
7049 ((const struct rte_flow_item_ipv6 *)
7050 items->mask)->hdr.proto;
7052 /* Reset for inner layer. */
7053 next_protocol = 0xff;
7056 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
7057 ret = flow_dv_validate_item_ipv6_frag_ext(items,
7062 last_item = tunnel ?
7063 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
7064 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
7065 if (items->mask != NULL &&
7066 ((const struct rte_flow_item_ipv6_frag_ext *)
7067 items->mask)->hdr.next_header) {
7069 ((const struct rte_flow_item_ipv6_frag_ext *)
7070 items->spec)->hdr.next_header;
7072 ((const struct rte_flow_item_ipv6_frag_ext *)
7073 items->mask)->hdr.next_header;
7075 /* Reset for inner layer. */
7076 next_protocol = 0xff;
7079 case RTE_FLOW_ITEM_TYPE_TCP:
7080 ret = mlx5_flow_validate_item_tcp
7087 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7088 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7090 case RTE_FLOW_ITEM_TYPE_UDP:
7091 ret = mlx5_flow_validate_item_udp(items, item_flags,
7094 const struct rte_flow_item_udp *spec = items->spec;
7095 const struct rte_flow_item_udp *mask = items->mask;
7097 mask = &rte_flow_item_udp_mask;
7099 udp_dport = rte_be_to_cpu_16
7100 (spec->hdr.dst_port &
7101 mask->hdr.dst_port);
7104 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7105 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7107 case RTE_FLOW_ITEM_TYPE_GRE:
7108 ret = mlx5_flow_validate_item_gre(items, item_flags,
7109 next_protocol, error);
7113 last_item = MLX5_FLOW_LAYER_GRE;
7115 case RTE_FLOW_ITEM_TYPE_NVGRE:
7116 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
7121 last_item = MLX5_FLOW_LAYER_NVGRE;
7123 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7124 ret = mlx5_flow_validate_item_gre_key
7125 (items, item_flags, gre_item, error);
7128 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7130 case RTE_FLOW_ITEM_TYPE_VXLAN:
7131 ret = mlx5_flow_validate_item_vxlan(dev, udp_dport,
7136 last_item = MLX5_FLOW_LAYER_VXLAN;
7138 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7139 ret = mlx5_flow_validate_item_vxlan_gpe(items,
7144 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7146 case RTE_FLOW_ITEM_TYPE_GENEVE:
7147 ret = mlx5_flow_validate_item_geneve(items,
7152 geneve_item = items;
7153 last_item = MLX5_FLOW_LAYER_GENEVE;
7155 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
7156 ret = mlx5_flow_validate_item_geneve_opt(items,
7163 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
7165 case RTE_FLOW_ITEM_TYPE_MPLS:
7166 ret = mlx5_flow_validate_item_mpls(dev, items,
7171 last_item = MLX5_FLOW_LAYER_MPLS;
7174 case RTE_FLOW_ITEM_TYPE_MARK:
7175 ret = flow_dv_validate_item_mark(dev, items, attr,
7179 last_item = MLX5_FLOW_ITEM_MARK;
7181 case RTE_FLOW_ITEM_TYPE_META:
7182 ret = flow_dv_validate_item_meta(dev, items, attr,
7186 last_item = MLX5_FLOW_ITEM_METADATA;
7188 case RTE_FLOW_ITEM_TYPE_ICMP:
7189 ret = mlx5_flow_validate_item_icmp(items, item_flags,
7194 last_item = MLX5_FLOW_LAYER_ICMP;
7196 case RTE_FLOW_ITEM_TYPE_ICMP6:
7197 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
7202 item_ipv6_proto = IPPROTO_ICMPV6;
7203 last_item = MLX5_FLOW_LAYER_ICMP6;
7205 case RTE_FLOW_ITEM_TYPE_TAG:
7206 ret = flow_dv_validate_item_tag(dev, items,
7210 last_item = MLX5_FLOW_ITEM_TAG;
7212 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7213 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7215 case RTE_FLOW_ITEM_TYPE_GTP:
7216 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
7221 last_item = MLX5_FLOW_LAYER_GTP;
7223 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
7224 ret = flow_dv_validate_item_gtp_psc(items, last_item,
7229 last_item = MLX5_FLOW_LAYER_GTP_PSC;
7231 case RTE_FLOW_ITEM_TYPE_ECPRI:
7232 /* Capacity will be checked in the translate stage. */
7233 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
7240 last_item = MLX5_FLOW_LAYER_ECPRI;
7242 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
7243 ret = flow_dv_validate_item_integrity(dev, items,
7251 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
7252 ret = flow_dv_validate_item_aso_ct(dev, items,
7253 &item_flags, error);
7257 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
7258 /* tunnel offload item was processed before
7259 * list it here as a supported type
7262 case RTE_FLOW_ITEM_TYPE_FLEX:
7263 ret = flow_dv_validate_item_flex(dev, items, item_flags,
7265 tunnel != 0, error);
7270 return rte_flow_error_set(error, ENOTSUP,
7271 RTE_FLOW_ERROR_TYPE_ITEM,
7272 NULL, "item not supported");
7274 item_flags |= last_item;
7276 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
7277 ret = flow_dv_validate_item_integrity_post(integrity_items,
7282 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
7283 int type = actions->type;
7284 bool shared_count = false;
7286 if (!mlx5_flow_os_action_supported(type))
7287 return rte_flow_error_set(error, ENOTSUP,
7288 RTE_FLOW_ERROR_TYPE_ACTION,
7290 "action not supported");
7291 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
7292 return rte_flow_error_set(error, ENOTSUP,
7293 RTE_FLOW_ERROR_TYPE_ACTION,
7294 actions, "too many actions");
7296 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
7297 return rte_flow_error_set(error, ENOTSUP,
7298 RTE_FLOW_ERROR_TYPE_ACTION,
7299 NULL, "meter action with policy "
7300 "must be the last action");
7302 case RTE_FLOW_ACTION_TYPE_VOID:
7304 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7305 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
7306 ret = flow_dv_validate_action_port_id(dev,
7313 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7316 case RTE_FLOW_ACTION_TYPE_FLAG:
7317 ret = flow_dv_validate_action_flag(dev, action_flags,
7321 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7322 /* Count all modify-header actions as one. */
7323 if (!(action_flags &
7324 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7326 action_flags |= MLX5_FLOW_ACTION_FLAG |
7327 MLX5_FLOW_ACTION_MARK_EXT;
7328 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7329 modify_after_mirror = 1;
7332 action_flags |= MLX5_FLOW_ACTION_FLAG;
7335 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7337 case RTE_FLOW_ACTION_TYPE_MARK:
7338 ret = flow_dv_validate_action_mark(dev, actions,
7343 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7344 /* Count all modify-header actions as one. */
7345 if (!(action_flags &
7346 MLX5_FLOW_MODIFY_HDR_ACTIONS))
7348 action_flags |= MLX5_FLOW_ACTION_MARK |
7349 MLX5_FLOW_ACTION_MARK_EXT;
7350 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7351 modify_after_mirror = 1;
7353 action_flags |= MLX5_FLOW_ACTION_MARK;
7356 rw_act_num += MLX5_ACT_NUM_SET_MARK;
7358 case RTE_FLOW_ACTION_TYPE_SET_META:
7359 ret = flow_dv_validate_action_set_meta(dev, actions,
7364 /* Count all modify-header actions as one action. */
7365 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7367 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7368 modify_after_mirror = 1;
7369 action_flags |= MLX5_FLOW_ACTION_SET_META;
7370 rw_act_num += MLX5_ACT_NUM_SET_META;
7372 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7373 ret = flow_dv_validate_action_set_tag(dev, actions,
7378 /* Count all modify-header actions as one action. */
7379 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7381 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7382 modify_after_mirror = 1;
7383 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7384 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7386 case RTE_FLOW_ACTION_TYPE_DROP:
7387 ret = mlx5_flow_validate_action_drop(action_flags,
7391 action_flags |= MLX5_FLOW_ACTION_DROP;
7394 case RTE_FLOW_ACTION_TYPE_QUEUE:
7395 ret = mlx5_flow_validate_action_queue(actions,
7400 queue_index = ((const struct rte_flow_action_queue *)
7401 (actions->conf))->index;
7402 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7405 case RTE_FLOW_ACTION_TYPE_RSS:
7406 rss = actions->conf;
7407 ret = mlx5_flow_validate_action_rss(actions,
7413 if (rss && sample_rss &&
7414 (sample_rss->level != rss->level ||
7415 sample_rss->types != rss->types))
7416 return rte_flow_error_set(error, ENOTSUP,
7417 RTE_FLOW_ERROR_TYPE_ACTION,
7419 "Can't use the different RSS types "
7420 "or level in the same flow");
7421 if (rss != NULL && rss->queue_num)
7422 queue_index = rss->queue[0];
7423 action_flags |= MLX5_FLOW_ACTION_RSS;
7426 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
7428 mlx5_flow_validate_action_default_miss(action_flags,
7432 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
7435 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
7436 shared_count = true;
7438 case RTE_FLOW_ACTION_TYPE_COUNT:
7439 ret = flow_dv_validate_action_count(dev, shared_count,
7444 action_flags |= MLX5_FLOW_ACTION_COUNT;
7447 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7448 if (flow_dv_validate_action_pop_vlan(dev,
7454 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7455 modify_after_mirror = 1;
7456 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7459 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7460 ret = flow_dv_validate_action_push_vlan(dev,
7467 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7468 modify_after_mirror = 1;
7469 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7472 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7473 ret = flow_dv_validate_action_set_vlan_pcp
7474 (action_flags, actions, error);
7477 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7478 modify_after_mirror = 1;
7479 /* Count PCP with push_vlan command. */
7480 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
7482 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7483 ret = flow_dv_validate_action_set_vlan_vid
7484 (item_flags, action_flags,
7488 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7489 modify_after_mirror = 1;
7490 /* Count VID with push_vlan command. */
7491 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7492 rw_act_num += MLX5_ACT_NUM_MDF_VID;
7494 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7495 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7496 ret = flow_dv_validate_action_l2_encap(dev,
7502 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7505 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7506 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7507 ret = flow_dv_validate_action_decap(dev, action_flags,
7508 actions, item_flags,
7512 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7513 modify_after_mirror = 1;
7514 action_flags |= MLX5_FLOW_ACTION_DECAP;
7517 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7518 ret = flow_dv_validate_action_raw_encap_decap
7519 (dev, NULL, actions->conf, attr, &action_flags,
7520 &actions_n, actions, item_flags, error);
7524 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7525 decap = actions->conf;
7526 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
7528 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7532 encap = actions->conf;
7534 ret = flow_dv_validate_action_raw_encap_decap
7536 decap ? decap : &empty_decap, encap,
7537 attr, &action_flags, &actions_n,
7538 actions, item_flags, error);
7541 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7542 (action_flags & MLX5_FLOW_ACTION_DECAP))
7543 modify_after_mirror = 1;
7545 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7546 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7547 ret = flow_dv_validate_action_modify_mac(action_flags,
7553 /* Count all modify-header actions as one action. */
7554 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7556 action_flags |= actions->type ==
7557 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7558 MLX5_FLOW_ACTION_SET_MAC_SRC :
7559 MLX5_FLOW_ACTION_SET_MAC_DST;
7560 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7561 modify_after_mirror = 1;
7563 * Even if the source and destination MAC addresses have
7564 * overlap in the header with 4B alignment, the convert
7565 * function will handle them separately and 4 SW actions
7566 * will be created. And 2 actions will be added each
7567 * time no matter how many bytes of address will be set.
7569 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
7571 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7572 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7573 ret = flow_dv_validate_action_modify_ipv4(action_flags,
7579 /* Count all modify-header actions as one action. */
7580 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7582 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7583 modify_after_mirror = 1;
7584 action_flags |= actions->type ==
7585 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7586 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7587 MLX5_FLOW_ACTION_SET_IPV4_DST;
7588 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
7590 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7591 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7592 ret = flow_dv_validate_action_modify_ipv6(action_flags,
7598 if (item_ipv6_proto == IPPROTO_ICMPV6)
7599 return rte_flow_error_set(error, ENOTSUP,
7600 RTE_FLOW_ERROR_TYPE_ACTION,
7602 "Can't change header "
7603 "with ICMPv6 proto");
7604 /* Count all modify-header actions as one action. */
7605 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7607 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7608 modify_after_mirror = 1;
7609 action_flags |= actions->type ==
7610 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7611 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7612 MLX5_FLOW_ACTION_SET_IPV6_DST;
7613 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
7615 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7616 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7617 ret = flow_dv_validate_action_modify_tp(action_flags,
7623 /* Count all modify-header actions as one action. */
7624 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7626 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7627 modify_after_mirror = 1;
7628 action_flags |= actions->type ==
7629 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7630 MLX5_FLOW_ACTION_SET_TP_SRC :
7631 MLX5_FLOW_ACTION_SET_TP_DST;
7632 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
7634 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7635 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7636 ret = flow_dv_validate_action_modify_ttl(action_flags,
7642 /* Count all modify-header actions as one action. */
7643 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7645 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7646 modify_after_mirror = 1;
7647 action_flags |= actions->type ==
7648 RTE_FLOW_ACTION_TYPE_SET_TTL ?
7649 MLX5_FLOW_ACTION_SET_TTL :
7650 MLX5_FLOW_ACTION_DEC_TTL;
7651 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
7653 case RTE_FLOW_ACTION_TYPE_JUMP:
7654 ret = flow_dv_validate_action_jump(dev, tunnel, actions,
7660 if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
7662 return rte_flow_error_set(error, EINVAL,
7663 RTE_FLOW_ERROR_TYPE_ACTION,
7665 "sample and jump action combination is not supported");
7667 action_flags |= MLX5_FLOW_ACTION_JUMP;
7669 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7670 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7671 ret = flow_dv_validate_action_modify_tcp_seq
7678 /* Count all modify-header actions as one action. */
7679 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7681 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7682 modify_after_mirror = 1;
7683 action_flags |= actions->type ==
7684 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7685 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7686 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7687 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
7689 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7690 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7691 ret = flow_dv_validate_action_modify_tcp_ack
7698 /* Count all modify-header actions as one action. */
7699 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7701 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7702 modify_after_mirror = 1;
7703 action_flags |= actions->type ==
7704 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7705 MLX5_FLOW_ACTION_INC_TCP_ACK :
7706 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7707 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
7709 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7711 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7712 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7713 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7715 case RTE_FLOW_ACTION_TYPE_METER:
7716 ret = mlx5_flow_validate_action_meter(dev,
7725 action_flags |= MLX5_FLOW_ACTION_METER;
7728 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
7730 /* Meter action will add one more TAG action. */
7731 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7733 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
7734 if (!attr->transfer && !attr->group)
7735 return rte_flow_error_set(error, ENOTSUP,
7736 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7738 "Shared ASO age action is not supported for group 0");
7739 if (action_flags & MLX5_FLOW_ACTION_AGE)
7740 return rte_flow_error_set
7742 RTE_FLOW_ERROR_TYPE_ACTION,
7744 "duplicate age actions set");
7745 action_flags |= MLX5_FLOW_ACTION_AGE;
7748 case RTE_FLOW_ACTION_TYPE_AGE:
7749 ret = flow_dv_validate_action_age(action_flags,
7755 * Validate the regular AGE action (using counter)
7756 * mutual exclusion with share counter actions.
7758 if (!priv->sh->flow_hit_aso_en) {
7760 return rte_flow_error_set
7762 RTE_FLOW_ERROR_TYPE_ACTION,
7764 "old age and shared count combination is not supported");
7766 return rte_flow_error_set
7768 RTE_FLOW_ERROR_TYPE_ACTION,
7770 "old age action and count must be in the same sub flow");
7772 action_flags |= MLX5_FLOW_ACTION_AGE;
7775 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7776 ret = flow_dv_validate_action_modify_ipv4_dscp
7783 /* Count all modify-header actions as one action. */
7784 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7786 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7787 modify_after_mirror = 1;
7788 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7789 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7791 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7792 ret = flow_dv_validate_action_modify_ipv6_dscp
7799 /* Count all modify-header actions as one action. */
7800 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7802 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7803 modify_after_mirror = 1;
7804 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7805 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
7807 case RTE_FLOW_ACTION_TYPE_SAMPLE:
7808 ret = flow_dv_validate_action_sample(&action_flags,
7817 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
7820 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
7821 ret = flow_dv_validate_action_modify_field(dev,
7828 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
7829 modify_after_mirror = 1;
7830 /* Count all modify-header actions as one action. */
7831 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
7833 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
7836 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
7837 ret = flow_dv_validate_action_aso_ct(dev, action_flags,
7842 action_flags |= MLX5_FLOW_ACTION_CT;
7844 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
7845 /* tunnel offload action was processed before
7846 * list it here as a supported type
7850 return rte_flow_error_set(error, ENOTSUP,
7851 RTE_FLOW_ERROR_TYPE_ACTION,
7853 "action not supported");
7857 * Validate actions in flow rules
7858 * - Explicit decap action is prohibited by the tunnel offload API.
7859 * - Drop action in tunnel steer rule is prohibited by the API.
7860 * - Application cannot use MARK action because it's value can mask
7861 * tunnel default miss nitification.
7862 * - JUMP in tunnel match rule has no support in current PMD
7864 * - TAG & META are reserved for future uses.
7866 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
7867 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP |
7868 MLX5_FLOW_ACTION_MARK |
7869 MLX5_FLOW_ACTION_SET_TAG |
7870 MLX5_FLOW_ACTION_SET_META |
7871 MLX5_FLOW_ACTION_DROP;
7873 if (action_flags & bad_actions_mask)
7874 return rte_flow_error_set
7876 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7877 "Invalid RTE action in tunnel "
7879 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
7880 return rte_flow_error_set
7882 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7883 "tunnel set decap rule must terminate "
7886 return rte_flow_error_set
7888 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7889 "tunnel flows for ingress traffic only");
7891 if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
7892 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP |
7893 MLX5_FLOW_ACTION_MARK |
7894 MLX5_FLOW_ACTION_SET_TAG |
7895 MLX5_FLOW_ACTION_SET_META;
7897 if (action_flags & bad_actions_mask)
7898 return rte_flow_error_set
7900 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7901 "Invalid RTE action in tunnel "
7905 * Validate the drop action mutual exclusion with other actions.
7906 * Drop action is mutually-exclusive with any other action, except for
7908 * Drop action compatibility with tunnel offload was already validated.
7910 if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7911 MLX5_FLOW_ACTION_TUNNEL_MATCH));
7912 else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7913 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7914 return rte_flow_error_set(error, EINVAL,
7915 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7916 "Drop action is mutually-exclusive "
7917 "with any other action, except for "
7919 /* Eswitch has few restrictions on using items and actions */
7920 if (attr->transfer) {
7921 if (!mlx5_flow_ext_mreg_supported(dev) &&
7922 action_flags & MLX5_FLOW_ACTION_FLAG)
7923 return rte_flow_error_set(error, ENOTSUP,
7924 RTE_FLOW_ERROR_TYPE_ACTION,
7926 "unsupported action FLAG");
7927 if (!mlx5_flow_ext_mreg_supported(dev) &&
7928 action_flags & MLX5_FLOW_ACTION_MARK)
7929 return rte_flow_error_set(error, ENOTSUP,
7930 RTE_FLOW_ERROR_TYPE_ACTION,
7932 "unsupported action MARK");
7933 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7934 return rte_flow_error_set(error, ENOTSUP,
7935 RTE_FLOW_ERROR_TYPE_ACTION,
7937 "unsupported action QUEUE");
7938 if (action_flags & MLX5_FLOW_ACTION_RSS)
7939 return rte_flow_error_set(error, ENOTSUP,
7940 RTE_FLOW_ERROR_TYPE_ACTION,
7942 "unsupported action RSS");
7943 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7944 return rte_flow_error_set(error, EINVAL,
7945 RTE_FLOW_ERROR_TYPE_ACTION,
7947 "no fate action is found");
7949 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7950 return rte_flow_error_set(error, EINVAL,
7951 RTE_FLOW_ERROR_TYPE_ACTION,
7953 "no fate action is found");
7956 * Continue validation for Xcap and VLAN actions.
7957 * If hairpin is working in explicit TX rule mode, there is no actions
7958 * splitting and the validation of hairpin ingress flow should be the
7959 * same as other standard flows.
7961 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7962 MLX5_FLOW_VLAN_ACTIONS)) &&
7963 (queue_index == 0xFFFF ||
7964 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7965 ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7966 conf->tx_explicit != 0))) {
7967 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7968 MLX5_FLOW_XCAP_ACTIONS)
7969 return rte_flow_error_set(error, ENOTSUP,
7970 RTE_FLOW_ERROR_TYPE_ACTION,
7971 NULL, "encap and decap "
7972 "combination aren't supported");
7973 if (!attr->transfer && attr->ingress) {
7974 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7975 return rte_flow_error_set
7977 RTE_FLOW_ERROR_TYPE_ACTION,
7978 NULL, "encap is not supported"
7979 " for ingress traffic");
7980 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7981 return rte_flow_error_set
7983 RTE_FLOW_ERROR_TYPE_ACTION,
7984 NULL, "push VLAN action not "
7985 "supported for ingress");
7986 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7987 MLX5_FLOW_VLAN_ACTIONS)
7988 return rte_flow_error_set
7990 RTE_FLOW_ERROR_TYPE_ACTION,
7991 NULL, "no support for "
7992 "multiple VLAN actions");
7995 if (action_flags & MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY) {
7996 if ((action_flags & (MLX5_FLOW_FATE_ACTIONS &
7997 ~MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)) &&
7999 return rte_flow_error_set
8001 RTE_FLOW_ERROR_TYPE_ACTION,
8002 NULL, "fate action not supported for "
8003 "meter with policy");
8005 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
8006 return rte_flow_error_set
8008 RTE_FLOW_ERROR_TYPE_ACTION,
8009 NULL, "modify header action in egress "
8010 "cannot be done before meter action");
8011 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
8012 return rte_flow_error_set
8014 RTE_FLOW_ERROR_TYPE_ACTION,
8015 NULL, "encap action in egress "
8016 "cannot be done before meter action");
8017 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8018 return rte_flow_error_set
8020 RTE_FLOW_ERROR_TYPE_ACTION,
8021 NULL, "push vlan action in egress "
8022 "cannot be done before meter action");
8026 * Hairpin flow will add one more TAG action in TX implicit mode.
8027 * In TX explicit mode, there will be no hairpin flow ID.
8030 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8031 /* extra metadata enabled: one more TAG action will be add. */
8032 if (dev_conf->dv_flow_en &&
8033 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
8034 mlx5_flow_ext_mreg_supported(dev))
8035 rw_act_num += MLX5_ACT_NUM_SET_TAG;
8037 flow_dv_modify_hdr_action_max(dev, is_root)) {
8038 return rte_flow_error_set(error, ENOTSUP,
8039 RTE_FLOW_ERROR_TYPE_ACTION,
8040 NULL, "too many header modify"
8041 " actions to support");
8043 /* Eswitch egress mirror and modify flow has limitation on CX5 */
8044 if (fdb_mirror_limit && modify_after_mirror)
8045 return rte_flow_error_set(error, EINVAL,
8046 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
8047 "sample before modify action is not supported");
8052 * Internal preparation function. Allocates the DV flow size,
8053 * this size is constant.
8056 * Pointer to the rte_eth_dev structure.
8058 * Pointer to the flow attributes.
8060 * Pointer to the list of items.
8061 * @param[in] actions
8062 * Pointer to the list of actions.
8064 * Pointer to the error structure.
8067 * Pointer to mlx5_flow object on success,
8068 * otherwise NULL and rte_errno is set.
8070 static struct mlx5_flow *
8071 flow_dv_prepare(struct rte_eth_dev *dev,
8072 const struct rte_flow_attr *attr __rte_unused,
8073 const struct rte_flow_item items[] __rte_unused,
8074 const struct rte_flow_action actions[] __rte_unused,
8075 struct rte_flow_error *error)
8077 uint32_t handle_idx = 0;
8078 struct mlx5_flow *dev_flow;
8079 struct mlx5_flow_handle *dev_handle;
8080 struct mlx5_priv *priv = dev->data->dev_private;
8081 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8084 wks->skip_matcher_reg = 0;
8086 wks->final_policy = NULL;
8087 /* In case of corrupting the memory. */
8088 if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
8089 rte_flow_error_set(error, ENOSPC,
8090 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8091 "not free temporary device flow");
8094 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8097 rte_flow_error_set(error, ENOMEM,
8098 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8099 "not enough memory to create flow handle");
8102 MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
8103 dev_flow = &wks->flows[wks->flow_idx++];
8104 memset(dev_flow, 0, sizeof(*dev_flow));
8105 dev_flow->handle = dev_handle;
8106 dev_flow->handle_idx = handle_idx;
8107 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
8108 dev_flow->ingress = attr->ingress;
8109 dev_flow->dv.transfer = attr->transfer;
8113 #ifdef RTE_LIBRTE_MLX5_DEBUG
8115 * Sanity check for match mask and value. Similar to check_valid_spec() in
8116 * kernel driver. If unmasked bit is present in value, it returns failure.
8119 * pointer to match mask buffer.
8120 * @param match_value
8121 * pointer to match value buffer.
8124 * 0 if valid, -EINVAL otherwise.
8127 flow_dv_check_valid_spec(void *match_mask, void *match_value)
8129 uint8_t *m = match_mask;
8130 uint8_t *v = match_value;
8133 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
8136 "match_value differs from match_criteria"
8137 " %p[%u] != %p[%u]",
8138 match_value, i, match_mask, i);
8147 * Add match of ip_version.
8151 * @param[in] headers_v
8152 * Values header pointer.
8153 * @param[in] headers_m
8154 * Masks header pointer.
8155 * @param[in] ip_version
8156 * The IP version to set.
8159 flow_dv_set_match_ip_version(uint32_t group,
8165 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
8167 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
8169 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
8170 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
8171 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
8175 * Add Ethernet item to matcher and to the value.
8177 * @param[in, out] matcher
8179 * @param[in, out] key
8180 * Flow matcher value.
8182 * Flow pattern to translate.
8184 * Item is inner pattern.
8187 flow_dv_translate_item_eth(void *matcher, void *key,
8188 const struct rte_flow_item *item, int inner,
8191 const struct rte_flow_item_eth *eth_m = item->mask;
8192 const struct rte_flow_item_eth *eth_v = item->spec;
8193 const struct rte_flow_item_eth nic_mask = {
8194 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8195 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
8196 .type = RTE_BE16(0xffff),
8209 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8211 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8213 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8215 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8217 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
8218 ð_m->dst, sizeof(eth_m->dst));
8219 /* The value must be in the range of the mask. */
8220 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
8221 for (i = 0; i < sizeof(eth_m->dst); ++i)
8222 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
8223 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
8224 ð_m->src, sizeof(eth_m->src));
8225 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
8226 /* The value must be in the range of the mask. */
8227 for (i = 0; i < sizeof(eth_m->dst); ++i)
8228 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
8230 * HW supports match on one Ethertype, the Ethertype following the last
8231 * VLAN tag of the packet (see PRM).
8232 * Set match on ethertype only if ETH header is not followed by VLAN.
8233 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8234 * ethertype, and use ip_version field instead.
8235 * eCPRI over Ether layer will use type value 0xAEFE.
8237 if (eth_m->type == 0xFFFF) {
8238 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
8239 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8240 switch (eth_v->type) {
8241 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8242 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8244 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
8245 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8246 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8248 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8249 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8251 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8252 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8258 if (eth_m->has_vlan) {
8259 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8260 if (eth_v->has_vlan) {
8262 * Here, when also has_more_vlan field in VLAN item is
8263 * not set, only single-tagged packets will be matched.
8265 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8269 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8270 rte_be_to_cpu_16(eth_m->type));
8271 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
8272 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
8276 * Add VLAN item to matcher and to the value.
8278 * @param[in, out] dev_flow
8280 * @param[in, out] matcher
8282 * @param[in, out] key
8283 * Flow matcher value.
8285 * Flow pattern to translate.
8287 * Item is inner pattern.
8290 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
8291 void *matcher, void *key,
8292 const struct rte_flow_item *item,
8293 int inner, uint32_t group)
8295 const struct rte_flow_item_vlan *vlan_m = item->mask;
8296 const struct rte_flow_item_vlan *vlan_v = item->spec;
8303 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8305 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8307 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
8309 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8311 * This is workaround, masks are not supported,
8312 * and pre-validated.
8315 dev_flow->handle->vf_vlan.tag =
8316 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
8319 * When VLAN item exists in flow, mark packet as tagged,
8320 * even if TCI is not specified.
8322 if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
8323 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
8324 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
8329 vlan_m = &rte_flow_item_vlan_mask;
8330 tci_m = rte_be_to_cpu_16(vlan_m->tci);
8331 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
8332 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
8333 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
8334 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
8335 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
8336 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
8337 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
8339 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
8340 * ethertype, and use ip_version field instead.
8342 if (vlan_m->inner_type == 0xFFFF) {
8343 switch (vlan_v->inner_type) {
8344 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
8345 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8346 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8347 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8349 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
8350 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
8352 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
8353 flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
8359 if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
8360 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
8361 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
8362 /* Only one vlan_tag bit can be set. */
8363 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
8366 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
8367 rte_be_to_cpu_16(vlan_m->inner_type));
8368 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
8369 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
8373 * Add IPV4 item to matcher and to the value.
8375 * @param[in, out] matcher
8377 * @param[in, out] key
8378 * Flow matcher value.
8380 * Flow pattern to translate.
8382 * Item is inner pattern.
8384 * The group to insert the rule.
8387 flow_dv_translate_item_ipv4(void *matcher, void *key,
8388 const struct rte_flow_item *item,
8389 int inner, uint32_t group)
8391 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
8392 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
8393 const struct rte_flow_item_ipv4 nic_mask = {
8395 .src_addr = RTE_BE32(0xffffffff),
8396 .dst_addr = RTE_BE32(0xffffffff),
8397 .type_of_service = 0xff,
8398 .next_proto_id = 0xff,
8399 .time_to_live = 0xff,
8406 uint8_t tos, ihl_m, ihl_v;
8409 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8411 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8413 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8415 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8417 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
8422 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8423 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8424 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8425 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
8426 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
8427 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
8428 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8429 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8430 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8431 src_ipv4_src_ipv6.ipv4_layout.ipv4);
8432 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
8433 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
8434 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
8435 ihl_m = ipv4_m->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8436 ihl_v = ipv4_v->hdr.version_ihl & RTE_IPV4_HDR_IHL_MASK;
8437 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_ihl, ihl_m);
8438 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_ihl, ihl_m & ihl_v);
8439 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
8440 ipv4_m->hdr.type_of_service);
8441 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
8442 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
8443 ipv4_m->hdr.type_of_service >> 2);
8444 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
8445 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8446 ipv4_m->hdr.next_proto_id);
8447 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8448 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
8449 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8450 ipv4_m->hdr.time_to_live);
8451 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8452 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
8453 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8454 !!(ipv4_m->hdr.fragment_offset));
8455 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8456 !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
8460 * Add IPV6 item to matcher and to the value.
8462 * @param[in, out] matcher
8464 * @param[in, out] key
8465 * Flow matcher value.
8467 * Flow pattern to translate.
8469 * Item is inner pattern.
8471 * The group to insert the rule.
8474 flow_dv_translate_item_ipv6(void *matcher, void *key,
8475 const struct rte_flow_item *item,
8476 int inner, uint32_t group)
8478 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
8479 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
8480 const struct rte_flow_item_ipv6 nic_mask = {
8483 "\xff\xff\xff\xff\xff\xff\xff\xff"
8484 "\xff\xff\xff\xff\xff\xff\xff\xff",
8486 "\xff\xff\xff\xff\xff\xff\xff\xff"
8487 "\xff\xff\xff\xff\xff\xff\xff\xff",
8488 .vtc_flow = RTE_BE32(0xffffffff),
8495 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8496 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8505 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8507 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8509 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8511 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8513 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
8518 size = sizeof(ipv6_m->hdr.dst_addr);
8519 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8520 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8521 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8522 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
8523 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
8524 for (i = 0; i < size; ++i)
8525 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
8526 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
8527 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8528 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
8529 src_ipv4_src_ipv6.ipv6_layout.ipv6);
8530 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
8531 for (i = 0; i < size; ++i)
8532 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
8534 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
8535 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
8536 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
8537 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
8538 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
8539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
8542 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
8544 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
8547 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
8549 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
8553 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8555 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8556 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
8558 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
8559 ipv6_m->hdr.hop_limits);
8560 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
8561 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
8562 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
8563 !!(ipv6_m->has_frag_ext));
8564 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
8565 !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
8569 * Add IPV6 fragment extension item to matcher and to the value.
8571 * @param[in, out] matcher
8573 * @param[in, out] key
8574 * Flow matcher value.
8576 * Flow pattern to translate.
8578 * Item is inner pattern.
8581 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
8582 const struct rte_flow_item *item,
8585 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
8586 const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
8587 const struct rte_flow_item_ipv6_frag_ext nic_mask = {
8589 .next_header = 0xff,
8590 .frag_data = RTE_BE16(0xffff),
8597 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8599 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8601 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8603 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8605 /* IPv6 fragment extension item exists, so packet is IP fragment. */
8606 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
8607 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
8608 if (!ipv6_frag_ext_v)
8610 if (!ipv6_frag_ext_m)
8611 ipv6_frag_ext_m = &nic_mask;
8612 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
8613 ipv6_frag_ext_m->hdr.next_header);
8614 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8615 ipv6_frag_ext_v->hdr.next_header &
8616 ipv6_frag_ext_m->hdr.next_header);
8620 * Add TCP item to matcher and to the value.
8622 * @param[in, out] matcher
8624 * @param[in, out] key
8625 * Flow matcher value.
8627 * Flow pattern to translate.
8629 * Item is inner pattern.
8632 flow_dv_translate_item_tcp(void *matcher, void *key,
8633 const struct rte_flow_item *item,
8636 const struct rte_flow_item_tcp *tcp_m = item->mask;
8637 const struct rte_flow_item_tcp *tcp_v = item->spec;
8642 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8644 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8646 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8648 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8650 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8651 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
8655 tcp_m = &rte_flow_item_tcp_mask;
8656 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
8657 rte_be_to_cpu_16(tcp_m->hdr.src_port));
8658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
8659 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
8660 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
8661 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
8662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
8663 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
8664 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
8665 tcp_m->hdr.tcp_flags);
8666 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
8667 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
8671 * Add UDP item to matcher and to the value.
8673 * @param[in, out] matcher
8675 * @param[in, out] key
8676 * Flow matcher value.
8678 * Flow pattern to translate.
8680 * Item is inner pattern.
8683 flow_dv_translate_item_udp(void *matcher, void *key,
8684 const struct rte_flow_item *item,
8687 const struct rte_flow_item_udp *udp_m = item->mask;
8688 const struct rte_flow_item_udp *udp_v = item->spec;
8693 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8695 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8697 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8699 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8701 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8702 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
8706 udp_m = &rte_flow_item_udp_mask;
8707 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
8708 rte_be_to_cpu_16(udp_m->hdr.src_port));
8709 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
8710 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
8711 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
8712 rte_be_to_cpu_16(udp_m->hdr.dst_port));
8713 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8714 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
8718 * Add GRE optional Key item to matcher and to the value.
8720 * @param[in, out] matcher
8722 * @param[in, out] key
8723 * Flow matcher value.
8725 * Flow pattern to translate.
8727 * Item is inner pattern.
8730 flow_dv_translate_item_gre_key(void *matcher, void *key,
8731 const struct rte_flow_item *item)
8733 const rte_be32_t *key_m = item->mask;
8734 const rte_be32_t *key_v = item->spec;
8735 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8736 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8737 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
8739 /* GRE K bit must be on and should already be validated */
8740 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
8741 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
8745 key_m = &gre_key_default_mask;
8746 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
8747 rte_be_to_cpu_32(*key_m) >> 8);
8748 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
8749 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
8750 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
8751 rte_be_to_cpu_32(*key_m) & 0xFF);
8752 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
8753 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
8757 * Add GRE item to matcher and to the value.
8759 * @param[in, out] matcher
8761 * @param[in, out] key
8762 * Flow matcher value.
8764 * Flow pattern to translate.
8765 * @param[in] pattern_flags
8766 * Accumulated pattern flags.
8769 flow_dv_translate_item_gre(void *matcher, void *key,
8770 const struct rte_flow_item *item,
8771 uint64_t pattern_flags)
8773 static const struct rte_flow_item_gre empty_gre = {0,};
8774 const struct rte_flow_item_gre *gre_m = item->mask;
8775 const struct rte_flow_item_gre *gre_v = item->spec;
8776 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8777 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8778 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8779 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8786 uint16_t s_present:1;
8787 uint16_t k_present:1;
8788 uint16_t rsvd_bit1:1;
8789 uint16_t c_present:1;
8793 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
8794 uint16_t protocol_m, protocol_v;
8796 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8797 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
8803 gre_m = &rte_flow_item_gre_mask;
8805 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
8806 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
8807 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
8808 gre_crks_rsvd0_ver_m.c_present);
8809 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
8810 gre_crks_rsvd0_ver_v.c_present &
8811 gre_crks_rsvd0_ver_m.c_present);
8812 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
8813 gre_crks_rsvd0_ver_m.k_present);
8814 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
8815 gre_crks_rsvd0_ver_v.k_present &
8816 gre_crks_rsvd0_ver_m.k_present);
8817 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
8818 gre_crks_rsvd0_ver_m.s_present);
8819 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
8820 gre_crks_rsvd0_ver_v.s_present &
8821 gre_crks_rsvd0_ver_m.s_present);
8822 protocol_m = rte_be_to_cpu_16(gre_m->protocol);
8823 protocol_v = rte_be_to_cpu_16(gre_v->protocol);
8825 /* Force next protocol to prevent matchers duplication */
8826 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
8828 protocol_m = 0xFFFF;
8830 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, protocol_m);
8831 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8832 protocol_m & protocol_v);
8836 * Add NVGRE item to matcher and to the value.
8838 * @param[in, out] matcher
8840 * @param[in, out] key
8841 * Flow matcher value.
8843 * Flow pattern to translate.
8844 * @param[in] pattern_flags
8845 * Accumulated pattern flags.
8848 flow_dv_translate_item_nvgre(void *matcher, void *key,
8849 const struct rte_flow_item *item,
8850 unsigned long pattern_flags)
8852 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
8853 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
8854 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8855 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8856 const char *tni_flow_id_m;
8857 const char *tni_flow_id_v;
8863 /* For NVGRE, GRE header fields must be set with defined values. */
8864 const struct rte_flow_item_gre gre_spec = {
8865 .c_rsvd0_ver = RTE_BE16(0x2000),
8866 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
8868 const struct rte_flow_item_gre gre_mask = {
8869 .c_rsvd0_ver = RTE_BE16(0xB000),
8870 .protocol = RTE_BE16(UINT16_MAX),
8872 const struct rte_flow_item gre_item = {
8877 flow_dv_translate_item_gre(matcher, key, &gre_item, pattern_flags);
8881 nvgre_m = &rte_flow_item_nvgre_mask;
8882 tni_flow_id_m = (const char *)nvgre_m->tni;
8883 tni_flow_id_v = (const char *)nvgre_v->tni;
8884 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
8885 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
8886 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
8887 memcpy(gre_key_m, tni_flow_id_m, size);
8888 for (i = 0; i < size; ++i)
8889 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
8893 * Add VXLAN item to matcher and to the value.
8896 * Pointer to the Ethernet device structure.
8898 * Flow rule attributes.
8899 * @param[in, out] matcher
8901 * @param[in, out] key
8902 * Flow matcher value.
8904 * Flow pattern to translate.
8906 * Item is inner pattern.
8909 flow_dv_translate_item_vxlan(struct rte_eth_dev *dev,
8910 const struct rte_flow_attr *attr,
8911 void *matcher, void *key,
8912 const struct rte_flow_item *item,
8915 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
8916 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
8921 uint32_t *tunnel_header_v;
8922 uint32_t *tunnel_header_m;
8924 struct mlx5_priv *priv = dev->data->dev_private;
8925 const struct rte_flow_item_vxlan nic_mask = {
8926 .vni = "\xff\xff\xff",
8931 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8933 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8935 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8937 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8939 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8940 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8941 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8942 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8943 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8945 dport = MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport);
8949 if ((!attr->group && !priv->sh->tunnel_header_0_1) ||
8950 (attr->group && !priv->sh->misc5_cap))
8951 vxlan_m = &rte_flow_item_vxlan_mask;
8953 vxlan_m = &nic_mask;
8955 if ((priv->sh->steering_format_version ==
8956 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 &&
8957 dport != MLX5_UDP_PORT_VXLAN) ||
8958 (!attr->group && !attr->transfer && !priv->sh->tunnel_header_0_1) ||
8959 ((attr->group || attr->transfer) && !priv->sh->misc5_cap)) {
8966 misc_m = MLX5_ADDR_OF(fte_match_param,
8967 matcher, misc_parameters);
8968 misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8969 size = sizeof(vxlan_m->vni);
8970 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8971 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8972 memcpy(vni_m, vxlan_m->vni, size);
8973 for (i = 0; i < size; ++i)
8974 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8977 misc5_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_5);
8978 misc5_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_5);
8979 tunnel_header_v = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8982 tunnel_header_m = (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc5,
8985 *tunnel_header_v = (vxlan_v->vni[0] & vxlan_m->vni[0]) |
8986 (vxlan_v->vni[1] & vxlan_m->vni[1]) << 8 |
8987 (vxlan_v->vni[2] & vxlan_m->vni[2]) << 16;
8988 if (*tunnel_header_v)
8989 *tunnel_header_m = vxlan_m->vni[0] |
8990 vxlan_m->vni[1] << 8 |
8991 vxlan_m->vni[2] << 16;
8993 *tunnel_header_m = 0x0;
8994 *tunnel_header_v |= (vxlan_v->rsvd1 & vxlan_m->rsvd1) << 24;
8995 if (vxlan_v->rsvd1 & vxlan_m->rsvd1)
8996 *tunnel_header_m |= vxlan_m->rsvd1 << 24;
9000 * Add VXLAN-GPE item to matcher and to the value.
9002 * @param[in, out] matcher
9004 * @param[in, out] key
9005 * Flow matcher value.
9007 * Flow pattern to translate.
9009 * Item is inner pattern.
9013 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
9014 const struct rte_flow_item *item,
9015 const uint64_t pattern_flags)
9017 static const struct rte_flow_item_vxlan_gpe dummy_vxlan_gpe_hdr = {0, };
9018 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
9019 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
9020 /* The item was validated to be on the outer side */
9021 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9022 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9024 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
9026 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9028 MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
9030 MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
9031 int i, size = sizeof(vxlan_m->vni);
9032 uint8_t flags_m = 0xff;
9033 uint8_t flags_v = 0xc;
9034 uint8_t m_protocol, v_protocol;
9036 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9037 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9038 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9039 MLX5_UDP_PORT_VXLAN_GPE);
9042 vxlan_v = &dummy_vxlan_gpe_hdr;
9043 vxlan_m = &dummy_vxlan_gpe_hdr;
9046 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
9048 memcpy(vni_m, vxlan_m->vni, size);
9049 for (i = 0; i < size; ++i)
9050 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
9051 if (vxlan_m->flags) {
9052 flags_m = vxlan_m->flags;
9053 flags_v = vxlan_v->flags;
9055 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
9056 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
9057 m_protocol = vxlan_m->protocol;
9058 v_protocol = vxlan_v->protocol;
9061 /* Force next protocol to ensure next headers parsing. */
9062 if (pattern_flags & MLX5_FLOW_LAYER_INNER_L2)
9063 v_protocol = RTE_VXLAN_GPE_TYPE_ETH;
9064 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4)
9065 v_protocol = RTE_VXLAN_GPE_TYPE_IPV4;
9066 else if (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)
9067 v_protocol = RTE_VXLAN_GPE_TYPE_IPV6;
9069 MLX5_SET(fte_match_set_misc3, misc_m,
9070 outer_vxlan_gpe_next_protocol, m_protocol);
9071 MLX5_SET(fte_match_set_misc3, misc_v,
9072 outer_vxlan_gpe_next_protocol, m_protocol & v_protocol);
9076 * Add Geneve item to matcher and to the value.
9078 * @param[in, out] matcher
9080 * @param[in, out] key
9081 * Flow matcher value.
9083 * Flow pattern to translate.
9085 * Item is inner pattern.
9089 flow_dv_translate_item_geneve(void *matcher, void *key,
9090 const struct rte_flow_item *item,
9091 uint64_t pattern_flags)
9093 static const struct rte_flow_item_geneve empty_geneve = {0,};
9094 const struct rte_flow_item_geneve *geneve_m = item->mask;
9095 const struct rte_flow_item_geneve *geneve_v = item->spec;
9096 /* GENEVE flow item validation allows single tunnel item */
9097 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9098 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9099 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9100 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9103 char *vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
9104 char *vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
9105 size_t size = sizeof(geneve_m->vni), i;
9106 uint16_t protocol_m, protocol_v;
9108 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9109 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9110 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9111 MLX5_UDP_PORT_GENEVE);
9114 geneve_v = &empty_geneve;
9115 geneve_m = &empty_geneve;
9118 geneve_m = &rte_flow_item_geneve_mask;
9120 memcpy(vni_m, geneve_m->vni, size);
9121 for (i = 0; i < size; ++i)
9122 vni_v[i] = vni_m[i] & geneve_v->vni[i];
9123 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
9124 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
9125 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
9126 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9127 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
9128 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
9129 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9130 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9131 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9132 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
9133 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
9134 protocol_m = rte_be_to_cpu_16(geneve_m->protocol);
9135 protocol_v = rte_be_to_cpu_16(geneve_v->protocol);
9137 /* Force next protocol to prevent matchers duplication */
9138 protocol_m = 0xFFFF;
9139 protocol_v = mlx5_translate_tunnel_etypes(pattern_flags);
9141 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type, protocol_m);
9142 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
9143 protocol_m & protocol_v);
9147 * Create Geneve TLV option resource.
9149 * @param dev[in, out]
9150 * Pointer to rte_eth_dev structure.
9151 * @param[in, out] tag_be24
9152 * Tag value in big endian then R-shift 8.
9153 * @parm[in, out] dev_flow
9154 * Pointer to the dev_flow.
9156 * pointer to error structure.
9159 * 0 on success otherwise -errno and errno is set.
9163 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
9164 const struct rte_flow_item *item,
9165 struct rte_flow_error *error)
9167 struct mlx5_priv *priv = dev->data->dev_private;
9168 struct mlx5_dev_ctx_shared *sh = priv->sh;
9169 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
9170 sh->geneve_tlv_option_resource;
9171 struct mlx5_devx_obj *obj;
9172 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9177 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
9178 if (geneve_opt_resource != NULL) {
9179 if (geneve_opt_resource->option_class ==
9180 geneve_opt_v->option_class &&
9181 geneve_opt_resource->option_type ==
9182 geneve_opt_v->option_type &&
9183 geneve_opt_resource->length ==
9184 geneve_opt_v->option_len) {
9185 /* We already have GENVE TLV option obj allocated. */
9186 __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
9189 ret = rte_flow_error_set(error, ENOMEM,
9190 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9191 "Only one GENEVE TLV option supported");
9195 /* Create a GENEVE TLV object and resource. */
9196 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->cdev->ctx,
9197 geneve_opt_v->option_class,
9198 geneve_opt_v->option_type,
9199 geneve_opt_v->option_len);
9201 ret = rte_flow_error_set(error, ENODATA,
9202 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9203 "Failed to create GENEVE TLV Devx object");
9206 sh->geneve_tlv_option_resource =
9207 mlx5_malloc(MLX5_MEM_ZERO,
9208 sizeof(*geneve_opt_resource),
9210 if (!sh->geneve_tlv_option_resource) {
9211 claim_zero(mlx5_devx_cmd_destroy(obj));
9212 ret = rte_flow_error_set(error, ENOMEM,
9213 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9214 "GENEVE TLV object memory allocation failed");
9217 geneve_opt_resource = sh->geneve_tlv_option_resource;
9218 geneve_opt_resource->obj = obj;
9219 geneve_opt_resource->option_class = geneve_opt_v->option_class;
9220 geneve_opt_resource->option_type = geneve_opt_v->option_type;
9221 geneve_opt_resource->length = geneve_opt_v->option_len;
9222 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
9226 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
9231 * Add Geneve TLV option item to matcher.
9233 * @param[in, out] dev
9234 * Pointer to rte_eth_dev structure.
9235 * @param[in, out] matcher
9237 * @param[in, out] key
9238 * Flow matcher value.
9240 * Flow pattern to translate.
9242 * Pointer to error structure.
9245 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
9246 void *key, const struct rte_flow_item *item,
9247 struct rte_flow_error *error)
9249 const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
9250 const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
9251 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9252 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9253 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9255 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9256 rte_be32_t opt_data_key = 0, opt_data_mask = 0;
9262 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
9263 ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
9266 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
9270 * Set the option length in GENEVE header if not requested.
9271 * The GENEVE TLV option length is expressed by the option length field
9272 * in the GENEVE header.
9273 * If the option length was not requested but the GENEVE TLV option item
9274 * is present we set the option length field implicitly.
9276 if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
9277 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
9278 MLX5_GENEVE_OPTLEN_MASK);
9279 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
9280 geneve_opt_v->option_len + 1);
9282 MLX5_SET(fte_match_set_misc, misc_m, geneve_tlv_option_0_exist, 1);
9283 MLX5_SET(fte_match_set_misc, misc_v, geneve_tlv_option_0_exist, 1);
9285 if (geneve_opt_v->data) {
9286 memcpy(&opt_data_key, geneve_opt_v->data,
9287 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9288 sizeof(opt_data_key)));
9289 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9290 sizeof(opt_data_key));
9291 memcpy(&opt_data_mask, geneve_opt_m->data,
9292 RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
9293 sizeof(opt_data_mask)));
9294 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
9295 sizeof(opt_data_mask));
9296 MLX5_SET(fte_match_set_misc3, misc3_m,
9297 geneve_tlv_option_0_data,
9298 rte_be_to_cpu_32(opt_data_mask));
9299 MLX5_SET(fte_match_set_misc3, misc3_v,
9300 geneve_tlv_option_0_data,
9301 rte_be_to_cpu_32(opt_data_key & opt_data_mask));
9307 * Add MPLS item to matcher and to the value.
9309 * @param[in, out] matcher
9311 * @param[in, out] key
9312 * Flow matcher value.
9314 * Flow pattern to translate.
9315 * @param[in] prev_layer
9316 * The protocol layer indicated in previous item.
9318 * Item is inner pattern.
9321 flow_dv_translate_item_mpls(void *matcher, void *key,
9322 const struct rte_flow_item *item,
9323 uint64_t prev_layer,
9326 const uint32_t *in_mpls_m = item->mask;
9327 const uint32_t *in_mpls_v = item->spec;
9328 uint32_t *out_mpls_m = 0;
9329 uint32_t *out_mpls_v = 0;
9330 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9331 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9332 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
9334 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9335 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
9336 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9338 switch (prev_layer) {
9339 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9340 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9341 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
9343 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
9344 MLX5_UDP_PORT_MPLS);
9347 case MLX5_FLOW_LAYER_GRE:
9349 case MLX5_FLOW_LAYER_GRE_KEY:
9350 if (!MLX5_GET16(fte_match_set_misc, misc_v, gre_protocol)) {
9351 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
9353 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
9354 RTE_ETHER_TYPE_MPLS);
9363 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
9364 switch (prev_layer) {
9365 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
9367 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9368 outer_first_mpls_over_udp);
9370 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9371 outer_first_mpls_over_udp);
9373 case MLX5_FLOW_LAYER_GRE:
9375 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
9376 outer_first_mpls_over_gre);
9378 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
9379 outer_first_mpls_over_gre);
9382 /* Inner MPLS not over GRE is not supported. */
9385 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9389 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
9395 if (out_mpls_m && out_mpls_v) {
9396 *out_mpls_m = *in_mpls_m;
9397 *out_mpls_v = *in_mpls_v & *in_mpls_m;
9402 * Add metadata register item to matcher
9404 * @param[in, out] matcher
9406 * @param[in, out] key
9407 * Flow matcher value.
9408 * @param[in] reg_type
9409 * Type of device metadata register
9416 flow_dv_match_meta_reg(void *matcher, void *key,
9417 enum modify_reg reg_type,
9418 uint32_t data, uint32_t mask)
9421 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
9423 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
9429 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
9430 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
9433 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
9434 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
9438 * The metadata register C0 field might be divided into
9439 * source vport index and META item value, we should set
9440 * this field according to specified mask, not as whole one.
9442 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
9444 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
9445 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
9448 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
9451 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
9452 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
9455 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
9456 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
9459 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
9460 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
9463 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
9464 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
9467 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
9468 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
9471 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
9472 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
9475 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
9476 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
9485 * Add MARK item to matcher
9488 * The device to configure through.
9489 * @param[in, out] matcher
9491 * @param[in, out] key
9492 * Flow matcher value.
9494 * Flow pattern to translate.
9497 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
9498 void *matcher, void *key,
9499 const struct rte_flow_item *item)
9501 struct mlx5_priv *priv = dev->data->dev_private;
9502 const struct rte_flow_item_mark *mark;
9506 mark = item->mask ? (const void *)item->mask :
9507 &rte_flow_item_mark_mask;
9508 mask = mark->id & priv->sh->dv_mark_mask;
9509 mark = (const void *)item->spec;
9511 value = mark->id & priv->sh->dv_mark_mask & mask;
9513 enum modify_reg reg;
9515 /* Get the metadata register index for the mark. */
9516 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
9517 MLX5_ASSERT(reg > 0);
9518 if (reg == REG_C_0) {
9519 struct mlx5_priv *priv = dev->data->dev_private;
9520 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9521 uint32_t shl_c0 = rte_bsf32(msk_c0);
9527 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9532 * Add META item to matcher
9535 * The devich to configure through.
9536 * @param[in, out] matcher
9538 * @param[in, out] key
9539 * Flow matcher value.
9541 * Attributes of flow that includes this item.
9543 * Flow pattern to translate.
9546 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
9547 void *matcher, void *key,
9548 const struct rte_flow_attr *attr,
9549 const struct rte_flow_item *item)
9551 const struct rte_flow_item_meta *meta_m;
9552 const struct rte_flow_item_meta *meta_v;
9554 meta_m = (const void *)item->mask;
9556 meta_m = &rte_flow_item_meta_mask;
9557 meta_v = (const void *)item->spec;
9560 uint32_t value = meta_v->data;
9561 uint32_t mask = meta_m->data;
9563 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
9566 MLX5_ASSERT(reg != REG_NON);
9567 if (reg == REG_C_0) {
9568 struct mlx5_priv *priv = dev->data->dev_private;
9569 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9570 uint32_t shl_c0 = rte_bsf32(msk_c0);
9576 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
9581 * Add vport metadata Reg C0 item to matcher
9583 * @param[in, out] matcher
9585 * @param[in, out] key
9586 * Flow matcher value.
9588 * Flow pattern to translate.
9591 flow_dv_translate_item_meta_vport(void *matcher, void *key,
9592 uint32_t value, uint32_t mask)
9594 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
9598 * Add tag item to matcher
9601 * The devich to configure through.
9602 * @param[in, out] matcher
9604 * @param[in, out] key
9605 * Flow matcher value.
9607 * Flow pattern to translate.
9610 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
9611 void *matcher, void *key,
9612 const struct rte_flow_item *item)
9614 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
9615 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
9616 uint32_t mask, value;
9619 value = tag_v->data;
9620 mask = tag_m ? tag_m->data : UINT32_MAX;
9621 if (tag_v->id == REG_C_0) {
9622 struct mlx5_priv *priv = dev->data->dev_private;
9623 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
9624 uint32_t shl_c0 = rte_bsf32(msk_c0);
9630 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
9634 * Add TAG item to matcher
9637 * The devich to configure through.
9638 * @param[in, out] matcher
9640 * @param[in, out] key
9641 * Flow matcher value.
9643 * Flow pattern to translate.
9646 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
9647 void *matcher, void *key,
9648 const struct rte_flow_item *item)
9650 const struct rte_flow_item_tag *tag_v = item->spec;
9651 const struct rte_flow_item_tag *tag_m = item->mask;
9652 enum modify_reg reg;
9655 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
9656 /* Get the metadata register index for the tag. */
9657 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
9658 MLX5_ASSERT(reg > 0);
9659 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
9663 * Add source vport match to the specified matcher.
9665 * @param[in, out] matcher
9667 * @param[in, out] key
9668 * Flow matcher value.
9670 * Source vport value to match
9675 flow_dv_translate_item_source_vport(void *matcher, void *key,
9676 int16_t port, uint16_t mask)
9678 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9679 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9681 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
9682 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
9686 * Translate port-id item to eswitch match on port-id.
9689 * The devich to configure through.
9690 * @param[in, out] matcher
9692 * @param[in, out] key
9693 * Flow matcher value.
9695 * Flow pattern to translate.
9700 * 0 on success, a negative errno value otherwise.
9703 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
9704 void *key, const struct rte_flow_item *item,
9705 const struct rte_flow_attr *attr)
9707 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
9708 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
9709 struct mlx5_priv *priv;
9712 if (pid_v && pid_v->id == MLX5_PORT_ESW_MGR) {
9713 flow_dv_translate_item_source_vport(matcher, key,
9714 flow_dv_get_esw_manager_vport_id(dev), 0xffff);
9717 mask = pid_m ? pid_m->id : 0xffff;
9718 id = pid_v ? pid_v->id : dev->data->port_id;
9719 priv = mlx5_port_to_eswitch_info(id, item == NULL);
9723 * Translate to vport field or to metadata, depending on mode.
9724 * Kernel can use either misc.source_port or half of C0 metadata
9727 if (priv->vport_meta_mask) {
9729 * Provide the hint for SW steering library
9730 * to insert the flow into ingress domain and
9731 * save the extra vport match.
9733 if (mask == 0xffff && priv->vport_id == 0xffff &&
9734 priv->pf_bond < 0 && attr->transfer)
9735 flow_dv_translate_item_source_vport
9736 (matcher, key, priv->vport_id, mask);
9738 * We should always set the vport metadata register,
9739 * otherwise the SW steering library can drop
9740 * the rule if wire vport metadata value is not zero,
9741 * it depends on kernel configuration.
9743 flow_dv_translate_item_meta_vport(matcher, key,
9744 priv->vport_meta_tag,
9745 priv->vport_meta_mask);
9747 flow_dv_translate_item_source_vport(matcher, key,
9748 priv->vport_id, mask);
9754 * Add ICMP6 item to matcher and to the value.
9756 * @param[in, out] matcher
9758 * @param[in, out] key
9759 * Flow matcher value.
9761 * Flow pattern to translate.
9763 * Item is inner pattern.
9766 flow_dv_translate_item_icmp6(void *matcher, void *key,
9767 const struct rte_flow_item *item,
9770 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
9771 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
9774 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9776 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9778 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9780 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9782 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9784 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9786 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
9791 icmp6_m = &rte_flow_item_icmp6_mask;
9792 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
9793 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
9794 icmp6_v->type & icmp6_m->type);
9795 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
9796 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
9797 icmp6_v->code & icmp6_m->code);
9801 * Add ICMP item to matcher and to the value.
9803 * @param[in, out] matcher
9805 * @param[in, out] key
9806 * Flow matcher value.
9808 * Flow pattern to translate.
9810 * Item is inner pattern.
9813 flow_dv_translate_item_icmp(void *matcher, void *key,
9814 const struct rte_flow_item *item,
9817 const struct rte_flow_item_icmp *icmp_m = item->mask;
9818 const struct rte_flow_item_icmp *icmp_v = item->spec;
9819 uint32_t icmp_header_data_m = 0;
9820 uint32_t icmp_header_data_v = 0;
9823 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9825 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9827 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9829 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9831 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9833 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9835 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
9836 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
9840 icmp_m = &rte_flow_item_icmp_mask;
9841 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
9842 icmp_m->hdr.icmp_type);
9843 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
9844 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
9845 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
9846 icmp_m->hdr.icmp_code);
9847 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
9848 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
9849 icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
9850 icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
9851 if (icmp_header_data_m) {
9852 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
9853 icmp_header_data_v |=
9854 rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
9855 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
9856 icmp_header_data_m);
9857 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
9858 icmp_header_data_v & icmp_header_data_m);
9863 * Add GTP item to matcher and to the value.
9865 * @param[in, out] matcher
9867 * @param[in, out] key
9868 * Flow matcher value.
9870 * Flow pattern to translate.
9872 * Item is inner pattern.
9875 flow_dv_translate_item_gtp(void *matcher, void *key,
9876 const struct rte_flow_item *item, int inner)
9878 const struct rte_flow_item_gtp *gtp_m = item->mask;
9879 const struct rte_flow_item_gtp *gtp_v = item->spec;
9882 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9884 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9885 uint16_t dport = RTE_GTPU_UDP_PORT;
9888 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9890 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
9892 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
9894 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
9896 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
9897 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
9898 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
9903 gtp_m = &rte_flow_item_gtp_mask;
9904 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
9905 gtp_m->v_pt_rsv_flags);
9906 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
9907 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
9908 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
9909 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
9910 gtp_v->msg_type & gtp_m->msg_type);
9911 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
9912 rte_be_to_cpu_32(gtp_m->teid));
9913 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
9914 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
9918 * Add GTP PSC item to matcher.
9920 * @param[in, out] matcher
9922 * @param[in, out] key
9923 * Flow matcher value.
9925 * Flow pattern to translate.
9928 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
9929 const struct rte_flow_item *item)
9931 const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
9932 const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
9933 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
9935 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
9941 uint8_t next_ext_header_type;
9946 /* Always set E-flag match on one, regardless of GTP item settings. */
9947 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
9948 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9949 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
9950 gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
9951 gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
9952 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
9953 /*Set next extension header type. */
9956 dw_2.next_ext_header_type = 0xff;
9957 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
9958 rte_cpu_to_be_32(dw_2.w32));
9961 dw_2.next_ext_header_type = 0x85;
9962 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
9963 rte_cpu_to_be_32(dw_2.w32));
9975 /*Set extension header PDU type and Qos. */
9977 gtp_psc_m = &rte_flow_item_gtp_psc_mask;
9979 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->hdr.type);
9980 dw_0.qfi = gtp_psc_m->hdr.qfi;
9981 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
9982 rte_cpu_to_be_32(dw_0.w32));
9984 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->hdr.type &
9985 gtp_psc_m->hdr.type);
9986 dw_0.qfi = gtp_psc_v->hdr.qfi & gtp_psc_m->hdr.qfi;
9987 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
9988 rte_cpu_to_be_32(dw_0.w32));
9994 * Add eCPRI item to matcher and to the value.
9997 * The devich to configure through.
9998 * @param[in, out] matcher
10000 * @param[in, out] key
10001 * Flow matcher value.
10003 * Flow pattern to translate.
10004 * @param[in] last_item
10008 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
10009 void *key, const struct rte_flow_item *item,
10010 uint64_t last_item)
10012 struct mlx5_priv *priv = dev->data->dev_private;
10013 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
10014 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
10015 struct rte_ecpri_common_hdr common;
10016 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
10017 misc_parameters_4);
10018 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
10024 * In case of eCPRI over Ethernet, if EtherType is not specified,
10025 * match on eCPRI EtherType implicitly.
10027 if (last_item & MLX5_FLOW_LAYER_OUTER_L2) {
10028 void *hdrs_m, *hdrs_v, *l2m, *l2v;
10030 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
10031 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
10032 l2m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, ethertype);
10033 l2v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
10034 if (*(uint16_t *)l2m == 0 && *(uint16_t *)l2v == 0) {
10035 *(uint16_t *)l2m = UINT16_MAX;
10036 *(uint16_t *)l2v = RTE_BE16(RTE_ETHER_TYPE_ECPRI);
10042 ecpri_m = &rte_flow_item_ecpri_mask;
10044 * Maximal four DW samples are supported in a single matching now.
10045 * Two are used now for a eCPRI matching:
10046 * 1. Type: one byte, mask should be 0x00ff0000 in network order
10047 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
10050 if (!ecpri_m->hdr.common.u32)
10052 samples = priv->sh->ecpri_parser.ids;
10053 /* Need to take the whole DW as the mask to fill the entry. */
10054 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10055 prog_sample_field_value_0);
10056 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10057 prog_sample_field_value_0);
10058 /* Already big endian (network order) in the header. */
10059 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
10060 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
10061 /* Sample#0, used for matching type, offset 0. */
10062 MLX5_SET(fte_match_set_misc4, misc4_m,
10063 prog_sample_field_id_0, samples[0]);
10064 /* It makes no sense to set the sample ID in the mask field. */
10065 MLX5_SET(fte_match_set_misc4, misc4_v,
10066 prog_sample_field_id_0, samples[0]);
10068 * Checking if message body part needs to be matched.
10069 * Some wildcard rules only matching type field should be supported.
10071 if (ecpri_m->hdr.dummy[0]) {
10072 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
10073 switch (common.type) {
10074 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
10075 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
10076 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
10077 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
10078 prog_sample_field_value_1);
10079 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
10080 prog_sample_field_value_1);
10081 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
10082 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
10083 ecpri_m->hdr.dummy[0];
10084 /* Sample#1, to match message body, offset 4. */
10085 MLX5_SET(fte_match_set_misc4, misc4_m,
10086 prog_sample_field_id_1, samples[1]);
10087 MLX5_SET(fte_match_set_misc4, misc4_v,
10088 prog_sample_field_id_1, samples[1]);
10091 /* Others, do not match any sample ID. */
10098 * Add connection tracking status item to matcher
10101 * The devich to configure through.
10102 * @param[in, out] matcher
10104 * @param[in, out] key
10105 * Flow matcher value.
10107 * Flow pattern to translate.
10110 flow_dv_translate_item_aso_ct(struct rte_eth_dev *dev,
10111 void *matcher, void *key,
10112 const struct rte_flow_item *item)
10114 uint32_t reg_value = 0;
10116 /* 8LSB 0b 11/0000/11, middle 4 bits are reserved. */
10117 uint32_t reg_mask = 0;
10118 const struct rte_flow_item_conntrack *spec = item->spec;
10119 const struct rte_flow_item_conntrack *mask = item->mask;
10121 struct rte_flow_error error;
10124 mask = &rte_flow_item_conntrack_mask;
10125 if (!spec || !mask->flags)
10127 flags = spec->flags & mask->flags;
10128 /* The conflict should be checked in the validation. */
10129 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_VALID)
10130 reg_value |= MLX5_CT_SYNDROME_VALID;
10131 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10132 reg_value |= MLX5_CT_SYNDROME_STATE_CHANGE;
10133 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_INVALID)
10134 reg_value |= MLX5_CT_SYNDROME_INVALID;
10135 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED)
10136 reg_value |= MLX5_CT_SYNDROME_TRAP;
10137 if (flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10138 reg_value |= MLX5_CT_SYNDROME_BAD_PACKET;
10139 if (mask->flags & (RTE_FLOW_CONNTRACK_PKT_STATE_VALID |
10140 RTE_FLOW_CONNTRACK_PKT_STATE_INVALID |
10141 RTE_FLOW_CONNTRACK_PKT_STATE_DISABLED))
10143 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_CHANGED)
10144 reg_mask |= MLX5_CT_SYNDROME_STATE_CHANGE;
10145 if (mask->flags & RTE_FLOW_CONNTRACK_PKT_STATE_BAD)
10146 reg_mask |= MLX5_CT_SYNDROME_BAD_PACKET;
10147 /* The REG_C_x value could be saved during startup. */
10148 reg_id = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, &error);
10149 if (reg_id == REG_NON)
10151 flow_dv_match_meta_reg(matcher, key, (enum modify_reg)reg_id,
10152 reg_value, reg_mask);
10156 flow_dv_translate_item_flex(struct rte_eth_dev *dev, void *matcher, void *key,
10157 const struct rte_flow_item *item,
10158 struct mlx5_flow *dev_flow, bool is_inner)
10160 const struct rte_flow_item_flex *spec =
10161 (const struct rte_flow_item_flex *)item->spec;
10162 int index = mlx5_flex_acquire_index(dev, spec->handle, false);
10164 MLX5_ASSERT(index >= 0 && index <= (int)(sizeof(uint32_t) * CHAR_BIT));
10167 if (!(dev_flow->handle->flex_item & RTE_BIT32(index))) {
10168 /* Don't count both inner and outer flex items in one rule. */
10169 if (mlx5_flex_acquire_index(dev, spec->handle, true) != index)
10170 MLX5_ASSERT(false);
10171 dev_flow->handle->flex_item |= RTE_BIT32(index);
10173 mlx5_flex_flow_translate_item(dev, matcher, key, item, is_inner);
10176 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
10178 #define HEADER_IS_ZERO(match_criteria, headers) \
10179 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
10180 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
10183 * Calculate flow matcher enable bitmap.
10185 * @param match_criteria
10186 * Pointer to flow matcher criteria.
10189 * Bitmap of enabled fields.
10192 flow_dv_matcher_enable(uint32_t *match_criteria)
10194 uint8_t match_criteria_enable;
10196 match_criteria_enable =
10197 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
10198 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
10199 match_criteria_enable |=
10200 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
10201 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
10202 match_criteria_enable |=
10203 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
10204 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
10205 match_criteria_enable |=
10206 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
10207 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
10208 match_criteria_enable |=
10209 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
10210 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
10211 match_criteria_enable |=
10212 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
10213 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
10214 match_criteria_enable |=
10215 (!HEADER_IS_ZERO(match_criteria, misc_parameters_5)) <<
10216 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT;
10217 return match_criteria_enable;
10221 __flow_dv_adjust_buf_size(size_t *size, uint8_t match_criteria)
10224 * Check flow matching criteria first, subtract misc5/4 length if flow
10225 * doesn't own misc5/4 parameters. In some old rdma-core releases,
10226 * misc5/4 are not supported, and matcher creation failure is expected
10227 * w/o subtration. If misc5 is provided, misc4 must be counted in since
10228 * misc5 is right after misc4.
10230 if (!(match_criteria & (1 << MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT))) {
10231 *size = MLX5_ST_SZ_BYTES(fte_match_param) -
10232 MLX5_ST_SZ_BYTES(fte_match_set_misc5);
10233 if (!(match_criteria & (1 <<
10234 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT))) {
10235 *size -= MLX5_ST_SZ_BYTES(fte_match_set_misc4);
10240 static struct mlx5_list_entry *
10241 flow_dv_matcher_clone_cb(void *tool_ctx __rte_unused,
10242 struct mlx5_list_entry *entry, void *cb_ctx)
10244 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10245 struct mlx5_flow_dv_matcher *ref = ctx->data;
10246 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10247 typeof(*tbl), tbl);
10248 struct mlx5_flow_dv_matcher *resource = mlx5_malloc(MLX5_MEM_ANY,
10253 rte_flow_error_set(ctx->error, ENOMEM,
10254 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10255 "cannot create matcher");
10258 memcpy(resource, entry, sizeof(*resource));
10259 resource->tbl = &tbl->tbl;
10260 return &resource->entry;
10264 flow_dv_matcher_clone_free_cb(void *tool_ctx __rte_unused,
10265 struct mlx5_list_entry *entry)
10270 struct mlx5_list_entry *
10271 flow_dv_tbl_create_cb(void *tool_ctx, void *cb_ctx)
10273 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10274 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10275 struct rte_eth_dev *dev = ctx->dev;
10276 struct mlx5_flow_tbl_data_entry *tbl_data;
10277 struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data2;
10278 struct rte_flow_error *error = ctx->error;
10279 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10280 struct mlx5_flow_tbl_resource *tbl;
10285 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10287 rte_flow_error_set(error, ENOMEM,
10288 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10290 "cannot allocate flow table data entry");
10293 tbl_data->idx = idx;
10294 tbl_data->tunnel = tt_prm->tunnel;
10295 tbl_data->group_id = tt_prm->group_id;
10296 tbl_data->external = !!tt_prm->external;
10297 tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
10298 tbl_data->is_egress = !!key.is_egress;
10299 tbl_data->is_transfer = !!key.is_fdb;
10300 tbl_data->dummy = !!key.dummy;
10301 tbl_data->level = key.level;
10302 tbl_data->id = key.id;
10303 tbl = &tbl_data->tbl;
10305 return &tbl_data->entry;
10307 domain = sh->fdb_domain;
10308 else if (key.is_egress)
10309 domain = sh->tx_domain;
10311 domain = sh->rx_domain;
10312 ret = mlx5_flow_os_create_flow_tbl(domain, key.level, &tbl->obj);
10314 rte_flow_error_set(error, ENOMEM,
10315 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10316 NULL, "cannot create flow table object");
10317 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10320 if (key.level != 0) {
10321 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
10322 (tbl->obj, &tbl_data->jump.action);
10324 rte_flow_error_set(error, ENOMEM,
10325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10327 "cannot create flow jump action");
10328 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10329 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10333 MKSTR(matcher_name, "%s_%s_%u_%u_matcher_list",
10334 key.is_fdb ? "FDB" : "NIC", key.is_egress ? "egress" : "ingress",
10335 key.level, key.id);
10336 tbl_data->matchers = mlx5_list_create(matcher_name, sh, true,
10337 flow_dv_matcher_create_cb,
10338 flow_dv_matcher_match_cb,
10339 flow_dv_matcher_remove_cb,
10340 flow_dv_matcher_clone_cb,
10341 flow_dv_matcher_clone_free_cb);
10342 if (!tbl_data->matchers) {
10343 rte_flow_error_set(error, ENOMEM,
10344 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10346 "cannot create tbl matcher list");
10347 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10348 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
10349 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
10352 return &tbl_data->entry;
10356 flow_dv_tbl_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10359 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10360 struct mlx5_flow_tbl_data_entry *tbl_data =
10361 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10362 union mlx5_flow_tbl_key key = { .v64 = *(uint64_t *)(ctx->data) };
10364 return tbl_data->level != key.level ||
10365 tbl_data->id != key.id ||
10366 tbl_data->dummy != key.dummy ||
10367 tbl_data->is_transfer != !!key.is_fdb ||
10368 tbl_data->is_egress != !!key.is_egress;
10371 struct mlx5_list_entry *
10372 flow_dv_tbl_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10375 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10376 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10377 struct mlx5_flow_tbl_data_entry *tbl_data;
10378 struct rte_flow_error *error = ctx->error;
10381 tbl_data = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
10383 rte_flow_error_set(error, ENOMEM,
10384 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10386 "cannot allocate flow table data entry");
10389 memcpy(tbl_data, oentry, sizeof(*tbl_data));
10390 tbl_data->idx = idx;
10391 return &tbl_data->entry;
10395 flow_dv_tbl_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10397 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10398 struct mlx5_flow_tbl_data_entry *tbl_data =
10399 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10401 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10405 * Get a flow table.
10407 * @param[in, out] dev
10408 * Pointer to rte_eth_dev structure.
10409 * @param[in] table_level
10410 * Table level to use.
10411 * @param[in] egress
10412 * Direction of the table.
10413 * @param[in] transfer
10414 * E-Switch or NIC flow.
10416 * Dummy entry for dv API.
10417 * @param[in] table_id
10419 * @param[out] error
10420 * pointer to error structure.
10423 * Returns tables resource based on the index, NULL in case of failed.
10425 struct mlx5_flow_tbl_resource *
10426 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
10427 uint32_t table_level, uint8_t egress,
10430 const struct mlx5_flow_tunnel *tunnel,
10431 uint32_t group_id, uint8_t dummy,
10433 struct rte_flow_error *error)
10435 struct mlx5_priv *priv = dev->data->dev_private;
10436 union mlx5_flow_tbl_key table_key = {
10438 .level = table_level,
10442 .is_fdb = !!transfer,
10443 .is_egress = !!egress,
10446 struct mlx5_flow_tbl_tunnel_prm tt_prm = {
10448 .group_id = group_id,
10449 .external = external,
10451 struct mlx5_flow_cb_ctx ctx = {
10454 .data = &table_key.v64,
10457 struct mlx5_list_entry *entry;
10458 struct mlx5_flow_tbl_data_entry *tbl_data;
10460 entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
10462 rte_flow_error_set(error, ENOMEM,
10463 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10464 "cannot get table");
10467 DRV_LOG(DEBUG, "table_level %u table_id %u "
10468 "tunnel %u group %u registered.",
10469 table_level, table_id,
10470 tunnel ? tunnel->tunnel_id : 0, group_id);
10471 tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10472 return &tbl_data->tbl;
10476 flow_dv_tbl_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10478 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10479 struct mlx5_flow_tbl_data_entry *tbl_data =
10480 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
10482 MLX5_ASSERT(entry && sh);
10483 if (tbl_data->jump.action)
10484 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
10485 if (tbl_data->tbl.obj)
10486 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
10487 if (tbl_data->tunnel_offload && tbl_data->external) {
10488 struct mlx5_list_entry *he;
10489 struct mlx5_hlist *tunnel_grp_hash;
10490 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
10491 union tunnel_tbl_key tunnel_key = {
10492 .tunnel_id = tbl_data->tunnel ?
10493 tbl_data->tunnel->tunnel_id : 0,
10494 .group = tbl_data->group_id
10496 uint32_t table_level = tbl_data->level;
10497 struct mlx5_flow_cb_ctx ctx = {
10498 .data = (void *)&tunnel_key.val,
10501 tunnel_grp_hash = tbl_data->tunnel ?
10502 tbl_data->tunnel->groups :
10504 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, &ctx);
10506 mlx5_hlist_unregister(tunnel_grp_hash, he);
10508 "table_level %u id %u tunnel %u group %u released.",
10512 tbl_data->tunnel->tunnel_id : 0,
10513 tbl_data->group_id);
10515 mlx5_list_destroy(tbl_data->matchers);
10516 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
10520 * Release a flow table.
10523 * Pointer to device shared structure.
10525 * Table resource to be released.
10528 * Returns 0 if table was released, else return 1;
10531 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
10532 struct mlx5_flow_tbl_resource *tbl)
10534 struct mlx5_flow_tbl_data_entry *tbl_data =
10535 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10539 return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
10543 flow_dv_matcher_match_cb(void *tool_ctx __rte_unused,
10544 struct mlx5_list_entry *entry, void *cb_ctx)
10546 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10547 struct mlx5_flow_dv_matcher *ref = ctx->data;
10548 struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
10551 return cur->crc != ref->crc ||
10552 cur->priority != ref->priority ||
10553 memcmp((const void *)cur->mask.buf,
10554 (const void *)ref->mask.buf, ref->mask.size);
10557 struct mlx5_list_entry *
10558 flow_dv_matcher_create_cb(void *tool_ctx, void *cb_ctx)
10560 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10561 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10562 struct mlx5_flow_dv_matcher *ref = ctx->data;
10563 struct mlx5_flow_dv_matcher *resource;
10564 struct mlx5dv_flow_matcher_attr dv_attr = {
10565 .type = IBV_FLOW_ATTR_NORMAL,
10566 .match_mask = (void *)&ref->mask,
10568 struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
10569 typeof(*tbl), tbl);
10572 resource = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*resource), 0,
10575 rte_flow_error_set(ctx->error, ENOMEM,
10576 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10577 "cannot create matcher");
10581 dv_attr.match_criteria_enable =
10582 flow_dv_matcher_enable(resource->mask.buf);
10583 __flow_dv_adjust_buf_size(&ref->mask.size,
10584 dv_attr.match_criteria_enable);
10585 dv_attr.priority = ref->priority;
10586 if (tbl->is_egress)
10587 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
10588 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
10590 &resource->matcher_object);
10592 mlx5_free(resource);
10593 rte_flow_error_set(ctx->error, ENOMEM,
10594 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10595 "cannot create matcher");
10598 return &resource->entry;
10602 * Register the flow matcher.
10604 * @param[in, out] dev
10605 * Pointer to rte_eth_dev structure.
10606 * @param[in, out] matcher
10607 * Pointer to flow matcher.
10608 * @param[in, out] key
10609 * Pointer to flow table key.
10610 * @parm[in, out] dev_flow
10611 * Pointer to the dev_flow.
10612 * @param[out] error
10613 * pointer to error structure.
10616 * 0 on success otherwise -errno and errno is set.
10619 flow_dv_matcher_register(struct rte_eth_dev *dev,
10620 struct mlx5_flow_dv_matcher *ref,
10621 union mlx5_flow_tbl_key *key,
10622 struct mlx5_flow *dev_flow,
10623 const struct mlx5_flow_tunnel *tunnel,
10625 struct rte_flow_error *error)
10627 struct mlx5_list_entry *entry;
10628 struct mlx5_flow_dv_matcher *resource;
10629 struct mlx5_flow_tbl_resource *tbl;
10630 struct mlx5_flow_tbl_data_entry *tbl_data;
10631 struct mlx5_flow_cb_ctx ctx = {
10636 * tunnel offload API requires this registration for cases when
10637 * tunnel match rule was inserted before tunnel set rule.
10639 tbl = flow_dv_tbl_resource_get(dev, key->level,
10640 key->is_egress, key->is_fdb,
10641 dev_flow->external, tunnel,
10642 group_id, 0, key->id, error);
10644 return -rte_errno; /* No need to refill the error info */
10645 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
10647 entry = mlx5_list_register(tbl_data->matchers, &ctx);
10649 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
10650 return rte_flow_error_set(error, ENOMEM,
10651 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10652 "cannot allocate ref memory");
10654 resource = container_of(entry, typeof(*resource), entry);
10655 dev_flow->handle->dvh.matcher = resource;
10659 struct mlx5_list_entry *
10660 flow_dv_tag_create_cb(void *tool_ctx, void *cb_ctx)
10662 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10663 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10664 struct mlx5_flow_dv_tag_resource *entry;
10668 entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10670 rte_flow_error_set(ctx->error, ENOMEM,
10671 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10672 "cannot allocate resource memory");
10676 entry->tag_id = *(uint32_t *)(ctx->data);
10677 ret = mlx5_flow_os_create_flow_action_tag(entry->tag_id,
10680 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
10681 rte_flow_error_set(ctx->error, ENOMEM,
10682 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10683 NULL, "cannot create action");
10686 return &entry->entry;
10690 flow_dv_tag_match_cb(void *tool_ctx __rte_unused, struct mlx5_list_entry *entry,
10693 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10694 struct mlx5_flow_dv_tag_resource *tag =
10695 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10697 return *(uint32_t *)(ctx->data) != tag->tag_id;
10700 struct mlx5_list_entry *
10701 flow_dv_tag_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry,
10704 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10705 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10706 struct mlx5_flow_dv_tag_resource *entry;
10709 entry = mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
10711 rte_flow_error_set(ctx->error, ENOMEM,
10712 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10713 "cannot allocate tag resource memory");
10716 memcpy(entry, oentry, sizeof(*entry));
10718 return &entry->entry;
10722 flow_dv_tag_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10724 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10725 struct mlx5_flow_dv_tag_resource *tag =
10726 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10728 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10732 * Find existing tag resource or create and register a new one.
10734 * @param dev[in, out]
10735 * Pointer to rte_eth_dev structure.
10736 * @param[in, out] tag_be24
10737 * Tag value in big endian then R-shift 8.
10738 * @parm[in, out] dev_flow
10739 * Pointer to the dev_flow.
10740 * @param[out] error
10741 * pointer to error structure.
10744 * 0 on success otherwise -errno and errno is set.
10747 flow_dv_tag_resource_register
10748 (struct rte_eth_dev *dev,
10750 struct mlx5_flow *dev_flow,
10751 struct rte_flow_error *error)
10753 struct mlx5_priv *priv = dev->data->dev_private;
10754 struct mlx5_flow_dv_tag_resource *resource;
10755 struct mlx5_list_entry *entry;
10756 struct mlx5_flow_cb_ctx ctx = {
10760 struct mlx5_hlist *tag_table;
10762 tag_table = flow_dv_hlist_prepare(priv->sh, &priv->sh->tag_table,
10764 MLX5_TAGS_HLIST_ARRAY_SIZE,
10765 false, false, priv->sh,
10766 flow_dv_tag_create_cb,
10767 flow_dv_tag_match_cb,
10768 flow_dv_tag_remove_cb,
10769 flow_dv_tag_clone_cb,
10770 flow_dv_tag_clone_free_cb);
10771 if (unlikely(!tag_table))
10773 entry = mlx5_hlist_register(tag_table, tag_be24, &ctx);
10775 resource = container_of(entry, struct mlx5_flow_dv_tag_resource,
10777 dev_flow->handle->dvh.rix_tag = resource->idx;
10778 dev_flow->dv.tag_resource = resource;
10785 flow_dv_tag_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
10787 struct mlx5_dev_ctx_shared *sh = tool_ctx;
10788 struct mlx5_flow_dv_tag_resource *tag =
10789 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
10791 MLX5_ASSERT(tag && sh && tag->action);
10792 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
10793 DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
10794 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
10801 * Pointer to Ethernet device.
10806 * 1 while a reference on it exists, 0 when freed.
10809 flow_dv_tag_release(struct rte_eth_dev *dev,
10812 struct mlx5_priv *priv = dev->data->dev_private;
10813 struct mlx5_flow_dv_tag_resource *tag;
10815 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
10818 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
10819 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
10820 return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
10824 * Translate action PORT_ID / REPRESENTED_PORT to vport.
10827 * Pointer to rte_eth_dev structure.
10828 * @param[in] action
10829 * Pointer to action PORT_ID / REPRESENTED_PORT.
10830 * @param[out] dst_port_id
10831 * The target port ID.
10832 * @param[out] error
10833 * Pointer to the error structure.
10836 * 0 on success, a negative errno value otherwise and rte_errno is set.
10839 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
10840 const struct rte_flow_action *action,
10841 uint32_t *dst_port_id,
10842 struct rte_flow_error *error)
10845 struct mlx5_priv *priv;
10847 switch (action->type) {
10848 case RTE_FLOW_ACTION_TYPE_PORT_ID: {
10849 const struct rte_flow_action_port_id *conf;
10851 conf = (const struct rte_flow_action_port_id *)action->conf;
10852 port = conf->original ? dev->data->port_id : conf->id;
10855 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT: {
10856 const struct rte_flow_action_ethdev *ethdev;
10858 ethdev = (const struct rte_flow_action_ethdev *)action->conf;
10859 port = ethdev->port_id;
10863 MLX5_ASSERT(false);
10864 return rte_flow_error_set(error, EINVAL,
10865 RTE_FLOW_ERROR_TYPE_ACTION, action,
10866 "unknown E-Switch action");
10869 priv = mlx5_port_to_eswitch_info(port, false);
10871 return rte_flow_error_set(error, -rte_errno,
10872 RTE_FLOW_ERROR_TYPE_ACTION,
10874 "No eswitch info was found for port");
10875 #ifdef HAVE_MLX5DV_DR_CREATE_DEST_IB_PORT
10877 * This parameter is transferred to
10878 * mlx5dv_dr_action_create_dest_ib_port().
10880 *dst_port_id = priv->dev_port;
10883 * Legacy mode, no LAG configurations is supported.
10884 * This parameter is transferred to
10885 * mlx5dv_dr_action_create_dest_vport().
10887 *dst_port_id = priv->vport_id;
10893 * Create a counter with aging configuration.
10896 * Pointer to rte_eth_dev structure.
10897 * @param[in] dev_flow
10898 * Pointer to the mlx5_flow.
10899 * @param[out] count
10900 * Pointer to the counter action configuration.
10902 * Pointer to the aging action configuration.
10905 * Index to flow counter on success, 0 otherwise.
10908 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
10909 struct mlx5_flow *dev_flow,
10910 const struct rte_flow_action_count *count
10912 const struct rte_flow_action_age *age)
10915 struct mlx5_age_param *age_param;
10917 counter = flow_dv_counter_alloc(dev, !!age);
10918 if (!counter || age == NULL)
10920 age_param = flow_dv_counter_idx_get_age(dev, counter);
10921 age_param->context = age->context ? age->context :
10922 (void *)(uintptr_t)(dev_flow->flow_idx);
10923 age_param->timeout = age->timeout;
10924 age_param->port_id = dev->data->port_id;
10925 __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
10926 __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
10931 * Add Tx queue matcher
10934 * Pointer to the dev struct.
10935 * @param[in, out] matcher
10937 * @param[in, out] key
10938 * Flow matcher value.
10940 * Flow pattern to translate.
10942 * Item is inner pattern.
10945 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
10946 void *matcher, void *key,
10947 const struct rte_flow_item *item)
10949 const struct mlx5_rte_flow_item_tx_queue *queue_m;
10950 const struct mlx5_rte_flow_item_tx_queue *queue_v;
10952 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
10954 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
10955 struct mlx5_txq_ctrl *txq;
10956 uint32_t queue, mask;
10958 queue_m = (const void *)item->mask;
10959 queue_v = (const void *)item->spec;
10962 txq = mlx5_txq_get(dev, queue_v->queue);
10965 if (txq->type == MLX5_TXQ_TYPE_HAIRPIN)
10966 queue = txq->obj->sq->id;
10968 queue = txq->obj->sq_obj.sq->id;
10969 mask = queue_m == NULL ? UINT32_MAX : queue_m->queue;
10970 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, mask);
10971 MLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue & mask);
10972 mlx5_txq_release(dev, queue_v->queue);
10976 * Set the hash fields according to the @p flow information.
10978 * @param[in] dev_flow
10979 * Pointer to the mlx5_flow.
10980 * @param[in] rss_desc
10981 * Pointer to the mlx5_flow_rss_desc.
10984 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
10985 struct mlx5_flow_rss_desc *rss_desc)
10987 uint64_t items = dev_flow->handle->layers;
10989 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
10991 dev_flow->hash_fields = 0;
10992 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
10993 if (rss_desc->level >= 2)
10996 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
10997 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
10998 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
10999 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11000 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
11001 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11002 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
11004 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
11006 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
11007 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
11008 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
11009 if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
11010 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
11011 else if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
11012 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
11014 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
11017 if (dev_flow->hash_fields == 0)
11019 * There is no match between the RSS types and the
11020 * L3 protocol (IPv4/IPv6) defined in the flow rule.
11023 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
11024 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
11025 if (rss_types & RTE_ETH_RSS_UDP) {
11026 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11027 dev_flow->hash_fields |=
11028 IBV_RX_HASH_SRC_PORT_UDP;
11029 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11030 dev_flow->hash_fields |=
11031 IBV_RX_HASH_DST_PORT_UDP;
11033 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
11035 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
11036 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
11037 if (rss_types & RTE_ETH_RSS_TCP) {
11038 if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
11039 dev_flow->hash_fields |=
11040 IBV_RX_HASH_SRC_PORT_TCP;
11041 else if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
11042 dev_flow->hash_fields |=
11043 IBV_RX_HASH_DST_PORT_TCP;
11045 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
11049 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
11053 * Prepare an Rx Hash queue.
11056 * Pointer to Ethernet device.
11057 * @param[in] dev_flow
11058 * Pointer to the mlx5_flow.
11059 * @param[in] rss_desc
11060 * Pointer to the mlx5_flow_rss_desc.
11061 * @param[out] hrxq_idx
11062 * Hash Rx queue index.
11065 * The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
11067 static struct mlx5_hrxq *
11068 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
11069 struct mlx5_flow *dev_flow,
11070 struct mlx5_flow_rss_desc *rss_desc,
11071 uint32_t *hrxq_idx)
11073 struct mlx5_priv *priv = dev->data->dev_private;
11074 struct mlx5_flow_handle *dh = dev_flow->handle;
11075 struct mlx5_hrxq *hrxq;
11077 MLX5_ASSERT(rss_desc->queue_num);
11078 rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
11079 rss_desc->hash_fields = dev_flow->hash_fields;
11080 rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
11081 rss_desc->shared_rss = 0;
11082 if (rss_desc->hash_fields == 0)
11083 rss_desc->queue_num = 1;
11084 *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
11087 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
11093 * Release sample sub action resource.
11095 * @param[in, out] dev
11096 * Pointer to rte_eth_dev structure.
11097 * @param[in] act_res
11098 * Pointer to sample sub action resource.
11101 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
11102 struct mlx5_flow_sub_actions_idx *act_res)
11104 if (act_res->rix_hrxq) {
11105 mlx5_hrxq_release(dev, act_res->rix_hrxq);
11106 act_res->rix_hrxq = 0;
11108 if (act_res->rix_encap_decap) {
11109 flow_dv_encap_decap_resource_release(dev,
11110 act_res->rix_encap_decap);
11111 act_res->rix_encap_decap = 0;
11113 if (act_res->rix_port_id_action) {
11114 flow_dv_port_id_action_resource_release(dev,
11115 act_res->rix_port_id_action);
11116 act_res->rix_port_id_action = 0;
11118 if (act_res->rix_tag) {
11119 flow_dv_tag_release(dev, act_res->rix_tag);
11120 act_res->rix_tag = 0;
11122 if (act_res->rix_jump) {
11123 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
11124 act_res->rix_jump = 0;
11129 flow_dv_sample_match_cb(void *tool_ctx __rte_unused,
11130 struct mlx5_list_entry *entry, void *cb_ctx)
11132 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11133 struct rte_eth_dev *dev = ctx->dev;
11134 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11135 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
11139 if (ctx_resource->ratio == resource->ratio &&
11140 ctx_resource->ft_type == resource->ft_type &&
11141 ctx_resource->ft_id == resource->ft_id &&
11142 ctx_resource->set_action == resource->set_action &&
11143 !memcmp((void *)&ctx_resource->sample_act,
11144 (void *)&resource->sample_act,
11145 sizeof(struct mlx5_flow_sub_actions_list))) {
11147 * Existing sample action should release the prepared
11148 * sub-actions reference counter.
11150 flow_dv_sample_sub_actions_release(dev,
11151 &ctx_resource->sample_idx);
11157 struct mlx5_list_entry *
11158 flow_dv_sample_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11160 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11161 struct rte_eth_dev *dev = ctx->dev;
11162 struct mlx5_flow_dv_sample_resource *ctx_resource = ctx->data;
11163 void **sample_dv_actions = ctx_resource->sub_actions;
11164 struct mlx5_flow_dv_sample_resource *resource;
11165 struct mlx5dv_dr_flow_sampler_attr sampler_attr;
11166 struct mlx5_priv *priv = dev->data->dev_private;
11167 struct mlx5_dev_ctx_shared *sh = priv->sh;
11168 struct mlx5_flow_tbl_resource *tbl;
11170 const uint32_t next_ft_step = 1;
11171 uint32_t next_ft_id = ctx_resource->ft_id + next_ft_step;
11172 uint8_t is_egress = 0;
11173 uint8_t is_transfer = 0;
11174 struct rte_flow_error *error = ctx->error;
11176 /* Register new sample resource. */
11177 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11179 rte_flow_error_set(error, ENOMEM,
11180 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11182 "cannot allocate resource memory");
11185 *resource = *ctx_resource;
11186 /* Create normal path table level */
11187 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11189 else if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
11191 tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
11192 is_egress, is_transfer,
11193 true, NULL, 0, 0, 0, error);
11195 rte_flow_error_set(error, ENOMEM,
11196 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11198 "fail to create normal path table "
11202 resource->normal_path_tbl = tbl;
11203 if (ctx_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
11204 if (!sh->default_miss_action) {
11205 rte_flow_error_set(error, ENOMEM,
11206 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11208 "default miss action was not "
11212 sample_dv_actions[ctx_resource->sample_act.actions_num++] =
11213 sh->default_miss_action;
11215 /* Create a DR sample action */
11216 sampler_attr.sample_ratio = resource->ratio;
11217 sampler_attr.default_next_table = tbl->obj;
11218 sampler_attr.num_sample_actions = ctx_resource->sample_act.actions_num;
11219 sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
11220 &sample_dv_actions[0];
11221 sampler_attr.action = resource->set_action;
11222 if (mlx5_os_flow_dr_create_flow_action_sampler
11223 (&sampler_attr, &resource->verbs_action)) {
11224 rte_flow_error_set(error, ENOMEM,
11225 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11226 NULL, "cannot create sample action");
11229 resource->idx = idx;
11230 resource->dev = dev;
11231 return &resource->entry;
11233 if (resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
11234 flow_dv_sample_sub_actions_release(dev,
11235 &resource->sample_idx);
11236 if (resource->normal_path_tbl)
11237 flow_dv_tbl_resource_release(MLX5_SH(dev),
11238 resource->normal_path_tbl);
11239 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
11244 struct mlx5_list_entry *
11245 flow_dv_sample_clone_cb(void *tool_ctx __rte_unused,
11246 struct mlx5_list_entry *entry __rte_unused,
11249 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11250 struct rte_eth_dev *dev = ctx->dev;
11251 struct mlx5_flow_dv_sample_resource *resource;
11252 struct mlx5_priv *priv = dev->data->dev_private;
11253 struct mlx5_dev_ctx_shared *sh = priv->sh;
11256 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
11258 rte_flow_error_set(ctx->error, ENOMEM,
11259 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11261 "cannot allocate resource memory");
11264 memcpy(resource, entry, sizeof(*resource));
11265 resource->idx = idx;
11266 resource->dev = dev;
11267 return &resource->entry;
11271 flow_dv_sample_clone_free_cb(void *tool_ctx __rte_unused,
11272 struct mlx5_list_entry *entry)
11274 struct mlx5_flow_dv_sample_resource *resource =
11275 container_of(entry, typeof(*resource), entry);
11276 struct rte_eth_dev *dev = resource->dev;
11277 struct mlx5_priv *priv = dev->data->dev_private;
11279 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
11283 * Find existing sample resource or create and register a new one.
11285 * @param[in, out] dev
11286 * Pointer to rte_eth_dev structure.
11288 * Pointer to sample resource reference.
11289 * @parm[in, out] dev_flow
11290 * Pointer to the dev_flow.
11291 * @param[out] error
11292 * pointer to error structure.
11295 * 0 on success otherwise -errno and errno is set.
11298 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
11299 struct mlx5_flow_dv_sample_resource *ref,
11300 struct mlx5_flow *dev_flow,
11301 struct rte_flow_error *error)
11303 struct mlx5_flow_dv_sample_resource *resource;
11304 struct mlx5_list_entry *entry;
11305 struct mlx5_priv *priv = dev->data->dev_private;
11306 struct mlx5_flow_cb_ctx ctx = {
11312 entry = mlx5_list_register(priv->sh->sample_action_list, &ctx);
11315 resource = container_of(entry, typeof(*resource), entry);
11316 dev_flow->handle->dvh.rix_sample = resource->idx;
11317 dev_flow->dv.sample_res = resource;
11322 flow_dv_dest_array_match_cb(void *tool_ctx __rte_unused,
11323 struct mlx5_list_entry *entry, void *cb_ctx)
11325 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11326 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11327 struct rte_eth_dev *dev = ctx->dev;
11328 struct mlx5_flow_dv_dest_array_resource *resource =
11329 container_of(entry, typeof(*resource), entry);
11332 if (ctx_resource->num_of_dest == resource->num_of_dest &&
11333 ctx_resource->ft_type == resource->ft_type &&
11334 !memcmp((void *)resource->sample_act,
11335 (void *)ctx_resource->sample_act,
11336 (ctx_resource->num_of_dest *
11337 sizeof(struct mlx5_flow_sub_actions_list)))) {
11339 * Existing sample action should release the prepared
11340 * sub-actions reference counter.
11342 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11343 flow_dv_sample_sub_actions_release(dev,
11344 &ctx_resource->sample_idx[idx]);
11350 struct mlx5_list_entry *
11351 flow_dv_dest_array_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)
11353 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11354 struct rte_eth_dev *dev = ctx->dev;
11355 struct mlx5_flow_dv_dest_array_resource *resource;
11356 struct mlx5_flow_dv_dest_array_resource *ctx_resource = ctx->data;
11357 struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
11358 struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
11359 struct mlx5_priv *priv = dev->data->dev_private;
11360 struct mlx5_dev_ctx_shared *sh = priv->sh;
11361 struct mlx5_flow_sub_actions_list *sample_act;
11362 struct mlx5dv_dr_domain *domain;
11363 uint32_t idx = 0, res_idx = 0;
11364 struct rte_flow_error *error = ctx->error;
11365 uint64_t action_flags;
11368 /* Register new destination array resource. */
11369 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11372 rte_flow_error_set(error, ENOMEM,
11373 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11375 "cannot allocate resource memory");
11378 *resource = *ctx_resource;
11379 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
11380 domain = sh->fdb_domain;
11381 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
11382 domain = sh->rx_domain;
11384 domain = sh->tx_domain;
11385 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11386 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
11387 mlx5_malloc(MLX5_MEM_ZERO,
11388 sizeof(struct mlx5dv_dr_action_dest_attr),
11390 if (!dest_attr[idx]) {
11391 rte_flow_error_set(error, ENOMEM,
11392 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11394 "cannot allocate resource memory");
11397 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
11398 sample_act = &ctx_resource->sample_act[idx];
11399 action_flags = sample_act->action_flags;
11400 switch (action_flags) {
11401 case MLX5_FLOW_ACTION_QUEUE:
11402 dest_attr[idx]->dest = sample_act->dr_queue_action;
11404 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
11405 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
11406 dest_attr[idx]->dest_reformat = &dest_reformat[idx];
11407 dest_attr[idx]->dest_reformat->reformat =
11408 sample_act->dr_encap_action;
11409 dest_attr[idx]->dest_reformat->dest =
11410 sample_act->dr_port_id_action;
11412 case MLX5_FLOW_ACTION_PORT_ID:
11413 dest_attr[idx]->dest = sample_act->dr_port_id_action;
11415 case MLX5_FLOW_ACTION_JUMP:
11416 dest_attr[idx]->dest = sample_act->dr_jump_action;
11419 rte_flow_error_set(error, EINVAL,
11420 RTE_FLOW_ERROR_TYPE_ACTION,
11422 "unsupported actions type");
11426 /* create a dest array actioin */
11427 ret = mlx5_os_flow_dr_create_flow_action_dest_array
11429 resource->num_of_dest,
11431 &resource->action);
11433 rte_flow_error_set(error, ENOMEM,
11434 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11436 "cannot create destination array action");
11439 resource->idx = res_idx;
11440 resource->dev = dev;
11441 for (idx = 0; idx < ctx_resource->num_of_dest; idx++)
11442 mlx5_free(dest_attr[idx]);
11443 return &resource->entry;
11445 for (idx = 0; idx < ctx_resource->num_of_dest; idx++) {
11446 flow_dv_sample_sub_actions_release(dev,
11447 &resource->sample_idx[idx]);
11448 if (dest_attr[idx])
11449 mlx5_free(dest_attr[idx]);
11451 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
11455 struct mlx5_list_entry *
11456 flow_dv_dest_array_clone_cb(void *tool_ctx __rte_unused,
11457 struct mlx5_list_entry *entry __rte_unused,
11460 struct mlx5_flow_cb_ctx *ctx = cb_ctx;
11461 struct rte_eth_dev *dev = ctx->dev;
11462 struct mlx5_flow_dv_dest_array_resource *resource;
11463 struct mlx5_priv *priv = dev->data->dev_private;
11464 struct mlx5_dev_ctx_shared *sh = priv->sh;
11465 uint32_t res_idx = 0;
11466 struct rte_flow_error *error = ctx->error;
11468 resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
11471 rte_flow_error_set(error, ENOMEM,
11472 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11474 "cannot allocate dest-array memory");
11477 memcpy(resource, entry, sizeof(*resource));
11478 resource->idx = res_idx;
11479 resource->dev = dev;
11480 return &resource->entry;
11484 flow_dv_dest_array_clone_free_cb(void *tool_ctx __rte_unused,
11485 struct mlx5_list_entry *entry)
11487 struct mlx5_flow_dv_dest_array_resource *resource =
11488 container_of(entry, typeof(*resource), entry);
11489 struct rte_eth_dev *dev = resource->dev;
11490 struct mlx5_priv *priv = dev->data->dev_private;
11492 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
11496 * Find existing destination array resource or create and register a new one.
11498 * @param[in, out] dev
11499 * Pointer to rte_eth_dev structure.
11501 * Pointer to destination array resource reference.
11502 * @parm[in, out] dev_flow
11503 * Pointer to the dev_flow.
11504 * @param[out] error
11505 * pointer to error structure.
11508 * 0 on success otherwise -errno and errno is set.
11511 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
11512 struct mlx5_flow_dv_dest_array_resource *ref,
11513 struct mlx5_flow *dev_flow,
11514 struct rte_flow_error *error)
11516 struct mlx5_flow_dv_dest_array_resource *resource;
11517 struct mlx5_priv *priv = dev->data->dev_private;
11518 struct mlx5_list_entry *entry;
11519 struct mlx5_flow_cb_ctx ctx = {
11525 entry = mlx5_list_register(priv->sh->dest_array_list, &ctx);
11528 resource = container_of(entry, typeof(*resource), entry);
11529 dev_flow->handle->dvh.rix_dest_array = resource->idx;
11530 dev_flow->dv.dest_array_res = resource;
11535 * Convert Sample action to DV specification.
11538 * Pointer to rte_eth_dev structure.
11539 * @param[in] action
11540 * Pointer to sample action structure.
11541 * @param[in, out] dev_flow
11542 * Pointer to the mlx5_flow.
11544 * Pointer to the flow attributes.
11545 * @param[in, out] num_of_dest
11546 * Pointer to the num of destination.
11547 * @param[in, out] sample_actions
11548 * Pointer to sample actions list.
11549 * @param[in, out] res
11550 * Pointer to sample resource.
11551 * @param[out] error
11552 * Pointer to the error structure.
11555 * 0 on success, a negative errno value otherwise and rte_errno is set.
11558 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
11559 const struct rte_flow_action_sample *action,
11560 struct mlx5_flow *dev_flow,
11561 const struct rte_flow_attr *attr,
11562 uint32_t *num_of_dest,
11563 void **sample_actions,
11564 struct mlx5_flow_dv_sample_resource *res,
11565 struct rte_flow_error *error)
11567 struct mlx5_priv *priv = dev->data->dev_private;
11568 const struct rte_flow_action *sub_actions;
11569 struct mlx5_flow_sub_actions_list *sample_act;
11570 struct mlx5_flow_sub_actions_idx *sample_idx;
11571 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11572 struct rte_flow *flow = dev_flow->flow;
11573 struct mlx5_flow_rss_desc *rss_desc;
11574 uint64_t action_flags = 0;
11577 rss_desc = &wks->rss_desc;
11578 sample_act = &res->sample_act;
11579 sample_idx = &res->sample_idx;
11580 res->ratio = action->ratio;
11581 sub_actions = action->actions;
11582 for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
11583 int type = sub_actions->type;
11584 uint32_t pre_rix = 0;
11587 case RTE_FLOW_ACTION_TYPE_QUEUE:
11589 const struct rte_flow_action_queue *queue;
11590 struct mlx5_hrxq *hrxq;
11593 queue = sub_actions->conf;
11594 rss_desc->queue_num = 1;
11595 rss_desc->queue[0] = queue->index;
11596 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11597 rss_desc, &hrxq_idx);
11599 return rte_flow_error_set
11601 RTE_FLOW_ERROR_TYPE_ACTION,
11603 "cannot create fate queue");
11604 sample_act->dr_queue_action = hrxq->action;
11605 sample_idx->rix_hrxq = hrxq_idx;
11606 sample_actions[sample_act->actions_num++] =
11609 action_flags |= MLX5_FLOW_ACTION_QUEUE;
11610 if (action_flags & MLX5_FLOW_ACTION_MARK)
11611 dev_flow->handle->rix_hrxq = hrxq_idx;
11612 dev_flow->handle->fate_action =
11613 MLX5_FLOW_FATE_QUEUE;
11616 case RTE_FLOW_ACTION_TYPE_RSS:
11618 struct mlx5_hrxq *hrxq;
11620 const struct rte_flow_action_rss *rss;
11621 const uint8_t *rss_key;
11623 rss = sub_actions->conf;
11624 memcpy(rss_desc->queue, rss->queue,
11625 rss->queue_num * sizeof(uint16_t));
11626 rss_desc->queue_num = rss->queue_num;
11627 /* NULL RSS key indicates default RSS key. */
11628 rss_key = !rss->key ? rss_hash_default_key : rss->key;
11629 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11631 * rss->level and rss.types should be set in advance
11632 * when expanding items for RSS.
11634 flow_dv_hashfields_set(dev_flow, rss_desc);
11635 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11636 rss_desc, &hrxq_idx);
11638 return rte_flow_error_set
11640 RTE_FLOW_ERROR_TYPE_ACTION,
11642 "cannot create fate queue");
11643 sample_act->dr_queue_action = hrxq->action;
11644 sample_idx->rix_hrxq = hrxq_idx;
11645 sample_actions[sample_act->actions_num++] =
11648 action_flags |= MLX5_FLOW_ACTION_RSS;
11649 if (action_flags & MLX5_FLOW_ACTION_MARK)
11650 dev_flow->handle->rix_hrxq = hrxq_idx;
11651 dev_flow->handle->fate_action =
11652 MLX5_FLOW_FATE_QUEUE;
11655 case RTE_FLOW_ACTION_TYPE_MARK:
11657 uint32_t tag_be = mlx5_flow_mark_set
11658 (((const struct rte_flow_action_mark *)
11659 (sub_actions->conf))->id);
11661 dev_flow->handle->mark = 1;
11662 pre_rix = dev_flow->handle->dvh.rix_tag;
11663 /* Save the mark resource before sample */
11664 pre_r = dev_flow->dv.tag_resource;
11665 if (flow_dv_tag_resource_register(dev, tag_be,
11668 MLX5_ASSERT(dev_flow->dv.tag_resource);
11669 sample_act->dr_tag_action =
11670 dev_flow->dv.tag_resource->action;
11671 sample_idx->rix_tag =
11672 dev_flow->handle->dvh.rix_tag;
11673 sample_actions[sample_act->actions_num++] =
11674 sample_act->dr_tag_action;
11675 /* Recover the mark resource after sample */
11676 dev_flow->dv.tag_resource = pre_r;
11677 dev_flow->handle->dvh.rix_tag = pre_rix;
11678 action_flags |= MLX5_FLOW_ACTION_MARK;
11681 case RTE_FLOW_ACTION_TYPE_COUNT:
11683 if (!flow->counter) {
11685 flow_dv_translate_create_counter(dev,
11686 dev_flow, sub_actions->conf,
11688 if (!flow->counter)
11689 return rte_flow_error_set
11691 RTE_FLOW_ERROR_TYPE_ACTION,
11693 "cannot create counter"
11696 sample_act->dr_cnt_action =
11697 (flow_dv_counter_get_by_idx(dev,
11698 flow->counter, NULL))->action;
11699 sample_actions[sample_act->actions_num++] =
11700 sample_act->dr_cnt_action;
11701 action_flags |= MLX5_FLOW_ACTION_COUNT;
11704 case RTE_FLOW_ACTION_TYPE_PORT_ID:
11705 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
11707 struct mlx5_flow_dv_port_id_action_resource
11709 uint32_t port_id = 0;
11711 memset(&port_id_resource, 0, sizeof(port_id_resource));
11712 /* Save the port id resource before sample */
11713 pre_rix = dev_flow->handle->rix_port_id_action;
11714 pre_r = dev_flow->dv.port_id_action;
11715 if (flow_dv_translate_action_port_id(dev, sub_actions,
11718 port_id_resource.port_id = port_id;
11719 if (flow_dv_port_id_action_resource_register
11720 (dev, &port_id_resource, dev_flow, error))
11722 sample_act->dr_port_id_action =
11723 dev_flow->dv.port_id_action->action;
11724 sample_idx->rix_port_id_action =
11725 dev_flow->handle->rix_port_id_action;
11726 sample_actions[sample_act->actions_num++] =
11727 sample_act->dr_port_id_action;
11728 /* Recover the port id resource after sample */
11729 dev_flow->dv.port_id_action = pre_r;
11730 dev_flow->handle->rix_port_id_action = pre_rix;
11732 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11735 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11736 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11737 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11738 /* Save the encap resource before sample */
11739 pre_rix = dev_flow->handle->dvh.rix_encap_decap;
11740 pre_r = dev_flow->dv.encap_decap;
11741 if (flow_dv_create_action_l2_encap(dev, sub_actions,
11746 sample_act->dr_encap_action =
11747 dev_flow->dv.encap_decap->action;
11748 sample_idx->rix_encap_decap =
11749 dev_flow->handle->dvh.rix_encap_decap;
11750 sample_actions[sample_act->actions_num++] =
11751 sample_act->dr_encap_action;
11752 /* Recover the encap resource after sample */
11753 dev_flow->dv.encap_decap = pre_r;
11754 dev_flow->handle->dvh.rix_encap_decap = pre_rix;
11755 action_flags |= MLX5_FLOW_ACTION_ENCAP;
11758 return rte_flow_error_set(error, EINVAL,
11759 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11761 "Not support for sampler action");
11764 sample_act->action_flags = action_flags;
11765 res->ft_id = dev_flow->dv.group;
11766 if (attr->transfer) {
11768 uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
11769 uint64_t set_action;
11770 } action_ctx = { .set_action = 0 };
11772 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
11773 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
11774 MLX5_MODIFICATION_TYPE_SET);
11775 MLX5_SET(set_action_in, action_ctx.action_in, field,
11776 MLX5_MODI_META_REG_C_0);
11777 MLX5_SET(set_action_in, action_ctx.action_in, data,
11778 priv->vport_meta_tag);
11779 res->set_action = action_ctx.set_action;
11780 } else if (attr->ingress) {
11781 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
11783 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
11789 * Convert Sample action to DV specification.
11792 * Pointer to rte_eth_dev structure.
11793 * @param[in, out] dev_flow
11794 * Pointer to the mlx5_flow.
11795 * @param[in] num_of_dest
11796 * The num of destination.
11797 * @param[in, out] res
11798 * Pointer to sample resource.
11799 * @param[in, out] mdest_res
11800 * Pointer to destination array resource.
11801 * @param[in] sample_actions
11802 * Pointer to sample path actions list.
11803 * @param[in] action_flags
11804 * Holds the actions detected until now.
11805 * @param[out] error
11806 * Pointer to the error structure.
11809 * 0 on success, a negative errno value otherwise and rte_errno is set.
11812 flow_dv_create_action_sample(struct rte_eth_dev *dev,
11813 struct mlx5_flow *dev_flow,
11814 uint32_t num_of_dest,
11815 struct mlx5_flow_dv_sample_resource *res,
11816 struct mlx5_flow_dv_dest_array_resource *mdest_res,
11817 void **sample_actions,
11818 uint64_t action_flags,
11819 struct rte_flow_error *error)
11821 /* update normal path action resource into last index of array */
11822 uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
11823 struct mlx5_flow_sub_actions_list *sample_act =
11824 &mdest_res->sample_act[dest_index];
11825 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11826 struct mlx5_flow_rss_desc *rss_desc;
11827 uint32_t normal_idx = 0;
11828 struct mlx5_hrxq *hrxq;
11832 rss_desc = &wks->rss_desc;
11833 if (num_of_dest > 1) {
11834 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
11835 /* Handle QP action for mirroring */
11836 hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
11837 rss_desc, &hrxq_idx);
11839 return rte_flow_error_set
11841 RTE_FLOW_ERROR_TYPE_ACTION,
11843 "cannot create rx queue");
11845 mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
11846 sample_act->dr_queue_action = hrxq->action;
11847 if (action_flags & MLX5_FLOW_ACTION_MARK)
11848 dev_flow->handle->rix_hrxq = hrxq_idx;
11849 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11851 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
11853 mdest_res->sample_idx[dest_index].rix_encap_decap =
11854 dev_flow->handle->dvh.rix_encap_decap;
11855 sample_act->dr_encap_action =
11856 dev_flow->dv.encap_decap->action;
11857 dev_flow->handle->dvh.rix_encap_decap = 0;
11859 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
11861 mdest_res->sample_idx[dest_index].rix_port_id_action =
11862 dev_flow->handle->rix_port_id_action;
11863 sample_act->dr_port_id_action =
11864 dev_flow->dv.port_id_action->action;
11865 dev_flow->handle->rix_port_id_action = 0;
11867 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
11869 mdest_res->sample_idx[dest_index].rix_jump =
11870 dev_flow->handle->rix_jump;
11871 sample_act->dr_jump_action =
11872 dev_flow->dv.jump->action;
11873 dev_flow->handle->rix_jump = 0;
11875 sample_act->actions_num = normal_idx;
11876 /* update sample action resource into first index of array */
11877 mdest_res->ft_type = res->ft_type;
11878 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
11879 sizeof(struct mlx5_flow_sub_actions_idx));
11880 memcpy(&mdest_res->sample_act[0], &res->sample_act,
11881 sizeof(struct mlx5_flow_sub_actions_list));
11882 mdest_res->num_of_dest = num_of_dest;
11883 if (flow_dv_dest_array_resource_register(dev, mdest_res,
11885 return rte_flow_error_set(error, EINVAL,
11886 RTE_FLOW_ERROR_TYPE_ACTION,
11887 NULL, "can't create sample "
11890 res->sub_actions = sample_actions;
11891 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
11892 return rte_flow_error_set(error, EINVAL,
11893 RTE_FLOW_ERROR_TYPE_ACTION,
11895 "can't create sample action");
11901 * Remove an ASO age action from age actions list.
11904 * Pointer to the Ethernet device structure.
11906 * Pointer to the aso age action handler.
11909 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
11910 struct mlx5_aso_age_action *age)
11912 struct mlx5_age_info *age_info;
11913 struct mlx5_age_param *age_param = &age->age_params;
11914 struct mlx5_priv *priv = dev->data->dev_private;
11915 uint16_t expected = AGE_CANDIDATE;
11917 age_info = GET_PORT_AGE_INFO(priv);
11918 if (!__atomic_compare_exchange_n(&age_param->state, &expected,
11919 AGE_FREE, false, __ATOMIC_RELAXED,
11920 __ATOMIC_RELAXED)) {
11922 * We need the lock even it is age timeout,
11923 * since age action may still in process.
11925 rte_spinlock_lock(&age_info->aged_sl);
11926 LIST_REMOVE(age, next);
11927 rte_spinlock_unlock(&age_info->aged_sl);
11928 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
11933 * Release an ASO age action.
11936 * Pointer to the Ethernet device structure.
11937 * @param[in] age_idx
11938 * Index of ASO age action to release.
11940 * True if the release operation is during flow destroy operation.
11941 * False if the release operation is during action destroy operation.
11944 * 0 when age action was removed, otherwise the number of references.
11947 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
11949 struct mlx5_priv *priv = dev->data->dev_private;
11950 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11951 struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
11952 uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
11955 flow_dv_aso_age_remove_from_age(dev, age);
11956 rte_spinlock_lock(&mng->free_sl);
11957 LIST_INSERT_HEAD(&mng->free, age, next);
11958 rte_spinlock_unlock(&mng->free_sl);
11964 * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
11967 * Pointer to the Ethernet device structure.
11970 * 0 on success, otherwise negative errno value and rte_errno is set.
11973 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
11975 struct mlx5_priv *priv = dev->data->dev_private;
11976 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
11977 void *old_pools = mng->pools;
11978 uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
11979 uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
11980 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
11983 rte_errno = ENOMEM;
11987 memcpy(pools, old_pools,
11988 mng->n * sizeof(struct mlx5_flow_counter_pool *));
11989 mlx5_free(old_pools);
11991 /* First ASO flow hit allocation - starting ASO data-path. */
11992 int ret = mlx5_aso_flow_hit_queue_poll_start(priv->sh);
12000 mng->pools = pools;
12005 * Create and initialize a new ASO aging pool.
12008 * Pointer to the Ethernet device structure.
12009 * @param[out] age_free
12010 * Where to put the pointer of a new age action.
12013 * The age actions pool pointer and @p age_free is set on success,
12014 * NULL otherwise and rte_errno is set.
12016 static struct mlx5_aso_age_pool *
12017 flow_dv_age_pool_create(struct rte_eth_dev *dev,
12018 struct mlx5_aso_age_action **age_free)
12020 struct mlx5_priv *priv = dev->data->dev_private;
12021 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12022 struct mlx5_aso_age_pool *pool = NULL;
12023 struct mlx5_devx_obj *obj = NULL;
12026 obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->cdev->ctx,
12027 priv->sh->cdev->pdn);
12029 rte_errno = ENODATA;
12030 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
12033 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12035 claim_zero(mlx5_devx_cmd_destroy(obj));
12036 rte_errno = ENOMEM;
12039 pool->flow_hit_aso_obj = obj;
12040 pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
12041 rte_rwlock_write_lock(&mng->resize_rwl);
12042 pool->index = mng->next;
12043 /* Resize pools array if there is no room for the new pool in it. */
12044 if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
12045 claim_zero(mlx5_devx_cmd_destroy(obj));
12047 rte_rwlock_write_unlock(&mng->resize_rwl);
12050 mng->pools[pool->index] = pool;
12052 rte_rwlock_write_unlock(&mng->resize_rwl);
12053 /* Assign the first action in the new pool, the rest go to free list. */
12054 *age_free = &pool->actions[0];
12055 for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
12056 pool->actions[i].offset = i;
12057 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
12063 * Allocate a ASO aging bit.
12066 * Pointer to the Ethernet device structure.
12067 * @param[out] error
12068 * Pointer to the error structure.
12071 * Index to ASO age action on success, 0 otherwise and rte_errno is set.
12074 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12076 struct mlx5_priv *priv = dev->data->dev_private;
12077 const struct mlx5_aso_age_pool *pool;
12078 struct mlx5_aso_age_action *age_free = NULL;
12079 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
12082 /* Try to get the next free age action bit. */
12083 rte_spinlock_lock(&mng->free_sl);
12084 age_free = LIST_FIRST(&mng->free);
12086 LIST_REMOVE(age_free, next);
12087 } else if (!flow_dv_age_pool_create(dev, &age_free)) {
12088 rte_spinlock_unlock(&mng->free_sl);
12089 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12090 NULL, "failed to create ASO age pool");
12091 return 0; /* 0 is an error. */
12093 rte_spinlock_unlock(&mng->free_sl);
12094 pool = container_of
12095 ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
12096 (age_free - age_free->offset), const struct mlx5_aso_age_pool,
12098 if (!age_free->dr_action) {
12099 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
12103 rte_flow_error_set(error, rte_errno,
12104 RTE_FLOW_ERROR_TYPE_ACTION,
12105 NULL, "failed to get reg_c "
12106 "for ASO flow hit");
12107 return 0; /* 0 is an error. */
12109 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
12110 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
12111 (priv->sh->rx_domain,
12112 pool->flow_hit_aso_obj->obj, age_free->offset,
12113 MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
12114 (reg_c - REG_C_0));
12115 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
12116 if (!age_free->dr_action) {
12118 rte_spinlock_lock(&mng->free_sl);
12119 LIST_INSERT_HEAD(&mng->free, age_free, next);
12120 rte_spinlock_unlock(&mng->free_sl);
12121 rte_flow_error_set(error, rte_errno,
12122 RTE_FLOW_ERROR_TYPE_ACTION,
12123 NULL, "failed to create ASO "
12124 "flow hit action");
12125 return 0; /* 0 is an error. */
12128 __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
12129 return pool->index | ((age_free->offset + 1) << 16);
12133 * Initialize flow ASO age parameters.
12136 * Pointer to rte_eth_dev structure.
12137 * @param[in] age_idx
12138 * Index of ASO age action.
12139 * @param[in] context
12140 * Pointer to flow counter age context.
12141 * @param[in] timeout
12142 * Aging timeout in seconds.
12146 flow_dv_aso_age_params_init(struct rte_eth_dev *dev,
12151 struct mlx5_aso_age_action *aso_age;
12153 aso_age = flow_aso_age_get_by_idx(dev, age_idx);
12154 MLX5_ASSERT(aso_age);
12155 aso_age->age_params.context = context;
12156 aso_age->age_params.timeout = timeout;
12157 aso_age->age_params.port_id = dev->data->port_id;
12158 __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
12160 __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
12165 flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,
12166 const struct rte_flow_item_integrity *value,
12167 void *headers_m, void *headers_v)
12170 /* RTE l4_ok filter aggregates hardware l4_ok and
12171 * l4_checksum_ok filters.
12172 * Positive RTE l4_ok match requires hardware match on both L4
12173 * hardware integrity bits.
12174 * For negative match, check hardware l4_checksum_ok bit only,
12175 * because hardware sets that bit to 0 for all packets
12178 if (value->l4_ok) {
12179 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);
12180 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);
12182 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12183 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12186 if (mask->l4_csum_ok) {
12187 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);
12188 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,
12189 value->l4_csum_ok);
12194 flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,
12195 const struct rte_flow_item_integrity *value,
12196 void *headers_m, void *headers_v, bool is_ipv4)
12199 /* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and
12200 * ipv4_csum_ok filters.
12201 * Positive RTE l3_ok match requires hardware match on both L3
12202 * hardware integrity bits.
12203 * For negative match, check hardware l3_csum_ok bit only,
12204 * because hardware sets that bit to 0 for all packets
12208 if (value->l3_ok) {
12209 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12211 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12214 MLX5_SET(fte_match_set_lyr_2_4, headers_m,
12215 ipv4_checksum_ok, 1);
12216 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
12217 ipv4_checksum_ok, !!value->l3_ok);
12219 MLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);
12220 MLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,
12224 if (mask->ipv4_csum_ok) {
12225 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);
12226 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,
12227 value->ipv4_csum_ok);
12232 set_integrity_bits(void *headers_m, void *headers_v,
12233 const struct rte_flow_item *integrity_item, bool is_l3_ip4)
12235 const struct rte_flow_item_integrity *spec = integrity_item->spec;
12236 const struct rte_flow_item_integrity *mask = integrity_item->mask;
12238 /* Integrity bits validation cleared spec pointer */
12239 MLX5_ASSERT(spec != NULL);
12241 mask = &rte_flow_item_integrity_mask;
12242 flow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,
12244 flow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);
12248 flow_dv_translate_item_integrity_post(void *matcher, void *key,
12250 struct rte_flow_item *integrity_items[2],
12251 uint64_t pattern_flags)
12253 void *headers_m, *headers_v;
12256 if (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {
12257 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12259 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
12260 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=
12262 set_integrity_bits(headers_m, headers_v,
12263 integrity_items[1], is_l3_ip4);
12265 if (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {
12266 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
12268 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
12269 is_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=
12271 set_integrity_bits(headers_m, headers_v,
12272 integrity_items[0], is_l3_ip4);
12277 flow_dv_translate_item_integrity(const struct rte_flow_item *item,
12278 const struct rte_flow_item *integrity_items[2],
12279 uint64_t *last_item)
12281 const struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;
12283 /* integrity bits validation cleared spec pointer */
12284 MLX5_ASSERT(spec != NULL);
12285 if (spec->level > 1) {
12286 integrity_items[1] = item;
12287 *last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;
12289 integrity_items[0] = item;
12290 *last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;
12295 * Prepares DV flow counter with aging configuration.
12296 * Gets it by index when exists, creates a new one when doesn't.
12299 * Pointer to rte_eth_dev structure.
12300 * @param[in] dev_flow
12301 * Pointer to the mlx5_flow.
12302 * @param[in, out] flow
12303 * Pointer to the sub flow.
12305 * Pointer to the counter action configuration.
12307 * Pointer to the aging action configuration.
12308 * @param[out] error
12309 * Pointer to the error structure.
12312 * Pointer to the counter, NULL otherwise.
12314 static struct mlx5_flow_counter *
12315 flow_dv_prepare_counter(struct rte_eth_dev *dev,
12316 struct mlx5_flow *dev_flow,
12317 struct rte_flow *flow,
12318 const struct rte_flow_action_count *count,
12319 const struct rte_flow_action_age *age,
12320 struct rte_flow_error *error)
12322 if (!flow->counter) {
12323 flow->counter = flow_dv_translate_create_counter(dev, dev_flow,
12325 if (!flow->counter) {
12326 rte_flow_error_set(error, rte_errno,
12327 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12328 "cannot create counter object.");
12332 return flow_dv_counter_get_by_idx(dev, flow->counter, NULL);
12336 * Release an ASO CT action by its own device.
12339 * Pointer to the Ethernet device structure.
12341 * Index of ASO CT action to release.
12344 * 0 when CT action was removed, otherwise the number of references.
12347 flow_dv_aso_ct_dev_release(struct rte_eth_dev *dev, uint32_t idx)
12349 struct mlx5_priv *priv = dev->data->dev_private;
12350 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12352 struct mlx5_aso_ct_action *ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12353 enum mlx5_aso_ct_state state =
12354 __atomic_load_n(&ct->state, __ATOMIC_RELAXED);
12356 /* Cannot release when CT is in the ASO SQ. */
12357 if (state == ASO_CONNTRACK_WAIT || state == ASO_CONNTRACK_QUERY)
12359 ret = __atomic_sub_fetch(&ct->refcnt, 1, __ATOMIC_RELAXED);
12361 if (ct->dr_action_orig) {
12362 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12363 claim_zero(mlx5_glue->destroy_flow_action
12364 (ct->dr_action_orig));
12366 ct->dr_action_orig = NULL;
12368 if (ct->dr_action_rply) {
12369 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12370 claim_zero(mlx5_glue->destroy_flow_action
12371 (ct->dr_action_rply));
12373 ct->dr_action_rply = NULL;
12375 /* Clear the state to free, no need in 1st allocation. */
12376 MLX5_ASO_CT_UPDATE_STATE(ct, ASO_CONNTRACK_FREE);
12377 rte_spinlock_lock(&mng->ct_sl);
12378 LIST_INSERT_HEAD(&mng->free_cts, ct, next);
12379 rte_spinlock_unlock(&mng->ct_sl);
12385 flow_dv_aso_ct_release(struct rte_eth_dev *dev, uint32_t own_idx,
12386 struct rte_flow_error *error)
12388 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(own_idx);
12389 uint32_t idx = MLX5_INDIRECT_ACT_CT_GET_IDX(own_idx);
12390 struct rte_eth_dev *owndev = &rte_eth_devices[owner];
12393 MLX5_ASSERT(owner < RTE_MAX_ETHPORTS);
12394 if (dev->data->dev_started != 1)
12395 return rte_flow_error_set(error, EAGAIN,
12396 RTE_FLOW_ERROR_TYPE_ACTION,
12398 "Indirect CT action cannot be destroyed when the port is stopped");
12399 ret = flow_dv_aso_ct_dev_release(owndev, idx);
12401 return rte_flow_error_set(error, EAGAIN,
12402 RTE_FLOW_ERROR_TYPE_ACTION,
12404 "Current state prevents indirect CT action from being destroyed");
12409 * Resize the ASO CT pools array by 64 pools.
12412 * Pointer to the Ethernet device structure.
12415 * 0 on success, otherwise negative errno value and rte_errno is set.
12418 flow_dv_aso_ct_pools_resize(struct rte_eth_dev *dev)
12420 struct mlx5_priv *priv = dev->data->dev_private;
12421 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12422 void *old_pools = mng->pools;
12423 /* Magic number now, need a macro. */
12424 uint32_t resize = mng->n + 64;
12425 uint32_t mem_size = sizeof(struct mlx5_aso_ct_pool *) * resize;
12426 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
12429 rte_errno = ENOMEM;
12432 rte_rwlock_write_lock(&mng->resize_rwl);
12433 /* ASO SQ/QP was already initialized in the startup. */
12435 /* Realloc could be an alternative choice. */
12436 rte_memcpy(pools, old_pools,
12437 mng->n * sizeof(struct mlx5_aso_ct_pool *));
12438 mlx5_free(old_pools);
12441 mng->pools = pools;
12442 rte_rwlock_write_unlock(&mng->resize_rwl);
12447 * Create and initialize a new ASO CT pool.
12450 * Pointer to the Ethernet device structure.
12451 * @param[out] ct_free
12452 * Where to put the pointer of a new CT action.
12455 * The CT actions pool pointer and @p ct_free is set on success,
12456 * NULL otherwise and rte_errno is set.
12458 static struct mlx5_aso_ct_pool *
12459 flow_dv_ct_pool_create(struct rte_eth_dev *dev,
12460 struct mlx5_aso_ct_action **ct_free)
12462 struct mlx5_priv *priv = dev->data->dev_private;
12463 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12464 struct mlx5_aso_ct_pool *pool = NULL;
12465 struct mlx5_devx_obj *obj = NULL;
12467 uint32_t log_obj_size = rte_log2_u32(MLX5_ASO_CT_ACTIONS_PER_POOL);
12469 obj = mlx5_devx_cmd_create_conn_track_offload_obj(priv->sh->cdev->ctx,
12470 priv->sh->cdev->pdn,
12473 rte_errno = ENODATA;
12474 DRV_LOG(ERR, "Failed to create conn_track_offload_obj using DevX.");
12477 pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
12479 rte_errno = ENOMEM;
12480 claim_zero(mlx5_devx_cmd_destroy(obj));
12483 pool->devx_obj = obj;
12484 pool->index = mng->next;
12485 /* Resize pools array if there is no room for the new pool in it. */
12486 if (pool->index == mng->n && flow_dv_aso_ct_pools_resize(dev)) {
12487 claim_zero(mlx5_devx_cmd_destroy(obj));
12491 mng->pools[pool->index] = pool;
12493 /* Assign the first action in the new pool, the rest go to free list. */
12494 *ct_free = &pool->actions[0];
12495 /* Lock outside, the list operation is safe here. */
12496 for (i = 1; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) {
12497 /* refcnt is 0 when allocating the memory. */
12498 pool->actions[i].offset = i;
12499 LIST_INSERT_HEAD(&mng->free_cts, &pool->actions[i], next);
12505 * Allocate a ASO CT action from free list.
12508 * Pointer to the Ethernet device structure.
12509 * @param[out] error
12510 * Pointer to the error structure.
12513 * Index to ASO CT action on success, 0 otherwise and rte_errno is set.
12516 flow_dv_aso_ct_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
12518 struct mlx5_priv *priv = dev->data->dev_private;
12519 struct mlx5_aso_ct_pools_mng *mng = priv->sh->ct_mng;
12520 struct mlx5_aso_ct_action *ct = NULL;
12521 struct mlx5_aso_ct_pool *pool;
12526 if (!priv->sh->devx) {
12527 rte_errno = ENOTSUP;
12530 /* Get a free CT action, if no, a new pool will be created. */
12531 rte_spinlock_lock(&mng->ct_sl);
12532 ct = LIST_FIRST(&mng->free_cts);
12534 LIST_REMOVE(ct, next);
12535 } else if (!flow_dv_ct_pool_create(dev, &ct)) {
12536 rte_spinlock_unlock(&mng->ct_sl);
12537 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
12538 NULL, "failed to create ASO CT pool");
12541 rte_spinlock_unlock(&mng->ct_sl);
12542 pool = container_of(ct, struct mlx5_aso_ct_pool, actions[ct->offset]);
12543 ct_idx = MLX5_MAKE_CT_IDX(pool->index, ct->offset);
12544 /* 0: inactive, 1: created, 2+: used by flows. */
12545 __atomic_store_n(&ct->refcnt, 1, __ATOMIC_RELAXED);
12546 reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_CONNTRACK, 0, error);
12547 if (!ct->dr_action_orig) {
12548 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12549 ct->dr_action_orig = mlx5_glue->dv_create_flow_action_aso
12550 (priv->sh->rx_domain, pool->devx_obj->obj,
12552 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_INITIATOR,
12555 RTE_SET_USED(reg_c);
12557 if (!ct->dr_action_orig) {
12558 flow_dv_aso_ct_dev_release(dev, ct_idx);
12559 rte_flow_error_set(error, rte_errno,
12560 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12561 "failed to create ASO CT action");
12565 if (!ct->dr_action_rply) {
12566 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT
12567 ct->dr_action_rply = mlx5_glue->dv_create_flow_action_aso
12568 (priv->sh->rx_domain, pool->devx_obj->obj,
12570 MLX5DV_DR_ACTION_FLAGS_ASO_CT_DIRECTION_RESPONDER,
12573 if (!ct->dr_action_rply) {
12574 flow_dv_aso_ct_dev_release(dev, ct_idx);
12575 rte_flow_error_set(error, rte_errno,
12576 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12577 "failed to create ASO CT action");
12585 * Create a conntrack object with context and actions by using ASO mechanism.
12588 * Pointer to rte_eth_dev structure.
12590 * Pointer to conntrack information profile.
12591 * @param[out] error
12592 * Pointer to the error structure.
12595 * Index to conntrack object on success, 0 otherwise.
12598 flow_dv_translate_create_conntrack(struct rte_eth_dev *dev,
12599 const struct rte_flow_action_conntrack *pro,
12600 struct rte_flow_error *error)
12602 struct mlx5_priv *priv = dev->data->dev_private;
12603 struct mlx5_dev_ctx_shared *sh = priv->sh;
12604 struct mlx5_aso_ct_action *ct;
12607 if (!sh->ct_aso_en)
12608 return rte_flow_error_set(error, ENOTSUP,
12609 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12610 "Connection is not supported");
12611 idx = flow_dv_aso_ct_alloc(dev, error);
12613 return rte_flow_error_set(error, rte_errno,
12614 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12615 "Failed to allocate CT object");
12616 ct = flow_aso_ct_get_by_dev_idx(dev, idx);
12617 if (mlx5_aso_ct_update_by_wqe(sh, ct, pro))
12618 return rte_flow_error_set(error, EBUSY,
12619 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12620 "Failed to update CT");
12621 ct->is_original = !!pro->is_original_dir;
12622 ct->peer = pro->peer_port;
12627 * Fill the flow with DV spec, lock free
12628 * (mutex should be acquired by caller).
12631 * Pointer to rte_eth_dev structure.
12632 * @param[in, out] dev_flow
12633 * Pointer to the sub flow.
12635 * Pointer to the flow attributes.
12637 * Pointer to the list of items.
12638 * @param[in] actions
12639 * Pointer to the list of actions.
12640 * @param[out] error
12641 * Pointer to the error structure.
12644 * 0 on success, a negative errno value otherwise and rte_errno is set.
12647 flow_dv_translate(struct rte_eth_dev *dev,
12648 struct mlx5_flow *dev_flow,
12649 const struct rte_flow_attr *attr,
12650 const struct rte_flow_item items[],
12651 const struct rte_flow_action actions[],
12652 struct rte_flow_error *error)
12654 struct mlx5_priv *priv = dev->data->dev_private;
12655 struct mlx5_dev_config *dev_conf = &priv->config;
12656 struct rte_flow *flow = dev_flow->flow;
12657 struct mlx5_flow_handle *handle = dev_flow->handle;
12658 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
12659 struct mlx5_flow_rss_desc *rss_desc;
12660 uint64_t item_flags = 0;
12661 uint64_t last_item = 0;
12662 uint64_t action_flags = 0;
12663 struct mlx5_flow_dv_matcher matcher = {
12665 .size = sizeof(matcher.mask.buf),
12669 bool actions_end = false;
12671 struct mlx5_flow_dv_modify_hdr_resource res;
12672 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
12673 sizeof(struct mlx5_modification_cmd) *
12674 (MLX5_MAX_MODIFY_NUM + 1)];
12676 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
12677 const struct rte_flow_action_count *count = NULL;
12678 const struct rte_flow_action_age *non_shared_age = NULL;
12679 union flow_dv_attr flow_attr = { .attr = 0 };
12681 union mlx5_flow_tbl_key tbl_key;
12682 uint32_t modify_action_position = UINT32_MAX;
12683 void *match_mask = matcher.mask.buf;
12684 void *match_value = dev_flow->dv.value.buf;
12685 uint8_t next_protocol = 0xff;
12686 struct rte_vlan_hdr vlan = { 0 };
12687 struct mlx5_flow_dv_dest_array_resource mdest_res;
12688 struct mlx5_flow_dv_sample_resource sample_res;
12689 void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
12690 const struct rte_flow_action_sample *sample = NULL;
12691 struct mlx5_flow_sub_actions_list *sample_act;
12692 uint32_t sample_act_pos = UINT32_MAX;
12693 uint32_t age_act_pos = UINT32_MAX;
12694 uint32_t num_of_dest = 0;
12695 int tmp_actions_n = 0;
12698 const struct mlx5_flow_tunnel *tunnel = NULL;
12699 struct flow_grp_info grp_info = {
12700 .external = !!dev_flow->external,
12701 .transfer = !!attr->transfer,
12702 .fdb_def_rule = !!priv->fdb_def_rule,
12703 .skip_scale = dev_flow->skip_scale &
12704 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
12705 .std_tbl_fix = true,
12707 const struct rte_flow_item *integrity_items[2] = {NULL, NULL};
12708 const struct rte_flow_item *tunnel_item = NULL;
12711 return rte_flow_error_set(error, ENOMEM,
12712 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12714 "failed to push flow workspace");
12715 rss_desc = &wks->rss_desc;
12716 memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
12717 memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
12718 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12719 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12720 /* update normal path action resource into last index of array */
12721 sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
12722 if (is_tunnel_offload_active(dev)) {
12723 if (dev_flow->tunnel) {
12724 RTE_VERIFY(dev_flow->tof_type ==
12725 MLX5_TUNNEL_OFFLOAD_MISS_RULE);
12726 tunnel = dev_flow->tunnel;
12728 tunnel = mlx5_get_tof(items, actions,
12729 &dev_flow->tof_type);
12730 dev_flow->tunnel = tunnel;
12732 grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
12733 (dev, attr, tunnel, dev_flow->tof_type);
12735 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
12736 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
12737 ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
12741 dev_flow->dv.group = table;
12742 if (attr->transfer)
12743 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
12744 /* number of actions must be set to 0 in case of dirty stack. */
12745 mhdr_res->actions_num = 0;
12746 if (is_flow_tunnel_match_rule(dev_flow->tof_type)) {
12748 * do not add decap action if match rule drops packet
12749 * HW rejects rules with decap & drop
12751 * if tunnel match rule was inserted before matching tunnel set
12752 * rule flow table used in the match rule must be registered.
12753 * current implementation handles that in the
12754 * flow_dv_match_register() at the function end.
12756 bool add_decap = true;
12757 const struct rte_flow_action *ptr = actions;
12759 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
12760 if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
12766 if (flow_dv_create_action_l2_decap(dev, dev_flow,
12770 dev_flow->dv.actions[actions_n++] =
12771 dev_flow->dv.encap_decap->action;
12772 action_flags |= MLX5_FLOW_ACTION_DECAP;
12775 for (; !actions_end ; actions++) {
12776 const struct rte_flow_action_queue *queue;
12777 const struct rte_flow_action_rss *rss;
12778 const struct rte_flow_action *action = actions;
12779 const uint8_t *rss_key;
12780 struct mlx5_flow_tbl_resource *tbl;
12781 struct mlx5_aso_age_action *age_act;
12782 struct mlx5_flow_counter *cnt_act;
12783 uint32_t port_id = 0;
12784 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
12785 int action_type = actions->type;
12786 const struct rte_flow_action *found_action = NULL;
12787 uint32_t jump_group = 0;
12788 uint32_t owner_idx;
12789 struct mlx5_aso_ct_action *ct;
12791 if (!mlx5_flow_os_action_supported(action_type))
12792 return rte_flow_error_set(error, ENOTSUP,
12793 RTE_FLOW_ERROR_TYPE_ACTION,
12795 "action not supported");
12796 switch (action_type) {
12797 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
12798 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
12800 case RTE_FLOW_ACTION_TYPE_VOID:
12802 case RTE_FLOW_ACTION_TYPE_PORT_ID:
12803 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
12804 if (flow_dv_translate_action_port_id(dev, action,
12807 port_id_resource.port_id = port_id;
12808 MLX5_ASSERT(!handle->rix_port_id_action);
12809 if (flow_dv_port_id_action_resource_register
12810 (dev, &port_id_resource, dev_flow, error))
12812 dev_flow->dv.actions[actions_n++] =
12813 dev_flow->dv.port_id_action->action;
12814 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12815 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
12816 sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
12819 case RTE_FLOW_ACTION_TYPE_FLAG:
12820 action_flags |= MLX5_FLOW_ACTION_FLAG;
12821 dev_flow->handle->mark = 1;
12822 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12823 struct rte_flow_action_mark mark = {
12824 .id = MLX5_FLOW_MARK_DEFAULT,
12827 if (flow_dv_convert_action_mark(dev, &mark,
12831 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12834 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
12836 * Only one FLAG or MARK is supported per device flow
12837 * right now. So the pointer to the tag resource must be
12838 * zero before the register process.
12840 MLX5_ASSERT(!handle->dvh.rix_tag);
12841 if (flow_dv_tag_resource_register(dev, tag_be,
12844 MLX5_ASSERT(dev_flow->dv.tag_resource);
12845 dev_flow->dv.actions[actions_n++] =
12846 dev_flow->dv.tag_resource->action;
12848 case RTE_FLOW_ACTION_TYPE_MARK:
12849 action_flags |= MLX5_FLOW_ACTION_MARK;
12850 dev_flow->handle->mark = 1;
12851 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
12852 const struct rte_flow_action_mark *mark =
12853 (const struct rte_flow_action_mark *)
12856 if (flow_dv_convert_action_mark(dev, mark,
12860 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
12864 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
12865 /* Legacy (non-extensive) MARK action. */
12866 tag_be = mlx5_flow_mark_set
12867 (((const struct rte_flow_action_mark *)
12868 (actions->conf))->id);
12869 MLX5_ASSERT(!handle->dvh.rix_tag);
12870 if (flow_dv_tag_resource_register(dev, tag_be,
12873 MLX5_ASSERT(dev_flow->dv.tag_resource);
12874 dev_flow->dv.actions[actions_n++] =
12875 dev_flow->dv.tag_resource->action;
12877 case RTE_FLOW_ACTION_TYPE_SET_META:
12878 if (flow_dv_convert_action_set_meta
12879 (dev, mhdr_res, attr,
12880 (const struct rte_flow_action_set_meta *)
12881 actions->conf, error))
12883 action_flags |= MLX5_FLOW_ACTION_SET_META;
12885 case RTE_FLOW_ACTION_TYPE_SET_TAG:
12886 if (flow_dv_convert_action_set_tag
12888 (const struct rte_flow_action_set_tag *)
12889 actions->conf, error))
12891 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
12893 case RTE_FLOW_ACTION_TYPE_DROP:
12894 action_flags |= MLX5_FLOW_ACTION_DROP;
12895 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
12897 case RTE_FLOW_ACTION_TYPE_QUEUE:
12898 queue = actions->conf;
12899 rss_desc->queue_num = 1;
12900 rss_desc->queue[0] = queue->index;
12901 action_flags |= MLX5_FLOW_ACTION_QUEUE;
12902 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
12903 sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
12906 case RTE_FLOW_ACTION_TYPE_RSS:
12907 rss = actions->conf;
12908 memcpy(rss_desc->queue, rss->queue,
12909 rss->queue_num * sizeof(uint16_t));
12910 rss_desc->queue_num = rss->queue_num;
12911 /* NULL RSS key indicates default RSS key. */
12912 rss_key = !rss->key ? rss_hash_default_key : rss->key;
12913 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12915 * rss->level and rss.types should be set in advance
12916 * when expanding items for RSS.
12918 action_flags |= MLX5_FLOW_ACTION_RSS;
12919 dev_flow->handle->fate_action = rss_desc->shared_rss ?
12920 MLX5_FLOW_FATE_SHARED_RSS :
12921 MLX5_FLOW_FATE_QUEUE;
12923 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
12924 owner_idx = (uint32_t)(uintptr_t)action->conf;
12925 age_act = flow_aso_age_get_by_idx(dev, owner_idx);
12926 if (flow->age == 0) {
12927 flow->age = owner_idx;
12928 __atomic_fetch_add(&age_act->refcnt, 1,
12931 age_act_pos = actions_n++;
12932 action_flags |= MLX5_FLOW_ACTION_AGE;
12934 case RTE_FLOW_ACTION_TYPE_AGE:
12935 non_shared_age = action->conf;
12936 age_act_pos = actions_n++;
12937 action_flags |= MLX5_FLOW_ACTION_AGE;
12939 case MLX5_RTE_FLOW_ACTION_TYPE_COUNT:
12940 owner_idx = (uint32_t)(uintptr_t)action->conf;
12941 cnt_act = flow_dv_counter_get_by_idx(dev, owner_idx,
12943 MLX5_ASSERT(cnt_act != NULL);
12945 * When creating meter drop flow in drop table, the
12946 * counter should not overwrite the rte flow counter.
12948 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
12949 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP) {
12950 dev_flow->dv.actions[actions_n++] =
12953 if (flow->counter == 0) {
12954 flow->counter = owner_idx;
12956 (&cnt_act->shared_info.refcnt,
12957 1, __ATOMIC_RELAXED);
12959 /* Save information first, will apply later. */
12960 action_flags |= MLX5_FLOW_ACTION_COUNT;
12963 case RTE_FLOW_ACTION_TYPE_COUNT:
12964 if (!priv->sh->devx) {
12965 return rte_flow_error_set
12967 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12969 "count action not supported");
12971 /* Save information first, will apply later. */
12972 count = action->conf;
12973 action_flags |= MLX5_FLOW_ACTION_COUNT;
12975 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
12976 dev_flow->dv.actions[actions_n++] =
12977 priv->sh->pop_vlan_action;
12978 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
12980 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
12981 if (!(action_flags &
12982 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
12983 flow_dev_get_vlan_info_from_items(items, &vlan);
12984 vlan.eth_proto = rte_be_to_cpu_16
12985 ((((const struct rte_flow_action_of_push_vlan *)
12986 actions->conf)->ethertype));
12987 found_action = mlx5_flow_find_action
12989 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
12991 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12992 found_action = mlx5_flow_find_action
12994 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
12996 mlx5_update_vlan_vid_pcp(found_action, &vlan);
12997 if (flow_dv_create_action_push_vlan
12998 (dev, attr, &vlan, dev_flow, error))
13000 dev_flow->dv.actions[actions_n++] =
13001 dev_flow->dv.push_vlan_res->action;
13002 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
13004 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
13005 /* of_vlan_push action handled this action */
13006 MLX5_ASSERT(action_flags &
13007 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
13009 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
13010 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
13012 flow_dev_get_vlan_info_from_items(items, &vlan);
13013 mlx5_update_vlan_vid_pcp(actions, &vlan);
13014 /* If no VLAN push - this is a modify header action */
13015 if (flow_dv_convert_action_modify_vlan_vid
13016 (mhdr_res, actions, error))
13018 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
13020 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
13021 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
13022 if (flow_dv_create_action_l2_encap(dev, actions,
13027 dev_flow->dv.actions[actions_n++] =
13028 dev_flow->dv.encap_decap->action;
13029 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13030 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13031 sample_act->action_flags |=
13032 MLX5_FLOW_ACTION_ENCAP;
13034 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
13035 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
13036 if (flow_dv_create_action_l2_decap(dev, dev_flow,
13040 dev_flow->dv.actions[actions_n++] =
13041 dev_flow->dv.encap_decap->action;
13042 action_flags |= MLX5_FLOW_ACTION_DECAP;
13044 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
13045 /* Handle encap with preceding decap. */
13046 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
13047 if (flow_dv_create_action_raw_encap
13048 (dev, actions, dev_flow, attr, error))
13050 dev_flow->dv.actions[actions_n++] =
13051 dev_flow->dv.encap_decap->action;
13053 /* Handle encap without preceding decap. */
13054 if (flow_dv_create_action_l2_encap
13055 (dev, actions, dev_flow, attr->transfer,
13058 dev_flow->dv.actions[actions_n++] =
13059 dev_flow->dv.encap_decap->action;
13061 action_flags |= MLX5_FLOW_ACTION_ENCAP;
13062 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
13063 sample_act->action_flags |=
13064 MLX5_FLOW_ACTION_ENCAP;
13066 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
13067 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
13069 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
13070 if (flow_dv_create_action_l2_decap
13071 (dev, dev_flow, attr->transfer, error))
13073 dev_flow->dv.actions[actions_n++] =
13074 dev_flow->dv.encap_decap->action;
13076 /* If decap is followed by encap, handle it at encap. */
13077 action_flags |= MLX5_FLOW_ACTION_DECAP;
13079 case MLX5_RTE_FLOW_ACTION_TYPE_JUMP:
13080 dev_flow->dv.actions[actions_n++] =
13081 (void *)(uintptr_t)action->conf;
13082 action_flags |= MLX5_FLOW_ACTION_JUMP;
13084 case RTE_FLOW_ACTION_TYPE_JUMP:
13085 jump_group = ((const struct rte_flow_action_jump *)
13086 action->conf)->group;
13087 grp_info.std_tbl_fix = 0;
13088 if (dev_flow->skip_scale &
13089 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
13090 grp_info.skip_scale = 1;
13092 grp_info.skip_scale = 0;
13093 ret = mlx5_flow_group_to_table(dev, tunnel,
13099 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
13101 !!dev_flow->external,
13102 tunnel, jump_group, 0,
13105 return rte_flow_error_set
13107 RTE_FLOW_ERROR_TYPE_ACTION,
13109 "cannot create jump action.");
13110 if (flow_dv_jump_tbl_resource_register
13111 (dev, tbl, dev_flow, error)) {
13112 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13113 return rte_flow_error_set
13115 RTE_FLOW_ERROR_TYPE_ACTION,
13117 "cannot create jump action.");
13119 dev_flow->dv.actions[actions_n++] =
13120 dev_flow->dv.jump->action;
13121 action_flags |= MLX5_FLOW_ACTION_JUMP;
13122 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
13123 sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
13126 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
13127 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
13128 if (flow_dv_convert_action_modify_mac
13129 (mhdr_res, actions, error))
13131 action_flags |= actions->type ==
13132 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
13133 MLX5_FLOW_ACTION_SET_MAC_SRC :
13134 MLX5_FLOW_ACTION_SET_MAC_DST;
13136 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
13137 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
13138 if (flow_dv_convert_action_modify_ipv4
13139 (mhdr_res, actions, error))
13141 action_flags |= actions->type ==
13142 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
13143 MLX5_FLOW_ACTION_SET_IPV4_SRC :
13144 MLX5_FLOW_ACTION_SET_IPV4_DST;
13146 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
13147 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
13148 if (flow_dv_convert_action_modify_ipv6
13149 (mhdr_res, actions, error))
13151 action_flags |= actions->type ==
13152 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
13153 MLX5_FLOW_ACTION_SET_IPV6_SRC :
13154 MLX5_FLOW_ACTION_SET_IPV6_DST;
13156 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
13157 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
13158 if (flow_dv_convert_action_modify_tp
13159 (mhdr_res, actions, items,
13160 &flow_attr, dev_flow, !!(action_flags &
13161 MLX5_FLOW_ACTION_DECAP), error))
13163 action_flags |= actions->type ==
13164 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
13165 MLX5_FLOW_ACTION_SET_TP_SRC :
13166 MLX5_FLOW_ACTION_SET_TP_DST;
13168 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
13169 if (flow_dv_convert_action_modify_dec_ttl
13170 (mhdr_res, items, &flow_attr, dev_flow,
13172 MLX5_FLOW_ACTION_DECAP), error))
13174 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
13176 case RTE_FLOW_ACTION_TYPE_SET_TTL:
13177 if (flow_dv_convert_action_modify_ttl
13178 (mhdr_res, actions, items, &flow_attr,
13179 dev_flow, !!(action_flags &
13180 MLX5_FLOW_ACTION_DECAP), error))
13182 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
13184 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
13185 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
13186 if (flow_dv_convert_action_modify_tcp_seq
13187 (mhdr_res, actions, error))
13189 action_flags |= actions->type ==
13190 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
13191 MLX5_FLOW_ACTION_INC_TCP_SEQ :
13192 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
13195 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
13196 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
13197 if (flow_dv_convert_action_modify_tcp_ack
13198 (mhdr_res, actions, error))
13200 action_flags |= actions->type ==
13201 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
13202 MLX5_FLOW_ACTION_INC_TCP_ACK :
13203 MLX5_FLOW_ACTION_DEC_TCP_ACK;
13205 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
13206 if (flow_dv_convert_action_set_reg
13207 (mhdr_res, actions, error))
13209 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13211 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
13212 if (flow_dv_convert_action_copy_mreg
13213 (dev, mhdr_res, actions, error))
13215 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
13217 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
13218 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
13219 dev_flow->handle->fate_action =
13220 MLX5_FLOW_FATE_DEFAULT_MISS;
13222 case RTE_FLOW_ACTION_TYPE_METER:
13224 return rte_flow_error_set(error, rte_errno,
13225 RTE_FLOW_ERROR_TYPE_ACTION,
13226 NULL, "Failed to get meter in flow.");
13227 /* Set the meter action. */
13228 dev_flow->dv.actions[actions_n++] =
13229 wks->fm->meter_action;
13230 action_flags |= MLX5_FLOW_ACTION_METER;
13232 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
13233 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
13236 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
13238 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
13239 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
13242 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
13244 case RTE_FLOW_ACTION_TYPE_SAMPLE:
13245 sample_act_pos = actions_n;
13246 sample = (const struct rte_flow_action_sample *)
13249 action_flags |= MLX5_FLOW_ACTION_SAMPLE;
13250 /* put encap action into group if work with port id */
13251 if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
13252 (action_flags & MLX5_FLOW_ACTION_PORT_ID))
13253 sample_act->action_flags |=
13254 MLX5_FLOW_ACTION_ENCAP;
13256 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
13257 if (flow_dv_convert_action_modify_field
13258 (dev, mhdr_res, actions, attr, error))
13260 action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
13262 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
13263 owner_idx = (uint32_t)(uintptr_t)action->conf;
13264 ct = flow_aso_ct_get_by_idx(dev, owner_idx);
13266 return rte_flow_error_set(error, EINVAL,
13267 RTE_FLOW_ERROR_TYPE_ACTION,
13269 "Failed to get CT object.");
13270 if (mlx5_aso_ct_available(priv->sh, ct))
13271 return rte_flow_error_set(error, rte_errno,
13272 RTE_FLOW_ERROR_TYPE_ACTION,
13274 "CT is unavailable.");
13275 if (ct->is_original)
13276 dev_flow->dv.actions[actions_n] =
13277 ct->dr_action_orig;
13279 dev_flow->dv.actions[actions_n] =
13280 ct->dr_action_rply;
13281 if (flow->ct == 0) {
13282 flow->indirect_type =
13283 MLX5_INDIRECT_ACTION_TYPE_CT;
13284 flow->ct = owner_idx;
13285 __atomic_fetch_add(&ct->refcnt, 1,
13289 action_flags |= MLX5_FLOW_ACTION_CT;
13291 case RTE_FLOW_ACTION_TYPE_END:
13292 actions_end = true;
13293 if (mhdr_res->actions_num) {
13294 /* create modify action if needed. */
13295 if (flow_dv_modify_hdr_resource_register
13296 (dev, mhdr_res, dev_flow, error))
13298 dev_flow->dv.actions[modify_action_position] =
13299 handle->dvh.modify_hdr->action;
13302 * Handle AGE and COUNT action by single HW counter
13303 * when they are not shared.
13305 if (action_flags & MLX5_FLOW_ACTION_AGE) {
13306 if ((non_shared_age && count) ||
13307 !(priv->sh->flow_hit_aso_en &&
13308 (attr->group || attr->transfer))) {
13309 /* Creates age by counters. */
13310 cnt_act = flow_dv_prepare_counter
13317 dev_flow->dv.actions[age_act_pos] =
13321 if (!flow->age && non_shared_age) {
13322 flow->age = flow_dv_aso_age_alloc
13326 flow_dv_aso_age_params_init
13328 non_shared_age->context ?
13329 non_shared_age->context :
13330 (void *)(uintptr_t)
13331 (dev_flow->flow_idx),
13332 non_shared_age->timeout);
13334 age_act = flow_aso_age_get_by_idx(dev,
13336 dev_flow->dv.actions[age_act_pos] =
13337 age_act->dr_action;
13339 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
13341 * Create one count action, to be used
13342 * by all sub-flows.
13344 cnt_act = flow_dv_prepare_counter(dev, dev_flow,
13349 dev_flow->dv.actions[actions_n++] =
13355 if (mhdr_res->actions_num &&
13356 modify_action_position == UINT32_MAX)
13357 modify_action_position = actions_n++;
13359 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
13360 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
13361 int item_type = items->type;
13363 if (!mlx5_flow_os_item_supported(item_type))
13364 return rte_flow_error_set(error, ENOTSUP,
13365 RTE_FLOW_ERROR_TYPE_ITEM,
13366 NULL, "item not supported");
13367 switch (item_type) {
13368 case RTE_FLOW_ITEM_TYPE_PORT_ID:
13369 flow_dv_translate_item_port_id
13370 (dev, match_mask, match_value, items, attr);
13371 last_item = MLX5_FLOW_ITEM_PORT_ID;
13373 case RTE_FLOW_ITEM_TYPE_ETH:
13374 flow_dv_translate_item_eth(match_mask, match_value,
13376 dev_flow->dv.group);
13377 matcher.priority = action_flags &
13378 MLX5_FLOW_ACTION_DEFAULT_MISS &&
13379 !dev_flow->external ?
13380 MLX5_PRIORITY_MAP_L3 :
13381 MLX5_PRIORITY_MAP_L2;
13382 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
13383 MLX5_FLOW_LAYER_OUTER_L2;
13385 case RTE_FLOW_ITEM_TYPE_VLAN:
13386 flow_dv_translate_item_vlan(dev_flow,
13387 match_mask, match_value,
13389 dev_flow->dv.group);
13390 matcher.priority = MLX5_PRIORITY_MAP_L2;
13391 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
13392 MLX5_FLOW_LAYER_INNER_VLAN) :
13393 (MLX5_FLOW_LAYER_OUTER_L2 |
13394 MLX5_FLOW_LAYER_OUTER_VLAN);
13396 case RTE_FLOW_ITEM_TYPE_IPV4:
13397 mlx5_flow_tunnel_ip_check(items, next_protocol,
13398 &item_flags, &tunnel);
13399 flow_dv_translate_item_ipv4(match_mask, match_value,
13401 dev_flow->dv.group);
13402 matcher.priority = MLX5_PRIORITY_MAP_L3;
13403 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
13404 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
13405 if (items->mask != NULL &&
13406 ((const struct rte_flow_item_ipv4 *)
13407 items->mask)->hdr.next_proto_id) {
13409 ((const struct rte_flow_item_ipv4 *)
13410 (items->spec))->hdr.next_proto_id;
13412 ((const struct rte_flow_item_ipv4 *)
13413 (items->mask))->hdr.next_proto_id;
13415 /* Reset for inner layer. */
13416 next_protocol = 0xff;
13419 case RTE_FLOW_ITEM_TYPE_IPV6:
13420 mlx5_flow_tunnel_ip_check(items, next_protocol,
13421 &item_flags, &tunnel);
13422 flow_dv_translate_item_ipv6(match_mask, match_value,
13424 dev_flow->dv.group);
13425 matcher.priority = MLX5_PRIORITY_MAP_L3;
13426 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
13427 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
13428 if (items->mask != NULL &&
13429 ((const struct rte_flow_item_ipv6 *)
13430 items->mask)->hdr.proto) {
13432 ((const struct rte_flow_item_ipv6 *)
13433 items->spec)->hdr.proto;
13435 ((const struct rte_flow_item_ipv6 *)
13436 items->mask)->hdr.proto;
13438 /* Reset for inner layer. */
13439 next_protocol = 0xff;
13442 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
13443 flow_dv_translate_item_ipv6_frag_ext(match_mask,
13446 last_item = tunnel ?
13447 MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
13448 MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
13449 if (items->mask != NULL &&
13450 ((const struct rte_flow_item_ipv6_frag_ext *)
13451 items->mask)->hdr.next_header) {
13453 ((const struct rte_flow_item_ipv6_frag_ext *)
13454 items->spec)->hdr.next_header;
13456 ((const struct rte_flow_item_ipv6_frag_ext *)
13457 items->mask)->hdr.next_header;
13459 /* Reset for inner layer. */
13460 next_protocol = 0xff;
13463 case RTE_FLOW_ITEM_TYPE_TCP:
13464 flow_dv_translate_item_tcp(match_mask, match_value,
13466 matcher.priority = MLX5_PRIORITY_MAP_L4;
13467 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
13468 MLX5_FLOW_LAYER_OUTER_L4_TCP;
13470 case RTE_FLOW_ITEM_TYPE_UDP:
13471 flow_dv_translate_item_udp(match_mask, match_value,
13473 matcher.priority = MLX5_PRIORITY_MAP_L4;
13474 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
13475 MLX5_FLOW_LAYER_OUTER_L4_UDP;
13477 case RTE_FLOW_ITEM_TYPE_GRE:
13478 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13479 last_item = MLX5_FLOW_LAYER_GRE;
13480 tunnel_item = items;
13482 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
13483 flow_dv_translate_item_gre_key(match_mask,
13484 match_value, items);
13485 last_item = MLX5_FLOW_LAYER_GRE_KEY;
13487 case RTE_FLOW_ITEM_TYPE_NVGRE:
13488 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13489 last_item = MLX5_FLOW_LAYER_GRE;
13490 tunnel_item = items;
13492 case RTE_FLOW_ITEM_TYPE_VXLAN:
13493 flow_dv_translate_item_vxlan(dev, attr,
13494 match_mask, match_value,
13496 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13497 last_item = MLX5_FLOW_LAYER_VXLAN;
13499 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
13500 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13501 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
13502 tunnel_item = items;
13504 case RTE_FLOW_ITEM_TYPE_GENEVE:
13505 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13506 last_item = MLX5_FLOW_LAYER_GENEVE;
13507 tunnel_item = items;
13509 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
13510 ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
13514 return rte_flow_error_set(error, -ret,
13515 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13516 "cannot create GENEVE TLV option");
13517 flow->geneve_tlv_option = 1;
13518 last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
13520 case RTE_FLOW_ITEM_TYPE_MPLS:
13521 flow_dv_translate_item_mpls(match_mask, match_value,
13522 items, last_item, tunnel);
13523 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13524 last_item = MLX5_FLOW_LAYER_MPLS;
13526 case RTE_FLOW_ITEM_TYPE_MARK:
13527 flow_dv_translate_item_mark(dev, match_mask,
13528 match_value, items);
13529 last_item = MLX5_FLOW_ITEM_MARK;
13531 case RTE_FLOW_ITEM_TYPE_META:
13532 flow_dv_translate_item_meta(dev, match_mask,
13533 match_value, attr, items);
13534 last_item = MLX5_FLOW_ITEM_METADATA;
13536 case RTE_FLOW_ITEM_TYPE_ICMP:
13537 flow_dv_translate_item_icmp(match_mask, match_value,
13539 last_item = MLX5_FLOW_LAYER_ICMP;
13541 case RTE_FLOW_ITEM_TYPE_ICMP6:
13542 flow_dv_translate_item_icmp6(match_mask, match_value,
13544 last_item = MLX5_FLOW_LAYER_ICMP6;
13546 case RTE_FLOW_ITEM_TYPE_TAG:
13547 flow_dv_translate_item_tag(dev, match_mask,
13548 match_value, items);
13549 last_item = MLX5_FLOW_ITEM_TAG;
13551 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
13552 flow_dv_translate_mlx5_item_tag(dev, match_mask,
13553 match_value, items);
13554 last_item = MLX5_FLOW_ITEM_TAG;
13556 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
13557 flow_dv_translate_item_tx_queue(dev, match_mask,
13560 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
13562 case RTE_FLOW_ITEM_TYPE_GTP:
13563 flow_dv_translate_item_gtp(match_mask, match_value,
13565 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
13566 last_item = MLX5_FLOW_LAYER_GTP;
13568 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
13569 ret = flow_dv_translate_item_gtp_psc(match_mask,
13573 return rte_flow_error_set(error, -ret,
13574 RTE_FLOW_ERROR_TYPE_ITEM, NULL,
13575 "cannot create GTP PSC item");
13576 last_item = MLX5_FLOW_LAYER_GTP_PSC;
13578 case RTE_FLOW_ITEM_TYPE_ECPRI:
13579 if (!mlx5_flex_parser_ecpri_exist(dev)) {
13580 /* Create it only the first time to be used. */
13581 ret = mlx5_flex_parser_ecpri_alloc(dev);
13583 return rte_flow_error_set
13585 RTE_FLOW_ERROR_TYPE_ITEM,
13587 "cannot create eCPRI parser");
13589 flow_dv_translate_item_ecpri(dev, match_mask,
13590 match_value, items,
13592 /* No other protocol should follow eCPRI layer. */
13593 last_item = MLX5_FLOW_LAYER_ECPRI;
13595 case RTE_FLOW_ITEM_TYPE_INTEGRITY:
13596 flow_dv_translate_item_integrity(items, integrity_items,
13599 case RTE_FLOW_ITEM_TYPE_CONNTRACK:
13600 flow_dv_translate_item_aso_ct(dev, match_mask,
13601 match_value, items);
13603 case RTE_FLOW_ITEM_TYPE_FLEX:
13604 flow_dv_translate_item_flex(dev, match_mask,
13605 match_value, items,
13606 dev_flow, tunnel != 0);
13607 last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :
13608 MLX5_FLOW_ITEM_OUTER_FLEX;
13613 item_flags |= last_item;
13616 * When E-Switch mode is enabled, we have two cases where we need to
13617 * set the source port manually.
13618 * The first one, is in case of Nic steering rule, and the second is
13619 * E-Switch rule where no port_id item was found. In both cases
13620 * the source port is set according the current port in use.
13622 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
13623 (priv->representor || priv->master)) {
13624 if (flow_dv_translate_item_port_id(dev, match_mask,
13625 match_value, NULL, attr))
13628 if (item_flags & MLX5_FLOW_ITEM_INTEGRITY) {
13629 flow_dv_translate_item_integrity_post(match_mask, match_value,
13633 if (item_flags & MLX5_FLOW_LAYER_VXLAN_GPE)
13634 flow_dv_translate_item_vxlan_gpe(match_mask, match_value,
13635 tunnel_item, item_flags);
13636 else if (item_flags & MLX5_FLOW_LAYER_GENEVE)
13637 flow_dv_translate_item_geneve(match_mask, match_value,
13638 tunnel_item, item_flags);
13639 else if (item_flags & MLX5_FLOW_LAYER_GRE) {
13640 if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE)
13641 flow_dv_translate_item_gre(match_mask, match_value,
13642 tunnel_item, item_flags);
13643 else if (tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE)
13644 flow_dv_translate_item_nvgre(match_mask, match_value,
13645 tunnel_item, item_flags);
13647 MLX5_ASSERT(false);
13649 #ifdef RTE_LIBRTE_MLX5_DEBUG
13650 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
13651 dev_flow->dv.value.buf));
13654 * Layers may be already initialized from prefix flow if this dev_flow
13655 * is the suffix flow.
13657 handle->layers |= item_flags;
13658 if (action_flags & MLX5_FLOW_ACTION_RSS)
13659 flow_dv_hashfields_set(dev_flow, rss_desc);
13660 /* If has RSS action in the sample action, the Sample/Mirror resource
13661 * should be registered after the hash filed be update.
13663 if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
13664 ret = flow_dv_translate_action_sample(dev,
13673 ret = flow_dv_create_action_sample(dev,
13682 return rte_flow_error_set
13684 RTE_FLOW_ERROR_TYPE_ACTION,
13686 "cannot create sample action");
13687 if (num_of_dest > 1) {
13688 dev_flow->dv.actions[sample_act_pos] =
13689 dev_flow->dv.dest_array_res->action;
13691 dev_flow->dv.actions[sample_act_pos] =
13692 dev_flow->dv.sample_res->verbs_action;
13696 * For multiple destination (sample action with ratio=1), the encap
13697 * action and port id action will be combined into group action.
13698 * So need remove the original these actions in the flow and only
13699 * use the sample action instead of.
13701 if (num_of_dest > 1 &&
13702 (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
13704 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
13706 for (i = 0; i < actions_n; i++) {
13707 if ((sample_act->dr_encap_action &&
13708 sample_act->dr_encap_action ==
13709 dev_flow->dv.actions[i]) ||
13710 (sample_act->dr_port_id_action &&
13711 sample_act->dr_port_id_action ==
13712 dev_flow->dv.actions[i]) ||
13713 (sample_act->dr_jump_action &&
13714 sample_act->dr_jump_action ==
13715 dev_flow->dv.actions[i]))
13717 temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
13719 memcpy((void *)dev_flow->dv.actions,
13720 (void *)temp_actions,
13721 tmp_actions_n * sizeof(void *));
13722 actions_n = tmp_actions_n;
13724 dev_flow->dv.actions_n = actions_n;
13725 dev_flow->act_flags = action_flags;
13726 if (wks->skip_matcher_reg)
13728 /* Register matcher. */
13729 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
13730 matcher.mask.size);
13731 matcher.priority = mlx5_get_matcher_priority(dev, attr,
13733 dev_flow->external);
13735 * When creating meter drop flow in drop table, using original
13736 * 5-tuple match, the matcher priority should be lower than
13739 if (attr->group == MLX5_FLOW_TABLE_LEVEL_METER &&
13740 dev_flow->dv.table_id == MLX5_MTR_TABLE_ID_DROP &&
13741 matcher.priority <= MLX5_REG_BITS)
13742 matcher.priority += MLX5_REG_BITS;
13743 /* reserved field no needs to be set to 0 here. */
13744 tbl_key.is_fdb = attr->transfer;
13745 tbl_key.is_egress = attr->egress;
13746 tbl_key.level = dev_flow->dv.group;
13747 tbl_key.id = dev_flow->dv.table_id;
13748 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
13749 tunnel, attr->group, error))
13755 * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13758 * @param[in, out] action
13759 * Shred RSS action holding hash RX queue objects.
13760 * @param[in] hash_fields
13761 * Defines combination of packet fields to participate in RX hash.
13762 * @param[in] tunnel
13764 * @param[in] hrxq_idx
13765 * Hash RX queue index to set.
13768 * 0 on success, otherwise negative errno value.
13771 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
13772 const uint64_t hash_fields,
13775 uint32_t *hrxqs = action->hrxq;
13777 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13778 case MLX5_RSS_HASH_IPV4:
13779 /* fall-through. */
13780 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13781 /* fall-through. */
13782 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13783 hrxqs[0] = hrxq_idx;
13785 case MLX5_RSS_HASH_IPV4_TCP:
13786 /* fall-through. */
13787 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13788 /* fall-through. */
13789 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13790 hrxqs[1] = hrxq_idx;
13792 case MLX5_RSS_HASH_IPV4_UDP:
13793 /* fall-through. */
13794 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13795 /* fall-through. */
13796 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13797 hrxqs[2] = hrxq_idx;
13799 case MLX5_RSS_HASH_IPV6:
13800 /* fall-through. */
13801 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13802 /* fall-through. */
13803 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13804 hrxqs[3] = hrxq_idx;
13806 case MLX5_RSS_HASH_IPV6_TCP:
13807 /* fall-through. */
13808 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13809 /* fall-through. */
13810 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13811 hrxqs[4] = hrxq_idx;
13813 case MLX5_RSS_HASH_IPV6_UDP:
13814 /* fall-through. */
13815 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13816 /* fall-through. */
13817 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13818 hrxqs[5] = hrxq_idx;
13820 case MLX5_RSS_HASH_NONE:
13821 hrxqs[6] = hrxq_idx;
13829 * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
13833 * Pointer to the Ethernet device structure.
13835 * Shared RSS action ID holding hash RX queue objects.
13836 * @param[in] hash_fields
13837 * Defines combination of packet fields to participate in RX hash.
13838 * @param[in] tunnel
13842 * Valid hash RX queue index, otherwise 0.
13845 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
13846 const uint64_t hash_fields)
13848 struct mlx5_priv *priv = dev->data->dev_private;
13849 struct mlx5_shared_action_rss *shared_rss =
13850 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
13851 const uint32_t *hrxqs = shared_rss->hrxq;
13853 switch (hash_fields & ~IBV_RX_HASH_INNER) {
13854 case MLX5_RSS_HASH_IPV4:
13855 /* fall-through. */
13856 case MLX5_RSS_HASH_IPV4_DST_ONLY:
13857 /* fall-through. */
13858 case MLX5_RSS_HASH_IPV4_SRC_ONLY:
13860 case MLX5_RSS_HASH_IPV4_TCP:
13861 /* fall-through. */
13862 case MLX5_RSS_HASH_IPV4_TCP_DST_ONLY:
13863 /* fall-through. */
13864 case MLX5_RSS_HASH_IPV4_TCP_SRC_ONLY:
13866 case MLX5_RSS_HASH_IPV4_UDP:
13867 /* fall-through. */
13868 case MLX5_RSS_HASH_IPV4_UDP_DST_ONLY:
13869 /* fall-through. */
13870 case MLX5_RSS_HASH_IPV4_UDP_SRC_ONLY:
13872 case MLX5_RSS_HASH_IPV6:
13873 /* fall-through. */
13874 case MLX5_RSS_HASH_IPV6_DST_ONLY:
13875 /* fall-through. */
13876 case MLX5_RSS_HASH_IPV6_SRC_ONLY:
13878 case MLX5_RSS_HASH_IPV6_TCP:
13879 /* fall-through. */
13880 case MLX5_RSS_HASH_IPV6_TCP_DST_ONLY:
13881 /* fall-through. */
13882 case MLX5_RSS_HASH_IPV6_TCP_SRC_ONLY:
13884 case MLX5_RSS_HASH_IPV6_UDP:
13885 /* fall-through. */
13886 case MLX5_RSS_HASH_IPV6_UDP_DST_ONLY:
13887 /* fall-through. */
13888 case MLX5_RSS_HASH_IPV6_UDP_SRC_ONLY:
13890 case MLX5_RSS_HASH_NONE:
13899 * Apply the flow to the NIC, lock free,
13900 * (mutex should be acquired by caller).
13903 * Pointer to the Ethernet device structure.
13904 * @param[in, out] flow
13905 * Pointer to flow structure.
13906 * @param[out] error
13907 * Pointer to error structure.
13910 * 0 on success, a negative errno value otherwise and rte_errno is set.
13913 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
13914 struct rte_flow_error *error)
13916 struct mlx5_flow_dv_workspace *dv;
13917 struct mlx5_flow_handle *dh;
13918 struct mlx5_flow_handle_dv *dv_h;
13919 struct mlx5_flow *dev_flow;
13920 struct mlx5_priv *priv = dev->data->dev_private;
13921 uint32_t handle_idx;
13925 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
13926 struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
13930 for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
13931 dev_flow = &wks->flows[idx];
13932 dv = &dev_flow->dv;
13933 dh = dev_flow->handle;
13936 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
13937 if (dv->transfer) {
13938 MLX5_ASSERT(priv->sh->dr_drop_action);
13939 dv->actions[n++] = priv->sh->dr_drop_action;
13941 #ifdef HAVE_MLX5DV_DR
13942 /* DR supports drop action placeholder. */
13943 MLX5_ASSERT(priv->sh->dr_drop_action);
13944 dv->actions[n++] = dv->group ?
13945 priv->sh->dr_drop_action :
13946 priv->root_drop_action;
13948 /* For DV we use the explicit drop queue. */
13949 MLX5_ASSERT(priv->drop_queue.hrxq);
13951 priv->drop_queue.hrxq->action;
13954 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
13955 !dv_h->rix_sample && !dv_h->rix_dest_array)) {
13956 struct mlx5_hrxq *hrxq;
13959 hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
13964 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13965 "cannot get hash queue");
13968 dh->rix_hrxq = hrxq_idx;
13969 dv->actions[n++] = hrxq->action;
13970 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
13971 struct mlx5_hrxq *hrxq = NULL;
13974 hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
13975 rss_desc->shared_rss,
13976 dev_flow->hash_fields);
13978 hrxq = mlx5_ipool_get
13979 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
13984 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13985 "cannot get hash queue");
13988 dh->rix_srss = rss_desc->shared_rss;
13989 dv->actions[n++] = hrxq->action;
13990 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
13991 if (!priv->sh->default_miss_action) {
13994 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
13995 "default miss action not be created.");
13998 dv->actions[n++] = priv->sh->default_miss_action;
14000 misc_mask = flow_dv_matcher_enable(dv->value.buf);
14001 __flow_dv_adjust_buf_size(&dv->value.size, misc_mask);
14002 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
14003 (void *)&dv->value, n,
14004 dv->actions, &dh->drv_flow);
14008 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
14010 (!priv->config.allow_duplicate_pattern &&
14012 "duplicating pattern is not allowed" :
14013 "hardware refuses to create flow");
14016 if (priv->vmwa_context &&
14017 dh->vf_vlan.tag && !dh->vf_vlan.created) {
14019 * The rule contains the VLAN pattern.
14020 * For VF we are going to create VLAN
14021 * interface to make hypervisor set correct
14022 * e-Switch vport context.
14024 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
14029 err = rte_errno; /* Save rte_errno before cleanup. */
14030 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
14031 handle_idx, dh, next) {
14032 /* hrxq is union, don't clear it if the flag is not set. */
14033 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
14034 mlx5_hrxq_release(dev, dh->rix_hrxq);
14036 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
14039 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14040 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14042 rte_errno = err; /* Restore rte_errno. */
14047 flow_dv_matcher_remove_cb(void *tool_ctx __rte_unused,
14048 struct mlx5_list_entry *entry)
14050 struct mlx5_flow_dv_matcher *resource = container_of(entry,
14054 claim_zero(mlx5_flow_os_destroy_flow_matcher(resource->matcher_object));
14055 mlx5_free(resource);
14059 * Release the flow matcher.
14062 * Pointer to Ethernet device.
14064 * Index to port ID action resource.
14067 * 1 while a reference on it exists, 0 when freed.
14070 flow_dv_matcher_release(struct rte_eth_dev *dev,
14071 struct mlx5_flow_handle *handle)
14073 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
14074 struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
14075 typeof(*tbl), tbl);
14078 MLX5_ASSERT(matcher->matcher_object);
14079 ret = mlx5_list_unregister(tbl->matchers, &matcher->entry);
14080 flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
14085 flow_dv_encap_decap_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14087 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14088 struct mlx5_flow_dv_encap_decap_resource *res =
14089 container_of(entry, typeof(*res), entry);
14091 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14092 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
14096 * Release an encap/decap resource.
14099 * Pointer to Ethernet device.
14100 * @param encap_decap_idx
14101 * Index of encap decap resource.
14104 * 1 while a reference on it exists, 0 when freed.
14107 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
14108 uint32_t encap_decap_idx)
14110 struct mlx5_priv *priv = dev->data->dev_private;
14111 struct mlx5_flow_dv_encap_decap_resource *resource;
14113 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
14117 MLX5_ASSERT(resource->action);
14118 return mlx5_hlist_unregister(priv->sh->encaps_decaps, &resource->entry);
14122 * Release an jump to table action resource.
14125 * Pointer to Ethernet device.
14127 * Index to the jump action resource.
14130 * 1 while a reference on it exists, 0 when freed.
14133 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
14136 struct mlx5_priv *priv = dev->data->dev_private;
14137 struct mlx5_flow_tbl_data_entry *tbl_data;
14139 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
14143 return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
14147 flow_dv_modify_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14149 struct mlx5_flow_dv_modify_hdr_resource *res =
14150 container_of(entry, typeof(*res), entry);
14151 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14153 claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
14154 mlx5_ipool_free(sh->mdh_ipools[res->actions_num - 1], res->idx);
14158 * Release a modify-header resource.
14161 * Pointer to Ethernet device.
14163 * Pointer to mlx5_flow_handle.
14166 * 1 while a reference on it exists, 0 when freed.
14169 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
14170 struct mlx5_flow_handle *handle)
14172 struct mlx5_priv *priv = dev->data->dev_private;
14173 struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
14175 MLX5_ASSERT(entry->action);
14176 return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
14180 flow_dv_port_id_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14182 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14183 struct mlx5_flow_dv_port_id_action_resource *resource =
14184 container_of(entry, typeof(*resource), entry);
14186 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14187 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], resource->idx);
14191 * Release port ID action resource.
14194 * Pointer to Ethernet device.
14196 * Pointer to mlx5_flow_handle.
14199 * 1 while a reference on it exists, 0 when freed.
14202 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
14205 struct mlx5_priv *priv = dev->data->dev_private;
14206 struct mlx5_flow_dv_port_id_action_resource *resource;
14208 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
14211 MLX5_ASSERT(resource->action);
14212 return mlx5_list_unregister(priv->sh->port_id_action_list,
14217 * Release shared RSS action resource.
14220 * Pointer to Ethernet device.
14222 * Shared RSS action index.
14225 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
14227 struct mlx5_priv *priv = dev->data->dev_private;
14228 struct mlx5_shared_action_rss *shared_rss;
14230 shared_rss = mlx5_ipool_get
14231 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
14232 __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14236 flow_dv_push_vlan_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry)
14238 struct mlx5_dev_ctx_shared *sh = tool_ctx;
14239 struct mlx5_flow_dv_push_vlan_action_resource *resource =
14240 container_of(entry, typeof(*resource), entry);
14242 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14243 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], resource->idx);
14247 * Release push vlan action resource.
14250 * Pointer to Ethernet device.
14252 * Pointer to mlx5_flow_handle.
14255 * 1 while a reference on it exists, 0 when freed.
14258 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
14259 struct mlx5_flow_handle *handle)
14261 struct mlx5_priv *priv = dev->data->dev_private;
14262 struct mlx5_flow_dv_push_vlan_action_resource *resource;
14263 uint32_t idx = handle->dvh.rix_push_vlan;
14265 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
14268 MLX5_ASSERT(resource->action);
14269 return mlx5_list_unregister(priv->sh->push_vlan_action_list,
14274 * Release the fate resource.
14277 * Pointer to Ethernet device.
14279 * Pointer to mlx5_flow_handle.
14282 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
14283 struct mlx5_flow_handle *handle)
14285 if (!handle->rix_fate)
14287 switch (handle->fate_action) {
14288 case MLX5_FLOW_FATE_QUEUE:
14289 if (!handle->dvh.rix_sample && !handle->dvh.rix_dest_array)
14290 mlx5_hrxq_release(dev, handle->rix_hrxq);
14292 case MLX5_FLOW_FATE_JUMP:
14293 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
14295 case MLX5_FLOW_FATE_PORT_ID:
14296 flow_dv_port_id_action_resource_release(dev,
14297 handle->rix_port_id_action);
14300 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
14303 handle->rix_fate = 0;
14307 flow_dv_sample_remove_cb(void *tool_ctx __rte_unused,
14308 struct mlx5_list_entry *entry)
14310 struct mlx5_flow_dv_sample_resource *resource = container_of(entry,
14313 struct rte_eth_dev *dev = resource->dev;
14314 struct mlx5_priv *priv = dev->data->dev_private;
14316 if (resource->verbs_action)
14317 claim_zero(mlx5_flow_os_destroy_flow_action
14318 (resource->verbs_action));
14319 if (resource->normal_path_tbl)
14320 flow_dv_tbl_resource_release(MLX5_SH(dev),
14321 resource->normal_path_tbl);
14322 flow_dv_sample_sub_actions_release(dev, &resource->sample_idx);
14323 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], resource->idx);
14324 DRV_LOG(DEBUG, "sample resource %p: removed", (void *)resource);
14328 * Release an sample resource.
14331 * Pointer to Ethernet device.
14333 * Pointer to mlx5_flow_handle.
14336 * 1 while a reference on it exists, 0 when freed.
14339 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
14340 struct mlx5_flow_handle *handle)
14342 struct mlx5_priv *priv = dev->data->dev_private;
14343 struct mlx5_flow_dv_sample_resource *resource;
14345 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
14346 handle->dvh.rix_sample);
14349 MLX5_ASSERT(resource->verbs_action);
14350 return mlx5_list_unregister(priv->sh->sample_action_list,
14355 flow_dv_dest_array_remove_cb(void *tool_ctx __rte_unused,
14356 struct mlx5_list_entry *entry)
14358 struct mlx5_flow_dv_dest_array_resource *resource =
14359 container_of(entry, typeof(*resource), entry);
14360 struct rte_eth_dev *dev = resource->dev;
14361 struct mlx5_priv *priv = dev->data->dev_private;
14364 MLX5_ASSERT(resource->action);
14365 if (resource->action)
14366 claim_zero(mlx5_flow_os_destroy_flow_action(resource->action));
14367 for (; i < resource->num_of_dest; i++)
14368 flow_dv_sample_sub_actions_release(dev,
14369 &resource->sample_idx[i]);
14370 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], resource->idx);
14371 DRV_LOG(DEBUG, "destination array resource %p: removed",
14376 * Release an destination array resource.
14379 * Pointer to Ethernet device.
14381 * Pointer to mlx5_flow_handle.
14384 * 1 while a reference on it exists, 0 when freed.
14387 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
14388 struct mlx5_flow_handle *handle)
14390 struct mlx5_priv *priv = dev->data->dev_private;
14391 struct mlx5_flow_dv_dest_array_resource *resource;
14393 resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
14394 handle->dvh.rix_dest_array);
14397 MLX5_ASSERT(resource->action);
14398 return mlx5_list_unregister(priv->sh->dest_array_list,
14403 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
14405 struct mlx5_priv *priv = dev->data->dev_private;
14406 struct mlx5_dev_ctx_shared *sh = priv->sh;
14407 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
14408 sh->geneve_tlv_option_resource;
14409 rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
14410 if (geneve_opt_resource) {
14411 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
14412 __ATOMIC_RELAXED))) {
14413 claim_zero(mlx5_devx_cmd_destroy
14414 (geneve_opt_resource->obj));
14415 mlx5_free(sh->geneve_tlv_option_resource);
14416 sh->geneve_tlv_option_resource = NULL;
14419 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
14423 * Remove the flow from the NIC but keeps it in memory.
14424 * Lock free, (mutex should be acquired by caller).
14427 * Pointer to Ethernet device.
14428 * @param[in, out] flow
14429 * Pointer to flow structure.
14432 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
14434 struct mlx5_flow_handle *dh;
14435 uint32_t handle_idx;
14436 struct mlx5_priv *priv = dev->data->dev_private;
14440 handle_idx = flow->dev_handles;
14441 while (handle_idx) {
14442 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14446 if (dh->drv_flow) {
14447 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
14448 dh->drv_flow = NULL;
14450 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
14451 flow_dv_fate_resource_release(dev, dh);
14452 if (dh->vf_vlan.tag && dh->vf_vlan.created)
14453 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
14454 handle_idx = dh->next.next;
14459 * Remove the flow from the NIC and the memory.
14460 * Lock free, (mutex should be acquired by caller).
14463 * Pointer to the Ethernet device structure.
14464 * @param[in, out] flow
14465 * Pointer to flow structure.
14468 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
14470 struct mlx5_flow_handle *dev_handle;
14471 struct mlx5_priv *priv = dev->data->dev_private;
14472 struct mlx5_flow_meter_info *fm = NULL;
14477 flow_dv_remove(dev, flow);
14478 if (flow->counter) {
14479 flow_dv_counter_free(dev, flow->counter);
14483 fm = flow_dv_meter_find_by_idx(priv, flow->meter);
14485 mlx5_flow_meter_detach(priv, fm);
14488 /* Keep the current age handling by default. */
14489 if (flow->indirect_type == MLX5_INDIRECT_ACTION_TYPE_CT && flow->ct)
14490 flow_dv_aso_ct_release(dev, flow->ct, NULL);
14491 else if (flow->age)
14492 flow_dv_aso_age_release(dev, flow->age);
14493 if (flow->geneve_tlv_option) {
14494 flow_dv_geneve_tlv_option_resource_release(dev);
14495 flow->geneve_tlv_option = 0;
14497 while (flow->dev_handles) {
14498 uint32_t tmp_idx = flow->dev_handles;
14500 dev_handle = mlx5_ipool_get(priv->sh->ipool
14501 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
14504 flow->dev_handles = dev_handle->next.next;
14505 while (dev_handle->flex_item) {
14506 int index = rte_bsf32(dev_handle->flex_item);
14508 mlx5_flex_release_index(dev, index);
14509 dev_handle->flex_item &= ~RTE_BIT32(index);
14511 if (dev_handle->dvh.matcher)
14512 flow_dv_matcher_release(dev, dev_handle);
14513 if (dev_handle->dvh.rix_sample)
14514 flow_dv_sample_resource_release(dev, dev_handle);
14515 if (dev_handle->dvh.rix_dest_array)
14516 flow_dv_dest_array_resource_release(dev, dev_handle);
14517 if (dev_handle->dvh.rix_encap_decap)
14518 flow_dv_encap_decap_resource_release(dev,
14519 dev_handle->dvh.rix_encap_decap);
14520 if (dev_handle->dvh.modify_hdr)
14521 flow_dv_modify_hdr_resource_release(dev, dev_handle);
14522 if (dev_handle->dvh.rix_push_vlan)
14523 flow_dv_push_vlan_action_resource_release(dev,
14525 if (dev_handle->dvh.rix_tag)
14526 flow_dv_tag_release(dev,
14527 dev_handle->dvh.rix_tag);
14528 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
14529 flow_dv_fate_resource_release(dev, dev_handle);
14531 srss = dev_handle->rix_srss;
14532 if (fm && dev_handle->is_meter_flow_id &&
14533 dev_handle->split_flow_id)
14534 mlx5_ipool_free(fm->flow_ipool,
14535 dev_handle->split_flow_id);
14536 else if (dev_handle->split_flow_id &&
14537 !dev_handle->is_meter_flow_id)
14538 mlx5_ipool_free(priv->sh->ipool
14539 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID],
14540 dev_handle->split_flow_id);
14541 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
14545 flow_dv_shared_rss_action_release(dev, srss);
14549 * Release array of hash RX queue objects.
14553 * Pointer to the Ethernet device structure.
14554 * @param[in, out] hrxqs
14555 * Array of hash RX queue objects.
14558 * Total number of references to hash RX queue objects in *hrxqs* array
14559 * after this operation.
14562 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
14563 uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
14568 for (i = 0; i < RTE_DIM(*hrxqs); i++) {
14569 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
14579 * Release all hash RX queue objects representing shared RSS action.
14582 * Pointer to the Ethernet device structure.
14583 * @param[in, out] action
14584 * Shared RSS action to remove hash RX queue objects from.
14587 * Total number of references to hash RX queue objects stored in *action*
14588 * after this operation.
14589 * Expected to be 0 if no external references held.
14592 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
14593 struct mlx5_shared_action_rss *shared_rss)
14595 return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq);
14599 * Adjust L3/L4 hash value of pre-created shared RSS hrxq according to
14602 * Only one hash value is available for one L3+L4 combination:
14604 * MLX5_RSS_HASH_IPV4, MLX5_RSS_HASH_IPV4_SRC_ONLY, and
14605 * MLX5_RSS_HASH_IPV4_DST_ONLY are mutually exclusive so they can share
14606 * same slot in mlx5_rss_hash_fields.
14609 * Pointer to the shared action RSS conf.
14610 * @param[in, out] hash_field
14611 * hash_field variable needed to be adjusted.
14617 __flow_dv_action_rss_l34_hash_adjust(struct mlx5_shared_action_rss *rss,
14618 uint64_t *hash_field)
14620 uint64_t rss_types = rss->origin.types;
14622 switch (*hash_field & ~IBV_RX_HASH_INNER) {
14623 case MLX5_RSS_HASH_IPV4:
14624 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
14625 *hash_field &= ~MLX5_RSS_HASH_IPV4;
14626 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14627 *hash_field |= IBV_RX_HASH_DST_IPV4;
14628 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14629 *hash_field |= IBV_RX_HASH_SRC_IPV4;
14631 *hash_field |= MLX5_RSS_HASH_IPV4;
14634 case MLX5_RSS_HASH_IPV6:
14635 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
14636 *hash_field &= ~MLX5_RSS_HASH_IPV6;
14637 if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)
14638 *hash_field |= IBV_RX_HASH_DST_IPV6;
14639 else if (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)
14640 *hash_field |= IBV_RX_HASH_SRC_IPV6;
14642 *hash_field |= MLX5_RSS_HASH_IPV6;
14645 case MLX5_RSS_HASH_IPV4_UDP:
14646 /* fall-through. */
14647 case MLX5_RSS_HASH_IPV6_UDP:
14648 if (rss_types & RTE_ETH_RSS_UDP) {
14649 *hash_field &= ~MLX5_UDP_IBV_RX_HASH;
14650 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14651 *hash_field |= IBV_RX_HASH_DST_PORT_UDP;
14652 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14653 *hash_field |= IBV_RX_HASH_SRC_PORT_UDP;
14655 *hash_field |= MLX5_UDP_IBV_RX_HASH;
14658 case MLX5_RSS_HASH_IPV4_TCP:
14659 /* fall-through. */
14660 case MLX5_RSS_HASH_IPV6_TCP:
14661 if (rss_types & RTE_ETH_RSS_TCP) {
14662 *hash_field &= ~MLX5_TCP_IBV_RX_HASH;
14663 if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)
14664 *hash_field |= IBV_RX_HASH_DST_PORT_TCP;
14665 else if (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)
14666 *hash_field |= IBV_RX_HASH_SRC_PORT_TCP;
14668 *hash_field |= MLX5_TCP_IBV_RX_HASH;
14677 * Setup shared RSS action.
14678 * Prepare set of hash RX queue objects sufficient to handle all valid
14679 * hash_fields combinations (see enum ibv_rx_hash_fields).
14682 * Pointer to the Ethernet device structure.
14683 * @param[in] action_idx
14684 * Shared RSS action ipool index.
14685 * @param[in, out] action
14686 * Partially initialized shared RSS action.
14687 * @param[out] error
14688 * Perform verbose error reporting if not NULL. Initialized in case of
14692 * 0 on success, otherwise negative errno value.
14695 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
14696 uint32_t action_idx,
14697 struct mlx5_shared_action_rss *shared_rss,
14698 struct rte_flow_error *error)
14700 struct mlx5_flow_rss_desc rss_desc = { 0 };
14704 if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl,
14705 !!dev->data->dev_started)) {
14706 return rte_flow_error_set(error, rte_errno,
14707 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14708 "cannot setup indirection table");
14710 memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
14711 rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
14712 rss_desc.const_q = shared_rss->origin.queue;
14713 rss_desc.queue_num = shared_rss->origin.queue_num;
14714 /* Set non-zero value to indicate a shared RSS. */
14715 rss_desc.shared_rss = action_idx;
14716 rss_desc.ind_tbl = shared_rss->ind_tbl;
14717 for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
14719 uint64_t hash_fields = mlx5_rss_hash_fields[i];
14722 __flow_dv_action_rss_l34_hash_adjust(shared_rss, &hash_fields);
14723 if (shared_rss->origin.level > 1) {
14724 hash_fields |= IBV_RX_HASH_INNER;
14727 rss_desc.tunnel = tunnel;
14728 rss_desc.hash_fields = hash_fields;
14729 hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
14733 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14734 "cannot get hash queue");
14735 goto error_hrxq_new;
14737 err = __flow_dv_action_rss_hrxq_set
14738 (shared_rss, hash_fields, hrxq_idx);
14744 __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14745 if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true, true))
14746 shared_rss->ind_tbl = NULL;
14752 * Create shared RSS action.
14755 * Pointer to the Ethernet device structure.
14757 * Shared action configuration.
14759 * RSS action specification used to create shared action.
14760 * @param[out] error
14761 * Perform verbose error reporting if not NULL. Initialized in case of
14765 * A valid shared action ID in case of success, 0 otherwise and
14766 * rte_errno is set.
14769 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
14770 const struct rte_flow_indir_action_conf *conf,
14771 const struct rte_flow_action_rss *rss,
14772 struct rte_flow_error *error)
14774 struct mlx5_priv *priv = dev->data->dev_private;
14775 struct mlx5_shared_action_rss *shared_rss = NULL;
14776 void *queue = NULL;
14777 struct rte_flow_action_rss *origin;
14778 const uint8_t *rss_key;
14779 uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
14782 RTE_SET_USED(conf);
14783 queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
14785 shared_rss = mlx5_ipool_zmalloc
14786 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
14787 if (!shared_rss || !queue) {
14788 rte_flow_error_set(error, ENOMEM,
14789 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14790 "cannot allocate resource memory");
14791 goto error_rss_init;
14793 if (idx > (1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET)) {
14794 rte_flow_error_set(error, E2BIG,
14795 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14796 "rss action number out of range");
14797 goto error_rss_init;
14799 shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
14800 sizeof(*shared_rss->ind_tbl),
14802 if (!shared_rss->ind_tbl) {
14803 rte_flow_error_set(error, ENOMEM,
14804 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
14805 "cannot allocate resource memory");
14806 goto error_rss_init;
14808 memcpy(queue, rss->queue, queue_size);
14809 shared_rss->ind_tbl->queues = queue;
14810 shared_rss->ind_tbl->queues_n = rss->queue_num;
14811 origin = &shared_rss->origin;
14812 origin->func = rss->func;
14813 origin->level = rss->level;
14814 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */
14815 origin->types = !rss->types ? RTE_ETH_RSS_IP : rss->types;
14816 /* NULL RSS key indicates default RSS key. */
14817 rss_key = !rss->key ? rss_hash_default_key : rss->key;
14818 memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
14819 origin->key = &shared_rss->key[0];
14820 origin->key_len = MLX5_RSS_HASH_KEY_LEN;
14821 origin->queue = queue;
14822 origin->queue_num = rss->queue_num;
14823 if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
14824 goto error_rss_init;
14825 rte_spinlock_init(&shared_rss->action_rss_sl);
14826 __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
14827 rte_spinlock_lock(&priv->shared_act_sl);
14828 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14829 &priv->rss_shared_actions, idx, shared_rss, next);
14830 rte_spinlock_unlock(&priv->shared_act_sl);
14834 if (shared_rss->ind_tbl)
14835 mlx5_free(shared_rss->ind_tbl);
14836 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14845 * Destroy the shared RSS action.
14846 * Release related hash RX queue objects.
14849 * Pointer to the Ethernet device structure.
14851 * The shared RSS action object ID to be removed.
14852 * @param[out] error
14853 * Perform verbose error reporting if not NULL. Initialized in case of
14857 * 0 on success, otherwise negative errno value.
14860 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
14861 struct rte_flow_error *error)
14863 struct mlx5_priv *priv = dev->data->dev_private;
14864 struct mlx5_shared_action_rss *shared_rss =
14865 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
14866 uint32_t old_refcnt = 1;
14868 uint16_t *queue = NULL;
14871 return rte_flow_error_set(error, EINVAL,
14872 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
14873 "invalid shared action");
14874 if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
14875 0, 0, __ATOMIC_ACQUIRE,
14877 return rte_flow_error_set(error, EBUSY,
14878 RTE_FLOW_ERROR_TYPE_ACTION,
14880 "shared rss has references");
14881 remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
14883 return rte_flow_error_set(error, EBUSY,
14884 RTE_FLOW_ERROR_TYPE_ACTION,
14886 "shared rss hrxq has references");
14887 queue = shared_rss->ind_tbl->queues;
14888 remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true,
14889 !!dev->data->dev_started);
14891 return rte_flow_error_set(error, EBUSY,
14892 RTE_FLOW_ERROR_TYPE_ACTION,
14894 "shared rss indirection table has"
14897 rte_spinlock_lock(&priv->shared_act_sl);
14898 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14899 &priv->rss_shared_actions, idx, shared_rss, next);
14900 rte_spinlock_unlock(&priv->shared_act_sl);
14901 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
14907 * Create indirect action, lock free,
14908 * (mutex should be acquired by caller).
14909 * Dispatcher for action type specific call.
14912 * Pointer to the Ethernet device structure.
14914 * Shared action configuration.
14915 * @param[in] action
14916 * Action specification used to create indirect action.
14917 * @param[out] error
14918 * Perform verbose error reporting if not NULL. Initialized in case of
14922 * A valid shared action handle in case of success, NULL otherwise and
14923 * rte_errno is set.
14925 static struct rte_flow_action_handle *
14926 flow_dv_action_create(struct rte_eth_dev *dev,
14927 const struct rte_flow_indir_action_conf *conf,
14928 const struct rte_flow_action *action,
14929 struct rte_flow_error *err)
14931 struct mlx5_priv *priv = dev->data->dev_private;
14932 uint32_t age_idx = 0;
14936 switch (action->type) {
14937 case RTE_FLOW_ACTION_TYPE_RSS:
14938 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
14939 idx = (MLX5_INDIRECT_ACTION_TYPE_RSS <<
14940 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14942 case RTE_FLOW_ACTION_TYPE_AGE:
14943 age_idx = flow_dv_aso_age_alloc(dev, err);
14948 idx = (MLX5_INDIRECT_ACTION_TYPE_AGE <<
14949 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | age_idx;
14950 flow_dv_aso_age_params_init(dev, age_idx,
14951 ((const struct rte_flow_action_age *)
14952 action->conf)->context ?
14953 ((const struct rte_flow_action_age *)
14954 action->conf)->context :
14955 (void *)(uintptr_t)idx,
14956 ((const struct rte_flow_action_age *)
14957 action->conf)->timeout);
14960 case RTE_FLOW_ACTION_TYPE_COUNT:
14961 ret = flow_dv_translate_create_counter(dev, NULL, NULL, NULL);
14962 idx = (MLX5_INDIRECT_ACTION_TYPE_COUNT <<
14963 MLX5_INDIRECT_ACTION_TYPE_OFFSET) | ret;
14965 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
14966 ret = flow_dv_translate_create_conntrack(dev, action->conf,
14968 idx = MLX5_INDIRECT_ACT_CT_GEN_IDX(PORT_ID(priv), ret);
14971 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
14972 NULL, "action type not supported");
14975 return ret ? (struct rte_flow_action_handle *)(uintptr_t)idx : NULL;
14979 * Destroy the indirect action.
14980 * Release action related resources on the NIC and the memory.
14981 * Lock free, (mutex should be acquired by caller).
14982 * Dispatcher for action type specific call.
14985 * Pointer to the Ethernet device structure.
14986 * @param[in] handle
14987 * The indirect action object handle to be removed.
14988 * @param[out] error
14989 * Perform verbose error reporting if not NULL. Initialized in case of
14993 * 0 on success, otherwise negative errno value.
14996 flow_dv_action_destroy(struct rte_eth_dev *dev,
14997 struct rte_flow_action_handle *handle,
14998 struct rte_flow_error *error)
15000 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15001 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15002 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15003 struct mlx5_flow_counter *cnt;
15004 uint32_t no_flow_refcnt = 1;
15008 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15009 return __flow_dv_action_rss_release(dev, idx, error);
15010 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15011 cnt = flow_dv_counter_get_by_idx(dev, idx, NULL);
15012 if (!__atomic_compare_exchange_n(&cnt->shared_info.refcnt,
15013 &no_flow_refcnt, 1, false,
15016 return rte_flow_error_set(error, EBUSY,
15017 RTE_FLOW_ERROR_TYPE_ACTION,
15019 "Indirect count action has references");
15020 flow_dv_counter_free(dev, idx);
15022 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15023 ret = flow_dv_aso_age_release(dev, idx);
15026 * In this case, the last flow has a reference will
15027 * actually release the age action.
15029 DRV_LOG(DEBUG, "Indirect age action %" PRIu32 " was"
15030 " released with references %d.", idx, ret);
15032 case MLX5_INDIRECT_ACTION_TYPE_CT:
15033 ret = flow_dv_aso_ct_release(dev, idx, error);
15037 DRV_LOG(DEBUG, "Connection tracking object %u still "
15038 "has references %d.", idx, ret);
15041 return rte_flow_error_set(error, ENOTSUP,
15042 RTE_FLOW_ERROR_TYPE_ACTION,
15044 "action type not supported");
15049 * Updates in place shared RSS action configuration.
15052 * Pointer to the Ethernet device structure.
15054 * The shared RSS action object ID to be updated.
15055 * @param[in] action_conf
15056 * RSS action specification used to modify *shared_rss*.
15057 * @param[out] error
15058 * Perform verbose error reporting if not NULL. Initialized in case of
15062 * 0 on success, otherwise negative errno value.
15063 * @note: currently only support update of RSS queues.
15066 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
15067 const struct rte_flow_action_rss *action_conf,
15068 struct rte_flow_error *error)
15070 struct mlx5_priv *priv = dev->data->dev_private;
15071 struct mlx5_shared_action_rss *shared_rss =
15072 mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
15074 void *queue = NULL;
15075 uint16_t *queue_old = NULL;
15076 uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
15077 bool dev_started = !!dev->data->dev_started;
15080 return rte_flow_error_set(error, EINVAL,
15081 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15082 "invalid shared action to update");
15083 if (priv->obj_ops.ind_table_modify == NULL)
15084 return rte_flow_error_set(error, ENOTSUP,
15085 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15086 "cannot modify indirection table");
15087 queue = mlx5_malloc(MLX5_MEM_ZERO,
15088 RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
15091 return rte_flow_error_set(error, ENOMEM,
15092 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15094 "cannot allocate resource memory");
15095 memcpy(queue, action_conf->queue, queue_size);
15096 MLX5_ASSERT(shared_rss->ind_tbl);
15097 rte_spinlock_lock(&shared_rss->action_rss_sl);
15098 queue_old = shared_rss->ind_tbl->queues;
15099 ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
15100 queue, action_conf->queue_num,
15101 true /* standalone */,
15102 dev_started /* ref_new_qs */,
15103 dev_started /* deref_old_qs */);
15106 ret = rte_flow_error_set(error, rte_errno,
15107 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15108 "cannot update indirection table");
15110 mlx5_free(queue_old);
15111 shared_rss->origin.queue = queue;
15112 shared_rss->origin.queue_num = action_conf->queue_num;
15114 rte_spinlock_unlock(&shared_rss->action_rss_sl);
15119 * Updates in place conntrack context or direction.
15120 * Context update should be synchronized.
15123 * Pointer to the Ethernet device structure.
15125 * The conntrack object ID to be updated.
15126 * @param[in] update
15127 * Pointer to the structure of information to update.
15128 * @param[out] error
15129 * Perform verbose error reporting if not NULL. Initialized in case of
15133 * 0 on success, otherwise negative errno value.
15136 __flow_dv_action_ct_update(struct rte_eth_dev *dev, uint32_t idx,
15137 const struct rte_flow_modify_conntrack *update,
15138 struct rte_flow_error *error)
15140 struct mlx5_priv *priv = dev->data->dev_private;
15141 struct mlx5_aso_ct_action *ct;
15142 const struct rte_flow_action_conntrack *new_prf;
15144 uint16_t owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15147 if (PORT_ID(priv) != owner)
15148 return rte_flow_error_set(error, EACCES,
15149 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15151 "CT object owned by another port");
15152 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15153 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15155 return rte_flow_error_set(error, ENOMEM,
15156 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15158 "CT object is inactive");
15159 new_prf = &update->new_ct;
15160 if (update->direction)
15161 ct->is_original = !!new_prf->is_original_dir;
15162 if (update->state) {
15163 /* Only validate the profile when it needs to be updated. */
15164 ret = mlx5_validate_action_ct(dev, new_prf, error);
15167 ret = mlx5_aso_ct_update_by_wqe(priv->sh, ct, new_prf);
15169 return rte_flow_error_set(error, EIO,
15170 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15172 "Failed to send CT context update WQE");
15173 /* Block until ready or a failure. */
15174 ret = mlx5_aso_ct_available(priv->sh, ct);
15176 rte_flow_error_set(error, rte_errno,
15177 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15179 "Timeout to get the CT update");
15185 * Updates in place shared action configuration, lock free,
15186 * (mutex should be acquired by caller).
15189 * Pointer to the Ethernet device structure.
15190 * @param[in] handle
15191 * The indirect action object handle to be updated.
15192 * @param[in] update
15193 * Action specification used to modify the action pointed by *handle*.
15194 * *update* could be of same type with the action pointed by the *handle*
15195 * handle argument, or some other structures like a wrapper, depending on
15196 * the indirect action type.
15197 * @param[out] error
15198 * Perform verbose error reporting if not NULL. Initialized in case of
15202 * 0 on success, otherwise negative errno value.
15205 flow_dv_action_update(struct rte_eth_dev *dev,
15206 struct rte_flow_action_handle *handle,
15207 const void *update,
15208 struct rte_flow_error *err)
15210 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15211 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15212 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15213 const void *action_conf;
15216 case MLX5_INDIRECT_ACTION_TYPE_RSS:
15217 action_conf = ((const struct rte_flow_action *)update)->conf;
15218 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
15219 case MLX5_INDIRECT_ACTION_TYPE_CT:
15220 return __flow_dv_action_ct_update(dev, idx, update, err);
15222 return rte_flow_error_set(err, ENOTSUP,
15223 RTE_FLOW_ERROR_TYPE_ACTION,
15225 "action type update not supported");
15230 * Destroy the meter sub policy table rules.
15231 * Lock free, (mutex should be acquired by caller).
15234 * Pointer to Ethernet device.
15235 * @param[in] sub_policy
15236 * Pointer to meter sub policy table.
15239 __flow_dv_destroy_sub_policy_rules(struct rte_eth_dev *dev,
15240 struct mlx5_flow_meter_sub_policy *sub_policy)
15242 struct mlx5_priv *priv = dev->data->dev_private;
15243 struct mlx5_flow_tbl_data_entry *tbl;
15244 struct mlx5_flow_meter_policy *policy = sub_policy->main_policy;
15245 struct mlx5_flow_meter_info *next_fm;
15246 struct mlx5_sub_policy_color_rule *color_rule;
15250 for (i = 0; i < RTE_COLORS; i++) {
15252 if (i == RTE_COLOR_GREEN && policy &&
15253 policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR)
15254 next_fm = mlx5_flow_meter_find(priv,
15255 policy->act_cnt[i].next_mtr_id, NULL);
15256 RTE_TAILQ_FOREACH_SAFE(color_rule, &sub_policy->color_rules[i],
15258 claim_zero(mlx5_flow_os_destroy_flow(color_rule->rule));
15259 tbl = container_of(color_rule->matcher->tbl,
15260 typeof(*tbl), tbl);
15261 mlx5_list_unregister(tbl->matchers,
15262 &color_rule->matcher->entry);
15263 TAILQ_REMOVE(&sub_policy->color_rules[i],
15264 color_rule, next_port);
15265 mlx5_free(color_rule);
15267 mlx5_flow_meter_detach(priv, next_fm);
15270 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15271 if (sub_policy->rix_hrxq[i]) {
15272 if (policy && !policy->is_hierarchy)
15273 mlx5_hrxq_release(dev, sub_policy->rix_hrxq[i]);
15274 sub_policy->rix_hrxq[i] = 0;
15276 if (sub_policy->jump_tbl[i]) {
15277 flow_dv_tbl_resource_release(MLX5_SH(dev),
15278 sub_policy->jump_tbl[i]);
15279 sub_policy->jump_tbl[i] = NULL;
15282 if (sub_policy->tbl_rsc) {
15283 flow_dv_tbl_resource_release(MLX5_SH(dev),
15284 sub_policy->tbl_rsc);
15285 sub_policy->tbl_rsc = NULL;
15290 * Destroy policy rules, lock free,
15291 * (mutex should be acquired by caller).
15292 * Dispatcher for action type specific call.
15295 * Pointer to the Ethernet device structure.
15296 * @param[in] mtr_policy
15297 * Meter policy struct.
15300 flow_dv_destroy_policy_rules(struct rte_eth_dev *dev,
15301 struct mlx5_flow_meter_policy *mtr_policy)
15304 struct mlx5_flow_meter_sub_policy *sub_policy;
15305 uint16_t sub_policy_num;
15307 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15308 sub_policy_num = (mtr_policy->sub_policy_num >>
15309 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15310 MLX5_MTR_SUB_POLICY_NUM_MASK;
15311 for (j = 0; j < sub_policy_num; j++) {
15312 sub_policy = mtr_policy->sub_policys[i][j];
15314 __flow_dv_destroy_sub_policy_rules(dev,
15321 * Destroy policy action, lock free,
15322 * (mutex should be acquired by caller).
15323 * Dispatcher for action type specific call.
15326 * Pointer to the Ethernet device structure.
15327 * @param[in] mtr_policy
15328 * Meter policy struct.
15331 flow_dv_destroy_mtr_policy_acts(struct rte_eth_dev *dev,
15332 struct mlx5_flow_meter_policy *mtr_policy)
15334 struct rte_flow_action *rss_action;
15335 struct mlx5_flow_handle dev_handle;
15338 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
15339 if (mtr_policy->act_cnt[i].rix_mark) {
15340 flow_dv_tag_release(dev,
15341 mtr_policy->act_cnt[i].rix_mark);
15342 mtr_policy->act_cnt[i].rix_mark = 0;
15344 if (mtr_policy->act_cnt[i].modify_hdr) {
15345 dev_handle.dvh.modify_hdr =
15346 mtr_policy->act_cnt[i].modify_hdr;
15347 flow_dv_modify_hdr_resource_release(dev, &dev_handle);
15349 switch (mtr_policy->act_cnt[i].fate_action) {
15350 case MLX5_FLOW_FATE_SHARED_RSS:
15351 rss_action = mtr_policy->act_cnt[i].rss;
15352 mlx5_free(rss_action);
15354 case MLX5_FLOW_FATE_PORT_ID:
15355 if (mtr_policy->act_cnt[i].rix_port_id_action) {
15356 flow_dv_port_id_action_resource_release(dev,
15357 mtr_policy->act_cnt[i].rix_port_id_action);
15358 mtr_policy->act_cnt[i].rix_port_id_action = 0;
15361 case MLX5_FLOW_FATE_DROP:
15362 case MLX5_FLOW_FATE_JUMP:
15363 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15364 mtr_policy->act_cnt[i].dr_jump_action[j] =
15368 /*Queue action do nothing*/
15372 for (j = 0; j < MLX5_MTR_DOMAIN_MAX; j++)
15373 mtr_policy->dr_drop_action[j] = NULL;
15377 * Create policy action per domain, lock free,
15378 * (mutex should be acquired by caller).
15379 * Dispatcher for action type specific call.
15382 * Pointer to the Ethernet device structure.
15383 * @param[in] mtr_policy
15384 * Meter policy struct.
15385 * @param[in] action
15386 * Action specification used to create meter actions.
15387 * @param[out] error
15388 * Perform verbose error reporting if not NULL. Initialized in case of
15392 * 0 on success, otherwise negative errno value.
15395 __flow_dv_create_domain_policy_acts(struct rte_eth_dev *dev,
15396 struct mlx5_flow_meter_policy *mtr_policy,
15397 const struct rte_flow_action *actions[RTE_COLORS],
15398 enum mlx5_meter_domain domain,
15399 struct rte_mtr_error *error)
15401 struct mlx5_priv *priv = dev->data->dev_private;
15402 struct rte_flow_error flow_err;
15403 const struct rte_flow_action *act;
15404 uint64_t action_flags;
15405 struct mlx5_flow_handle dh;
15406 struct mlx5_flow dev_flow;
15407 struct mlx5_flow_dv_port_id_action_resource port_id_action;
15409 uint8_t egress, transfer;
15410 struct mlx5_meter_policy_action_container *act_cnt = NULL;
15412 struct mlx5_flow_dv_modify_hdr_resource res;
15413 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
15414 sizeof(struct mlx5_modification_cmd) *
15415 (MLX5_MAX_MODIFY_NUM + 1)];
15417 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
15419 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
15420 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
15421 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
15422 memset(&dev_flow, 0, sizeof(struct mlx5_flow));
15423 memset(&port_id_action, 0,
15424 sizeof(struct mlx5_flow_dv_port_id_action_resource));
15425 memset(mhdr_res, 0, sizeof(*mhdr_res));
15426 mhdr_res->ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
15427 (egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
15428 MLX5DV_FLOW_TABLE_TYPE_NIC_RX);
15429 dev_flow.handle = &dh;
15430 dev_flow.dv.port_id_action = &port_id_action;
15431 dev_flow.external = true;
15432 for (i = 0; i < RTE_COLORS; i++) {
15433 if (i < MLX5_MTR_RTE_COLORS)
15434 act_cnt = &mtr_policy->act_cnt[i];
15435 /* Skip the color policy actions creation. */
15436 if ((i == RTE_COLOR_YELLOW && mtr_policy->skip_y) ||
15437 (i == RTE_COLOR_GREEN && mtr_policy->skip_g))
15440 for (act = actions[i];
15441 act && act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
15442 switch (act->type) {
15443 case RTE_FLOW_ACTION_TYPE_MARK:
15445 uint32_t tag_be = mlx5_flow_mark_set
15446 (((const struct rte_flow_action_mark *)
15449 if (i >= MLX5_MTR_RTE_COLORS)
15450 return -rte_mtr_error_set(error,
15452 RTE_MTR_ERROR_TYPE_METER_POLICY,
15454 "cannot create policy "
15455 "mark action for this color");
15456 dev_flow.handle->mark = 1;
15457 if (flow_dv_tag_resource_register(dev, tag_be,
15458 &dev_flow, &flow_err))
15459 return -rte_mtr_error_set(error,
15461 RTE_MTR_ERROR_TYPE_METER_POLICY,
15463 "cannot setup policy mark action");
15464 MLX5_ASSERT(dev_flow.dv.tag_resource);
15465 act_cnt->rix_mark =
15466 dev_flow.handle->dvh.rix_tag;
15467 action_flags |= MLX5_FLOW_ACTION_MARK;
15470 case RTE_FLOW_ACTION_TYPE_SET_TAG:
15471 if (i >= MLX5_MTR_RTE_COLORS)
15472 return -rte_mtr_error_set(error,
15474 RTE_MTR_ERROR_TYPE_METER_POLICY,
15476 "cannot create policy "
15477 "set tag action for this color");
15478 if (flow_dv_convert_action_set_tag
15480 (const struct rte_flow_action_set_tag *)
15481 act->conf, &flow_err))
15482 return -rte_mtr_error_set(error,
15484 RTE_MTR_ERROR_TYPE_METER_POLICY,
15485 NULL, "cannot convert policy "
15487 if (!mhdr_res->actions_num)
15488 return -rte_mtr_error_set(error,
15490 RTE_MTR_ERROR_TYPE_METER_POLICY,
15491 NULL, "cannot find policy "
15493 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
15495 case RTE_FLOW_ACTION_TYPE_DROP:
15497 struct mlx5_flow_mtr_mng *mtrmng =
15499 struct mlx5_flow_tbl_data_entry *tbl_data;
15502 * Create the drop table with
15503 * METER DROP level.
15505 if (!mtrmng->drop_tbl[domain]) {
15506 mtrmng->drop_tbl[domain] =
15507 flow_dv_tbl_resource_get(dev,
15508 MLX5_FLOW_TABLE_LEVEL_METER,
15509 egress, transfer, false, NULL, 0,
15510 0, MLX5_MTR_TABLE_ID_DROP, &flow_err);
15511 if (!mtrmng->drop_tbl[domain])
15512 return -rte_mtr_error_set
15514 RTE_MTR_ERROR_TYPE_METER_POLICY,
15516 "Failed to create meter drop table");
15518 tbl_data = container_of
15519 (mtrmng->drop_tbl[domain],
15520 struct mlx5_flow_tbl_data_entry, tbl);
15521 if (i < MLX5_MTR_RTE_COLORS) {
15522 act_cnt->dr_jump_action[domain] =
15523 tbl_data->jump.action;
15524 act_cnt->fate_action =
15525 MLX5_FLOW_FATE_DROP;
15527 if (i == RTE_COLOR_RED)
15528 mtr_policy->dr_drop_action[domain] =
15529 tbl_data->jump.action;
15530 action_flags |= MLX5_FLOW_ACTION_DROP;
15533 case RTE_FLOW_ACTION_TYPE_QUEUE:
15535 if (i >= MLX5_MTR_RTE_COLORS)
15536 return -rte_mtr_error_set(error,
15538 RTE_MTR_ERROR_TYPE_METER_POLICY,
15539 NULL, "cannot create policy "
15540 "fate queue for this color");
15542 ((const struct rte_flow_action_queue *)
15543 (act->conf))->index;
15544 act_cnt->fate_action =
15545 MLX5_FLOW_FATE_QUEUE;
15546 dev_flow.handle->fate_action =
15547 MLX5_FLOW_FATE_QUEUE;
15548 mtr_policy->is_queue = 1;
15549 action_flags |= MLX5_FLOW_ACTION_QUEUE;
15552 case RTE_FLOW_ACTION_TYPE_RSS:
15556 if (i >= MLX5_MTR_RTE_COLORS)
15557 return -rte_mtr_error_set(error,
15559 RTE_MTR_ERROR_TYPE_METER_POLICY,
15561 "cannot create policy "
15562 "rss action for this color");
15564 * Save RSS conf into policy struct
15565 * for translate stage.
15567 rss_size = (int)rte_flow_conv
15568 (RTE_FLOW_CONV_OP_ACTION,
15569 NULL, 0, act, &flow_err);
15571 return -rte_mtr_error_set(error,
15573 RTE_MTR_ERROR_TYPE_METER_POLICY,
15574 NULL, "Get the wrong "
15575 "rss action struct size");
15576 act_cnt->rss = mlx5_malloc(MLX5_MEM_ZERO,
15577 rss_size, 0, SOCKET_ID_ANY);
15579 return -rte_mtr_error_set(error,
15581 RTE_MTR_ERROR_TYPE_METER_POLICY,
15583 "Fail to malloc rss action memory");
15584 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTION,
15585 act_cnt->rss, rss_size,
15588 return -rte_mtr_error_set(error,
15590 RTE_MTR_ERROR_TYPE_METER_POLICY,
15591 NULL, "Fail to save "
15592 "rss action into policy struct");
15593 act_cnt->fate_action =
15594 MLX5_FLOW_FATE_SHARED_RSS;
15595 action_flags |= MLX5_FLOW_ACTION_RSS;
15598 case RTE_FLOW_ACTION_TYPE_PORT_ID:
15599 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
15601 struct mlx5_flow_dv_port_id_action_resource
15603 uint32_t port_id = 0;
15605 if (i >= MLX5_MTR_RTE_COLORS)
15606 return -rte_mtr_error_set(error,
15608 RTE_MTR_ERROR_TYPE_METER_POLICY,
15609 NULL, "cannot create policy "
15610 "port action for this color");
15611 memset(&port_id_resource, 0,
15612 sizeof(port_id_resource));
15613 if (flow_dv_translate_action_port_id(dev, act,
15614 &port_id, &flow_err))
15615 return -rte_mtr_error_set(error,
15617 RTE_MTR_ERROR_TYPE_METER_POLICY,
15618 NULL, "cannot translate "
15619 "policy port action");
15620 port_id_resource.port_id = port_id;
15621 if (flow_dv_port_id_action_resource_register
15622 (dev, &port_id_resource,
15623 &dev_flow, &flow_err))
15624 return -rte_mtr_error_set(error,
15626 RTE_MTR_ERROR_TYPE_METER_POLICY,
15627 NULL, "cannot setup "
15628 "policy port action");
15629 act_cnt->rix_port_id_action =
15630 dev_flow.handle->rix_port_id_action;
15631 act_cnt->fate_action =
15632 MLX5_FLOW_FATE_PORT_ID;
15633 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
15636 case RTE_FLOW_ACTION_TYPE_JUMP:
15638 uint32_t jump_group = 0;
15639 uint32_t table = 0;
15640 struct mlx5_flow_tbl_data_entry *tbl_data;
15641 struct flow_grp_info grp_info = {
15642 .external = !!dev_flow.external,
15643 .transfer = !!transfer,
15644 .fdb_def_rule = !!priv->fdb_def_rule,
15646 .skip_scale = dev_flow.skip_scale &
15647 (1 << MLX5_SCALE_FLOW_GROUP_BIT),
15649 struct mlx5_flow_meter_sub_policy *sub_policy =
15650 mtr_policy->sub_policys[domain][0];
15652 if (i >= MLX5_MTR_RTE_COLORS)
15653 return -rte_mtr_error_set(error,
15655 RTE_MTR_ERROR_TYPE_METER_POLICY,
15657 "cannot create policy "
15658 "jump action for this color");
15660 ((const struct rte_flow_action_jump *)
15662 if (mlx5_flow_group_to_table(dev, NULL,
15665 &grp_info, &flow_err))
15666 return -rte_mtr_error_set(error,
15668 RTE_MTR_ERROR_TYPE_METER_POLICY,
15669 NULL, "cannot setup "
15670 "policy jump action");
15671 sub_policy->jump_tbl[i] =
15672 flow_dv_tbl_resource_get(dev,
15675 !!dev_flow.external,
15676 NULL, jump_group, 0,
15679 (!sub_policy->jump_tbl[i])
15680 return -rte_mtr_error_set(error,
15682 RTE_MTR_ERROR_TYPE_METER_POLICY,
15683 NULL, "cannot create jump action.");
15684 tbl_data = container_of
15685 (sub_policy->jump_tbl[i],
15686 struct mlx5_flow_tbl_data_entry, tbl);
15687 act_cnt->dr_jump_action[domain] =
15688 tbl_data->jump.action;
15689 act_cnt->fate_action =
15690 MLX5_FLOW_FATE_JUMP;
15691 action_flags |= MLX5_FLOW_ACTION_JUMP;
15695 * No need to check meter hierarchy for Y or R colors
15696 * here since it is done in the validation stage.
15698 case RTE_FLOW_ACTION_TYPE_METER:
15700 const struct rte_flow_action_meter *mtr;
15701 struct mlx5_flow_meter_info *next_fm;
15702 struct mlx5_flow_meter_policy *next_policy;
15703 struct rte_flow_action tag_action;
15704 struct mlx5_rte_flow_action_set_tag set_tag;
15705 uint32_t next_mtr_idx = 0;
15708 next_fm = mlx5_flow_meter_find(priv,
15712 return -rte_mtr_error_set(error, EINVAL,
15713 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15714 "Fail to find next meter.");
15715 if (next_fm->def_policy)
15716 return -rte_mtr_error_set(error, EINVAL,
15717 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
15718 "Hierarchy only supports termination meter.");
15719 next_policy = mlx5_flow_meter_policy_find(dev,
15720 next_fm->policy_id, NULL);
15721 MLX5_ASSERT(next_policy);
15722 if (next_fm->drop_cnt) {
15725 mlx5_flow_get_reg_id(dev,
15728 (struct rte_flow_error *)error);
15729 set_tag.offset = (priv->mtr_reg_share ?
15730 MLX5_MTR_COLOR_BITS : 0);
15731 set_tag.length = (priv->mtr_reg_share ?
15732 MLX5_MTR_IDLE_BITS_IN_COLOR_REG :
15734 set_tag.data = next_mtr_idx;
15736 (enum rte_flow_action_type)
15737 MLX5_RTE_FLOW_ACTION_TYPE_TAG;
15738 tag_action.conf = &set_tag;
15739 if (flow_dv_convert_action_set_reg
15740 (mhdr_res, &tag_action,
15741 (struct rte_flow_error *)error))
15744 MLX5_FLOW_ACTION_SET_TAG;
15746 act_cnt->fate_action = MLX5_FLOW_FATE_MTR;
15747 act_cnt->next_mtr_id = next_fm->meter_id;
15748 act_cnt->next_sub_policy = NULL;
15749 mtr_policy->is_hierarchy = 1;
15750 mtr_policy->dev = next_policy->dev;
15752 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
15756 return -rte_mtr_error_set(error, ENOTSUP,
15757 RTE_MTR_ERROR_TYPE_METER_POLICY,
15758 NULL, "action type not supported");
15760 if (action_flags & MLX5_FLOW_ACTION_SET_TAG) {
15761 /* create modify action if needed. */
15762 dev_flow.dv.group = 1;
15763 if (flow_dv_modify_hdr_resource_register
15764 (dev, mhdr_res, &dev_flow, &flow_err))
15765 return -rte_mtr_error_set(error,
15767 RTE_MTR_ERROR_TYPE_METER_POLICY,
15768 NULL, "cannot register policy "
15770 act_cnt->modify_hdr =
15771 dev_flow.handle->dvh.modify_hdr;
15779 * Create policy action per domain, lock free,
15780 * (mutex should be acquired by caller).
15781 * Dispatcher for action type specific call.
15784 * Pointer to the Ethernet device structure.
15785 * @param[in] mtr_policy
15786 * Meter policy struct.
15787 * @param[in] action
15788 * Action specification used to create meter actions.
15789 * @param[out] error
15790 * Perform verbose error reporting if not NULL. Initialized in case of
15794 * 0 on success, otherwise negative errno value.
15797 flow_dv_create_mtr_policy_acts(struct rte_eth_dev *dev,
15798 struct mlx5_flow_meter_policy *mtr_policy,
15799 const struct rte_flow_action *actions[RTE_COLORS],
15800 struct rte_mtr_error *error)
15803 uint16_t sub_policy_num;
15805 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
15806 sub_policy_num = (mtr_policy->sub_policy_num >>
15807 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
15808 MLX5_MTR_SUB_POLICY_NUM_MASK;
15809 if (sub_policy_num) {
15810 ret = __flow_dv_create_domain_policy_acts(dev,
15811 mtr_policy, actions,
15812 (enum mlx5_meter_domain)i, error);
15813 /* Cleaning resource is done in the caller level. */
15822 * Query a DV flow rule for its statistics via DevX.
15825 * Pointer to Ethernet device.
15826 * @param[in] cnt_idx
15827 * Index to the flow counter.
15829 * Data retrieved by the query.
15830 * @param[out] error
15831 * Perform verbose error reporting if not NULL.
15834 * 0 on success, a negative errno value otherwise and rte_errno is set.
15837 flow_dv_query_count(struct rte_eth_dev *dev, uint32_t cnt_idx, void *data,
15838 struct rte_flow_error *error)
15840 struct mlx5_priv *priv = dev->data->dev_private;
15841 struct rte_flow_query_count *qc = data;
15843 if (!priv->sh->devx)
15844 return rte_flow_error_set(error, ENOTSUP,
15845 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15847 "counters are not supported");
15849 uint64_t pkts, bytes;
15850 struct mlx5_flow_counter *cnt;
15851 int err = _flow_dv_query_count(dev, cnt_idx, &pkts, &bytes);
15854 return rte_flow_error_set(error, -err,
15855 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15856 NULL, "cannot read counters");
15857 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15860 qc->hits = pkts - cnt->hits;
15861 qc->bytes = bytes - cnt->bytes;
15864 cnt->bytes = bytes;
15868 return rte_flow_error_set(error, EINVAL,
15869 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15871 "counters are not available");
15876 * Query counter's action pointer for a DV flow rule via DevX.
15879 * Pointer to Ethernet device.
15880 * @param[in] cnt_idx
15881 * Index to the flow counter.
15882 * @param[out] action_ptr
15883 * Action pointer for counter.
15884 * @param[out] error
15885 * Perform verbose error reporting if not NULL.
15888 * 0 on success, a negative errno value otherwise and rte_errno is set.
15891 flow_dv_query_count_ptr(struct rte_eth_dev *dev, uint32_t cnt_idx,
15892 void **action_ptr, struct rte_flow_error *error)
15894 struct mlx5_priv *priv = dev->data->dev_private;
15896 if (!priv->sh->devx || !action_ptr)
15897 return rte_flow_error_set(error, ENOTSUP,
15898 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15900 "counters are not supported");
15903 struct mlx5_flow_counter *cnt = NULL;
15904 cnt = flow_dv_counter_get_by_idx(dev, cnt_idx, NULL);
15906 *action_ptr = cnt->action;
15910 return rte_flow_error_set(error, EINVAL,
15911 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15913 "counters are not available");
15917 flow_dv_action_query(struct rte_eth_dev *dev,
15918 const struct rte_flow_action_handle *handle, void *data,
15919 struct rte_flow_error *error)
15921 struct mlx5_age_param *age_param;
15922 struct rte_flow_query_age *resp;
15923 uint32_t act_idx = (uint32_t)(uintptr_t)handle;
15924 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET;
15925 uint32_t idx = act_idx & ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1);
15926 struct mlx5_priv *priv = dev->data->dev_private;
15927 struct mlx5_aso_ct_action *ct;
15932 case MLX5_INDIRECT_ACTION_TYPE_AGE:
15933 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
15935 resp->aged = __atomic_load_n(&age_param->state,
15936 __ATOMIC_RELAXED) == AGE_TMOUT ?
15938 resp->sec_since_last_hit_valid = !resp->aged;
15939 if (resp->sec_since_last_hit_valid)
15940 resp->sec_since_last_hit = __atomic_load_n
15941 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
15943 case MLX5_INDIRECT_ACTION_TYPE_COUNT:
15944 return flow_dv_query_count(dev, idx, data, error);
15945 case MLX5_INDIRECT_ACTION_TYPE_CT:
15946 owner = (uint16_t)MLX5_INDIRECT_ACT_CT_GET_OWNER(idx);
15947 if (owner != PORT_ID(priv))
15948 return rte_flow_error_set(error, EACCES,
15949 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15951 "CT object owned by another port");
15952 dev_idx = MLX5_INDIRECT_ACT_CT_GET_IDX(idx);
15953 ct = flow_aso_ct_get_by_dev_idx(dev, dev_idx);
15956 return rte_flow_error_set(error, EFAULT,
15957 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15959 "CT object is inactive");
15960 ((struct rte_flow_action_conntrack *)data)->peer_port =
15962 ((struct rte_flow_action_conntrack *)data)->is_original_dir =
15964 if (mlx5_aso_ct_query_by_wqe(priv->sh, ct, data))
15965 return rte_flow_error_set(error, EIO,
15966 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
15968 "Failed to query CT context");
15971 return rte_flow_error_set(error, ENOTSUP,
15972 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
15973 "action type query not supported");
15978 * Query a flow rule AGE action for aging information.
15981 * Pointer to Ethernet device.
15983 * Pointer to the sub flow.
15985 * data retrieved by the query.
15986 * @param[out] error
15987 * Perform verbose error reporting if not NULL.
15990 * 0 on success, a negative errno value otherwise and rte_errno is set.
15993 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
15994 void *data, struct rte_flow_error *error)
15996 struct rte_flow_query_age *resp = data;
15997 struct mlx5_age_param *age_param;
16000 struct mlx5_aso_age_action *act =
16001 flow_aso_age_get_by_idx(dev, flow->age);
16003 age_param = &act->age_params;
16004 } else if (flow->counter) {
16005 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
16007 if (!age_param || !age_param->timeout)
16008 return rte_flow_error_set
16010 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16011 NULL, "cannot read age data");
16013 return rte_flow_error_set(error, EINVAL,
16014 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
16015 NULL, "age data not available");
16017 resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
16019 resp->sec_since_last_hit_valid = !resp->aged;
16020 if (resp->sec_since_last_hit_valid)
16021 resp->sec_since_last_hit = __atomic_load_n
16022 (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
16029 * @see rte_flow_query()
16030 * @see rte_flow_ops
16033 flow_dv_query(struct rte_eth_dev *dev,
16034 struct rte_flow *flow __rte_unused,
16035 const struct rte_flow_action *actions __rte_unused,
16036 void *data __rte_unused,
16037 struct rte_flow_error *error __rte_unused)
16041 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
16042 switch (actions->type) {
16043 case RTE_FLOW_ACTION_TYPE_VOID:
16045 case RTE_FLOW_ACTION_TYPE_COUNT:
16046 ret = flow_dv_query_count(dev, flow->counter, data,
16049 case RTE_FLOW_ACTION_TYPE_AGE:
16050 ret = flow_dv_query_age(dev, flow, data, error);
16053 return rte_flow_error_set(error, ENOTSUP,
16054 RTE_FLOW_ERROR_TYPE_ACTION,
16056 "action not supported");
16063 * Destroy the meter table set.
16064 * Lock free, (mutex should be acquired by caller).
16067 * Pointer to Ethernet device.
16069 * Meter information table.
16072 flow_dv_destroy_mtr_tbls(struct rte_eth_dev *dev,
16073 struct mlx5_flow_meter_info *fm)
16075 struct mlx5_priv *priv = dev->data->dev_private;
16078 if (!fm || !priv->config.dv_flow_en)
16080 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16081 if (fm->drop_rule[i]) {
16082 claim_zero(mlx5_flow_os_destroy_flow(fm->drop_rule[i]));
16083 fm->drop_rule[i] = NULL;
16089 flow_dv_destroy_mtr_drop_tbls(struct rte_eth_dev *dev)
16091 struct mlx5_priv *priv = dev->data->dev_private;
16092 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16093 struct mlx5_flow_tbl_data_entry *tbl;
16096 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16097 if (mtrmng->def_rule[i]) {
16098 claim_zero(mlx5_flow_os_destroy_flow
16099 (mtrmng->def_rule[i]));
16100 mtrmng->def_rule[i] = NULL;
16102 if (mtrmng->def_matcher[i]) {
16103 tbl = container_of(mtrmng->def_matcher[i]->tbl,
16104 struct mlx5_flow_tbl_data_entry, tbl);
16105 mlx5_list_unregister(tbl->matchers,
16106 &mtrmng->def_matcher[i]->entry);
16107 mtrmng->def_matcher[i] = NULL;
16109 for (j = 0; j < MLX5_REG_BITS; j++) {
16110 if (mtrmng->drop_matcher[i][j]) {
16112 container_of(mtrmng->drop_matcher[i][j]->tbl,
16113 struct mlx5_flow_tbl_data_entry,
16115 mlx5_list_unregister(tbl->matchers,
16116 &mtrmng->drop_matcher[i][j]->entry);
16117 mtrmng->drop_matcher[i][j] = NULL;
16120 if (mtrmng->drop_tbl[i]) {
16121 flow_dv_tbl_resource_release(MLX5_SH(dev),
16122 mtrmng->drop_tbl[i]);
16123 mtrmng->drop_tbl[i] = NULL;
16128 /* Number of meter flow actions, count and jump or count and drop. */
16129 #define METER_ACTIONS 2
16132 __flow_dv_destroy_domain_def_policy(struct rte_eth_dev *dev,
16133 enum mlx5_meter_domain domain)
16135 struct mlx5_priv *priv = dev->data->dev_private;
16136 struct mlx5_flow_meter_def_policy *def_policy =
16137 priv->sh->mtrmng->def_policy[domain];
16139 __flow_dv_destroy_sub_policy_rules(dev, &def_policy->sub_policy);
16140 mlx5_free(def_policy);
16141 priv->sh->mtrmng->def_policy[domain] = NULL;
16145 * Destroy the default policy table set.
16148 * Pointer to Ethernet device.
16151 flow_dv_destroy_def_policy(struct rte_eth_dev *dev)
16153 struct mlx5_priv *priv = dev->data->dev_private;
16156 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++)
16157 if (priv->sh->mtrmng->def_policy[i])
16158 __flow_dv_destroy_domain_def_policy(dev,
16159 (enum mlx5_meter_domain)i);
16160 priv->sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID;
16164 __flow_dv_create_policy_flow(struct rte_eth_dev *dev,
16165 uint32_t color_reg_c_idx,
16166 enum rte_color color, void *matcher_object,
16167 int actions_n, void *actions,
16168 bool match_src_port, const struct rte_flow_item *item,
16169 void **rule, const struct rte_flow_attr *attr)
16172 struct mlx5_flow_dv_match_params value = {
16173 .size = sizeof(value.buf),
16175 struct mlx5_flow_dv_match_params matcher = {
16176 .size = sizeof(matcher.buf),
16178 struct mlx5_priv *priv = dev->data->dev_private;
16181 if (match_src_port && (priv->representor || priv->master)) {
16182 if (flow_dv_translate_item_port_id(dev, matcher.buf,
16183 value.buf, item, attr)) {
16184 DRV_LOG(ERR, "Failed to create meter policy%d flow's"
16185 " value with port.", color);
16189 flow_dv_match_meta_reg(matcher.buf, value.buf,
16190 (enum modify_reg)color_reg_c_idx,
16191 rte_col_2_mlx5_col(color), UINT32_MAX);
16192 misc_mask = flow_dv_matcher_enable(value.buf);
16193 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16194 ret = mlx5_flow_os_create_flow(matcher_object, (void *)&value,
16195 actions_n, actions, rule);
16197 DRV_LOG(ERR, "Failed to create meter policy%d flow.", color);
16204 __flow_dv_create_policy_matcher(struct rte_eth_dev *dev,
16205 uint32_t color_reg_c_idx,
16207 struct mlx5_flow_meter_sub_policy *sub_policy,
16208 const struct rte_flow_attr *attr,
16209 bool match_src_port,
16210 const struct rte_flow_item *item,
16211 struct mlx5_flow_dv_matcher **policy_matcher,
16212 struct rte_flow_error *error)
16214 struct mlx5_list_entry *entry;
16215 struct mlx5_flow_tbl_resource *tbl_rsc = sub_policy->tbl_rsc;
16216 struct mlx5_flow_dv_matcher matcher = {
16218 .size = sizeof(matcher.mask.buf),
16222 struct mlx5_flow_dv_match_params value = {
16223 .size = sizeof(value.buf),
16225 struct mlx5_flow_cb_ctx ctx = {
16229 struct mlx5_flow_tbl_data_entry *tbl_data;
16230 struct mlx5_priv *priv = dev->data->dev_private;
16231 const uint32_t color_mask = (UINT32_C(1) << MLX5_MTR_COLOR_BITS) - 1;
16233 if (match_src_port && (priv->representor || priv->master)) {
16234 if (flow_dv_translate_item_port_id(dev, matcher.mask.buf,
16235 value.buf, item, attr)) {
16236 DRV_LOG(ERR, "Failed to register meter policy%d matcher"
16237 " with port.", priority);
16241 tbl_data = container_of(tbl_rsc, struct mlx5_flow_tbl_data_entry, tbl);
16242 if (priority < RTE_COLOR_RED)
16243 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16244 (enum modify_reg)color_reg_c_idx, 0, color_mask);
16245 matcher.priority = priority;
16246 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
16247 matcher.mask.size);
16248 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16250 DRV_LOG(ERR, "Failed to register meter drop matcher.");
16254 container_of(entry, struct mlx5_flow_dv_matcher, entry);
16259 * Create the policy rules per domain.
16262 * Pointer to Ethernet device.
16263 * @param[in] sub_policy
16264 * Pointer to sub policy table..
16265 * @param[in] egress
16266 * Direction of the table.
16267 * @param[in] transfer
16268 * E-Switch or NIC flow.
16270 * Pointer to policy action list per color.
16273 * 0 on success, -1 otherwise.
16276 __flow_dv_create_domain_policy_rules(struct rte_eth_dev *dev,
16277 struct mlx5_flow_meter_sub_policy *sub_policy,
16278 uint8_t egress, uint8_t transfer, bool match_src_port,
16279 struct mlx5_meter_policy_acts acts[RTE_COLORS])
16281 struct mlx5_priv *priv = dev->data->dev_private;
16282 struct rte_flow_error flow_err;
16283 uint32_t color_reg_c_idx;
16284 struct rte_flow_attr attr = {
16285 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
16288 .egress = !!egress,
16289 .transfer = !!transfer,
16293 int ret = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, &flow_err);
16294 struct mlx5_sub_policy_color_rule *color_rule;
16296 struct mlx5_sub_policy_color_rule *tmp_rules[RTE_COLORS] = {NULL};
16300 /* Create policy table with POLICY level. */
16301 if (!sub_policy->tbl_rsc)
16302 sub_policy->tbl_rsc = flow_dv_tbl_resource_get(dev,
16303 MLX5_FLOW_TABLE_LEVEL_POLICY,
16304 egress, transfer, false, NULL, 0, 0,
16305 sub_policy->idx, &flow_err);
16306 if (!sub_policy->tbl_rsc) {
16308 "Failed to create meter sub policy table.");
16311 /* Prepare matchers. */
16312 color_reg_c_idx = ret;
16313 for (i = 0; i < RTE_COLORS; i++) {
16314 TAILQ_INIT(&sub_policy->color_rules[i]);
16315 if (!acts[i].actions_n)
16317 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
16318 sizeof(struct mlx5_sub_policy_color_rule),
16321 DRV_LOG(ERR, "No memory to create color rule.");
16324 tmp_rules[i] = color_rule;
16325 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
16326 color_rule, next_port);
16327 color_rule->src_port = priv->representor_id;
16330 /* Create matchers for colors. */
16331 svport_match = (i != RTE_COLOR_RED) ? match_src_port : false;
16332 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
16333 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
16334 &attr, svport_match, NULL,
16335 &color_rule->matcher, &flow_err)) {
16336 DRV_LOG(ERR, "Failed to create color%u matcher.", i);
16339 /* Create flow, matching color. */
16340 if (__flow_dv_create_policy_flow(dev,
16341 color_reg_c_idx, (enum rte_color)i,
16342 color_rule->matcher->matcher_object,
16343 acts[i].actions_n, acts[i].dv_actions,
16344 svport_match, NULL, &color_rule->rule,
16346 DRV_LOG(ERR, "Failed to create color%u rule.", i);
16352 /* All the policy rules will be cleared. */
16354 color_rule = tmp_rules[i];
16356 if (color_rule->rule)
16357 mlx5_flow_os_destroy_flow(color_rule->rule);
16358 if (color_rule->matcher) {
16359 struct mlx5_flow_tbl_data_entry *tbl =
16360 container_of(color_rule->matcher->tbl,
16361 typeof(*tbl), tbl);
16362 mlx5_list_unregister(tbl->matchers,
16363 &color_rule->matcher->entry);
16365 TAILQ_REMOVE(&sub_policy->color_rules[i],
16366 color_rule, next_port);
16367 mlx5_free(color_rule);
16374 __flow_dv_create_policy_acts_rules(struct rte_eth_dev *dev,
16375 struct mlx5_flow_meter_policy *mtr_policy,
16376 struct mlx5_flow_meter_sub_policy *sub_policy,
16379 struct mlx5_priv *priv = dev->data->dev_private;
16380 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16381 struct mlx5_flow_dv_tag_resource *tag;
16382 struct mlx5_flow_dv_port_id_action_resource *port_action;
16383 struct mlx5_hrxq *hrxq;
16384 struct mlx5_flow_meter_info *next_fm = NULL;
16385 struct mlx5_flow_meter_policy *next_policy;
16386 struct mlx5_flow_meter_sub_policy *next_sub_policy;
16387 struct mlx5_flow_tbl_data_entry *tbl_data;
16388 struct rte_flow_error error;
16389 uint8_t egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16390 uint8_t transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16391 bool mtr_first = egress || (transfer && priv->representor_id != UINT16_MAX);
16392 bool match_src_port = false;
16395 /* If RSS or Queue, no previous actions / rules is created. */
16396 for (i = 0; i < RTE_COLORS; i++) {
16397 acts[i].actions_n = 0;
16398 if (i == RTE_COLOR_RED) {
16399 /* Only support drop on red. */
16400 acts[i].dv_actions[0] =
16401 mtr_policy->dr_drop_action[domain];
16402 acts[i].actions_n = 1;
16405 if (i == RTE_COLOR_GREEN &&
16406 mtr_policy->act_cnt[i].fate_action == MLX5_FLOW_FATE_MTR) {
16407 struct rte_flow_attr attr = {
16408 .transfer = transfer
16411 next_fm = mlx5_flow_meter_find(priv,
16412 mtr_policy->act_cnt[i].next_mtr_id,
16416 "Failed to get next hierarchy meter.");
16419 if (mlx5_flow_meter_attach(priv, next_fm,
16421 DRV_LOG(ERR, "%s", error.message);
16425 /* Meter action must be the first for TX. */
16427 acts[i].dv_actions[acts[i].actions_n] =
16428 next_fm->meter_action;
16429 acts[i].actions_n++;
16432 if (mtr_policy->act_cnt[i].rix_mark) {
16433 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG],
16434 mtr_policy->act_cnt[i].rix_mark);
16436 DRV_LOG(ERR, "Failed to find "
16437 "mark action for policy.");
16440 acts[i].dv_actions[acts[i].actions_n] = tag->action;
16441 acts[i].actions_n++;
16443 if (mtr_policy->act_cnt[i].modify_hdr) {
16444 acts[i].dv_actions[acts[i].actions_n] =
16445 mtr_policy->act_cnt[i].modify_hdr->action;
16446 acts[i].actions_n++;
16448 if (mtr_policy->act_cnt[i].fate_action) {
16449 switch (mtr_policy->act_cnt[i].fate_action) {
16450 case MLX5_FLOW_FATE_PORT_ID:
16451 port_action = mlx5_ipool_get
16452 (priv->sh->ipool[MLX5_IPOOL_PORT_ID],
16453 mtr_policy->act_cnt[i].rix_port_id_action);
16454 if (!port_action) {
16455 DRV_LOG(ERR, "Failed to find "
16456 "port action for policy.");
16459 acts[i].dv_actions[acts[i].actions_n] =
16460 port_action->action;
16461 acts[i].actions_n++;
16462 mtr_policy->dev = dev;
16463 match_src_port = true;
16465 case MLX5_FLOW_FATE_DROP:
16466 case MLX5_FLOW_FATE_JUMP:
16467 acts[i].dv_actions[acts[i].actions_n] =
16468 mtr_policy->act_cnt[i].dr_jump_action[domain];
16469 acts[i].actions_n++;
16471 case MLX5_FLOW_FATE_SHARED_RSS:
16472 case MLX5_FLOW_FATE_QUEUE:
16473 hrxq = mlx5_ipool_get
16474 (priv->sh->ipool[MLX5_IPOOL_HRXQ],
16475 sub_policy->rix_hrxq[i]);
16477 DRV_LOG(ERR, "Failed to find "
16478 "queue action for policy.");
16481 acts[i].dv_actions[acts[i].actions_n] =
16483 acts[i].actions_n++;
16485 case MLX5_FLOW_FATE_MTR:
16488 "No next hierarchy meter.");
16492 acts[i].dv_actions[acts[i].actions_n] =
16493 next_fm->meter_action;
16494 acts[i].actions_n++;
16496 if (mtr_policy->act_cnt[i].next_sub_policy) {
16498 mtr_policy->act_cnt[i].next_sub_policy;
16501 mlx5_flow_meter_policy_find(dev,
16502 next_fm->policy_id, NULL);
16503 MLX5_ASSERT(next_policy);
16505 next_policy->sub_policys[domain][0];
16508 container_of(next_sub_policy->tbl_rsc,
16509 struct mlx5_flow_tbl_data_entry, tbl);
16510 acts[i].dv_actions[acts[i].actions_n++] =
16511 tbl_data->jump.action;
16512 if (mtr_policy->act_cnt[i].modify_hdr)
16513 match_src_port = !!transfer;
16516 /*Queue action do nothing*/
16521 if (__flow_dv_create_domain_policy_rules(dev, sub_policy,
16522 egress, transfer, match_src_port, acts)) {
16524 "Failed to create policy rules per domain.");
16530 mlx5_flow_meter_detach(priv, next_fm);
16535 * Create the policy rules.
16538 * Pointer to Ethernet device.
16539 * @param[in,out] mtr_policy
16540 * Pointer to meter policy table.
16543 * 0 on success, -1 otherwise.
16546 flow_dv_create_policy_rules(struct rte_eth_dev *dev,
16547 struct mlx5_flow_meter_policy *mtr_policy)
16550 uint16_t sub_policy_num;
16552 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16553 sub_policy_num = (mtr_policy->sub_policy_num >>
16554 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i)) &
16555 MLX5_MTR_SUB_POLICY_NUM_MASK;
16556 if (!sub_policy_num)
16558 /* Prepare actions list and create policy rules. */
16559 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16560 mtr_policy->sub_policys[i][0], i)) {
16561 DRV_LOG(ERR, "Failed to create policy action "
16562 "list per domain.");
16570 __flow_dv_create_domain_def_policy(struct rte_eth_dev *dev, uint32_t domain)
16572 struct mlx5_priv *priv = dev->data->dev_private;
16573 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16574 struct mlx5_flow_meter_def_policy *def_policy;
16575 struct mlx5_flow_tbl_resource *jump_tbl;
16576 struct mlx5_flow_tbl_data_entry *tbl_data;
16577 uint8_t egress, transfer;
16578 struct rte_flow_error error;
16579 struct mlx5_meter_policy_acts acts[RTE_COLORS];
16582 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16583 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16584 def_policy = mtrmng->def_policy[domain];
16586 def_policy = mlx5_malloc(MLX5_MEM_ZERO,
16587 sizeof(struct mlx5_flow_meter_def_policy),
16588 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
16590 DRV_LOG(ERR, "Failed to alloc default policy table.");
16591 goto def_policy_error;
16593 mtrmng->def_policy[domain] = def_policy;
16594 /* Create the meter suffix table with SUFFIX level. */
16595 jump_tbl = flow_dv_tbl_resource_get(dev,
16596 MLX5_FLOW_TABLE_LEVEL_METER,
16597 egress, transfer, false, NULL, 0,
16598 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16601 "Failed to create meter suffix table.");
16602 goto def_policy_error;
16604 def_policy->sub_policy.jump_tbl[RTE_COLOR_GREEN] = jump_tbl;
16605 tbl_data = container_of(jump_tbl,
16606 struct mlx5_flow_tbl_data_entry, tbl);
16607 def_policy->dr_jump_action[RTE_COLOR_GREEN] =
16608 tbl_data->jump.action;
16609 acts[RTE_COLOR_GREEN].dv_actions[0] = tbl_data->jump.action;
16610 acts[RTE_COLOR_GREEN].actions_n = 1;
16612 * YELLOW has the same default policy as GREEN does.
16613 * G & Y share the same table and action. The 2nd time of table
16614 * resource getting is just to update the reference count for
16615 * the releasing stage.
16617 jump_tbl = flow_dv_tbl_resource_get(dev,
16618 MLX5_FLOW_TABLE_LEVEL_METER,
16619 egress, transfer, false, NULL, 0,
16620 0, MLX5_MTR_TABLE_ID_SUFFIX, &error);
16623 "Failed to get meter suffix table.");
16624 goto def_policy_error;
16626 def_policy->sub_policy.jump_tbl[RTE_COLOR_YELLOW] = jump_tbl;
16627 tbl_data = container_of(jump_tbl,
16628 struct mlx5_flow_tbl_data_entry, tbl);
16629 def_policy->dr_jump_action[RTE_COLOR_YELLOW] =
16630 tbl_data->jump.action;
16631 acts[RTE_COLOR_YELLOW].dv_actions[0] = tbl_data->jump.action;
16632 acts[RTE_COLOR_YELLOW].actions_n = 1;
16633 /* Create jump action to the drop table. */
16634 if (!mtrmng->drop_tbl[domain]) {
16635 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get
16636 (dev, MLX5_FLOW_TABLE_LEVEL_METER,
16637 egress, transfer, false, NULL, 0,
16638 0, MLX5_MTR_TABLE_ID_DROP, &error);
16639 if (!mtrmng->drop_tbl[domain]) {
16640 DRV_LOG(ERR, "Failed to create meter "
16641 "drop table for default policy.");
16642 goto def_policy_error;
16645 /* all RED: unique Drop table for jump action. */
16646 tbl_data = container_of(mtrmng->drop_tbl[domain],
16647 struct mlx5_flow_tbl_data_entry, tbl);
16648 def_policy->dr_jump_action[RTE_COLOR_RED] =
16649 tbl_data->jump.action;
16650 acts[RTE_COLOR_RED].dv_actions[0] = tbl_data->jump.action;
16651 acts[RTE_COLOR_RED].actions_n = 1;
16652 /* Create default policy rules. */
16653 ret = __flow_dv_create_domain_policy_rules(dev,
16654 &def_policy->sub_policy,
16655 egress, transfer, false, acts);
16657 DRV_LOG(ERR, "Failed to create default policy rules.");
16658 goto def_policy_error;
16663 __flow_dv_destroy_domain_def_policy(dev,
16664 (enum mlx5_meter_domain)domain);
16669 * Create the default policy table set.
16672 * Pointer to Ethernet device.
16674 * 0 on success, -1 otherwise.
16677 flow_dv_create_def_policy(struct rte_eth_dev *dev)
16679 struct mlx5_priv *priv = dev->data->dev_private;
16682 /* Non-termination policy table. */
16683 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16684 if (!priv->config.dv_esw_en && i == MLX5_MTR_DOMAIN_TRANSFER)
16686 if (__flow_dv_create_domain_def_policy(dev, i)) {
16687 DRV_LOG(ERR, "Failed to create default policy");
16688 /* Rollback the created default policies for others. */
16689 flow_dv_destroy_def_policy(dev);
16697 * Create the needed meter tables.
16698 * Lock free, (mutex should be acquired by caller).
16701 * Pointer to Ethernet device.
16703 * Meter information table.
16704 * @param[in] mtr_idx
16706 * @param[in] domain_bitmap
16709 * 0 on success, -1 otherwise.
16712 flow_dv_create_mtr_tbls(struct rte_eth_dev *dev,
16713 struct mlx5_flow_meter_info *fm,
16715 uint8_t domain_bitmap)
16717 struct mlx5_priv *priv = dev->data->dev_private;
16718 struct mlx5_flow_mtr_mng *mtrmng = priv->sh->mtrmng;
16719 struct rte_flow_error error;
16720 struct mlx5_flow_tbl_data_entry *tbl_data;
16721 uint8_t egress, transfer;
16722 void *actions[METER_ACTIONS];
16723 int domain, ret, i;
16724 struct mlx5_flow_counter *cnt;
16725 struct mlx5_flow_dv_match_params value = {
16726 .size = sizeof(value.buf),
16728 struct mlx5_flow_dv_match_params matcher_para = {
16729 .size = sizeof(matcher_para.buf),
16731 int mtr_id_reg_c = mlx5_flow_get_reg_id(dev, MLX5_MTR_ID,
16733 uint32_t mtr_id_mask = (UINT32_C(1) << mtrmng->max_mtr_bits) - 1;
16734 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0;
16735 struct mlx5_list_entry *entry;
16736 struct mlx5_flow_dv_matcher matcher = {
16738 .size = sizeof(matcher.mask.buf),
16741 struct mlx5_flow_dv_matcher *drop_matcher;
16742 struct mlx5_flow_cb_ctx ctx = {
16748 if (!priv->mtr_en || mtr_id_reg_c < 0) {
16749 rte_errno = ENOTSUP;
16752 for (domain = 0; domain < MLX5_MTR_DOMAIN_MAX; domain++) {
16753 if (!(domain_bitmap & (1 << domain)) ||
16754 (mtrmng->def_rule[domain] && !fm->drop_cnt))
16756 egress = (domain == MLX5_MTR_DOMAIN_EGRESS) ? 1 : 0;
16757 transfer = (domain == MLX5_MTR_DOMAIN_TRANSFER) ? 1 : 0;
16758 /* Create the drop table with METER DROP level. */
16759 if (!mtrmng->drop_tbl[domain]) {
16760 mtrmng->drop_tbl[domain] = flow_dv_tbl_resource_get(dev,
16761 MLX5_FLOW_TABLE_LEVEL_METER,
16762 egress, transfer, false, NULL, 0,
16763 0, MLX5_MTR_TABLE_ID_DROP, &error);
16764 if (!mtrmng->drop_tbl[domain]) {
16765 DRV_LOG(ERR, "Failed to create meter drop table.");
16769 /* Create default matcher in drop table. */
16770 matcher.tbl = mtrmng->drop_tbl[domain],
16771 tbl_data = container_of(mtrmng->drop_tbl[domain],
16772 struct mlx5_flow_tbl_data_entry, tbl);
16773 if (!mtrmng->def_matcher[domain]) {
16774 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16775 (enum modify_reg)mtr_id_reg_c,
16777 matcher.priority = MLX5_MTRS_DEFAULT_RULE_PRIORITY;
16778 matcher.crc = rte_raw_cksum
16779 ((const void *)matcher.mask.buf,
16780 matcher.mask.size);
16781 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16783 DRV_LOG(ERR, "Failed to register meter "
16784 "drop default matcher.");
16787 mtrmng->def_matcher[domain] = container_of(entry,
16788 struct mlx5_flow_dv_matcher, entry);
16790 /* Create default rule in drop table. */
16791 if (!mtrmng->def_rule[domain]) {
16793 actions[i++] = priv->sh->dr_drop_action;
16794 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16795 (enum modify_reg)mtr_id_reg_c, 0, 0);
16796 misc_mask = flow_dv_matcher_enable(value.buf);
16797 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16798 ret = mlx5_flow_os_create_flow
16799 (mtrmng->def_matcher[domain]->matcher_object,
16800 (void *)&value, i, actions,
16801 &mtrmng->def_rule[domain]);
16803 DRV_LOG(ERR, "Failed to create meter "
16804 "default drop rule for drop table.");
16810 MLX5_ASSERT(mtrmng->max_mtr_bits);
16811 if (!mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1]) {
16812 /* Create matchers for Drop. */
16813 flow_dv_match_meta_reg(matcher.mask.buf, value.buf,
16814 (enum modify_reg)mtr_id_reg_c, 0,
16815 (mtr_id_mask << mtr_id_offset));
16816 matcher.priority = MLX5_REG_BITS - mtrmng->max_mtr_bits;
16817 matcher.crc = rte_raw_cksum
16818 ((const void *)matcher.mask.buf,
16819 matcher.mask.size);
16820 entry = mlx5_list_register(tbl_data->matchers, &ctx);
16823 "Failed to register meter drop matcher.");
16826 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1] =
16827 container_of(entry, struct mlx5_flow_dv_matcher,
16831 mtrmng->drop_matcher[domain][mtrmng->max_mtr_bits - 1];
16832 /* Create drop rule, matching meter_id only. */
16833 flow_dv_match_meta_reg(matcher_para.buf, value.buf,
16834 (enum modify_reg)mtr_id_reg_c,
16835 (mtr_idx << mtr_id_offset), UINT32_MAX);
16837 cnt = flow_dv_counter_get_by_idx(dev,
16838 fm->drop_cnt, NULL);
16839 actions[i++] = cnt->action;
16840 actions[i++] = priv->sh->dr_drop_action;
16841 misc_mask = flow_dv_matcher_enable(value.buf);
16842 __flow_dv_adjust_buf_size(&value.size, misc_mask);
16843 ret = mlx5_flow_os_create_flow(drop_matcher->matcher_object,
16844 (void *)&value, i, actions,
16845 &fm->drop_rule[domain]);
16847 DRV_LOG(ERR, "Failed to create meter "
16848 "drop rule for drop table.");
16854 for (i = 0; i < MLX5_MTR_DOMAIN_MAX; i++) {
16855 if (fm->drop_rule[i]) {
16856 claim_zero(mlx5_flow_os_destroy_flow
16857 (fm->drop_rule[i]));
16858 fm->drop_rule[i] = NULL;
16864 static struct mlx5_flow_meter_sub_policy *
16865 __flow_dv_meter_get_rss_sub_policy(struct rte_eth_dev *dev,
16866 struct mlx5_flow_meter_policy *mtr_policy,
16867 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS],
16868 struct mlx5_flow_meter_sub_policy *next_sub_policy,
16871 struct mlx5_priv *priv = dev->data->dev_private;
16872 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
16873 uint32_t sub_policy_idx = 0;
16874 uint32_t hrxq_idx[MLX5_MTR_RTE_COLORS] = {0};
16876 struct mlx5_hrxq *hrxq;
16877 struct mlx5_flow_handle dh;
16878 struct mlx5_meter_policy_action_container *act_cnt;
16879 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
16880 uint16_t sub_policy_num;
16882 rte_spinlock_lock(&mtr_policy->sl);
16883 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16886 hrxq_idx[i] = mlx5_hrxq_get(dev, rss_desc[i]);
16887 if (!hrxq_idx[i]) {
16888 rte_spinlock_unlock(&mtr_policy->sl);
16892 sub_policy_num = (mtr_policy->sub_policy_num >>
16893 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16894 MLX5_MTR_SUB_POLICY_NUM_MASK;
16895 for (j = 0; j < sub_policy_num; j++) {
16896 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16899 mtr_policy->sub_policys[domain][j]->rix_hrxq[i])
16902 if (i >= MLX5_MTR_RTE_COLORS) {
16904 * Found the sub policy table with
16905 * the same queue per color.
16907 rte_spinlock_unlock(&mtr_policy->sl);
16908 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16909 mlx5_hrxq_release(dev, hrxq_idx[i]);
16911 return mtr_policy->sub_policys[domain][j];
16914 /* Create sub policy. */
16915 if (!mtr_policy->sub_policys[domain][0]->rix_hrxq[0]) {
16916 /* Reuse the first pre-allocated sub_policy. */
16917 sub_policy = mtr_policy->sub_policys[domain][0];
16918 sub_policy_idx = sub_policy->idx;
16920 sub_policy = mlx5_ipool_zmalloc
16921 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16924 sub_policy_idx > MLX5_MAX_SUB_POLICY_TBL_NUM) {
16925 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++)
16926 mlx5_hrxq_release(dev, hrxq_idx[i]);
16927 goto rss_sub_policy_error;
16929 sub_policy->idx = sub_policy_idx;
16930 sub_policy->main_policy = mtr_policy;
16932 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
16935 sub_policy->rix_hrxq[i] = hrxq_idx[i];
16936 if (mtr_policy->is_hierarchy) {
16937 act_cnt = &mtr_policy->act_cnt[i];
16938 act_cnt->next_sub_policy = next_sub_policy;
16939 mlx5_hrxq_release(dev, hrxq_idx[i]);
16942 * Overwrite the last action from
16943 * RSS action to Queue action.
16945 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
16948 DRV_LOG(ERR, "Failed to get policy hrxq");
16949 goto rss_sub_policy_error;
16951 act_cnt = &mtr_policy->act_cnt[i];
16952 if (act_cnt->rix_mark || act_cnt->modify_hdr) {
16953 memset(&dh, 0, sizeof(struct mlx5_flow_handle));
16954 if (act_cnt->rix_mark)
16956 dh.fate_action = MLX5_FLOW_FATE_QUEUE;
16957 dh.rix_hrxq = hrxq_idx[i];
16958 flow_drv_rxq_flags_set(dev, &dh);
16962 if (__flow_dv_create_policy_acts_rules(dev, mtr_policy,
16963 sub_policy, domain)) {
16964 DRV_LOG(ERR, "Failed to create policy "
16965 "rules for ingress domain.");
16966 goto rss_sub_policy_error;
16968 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16969 i = (mtr_policy->sub_policy_num >>
16970 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16971 MLX5_MTR_SUB_POLICY_NUM_MASK;
16972 if (i >= MLX5_MTR_RSS_MAX_SUB_POLICY) {
16973 DRV_LOG(ERR, "No free sub-policy slot.");
16974 goto rss_sub_policy_error;
16976 mtr_policy->sub_policys[domain][i] = sub_policy;
16978 mtr_policy->sub_policy_num &= ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
16979 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
16980 mtr_policy->sub_policy_num |=
16981 (i & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
16982 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
16984 rte_spinlock_unlock(&mtr_policy->sl);
16987 rss_sub_policy_error:
16989 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
16990 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
16991 i = (mtr_policy->sub_policy_num >>
16992 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
16993 MLX5_MTR_SUB_POLICY_NUM_MASK;
16994 mtr_policy->sub_policys[domain][i] = NULL;
16995 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
16999 rte_spinlock_unlock(&mtr_policy->sl);
17004 * Find the policy table for prefix table with RSS.
17007 * Pointer to Ethernet device.
17008 * @param[in] mtr_policy
17009 * Pointer to meter policy table.
17010 * @param[in] rss_desc
17011 * Pointer to rss_desc
17013 * Pointer to table set on success, NULL otherwise and rte_errno is set.
17015 static struct mlx5_flow_meter_sub_policy *
17016 flow_dv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev,
17017 struct mlx5_flow_meter_policy *mtr_policy,
17018 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS])
17020 struct mlx5_priv *priv = dev->data->dev_private;
17021 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17022 struct mlx5_flow_meter_info *next_fm;
17023 struct mlx5_flow_meter_policy *next_policy;
17024 struct mlx5_flow_meter_sub_policy *next_sub_policy = NULL;
17025 struct mlx5_flow_meter_policy *policies[MLX5_MTR_CHAIN_MAX_NUM];
17026 struct mlx5_flow_meter_sub_policy *sub_policies[MLX5_MTR_CHAIN_MAX_NUM];
17027 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17028 bool reuse_sub_policy;
17033 /* Iterate hierarchy to get all policies in this hierarchy. */
17034 policies[i++] = mtr_policy;
17035 if (!mtr_policy->is_hierarchy)
17037 if (i >= MLX5_MTR_CHAIN_MAX_NUM) {
17038 DRV_LOG(ERR, "Exceed max meter number in hierarchy.");
17041 next_fm = mlx5_flow_meter_find(priv,
17042 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17044 DRV_LOG(ERR, "Failed to get next meter in hierarchy.");
17048 mlx5_flow_meter_policy_find(dev, next_fm->policy_id,
17050 MLX5_ASSERT(next_policy);
17051 mtr_policy = next_policy;
17055 * From last policy to the first one in hierarchy,
17056 * create / get the sub policy for each of them.
17058 sub_policy = __flow_dv_meter_get_rss_sub_policy(dev,
17062 &reuse_sub_policy);
17064 DRV_LOG(ERR, "Failed to get the sub policy.");
17067 if (!reuse_sub_policy)
17068 sub_policies[j++] = sub_policy;
17069 next_sub_policy = sub_policy;
17074 uint16_t sub_policy_num;
17076 sub_policy = sub_policies[--j];
17077 mtr_policy = sub_policy->main_policy;
17078 __flow_dv_destroy_sub_policy_rules(dev, sub_policy);
17079 if (sub_policy != mtr_policy->sub_policys[domain][0]) {
17080 sub_policy_num = (mtr_policy->sub_policy_num >>
17081 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17082 MLX5_MTR_SUB_POLICY_NUM_MASK;
17083 mtr_policy->sub_policys[domain][sub_policy_num - 1] =
17086 mtr_policy->sub_policy_num &=
17087 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17088 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i));
17089 mtr_policy->sub_policy_num |=
17090 (sub_policy_num & MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17091 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * i);
17092 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17100 * Create the sub policy tag rule for all meters in hierarchy.
17103 * Pointer to Ethernet device.
17105 * Meter information table.
17106 * @param[in] src_port
17107 * The src port this extra rule should use.
17109 * The src port match item.
17110 * @param[out] error
17111 * Perform verbose error reporting if not NULL.
17113 * 0 on success, a negative errno value otherwise and rte_errno is set.
17116 flow_dv_meter_hierarchy_rule_create(struct rte_eth_dev *dev,
17117 struct mlx5_flow_meter_info *fm,
17119 const struct rte_flow_item *item,
17120 struct rte_flow_error *error)
17122 struct mlx5_priv *priv = dev->data->dev_private;
17123 struct mlx5_flow_meter_policy *mtr_policy;
17124 struct mlx5_flow_meter_sub_policy *sub_policy;
17125 struct mlx5_flow_meter_info *next_fm = NULL;
17126 struct mlx5_flow_meter_policy *next_policy;
17127 struct mlx5_flow_meter_sub_policy *next_sub_policy;
17128 struct mlx5_flow_tbl_data_entry *tbl_data;
17129 struct mlx5_sub_policy_color_rule *color_rule;
17130 struct mlx5_meter_policy_acts acts;
17131 uint32_t color_reg_c_idx;
17132 bool mtr_first = (src_port != UINT16_MAX) ? true : false;
17133 struct rte_flow_attr attr = {
17134 .group = MLX5_FLOW_TABLE_LEVEL_POLICY,
17141 uint32_t domain = MLX5_MTR_DOMAIN_TRANSFER;
17144 mtr_policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17145 MLX5_ASSERT(mtr_policy);
17146 if (!mtr_policy->is_hierarchy)
17148 next_fm = mlx5_flow_meter_find(priv,
17149 mtr_policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id, NULL);
17151 return rte_flow_error_set(error, EINVAL,
17152 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
17153 "Failed to find next meter in hierarchy.");
17155 if (!next_fm->drop_cnt)
17157 color_reg_c_idx = mlx5_flow_get_reg_id(dev, MLX5_MTR_COLOR, 0, error);
17158 sub_policy = mtr_policy->sub_policys[domain][0];
17159 for (i = 0; i < RTE_COLORS; i++) {
17160 bool rule_exist = false;
17161 struct mlx5_meter_policy_action_container *act_cnt;
17163 if (i >= RTE_COLOR_YELLOW)
17165 TAILQ_FOREACH(color_rule,
17166 &sub_policy->color_rules[i], next_port)
17167 if (color_rule->src_port == src_port) {
17173 color_rule = mlx5_malloc(MLX5_MEM_ZERO,
17174 sizeof(struct mlx5_sub_policy_color_rule),
17177 return rte_flow_error_set(error, ENOMEM,
17178 RTE_FLOW_ERROR_TYPE_ACTION,
17179 NULL, "No memory to create tag color rule.");
17180 color_rule->src_port = src_port;
17182 next_policy = mlx5_flow_meter_policy_find(dev,
17183 next_fm->policy_id, NULL);
17184 MLX5_ASSERT(next_policy);
17185 next_sub_policy = next_policy->sub_policys[domain][0];
17186 tbl_data = container_of(next_sub_policy->tbl_rsc,
17187 struct mlx5_flow_tbl_data_entry, tbl);
17188 act_cnt = &mtr_policy->act_cnt[i];
17190 acts.dv_actions[0] = next_fm->meter_action;
17191 acts.dv_actions[1] = act_cnt->modify_hdr->action;
17193 acts.dv_actions[0] = act_cnt->modify_hdr->action;
17194 acts.dv_actions[1] = next_fm->meter_action;
17196 acts.dv_actions[2] = tbl_data->jump.action;
17197 acts.actions_n = 3;
17198 if (mlx5_flow_meter_attach(priv, next_fm, &attr, error)) {
17202 if (__flow_dv_create_policy_matcher(dev, color_reg_c_idx,
17203 MLX5_MTR_POLICY_MATCHER_PRIO, sub_policy,
17205 &color_rule->matcher, error)) {
17206 rte_flow_error_set(error, errno,
17207 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17208 "Failed to create hierarchy meter matcher.");
17211 if (__flow_dv_create_policy_flow(dev, color_reg_c_idx,
17213 color_rule->matcher->matcher_object,
17214 acts.actions_n, acts.dv_actions,
17216 &color_rule->rule, &attr)) {
17217 rte_flow_error_set(error, errno,
17218 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17219 "Failed to create hierarchy meter rule.");
17222 TAILQ_INSERT_TAIL(&sub_policy->color_rules[i],
17223 color_rule, next_port);
17227 * Recursive call to iterate all meters in hierarchy and
17228 * create needed rules.
17230 return flow_dv_meter_hierarchy_rule_create(dev, next_fm,
17231 src_port, item, error);
17234 if (color_rule->rule)
17235 mlx5_flow_os_destroy_flow(color_rule->rule);
17236 if (color_rule->matcher) {
17237 struct mlx5_flow_tbl_data_entry *tbl =
17238 container_of(color_rule->matcher->tbl,
17239 typeof(*tbl), tbl);
17240 mlx5_list_unregister(tbl->matchers,
17241 &color_rule->matcher->entry);
17243 mlx5_free(color_rule);
17246 mlx5_flow_meter_detach(priv, next_fm);
17251 * Destroy the sub policy table with RX queue.
17254 * Pointer to Ethernet device.
17255 * @param[in] mtr_policy
17256 * Pointer to meter policy table.
17259 flow_dv_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev,
17260 struct mlx5_flow_meter_policy *mtr_policy)
17262 struct mlx5_priv *priv = dev->data->dev_private;
17263 struct mlx5_flow_meter_sub_policy *sub_policy = NULL;
17264 uint32_t domain = MLX5_MTR_DOMAIN_INGRESS;
17266 uint16_t sub_policy_num, new_policy_num;
17268 rte_spinlock_lock(&mtr_policy->sl);
17269 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) {
17270 switch (mtr_policy->act_cnt[i].fate_action) {
17271 case MLX5_FLOW_FATE_SHARED_RSS:
17272 sub_policy_num = (mtr_policy->sub_policy_num >>
17273 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain)) &
17274 MLX5_MTR_SUB_POLICY_NUM_MASK;
17275 new_policy_num = sub_policy_num;
17276 for (j = 0; j < sub_policy_num; j++) {
17278 mtr_policy->sub_policys[domain][j];
17280 __flow_dv_destroy_sub_policy_rules(dev,
17283 mtr_policy->sub_policys[domain][0]) {
17284 mtr_policy->sub_policys[domain][j] =
17287 (priv->sh->ipool[MLX5_IPOOL_MTR_POLICY],
17293 if (new_policy_num != sub_policy_num) {
17294 mtr_policy->sub_policy_num &=
17295 ~(MLX5_MTR_SUB_POLICY_NUM_MASK <<
17296 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain));
17297 mtr_policy->sub_policy_num |=
17299 MLX5_MTR_SUB_POLICY_NUM_MASK) <<
17300 (MLX5_MTR_SUB_POLICY_NUM_SHIFT * domain);
17303 case MLX5_FLOW_FATE_QUEUE:
17304 sub_policy = mtr_policy->sub_policys[domain][0];
17305 __flow_dv_destroy_sub_policy_rules(dev,
17309 /*Other actions without queue and do nothing*/
17313 rte_spinlock_unlock(&mtr_policy->sl);
17316 * Check whether the DR drop action is supported on the root table or not.
17318 * Create a simple flow with DR drop action on root table to validate
17319 * if DR drop action on root table is supported or not.
17322 * Pointer to rte_eth_dev structure.
17325 * 0 on success, a negative errno value otherwise and rte_errno is set.
17328 mlx5_flow_discover_dr_action_support(struct rte_eth_dev *dev)
17330 struct mlx5_priv *priv = dev->data->dev_private;
17331 struct mlx5_dev_ctx_shared *sh = priv->sh;
17332 struct mlx5_flow_dv_match_params mask = {
17333 .size = sizeof(mask.buf),
17335 struct mlx5_flow_dv_match_params value = {
17336 .size = sizeof(value.buf),
17338 struct mlx5dv_flow_matcher_attr dv_attr = {
17339 .type = IBV_FLOW_ATTR_NORMAL,
17341 .match_criteria_enable = 0,
17342 .match_mask = (void *)&mask,
17344 struct mlx5_flow_tbl_resource *tbl = NULL;
17345 void *matcher = NULL;
17349 tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL,
17353 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17354 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17355 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17356 tbl->obj, &matcher);
17359 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17360 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17361 &sh->dr_drop_action, &flow);
17364 * If DR drop action is not supported on root table, flow create will
17365 * be failed with EOPNOTSUPP or EPROTONOSUPPORT.
17369 (errno == EPROTONOSUPPORT || errno == EOPNOTSUPP))
17370 DRV_LOG(INFO, "DR drop action is not supported in root table.");
17372 DRV_LOG(ERR, "Unexpected error in DR drop action support detection");
17375 claim_zero(mlx5_flow_os_destroy_flow(flow));
17378 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17380 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17385 * Validate the batch counter support in root table.
17387 * Create a simple flow with invalid counter and drop action on root table to
17388 * validate if batch counter with offset on root table is supported or not.
17391 * Pointer to rte_eth_dev structure.
17394 * 0 on success, a negative errno value otherwise and rte_errno is set.
17397 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
17399 struct mlx5_priv *priv = dev->data->dev_private;
17400 struct mlx5_dev_ctx_shared *sh = priv->sh;
17401 struct mlx5_flow_dv_match_params mask = {
17402 .size = sizeof(mask.buf),
17404 struct mlx5_flow_dv_match_params value = {
17405 .size = sizeof(value.buf),
17407 struct mlx5dv_flow_matcher_attr dv_attr = {
17408 .type = IBV_FLOW_ATTR_NORMAL | IBV_FLOW_ATTR_FLAGS_EGRESS,
17410 .match_criteria_enable = 0,
17411 .match_mask = (void *)&mask,
17413 void *actions[2] = { 0 };
17414 struct mlx5_flow_tbl_resource *tbl = NULL;
17415 struct mlx5_devx_obj *dcs = NULL;
17416 void *matcher = NULL;
17420 tbl = flow_dv_tbl_resource_get(dev, 0, 1, 0, false, NULL,
17424 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->cdev->ctx, 0x4);
17427 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
17431 dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
17432 __flow_dv_adjust_buf_size(&mask.size, dv_attr.match_criteria_enable);
17433 ret = mlx5_flow_os_create_flow_matcher(sh->cdev->ctx, &dv_attr,
17434 tbl->obj, &matcher);
17437 __flow_dv_adjust_buf_size(&value.size, dv_attr.match_criteria_enable);
17438 ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 1,
17442 * If batch counter with offset is not supported, the driver will not
17443 * validate the invalid offset value, flow create should success.
17444 * In this case, it means batch counter is not supported in root table.
17446 * Otherwise, if flow create is failed, counter offset is supported.
17449 DRV_LOG(INFO, "Batch counter is not supported in root "
17450 "table. Switch to fallback mode.");
17451 rte_errno = ENOTSUP;
17453 claim_zero(mlx5_flow_os_destroy_flow(flow));
17455 /* Check matcher to make sure validate fail at flow create. */
17456 if (!matcher || (matcher && errno != EINVAL))
17457 DRV_LOG(ERR, "Unexpected error in counter offset "
17458 "support detection");
17462 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
17464 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
17466 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
17468 claim_zero(mlx5_devx_cmd_destroy(dcs));
17473 * Query a devx counter.
17476 * Pointer to the Ethernet device structure.
17478 * Index to the flow counter.
17480 * Set to clear the counter statistics.
17482 * The statistics value of packets.
17483 * @param[out] bytes
17484 * The statistics value of bytes.
17487 * 0 on success, otherwise return -1.
17490 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
17491 uint64_t *pkts, uint64_t *bytes)
17493 struct mlx5_priv *priv = dev->data->dev_private;
17494 struct mlx5_flow_counter *cnt;
17495 uint64_t inn_pkts, inn_bytes;
17498 if (!priv->sh->devx)
17501 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
17504 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
17505 *pkts = inn_pkts - cnt->hits;
17506 *bytes = inn_bytes - cnt->bytes;
17508 cnt->hits = inn_pkts;
17509 cnt->bytes = inn_bytes;
17515 * Get aged-out flows.
17518 * Pointer to the Ethernet device structure.
17519 * @param[in] context
17520 * The address of an array of pointers to the aged-out flows contexts.
17521 * @param[in] nb_contexts
17522 * The length of context array pointers.
17523 * @param[out] error
17524 * Perform verbose error reporting if not NULL. Initialized in case of
17528 * how many contexts get in success, otherwise negative errno value.
17529 * if nb_contexts is 0, return the amount of all aged contexts.
17530 * if nb_contexts is not 0 , return the amount of aged flows reported
17531 * in the context array.
17532 * @note: only stub for now
17535 flow_dv_get_aged_flows(struct rte_eth_dev *dev,
17537 uint32_t nb_contexts,
17538 struct rte_flow_error *error)
17540 struct mlx5_priv *priv = dev->data->dev_private;
17541 struct mlx5_age_info *age_info;
17542 struct mlx5_age_param *age_param;
17543 struct mlx5_flow_counter *counter;
17544 struct mlx5_aso_age_action *act;
17547 if (nb_contexts && !context)
17548 return rte_flow_error_set(error, EINVAL,
17549 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17550 NULL, "empty context");
17551 age_info = GET_PORT_AGE_INFO(priv);
17552 rte_spinlock_lock(&age_info->aged_sl);
17553 LIST_FOREACH(act, &age_info->aged_aso, next) {
17556 context[nb_flows - 1] =
17557 act->age_params.context;
17558 if (!(--nb_contexts))
17562 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
17565 age_param = MLX5_CNT_TO_AGE(counter);
17566 context[nb_flows - 1] = age_param->context;
17567 if (!(--nb_contexts))
17571 rte_spinlock_unlock(&age_info->aged_sl);
17572 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
17577 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
17580 flow_dv_counter_allocate(struct rte_eth_dev *dev)
17582 return flow_dv_counter_alloc(dev, 0);
17586 * Validate indirect action.
17587 * Dispatcher for action type specific validation.
17590 * Pointer to the Ethernet device structure.
17592 * Indirect action configuration.
17593 * @param[in] action
17594 * The indirect action object to validate.
17595 * @param[out] error
17596 * Perform verbose error reporting if not NULL. Initialized in case of
17600 * 0 on success, otherwise negative errno value.
17603 flow_dv_action_validate(struct rte_eth_dev *dev,
17604 const struct rte_flow_indir_action_conf *conf,
17605 const struct rte_flow_action *action,
17606 struct rte_flow_error *err)
17608 struct mlx5_priv *priv = dev->data->dev_private;
17610 RTE_SET_USED(conf);
17611 switch (action->type) {
17612 case RTE_FLOW_ACTION_TYPE_RSS:
17614 * priv->obj_ops is set according to driver capabilities.
17615 * When DevX capabilities are
17616 * sufficient, it is set to devx_obj_ops.
17617 * Otherwise, it is set to ibv_obj_ops.
17618 * ibv_obj_ops doesn't support ind_table_modify operation.
17619 * In this case the indirect RSS action can't be used.
17621 if (priv->obj_ops.ind_table_modify == NULL)
17622 return rte_flow_error_set
17624 RTE_FLOW_ERROR_TYPE_ACTION,
17626 "Indirect RSS action not supported");
17627 return mlx5_validate_action_rss(dev, action, err);
17628 case RTE_FLOW_ACTION_TYPE_AGE:
17629 if (!priv->sh->aso_age_mng)
17630 return rte_flow_error_set(err, ENOTSUP,
17631 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
17633 "Indirect age action not supported");
17634 return flow_dv_validate_action_age(0, action, dev, err);
17635 case RTE_FLOW_ACTION_TYPE_COUNT:
17636 return flow_dv_validate_action_count(dev, true, 0, err);
17637 case RTE_FLOW_ACTION_TYPE_CONNTRACK:
17638 if (!priv->sh->ct_aso_en)
17639 return rte_flow_error_set(err, ENOTSUP,
17640 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
17641 "ASO CT is not supported");
17642 return mlx5_validate_action_ct(dev, action->conf, err);
17644 return rte_flow_error_set(err, ENOTSUP,
17645 RTE_FLOW_ERROR_TYPE_ACTION,
17647 "action type not supported");
17652 * Check if the RSS configurations for colors of a meter policy match
17653 * each other, except the queues.
17656 * Pointer to the first RSS flow action.
17658 * Pointer to the second RSS flow action.
17661 * 0 on match, 1 on conflict.
17664 flow_dv_mtr_policy_rss_compare(const struct rte_flow_action_rss *r1,
17665 const struct rte_flow_action_rss *r2)
17667 if (r1 == NULL || r2 == NULL)
17669 if (!(r1->level <= 1 && r2->level <= 1) &&
17670 !(r1->level > 1 && r2->level > 1))
17672 if (r1->types != r2->types &&
17673 !((r1->types == 0 || r1->types == RTE_ETH_RSS_IP) &&
17674 (r2->types == 0 || r2->types == RTE_ETH_RSS_IP)))
17676 if (r1->key || r2->key) {
17677 const void *key1 = r1->key ? r1->key : rss_hash_default_key;
17678 const void *key2 = r2->key ? r2->key : rss_hash_default_key;
17680 if (memcmp(key1, key2, MLX5_RSS_HASH_KEY_LEN))
17687 * Validate the meter hierarchy chain for meter policy.
17690 * Pointer to the Ethernet device structure.
17691 * @param[in] meter_id
17693 * @param[in] action_flags
17694 * Holds the actions detected until now.
17695 * @param[out] is_rss
17697 * @param[out] hierarchy_domain
17698 * The domain bitmap for hierarchy policy.
17699 * @param[out] error
17700 * Perform verbose error reporting if not NULL. Initialized in case of
17704 * 0 on success, otherwise negative errno value with error set.
17707 flow_dv_validate_policy_mtr_hierarchy(struct rte_eth_dev *dev,
17709 uint64_t action_flags,
17711 uint8_t *hierarchy_domain,
17712 struct rte_mtr_error *error)
17714 struct mlx5_priv *priv = dev->data->dev_private;
17715 struct mlx5_flow_meter_info *fm;
17716 struct mlx5_flow_meter_policy *policy;
17719 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
17720 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
17721 return -rte_mtr_error_set(error, EINVAL,
17722 RTE_MTR_ERROR_TYPE_POLICER_ACTION_GREEN,
17724 "Multiple fate actions not supported.");
17725 *hierarchy_domain = 0;
17727 fm = mlx5_flow_meter_find(priv, meter_id, NULL);
17729 return -rte_mtr_error_set(error, EINVAL,
17730 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17731 "Meter not found in meter hierarchy.");
17732 if (fm->def_policy)
17733 return -rte_mtr_error_set(error, EINVAL,
17734 RTE_MTR_ERROR_TYPE_MTR_ID, NULL,
17735 "Non termination meter not supported in hierarchy.");
17736 policy = mlx5_flow_meter_policy_find(dev, fm->policy_id, NULL);
17737 MLX5_ASSERT(policy);
17739 * Only inherit the supported domains of the first meter in
17741 * One meter supports at least one domain.
17743 if (!*hierarchy_domain) {
17744 if (policy->transfer)
17745 *hierarchy_domain |=
17746 MLX5_MTR_DOMAIN_TRANSFER_BIT;
17747 if (policy->ingress)
17748 *hierarchy_domain |=
17749 MLX5_MTR_DOMAIN_INGRESS_BIT;
17750 if (policy->egress)
17751 *hierarchy_domain |= MLX5_MTR_DOMAIN_EGRESS_BIT;
17753 if (!policy->is_hierarchy) {
17754 *is_rss = policy->is_rss;
17757 meter_id = policy->act_cnt[RTE_COLOR_GREEN].next_mtr_id;
17758 if (++cnt >= MLX5_MTR_CHAIN_MAX_NUM)
17759 return -rte_mtr_error_set(error, EINVAL,
17760 RTE_MTR_ERROR_TYPE_METER_POLICY, NULL,
17761 "Exceed max hierarchy meter number.");
17767 * Validate meter policy actions.
17768 * Dispatcher for action type specific validation.
17771 * Pointer to the Ethernet device structure.
17772 * @param[in] action
17773 * The meter policy action object to validate.
17775 * Attributes of flow to determine steering domain.
17776 * @param[out] error
17777 * Perform verbose error reporting if not NULL. Initialized in case of
17781 * 0 on success, otherwise negative errno value.
17784 flow_dv_validate_mtr_policy_acts(struct rte_eth_dev *dev,
17785 const struct rte_flow_action *actions[RTE_COLORS],
17786 struct rte_flow_attr *attr,
17788 uint8_t *domain_bitmap,
17789 uint8_t *policy_mode,
17790 struct rte_mtr_error *error)
17792 struct mlx5_priv *priv = dev->data->dev_private;
17793 struct mlx5_dev_config *dev_conf = &priv->config;
17794 const struct rte_flow_action *act;
17795 uint64_t action_flags[RTE_COLORS] = {0};
17798 struct rte_flow_error flow_err;
17799 uint8_t domain_color[RTE_COLORS] = {0};
17800 uint8_t def_domain = MLX5_MTR_ALL_DOMAIN_BIT;
17801 uint8_t hierarchy_domain = 0;
17802 const struct rte_flow_action_meter *mtr;
17803 bool def_green = false;
17804 bool def_yellow = false;
17805 const struct rte_flow_action_rss *rss_color[RTE_COLORS] = {NULL};
17807 if (!priv->config.dv_esw_en)
17808 def_domain &= ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
17809 *domain_bitmap = def_domain;
17810 /* Red color could only support DROP action. */
17811 if (!actions[RTE_COLOR_RED] ||
17812 actions[RTE_COLOR_RED]->type != RTE_FLOW_ACTION_TYPE_DROP)
17813 return -rte_mtr_error_set(error, ENOTSUP,
17814 RTE_MTR_ERROR_TYPE_METER_POLICY,
17815 NULL, "Red color only supports drop action.");
17817 * Check default policy actions:
17818 * Green / Yellow: no action, Red: drop action
17819 * Either G or Y will trigger default policy actions to be created.
17821 if (!actions[RTE_COLOR_GREEN] ||
17822 actions[RTE_COLOR_GREEN]->type == RTE_FLOW_ACTION_TYPE_END)
17824 if (!actions[RTE_COLOR_YELLOW] ||
17825 actions[RTE_COLOR_YELLOW]->type == RTE_FLOW_ACTION_TYPE_END)
17827 if (def_green && def_yellow) {
17828 *policy_mode = MLX5_MTR_POLICY_MODE_DEF;
17830 } else if (!def_green && def_yellow) {
17831 *policy_mode = MLX5_MTR_POLICY_MODE_OG;
17832 } else if (def_green && !def_yellow) {
17833 *policy_mode = MLX5_MTR_POLICY_MODE_OY;
17835 *policy_mode = MLX5_MTR_POLICY_MODE_ALL;
17837 /* Set to empty string in case of NULL pointer access by user. */
17838 flow_err.message = "";
17839 for (i = 0; i < RTE_COLORS; i++) {
17841 for (action_flags[i] = 0, actions_n = 0;
17842 act && act->type != RTE_FLOW_ACTION_TYPE_END;
17844 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
17845 return -rte_mtr_error_set(error, ENOTSUP,
17846 RTE_MTR_ERROR_TYPE_METER_POLICY,
17847 NULL, "too many actions");
17848 switch (act->type) {
17849 case RTE_FLOW_ACTION_TYPE_PORT_ID:
17850 case RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT:
17851 if (!priv->config.dv_esw_en)
17852 return -rte_mtr_error_set(error,
17854 RTE_MTR_ERROR_TYPE_METER_POLICY,
17855 NULL, "PORT action validate check"
17856 " fail for ESW disable");
17857 ret = flow_dv_validate_action_port_id(dev,
17859 act, attr, &flow_err);
17861 return -rte_mtr_error_set(error,
17863 RTE_MTR_ERROR_TYPE_METER_POLICY,
17864 NULL, flow_err.message ?
17866 "PORT action validate check fail");
17868 action_flags[i] |= MLX5_FLOW_ACTION_PORT_ID;
17870 case RTE_FLOW_ACTION_TYPE_MARK:
17871 ret = flow_dv_validate_action_mark(dev, act,
17875 return -rte_mtr_error_set(error,
17877 RTE_MTR_ERROR_TYPE_METER_POLICY,
17878 NULL, flow_err.message ?
17880 "Mark action validate check fail");
17881 if (dev_conf->dv_xmeta_en !=
17882 MLX5_XMETA_MODE_LEGACY)
17883 return -rte_mtr_error_set(error,
17885 RTE_MTR_ERROR_TYPE_METER_POLICY,
17886 NULL, "Extend MARK action is "
17887 "not supported. Please try use "
17888 "default policy for meter.");
17889 action_flags[i] |= MLX5_FLOW_ACTION_MARK;
17892 case RTE_FLOW_ACTION_TYPE_SET_TAG:
17893 ret = flow_dv_validate_action_set_tag(dev,
17894 act, action_flags[i],
17897 return -rte_mtr_error_set(error,
17899 RTE_MTR_ERROR_TYPE_METER_POLICY,
17900 NULL, flow_err.message ?
17902 "Set tag action validate check fail");
17903 action_flags[i] |= MLX5_FLOW_ACTION_SET_TAG;
17906 case RTE_FLOW_ACTION_TYPE_DROP:
17907 ret = mlx5_flow_validate_action_drop
17908 (action_flags[i], attr, &flow_err);
17910 return -rte_mtr_error_set(error,
17912 RTE_MTR_ERROR_TYPE_METER_POLICY,
17913 NULL, flow_err.message ?
17915 "Drop action validate check fail");
17916 action_flags[i] |= MLX5_FLOW_ACTION_DROP;
17919 case RTE_FLOW_ACTION_TYPE_QUEUE:
17921 * Check whether extensive
17922 * metadata feature is engaged.
17924 if (dev_conf->dv_flow_en &&
17925 (dev_conf->dv_xmeta_en !=
17926 MLX5_XMETA_MODE_LEGACY) &&
17927 mlx5_flow_ext_mreg_supported(dev))
17928 return -rte_mtr_error_set(error,
17930 RTE_MTR_ERROR_TYPE_METER_POLICY,
17931 NULL, "Queue action with meta "
17932 "is not supported. Please try use "
17933 "default policy for meter.");
17934 ret = mlx5_flow_validate_action_queue(act,
17935 action_flags[i], dev,
17938 return -rte_mtr_error_set(error,
17940 RTE_MTR_ERROR_TYPE_METER_POLICY,
17941 NULL, flow_err.message ?
17943 "Queue action validate check fail");
17944 action_flags[i] |= MLX5_FLOW_ACTION_QUEUE;
17947 case RTE_FLOW_ACTION_TYPE_RSS:
17948 if (dev_conf->dv_flow_en &&
17949 (dev_conf->dv_xmeta_en !=
17950 MLX5_XMETA_MODE_LEGACY) &&
17951 mlx5_flow_ext_mreg_supported(dev))
17952 return -rte_mtr_error_set(error,
17954 RTE_MTR_ERROR_TYPE_METER_POLICY,
17955 NULL, "RSS action with meta "
17956 "is not supported. Please try use "
17957 "default policy for meter.");
17958 ret = mlx5_validate_action_rss(dev, act,
17961 return -rte_mtr_error_set(error,
17963 RTE_MTR_ERROR_TYPE_METER_POLICY,
17964 NULL, flow_err.message ?
17966 "RSS action validate check fail");
17967 action_flags[i] |= MLX5_FLOW_ACTION_RSS;
17969 /* Either G or Y will set the RSS. */
17970 rss_color[i] = act->conf;
17972 case RTE_FLOW_ACTION_TYPE_JUMP:
17973 ret = flow_dv_validate_action_jump(dev,
17974 NULL, act, action_flags[i],
17975 attr, true, &flow_err);
17977 return -rte_mtr_error_set(error,
17979 RTE_MTR_ERROR_TYPE_METER_POLICY,
17980 NULL, flow_err.message ?
17982 "Jump action validate check fail");
17984 action_flags[i] |= MLX5_FLOW_ACTION_JUMP;
17987 * Only the last meter in the hierarchy will support
17988 * the YELLOW color steering. Then in the meter policy
17989 * actions list, there should be no other meter inside.
17991 case RTE_FLOW_ACTION_TYPE_METER:
17992 if (i != RTE_COLOR_GREEN)
17993 return -rte_mtr_error_set(error,
17995 RTE_MTR_ERROR_TYPE_METER_POLICY,
17997 "Meter hierarchy only supports GREEN color.");
17998 if (*policy_mode != MLX5_MTR_POLICY_MODE_OG)
17999 return -rte_mtr_error_set(error,
18001 RTE_MTR_ERROR_TYPE_METER_POLICY,
18003 "No yellow policy should be provided in meter hierarchy.");
18005 ret = flow_dv_validate_policy_mtr_hierarchy(dev,
18015 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY;
18018 return -rte_mtr_error_set(error, ENOTSUP,
18019 RTE_MTR_ERROR_TYPE_METER_POLICY,
18021 "Doesn't support optional action");
18024 if (action_flags[i] & MLX5_FLOW_ACTION_PORT_ID) {
18025 domain_color[i] = MLX5_MTR_DOMAIN_TRANSFER_BIT;
18026 } else if ((action_flags[i] &
18027 (MLX5_FLOW_ACTION_RSS | MLX5_FLOW_ACTION_QUEUE)) ||
18028 (action_flags[i] & MLX5_FLOW_ACTION_MARK)) {
18030 * Only support MLX5_XMETA_MODE_LEGACY
18031 * so MARK action is only in ingress domain.
18033 domain_color[i] = MLX5_MTR_DOMAIN_INGRESS_BIT;
18035 domain_color[i] = def_domain;
18036 if (action_flags[i] &&
18037 !(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18039 ~MLX5_MTR_DOMAIN_TRANSFER_BIT;
18041 if (action_flags[i] &
18042 MLX5_FLOW_ACTION_METER_WITH_TERMINATED_POLICY)
18043 domain_color[i] &= hierarchy_domain;
18045 * Non-termination actions only support NIC Tx domain.
18046 * The adjustion should be skipped when there is no
18047 * action or only END is provided. The default domains
18048 * bit-mask is set to find the MIN intersection.
18049 * The action flags checking should also be skipped.
18051 if ((def_green && i == RTE_COLOR_GREEN) ||
18052 (def_yellow && i == RTE_COLOR_YELLOW))
18055 * Validate the drop action mutual exclusion
18056 * with other actions. Drop action is mutually-exclusive
18057 * with any other action, except for Count action.
18059 if ((action_flags[i] & MLX5_FLOW_ACTION_DROP) &&
18060 (action_flags[i] & ~MLX5_FLOW_ACTION_DROP)) {
18061 return -rte_mtr_error_set(error, ENOTSUP,
18062 RTE_MTR_ERROR_TYPE_METER_POLICY,
18063 NULL, "Drop action is mutually-exclusive "
18064 "with any other action");
18066 /* Eswitch has few restrictions on using items and actions */
18067 if (domain_color[i] & MLX5_MTR_DOMAIN_TRANSFER_BIT) {
18068 if (!mlx5_flow_ext_mreg_supported(dev) &&
18069 action_flags[i] & MLX5_FLOW_ACTION_MARK)
18070 return -rte_mtr_error_set(error, ENOTSUP,
18071 RTE_MTR_ERROR_TYPE_METER_POLICY,
18072 NULL, "unsupported action MARK");
18073 if (action_flags[i] & MLX5_FLOW_ACTION_QUEUE)
18074 return -rte_mtr_error_set(error, ENOTSUP,
18075 RTE_MTR_ERROR_TYPE_METER_POLICY,
18076 NULL, "unsupported action QUEUE");
18077 if (action_flags[i] & MLX5_FLOW_ACTION_RSS)
18078 return -rte_mtr_error_set(error, ENOTSUP,
18079 RTE_MTR_ERROR_TYPE_METER_POLICY,
18080 NULL, "unsupported action RSS");
18081 if (!(action_flags[i] & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
18082 return -rte_mtr_error_set(error, ENOTSUP,
18083 RTE_MTR_ERROR_TYPE_METER_POLICY,
18084 NULL, "no fate action is found");
18086 if (!(action_flags[i] & MLX5_FLOW_FATE_ACTIONS) &&
18087 (domain_color[i] & MLX5_MTR_DOMAIN_INGRESS_BIT)) {
18088 if ((domain_color[i] &
18089 MLX5_MTR_DOMAIN_EGRESS_BIT))
18091 MLX5_MTR_DOMAIN_EGRESS_BIT;
18093 return -rte_mtr_error_set(error,
18095 RTE_MTR_ERROR_TYPE_METER_POLICY,
18097 "no fate action is found");
18101 /* If both colors have RSS, the attributes should be the same. */
18102 if (flow_dv_mtr_policy_rss_compare(rss_color[RTE_COLOR_GREEN],
18103 rss_color[RTE_COLOR_YELLOW]))
18104 return -rte_mtr_error_set(error, EINVAL,
18105 RTE_MTR_ERROR_TYPE_METER_POLICY,
18106 NULL, "policy RSS attr conflict");
18107 if (rss_color[RTE_COLOR_GREEN] || rss_color[RTE_COLOR_YELLOW])
18109 /* "domain_color[C]" is non-zero for each color, default is ALL. */
18110 if (!def_green && !def_yellow &&
18111 domain_color[RTE_COLOR_GREEN] != domain_color[RTE_COLOR_YELLOW] &&
18112 !(action_flags[RTE_COLOR_GREEN] & MLX5_FLOW_ACTION_DROP) &&
18113 !(action_flags[RTE_COLOR_YELLOW] & MLX5_FLOW_ACTION_DROP))
18114 return -rte_mtr_error_set(error, EINVAL,
18115 RTE_MTR_ERROR_TYPE_METER_POLICY,
18116 NULL, "policy domains conflict");
18118 * At least one color policy is listed in the actions, the domains
18119 * to be supported should be the intersection.
18121 *domain_bitmap = domain_color[RTE_COLOR_GREEN] &
18122 domain_color[RTE_COLOR_YELLOW];
18127 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
18129 struct mlx5_priv *priv = dev->data->dev_private;
18132 if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
18133 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
18138 if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
18139 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
18143 if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
18144 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
18152 * Discover the number of available flow priorities
18153 * by trying to create a flow with the highest priority value
18154 * for each possible number.
18159 * List of possible number of available priorities.
18160 * @param[in] vprio_n
18161 * Size of @p vprio array.
18163 * On success, number of available flow priorities.
18164 * On failure, a negative errno-style code and rte_errno is set.
18167 flow_dv_discover_priorities(struct rte_eth_dev *dev,
18168 const uint16_t *vprio, int vprio_n)
18170 struct mlx5_priv *priv = dev->data->dev_private;
18171 struct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];
18172 struct rte_flow_item_eth eth;
18173 struct rte_flow_item item = {
18174 .type = RTE_FLOW_ITEM_TYPE_ETH,
18178 struct mlx5_flow_dv_matcher matcher = {
18180 .size = sizeof(matcher.mask.buf),
18183 union mlx5_flow_tbl_key tbl_key;
18184 struct mlx5_flow flow;
18186 struct rte_flow_error error;
18188 int i, err, ret = -ENOTSUP;
18191 * Prepare a flow with a catch-all pattern and a drop action.
18192 * Use drop queue, because shared drop action may be unavailable.
18194 action = priv->drop_queue.hrxq->action;
18195 if (action == NULL) {
18196 DRV_LOG(ERR, "Priority discovery requires a drop action");
18197 rte_errno = ENOTSUP;
18200 memset(&flow, 0, sizeof(flow));
18201 flow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);
18202 if (flow.handle == NULL) {
18203 DRV_LOG(ERR, "Cannot create flow handle");
18204 rte_errno = ENOMEM;
18207 flow.ingress = true;
18208 flow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
18209 flow.dv.actions[0] = action;
18210 flow.dv.actions_n = 1;
18211 memset(ð, 0, sizeof(eth));
18212 flow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,
18213 &item, /* inner */ false, /* group */ 0);
18214 matcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);
18215 for (i = 0; i < vprio_n; i++) {
18216 /* Configure the next proposed maximum priority. */
18217 matcher.priority = vprio[i] - 1;
18218 memset(&tbl_key, 0, sizeof(tbl_key));
18219 err = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,
18224 /* This action is pure SW and must always succeed. */
18225 DRV_LOG(ERR, "Cannot register matcher");
18229 /* Try to apply the flow to HW. */
18230 misc_mask = flow_dv_matcher_enable(flow.dv.value.buf);
18231 __flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);
18232 err = mlx5_flow_os_create_flow
18233 (flow.handle->dvh.matcher->matcher_object,
18234 (void *)&flow.dv.value, flow.dv.actions_n,
18235 flow.dv.actions, &flow.handle->drv_flow);
18237 claim_zero(mlx5_flow_os_destroy_flow
18238 (flow.handle->drv_flow));
18239 flow.handle->drv_flow = NULL;
18241 claim_zero(flow_dv_matcher_release(dev, flow.handle));
18246 mlx5_ipool_free(pool, flow.handle_idx);
18247 /* Set rte_errno if no expected priority value matched. */
18253 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
18254 .validate = flow_dv_validate,
18255 .prepare = flow_dv_prepare,
18256 .translate = flow_dv_translate,
18257 .apply = flow_dv_apply,
18258 .remove = flow_dv_remove,
18259 .destroy = flow_dv_destroy,
18260 .query = flow_dv_query,
18261 .create_mtr_tbls = flow_dv_create_mtr_tbls,
18262 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbls,
18263 .destroy_mtr_drop_tbls = flow_dv_destroy_mtr_drop_tbls,
18264 .create_meter = flow_dv_mtr_alloc,
18265 .free_meter = flow_dv_aso_mtr_release_to_pool,
18266 .validate_mtr_acts = flow_dv_validate_mtr_policy_acts,
18267 .create_mtr_acts = flow_dv_create_mtr_policy_acts,
18268 .destroy_mtr_acts = flow_dv_destroy_mtr_policy_acts,
18269 .create_policy_rules = flow_dv_create_policy_rules,
18270 .destroy_policy_rules = flow_dv_destroy_policy_rules,
18271 .create_def_policy = flow_dv_create_def_policy,
18272 .destroy_def_policy = flow_dv_destroy_def_policy,
18273 .meter_sub_policy_rss_prepare = flow_dv_meter_sub_policy_rss_prepare,
18274 .meter_hierarchy_rule_create = flow_dv_meter_hierarchy_rule_create,
18275 .destroy_sub_policy_with_rxq = flow_dv_destroy_sub_policy_with_rxq,
18276 .counter_alloc = flow_dv_counter_allocate,
18277 .counter_free = flow_dv_counter_free,
18278 .counter_query = flow_dv_counter_query,
18279 .get_aged_flows = flow_dv_get_aged_flows,
18280 .action_validate = flow_dv_action_validate,
18281 .action_create = flow_dv_action_create,
18282 .action_destroy = flow_dv_action_destroy,
18283 .action_update = flow_dv_action_update,
18284 .action_query = flow_dv_action_query,
18285 .sync_domain = flow_dv_sync_domain,
18286 .discover_priorities = flow_dv_discover_priorities,
18287 .item_create = flow_dv_item_create,
18288 .item_release = flow_dv_item_release,
18291 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */