1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
58 sizeof(struct rte_flow_item_ipv4))
59 /* VLAN header definitions */
60 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
61 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
62 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
63 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
64 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
79 * Initialize flow attributes structure according to flow items' types.
81 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
82 * mode. For tunnel mode, the items to be modified are the outermost ones.
85 * Pointer to item specification.
87 * Pointer to flow attributes structure.
90 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
92 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
94 case RTE_FLOW_ITEM_TYPE_IPV4:
98 case RTE_FLOW_ITEM_TYPE_IPV6:
102 case RTE_FLOW_ITEM_TYPE_UDP:
106 case RTE_FLOW_ITEM_TYPE_TCP:
118 * Convert rte_mtr_color to mlx5 color.
127 rte_col_2_mlx5_col(enum rte_color rcol)
130 case RTE_COLOR_GREEN:
131 return MLX5_FLOW_COLOR_GREEN;
132 case RTE_COLOR_YELLOW:
133 return MLX5_FLOW_COLOR_YELLOW;
135 return MLX5_FLOW_COLOR_RED;
139 return MLX5_FLOW_COLOR_UNDEFINED;
142 struct field_modify_info {
143 uint32_t size; /* Size of field in protocol header, in bytes. */
144 uint32_t offset; /* Offset of field in protocol header, in bytes. */
145 enum mlx5_modification_field id;
148 struct field_modify_info modify_eth[] = {
149 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
150 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
151 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
152 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
156 struct field_modify_info modify_vlan_out_first_vid[] = {
157 /* Size in bits !!! */
158 {12, 0, MLX5_MODI_OUT_FIRST_VID},
162 struct field_modify_info modify_ipv4[] = {
163 {1, 1, MLX5_MODI_OUT_IP_DSCP},
164 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
165 {4, 12, MLX5_MODI_OUT_SIPV4},
166 {4, 16, MLX5_MODI_OUT_DIPV4},
170 struct field_modify_info modify_ipv6[] = {
171 {1, 0, MLX5_MODI_OUT_IP_DSCP},
172 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
173 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
174 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
175 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
176 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
177 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
178 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
179 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
180 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
184 struct field_modify_info modify_udp[] = {
185 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
186 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
190 struct field_modify_info modify_tcp[] = {
191 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
192 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
193 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
194 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
199 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
200 uint8_t next_protocol, uint64_t *item_flags,
203 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
204 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
205 if (next_protocol == IPPROTO_IPIP) {
206 *item_flags |= MLX5_FLOW_LAYER_IPIP;
209 if (next_protocol == IPPROTO_IPV6) {
210 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
216 * Acquire the synchronizing object to protect multithreaded access
217 * to shared dv context. Lock occurs only if context is actually
218 * shared, i.e. we have multiport IB device and representors are
222 * Pointer to the rte_eth_dev structure.
225 flow_dv_shared_lock(struct rte_eth_dev *dev)
227 struct mlx5_priv *priv = dev->data->dev_private;
228 struct mlx5_ibv_shared *sh = priv->sh;
230 if (sh->dv_refcnt > 1) {
233 ret = pthread_mutex_lock(&sh->dv_mutex);
240 flow_dv_shared_unlock(struct rte_eth_dev *dev)
242 struct mlx5_priv *priv = dev->data->dev_private;
243 struct mlx5_ibv_shared *sh = priv->sh;
245 if (sh->dv_refcnt > 1) {
248 ret = pthread_mutex_unlock(&sh->dv_mutex);
254 /* Update VLAN's VID/PCP based on input rte_flow_action.
257 * Pointer to struct rte_flow_action.
259 * Pointer to struct rte_vlan_hdr.
262 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
263 struct rte_vlan_hdr *vlan)
266 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
268 ((const struct rte_flow_action_of_set_vlan_pcp *)
269 action->conf)->vlan_pcp;
270 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
271 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
272 vlan->vlan_tci |= vlan_tci;
273 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
274 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
275 vlan->vlan_tci |= rte_be_to_cpu_16
276 (((const struct rte_flow_action_of_set_vlan_vid *)
277 action->conf)->vlan_vid);
282 * Fetch 1, 2, 3 or 4 byte field from the byte array
283 * and return as unsigned integer in host-endian format.
286 * Pointer to data array.
288 * Size of field to extract.
291 * converted field in host endian format.
293 static inline uint32_t
294 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
303 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
306 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
307 ret = (ret << 8) | *(data + sizeof(uint16_t));
310 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
321 * Convert modify-header action to DV specification.
323 * Data length of each action is determined by provided field description
324 * and the item mask. Data bit offset and width of each action is determined
325 * by provided item mask.
328 * Pointer to item specification.
330 * Pointer to field modification information.
331 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
332 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
333 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
335 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
336 * Negative offset value sets the same offset as source offset.
337 * size field is ignored, value is taken from source field.
338 * @param[in,out] resource
339 * Pointer to the modify-header resource.
341 * Type of modification.
343 * Pointer to the error structure.
346 * 0 on success, a negative errno value otherwise and rte_errno is set.
349 flow_dv_convert_modify_action(struct rte_flow_item *item,
350 struct field_modify_info *field,
351 struct field_modify_info *dcopy,
352 struct mlx5_flow_dv_modify_hdr_resource *resource,
353 uint32_t type, struct rte_flow_error *error)
355 uint32_t i = resource->actions_num;
356 struct mlx5_modification_cmd *actions = resource->actions;
359 * The item and mask are provided in big-endian format.
360 * The fields should be presented as in big-endian format either.
361 * Mask must be always present, it defines the actual field width.
363 MLX5_ASSERT(item->mask);
364 MLX5_ASSERT(field->size);
371 if (i >= MLX5_MAX_MODIFY_NUM)
372 return rte_flow_error_set(error, EINVAL,
373 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
374 "too many items to modify");
375 /* Fetch variable byte size mask from the array. */
376 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
377 field->offset, field->size);
382 /* Deduce actual data width in bits from mask value. */
383 off_b = rte_bsf32(mask);
384 size_b = sizeof(uint32_t) * CHAR_BIT -
385 off_b - __builtin_clz(mask);
387 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
388 actions[i].action_type = type;
389 actions[i].field = field->id;
390 actions[i].offset = off_b;
391 actions[i].length = size_b;
392 /* Convert entire record to expected big-endian format. */
393 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
394 if (type == MLX5_MODIFICATION_TYPE_COPY) {
396 actions[i].dst_field = dcopy->id;
397 actions[i].dst_offset =
398 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
399 /* Convert entire record to big-endian format. */
400 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
402 MLX5_ASSERT(item->spec);
403 data = flow_dv_fetch_field((const uint8_t *)item->spec +
404 field->offset, field->size);
405 /* Shift out the trailing masked bits from data. */
406 data = (data & mask) >> off_b;
407 actions[i].data1 = rte_cpu_to_be_32(data);
411 } while (field->size);
412 if (resource->actions_num == i)
413 return rte_flow_error_set(error, EINVAL,
414 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
415 "invalid modification flow item");
416 resource->actions_num = i;
421 * Convert modify-header set IPv4 address action to DV specification.
423 * @param[in,out] resource
424 * Pointer to the modify-header resource.
426 * Pointer to action specification.
428 * Pointer to the error structure.
431 * 0 on success, a negative errno value otherwise and rte_errno is set.
434 flow_dv_convert_action_modify_ipv4
435 (struct mlx5_flow_dv_modify_hdr_resource *resource,
436 const struct rte_flow_action *action,
437 struct rte_flow_error *error)
439 const struct rte_flow_action_set_ipv4 *conf =
440 (const struct rte_flow_action_set_ipv4 *)(action->conf);
441 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
442 struct rte_flow_item_ipv4 ipv4;
443 struct rte_flow_item_ipv4 ipv4_mask;
445 memset(&ipv4, 0, sizeof(ipv4));
446 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
447 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
448 ipv4.hdr.src_addr = conf->ipv4_addr;
449 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
451 ipv4.hdr.dst_addr = conf->ipv4_addr;
452 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
455 item.mask = &ipv4_mask;
456 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
457 MLX5_MODIFICATION_TYPE_SET, error);
461 * Convert modify-header set IPv6 address action to DV specification.
463 * @param[in,out] resource
464 * Pointer to the modify-header resource.
466 * Pointer to action specification.
468 * Pointer to the error structure.
471 * 0 on success, a negative errno value otherwise and rte_errno is set.
474 flow_dv_convert_action_modify_ipv6
475 (struct mlx5_flow_dv_modify_hdr_resource *resource,
476 const struct rte_flow_action *action,
477 struct rte_flow_error *error)
479 const struct rte_flow_action_set_ipv6 *conf =
480 (const struct rte_flow_action_set_ipv6 *)(action->conf);
481 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
482 struct rte_flow_item_ipv6 ipv6;
483 struct rte_flow_item_ipv6 ipv6_mask;
485 memset(&ipv6, 0, sizeof(ipv6));
486 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
487 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
488 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
489 sizeof(ipv6.hdr.src_addr));
490 memcpy(&ipv6_mask.hdr.src_addr,
491 &rte_flow_item_ipv6_mask.hdr.src_addr,
492 sizeof(ipv6.hdr.src_addr));
494 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
495 sizeof(ipv6.hdr.dst_addr));
496 memcpy(&ipv6_mask.hdr.dst_addr,
497 &rte_flow_item_ipv6_mask.hdr.dst_addr,
498 sizeof(ipv6.hdr.dst_addr));
501 item.mask = &ipv6_mask;
502 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
503 MLX5_MODIFICATION_TYPE_SET, error);
507 * Convert modify-header set MAC address action to DV specification.
509 * @param[in,out] resource
510 * Pointer to the modify-header resource.
512 * Pointer to action specification.
514 * Pointer to the error structure.
517 * 0 on success, a negative errno value otherwise and rte_errno is set.
520 flow_dv_convert_action_modify_mac
521 (struct mlx5_flow_dv_modify_hdr_resource *resource,
522 const struct rte_flow_action *action,
523 struct rte_flow_error *error)
525 const struct rte_flow_action_set_mac *conf =
526 (const struct rte_flow_action_set_mac *)(action->conf);
527 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
528 struct rte_flow_item_eth eth;
529 struct rte_flow_item_eth eth_mask;
531 memset(ð, 0, sizeof(eth));
532 memset(ð_mask, 0, sizeof(eth_mask));
533 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
534 memcpy(ð.src.addr_bytes, &conf->mac_addr,
535 sizeof(eth.src.addr_bytes));
536 memcpy(ð_mask.src.addr_bytes,
537 &rte_flow_item_eth_mask.src.addr_bytes,
538 sizeof(eth_mask.src.addr_bytes));
540 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
541 sizeof(eth.dst.addr_bytes));
542 memcpy(ð_mask.dst.addr_bytes,
543 &rte_flow_item_eth_mask.dst.addr_bytes,
544 sizeof(eth_mask.dst.addr_bytes));
547 item.mask = ð_mask;
548 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
549 MLX5_MODIFICATION_TYPE_SET, error);
553 * Convert modify-header set VLAN VID action to DV specification.
555 * @param[in,out] resource
556 * Pointer to the modify-header resource.
558 * Pointer to action specification.
560 * Pointer to the error structure.
563 * 0 on success, a negative errno value otherwise and rte_errno is set.
566 flow_dv_convert_action_modify_vlan_vid
567 (struct mlx5_flow_dv_modify_hdr_resource *resource,
568 const struct rte_flow_action *action,
569 struct rte_flow_error *error)
571 const struct rte_flow_action_of_set_vlan_vid *conf =
572 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
573 int i = resource->actions_num;
574 struct mlx5_modification_cmd *actions = &resource->actions[i];
575 struct field_modify_info *field = modify_vlan_out_first_vid;
577 if (i >= MLX5_MAX_MODIFY_NUM)
578 return rte_flow_error_set(error, EINVAL,
579 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
580 "too many items to modify");
581 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
582 actions[i].field = field->id;
583 actions[i].length = field->size;
584 actions[i].offset = field->offset;
585 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
586 actions[i].data1 = conf->vlan_vid;
587 actions[i].data1 = actions[i].data1 << 16;
588 resource->actions_num = ++i;
593 * Convert modify-header set TP action to DV specification.
595 * @param[in,out] resource
596 * Pointer to the modify-header resource.
598 * Pointer to action specification.
600 * Pointer to rte_flow_item objects list.
602 * Pointer to flow attributes structure.
604 * Pointer to the error structure.
607 * 0 on success, a negative errno value otherwise and rte_errno is set.
610 flow_dv_convert_action_modify_tp
611 (struct mlx5_flow_dv_modify_hdr_resource *resource,
612 const struct rte_flow_action *action,
613 const struct rte_flow_item *items,
614 union flow_dv_attr *attr,
615 struct rte_flow_error *error)
617 const struct rte_flow_action_set_tp *conf =
618 (const struct rte_flow_action_set_tp *)(action->conf);
619 struct rte_flow_item item;
620 struct rte_flow_item_udp udp;
621 struct rte_flow_item_udp udp_mask;
622 struct rte_flow_item_tcp tcp;
623 struct rte_flow_item_tcp tcp_mask;
624 struct field_modify_info *field;
627 flow_dv_attr_init(items, attr);
629 memset(&udp, 0, sizeof(udp));
630 memset(&udp_mask, 0, sizeof(udp_mask));
631 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
632 udp.hdr.src_port = conf->port;
633 udp_mask.hdr.src_port =
634 rte_flow_item_udp_mask.hdr.src_port;
636 udp.hdr.dst_port = conf->port;
637 udp_mask.hdr.dst_port =
638 rte_flow_item_udp_mask.hdr.dst_port;
640 item.type = RTE_FLOW_ITEM_TYPE_UDP;
642 item.mask = &udp_mask;
646 memset(&tcp, 0, sizeof(tcp));
647 memset(&tcp_mask, 0, sizeof(tcp_mask));
648 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
649 tcp.hdr.src_port = conf->port;
650 tcp_mask.hdr.src_port =
651 rte_flow_item_tcp_mask.hdr.src_port;
653 tcp.hdr.dst_port = conf->port;
654 tcp_mask.hdr.dst_port =
655 rte_flow_item_tcp_mask.hdr.dst_port;
657 item.type = RTE_FLOW_ITEM_TYPE_TCP;
659 item.mask = &tcp_mask;
662 return flow_dv_convert_modify_action(&item, field, NULL, resource,
663 MLX5_MODIFICATION_TYPE_SET, error);
667 * Convert modify-header set TTL action to DV specification.
669 * @param[in,out] resource
670 * Pointer to the modify-header resource.
672 * Pointer to action specification.
674 * Pointer to rte_flow_item objects list.
676 * Pointer to flow attributes structure.
678 * Pointer to the error structure.
681 * 0 on success, a negative errno value otherwise and rte_errno is set.
684 flow_dv_convert_action_modify_ttl
685 (struct mlx5_flow_dv_modify_hdr_resource *resource,
686 const struct rte_flow_action *action,
687 const struct rte_flow_item *items,
688 union flow_dv_attr *attr,
689 struct rte_flow_error *error)
691 const struct rte_flow_action_set_ttl *conf =
692 (const struct rte_flow_action_set_ttl *)(action->conf);
693 struct rte_flow_item item;
694 struct rte_flow_item_ipv4 ipv4;
695 struct rte_flow_item_ipv4 ipv4_mask;
696 struct rte_flow_item_ipv6 ipv6;
697 struct rte_flow_item_ipv6 ipv6_mask;
698 struct field_modify_info *field;
701 flow_dv_attr_init(items, attr);
703 memset(&ipv4, 0, sizeof(ipv4));
704 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
705 ipv4.hdr.time_to_live = conf->ttl_value;
706 ipv4_mask.hdr.time_to_live = 0xFF;
707 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
709 item.mask = &ipv4_mask;
713 memset(&ipv6, 0, sizeof(ipv6));
714 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
715 ipv6.hdr.hop_limits = conf->ttl_value;
716 ipv6_mask.hdr.hop_limits = 0xFF;
717 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
719 item.mask = &ipv6_mask;
722 return flow_dv_convert_modify_action(&item, field, NULL, resource,
723 MLX5_MODIFICATION_TYPE_SET, error);
727 * Convert modify-header decrement TTL action to DV specification.
729 * @param[in,out] resource
730 * Pointer to the modify-header resource.
732 * Pointer to action specification.
734 * Pointer to rte_flow_item objects list.
736 * Pointer to flow attributes structure.
738 * Pointer to the error structure.
741 * 0 on success, a negative errno value otherwise and rte_errno is set.
744 flow_dv_convert_action_modify_dec_ttl
745 (struct mlx5_flow_dv_modify_hdr_resource *resource,
746 const struct rte_flow_item *items,
747 union flow_dv_attr *attr,
748 struct rte_flow_error *error)
750 struct rte_flow_item item;
751 struct rte_flow_item_ipv4 ipv4;
752 struct rte_flow_item_ipv4 ipv4_mask;
753 struct rte_flow_item_ipv6 ipv6;
754 struct rte_flow_item_ipv6 ipv6_mask;
755 struct field_modify_info *field;
758 flow_dv_attr_init(items, attr);
760 memset(&ipv4, 0, sizeof(ipv4));
761 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
762 ipv4.hdr.time_to_live = 0xFF;
763 ipv4_mask.hdr.time_to_live = 0xFF;
764 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
766 item.mask = &ipv4_mask;
770 memset(&ipv6, 0, sizeof(ipv6));
771 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
772 ipv6.hdr.hop_limits = 0xFF;
773 ipv6_mask.hdr.hop_limits = 0xFF;
774 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
776 item.mask = &ipv6_mask;
779 return flow_dv_convert_modify_action(&item, field, NULL, resource,
780 MLX5_MODIFICATION_TYPE_ADD, error);
784 * Convert modify-header increment/decrement TCP Sequence number
785 * to DV specification.
787 * @param[in,out] resource
788 * Pointer to the modify-header resource.
790 * Pointer to action specification.
792 * Pointer to the error structure.
795 * 0 on success, a negative errno value otherwise and rte_errno is set.
798 flow_dv_convert_action_modify_tcp_seq
799 (struct mlx5_flow_dv_modify_hdr_resource *resource,
800 const struct rte_flow_action *action,
801 struct rte_flow_error *error)
803 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
804 uint64_t value = rte_be_to_cpu_32(*conf);
805 struct rte_flow_item item;
806 struct rte_flow_item_tcp tcp;
807 struct rte_flow_item_tcp tcp_mask;
809 memset(&tcp, 0, sizeof(tcp));
810 memset(&tcp_mask, 0, sizeof(tcp_mask));
811 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
813 * The HW has no decrement operation, only increment operation.
814 * To simulate decrement X from Y using increment operation
815 * we need to add UINT32_MAX X times to Y.
816 * Each adding of UINT32_MAX decrements Y by 1.
819 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
820 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
821 item.type = RTE_FLOW_ITEM_TYPE_TCP;
823 item.mask = &tcp_mask;
824 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
825 MLX5_MODIFICATION_TYPE_ADD, error);
829 * Convert modify-header increment/decrement TCP Acknowledgment number
830 * to DV specification.
832 * @param[in,out] resource
833 * Pointer to the modify-header resource.
835 * Pointer to action specification.
837 * Pointer to the error structure.
840 * 0 on success, a negative errno value otherwise and rte_errno is set.
843 flow_dv_convert_action_modify_tcp_ack
844 (struct mlx5_flow_dv_modify_hdr_resource *resource,
845 const struct rte_flow_action *action,
846 struct rte_flow_error *error)
848 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
849 uint64_t value = rte_be_to_cpu_32(*conf);
850 struct rte_flow_item item;
851 struct rte_flow_item_tcp tcp;
852 struct rte_flow_item_tcp tcp_mask;
854 memset(&tcp, 0, sizeof(tcp));
855 memset(&tcp_mask, 0, sizeof(tcp_mask));
856 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
858 * The HW has no decrement operation, only increment operation.
859 * To simulate decrement X from Y using increment operation
860 * we need to add UINT32_MAX X times to Y.
861 * Each adding of UINT32_MAX decrements Y by 1.
864 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
865 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
866 item.type = RTE_FLOW_ITEM_TYPE_TCP;
868 item.mask = &tcp_mask;
869 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
870 MLX5_MODIFICATION_TYPE_ADD, error);
873 static enum mlx5_modification_field reg_to_field[] = {
874 [REG_NONE] = MLX5_MODI_OUT_NONE,
875 [REG_A] = MLX5_MODI_META_DATA_REG_A,
876 [REG_B] = MLX5_MODI_META_DATA_REG_B,
877 [REG_C_0] = MLX5_MODI_META_REG_C_0,
878 [REG_C_1] = MLX5_MODI_META_REG_C_1,
879 [REG_C_2] = MLX5_MODI_META_REG_C_2,
880 [REG_C_3] = MLX5_MODI_META_REG_C_3,
881 [REG_C_4] = MLX5_MODI_META_REG_C_4,
882 [REG_C_5] = MLX5_MODI_META_REG_C_5,
883 [REG_C_6] = MLX5_MODI_META_REG_C_6,
884 [REG_C_7] = MLX5_MODI_META_REG_C_7,
888 * Convert register set to DV specification.
890 * @param[in,out] resource
891 * Pointer to the modify-header resource.
893 * Pointer to action specification.
895 * Pointer to the error structure.
898 * 0 on success, a negative errno value otherwise and rte_errno is set.
901 flow_dv_convert_action_set_reg
902 (struct mlx5_flow_dv_modify_hdr_resource *resource,
903 const struct rte_flow_action *action,
904 struct rte_flow_error *error)
906 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
907 struct mlx5_modification_cmd *actions = resource->actions;
908 uint32_t i = resource->actions_num;
910 if (i >= MLX5_MAX_MODIFY_NUM)
911 return rte_flow_error_set(error, EINVAL,
912 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
913 "too many items to modify");
914 MLX5_ASSERT(conf->id != REG_NONE);
915 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
916 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
917 actions[i].field = reg_to_field[conf->id];
918 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
919 actions[i].data1 = rte_cpu_to_be_32(conf->data);
921 resource->actions_num = i;
926 * Convert SET_TAG action to DV specification.
929 * Pointer to the rte_eth_dev structure.
930 * @param[in,out] resource
931 * Pointer to the modify-header resource.
933 * Pointer to action specification.
935 * Pointer to the error structure.
938 * 0 on success, a negative errno value otherwise and rte_errno is set.
941 flow_dv_convert_action_set_tag
942 (struct rte_eth_dev *dev,
943 struct mlx5_flow_dv_modify_hdr_resource *resource,
944 const struct rte_flow_action_set_tag *conf,
945 struct rte_flow_error *error)
947 rte_be32_t data = rte_cpu_to_be_32(conf->data);
948 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
949 struct rte_flow_item item = {
953 struct field_modify_info reg_c_x[] = {
956 enum mlx5_modification_field reg_type;
959 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
962 MLX5_ASSERT(ret != REG_NONE);
963 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
964 reg_type = reg_to_field[ret];
965 MLX5_ASSERT(reg_type > 0);
966 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
967 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
968 MLX5_MODIFICATION_TYPE_SET, error);
972 * Convert internal COPY_REG action to DV specification.
975 * Pointer to the rte_eth_dev structure.
977 * Pointer to the modify-header resource.
979 * Pointer to action specification.
981 * Pointer to the error structure.
984 * 0 on success, a negative errno value otherwise and rte_errno is set.
987 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
988 struct mlx5_flow_dv_modify_hdr_resource *res,
989 const struct rte_flow_action *action,
990 struct rte_flow_error *error)
992 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
993 rte_be32_t mask = RTE_BE32(UINT32_MAX);
994 struct rte_flow_item item = {
998 struct field_modify_info reg_src[] = {
999 {4, 0, reg_to_field[conf->src]},
1002 struct field_modify_info reg_dst = {
1004 .id = reg_to_field[conf->dst],
1006 /* Adjust reg_c[0] usage according to reported mask. */
1007 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1008 struct mlx5_priv *priv = dev->data->dev_private;
1009 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1011 MLX5_ASSERT(reg_c0);
1012 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1013 if (conf->dst == REG_C_0) {
1014 /* Copy to reg_c[0], within mask only. */
1015 reg_dst.offset = rte_bsf32(reg_c0);
1017 * Mask is ignoring the enianness, because
1018 * there is no conversion in datapath.
1020 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1021 /* Copy from destination lower bits to reg_c[0]. */
1022 mask = reg_c0 >> reg_dst.offset;
1024 /* Copy from destination upper bits to reg_c[0]. */
1025 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1026 rte_fls_u32(reg_c0));
1029 mask = rte_cpu_to_be_32(reg_c0);
1030 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1031 /* Copy from reg_c[0] to destination lower bits. */
1034 /* Copy from reg_c[0] to destination upper bits. */
1035 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1036 (rte_fls_u32(reg_c0) -
1041 return flow_dv_convert_modify_action(&item,
1042 reg_src, ®_dst, res,
1043 MLX5_MODIFICATION_TYPE_COPY,
1048 * Convert MARK action to DV specification. This routine is used
1049 * in extensive metadata only and requires metadata register to be
1050 * handled. In legacy mode hardware tag resource is engaged.
1053 * Pointer to the rte_eth_dev structure.
1055 * Pointer to MARK action specification.
1056 * @param[in,out] resource
1057 * Pointer to the modify-header resource.
1059 * Pointer to the error structure.
1062 * 0 on success, a negative errno value otherwise and rte_errno is set.
1065 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1066 const struct rte_flow_action_mark *conf,
1067 struct mlx5_flow_dv_modify_hdr_resource *resource,
1068 struct rte_flow_error *error)
1070 struct mlx5_priv *priv = dev->data->dev_private;
1071 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1072 priv->sh->dv_mark_mask);
1073 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1074 struct rte_flow_item item = {
1078 struct field_modify_info reg_c_x[] = {
1079 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1085 return rte_flow_error_set(error, EINVAL,
1086 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1087 NULL, "zero mark action mask");
1088 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1091 MLX5_ASSERT(reg > 0);
1092 if (reg == REG_C_0) {
1093 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1094 uint32_t shl_c0 = rte_bsf32(msk_c0);
1096 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1097 mask = rte_cpu_to_be_32(mask) & msk_c0;
1098 mask = rte_cpu_to_be_32(mask << shl_c0);
1100 reg_c_x[0].id = reg_to_field[reg];
1101 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1102 MLX5_MODIFICATION_TYPE_SET, error);
1106 * Get metadata register index for specified steering domain.
1109 * Pointer to the rte_eth_dev structure.
1111 * Attributes of flow to determine steering domain.
1113 * Pointer to the error structure.
1116 * positive index on success, a negative errno value otherwise
1117 * and rte_errno is set.
1119 static enum modify_reg
1120 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1121 const struct rte_flow_attr *attr,
1122 struct rte_flow_error *error)
1125 mlx5_flow_get_reg_id(dev, attr->transfer ?
1129 MLX5_METADATA_RX, 0, error);
1131 return rte_flow_error_set(error,
1132 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1133 NULL, "unavailable "
1134 "metadata register");
1139 * Convert SET_META action to DV specification.
1142 * Pointer to the rte_eth_dev structure.
1143 * @param[in,out] resource
1144 * Pointer to the modify-header resource.
1146 * Attributes of flow that includes this item.
1148 * Pointer to action specification.
1150 * Pointer to the error structure.
1153 * 0 on success, a negative errno value otherwise and rte_errno is set.
1156 flow_dv_convert_action_set_meta
1157 (struct rte_eth_dev *dev,
1158 struct mlx5_flow_dv_modify_hdr_resource *resource,
1159 const struct rte_flow_attr *attr,
1160 const struct rte_flow_action_set_meta *conf,
1161 struct rte_flow_error *error)
1163 uint32_t data = conf->data;
1164 uint32_t mask = conf->mask;
1165 struct rte_flow_item item = {
1169 struct field_modify_info reg_c_x[] = {
1172 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1177 * In datapath code there is no endianness
1178 * coversions for perfromance reasons, all
1179 * pattern conversions are done in rte_flow.
1181 if (reg == REG_C_0) {
1182 struct mlx5_priv *priv = dev->data->dev_private;
1183 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1186 MLX5_ASSERT(msk_c0);
1187 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1188 shl_c0 = rte_bsf32(msk_c0);
1190 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1194 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1196 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1197 /* The routine expects parameters in memory as big-endian ones. */
1198 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1199 MLX5_MODIFICATION_TYPE_SET, error);
1203 * Convert modify-header set IPv4 DSCP action to DV specification.
1205 * @param[in,out] resource
1206 * Pointer to the modify-header resource.
1208 * Pointer to action specification.
1210 * Pointer to the error structure.
1213 * 0 on success, a negative errno value otherwise and rte_errno is set.
1216 flow_dv_convert_action_modify_ipv4_dscp
1217 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1218 const struct rte_flow_action *action,
1219 struct rte_flow_error *error)
1221 const struct rte_flow_action_set_dscp *conf =
1222 (const struct rte_flow_action_set_dscp *)(action->conf);
1223 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1224 struct rte_flow_item_ipv4 ipv4;
1225 struct rte_flow_item_ipv4 ipv4_mask;
1227 memset(&ipv4, 0, sizeof(ipv4));
1228 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1229 ipv4.hdr.type_of_service = conf->dscp;
1230 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1232 item.mask = &ipv4_mask;
1233 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1234 MLX5_MODIFICATION_TYPE_SET, error);
1238 * Convert modify-header set IPv6 DSCP action to DV specification.
1240 * @param[in,out] resource
1241 * Pointer to the modify-header resource.
1243 * Pointer to action specification.
1245 * Pointer to the error structure.
1248 * 0 on success, a negative errno value otherwise and rte_errno is set.
1251 flow_dv_convert_action_modify_ipv6_dscp
1252 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1253 const struct rte_flow_action *action,
1254 struct rte_flow_error *error)
1256 const struct rte_flow_action_set_dscp *conf =
1257 (const struct rte_flow_action_set_dscp *)(action->conf);
1258 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1259 struct rte_flow_item_ipv6 ipv6;
1260 struct rte_flow_item_ipv6 ipv6_mask;
1262 memset(&ipv6, 0, sizeof(ipv6));
1263 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1265 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1266 * rdma-core only accept the DSCP bits byte aligned start from
1267 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1268 * bits in IPv6 case as rdma-core requires byte aligned value.
1270 ipv6.hdr.vtc_flow = conf->dscp;
1271 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1273 item.mask = &ipv6_mask;
1274 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1275 MLX5_MODIFICATION_TYPE_SET, error);
1279 * Validate MARK item.
1282 * Pointer to the rte_eth_dev structure.
1284 * Item specification.
1286 * Attributes of flow that includes this item.
1288 * Pointer to error structure.
1291 * 0 on success, a negative errno value otherwise and rte_errno is set.
1294 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1295 const struct rte_flow_item *item,
1296 const struct rte_flow_attr *attr __rte_unused,
1297 struct rte_flow_error *error)
1299 struct mlx5_priv *priv = dev->data->dev_private;
1300 struct mlx5_dev_config *config = &priv->config;
1301 const struct rte_flow_item_mark *spec = item->spec;
1302 const struct rte_flow_item_mark *mask = item->mask;
1303 const struct rte_flow_item_mark nic_mask = {
1304 .id = priv->sh->dv_mark_mask,
1308 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1309 return rte_flow_error_set(error, ENOTSUP,
1310 RTE_FLOW_ERROR_TYPE_ITEM, item,
1311 "extended metadata feature"
1313 if (!mlx5_flow_ext_mreg_supported(dev))
1314 return rte_flow_error_set(error, ENOTSUP,
1315 RTE_FLOW_ERROR_TYPE_ITEM, item,
1316 "extended metadata register"
1317 " isn't supported");
1319 return rte_flow_error_set(error, ENOTSUP,
1320 RTE_FLOW_ERROR_TYPE_ITEM, item,
1321 "extended metadata register"
1322 " isn't available");
1323 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1327 return rte_flow_error_set(error, EINVAL,
1328 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1330 "data cannot be empty");
1331 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1332 return rte_flow_error_set(error, EINVAL,
1333 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1335 "mark id exceeds the limit");
1338 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1339 (const uint8_t *)&nic_mask,
1340 sizeof(struct rte_flow_item_mark),
1348 * Validate META item.
1351 * Pointer to the rte_eth_dev structure.
1353 * Item specification.
1355 * Attributes of flow that includes this item.
1357 * Pointer to error structure.
1360 * 0 on success, a negative errno value otherwise and rte_errno is set.
1363 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1364 const struct rte_flow_item *item,
1365 const struct rte_flow_attr *attr,
1366 struct rte_flow_error *error)
1368 struct mlx5_priv *priv = dev->data->dev_private;
1369 struct mlx5_dev_config *config = &priv->config;
1370 const struct rte_flow_item_meta *spec = item->spec;
1371 const struct rte_flow_item_meta *mask = item->mask;
1372 struct rte_flow_item_meta nic_mask = {
1379 return rte_flow_error_set(error, EINVAL,
1380 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1382 "data cannot be empty");
1384 return rte_flow_error_set(error, EINVAL,
1385 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1386 "data cannot be zero");
1387 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1388 if (!mlx5_flow_ext_mreg_supported(dev))
1389 return rte_flow_error_set(error, ENOTSUP,
1390 RTE_FLOW_ERROR_TYPE_ITEM, item,
1391 "extended metadata register"
1392 " isn't supported");
1393 reg = flow_dv_get_metadata_reg(dev, attr, error);
1397 return rte_flow_error_set(error, ENOTSUP,
1398 RTE_FLOW_ERROR_TYPE_ITEM, item,
1402 nic_mask.data = priv->sh->dv_meta_mask;
1405 mask = &rte_flow_item_meta_mask;
1406 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1407 (const uint8_t *)&nic_mask,
1408 sizeof(struct rte_flow_item_meta),
1414 * Validate TAG item.
1417 * Pointer to the rte_eth_dev structure.
1419 * Item specification.
1421 * Attributes of flow that includes this item.
1423 * Pointer to error structure.
1426 * 0 on success, a negative errno value otherwise and rte_errno is set.
1429 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1430 const struct rte_flow_item *item,
1431 const struct rte_flow_attr *attr __rte_unused,
1432 struct rte_flow_error *error)
1434 const struct rte_flow_item_tag *spec = item->spec;
1435 const struct rte_flow_item_tag *mask = item->mask;
1436 const struct rte_flow_item_tag nic_mask = {
1437 .data = RTE_BE32(UINT32_MAX),
1442 if (!mlx5_flow_ext_mreg_supported(dev))
1443 return rte_flow_error_set(error, ENOTSUP,
1444 RTE_FLOW_ERROR_TYPE_ITEM, item,
1445 "extensive metadata register"
1446 " isn't supported");
1448 return rte_flow_error_set(error, EINVAL,
1449 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1451 "data cannot be empty");
1453 mask = &rte_flow_item_tag_mask;
1454 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1455 (const uint8_t *)&nic_mask,
1456 sizeof(struct rte_flow_item_tag),
1460 if (mask->index != 0xff)
1461 return rte_flow_error_set(error, EINVAL,
1462 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1463 "partial mask for tag index"
1464 " is not supported");
1465 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1468 MLX5_ASSERT(ret != REG_NONE);
1473 * Validate vport item.
1476 * Pointer to the rte_eth_dev structure.
1478 * Item specification.
1480 * Attributes of flow that includes this item.
1481 * @param[in] item_flags
1482 * Bit-fields that holds the items detected until now.
1484 * Pointer to error structure.
1487 * 0 on success, a negative errno value otherwise and rte_errno is set.
1490 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1491 const struct rte_flow_item *item,
1492 const struct rte_flow_attr *attr,
1493 uint64_t item_flags,
1494 struct rte_flow_error *error)
1496 const struct rte_flow_item_port_id *spec = item->spec;
1497 const struct rte_flow_item_port_id *mask = item->mask;
1498 const struct rte_flow_item_port_id switch_mask = {
1501 struct mlx5_priv *esw_priv;
1502 struct mlx5_priv *dev_priv;
1505 if (!attr->transfer)
1506 return rte_flow_error_set(error, EINVAL,
1507 RTE_FLOW_ERROR_TYPE_ITEM,
1509 "match on port id is valid only"
1510 " when transfer flag is enabled");
1511 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1512 return rte_flow_error_set(error, ENOTSUP,
1513 RTE_FLOW_ERROR_TYPE_ITEM, item,
1514 "multiple source ports are not"
1517 mask = &switch_mask;
1518 if (mask->id != 0xffffffff)
1519 return rte_flow_error_set(error, ENOTSUP,
1520 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1522 "no support for partial mask on"
1524 ret = mlx5_flow_item_acceptable
1525 (item, (const uint8_t *)mask,
1526 (const uint8_t *)&rte_flow_item_port_id_mask,
1527 sizeof(struct rte_flow_item_port_id),
1533 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1535 return rte_flow_error_set(error, rte_errno,
1536 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1537 "failed to obtain E-Switch info for"
1539 dev_priv = mlx5_dev_to_eswitch_info(dev);
1541 return rte_flow_error_set(error, rte_errno,
1542 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1544 "failed to obtain E-Switch info");
1545 if (esw_priv->domain_id != dev_priv->domain_id)
1546 return rte_flow_error_set(error, EINVAL,
1547 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1548 "cannot match on a port from a"
1549 " different E-Switch");
1554 * Validate GTP item.
1557 * Pointer to the rte_eth_dev structure.
1559 * Item specification.
1560 * @param[in] item_flags
1561 * Bit-fields that holds the items detected until now.
1563 * Pointer to error structure.
1566 * 0 on success, a negative errno value otherwise and rte_errno is set.
1569 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1570 const struct rte_flow_item *item,
1571 uint64_t item_flags,
1572 struct rte_flow_error *error)
1574 struct mlx5_priv *priv = dev->data->dev_private;
1575 const struct rte_flow_item_gtp *mask = item->mask;
1576 const struct rte_flow_item_gtp nic_mask = {
1578 .teid = RTE_BE32(0xffffffff),
1581 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1582 return rte_flow_error_set(error, ENOTSUP,
1583 RTE_FLOW_ERROR_TYPE_ITEM, item,
1584 "GTP support is not enabled");
1585 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1586 return rte_flow_error_set(error, ENOTSUP,
1587 RTE_FLOW_ERROR_TYPE_ITEM, item,
1588 "multiple tunnel layers not"
1590 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1591 return rte_flow_error_set(error, EINVAL,
1592 RTE_FLOW_ERROR_TYPE_ITEM, item,
1593 "no outer UDP layer found");
1595 mask = &rte_flow_item_gtp_mask;
1596 return mlx5_flow_item_acceptable
1597 (item, (const uint8_t *)mask,
1598 (const uint8_t *)&nic_mask,
1599 sizeof(struct rte_flow_item_gtp),
1604 * Validate the pop VLAN action.
1607 * Pointer to the rte_eth_dev structure.
1608 * @param[in] action_flags
1609 * Holds the actions detected until now.
1611 * Pointer to the pop vlan action.
1612 * @param[in] item_flags
1613 * The items found in this flow rule.
1615 * Pointer to flow attributes.
1617 * Pointer to error structure.
1620 * 0 on success, a negative errno value otherwise and rte_errno is set.
1623 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1624 uint64_t action_flags,
1625 const struct rte_flow_action *action,
1626 uint64_t item_flags,
1627 const struct rte_flow_attr *attr,
1628 struct rte_flow_error *error)
1630 struct mlx5_priv *priv = dev->data->dev_private;
1634 if (!priv->sh->pop_vlan_action)
1635 return rte_flow_error_set(error, ENOTSUP,
1636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1638 "pop vlan action is not supported");
1640 return rte_flow_error_set(error, ENOTSUP,
1641 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1643 "pop vlan action not supported for "
1645 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1646 return rte_flow_error_set(error, ENOTSUP,
1647 RTE_FLOW_ERROR_TYPE_ACTION, action,
1648 "no support for multiple VLAN "
1650 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1651 return rte_flow_error_set(error, ENOTSUP,
1652 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1654 "cannot pop vlan without a "
1655 "match on (outer) vlan in the flow");
1656 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1657 return rte_flow_error_set(error, EINVAL,
1658 RTE_FLOW_ERROR_TYPE_ACTION, action,
1659 "wrong action order, port_id should "
1660 "be after pop VLAN action");
1665 * Get VLAN default info from vlan match info.
1668 * the list of item specifications.
1670 * pointer VLAN info to fill to.
1673 * 0 on success, a negative errno value otherwise and rte_errno is set.
1676 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1677 struct rte_vlan_hdr *vlan)
1679 const struct rte_flow_item_vlan nic_mask = {
1680 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1681 MLX5DV_FLOW_VLAN_VID_MASK),
1682 .inner_type = RTE_BE16(0xffff),
1687 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1688 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1690 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1691 const struct rte_flow_item_vlan *vlan_m = items->mask;
1692 const struct rte_flow_item_vlan *vlan_v = items->spec;
1696 /* Only full match values are accepted */
1697 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1698 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1699 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1701 rte_be_to_cpu_16(vlan_v->tci &
1702 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1704 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1705 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1706 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1708 rte_be_to_cpu_16(vlan_v->tci &
1709 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1711 if (vlan_m->inner_type == nic_mask.inner_type)
1712 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1713 vlan_m->inner_type);
1718 * Validate the push VLAN action.
1720 * @param[in] action_flags
1721 * Holds the actions detected until now.
1722 * @param[in] item_flags
1723 * The items found in this flow rule.
1725 * Pointer to the action structure.
1727 * Pointer to flow attributes
1729 * Pointer to error structure.
1732 * 0 on success, a negative errno value otherwise and rte_errno is set.
1735 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1736 uint64_t item_flags __rte_unused,
1737 const struct rte_flow_action *action,
1738 const struct rte_flow_attr *attr,
1739 struct rte_flow_error *error)
1741 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1744 return rte_flow_error_set(error, ENOTSUP,
1745 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1747 "push VLAN action not supported for "
1749 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1750 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1751 return rte_flow_error_set(error, EINVAL,
1752 RTE_FLOW_ERROR_TYPE_ACTION, action,
1753 "invalid vlan ethertype");
1754 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1755 return rte_flow_error_set(error, ENOTSUP,
1756 RTE_FLOW_ERROR_TYPE_ACTION, action,
1757 "no support for multiple VLAN "
1759 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1760 return rte_flow_error_set(error, EINVAL,
1761 RTE_FLOW_ERROR_TYPE_ACTION, action,
1762 "wrong action order, port_id should "
1763 "be after push VLAN");
1769 * Validate the set VLAN PCP.
1771 * @param[in] action_flags
1772 * Holds the actions detected until now.
1773 * @param[in] actions
1774 * Pointer to the list of actions remaining in the flow rule.
1776 * Pointer to error structure.
1779 * 0 on success, a negative errno value otherwise and rte_errno is set.
1782 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1783 const struct rte_flow_action actions[],
1784 struct rte_flow_error *error)
1786 const struct rte_flow_action *action = actions;
1787 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1789 if (conf->vlan_pcp > 7)
1790 return rte_flow_error_set(error, EINVAL,
1791 RTE_FLOW_ERROR_TYPE_ACTION, action,
1792 "VLAN PCP value is too big");
1793 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1794 return rte_flow_error_set(error, ENOTSUP,
1795 RTE_FLOW_ERROR_TYPE_ACTION, action,
1796 "set VLAN PCP action must follow "
1797 "the push VLAN action");
1798 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1799 return rte_flow_error_set(error, ENOTSUP,
1800 RTE_FLOW_ERROR_TYPE_ACTION, action,
1801 "Multiple VLAN PCP modification are "
1803 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1804 return rte_flow_error_set(error, EINVAL,
1805 RTE_FLOW_ERROR_TYPE_ACTION, action,
1806 "wrong action order, port_id should "
1807 "be after set VLAN PCP");
1812 * Validate the set VLAN VID.
1814 * @param[in] item_flags
1815 * Holds the items detected in this rule.
1816 * @param[in] action_flags
1817 * Holds the actions detected until now.
1818 * @param[in] actions
1819 * Pointer to the list of actions remaining in the flow rule.
1821 * Pointer to error structure.
1824 * 0 on success, a negative errno value otherwise and rte_errno is set.
1827 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1828 uint64_t action_flags,
1829 const struct rte_flow_action actions[],
1830 struct rte_flow_error *error)
1832 const struct rte_flow_action *action = actions;
1833 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1835 if (conf->vlan_vid > RTE_BE16(0xFFE))
1836 return rte_flow_error_set(error, EINVAL,
1837 RTE_FLOW_ERROR_TYPE_ACTION, action,
1838 "VLAN VID value is too big");
1839 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1840 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1841 return rte_flow_error_set(error, ENOTSUP,
1842 RTE_FLOW_ERROR_TYPE_ACTION, action,
1843 "set VLAN VID action must follow push"
1844 " VLAN action or match on VLAN item");
1845 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1846 return rte_flow_error_set(error, ENOTSUP,
1847 RTE_FLOW_ERROR_TYPE_ACTION, action,
1848 "Multiple VLAN VID modifications are "
1850 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1851 return rte_flow_error_set(error, EINVAL,
1852 RTE_FLOW_ERROR_TYPE_ACTION, action,
1853 "wrong action order, port_id should "
1854 "be after set VLAN VID");
1859 * Validate the FLAG action.
1862 * Pointer to the rte_eth_dev structure.
1863 * @param[in] action_flags
1864 * Holds the actions detected until now.
1866 * Pointer to flow attributes
1868 * Pointer to error structure.
1871 * 0 on success, a negative errno value otherwise and rte_errno is set.
1874 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1875 uint64_t action_flags,
1876 const struct rte_flow_attr *attr,
1877 struct rte_flow_error *error)
1879 struct mlx5_priv *priv = dev->data->dev_private;
1880 struct mlx5_dev_config *config = &priv->config;
1883 /* Fall back if no extended metadata register support. */
1884 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1885 return mlx5_flow_validate_action_flag(action_flags, attr,
1887 /* Extensive metadata mode requires registers. */
1888 if (!mlx5_flow_ext_mreg_supported(dev))
1889 return rte_flow_error_set(error, ENOTSUP,
1890 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1891 "no metadata registers "
1892 "to support flag action");
1893 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1894 return rte_flow_error_set(error, ENOTSUP,
1895 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1896 "extended metadata register"
1897 " isn't available");
1898 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1901 MLX5_ASSERT(ret > 0);
1902 if (action_flags & MLX5_FLOW_ACTION_MARK)
1903 return rte_flow_error_set(error, EINVAL,
1904 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1905 "can't mark and flag in same flow");
1906 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1907 return rte_flow_error_set(error, EINVAL,
1908 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1910 " actions in same flow");
1915 * Validate MARK action.
1918 * Pointer to the rte_eth_dev structure.
1920 * Pointer to action.
1921 * @param[in] action_flags
1922 * Holds the actions detected until now.
1924 * Pointer to flow attributes
1926 * Pointer to error structure.
1929 * 0 on success, a negative errno value otherwise and rte_errno is set.
1932 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1933 const struct rte_flow_action *action,
1934 uint64_t action_flags,
1935 const struct rte_flow_attr *attr,
1936 struct rte_flow_error *error)
1938 struct mlx5_priv *priv = dev->data->dev_private;
1939 struct mlx5_dev_config *config = &priv->config;
1940 const struct rte_flow_action_mark *mark = action->conf;
1943 /* Fall back if no extended metadata register support. */
1944 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1945 return mlx5_flow_validate_action_mark(action, action_flags,
1947 /* Extensive metadata mode requires registers. */
1948 if (!mlx5_flow_ext_mreg_supported(dev))
1949 return rte_flow_error_set(error, ENOTSUP,
1950 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1951 "no metadata registers "
1952 "to support mark action");
1953 if (!priv->sh->dv_mark_mask)
1954 return rte_flow_error_set(error, ENOTSUP,
1955 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1956 "extended metadata register"
1957 " isn't available");
1958 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1961 MLX5_ASSERT(ret > 0);
1963 return rte_flow_error_set(error, EINVAL,
1964 RTE_FLOW_ERROR_TYPE_ACTION, action,
1965 "configuration cannot be null");
1966 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1967 return rte_flow_error_set(error, EINVAL,
1968 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1970 "mark id exceeds the limit");
1971 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1972 return rte_flow_error_set(error, EINVAL,
1973 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1974 "can't flag and mark in same flow");
1975 if (action_flags & MLX5_FLOW_ACTION_MARK)
1976 return rte_flow_error_set(error, EINVAL,
1977 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1978 "can't have 2 mark actions in same"
1984 * Validate SET_META action.
1987 * Pointer to the rte_eth_dev structure.
1989 * Pointer to the action structure.
1990 * @param[in] action_flags
1991 * Holds the actions detected until now.
1993 * Pointer to flow attributes
1995 * Pointer to error structure.
1998 * 0 on success, a negative errno value otherwise and rte_errno is set.
2001 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2002 const struct rte_flow_action *action,
2003 uint64_t action_flags __rte_unused,
2004 const struct rte_flow_attr *attr,
2005 struct rte_flow_error *error)
2007 const struct rte_flow_action_set_meta *conf;
2008 uint32_t nic_mask = UINT32_MAX;
2011 if (!mlx5_flow_ext_mreg_supported(dev))
2012 return rte_flow_error_set(error, ENOTSUP,
2013 RTE_FLOW_ERROR_TYPE_ACTION, action,
2014 "extended metadata register"
2015 " isn't supported");
2016 reg = flow_dv_get_metadata_reg(dev, attr, error);
2019 if (reg != REG_A && reg != REG_B) {
2020 struct mlx5_priv *priv = dev->data->dev_private;
2022 nic_mask = priv->sh->dv_meta_mask;
2024 if (!(action->conf))
2025 return rte_flow_error_set(error, EINVAL,
2026 RTE_FLOW_ERROR_TYPE_ACTION, action,
2027 "configuration cannot be null");
2028 conf = (const struct rte_flow_action_set_meta *)action->conf;
2030 return rte_flow_error_set(error, EINVAL,
2031 RTE_FLOW_ERROR_TYPE_ACTION, action,
2032 "zero mask doesn't have any effect");
2033 if (conf->mask & ~nic_mask)
2034 return rte_flow_error_set(error, EINVAL,
2035 RTE_FLOW_ERROR_TYPE_ACTION, action,
2036 "meta data must be within reg C0");
2037 if (!(conf->data & conf->mask))
2038 return rte_flow_error_set(error, EINVAL,
2039 RTE_FLOW_ERROR_TYPE_ACTION, action,
2040 "zero value has no effect");
2045 * Validate SET_TAG action.
2048 * Pointer to the rte_eth_dev structure.
2050 * Pointer to the action structure.
2051 * @param[in] action_flags
2052 * Holds the actions detected until now.
2054 * Pointer to flow attributes
2056 * Pointer to error structure.
2059 * 0 on success, a negative errno value otherwise and rte_errno is set.
2062 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2063 const struct rte_flow_action *action,
2064 uint64_t action_flags,
2065 const struct rte_flow_attr *attr,
2066 struct rte_flow_error *error)
2068 const struct rte_flow_action_set_tag *conf;
2069 const uint64_t terminal_action_flags =
2070 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2071 MLX5_FLOW_ACTION_RSS;
2074 if (!mlx5_flow_ext_mreg_supported(dev))
2075 return rte_flow_error_set(error, ENOTSUP,
2076 RTE_FLOW_ERROR_TYPE_ACTION, action,
2077 "extensive metadata register"
2078 " isn't supported");
2079 if (!(action->conf))
2080 return rte_flow_error_set(error, EINVAL,
2081 RTE_FLOW_ERROR_TYPE_ACTION, action,
2082 "configuration cannot be null");
2083 conf = (const struct rte_flow_action_set_tag *)action->conf;
2085 return rte_flow_error_set(error, EINVAL,
2086 RTE_FLOW_ERROR_TYPE_ACTION, action,
2087 "zero mask doesn't have any effect");
2088 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2091 if (!attr->transfer && attr->ingress &&
2092 (action_flags & terminal_action_flags))
2093 return rte_flow_error_set(error, EINVAL,
2094 RTE_FLOW_ERROR_TYPE_ACTION, action,
2095 "set_tag has no effect"
2096 " with terminal actions");
2101 * Validate count action.
2104 * Pointer to rte_eth_dev structure.
2106 * Pointer to error structure.
2109 * 0 on success, a negative errno value otherwise and rte_errno is set.
2112 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2113 struct rte_flow_error *error)
2115 struct mlx5_priv *priv = dev->data->dev_private;
2117 if (!priv->config.devx)
2119 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2123 return rte_flow_error_set
2125 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2127 "count action not supported");
2131 * Validate the L2 encap action.
2133 * @param[in] action_flags
2134 * Holds the actions detected until now.
2136 * Pointer to the action structure.
2138 * Pointer to flow attributes
2140 * Pointer to error structure.
2143 * 0 on success, a negative errno value otherwise and rte_errno is set.
2146 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2147 const struct rte_flow_action *action,
2148 const struct rte_flow_attr *attr,
2149 struct rte_flow_error *error)
2151 if (!(action->conf))
2152 return rte_flow_error_set(error, EINVAL,
2153 RTE_FLOW_ERROR_TYPE_ACTION, action,
2154 "configuration cannot be null");
2155 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2156 return rte_flow_error_set(error, EINVAL,
2157 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2158 "can only have a single encap or"
2159 " decap action in a flow");
2160 if (!attr->transfer && attr->ingress)
2161 return rte_flow_error_set(error, ENOTSUP,
2162 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2164 "encap action not supported for "
2170 * Validate the L2 decap action.
2172 * @param[in] action_flags
2173 * Holds the actions detected until now.
2175 * Pointer to flow attributes
2177 * Pointer to error structure.
2180 * 0 on success, a negative errno value otherwise and rte_errno is set.
2183 flow_dv_validate_action_l2_decap(uint64_t action_flags,
2184 const struct rte_flow_attr *attr,
2185 struct rte_flow_error *error)
2187 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2188 return rte_flow_error_set(error, EINVAL,
2189 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2190 "can only have a single encap or"
2191 " decap action in a flow");
2192 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2193 return rte_flow_error_set(error, EINVAL,
2194 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2195 "can't have decap action after"
2198 return rte_flow_error_set(error, ENOTSUP,
2199 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2201 "decap action not supported for "
2207 * Validate the raw encap action.
2209 * @param[in] action_flags
2210 * Holds the actions detected until now.
2212 * Pointer to the encap action.
2214 * Pointer to flow attributes
2216 * Pointer to error structure.
2219 * 0 on success, a negative errno value otherwise and rte_errno is set.
2222 flow_dv_validate_action_raw_encap(uint64_t action_flags,
2223 const struct rte_flow_action *action,
2224 const struct rte_flow_attr *attr,
2225 struct rte_flow_error *error)
2227 const struct rte_flow_action_raw_encap *raw_encap =
2228 (const struct rte_flow_action_raw_encap *)action->conf;
2229 if (!(action->conf))
2230 return rte_flow_error_set(error, EINVAL,
2231 RTE_FLOW_ERROR_TYPE_ACTION, action,
2232 "configuration cannot be null");
2233 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2234 return rte_flow_error_set(error, EINVAL,
2235 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2236 "can only have a single encap"
2237 " action in a flow");
2238 /* encap without preceding decap is not supported for ingress */
2239 if (!attr->transfer && attr->ingress &&
2240 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
2241 return rte_flow_error_set(error, ENOTSUP,
2242 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2244 "encap action not supported for "
2246 if (!raw_encap->size || !raw_encap->data)
2247 return rte_flow_error_set(error, EINVAL,
2248 RTE_FLOW_ERROR_TYPE_ACTION, action,
2249 "raw encap data cannot be empty");
2254 * Validate the raw decap action.
2256 * @param[in] action_flags
2257 * Holds the actions detected until now.
2259 * Pointer to the encap action.
2261 * Pointer to flow attributes
2263 * Pointer to error structure.
2266 * 0 on success, a negative errno value otherwise and rte_errno is set.
2269 flow_dv_validate_action_raw_decap(uint64_t action_flags,
2270 const struct rte_flow_action *action,
2271 const struct rte_flow_attr *attr,
2272 struct rte_flow_error *error)
2274 const struct rte_flow_action_raw_decap *decap = action->conf;
2276 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2277 return rte_flow_error_set(error, EINVAL,
2278 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2279 "can't have encap action before"
2281 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
2282 return rte_flow_error_set(error, EINVAL,
2283 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2284 "can only have a single decap"
2285 " action in a flow");
2286 /* decap action is valid on egress only if it is followed by encap */
2287 if (attr->egress && decap &&
2288 decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) {
2289 return rte_flow_error_set(error, ENOTSUP,
2290 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2291 NULL, "decap action not supported"
2293 } else if (decap && decap->size > MLX5_ENCAPSULATION_DECISION_SIZE &&
2294 (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)) {
2295 return rte_flow_error_set(error, EINVAL,
2296 RTE_FLOW_ERROR_TYPE_ACTION,
2298 "can't have decap action "
2299 "after modify action");
2305 * Find existing encap/decap resource or create and register a new one.
2307 * @param[in, out] dev
2308 * Pointer to rte_eth_dev structure.
2309 * @param[in, out] resource
2310 * Pointer to encap/decap resource.
2311 * @parm[in, out] dev_flow
2312 * Pointer to the dev_flow.
2314 * pointer to error structure.
2317 * 0 on success otherwise -errno and errno is set.
2320 flow_dv_encap_decap_resource_register
2321 (struct rte_eth_dev *dev,
2322 struct mlx5_flow_dv_encap_decap_resource *resource,
2323 struct mlx5_flow *dev_flow,
2324 struct rte_flow_error *error)
2326 struct mlx5_priv *priv = dev->data->dev_private;
2327 struct mlx5_ibv_shared *sh = priv->sh;
2328 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2329 struct mlx5dv_dr_domain *domain;
2331 resource->flags = dev_flow->group ? 0 : 1;
2332 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2333 domain = sh->fdb_domain;
2334 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2335 domain = sh->rx_domain;
2337 domain = sh->tx_domain;
2338 /* Lookup a matching resource from cache. */
2339 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2340 if (resource->reformat_type == cache_resource->reformat_type &&
2341 resource->ft_type == cache_resource->ft_type &&
2342 resource->flags == cache_resource->flags &&
2343 resource->size == cache_resource->size &&
2344 !memcmp((const void *)resource->buf,
2345 (const void *)cache_resource->buf,
2347 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2348 (void *)cache_resource,
2349 rte_atomic32_read(&cache_resource->refcnt));
2350 rte_atomic32_inc(&cache_resource->refcnt);
2351 dev_flow->dv.encap_decap = cache_resource;
2355 /* Register new encap/decap resource. */
2356 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2357 if (!cache_resource)
2358 return rte_flow_error_set(error, ENOMEM,
2359 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2360 "cannot allocate resource memory");
2361 *cache_resource = *resource;
2362 cache_resource->verbs_action =
2363 mlx5_glue->dv_create_flow_action_packet_reformat
2364 (sh->ctx, cache_resource->reformat_type,
2365 cache_resource->ft_type, domain, cache_resource->flags,
2366 cache_resource->size,
2367 (cache_resource->size ? cache_resource->buf : NULL));
2368 if (!cache_resource->verbs_action) {
2369 rte_free(cache_resource);
2370 return rte_flow_error_set(error, ENOMEM,
2371 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2372 NULL, "cannot create action");
2374 rte_atomic32_init(&cache_resource->refcnt);
2375 rte_atomic32_inc(&cache_resource->refcnt);
2376 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2377 dev_flow->dv.encap_decap = cache_resource;
2378 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2379 (void *)cache_resource,
2380 rte_atomic32_read(&cache_resource->refcnt));
2385 * Find existing table jump resource or create and register a new one.
2387 * @param[in, out] dev
2388 * Pointer to rte_eth_dev structure.
2389 * @param[in, out] tbl
2390 * Pointer to flow table resource.
2391 * @parm[in, out] dev_flow
2392 * Pointer to the dev_flow.
2394 * pointer to error structure.
2397 * 0 on success otherwise -errno and errno is set.
2400 flow_dv_jump_tbl_resource_register
2401 (struct rte_eth_dev *dev __rte_unused,
2402 struct mlx5_flow_tbl_resource *tbl,
2403 struct mlx5_flow *dev_flow,
2404 struct rte_flow_error *error)
2406 struct mlx5_flow_tbl_data_entry *tbl_data =
2407 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2411 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2413 tbl_data->jump.action =
2414 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2416 if (!tbl_data->jump.action)
2417 return rte_flow_error_set(error, ENOMEM,
2418 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2419 NULL, "cannot create jump action");
2420 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2421 (void *)&tbl_data->jump, cnt);
2423 MLX5_ASSERT(tbl_data->jump.action);
2424 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2425 (void *)&tbl_data->jump, cnt);
2427 rte_atomic32_inc(&tbl_data->jump.refcnt);
2428 dev_flow->dv.jump = &tbl_data->jump;
2433 * Find existing table port ID resource or create and register a new one.
2435 * @param[in, out] dev
2436 * Pointer to rte_eth_dev structure.
2437 * @param[in, out] resource
2438 * Pointer to port ID action resource.
2439 * @parm[in, out] dev_flow
2440 * Pointer to the dev_flow.
2442 * pointer to error structure.
2445 * 0 on success otherwise -errno and errno is set.
2448 flow_dv_port_id_action_resource_register
2449 (struct rte_eth_dev *dev,
2450 struct mlx5_flow_dv_port_id_action_resource *resource,
2451 struct mlx5_flow *dev_flow,
2452 struct rte_flow_error *error)
2454 struct mlx5_priv *priv = dev->data->dev_private;
2455 struct mlx5_ibv_shared *sh = priv->sh;
2456 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2458 /* Lookup a matching resource from cache. */
2459 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2460 if (resource->port_id == cache_resource->port_id) {
2461 DRV_LOG(DEBUG, "port id action resource resource %p: "
2463 (void *)cache_resource,
2464 rte_atomic32_read(&cache_resource->refcnt));
2465 rte_atomic32_inc(&cache_resource->refcnt);
2466 dev_flow->dv.port_id_action = cache_resource;
2470 /* Register new port id action resource. */
2471 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2472 if (!cache_resource)
2473 return rte_flow_error_set(error, ENOMEM,
2474 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2475 "cannot allocate resource memory");
2476 *cache_resource = *resource;
2478 * Depending on rdma_core version the glue routine calls
2479 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2480 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2482 cache_resource->action =
2483 mlx5_glue->dr_create_flow_action_dest_port
2484 (priv->sh->fdb_domain, resource->port_id);
2485 if (!cache_resource->action) {
2486 rte_free(cache_resource);
2487 return rte_flow_error_set(error, ENOMEM,
2488 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2489 NULL, "cannot create action");
2491 rte_atomic32_init(&cache_resource->refcnt);
2492 rte_atomic32_inc(&cache_resource->refcnt);
2493 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2494 dev_flow->dv.port_id_action = cache_resource;
2495 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2496 (void *)cache_resource,
2497 rte_atomic32_read(&cache_resource->refcnt));
2502 * Find existing push vlan resource or create and register a new one.
2504 * @param [in, out] dev
2505 * Pointer to rte_eth_dev structure.
2506 * @param[in, out] resource
2507 * Pointer to port ID action resource.
2508 * @parm[in, out] dev_flow
2509 * Pointer to the dev_flow.
2511 * pointer to error structure.
2514 * 0 on success otherwise -errno and errno is set.
2517 flow_dv_push_vlan_action_resource_register
2518 (struct rte_eth_dev *dev,
2519 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2520 struct mlx5_flow *dev_flow,
2521 struct rte_flow_error *error)
2523 struct mlx5_priv *priv = dev->data->dev_private;
2524 struct mlx5_ibv_shared *sh = priv->sh;
2525 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2526 struct mlx5dv_dr_domain *domain;
2528 /* Lookup a matching resource from cache. */
2529 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2530 if (resource->vlan_tag == cache_resource->vlan_tag &&
2531 resource->ft_type == cache_resource->ft_type) {
2532 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2534 (void *)cache_resource,
2535 rte_atomic32_read(&cache_resource->refcnt));
2536 rte_atomic32_inc(&cache_resource->refcnt);
2537 dev_flow->dv.push_vlan_res = cache_resource;
2541 /* Register new push_vlan action resource. */
2542 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2543 if (!cache_resource)
2544 return rte_flow_error_set(error, ENOMEM,
2545 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2546 "cannot allocate resource memory");
2547 *cache_resource = *resource;
2548 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2549 domain = sh->fdb_domain;
2550 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2551 domain = sh->rx_domain;
2553 domain = sh->tx_domain;
2554 cache_resource->action =
2555 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2556 resource->vlan_tag);
2557 if (!cache_resource->action) {
2558 rte_free(cache_resource);
2559 return rte_flow_error_set(error, ENOMEM,
2560 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2561 NULL, "cannot create action");
2563 rte_atomic32_init(&cache_resource->refcnt);
2564 rte_atomic32_inc(&cache_resource->refcnt);
2565 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2566 dev_flow->dv.push_vlan_res = cache_resource;
2567 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2568 (void *)cache_resource,
2569 rte_atomic32_read(&cache_resource->refcnt));
2573 * Get the size of specific rte_flow_item_type
2575 * @param[in] item_type
2576 * Tested rte_flow_item_type.
2579 * sizeof struct item_type, 0 if void or irrelevant.
2582 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2586 switch (item_type) {
2587 case RTE_FLOW_ITEM_TYPE_ETH:
2588 retval = sizeof(struct rte_flow_item_eth);
2590 case RTE_FLOW_ITEM_TYPE_VLAN:
2591 retval = sizeof(struct rte_flow_item_vlan);
2593 case RTE_FLOW_ITEM_TYPE_IPV4:
2594 retval = sizeof(struct rte_flow_item_ipv4);
2596 case RTE_FLOW_ITEM_TYPE_IPV6:
2597 retval = sizeof(struct rte_flow_item_ipv6);
2599 case RTE_FLOW_ITEM_TYPE_UDP:
2600 retval = sizeof(struct rte_flow_item_udp);
2602 case RTE_FLOW_ITEM_TYPE_TCP:
2603 retval = sizeof(struct rte_flow_item_tcp);
2605 case RTE_FLOW_ITEM_TYPE_VXLAN:
2606 retval = sizeof(struct rte_flow_item_vxlan);
2608 case RTE_FLOW_ITEM_TYPE_GRE:
2609 retval = sizeof(struct rte_flow_item_gre);
2611 case RTE_FLOW_ITEM_TYPE_NVGRE:
2612 retval = sizeof(struct rte_flow_item_nvgre);
2614 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2615 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2617 case RTE_FLOW_ITEM_TYPE_MPLS:
2618 retval = sizeof(struct rte_flow_item_mpls);
2620 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2628 #define MLX5_ENCAP_IPV4_VERSION 0x40
2629 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2630 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2631 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2632 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2633 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2634 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2637 * Convert the encap action data from list of rte_flow_item to raw buffer
2640 * Pointer to rte_flow_item objects list.
2642 * Pointer to the output buffer.
2644 * Pointer to the output buffer size.
2646 * Pointer to the error structure.
2649 * 0 on success, a negative errno value otherwise and rte_errno is set.
2652 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2653 size_t *size, struct rte_flow_error *error)
2655 struct rte_ether_hdr *eth = NULL;
2656 struct rte_vlan_hdr *vlan = NULL;
2657 struct rte_ipv4_hdr *ipv4 = NULL;
2658 struct rte_ipv6_hdr *ipv6 = NULL;
2659 struct rte_udp_hdr *udp = NULL;
2660 struct rte_vxlan_hdr *vxlan = NULL;
2661 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2662 struct rte_gre_hdr *gre = NULL;
2664 size_t temp_size = 0;
2667 return rte_flow_error_set(error, EINVAL,
2668 RTE_FLOW_ERROR_TYPE_ACTION,
2669 NULL, "invalid empty data");
2670 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2671 len = flow_dv_get_item_len(items->type);
2672 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2673 return rte_flow_error_set(error, EINVAL,
2674 RTE_FLOW_ERROR_TYPE_ACTION,
2675 (void *)items->type,
2676 "items total size is too big"
2677 " for encap action");
2678 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2679 switch (items->type) {
2680 case RTE_FLOW_ITEM_TYPE_ETH:
2681 eth = (struct rte_ether_hdr *)&buf[temp_size];
2683 case RTE_FLOW_ITEM_TYPE_VLAN:
2684 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2686 return rte_flow_error_set(error, EINVAL,
2687 RTE_FLOW_ERROR_TYPE_ACTION,
2688 (void *)items->type,
2689 "eth header not found");
2690 if (!eth->ether_type)
2691 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2693 case RTE_FLOW_ITEM_TYPE_IPV4:
2694 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2696 return rte_flow_error_set(error, EINVAL,
2697 RTE_FLOW_ERROR_TYPE_ACTION,
2698 (void *)items->type,
2699 "neither eth nor vlan"
2701 if (vlan && !vlan->eth_proto)
2702 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2703 else if (eth && !eth->ether_type)
2704 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2705 if (!ipv4->version_ihl)
2706 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2707 MLX5_ENCAP_IPV4_IHL_MIN;
2708 if (!ipv4->time_to_live)
2709 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2711 case RTE_FLOW_ITEM_TYPE_IPV6:
2712 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2714 return rte_flow_error_set(error, EINVAL,
2715 RTE_FLOW_ERROR_TYPE_ACTION,
2716 (void *)items->type,
2717 "neither eth nor vlan"
2719 if (vlan && !vlan->eth_proto)
2720 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2721 else if (eth && !eth->ether_type)
2722 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2723 if (!ipv6->vtc_flow)
2725 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2726 if (!ipv6->hop_limits)
2727 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2729 case RTE_FLOW_ITEM_TYPE_UDP:
2730 udp = (struct rte_udp_hdr *)&buf[temp_size];
2732 return rte_flow_error_set(error, EINVAL,
2733 RTE_FLOW_ERROR_TYPE_ACTION,
2734 (void *)items->type,
2735 "ip header not found");
2736 if (ipv4 && !ipv4->next_proto_id)
2737 ipv4->next_proto_id = IPPROTO_UDP;
2738 else if (ipv6 && !ipv6->proto)
2739 ipv6->proto = IPPROTO_UDP;
2741 case RTE_FLOW_ITEM_TYPE_VXLAN:
2742 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2744 return rte_flow_error_set(error, EINVAL,
2745 RTE_FLOW_ERROR_TYPE_ACTION,
2746 (void *)items->type,
2747 "udp header not found");
2749 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2750 if (!vxlan->vx_flags)
2752 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2754 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2755 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2757 return rte_flow_error_set(error, EINVAL,
2758 RTE_FLOW_ERROR_TYPE_ACTION,
2759 (void *)items->type,
2760 "udp header not found");
2761 if (!vxlan_gpe->proto)
2762 return rte_flow_error_set(error, EINVAL,
2763 RTE_FLOW_ERROR_TYPE_ACTION,
2764 (void *)items->type,
2765 "next protocol not found");
2768 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2769 if (!vxlan_gpe->vx_flags)
2770 vxlan_gpe->vx_flags =
2771 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2773 case RTE_FLOW_ITEM_TYPE_GRE:
2774 case RTE_FLOW_ITEM_TYPE_NVGRE:
2775 gre = (struct rte_gre_hdr *)&buf[temp_size];
2777 return rte_flow_error_set(error, EINVAL,
2778 RTE_FLOW_ERROR_TYPE_ACTION,
2779 (void *)items->type,
2780 "next protocol not found");
2782 return rte_flow_error_set(error, EINVAL,
2783 RTE_FLOW_ERROR_TYPE_ACTION,
2784 (void *)items->type,
2785 "ip header not found");
2786 if (ipv4 && !ipv4->next_proto_id)
2787 ipv4->next_proto_id = IPPROTO_GRE;
2788 else if (ipv6 && !ipv6->proto)
2789 ipv6->proto = IPPROTO_GRE;
2791 case RTE_FLOW_ITEM_TYPE_VOID:
2794 return rte_flow_error_set(error, EINVAL,
2795 RTE_FLOW_ERROR_TYPE_ACTION,
2796 (void *)items->type,
2797 "unsupported item type");
2807 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2809 struct rte_ether_hdr *eth = NULL;
2810 struct rte_vlan_hdr *vlan = NULL;
2811 struct rte_ipv6_hdr *ipv6 = NULL;
2812 struct rte_udp_hdr *udp = NULL;
2816 eth = (struct rte_ether_hdr *)data;
2817 next_hdr = (char *)(eth + 1);
2818 proto = RTE_BE16(eth->ether_type);
2821 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2822 vlan = (struct rte_vlan_hdr *)next_hdr;
2823 proto = RTE_BE16(vlan->eth_proto);
2824 next_hdr += sizeof(struct rte_vlan_hdr);
2827 /* HW calculates IPv4 csum. no need to proceed */
2828 if (proto == RTE_ETHER_TYPE_IPV4)
2831 /* non IPv4/IPv6 header. not supported */
2832 if (proto != RTE_ETHER_TYPE_IPV6) {
2833 return rte_flow_error_set(error, ENOTSUP,
2834 RTE_FLOW_ERROR_TYPE_ACTION,
2835 NULL, "Cannot offload non IPv4/IPv6");
2838 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2840 /* ignore non UDP */
2841 if (ipv6->proto != IPPROTO_UDP)
2844 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2845 udp->dgram_cksum = 0;
2851 * Convert L2 encap action to DV specification.
2854 * Pointer to rte_eth_dev structure.
2856 * Pointer to action structure.
2857 * @param[in, out] dev_flow
2858 * Pointer to the mlx5_flow.
2859 * @param[in] transfer
2860 * Mark if the flow is E-Switch flow.
2862 * Pointer to the error structure.
2865 * 0 on success, a negative errno value otherwise and rte_errno is set.
2868 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2869 const struct rte_flow_action *action,
2870 struct mlx5_flow *dev_flow,
2872 struct rte_flow_error *error)
2874 const struct rte_flow_item *encap_data;
2875 const struct rte_flow_action_raw_encap *raw_encap_data;
2876 struct mlx5_flow_dv_encap_decap_resource res = {
2878 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2879 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2880 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2883 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2885 (const struct rte_flow_action_raw_encap *)action->conf;
2886 res.size = raw_encap_data->size;
2887 memcpy(res.buf, raw_encap_data->data, res.size);
2889 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2891 ((const struct rte_flow_action_vxlan_encap *)
2892 action->conf)->definition;
2895 ((const struct rte_flow_action_nvgre_encap *)
2896 action->conf)->definition;
2897 if (flow_dv_convert_encap_data(encap_data, res.buf,
2901 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2903 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2904 return rte_flow_error_set(error, EINVAL,
2905 RTE_FLOW_ERROR_TYPE_ACTION,
2906 NULL, "can't create L2 encap action");
2911 * Convert L2 decap action to DV specification.
2914 * Pointer to rte_eth_dev structure.
2915 * @param[in, out] dev_flow
2916 * Pointer to the mlx5_flow.
2917 * @param[in] transfer
2918 * Mark if the flow is E-Switch flow.
2920 * Pointer to the error structure.
2923 * 0 on success, a negative errno value otherwise and rte_errno is set.
2926 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2927 struct mlx5_flow *dev_flow,
2929 struct rte_flow_error *error)
2931 struct mlx5_flow_dv_encap_decap_resource res = {
2934 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2935 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2936 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2939 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2940 return rte_flow_error_set(error, EINVAL,
2941 RTE_FLOW_ERROR_TYPE_ACTION,
2942 NULL, "can't create L2 decap action");
2947 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2950 * Pointer to rte_eth_dev structure.
2952 * Pointer to action structure.
2953 * @param[in, out] dev_flow
2954 * Pointer to the mlx5_flow.
2956 * Pointer to the flow attributes.
2958 * Pointer to the error structure.
2961 * 0 on success, a negative errno value otherwise and rte_errno is set.
2964 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2965 const struct rte_flow_action *action,
2966 struct mlx5_flow *dev_flow,
2967 const struct rte_flow_attr *attr,
2968 struct rte_flow_error *error)
2970 const struct rte_flow_action_raw_encap *encap_data;
2971 struct mlx5_flow_dv_encap_decap_resource res;
2973 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2974 res.size = encap_data->size;
2975 memcpy(res.buf, encap_data->data, res.size);
2976 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
2977 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
2978 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
2980 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2982 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2983 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2984 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2985 return rte_flow_error_set(error, EINVAL,
2986 RTE_FLOW_ERROR_TYPE_ACTION,
2987 NULL, "can't create encap action");
2992 * Create action push VLAN.
2995 * Pointer to rte_eth_dev structure.
2997 * Pointer to the flow attributes.
2999 * Pointer to the vlan to push to the Ethernet header.
3000 * @param[in, out] dev_flow
3001 * Pointer to the mlx5_flow.
3003 * Pointer to the error structure.
3006 * 0 on success, a negative errno value otherwise and rte_errno is set.
3009 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3010 const struct rte_flow_attr *attr,
3011 const struct rte_vlan_hdr *vlan,
3012 struct mlx5_flow *dev_flow,
3013 struct rte_flow_error *error)
3015 struct mlx5_flow_dv_push_vlan_action_resource res;
3018 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3021 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3023 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3024 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3025 return flow_dv_push_vlan_action_resource_register
3026 (dev, &res, dev_flow, error);
3030 * Validate the modify-header actions.
3032 * @param[in] action_flags
3033 * Holds the actions detected until now.
3035 * Pointer to the modify action.
3037 * Pointer to error structure.
3040 * 0 on success, a negative errno value otherwise and rte_errno is set.
3043 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3044 const struct rte_flow_action *action,
3045 struct rte_flow_error *error)
3047 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3048 return rte_flow_error_set(error, EINVAL,
3049 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3050 NULL, "action configuration not set");
3051 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
3052 return rte_flow_error_set(error, EINVAL,
3053 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3054 "can't have encap action before"
3060 * Validate the modify-header MAC address actions.
3062 * @param[in] action_flags
3063 * Holds the actions detected until now.
3065 * Pointer to the modify action.
3066 * @param[in] item_flags
3067 * Holds the items detected.
3069 * Pointer to error structure.
3072 * 0 on success, a negative errno value otherwise and rte_errno is set.
3075 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3076 const struct rte_flow_action *action,
3077 const uint64_t item_flags,
3078 struct rte_flow_error *error)
3082 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3084 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3085 return rte_flow_error_set(error, EINVAL,
3086 RTE_FLOW_ERROR_TYPE_ACTION,
3088 "no L2 item in pattern");
3094 * Validate the modify-header IPv4 address actions.
3096 * @param[in] action_flags
3097 * Holds the actions detected until now.
3099 * Pointer to the modify action.
3100 * @param[in] item_flags
3101 * Holds the items detected.
3103 * Pointer to error structure.
3106 * 0 on success, a negative errno value otherwise and rte_errno is set.
3109 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3110 const struct rte_flow_action *action,
3111 const uint64_t item_flags,
3112 struct rte_flow_error *error)
3116 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3118 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3119 return rte_flow_error_set(error, EINVAL,
3120 RTE_FLOW_ERROR_TYPE_ACTION,
3122 "no ipv4 item in pattern");
3128 * Validate the modify-header IPv6 address actions.
3130 * @param[in] action_flags
3131 * Holds the actions detected until now.
3133 * Pointer to the modify action.
3134 * @param[in] item_flags
3135 * Holds the items detected.
3137 * Pointer to error structure.
3140 * 0 on success, a negative errno value otherwise and rte_errno is set.
3143 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3144 const struct rte_flow_action *action,
3145 const uint64_t item_flags,
3146 struct rte_flow_error *error)
3150 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3152 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3153 return rte_flow_error_set(error, EINVAL,
3154 RTE_FLOW_ERROR_TYPE_ACTION,
3156 "no ipv6 item in pattern");
3162 * Validate the modify-header TP actions.
3164 * @param[in] action_flags
3165 * Holds the actions detected until now.
3167 * Pointer to the modify action.
3168 * @param[in] item_flags
3169 * Holds the items detected.
3171 * Pointer to error structure.
3174 * 0 on success, a negative errno value otherwise and rte_errno is set.
3177 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3178 const struct rte_flow_action *action,
3179 const uint64_t item_flags,
3180 struct rte_flow_error *error)
3184 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3186 if (!(item_flags & MLX5_FLOW_LAYER_L4))
3187 return rte_flow_error_set(error, EINVAL,
3188 RTE_FLOW_ERROR_TYPE_ACTION,
3189 NULL, "no transport layer "
3196 * Validate the modify-header actions of increment/decrement
3197 * TCP Sequence-number.
3199 * @param[in] action_flags
3200 * Holds the actions detected until now.
3202 * Pointer to the modify action.
3203 * @param[in] item_flags
3204 * Holds the items detected.
3206 * Pointer to error structure.
3209 * 0 on success, a negative errno value otherwise and rte_errno is set.
3212 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3213 const struct rte_flow_action *action,
3214 const uint64_t item_flags,
3215 struct rte_flow_error *error)
3219 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3221 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3222 return rte_flow_error_set(error, EINVAL,
3223 RTE_FLOW_ERROR_TYPE_ACTION,
3224 NULL, "no TCP item in"
3226 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3227 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3228 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3229 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3230 return rte_flow_error_set(error, EINVAL,
3231 RTE_FLOW_ERROR_TYPE_ACTION,
3233 "cannot decrease and increase"
3234 " TCP sequence number"
3235 " at the same time");
3241 * Validate the modify-header actions of increment/decrement
3242 * TCP Acknowledgment number.
3244 * @param[in] action_flags
3245 * Holds the actions detected until now.
3247 * Pointer to the modify action.
3248 * @param[in] item_flags
3249 * Holds the items detected.
3251 * Pointer to error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3258 const struct rte_flow_action *action,
3259 const uint64_t item_flags,
3260 struct rte_flow_error *error)
3264 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3266 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3267 return rte_flow_error_set(error, EINVAL,
3268 RTE_FLOW_ERROR_TYPE_ACTION,
3269 NULL, "no TCP item in"
3271 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3272 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3273 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3274 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3275 return rte_flow_error_set(error, EINVAL,
3276 RTE_FLOW_ERROR_TYPE_ACTION,
3278 "cannot decrease and increase"
3279 " TCP acknowledgment number"
3280 " at the same time");
3286 * Validate the modify-header TTL actions.
3288 * @param[in] action_flags
3289 * Holds the actions detected until now.
3291 * Pointer to the modify action.
3292 * @param[in] item_flags
3293 * Holds the items detected.
3295 * Pointer to error structure.
3298 * 0 on success, a negative errno value otherwise and rte_errno is set.
3301 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3302 const struct rte_flow_action *action,
3303 const uint64_t item_flags,
3304 struct rte_flow_error *error)
3308 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3310 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3311 return rte_flow_error_set(error, EINVAL,
3312 RTE_FLOW_ERROR_TYPE_ACTION,
3314 "no IP protocol in pattern");
3320 * Validate jump action.
3323 * Pointer to the jump action.
3324 * @param[in] action_flags
3325 * Holds the actions detected until now.
3326 * @param[in] attributes
3327 * Pointer to flow attributes
3328 * @param[in] external
3329 * Action belongs to flow rule created by request external to PMD.
3331 * Pointer to error structure.
3334 * 0 on success, a negative errno value otherwise and rte_errno is set.
3337 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3338 uint64_t action_flags,
3339 const struct rte_flow_attr *attributes,
3340 bool external, struct rte_flow_error *error)
3342 uint32_t target_group, table;
3345 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3346 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3347 return rte_flow_error_set(error, EINVAL,
3348 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3349 "can't have 2 fate actions in"
3351 if (action_flags & MLX5_FLOW_ACTION_METER)
3352 return rte_flow_error_set(error, ENOTSUP,
3353 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3354 "jump with meter not support");
3356 return rte_flow_error_set(error, EINVAL,
3357 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3358 NULL, "action configuration not set");
3360 ((const struct rte_flow_action_jump *)action->conf)->group;
3361 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3362 true, &table, error);
3365 if (attributes->group == target_group)
3366 return rte_flow_error_set(error, EINVAL,
3367 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3368 "target group must be other than"
3369 " the current flow group");
3374 * Validate the port_id action.
3377 * Pointer to rte_eth_dev structure.
3378 * @param[in] action_flags
3379 * Bit-fields that holds the actions detected until now.
3381 * Port_id RTE action structure.
3383 * Attributes of flow that includes this action.
3385 * Pointer to error structure.
3388 * 0 on success, a negative errno value otherwise and rte_errno is set.
3391 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3392 uint64_t action_flags,
3393 const struct rte_flow_action *action,
3394 const struct rte_flow_attr *attr,
3395 struct rte_flow_error *error)
3397 const struct rte_flow_action_port_id *port_id;
3398 struct mlx5_priv *act_priv;
3399 struct mlx5_priv *dev_priv;
3402 if (!attr->transfer)
3403 return rte_flow_error_set(error, ENOTSUP,
3404 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3406 "port id action is valid in transfer"
3408 if (!action || !action->conf)
3409 return rte_flow_error_set(error, ENOTSUP,
3410 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3412 "port id action parameters must be"
3414 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3415 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3416 return rte_flow_error_set(error, EINVAL,
3417 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3418 "can have only one fate actions in"
3420 dev_priv = mlx5_dev_to_eswitch_info(dev);
3422 return rte_flow_error_set(error, rte_errno,
3423 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3425 "failed to obtain E-Switch info");
3426 port_id = action->conf;
3427 port = port_id->original ? dev->data->port_id : port_id->id;
3428 act_priv = mlx5_port_to_eswitch_info(port, false);
3430 return rte_flow_error_set
3432 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3433 "failed to obtain E-Switch port id for port");
3434 if (act_priv->domain_id != dev_priv->domain_id)
3435 return rte_flow_error_set
3437 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3438 "port does not belong to"
3439 " E-Switch being configured");
3444 * Get the maximum number of modify header actions.
3447 * Pointer to rte_eth_dev structure.
3449 * Flags bits to check if root level.
3452 * Max number of modify header actions device can support.
3455 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3458 * There's no way to directly query the max cap. Although it has to be
3459 * acquried by iterative trial, it is a safe assumption that more
3460 * actions are supported by FW if extensive metadata register is
3461 * supported. (Only in the root table)
3463 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3464 return MLX5_MAX_MODIFY_NUM;
3466 return mlx5_flow_ext_mreg_supported(dev) ?
3467 MLX5_ROOT_TBL_MODIFY_NUM :
3468 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3472 * Validate the meter action.
3475 * Pointer to rte_eth_dev structure.
3476 * @param[in] action_flags
3477 * Bit-fields that holds the actions detected until now.
3479 * Pointer to the meter action.
3481 * Attributes of flow that includes this action.
3483 * Pointer to error structure.
3486 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3489 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3490 uint64_t action_flags,
3491 const struct rte_flow_action *action,
3492 const struct rte_flow_attr *attr,
3493 struct rte_flow_error *error)
3495 struct mlx5_priv *priv = dev->data->dev_private;
3496 const struct rte_flow_action_meter *am = action->conf;
3497 struct mlx5_flow_meter *fm;
3500 return rte_flow_error_set(error, EINVAL,
3501 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3502 "meter action conf is NULL");
3504 if (action_flags & MLX5_FLOW_ACTION_METER)
3505 return rte_flow_error_set(error, ENOTSUP,
3506 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3507 "meter chaining not support");
3508 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3509 return rte_flow_error_set(error, ENOTSUP,
3510 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3511 "meter with jump not support");
3513 return rte_flow_error_set(error, ENOTSUP,
3514 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3516 "meter action not supported");
3517 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3519 return rte_flow_error_set(error, EINVAL,
3520 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3522 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3523 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3524 (!fm->attr.egress && !attr->egress && attr->ingress))))
3525 return rte_flow_error_set(error, EINVAL,
3526 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3527 "Flow attributes are either invalid "
3528 "or have a conflict with current "
3529 "meter attributes");
3534 * Validate the modify-header IPv4 DSCP actions.
3536 * @param[in] action_flags
3537 * Holds the actions detected until now.
3539 * Pointer to the modify action.
3540 * @param[in] item_flags
3541 * Holds the items detected.
3543 * Pointer to error structure.
3546 * 0 on success, a negative errno value otherwise and rte_errno is set.
3549 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3550 const struct rte_flow_action *action,
3551 const uint64_t item_flags,
3552 struct rte_flow_error *error)
3556 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3558 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3559 return rte_flow_error_set(error, EINVAL,
3560 RTE_FLOW_ERROR_TYPE_ACTION,
3562 "no ipv4 item in pattern");
3568 * Validate the modify-header IPv6 DSCP actions.
3570 * @param[in] action_flags
3571 * Holds the actions detected until now.
3573 * Pointer to the modify action.
3574 * @param[in] item_flags
3575 * Holds the items detected.
3577 * Pointer to error structure.
3580 * 0 on success, a negative errno value otherwise and rte_errno is set.
3583 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3584 const struct rte_flow_action *action,
3585 const uint64_t item_flags,
3586 struct rte_flow_error *error)
3590 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3592 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3593 return rte_flow_error_set(error, EINVAL,
3594 RTE_FLOW_ERROR_TYPE_ACTION,
3596 "no ipv6 item in pattern");
3602 * Find existing modify-header resource or create and register a new one.
3604 * @param dev[in, out]
3605 * Pointer to rte_eth_dev structure.
3606 * @param[in, out] resource
3607 * Pointer to modify-header resource.
3608 * @parm[in, out] dev_flow
3609 * Pointer to the dev_flow.
3611 * pointer to error structure.
3614 * 0 on success otherwise -errno and errno is set.
3617 flow_dv_modify_hdr_resource_register
3618 (struct rte_eth_dev *dev,
3619 struct mlx5_flow_dv_modify_hdr_resource *resource,
3620 struct mlx5_flow *dev_flow,
3621 struct rte_flow_error *error)
3623 struct mlx5_priv *priv = dev->data->dev_private;
3624 struct mlx5_ibv_shared *sh = priv->sh;
3625 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3626 struct mlx5dv_dr_domain *ns;
3627 uint32_t actions_len;
3630 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3631 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3633 return rte_flow_error_set(error, EOVERFLOW,
3634 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3635 "too many modify header items");
3636 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3637 ns = sh->fdb_domain;
3638 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3642 /* Lookup a matching resource from cache. */
3643 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3644 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3645 if (resource->ft_type == cache_resource->ft_type &&
3646 resource->actions_num == cache_resource->actions_num &&
3647 resource->flags == cache_resource->flags &&
3648 !memcmp((const void *)resource->actions,
3649 (const void *)cache_resource->actions,
3651 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3652 (void *)cache_resource,
3653 rte_atomic32_read(&cache_resource->refcnt));
3654 rte_atomic32_inc(&cache_resource->refcnt);
3655 dev_flow->dv.modify_hdr = cache_resource;
3659 /* Register new modify-header resource. */
3660 cache_resource = rte_calloc(__func__, 1,
3661 sizeof(*cache_resource) + actions_len, 0);
3662 if (!cache_resource)
3663 return rte_flow_error_set(error, ENOMEM,
3664 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3665 "cannot allocate resource memory");
3666 *cache_resource = *resource;
3667 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3668 cache_resource->verbs_action =
3669 mlx5_glue->dv_create_flow_action_modify_header
3670 (sh->ctx, cache_resource->ft_type, ns,
3671 cache_resource->flags, actions_len,
3672 (uint64_t *)cache_resource->actions);
3673 if (!cache_resource->verbs_action) {
3674 rte_free(cache_resource);
3675 return rte_flow_error_set(error, ENOMEM,
3676 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3677 NULL, "cannot create action");
3679 rte_atomic32_init(&cache_resource->refcnt);
3680 rte_atomic32_inc(&cache_resource->refcnt);
3681 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3682 dev_flow->dv.modify_hdr = cache_resource;
3683 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3684 (void *)cache_resource,
3685 rte_atomic32_read(&cache_resource->refcnt));
3689 #define MLX5_CNT_CONTAINER_RESIZE 64
3692 * Get or create a flow counter.
3695 * Pointer to the Ethernet device structure.
3697 * Indicate if this counter is shared with other flows.
3699 * Counter identifier.
3702 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3704 static struct mlx5_flow_counter *
3705 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3708 struct mlx5_priv *priv = dev->data->dev_private;
3709 struct mlx5_flow_counter *cnt = NULL;
3710 struct mlx5_devx_obj *dcs = NULL;
3712 if (!priv->config.devx) {
3713 rte_errno = ENOTSUP;
3717 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3718 if (cnt->shared && cnt->id == id) {
3724 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3727 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3729 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3733 struct mlx5_flow_counter tmpl = {
3739 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3741 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3747 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3752 * Release a flow counter.
3755 * Pointer to the Ethernet device structure.
3756 * @param[in] counter
3757 * Pointer to the counter handler.
3760 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3761 struct mlx5_flow_counter *counter)
3763 struct mlx5_priv *priv = dev->data->dev_private;
3767 if (--counter->ref_cnt == 0) {
3768 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3769 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3775 * Query a devx flow counter.
3778 * Pointer to the Ethernet device structure.
3780 * Pointer to the flow counter.
3782 * The statistics value of packets.
3784 * The statistics value of bytes.
3787 * 0 on success, otherwise a negative errno value and rte_errno is set.
3790 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3791 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3794 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3799 * Get a pool by a counter.
3802 * Pointer to the counter.
3807 static struct mlx5_flow_counter_pool *
3808 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3811 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3812 return (struct mlx5_flow_counter_pool *)cnt - 1;
3818 * Get a pool by devx counter ID.
3821 * Pointer to the counter container.
3823 * The counter devx ID.
3826 * The counter pool pointer if exists, NULL otherwise,
3828 static struct mlx5_flow_counter_pool *
3829 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3831 struct mlx5_flow_counter_pool *pool;
3833 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3834 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3835 MLX5_COUNTERS_PER_POOL;
3837 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3844 * Allocate a new memory for the counter values wrapped by all the needed
3848 * Pointer to the Ethernet device structure.
3850 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3853 * The new memory management pointer on success, otherwise NULL and rte_errno
3856 static struct mlx5_counter_stats_mem_mng *
3857 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3859 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3860 (dev->data->dev_private))->sh;
3861 struct mlx5_devx_mkey_attr mkey_attr;
3862 struct mlx5_counter_stats_mem_mng *mem_mng;
3863 volatile struct flow_counter_stats *raw_data;
3864 int size = (sizeof(struct flow_counter_stats) *
3865 MLX5_COUNTERS_PER_POOL +
3866 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3867 sizeof(struct mlx5_counter_stats_mem_mng);
3868 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3875 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3876 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3877 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3878 IBV_ACCESS_LOCAL_WRITE);
3879 if (!mem_mng->umem) {
3884 mkey_attr.addr = (uintptr_t)mem;
3885 mkey_attr.size = size;
3886 mkey_attr.umem_id = mem_mng->umem->umem_id;
3887 mkey_attr.pd = sh->pdn;
3888 mkey_attr.log_entity_size = 0;
3889 mkey_attr.pg_access = 0;
3890 mkey_attr.klm_array = NULL;
3891 mkey_attr.klm_num = 0;
3892 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3894 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3899 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3900 raw_data = (volatile struct flow_counter_stats *)mem;
3901 for (i = 0; i < raws_n; ++i) {
3902 mem_mng->raws[i].mem_mng = mem_mng;
3903 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3905 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3910 * Resize a counter container.
3913 * Pointer to the Ethernet device structure.
3915 * Whether the pool is for counter that was allocated by batch command.
3918 * The new container pointer on success, otherwise NULL and rte_errno is set.
3920 static struct mlx5_pools_container *
3921 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3923 struct mlx5_priv *priv = dev->data->dev_private;
3924 struct mlx5_pools_container *cont =
3925 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3926 struct mlx5_pools_container *new_cont =
3927 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3928 struct mlx5_counter_stats_mem_mng *mem_mng;
3929 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3930 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3933 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3934 /* The last resize still hasn't detected by the host thread. */
3938 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3939 if (!new_cont->pools) {
3944 memcpy(new_cont->pools, cont->pools, cont->n *
3945 sizeof(struct mlx5_flow_counter_pool *));
3946 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3947 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3949 rte_free(new_cont->pools);
3952 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3953 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3954 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3956 new_cont->n = resize;
3957 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3958 TAILQ_INIT(&new_cont->pool_list);
3959 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3960 new_cont->init_mem_mng = mem_mng;
3962 /* Flip the master container. */
3963 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3968 * Query a devx flow counter.
3971 * Pointer to the Ethernet device structure.
3973 * Pointer to the flow counter.
3975 * The statistics value of packets.
3977 * The statistics value of bytes.
3980 * 0 on success, otherwise a negative errno value and rte_errno is set.
3983 _flow_dv_query_count(struct rte_eth_dev *dev,
3984 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3987 struct mlx5_priv *priv = dev->data->dev_private;
3988 struct mlx5_flow_counter_pool *pool =
3989 flow_dv_counter_pool_get(cnt);
3990 int offset = cnt - &pool->counters_raw[0];
3992 if (priv->counter_fallback)
3993 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3995 rte_spinlock_lock(&pool->sl);
3997 * The single counters allocation may allocate smaller ID than the
3998 * current allocated in parallel to the host reading.
3999 * In this case the new counter values must be reported as 0.
4001 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4005 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4006 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4008 rte_spinlock_unlock(&pool->sl);
4013 * Create and initialize a new counter pool.
4016 * Pointer to the Ethernet device structure.
4018 * The devX counter handle.
4020 * Whether the pool is for counter that was allocated by batch command.
4023 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4025 static struct mlx5_flow_counter_pool *
4026 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4029 struct mlx5_priv *priv = dev->data->dev_private;
4030 struct mlx5_flow_counter_pool *pool;
4031 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4033 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4036 if (cont->n == n_valid) {
4037 cont = flow_dv_container_resize(dev, batch);
4041 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4042 sizeof(struct mlx5_flow_counter);
4043 pool = rte_calloc(__func__, 1, size, 0);
4048 pool->min_dcs = dcs;
4049 pool->raw = cont->init_mem_mng->raws + n_valid %
4050 MLX5_CNT_CONTAINER_RESIZE;
4051 pool->raw_hw = NULL;
4052 rte_spinlock_init(&pool->sl);
4054 * The generation of the new allocated counters in this pool is 0, 2 in
4055 * the pool generation makes all the counters valid for allocation.
4057 rte_atomic64_set(&pool->query_gen, 0x2);
4058 TAILQ_INIT(&pool->counters);
4059 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4060 cont->pools[n_valid] = pool;
4061 /* Pool initialization must be updated before host thread access. */
4063 rte_atomic16_add(&cont->n_valid, 1);
4068 * Prepare a new counter and/or a new counter pool.
4071 * Pointer to the Ethernet device structure.
4072 * @param[out] cnt_free
4073 * Where to put the pointer of a new counter.
4075 * Whether the pool is for counter that was allocated by batch command.
4078 * The free counter pool pointer and @p cnt_free is set on success,
4079 * NULL otherwise and rte_errno is set.
4081 static struct mlx5_flow_counter_pool *
4082 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4083 struct mlx5_flow_counter **cnt_free,
4086 struct mlx5_priv *priv = dev->data->dev_private;
4087 struct mlx5_flow_counter_pool *pool;
4088 struct mlx5_devx_obj *dcs = NULL;
4089 struct mlx5_flow_counter *cnt;
4093 /* bulk_bitmap must be 0 for single counter allocation. */
4094 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4097 pool = flow_dv_find_pool_by_id
4098 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4100 pool = flow_dv_pool_create(dev, dcs, batch);
4102 mlx5_devx_cmd_destroy(dcs);
4105 } else if (dcs->id < pool->min_dcs->id) {
4106 rte_atomic64_set(&pool->a64_dcs,
4107 (int64_t)(uintptr_t)dcs);
4109 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4110 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4115 /* bulk_bitmap is in 128 counters units. */
4116 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4117 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4119 rte_errno = ENODATA;
4122 pool = flow_dv_pool_create(dev, dcs, batch);
4124 mlx5_devx_cmd_destroy(dcs);
4127 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4128 cnt = &pool->counters_raw[i];
4130 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4132 *cnt_free = &pool->counters_raw[0];
4137 * Search for existed shared counter.
4140 * Pointer to the relevant counter pool container.
4142 * The shared counter ID to search.
4145 * NULL if not existed, otherwise pointer to the shared counter.
4147 static struct mlx5_flow_counter *
4148 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4151 static struct mlx5_flow_counter *cnt;
4152 struct mlx5_flow_counter_pool *pool;
4155 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4156 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4157 cnt = &pool->counters_raw[i];
4158 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4166 * Allocate a flow counter.
4169 * Pointer to the Ethernet device structure.
4171 * Indicate if this counter is shared with other flows.
4173 * Counter identifier.
4175 * Counter flow group.
4178 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4180 static struct mlx5_flow_counter *
4181 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4184 struct mlx5_priv *priv = dev->data->dev_private;
4185 struct mlx5_flow_counter_pool *pool = NULL;
4186 struct mlx5_flow_counter *cnt_free = NULL;
4188 * Currently group 0 flow counter cannot be assigned to a flow if it is
4189 * not the first one in the batch counter allocation, so it is better
4190 * to allocate counters one by one for these flows in a separate
4192 * A counter can be shared between different groups so need to take
4193 * shared counters from the single container.
4195 uint32_t batch = (group && !shared) ? 1 : 0;
4196 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4199 if (priv->counter_fallback)
4200 return flow_dv_counter_alloc_fallback(dev, shared, id);
4201 if (!priv->config.devx) {
4202 rte_errno = ENOTSUP;
4206 cnt_free = flow_dv_counter_shared_search(cont, id);
4208 if (cnt_free->ref_cnt + 1 == 0) {
4212 cnt_free->ref_cnt++;
4216 /* Pools which has a free counters are in the start. */
4217 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4219 * The free counter reset values must be updated between the
4220 * counter release to the counter allocation, so, at least one
4221 * query must be done in this time. ensure it by saving the
4222 * query generation in the release time.
4223 * The free list is sorted according to the generation - so if
4224 * the first one is not updated, all the others are not
4227 cnt_free = TAILQ_FIRST(&pool->counters);
4228 if (cnt_free && cnt_free->query_gen + 1 <
4229 rte_atomic64_read(&pool->query_gen))
4234 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4238 cnt_free->batch = batch;
4239 /* Create a DV counter action only in the first time usage. */
4240 if (!cnt_free->action) {
4242 struct mlx5_devx_obj *dcs;
4245 offset = cnt_free - &pool->counters_raw[0];
4246 dcs = pool->min_dcs;
4249 dcs = cnt_free->dcs;
4251 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4253 if (!cnt_free->action) {
4258 /* Update the counter reset values. */
4259 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4262 cnt_free->shared = shared;
4263 cnt_free->ref_cnt = 1;
4265 if (!priv->sh->cmng.query_thread_on)
4266 /* Start the asynchronous batch query by the host thread. */
4267 mlx5_set_query_alarm(priv->sh);
4268 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4269 if (TAILQ_EMPTY(&pool->counters)) {
4270 /* Move the pool to the end of the container pool list. */
4271 TAILQ_REMOVE(&cont->pool_list, pool, next);
4272 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4278 * Release a flow counter.
4281 * Pointer to the Ethernet device structure.
4282 * @param[in] counter
4283 * Pointer to the counter handler.
4286 flow_dv_counter_release(struct rte_eth_dev *dev,
4287 struct mlx5_flow_counter *counter)
4289 struct mlx5_priv *priv = dev->data->dev_private;
4293 if (priv->counter_fallback) {
4294 flow_dv_counter_release_fallback(dev, counter);
4297 if (--counter->ref_cnt == 0) {
4298 struct mlx5_flow_counter_pool *pool =
4299 flow_dv_counter_pool_get(counter);
4301 /* Put the counter in the end - the last updated one. */
4302 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4303 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4308 * Verify the @p attributes will be correctly understood by the NIC and store
4309 * them in the @p flow if everything is correct.
4312 * Pointer to dev struct.
4313 * @param[in] attributes
4314 * Pointer to flow attributes
4315 * @param[in] external
4316 * This flow rule is created by request external to PMD.
4318 * Pointer to error structure.
4321 * 0 on success, a negative errno value otherwise and rte_errno is set.
4324 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4325 const struct rte_flow_attr *attributes,
4326 bool external __rte_unused,
4327 struct rte_flow_error *error)
4329 struct mlx5_priv *priv = dev->data->dev_private;
4330 uint32_t priority_max = priv->config.flow_prio - 1;
4332 #ifndef HAVE_MLX5DV_DR
4333 if (attributes->group)
4334 return rte_flow_error_set(error, ENOTSUP,
4335 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4337 "groups are not supported");
4342 ret = mlx5_flow_group_to_table(attributes, external,
4343 attributes->group, !!priv->fdb_def_rule,
4348 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4349 attributes->priority >= priority_max)
4350 return rte_flow_error_set(error, ENOTSUP,
4351 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4353 "priority out of range");
4354 if (attributes->transfer) {
4355 if (!priv->config.dv_esw_en)
4356 return rte_flow_error_set
4358 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4359 "E-Switch dr is not supported");
4360 if (!(priv->representor || priv->master))
4361 return rte_flow_error_set
4362 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4363 NULL, "E-Switch configuration can only be"
4364 " done by a master or a representor device");
4365 if (attributes->egress)
4366 return rte_flow_error_set
4368 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4369 "egress is not supported");
4371 if (!(attributes->egress ^ attributes->ingress))
4372 return rte_flow_error_set(error, ENOTSUP,
4373 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4374 "must specify exactly one of "
4375 "ingress or egress");
4380 * Internal validation function. For validating both actions and items.
4383 * Pointer to the rte_eth_dev structure.
4385 * Pointer to the flow attributes.
4387 * Pointer to the list of items.
4388 * @param[in] actions
4389 * Pointer to the list of actions.
4390 * @param[in] external
4391 * This flow rule is created by request external to PMD.
4393 * Pointer to the error structure.
4396 * 0 on success, a negative errno value otherwise and rte_errno is set.
4399 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4400 const struct rte_flow_item items[],
4401 const struct rte_flow_action actions[],
4402 bool external, struct rte_flow_error *error)
4405 uint64_t action_flags = 0;
4406 uint64_t item_flags = 0;
4407 uint64_t last_item = 0;
4408 uint8_t next_protocol = 0xff;
4409 uint16_t ether_type = 0;
4411 uint8_t item_ipv6_proto = 0;
4412 const struct rte_flow_item *gre_item = NULL;
4413 struct rte_flow_item_tcp nic_tcp_mask = {
4416 .src_port = RTE_BE16(UINT16_MAX),
4417 .dst_port = RTE_BE16(UINT16_MAX),
4420 struct mlx5_priv *priv = dev->data->dev_private;
4421 struct mlx5_dev_config *dev_conf = &priv->config;
4425 ret = flow_dv_validate_attributes(dev, attr, external, error);
4428 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4429 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4430 int type = items->type;
4433 case RTE_FLOW_ITEM_TYPE_VOID:
4435 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4436 ret = flow_dv_validate_item_port_id
4437 (dev, items, attr, item_flags, error);
4440 last_item = MLX5_FLOW_ITEM_PORT_ID;
4442 case RTE_FLOW_ITEM_TYPE_ETH:
4443 ret = mlx5_flow_validate_item_eth(items, item_flags,
4447 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4448 MLX5_FLOW_LAYER_OUTER_L2;
4449 if (items->mask != NULL && items->spec != NULL) {
4451 ((const struct rte_flow_item_eth *)
4454 ((const struct rte_flow_item_eth *)
4456 ether_type = rte_be_to_cpu_16(ether_type);
4461 case RTE_FLOW_ITEM_TYPE_VLAN:
4462 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4466 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4467 MLX5_FLOW_LAYER_OUTER_VLAN;
4468 if (items->mask != NULL && items->spec != NULL) {
4470 ((const struct rte_flow_item_vlan *)
4471 items->spec)->inner_type;
4473 ((const struct rte_flow_item_vlan *)
4474 items->mask)->inner_type;
4475 ether_type = rte_be_to_cpu_16(ether_type);
4480 case RTE_FLOW_ITEM_TYPE_IPV4:
4481 mlx5_flow_tunnel_ip_check(items, next_protocol,
4482 &item_flags, &tunnel);
4483 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4489 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4490 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4491 if (items->mask != NULL &&
4492 ((const struct rte_flow_item_ipv4 *)
4493 items->mask)->hdr.next_proto_id) {
4495 ((const struct rte_flow_item_ipv4 *)
4496 (items->spec))->hdr.next_proto_id;
4498 ((const struct rte_flow_item_ipv4 *)
4499 (items->mask))->hdr.next_proto_id;
4501 /* Reset for inner layer. */
4502 next_protocol = 0xff;
4505 case RTE_FLOW_ITEM_TYPE_IPV6:
4506 mlx5_flow_tunnel_ip_check(items, next_protocol,
4507 &item_flags, &tunnel);
4508 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4514 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4515 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4516 if (items->mask != NULL &&
4517 ((const struct rte_flow_item_ipv6 *)
4518 items->mask)->hdr.proto) {
4520 ((const struct rte_flow_item_ipv6 *)
4521 items->spec)->hdr.proto;
4523 ((const struct rte_flow_item_ipv6 *)
4524 items->spec)->hdr.proto;
4526 ((const struct rte_flow_item_ipv6 *)
4527 items->mask)->hdr.proto;
4529 /* Reset for inner layer. */
4530 next_protocol = 0xff;
4533 case RTE_FLOW_ITEM_TYPE_TCP:
4534 ret = mlx5_flow_validate_item_tcp
4541 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4542 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4544 case RTE_FLOW_ITEM_TYPE_UDP:
4545 ret = mlx5_flow_validate_item_udp(items, item_flags,
4550 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4551 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4553 case RTE_FLOW_ITEM_TYPE_GRE:
4554 ret = mlx5_flow_validate_item_gre(items, item_flags,
4555 next_protocol, error);
4559 last_item = MLX5_FLOW_LAYER_GRE;
4561 case RTE_FLOW_ITEM_TYPE_NVGRE:
4562 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4567 last_item = MLX5_FLOW_LAYER_NVGRE;
4569 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4570 ret = mlx5_flow_validate_item_gre_key
4571 (items, item_flags, gre_item, error);
4574 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4576 case RTE_FLOW_ITEM_TYPE_VXLAN:
4577 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4581 last_item = MLX5_FLOW_LAYER_VXLAN;
4583 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4584 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4589 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4591 case RTE_FLOW_ITEM_TYPE_GENEVE:
4592 ret = mlx5_flow_validate_item_geneve(items,
4597 last_item = MLX5_FLOW_LAYER_GENEVE;
4599 case RTE_FLOW_ITEM_TYPE_MPLS:
4600 ret = mlx5_flow_validate_item_mpls(dev, items,
4605 last_item = MLX5_FLOW_LAYER_MPLS;
4608 case RTE_FLOW_ITEM_TYPE_MARK:
4609 ret = flow_dv_validate_item_mark(dev, items, attr,
4613 last_item = MLX5_FLOW_ITEM_MARK;
4615 case RTE_FLOW_ITEM_TYPE_META:
4616 ret = flow_dv_validate_item_meta(dev, items, attr,
4620 last_item = MLX5_FLOW_ITEM_METADATA;
4622 case RTE_FLOW_ITEM_TYPE_ICMP:
4623 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4628 last_item = MLX5_FLOW_LAYER_ICMP;
4630 case RTE_FLOW_ITEM_TYPE_ICMP6:
4631 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4636 last_item = MLX5_FLOW_LAYER_ICMP6;
4638 case RTE_FLOW_ITEM_TYPE_TAG:
4639 ret = flow_dv_validate_item_tag(dev, items,
4643 last_item = MLX5_FLOW_ITEM_TAG;
4645 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4646 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4648 case RTE_FLOW_ITEM_TYPE_GTP:
4649 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4653 last_item = MLX5_FLOW_LAYER_GTP;
4656 return rte_flow_error_set(error, ENOTSUP,
4657 RTE_FLOW_ERROR_TYPE_ITEM,
4658 NULL, "item not supported");
4660 item_flags |= last_item;
4662 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4663 int type = actions->type;
4664 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4665 return rte_flow_error_set(error, ENOTSUP,
4666 RTE_FLOW_ERROR_TYPE_ACTION,
4667 actions, "too many actions");
4669 case RTE_FLOW_ACTION_TYPE_VOID:
4671 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4672 ret = flow_dv_validate_action_port_id(dev,
4679 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4682 case RTE_FLOW_ACTION_TYPE_FLAG:
4683 ret = flow_dv_validate_action_flag(dev, action_flags,
4687 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4688 /* Count all modify-header actions as one. */
4689 if (!(action_flags &
4690 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4692 action_flags |= MLX5_FLOW_ACTION_FLAG |
4693 MLX5_FLOW_ACTION_MARK_EXT;
4695 action_flags |= MLX5_FLOW_ACTION_FLAG;
4699 case RTE_FLOW_ACTION_TYPE_MARK:
4700 ret = flow_dv_validate_action_mark(dev, actions,
4705 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4706 /* Count all modify-header actions as one. */
4707 if (!(action_flags &
4708 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4710 action_flags |= MLX5_FLOW_ACTION_MARK |
4711 MLX5_FLOW_ACTION_MARK_EXT;
4713 action_flags |= MLX5_FLOW_ACTION_MARK;
4717 case RTE_FLOW_ACTION_TYPE_SET_META:
4718 ret = flow_dv_validate_action_set_meta(dev, actions,
4723 /* Count all modify-header actions as one action. */
4724 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4726 action_flags |= MLX5_FLOW_ACTION_SET_META;
4728 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4729 ret = flow_dv_validate_action_set_tag(dev, actions,
4734 /* Count all modify-header actions as one action. */
4735 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4737 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4739 case RTE_FLOW_ACTION_TYPE_DROP:
4740 ret = mlx5_flow_validate_action_drop(action_flags,
4744 action_flags |= MLX5_FLOW_ACTION_DROP;
4747 case RTE_FLOW_ACTION_TYPE_QUEUE:
4748 ret = mlx5_flow_validate_action_queue(actions,
4753 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4756 case RTE_FLOW_ACTION_TYPE_RSS:
4757 ret = mlx5_flow_validate_action_rss(actions,
4763 action_flags |= MLX5_FLOW_ACTION_RSS;
4766 case RTE_FLOW_ACTION_TYPE_COUNT:
4767 ret = flow_dv_validate_action_count(dev, error);
4770 action_flags |= MLX5_FLOW_ACTION_COUNT;
4773 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4774 if (flow_dv_validate_action_pop_vlan(dev,
4780 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4783 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4784 ret = flow_dv_validate_action_push_vlan(action_flags,
4790 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4793 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4794 ret = flow_dv_validate_action_set_vlan_pcp
4795 (action_flags, actions, error);
4798 /* Count PCP with push_vlan command. */
4799 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4801 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4802 ret = flow_dv_validate_action_set_vlan_vid
4803 (item_flags, action_flags,
4807 /* Count VID with push_vlan command. */
4808 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4810 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4811 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4812 ret = flow_dv_validate_action_l2_encap(action_flags,
4817 action_flags |= actions->type ==
4818 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4819 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4820 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4823 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4824 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4825 ret = flow_dv_validate_action_l2_decap(action_flags,
4829 action_flags |= actions->type ==
4830 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4831 MLX5_FLOW_ACTION_VXLAN_DECAP :
4832 MLX5_FLOW_ACTION_NVGRE_DECAP;
4835 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4836 ret = flow_dv_validate_action_raw_encap(action_flags,
4841 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4844 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4845 ret = flow_dv_validate_action_raw_decap(action_flags,
4850 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4853 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4854 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4855 ret = flow_dv_validate_action_modify_mac(action_flags,
4861 /* Count all modify-header actions as one action. */
4862 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4864 action_flags |= actions->type ==
4865 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4866 MLX5_FLOW_ACTION_SET_MAC_SRC :
4867 MLX5_FLOW_ACTION_SET_MAC_DST;
4870 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4871 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4872 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4878 /* Count all modify-header actions as one action. */
4879 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4881 action_flags |= actions->type ==
4882 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4883 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4884 MLX5_FLOW_ACTION_SET_IPV4_DST;
4886 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4887 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4888 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4894 if (item_ipv6_proto == IPPROTO_ICMPV6)
4895 return rte_flow_error_set(error, ENOTSUP,
4896 RTE_FLOW_ERROR_TYPE_ACTION,
4898 "Can't change header "
4899 "with ICMPv6 proto");
4900 /* Count all modify-header actions as one action. */
4901 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4903 action_flags |= actions->type ==
4904 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4905 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4906 MLX5_FLOW_ACTION_SET_IPV6_DST;
4908 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4909 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4910 ret = flow_dv_validate_action_modify_tp(action_flags,
4916 /* Count all modify-header actions as one action. */
4917 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4919 action_flags |= actions->type ==
4920 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4921 MLX5_FLOW_ACTION_SET_TP_SRC :
4922 MLX5_FLOW_ACTION_SET_TP_DST;
4924 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4925 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4926 ret = flow_dv_validate_action_modify_ttl(action_flags,
4932 /* Count all modify-header actions as one action. */
4933 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4935 action_flags |= actions->type ==
4936 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4937 MLX5_FLOW_ACTION_SET_TTL :
4938 MLX5_FLOW_ACTION_DEC_TTL;
4940 case RTE_FLOW_ACTION_TYPE_JUMP:
4941 ret = flow_dv_validate_action_jump(actions,
4948 action_flags |= MLX5_FLOW_ACTION_JUMP;
4950 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4951 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4952 ret = flow_dv_validate_action_modify_tcp_seq
4959 /* Count all modify-header actions as one action. */
4960 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4962 action_flags |= actions->type ==
4963 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4964 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4965 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4967 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4968 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4969 ret = flow_dv_validate_action_modify_tcp_ack
4976 /* Count all modify-header actions as one action. */
4977 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4979 action_flags |= actions->type ==
4980 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4981 MLX5_FLOW_ACTION_INC_TCP_ACK :
4982 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4984 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4985 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
4986 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4988 case RTE_FLOW_ACTION_TYPE_METER:
4989 ret = mlx5_flow_validate_action_meter(dev,
4995 action_flags |= MLX5_FLOW_ACTION_METER;
4998 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
4999 ret = flow_dv_validate_action_modify_ipv4_dscp
5006 /* Count all modify-header actions as one action. */
5007 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5009 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5011 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5012 ret = flow_dv_validate_action_modify_ipv6_dscp
5019 /* Count all modify-header actions as one action. */
5020 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5022 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5025 return rte_flow_error_set(error, ENOTSUP,
5026 RTE_FLOW_ERROR_TYPE_ACTION,
5028 "action not supported");
5032 * Validate the drop action mutual exclusion with other actions.
5033 * Drop action is mutually-exclusive with any other action, except for
5036 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5037 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5038 return rte_flow_error_set(error, EINVAL,
5039 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5040 "Drop action is mutually-exclusive "
5041 "with any other action, except for "
5043 /* Eswitch has few restrictions on using items and actions */
5044 if (attr->transfer) {
5045 if (!mlx5_flow_ext_mreg_supported(dev) &&
5046 action_flags & MLX5_FLOW_ACTION_FLAG)
5047 return rte_flow_error_set(error, ENOTSUP,
5048 RTE_FLOW_ERROR_TYPE_ACTION,
5050 "unsupported action FLAG");
5051 if (!mlx5_flow_ext_mreg_supported(dev) &&
5052 action_flags & MLX5_FLOW_ACTION_MARK)
5053 return rte_flow_error_set(error, ENOTSUP,
5054 RTE_FLOW_ERROR_TYPE_ACTION,
5056 "unsupported action MARK");
5057 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5058 return rte_flow_error_set(error, ENOTSUP,
5059 RTE_FLOW_ERROR_TYPE_ACTION,
5061 "unsupported action QUEUE");
5062 if (action_flags & MLX5_FLOW_ACTION_RSS)
5063 return rte_flow_error_set(error, ENOTSUP,
5064 RTE_FLOW_ERROR_TYPE_ACTION,
5066 "unsupported action RSS");
5067 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5068 return rte_flow_error_set(error, EINVAL,
5069 RTE_FLOW_ERROR_TYPE_ACTION,
5071 "no fate action is found");
5073 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5074 return rte_flow_error_set(error, EINVAL,
5075 RTE_FLOW_ERROR_TYPE_ACTION,
5077 "no fate action is found");
5083 * Internal preparation function. Allocates the DV flow size,
5084 * this size is constant.
5087 * Pointer to the flow attributes.
5089 * Pointer to the list of items.
5090 * @param[in] actions
5091 * Pointer to the list of actions.
5093 * Pointer to the error structure.
5096 * Pointer to mlx5_flow object on success,
5097 * otherwise NULL and rte_errno is set.
5099 static struct mlx5_flow *
5100 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5101 const struct rte_flow_item items[] __rte_unused,
5102 const struct rte_flow_action actions[] __rte_unused,
5103 struct rte_flow_error *error)
5105 size_t size = sizeof(struct mlx5_flow);
5106 struct mlx5_flow *dev_flow;
5108 dev_flow = rte_calloc(__func__, 1, size, 0);
5110 rte_flow_error_set(error, ENOMEM,
5111 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5112 "not enough memory to create flow");
5115 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5116 dev_flow->ingress = attr->ingress;
5117 dev_flow->transfer = attr->transfer;
5121 #ifdef RTE_LIBRTE_MLX5_DEBUG
5123 * Sanity check for match mask and value. Similar to check_valid_spec() in
5124 * kernel driver. If unmasked bit is present in value, it returns failure.
5127 * pointer to match mask buffer.
5128 * @param match_value
5129 * pointer to match value buffer.
5132 * 0 if valid, -EINVAL otherwise.
5135 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5137 uint8_t *m = match_mask;
5138 uint8_t *v = match_value;
5141 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5144 "match_value differs from match_criteria"
5145 " %p[%u] != %p[%u]",
5146 match_value, i, match_mask, i);
5155 * Add Ethernet item to matcher and to the value.
5157 * @param[in, out] matcher
5159 * @param[in, out] key
5160 * Flow matcher value.
5162 * Flow pattern to translate.
5164 * Item is inner pattern.
5167 flow_dv_translate_item_eth(void *matcher, void *key,
5168 const struct rte_flow_item *item, int inner)
5170 const struct rte_flow_item_eth *eth_m = item->mask;
5171 const struct rte_flow_item_eth *eth_v = item->spec;
5172 const struct rte_flow_item_eth nic_mask = {
5173 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5174 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5175 .type = RTE_BE16(0xffff),
5187 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5189 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5191 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5193 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5195 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5196 ð_m->dst, sizeof(eth_m->dst));
5197 /* The value must be in the range of the mask. */
5198 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5199 for (i = 0; i < sizeof(eth_m->dst); ++i)
5200 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5201 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5202 ð_m->src, sizeof(eth_m->src));
5203 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5204 /* The value must be in the range of the mask. */
5205 for (i = 0; i < sizeof(eth_m->dst); ++i)
5206 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5207 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5208 rte_be_to_cpu_16(eth_m->type));
5209 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5210 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5214 * Add VLAN item to matcher and to the value.
5216 * @param[in, out] dev_flow
5218 * @param[in, out] matcher
5220 * @param[in, out] key
5221 * Flow matcher value.
5223 * Flow pattern to translate.
5225 * Item is inner pattern.
5228 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5229 void *matcher, void *key,
5230 const struct rte_flow_item *item,
5233 const struct rte_flow_item_vlan *vlan_m = item->mask;
5234 const struct rte_flow_item_vlan *vlan_v = item->spec;
5243 vlan_m = &rte_flow_item_vlan_mask;
5245 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5247 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5249 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5251 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5253 * This is workaround, masks are not supported,
5254 * and pre-validated.
5256 dev_flow->dv.vf_vlan.tag =
5257 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5259 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5260 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5261 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5262 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5263 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5264 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5265 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5266 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5267 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5268 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5269 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5270 rte_be_to_cpu_16(vlan_m->inner_type));
5271 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5272 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5276 * Add IPV4 item to matcher and to the value.
5278 * @param[in, out] matcher
5280 * @param[in, out] key
5281 * Flow matcher value.
5283 * Flow pattern to translate.
5285 * Item is inner pattern.
5287 * The group to insert the rule.
5290 flow_dv_translate_item_ipv4(void *matcher, void *key,
5291 const struct rte_flow_item *item,
5292 int inner, uint32_t group)
5294 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5295 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5296 const struct rte_flow_item_ipv4 nic_mask = {
5298 .src_addr = RTE_BE32(0xffffffff),
5299 .dst_addr = RTE_BE32(0xffffffff),
5300 .type_of_service = 0xff,
5301 .next_proto_id = 0xff,
5311 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5313 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5315 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5317 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5320 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5322 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5323 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5328 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5329 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5330 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5331 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5332 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5333 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5334 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5335 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5336 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5337 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5338 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5339 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5340 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5341 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5342 ipv4_m->hdr.type_of_service);
5343 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5344 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5345 ipv4_m->hdr.type_of_service >> 2);
5346 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5347 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5348 ipv4_m->hdr.next_proto_id);
5349 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5350 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5354 * Add IPV6 item to matcher and to the value.
5356 * @param[in, out] matcher
5358 * @param[in, out] key
5359 * Flow matcher value.
5361 * Flow pattern to translate.
5363 * Item is inner pattern.
5365 * The group to insert the rule.
5368 flow_dv_translate_item_ipv6(void *matcher, void *key,
5369 const struct rte_flow_item *item,
5370 int inner, uint32_t group)
5372 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5373 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5374 const struct rte_flow_item_ipv6 nic_mask = {
5377 "\xff\xff\xff\xff\xff\xff\xff\xff"
5378 "\xff\xff\xff\xff\xff\xff\xff\xff",
5380 "\xff\xff\xff\xff\xff\xff\xff\xff"
5381 "\xff\xff\xff\xff\xff\xff\xff\xff",
5382 .vtc_flow = RTE_BE32(0xffffffff),
5389 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5390 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5399 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5401 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5403 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5405 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5408 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5410 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5411 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5416 size = sizeof(ipv6_m->hdr.dst_addr);
5417 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5418 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5419 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5420 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5421 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5422 for (i = 0; i < size; ++i)
5423 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5424 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5425 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5426 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5427 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5428 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5429 for (i = 0; i < size; ++i)
5430 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5432 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5433 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5434 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5435 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5436 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5437 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5440 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5442 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5445 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5447 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5451 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5453 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5454 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5458 * Add TCP item to matcher and to the value.
5460 * @param[in, out] matcher
5462 * @param[in, out] key
5463 * Flow matcher value.
5465 * Flow pattern to translate.
5467 * Item is inner pattern.
5470 flow_dv_translate_item_tcp(void *matcher, void *key,
5471 const struct rte_flow_item *item,
5474 const struct rte_flow_item_tcp *tcp_m = item->mask;
5475 const struct rte_flow_item_tcp *tcp_v = item->spec;
5480 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5482 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5484 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5486 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5488 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5489 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5493 tcp_m = &rte_flow_item_tcp_mask;
5494 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5495 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5496 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5497 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5498 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5499 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5500 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5501 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5502 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5503 tcp_m->hdr.tcp_flags);
5504 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5505 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5509 * Add UDP item to matcher and to the value.
5511 * @param[in, out] matcher
5513 * @param[in, out] key
5514 * Flow matcher value.
5516 * Flow pattern to translate.
5518 * Item is inner pattern.
5521 flow_dv_translate_item_udp(void *matcher, void *key,
5522 const struct rte_flow_item *item,
5525 const struct rte_flow_item_udp *udp_m = item->mask;
5526 const struct rte_flow_item_udp *udp_v = item->spec;
5531 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5533 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5535 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5537 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5539 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5540 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5544 udp_m = &rte_flow_item_udp_mask;
5545 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5546 rte_be_to_cpu_16(udp_m->hdr.src_port));
5547 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5548 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5549 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5550 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5551 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5552 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5556 * Add GRE optional Key item to matcher and to the value.
5558 * @param[in, out] matcher
5560 * @param[in, out] key
5561 * Flow matcher value.
5563 * Flow pattern to translate.
5565 * Item is inner pattern.
5568 flow_dv_translate_item_gre_key(void *matcher, void *key,
5569 const struct rte_flow_item *item)
5571 const rte_be32_t *key_m = item->mask;
5572 const rte_be32_t *key_v = item->spec;
5573 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5574 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5575 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5580 key_m = &gre_key_default_mask;
5581 /* GRE K bit must be on and should already be validated */
5582 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5583 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5584 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5585 rte_be_to_cpu_32(*key_m) >> 8);
5586 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5587 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5588 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5589 rte_be_to_cpu_32(*key_m) & 0xFF);
5590 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5591 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5595 * Add GRE item to matcher and to the value.
5597 * @param[in, out] matcher
5599 * @param[in, out] key
5600 * Flow matcher value.
5602 * Flow pattern to translate.
5604 * Item is inner pattern.
5607 flow_dv_translate_item_gre(void *matcher, void *key,
5608 const struct rte_flow_item *item,
5611 const struct rte_flow_item_gre *gre_m = item->mask;
5612 const struct rte_flow_item_gre *gre_v = item->spec;
5615 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5616 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5623 uint16_t s_present:1;
5624 uint16_t k_present:1;
5625 uint16_t rsvd_bit1:1;
5626 uint16_t c_present:1;
5630 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5633 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5635 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5637 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5639 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5641 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5642 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5646 gre_m = &rte_flow_item_gre_mask;
5647 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5648 rte_be_to_cpu_16(gre_m->protocol));
5649 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5650 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5651 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5652 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5653 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5654 gre_crks_rsvd0_ver_m.c_present);
5655 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5656 gre_crks_rsvd0_ver_v.c_present &
5657 gre_crks_rsvd0_ver_m.c_present);
5658 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5659 gre_crks_rsvd0_ver_m.k_present);
5660 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5661 gre_crks_rsvd0_ver_v.k_present &
5662 gre_crks_rsvd0_ver_m.k_present);
5663 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5664 gre_crks_rsvd0_ver_m.s_present);
5665 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5666 gre_crks_rsvd0_ver_v.s_present &
5667 gre_crks_rsvd0_ver_m.s_present);
5671 * Add NVGRE item to matcher and to the value.
5673 * @param[in, out] matcher
5675 * @param[in, out] key
5676 * Flow matcher value.
5678 * Flow pattern to translate.
5680 * Item is inner pattern.
5683 flow_dv_translate_item_nvgre(void *matcher, void *key,
5684 const struct rte_flow_item *item,
5687 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5688 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5689 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5690 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5691 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5692 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5698 /* For NVGRE, GRE header fields must be set with defined values. */
5699 const struct rte_flow_item_gre gre_spec = {
5700 .c_rsvd0_ver = RTE_BE16(0x2000),
5701 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5703 const struct rte_flow_item_gre gre_mask = {
5704 .c_rsvd0_ver = RTE_BE16(0xB000),
5705 .protocol = RTE_BE16(UINT16_MAX),
5707 const struct rte_flow_item gre_item = {
5712 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5716 nvgre_m = &rte_flow_item_nvgre_mask;
5717 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5718 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5719 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5720 memcpy(gre_key_m, tni_flow_id_m, size);
5721 for (i = 0; i < size; ++i)
5722 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5726 * Add VXLAN item to matcher and to the value.
5728 * @param[in, out] matcher
5730 * @param[in, out] key
5731 * Flow matcher value.
5733 * Flow pattern to translate.
5735 * Item is inner pattern.
5738 flow_dv_translate_item_vxlan(void *matcher, void *key,
5739 const struct rte_flow_item *item,
5742 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5743 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5746 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5747 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5755 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5757 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5759 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5761 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5763 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5764 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5765 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5766 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5767 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5772 vxlan_m = &rte_flow_item_vxlan_mask;
5773 size = sizeof(vxlan_m->vni);
5774 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5775 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5776 memcpy(vni_m, vxlan_m->vni, size);
5777 for (i = 0; i < size; ++i)
5778 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5782 * Add VXLAN-GPE item to matcher and to the value.
5784 * @param[in, out] matcher
5786 * @param[in, out] key
5787 * Flow matcher value.
5789 * Flow pattern to translate.
5791 * Item is inner pattern.
5795 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
5796 const struct rte_flow_item *item, int inner)
5798 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
5799 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
5803 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
5805 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5811 uint8_t flags_m = 0xff;
5812 uint8_t flags_v = 0xc;
5815 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5817 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5819 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5821 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5823 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5824 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5825 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5826 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5827 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5832 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
5833 size = sizeof(vxlan_m->vni);
5834 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
5835 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
5836 memcpy(vni_m, vxlan_m->vni, size);
5837 for (i = 0; i < size; ++i)
5838 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5839 if (vxlan_m->flags) {
5840 flags_m = vxlan_m->flags;
5841 flags_v = vxlan_v->flags;
5843 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
5844 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
5845 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
5847 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
5852 * Add Geneve item to matcher and to the value.
5854 * @param[in, out] matcher
5856 * @param[in, out] key
5857 * Flow matcher value.
5859 * Flow pattern to translate.
5861 * Item is inner pattern.
5865 flow_dv_translate_item_geneve(void *matcher, void *key,
5866 const struct rte_flow_item *item, int inner)
5868 const struct rte_flow_item_geneve *geneve_m = item->mask;
5869 const struct rte_flow_item_geneve *geneve_v = item->spec;
5872 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5873 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5882 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5884 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5886 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5888 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5890 dport = MLX5_UDP_PORT_GENEVE;
5891 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5892 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5893 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5898 geneve_m = &rte_flow_item_geneve_mask;
5899 size = sizeof(geneve_m->vni);
5900 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5901 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5902 memcpy(vni_m, geneve_m->vni, size);
5903 for (i = 0; i < size; ++i)
5904 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5905 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5906 rte_be_to_cpu_16(geneve_m->protocol));
5907 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5908 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5909 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5910 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5911 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5912 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5913 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5914 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5915 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5916 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5917 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5918 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5919 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5923 * Add MPLS item to matcher and to the value.
5925 * @param[in, out] matcher
5927 * @param[in, out] key
5928 * Flow matcher value.
5930 * Flow pattern to translate.
5931 * @param[in] prev_layer
5932 * The protocol layer indicated in previous item.
5934 * Item is inner pattern.
5937 flow_dv_translate_item_mpls(void *matcher, void *key,
5938 const struct rte_flow_item *item,
5939 uint64_t prev_layer,
5942 const uint32_t *in_mpls_m = item->mask;
5943 const uint32_t *in_mpls_v = item->spec;
5944 uint32_t *out_mpls_m = 0;
5945 uint32_t *out_mpls_v = 0;
5946 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5947 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5948 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5950 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5951 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5952 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5954 switch (prev_layer) {
5955 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5956 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5957 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5958 MLX5_UDP_PORT_MPLS);
5960 case MLX5_FLOW_LAYER_GRE:
5961 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5962 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5963 RTE_ETHER_TYPE_MPLS);
5966 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5967 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5974 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5975 switch (prev_layer) {
5976 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5978 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5979 outer_first_mpls_over_udp);
5981 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5982 outer_first_mpls_over_udp);
5984 case MLX5_FLOW_LAYER_GRE:
5986 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5987 outer_first_mpls_over_gre);
5989 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5990 outer_first_mpls_over_gre);
5993 /* Inner MPLS not over GRE is not supported. */
5996 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6000 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6006 if (out_mpls_m && out_mpls_v) {
6007 *out_mpls_m = *in_mpls_m;
6008 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6013 * Add metadata register item to matcher
6015 * @param[in, out] matcher
6017 * @param[in, out] key
6018 * Flow matcher value.
6019 * @param[in] reg_type
6020 * Type of device metadata register
6027 flow_dv_match_meta_reg(void *matcher, void *key,
6028 enum modify_reg reg_type,
6029 uint32_t data, uint32_t mask)
6032 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6034 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6040 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6041 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6044 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6045 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6049 * The metadata register C0 field might be divided into
6050 * source vport index and META item value, we should set
6051 * this field according to specified mask, not as whole one.
6053 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6055 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6056 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6059 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6062 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6063 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6066 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6067 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6070 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6071 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6074 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6075 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6078 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6079 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6082 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6083 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6086 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6087 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6096 * Add MARK item to matcher
6099 * The device to configure through.
6100 * @param[in, out] matcher
6102 * @param[in, out] key
6103 * Flow matcher value.
6105 * Flow pattern to translate.
6108 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6109 void *matcher, void *key,
6110 const struct rte_flow_item *item)
6112 struct mlx5_priv *priv = dev->data->dev_private;
6113 const struct rte_flow_item_mark *mark;
6117 mark = item->mask ? (const void *)item->mask :
6118 &rte_flow_item_mark_mask;
6119 mask = mark->id & priv->sh->dv_mark_mask;
6120 mark = (const void *)item->spec;
6122 value = mark->id & priv->sh->dv_mark_mask & mask;
6124 enum modify_reg reg;
6126 /* Get the metadata register index for the mark. */
6127 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6128 MLX5_ASSERT(reg > 0);
6129 if (reg == REG_C_0) {
6130 struct mlx5_priv *priv = dev->data->dev_private;
6131 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6132 uint32_t shl_c0 = rte_bsf32(msk_c0);
6138 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6143 * Add META item to matcher
6146 * The devich to configure through.
6147 * @param[in, out] matcher
6149 * @param[in, out] key
6150 * Flow matcher value.
6152 * Attributes of flow that includes this item.
6154 * Flow pattern to translate.
6157 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6158 void *matcher, void *key,
6159 const struct rte_flow_attr *attr,
6160 const struct rte_flow_item *item)
6162 const struct rte_flow_item_meta *meta_m;
6163 const struct rte_flow_item_meta *meta_v;
6165 meta_m = (const void *)item->mask;
6167 meta_m = &rte_flow_item_meta_mask;
6168 meta_v = (const void *)item->spec;
6171 uint32_t value = meta_v->data;
6172 uint32_t mask = meta_m->data;
6174 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6178 * In datapath code there is no endianness
6179 * coversions for perfromance reasons, all
6180 * pattern conversions are done in rte_flow.
6182 value = rte_cpu_to_be_32(value);
6183 mask = rte_cpu_to_be_32(mask);
6184 if (reg == REG_C_0) {
6185 struct mlx5_priv *priv = dev->data->dev_private;
6186 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6187 uint32_t shl_c0 = rte_bsf32(msk_c0);
6188 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6189 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6196 MLX5_ASSERT(msk_c0);
6197 MLX5_ASSERT(!(~msk_c0 & mask));
6199 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6204 * Add vport metadata Reg C0 item to matcher
6206 * @param[in, out] matcher
6208 * @param[in, out] key
6209 * Flow matcher value.
6211 * Flow pattern to translate.
6214 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6215 uint32_t value, uint32_t mask)
6217 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6221 * Add tag item to matcher
6224 * The devich to configure through.
6225 * @param[in, out] matcher
6227 * @param[in, out] key
6228 * Flow matcher value.
6230 * Flow pattern to translate.
6233 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6234 void *matcher, void *key,
6235 const struct rte_flow_item *item)
6237 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6238 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6239 uint32_t mask, value;
6242 value = tag_v->data;
6243 mask = tag_m ? tag_m->data : UINT32_MAX;
6244 if (tag_v->id == REG_C_0) {
6245 struct mlx5_priv *priv = dev->data->dev_private;
6246 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6247 uint32_t shl_c0 = rte_bsf32(msk_c0);
6253 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6257 * Add TAG item to matcher
6260 * The devich to configure through.
6261 * @param[in, out] matcher
6263 * @param[in, out] key
6264 * Flow matcher value.
6266 * Flow pattern to translate.
6269 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6270 void *matcher, void *key,
6271 const struct rte_flow_item *item)
6273 const struct rte_flow_item_tag *tag_v = item->spec;
6274 const struct rte_flow_item_tag *tag_m = item->mask;
6275 enum modify_reg reg;
6278 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6279 /* Get the metadata register index for the tag. */
6280 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6281 MLX5_ASSERT(reg > 0);
6282 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6286 * Add source vport match to the specified matcher.
6288 * @param[in, out] matcher
6290 * @param[in, out] key
6291 * Flow matcher value.
6293 * Source vport value to match
6298 flow_dv_translate_item_source_vport(void *matcher, void *key,
6299 int16_t port, uint16_t mask)
6301 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6302 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6304 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6305 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6309 * Translate port-id item to eswitch match on port-id.
6312 * The devich to configure through.
6313 * @param[in, out] matcher
6315 * @param[in, out] key
6316 * Flow matcher value.
6318 * Flow pattern to translate.
6321 * 0 on success, a negative errno value otherwise.
6324 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6325 void *key, const struct rte_flow_item *item)
6327 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6328 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6329 struct mlx5_priv *priv;
6332 mask = pid_m ? pid_m->id : 0xffff;
6333 id = pid_v ? pid_v->id : dev->data->port_id;
6334 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6337 /* Translate to vport field or to metadata, depending on mode. */
6338 if (priv->vport_meta_mask)
6339 flow_dv_translate_item_meta_vport(matcher, key,
6340 priv->vport_meta_tag,
6341 priv->vport_meta_mask);
6343 flow_dv_translate_item_source_vport(matcher, key,
6344 priv->vport_id, mask);
6349 * Add ICMP6 item to matcher and to the value.
6351 * @param[in, out] matcher
6353 * @param[in, out] key
6354 * Flow matcher value.
6356 * Flow pattern to translate.
6358 * Item is inner pattern.
6361 flow_dv_translate_item_icmp6(void *matcher, void *key,
6362 const struct rte_flow_item *item,
6365 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6366 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6369 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6371 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6373 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6375 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6377 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6379 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6381 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6382 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6386 icmp6_m = &rte_flow_item_icmp6_mask;
6387 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6388 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6389 icmp6_v->type & icmp6_m->type);
6390 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6391 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6392 icmp6_v->code & icmp6_m->code);
6396 * Add ICMP item to matcher and to the value.
6398 * @param[in, out] matcher
6400 * @param[in, out] key
6401 * Flow matcher value.
6403 * Flow pattern to translate.
6405 * Item is inner pattern.
6408 flow_dv_translate_item_icmp(void *matcher, void *key,
6409 const struct rte_flow_item *item,
6412 const struct rte_flow_item_icmp *icmp_m = item->mask;
6413 const struct rte_flow_item_icmp *icmp_v = item->spec;
6416 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6418 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6420 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6422 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6424 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6426 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6428 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6429 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6433 icmp_m = &rte_flow_item_icmp_mask;
6434 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6435 icmp_m->hdr.icmp_type);
6436 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6437 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6438 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6439 icmp_m->hdr.icmp_code);
6440 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6441 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6445 * Add GTP item to matcher and to the value.
6447 * @param[in, out] matcher
6449 * @param[in, out] key
6450 * Flow matcher value.
6452 * Flow pattern to translate.
6454 * Item is inner pattern.
6457 flow_dv_translate_item_gtp(void *matcher, void *key,
6458 const struct rte_flow_item *item, int inner)
6460 const struct rte_flow_item_gtp *gtp_m = item->mask;
6461 const struct rte_flow_item_gtp *gtp_v = item->spec;
6464 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6466 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6467 uint16_t dport = RTE_GTPU_UDP_PORT;
6470 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6472 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6474 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6476 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6478 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6479 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6480 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6485 gtp_m = &rte_flow_item_gtp_mask;
6486 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6487 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6488 gtp_v->msg_type & gtp_m->msg_type);
6489 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6490 rte_be_to_cpu_32(gtp_m->teid));
6491 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6492 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6495 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6497 #define HEADER_IS_ZERO(match_criteria, headers) \
6498 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6499 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6502 * Calculate flow matcher enable bitmap.
6504 * @param match_criteria
6505 * Pointer to flow matcher criteria.
6508 * Bitmap of enabled fields.
6511 flow_dv_matcher_enable(uint32_t *match_criteria)
6513 uint8_t match_criteria_enable;
6515 match_criteria_enable =
6516 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6517 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6518 match_criteria_enable |=
6519 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6520 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6521 match_criteria_enable |=
6522 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6523 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6524 match_criteria_enable |=
6525 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6526 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6527 match_criteria_enable |=
6528 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6529 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6530 return match_criteria_enable;
6537 * @param[in, out] dev
6538 * Pointer to rte_eth_dev structure.
6539 * @param[in] table_id
6542 * Direction of the table.
6543 * @param[in] transfer
6544 * E-Switch or NIC flow.
6546 * pointer to error structure.
6549 * Returns tables resource based on the index, NULL in case of failed.
6551 static struct mlx5_flow_tbl_resource *
6552 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6553 uint32_t table_id, uint8_t egress,
6555 struct rte_flow_error *error)
6557 struct mlx5_priv *priv = dev->data->dev_private;
6558 struct mlx5_ibv_shared *sh = priv->sh;
6559 struct mlx5_flow_tbl_resource *tbl;
6560 union mlx5_flow_tbl_key table_key = {
6562 .table_id = table_id,
6564 .domain = !!transfer,
6565 .direction = !!egress,
6568 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6570 struct mlx5_flow_tbl_data_entry *tbl_data;
6575 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6577 tbl = &tbl_data->tbl;
6578 rte_atomic32_inc(&tbl->refcnt);
6581 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6583 rte_flow_error_set(error, ENOMEM,
6584 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6586 "cannot allocate flow table data entry");
6589 tbl = &tbl_data->tbl;
6590 pos = &tbl_data->entry;
6592 domain = sh->fdb_domain;
6594 domain = sh->tx_domain;
6596 domain = sh->rx_domain;
6597 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6599 rte_flow_error_set(error, ENOMEM,
6600 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6601 NULL, "cannot create flow table object");
6606 * No multi-threads now, but still better to initialize the reference
6607 * count before insert it into the hash list.
6609 rte_atomic32_init(&tbl->refcnt);
6610 /* Jump action reference count is initialized here. */
6611 rte_atomic32_init(&tbl_data->jump.refcnt);
6612 pos->key = table_key.v64;
6613 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6615 rte_flow_error_set(error, -ret,
6616 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6617 "cannot insert flow table data entry");
6618 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6621 rte_atomic32_inc(&tbl->refcnt);
6626 * Release a flow table.
6629 * Pointer to rte_eth_dev structure.
6631 * Table resource to be released.
6634 * Returns 0 if table was released, else return 1;
6637 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6638 struct mlx5_flow_tbl_resource *tbl)
6640 struct mlx5_priv *priv = dev->data->dev_private;
6641 struct mlx5_ibv_shared *sh = priv->sh;
6642 struct mlx5_flow_tbl_data_entry *tbl_data =
6643 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6647 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6648 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6650 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6652 /* remove the entry from the hash list and free memory. */
6653 mlx5_hlist_remove(sh->flow_tbls, pos);
6661 * Register the flow matcher.
6663 * @param[in, out] dev
6664 * Pointer to rte_eth_dev structure.
6665 * @param[in, out] matcher
6666 * Pointer to flow matcher.
6667 * @param[in, out] key
6668 * Pointer to flow table key.
6669 * @parm[in, out] dev_flow
6670 * Pointer to the dev_flow.
6672 * pointer to error structure.
6675 * 0 on success otherwise -errno and errno is set.
6678 flow_dv_matcher_register(struct rte_eth_dev *dev,
6679 struct mlx5_flow_dv_matcher *matcher,
6680 union mlx5_flow_tbl_key *key,
6681 struct mlx5_flow *dev_flow,
6682 struct rte_flow_error *error)
6684 struct mlx5_priv *priv = dev->data->dev_private;
6685 struct mlx5_ibv_shared *sh = priv->sh;
6686 struct mlx5_flow_dv_matcher *cache_matcher;
6687 struct mlx5dv_flow_matcher_attr dv_attr = {
6688 .type = IBV_FLOW_ATTR_NORMAL,
6689 .match_mask = (void *)&matcher->mask,
6691 struct mlx5_flow_tbl_resource *tbl;
6692 struct mlx5_flow_tbl_data_entry *tbl_data;
6694 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6695 key->domain, error);
6697 return -rte_errno; /* No need to refill the error info */
6698 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6699 /* Lookup from cache. */
6700 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6701 if (matcher->crc == cache_matcher->crc &&
6702 matcher->priority == cache_matcher->priority &&
6703 !memcmp((const void *)matcher->mask.buf,
6704 (const void *)cache_matcher->mask.buf,
6705 cache_matcher->mask.size)) {
6707 "%s group %u priority %hd use %s "
6708 "matcher %p: refcnt %d++",
6709 key->domain ? "FDB" : "NIC", key->table_id,
6710 cache_matcher->priority,
6711 key->direction ? "tx" : "rx",
6712 (void *)cache_matcher,
6713 rte_atomic32_read(&cache_matcher->refcnt));
6714 rte_atomic32_inc(&cache_matcher->refcnt);
6715 dev_flow->dv.matcher = cache_matcher;
6716 /* old matcher should not make the table ref++. */
6717 flow_dv_tbl_resource_release(dev, tbl);
6721 /* Register new matcher. */
6722 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6723 if (!cache_matcher) {
6724 flow_dv_tbl_resource_release(dev, tbl);
6725 return rte_flow_error_set(error, ENOMEM,
6726 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6727 "cannot allocate matcher memory");
6729 *cache_matcher = *matcher;
6730 dv_attr.match_criteria_enable =
6731 flow_dv_matcher_enable(cache_matcher->mask.buf);
6732 dv_attr.priority = matcher->priority;
6734 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6735 cache_matcher->matcher_object =
6736 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6737 if (!cache_matcher->matcher_object) {
6738 rte_free(cache_matcher);
6739 #ifdef HAVE_MLX5DV_DR
6740 flow_dv_tbl_resource_release(dev, tbl);
6742 return rte_flow_error_set(error, ENOMEM,
6743 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6744 NULL, "cannot create matcher");
6746 /* Save the table information */
6747 cache_matcher->tbl = tbl;
6748 rte_atomic32_init(&cache_matcher->refcnt);
6749 /* only matcher ref++, table ref++ already done above in get API. */
6750 rte_atomic32_inc(&cache_matcher->refcnt);
6751 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6752 dev_flow->dv.matcher = cache_matcher;
6753 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6754 key->domain ? "FDB" : "NIC", key->table_id,
6755 cache_matcher->priority,
6756 key->direction ? "tx" : "rx", (void *)cache_matcher,
6757 rte_atomic32_read(&cache_matcher->refcnt));
6762 * Find existing tag resource or create and register a new one.
6764 * @param dev[in, out]
6765 * Pointer to rte_eth_dev structure.
6766 * @param[in, out] tag_be24
6767 * Tag value in big endian then R-shift 8.
6768 * @parm[in, out] dev_flow
6769 * Pointer to the dev_flow.
6771 * pointer to error structure.
6774 * 0 on success otherwise -errno and errno is set.
6777 flow_dv_tag_resource_register
6778 (struct rte_eth_dev *dev,
6780 struct mlx5_flow *dev_flow,
6781 struct rte_flow_error *error)
6783 struct mlx5_priv *priv = dev->data->dev_private;
6784 struct mlx5_ibv_shared *sh = priv->sh;
6785 struct mlx5_flow_dv_tag_resource *cache_resource;
6786 struct mlx5_hlist_entry *entry;
6788 /* Lookup a matching resource from cache. */
6789 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6791 cache_resource = container_of
6792 (entry, struct mlx5_flow_dv_tag_resource, entry);
6793 rte_atomic32_inc(&cache_resource->refcnt);
6794 dev_flow->dv.tag_resource = cache_resource;
6795 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6796 (void *)cache_resource,
6797 rte_atomic32_read(&cache_resource->refcnt));
6800 /* Register new resource. */
6801 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6802 if (!cache_resource)
6803 return rte_flow_error_set(error, ENOMEM,
6804 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6805 "cannot allocate resource memory");
6806 cache_resource->entry.key = (uint64_t)tag_be24;
6807 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6808 if (!cache_resource->action) {
6809 rte_free(cache_resource);
6810 return rte_flow_error_set(error, ENOMEM,
6811 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6812 NULL, "cannot create action");
6814 rte_atomic32_init(&cache_resource->refcnt);
6815 rte_atomic32_inc(&cache_resource->refcnt);
6816 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6817 mlx5_glue->destroy_flow_action(cache_resource->action);
6818 rte_free(cache_resource);
6819 return rte_flow_error_set(error, EEXIST,
6820 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6821 NULL, "cannot insert tag");
6823 dev_flow->dv.tag_resource = cache_resource;
6824 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6825 (void *)cache_resource,
6826 rte_atomic32_read(&cache_resource->refcnt));
6834 * Pointer to Ethernet device.
6836 * Pointer to mlx5_flow.
6839 * 1 while a reference on it exists, 0 when freed.
6842 flow_dv_tag_release(struct rte_eth_dev *dev,
6843 struct mlx5_flow_dv_tag_resource *tag)
6845 struct mlx5_priv *priv = dev->data->dev_private;
6846 struct mlx5_ibv_shared *sh = priv->sh;
6849 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6850 dev->data->port_id, (void *)tag,
6851 rte_atomic32_read(&tag->refcnt));
6852 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6853 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6854 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6855 DRV_LOG(DEBUG, "port %u tag %p: removed",
6856 dev->data->port_id, (void *)tag);
6864 * Translate port ID action to vport.
6867 * Pointer to rte_eth_dev structure.
6869 * Pointer to the port ID action.
6870 * @param[out] dst_port_id
6871 * The target port ID.
6873 * Pointer to the error structure.
6876 * 0 on success, a negative errno value otherwise and rte_errno is set.
6879 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6880 const struct rte_flow_action *action,
6881 uint32_t *dst_port_id,
6882 struct rte_flow_error *error)
6885 struct mlx5_priv *priv;
6886 const struct rte_flow_action_port_id *conf =
6887 (const struct rte_flow_action_port_id *)action->conf;
6889 port = conf->original ? dev->data->port_id : conf->id;
6890 priv = mlx5_port_to_eswitch_info(port, false);
6892 return rte_flow_error_set(error, -rte_errno,
6893 RTE_FLOW_ERROR_TYPE_ACTION,
6895 "No eswitch info was found for port");
6896 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6898 * This parameter is transferred to
6899 * mlx5dv_dr_action_create_dest_ib_port().
6901 *dst_port_id = priv->ibv_port;
6904 * Legacy mode, no LAG configurations is supported.
6905 * This parameter is transferred to
6906 * mlx5dv_dr_action_create_dest_vport().
6908 *dst_port_id = priv->vport_id;
6914 * Add Tx queue matcher
6917 * Pointer to the dev struct.
6918 * @param[in, out] matcher
6920 * @param[in, out] key
6921 * Flow matcher value.
6923 * Flow pattern to translate.
6925 * Item is inner pattern.
6928 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6929 void *matcher, void *key,
6930 const struct rte_flow_item *item)
6932 const struct mlx5_rte_flow_item_tx_queue *queue_m;
6933 const struct mlx5_rte_flow_item_tx_queue *queue_v;
6935 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6937 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6938 struct mlx5_txq_ctrl *txq;
6942 queue_m = (const void *)item->mask;
6945 queue_v = (const void *)item->spec;
6948 txq = mlx5_txq_get(dev, queue_v->queue);
6951 queue = txq->obj->sq->id;
6952 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6953 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6954 queue & queue_m->queue);
6955 mlx5_txq_release(dev, queue_v->queue);
6959 * Set the hash fields according to the @p flow information.
6961 * @param[in] dev_flow
6962 * Pointer to the mlx5_flow.
6965 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
6967 struct rte_flow *flow = dev_flow->flow;
6968 uint64_t items = dev_flow->layers;
6970 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
6972 dev_flow->hash_fields = 0;
6973 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
6974 if (flow->rss.level >= 2) {
6975 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
6979 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
6980 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
6981 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
6982 if (rss_types & ETH_RSS_L3_SRC_ONLY)
6983 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
6984 else if (rss_types & ETH_RSS_L3_DST_ONLY)
6985 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
6987 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
6989 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
6990 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
6991 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
6992 if (rss_types & ETH_RSS_L3_SRC_ONLY)
6993 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
6994 else if (rss_types & ETH_RSS_L3_DST_ONLY)
6995 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
6997 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7000 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7001 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7002 if (rss_types & ETH_RSS_UDP) {
7003 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7004 dev_flow->hash_fields |=
7005 IBV_RX_HASH_SRC_PORT_UDP;
7006 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7007 dev_flow->hash_fields |=
7008 IBV_RX_HASH_DST_PORT_UDP;
7010 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7012 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7013 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7014 if (rss_types & ETH_RSS_TCP) {
7015 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7016 dev_flow->hash_fields |=
7017 IBV_RX_HASH_SRC_PORT_TCP;
7018 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7019 dev_flow->hash_fields |=
7020 IBV_RX_HASH_DST_PORT_TCP;
7022 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7028 * Fill the flow with DV spec, lock free
7029 * (mutex should be acquired by caller).
7032 * Pointer to rte_eth_dev structure.
7033 * @param[in, out] dev_flow
7034 * Pointer to the sub flow.
7036 * Pointer to the flow attributes.
7038 * Pointer to the list of items.
7039 * @param[in] actions
7040 * Pointer to the list of actions.
7042 * Pointer to the error structure.
7045 * 0 on success, a negative errno value otherwise and rte_errno is set.
7048 __flow_dv_translate(struct rte_eth_dev *dev,
7049 struct mlx5_flow *dev_flow,
7050 const struct rte_flow_attr *attr,
7051 const struct rte_flow_item items[],
7052 const struct rte_flow_action actions[],
7053 struct rte_flow_error *error)
7055 struct mlx5_priv *priv = dev->data->dev_private;
7056 struct mlx5_dev_config *dev_conf = &priv->config;
7057 struct rte_flow *flow = dev_flow->flow;
7058 uint64_t item_flags = 0;
7059 uint64_t last_item = 0;
7060 uint64_t action_flags = 0;
7061 uint64_t priority = attr->priority;
7062 struct mlx5_flow_dv_matcher matcher = {
7064 .size = sizeof(matcher.mask.buf),
7068 bool actions_end = false;
7070 struct mlx5_flow_dv_modify_hdr_resource res;
7071 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7072 sizeof(struct mlx5_modification_cmd) *
7073 (MLX5_MAX_MODIFY_NUM + 1)];
7075 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7076 union flow_dv_attr flow_attr = { .attr = 0 };
7078 union mlx5_flow_tbl_key tbl_key;
7079 uint32_t modify_action_position = UINT32_MAX;
7080 void *match_mask = matcher.mask.buf;
7081 void *match_value = dev_flow->dv.value.buf;
7082 uint8_t next_protocol = 0xff;
7083 struct rte_vlan_hdr vlan = { 0 };
7087 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7088 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7089 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7090 !!priv->fdb_def_rule, &table, error);
7093 dev_flow->group = table;
7095 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7096 if (priority == MLX5_FLOW_PRIO_RSVD)
7097 priority = dev_conf->flow_prio - 1;
7098 /* number of actions must be set to 0 in case of dirty stack. */
7099 mhdr_res->actions_num = 0;
7100 for (; !actions_end ; actions++) {
7101 const struct rte_flow_action_queue *queue;
7102 const struct rte_flow_action_rss *rss;
7103 const struct rte_flow_action *action = actions;
7104 const struct rte_flow_action_count *count = action->conf;
7105 const uint8_t *rss_key;
7106 const struct rte_flow_action_jump *jump_data;
7107 const struct rte_flow_action_meter *mtr;
7108 struct mlx5_flow_tbl_resource *tbl;
7109 uint32_t port_id = 0;
7110 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7111 int action_type = actions->type;
7112 const struct rte_flow_action *found_action = NULL;
7114 switch (action_type) {
7115 case RTE_FLOW_ACTION_TYPE_VOID:
7117 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7118 if (flow_dv_translate_action_port_id(dev, action,
7121 port_id_resource.port_id = port_id;
7122 if (flow_dv_port_id_action_resource_register
7123 (dev, &port_id_resource, dev_flow, error))
7125 dev_flow->dv.actions[actions_n++] =
7126 dev_flow->dv.port_id_action->action;
7127 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7129 case RTE_FLOW_ACTION_TYPE_FLAG:
7130 action_flags |= MLX5_FLOW_ACTION_FLAG;
7131 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7132 struct rte_flow_action_mark mark = {
7133 .id = MLX5_FLOW_MARK_DEFAULT,
7136 if (flow_dv_convert_action_mark(dev, &mark,
7140 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7143 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7144 if (!dev_flow->dv.tag_resource)
7145 if (flow_dv_tag_resource_register
7146 (dev, tag_be, dev_flow, error))
7148 dev_flow->dv.actions[actions_n++] =
7149 dev_flow->dv.tag_resource->action;
7151 case RTE_FLOW_ACTION_TYPE_MARK:
7152 action_flags |= MLX5_FLOW_ACTION_MARK;
7153 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7154 const struct rte_flow_action_mark *mark =
7155 (const struct rte_flow_action_mark *)
7158 if (flow_dv_convert_action_mark(dev, mark,
7162 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7166 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7167 /* Legacy (non-extensive) MARK action. */
7168 tag_be = mlx5_flow_mark_set
7169 (((const struct rte_flow_action_mark *)
7170 (actions->conf))->id);
7171 if (!dev_flow->dv.tag_resource)
7172 if (flow_dv_tag_resource_register
7173 (dev, tag_be, dev_flow, error))
7175 dev_flow->dv.actions[actions_n++] =
7176 dev_flow->dv.tag_resource->action;
7178 case RTE_FLOW_ACTION_TYPE_SET_META:
7179 if (flow_dv_convert_action_set_meta
7180 (dev, mhdr_res, attr,
7181 (const struct rte_flow_action_set_meta *)
7182 actions->conf, error))
7184 action_flags |= MLX5_FLOW_ACTION_SET_META;
7186 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7187 if (flow_dv_convert_action_set_tag
7189 (const struct rte_flow_action_set_tag *)
7190 actions->conf, error))
7192 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7194 case RTE_FLOW_ACTION_TYPE_DROP:
7195 action_flags |= MLX5_FLOW_ACTION_DROP;
7197 case RTE_FLOW_ACTION_TYPE_QUEUE:
7198 MLX5_ASSERT(flow->rss.queue);
7199 queue = actions->conf;
7200 flow->rss.queue_num = 1;
7201 (*flow->rss.queue)[0] = queue->index;
7202 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7204 case RTE_FLOW_ACTION_TYPE_RSS:
7205 MLX5_ASSERT(flow->rss.queue);
7206 rss = actions->conf;
7207 if (flow->rss.queue)
7208 memcpy((*flow->rss.queue), rss->queue,
7209 rss->queue_num * sizeof(uint16_t));
7210 flow->rss.queue_num = rss->queue_num;
7211 /* NULL RSS key indicates default RSS key. */
7212 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7213 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7215 * rss->level and rss.types should be set in advance
7216 * when expanding items for RSS.
7218 action_flags |= MLX5_FLOW_ACTION_RSS;
7220 case RTE_FLOW_ACTION_TYPE_COUNT:
7221 if (!dev_conf->devx) {
7222 rte_errno = ENOTSUP;
7225 flow->counter = flow_dv_counter_alloc(dev,
7229 if (flow->counter == NULL)
7231 dev_flow->dv.actions[actions_n++] =
7232 flow->counter->action;
7233 action_flags |= MLX5_FLOW_ACTION_COUNT;
7236 if (rte_errno == ENOTSUP)
7237 return rte_flow_error_set
7239 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7241 "count action not supported");
7243 return rte_flow_error_set
7245 RTE_FLOW_ERROR_TYPE_ACTION,
7247 "cannot create counter"
7250 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7251 dev_flow->dv.actions[actions_n++] =
7252 priv->sh->pop_vlan_action;
7253 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7255 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7256 flow_dev_get_vlan_info_from_items(items, &vlan);
7257 vlan.eth_proto = rte_be_to_cpu_16
7258 ((((const struct rte_flow_action_of_push_vlan *)
7259 actions->conf)->ethertype));
7260 found_action = mlx5_flow_find_action
7262 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7264 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7265 found_action = mlx5_flow_find_action
7267 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7269 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7270 if (flow_dv_create_action_push_vlan
7271 (dev, attr, &vlan, dev_flow, error))
7273 dev_flow->dv.actions[actions_n++] =
7274 dev_flow->dv.push_vlan_res->action;
7275 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7277 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7278 /* of_vlan_push action handled this action */
7279 MLX5_ASSERT(action_flags &
7280 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7282 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7283 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7285 flow_dev_get_vlan_info_from_items(items, &vlan);
7286 mlx5_update_vlan_vid_pcp(actions, &vlan);
7287 /* If no VLAN push - this is a modify header action */
7288 if (flow_dv_convert_action_modify_vlan_vid
7289 (mhdr_res, actions, error))
7291 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7293 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7294 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7295 if (flow_dv_create_action_l2_encap(dev, actions,
7300 dev_flow->dv.actions[actions_n++] =
7301 dev_flow->dv.encap_decap->verbs_action;
7302 action_flags |= actions->type ==
7303 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
7304 MLX5_FLOW_ACTION_VXLAN_ENCAP :
7305 MLX5_FLOW_ACTION_NVGRE_ENCAP;
7307 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7308 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7309 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7313 dev_flow->dv.actions[actions_n++] =
7314 dev_flow->dv.encap_decap->verbs_action;
7315 action_flags |= actions->type ==
7316 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7317 MLX5_FLOW_ACTION_VXLAN_DECAP :
7318 MLX5_FLOW_ACTION_NVGRE_DECAP;
7320 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7321 /* Handle encap with preceding decap. */
7322 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
7323 if (flow_dv_create_action_raw_encap
7324 (dev, actions, dev_flow, attr, error))
7326 dev_flow->dv.actions[actions_n++] =
7327 dev_flow->dv.encap_decap->verbs_action;
7329 /* Handle encap without preceding decap. */
7330 if (flow_dv_create_action_l2_encap
7331 (dev, actions, dev_flow, attr->transfer,
7334 dev_flow->dv.actions[actions_n++] =
7335 dev_flow->dv.encap_decap->verbs_action;
7337 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
7339 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7340 /* Check if this decap is followed by encap. */
7341 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
7342 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
7345 /* Handle decap only if it isn't followed by encap. */
7346 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7347 if (flow_dv_create_action_l2_decap
7348 (dev, dev_flow, attr->transfer, error))
7350 dev_flow->dv.actions[actions_n++] =
7351 dev_flow->dv.encap_decap->verbs_action;
7353 /* If decap is followed by encap, handle it at encap. */
7354 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
7356 case RTE_FLOW_ACTION_TYPE_JUMP:
7357 jump_data = action->conf;
7358 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7360 !!priv->fdb_def_rule,
7364 tbl = flow_dv_tbl_resource_get(dev, table,
7366 attr->transfer, error);
7368 return rte_flow_error_set
7370 RTE_FLOW_ERROR_TYPE_ACTION,
7372 "cannot create jump action.");
7373 if (flow_dv_jump_tbl_resource_register
7374 (dev, tbl, dev_flow, error)) {
7375 flow_dv_tbl_resource_release(dev, tbl);
7376 return rte_flow_error_set
7378 RTE_FLOW_ERROR_TYPE_ACTION,
7380 "cannot create jump action.");
7382 dev_flow->dv.actions[actions_n++] =
7383 dev_flow->dv.jump->action;
7384 action_flags |= MLX5_FLOW_ACTION_JUMP;
7386 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7387 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7388 if (flow_dv_convert_action_modify_mac
7389 (mhdr_res, actions, error))
7391 action_flags |= actions->type ==
7392 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7393 MLX5_FLOW_ACTION_SET_MAC_SRC :
7394 MLX5_FLOW_ACTION_SET_MAC_DST;
7396 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7397 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7398 if (flow_dv_convert_action_modify_ipv4
7399 (mhdr_res, actions, error))
7401 action_flags |= actions->type ==
7402 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7403 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7404 MLX5_FLOW_ACTION_SET_IPV4_DST;
7406 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7407 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7408 if (flow_dv_convert_action_modify_ipv6
7409 (mhdr_res, actions, error))
7411 action_flags |= actions->type ==
7412 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7413 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7414 MLX5_FLOW_ACTION_SET_IPV6_DST;
7416 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7417 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7418 if (flow_dv_convert_action_modify_tp
7419 (mhdr_res, actions, items,
7422 action_flags |= actions->type ==
7423 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7424 MLX5_FLOW_ACTION_SET_TP_SRC :
7425 MLX5_FLOW_ACTION_SET_TP_DST;
7427 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7428 if (flow_dv_convert_action_modify_dec_ttl
7429 (mhdr_res, items, &flow_attr, error))
7431 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7433 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7434 if (flow_dv_convert_action_modify_ttl
7435 (mhdr_res, actions, items,
7438 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7440 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7441 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7442 if (flow_dv_convert_action_modify_tcp_seq
7443 (mhdr_res, actions, error))
7445 action_flags |= actions->type ==
7446 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7447 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7448 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7451 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7452 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7453 if (flow_dv_convert_action_modify_tcp_ack
7454 (mhdr_res, actions, error))
7456 action_flags |= actions->type ==
7457 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7458 MLX5_FLOW_ACTION_INC_TCP_ACK :
7459 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7461 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7462 if (flow_dv_convert_action_set_reg
7463 (mhdr_res, actions, error))
7465 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7467 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7468 if (flow_dv_convert_action_copy_mreg
7469 (dev, mhdr_res, actions, error))
7471 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7473 case RTE_FLOW_ACTION_TYPE_METER:
7474 mtr = actions->conf;
7476 flow->meter = mlx5_flow_meter_attach(priv,
7480 return rte_flow_error_set(error,
7482 RTE_FLOW_ERROR_TYPE_ACTION,
7485 "or invalid parameters");
7487 /* Set the meter action. */
7488 dev_flow->dv.actions[actions_n++] =
7489 flow->meter->mfts->meter_action;
7490 action_flags |= MLX5_FLOW_ACTION_METER;
7492 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7493 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7496 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7498 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7499 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7502 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7504 case RTE_FLOW_ACTION_TYPE_END:
7506 if (mhdr_res->actions_num) {
7507 /* create modify action if needed. */
7508 if (flow_dv_modify_hdr_resource_register
7509 (dev, mhdr_res, dev_flow, error))
7511 dev_flow->dv.actions[modify_action_position] =
7512 dev_flow->dv.modify_hdr->verbs_action;
7518 if (mhdr_res->actions_num &&
7519 modify_action_position == UINT32_MAX)
7520 modify_action_position = actions_n++;
7522 dev_flow->dv.actions_n = actions_n;
7523 dev_flow->actions = action_flags;
7524 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7525 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7526 int item_type = items->type;
7528 switch (item_type) {
7529 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7530 flow_dv_translate_item_port_id(dev, match_mask,
7531 match_value, items);
7532 last_item = MLX5_FLOW_ITEM_PORT_ID;
7534 case RTE_FLOW_ITEM_TYPE_ETH:
7535 flow_dv_translate_item_eth(match_mask, match_value,
7537 matcher.priority = MLX5_PRIORITY_MAP_L2;
7538 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7539 MLX5_FLOW_LAYER_OUTER_L2;
7541 case RTE_FLOW_ITEM_TYPE_VLAN:
7542 flow_dv_translate_item_vlan(dev_flow,
7543 match_mask, match_value,
7545 matcher.priority = MLX5_PRIORITY_MAP_L2;
7546 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7547 MLX5_FLOW_LAYER_INNER_VLAN) :
7548 (MLX5_FLOW_LAYER_OUTER_L2 |
7549 MLX5_FLOW_LAYER_OUTER_VLAN);
7551 case RTE_FLOW_ITEM_TYPE_IPV4:
7552 mlx5_flow_tunnel_ip_check(items, next_protocol,
7553 &item_flags, &tunnel);
7554 flow_dv_translate_item_ipv4(match_mask, match_value,
7557 matcher.priority = MLX5_PRIORITY_MAP_L3;
7558 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7559 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7560 if (items->mask != NULL &&
7561 ((const struct rte_flow_item_ipv4 *)
7562 items->mask)->hdr.next_proto_id) {
7564 ((const struct rte_flow_item_ipv4 *)
7565 (items->spec))->hdr.next_proto_id;
7567 ((const struct rte_flow_item_ipv4 *)
7568 (items->mask))->hdr.next_proto_id;
7570 /* Reset for inner layer. */
7571 next_protocol = 0xff;
7574 case RTE_FLOW_ITEM_TYPE_IPV6:
7575 mlx5_flow_tunnel_ip_check(items, next_protocol,
7576 &item_flags, &tunnel);
7577 flow_dv_translate_item_ipv6(match_mask, match_value,
7580 matcher.priority = MLX5_PRIORITY_MAP_L3;
7581 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7582 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7583 if (items->mask != NULL &&
7584 ((const struct rte_flow_item_ipv6 *)
7585 items->mask)->hdr.proto) {
7587 ((const struct rte_flow_item_ipv6 *)
7588 items->spec)->hdr.proto;
7590 ((const struct rte_flow_item_ipv6 *)
7591 items->mask)->hdr.proto;
7593 /* Reset for inner layer. */
7594 next_protocol = 0xff;
7597 case RTE_FLOW_ITEM_TYPE_TCP:
7598 flow_dv_translate_item_tcp(match_mask, match_value,
7600 matcher.priority = MLX5_PRIORITY_MAP_L4;
7601 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7602 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7604 case RTE_FLOW_ITEM_TYPE_UDP:
7605 flow_dv_translate_item_udp(match_mask, match_value,
7607 matcher.priority = MLX5_PRIORITY_MAP_L4;
7608 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7609 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7611 case RTE_FLOW_ITEM_TYPE_GRE:
7612 flow_dv_translate_item_gre(match_mask, match_value,
7614 last_item = MLX5_FLOW_LAYER_GRE;
7616 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7617 flow_dv_translate_item_gre_key(match_mask,
7618 match_value, items);
7619 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7621 case RTE_FLOW_ITEM_TYPE_NVGRE:
7622 flow_dv_translate_item_nvgre(match_mask, match_value,
7624 last_item = MLX5_FLOW_LAYER_GRE;
7626 case RTE_FLOW_ITEM_TYPE_VXLAN:
7627 flow_dv_translate_item_vxlan(match_mask, match_value,
7629 last_item = MLX5_FLOW_LAYER_VXLAN;
7631 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7632 flow_dv_translate_item_vxlan_gpe(match_mask,
7635 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7637 case RTE_FLOW_ITEM_TYPE_GENEVE:
7638 flow_dv_translate_item_geneve(match_mask, match_value,
7640 last_item = MLX5_FLOW_LAYER_GENEVE;
7642 case RTE_FLOW_ITEM_TYPE_MPLS:
7643 flow_dv_translate_item_mpls(match_mask, match_value,
7644 items, last_item, tunnel);
7645 last_item = MLX5_FLOW_LAYER_MPLS;
7647 case RTE_FLOW_ITEM_TYPE_MARK:
7648 flow_dv_translate_item_mark(dev, match_mask,
7649 match_value, items);
7650 last_item = MLX5_FLOW_ITEM_MARK;
7652 case RTE_FLOW_ITEM_TYPE_META:
7653 flow_dv_translate_item_meta(dev, match_mask,
7654 match_value, attr, items);
7655 last_item = MLX5_FLOW_ITEM_METADATA;
7657 case RTE_FLOW_ITEM_TYPE_ICMP:
7658 flow_dv_translate_item_icmp(match_mask, match_value,
7660 last_item = MLX5_FLOW_LAYER_ICMP;
7662 case RTE_FLOW_ITEM_TYPE_ICMP6:
7663 flow_dv_translate_item_icmp6(match_mask, match_value,
7665 last_item = MLX5_FLOW_LAYER_ICMP6;
7667 case RTE_FLOW_ITEM_TYPE_TAG:
7668 flow_dv_translate_item_tag(dev, match_mask,
7669 match_value, items);
7670 last_item = MLX5_FLOW_ITEM_TAG;
7672 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7673 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7674 match_value, items);
7675 last_item = MLX5_FLOW_ITEM_TAG;
7677 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7678 flow_dv_translate_item_tx_queue(dev, match_mask,
7681 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7683 case RTE_FLOW_ITEM_TYPE_GTP:
7684 flow_dv_translate_item_gtp(match_mask, match_value,
7686 last_item = MLX5_FLOW_LAYER_GTP;
7691 item_flags |= last_item;
7694 * When E-Switch mode is enabled, we have two cases where we need to
7695 * set the source port manually.
7696 * The first one, is in case of Nic steering rule, and the second is
7697 * E-Switch rule where no port_id item was found. In both cases
7698 * the source port is set according the current port in use.
7700 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7701 (priv->representor || priv->master)) {
7702 if (flow_dv_translate_item_port_id(dev, match_mask,
7706 #ifdef RTE_LIBRTE_MLX5_DEBUG
7707 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
7708 dev_flow->dv.value.buf));
7710 dev_flow->layers = item_flags;
7711 if (action_flags & MLX5_FLOW_ACTION_RSS)
7712 flow_dv_hashfields_set(dev_flow);
7713 /* Register matcher. */
7714 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7716 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7718 /* reserved field no needs to be set to 0 here. */
7719 tbl_key.domain = attr->transfer;
7720 tbl_key.direction = attr->egress;
7721 tbl_key.table_id = dev_flow->group;
7722 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7728 * Apply the flow to the NIC, lock free,
7729 * (mutex should be acquired by caller).
7732 * Pointer to the Ethernet device structure.
7733 * @param[in, out] flow
7734 * Pointer to flow structure.
7736 * Pointer to error structure.
7739 * 0 on success, a negative errno value otherwise and rte_errno is set.
7742 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7743 struct rte_flow_error *error)
7745 struct mlx5_flow_dv *dv;
7746 struct mlx5_flow *dev_flow;
7747 struct mlx5_priv *priv = dev->data->dev_private;
7751 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7754 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7755 if (dev_flow->transfer) {
7756 dv->actions[n++] = priv->sh->esw_drop_action;
7758 dv->hrxq = mlx5_hrxq_drop_new(dev);
7762 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7764 "cannot get drop hash queue");
7767 dv->actions[n++] = dv->hrxq->action;
7769 } else if (dev_flow->actions &
7770 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7771 struct mlx5_hrxq *hrxq;
7773 MLX5_ASSERT(flow->rss.queue);
7774 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7775 MLX5_RSS_HASH_KEY_LEN,
7776 dev_flow->hash_fields,
7778 flow->rss.queue_num);
7780 hrxq = mlx5_hrxq_new
7781 (dev, flow->rss.key,
7782 MLX5_RSS_HASH_KEY_LEN,
7783 dev_flow->hash_fields,
7785 flow->rss.queue_num,
7786 !!(dev_flow->layers &
7787 MLX5_FLOW_LAYER_TUNNEL));
7792 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7793 "cannot get hash queue");
7797 dv->actions[n++] = dv->hrxq->action;
7800 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7801 (void *)&dv->value, n,
7804 rte_flow_error_set(error, errno,
7805 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7807 "hardware refuses to create flow");
7810 if (priv->vmwa_context &&
7811 dev_flow->dv.vf_vlan.tag &&
7812 !dev_flow->dv.vf_vlan.created) {
7814 * The rule contains the VLAN pattern.
7815 * For VF we are going to create VLAN
7816 * interface to make hypervisor set correct
7817 * e-Switch vport context.
7819 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7824 err = rte_errno; /* Save rte_errno before cleanup. */
7825 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7826 struct mlx5_flow_dv *dv = &dev_flow->dv;
7828 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7829 mlx5_hrxq_drop_release(dev);
7831 mlx5_hrxq_release(dev, dv->hrxq);
7834 if (dev_flow->dv.vf_vlan.tag &&
7835 dev_flow->dv.vf_vlan.created)
7836 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7838 rte_errno = err; /* Restore rte_errno. */
7843 * Release the flow matcher.
7846 * Pointer to Ethernet device.
7848 * Pointer to mlx5_flow.
7851 * 1 while a reference on it exists, 0 when freed.
7854 flow_dv_matcher_release(struct rte_eth_dev *dev,
7855 struct mlx5_flow *flow)
7857 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7859 MLX5_ASSERT(matcher->matcher_object);
7860 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7861 dev->data->port_id, (void *)matcher,
7862 rte_atomic32_read(&matcher->refcnt));
7863 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7864 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7865 (matcher->matcher_object));
7866 LIST_REMOVE(matcher, next);
7867 /* table ref-- in release interface. */
7868 flow_dv_tbl_resource_release(dev, matcher->tbl);
7870 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7871 dev->data->port_id, (void *)matcher);
7878 * Release an encap/decap resource.
7881 * Pointer to mlx5_flow.
7884 * 1 while a reference on it exists, 0 when freed.
7887 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7889 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7890 flow->dv.encap_decap;
7892 MLX5_ASSERT(cache_resource->verbs_action);
7893 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7894 (void *)cache_resource,
7895 rte_atomic32_read(&cache_resource->refcnt));
7896 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7897 claim_zero(mlx5_glue->destroy_flow_action
7898 (cache_resource->verbs_action));
7899 LIST_REMOVE(cache_resource, next);
7900 rte_free(cache_resource);
7901 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7902 (void *)cache_resource);
7909 * Release an jump to table action resource.
7912 * Pointer to Ethernet device.
7914 * Pointer to mlx5_flow.
7917 * 1 while a reference on it exists, 0 when freed.
7920 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
7921 struct mlx5_flow *flow)
7923 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
7924 struct mlx5_flow_tbl_data_entry *tbl_data =
7925 container_of(cache_resource,
7926 struct mlx5_flow_tbl_data_entry, jump);
7928 MLX5_ASSERT(cache_resource->action);
7929 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7930 (void *)cache_resource,
7931 rte_atomic32_read(&cache_resource->refcnt));
7932 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7933 claim_zero(mlx5_glue->destroy_flow_action
7934 (cache_resource->action));
7935 /* jump action memory free is inside the table release. */
7936 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
7937 DRV_LOG(DEBUG, "jump table resource %p: removed",
7938 (void *)cache_resource);
7945 * Release a modify-header resource.
7948 * Pointer to mlx5_flow.
7951 * 1 while a reference on it exists, 0 when freed.
7954 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7956 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7957 flow->dv.modify_hdr;
7959 MLX5_ASSERT(cache_resource->verbs_action);
7960 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7961 (void *)cache_resource,
7962 rte_atomic32_read(&cache_resource->refcnt));
7963 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7964 claim_zero(mlx5_glue->destroy_flow_action
7965 (cache_resource->verbs_action));
7966 LIST_REMOVE(cache_resource, next);
7967 rte_free(cache_resource);
7968 DRV_LOG(DEBUG, "modify-header resource %p: removed",
7969 (void *)cache_resource);
7976 * Release port ID action resource.
7979 * Pointer to mlx5_flow.
7982 * 1 while a reference on it exists, 0 when freed.
7985 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
7987 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
7988 flow->dv.port_id_action;
7990 MLX5_ASSERT(cache_resource->action);
7991 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
7992 (void *)cache_resource,
7993 rte_atomic32_read(&cache_resource->refcnt));
7994 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7995 claim_zero(mlx5_glue->destroy_flow_action
7996 (cache_resource->action));
7997 LIST_REMOVE(cache_resource, next);
7998 rte_free(cache_resource);
7999 DRV_LOG(DEBUG, "port id action resource %p: removed",
8000 (void *)cache_resource);
8007 * Release push vlan action resource.
8010 * Pointer to mlx5_flow.
8013 * 1 while a reference on it exists, 0 when freed.
8016 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
8018 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8019 flow->dv.push_vlan_res;
8021 MLX5_ASSERT(cache_resource->action);
8022 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8023 (void *)cache_resource,
8024 rte_atomic32_read(&cache_resource->refcnt));
8025 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8026 claim_zero(mlx5_glue->destroy_flow_action
8027 (cache_resource->action));
8028 LIST_REMOVE(cache_resource, next);
8029 rte_free(cache_resource);
8030 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8031 (void *)cache_resource);
8038 * Remove the flow from the NIC but keeps it in memory.
8039 * Lock free, (mutex should be acquired by caller).
8042 * Pointer to Ethernet device.
8043 * @param[in, out] flow
8044 * Pointer to flow structure.
8047 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8049 struct mlx5_flow_dv *dv;
8050 struct mlx5_flow *dev_flow;
8054 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
8057 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
8061 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
8062 mlx5_hrxq_drop_release(dev);
8064 mlx5_hrxq_release(dev, dv->hrxq);
8067 if (dev_flow->dv.vf_vlan.tag &&
8068 dev_flow->dv.vf_vlan.created)
8069 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
8074 * Remove the flow from the NIC and the memory.
8075 * Lock free, (mutex should be acquired by caller).
8078 * Pointer to the Ethernet device structure.
8079 * @param[in, out] flow
8080 * Pointer to flow structure.
8083 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8085 struct mlx5_flow *dev_flow;
8089 __flow_dv_remove(dev, flow);
8090 if (flow->counter) {
8091 flow_dv_counter_release(dev, flow->counter);
8092 flow->counter = NULL;
8095 mlx5_flow_meter_detach(flow->meter);
8098 while (!LIST_EMPTY(&flow->dev_flows)) {
8099 dev_flow = LIST_FIRST(&flow->dev_flows);
8100 LIST_REMOVE(dev_flow, next);
8101 if (dev_flow->dv.matcher)
8102 flow_dv_matcher_release(dev, dev_flow);
8103 if (dev_flow->dv.encap_decap)
8104 flow_dv_encap_decap_resource_release(dev_flow);
8105 if (dev_flow->dv.modify_hdr)
8106 flow_dv_modify_hdr_resource_release(dev_flow);
8107 if (dev_flow->dv.jump)
8108 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8109 if (dev_flow->dv.port_id_action)
8110 flow_dv_port_id_action_resource_release(dev_flow);
8111 if (dev_flow->dv.push_vlan_res)
8112 flow_dv_push_vlan_action_resource_release(dev_flow);
8113 if (dev_flow->dv.tag_resource)
8114 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8120 * Query a dv flow rule for its statistics via devx.
8123 * Pointer to Ethernet device.
8125 * Pointer to the sub flow.
8127 * data retrieved by the query.
8129 * Perform verbose error reporting if not NULL.
8132 * 0 on success, a negative errno value otherwise and rte_errno is set.
8135 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8136 void *data, struct rte_flow_error *error)
8138 struct mlx5_priv *priv = dev->data->dev_private;
8139 struct rte_flow_query_count *qc = data;
8141 if (!priv->config.devx)
8142 return rte_flow_error_set(error, ENOTSUP,
8143 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8145 "counters are not supported");
8146 if (flow->counter) {
8147 uint64_t pkts, bytes;
8148 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8152 return rte_flow_error_set(error, -err,
8153 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8154 NULL, "cannot read counters");
8157 qc->hits = pkts - flow->counter->hits;
8158 qc->bytes = bytes - flow->counter->bytes;
8160 flow->counter->hits = pkts;
8161 flow->counter->bytes = bytes;
8165 return rte_flow_error_set(error, EINVAL,
8166 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8168 "counters are not available");
8174 * @see rte_flow_query()
8178 flow_dv_query(struct rte_eth_dev *dev,
8179 struct rte_flow *flow __rte_unused,
8180 const struct rte_flow_action *actions __rte_unused,
8181 void *data __rte_unused,
8182 struct rte_flow_error *error __rte_unused)
8186 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8187 switch (actions->type) {
8188 case RTE_FLOW_ACTION_TYPE_VOID:
8190 case RTE_FLOW_ACTION_TYPE_COUNT:
8191 ret = flow_dv_query_count(dev, flow, data, error);
8194 return rte_flow_error_set(error, ENOTSUP,
8195 RTE_FLOW_ERROR_TYPE_ACTION,
8197 "action not supported");
8204 * Destroy the meter table set.
8205 * Lock free, (mutex should be acquired by caller).
8208 * Pointer to Ethernet device.
8210 * Pointer to the meter table set.
8216 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8217 struct mlx5_meter_domains_infos *tbl)
8219 struct mlx5_priv *priv = dev->data->dev_private;
8220 struct mlx5_meter_domains_infos *mtd =
8221 (struct mlx5_meter_domains_infos *)tbl;
8223 if (!mtd || !priv->config.dv_flow_en)
8225 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8226 claim_zero(mlx5_glue->dv_destroy_flow
8227 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8228 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8229 claim_zero(mlx5_glue->dv_destroy_flow
8230 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8231 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8232 claim_zero(mlx5_glue->dv_destroy_flow
8233 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8234 if (mtd->egress.color_matcher)
8235 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8236 (mtd->egress.color_matcher));
8237 if (mtd->egress.any_matcher)
8238 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8239 (mtd->egress.any_matcher));
8240 if (mtd->egress.tbl)
8241 claim_zero(flow_dv_tbl_resource_release(dev,
8243 if (mtd->ingress.color_matcher)
8244 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8245 (mtd->ingress.color_matcher));
8246 if (mtd->ingress.any_matcher)
8247 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8248 (mtd->ingress.any_matcher));
8249 if (mtd->ingress.tbl)
8250 claim_zero(flow_dv_tbl_resource_release(dev,
8252 if (mtd->transfer.color_matcher)
8253 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8254 (mtd->transfer.color_matcher));
8255 if (mtd->transfer.any_matcher)
8256 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8257 (mtd->transfer.any_matcher));
8258 if (mtd->transfer.tbl)
8259 claim_zero(flow_dv_tbl_resource_release(dev,
8260 mtd->transfer.tbl));
8262 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8267 /* Number of meter flow actions, count and jump or count and drop. */
8268 #define METER_ACTIONS 2
8271 * Create specify domain meter table and suffix table.
8274 * Pointer to Ethernet device.
8275 * @param[in,out] mtb
8276 * Pointer to DV meter table set.
8279 * @param[in] transfer
8281 * @param[in] color_reg_c_idx
8282 * Reg C index for color match.
8285 * 0 on success, -1 otherwise and rte_errno is set.
8288 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8289 struct mlx5_meter_domains_infos *mtb,
8290 uint8_t egress, uint8_t transfer,
8291 uint32_t color_reg_c_idx)
8293 struct mlx5_priv *priv = dev->data->dev_private;
8294 struct mlx5_ibv_shared *sh = priv->sh;
8295 struct mlx5_flow_dv_match_params mask = {
8296 .size = sizeof(mask.buf),
8298 struct mlx5_flow_dv_match_params value = {
8299 .size = sizeof(value.buf),
8301 struct mlx5dv_flow_matcher_attr dv_attr = {
8302 .type = IBV_FLOW_ATTR_NORMAL,
8304 .match_criteria_enable = 0,
8305 .match_mask = (void *)&mask,
8307 void *actions[METER_ACTIONS];
8308 struct mlx5_flow_tbl_resource **sfx_tbl;
8309 struct mlx5_meter_domain_info *dtb;
8310 struct rte_flow_error error;
8314 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8315 dtb = &mtb->transfer;
8316 } else if (egress) {
8317 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8320 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8321 dtb = &mtb->ingress;
8323 /* If the suffix table in missing, create it. */
8325 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8326 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8327 egress, transfer, &error);
8329 DRV_LOG(ERR, "Failed to create meter suffix table.");
8333 /* Create the meter table with METER level. */
8334 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8335 egress, transfer, &error);
8337 DRV_LOG(ERR, "Failed to create meter policer table.");
8340 /* Create matchers, Any and Color. */
8341 dv_attr.priority = 3;
8342 dv_attr.match_criteria_enable = 0;
8343 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8346 if (!dtb->any_matcher) {
8347 DRV_LOG(ERR, "Failed to create meter"
8348 " policer default matcher.");
8351 dv_attr.priority = 0;
8352 dv_attr.match_criteria_enable =
8353 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8354 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8355 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8356 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8359 if (!dtb->color_matcher) {
8360 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8363 if (mtb->count_actns[RTE_MTR_DROPPED])
8364 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8365 actions[i++] = mtb->drop_actn;
8366 /* Default rule: lowest priority, match any, actions: drop. */
8367 dtb->policer_rules[RTE_MTR_DROPPED] =
8368 mlx5_glue->dv_create_flow(dtb->any_matcher,
8369 (void *)&value, i, actions);
8370 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8371 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8380 * Create the needed meter and suffix tables.
8381 * Lock free, (mutex should be acquired by caller).
8384 * Pointer to Ethernet device.
8386 * Pointer to the flow meter.
8389 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8391 static struct mlx5_meter_domains_infos *
8392 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8393 const struct mlx5_flow_meter *fm)
8395 struct mlx5_priv *priv = dev->data->dev_private;
8396 struct mlx5_meter_domains_infos *mtb;
8400 if (!priv->mtr_en) {
8401 rte_errno = ENOTSUP;
8404 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8406 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8409 /* Create meter count actions */
8410 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8411 if (!fm->policer_stats.cnt[i])
8413 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8415 /* Create drop action. */
8416 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8417 if (!mtb->drop_actn) {
8418 DRV_LOG(ERR, "Failed to create drop action.");
8421 /* Egress meter table. */
8422 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8424 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8427 /* Ingress meter table. */
8428 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8430 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8433 /* FDB meter table. */
8434 if (priv->config.dv_esw_en) {
8435 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8436 priv->mtr_color_reg);
8438 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8444 flow_dv_destroy_mtr_tbl(dev, mtb);
8449 * Destroy domain policer rule.
8452 * Pointer to domain table.
8455 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8459 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8460 if (dt->policer_rules[i]) {
8461 claim_zero(mlx5_glue->dv_destroy_flow
8462 (dt->policer_rules[i]));
8463 dt->policer_rules[i] = NULL;
8466 if (dt->jump_actn) {
8467 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8468 dt->jump_actn = NULL;
8473 * Destroy policer rules.
8476 * Pointer to Ethernet device.
8478 * Pointer to flow meter structure.
8480 * Pointer to flow attributes.
8486 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8487 const struct mlx5_flow_meter *fm,
8488 const struct rte_flow_attr *attr)
8490 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8495 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8497 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8499 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8504 * Create specify domain meter policer rule.
8507 * Pointer to flow meter structure.
8509 * Pointer to DV meter table set.
8511 * Pointer to suffix table.
8512 * @param[in] mtr_reg_c
8513 * Color match REG_C.
8516 * 0 on success, -1 otherwise.
8519 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8520 struct mlx5_meter_domain_info *dtb,
8521 struct mlx5_flow_tbl_resource *sfx_tb,
8524 struct mlx5_flow_dv_match_params matcher = {
8525 .size = sizeof(matcher.buf),
8527 struct mlx5_flow_dv_match_params value = {
8528 .size = sizeof(value.buf),
8530 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8531 void *actions[METER_ACTIONS];
8534 /* Create jump action. */
8537 if (!dtb->jump_actn)
8539 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8541 if (!dtb->jump_actn) {
8542 DRV_LOG(ERR, "Failed to create policer jump action.");
8545 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8548 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8549 rte_col_2_mlx5_col(i), UINT8_MAX);
8550 if (mtb->count_actns[i])
8551 actions[j++] = mtb->count_actns[i];
8552 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8553 actions[j++] = mtb->drop_actn;
8555 actions[j++] = dtb->jump_actn;
8556 dtb->policer_rules[i] =
8557 mlx5_glue->dv_create_flow(dtb->color_matcher,
8560 if (!dtb->policer_rules[i]) {
8561 DRV_LOG(ERR, "Failed to create policer rule.");
8572 * Create policer rules.
8575 * Pointer to Ethernet device.
8577 * Pointer to flow meter structure.
8579 * Pointer to flow attributes.
8582 * 0 on success, -1 otherwise.
8585 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8586 struct mlx5_flow_meter *fm,
8587 const struct rte_flow_attr *attr)
8589 struct mlx5_priv *priv = dev->data->dev_private;
8590 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8594 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8595 priv->sh->tx_mtr_sfx_tbl,
8596 priv->mtr_color_reg);
8598 DRV_LOG(ERR, "Failed to create egress policer.");
8602 if (attr->ingress) {
8603 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8604 priv->sh->rx_mtr_sfx_tbl,
8605 priv->mtr_color_reg);
8607 DRV_LOG(ERR, "Failed to create ingress policer.");
8611 if (attr->transfer) {
8612 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8613 priv->sh->fdb_mtr_sfx_tbl,
8614 priv->mtr_color_reg);
8616 DRV_LOG(ERR, "Failed to create transfer policer.");
8622 flow_dv_destroy_policer_rules(dev, fm, attr);
8627 * Query a devx counter.
8630 * Pointer to the Ethernet device structure.
8632 * Pointer to the flow counter.
8634 * Set to clear the counter statistics.
8636 * The statistics value of packets.
8638 * The statistics value of bytes.
8641 * 0 on success, otherwise return -1.
8644 flow_dv_counter_query(struct rte_eth_dev *dev,
8645 struct mlx5_flow_counter *cnt, bool clear,
8646 uint64_t *pkts, uint64_t *bytes)
8648 struct mlx5_priv *priv = dev->data->dev_private;
8649 uint64_t inn_pkts, inn_bytes;
8652 if (!priv->config.devx)
8654 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8657 *pkts = inn_pkts - cnt->hits;
8658 *bytes = inn_bytes - cnt->bytes;
8660 cnt->hits = inn_pkts;
8661 cnt->bytes = inn_bytes;
8667 * Mutex-protected thunk to lock-free __flow_dv_translate().
8670 flow_dv_translate(struct rte_eth_dev *dev,
8671 struct mlx5_flow *dev_flow,
8672 const struct rte_flow_attr *attr,
8673 const struct rte_flow_item items[],
8674 const struct rte_flow_action actions[],
8675 struct rte_flow_error *error)
8679 flow_dv_shared_lock(dev);
8680 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8681 flow_dv_shared_unlock(dev);
8686 * Mutex-protected thunk to lock-free __flow_dv_apply().
8689 flow_dv_apply(struct rte_eth_dev *dev,
8690 struct rte_flow *flow,
8691 struct rte_flow_error *error)
8695 flow_dv_shared_lock(dev);
8696 ret = __flow_dv_apply(dev, flow, error);
8697 flow_dv_shared_unlock(dev);
8702 * Mutex-protected thunk to lock-free __flow_dv_remove().
8705 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8707 flow_dv_shared_lock(dev);
8708 __flow_dv_remove(dev, flow);
8709 flow_dv_shared_unlock(dev);
8713 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8716 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8718 flow_dv_shared_lock(dev);
8719 __flow_dv_destroy(dev, flow);
8720 flow_dv_shared_unlock(dev);
8724 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8726 static struct mlx5_flow_counter *
8727 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8729 struct mlx5_flow_counter *cnt;
8731 flow_dv_shared_lock(dev);
8732 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8733 flow_dv_shared_unlock(dev);
8738 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8741 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8743 flow_dv_shared_lock(dev);
8744 flow_dv_counter_release(dev, cnt);
8745 flow_dv_shared_unlock(dev);
8748 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8749 .validate = flow_dv_validate,
8750 .prepare = flow_dv_prepare,
8751 .translate = flow_dv_translate,
8752 .apply = flow_dv_apply,
8753 .remove = flow_dv_remove,
8754 .destroy = flow_dv_destroy,
8755 .query = flow_dv_query,
8756 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8757 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8758 .create_policer_rules = flow_dv_create_policer_rules,
8759 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8760 .counter_alloc = flow_dv_counter_allocate,
8761 .counter_free = flow_dv_counter_free,
8762 .counter_query = flow_dv_counter_query,
8765 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */