drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                       uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84
  85 /**
  86  * Initialize flow attributes structure according to flow items' types.
  87  *
  88  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  89  * mode. For tunnel mode, the items to be modified are the outermost ones.
  90  *
  91  * @param[in] item
  92  *   Pointer to item specification.
  93  * @param[out] attr
  94  *   Pointer to flow attributes structure.
  95  * @param[in] dev_flow
  96  *   Pointer to the sub flow.
  97  * @param[in] tunnel_decap
  98  *   Whether action is after tunnel decapsulation.
  99  */
 100 static void
 101 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 102                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 103 {
 104         uint64_t layers = dev_flow->handle->layers;
 105
 106         /*
 107          * If layers is already initialized, it means this dev_flow is the
 108          * suffix flow, the layers flags is set by the prefix flow. Need to
 109          * use the layer flags from prefix flow as the suffix flow may not
 110          * have the user defined items as the flow is split.
 111          */
 112         if (layers) {
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 114                         attr->ipv4 = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 116                         attr->ipv6 = 1;
 117                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 118                         attr->tcp = 1;
 119                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 120                         attr->udp = 1;
 121                 attr->valid = 1;
 122                 return;
 123         }
 124         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 125                 uint8_t next_protocol = 0xff;
 126                 switch (item->type) {
 127                 case RTE_FLOW_ITEM_TYPE_GRE:
 128                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 129                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 130                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 131                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 132                 case RTE_FLOW_ITEM_TYPE_MPLS:
 133                         if (tunnel_decap)
 134                                 attr->attr = 0;
 135                         break;
 136                 case RTE_FLOW_ITEM_TYPE_IPV4:
 137                         if (!attr->ipv6)
 138                                 attr->ipv4 = 1;
 139                         if (item->mask != NULL &&
 140                             ((const struct rte_flow_item_ipv4 *)
 141                             item->mask)->hdr.next_proto_id)
 142                                 next_protocol =
 143                                     ((const struct rte_flow_item_ipv4 *)
 144                                       (item->spec))->hdr.next_proto_id &
 145                                     ((const struct rte_flow_item_ipv4 *)
 146                                       (item->mask))->hdr.next_proto_id;
 147                         if ((next_protocol == IPPROTO_IPIP ||
 148                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 149                                 attr->attr = 0;
 150                         break;
 151                 case RTE_FLOW_ITEM_TYPE_IPV6:
 152                         if (!attr->ipv4)
 153                                 attr->ipv6 = 1;
 154                         if (item->mask != NULL &&
 155                             ((const struct rte_flow_item_ipv6 *)
 156                             item->mask)->hdr.proto)
 157                                 next_protocol =
 158                                     ((const struct rte_flow_item_ipv6 *)
 159                                       (item->spec))->hdr.proto &
 160                                     ((const struct rte_flow_item_ipv6 *)
 161                                       (item->mask))->hdr.proto;
 162                         if ((next_protocol == IPPROTO_IPIP ||
 163                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 164                                 attr->attr = 0;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_UDP:
 167                         if (!attr->tcp)
 168                                 attr->udp = 1;
 169                         break;
 170                 case RTE_FLOW_ITEM_TYPE_TCP:
 171                         if (!attr->udp)
 172                                 attr->tcp = 1;
 173                         break;
 174                 default:
 175                         break;
 176                 }
 177         }
 178         attr->valid = 1;
 179 }
 180
 181 /**
 182  * Convert rte_mtr_color to mlx5 color.
 183  *
 184  * @param[in] rcol
 185  *   rte_mtr_color.
 186  *
 187  * @return
 188  *   mlx5 color.
 189  */
 190 static int
 191 rte_col_2_mlx5_col(enum rte_color rcol)
 192 {
 193         switch (rcol) {
 194         case RTE_COLOR_GREEN:
 195                 return MLX5_FLOW_COLOR_GREEN;
 196         case RTE_COLOR_YELLOW:
 197                 return MLX5_FLOW_COLOR_YELLOW;
 198         case RTE_COLOR_RED:
 199                 return MLX5_FLOW_COLOR_RED;
 200         default:
 201                 break;
 202         }
 203         return MLX5_FLOW_COLOR_UNDEFINED;
 204 }
 205
 206 struct field_modify_info {
 207         uint32_t size; /* Size of field in protocol header, in bytes. */
 208         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 209         enum mlx5_modification_field id;
 210 };
 211
 212 struct field_modify_info modify_eth[] = {
 213         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 214         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 215         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 216         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 217         {0, 0, 0},
 218 };
 219
 220 struct field_modify_info modify_vlan_out_first_vid[] = {
 221         /* Size in bits !!! */
 222         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_ipv4[] = {
 227         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 228         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 229         {4, 12, MLX5_MODI_OUT_SIPV4},
 230         {4, 16, MLX5_MODI_OUT_DIPV4},
 231         {0, 0, 0},
 232 };
 233
 234 struct field_modify_info modify_ipv6[] = {
 235         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 236         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 237         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 238         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 239         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 240         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 241         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 242         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 243         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 244         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 245         {0, 0, 0},
 246 };
 247
 248 struct field_modify_info modify_udp[] = {
 249         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 250         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_tcp[] = {
 255         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 257         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 258         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 259         {0, 0, 0},
 260 };
 261
 262 static void
 263 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 264                           uint8_t next_protocol, uint64_t *item_flags,
 265                           int *tunnel)
 266 {
 267         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 268                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 269         if (next_protocol == IPPROTO_IPIP) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 271                 *tunnel = 1;
 272         }
 273         if (next_protocol == IPPROTO_IPV6) {
 274                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 275                 *tunnel = 1;
 276         }
 277 }
 278
 279 /**
 280  * Acquire the synchronizing object to protect multithreaded access
 281  * to shared dv context. Lock occurs only if context is actually
 282  * shared, i.e. we have multiport IB device and representors are
 283  * created.
 284  *
 285  * @param[in] dev
 286  *   Pointer to the rte_eth_dev structure.
 287  */
 288 static void
 289 flow_dv_shared_lock(struct rte_eth_dev *dev)
 290 {
 291         struct mlx5_priv *priv = dev->data->dev_private;
 292         struct mlx5_dev_ctx_shared *sh = priv->sh;
 293
 294         if (sh->refcnt > 1) {
 295                 int ret;
 296
 297                 ret = pthread_mutex_lock(&sh->dv_mutex);
 298                 MLX5_ASSERT(!ret);
 299                 (void)ret;
 300         }
 301 }
 302
 303 static void
 304 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 305 {
 306         struct mlx5_priv *priv = dev->data->dev_private;
 307         struct mlx5_dev_ctx_shared *sh = priv->sh;
 308
 309         if (sh->refcnt > 1) {
 310                 int ret;
 311
 312                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 313                 MLX5_ASSERT(!ret);
 314                 (void)ret;
 315         }
 316 }
 317
 318 /* Update VLAN's VID/PCP based on input rte_flow_action.
 319  *
 320  * @param[in] action
 321  *   Pointer to struct rte_flow_action.
 322  * @param[out] vlan
 323  *   Pointer to struct rte_vlan_hdr.
 324  */
 325 static void
 326 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 327                          struct rte_vlan_hdr *vlan)
 328 {
 329         uint16_t vlan_tci;
 330         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 331                 vlan_tci =
 332                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 333                                                action->conf)->vlan_pcp;
 334                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 335                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 336                 vlan->vlan_tci |= vlan_tci;
 337         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 338                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 339                 vlan->vlan_tci |= rte_be_to_cpu_16
 340                     (((const struct rte_flow_action_of_set_vlan_vid *)
 341                                              action->conf)->vlan_vid);
 342         }
 343 }
 344
 345 /**
 346  * Fetch 1, 2, 3 or 4 byte field from the byte array
 347  * and return as unsigned integer in host-endian format.
 348  *
 349  * @param[in] data
 350  *   Pointer to data array.
 351  * @param[in] size
 352  *   Size of field to extract.
 353  *
 354  * @return
 355  *   converted field in host endian format.
 356  */
 357 static inline uint32_t
 358 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 359 {
 360         uint32_t ret;
 361
 362         switch (size) {
 363         case 1:
 364                 ret = *data;
 365                 break;
 366         case 2:
 367                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 368                 break;
 369         case 3:
 370                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 371                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 372                 break;
 373         case 4:
 374                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 375                 break;
 376         default:
 377                 MLX5_ASSERT(false);
 378                 ret = 0;
 379                 break;
 380         }
 381         return ret;
 382 }
 383
 384 /**
 385  * Convert modify-header action to DV specification.
 386  *
 387  * Data length of each action is determined by provided field description
 388  * and the item mask. Data bit offset and width of each action is determined
 389  * by provided item mask.
 390  *
 391  * @param[in] item
 392  *   Pointer to item specification.
 393  * @param[in] field
 394  *   Pointer to field modification information.
 395  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 396  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 397  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 398  * @param[in] dcopy
 399  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 400  *   Negative offset value sets the same offset as source offset.
 401  *   size field is ignored, value is taken from source field.
 402  * @param[in,out] resource
 403  *   Pointer to the modify-header resource.
 404  * @param[in] type
 405  *   Type of modification.
 406  * @param[out] error
 407  *   Pointer to the error structure.
 408  *
 409  * @return
 410  *   0 on success, a negative errno value otherwise and rte_errno is set.
 411  */
 412 static int
 413 flow_dv_convert_modify_action(struct rte_flow_item *item,
 414                               struct field_modify_info *field,
 415                               struct field_modify_info *dcopy,
 416                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 417                               uint32_t type, struct rte_flow_error *error)
 418 {
 419         uint32_t i = resource->actions_num;
 420         struct mlx5_modification_cmd *actions = resource->actions;
 421
 422         /*
 423          * The item and mask are provided in big-endian format.
 424          * The fields should be presented as in big-endian format either.
 425          * Mask must be always present, it defines the actual field width.
 426          */
 427         MLX5_ASSERT(item->mask);
 428         MLX5_ASSERT(field->size);
 429         do {
 430                 unsigned int size_b;
 431                 unsigned int off_b;
 432                 uint32_t mask;
 433                 uint32_t data;
 434
 435                 if (i >= MLX5_MAX_MODIFY_NUM)
 436                         return rte_flow_error_set(error, EINVAL,
 437                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 438                                  "too many items to modify");
 439                 /* Fetch variable byte size mask from the array. */
 440                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 441                                            field->offset, field->size);
 442                 if (!mask) {
 443                         ++field;
 444                         continue;
 445                 }
 446                 /* Deduce actual data width in bits from mask value. */
 447                 off_b = rte_bsf32(mask);
 448                 size_b = sizeof(uint32_t) * CHAR_BIT -
 449                          off_b - __builtin_clz(mask);
 450                 MLX5_ASSERT(size_b);
 451                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 452                 actions[i] = (struct mlx5_modification_cmd) {
 453                         .action_type = type,
 454                         .field = field->id,
 455                         .offset = off_b,
 456                         .length = size_b,
 457                 };
 458                 /* Convert entire record to expected big-endian format. */
 459                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 460                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 461                         MLX5_ASSERT(dcopy);
 462                         actions[i].dst_field = dcopy->id;
 463                         actions[i].dst_offset =
 464                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 465                         /* Convert entire record to big-endian format. */
 466                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 467                 } else {
 468                         MLX5_ASSERT(item->spec);
 469                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 470                                                    field->offset, field->size);
 471                         /* Shift out the trailing masked bits from data. */
 472                         data = (data & mask) >> off_b;
 473                         actions[i].data1 = rte_cpu_to_be_32(data);
 474                 }
 475                 ++i;
 476                 ++field;
 477         } while (field->size);
 478         if (resource->actions_num == i)
 479                 return rte_flow_error_set(error, EINVAL,
 480                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 481                                           "invalid modification flow item");
 482         resource->actions_num = i;
 483         return 0;
 484 }
 485
 486 /**
 487  * Convert modify-header set IPv4 address action to DV specification.
 488  *
 489  * @param[in,out] resource
 490  *   Pointer to the modify-header resource.
 491  * @param[in] action
 492  *   Pointer to action specification.
 493  * @param[out] error
 494  *   Pointer to the error structure.
 495  *
 496  * @return
 497  *   0 on success, a negative errno value otherwise and rte_errno is set.
 498  */
 499 static int
 500 flow_dv_convert_action_modify_ipv4
 501                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 502                          const struct rte_flow_action *action,
 503                          struct rte_flow_error *error)
 504 {
 505         const struct rte_flow_action_set_ipv4 *conf =
 506                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 507         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 508         struct rte_flow_item_ipv4 ipv4;
 509         struct rte_flow_item_ipv4 ipv4_mask;
 510
 511         memset(&ipv4, 0, sizeof(ipv4));
 512         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 513         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 514                 ipv4.hdr.src_addr = conf->ipv4_addr;
 515                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 516         } else {
 517                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 518                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 519         }
 520         item.spec = &ipv4;
 521         item.mask = &ipv4_mask;
 522         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 523                                              MLX5_MODIFICATION_TYPE_SET, error);
 524 }
 525
 526 /**
 527  * Convert modify-header set IPv6 address action to DV specification.
 528  *
 529  * @param[in,out] resource
 530  *   Pointer to the modify-header resource.
 531  * @param[in] action
 532  *   Pointer to action specification.
 533  * @param[out] error
 534  *   Pointer to the error structure.
 535  *
 536  * @return
 537  *   0 on success, a negative errno value otherwise and rte_errno is set.
 538  */
 539 static int
 540 flow_dv_convert_action_modify_ipv6
 541                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 542                          const struct rte_flow_action *action,
 543                          struct rte_flow_error *error)
 544 {
 545         const struct rte_flow_action_set_ipv6 *conf =
 546                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 547         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 548         struct rte_flow_item_ipv6 ipv6;
 549         struct rte_flow_item_ipv6 ipv6_mask;
 550
 551         memset(&ipv6, 0, sizeof(ipv6));
 552         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 553         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 554                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 555                        sizeof(ipv6.hdr.src_addr));
 556                 memcpy(&ipv6_mask.hdr.src_addr,
 557                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 558                        sizeof(ipv6.hdr.src_addr));
 559         } else {
 560                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 561                        sizeof(ipv6.hdr.dst_addr));
 562                 memcpy(&ipv6_mask.hdr.dst_addr,
 563                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 564                        sizeof(ipv6.hdr.dst_addr));
 565         }
 566         item.spec = &ipv6;
 567         item.mask = &ipv6_mask;
 568         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 569                                              MLX5_MODIFICATION_TYPE_SET, error);
 570 }
 571
 572 /**
 573  * Convert modify-header set MAC address action to DV specification.
 574  *
 575  * @param[in,out] resource
 576  *   Pointer to the modify-header resource.
 577  * @param[in] action
 578  *   Pointer to action specification.
 579  * @param[out] error
 580  *   Pointer to the error structure.
 581  *
 582  * @return
 583  *   0 on success, a negative errno value otherwise and rte_errno is set.
 584  */
 585 static int
 586 flow_dv_convert_action_modify_mac
 587                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 588                          const struct rte_flow_action *action,
 589                          struct rte_flow_error *error)
 590 {
 591         const struct rte_flow_action_set_mac *conf =
 592                 (const struct rte_flow_action_set_mac *)(action->conf);
 593         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 594         struct rte_flow_item_eth eth;
 595         struct rte_flow_item_eth eth_mask;
 596
 597         memset(&eth, 0, sizeof(eth));
 598         memset(&eth_mask, 0, sizeof(eth_mask));
 599         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 600                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 601                        sizeof(eth.src.addr_bytes));
 602                 memcpy(&eth_mask.src.addr_bytes,
 603                        &rte_flow_item_eth_mask.src.addr_bytes,
 604                        sizeof(eth_mask.src.addr_bytes));
 605         } else {
 606                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 607                        sizeof(eth.dst.addr_bytes));
 608                 memcpy(&eth_mask.dst.addr_bytes,
 609                        &rte_flow_item_eth_mask.dst.addr_bytes,
 610                        sizeof(eth_mask.dst.addr_bytes));
 611         }
 612         item.spec = &eth;
 613         item.mask = &eth_mask;
 614         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 615                                              MLX5_MODIFICATION_TYPE_SET, error);
 616 }
 617
 618 /**
 619  * Convert modify-header set VLAN VID action to DV specification.
 620  *
 621  * @param[in,out] resource
 622  *   Pointer to the modify-header resource.
 623  * @param[in] action
 624  *   Pointer to action specification.
 625  * @param[out] error
 626  *   Pointer to the error structure.
 627  *
 628  * @return
 629  *   0 on success, a negative errno value otherwise and rte_errno is set.
 630  */
 631 static int
 632 flow_dv_convert_action_modify_vlan_vid
 633                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 634                          const struct rte_flow_action *action,
 635                          struct rte_flow_error *error)
 636 {
 637         const struct rte_flow_action_of_set_vlan_vid *conf =
 638                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 639         int i = resource->actions_num;
 640         struct mlx5_modification_cmd *actions = resource->actions;
 641         struct field_modify_info *field = modify_vlan_out_first_vid;
 642
 643         if (i >= MLX5_MAX_MODIFY_NUM)
 644                 return rte_flow_error_set(error, EINVAL,
 645                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 646                          "too many items to modify");
 647         actions[i] = (struct mlx5_modification_cmd) {
 648                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 649                 .field = field->id,
 650                 .length = field->size,
 651                 .offset = field->offset,
 652         };
 653         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 654         actions[i].data1 = conf->vlan_vid;
 655         actions[i].data1 = actions[i].data1 << 16;
 656         resource->actions_num = ++i;
 657         return 0;
 658 }
 659
 660 /**
 661  * Convert modify-header set TP action to DV specification.
 662  *
 663  * @param[in,out] resource
 664  *   Pointer to the modify-header resource.
 665  * @param[in] action
 666  *   Pointer to action specification.
 667  * @param[in] items
 668  *   Pointer to rte_flow_item objects list.
 669  * @param[in] attr
 670  *   Pointer to flow attributes structure.
 671  * @param[in] dev_flow
 672  *   Pointer to the sub flow.
 673  * @param[in] tunnel_decap
 674  *   Whether action is after tunnel decapsulation.
 675  * @param[out] error
 676  *   Pointer to the error structure.
 677  *
 678  * @return
 679  *   0 on success, a negative errno value otherwise and rte_errno is set.
 680  */
 681 static int
 682 flow_dv_convert_action_modify_tp
 683                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 684                          const struct rte_flow_action *action,
 685                          const struct rte_flow_item *items,
 686                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 687                          bool tunnel_decap, struct rte_flow_error *error)
 688 {
 689         const struct rte_flow_action_set_tp *conf =
 690                 (const struct rte_flow_action_set_tp *)(action->conf);
 691         struct rte_flow_item item;
 692         struct rte_flow_item_udp udp;
 693         struct rte_flow_item_udp udp_mask;
 694         struct rte_flow_item_tcp tcp;
 695         struct rte_flow_item_tcp tcp_mask;
 696         struct field_modify_info *field;
 697
 698         if (!attr->valid)
 699                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 700         if (attr->udp) {
 701                 memset(&udp, 0, sizeof(udp));
 702                 memset(&udp_mask, 0, sizeof(udp_mask));
 703                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 704                         udp.hdr.src_port = conf->port;
 705                         udp_mask.hdr.src_port =
 706                                         rte_flow_item_udp_mask.hdr.src_port;
 707                 } else {
 708                         udp.hdr.dst_port = conf->port;
 709                         udp_mask.hdr.dst_port =
 710                                         rte_flow_item_udp_mask.hdr.dst_port;
 711                 }
 712                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 713                 item.spec = &udp;
 714                 item.mask = &udp_mask;
 715                 field = modify_udp;
 716         } else {
 717                 MLX5_ASSERT(attr->tcp);
 718                 memset(&tcp, 0, sizeof(tcp));
 719                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 720                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 721                         tcp.hdr.src_port = conf->port;
 722                         tcp_mask.hdr.src_port =
 723                                         rte_flow_item_tcp_mask.hdr.src_port;
 724                 } else {
 725                         tcp.hdr.dst_port = conf->port;
 726                         tcp_mask.hdr.dst_port =
 727                                         rte_flow_item_tcp_mask.hdr.dst_port;
 728                 }
 729                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 730                 item.spec = &tcp;
 731                 item.mask = &tcp_mask;
 732                 field = modify_tcp;
 733         }
 734         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 735                                              MLX5_MODIFICATION_TYPE_SET, error);
 736 }
 737
 738 /**
 739  * Convert modify-header set TTL action to DV specification.
 740  *
 741  * @param[in,out] resource
 742  *   Pointer to the modify-header resource.
 743  * @param[in] action
 744  *   Pointer to action specification.
 745  * @param[in] items
 746  *   Pointer to rte_flow_item objects list.
 747  * @param[in] attr
 748  *   Pointer to flow attributes structure.
 749  * @param[in] dev_flow
 750  *   Pointer to the sub flow.
 751  * @param[in] tunnel_decap
 752  *   Whether action is after tunnel decapsulation.
 753  * @param[out] error
 754  *   Pointer to the error structure.
 755  *
 756  * @return
 757  *   0 on success, a negative errno value otherwise and rte_errno is set.
 758  */
 759 static int
 760 flow_dv_convert_action_modify_ttl
 761                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 762                          const struct rte_flow_action *action,
 763                          const struct rte_flow_item *items,
 764                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 765                          bool tunnel_decap, struct rte_flow_error *error)
 766 {
 767         const struct rte_flow_action_set_ttl *conf =
 768                 (const struct rte_flow_action_set_ttl *)(action->conf);
 769         struct rte_flow_item item;
 770         struct rte_flow_item_ipv4 ipv4;
 771         struct rte_flow_item_ipv4 ipv4_mask;
 772         struct rte_flow_item_ipv6 ipv6;
 773         struct rte_flow_item_ipv6 ipv6_mask;
 774         struct field_modify_info *field;
 775
 776         if (!attr->valid)
 777                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 778         if (attr->ipv4) {
 779                 memset(&ipv4, 0, sizeof(ipv4));
 780                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 781                 ipv4.hdr.time_to_live = conf->ttl_value;
 782                 ipv4_mask.hdr.time_to_live = 0xFF;
 783                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 784                 item.spec = &ipv4;
 785                 item.mask = &ipv4_mask;
 786                 field = modify_ipv4;
 787         } else {
 788                 MLX5_ASSERT(attr->ipv6);
 789                 memset(&ipv6, 0, sizeof(ipv6));
 790                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 791                 ipv6.hdr.hop_limits = conf->ttl_value;
 792                 ipv6_mask.hdr.hop_limits = 0xFF;
 793                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 794                 item.spec = &ipv6;
 795                 item.mask = &ipv6_mask;
 796                 field = modify_ipv6;
 797         }
 798         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 799                                              MLX5_MODIFICATION_TYPE_SET, error);
 800 }
 801
 802 /**
 803  * Convert modify-header decrement TTL action to DV specification.
 804  *
 805  * @param[in,out] resource
 806  *   Pointer to the modify-header resource.
 807  * @param[in] action
 808  *   Pointer to action specification.
 809  * @param[in] items
 810  *   Pointer to rte_flow_item objects list.
 811  * @param[in] attr
 812  *   Pointer to flow attributes structure.
 813  * @param[in] dev_flow
 814  *   Pointer to the sub flow.
 815  * @param[in] tunnel_decap
 816  *   Whether action is after tunnel decapsulation.
 817  * @param[out] error
 818  *   Pointer to the error structure.
 819  *
 820  * @return
 821  *   0 on success, a negative errno value otherwise and rte_errno is set.
 822  */
 823 static int
 824 flow_dv_convert_action_modify_dec_ttl
 825                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 826                          const struct rte_flow_item *items,
 827                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 828                          bool tunnel_decap, struct rte_flow_error *error)
 829 {
 830         struct rte_flow_item item;
 831         struct rte_flow_item_ipv4 ipv4;
 832         struct rte_flow_item_ipv4 ipv4_mask;
 833         struct rte_flow_item_ipv6 ipv6;
 834         struct rte_flow_item_ipv6 ipv6_mask;
 835         struct field_modify_info *field;
 836
 837         if (!attr->valid)
 838                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 839         if (attr->ipv4) {
 840                 memset(&ipv4, 0, sizeof(ipv4));
 841                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 842                 ipv4.hdr.time_to_live = 0xFF;
 843                 ipv4_mask.hdr.time_to_live = 0xFF;
 844                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 845                 item.spec = &ipv4;
 846                 item.mask = &ipv4_mask;
 847                 field = modify_ipv4;
 848         } else {
 849                 MLX5_ASSERT(attr->ipv6);
 850                 memset(&ipv6, 0, sizeof(ipv6));
 851                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 852                 ipv6.hdr.hop_limits = 0xFF;
 853                 ipv6_mask.hdr.hop_limits = 0xFF;
 854                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 855                 item.spec = &ipv6;
 856                 item.mask = &ipv6_mask;
 857                 field = modify_ipv6;
 858         }
 859         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 860                                              MLX5_MODIFICATION_TYPE_ADD, error);
 861 }
 862
 863 /**
 864  * Convert modify-header increment/decrement TCP Sequence number
 865  * to DV specification.
 866  *
 867  * @param[in,out] resource
 868  *   Pointer to the modify-header resource.
 869  * @param[in] action
 870  *   Pointer to action specification.
 871  * @param[out] error
 872  *   Pointer to the error structure.
 873  *
 874  * @return
 875  *   0 on success, a negative errno value otherwise and rte_errno is set.
 876  */
 877 static int
 878 flow_dv_convert_action_modify_tcp_seq
 879                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 880                          const struct rte_flow_action *action,
 881                          struct rte_flow_error *error)
 882 {
 883         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 884         uint64_t value = rte_be_to_cpu_32(*conf);
 885         struct rte_flow_item item;
 886         struct rte_flow_item_tcp tcp;
 887         struct rte_flow_item_tcp tcp_mask;
 888
 889         memset(&tcp, 0, sizeof(tcp));
 890         memset(&tcp_mask, 0, sizeof(tcp_mask));
 891         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 892                 /*
 893                  * The HW has no decrement operation, only increment operation.
 894                  * To simulate decrement X from Y using increment operation
 895                  * we need to add UINT32_MAX X times to Y.
 896                  * Each adding of UINT32_MAX decrements Y by 1.
 897                  */
 898                 value *= UINT32_MAX;
 899         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 900         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 901         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 902         item.spec = &tcp;
 903         item.mask = &tcp_mask;
 904         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 905                                              MLX5_MODIFICATION_TYPE_ADD, error);
 906 }
 907
 908 /**
 909  * Convert modify-header increment/decrement TCP Acknowledgment number
 910  * to DV specification.
 911  *
 912  * @param[in,out] resource
 913  *   Pointer to the modify-header resource.
 914  * @param[in] action
 915  *   Pointer to action specification.
 916  * @param[out] error
 917  *   Pointer to the error structure.
 918  *
 919  * @return
 920  *   0 on success, a negative errno value otherwise and rte_errno is set.
 921  */
 922 static int
 923 flow_dv_convert_action_modify_tcp_ack
 924                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 925                          const struct rte_flow_action *action,
 926                          struct rte_flow_error *error)
 927 {
 928         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 929         uint64_t value = rte_be_to_cpu_32(*conf);
 930         struct rte_flow_item item;
 931         struct rte_flow_item_tcp tcp;
 932         struct rte_flow_item_tcp tcp_mask;
 933
 934         memset(&tcp, 0, sizeof(tcp));
 935         memset(&tcp_mask, 0, sizeof(tcp_mask));
 936         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 937                 /*
 938                  * The HW has no decrement operation, only increment operation.
 939                  * To simulate decrement X from Y using increment operation
 940                  * we need to add UINT32_MAX X times to Y.
 941                  * Each adding of UINT32_MAX decrements Y by 1.
 942                  */
 943                 value *= UINT32_MAX;
 944         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 945         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 946         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 947         item.spec = &tcp;
 948         item.mask = &tcp_mask;
 949         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 950                                              MLX5_MODIFICATION_TYPE_ADD, error);
 951 }
 952
 953 static enum mlx5_modification_field reg_to_field[] = {
 954         [REG_NON] = MLX5_MODI_OUT_NONE,
 955         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 956         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 957         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 958         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 959         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 960         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 961         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 962         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 963         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 964         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 965 };
 966
 967 /**
 968  * Convert register set to DV specification.
 969  *
 970  * @param[in,out] resource
 971  *   Pointer to the modify-header resource.
 972  * @param[in] action
 973  *   Pointer to action specification.
 974  * @param[out] error
 975  *   Pointer to the error structure.
 976  *
 977  * @return
 978  *   0 on success, a negative errno value otherwise and rte_errno is set.
 979  */
 980 static int
 981 flow_dv_convert_action_set_reg
 982                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 983                          const struct rte_flow_action *action,
 984                          struct rte_flow_error *error)
 985 {
 986         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 987         struct mlx5_modification_cmd *actions = resource->actions;
 988         uint32_t i = resource->actions_num;
 989
 990         if (i >= MLX5_MAX_MODIFY_NUM)
 991                 return rte_flow_error_set(error, EINVAL,
 992                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 993                                           "too many items to modify");
 994         MLX5_ASSERT(conf->id != REG_NON);
 995         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 996         actions[i] = (struct mlx5_modification_cmd) {
 997                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 998                 .field = reg_to_field[conf->id],
 999         };
1000         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1001         actions[i].data1 = rte_cpu_to_be_32(conf->data);
1002         ++i;
1003         resource->actions_num = i;
1004         return 0;
1005 }
1006
1007 /**
1008  * Convert SET_TAG action to DV specification.
1009  *
1010  * @param[in] dev
1011  *   Pointer to the rte_eth_dev structure.
1012  * @param[in,out] resource
1013  *   Pointer to the modify-header resource.
1014  * @param[in] conf
1015  *   Pointer to action specification.
1016  * @param[out] error
1017  *   Pointer to the error structure.
1018  *
1019  * @return
1020  *   0 on success, a negative errno value otherwise and rte_errno is set.
1021  */
1022 static int
1023 flow_dv_convert_action_set_tag
1024                         (struct rte_eth_dev *dev,
1025                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1026                          const struct rte_flow_action_set_tag *conf,
1027                          struct rte_flow_error *error)
1028 {
1029         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1030         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1031         struct rte_flow_item item = {
1032                 .spec = &data,
1033                 .mask = &mask,
1034         };
1035         struct field_modify_info reg_c_x[] = {
1036                 [1] = {0, 0, 0},
1037         };
1038         enum mlx5_modification_field reg_type;
1039         int ret;
1040
1041         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1042         if (ret < 0)
1043                 return ret;
1044         MLX5_ASSERT(ret != REG_NON);
1045         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1046         reg_type = reg_to_field[ret];
1047         MLX5_ASSERT(reg_type > 0);
1048         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1049         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1050                                              MLX5_MODIFICATION_TYPE_SET, error);
1051 }
1052
1053 /**
1054  * Convert internal COPY_REG action to DV specification.
1055  *
1056  * @param[in] dev
1057  *   Pointer to the rte_eth_dev structure.
1058  * @param[in,out] res
1059  *   Pointer to the modify-header resource.
1060  * @param[in] action
1061  *   Pointer to action specification.
1062  * @param[out] error
1063  *   Pointer to the error structure.
1064  *
1065  * @return
1066  *   0 on success, a negative errno value otherwise and rte_errno is set.
1067  */
1068 static int
1069 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1070                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1071                                  const struct rte_flow_action *action,
1072                                  struct rte_flow_error *error)
1073 {
1074         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1075         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1076         struct rte_flow_item item = {
1077                 .spec = NULL,
1078                 .mask = &mask,
1079         };
1080         struct field_modify_info reg_src[] = {
1081                 {4, 0, reg_to_field[conf->src]},
1082                 {0, 0, 0},
1083         };
1084         struct field_modify_info reg_dst = {
1085                 .offset = 0,
1086                 .id = reg_to_field[conf->dst],
1087         };
1088         /* Adjust reg_c[0] usage according to reported mask. */
1089         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1090                 struct mlx5_priv *priv = dev->data->dev_private;
1091                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1092
1093                 MLX5_ASSERT(reg_c0);
1094                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1095                 if (conf->dst == REG_C_0) {
1096                         /* Copy to reg_c[0], within mask only. */
1097                         reg_dst.offset = rte_bsf32(reg_c0);
1098                         /*
1099                          * Mask is ignoring the enianness, because
1100                          * there is no conversion in datapath.
1101                          */
1102 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1103                         /* Copy from destination lower bits to reg_c[0]. */
1104                         mask = reg_c0 >> reg_dst.offset;
1105 #else
1106                         /* Copy from destination upper bits to reg_c[0]. */
1107                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1108                                           rte_fls_u32(reg_c0));
1109 #endif
1110                 } else {
1111                         mask = rte_cpu_to_be_32(reg_c0);
1112 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1113                         /* Copy from reg_c[0] to destination lower bits. */
1114                         reg_dst.offset = 0;
1115 #else
1116                         /* Copy from reg_c[0] to destination upper bits. */
1117                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1118                                          (rte_fls_u32(reg_c0) -
1119                                           rte_bsf32(reg_c0));
1120 #endif
1121                 }
1122         }
1123         return flow_dv_convert_modify_action(&item,
1124                                              reg_src, &reg_dst, res,
1125                                              MLX5_MODIFICATION_TYPE_COPY,
1126                                              error);
1127 }
1128
1129 /**
1130  * Convert MARK action to DV specification. This routine is used
1131  * in extensive metadata only and requires metadata register to be
1132  * handled. In legacy mode hardware tag resource is engaged.
1133  *
1134  * @param[in] dev
1135  *   Pointer to the rte_eth_dev structure.
1136  * @param[in] conf
1137  *   Pointer to MARK action specification.
1138  * @param[in,out] resource
1139  *   Pointer to the modify-header resource.
1140  * @param[out] error
1141  *   Pointer to the error structure.
1142  *
1143  * @return
1144  *   0 on success, a negative errno value otherwise and rte_errno is set.
1145  */
1146 static int
1147 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1148                             const struct rte_flow_action_mark *conf,
1149                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1150                             struct rte_flow_error *error)
1151 {
1152         struct mlx5_priv *priv = dev->data->dev_private;
1153         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1154                                            priv->sh->dv_mark_mask);
1155         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1156         struct rte_flow_item item = {
1157                 .spec = &data,
1158                 .mask = &mask,
1159         };
1160         struct field_modify_info reg_c_x[] = {
1161                 [1] = {0, 0, 0},
1162         };
1163         int reg;
1164
1165         if (!mask)
1166                 return rte_flow_error_set(error, EINVAL,
1167                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1168                                           NULL, "zero mark action mask");
1169         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1170         if (reg < 0)
1171                 return reg;
1172         MLX5_ASSERT(reg > 0);
1173         if (reg == REG_C_0) {
1174                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1175                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1176
1177                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1178                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1179                 mask = rte_cpu_to_be_32(mask << shl_c0);
1180         }
1181         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1182         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1183                                              MLX5_MODIFICATION_TYPE_SET, error);
1184 }
1185
1186 /**
1187  * Get metadata register index for specified steering domain.
1188  *
1189  * @param[in] dev
1190  *   Pointer to the rte_eth_dev structure.
1191  * @param[in] attr
1192  *   Attributes of flow to determine steering domain.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   positive index on success, a negative errno value otherwise
1198  *   and rte_errno is set.
1199  */
1200 static enum modify_reg
1201 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1202                          const struct rte_flow_attr *attr,
1203                          struct rte_flow_error *error)
1204 {
1205         int reg =
1206                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1207                                           MLX5_METADATA_FDB :
1208                                             attr->egress ?
1209                                             MLX5_METADATA_TX :
1210                                             MLX5_METADATA_RX, 0, error);
1211         if (reg < 0)
1212                 return rte_flow_error_set(error,
1213                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1214                                           NULL, "unavailable "
1215                                           "metadata register");
1216         return reg;
1217 }
1218
1219 /**
1220  * Convert SET_META action to DV specification.
1221  *
1222  * @param[in] dev
1223  *   Pointer to the rte_eth_dev structure.
1224  * @param[in,out] resource
1225  *   Pointer to the modify-header resource.
1226  * @param[in] attr
1227  *   Attributes of flow that includes this item.
1228  * @param[in] conf
1229  *   Pointer to action specification.
1230  * @param[out] error
1231  *   Pointer to the error structure.
1232  *
1233  * @return
1234  *   0 on success, a negative errno value otherwise and rte_errno is set.
1235  */
1236 static int
1237 flow_dv_convert_action_set_meta
1238                         (struct rte_eth_dev *dev,
1239                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1240                          const struct rte_flow_attr *attr,
1241                          const struct rte_flow_action_set_meta *conf,
1242                          struct rte_flow_error *error)
1243 {
1244         uint32_t data = conf->data;
1245         uint32_t mask = conf->mask;
1246         struct rte_flow_item item = {
1247                 .spec = &data,
1248                 .mask = &mask,
1249         };
1250         struct field_modify_info reg_c_x[] = {
1251                 [1] = {0, 0, 0},
1252         };
1253         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1254
1255         if (reg < 0)
1256                 return reg;
1257         /*
1258          * In datapath code there is no endianness
1259          * coversions for perfromance reasons, all
1260          * pattern conversions are done in rte_flow.
1261          */
1262         if (reg == REG_C_0) {
1263                 struct mlx5_priv *priv = dev->data->dev_private;
1264                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1265                 uint32_t shl_c0;
1266
1267                 MLX5_ASSERT(msk_c0);
1268 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1269                 shl_c0 = rte_bsf32(msk_c0);
1270 #else
1271                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1272 #endif
1273                 mask <<= shl_c0;
1274                 data <<= shl_c0;
1275                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1276         }
1277         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1278         /* The routine expects parameters in memory as big-endian ones. */
1279         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1280                                              MLX5_MODIFICATION_TYPE_SET, error);
1281 }
1282
1283 /**
1284  * Convert modify-header set IPv4 DSCP action to DV specification.
1285  *
1286  * @param[in,out] resource
1287  *   Pointer to the modify-header resource.
1288  * @param[in] action
1289  *   Pointer to action specification.
1290  * @param[out] error
1291  *   Pointer to the error structure.
1292  *
1293  * @return
1294  *   0 on success, a negative errno value otherwise and rte_errno is set.
1295  */
1296 static int
1297 flow_dv_convert_action_modify_ipv4_dscp
1298                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1299                          const struct rte_flow_action *action,
1300                          struct rte_flow_error *error)
1301 {
1302         const struct rte_flow_action_set_dscp *conf =
1303                 (const struct rte_flow_action_set_dscp *)(action->conf);
1304         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1305         struct rte_flow_item_ipv4 ipv4;
1306         struct rte_flow_item_ipv4 ipv4_mask;
1307
1308         memset(&ipv4, 0, sizeof(ipv4));
1309         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1310         ipv4.hdr.type_of_service = conf->dscp;
1311         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1312         item.spec = &ipv4;
1313         item.mask = &ipv4_mask;
1314         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1315                                              MLX5_MODIFICATION_TYPE_SET, error);
1316 }
1317
1318 /**
1319  * Convert modify-header set IPv6 DSCP action to DV specification.
1320  *
1321  * @param[in,out] resource
1322  *   Pointer to the modify-header resource.
1323  * @param[in] action
1324  *   Pointer to action specification.
1325  * @param[out] error
1326  *   Pointer to the error structure.
1327  *
1328  * @return
1329  *   0 on success, a negative errno value otherwise and rte_errno is set.
1330  */
1331 static int
1332 flow_dv_convert_action_modify_ipv6_dscp
1333                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1334                          const struct rte_flow_action *action,
1335                          struct rte_flow_error *error)
1336 {
1337         const struct rte_flow_action_set_dscp *conf =
1338                 (const struct rte_flow_action_set_dscp *)(action->conf);
1339         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1340         struct rte_flow_item_ipv6 ipv6;
1341         struct rte_flow_item_ipv6 ipv6_mask;
1342
1343         memset(&ipv6, 0, sizeof(ipv6));
1344         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1345         /*
1346          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1347          * rdma-core only accept the DSCP bits byte aligned start from
1348          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1349          * bits in IPv6 case as rdma-core requires byte aligned value.
1350          */
1351         ipv6.hdr.vtc_flow = conf->dscp;
1352         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1353         item.spec = &ipv6;
1354         item.mask = &ipv6_mask;
1355         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1356                                              MLX5_MODIFICATION_TYPE_SET, error);
1357 }
1358
1359 /**
1360  * Validate MARK item.
1361  *
1362  * @param[in] dev
1363  *   Pointer to the rte_eth_dev structure.
1364  * @param[in] item
1365  *   Item specification.
1366  * @param[in] attr
1367  *   Attributes of flow that includes this item.
1368  * @param[out] error
1369  *   Pointer to error structure.
1370  *
1371  * @return
1372  *   0 on success, a negative errno value otherwise and rte_errno is set.
1373  */
1374 static int
1375 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1376                            const struct rte_flow_item *item,
1377                            const struct rte_flow_attr *attr __rte_unused,
1378                            struct rte_flow_error *error)
1379 {
1380         struct mlx5_priv *priv = dev->data->dev_private;
1381         struct mlx5_dev_config *config = &priv->config;
1382         const struct rte_flow_item_mark *spec = item->spec;
1383         const struct rte_flow_item_mark *mask = item->mask;
1384         const struct rte_flow_item_mark nic_mask = {
1385                 .id = priv->sh->dv_mark_mask,
1386         };
1387         int ret;
1388
1389         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1390                 return rte_flow_error_set(error, ENOTSUP,
1391                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1392                                           "extended metadata feature"
1393                                           " isn't enabled");
1394         if (!mlx5_flow_ext_mreg_supported(dev))
1395                 return rte_flow_error_set(error, ENOTSUP,
1396                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1397                                           "extended metadata register"
1398                                           " isn't supported");
1399         if (!nic_mask.id)
1400                 return rte_flow_error_set(error, ENOTSUP,
1401                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1402                                           "extended metadata register"
1403                                           " isn't available");
1404         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1405         if (ret < 0)
1406                 return ret;
1407         if (!spec)
1408                 return rte_flow_error_set(error, EINVAL,
1409                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1410                                           item->spec,
1411                                           "data cannot be empty");
1412         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1413                 return rte_flow_error_set(error, EINVAL,
1414                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1415                                           &spec->id,
1416                                           "mark id exceeds the limit");
1417         if (!mask)
1418                 mask = &nic_mask;
1419         if (!mask->id)
1420                 return rte_flow_error_set(error, EINVAL,
1421                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1422                                         "mask cannot be zero");
1423
1424         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1425                                         (const uint8_t *)&nic_mask,
1426                                         sizeof(struct rte_flow_item_mark),
1427                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1428         if (ret < 0)
1429                 return ret;
1430         return 0;
1431 }
1432
1433 /**
1434  * Validate META item.
1435  *
1436  * @param[in] dev
1437  *   Pointer to the rte_eth_dev structure.
1438  * @param[in] item
1439  *   Item specification.
1440  * @param[in] attr
1441  *   Attributes of flow that includes this item.
1442  * @param[out] error
1443  *   Pointer to error structure.
1444  *
1445  * @return
1446  *   0 on success, a negative errno value otherwise and rte_errno is set.
1447  */
1448 static int
1449 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1450                            const struct rte_flow_item *item,
1451                            const struct rte_flow_attr *attr,
1452                            struct rte_flow_error *error)
1453 {
1454         struct mlx5_priv *priv = dev->data->dev_private;
1455         struct mlx5_dev_config *config = &priv->config;
1456         const struct rte_flow_item_meta *spec = item->spec;
1457         const struct rte_flow_item_meta *mask = item->mask;
1458         struct rte_flow_item_meta nic_mask = {
1459                 .data = UINT32_MAX
1460         };
1461         int reg;
1462         int ret;
1463
1464         if (!spec)
1465                 return rte_flow_error_set(error, EINVAL,
1466                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1467                                           item->spec,
1468                                           "data cannot be empty");
1469         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1470                 if (!mlx5_flow_ext_mreg_supported(dev))
1471                         return rte_flow_error_set(error, ENOTSUP,
1472                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1473                                           "extended metadata register"
1474                                           " isn't supported");
1475                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1476                 if (reg < 0)
1477                         return reg;
1478                 if (reg == REG_B)
1479                         return rte_flow_error_set(error, ENOTSUP,
1480                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1481                                           "match on reg_b "
1482                                           "isn't supported");
1483                 if (reg != REG_A)
1484                         nic_mask.data = priv->sh->dv_meta_mask;
1485         } else if (attr->transfer) {
1486                 return rte_flow_error_set(error, ENOTSUP,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1488                                         "extended metadata feature "
1489                                         "should be enabled when "
1490                                         "meta item is requested "
1491                                         "with e-switch mode ");
1492         }
1493         if (!mask)
1494                 mask = &rte_flow_item_meta_mask;
1495         if (!mask->data)
1496                 return rte_flow_error_set(error, EINVAL,
1497                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1498                                         "mask cannot be zero");
1499
1500         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1501                                         (const uint8_t *)&nic_mask,
1502                                         sizeof(struct rte_flow_item_meta),
1503                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1504         return ret;
1505 }
1506
1507 /**
1508  * Validate TAG item.
1509  *
1510  * @param[in] dev
1511  *   Pointer to the rte_eth_dev structure.
1512  * @param[in] item
1513  *   Item specification.
1514  * @param[in] attr
1515  *   Attributes of flow that includes this item.
1516  * @param[out] error
1517  *   Pointer to error structure.
1518  *
1519  * @return
1520  *   0 on success, a negative errno value otherwise and rte_errno is set.
1521  */
1522 static int
1523 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1524                           const struct rte_flow_item *item,
1525                           const struct rte_flow_attr *attr __rte_unused,
1526                           struct rte_flow_error *error)
1527 {
1528         const struct rte_flow_item_tag *spec = item->spec;
1529         const struct rte_flow_item_tag *mask = item->mask;
1530         const struct rte_flow_item_tag nic_mask = {
1531                 .data = RTE_BE32(UINT32_MAX),
1532                 .index = 0xff,
1533         };
1534         int ret;
1535
1536         if (!mlx5_flow_ext_mreg_supported(dev))
1537                 return rte_flow_error_set(error, ENOTSUP,
1538                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1539                                           "extensive metadata register"
1540                                           " isn't supported");
1541         if (!spec)
1542                 return rte_flow_error_set(error, EINVAL,
1543                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1544                                           item->spec,
1545                                           "data cannot be empty");
1546         if (!mask)
1547                 mask = &rte_flow_item_tag_mask;
1548         if (!mask->data)
1549                 return rte_flow_error_set(error, EINVAL,
1550                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551                                         "mask cannot be zero");
1552
1553         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1554                                         (const uint8_t *)&nic_mask,
1555                                         sizeof(struct rte_flow_item_tag),
1556                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1557         if (ret < 0)
1558                 return ret;
1559         if (mask->index != 0xff)
1560                 return rte_flow_error_set(error, EINVAL,
1561                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1562                                           "partial mask for tag index"
1563                                           " is not supported");
1564         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1565         if (ret < 0)
1566                 return ret;
1567         MLX5_ASSERT(ret != REG_NON);
1568         return 0;
1569 }
1570
1571 /**
1572  * Validate vport item.
1573  *
1574  * @param[in] dev
1575  *   Pointer to the rte_eth_dev structure.
1576  * @param[in] item
1577  *   Item specification.
1578  * @param[in] attr
1579  *   Attributes of flow that includes this item.
1580  * @param[in] item_flags
1581  *   Bit-fields that holds the items detected until now.
1582  * @param[out] error
1583  *   Pointer to error structure.
1584  *
1585  * @return
1586  *   0 on success, a negative errno value otherwise and rte_errno is set.
1587  */
1588 static int
1589 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1590                               const struct rte_flow_item *item,
1591                               const struct rte_flow_attr *attr,
1592                               uint64_t item_flags,
1593                               struct rte_flow_error *error)
1594 {
1595         const struct rte_flow_item_port_id *spec = item->spec;
1596         const struct rte_flow_item_port_id *mask = item->mask;
1597         const struct rte_flow_item_port_id switch_mask = {
1598                         .id = 0xffffffff,
1599         };
1600         struct mlx5_priv *esw_priv;
1601         struct mlx5_priv *dev_priv;
1602         int ret;
1603
1604         if (!attr->transfer)
1605                 return rte_flow_error_set(error, EINVAL,
1606                                           RTE_FLOW_ERROR_TYPE_ITEM,
1607                                           NULL,
1608                                           "match on port id is valid only"
1609                                           " when transfer flag is enabled");
1610         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1611                 return rte_flow_error_set(error, ENOTSUP,
1612                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1613                                           "multiple source ports are not"
1614                                           " supported");
1615         if (!mask)
1616                 mask = &switch_mask;
1617         if (mask->id != 0xffffffff)
1618                 return rte_flow_error_set(error, ENOTSUP,
1619                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1620                                            mask,
1621                                            "no support for partial mask on"
1622                                            " \"id\" field");
1623         ret = mlx5_flow_item_acceptable
1624                                 (item, (const uint8_t *)mask,
1625                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1626                                  sizeof(struct rte_flow_item_port_id),
1627                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1628         if (ret)
1629                 return ret;
1630         if (!spec)
1631                 return 0;
1632         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1633         if (!esw_priv)
1634                 return rte_flow_error_set(error, rte_errno,
1635                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636                                           "failed to obtain E-Switch info for"
1637                                           " port");
1638         dev_priv = mlx5_dev_to_eswitch_info(dev);
1639         if (!dev_priv)
1640                 return rte_flow_error_set(error, rte_errno,
1641                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1642                                           NULL,
1643                                           "failed to obtain E-Switch info");
1644         if (esw_priv->domain_id != dev_priv->domain_id)
1645                 return rte_flow_error_set(error, EINVAL,
1646                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1647                                           "cannot match on a port from a"
1648                                           " different E-Switch");
1649         return 0;
1650 }
1651
1652 /**
1653  * Validate VLAN item.
1654  *
1655  * @param[in] item
1656  *   Item specification.
1657  * @param[in] item_flags
1658  *   Bit-fields that holds the items detected until now.
1659  * @param[in] dev
1660  *   Ethernet device flow is being created on.
1661  * @param[out] error
1662  *   Pointer to error structure.
1663  *
1664  * @return
1665  *   0 on success, a negative errno value otherwise and rte_errno is set.
1666  */
1667 static int
1668 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1669                            uint64_t item_flags,
1670                            struct rte_eth_dev *dev,
1671                            struct rte_flow_error *error)
1672 {
1673         const struct rte_flow_item_vlan *mask = item->mask;
1674         const struct rte_flow_item_vlan nic_mask = {
1675                 .tci = RTE_BE16(UINT16_MAX),
1676                 .inner_type = RTE_BE16(UINT16_MAX),
1677                 .has_more_vlan = 1,
1678         };
1679         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1680         int ret;
1681         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1682                                         MLX5_FLOW_LAYER_INNER_L4) :
1683                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1684                                         MLX5_FLOW_LAYER_OUTER_L4);
1685         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1686                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1687
1688         if (item_flags & vlanm)
1689                 return rte_flow_error_set(error, EINVAL,
1690                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1691                                           "multiple VLAN layers not supported");
1692         else if ((item_flags & l34m) != 0)
1693                 return rte_flow_error_set(error, EINVAL,
1694                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1695                                           "VLAN cannot follow L3/L4 layer");
1696         if (!mask)
1697                 mask = &rte_flow_item_vlan_mask;
1698         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1699                                         (const uint8_t *)&nic_mask,
1700                                         sizeof(struct rte_flow_item_vlan),
1701                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1702         if (ret)
1703                 return ret;
1704         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1705                 struct mlx5_priv *priv = dev->data->dev_private;
1706
1707                 if (priv->vmwa_context) {
1708                         /*
1709                          * Non-NULL context means we have a virtual machine
1710                          * and SR-IOV enabled, we have to create VLAN interface
1711                          * to make hypervisor to setup E-Switch vport
1712                          * context correctly. We avoid creating the multiple
1713                          * VLAN interfaces, so we cannot support VLAN tag mask.
1714                          */
1715                         return rte_flow_error_set(error, EINVAL,
1716                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1717                                                   item,
1718                                                   "VLAN tag mask is not"
1719                                                   " supported in virtual"
1720                                                   " environment");
1721                 }
1722         }
1723         return 0;
1724 }
1725
1726 /*
1727  * GTP flags are contained in 1 byte of the format:
1728  * -------------------------------------------
1729  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1730  * |-----------------------------------------|
1731  * | value | Version | PT | Res | E | S | PN |
1732  * -------------------------------------------
1733  *
1734  * Matching is supported only for GTP flags E, S, PN.
1735  */
1736 #define MLX5_GTP_FLAGS_MASK     0x07
1737
1738 /**
1739  * Validate GTP item.
1740  *
1741  * @param[in] dev
1742  *   Pointer to the rte_eth_dev structure.
1743  * @param[in] item
1744  *   Item specification.
1745  * @param[in] item_flags
1746  *   Bit-fields that holds the items detected until now.
1747  * @param[out] error
1748  *   Pointer to error structure.
1749  *
1750  * @return
1751  *   0 on success, a negative errno value otherwise and rte_errno is set.
1752  */
1753 static int
1754 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1755                           const struct rte_flow_item *item,
1756                           uint64_t item_flags,
1757                           struct rte_flow_error *error)
1758 {
1759         struct mlx5_priv *priv = dev->data->dev_private;
1760         const struct rte_flow_item_gtp *spec = item->spec;
1761         const struct rte_flow_item_gtp *mask = item->mask;
1762         const struct rte_flow_item_gtp nic_mask = {
1763                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1764                 .msg_type = 0xff,
1765                 .teid = RTE_BE32(0xffffffff),
1766         };
1767
1768         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1769                 return rte_flow_error_set(error, ENOTSUP,
1770                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1771                                           "GTP support is not enabled");
1772         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "multiple tunnel layers not"
1776                                           " supported");
1777         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1778                 return rte_flow_error_set(error, EINVAL,
1779                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1780                                           "no outer UDP layer found");
1781         if (!mask)
1782                 mask = &rte_flow_item_gtp_mask;
1783         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1784                 return rte_flow_error_set(error, ENOTSUP,
1785                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1786                                           "Match is supported for GTP"
1787                                           " flags only");
1788         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1789                                          (const uint8_t *)&nic_mask,
1790                                          sizeof(struct rte_flow_item_gtp),
1791                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1792 }
1793
1794 /**
1795  * Validate IPV4 item.
1796  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1797  * add specific validation of fragment_offset field,
1798  *
1799  * @param[in] item
1800  *   Item specification.
1801  * @param[in] item_flags
1802  *   Bit-fields that holds the items detected until now.
1803  * @param[out] error
1804  *   Pointer to error structure.
1805  *
1806  * @return
1807  *   0 on success, a negative errno value otherwise and rte_errno is set.
1808  */
1809 static int
1810 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1811                            uint64_t item_flags,
1812                            uint64_t last_item,
1813                            uint16_t ether_type,
1814                            struct rte_flow_error *error)
1815 {
1816         int ret;
1817         const struct rte_flow_item_ipv4 *spec = item->spec;
1818         const struct rte_flow_item_ipv4 *last = item->last;
1819         const struct rte_flow_item_ipv4 *mask = item->mask;
1820         rte_be16_t fragment_offset_spec = 0;
1821         rte_be16_t fragment_offset_last = 0;
1822         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1823                 .hdr = {
1824                         .src_addr = RTE_BE32(0xffffffff),
1825                         .dst_addr = RTE_BE32(0xffffffff),
1826                         .type_of_service = 0xff,
1827                         .fragment_offset = RTE_BE16(0xffff),
1828                         .next_proto_id = 0xff,
1829                         .time_to_live = 0xff,
1830                 },
1831         };
1832
1833         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1834                                            ether_type, &nic_ipv4_mask,
1835                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1836         if (ret < 0)
1837                 return ret;
1838         if (spec && mask)
1839                 fragment_offset_spec = spec->hdr.fragment_offset &
1840                                        mask->hdr.fragment_offset;
1841         if (!fragment_offset_spec)
1842                 return 0;
1843         /*
1844          * spec and mask are valid, enforce using full mask to make sure the
1845          * complete value is used correctly.
1846          */
1847         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1848                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1849                 return rte_flow_error_set(error, EINVAL,
1850                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1851                                           item, "must use full mask for"
1852                                           " fragment_offset");
1853         /*
1854          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1855          * indicating this is 1st fragment of fragmented packet.
1856          * This is not yet supported in MLX5, return appropriate error message.
1857          */
1858         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1859                 return rte_flow_error_set(error, ENOTSUP,
1860                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1861                                           "match on first fragment not "
1862                                           "supported");
1863         if (fragment_offset_spec && !last)
1864                 return rte_flow_error_set(error, ENOTSUP,
1865                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1866                                           "specified value not supported");
1867         /* spec and last are valid, validate the specified range. */
1868         fragment_offset_last = last->hdr.fragment_offset &
1869                                mask->hdr.fragment_offset;
1870         /*
1871          * Match on fragment_offset spec 0x2001 and last 0x3fff
1872          * means MF is 1 and frag-offset is > 0.
1873          * This packet is fragment 2nd and onward, excluding last.
1874          * This is not yet supported in MLX5, return appropriate
1875          * error message.
1876          */
1877         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1878             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1879                 return rte_flow_error_set(error, ENOTSUP,
1880                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1881                                           last, "match on following "
1882                                           "fragments not supported");
1883         /*
1884          * Match on fragment_offset spec 0x0001 and last 0x1fff
1885          * means MF is 0 and frag-offset is > 0.
1886          * This packet is last fragment of fragmented packet.
1887          * This is not yet supported in MLX5, return appropriate
1888          * error message.
1889          */
1890         if (fragment_offset_spec == RTE_BE16(1) &&
1891             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1892                 return rte_flow_error_set(error, ENOTSUP,
1893                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1894                                           last, "match on last "
1895                                           "fragment not supported");
1896         /*
1897          * Match on fragment_offset spec 0x0001 and last 0x3fff
1898          * means MF and/or frag-offset is not 0.
1899          * This is a fragmented packet.
1900          * Other range values are invalid and rejected.
1901          */
1902         if (!(fragment_offset_spec == RTE_BE16(1) &&
1903               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1904                 return rte_flow_error_set(error, ENOTSUP,
1905                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1906                                           "specified range not supported");
1907         return 0;
1908 }
1909
1910 /**
1911  * Validate IPV6 fragment extension item.
1912  *
1913  * @param[in] item
1914  *   Item specification.
1915  * @param[in] item_flags
1916  *   Bit-fields that holds the items detected until now.
1917  * @param[out] error
1918  *   Pointer to error structure.
1919  *
1920  * @return
1921  *   0 on success, a negative errno value otherwise and rte_errno is set.
1922  */
1923 static int
1924 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1925                                     uint64_t item_flags,
1926                                     struct rte_flow_error *error)
1927 {
1928         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1929         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1930         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1931         rte_be16_t frag_data_spec = 0;
1932         rte_be16_t frag_data_last = 0;
1933         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1934         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1935                                       MLX5_FLOW_LAYER_OUTER_L4;
1936         int ret = 0;
1937         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1938                 .hdr = {
1939                         .next_header = 0xff,
1940                         .frag_data = RTE_BE16(0xffff),
1941                 },
1942         };
1943
1944         if (item_flags & l4m)
1945                 return rte_flow_error_set(error, EINVAL,
1946                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1947                                           "ipv6 fragment extension item cannot "
1948                                           "follow L4 item.");
1949         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1950             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1951                 return rte_flow_error_set(error, EINVAL,
1952                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1953                                           "ipv6 fragment extension item must "
1954                                           "follow ipv6 item");
1955         if (spec && mask)
1956                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1957         if (!frag_data_spec)
1958                 return 0;
1959         /*
1960          * spec and mask are valid, enforce using full mask to make sure the
1961          * complete value is used correctly.
1962          */
1963         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1964                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1965                 return rte_flow_error_set(error, EINVAL,
1966                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1967                                           item, "must use full mask for"
1968                                           " frag_data");
1969         /*
1970          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1971          * This is 1st fragment of fragmented packet.
1972          */
1973         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1974                 return rte_flow_error_set(error, ENOTSUP,
1975                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1976                                           "match on first fragment not "
1977                                           "supported");
1978         if (frag_data_spec && !last)
1979                 return rte_flow_error_set(error, EINVAL,
1980                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1981                                           "specified value not supported");
1982         ret = mlx5_flow_item_acceptable
1983                                 (item, (const uint8_t *)mask,
1984                                  (const uint8_t *)&nic_mask,
1985                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
1986                                  MLX5_ITEM_RANGE_ACCEPTED, error);
1987         if (ret)
1988                 return ret;
1989         /* spec and last are valid, validate the specified range. */
1990         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1991         /*
1992          * Match on frag_data spec 0x0009 and last 0xfff9
1993          * means M is 1 and frag-offset is > 0.
1994          * This packet is fragment 2nd and onward, excluding last.
1995          * This is not yet supported in MLX5, return appropriate
1996          * error message.
1997          */
1998         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
1999                                        RTE_IPV6_EHDR_MF_MASK) &&
2000             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2001                 return rte_flow_error_set(error, ENOTSUP,
2002                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2003                                           last, "match on following "
2004                                           "fragments not supported");
2005         /*
2006          * Match on frag_data spec 0x0008 and last 0xfff8
2007          * means M is 0 and frag-offset is > 0.
2008          * This packet is last fragment of fragmented packet.
2009          * This is not yet supported in MLX5, return appropriate
2010          * error message.
2011          */
2012         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2013             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2014                 return rte_flow_error_set(error, ENOTSUP,
2015                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2016                                           last, "match on last "
2017                                           "fragment not supported");
2018         /* Other range values are invalid and rejected. */
2019         return rte_flow_error_set(error, EINVAL,
2020                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2021                                   "specified range not supported");
2022 }
2023
2024 /**
2025  * Validate the pop VLAN action.
2026  *
2027  * @param[in] dev
2028  *   Pointer to the rte_eth_dev structure.
2029  * @param[in] action_flags
2030  *   Holds the actions detected until now.
2031  * @param[in] action
2032  *   Pointer to the pop vlan action.
2033  * @param[in] item_flags
2034  *   The items found in this flow rule.
2035  * @param[in] attr
2036  *   Pointer to flow attributes.
2037  * @param[out] error
2038  *   Pointer to error structure.
2039  *
2040  * @return
2041  *   0 on success, a negative errno value otherwise and rte_errno is set.
2042  */
2043 static int
2044 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2045                                  uint64_t action_flags,
2046                                  const struct rte_flow_action *action,
2047                                  uint64_t item_flags,
2048                                  const struct rte_flow_attr *attr,
2049                                  struct rte_flow_error *error)
2050 {
2051         const struct mlx5_priv *priv = dev->data->dev_private;
2052
2053         (void)action;
2054         (void)attr;
2055         if (!priv->sh->pop_vlan_action)
2056                 return rte_flow_error_set(error, ENOTSUP,
2057                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2058                                           NULL,
2059                                           "pop vlan action is not supported");
2060         if (attr->egress)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2063                                           NULL,
2064                                           "pop vlan action not supported for "
2065                                           "egress");
2066         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2067                 return rte_flow_error_set(error, ENOTSUP,
2068                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2069                                           "no support for multiple VLAN "
2070                                           "actions");
2071         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2072         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2073             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2074                 return rte_flow_error_set(error, ENOTSUP,
2075                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2076                                           NULL,
2077                                           "cannot pop vlan after decap without "
2078                                           "match on inner vlan in the flow");
2079         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2080         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2081             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2082                 return rte_flow_error_set(error, ENOTSUP,
2083                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2084                                           NULL,
2085                                           "cannot pop vlan without a "
2086                                           "match on (outer) vlan in the flow");
2087         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2088                 return rte_flow_error_set(error, EINVAL,
2089                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2090                                           "wrong action order, port_id should "
2091                                           "be after pop VLAN action");
2092         if (!attr->transfer && priv->representor)
2093                 return rte_flow_error_set(error, ENOTSUP,
2094                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2095                                           "pop vlan action for VF representor "
2096                                           "not supported on NIC table");
2097         return 0;
2098 }
2099
2100 /**
2101  * Get VLAN default info from vlan match info.
2102  *
2103  * @param[in] items
2104  *   the list of item specifications.
2105  * @param[out] vlan
2106  *   pointer VLAN info to fill to.
2107  *
2108  * @return
2109  *   0 on success, a negative errno value otherwise and rte_errno is set.
2110  */
2111 static void
2112 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2113                                   struct rte_vlan_hdr *vlan)
2114 {
2115         const struct rte_flow_item_vlan nic_mask = {
2116                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2117                                 MLX5DV_FLOW_VLAN_VID_MASK),
2118                 .inner_type = RTE_BE16(0xffff),
2119         };
2120
2121         if (items == NULL)
2122                 return;
2123         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2124                 int type = items->type;
2125
2126                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2127                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2128                         break;
2129         }
2130         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2131                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2132                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2133
2134                 /* If VLAN item in pattern doesn't contain data, return here. */
2135                 if (!vlan_v)
2136                         return;
2137                 if (!vlan_m)
2138                         vlan_m = &nic_mask;
2139                 /* Only full match values are accepted */
2140                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2141                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2142                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2143                         vlan->vlan_tci |=
2144                                 rte_be_to_cpu_16(vlan_v->tci &
2145                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2146                 }
2147                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2148                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2149                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2150                         vlan->vlan_tci |=
2151                                 rte_be_to_cpu_16(vlan_v->tci &
2152                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2153                 }
2154                 if (vlan_m->inner_type == nic_mask.inner_type)
2155                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2156                                                            vlan_m->inner_type);
2157         }
2158 }
2159
2160 /**
2161  * Validate the push VLAN action.
2162  *
2163  * @param[in] dev
2164  *   Pointer to the rte_eth_dev structure.
2165  * @param[in] action_flags
2166  *   Holds the actions detected until now.
2167  * @param[in] item_flags
2168  *   The items found in this flow rule.
2169  * @param[in] action
2170  *   Pointer to the action structure.
2171  * @param[in] attr
2172  *   Pointer to flow attributes
2173  * @param[out] error
2174  *   Pointer to error structure.
2175  *
2176  * @return
2177  *   0 on success, a negative errno value otherwise and rte_errno is set.
2178  */
2179 static int
2180 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2181                                   uint64_t action_flags,
2182                                   const struct rte_flow_item_vlan *vlan_m,
2183                                   const struct rte_flow_action *action,
2184                                   const struct rte_flow_attr *attr,
2185                                   struct rte_flow_error *error)
2186 {
2187         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2188         const struct mlx5_priv *priv = dev->data->dev_private;
2189
2190         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2191             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2192                 return rte_flow_error_set(error, EINVAL,
2193                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2194                                           "invalid vlan ethertype");
2195         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2196                 return rte_flow_error_set(error, EINVAL,
2197                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2198                                           "wrong action order, port_id should "
2199                                           "be after push VLAN");
2200         if (!attr->transfer && priv->representor)
2201                 return rte_flow_error_set(error, ENOTSUP,
2202                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2203                                           "push vlan action for VF representor "
2204                                           "not supported on NIC table");
2205         if (vlan_m &&
2206             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2207             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2208                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2209             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2210             !(mlx5_flow_find_action
2211                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2212                 return rte_flow_error_set(error, EINVAL,
2213                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2214                                           "not full match mask on VLAN PCP and "
2215                                           "there is no of_set_vlan_pcp action, "
2216                                           "push VLAN action cannot figure out "
2217                                           "PCP value");
2218         if (vlan_m &&
2219             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2220             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2221                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2222             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2223             !(mlx5_flow_find_action
2224                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2225                 return rte_flow_error_set(error, EINVAL,
2226                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2227                                           "not full match mask on VLAN VID and "
2228                                           "there is no of_set_vlan_vid action, "
2229                                           "push VLAN action cannot figure out "
2230                                           "VID value");
2231         (void)attr;
2232         return 0;
2233 }
2234
2235 /**
2236  * Validate the set VLAN PCP.
2237  *
2238  * @param[in] action_flags
2239  *   Holds the actions detected until now.
2240  * @param[in] actions
2241  *   Pointer to the list of actions remaining in the flow rule.
2242  * @param[out] error
2243  *   Pointer to error structure.
2244  *
2245  * @return
2246  *   0 on success, a negative errno value otherwise and rte_errno is set.
2247  */
2248 static int
2249 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2250                                      const struct rte_flow_action actions[],
2251                                      struct rte_flow_error *error)
2252 {
2253         const struct rte_flow_action *action = actions;
2254         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2255
2256         if (conf->vlan_pcp > 7)
2257                 return rte_flow_error_set(error, EINVAL,
2258                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2259                                           "VLAN PCP value is too big");
2260         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2261                 return rte_flow_error_set(error, ENOTSUP,
2262                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2263                                           "set VLAN PCP action must follow "
2264                                           "the push VLAN action");
2265         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2266                 return rte_flow_error_set(error, ENOTSUP,
2267                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2268                                           "Multiple VLAN PCP modification are "
2269                                           "not supported");
2270         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2271                 return rte_flow_error_set(error, EINVAL,
2272                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2273                                           "wrong action order, port_id should "
2274                                           "be after set VLAN PCP");
2275         return 0;
2276 }
2277
2278 /**
2279  * Validate the set VLAN VID.
2280  *
2281  * @param[in] item_flags
2282  *   Holds the items detected in this rule.
2283  * @param[in] action_flags
2284  *   Holds the actions detected until now.
2285  * @param[in] actions
2286  *   Pointer to the list of actions remaining in the flow rule.
2287  * @param[out] error
2288  *   Pointer to error structure.
2289  *
2290  * @return
2291  *   0 on success, a negative errno value otherwise and rte_errno is set.
2292  */
2293 static int
2294 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2295                                      uint64_t action_flags,
2296                                      const struct rte_flow_action actions[],
2297                                      struct rte_flow_error *error)
2298 {
2299         const struct rte_flow_action *action = actions;
2300         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2301
2302         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2303                 return rte_flow_error_set(error, EINVAL,
2304                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2305                                           "VLAN VID value is too big");
2306         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2307             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2308                 return rte_flow_error_set(error, ENOTSUP,
2309                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2310                                           "set VLAN VID action must follow push"
2311                                           " VLAN action or match on VLAN item");
2312         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2313                 return rte_flow_error_set(error, ENOTSUP,
2314                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2315                                           "Multiple VLAN VID modifications are "
2316                                           "not supported");
2317         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2318                 return rte_flow_error_set(error, EINVAL,
2319                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2320                                           "wrong action order, port_id should "
2321                                           "be after set VLAN VID");
2322         return 0;
2323 }
2324
2325 /*
2326  * Validate the FLAG action.
2327  *
2328  * @param[in] dev
2329  *   Pointer to the rte_eth_dev structure.
2330  * @param[in] action_flags
2331  *   Holds the actions detected until now.
2332  * @param[in] attr
2333  *   Pointer to flow attributes
2334  * @param[out] error
2335  *   Pointer to error structure.
2336  *
2337  * @return
2338  *   0 on success, a negative errno value otherwise and rte_errno is set.
2339  */
2340 static int
2341 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2342                              uint64_t action_flags,
2343                              const struct rte_flow_attr *attr,
2344                              struct rte_flow_error *error)
2345 {
2346         struct mlx5_priv *priv = dev->data->dev_private;
2347         struct mlx5_dev_config *config = &priv->config;
2348         int ret;
2349
2350         /* Fall back if no extended metadata register support. */
2351         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2352                 return mlx5_flow_validate_action_flag(action_flags, attr,
2353                                                       error);
2354         /* Extensive metadata mode requires registers. */
2355         if (!mlx5_flow_ext_mreg_supported(dev))
2356                 return rte_flow_error_set(error, ENOTSUP,
2357                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2358                                           "no metadata registers "
2359                                           "to support flag action");
2360         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2361                 return rte_flow_error_set(error, ENOTSUP,
2362                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2363                                           "extended metadata register"
2364                                           " isn't available");
2365         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2366         if (ret < 0)
2367                 return ret;
2368         MLX5_ASSERT(ret > 0);
2369         if (action_flags & MLX5_FLOW_ACTION_MARK)
2370                 return rte_flow_error_set(error, EINVAL,
2371                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2372                                           "can't mark and flag in same flow");
2373         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2374                 return rte_flow_error_set(error, EINVAL,
2375                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2376                                           "can't have 2 flag"
2377                                           " actions in same flow");
2378         return 0;
2379 }
2380
2381 /**
2382  * Validate MARK action.
2383  *
2384  * @param[in] dev
2385  *   Pointer to the rte_eth_dev structure.
2386  * @param[in] action
2387  *   Pointer to action.
2388  * @param[in] action_flags
2389  *   Holds the actions detected until now.
2390  * @param[in] attr
2391  *   Pointer to flow attributes
2392  * @param[out] error
2393  *   Pointer to error structure.
2394  *
2395  * @return
2396  *   0 on success, a negative errno value otherwise and rte_errno is set.
2397  */
2398 static int
2399 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2400                              const struct rte_flow_action *action,
2401                              uint64_t action_flags,
2402                              const struct rte_flow_attr *attr,
2403                              struct rte_flow_error *error)
2404 {
2405         struct mlx5_priv *priv = dev->data->dev_private;
2406         struct mlx5_dev_config *config = &priv->config;
2407         const struct rte_flow_action_mark *mark = action->conf;
2408         int ret;
2409
2410         /* Fall back if no extended metadata register support. */
2411         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2412                 return mlx5_flow_validate_action_mark(action, action_flags,
2413                                                       attr, error);
2414         /* Extensive metadata mode requires registers. */
2415         if (!mlx5_flow_ext_mreg_supported(dev))
2416                 return rte_flow_error_set(error, ENOTSUP,
2417                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2418                                           "no metadata registers "
2419                                           "to support mark action");
2420         if (!priv->sh->dv_mark_mask)
2421                 return rte_flow_error_set(error, ENOTSUP,
2422                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2423                                           "extended metadata register"
2424                                           " isn't available");
2425         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2426         if (ret < 0)
2427                 return ret;
2428         MLX5_ASSERT(ret > 0);
2429         if (!mark)
2430                 return rte_flow_error_set(error, EINVAL,
2431                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2432                                           "configuration cannot be null");
2433         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2434                 return rte_flow_error_set(error, EINVAL,
2435                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2436                                           &mark->id,
2437                                           "mark id exceeds the limit");
2438         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2439                 return rte_flow_error_set(error, EINVAL,
2440                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2441                                           "can't flag and mark in same flow");
2442         if (action_flags & MLX5_FLOW_ACTION_MARK)
2443                 return rte_flow_error_set(error, EINVAL,
2444                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2445                                           "can't have 2 mark actions in same"
2446                                           " flow");
2447         return 0;
2448 }
2449
2450 /**
2451  * Validate SET_META action.
2452  *
2453  * @param[in] dev
2454  *   Pointer to the rte_eth_dev structure.
2455  * @param[in] action
2456  *   Pointer to the action structure.
2457  * @param[in] action_flags
2458  *   Holds the actions detected until now.
2459  * @param[in] attr
2460  *   Pointer to flow attributes
2461  * @param[out] error
2462  *   Pointer to error structure.
2463  *
2464  * @return
2465  *   0 on success, a negative errno value otherwise and rte_errno is set.
2466  */
2467 static int
2468 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2469                                  const struct rte_flow_action *action,
2470                                  uint64_t action_flags __rte_unused,
2471                                  const struct rte_flow_attr *attr,
2472                                  struct rte_flow_error *error)
2473 {
2474         const struct rte_flow_action_set_meta *conf;
2475         uint32_t nic_mask = UINT32_MAX;
2476         int reg;
2477
2478         if (!mlx5_flow_ext_mreg_supported(dev))
2479                 return rte_flow_error_set(error, ENOTSUP,
2480                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2481                                           "extended metadata register"
2482                                           " isn't supported");
2483         reg = flow_dv_get_metadata_reg(dev, attr, error);
2484         if (reg < 0)
2485                 return reg;
2486         if (reg != REG_A && reg != REG_B) {
2487                 struct mlx5_priv *priv = dev->data->dev_private;
2488
2489                 nic_mask = priv->sh->dv_meta_mask;
2490         }
2491         if (!(action->conf))
2492                 return rte_flow_error_set(error, EINVAL,
2493                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2494                                           "configuration cannot be null");
2495         conf = (const struct rte_flow_action_set_meta *)action->conf;
2496         if (!conf->mask)
2497                 return rte_flow_error_set(error, EINVAL,
2498                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2499                                           "zero mask doesn't have any effect");
2500         if (conf->mask & ~nic_mask)
2501                 return rte_flow_error_set(error, EINVAL,
2502                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2503                                           "meta data must be within reg C0");
2504         return 0;
2505 }
2506
2507 /**
2508  * Validate SET_TAG action.
2509  *
2510  * @param[in] dev
2511  *   Pointer to the rte_eth_dev structure.
2512  * @param[in] action
2513  *   Pointer to the action structure.
2514  * @param[in] action_flags
2515  *   Holds the actions detected until now.
2516  * @param[in] attr
2517  *   Pointer to flow attributes
2518  * @param[out] error
2519  *   Pointer to error structure.
2520  *
2521  * @return
2522  *   0 on success, a negative errno value otherwise and rte_errno is set.
2523  */
2524 static int
2525 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2526                                 const struct rte_flow_action *action,
2527                                 uint64_t action_flags,
2528                                 const struct rte_flow_attr *attr,
2529                                 struct rte_flow_error *error)
2530 {
2531         const struct rte_flow_action_set_tag *conf;
2532         const uint64_t terminal_action_flags =
2533                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2534                 MLX5_FLOW_ACTION_RSS;
2535         int ret;
2536
2537         if (!mlx5_flow_ext_mreg_supported(dev))
2538                 return rte_flow_error_set(error, ENOTSUP,
2539                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2540                                           "extensive metadata register"
2541                                           " isn't supported");
2542         if (!(action->conf))
2543                 return rte_flow_error_set(error, EINVAL,
2544                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2545                                           "configuration cannot be null");
2546         conf = (const struct rte_flow_action_set_tag *)action->conf;
2547         if (!conf->mask)
2548                 return rte_flow_error_set(error, EINVAL,
2549                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2550                                           "zero mask doesn't have any effect");
2551         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2552         if (ret < 0)
2553                 return ret;
2554         if (!attr->transfer && attr->ingress &&
2555             (action_flags & terminal_action_flags))
2556                 return rte_flow_error_set(error, EINVAL,
2557                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2558                                           "set_tag has no effect"
2559                                           " with terminal actions");
2560         return 0;
2561 }
2562
2563 /**
2564  * Validate count action.
2565  *
2566  * @param[in] dev
2567  *   Pointer to rte_eth_dev structure.
2568  * @param[out] error
2569  *   Pointer to error structure.
2570  *
2571  * @return
2572  *   0 on success, a negative errno value otherwise and rte_errno is set.
2573  */
2574 static int
2575 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2576                               struct rte_flow_error *error)
2577 {
2578         struct mlx5_priv *priv = dev->data->dev_private;
2579
2580         if (!priv->config.devx)
2581                 goto notsup_err;
2582 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2583         return 0;
2584 #endif
2585 notsup_err:
2586         return rte_flow_error_set
2587                       (error, ENOTSUP,
2588                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2589                        NULL,
2590                        "count action not supported");
2591 }
2592
2593 /**
2594  * Validate the L2 encap action.
2595  *
2596  * @param[in] dev
2597  *   Pointer to the rte_eth_dev structure.
2598  * @param[in] action_flags
2599  *   Holds the actions detected until now.
2600  * @param[in] action
2601  *   Pointer to the action structure.
2602  * @param[in] attr
2603  *   Pointer to flow attributes.
2604  * @param[out] error
2605  *   Pointer to error structure.
2606  *
2607  * @return
2608  *   0 on success, a negative errno value otherwise and rte_errno is set.
2609  */
2610 static int
2611 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2612                                  uint64_t action_flags,
2613                                  const struct rte_flow_action *action,
2614                                  const struct rte_flow_attr *attr,
2615                                  struct rte_flow_error *error)
2616 {
2617         const struct mlx5_priv *priv = dev->data->dev_private;
2618
2619         if (!(action->conf))
2620                 return rte_flow_error_set(error, EINVAL,
2621                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2622                                           "configuration cannot be null");
2623         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2624                 return rte_flow_error_set(error, EINVAL,
2625                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2626                                           "can only have a single encap action "
2627                                           "in a flow");
2628         if (!attr->transfer && priv->representor)
2629                 return rte_flow_error_set(error, ENOTSUP,
2630                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2631                                           "encap action for VF representor "
2632                                           "not supported on NIC table");
2633         return 0;
2634 }
2635
2636 /**
2637  * Validate a decap action.
2638  *
2639  * @param[in] dev
2640  *   Pointer to the rte_eth_dev structure.
2641  * @param[in] action_flags
2642  *   Holds the actions detected until now.
2643  * @param[in] attr
2644  *   Pointer to flow attributes
2645  * @param[out] error
2646  *   Pointer to error structure.
2647  *
2648  * @return
2649  *   0 on success, a negative errno value otherwise and rte_errno is set.
2650  */
2651 static int
2652 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2653                               uint64_t action_flags,
2654                               const struct rte_flow_attr *attr,
2655                               struct rte_flow_error *error)
2656 {
2657         const struct mlx5_priv *priv = dev->data->dev_private;
2658
2659         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2660             !priv->config.decap_en)
2661                 return rte_flow_error_set(error, ENOTSUP,
2662                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2663                                           "decap is not enabled");
2664         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2665                 return rte_flow_error_set(error, ENOTSUP,
2666                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2667                                           action_flags &
2668                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2669                                           "have a single decap action" : "decap "
2670                                           "after encap is not supported");
2671         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2672                 return rte_flow_error_set(error, EINVAL,
2673                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2674                                           "can't have decap action after"
2675                                           " modify action");
2676         if (attr->egress)
2677                 return rte_flow_error_set(error, ENOTSUP,
2678                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2679                                           NULL,
2680                                           "decap action not supported for "
2681                                           "egress");
2682         if (!attr->transfer && priv->representor)
2683                 return rte_flow_error_set(error, ENOTSUP,
2684                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2685                                           "decap action for VF representor "
2686                                           "not supported on NIC table");
2687         return 0;
2688 }
2689
2690 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2691
2692 /**
2693  * Validate the raw encap and decap actions.
2694  *
2695  * @param[in] dev
2696  *   Pointer to the rte_eth_dev structure.
2697  * @param[in] decap
2698  *   Pointer to the decap action.
2699  * @param[in] encap
2700  *   Pointer to the encap action.
2701  * @param[in] attr
2702  *   Pointer to flow attributes
2703  * @param[in/out] action_flags
2704  *   Holds the actions detected until now.
2705  * @param[out] actions_n
2706  *   pointer to the number of actions counter.
2707  * @param[out] error
2708  *   Pointer to error structure.
2709  *
2710  * @return
2711  *   0 on success, a negative errno value otherwise and rte_errno is set.
2712  */
2713 static int
2714 flow_dv_validate_action_raw_encap_decap
2715         (struct rte_eth_dev *dev,
2716          const struct rte_flow_action_raw_decap *decap,
2717          const struct rte_flow_action_raw_encap *encap,
2718          const struct rte_flow_attr *attr, uint64_t *action_flags,
2719          int *actions_n, struct rte_flow_error *error)
2720 {
2721         const struct mlx5_priv *priv = dev->data->dev_private;
2722         int ret;
2723
2724         if (encap && (!encap->size || !encap->data))
2725                 return rte_flow_error_set(error, EINVAL,
2726                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2727                                           "raw encap data cannot be empty");
2728         if (decap && encap) {
2729                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2730                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2731                         /* L3 encap. */
2732                         decap = NULL;
2733                 else if (encap->size <=
2734                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2735                            decap->size >
2736                            MLX5_ENCAPSULATION_DECISION_SIZE)
2737                         /* L3 decap. */
2738                         encap = NULL;
2739                 else if (encap->size >
2740                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2741                            decap->size >
2742                            MLX5_ENCAPSULATION_DECISION_SIZE)
2743                         /* 2 L2 actions: encap and decap. */
2744                         ;
2745                 else
2746                         return rte_flow_error_set(error,
2747                                 ENOTSUP,
2748                                 RTE_FLOW_ERROR_TYPE_ACTION,
2749                                 NULL, "unsupported too small "
2750                                 "raw decap and too small raw "
2751                                 "encap combination");
2752         }
2753         if (decap) {
2754                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2755                                                     error);
2756                 if (ret < 0)
2757                         return ret;
2758                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2759                 ++(*actions_n);
2760         }
2761         if (encap) {
2762                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2763                         return rte_flow_error_set(error, ENOTSUP,
2764                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2765                                                   NULL,
2766                                                   "small raw encap size");
2767                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2768                         return rte_flow_error_set(error, EINVAL,
2769                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2770                                                   NULL,
2771                                                   "more than one encap action");
2772                 if (!attr->transfer && priv->representor)
2773                         return rte_flow_error_set
2774                                         (error, ENOTSUP,
2775                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2776                                          "encap action for VF representor "
2777                                          "not supported on NIC table");
2778                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2779                 ++(*actions_n);
2780         }
2781         return 0;
2782 }
2783
2784 /**
2785  * Match encap_decap resource.
2786  *
2787  * @param entry
2788  *   Pointer to exist resource entry object.
2789  * @param ctx
2790  *   Pointer to new encap_decap resource.
2791  *
2792  * @return
2793  *   0 on matching, -1 otherwise.
2794  */
2795 static int
2796 flow_dv_encap_decap_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
2797 {
2798         struct mlx5_flow_dv_encap_decap_resource *resource;
2799         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2800
2801         resource = (struct mlx5_flow_dv_encap_decap_resource *)ctx;
2802         cache_resource = container_of(entry,
2803                                       struct mlx5_flow_dv_encap_decap_resource,
2804                                       entry);
2805         if (resource->entry.key == cache_resource->entry.key &&
2806             resource->reformat_type == cache_resource->reformat_type &&
2807             resource->ft_type == cache_resource->ft_type &&
2808             resource->flags == cache_resource->flags &&
2809             resource->size == cache_resource->size &&
2810             !memcmp((const void *)resource->buf,
2811                     (const void *)cache_resource->buf,
2812                     resource->size))
2813                 return 0;
2814         return -1;
2815 }
2816
2817 /**
2818  * Find existing encap/decap resource or create and register a new one.
2819  *
2820  * @param[in, out] dev
2821  *   Pointer to rte_eth_dev structure.
2822  * @param[in, out] resource
2823  *   Pointer to encap/decap resource.
2824  * @parm[in, out] dev_flow
2825  *   Pointer to the dev_flow.
2826  * @param[out] error
2827  *   pointer to error structure.
2828  *
2829  * @return
2830  *   0 on success otherwise -errno and errno is set.
2831  */
2832 static int
2833 flow_dv_encap_decap_resource_register
2834                         (struct rte_eth_dev *dev,
2835                          struct mlx5_flow_dv_encap_decap_resource *resource,
2836                          struct mlx5_flow *dev_flow,
2837                          struct rte_flow_error *error)
2838 {
2839         struct mlx5_priv *priv = dev->data->dev_private;
2840         struct mlx5_dev_ctx_shared *sh = priv->sh;
2841         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2842         struct mlx5dv_dr_domain *domain;
2843         struct mlx5_hlist_entry *entry;
2844         union mlx5_flow_encap_decap_key encap_decap_key = {
2845                 {
2846                         .ft_type = resource->ft_type,
2847                         .refmt_type = resource->reformat_type,
2848                         .buf_size = resource->size,
2849                         .table_level = !!dev_flow->dv.group,
2850                         .cksum = 0,
2851                 }
2852         };
2853         int ret;
2854
2855         resource->flags = dev_flow->dv.group ? 0 : 1;
2856         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2857                 domain = sh->fdb_domain;
2858         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2859                 domain = sh->rx_domain;
2860         else
2861                 domain = sh->tx_domain;
2862         encap_decap_key.cksum = __rte_raw_cksum(resource->buf,
2863                                                 resource->size, 0);
2864         resource->entry.key = encap_decap_key.v64;
2865         /* Lookup a matching resource from cache. */
2866         entry = mlx5_hlist_lookup_ex(sh->encaps_decaps, resource->entry.key,
2867                                      flow_dv_encap_decap_resource_match,
2868                                      (void *)resource);
2869         if (entry) {
2870                 cache_resource = container_of(entry,
2871                         struct mlx5_flow_dv_encap_decap_resource, entry);
2872                 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2873                         (void *)cache_resource,
2874                         __atomic_load_n(&cache_resource->refcnt,
2875                                         __ATOMIC_RELAXED));
2876                 __atomic_fetch_add(&cache_resource->refcnt, 1,
2877                                    __ATOMIC_RELAXED);
2878                 dev_flow->handle->dvh.rix_encap_decap = cache_resource->idx;
2879                 dev_flow->dv.encap_decap = cache_resource;
2880                 return 0;
2881         }
2882         /* Register new encap/decap resource. */
2883         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2884                                        &dev_flow->handle->dvh.rix_encap_decap);
2885         if (!cache_resource)
2886                 return rte_flow_error_set(error, ENOMEM,
2887                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2888                                           "cannot allocate resource memory");
2889         *cache_resource = *resource;
2890         cache_resource->idx = dev_flow->handle->dvh.rix_encap_decap;
2891         ret = mlx5_flow_os_create_flow_action_packet_reformat
2892                                         (sh->ctx, domain, cache_resource,
2893                                          &cache_resource->action);
2894         if (ret) {
2895                 mlx5_free(cache_resource);
2896                 return rte_flow_error_set(error, ENOMEM,
2897                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2898                                           NULL, "cannot create action");
2899         }
2900         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
2901         if (mlx5_hlist_insert_ex(sh->encaps_decaps, &cache_resource->entry,
2902                                  flow_dv_encap_decap_resource_match,
2903                                  (void *)cache_resource)) {
2904                 claim_zero(mlx5_flow_os_destroy_flow_action
2905                                                 (cache_resource->action));
2906                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2907                                 cache_resource->idx);
2908                 return rte_flow_error_set(error, EEXIST,
2909                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2910                                           NULL, "action exist");
2911         }
2912         dev_flow->dv.encap_decap = cache_resource;
2913         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2914                 (void *)cache_resource,
2915                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
2916         return 0;
2917 }
2918
2919 /**
2920  * Find existing table jump resource or create and register a new one.
2921  *
2922  * @param[in, out] dev
2923  *   Pointer to rte_eth_dev structure.
2924  * @param[in, out] tbl
2925  *   Pointer to flow table resource.
2926  * @parm[in, out] dev_flow
2927  *   Pointer to the dev_flow.
2928  * @param[out] error
2929  *   pointer to error structure.
2930  *
2931  * @return
2932  *   0 on success otherwise -errno and errno is set.
2933  */
2934 static int
2935 flow_dv_jump_tbl_resource_register
2936                         (struct rte_eth_dev *dev __rte_unused,
2937                          struct mlx5_flow_tbl_resource *tbl,
2938                          struct mlx5_flow *dev_flow,
2939                          struct rte_flow_error *error __rte_unused)
2940 {
2941         struct mlx5_flow_tbl_data_entry *tbl_data =
2942                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2943
2944         MLX5_ASSERT(tbl);
2945         MLX5_ASSERT(tbl_data->jump.action);
2946         dev_flow->handle->rix_jump = tbl_data->idx;
2947         dev_flow->dv.jump = &tbl_data->jump;
2948         return 0;
2949 }
2950
2951 /**
2952  * Find existing table port ID resource or create and register a new one.
2953  *
2954  * @param[in, out] dev
2955  *   Pointer to rte_eth_dev structure.
2956  * @param[in, out] resource
2957  *   Pointer to port ID action resource.
2958  * @parm[in, out] dev_flow
2959  *   Pointer to the dev_flow.
2960  * @param[out] error
2961  *   pointer to error structure.
2962  *
2963  * @return
2964  *   0 on success otherwise -errno and errno is set.
2965  */
2966 static int
2967 flow_dv_port_id_action_resource_register
2968                         (struct rte_eth_dev *dev,
2969                          struct mlx5_flow_dv_port_id_action_resource *resource,
2970                          struct mlx5_flow *dev_flow,
2971                          struct rte_flow_error *error)
2972 {
2973         struct mlx5_priv *priv = dev->data->dev_private;
2974         struct mlx5_dev_ctx_shared *sh = priv->sh;
2975         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2976         uint32_t idx = 0;
2977         int ret;
2978
2979         /* Lookup a matching resource from cache. */
2980         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2981                       idx, cache_resource, next) {
2982                 if (resource->port_id == cache_resource->port_id) {
2983                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2984                                 "refcnt %d++",
2985                                 (void *)cache_resource,
2986                                 __atomic_load_n(&cache_resource->refcnt,
2987                                                 __ATOMIC_RELAXED));
2988                         __atomic_fetch_add(&cache_resource->refcnt, 1,
2989                                            __ATOMIC_RELAXED);
2990                         dev_flow->handle->rix_port_id_action = idx;
2991                         dev_flow->dv.port_id_action = cache_resource;
2992                         return 0;
2993                 }
2994         }
2995         /* Register new port id action resource. */
2996         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2997                                        &dev_flow->handle->rix_port_id_action);
2998         if (!cache_resource)
2999                 return rte_flow_error_set(error, ENOMEM,
3000                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3001                                           "cannot allocate resource memory");
3002         *cache_resource = *resource;
3003         ret = mlx5_flow_os_create_flow_action_dest_port
3004                                 (priv->sh->fdb_domain, resource->port_id,
3005                                  &cache_resource->action);
3006         if (ret) {
3007                 mlx5_free(cache_resource);
3008                 return rte_flow_error_set(error, ENOMEM,
3009                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3010                                           NULL, "cannot create action");
3011         }
3012         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
3013         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
3014                      dev_flow->handle->rix_port_id_action, cache_resource,
3015                      next);
3016         dev_flow->dv.port_id_action = cache_resource;
3017         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
3018                 (void *)cache_resource,
3019                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
3020         return 0;
3021 }
3022
3023 /**
3024  * Find existing push vlan resource or create and register a new one.
3025  *
3026  * @param [in, out] dev
3027  *   Pointer to rte_eth_dev structure.
3028  * @param[in, out] resource
3029  *   Pointer to port ID action resource.
3030  * @parm[in, out] dev_flow
3031  *   Pointer to the dev_flow.
3032  * @param[out] error
3033  *   pointer to error structure.
3034  *
3035  * @return
3036  *   0 on success otherwise -errno and errno is set.
3037  */
3038 static int
3039 flow_dv_push_vlan_action_resource_register
3040                        (struct rte_eth_dev *dev,
3041                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3042                         struct mlx5_flow *dev_flow,
3043                         struct rte_flow_error *error)
3044 {
3045         struct mlx5_priv *priv = dev->data->dev_private;
3046         struct mlx5_dev_ctx_shared *sh = priv->sh;
3047         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
3048         struct mlx5dv_dr_domain *domain;
3049         uint32_t idx = 0;
3050         int ret;
3051
3052         /* Lookup a matching resource from cache. */
3053         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3054                       sh->push_vlan_action_list, idx, cache_resource, next) {
3055                 if (resource->vlan_tag == cache_resource->vlan_tag &&
3056                     resource->ft_type == cache_resource->ft_type) {
3057                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
3058                                 "refcnt %d++",
3059                                 (void *)cache_resource,
3060                                 __atomic_load_n(&cache_resource->refcnt,
3061                                                 __ATOMIC_RELAXED));
3062                         __atomic_fetch_add(&cache_resource->refcnt, 1,
3063                                            __ATOMIC_RELAXED);
3064                         dev_flow->handle->dvh.rix_push_vlan = idx;
3065                         dev_flow->dv.push_vlan_res = cache_resource;
3066                         return 0;
3067                 }
3068         }
3069         /* Register new push_vlan action resource. */
3070         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3071                                        &dev_flow->handle->dvh.rix_push_vlan);
3072         if (!cache_resource)
3073                 return rte_flow_error_set(error, ENOMEM,
3074                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3075                                           "cannot allocate resource memory");
3076         *cache_resource = *resource;
3077         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3078                 domain = sh->fdb_domain;
3079         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3080                 domain = sh->rx_domain;
3081         else
3082                 domain = sh->tx_domain;
3083         ret = mlx5_flow_os_create_flow_action_push_vlan
3084                                         (domain, resource->vlan_tag,
3085                                          &cache_resource->action);
3086         if (ret) {
3087                 mlx5_free(cache_resource);
3088                 return rte_flow_error_set(error, ENOMEM,
3089                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3090                                           NULL, "cannot create action");
3091         }
3092         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
3093         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3094                      &sh->push_vlan_action_list,
3095                      dev_flow->handle->dvh.rix_push_vlan,
3096                      cache_resource, next);
3097         dev_flow->dv.push_vlan_res = cache_resource;
3098         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
3099                 (void *)cache_resource,
3100                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
3101         return 0;
3102 }
3103 /**
3104  * Get the size of specific rte_flow_item_type hdr size
3105  *
3106  * @param[in] item_type
3107  *   Tested rte_flow_item_type.
3108  *
3109  * @return
3110  *   sizeof struct item_type, 0 if void or irrelevant.
3111  */
3112 static size_t
3113 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3114 {
3115         size_t retval;
3116
3117         switch (item_type) {
3118         case RTE_FLOW_ITEM_TYPE_ETH:
3119                 retval = sizeof(struct rte_ether_hdr);
3120                 break;
3121         case RTE_FLOW_ITEM_TYPE_VLAN:
3122                 retval = sizeof(struct rte_vlan_hdr);
3123                 break;
3124         case RTE_FLOW_ITEM_TYPE_IPV4:
3125                 retval = sizeof(struct rte_ipv4_hdr);
3126                 break;
3127         case RTE_FLOW_ITEM_TYPE_IPV6:
3128                 retval = sizeof(struct rte_ipv6_hdr);
3129                 break;
3130         case RTE_FLOW_ITEM_TYPE_UDP:
3131                 retval = sizeof(struct rte_udp_hdr);
3132                 break;
3133         case RTE_FLOW_ITEM_TYPE_TCP:
3134                 retval = sizeof(struct rte_tcp_hdr);
3135                 break;
3136         case RTE_FLOW_ITEM_TYPE_VXLAN:
3137         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3138                 retval = sizeof(struct rte_vxlan_hdr);
3139                 break;
3140         case RTE_FLOW_ITEM_TYPE_GRE:
3141         case RTE_FLOW_ITEM_TYPE_NVGRE:
3142                 retval = sizeof(struct rte_gre_hdr);
3143                 break;
3144         case RTE_FLOW_ITEM_TYPE_MPLS:
3145                 retval = sizeof(struct rte_mpls_hdr);
3146                 break;
3147         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3148         default:
3149                 retval = 0;
3150                 break;
3151         }
3152         return retval;
3153 }
3154
3155 #define MLX5_ENCAP_IPV4_VERSION         0x40
3156 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3157 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3158 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3159 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3160 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3161 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3162
3163 /**
3164  * Convert the encap action data from list of rte_flow_item to raw buffer
3165  *
3166  * @param[in] items
3167  *   Pointer to rte_flow_item objects list.
3168  * @param[out] buf
3169  *   Pointer to the output buffer.
3170  * @param[out] size
3171  *   Pointer to the output buffer size.
3172  * @param[out] error
3173  *   Pointer to the error structure.
3174  *
3175  * @return
3176  *   0 on success, a negative errno value otherwise and rte_errno is set.
3177  */
3178 static int
3179 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3180                            size_t *size, struct rte_flow_error *error)
3181 {
3182         struct rte_ether_hdr *eth = NULL;
3183         struct rte_vlan_hdr *vlan = NULL;
3184         struct rte_ipv4_hdr *ipv4 = NULL;
3185         struct rte_ipv6_hdr *ipv6 = NULL;
3186         struct rte_udp_hdr *udp = NULL;
3187         struct rte_vxlan_hdr *vxlan = NULL;
3188         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3189         struct rte_gre_hdr *gre = NULL;
3190         size_t len;
3191         size_t temp_size = 0;
3192
3193         if (!items)
3194                 return rte_flow_error_set(error, EINVAL,
3195                                           RTE_FLOW_ERROR_TYPE_ACTION,
3196                                           NULL, "invalid empty data");
3197         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3198                 len = flow_dv_get_item_hdr_len(items->type);
3199                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3200                         return rte_flow_error_set(error, EINVAL,
3201                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3202                                                   (void *)items->type,
3203                                                   "items total size is too big"
3204                                                   " for encap action");
3205                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3206                 switch (items->type) {
3207                 case RTE_FLOW_ITEM_TYPE_ETH:
3208                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3209                         break;
3210                 case RTE_FLOW_ITEM_TYPE_VLAN:
3211                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3212                         if (!eth)
3213                                 return rte_flow_error_set(error, EINVAL,
3214                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3215                                                 (void *)items->type,
3216                                                 "eth header not found");
3217                         if (!eth->ether_type)
3218                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3219                         break;
3220                 case RTE_FLOW_ITEM_TYPE_IPV4:
3221                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3222                         if (!vlan && !eth)
3223                                 return rte_flow_error_set(error, EINVAL,
3224                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3225                                                 (void *)items->type,
3226                                                 "neither eth nor vlan"
3227                                                 " header found");
3228                         if (vlan && !vlan->eth_proto)
3229                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3230                         else if (eth && !eth->ether_type)
3231                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3232                         if (!ipv4->version_ihl)
3233                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3234                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3235                         if (!ipv4->time_to_live)
3236                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3237                         break;
3238                 case RTE_FLOW_ITEM_TYPE_IPV6:
3239                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3240                         if (!vlan && !eth)
3241                                 return rte_flow_error_set(error, EINVAL,
3242                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3243                                                 (void *)items->type,
3244                                                 "neither eth nor vlan"
3245                                                 " header found");
3246                         if (vlan && !vlan->eth_proto)
3247                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3248                         else if (eth && !eth->ether_type)
3249                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3250                         if (!ipv6->vtc_flow)
3251                                 ipv6->vtc_flow =
3252                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3253                         if (!ipv6->hop_limits)
3254                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3255                         break;
3256                 case RTE_FLOW_ITEM_TYPE_UDP:
3257                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3258                         if (!ipv4 && !ipv6)
3259                                 return rte_flow_error_set(error, EINVAL,
3260                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3261                                                 (void *)items->type,
3262                                                 "ip header not found");
3263                         if (ipv4 && !ipv4->next_proto_id)
3264                                 ipv4->next_proto_id = IPPROTO_UDP;
3265                         else if (ipv6 && !ipv6->proto)
3266                                 ipv6->proto = IPPROTO_UDP;
3267                         break;
3268                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3269                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3270                         if (!udp)
3271                                 return rte_flow_error_set(error, EINVAL,
3272                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3273                                                 (void *)items->type,
3274                                                 "udp header not found");
3275                         if (!udp->dst_port)
3276                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3277                         if (!vxlan->vx_flags)
3278                                 vxlan->vx_flags =
3279                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3280                         break;
3281                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3282                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3283                         if (!udp)
3284                                 return rte_flow_error_set(error, EINVAL,
3285                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3286                                                 (void *)items->type,
3287                                                 "udp header not found");
3288                         if (!vxlan_gpe->proto)
3289                                 return rte_flow_error_set(error, EINVAL,
3290                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3291                                                 (void *)items->type,
3292                                                 "next protocol not found");
3293                         if (!udp->dst_port)
3294                                 udp->dst_port =
3295                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3296                         if (!vxlan_gpe->vx_flags)
3297                                 vxlan_gpe->vx_flags =
3298                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3299                         break;
3300                 case RTE_FLOW_ITEM_TYPE_GRE:
3301                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3302                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3303                         if (!gre->proto)
3304                                 return rte_flow_error_set(error, EINVAL,
3305                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3306                                                 (void *)items->type,
3307                                                 "next protocol not found");
3308                         if (!ipv4 && !ipv6)
3309                                 return rte_flow_error_set(error, EINVAL,
3310                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3311                                                 (void *)items->type,
3312                                                 "ip header not found");
3313                         if (ipv4 && !ipv4->next_proto_id)
3314                                 ipv4->next_proto_id = IPPROTO_GRE;
3315                         else if (ipv6 && !ipv6->proto)
3316                                 ipv6->proto = IPPROTO_GRE;
3317                         break;
3318                 case RTE_FLOW_ITEM_TYPE_VOID:
3319                         break;
3320                 default:
3321                         return rte_flow_error_set(error, EINVAL,
3322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3323                                                   (void *)items->type,
3324                                                   "unsupported item type");
3325                         break;
3326                 }
3327                 temp_size += len;
3328         }
3329         *size = temp_size;
3330         return 0;
3331 }
3332
3333 static int
3334 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3335 {
3336         struct rte_ether_hdr *eth = NULL;
3337         struct rte_vlan_hdr *vlan = NULL;
3338         struct rte_ipv6_hdr *ipv6 = NULL;
3339         struct rte_udp_hdr *udp = NULL;
3340         char *next_hdr;
3341         uint16_t proto;
3342
3343         eth = (struct rte_ether_hdr *)data;
3344         next_hdr = (char *)(eth + 1);
3345         proto = RTE_BE16(eth->ether_type);
3346
3347         /* VLAN skipping */
3348         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3349                 vlan = (struct rte_vlan_hdr *)next_hdr;
3350                 proto = RTE_BE16(vlan->eth_proto);
3351                 next_hdr += sizeof(struct rte_vlan_hdr);
3352         }
3353
3354         /* HW calculates IPv4 csum. no need to proceed */
3355         if (proto == RTE_ETHER_TYPE_IPV4)
3356                 return 0;
3357
3358         /* non IPv4/IPv6 header. not supported */
3359         if (proto != RTE_ETHER_TYPE_IPV6) {
3360                 return rte_flow_error_set(error, ENOTSUP,
3361                                           RTE_FLOW_ERROR_TYPE_ACTION,
3362                                           NULL, "Cannot offload non IPv4/IPv6");
3363         }
3364
3365         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3366
3367         /* ignore non UDP */
3368         if (ipv6->proto != IPPROTO_UDP)
3369                 return 0;
3370
3371         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3372         udp->dgram_cksum = 0;
3373
3374         return 0;
3375 }
3376
3377 /**
3378  * Convert L2 encap action to DV specification.
3379  *
3380  * @param[in] dev
3381  *   Pointer to rte_eth_dev structure.
3382  * @param[in] action
3383  *   Pointer to action structure.
3384  * @param[in, out] dev_flow
3385  *   Pointer to the mlx5_flow.
3386  * @param[in] transfer
3387  *   Mark if the flow is E-Switch flow.
3388  * @param[out] error
3389  *   Pointer to the error structure.
3390  *
3391  * @return
3392  *   0 on success, a negative errno value otherwise and rte_errno is set.
3393  */
3394 static int
3395 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3396                                const struct rte_flow_action *action,
3397                                struct mlx5_flow *dev_flow,
3398                                uint8_t transfer,
3399                                struct rte_flow_error *error)
3400 {
3401         const struct rte_flow_item *encap_data;
3402         const struct rte_flow_action_raw_encap *raw_encap_data;
3403         struct mlx5_flow_dv_encap_decap_resource res = {
3404                 .reformat_type =
3405                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3406                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3407                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3408         };
3409
3410         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3411                 raw_encap_data =
3412                         (const struct rte_flow_action_raw_encap *)action->conf;
3413                 res.size = raw_encap_data->size;
3414                 memcpy(res.buf, raw_encap_data->data, res.size);
3415         } else {
3416                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3417                         encap_data =
3418                                 ((const struct rte_flow_action_vxlan_encap *)
3419                                                 action->conf)->definition;
3420                 else
3421                         encap_data =
3422                                 ((const struct rte_flow_action_nvgre_encap *)
3423                                                 action->conf)->definition;
3424                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3425                                                &res.size, error))
3426                         return -rte_errno;
3427         }
3428         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3429                 return -rte_errno;
3430         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3431                 return rte_flow_error_set(error, EINVAL,
3432                                           RTE_FLOW_ERROR_TYPE_ACTION,
3433                                           NULL, "can't create L2 encap action");
3434         return 0;
3435 }
3436
3437 /**
3438  * Convert L2 decap action to DV specification.
3439  *
3440  * @param[in] dev
3441  *   Pointer to rte_eth_dev structure.
3442  * @param[in, out] dev_flow
3443  *   Pointer to the mlx5_flow.
3444  * @param[in] transfer
3445  *   Mark if the flow is E-Switch flow.
3446  * @param[out] error
3447  *   Pointer to the error structure.
3448  *
3449  * @return
3450  *   0 on success, a negative errno value otherwise and rte_errno is set.
3451  */
3452 static int
3453 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3454                                struct mlx5_flow *dev_flow,
3455                                uint8_t transfer,
3456                                struct rte_flow_error *error)
3457 {
3458         struct mlx5_flow_dv_encap_decap_resource res = {
3459                 .size = 0,
3460                 .reformat_type =
3461                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3462                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3463                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3464         };
3465
3466         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3467                 return rte_flow_error_set(error, EINVAL,
3468                                           RTE_FLOW_ERROR_TYPE_ACTION,
3469                                           NULL, "can't create L2 decap action");
3470         return 0;
3471 }
3472
3473 /**
3474  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3475  *
3476  * @param[in] dev
3477  *   Pointer to rte_eth_dev structure.
3478  * @param[in] action
3479  *   Pointer to action structure.
3480  * @param[in, out] dev_flow
3481  *   Pointer to the mlx5_flow.
3482  * @param[in] attr
3483  *   Pointer to the flow attributes.
3484  * @param[out] error
3485  *   Pointer to the error structure.
3486  *
3487  * @return
3488  *   0 on success, a negative errno value otherwise and rte_errno is set.
3489  */
3490 static int
3491 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3492                                 const struct rte_flow_action *action,
3493                                 struct mlx5_flow *dev_flow,
3494                                 const struct rte_flow_attr *attr,
3495                                 struct rte_flow_error *error)
3496 {
3497         const struct rte_flow_action_raw_encap *encap_data;
3498         struct mlx5_flow_dv_encap_decap_resource res;
3499
3500         memset(&res, 0, sizeof(res));
3501         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3502         res.size = encap_data->size;
3503         memcpy(res.buf, encap_data->data, res.size);
3504         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3505                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3506                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3507         if (attr->transfer)
3508                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3509         else
3510                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3511                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3512         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3513                 return rte_flow_error_set(error, EINVAL,
3514                                           RTE_FLOW_ERROR_TYPE_ACTION,
3515                                           NULL, "can't create encap action");
3516         return 0;
3517 }
3518
3519 /**
3520  * Create action push VLAN.
3521  *
3522  * @param[in] dev
3523  *   Pointer to rte_eth_dev structure.
3524  * @param[in] attr
3525  *   Pointer to the flow attributes.
3526  * @param[in] vlan
3527  *   Pointer to the vlan to push to the Ethernet header.
3528  * @param[in, out] dev_flow
3529  *   Pointer to the mlx5_flow.
3530  * @param[out] error
3531  *   Pointer to the error structure.
3532  *
3533  * @return
3534  *   0 on success, a negative errno value otherwise and rte_errno is set.
3535  */
3536 static int
3537 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3538                                 const struct rte_flow_attr *attr,
3539                                 const struct rte_vlan_hdr *vlan,
3540                                 struct mlx5_flow *dev_flow,
3541                                 struct rte_flow_error *error)
3542 {
3543         struct mlx5_flow_dv_push_vlan_action_resource res;
3544
3545         memset(&res, 0, sizeof(res));
3546         res.vlan_tag =
3547                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3548                                  vlan->vlan_tci);
3549         if (attr->transfer)
3550                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3551         else
3552                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3553                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3554         return flow_dv_push_vlan_action_resource_register
3555                                             (dev, &res, dev_flow, error);
3556 }
3557
3558 static int fdb_mirror;
3559
3560 /**
3561  * Validate the modify-header actions.
3562  *
3563  * @param[in] action_flags
3564  *   Holds the actions detected until now.
3565  * @param[in] action
3566  *   Pointer to the modify action.
3567  * @param[out] error
3568  *   Pointer to error structure.
3569  *
3570  * @return
3571  *   0 on success, a negative errno value otherwise and rte_errno is set.
3572  */
3573 static int
3574 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3575                                    const struct rte_flow_action *action,
3576                                    struct rte_flow_error *error)
3577 {
3578         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3579                 return rte_flow_error_set(error, EINVAL,
3580                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3581                                           NULL, "action configuration not set");
3582         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3583                 return rte_flow_error_set(error, EINVAL,
3584                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3585                                           "can't have encap action before"
3586                                           " modify action");
3587         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3588                 return rte_flow_error_set(error, EINVAL,
3589                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3590                                           "can't support sample action before"
3591                                           " modify action for E-Switch"
3592                                           " mirroring");
3593         return 0;
3594 }
3595
3596 /**
3597  * Validate the modify-header MAC address actions.
3598  *
3599  * @param[in] action_flags
3600  *   Holds the actions detected until now.
3601  * @param[in] action
3602  *   Pointer to the modify action.
3603  * @param[in] item_flags
3604  *   Holds the items detected.
3605  * @param[out] error
3606  *   Pointer to error structure.
3607  *
3608  * @return
3609  *   0 on success, a negative errno value otherwise and rte_errno is set.
3610  */
3611 static int
3612 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3613                                    const struct rte_flow_action *action,
3614                                    const uint64_t item_flags,
3615                                    struct rte_flow_error *error)
3616 {
3617         int ret = 0;
3618
3619         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3620         if (!ret) {
3621                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3622                         return rte_flow_error_set(error, EINVAL,
3623                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3624                                                   NULL,
3625                                                   "no L2 item in pattern");
3626         }
3627         return ret;
3628 }
3629
3630 /**
3631  * Validate the modify-header IPv4 address actions.
3632  *
3633  * @param[in] action_flags
3634  *   Holds the actions detected until now.
3635  * @param[in] action
3636  *   Pointer to the modify action.
3637  * @param[in] item_flags
3638  *   Holds the items detected.
3639  * @param[out] error
3640  *   Pointer to error structure.
3641  *
3642  * @return
3643  *   0 on success, a negative errno value otherwise and rte_errno is set.
3644  */
3645 static int
3646 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3647                                     const struct rte_flow_action *action,
3648                                     const uint64_t item_flags,
3649                                     struct rte_flow_error *error)
3650 {
3651         int ret = 0;
3652         uint64_t layer;
3653
3654         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3655         if (!ret) {
3656                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3657                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3658                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3659                 if (!(item_flags & layer))
3660                         return rte_flow_error_set(error, EINVAL,
3661                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3662                                                   NULL,
3663                                                   "no ipv4 item in pattern");
3664         }
3665         return ret;
3666 }
3667
3668 /**
3669  * Validate the modify-header IPv6 address actions.
3670  *
3671  * @param[in] action_flags
3672  *   Holds the actions detected until now.
3673  * @param[in] action
3674  *   Pointer to the modify action.
3675  * @param[in] item_flags
3676  *   Holds the items detected.
3677  * @param[out] error
3678  *   Pointer to error structure.
3679  *
3680  * @return
3681  *   0 on success, a negative errno value otherwise and rte_errno is set.
3682  */
3683 static int
3684 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3685                                     const struct rte_flow_action *action,
3686                                     const uint64_t item_flags,
3687                                     struct rte_flow_error *error)
3688 {
3689         int ret = 0;
3690         uint64_t layer;
3691
3692         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3693         if (!ret) {
3694                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3695                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3696                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3697                 if (!(item_flags & layer))
3698                         return rte_flow_error_set(error, EINVAL,
3699                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3700                                                   NULL,
3701                                                   "no ipv6 item in pattern");
3702         }
3703         return ret;
3704 }
3705
3706 /**
3707  * Validate the modify-header TP actions.
3708  *
3709  * @param[in] action_flags
3710  *   Holds the actions detected until now.
3711  * @param[in] action
3712  *   Pointer to the modify action.
3713  * @param[in] item_flags
3714  *   Holds the items detected.
3715  * @param[out] error
3716  *   Pointer to error structure.
3717  *
3718  * @return
3719  *   0 on success, a negative errno value otherwise and rte_errno is set.
3720  */
3721 static int
3722 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3723                                   const struct rte_flow_action *action,
3724                                   const uint64_t item_flags,
3725                                   struct rte_flow_error *error)
3726 {
3727         int ret = 0;
3728         uint64_t layer;
3729
3730         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3731         if (!ret) {
3732                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3733                                  MLX5_FLOW_LAYER_INNER_L4 :
3734                                  MLX5_FLOW_LAYER_OUTER_L4;
3735                 if (!(item_flags & layer))
3736                         return rte_flow_error_set(error, EINVAL,
3737                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3738                                                   NULL, "no transport layer "
3739                                                   "in pattern");
3740         }
3741         return ret;
3742 }
3743
3744 /**
3745  * Validate the modify-header actions of increment/decrement
3746  * TCP Sequence-number.
3747  *
3748  * @param[in] action_flags
3749  *   Holds the actions detected until now.
3750  * @param[in] action
3751  *   Pointer to the modify action.
3752  * @param[in] item_flags
3753  *   Holds the items detected.
3754  * @param[out] error
3755  *   Pointer to error structure.
3756  *
3757  * @return
3758  *   0 on success, a negative errno value otherwise and rte_errno is set.
3759  */
3760 static int
3761 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3762                                        const struct rte_flow_action *action,
3763                                        const uint64_t item_flags,
3764                                        struct rte_flow_error *error)
3765 {
3766         int ret = 0;
3767         uint64_t layer;
3768
3769         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3770         if (!ret) {
3771                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3772                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3773                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3774                 if (!(item_flags & layer))
3775                         return rte_flow_error_set(error, EINVAL,
3776                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3777                                                   NULL, "no TCP item in"
3778                                                   " pattern");
3779                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3780                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3781                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3782                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3783                         return rte_flow_error_set(error, EINVAL,
3784                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3785                                                   NULL,
3786                                                   "cannot decrease and increase"
3787                                                   " TCP sequence number"
3788                                                   " at the same time");
3789         }
3790         return ret;
3791 }
3792
3793 /**
3794  * Validate the modify-header actions of increment/decrement
3795  * TCP Acknowledgment number.
3796  *
3797  * @param[in] action_flags
3798  *   Holds the actions detected until now.
3799  * @param[in] action
3800  *   Pointer to the modify action.
3801  * @param[in] item_flags
3802  *   Holds the items detected.
3803  * @param[out] error
3804  *   Pointer to error structure.
3805  *
3806  * @return
3807  *   0 on success, a negative errno value otherwise and rte_errno is set.
3808  */
3809 static int
3810 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3811                                        const struct rte_flow_action *action,
3812                                        const uint64_t item_flags,
3813                                        struct rte_flow_error *error)
3814 {
3815         int ret = 0;
3816         uint64_t layer;
3817
3818         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3819         if (!ret) {
3820                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3821                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3822                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3823                 if (!(item_flags & layer))
3824                         return rte_flow_error_set(error, EINVAL,
3825                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3826                                                   NULL, "no TCP item in"
3827                                                   " pattern");
3828                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3829                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3830                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3831                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3832                         return rte_flow_error_set(error, EINVAL,
3833                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3834                                                   NULL,
3835                                                   "cannot decrease and increase"
3836                                                   " TCP acknowledgment number"
3837                                                   " at the same time");
3838         }
3839         return ret;
3840 }
3841
3842 /**
3843  * Validate the modify-header TTL actions.
3844  *
3845  * @param[in] action_flags
3846  *   Holds the actions detected until now.
3847  * @param[in] action
3848  *   Pointer to the modify action.
3849  * @param[in] item_flags
3850  *   Holds the items detected.
3851  * @param[out] error
3852  *   Pointer to error structure.
3853  *
3854  * @return
3855  *   0 on success, a negative errno value otherwise and rte_errno is set.
3856  */
3857 static int
3858 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3859                                    const struct rte_flow_action *action,
3860                                    const uint64_t item_flags,
3861                                    struct rte_flow_error *error)
3862 {
3863         int ret = 0;
3864         uint64_t layer;
3865
3866         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3867         if (!ret) {
3868                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3869                                  MLX5_FLOW_LAYER_INNER_L3 :
3870                                  MLX5_FLOW_LAYER_OUTER_L3;
3871                 if (!(item_flags & layer))
3872                         return rte_flow_error_set(error, EINVAL,
3873                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                   NULL,
3875                                                   "no IP protocol in pattern");
3876         }
3877         return ret;
3878 }
3879
3880 /**
3881  * Validate jump action.
3882  *
3883  * @param[in] action
3884  *   Pointer to the jump action.
3885  * @param[in] action_flags
3886  *   Holds the actions detected until now.
3887  * @param[in] attributes
3888  *   Pointer to flow attributes
3889  * @param[in] external
3890  *   Action belongs to flow rule created by request external to PMD.
3891  * @param[out] error
3892  *   Pointer to error structure.
3893  *
3894  * @return
3895  *   0 on success, a negative errno value otherwise and rte_errno is set.
3896  */
3897 static int
3898 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3899                              const struct mlx5_flow_tunnel *tunnel,
3900                              const struct rte_flow_action *action,
3901                              uint64_t action_flags,
3902                              const struct rte_flow_attr *attributes,
3903                              bool external, struct rte_flow_error *error)
3904 {
3905         uint32_t target_group, table;
3906         int ret = 0;
3907         struct flow_grp_info grp_info = {
3908                 .external = !!external,
3909                 .transfer = !!attributes->transfer,
3910                 .fdb_def_rule = 1,
3911                 .std_tbl_fix = 0
3912         };
3913         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3914                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3915                 return rte_flow_error_set(error, EINVAL,
3916                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3917                                           "can't have 2 fate actions in"
3918                                           " same flow");
3919         if (action_flags & MLX5_FLOW_ACTION_METER)
3920                 return rte_flow_error_set(error, ENOTSUP,
3921                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3922                                           "jump with meter not support");
3923         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3924                 return rte_flow_error_set(error, EINVAL,
3925                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3926                                           "E-Switch mirroring can't support"
3927                                           " Sample action and jump action in"
3928                                           " same flow now");
3929         if (!action->conf)
3930                 return rte_flow_error_set(error, EINVAL,
3931                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3932                                           NULL, "action configuration not set");
3933         target_group =
3934                 ((const struct rte_flow_action_jump *)action->conf)->group;
3935         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3936                                        grp_info, error);
3937         if (ret)
3938                 return ret;
3939         if (attributes->group == target_group &&
3940             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3941                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3942                 return rte_flow_error_set(error, EINVAL,
3943                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3944                                           "target group must be other than"
3945                                           " the current flow group");
3946         return 0;
3947 }
3948
3949 /*
3950  * Validate the port_id action.
3951  *
3952  * @param[in] dev
3953  *   Pointer to rte_eth_dev structure.
3954  * @param[in] action_flags
3955  *   Bit-fields that holds the actions detected until now.
3956  * @param[in] action
3957  *   Port_id RTE action structure.
3958  * @param[in] attr
3959  *   Attributes of flow that includes this action.
3960  * @param[out] error
3961  *   Pointer to error structure.
3962  *
3963  * @return
3964  *   0 on success, a negative errno value otherwise and rte_errno is set.
3965  */
3966 static int
3967 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3968                                 uint64_t action_flags,
3969                                 const struct rte_flow_action *action,
3970                                 const struct rte_flow_attr *attr,
3971                                 struct rte_flow_error *error)
3972 {
3973         const struct rte_flow_action_port_id *port_id;
3974         struct mlx5_priv *act_priv;
3975         struct mlx5_priv *dev_priv;
3976         uint16_t port;
3977
3978         if (!attr->transfer)
3979                 return rte_flow_error_set(error, ENOTSUP,
3980                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3981                                           NULL,
3982                                           "port id action is valid in transfer"
3983                                           " mode only");
3984         if (!action || !action->conf)
3985                 return rte_flow_error_set(error, ENOTSUP,
3986                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3987                                           NULL,
3988                                           "port id action parameters must be"
3989                                           " specified");
3990         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3991                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3992                 return rte_flow_error_set(error, EINVAL,
3993                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3994                                           "can have only one fate actions in"
3995                                           " a flow");
3996         dev_priv = mlx5_dev_to_eswitch_info(dev);
3997         if (!dev_priv)
3998                 return rte_flow_error_set(error, rte_errno,
3999                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4000                                           NULL,
4001                                           "failed to obtain E-Switch info");
4002         port_id = action->conf;
4003         port = port_id->original ? dev->data->port_id : port_id->id;
4004         act_priv = mlx5_port_to_eswitch_info(port, false);
4005         if (!act_priv)
4006                 return rte_flow_error_set
4007                                 (error, rte_errno,
4008                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4009                                  "failed to obtain E-Switch port id for port");
4010         if (act_priv->domain_id != dev_priv->domain_id)
4011                 return rte_flow_error_set
4012                                 (error, EINVAL,
4013                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4014                                  "port does not belong to"
4015                                  " E-Switch being configured");
4016         return 0;
4017 }
4018
4019 /**
4020  * Get the maximum number of modify header actions.
4021  *
4022  * @param dev
4023  *   Pointer to rte_eth_dev structure.
4024  * @param flags
4025  *   Flags bits to check if root level.
4026  *
4027  * @return
4028  *   Max number of modify header actions device can support.
4029  */
4030 static inline unsigned int
4031 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4032                               uint64_t flags)
4033 {
4034         /*
4035          * There's no way to directly query the max capacity from FW.
4036          * The maximal value on root table should be assumed to be supported.
4037          */
4038         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4039                 return MLX5_MAX_MODIFY_NUM;
4040         else
4041                 return MLX5_ROOT_TBL_MODIFY_NUM;
4042 }
4043
4044 /**
4045  * Validate the meter action.
4046  *
4047  * @param[in] dev
4048  *   Pointer to rte_eth_dev structure.
4049  * @param[in] action_flags
4050  *   Bit-fields that holds the actions detected until now.
4051  * @param[in] action
4052  *   Pointer to the meter action.
4053  * @param[in] attr
4054  *   Attributes of flow that includes this action.
4055  * @param[out] error
4056  *   Pointer to error structure.
4057  *
4058  * @return
4059  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4060  */
4061 static int
4062 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4063                                 uint64_t action_flags,
4064                                 const struct rte_flow_action *action,
4065                                 const struct rte_flow_attr *attr,
4066                                 struct rte_flow_error *error)
4067 {
4068         struct mlx5_priv *priv = dev->data->dev_private;
4069         const struct rte_flow_action_meter *am = action->conf;
4070         struct mlx5_flow_meter *fm;
4071
4072         if (!am)
4073                 return rte_flow_error_set(error, EINVAL,
4074                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4075                                           "meter action conf is NULL");
4076
4077         if (action_flags & MLX5_FLOW_ACTION_METER)
4078                 return rte_flow_error_set(error, ENOTSUP,
4079                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4080                                           "meter chaining not support");
4081         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4082                 return rte_flow_error_set(error, ENOTSUP,
4083                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4084                                           "meter with jump not support");
4085         if (!priv->mtr_en)
4086                 return rte_flow_error_set(error, ENOTSUP,
4087                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4088                                           NULL,
4089                                           "meter action not supported");
4090         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4091         if (!fm)
4092                 return rte_flow_error_set(error, EINVAL,
4093                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4094                                           "Meter not found");
4095         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4096               (!fm->ingress && !attr->ingress && attr->egress) ||
4097               (!fm->egress && !attr->egress && attr->ingress))))
4098                 return rte_flow_error_set(error, EINVAL,
4099                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4100                                           "Flow attributes are either invalid "
4101                                           "or have a conflict with current "
4102                                           "meter attributes");
4103         return 0;
4104 }
4105
4106 /**
4107  * Validate the age action.
4108  *
4109  * @param[in] action_flags
4110  *   Holds the actions detected until now.
4111  * @param[in] action
4112  *   Pointer to the age action.
4113  * @param[in] dev
4114  *   Pointer to the Ethernet device structure.
4115  * @param[out] error
4116  *   Pointer to error structure.
4117  *
4118  * @return
4119  *   0 on success, a negative errno value otherwise and rte_errno is set.
4120  */
4121 static int
4122 flow_dv_validate_action_age(uint64_t action_flags,
4123                             const struct rte_flow_action *action,
4124                             struct rte_eth_dev *dev,
4125                             struct rte_flow_error *error)
4126 {
4127         struct mlx5_priv *priv = dev->data->dev_private;
4128         const struct rte_flow_action_age *age = action->conf;
4129
4130         if (!priv->config.devx || priv->sh->cmng.counter_fallback)
4131                 return rte_flow_error_set(error, ENOTSUP,
4132                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4133                                           NULL,
4134                                           "age action not supported");
4135         if (!(action->conf))
4136                 return rte_flow_error_set(error, EINVAL,
4137                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4138                                           "configuration cannot be null");
4139         if (!(age->timeout))
4140                 return rte_flow_error_set(error, EINVAL,
4141                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4142                                           "invalid timeout value 0");
4143         if (action_flags & MLX5_FLOW_ACTION_AGE)
4144                 return rte_flow_error_set(error, EINVAL,
4145                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4146                                           "duplicate age actions set");
4147         return 0;
4148 }
4149
4150 /**
4151  * Validate the modify-header IPv4 DSCP actions.
4152  *
4153  * @param[in] action_flags
4154  *   Holds the actions detected until now.
4155  * @param[in] action
4156  *   Pointer to the modify action.
4157  * @param[in] item_flags
4158  *   Holds the items detected.
4159  * @param[out] error
4160  *   Pointer to error structure.
4161  *
4162  * @return
4163  *   0 on success, a negative errno value otherwise and rte_errno is set.
4164  */
4165 static int
4166 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4167                                          const struct rte_flow_action *action,
4168                                          const uint64_t item_flags,
4169                                          struct rte_flow_error *error)
4170 {
4171         int ret = 0;
4172
4173         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4174         if (!ret) {
4175                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4176                         return rte_flow_error_set(error, EINVAL,
4177                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4178                                                   NULL,
4179                                                   "no ipv4 item in pattern");
4180         }
4181         return ret;
4182 }
4183
4184 /**
4185  * Validate the modify-header IPv6 DSCP actions.
4186  *
4187  * @param[in] action_flags
4188  *   Holds the actions detected until now.
4189  * @param[in] action
4190  *   Pointer to the modify action.
4191  * @param[in] item_flags
4192  *   Holds the items detected.
4193  * @param[out] error
4194  *   Pointer to error structure.
4195  *
4196  * @return
4197  *   0 on success, a negative errno value otherwise and rte_errno is set.
4198  */
4199 static int
4200 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4201                                          const struct rte_flow_action *action,
4202                                          const uint64_t item_flags,
4203                                          struct rte_flow_error *error)
4204 {
4205         int ret = 0;
4206
4207         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4208         if (!ret) {
4209                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4210                         return rte_flow_error_set(error, EINVAL,
4211                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4212                                                   NULL,
4213                                                   "no ipv6 item in pattern");
4214         }
4215         return ret;
4216 }
4217
4218 /**
4219  * Match modify-header resource.
4220  *
4221  * @param entry
4222  *   Pointer to exist resource entry object.
4223  * @param ctx
4224  *   Pointer to new modify-header resource.
4225  *
4226  * @return
4227  *   0 on matching, -1 otherwise.
4228  */
4229 static int
4230 flow_dv_modify_hdr_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
4231 {
4232         struct mlx5_flow_dv_modify_hdr_resource *resource;
4233         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4234         uint32_t actions_len;
4235
4236         resource = (struct mlx5_flow_dv_modify_hdr_resource *)ctx;
4237         cache_resource = container_of(entry,
4238                                       struct mlx5_flow_dv_modify_hdr_resource,
4239                                       entry);
4240         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4241         if (resource->entry.key == cache_resource->entry.key &&
4242             resource->ft_type == cache_resource->ft_type &&
4243             resource->actions_num == cache_resource->actions_num &&
4244             resource->flags == cache_resource->flags &&
4245             !memcmp((const void *)resource->actions,
4246                     (const void *)cache_resource->actions,
4247                     actions_len))
4248                 return 0;
4249         return -1;
4250 }
4251
4252 /**
4253  * Validate the sample action.
4254  *
4255  * @param[in] action_flags
4256  *   Holds the actions detected until now.
4257  * @param[in] action
4258  *   Pointer to the sample action.
4259  * @param[in] dev
4260  *   Pointer to the Ethernet device structure.
4261  * @param[in] attr
4262  *   Attributes of flow that includes this action.
4263  * @param[out] error
4264  *   Pointer to error structure.
4265  *
4266  * @return
4267  *   0 on success, a negative errno value otherwise and rte_errno is set.
4268  */
4269 static int
4270 flow_dv_validate_action_sample(uint64_t action_flags,
4271                                const struct rte_flow_action *action,
4272                                struct rte_eth_dev *dev,
4273                                const struct rte_flow_attr *attr,
4274                                struct rte_flow_error *error)
4275 {
4276         struct mlx5_priv *priv = dev->data->dev_private;
4277         struct mlx5_dev_config *dev_conf = &priv->config;
4278         const struct rte_flow_action_sample *sample = action->conf;
4279         const struct rte_flow_action *act;
4280         uint64_t sub_action_flags = 0;
4281         uint16_t queue_index = 0xFFFF;
4282         int actions_n = 0;
4283         int ret;
4284         fdb_mirror = 0;
4285
4286         if (!sample)
4287                 return rte_flow_error_set(error, EINVAL,
4288                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4289                                           "configuration cannot be NULL");
4290         if (sample->ratio == 0)
4291                 return rte_flow_error_set(error, EINVAL,
4292                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4293                                           "ratio value starts from 1");
4294         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4295                 return rte_flow_error_set(error, ENOTSUP,
4296                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4297                                           NULL,
4298                                           "sample action not supported");
4299         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4300                 return rte_flow_error_set(error, EINVAL,
4301                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4302                                           "Multiple sample actions not "
4303                                           "supported");
4304         if (action_flags & MLX5_FLOW_ACTION_METER)
4305                 return rte_flow_error_set(error, EINVAL,
4306                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4307                                           "wrong action order, meter should "
4308                                           "be after sample action");
4309         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4310                 return rte_flow_error_set(error, EINVAL,
4311                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4312                                           "wrong action order, jump should "
4313                                           "be after sample action");
4314         act = sample->actions;
4315         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4316                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4317                         return rte_flow_error_set(error, ENOTSUP,
4318                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4319                                                   act, "too many actions");
4320                 switch (act->type) {
4321                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4322                         ret = mlx5_flow_validate_action_queue(act,
4323                                                               sub_action_flags,
4324                                                               dev,
4325                                                               attr, error);
4326                         if (ret < 0)
4327                                 return ret;
4328                         queue_index = ((const struct rte_flow_action_queue *)
4329                                                         (act->conf))->index;
4330                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4331                         ++actions_n;
4332                         break;
4333                 case RTE_FLOW_ACTION_TYPE_MARK:
4334                         ret = flow_dv_validate_action_mark(dev, act,
4335                                                            sub_action_flags,
4336                                                            attr, error);
4337                         if (ret < 0)
4338                                 return ret;
4339                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4340                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4341                                                 MLX5_FLOW_ACTION_MARK_EXT;
4342                         else
4343                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4344                         ++actions_n;
4345                         break;
4346                 case RTE_FLOW_ACTION_TYPE_COUNT:
4347                         ret = flow_dv_validate_action_count(dev, error);
4348                         if (ret < 0)
4349                                 return ret;
4350                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4351                         ++actions_n;
4352                         break;
4353                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4354                         ret = flow_dv_validate_action_port_id(dev,
4355                                                               sub_action_flags,
4356                                                               act,
4357                                                               attr,
4358                                                               error);
4359                         if (ret)
4360                                 return ret;
4361                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4362                         ++actions_n;
4363                         break;
4364                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4365                         ret = flow_dv_validate_action_raw_encap_decap
4366                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4367                                  &actions_n, error);
4368                         if (ret < 0)
4369                                 return ret;
4370                         ++actions_n;
4371                         break;
4372                 default:
4373                         return rte_flow_error_set(error, ENOTSUP,
4374                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4375                                                   NULL,
4376                                                   "Doesn't support optional "
4377                                                   "action");
4378                 }
4379         }
4380         if (attr->ingress && !attr->transfer) {
4381                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4382                         return rte_flow_error_set(error, EINVAL,
4383                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4384                                                   NULL,
4385                                                   "Ingress must has a dest "
4386                                                   "QUEUE for Sample");
4387         } else if (attr->egress && !attr->transfer) {
4388                 return rte_flow_error_set(error, ENOTSUP,
4389                                           RTE_FLOW_ERROR_TYPE_ACTION,
4390                                           NULL,
4391                                           "Sample Only support Ingress "
4392                                           "or E-Switch");
4393         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4394                 MLX5_ASSERT(attr->transfer);
4395                 if (sample->ratio > 1)
4396                         return rte_flow_error_set(error, ENOTSUP,
4397                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4398                                                   NULL,
4399                                                   "E-Switch doesn't support "
4400                                                   "any optional action "
4401                                                   "for sampling");
4402                 fdb_mirror = 1;
4403                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4404                         return rte_flow_error_set(error, ENOTSUP,
4405                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4406                                                   NULL,
4407                                                   "unsupported action QUEUE");
4408                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4409                         return rte_flow_error_set(error, EINVAL,
4410                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4411                                                   NULL,
4412                                                   "E-Switch must has a dest "
4413                                                   "port for mirroring");
4414         }
4415         /* Continue validation for Xcap actions.*/
4416         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4417             (queue_index == 0xFFFF ||
4418              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4419                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4420                      MLX5_FLOW_XCAP_ACTIONS)
4421                         return rte_flow_error_set(error, ENOTSUP,
4422                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4423                                                   NULL, "encap and decap "
4424                                                   "combination aren't "
4425                                                   "supported");
4426                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4427                                                         MLX5_FLOW_ACTION_ENCAP))
4428                         return rte_flow_error_set(error, ENOTSUP,
4429                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4430                                                   NULL, "encap is not supported"
4431                                                   " for ingress traffic");
4432         }
4433         return 0;
4434 }
4435
4436 /**
4437  * Find existing modify-header resource or create and register a new one.
4438  *
4439  * @param dev[in, out]
4440  *   Pointer to rte_eth_dev structure.
4441  * @param[in, out] resource
4442  *   Pointer to modify-header resource.
4443  * @parm[in, out] dev_flow
4444  *   Pointer to the dev_flow.
4445  * @param[out] error
4446  *   pointer to error structure.
4447  *
4448  * @return
4449  *   0 on success otherwise -errno and errno is set.
4450  */
4451 static int
4452 flow_dv_modify_hdr_resource_register
4453                         (struct rte_eth_dev *dev,
4454                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4455                          struct mlx5_flow *dev_flow,
4456                          struct rte_flow_error *error)
4457 {
4458         struct mlx5_priv *priv = dev->data->dev_private;
4459         struct mlx5_dev_ctx_shared *sh = priv->sh;
4460         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4461         struct mlx5dv_dr_domain *ns;
4462         uint32_t actions_len;
4463         struct mlx5_hlist_entry *entry;
4464         union mlx5_flow_modify_hdr_key hdr_mod_key = {
4465                 {
4466                         .ft_type = resource->ft_type,
4467                         .actions_num = resource->actions_num,
4468                         .group = dev_flow->dv.group,
4469                         .cksum = 0,
4470                 }
4471         };
4472         int ret;
4473
4474         resource->flags = dev_flow->dv.group ? 0 :
4475                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4476         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4477                                     resource->flags))
4478                 return rte_flow_error_set(error, EOVERFLOW,
4479                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4480                                           "too many modify header items");
4481         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4482                 ns = sh->fdb_domain;
4483         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4484                 ns = sh->tx_domain;
4485         else
4486                 ns = sh->rx_domain;
4487         /* Lookup a matching resource from cache. */
4488         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4489         hdr_mod_key.cksum = __rte_raw_cksum(resource->actions, actions_len, 0);
4490         resource->entry.key = hdr_mod_key.v64;
4491         entry = mlx5_hlist_lookup_ex(sh->modify_cmds, resource->entry.key,
4492                                      flow_dv_modify_hdr_resource_match,
4493                                      (void *)resource);
4494         if (entry) {
4495                 cache_resource = container_of(entry,
4496                                         struct mlx5_flow_dv_modify_hdr_resource,
4497                                         entry);
4498                 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4499                         (void *)cache_resource,
4500                         __atomic_load_n(&cache_resource->refcnt,
4501                                         __ATOMIC_RELAXED));
4502                 __atomic_fetch_add(&cache_resource->refcnt, 1,
4503                                    __ATOMIC_RELAXED);
4504                 dev_flow->handle->dvh.modify_hdr = cache_resource;
4505                 return 0;
4506
4507         }
4508         /* Register new modify-header resource. */
4509         cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4510                                     sizeof(*cache_resource) + actions_len, 0,
4511                                     SOCKET_ID_ANY);
4512         if (!cache_resource)
4513                 return rte_flow_error_set(error, ENOMEM,
4514                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4515                                           "cannot allocate resource memory");
4516         *cache_resource = *resource;
4517         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4518         ret = mlx5_flow_os_create_flow_action_modify_header
4519                                         (sh->ctx, ns, cache_resource,
4520                                          actions_len, &cache_resource->action);
4521         if (ret) {
4522                 mlx5_free(cache_resource);
4523                 return rte_flow_error_set(error, ENOMEM,
4524                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4525                                           NULL, "cannot create action");
4526         }
4527         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
4528         if (mlx5_hlist_insert_ex(sh->modify_cmds, &cache_resource->entry,
4529                                  flow_dv_modify_hdr_resource_match,
4530                                  (void *)cache_resource)) {
4531                 claim_zero(mlx5_flow_os_destroy_flow_action
4532                                                 (cache_resource->action));
4533                 mlx5_free(cache_resource);
4534                 return rte_flow_error_set(error, EEXIST,
4535                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4536                                           NULL, "action exist");
4537         }
4538         dev_flow->handle->dvh.modify_hdr = cache_resource;
4539         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4540                 (void *)cache_resource,
4541                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
4542         return 0;
4543 }
4544
4545 /**
4546  * Get DV flow counter by index.
4547  *
4548  * @param[in] dev
4549  *   Pointer to the Ethernet device structure.
4550  * @param[in] idx
4551  *   mlx5 flow counter index in the container.
4552  * @param[out] ppool
4553  *   mlx5 flow counter pool in the container,
4554  *
4555  * @return
4556  *   Pointer to the counter, NULL otherwise.
4557  */
4558 static struct mlx5_flow_counter *
4559 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4560                            uint32_t idx,
4561                            struct mlx5_flow_counter_pool **ppool)
4562 {
4563         struct mlx5_priv *priv = dev->data->dev_private;
4564         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4565         struct mlx5_flow_counter_pool *pool;
4566
4567         /* Decrease to original index and clear shared bit. */
4568         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4569         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4570         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4571         MLX5_ASSERT(pool);
4572         if (ppool)
4573                 *ppool = pool;
4574         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4575 }
4576
4577 /**
4578  * Check the devx counter belongs to the pool.
4579  *
4580  * @param[in] pool
4581  *   Pointer to the counter pool.
4582  * @param[in] id
4583  *   The counter devx ID.
4584  *
4585  * @return
4586  *   True if counter belongs to the pool, false otherwise.
4587  */
4588 static bool
4589 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4590 {
4591         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4592                    MLX5_COUNTERS_PER_POOL;
4593
4594         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4595                 return true;
4596         return false;
4597 }
4598
4599 /**
4600  * Get a pool by devx counter ID.
4601  *
4602  * @param[in] cmng
4603  *   Pointer to the counter management.
4604  * @param[in] id
4605  *   The counter devx ID.
4606  *
4607  * @return
4608  *   The counter pool pointer if exists, NULL otherwise,
4609  */
4610 static struct mlx5_flow_counter_pool *
4611 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4612 {
4613         uint32_t i;
4614         struct mlx5_flow_counter_pool *pool = NULL;
4615
4616         rte_spinlock_lock(&cmng->pool_update_sl);
4617         /* Check last used pool. */
4618         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4619             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4620                 pool = cmng->pools[cmng->last_pool_idx];
4621                 goto out;
4622         }
4623         /* ID out of range means no suitable pool in the container. */
4624         if (id > cmng->max_id || id < cmng->min_id)
4625                 goto out;
4626         /*
4627          * Find the pool from the end of the container, since mostly counter
4628          * ID is sequence increasing, and the last pool should be the needed
4629          * one.
4630          */
4631         i = cmng->n_valid;
4632         while (i--) {
4633                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4634
4635                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4636                         pool = pool_tmp;
4637                         break;
4638                 }
4639         }
4640 out:
4641         rte_spinlock_unlock(&cmng->pool_update_sl);
4642         return pool;
4643 }
4644
4645 /**
4646  * Resize a counter container.
4647  *
4648  * @param[in] dev
4649  *   Pointer to the Ethernet device structure.
4650  *
4651  * @return
4652  *   0 on success, otherwise negative errno value and rte_errno is set.
4653  */
4654 static int
4655 flow_dv_container_resize(struct rte_eth_dev *dev)
4656 {
4657         struct mlx5_priv *priv = dev->data->dev_private;
4658         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4659         void *old_pools = cmng->pools;
4660         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4661         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4662         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4663
4664         if (!pools) {
4665                 rte_errno = ENOMEM;
4666                 return -ENOMEM;
4667         }
4668         if (old_pools)
4669                 memcpy(pools, old_pools, cmng->n *
4670                                        sizeof(struct mlx5_flow_counter_pool *));
4671         cmng->n = resize;
4672         cmng->pools = pools;
4673         if (old_pools)
4674                 mlx5_free(old_pools);
4675         return 0;
4676 }
4677
4678 /**
4679  * Query a devx flow counter.
4680  *
4681  * @param[in] dev
4682  *   Pointer to the Ethernet device structure.
4683  * @param[in] cnt
4684  *   Index to the flow counter.
4685  * @param[out] pkts
4686  *   The statistics value of packets.
4687  * @param[out] bytes
4688  *   The statistics value of bytes.
4689  *
4690  * @return
4691  *   0 on success, otherwise a negative errno value and rte_errno is set.
4692  */
4693 static inline int
4694 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4695                      uint64_t *bytes)
4696 {
4697         struct mlx5_priv *priv = dev->data->dev_private;
4698         struct mlx5_flow_counter_pool *pool = NULL;
4699         struct mlx5_flow_counter *cnt;
4700         int offset;
4701
4702         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4703         MLX5_ASSERT(pool);
4704         if (priv->sh->cmng.counter_fallback)
4705                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4706                                         0, pkts, bytes, 0, NULL, NULL, 0);
4707         rte_spinlock_lock(&pool->sl);
4708         if (!pool->raw) {
4709                 *pkts = 0;
4710                 *bytes = 0;
4711         } else {
4712                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4713                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4714                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4715         }
4716         rte_spinlock_unlock(&pool->sl);
4717         return 0;
4718 }
4719
4720 /**
4721  * Create and initialize a new counter pool.
4722  *
4723  * @param[in] dev
4724  *   Pointer to the Ethernet device structure.
4725  * @param[out] dcs
4726  *   The devX counter handle.
4727  * @param[in] age
4728  *   Whether the pool is for counter that was allocated for aging.
4729  * @param[in/out] cont_cur
4730  *   Pointer to the container pointer, it will be update in pool resize.
4731  *
4732  * @return
4733  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4734  */
4735 static struct mlx5_flow_counter_pool *
4736 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4737                     uint32_t age)
4738 {
4739         struct mlx5_priv *priv = dev->data->dev_private;
4740         struct mlx5_flow_counter_pool *pool;
4741         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4742         bool fallback = priv->sh->cmng.counter_fallback;
4743         uint32_t size = sizeof(*pool);
4744
4745         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4746         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4747         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4748         if (!pool) {
4749                 rte_errno = ENOMEM;
4750                 return NULL;
4751         }
4752         pool->raw = NULL;
4753         pool->is_aged = !!age;
4754         pool->query_gen = 0;
4755         pool->min_dcs = dcs;
4756         rte_spinlock_init(&pool->sl);
4757         rte_spinlock_init(&pool->csl);
4758         TAILQ_INIT(&pool->counters[0]);
4759         TAILQ_INIT(&pool->counters[1]);
4760         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4761         rte_spinlock_lock(&cmng->pool_update_sl);
4762         pool->index = cmng->n_valid;
4763         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4764                 mlx5_free(pool);
4765                 rte_spinlock_unlock(&cmng->pool_update_sl);
4766                 return NULL;
4767         }
4768         cmng->pools[pool->index] = pool;
4769         cmng->n_valid++;
4770         if (unlikely(fallback)) {
4771                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4772
4773                 if (base < cmng->min_id)
4774                         cmng->min_id = base;
4775                 if (base > cmng->max_id)
4776                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4777                 cmng->last_pool_idx = pool->index;
4778         }
4779         rte_spinlock_unlock(&cmng->pool_update_sl);
4780         return pool;
4781 }
4782
4783 /**
4784  * Prepare a new counter and/or a new counter pool.
4785  *
4786  * @param[in] dev
4787  *   Pointer to the Ethernet device structure.
4788  * @param[out] cnt_free
4789  *   Where to put the pointer of a new counter.
4790  * @param[in] age
4791  *   Whether the pool is for counter that was allocated for aging.
4792  *
4793  * @return
4794  *   The counter pool pointer and @p cnt_free is set on success,
4795  *   NULL otherwise and rte_errno is set.
4796  */
4797 static struct mlx5_flow_counter_pool *
4798 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4799                              struct mlx5_flow_counter **cnt_free,
4800                              uint32_t age)
4801 {
4802         struct mlx5_priv *priv = dev->data->dev_private;
4803         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4804         struct mlx5_flow_counter_pool *pool;
4805         struct mlx5_counters tmp_tq;
4806         struct mlx5_devx_obj *dcs = NULL;
4807         struct mlx5_flow_counter *cnt;
4808         enum mlx5_counter_type cnt_type =
4809                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4810         bool fallback = priv->sh->cmng.counter_fallback;
4811         uint32_t i;
4812
4813         if (fallback) {
4814                 /* bulk_bitmap must be 0 for single counter allocation. */
4815                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4816                 if (!dcs)
4817                         return NULL;
4818                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4819                 if (!pool) {
4820                         pool = flow_dv_pool_create(dev, dcs, age);
4821                         if (!pool) {
4822                                 mlx5_devx_cmd_destroy(dcs);
4823                                 return NULL;
4824                         }
4825                 }
4826                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4827                 cnt = MLX5_POOL_GET_CNT(pool, i);
4828                 cnt->pool = pool;
4829                 cnt->dcs_when_free = dcs;
4830                 *cnt_free = cnt;
4831                 return pool;
4832         }
4833         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4834         if (!dcs) {
4835                 rte_errno = ENODATA;
4836                 return NULL;
4837         }
4838         pool = flow_dv_pool_create(dev, dcs, age);
4839         if (!pool) {
4840                 mlx5_devx_cmd_destroy(dcs);
4841                 return NULL;
4842         }
4843         TAILQ_INIT(&tmp_tq);
4844         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4845                 cnt = MLX5_POOL_GET_CNT(pool, i);
4846                 cnt->pool = pool;
4847                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4848         }
4849         rte_spinlock_lock(&cmng->csl[cnt_type]);
4850         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4851         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4852         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4853         (*cnt_free)->pool = pool;
4854         return pool;
4855 }
4856
4857 /**
4858  * Allocate a flow counter.
4859  *
4860  * @param[in] dev
4861  *   Pointer to the Ethernet device structure.
4862  * @param[in] age
4863  *   Whether the counter was allocated for aging.
4864  *
4865  * @return
4866  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4867  */
4868 static uint32_t
4869 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4870 {
4871         struct mlx5_priv *priv = dev->data->dev_private;
4872         struct mlx5_flow_counter_pool *pool = NULL;
4873         struct mlx5_flow_counter *cnt_free = NULL;
4874         bool fallback = priv->sh->cmng.counter_fallback;
4875         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4876         enum mlx5_counter_type cnt_type =
4877                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4878         uint32_t cnt_idx;
4879
4880         if (!priv->config.devx) {
4881                 rte_errno = ENOTSUP;
4882                 return 0;
4883         }
4884         /* Get free counters from container. */
4885         rte_spinlock_lock(&cmng->csl[cnt_type]);
4886         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4887         if (cnt_free)
4888                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4889         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4890         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4891                 goto err;
4892         pool = cnt_free->pool;
4893         if (fallback)
4894                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4895         /* Create a DV counter action only in the first time usage. */
4896         if (!cnt_free->action) {
4897                 uint16_t offset;
4898                 struct mlx5_devx_obj *dcs;
4899                 int ret;
4900
4901                 if (!fallback) {
4902                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4903                         dcs = pool->min_dcs;
4904                 } else {
4905                         offset = 0;
4906                         dcs = cnt_free->dcs_when_free;
4907                 }
4908                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4909                                                             &cnt_free->action);
4910                 if (ret) {
4911                         rte_errno = errno;
4912                         goto err;
4913                 }
4914         }
4915         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4916                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4917         /* Update the counter reset values. */
4918         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4919                                  &cnt_free->bytes))
4920                 goto err;
4921         if (!fallback && !priv->sh->cmng.query_thread_on)
4922                 /* Start the asynchronous batch query by the host thread. */
4923                 mlx5_set_query_alarm(priv->sh);
4924         return cnt_idx;
4925 err:
4926         if (cnt_free) {
4927                 cnt_free->pool = pool;
4928                 if (fallback)
4929                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4930                 rte_spinlock_lock(&cmng->csl[cnt_type]);
4931                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4932                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4933         }
4934         return 0;
4935 }
4936
4937 /**
4938  * Allocate a shared flow counter.
4939  *
4940  * @param[in] ctx
4941  *   Pointer to the shared counter configuration.
4942  * @param[in] data
4943  *   Pointer to save the allocated counter index.
4944  *
4945  * @return
4946  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4947  */
4948
4949 static int32_t
4950 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
4951 {
4952         struct mlx5_shared_counter_conf *conf = ctx;
4953         struct rte_eth_dev *dev = conf->dev;
4954         struct mlx5_flow_counter *cnt;
4955
4956         data->dword = flow_dv_counter_alloc(dev, 0);
4957         data->dword |= MLX5_CNT_SHARED_OFFSET;
4958         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
4959         cnt->shared_info.id = conf->id;
4960         return 0;
4961 }
4962
4963 /**
4964  * Get a shared flow counter.
4965  *
4966  * @param[in] dev
4967  *   Pointer to the Ethernet device structure.
4968  * @param[in] id
4969  *   Counter identifier.
4970  *
4971  * @return
4972  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4973  */
4974 static uint32_t
4975 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
4976 {
4977         struct mlx5_priv *priv = dev->data->dev_private;
4978         struct mlx5_shared_counter_conf conf = {
4979                 .dev = dev,
4980                 .id = id,
4981         };
4982         union mlx5_l3t_data data = {
4983                 .dword = 0,
4984         };
4985
4986         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
4987                                flow_dv_counter_alloc_shared_cb, &conf);
4988         return data.dword;
4989 }
4990
4991 /**
4992  * Get age param from counter index.
4993  *
4994  * @param[in] dev
4995  *   Pointer to the Ethernet device structure.
4996  * @param[in] counter
4997  *   Index to the counter handler.
4998  *
4999  * @return
5000  *   The aging parameter specified for the counter index.
5001  */
5002 static struct mlx5_age_param*
5003 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5004                                 uint32_t counter)
5005 {
5006         struct mlx5_flow_counter *cnt;
5007         struct mlx5_flow_counter_pool *pool = NULL;
5008
5009         flow_dv_counter_get_by_idx(dev, counter, &pool);
5010         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5011         cnt = MLX5_POOL_GET_CNT(pool, counter);
5012         return MLX5_CNT_TO_AGE(cnt);
5013 }
5014
5015 /**
5016  * Remove a flow counter from aged counter list.
5017  *
5018  * @param[in] dev
5019  *   Pointer to the Ethernet device structure.
5020  * @param[in] counter
5021  *   Index to the counter handler.
5022  * @param[in] cnt
5023  *   Pointer to the counter handler.
5024  */
5025 static void
5026 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5027                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5028 {
5029         struct mlx5_age_info *age_info;
5030         struct mlx5_age_param *age_param;
5031         struct mlx5_priv *priv = dev->data->dev_private;
5032         uint16_t expected = AGE_CANDIDATE;
5033
5034         age_info = GET_PORT_AGE_INFO(priv);
5035         age_param = flow_dv_counter_idx_get_age(dev, counter);
5036         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5037                                          AGE_FREE, false, __ATOMIC_RELAXED,
5038                                          __ATOMIC_RELAXED)) {
5039                 /**
5040                  * We need the lock even it is age timeout,
5041                  * since counter may still in process.
5042                  */
5043                 rte_spinlock_lock(&age_info->aged_sl);
5044                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5045                 rte_spinlock_unlock(&age_info->aged_sl);
5046                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5047         }
5048 }
5049
5050 /**
5051  * Release a flow counter.
5052  *
5053  * @param[in] dev
5054  *   Pointer to the Ethernet device structure.
5055  * @param[in] counter
5056  *   Index to the counter handler.
5057  */
5058 static void
5059 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
5060 {
5061         struct mlx5_priv *priv = dev->data->dev_private;
5062         struct mlx5_flow_counter_pool *pool = NULL;
5063         struct mlx5_flow_counter *cnt;
5064         enum mlx5_counter_type cnt_type;
5065
5066         if (!counter)
5067                 return;
5068         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5069         MLX5_ASSERT(pool);
5070         if (IS_SHARED_CNT(counter) &&
5071             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5072                 return;
5073         if (pool->is_aged)
5074                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5075         cnt->pool = pool;
5076         /*
5077          * Put the counter back to list to be updated in none fallback mode.
5078          * Currently, we are using two list alternately, while one is in query,
5079          * add the freed counter to the other list based on the pool query_gen
5080          * value. After query finishes, add counter the list to the global
5081          * container counter list. The list changes while query starts. In
5082          * this case, lock will not be needed as query callback and release
5083          * function both operate with the different list.
5084          *
5085          */
5086         if (!priv->sh->cmng.counter_fallback) {
5087                 rte_spinlock_lock(&pool->csl);
5088                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5089                 rte_spinlock_unlock(&pool->csl);
5090         } else {
5091                 cnt->dcs_when_free = cnt->dcs_when_active;
5092                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5093                                            MLX5_COUNTER_TYPE_ORIGIN;
5094                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5095                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5096                                   cnt, next);
5097                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5098         }
5099 }
5100
5101 /**
5102  * Verify the @p attributes will be correctly understood by the NIC and store
5103  * them in the @p flow if everything is correct.
5104  *
5105  * @param[in] dev
5106  *   Pointer to dev struct.
5107  * @param[in] attributes
5108  *   Pointer to flow attributes
5109  * @param[in] external
5110  *   This flow rule is created by request external to PMD.
5111  * @param[out] error
5112  *   Pointer to error structure.
5113  *
5114  * @return
5115  *   - 0 on success and non root table.
5116  *   - 1 on success and root table.
5117  *   - a negative errno value otherwise and rte_errno is set.
5118  */
5119 static int
5120 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5121                             const struct mlx5_flow_tunnel *tunnel,
5122                             const struct rte_flow_attr *attributes,
5123                             struct flow_grp_info grp_info,
5124                             struct rte_flow_error *error)
5125 {
5126         struct mlx5_priv *priv = dev->data->dev_private;
5127         uint32_t priority_max = priv->config.flow_prio - 1;
5128         int ret = 0;
5129
5130 #ifndef HAVE_MLX5DV_DR
5131         RTE_SET_USED(tunnel);
5132         RTE_SET_USED(grp_info);
5133         if (attributes->group)
5134                 return rte_flow_error_set(error, ENOTSUP,
5135                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5136                                           NULL,
5137                                           "groups are not supported");
5138 #else
5139         uint32_t table = 0;
5140
5141         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5142                                        grp_info, error);
5143         if (ret)
5144                 return ret;
5145         if (!table)
5146                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5147 #endif
5148         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5149             attributes->priority >= priority_max)
5150                 return rte_flow_error_set(error, ENOTSUP,
5151                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5152                                           NULL,
5153                                           "priority out of range");
5154         if (attributes->transfer) {
5155                 if (!priv->config.dv_esw_en)
5156                         return rte_flow_error_set
5157                                 (error, ENOTSUP,
5158                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5159                                  "E-Switch dr is not supported");
5160                 if (!(priv->representor || priv->master))
5161                         return rte_flow_error_set
5162                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5163                                  NULL, "E-Switch configuration can only be"
5164                                  " done by a master or a representor device");
5165                 if (attributes->egress)
5166                         return rte_flow_error_set
5167                                 (error, ENOTSUP,
5168                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5169                                  "egress is not supported");
5170         }
5171         if (!(attributes->egress ^ attributes->ingress))
5172                 return rte_flow_error_set(error, ENOTSUP,
5173                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5174                                           "must specify exactly one of "
5175                                           "ingress or egress");
5176         return ret;
5177 }
5178
5179 /**
5180  * Internal validation function. For validating both actions and items.
5181  *
5182  * @param[in] dev
5183  *   Pointer to the rte_eth_dev structure.
5184  * @param[in] attr
5185  *   Pointer to the flow attributes.
5186  * @param[in] items
5187  *   Pointer to the list of items.
5188  * @param[in] actions
5189  *   Pointer to the list of actions.
5190  * @param[in] external
5191  *   This flow rule is created by request external to PMD.
5192  * @param[in] hairpin
5193  *   Number of hairpin TX actions, 0 means classic flow.
5194  * @param[out] error
5195  *   Pointer to the error structure.
5196  *
5197  * @return
5198  *   0 on success, a negative errno value otherwise and rte_errno is set.
5199  */
5200 static int
5201 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5202                  const struct rte_flow_item items[],
5203                  const struct rte_flow_action actions[],
5204                  bool external, int hairpin, struct rte_flow_error *error)
5205 {
5206         int ret;
5207         uint64_t action_flags = 0;
5208         uint64_t item_flags = 0;
5209         uint64_t last_item = 0;
5210         uint8_t next_protocol = 0xff;
5211         uint16_t ether_type = 0;
5212         int actions_n = 0;
5213         uint8_t item_ipv6_proto = 0;
5214         const struct rte_flow_item *gre_item = NULL;
5215         const struct rte_flow_action_raw_decap *decap;
5216         const struct rte_flow_action_raw_encap *encap;
5217         const struct rte_flow_action_rss *rss;
5218         const struct rte_flow_item_tcp nic_tcp_mask = {
5219                 .hdr = {
5220                         .tcp_flags = 0xFF,
5221                         .src_port = RTE_BE16(UINT16_MAX),
5222                         .dst_port = RTE_BE16(UINT16_MAX),
5223                 }
5224         };
5225         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5226                 .hdr = {
5227                         .src_addr =
5228                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5229                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5230                         .dst_addr =
5231                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5232                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5233                         .vtc_flow = RTE_BE32(0xffffffff),
5234                         .proto = 0xff,
5235                         .hop_limits = 0xff,
5236                 },
5237                 .has_frag_ext = 1,
5238         };
5239         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5240                 .hdr = {
5241                         .common = {
5242                                 .u32 =
5243                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5244                                         .type = 0xFF,
5245                                         }).u32),
5246                         },
5247                         .dummy[0] = 0xffffffff,
5248                 },
5249         };
5250         struct mlx5_priv *priv = dev->data->dev_private;
5251         struct mlx5_dev_config *dev_conf = &priv->config;
5252         uint16_t queue_index = 0xFFFF;
5253         const struct rte_flow_item_vlan *vlan_m = NULL;
5254         int16_t rw_act_num = 0;
5255         uint64_t is_root;
5256         const struct mlx5_flow_tunnel *tunnel;
5257         struct flow_grp_info grp_info = {
5258                 .external = !!external,
5259                 .transfer = !!attr->transfer,
5260                 .fdb_def_rule = !!priv->fdb_def_rule,
5261         };
5262         const struct rte_eth_hairpin_conf *conf;
5263
5264         if (items == NULL)
5265                 return -1;
5266         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5267                 tunnel = flow_items_to_tunnel(items);
5268                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5269                                 MLX5_FLOW_ACTION_DECAP;
5270         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5271                 tunnel = flow_actions_to_tunnel(actions);
5272                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5273         } else {
5274                 tunnel = NULL;
5275         }
5276         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5277                                 (dev, tunnel, attr, items, actions);
5278         ret = flow_dv_validate_attributes(dev, tunnel, attr, grp_info, error);
5279         if (ret < 0)
5280                 return ret;
5281         is_root = (uint64_t)ret;
5282         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5283                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5284                 int type = items->type;
5285
5286                 if (!mlx5_flow_os_item_supported(type))
5287                         return rte_flow_error_set(error, ENOTSUP,
5288                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5289                                                   NULL, "item not supported");
5290                 switch (type) {
5291                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5292                         if (items[0].type != (typeof(items[0].type))
5293                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5294                                 return rte_flow_error_set
5295                                                 (error, EINVAL,
5296                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5297                                                 NULL, "MLX5 private items "
5298                                                 "must be the first");
5299                         break;
5300                 case RTE_FLOW_ITEM_TYPE_VOID:
5301                         break;
5302                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5303                         ret = flow_dv_validate_item_port_id
5304                                         (dev, items, attr, item_flags, error);
5305                         if (ret < 0)
5306                                 return ret;
5307                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5308                         break;
5309                 case RTE_FLOW_ITEM_TYPE_ETH:
5310                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5311                                                           true, error);
5312                         if (ret < 0)
5313                                 return ret;
5314                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5315                                              MLX5_FLOW_LAYER_OUTER_L2;
5316                         if (items->mask != NULL && items->spec != NULL) {
5317                                 ether_type =
5318                                         ((const struct rte_flow_item_eth *)
5319                                          items->spec)->type;
5320                                 ether_type &=
5321                                         ((const struct rte_flow_item_eth *)
5322                                          items->mask)->type;
5323                                 ether_type = rte_be_to_cpu_16(ether_type);
5324                         } else {
5325                                 ether_type = 0;
5326                         }
5327                         break;
5328                 case RTE_FLOW_ITEM_TYPE_VLAN:
5329                         ret = flow_dv_validate_item_vlan(items, item_flags,
5330                                                          dev, error);
5331                         if (ret < 0)
5332                                 return ret;
5333                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5334                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5335                         if (items->mask != NULL && items->spec != NULL) {
5336                                 ether_type =
5337                                         ((const struct rte_flow_item_vlan *)
5338                                          items->spec)->inner_type;
5339                                 ether_type &=
5340                                         ((const struct rte_flow_item_vlan *)
5341                                          items->mask)->inner_type;
5342                                 ether_type = rte_be_to_cpu_16(ether_type);
5343                         } else {
5344                                 ether_type = 0;
5345                         }
5346                         /* Store outer VLAN mask for of_push_vlan action. */
5347                         if (!tunnel)
5348                                 vlan_m = items->mask;
5349                         break;
5350                 case RTE_FLOW_ITEM_TYPE_IPV4:
5351                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5352                                                   &item_flags, &tunnel);
5353                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5354                                                          last_item, ether_type,
5355                                                          error);
5356                         if (ret < 0)
5357                                 return ret;
5358                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5359                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5360                         if (items->mask != NULL &&
5361                             ((const struct rte_flow_item_ipv4 *)
5362                              items->mask)->hdr.next_proto_id) {
5363                                 next_protocol =
5364                                         ((const struct rte_flow_item_ipv4 *)
5365                                          (items->spec))->hdr.next_proto_id;
5366                                 next_protocol &=
5367                                         ((const struct rte_flow_item_ipv4 *)
5368                                          (items->mask))->hdr.next_proto_id;
5369                         } else {
5370                                 /* Reset for inner layer. */
5371                                 next_protocol = 0xff;
5372                         }
5373                         break;
5374                 case RTE_FLOW_ITEM_TYPE_IPV6:
5375                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5376                                                   &item_flags, &tunnel);
5377                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5378                                                            last_item,
5379                                                            ether_type,
5380                                                            &nic_ipv6_mask,
5381                                                            error);
5382                         if (ret < 0)
5383                                 return ret;
5384                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5385                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5386                         if (items->mask != NULL &&
5387                             ((const struct rte_flow_item_ipv6 *)
5388                              items->mask)->hdr.proto) {
5389                                 item_ipv6_proto =
5390                                         ((const struct rte_flow_item_ipv6 *)
5391                                          items->spec)->hdr.proto;
5392                                 next_protocol =
5393                                         ((const struct rte_flow_item_ipv6 *)
5394                                          items->spec)->hdr.proto;
5395                                 next_protocol &=
5396                                         ((const struct rte_flow_item_ipv6 *)
5397                                          items->mask)->hdr.proto;
5398                         } else {
5399                                 /* Reset for inner layer. */
5400                                 next_protocol = 0xff;
5401                         }
5402                         break;
5403                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5404                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5405                                                                   item_flags,
5406                                                                   error);
5407                         if (ret < 0)
5408                                 return ret;
5409                         last_item = tunnel ?
5410                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5411                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5412                         if (items->mask != NULL &&
5413                             ((const struct rte_flow_item_ipv6_frag_ext *)
5414                              items->mask)->hdr.next_header) {
5415                                 next_protocol =
5416                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5417                                  items->spec)->hdr.next_header;
5418                                 next_protocol &=
5419                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5420                                  items->mask)->hdr.next_header;
5421                         } else {
5422                                 /* Reset for inner layer. */
5423                                 next_protocol = 0xff;
5424                         }
5425                         break;
5426                 case RTE_FLOW_ITEM_TYPE_TCP:
5427                         ret = mlx5_flow_validate_item_tcp
5428                                                 (items, item_flags,
5429                                                  next_protocol,
5430                                                  &nic_tcp_mask,
5431                                                  error);
5432                         if (ret < 0)
5433                                 return ret;
5434                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5435                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5436                         break;
5437                 case RTE_FLOW_ITEM_TYPE_UDP:
5438                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5439                                                           next_protocol,
5440                                                           error);
5441                         if (ret < 0)
5442                                 return ret;
5443                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5444                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5445                         break;
5446                 case RTE_FLOW_ITEM_TYPE_GRE:
5447                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5448                                                           next_protocol, error);
5449                         if (ret < 0)
5450                                 return ret;
5451                         gre_item = items;
5452                         last_item = MLX5_FLOW_LAYER_GRE;
5453                         break;
5454                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5455                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5456                                                             next_protocol,
5457                                                             error);
5458                         if (ret < 0)
5459                                 return ret;
5460                         last_item = MLX5_FLOW_LAYER_NVGRE;
5461                         break;
5462                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5463                         ret = mlx5_flow_validate_item_gre_key
5464                                 (items, item_flags, gre_item, error);
5465                         if (ret < 0)
5466                                 return ret;
5467                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5468                         break;
5469                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5470                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5471                                                             error);
5472                         if (ret < 0)
5473                                 return ret;
5474                         last_item = MLX5_FLOW_LAYER_VXLAN;
5475                         break;
5476                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5477                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5478                                                                 item_flags, dev,
5479                                                                 error);
5480                         if (ret < 0)
5481                                 return ret;
5482                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5483                         break;
5484                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5485                         ret = mlx5_flow_validate_item_geneve(items,
5486                                                              item_flags, dev,
5487                                                              error);
5488                         if (ret < 0)
5489                                 return ret;
5490                         last_item = MLX5_FLOW_LAYER_GENEVE;
5491                         break;
5492                 case RTE_FLOW_ITEM_TYPE_MPLS:
5493                         ret = mlx5_flow_validate_item_mpls(dev, items,
5494                                                            item_flags,
5495                                                            last_item, error);
5496                         if (ret < 0)
5497                                 return ret;
5498                         last_item = MLX5_FLOW_LAYER_MPLS;
5499                         break;
5500
5501                 case RTE_FLOW_ITEM_TYPE_MARK:
5502                         ret = flow_dv_validate_item_mark(dev, items, attr,
5503                                                          error);
5504                         if (ret < 0)
5505                                 return ret;
5506                         last_item = MLX5_FLOW_ITEM_MARK;
5507                         break;
5508                 case RTE_FLOW_ITEM_TYPE_META:
5509                         ret = flow_dv_validate_item_meta(dev, items, attr,
5510                                                          error);
5511                         if (ret < 0)
5512                                 return ret;
5513                         last_item = MLX5_FLOW_ITEM_METADATA;
5514                         break;
5515                 case RTE_FLOW_ITEM_TYPE_ICMP:
5516                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5517                                                            next_protocol,
5518                                                            error);
5519                         if (ret < 0)
5520                                 return ret;
5521                         last_item = MLX5_FLOW_LAYER_ICMP;
5522                         break;
5523                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5524                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5525                                                             next_protocol,
5526                                                             error);
5527                         if (ret < 0)
5528                                 return ret;
5529                         item_ipv6_proto = IPPROTO_ICMPV6;
5530                         last_item = MLX5_FLOW_LAYER_ICMP6;
5531                         break;
5532                 case RTE_FLOW_ITEM_TYPE_TAG:
5533                         ret = flow_dv_validate_item_tag(dev, items,
5534                                                         attr, error);
5535                         if (ret < 0)
5536                                 return ret;
5537                         last_item = MLX5_FLOW_ITEM_TAG;
5538                         break;
5539                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5540                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5541                         break;
5542                 case RTE_FLOW_ITEM_TYPE_GTP:
5543                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5544                                                         error);
5545                         if (ret < 0)
5546                                 return ret;
5547                         last_item = MLX5_FLOW_LAYER_GTP;
5548                         break;
5549                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5550                         /* Capacity will be checked in the translate stage. */
5551                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5552                                                             last_item,
5553                                                             ether_type,
5554                                                             &nic_ecpri_mask,
5555                                                             error);
5556                         if (ret < 0)
5557                                 return ret;
5558                         last_item = MLX5_FLOW_LAYER_ECPRI;
5559                         break;
5560                 default:
5561                         return rte_flow_error_set(error, ENOTSUP,
5562                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5563                                                   NULL, "item not supported");
5564                 }
5565                 item_flags |= last_item;
5566         }
5567         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5568                 int type = actions->type;
5569
5570                 if (!mlx5_flow_os_action_supported(type))
5571                         return rte_flow_error_set(error, ENOTSUP,
5572                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5573                                                   actions,
5574                                                   "action not supported");
5575                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5576                         return rte_flow_error_set(error, ENOTSUP,
5577                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5578                                                   actions, "too many actions");
5579                 switch (type) {
5580                 case RTE_FLOW_ACTION_TYPE_VOID:
5581                         break;
5582                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5583                         ret = flow_dv_validate_action_port_id(dev,
5584                                                               action_flags,
5585                                                               actions,
5586                                                               attr,
5587                                                               error);
5588                         if (ret)
5589                                 return ret;
5590                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5591                         ++actions_n;
5592                         break;
5593                 case RTE_FLOW_ACTION_TYPE_FLAG:
5594                         ret = flow_dv_validate_action_flag(dev, action_flags,
5595                                                            attr, error);
5596                         if (ret < 0)
5597                                 return ret;
5598                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5599                                 /* Count all modify-header actions as one. */
5600                                 if (!(action_flags &
5601                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5602                                         ++actions_n;
5603                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5604                                                 MLX5_FLOW_ACTION_MARK_EXT;
5605                         } else {
5606                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5607                                 ++actions_n;
5608                         }
5609                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5610                         break;
5611                 case RTE_FLOW_ACTION_TYPE_MARK:
5612                         ret = flow_dv_validate_action_mark(dev, actions,
5613                                                            action_flags,
5614                                                            attr, error);
5615                         if (ret < 0)
5616                                 return ret;
5617                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5618                                 /* Count all modify-header actions as one. */
5619                                 if (!(action_flags &
5620                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5621                                         ++actions_n;
5622                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5623                                                 MLX5_FLOW_ACTION_MARK_EXT;
5624                         } else {
5625                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5626                                 ++actions_n;
5627                         }
5628                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5629                         break;
5630                 case RTE_FLOW_ACTION_TYPE_SET_META:
5631                         ret = flow_dv_validate_action_set_meta(dev, actions,
5632                                                                action_flags,
5633                                                                attr, error);
5634                         if (ret < 0)
5635                                 return ret;
5636                         /* Count all modify-header actions as one action. */
5637                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5638                                 ++actions_n;
5639                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5640                         rw_act_num += MLX5_ACT_NUM_SET_META;
5641                         break;
5642                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5643                         ret = flow_dv_validate_action_set_tag(dev, actions,
5644                                                               action_flags,
5645                                                               attr, error);
5646                         if (ret < 0)
5647                                 return ret;
5648                         /* Count all modify-header actions as one action. */
5649                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5650                                 ++actions_n;
5651                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5652                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5653                         break;
5654                 case RTE_FLOW_ACTION_TYPE_DROP:
5655                         ret = mlx5_flow_validate_action_drop(action_flags,
5656                                                              attr, error);
5657                         if (ret < 0)
5658                                 return ret;
5659                         action_flags |= MLX5_FLOW_ACTION_DROP;
5660                         ++actions_n;
5661                         break;
5662                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5663                         ret = mlx5_flow_validate_action_queue(actions,
5664                                                               action_flags, dev,
5665                                                               attr, error);
5666                         if (ret < 0)
5667                                 return ret;
5668                         queue_index = ((const struct rte_flow_action_queue *)
5669                                                         (actions->conf))->index;
5670                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5671                         ++actions_n;
5672                         break;
5673                 case RTE_FLOW_ACTION_TYPE_RSS:
5674                         rss = actions->conf;
5675                         ret = mlx5_flow_validate_action_rss(actions,
5676                                                             action_flags, dev,
5677                                                             attr, item_flags,
5678                                                             error);
5679                         if (ret < 0)
5680                                 return ret;
5681                         if (rss != NULL && rss->queue_num)
5682                                 queue_index = rss->queue[0];
5683                         action_flags |= MLX5_FLOW_ACTION_RSS;
5684                         ++actions_n;
5685                         break;
5686                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5687                         ret =
5688                         mlx5_flow_validate_action_default_miss(action_flags,
5689                                         attr, error);
5690                         if (ret < 0)
5691                                 return ret;
5692                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5693                         ++actions_n;
5694                         break;
5695                 case RTE_FLOW_ACTION_TYPE_COUNT:
5696                         ret = flow_dv_validate_action_count(dev, error);
5697                         if (ret < 0)
5698                                 return ret;
5699                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5700                         ++actions_n;
5701                         break;
5702                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5703                         if (flow_dv_validate_action_pop_vlan(dev,
5704                                                              action_flags,
5705                                                              actions,
5706                                                              item_flags, attr,
5707                                                              error))
5708                                 return -rte_errno;
5709                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5710                         ++actions_n;
5711                         break;
5712                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5713                         ret = flow_dv_validate_action_push_vlan(dev,
5714                                                                 action_flags,
5715                                                                 vlan_m,
5716                                                                 actions, attr,
5717                                                                 error);
5718                         if (ret < 0)
5719                                 return ret;
5720                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5721                         ++actions_n;
5722                         break;
5723                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5724                         ret = flow_dv_validate_action_set_vlan_pcp
5725                                                 (action_flags, actions, error);
5726                         if (ret < 0)
5727                                 return ret;
5728                         /* Count PCP with push_vlan command. */
5729                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5730                         break;
5731                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5732                         ret = flow_dv_validate_action_set_vlan_vid
5733                                                 (item_flags, action_flags,
5734                                                  actions, error);
5735                         if (ret < 0)
5736                                 return ret;
5737                         /* Count VID with push_vlan command. */
5738                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5739                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5740                         break;
5741                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5742                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5743                         ret = flow_dv_validate_action_l2_encap(dev,
5744                                                                action_flags,
5745                                                                actions, attr,
5746                                                                error);
5747                         if (ret < 0)
5748                                 return ret;
5749                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5750                         ++actions_n;
5751                         break;
5752                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5753                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5754                         ret = flow_dv_validate_action_decap(dev, action_flags,
5755                                                             attr, error);
5756                         if (ret < 0)
5757                                 return ret;
5758                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5759                         ++actions_n;
5760                         break;
5761                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5762                         ret = flow_dv_validate_action_raw_encap_decap
5763                                 (dev, NULL, actions->conf, attr, &action_flags,
5764                                  &actions_n, error);
5765                         if (ret < 0)
5766                                 return ret;
5767                         break;
5768                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5769                         decap = actions->conf;
5770                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5771                                 ;
5772                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5773                                 encap = NULL;
5774                                 actions--;
5775                         } else {
5776                                 encap = actions->conf;
5777                         }
5778                         ret = flow_dv_validate_action_raw_encap_decap
5779                                            (dev,
5780                                             decap ? decap : &empty_decap, encap,
5781                                             attr, &action_flags, &actions_n,
5782                                             error);
5783                         if (ret < 0)
5784                                 return ret;
5785                         break;
5786                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5787                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5788                         ret = flow_dv_validate_action_modify_mac(action_flags,
5789                                                                  actions,
5790                                                                  item_flags,
5791                                                                  error);
5792                         if (ret < 0)
5793                                 return ret;
5794                         /* Count all modify-header actions as one action. */
5795                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5796                                 ++actions_n;
5797                         action_flags |= actions->type ==
5798                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5799                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5800                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5801                         /*
5802                          * Even if the source and destination MAC addresses have
5803                          * overlap in the header with 4B alignment, the convert
5804                          * function will handle them separately and 4 SW actions
5805                          * will be created. And 2 actions will be added each
5806                          * time no matter how many bytes of address will be set.
5807                          */
5808                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5809                         break;
5810                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5811                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5812                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5813                                                                   actions,
5814                                                                   item_flags,
5815                                                                   error);
5816                         if (ret < 0)
5817                                 return ret;
5818                         /* Count all modify-header actions as one action. */
5819                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5820                                 ++actions_n;
5821                         action_flags |= actions->type ==
5822                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5823                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5824                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5825                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5826                         break;
5827                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5828                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5829                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5830                                                                   actions,
5831                                                                   item_flags,
5832                                                                   error);
5833                         if (ret < 0)
5834                                 return ret;
5835                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5836                                 return rte_flow_error_set(error, ENOTSUP,
5837                                         RTE_FLOW_ERROR_TYPE_ACTION,
5838                                         actions,
5839                                         "Can't change header "
5840                                         "with ICMPv6 proto");
5841                         /* Count all modify-header actions as one action. */
5842                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5843                                 ++actions_n;
5844                         action_flags |= actions->type ==
5845                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5846                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5847                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5848                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5849                         break;
5850                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5851                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5852                         ret = flow_dv_validate_action_modify_tp(action_flags,
5853                                                                 actions,
5854                                                                 item_flags,
5855                                                                 error);
5856                         if (ret < 0)
5857                                 return ret;
5858                         /* Count all modify-header actions as one action. */
5859                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5860                                 ++actions_n;
5861                         action_flags |= actions->type ==
5862                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5863                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5864                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5865                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5866                         break;
5867                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5868                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5869                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5870                                                                  actions,
5871                                                                  item_flags,
5872                                                                  error);
5873                         if (ret < 0)
5874                                 return ret;
5875                         /* Count all modify-header actions as one action. */
5876                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5877                                 ++actions_n;
5878                         action_flags |= actions->type ==
5879                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5880                                                 MLX5_FLOW_ACTION_SET_TTL :
5881                                                 MLX5_FLOW_ACTION_DEC_TTL;
5882                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5883                         break;
5884                 case RTE_FLOW_ACTION_TYPE_JUMP:
5885                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5886                                                            action_flags,
5887                                                            attr, external,
5888                                                            error);
5889                         if (ret)
5890                                 return ret;
5891                         ++actions_n;
5892                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5893                         break;
5894                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5895                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5896                         ret = flow_dv_validate_action_modify_tcp_seq
5897                                                                 (action_flags,
5898                                                                  actions,
5899                                                                  item_flags,
5900                                                                  error);
5901                         if (ret < 0)
5902                                 return ret;
5903                         /* Count all modify-header actions as one action. */
5904                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5905                                 ++actions_n;
5906                         action_flags |= actions->type ==
5907                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5908                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5909                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5910                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5911                         break;
5912                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5913                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5914                         ret = flow_dv_validate_action_modify_tcp_ack
5915                                                                 (action_flags,
5916                                                                  actions,
5917                                                                  item_flags,
5918                                                                  error);
5919                         if (ret < 0)
5920                                 return ret;
5921                         /* Count all modify-header actions as one action. */
5922                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5923                                 ++actions_n;
5924                         action_flags |= actions->type ==
5925                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5926                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5927                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5928                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5929                         break;
5930                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5931                         break;
5932                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5933                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5934                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5935                         break;
5936                 case RTE_FLOW_ACTION_TYPE_METER:
5937                         ret = mlx5_flow_validate_action_meter(dev,
5938                                                               action_flags,
5939                                                               actions, attr,
5940                                                               error);
5941                         if (ret < 0)
5942                                 return ret;
5943                         action_flags |= MLX5_FLOW_ACTION_METER;
5944                         ++actions_n;
5945                         /* Meter action will add one more TAG action. */
5946                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5947                         break;
5948                 case RTE_FLOW_ACTION_TYPE_AGE:
5949                         ret = flow_dv_validate_action_age(action_flags,
5950                                                           actions, dev,
5951                                                           error);
5952                         if (ret < 0)
5953                                 return ret;
5954                         action_flags |= MLX5_FLOW_ACTION_AGE;
5955                         ++actions_n;
5956                         break;
5957                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5958                         ret = flow_dv_validate_action_modify_ipv4_dscp
5959                                                          (action_flags,
5960                                                           actions,
5961                                                           item_flags,
5962                                                           error);
5963                         if (ret < 0)
5964                                 return ret;
5965                         /* Count all modify-header actions as one action. */
5966                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5967                                 ++actions_n;
5968                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5969                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5970                         break;
5971                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5972                         ret = flow_dv_validate_action_modify_ipv6_dscp
5973                                                                 (action_flags,
5974                                                                  actions,
5975                                                                  item_flags,
5976                                                                  error);
5977                         if (ret < 0)
5978                                 return ret;
5979                         /* Count all modify-header actions as one action. */
5980                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5981                                 ++actions_n;
5982                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5983                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5984                         break;
5985                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
5986                         ret = flow_dv_validate_action_sample(action_flags,
5987                                                              actions, dev,
5988                                                              attr, error);
5989                         if (ret < 0)
5990                                 return ret;
5991                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
5992                         ++actions_n;
5993                         break;
5994                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
5995                         if (actions[0].type != (typeof(actions[0].type))
5996                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
5997                                 return rte_flow_error_set
5998                                                 (error, EINVAL,
5999                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6000                                                 NULL, "MLX5 private action "
6001                                                 "must be the first");
6002
6003                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6004                         break;
6005                 default:
6006                         return rte_flow_error_set(error, ENOTSUP,
6007                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6008                                                   actions,
6009                                                   "action not supported");
6010                 }
6011         }
6012         /*
6013          * Validate actions in flow rules
6014          * - Explicit decap action is prohibited by the tunnel offload API.
6015          * - Drop action in tunnel steer rule is prohibited by the API.
6016          * - Application cannot use MARK action because it's value can mask
6017          *   tunnel default miss nitification.
6018          * - JUMP in tunnel match rule has no support in current PMD
6019          *   implementation.
6020          * - TAG & META are reserved for future uses.
6021          */
6022         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6023                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6024                                             MLX5_FLOW_ACTION_MARK     |
6025                                             MLX5_FLOW_ACTION_SET_TAG  |
6026                                             MLX5_FLOW_ACTION_SET_META |
6027                                             MLX5_FLOW_ACTION_DROP;
6028
6029                 if (action_flags & bad_actions_mask)
6030                         return rte_flow_error_set
6031                                         (error, EINVAL,
6032                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6033                                         "Invalid RTE action in tunnel "
6034                                         "set decap rule");
6035                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6036                         return rte_flow_error_set
6037                                         (error, EINVAL,
6038                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6039                                         "tunnel set decap rule must terminate "
6040                                         "with JUMP");
6041                 if (!attr->ingress)
6042                         return rte_flow_error_set
6043                                         (error, EINVAL,
6044                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6045                                         "tunnel flows for ingress traffic only");
6046         }
6047         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6048                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6049                                             MLX5_FLOW_ACTION_MARK    |
6050                                             MLX5_FLOW_ACTION_SET_TAG |
6051                                             MLX5_FLOW_ACTION_SET_META;
6052
6053                 if (action_flags & bad_actions_mask)
6054                         return rte_flow_error_set
6055                                         (error, EINVAL,
6056                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6057                                         "Invalid RTE action in tunnel "
6058                                         "set match rule");
6059         }
6060         /*
6061          * Validate the drop action mutual exclusion with other actions.
6062          * Drop action is mutually-exclusive with any other action, except for
6063          * Count action.
6064          */
6065         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6066             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6067                 return rte_flow_error_set(error, EINVAL,
6068                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6069                                           "Drop action is mutually-exclusive "
6070                                           "with any other action, except for "
6071                                           "Count action");
6072         /* Eswitch has few restrictions on using items and actions */
6073         if (attr->transfer) {
6074                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6075                     action_flags & MLX5_FLOW_ACTION_FLAG)
6076                         return rte_flow_error_set(error, ENOTSUP,
6077                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6078                                                   NULL,
6079                                                   "unsupported action FLAG");
6080                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6081                     action_flags & MLX5_FLOW_ACTION_MARK)
6082                         return rte_flow_error_set(error, ENOTSUP,
6083                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6084                                                   NULL,
6085                                                   "unsupported action MARK");
6086                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6087                         return rte_flow_error_set(error, ENOTSUP,
6088                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6089                                                   NULL,
6090                                                   "unsupported action QUEUE");
6091                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6092                         return rte_flow_error_set(error, ENOTSUP,
6093                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6094                                                   NULL,
6095                                                   "unsupported action RSS");
6096                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6097                         return rte_flow_error_set(error, EINVAL,
6098                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6099                                                   actions,
6100                                                   "no fate action is found");
6101         } else {
6102                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6103                         return rte_flow_error_set(error, EINVAL,
6104                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6105                                                   actions,
6106                                                   "no fate action is found");
6107         }
6108         /*
6109          * Continue validation for Xcap and VLAN actions.
6110          * If hairpin is working in explicit TX rule mode, there is no actions
6111          * splitting and the validation of hairpin ingress flow should be the
6112          * same as other standard flows.
6113          */
6114         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6115                              MLX5_FLOW_VLAN_ACTIONS)) &&
6116             (queue_index == 0xFFFF ||
6117              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6118              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6119              conf->tx_explicit != 0))) {
6120                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6121                     MLX5_FLOW_XCAP_ACTIONS)
6122                         return rte_flow_error_set(error, ENOTSUP,
6123                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6124                                                   NULL, "encap and decap "
6125                                                   "combination aren't supported");
6126                 if (!attr->transfer && attr->ingress) {
6127                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6128                                 return rte_flow_error_set
6129                                                 (error, ENOTSUP,
6130                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6131                                                  NULL, "encap is not supported"
6132                                                  " for ingress traffic");
6133                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6134                                 return rte_flow_error_set
6135                                                 (error, ENOTSUP,
6136                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6137                                                  NULL, "push VLAN action not "
6138                                                  "supported for ingress");
6139                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6140                                         MLX5_FLOW_VLAN_ACTIONS)
6141                                 return rte_flow_error_set
6142                                                 (error, ENOTSUP,
6143                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6144                                                  NULL, "no support for "
6145                                                  "multiple VLAN actions");
6146                 }
6147         }
6148         /*
6149          * Hairpin flow will add one more TAG action in TX implicit mode.
6150          * In TX explicit mode, there will be no hairpin flow ID.
6151          */
6152         if (hairpin > 0)
6153                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6154         /* extra metadata enabled: one more TAG action will be add. */
6155         if (dev_conf->dv_flow_en &&
6156             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6157             mlx5_flow_ext_mreg_supported(dev))
6158                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6159         if ((uint32_t)rw_act_num >
6160                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6161                 return rte_flow_error_set(error, ENOTSUP,
6162                                           RTE_FLOW_ERROR_TYPE_ACTION,
6163                                           NULL, "too many header modify"
6164                                           " actions to support");
6165         }
6166         return 0;
6167 }
6168
6169 /**
6170  * Internal preparation function. Allocates the DV flow size,
6171  * this size is constant.
6172  *
6173  * @param[in] dev
6174  *   Pointer to the rte_eth_dev structure.
6175  * @param[in] attr
6176  *   Pointer to the flow attributes.
6177  * @param[in] items
6178  *   Pointer to the list of items.
6179  * @param[in] actions
6180  *   Pointer to the list of actions.
6181  * @param[out] error
6182  *   Pointer to the error structure.
6183  *
6184  * @return
6185  *   Pointer to mlx5_flow object on success,
6186  *   otherwise NULL and rte_errno is set.
6187  */
6188 static struct mlx5_flow *
6189 flow_dv_prepare(struct rte_eth_dev *dev,
6190                 const struct rte_flow_attr *attr __rte_unused,
6191                 const struct rte_flow_item items[] __rte_unused,
6192                 const struct rte_flow_action actions[] __rte_unused,
6193                 struct rte_flow_error *error)
6194 {
6195         uint32_t handle_idx = 0;
6196         struct mlx5_flow *dev_flow;
6197         struct mlx5_flow_handle *dev_handle;
6198         struct mlx5_priv *priv = dev->data->dev_private;
6199         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6200
6201         MLX5_ASSERT(wks);
6202         /* In case of corrupting the memory. */
6203         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6204                 rte_flow_error_set(error, ENOSPC,
6205                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6206                                    "not free temporary device flow");
6207                 return NULL;
6208         }
6209         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6210                                    &handle_idx);
6211         if (!dev_handle) {
6212                 rte_flow_error_set(error, ENOMEM,
6213                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6214                                    "not enough memory to create flow handle");
6215                 return NULL;
6216         }
6217         MLX5_ASSERT(wks->flow_idx + 1 < RTE_DIM(wks->flows));
6218         dev_flow = &wks->flows[wks->flow_idx++];
6219         dev_flow->handle = dev_handle;
6220         dev_flow->handle_idx = handle_idx;
6221         /*
6222          * In some old rdma-core releases, before continuing, a check of the
6223          * length of matching parameter will be done at first. It needs to use
6224          * the length without misc4 param. If the flow has misc4 support, then
6225          * the length needs to be adjusted accordingly. Each param member is
6226          * aligned with a 64B boundary naturally.
6227          */
6228         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6229                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6230         /*
6231          * The matching value needs to be cleared to 0 before using. In the
6232          * past, it will be automatically cleared when using rte_*alloc
6233          * API. The time consumption will be almost the same as before.
6234          */
6235         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6236         dev_flow->ingress = attr->ingress;
6237         dev_flow->dv.transfer = attr->transfer;
6238         return dev_flow;
6239 }
6240
6241 #ifdef RTE_LIBRTE_MLX5_DEBUG
6242 /**
6243  * Sanity check for match mask and value. Similar to check_valid_spec() in
6244  * kernel driver. If unmasked bit is present in value, it returns failure.
6245  *
6246  * @param match_mask
6247  *   pointer to match mask buffer.
6248  * @param match_value
6249  *   pointer to match value buffer.
6250  *
6251  * @return
6252  *   0 if valid, -EINVAL otherwise.
6253  */
6254 static int
6255 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6256 {
6257         uint8_t *m = match_mask;
6258         uint8_t *v = match_value;
6259         unsigned int i;
6260
6261         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6262                 if (v[i] & ~m[i]) {
6263                         DRV_LOG(ERR,
6264                                 "match_value differs from match_criteria"
6265                                 " %p[%u] != %p[%u]",
6266                                 match_value, i, match_mask, i);
6267                         return -EINVAL;
6268                 }
6269         }
6270         return 0;
6271 }
6272 #endif
6273
6274 /**
6275  * Add match of ip_version.
6276  *
6277  * @param[in] group
6278  *   Flow group.
6279  * @param[in] headers_v
6280  *   Values header pointer.
6281  * @param[in] headers_m
6282  *   Masks header pointer.
6283  * @param[in] ip_version
6284  *   The IP version to set.
6285  */
6286 static inline void
6287 flow_dv_set_match_ip_version(uint32_t group,
6288                              void *headers_v,
6289                              void *headers_m,
6290                              uint8_t ip_version)
6291 {
6292         if (group == 0)
6293                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6294         else
6295                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6296                          ip_version);
6297         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6298         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6299         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6300 }
6301
6302 /**
6303  * Add Ethernet item to matcher and to the value.
6304  *
6305  * @param[in, out] matcher
6306  *   Flow matcher.
6307  * @param[in, out] key
6308  *   Flow matcher value.
6309  * @param[in] item
6310  *   Flow pattern to translate.
6311  * @param[in] inner
6312  *   Item is inner pattern.
6313  */
6314 static void
6315 flow_dv_translate_item_eth(void *matcher, void *key,
6316                            const struct rte_flow_item *item, int inner,
6317                            uint32_t group)
6318 {
6319         const struct rte_flow_item_eth *eth_m = item->mask;
6320         const struct rte_flow_item_eth *eth_v = item->spec;
6321         const struct rte_flow_item_eth nic_mask = {
6322                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6323                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6324                 .type = RTE_BE16(0xffff),
6325                 .has_vlan = 0,
6326         };
6327         void *hdrs_m;
6328         void *hdrs_v;
6329         char *l24_v;
6330         unsigned int i;
6331
6332         if (!eth_v)
6333                 return;
6334         if (!eth_m)
6335                 eth_m = &nic_mask;
6336         if (inner) {
6337                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6338                                          inner_headers);
6339                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6340         } else {
6341                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6342                                          outer_headers);
6343                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6344         }
6345         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6346                &eth_m->dst, sizeof(eth_m->dst));
6347         /* The value must be in the range of the mask. */
6348         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6349         for (i = 0; i < sizeof(eth_m->dst); ++i)
6350                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6351         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6352                &eth_m->src, sizeof(eth_m->src));
6353         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6354         /* The value must be in the range of the mask. */
6355         for (i = 0; i < sizeof(eth_m->dst); ++i)
6356                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6357         /*
6358          * HW supports match on one Ethertype, the Ethertype following the last
6359          * VLAN tag of the packet (see PRM).
6360          * Set match on ethertype only if ETH header is not followed by VLAN.
6361          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6362          * ethertype, and use ip_version field instead.
6363          * eCPRI over Ether layer will use type value 0xAEFE.
6364          */
6365         if (eth_m->type == 0xFFFF) {
6366                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6367                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6368                 switch (eth_v->type) {
6369                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6370                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6371                         return;
6372                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6373                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6374                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6375                         return;
6376                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6377                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6378                         return;
6379                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6380                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6381                         return;
6382                 default:
6383                         break;
6384                 }
6385         }
6386         if (eth_m->has_vlan) {
6387                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6388                 if (eth_v->has_vlan) {
6389                         /*
6390                          * Here, when also has_more_vlan field in VLAN item is
6391                          * not set, only single-tagged packets will be matched.
6392                          */
6393                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6394                         return;
6395                 }
6396         }
6397         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6398                  rte_be_to_cpu_16(eth_m->type));
6399         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6400         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6401 }
6402
6403 /**
6404  * Add VLAN item to matcher and to the value.
6405  *
6406  * @param[in, out] dev_flow
6407  *   Flow descriptor.
6408  * @param[in, out] matcher
6409  *   Flow matcher.
6410  * @param[in, out] key
6411  *   Flow matcher value.
6412  * @param[in] item
6413  *   Flow pattern to translate.
6414  * @param[in] inner
6415  *   Item is inner pattern.
6416  */
6417 static void
6418 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6419                             void *matcher, void *key,
6420                             const struct rte_flow_item *item,
6421                             int inner, uint32_t group)
6422 {
6423         const struct rte_flow_item_vlan *vlan_m = item->mask;
6424         const struct rte_flow_item_vlan *vlan_v = item->spec;
6425         void *hdrs_m;
6426         void *hdrs_v;
6427         uint16_t tci_m;
6428         uint16_t tci_v;
6429
6430         if (inner) {
6431                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6432                                          inner_headers);
6433                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6434         } else {
6435                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6436                                          outer_headers);
6437                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6438                 /*
6439                  * This is workaround, masks are not supported,
6440                  * and pre-validated.
6441                  */
6442                 if (vlan_v)
6443                         dev_flow->handle->vf_vlan.tag =
6444                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6445         }
6446         /*
6447          * When VLAN item exists in flow, mark packet as tagged,
6448          * even if TCI is not specified.
6449          */
6450         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6451                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6452                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6453         }
6454         if (!vlan_v)
6455                 return;
6456         if (!vlan_m)
6457                 vlan_m = &rte_flow_item_vlan_mask;
6458         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6459         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6460         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6461         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6462         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6463         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6464         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6465         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6466         /*
6467          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6468          * ethertype, and use ip_version field instead.
6469          */
6470         if (vlan_m->inner_type == 0xFFFF) {
6471                 switch (vlan_v->inner_type) {
6472                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6473                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6474                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6475                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6476                         return;
6477                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6478                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6479                         return;
6480                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6481                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6482                         return;
6483                 default:
6484                         break;
6485                 }
6486         }
6487         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6488                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6489                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6490                 /* Only one vlan_tag bit can be set. */
6491                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6492                 return;
6493         }
6494         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6495                  rte_be_to_cpu_16(vlan_m->inner_type));
6496         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6497                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6498 }
6499
6500 /**
6501  * Add IPV4 item to matcher and to the value.
6502  *
6503  * @param[in, out] matcher
6504  *   Flow matcher.
6505  * @param[in, out] key
6506  *   Flow matcher value.
6507  * @param[in] item
6508  *   Flow pattern to translate.
6509  * @param[in] inner
6510  *   Item is inner pattern.
6511  * @param[in] group
6512  *   The group to insert the rule.
6513  */
6514 static void
6515 flow_dv_translate_item_ipv4(void *matcher, void *key,
6516                             const struct rte_flow_item *item,
6517                             int inner, uint32_t group)
6518 {
6519         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6520         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6521         const struct rte_flow_item_ipv4 nic_mask = {
6522                 .hdr = {
6523                         .src_addr = RTE_BE32(0xffffffff),
6524                         .dst_addr = RTE_BE32(0xffffffff),
6525                         .type_of_service = 0xff,
6526                         .next_proto_id = 0xff,
6527                         .time_to_live = 0xff,
6528                 },
6529         };
6530         void *headers_m;
6531         void *headers_v;
6532         char *l24_m;
6533         char *l24_v;
6534         uint8_t tos;
6535
6536         if (inner) {
6537                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6538                                          inner_headers);
6539                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6540         } else {
6541                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6542                                          outer_headers);
6543                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6544         }
6545         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6546         if (!ipv4_v)
6547                 return;
6548         if (!ipv4_m)
6549                 ipv4_m = &nic_mask;
6550         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6551                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6552         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6553                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6554         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6555         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6556         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6557                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6558         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6559                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6560         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6561         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6562         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6563         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6564                  ipv4_m->hdr.type_of_service);
6565         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6566         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6567                  ipv4_m->hdr.type_of_service >> 2);
6568         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6569         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6570                  ipv4_m->hdr.next_proto_id);
6571         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6572                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6573         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6574                  ipv4_m->hdr.time_to_live);
6575         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6576                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6577         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6578                  !!(ipv4_m->hdr.fragment_offset));
6579         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6580                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6581 }
6582
6583 /**
6584  * Add IPV6 item to matcher and to the value.
6585  *
6586  * @param[in, out] matcher
6587  *   Flow matcher.
6588  * @param[in, out] key
6589  *   Flow matcher value.
6590  * @param[in] item
6591  *   Flow pattern to translate.
6592  * @param[in] inner
6593  *   Item is inner pattern.
6594  * @param[in] group
6595  *   The group to insert the rule.
6596  */
6597 static void
6598 flow_dv_translate_item_ipv6(void *matcher, void *key,
6599                             const struct rte_flow_item *item,
6600                             int inner, uint32_t group)
6601 {
6602         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6603         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6604         const struct rte_flow_item_ipv6 nic_mask = {
6605                 .hdr = {
6606                         .src_addr =
6607                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6608                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6609                         .dst_addr =
6610                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6611                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6612                         .vtc_flow = RTE_BE32(0xffffffff),
6613                         .proto = 0xff,
6614                         .hop_limits = 0xff,
6615                 },
6616         };
6617         void *headers_m;
6618         void *headers_v;
6619         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6620         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6621         char *l24_m;
6622         char *l24_v;
6623         uint32_t vtc_m;
6624         uint32_t vtc_v;
6625         int i;
6626         int size;
6627
6628         if (inner) {
6629                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6630                                          inner_headers);
6631                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6632         } else {
6633                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6634                                          outer_headers);
6635                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6636         }
6637         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6638         if (!ipv6_v)
6639                 return;
6640         if (!ipv6_m)
6641                 ipv6_m = &nic_mask;
6642         size = sizeof(ipv6_m->hdr.dst_addr);
6643         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6644                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6645         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6646                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6647         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6648         for (i = 0; i < size; ++i)
6649                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6650         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6651                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6652         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6653                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6654         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6655         for (i = 0; i < size; ++i)
6656                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6657         /* TOS. */
6658         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6659         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6660         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6661         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6662         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6663         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6664         /* Label. */
6665         if (inner) {
6666                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6667                          vtc_m);
6668                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6669                          vtc_v);
6670         } else {
6671                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6672                          vtc_m);
6673                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6674                          vtc_v);
6675         }
6676         /* Protocol. */
6677         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6678                  ipv6_m->hdr.proto);
6679         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6680                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6681         /* Hop limit. */
6682         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6683                  ipv6_m->hdr.hop_limits);
6684         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6685                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6686         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6687                  !!(ipv6_m->has_frag_ext));
6688         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6689                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6690 }
6691
6692 /**
6693  * Add IPV6 fragment extension item to matcher and to the value.
6694  *
6695  * @param[in, out] matcher
6696  *   Flow matcher.
6697  * @param[in, out] key
6698  *   Flow matcher value.
6699  * @param[in] item
6700  *   Flow pattern to translate.
6701  * @param[in] inner
6702  *   Item is inner pattern.
6703  */
6704 static void
6705 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6706                                      const struct rte_flow_item *item,
6707                                      int inner)
6708 {
6709         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6710         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6711         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6712                 .hdr = {
6713                         .next_header = 0xff,
6714                         .frag_data = RTE_BE16(0xffff),
6715                 },
6716         };
6717         void *headers_m;
6718         void *headers_v;
6719
6720         if (inner) {
6721                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6722                                          inner_headers);
6723                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6724         } else {
6725                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6726                                          outer_headers);
6727                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6728         }
6729         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6730         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6731         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6732         if (!ipv6_frag_ext_v)
6733                 return;
6734         if (!ipv6_frag_ext_m)
6735                 ipv6_frag_ext_m = &nic_mask;
6736         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6737                  ipv6_frag_ext_m->hdr.next_header);
6738         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6739                  ipv6_frag_ext_v->hdr.next_header &
6740                  ipv6_frag_ext_m->hdr.next_header);
6741 }
6742
6743 /**
6744  * Add TCP item to matcher and to the value.
6745  *
6746  * @param[in, out] matcher
6747  *   Flow matcher.
6748  * @param[in, out] key
6749  *   Flow matcher value.
6750  * @param[in] item
6751  *   Flow pattern to translate.
6752  * @param[in] inner
6753  *   Item is inner pattern.
6754  */
6755 static void
6756 flow_dv_translate_item_tcp(void *matcher, void *key,
6757                            const struct rte_flow_item *item,
6758                            int inner)
6759 {
6760         const struct rte_flow_item_tcp *tcp_m = item->mask;
6761         const struct rte_flow_item_tcp *tcp_v = item->spec;
6762         void *headers_m;
6763         void *headers_v;
6764
6765         if (inner) {
6766                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6767                                          inner_headers);
6768                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6769         } else {
6770                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6771                                          outer_headers);
6772                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6773         }
6774         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6775         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6776         if (!tcp_v)
6777                 return;
6778         if (!tcp_m)
6779                 tcp_m = &rte_flow_item_tcp_mask;
6780         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6781                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6782         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6783                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6784         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6785                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6786         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6787                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6788         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6789                  tcp_m->hdr.tcp_flags);
6790         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6791                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6792 }
6793
6794 /**
6795  * Add UDP item to matcher and to the value.
6796  *
6797  * @param[in, out] matcher
6798  *   Flow matcher.
6799  * @param[in, out] key
6800  *   Flow matcher value.
6801  * @param[in] item
6802  *   Flow pattern to translate.
6803  * @param[in] inner
6804  *   Item is inner pattern.
6805  */
6806 static void
6807 flow_dv_translate_item_udp(void *matcher, void *key,
6808                            const struct rte_flow_item *item,
6809                            int inner)
6810 {
6811         const struct rte_flow_item_udp *udp_m = item->mask;
6812         const struct rte_flow_item_udp *udp_v = item->spec;
6813         void *headers_m;
6814         void *headers_v;
6815
6816         if (inner) {
6817                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6818                                          inner_headers);
6819                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6820         } else {
6821                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6822                                          outer_headers);
6823                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6824         }
6825         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6826         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6827         if (!udp_v)
6828                 return;
6829         if (!udp_m)
6830                 udp_m = &rte_flow_item_udp_mask;
6831         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6832                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6833         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6834                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6835         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6836                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6837         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6838                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6839 }
6840
6841 /**
6842  * Add GRE optional Key item to matcher and to the value.
6843  *
6844  * @param[in, out] matcher
6845  *   Flow matcher.
6846  * @param[in, out] key
6847  *   Flow matcher value.
6848  * @param[in] item
6849  *   Flow pattern to translate.
6850  * @param[in] inner
6851  *   Item is inner pattern.
6852  */
6853 static void
6854 flow_dv_translate_item_gre_key(void *matcher, void *key,
6855                                    const struct rte_flow_item *item)
6856 {
6857         const rte_be32_t *key_m = item->mask;
6858         const rte_be32_t *key_v = item->spec;
6859         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6860         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6861         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6862
6863         /* GRE K bit must be on and should already be validated */
6864         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6865         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6866         if (!key_v)
6867                 return;
6868         if (!key_m)
6869                 key_m = &gre_key_default_mask;
6870         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6871                  rte_be_to_cpu_32(*key_m) >> 8);
6872         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6873                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6874         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6875                  rte_be_to_cpu_32(*key_m) & 0xFF);
6876         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6877                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6878 }
6879
6880 /**
6881  * Add GRE item to matcher and to the value.
6882  *
6883  * @param[in, out] matcher
6884  *   Flow matcher.
6885  * @param[in, out] key
6886  *   Flow matcher value.
6887  * @param[in] item
6888  *   Flow pattern to translate.
6889  * @param[in] inner
6890  *   Item is inner pattern.
6891  */
6892 static void
6893 flow_dv_translate_item_gre(void *matcher, void *key,
6894                            const struct rte_flow_item *item,
6895                            int inner)
6896 {
6897         const struct rte_flow_item_gre *gre_m = item->mask;
6898         const struct rte_flow_item_gre *gre_v = item->spec;
6899         void *headers_m;
6900         void *headers_v;
6901         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6902         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6903         struct {
6904                 union {
6905                         __extension__
6906                         struct {
6907                                 uint16_t version:3;
6908                                 uint16_t rsvd0:9;
6909                                 uint16_t s_present:1;
6910                                 uint16_t k_present:1;
6911                                 uint16_t rsvd_bit1:1;
6912                                 uint16_t c_present:1;
6913                         };
6914                         uint16_t value;
6915                 };
6916         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6917
6918         if (inner) {
6919                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6920                                          inner_headers);
6921                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6922         } else {
6923                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6924                                          outer_headers);
6925                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6926         }
6927         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6928         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6929         if (!gre_v)
6930                 return;
6931         if (!gre_m)
6932                 gre_m = &rte_flow_item_gre_mask;
6933         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6934                  rte_be_to_cpu_16(gre_m->protocol));
6935         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6936                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6937         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6938         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6939         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6940                  gre_crks_rsvd0_ver_m.c_present);
6941         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6942                  gre_crks_rsvd0_ver_v.c_present &
6943                  gre_crks_rsvd0_ver_m.c_present);
6944         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6945                  gre_crks_rsvd0_ver_m.k_present);
6946         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6947                  gre_crks_rsvd0_ver_v.k_present &
6948                  gre_crks_rsvd0_ver_m.k_present);
6949         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6950                  gre_crks_rsvd0_ver_m.s_present);
6951         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6952                  gre_crks_rsvd0_ver_v.s_present &
6953                  gre_crks_rsvd0_ver_m.s_present);
6954 }
6955
6956 /**
6957  * Add NVGRE item to matcher and to the value.
6958  *
6959  * @param[in, out] matcher
6960  *   Flow matcher.
6961  * @param[in, out] key
6962  *   Flow matcher value.
6963  * @param[in] item
6964  *   Flow pattern to translate.
6965  * @param[in] inner
6966  *   Item is inner pattern.
6967  */
6968 static void
6969 flow_dv_translate_item_nvgre(void *matcher, void *key,
6970                              const struct rte_flow_item *item,
6971                              int inner)
6972 {
6973         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6974         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6975         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6976         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6977         const char *tni_flow_id_m;
6978         const char *tni_flow_id_v;
6979         char *gre_key_m;
6980         char *gre_key_v;
6981         int size;
6982         int i;
6983
6984         /* For NVGRE, GRE header fields must be set with defined values. */
6985         const struct rte_flow_item_gre gre_spec = {
6986                 .c_rsvd0_ver = RTE_BE16(0x2000),
6987                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6988         };
6989         const struct rte_flow_item_gre gre_mask = {
6990                 .c_rsvd0_ver = RTE_BE16(0xB000),
6991                 .protocol = RTE_BE16(UINT16_MAX),
6992         };
6993         const struct rte_flow_item gre_item = {
6994                 .spec = &gre_spec,
6995                 .mask = &gre_mask,
6996                 .last = NULL,
6997         };
6998         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6999         if (!nvgre_v)
7000                 return;
7001         if (!nvgre_m)
7002                 nvgre_m = &rte_flow_item_nvgre_mask;
7003         tni_flow_id_m = (const char *)nvgre_m->tni;
7004         tni_flow_id_v = (const char *)nvgre_v->tni;
7005         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7006         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7007         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7008         memcpy(gre_key_m, tni_flow_id_m, size);
7009         for (i = 0; i < size; ++i)
7010                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7011 }
7012
7013 /**
7014  * Add VXLAN item to matcher and to the value.
7015  *
7016  * @param[in, out] matcher
7017  *   Flow matcher.
7018  * @param[in, out] key
7019  *   Flow matcher value.
7020  * @param[in] item
7021  *   Flow pattern to translate.
7022  * @param[in] inner
7023  *   Item is inner pattern.
7024  */
7025 static void
7026 flow_dv_translate_item_vxlan(void *matcher, void *key,
7027                              const struct rte_flow_item *item,
7028                              int inner)
7029 {
7030         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7031         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7032         void *headers_m;
7033         void *headers_v;
7034         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7035         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7036         char *vni_m;
7037         char *vni_v;
7038         uint16_t dport;
7039         int size;
7040         int i;
7041
7042         if (inner) {
7043                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7044                                          inner_headers);
7045                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7046         } else {
7047                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7048                                          outer_headers);
7049                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7050         }
7051         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7052                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7053         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7054                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7055                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7056         }
7057         if (!vxlan_v)
7058                 return;
7059         if (!vxlan_m)
7060                 vxlan_m = &rte_flow_item_vxlan_mask;
7061         size = sizeof(vxlan_m->vni);
7062         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7063         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7064         memcpy(vni_m, vxlan_m->vni, size);
7065         for (i = 0; i < size; ++i)
7066                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7067 }
7068
7069 /**
7070  * Add VXLAN-GPE item to matcher and to the value.
7071  *
7072  * @param[in, out] matcher
7073  *   Flow matcher.
7074  * @param[in, out] key
7075  *   Flow matcher value.
7076  * @param[in] item
7077  *   Flow pattern to translate.
7078  * @param[in] inner
7079  *   Item is inner pattern.
7080  */
7081
7082 static void
7083 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7084                                  const struct rte_flow_item *item, int inner)
7085 {
7086         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7087         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7088         void *headers_m;
7089         void *headers_v;
7090         void *misc_m =
7091                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7092         void *misc_v =
7093                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7094         char *vni_m;
7095         char *vni_v;
7096         uint16_t dport;
7097         int size;
7098         int i;
7099         uint8_t flags_m = 0xff;
7100         uint8_t flags_v = 0xc;
7101
7102         if (inner) {
7103                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7104                                          inner_headers);
7105                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7106         } else {
7107                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7108                                          outer_headers);
7109                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7110         }
7111         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7112                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7113         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7114                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7115                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7116         }
7117         if (!vxlan_v)
7118                 return;
7119         if (!vxlan_m)
7120                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7121         size = sizeof(vxlan_m->vni);
7122         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7123         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7124         memcpy(vni_m, vxlan_m->vni, size);
7125         for (i = 0; i < size; ++i)
7126                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7127         if (vxlan_m->flags) {
7128                 flags_m = vxlan_m->flags;
7129                 flags_v = vxlan_v->flags;
7130         }
7131         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7132         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7133         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7134                  vxlan_m->protocol);
7135         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7136                  vxlan_v->protocol);
7137 }
7138
7139 /**
7140  * Add Geneve item to matcher and to the value.
7141  *
7142  * @param[in, out] matcher
7143  *   Flow matcher.
7144  * @param[in, out] key
7145  *   Flow matcher value.
7146  * @param[in] item
7147  *   Flow pattern to translate.
7148  * @param[in] inner
7149  *   Item is inner pattern.
7150  */
7151
7152 static void
7153 flow_dv_translate_item_geneve(void *matcher, void *key,
7154                               const struct rte_flow_item *item, int inner)
7155 {
7156         const struct rte_flow_item_geneve *geneve_m = item->mask;
7157         const struct rte_flow_item_geneve *geneve_v = item->spec;
7158         void *headers_m;
7159         void *headers_v;
7160         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7161         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7162         uint16_t dport;
7163         uint16_t gbhdr_m;
7164         uint16_t gbhdr_v;
7165         char *vni_m;
7166         char *vni_v;
7167         size_t size, i;
7168
7169         if (inner) {
7170                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7171                                          inner_headers);
7172                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7173         } else {
7174                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7175                                          outer_headers);
7176                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7177         }
7178         dport = MLX5_UDP_PORT_GENEVE;
7179         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7180                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7181                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7182         }
7183         if (!geneve_v)
7184                 return;
7185         if (!geneve_m)
7186                 geneve_m = &rte_flow_item_geneve_mask;
7187         size = sizeof(geneve_m->vni);
7188         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7189         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7190         memcpy(vni_m, geneve_m->vni, size);
7191         for (i = 0; i < size; ++i)
7192                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7193         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7194                  rte_be_to_cpu_16(geneve_m->protocol));
7195         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7196                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7197         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7198         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7199         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7200                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7201         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7202                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7203         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7204                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7205         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7206                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7207                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7208 }
7209
7210 /**
7211  * Add MPLS item to matcher and to the value.
7212  *
7213  * @param[in, out] matcher
7214  *   Flow matcher.
7215  * @param[in, out] key
7216  *   Flow matcher value.
7217  * @param[in] item
7218  *   Flow pattern to translate.
7219  * @param[in] prev_layer
7220  *   The protocol layer indicated in previous item.
7221  * @param[in] inner
7222  *   Item is inner pattern.
7223  */
7224 static void
7225 flow_dv_translate_item_mpls(void *matcher, void *key,
7226                             const struct rte_flow_item *item,
7227                             uint64_t prev_layer,
7228                             int inner)
7229 {
7230         const uint32_t *in_mpls_m = item->mask;
7231         const uint32_t *in_mpls_v = item->spec;
7232         uint32_t *out_mpls_m = 0;
7233         uint32_t *out_mpls_v = 0;
7234         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7235         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7236         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7237                                      misc_parameters_2);
7238         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7239         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7240         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7241
7242         switch (prev_layer) {
7243         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7244                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7245                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7246                          MLX5_UDP_PORT_MPLS);
7247                 break;
7248         case MLX5_FLOW_LAYER_GRE:
7249                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7250                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7251                          RTE_ETHER_TYPE_MPLS);
7252                 break;
7253         default:
7254                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7255                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7256                          IPPROTO_MPLS);
7257                 break;
7258         }
7259         if (!in_mpls_v)
7260                 return;
7261         if (!in_mpls_m)
7262                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7263         switch (prev_layer) {
7264         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7265                 out_mpls_m =
7266                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7267                                                  outer_first_mpls_over_udp);
7268                 out_mpls_v =
7269                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7270                                                  outer_first_mpls_over_udp);
7271                 break;
7272         case MLX5_FLOW_LAYER_GRE:
7273                 out_mpls_m =
7274                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7275                                                  outer_first_mpls_over_gre);
7276                 out_mpls_v =
7277                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7278                                                  outer_first_mpls_over_gre);
7279                 break;
7280         default:
7281                 /* Inner MPLS not over GRE is not supported. */
7282                 if (!inner) {
7283                         out_mpls_m =
7284                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7285                                                          misc2_m,
7286                                                          outer_first_mpls);
7287                         out_mpls_v =
7288                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7289                                                          misc2_v,
7290                                                          outer_first_mpls);
7291                 }
7292                 break;
7293         }
7294         if (out_mpls_m && out_mpls_v) {
7295                 *out_mpls_m = *in_mpls_m;
7296                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7297         }
7298 }
7299
7300 /**
7301  * Add metadata register item to matcher
7302  *
7303  * @param[in, out] matcher
7304  *   Flow matcher.
7305  * @param[in, out] key
7306  *   Flow matcher value.
7307  * @param[in] reg_type
7308  *   Type of device metadata register
7309  * @param[in] value
7310  *   Register value
7311  * @param[in] mask
7312  *   Register mask
7313  */
7314 static void
7315 flow_dv_match_meta_reg(void *matcher, void *key,
7316                        enum modify_reg reg_type,
7317                        uint32_t data, uint32_t mask)
7318 {
7319         void *misc2_m =
7320                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7321         void *misc2_v =
7322                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7323         uint32_t temp;
7324
7325         data &= mask;
7326         switch (reg_type) {
7327         case REG_A:
7328                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7329                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7330                 break;
7331         case REG_B:
7332                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7333                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7334                 break;
7335         case REG_C_0:
7336                 /*
7337                  * The metadata register C0 field might be divided into
7338                  * source vport index and META item value, we should set
7339                  * this field according to specified mask, not as whole one.
7340                  */
7341                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7342                 temp |= mask;
7343                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7344                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7345                 temp &= ~mask;
7346                 temp |= data;
7347                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7348                 break;
7349         case REG_C_1:
7350                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7351                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7352                 break;
7353         case REG_C_2:
7354                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7355                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7356                 break;
7357         case REG_C_3:
7358                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7359                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7360                 break;
7361         case REG_C_4:
7362                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7363                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7364                 break;
7365         case REG_C_5:
7366                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7367                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7368                 break;
7369         case REG_C_6:
7370                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7371                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7372                 break;
7373         case REG_C_7:
7374                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7375                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7376                 break;
7377         default:
7378                 MLX5_ASSERT(false);
7379                 break;
7380         }
7381 }
7382
7383 /**
7384  * Add MARK item to matcher
7385  *
7386  * @param[in] dev
7387  *   The device to configure through.
7388  * @param[in, out] matcher
7389  *   Flow matcher.
7390  * @param[in, out] key
7391  *   Flow matcher value.
7392  * @param[in] item
7393  *   Flow pattern to translate.
7394  */
7395 static void
7396 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7397                             void *matcher, void *key,
7398                             const struct rte_flow_item *item)
7399 {
7400         struct mlx5_priv *priv = dev->data->dev_private;
7401         const struct rte_flow_item_mark *mark;
7402         uint32_t value;
7403         uint32_t mask;
7404
7405         mark = item->mask ? (const void *)item->mask :
7406                             &rte_flow_item_mark_mask;
7407         mask = mark->id & priv->sh->dv_mark_mask;
7408         mark = (const void *)item->spec;
7409         MLX5_ASSERT(mark);
7410         value = mark->id & priv->sh->dv_mark_mask & mask;
7411         if (mask) {
7412                 enum modify_reg reg;
7413
7414                 /* Get the metadata register index for the mark. */
7415                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7416                 MLX5_ASSERT(reg > 0);
7417                 if (reg == REG_C_0) {
7418                         struct mlx5_priv *priv = dev->data->dev_private;
7419                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7420                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7421
7422                         mask &= msk_c0;
7423                         mask <<= shl_c0;
7424                         value <<= shl_c0;
7425                 }
7426                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7427         }
7428 }
7429
7430 /**
7431  * Add META item to matcher
7432  *
7433  * @param[in] dev
7434  *   The devich to configure through.
7435  * @param[in, out] matcher
7436  *   Flow matcher.
7437  * @param[in, out] key
7438  *   Flow matcher value.
7439  * @param[in] attr
7440  *   Attributes of flow that includes this item.
7441  * @param[in] item
7442  *   Flow pattern to translate.
7443  */
7444 static void
7445 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7446                             void *matcher, void *key,
7447                             const struct rte_flow_attr *attr,
7448                             const struct rte_flow_item *item)
7449 {
7450         const struct rte_flow_item_meta *meta_m;
7451         const struct rte_flow_item_meta *meta_v;
7452
7453         meta_m = (const void *)item->mask;
7454         if (!meta_m)
7455                 meta_m = &rte_flow_item_meta_mask;
7456         meta_v = (const void *)item->spec;
7457         if (meta_v) {
7458                 int reg;
7459                 uint32_t value = meta_v->data;
7460                 uint32_t mask = meta_m->data;
7461
7462                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7463                 if (reg < 0)
7464                         return;
7465                 /*
7466                  * In datapath code there is no endianness
7467                  * coversions for perfromance reasons, all
7468                  * pattern conversions are done in rte_flow.
7469                  */
7470                 value = rte_cpu_to_be_32(value);
7471                 mask = rte_cpu_to_be_32(mask);
7472                 if (reg == REG_C_0) {
7473                         struct mlx5_priv *priv = dev->data->dev_private;
7474                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7475                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7476 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7477                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7478
7479                         value >>= shr_c0;
7480                         mask >>= shr_c0;
7481 #endif
7482                         value <<= shl_c0;
7483                         mask <<= shl_c0;
7484                         MLX5_ASSERT(msk_c0);
7485                         MLX5_ASSERT(!(~msk_c0 & mask));
7486                 }
7487                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7488         }
7489 }
7490
7491 /**
7492  * Add vport metadata Reg C0 item to matcher
7493  *
7494  * @param[in, out] matcher
7495  *   Flow matcher.
7496  * @param[in, out] key
7497  *   Flow matcher value.
7498  * @param[in] reg
7499  *   Flow pattern to translate.
7500  */
7501 static void
7502 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7503                                   uint32_t value, uint32_t mask)
7504 {
7505         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7506 }
7507
7508 /**
7509  * Add tag item to matcher
7510  *
7511  * @param[in] dev
7512  *   The devich to configure through.
7513  * @param[in, out] matcher
7514  *   Flow matcher.
7515  * @param[in, out] key
7516  *   Flow matcher value.
7517  * @param[in] item
7518  *   Flow pattern to translate.
7519  */
7520 static void
7521 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7522                                 void *matcher, void *key,
7523                                 const struct rte_flow_item *item)
7524 {
7525         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7526         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7527         uint32_t mask, value;
7528
7529         MLX5_ASSERT(tag_v);
7530         value = tag_v->data;
7531         mask = tag_m ? tag_m->data : UINT32_MAX;
7532         if (tag_v->id == REG_C_0) {
7533                 struct mlx5_priv *priv = dev->data->dev_private;
7534                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7535                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7536
7537                 mask &= msk_c0;
7538                 mask <<= shl_c0;
7539                 value <<= shl_c0;
7540         }
7541         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7542 }
7543
7544 /**
7545  * Add TAG item to matcher
7546  *
7547  * @param[in] dev
7548  *   The devich to configure through.
7549  * @param[in, out] matcher
7550  *   Flow matcher.
7551  * @param[in, out] key
7552  *   Flow matcher value.
7553  * @param[in] item
7554  *   Flow pattern to translate.
7555  */
7556 static void
7557 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7558                            void *matcher, void *key,
7559                            const struct rte_flow_item *item)
7560 {
7561         const struct rte_flow_item_tag *tag_v = item->spec;
7562         const struct rte_flow_item_tag *tag_m = item->mask;
7563         enum modify_reg reg;
7564
7565         MLX5_ASSERT(tag_v);
7566         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7567         /* Get the metadata register index for the tag. */
7568         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7569         MLX5_ASSERT(reg > 0);
7570         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7571 }
7572
7573 /**
7574  * Add source vport match to the specified matcher.
7575  *
7576  * @param[in, out] matcher
7577  *   Flow matcher.
7578  * @param[in, out] key
7579  *   Flow matcher value.
7580  * @param[in] port
7581  *   Source vport value to match
7582  * @param[in] mask
7583  *   Mask
7584  */
7585 static void
7586 flow_dv_translate_item_source_vport(void *matcher, void *key,
7587                                     int16_t port, uint16_t mask)
7588 {
7589         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7590         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7591
7592         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7593         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7594 }
7595
7596 /**
7597  * Translate port-id item to eswitch match on  port-id.
7598  *
7599  * @param[in] dev
7600  *   The devich to configure through.
7601  * @param[in, out] matcher
7602  *   Flow matcher.
7603  * @param[in, out] key
7604  *   Flow matcher value.
7605  * @param[in] item
7606  *   Flow pattern to translate.
7607  *
7608  * @return
7609  *   0 on success, a negative errno value otherwise.
7610  */
7611 static int
7612 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7613                                void *key, const struct rte_flow_item *item)
7614 {
7615         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7616         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7617         struct mlx5_priv *priv;
7618         uint16_t mask, id;
7619
7620         mask = pid_m ? pid_m->id : 0xffff;
7621         id = pid_v ? pid_v->id : dev->data->port_id;
7622         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7623         if (!priv)
7624                 return -rte_errno;
7625         /* Translate to vport field or to metadata, depending on mode. */
7626         if (priv->vport_meta_mask)
7627                 flow_dv_translate_item_meta_vport(matcher, key,
7628                                                   priv->vport_meta_tag,
7629                                                   priv->vport_meta_mask);
7630         else
7631                 flow_dv_translate_item_source_vport(matcher, key,
7632                                                     priv->vport_id, mask);
7633         return 0;
7634 }
7635
7636 /**
7637  * Add ICMP6 item to matcher and to the value.
7638  *
7639  * @param[in, out] matcher
7640  *   Flow matcher.
7641  * @param[in, out] key
7642  *   Flow matcher value.
7643  * @param[in] item
7644  *   Flow pattern to translate.
7645  * @param[in] inner
7646  *   Item is inner pattern.
7647  */
7648 static void
7649 flow_dv_translate_item_icmp6(void *matcher, void *key,
7650                               const struct rte_flow_item *item,
7651                               int inner)
7652 {
7653         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7654         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7655         void *headers_m;
7656         void *headers_v;
7657         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7658                                      misc_parameters_3);
7659         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7660         if (inner) {
7661                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7662                                          inner_headers);
7663                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7664         } else {
7665                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7666                                          outer_headers);
7667                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7668         }
7669         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7670         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7671         if (!icmp6_v)
7672                 return;
7673         if (!icmp6_m)
7674                 icmp6_m = &rte_flow_item_icmp6_mask;
7675         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7676         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7677                  icmp6_v->type & icmp6_m->type);
7678         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7679         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7680                  icmp6_v->code & icmp6_m->code);
7681 }
7682
7683 /**
7684  * Add ICMP item to matcher and to the value.
7685  *
7686  * @param[in, out] matcher
7687  *   Flow matcher.
7688  * @param[in, out] key
7689  *   Flow matcher value.
7690  * @param[in] item
7691  *   Flow pattern to translate.
7692  * @param[in] inner
7693  *   Item is inner pattern.
7694  */
7695 static void
7696 flow_dv_translate_item_icmp(void *matcher, void *key,
7697                             const struct rte_flow_item *item,
7698                             int inner)
7699 {
7700         const struct rte_flow_item_icmp *icmp_m = item->mask;
7701         const struct rte_flow_item_icmp *icmp_v = item->spec;
7702         uint32_t icmp_header_data_m = 0;
7703         uint32_t icmp_header_data_v = 0;
7704         void *headers_m;
7705         void *headers_v;
7706         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7707                                      misc_parameters_3);
7708         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7709         if (inner) {
7710                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7711                                          inner_headers);
7712                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7713         } else {
7714                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7715                                          outer_headers);
7716                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7717         }
7718         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7719         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7720         if (!icmp_v)
7721                 return;
7722         if (!icmp_m)
7723                 icmp_m = &rte_flow_item_icmp_mask;
7724         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7725                  icmp_m->hdr.icmp_type);
7726         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7727                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7728         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7729                  icmp_m->hdr.icmp_code);
7730         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7731                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7732         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7733         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7734         if (icmp_header_data_m) {
7735                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7736                 icmp_header_data_v |=
7737                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7738                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7739                          icmp_header_data_m);
7740                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7741                          icmp_header_data_v & icmp_header_data_m);
7742         }
7743 }
7744
7745 /**
7746  * Add GTP item to matcher and to the value.
7747  *
7748  * @param[in, out] matcher
7749  *   Flow matcher.
7750  * @param[in, out] key
7751  *   Flow matcher value.
7752  * @param[in] item
7753  *   Flow pattern to translate.
7754  * @param[in] inner
7755  *   Item is inner pattern.
7756  */
7757 static void
7758 flow_dv_translate_item_gtp(void *matcher, void *key,
7759                            const struct rte_flow_item *item, int inner)
7760 {
7761         const struct rte_flow_item_gtp *gtp_m = item->mask;
7762         const struct rte_flow_item_gtp *gtp_v = item->spec;
7763         void *headers_m;
7764         void *headers_v;
7765         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7766                                      misc_parameters_3);
7767         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7768         uint16_t dport = RTE_GTPU_UDP_PORT;
7769
7770         if (inner) {
7771                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7772                                          inner_headers);
7773                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7774         } else {
7775                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7776                                          outer_headers);
7777                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7778         }
7779         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7780                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7781                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7782         }
7783         if (!gtp_v)
7784                 return;
7785         if (!gtp_m)
7786                 gtp_m = &rte_flow_item_gtp_mask;
7787         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7788                  gtp_m->v_pt_rsv_flags);
7789         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7790                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7791         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7792         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7793                  gtp_v->msg_type & gtp_m->msg_type);
7794         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7795                  rte_be_to_cpu_32(gtp_m->teid));
7796         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7797                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7798 }
7799
7800 /**
7801  * Add eCPRI item to matcher and to the value.
7802  *
7803  * @param[in] dev
7804  *   The devich to configure through.
7805  * @param[in, out] matcher
7806  *   Flow matcher.
7807  * @param[in, out] key
7808  *   Flow matcher value.
7809  * @param[in] item
7810  *   Flow pattern to translate.
7811  * @param[in] samples
7812  *   Sample IDs to be used in the matching.
7813  */
7814 static void
7815 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7816                              void *key, const struct rte_flow_item *item)
7817 {
7818         struct mlx5_priv *priv = dev->data->dev_private;
7819         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7820         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7821         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7822                                      misc_parameters_4);
7823         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7824         uint32_t *samples;
7825         void *dw_m;
7826         void *dw_v;
7827
7828         if (!ecpri_v)
7829                 return;
7830         if (!ecpri_m)
7831                 ecpri_m = &rte_flow_item_ecpri_mask;
7832         /*
7833          * Maximal four DW samples are supported in a single matching now.
7834          * Two are used now for a eCPRI matching:
7835          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7836          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7837          *    if any.
7838          */
7839         if (!ecpri_m->hdr.common.u32)
7840                 return;
7841         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7842         /* Need to take the whole DW as the mask to fill the entry. */
7843         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7844                             prog_sample_field_value_0);
7845         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7846                             prog_sample_field_value_0);
7847         /* Already big endian (network order) in the header. */
7848         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7849         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7850         /* Sample#0, used for matching type, offset 0. */
7851         MLX5_SET(fte_match_set_misc4, misc4_m,
7852                  prog_sample_field_id_0, samples[0]);
7853         /* It makes no sense to set the sample ID in the mask field. */
7854         MLX5_SET(fte_match_set_misc4, misc4_v,
7855                  prog_sample_field_id_0, samples[0]);
7856         /*
7857          * Checking if message body part needs to be matched.
7858          * Some wildcard rules only matching type field should be supported.
7859          */
7860         if (ecpri_m->hdr.dummy[0]) {
7861                 switch (ecpri_v->hdr.common.type) {
7862                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7863                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7864                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7865                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7866                                             prog_sample_field_value_1);
7867                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7868                                             prog_sample_field_value_1);
7869                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7870                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7871                         /* Sample#1, to match message body, offset 4. */
7872                         MLX5_SET(fte_match_set_misc4, misc4_m,
7873                                  prog_sample_field_id_1, samples[1]);
7874                         MLX5_SET(fte_match_set_misc4, misc4_v,
7875                                  prog_sample_field_id_1, samples[1]);
7876                         break;
7877                 default:
7878                         /* Others, do not match any sample ID. */
7879                         break;
7880                 }
7881         }
7882 }
7883
7884 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7885
7886 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7887         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7888                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7889
7890 /**
7891  * Calculate flow matcher enable bitmap.
7892  *
7893  * @param match_criteria
7894  *   Pointer to flow matcher criteria.
7895  *
7896  * @return
7897  *   Bitmap of enabled fields.
7898  */
7899 static uint8_t
7900 flow_dv_matcher_enable(uint32_t *match_criteria)
7901 {
7902         uint8_t match_criteria_enable;
7903
7904         match_criteria_enable =
7905                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7906                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7907         match_criteria_enable |=
7908                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7909                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7910         match_criteria_enable |=
7911                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7912                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7913         match_criteria_enable |=
7914                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7915                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7916         match_criteria_enable |=
7917                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7918                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7919         match_criteria_enable |=
7920                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7921                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7922         return match_criteria_enable;
7923 }
7924
7925
7926 /**
7927  * Get a flow table.
7928  *
7929  * @param[in, out] dev
7930  *   Pointer to rte_eth_dev structure.
7931  * @param[in] table_id
7932  *   Table id to use.
7933  * @param[in] egress
7934  *   Direction of the table.
7935  * @param[in] transfer
7936  *   E-Switch or NIC flow.
7937  * @param[out] error
7938  *   pointer to error structure.
7939  *
7940  * @return
7941  *   Returns tables resource based on the index, NULL in case of failed.
7942  */
7943 static struct mlx5_flow_tbl_resource *
7944 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7945                          uint32_t table_id, uint8_t egress,
7946                          uint8_t transfer,
7947                          bool external,
7948                          const struct mlx5_flow_tunnel *tunnel,
7949                          uint32_t group_id,
7950                          struct rte_flow_error *error)
7951 {
7952         struct mlx5_priv *priv = dev->data->dev_private;
7953         struct mlx5_dev_ctx_shared *sh = priv->sh;
7954         struct mlx5_flow_tbl_resource *tbl;
7955         union mlx5_flow_tbl_key table_key = {
7956                 {
7957                         .table_id = table_id,
7958                         .reserved = 0,
7959                         .domain = !!transfer,
7960                         .direction = !!egress,
7961                 }
7962         };
7963         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7964                                                          table_key.v64);
7965         struct mlx5_flow_tbl_data_entry *tbl_data;
7966         uint32_t idx = 0;
7967         int ret;
7968         void *domain;
7969
7970         if (pos) {
7971                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7972                                         entry);
7973                 tbl = &tbl_data->tbl;
7974                 __atomic_fetch_add(&tbl->refcnt, 1, __ATOMIC_RELAXED);
7975                 return tbl;
7976         }
7977         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7978         if (!tbl_data) {
7979                 rte_flow_error_set(error, ENOMEM,
7980                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7981                                    NULL,
7982                                    "cannot allocate flow table data entry");
7983                 return NULL;
7984         }
7985         tbl_data->idx = idx;
7986         tbl_data->tunnel = tunnel;
7987         tbl_data->group_id = group_id;
7988         tbl_data->external = external;
7989         tbl = &tbl_data->tbl;
7990         pos = &tbl_data->entry;
7991         if (transfer)
7992                 domain = sh->fdb_domain;
7993         else if (egress)
7994                 domain = sh->tx_domain;
7995         else
7996                 domain = sh->rx_domain;
7997         ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7998         if (ret) {
7999                 rte_flow_error_set(error, ENOMEM,
8000                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8001                                    NULL, "cannot create flow table object");
8002                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8003                 return NULL;
8004         }
8005         /*
8006          * No multi-threads now, but still better to initialize the reference
8007          * count before insert it into the hash list.
8008          */
8009         __atomic_store_n(&tbl->refcnt, 0, __ATOMIC_RELAXED);
8010
8011         if (table_id) {
8012                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
8013                                         (tbl->obj, &tbl_data->jump.action);
8014                 if (ret) {
8015                         rte_flow_error_set(error, ENOMEM,
8016                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8017                                            NULL,
8018                                            "cannot create flow jump action");
8019                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8020                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8021                         return NULL;
8022                 }
8023         }
8024         pos->key = table_key.v64;
8025         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
8026         if (ret < 0) {
8027                 rte_flow_error_set(error, -ret,
8028                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8029                                    "cannot insert flow table data entry");
8030                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8031                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8032         }
8033         __atomic_fetch_add(&tbl->refcnt, 1, __ATOMIC_RELAXED);
8034         return tbl;
8035 }
8036
8037 /**
8038  * Release a flow table.
8039  *
8040  * @param[in] dev
8041  *   Pointer to rte_eth_dev structure.
8042  * @param[in] tbl
8043  *   Table resource to be released.
8044  *
8045  * @return
8046  *   Returns 0 if table was released, else return 1;
8047  */
8048 static int
8049 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
8050                              struct mlx5_flow_tbl_resource *tbl)
8051 {
8052         struct mlx5_priv *priv = dev->data->dev_private;
8053         struct mlx5_dev_ctx_shared *sh = priv->sh;
8054         struct mlx5_flow_tbl_data_entry *tbl_data =
8055                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8056
8057         if (!tbl)
8058                 return 0;
8059         if (__atomic_sub_fetch(&tbl->refcnt, 1, __ATOMIC_RELAXED) == 0) {
8060                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
8061
8062                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8063                 tbl->obj = NULL;
8064                 if (is_tunnel_offload_active(dev) && tbl_data->external) {
8065                         struct mlx5_hlist_entry *he;
8066                         struct mlx5_hlist *tunnel_grp_hash;
8067                         struct mlx5_flow_tunnel_hub *thub =
8068                                                         mlx5_tunnel_hub(dev);
8069                         union tunnel_tbl_key tunnel_key = {
8070                                 .tunnel_id = tbl_data->tunnel ?
8071                                                 tbl_data->tunnel->tunnel_id : 0,
8072                                 .group = tbl_data->group_id
8073                         };
8074                         union mlx5_flow_tbl_key table_key = {
8075                                 .v64 = pos->key
8076                         };
8077                         uint32_t table_id = table_key.table_id;
8078
8079                         tunnel_grp_hash = tbl_data->tunnel ?
8080                                                 tbl_data->tunnel->groups :
8081                                                 thub->groups;
8082                         he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val);
8083                         if (he) {
8084                                 struct tunnel_tbl_entry *tte;
8085                                 tte = container_of(he, typeof(*tte), hash);
8086                                 MLX5_ASSERT(tte->flow_table == table_id);
8087                                 mlx5_hlist_remove(tunnel_grp_hash, he);
8088                                 mlx5_free(tte);
8089                         }
8090                         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TNL_TBL_ID],
8091                                         tunnel_flow_tbl_to_id(table_id));
8092                         DRV_LOG(DEBUG,
8093                                 "port %u release table_id %#x tunnel %u group %u",
8094                                 dev->data->port_id, table_id,
8095                                 tbl_data->tunnel ?
8096                                 tbl_data->tunnel->tunnel_id : 0,
8097                                 tbl_data->group_id);
8098                 }
8099                 /* remove the entry from the hash list and free memory. */
8100                 mlx5_hlist_remove(sh->flow_tbls, pos);
8101                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
8102                                 tbl_data->idx);
8103                 return 0;
8104         }
8105         return 1;
8106 }
8107
8108 /**
8109  * Register the flow matcher.
8110  *
8111  * @param[in, out] dev
8112  *   Pointer to rte_eth_dev structure.
8113  * @param[in, out] matcher
8114  *   Pointer to flow matcher.
8115  * @param[in, out] key
8116  *   Pointer to flow table key.
8117  * @parm[in, out] dev_flow
8118  *   Pointer to the dev_flow.
8119  * @param[out] error
8120  *   pointer to error structure.
8121  *
8122  * @return
8123  *   0 on success otherwise -errno and errno is set.
8124  */
8125 static int
8126 flow_dv_matcher_register(struct rte_eth_dev *dev,
8127                          struct mlx5_flow_dv_matcher *matcher,
8128                          union mlx5_flow_tbl_key *key,
8129                          struct mlx5_flow *dev_flow,
8130                          struct rte_flow_error *error)
8131 {
8132         struct mlx5_priv *priv = dev->data->dev_private;
8133         struct mlx5_dev_ctx_shared *sh = priv->sh;
8134         struct mlx5_flow_dv_matcher *cache_matcher;
8135         struct mlx5dv_flow_matcher_attr dv_attr = {
8136                 .type = IBV_FLOW_ATTR_NORMAL,
8137                 .match_mask = (void *)&matcher->mask,
8138         };
8139         struct mlx5_flow_tbl_resource *tbl;
8140         struct mlx5_flow_tbl_data_entry *tbl_data;
8141         int ret;
8142
8143         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
8144                                        key->domain, false, NULL, 0, error);
8145         if (!tbl)
8146                 return -rte_errno;      /* No need to refill the error info */
8147         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8148         /* Lookup from cache. */
8149         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
8150                 if (matcher->crc == cache_matcher->crc &&
8151                     matcher->priority == cache_matcher->priority &&
8152                     !memcmp((const void *)matcher->mask.buf,
8153                             (const void *)cache_matcher->mask.buf,
8154                             cache_matcher->mask.size)) {
8155                         DRV_LOG(DEBUG,
8156                                 "%s group %u priority %hd use %s "
8157                                 "matcher %p: refcnt %d++",
8158                                 key->domain ? "FDB" : "NIC", key->table_id,
8159                                 cache_matcher->priority,
8160                                 key->direction ? "tx" : "rx",
8161                                 (void *)cache_matcher,
8162                                 __atomic_load_n(&cache_matcher->refcnt,
8163                                                 __ATOMIC_RELAXED));
8164                         __atomic_fetch_add(&cache_matcher->refcnt, 1,
8165                                            __ATOMIC_RELAXED);
8166                         dev_flow->handle->dvh.matcher = cache_matcher;
8167                         /* old matcher should not make the table ref++. */
8168                         flow_dv_tbl_resource_release(dev, tbl);
8169                         return 0;
8170                 }
8171         }
8172         /* Register new matcher. */
8173         cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
8174                                     SOCKET_ID_ANY);
8175         if (!cache_matcher) {
8176                 flow_dv_tbl_resource_release(dev, tbl);
8177                 return rte_flow_error_set(error, ENOMEM,
8178                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8179                                           "cannot allocate matcher memory");
8180         }
8181         *cache_matcher = *matcher;
8182         dv_attr.match_criteria_enable =
8183                 flow_dv_matcher_enable(cache_matcher->mask.buf);
8184         dv_attr.priority = matcher->priority;
8185         if (key->direction)
8186                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8187         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
8188                                                &cache_matcher->matcher_object);
8189         if (ret) {
8190                 mlx5_free(cache_matcher);
8191 #ifdef HAVE_MLX5DV_DR
8192                 flow_dv_tbl_resource_release(dev, tbl);
8193 #endif
8194                 return rte_flow_error_set(error, ENOMEM,
8195                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8196                                           NULL, "cannot create matcher");
8197         }
8198         /* Save the table information */
8199         cache_matcher->tbl = tbl;
8200         /* only matcher ref++, table ref++ already done above in get API. */
8201         __atomic_store_n(&cache_matcher->refcnt, 1, __ATOMIC_RELAXED);
8202         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
8203         dev_flow->handle->dvh.matcher = cache_matcher;
8204         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
8205                 key->domain ? "FDB" : "NIC", key->table_id,
8206                 cache_matcher->priority,
8207                 key->direction ? "tx" : "rx", (void *)cache_matcher,
8208                 __atomic_load_n(&cache_matcher->refcnt, __ATOMIC_RELAXED));
8209         return 0;
8210 }
8211
8212 /**
8213  * Find existing tag resource or create and register a new one.
8214  *
8215  * @param dev[in, out]
8216  *   Pointer to rte_eth_dev structure.
8217  * @param[in, out] tag_be24
8218  *   Tag value in big endian then R-shift 8.
8219  * @parm[in, out] dev_flow
8220  *   Pointer to the dev_flow.
8221  * @param[out] error
8222  *   pointer to error structure.
8223  *
8224  * @return
8225  *   0 on success otherwise -errno and errno is set.
8226  */
8227 static int
8228 flow_dv_tag_resource_register
8229                         (struct rte_eth_dev *dev,
8230                          uint32_t tag_be24,
8231                          struct mlx5_flow *dev_flow,
8232                          struct rte_flow_error *error)
8233 {
8234         struct mlx5_priv *priv = dev->data->dev_private;
8235         struct mlx5_dev_ctx_shared *sh = priv->sh;
8236         struct mlx5_flow_dv_tag_resource *cache_resource;
8237         struct mlx5_hlist_entry *entry;
8238         int ret;
8239
8240         /* Lookup a matching resource from cache. */
8241         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
8242         if (entry) {
8243                 cache_resource = container_of
8244                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8245                 __atomic_fetch_add(&cache_resource->refcnt, 1,
8246                                    __ATOMIC_RELAXED);
8247                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8248                 dev_flow->dv.tag_resource = cache_resource;
8249                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
8250                         (void *)cache_resource,
8251                         __atomic_load_n(&cache_resource->refcnt,
8252                                         __ATOMIC_RELAXED));
8253                 return 0;
8254         }
8255         /* Register new resource. */
8256         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
8257                                        &dev_flow->handle->dvh.rix_tag);
8258         if (!cache_resource)
8259                 return rte_flow_error_set(error, ENOMEM,
8260                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8261                                           "cannot allocate resource memory");
8262         cache_resource->entry.key = (uint64_t)tag_be24;
8263         ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
8264                                                   &cache_resource->action);
8265         if (ret) {
8266                 mlx5_free(cache_resource);
8267                 return rte_flow_error_set(error, ENOMEM,
8268                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8269                                           NULL, "cannot create action");
8270         }
8271         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8272         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
8273                 mlx5_flow_os_destroy_flow_action(cache_resource->action);
8274                 mlx5_free(cache_resource);
8275                 return rte_flow_error_set(error, EEXIST,
8276                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8277                                           NULL, "cannot insert tag");
8278         }
8279         dev_flow->dv.tag_resource = cache_resource;
8280         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
8281                 (void *)cache_resource,
8282                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8283         return 0;
8284 }
8285
8286 /**
8287  * Release the tag.
8288  *
8289  * @param dev
8290  *   Pointer to Ethernet device.
8291  * @param tag_idx
8292  *   Tag index.
8293  *
8294  * @return
8295  *   1 while a reference on it exists, 0 when freed.
8296  */
8297 static int
8298 flow_dv_tag_release(struct rte_eth_dev *dev,
8299                     uint32_t tag_idx)
8300 {
8301         struct mlx5_priv *priv = dev->data->dev_private;
8302         struct mlx5_dev_ctx_shared *sh = priv->sh;
8303         struct mlx5_flow_dv_tag_resource *tag;
8304
8305         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8306         if (!tag)
8307                 return 0;
8308         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8309                 dev->data->port_id, (void *)tag,
8310                 __atomic_load_n(&tag->refcnt, __ATOMIC_RELAXED));
8311         if (__atomic_sub_fetch(&tag->refcnt, 1, __ATOMIC_RELAXED) == 0) {
8312                 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8313                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
8314                 DRV_LOG(DEBUG, "port %u tag %p: removed",
8315                         dev->data->port_id, (void *)tag);
8316                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8317                 return 0;
8318         }
8319         return 1;
8320 }
8321
8322 /**
8323  * Translate port ID action to vport.
8324  *
8325  * @param[in] dev
8326  *   Pointer to rte_eth_dev structure.
8327  * @param[in] action
8328  *   Pointer to the port ID action.
8329  * @param[out] dst_port_id
8330  *   The target port ID.
8331  * @param[out] error
8332  *   Pointer to the error structure.
8333  *
8334  * @return
8335  *   0 on success, a negative errno value otherwise and rte_errno is set.
8336  */
8337 static int
8338 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8339                                  const struct rte_flow_action *action,
8340                                  uint32_t *dst_port_id,
8341                                  struct rte_flow_error *error)
8342 {
8343         uint32_t port;
8344         struct mlx5_priv *priv;
8345         const struct rte_flow_action_port_id *conf =
8346                         (const struct rte_flow_action_port_id *)action->conf;
8347
8348         port = conf->original ? dev->data->port_id : conf->id;
8349         priv = mlx5_port_to_eswitch_info(port, false);
8350         if (!priv)
8351                 return rte_flow_error_set(error, -rte_errno,
8352                                           RTE_FLOW_ERROR_TYPE_ACTION,
8353                                           NULL,
8354                                           "No eswitch info was found for port");
8355 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8356         /*
8357          * This parameter is transferred to
8358          * mlx5dv_dr_action_create_dest_ib_port().
8359          */
8360         *dst_port_id = priv->dev_port;
8361 #else
8362         /*
8363          * Legacy mode, no LAG configurations is supported.
8364          * This parameter is transferred to
8365          * mlx5dv_dr_action_create_dest_vport().
8366          */
8367         *dst_port_id = priv->vport_id;
8368 #endif
8369         return 0;
8370 }
8371
8372 /**
8373  * Create a counter with aging configuration.
8374  *
8375  * @param[in] dev
8376  *   Pointer to rte_eth_dev structure.
8377  * @param[out] count
8378  *   Pointer to the counter action configuration.
8379  * @param[in] age
8380  *   Pointer to the aging action configuration.
8381  *
8382  * @return
8383  *   Index to flow counter on success, 0 otherwise.
8384  */
8385 static uint32_t
8386 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8387                                 struct mlx5_flow *dev_flow,
8388                                 const struct rte_flow_action_count *count,
8389                                 const struct rte_flow_action_age *age)
8390 {
8391         uint32_t counter;
8392         struct mlx5_age_param *age_param;
8393
8394         if (count && count->shared)
8395                 counter = flow_dv_counter_get_shared(dev, count->id);
8396         else
8397                 counter = flow_dv_counter_alloc(dev, !!age);
8398         if (!counter || age == NULL)
8399                 return counter;
8400         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8401         age_param->context = age->context ? age->context :
8402                 (void *)(uintptr_t)(dev_flow->flow_idx);
8403         age_param->timeout = age->timeout;
8404         age_param->port_id = dev->data->port_id;
8405         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8406         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8407         return counter;
8408 }
8409 /**
8410  * Add Tx queue matcher
8411  *
8412  * @param[in] dev
8413  *   Pointer to the dev struct.
8414  * @param[in, out] matcher
8415  *   Flow matcher.
8416  * @param[in, out] key
8417  *   Flow matcher value.
8418  * @param[in] item
8419  *   Flow pattern to translate.
8420  * @param[in] inner
8421  *   Item is inner pattern.
8422  */
8423 static void
8424 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8425                                 void *matcher, void *key,
8426                                 const struct rte_flow_item *item)
8427 {
8428         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8429         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8430         void *misc_m =
8431                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8432         void *misc_v =
8433                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8434         struct mlx5_txq_ctrl *txq;
8435         uint32_t queue;
8436
8437
8438         queue_m = (const void *)item->mask;
8439         if (!queue_m)
8440                 return;
8441         queue_v = (const void *)item->spec;
8442         if (!queue_v)
8443                 return;
8444         txq = mlx5_txq_get(dev, queue_v->queue);
8445         if (!txq)
8446                 return;
8447         queue = txq->obj->sq->id;
8448         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8449         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8450                  queue & queue_m->queue);
8451         mlx5_txq_release(dev, queue_v->queue);
8452 }
8453
8454 /**
8455  * Set the hash fields according to the @p flow information.
8456  *
8457  * @param[in] dev_flow
8458  *   Pointer to the mlx5_flow.
8459  * @param[in] rss_desc
8460  *   Pointer to the mlx5_flow_rss_desc.
8461  */
8462 static void
8463 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8464                        struct mlx5_flow_rss_desc *rss_desc)
8465 {
8466         uint64_t items = dev_flow->handle->layers;
8467         int rss_inner = 0;
8468         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8469
8470         dev_flow->hash_fields = 0;
8471 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8472         if (rss_desc->level >= 2) {
8473                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8474                 rss_inner = 1;
8475         }
8476 #endif
8477         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8478             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8479                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8480                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8481                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8482                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8483                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8484                         else
8485                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8486                 }
8487         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8488                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8489                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8490                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8491                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8492                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8493                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8494                         else
8495                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8496                 }
8497         }
8498         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8499             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8500                 if (rss_types & ETH_RSS_UDP) {
8501                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8502                                 dev_flow->hash_fields |=
8503                                                 IBV_RX_HASH_SRC_PORT_UDP;
8504                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8505                                 dev_flow->hash_fields |=
8506                                                 IBV_RX_HASH_DST_PORT_UDP;
8507                         else
8508                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8509                 }
8510         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8511                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8512                 if (rss_types & ETH_RSS_TCP) {
8513                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8514                                 dev_flow->hash_fields |=
8515                                                 IBV_RX_HASH_SRC_PORT_TCP;
8516                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8517                                 dev_flow->hash_fields |=
8518                                                 IBV_RX_HASH_DST_PORT_TCP;
8519                         else
8520                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8521                 }
8522         }
8523 }
8524
8525 /**
8526  * Create an Rx Hash queue.
8527  *
8528  * @param dev
8529  *   Pointer to Ethernet device.
8530  * @param[in] dev_flow
8531  *   Pointer to the mlx5_flow.
8532  * @param[in] rss_desc
8533  *   Pointer to the mlx5_flow_rss_desc.
8534  * @param[out] hrxq_idx
8535  *   Hash Rx queue index.
8536  *
8537  * @return
8538  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8539  */
8540 static struct mlx5_hrxq *
8541 flow_dv_handle_rx_queue(struct rte_eth_dev *dev,
8542                         struct mlx5_flow *dev_flow,
8543                         struct mlx5_flow_rss_desc *rss_desc,
8544                         uint32_t *hrxq_idx)
8545 {
8546         struct mlx5_priv *priv = dev->data->dev_private;
8547         struct mlx5_flow_handle *dh = dev_flow->handle;
8548         struct mlx5_hrxq *hrxq;
8549
8550         MLX5_ASSERT(rss_desc->queue_num);
8551         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8552                                   dev_flow->hash_fields,
8553                                   rss_desc->queue, rss_desc->queue_num);
8554         if (!*hrxq_idx) {
8555                 *hrxq_idx = mlx5_hrxq_new
8556                                 (dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8557                                  dev_flow->hash_fields,
8558                                  rss_desc->queue, rss_desc->queue_num,
8559                                  !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL),
8560                                  false);
8561                 if (!*hrxq_idx)
8562                         return NULL;
8563         }
8564         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8565                               *hrxq_idx);
8566         return hrxq;
8567 }
8568
8569 /**
8570  * Find existing sample resource or create and register a new one.
8571  *
8572  * @param[in, out] dev
8573  *   Pointer to rte_eth_dev structure.
8574  * @param[in] attr
8575  *   Attributes of flow that includes this item.
8576  * @param[in] resource
8577  *   Pointer to sample resource.
8578  * @parm[in, out] dev_flow
8579  *   Pointer to the dev_flow.
8580  * @param[in, out] sample_dv_actions
8581  *   Pointer to sample actions list.
8582  * @param[out] error
8583  *   pointer to error structure.
8584  *
8585  * @return
8586  *   0 on success otherwise -errno and errno is set.
8587  */
8588 static int
8589 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8590                          const struct rte_flow_attr *attr,
8591                          struct mlx5_flow_dv_sample_resource *resource,
8592                          struct mlx5_flow *dev_flow,
8593                          void **sample_dv_actions,
8594                          struct rte_flow_error *error)
8595 {
8596         struct mlx5_flow_dv_sample_resource *cache_resource;
8597         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8598         struct mlx5_priv *priv = dev->data->dev_private;
8599         struct mlx5_dev_ctx_shared *sh = priv->sh;
8600         struct mlx5_flow_tbl_resource *tbl;
8601         uint32_t idx = 0;
8602         const uint32_t next_ft_step = 1;
8603         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8604
8605         /* Lookup a matching resource from cache. */
8606         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_SAMPLE], sh->sample_action_list,
8607                       idx, cache_resource, next) {
8608                 if (resource->ratio == cache_resource->ratio &&
8609                     resource->ft_type == cache_resource->ft_type &&
8610                     resource->ft_id == cache_resource->ft_id &&
8611                     resource->set_action == cache_resource->set_action &&
8612                     !memcmp((void *)&resource->sample_act,
8613                             (void *)&cache_resource->sample_act,
8614                             sizeof(struct mlx5_flow_sub_actions_list))) {
8615                         DRV_LOG(DEBUG, "sample resource %p: refcnt %d++",
8616                                 (void *)cache_resource,
8617                                 __atomic_load_n(&cache_resource->refcnt,
8618                                                 __ATOMIC_RELAXED));
8619                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8620                                            __ATOMIC_RELAXED);
8621                         dev_flow->handle->dvh.rix_sample = idx;
8622                         dev_flow->dv.sample_res = cache_resource;
8623                         return 0;
8624                 }
8625         }
8626         /* Register new sample resource. */
8627         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE],
8628                                        &dev_flow->handle->dvh.rix_sample);
8629         if (!cache_resource)
8630                 return rte_flow_error_set(error, ENOMEM,
8631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8632                                           NULL,
8633                                           "cannot allocate resource memory");
8634         *cache_resource = *resource;
8635         /* Create normal path table level */
8636         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8637                                         attr->egress, attr->transfer,
8638                                         dev_flow->external, NULL, 0, error);
8639         if (!tbl) {
8640                 rte_flow_error_set(error, ENOMEM,
8641                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8642                                           NULL,
8643                                           "fail to create normal path table "
8644                                           "for sample");
8645                 goto error;
8646         }
8647         cache_resource->normal_path_tbl = tbl;
8648         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8649                 cache_resource->default_miss =
8650                                 mlx5_glue->dr_create_flow_action_default_miss();
8651                 if (!cache_resource->default_miss) {
8652                         rte_flow_error_set(error, ENOMEM,
8653                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8654                                                 NULL,
8655                                                 "cannot create default miss "
8656                                                 "action");
8657                         goto error;
8658                 }
8659                 sample_dv_actions[resource->sample_act.actions_num++] =
8660                                                 cache_resource->default_miss;
8661         }
8662         /* Create a DR sample action */
8663         sampler_attr.sample_ratio = cache_resource->ratio;
8664         sampler_attr.default_next_table = tbl->obj;
8665         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8666         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8667                                                         &sample_dv_actions[0];
8668         sampler_attr.action = cache_resource->set_action;
8669         cache_resource->verbs_action =
8670                 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8671         if (!cache_resource->verbs_action) {
8672                 rte_flow_error_set(error, ENOMEM,
8673                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8674                                         NULL, "cannot create sample action");
8675                 goto error;
8676         }
8677         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8678         ILIST_INSERT(sh->ipool[MLX5_IPOOL_SAMPLE], &sh->sample_action_list,
8679                      dev_flow->handle->dvh.rix_sample, cache_resource,
8680                      next);
8681         dev_flow->dv.sample_res = cache_resource;
8682         DRV_LOG(DEBUG, "new sample resource %p: refcnt %d++",
8683                 (void *)cache_resource,
8684                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8685         return 0;
8686 error:
8687         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8688                 if (cache_resource->default_miss)
8689                         claim_zero(mlx5_glue->destroy_flow_action
8690                                 (cache_resource->default_miss));
8691         } else {
8692                 if (cache_resource->sample_idx.rix_hrxq &&
8693                     !mlx5_hrxq_release(dev,
8694                                 cache_resource->sample_idx.rix_hrxq))
8695                         cache_resource->sample_idx.rix_hrxq = 0;
8696                 if (cache_resource->sample_idx.rix_tag &&
8697                     !flow_dv_tag_release(dev,
8698                                 cache_resource->sample_idx.rix_tag))
8699                         cache_resource->sample_idx.rix_tag = 0;
8700                 if (cache_resource->sample_idx.cnt) {
8701                         flow_dv_counter_release(dev,
8702                                 cache_resource->sample_idx.cnt);
8703                         cache_resource->sample_idx.cnt = 0;
8704                 }
8705         }
8706         if (cache_resource->normal_path_tbl)
8707                 flow_dv_tbl_resource_release(dev,
8708                                 cache_resource->normal_path_tbl);
8709         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE],
8710                                 dev_flow->handle->dvh.rix_sample);
8711         dev_flow->handle->dvh.rix_sample = 0;
8712         return -rte_errno;
8713 }
8714
8715 /**
8716  * Find existing destination array resource or create and register a new one.
8717  *
8718  * @param[in, out] dev
8719  *   Pointer to rte_eth_dev structure.
8720  * @param[in] attr
8721  *   Attributes of flow that includes this item.
8722  * @param[in] resource
8723  *   Pointer to destination array resource.
8724  * @parm[in, out] dev_flow
8725  *   Pointer to the dev_flow.
8726  * @param[out] error
8727  *   pointer to error structure.
8728  *
8729  * @return
8730  *   0 on success otherwise -errno and errno is set.
8731  */
8732 static int
8733 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
8734                          const struct rte_flow_attr *attr,
8735                          struct mlx5_flow_dv_dest_array_resource *resource,
8736                          struct mlx5_flow *dev_flow,
8737                          struct rte_flow_error *error)
8738 {
8739         struct mlx5_flow_dv_dest_array_resource *cache_resource;
8740         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8741         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8742         struct mlx5_priv *priv = dev->data->dev_private;
8743         struct mlx5_dev_ctx_shared *sh = priv->sh;
8744         struct mlx5_flow_sub_actions_list *sample_act;
8745         struct mlx5dv_dr_domain *domain;
8746         uint32_t idx = 0;
8747
8748         /* Lookup a matching resource from cache. */
8749         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8750                       sh->dest_array_list,
8751                       idx, cache_resource, next) {
8752                 if (resource->num_of_dest == cache_resource->num_of_dest &&
8753                     resource->ft_type == cache_resource->ft_type &&
8754                     !memcmp((void *)cache_resource->sample_act,
8755                             (void *)resource->sample_act,
8756                            (resource->num_of_dest *
8757                            sizeof(struct mlx5_flow_sub_actions_list)))) {
8758                         DRV_LOG(DEBUG, "dest array resource %p: refcnt %d++",
8759                                 (void *)cache_resource,
8760                                 __atomic_load_n(&cache_resource->refcnt,
8761                                                 __ATOMIC_RELAXED));
8762                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8763                                            __ATOMIC_RELAXED);
8764                         dev_flow->handle->dvh.rix_dest_array = idx;
8765                         dev_flow->dv.dest_array_res = cache_resource;
8766                         return 0;
8767                 }
8768         }
8769         /* Register new destination array resource. */
8770         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8771                                        &dev_flow->handle->dvh.rix_dest_array);
8772         if (!cache_resource)
8773                 return rte_flow_error_set(error, ENOMEM,
8774                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8775                                           NULL,
8776                                           "cannot allocate resource memory");
8777         *cache_resource = *resource;
8778         if (attr->transfer)
8779                 domain = sh->fdb_domain;
8780         else if (attr->ingress)
8781                 domain = sh->rx_domain;
8782         else
8783                 domain = sh->tx_domain;
8784         for (idx = 0; idx < resource->num_of_dest; idx++) {
8785                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8786                                  mlx5_malloc(MLX5_MEM_ZERO,
8787                                  sizeof(struct mlx5dv_dr_action_dest_attr),
8788                                  0, SOCKET_ID_ANY);
8789                 if (!dest_attr[idx]) {
8790                         rte_flow_error_set(error, ENOMEM,
8791                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8792                                            NULL,
8793                                            "cannot allocate resource memory");
8794                         goto error;
8795                 }
8796                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8797                 sample_act = &resource->sample_act[idx];
8798                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8799                         dest_attr[idx]->dest = sample_act->dr_queue_action;
8800                 } else if (sample_act->action_flags ==
8801                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8802                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8803                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8804                         dest_attr[idx]->dest_reformat->reformat =
8805                                         sample_act->dr_encap_action;
8806                         dest_attr[idx]->dest_reformat->dest =
8807                                         sample_act->dr_port_id_action;
8808                 } else if (sample_act->action_flags ==
8809                            MLX5_FLOW_ACTION_PORT_ID) {
8810                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
8811                 }
8812         }
8813         /* create a dest array actioin */
8814         cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8815                                                 (domain,
8816                                                  cache_resource->num_of_dest,
8817                                                  dest_attr);
8818         if (!cache_resource->action) {
8819                 rte_flow_error_set(error, ENOMEM,
8820                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8821                                    NULL,
8822                                    "cannot create destination array action");
8823                 goto error;
8824         }
8825         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8826         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8827                      &sh->dest_array_list,
8828                      dev_flow->handle->dvh.rix_dest_array, cache_resource,
8829                      next);
8830         dev_flow->dv.dest_array_res = cache_resource;
8831         DRV_LOG(DEBUG, "new destination array resource %p: refcnt %d++",
8832                 (void *)cache_resource,
8833                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8834         for (idx = 0; idx < resource->num_of_dest; idx++)
8835                 mlx5_free(dest_attr[idx]);
8836         return 0;
8837 error:
8838         for (idx = 0; idx < resource->num_of_dest; idx++) {
8839                 struct mlx5_flow_sub_actions_idx *act_res =
8840                                         &cache_resource->sample_idx[idx];
8841                 if (act_res->rix_hrxq &&
8842                     !mlx5_hrxq_release(dev,
8843                                 act_res->rix_hrxq))
8844                         act_res->rix_hrxq = 0;
8845                 if (act_res->rix_encap_decap &&
8846                         !flow_dv_encap_decap_resource_release(dev,
8847                                 act_res->rix_encap_decap))
8848                         act_res->rix_encap_decap = 0;
8849                 if (act_res->rix_port_id_action &&
8850                         !flow_dv_port_id_action_resource_release(dev,
8851                                 act_res->rix_port_id_action))
8852                         act_res->rix_port_id_action = 0;
8853                 if (dest_attr[idx])
8854                         mlx5_free(dest_attr[idx]);
8855         }
8856
8857         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8858                                 dev_flow->handle->dvh.rix_dest_array);
8859         dev_flow->handle->dvh.rix_dest_array = 0;
8860         return -rte_errno;
8861 }
8862
8863 /**
8864  * Convert Sample action to DV specification.
8865  *
8866  * @param[in] dev
8867  *   Pointer to rte_eth_dev structure.
8868  * @param[in] action
8869  *   Pointer to action structure.
8870  * @param[in, out] dev_flow
8871  *   Pointer to the mlx5_flow.
8872  * @param[in] attr
8873  *   Pointer to the flow attributes.
8874  * @param[in, out] num_of_dest
8875  *   Pointer to the num of destination.
8876  * @param[in, out] sample_actions
8877  *   Pointer to sample actions list.
8878  * @param[in, out] res
8879  *   Pointer to sample resource.
8880  * @param[out] error
8881  *   Pointer to the error structure.
8882  *
8883  * @return
8884  *   0 on success, a negative errno value otherwise and rte_errno is set.
8885  */
8886 static int
8887 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
8888                                 const struct rte_flow_action *action,
8889                                 struct mlx5_flow *dev_flow,
8890                                 const struct rte_flow_attr *attr,
8891                                 uint32_t *num_of_dest,
8892                                 void **sample_actions,
8893                                 struct mlx5_flow_dv_sample_resource *res,
8894                                 struct rte_flow_error *error)
8895 {
8896         struct mlx5_priv *priv = dev->data->dev_private;
8897         const struct rte_flow_action_sample *sample_action;
8898         const struct rte_flow_action *sub_actions;
8899         const struct rte_flow_action_queue *queue;
8900         struct mlx5_flow_sub_actions_list *sample_act;
8901         struct mlx5_flow_sub_actions_idx *sample_idx;
8902         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8903         struct mlx5_flow_rss_desc *rss_desc;
8904         uint64_t action_flags = 0;
8905
8906         MLX5_ASSERT(wks);
8907         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
8908         sample_act = &res->sample_act;
8909         sample_idx = &res->sample_idx;
8910         sample_action = (const struct rte_flow_action_sample *)action->conf;
8911         res->ratio = sample_action->ratio;
8912         sub_actions = sample_action->actions;
8913         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
8914                 int type = sub_actions->type;
8915                 uint32_t pre_rix = 0;
8916                 void *pre_r;
8917                 switch (type) {
8918                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8919                 {
8920                         struct mlx5_hrxq *hrxq;
8921                         uint32_t hrxq_idx;
8922
8923                         queue = sub_actions->conf;
8924                         rss_desc->queue_num = 1;
8925                         rss_desc->queue[0] = queue->index;
8926                         hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
8927                                         rss_desc, &hrxq_idx);
8928                         if (!hrxq)
8929                                 return rte_flow_error_set
8930                                         (error, rte_errno,
8931                                          RTE_FLOW_ERROR_TYPE_ACTION,
8932                                          NULL,
8933                                          "cannot create fate queue");
8934                         sample_act->dr_queue_action = hrxq->action;
8935                         sample_idx->rix_hrxq = hrxq_idx;
8936                         sample_actions[sample_act->actions_num++] =
8937                                                 hrxq->action;
8938                         (*num_of_dest)++;
8939                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8940                         if (action_flags & MLX5_FLOW_ACTION_MARK)
8941                                 dev_flow->handle->rix_hrxq = hrxq_idx;
8942                         dev_flow->handle->fate_action =
8943                                         MLX5_FLOW_FATE_QUEUE;
8944                         break;
8945                 }
8946                 case RTE_FLOW_ACTION_TYPE_MARK:
8947                 {
8948                         uint32_t tag_be = mlx5_flow_mark_set
8949                                 (((const struct rte_flow_action_mark *)
8950                                 (sub_actions->conf))->id);
8951
8952                         dev_flow->handle->mark = 1;
8953                         pre_rix = dev_flow->handle->dvh.rix_tag;
8954                         /* Save the mark resource before sample */
8955                         pre_r = dev_flow->dv.tag_resource;
8956                         if (flow_dv_tag_resource_register(dev, tag_be,
8957                                                   dev_flow, error))
8958                                 return -rte_errno;
8959                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8960                         sample_act->dr_tag_action =
8961                                 dev_flow->dv.tag_resource->action;
8962                         sample_idx->rix_tag =
8963                                 dev_flow->handle->dvh.rix_tag;
8964                         sample_actions[sample_act->actions_num++] =
8965                                                 sample_act->dr_tag_action;
8966                         /* Recover the mark resource after sample */
8967                         dev_flow->dv.tag_resource = pre_r;
8968                         dev_flow->handle->dvh.rix_tag = pre_rix;
8969                         action_flags |= MLX5_FLOW_ACTION_MARK;
8970                         break;
8971                 }
8972                 case RTE_FLOW_ACTION_TYPE_COUNT:
8973                 {
8974                         uint32_t counter;
8975
8976                         counter = flow_dv_translate_create_counter(dev,
8977                                         dev_flow, sub_actions->conf, 0);
8978                         if (!counter)
8979                                 return rte_flow_error_set
8980                                                 (error, rte_errno,
8981                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8982                                                  NULL,
8983                                                  "cannot create counter"
8984                                                  " object.");
8985                         sample_idx->cnt = counter;
8986                         sample_act->dr_cnt_action =
8987                                   (flow_dv_counter_get_by_idx(dev,
8988                                   counter, NULL))->action;
8989                         sample_actions[sample_act->actions_num++] =
8990                                                 sample_act->dr_cnt_action;
8991                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8992                         break;
8993                 }
8994                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8995                 {
8996                         struct mlx5_flow_dv_port_id_action_resource
8997                                         port_id_resource;
8998                         uint32_t port_id = 0;
8999
9000                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9001                         /* Save the port id resource before sample */
9002                         pre_rix = dev_flow->handle->rix_port_id_action;
9003                         pre_r = dev_flow->dv.port_id_action;
9004                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9005                                                              &port_id, error))
9006                                 return -rte_errno;
9007                         port_id_resource.port_id = port_id;
9008                         if (flow_dv_port_id_action_resource_register
9009                             (dev, &port_id_resource, dev_flow, error))
9010                                 return -rte_errno;
9011                         sample_act->dr_port_id_action =
9012                                 dev_flow->dv.port_id_action->action;
9013                         sample_idx->rix_port_id_action =
9014                                 dev_flow->handle->rix_port_id_action;
9015                         sample_actions[sample_act->actions_num++] =
9016                                                 sample_act->dr_port_id_action;
9017                         /* Recover the port id resource after sample */
9018                         dev_flow->dv.port_id_action = pre_r;
9019                         dev_flow->handle->rix_port_id_action = pre_rix;
9020                         (*num_of_dest)++;
9021                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9022                         break;
9023                 }
9024                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9025                         /* Save the encap resource before sample */
9026                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9027                         pre_r = dev_flow->dv.encap_decap;
9028                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9029                                                            dev_flow,
9030                                                            attr->transfer,
9031                                                            error))
9032                                 return -rte_errno;
9033                         sample_act->dr_encap_action =
9034                                 dev_flow->dv.encap_decap->action;
9035                         sample_idx->rix_encap_decap =
9036                                 dev_flow->handle->dvh.rix_encap_decap;
9037                         sample_actions[sample_act->actions_num++] =
9038                                                 sample_act->dr_encap_action;
9039                         /* Recover the encap resource after sample */
9040                         dev_flow->dv.encap_decap = pre_r;
9041                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9042                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9043                         break;
9044                 default:
9045                         return rte_flow_error_set(error, EINVAL,
9046                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9047                                 NULL,
9048                                 "Not support for sampler action");
9049                 }
9050         }
9051         sample_act->action_flags = action_flags;
9052         res->ft_id = dev_flow->dv.group;
9053         if (attr->transfer) {
9054                 union {
9055                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9056                         uint64_t set_action;
9057                 } action_ctx = { .set_action = 0 };
9058
9059                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9060                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9061                          MLX5_MODIFICATION_TYPE_SET);
9062                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9063                          MLX5_MODI_META_REG_C_0);
9064                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9065                          priv->vport_meta_tag);
9066                 res->set_action = action_ctx.set_action;
9067         } else if (attr->ingress) {
9068                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9069         }
9070         return 0;
9071 }
9072
9073 /**
9074  * Convert Sample action to DV specification.
9075  *
9076  * @param[in] dev
9077  *   Pointer to rte_eth_dev structure.
9078  * @param[in, out] dev_flow
9079  *   Pointer to the mlx5_flow.
9080  * @param[in] attr
9081  *   Pointer to the flow attributes.
9082  * @param[in] num_of_dest
9083  *   The num of destination.
9084  * @param[in, out] res
9085  *   Pointer to sample resource.
9086  * @param[in, out] mdest_res
9087  *   Pointer to destination array resource.
9088  * @param[in] sample_actions
9089  *   Pointer to sample path actions list.
9090  * @param[in] action_flags
9091  *   Holds the actions detected until now.
9092  * @param[out] error
9093  *   Pointer to the error structure.
9094  *
9095  * @return
9096  *   0 on success, a negative errno value otherwise and rte_errno is set.
9097  */
9098 static int
9099 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9100                              struct mlx5_flow *dev_flow,
9101                              const struct rte_flow_attr *attr,
9102                              uint32_t num_of_dest,
9103                              struct mlx5_flow_dv_sample_resource *res,
9104                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9105                              void **sample_actions,
9106                              uint64_t action_flags,
9107                              struct rte_flow_error *error)
9108 {
9109         /* update normal path action resource into last index of array */
9110         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9111         struct mlx5_flow_sub_actions_list *sample_act =
9112                                         &mdest_res->sample_act[dest_index];
9113         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9114         struct mlx5_flow_rss_desc *rss_desc;
9115         uint32_t normal_idx = 0;
9116         struct mlx5_hrxq *hrxq;
9117         uint32_t hrxq_idx;
9118
9119         MLX5_ASSERT(wks);
9120         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
9121         if (num_of_dest > 1) {
9122                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9123                         /* Handle QP action for mirroring */
9124                         hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
9125                                                        rss_desc, &hrxq_idx);
9126                         if (!hrxq)
9127                                 return rte_flow_error_set
9128                                      (error, rte_errno,
9129                                       RTE_FLOW_ERROR_TYPE_ACTION,
9130                                       NULL,
9131                                       "cannot create rx queue");
9132                         normal_idx++;
9133                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9134                         sample_act->dr_queue_action = hrxq->action;
9135                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9136                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9137                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9138                 }
9139                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9140                         normal_idx++;
9141                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9142                                 dev_flow->handle->dvh.rix_encap_decap;
9143                         sample_act->dr_encap_action =
9144                                 dev_flow->dv.encap_decap->action;
9145                 }
9146                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9147                         normal_idx++;
9148                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9149                                 dev_flow->handle->rix_port_id_action;
9150                         sample_act->dr_port_id_action =
9151                                 dev_flow->dv.port_id_action->action;
9152                 }
9153                 sample_act->actions_num = normal_idx;
9154                 /* update sample action resource into first index of array */
9155                 mdest_res->ft_type = res->ft_type;
9156                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9157                                 sizeof(struct mlx5_flow_sub_actions_idx));
9158                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9159                                 sizeof(struct mlx5_flow_sub_actions_list));
9160                 mdest_res->num_of_dest = num_of_dest;
9161                 if (flow_dv_dest_array_resource_register(dev, attr, mdest_res,
9162                                                          dev_flow, error))
9163                         return rte_flow_error_set(error, EINVAL,
9164                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9165                                                   NULL, "can't create sample "
9166                                                   "action");
9167         } else {
9168                 if (flow_dv_sample_resource_register(dev, attr, res, dev_flow,
9169                                                      sample_actions, error))
9170                         return rte_flow_error_set(error, EINVAL,
9171                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9172                                                   NULL,
9173                                                   "can't create sample action");
9174         }
9175         return 0;
9176 }
9177
9178 /**
9179  * Fill the flow with DV spec, lock free
9180  * (mutex should be acquired by caller).
9181  *
9182  * @param[in] dev
9183  *   Pointer to rte_eth_dev structure.
9184  * @param[in, out] dev_flow
9185  *   Pointer to the sub flow.
9186  * @param[in] attr
9187  *   Pointer to the flow attributes.
9188  * @param[in] items
9189  *   Pointer to the list of items.
9190  * @param[in] actions
9191  *   Pointer to the list of actions.
9192  * @param[out] error
9193  *   Pointer to the error structure.
9194  *
9195  * @return
9196  *   0 on success, a negative errno value otherwise and rte_errno is set.
9197  */
9198 static int
9199 __flow_dv_translate(struct rte_eth_dev *dev,
9200                     struct mlx5_flow *dev_flow,
9201                     const struct rte_flow_attr *attr,
9202                     const struct rte_flow_item items[],
9203                     const struct rte_flow_action actions[],
9204                     struct rte_flow_error *error)
9205 {
9206         struct mlx5_priv *priv = dev->data->dev_private;
9207         struct mlx5_dev_config *dev_conf = &priv->config;
9208         struct rte_flow *flow = dev_flow->flow;
9209         struct mlx5_flow_handle *handle = dev_flow->handle;
9210         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9211         struct mlx5_flow_rss_desc *rss_desc;
9212         uint64_t item_flags = 0;
9213         uint64_t last_item = 0;
9214         uint64_t action_flags = 0;
9215         uint64_t priority = attr->priority;
9216         struct mlx5_flow_dv_matcher matcher = {
9217                 .mask = {
9218                         .size = sizeof(matcher.mask.buf) -
9219                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9220                 },
9221         };
9222         int actions_n = 0;
9223         bool actions_end = false;
9224         union {
9225                 struct mlx5_flow_dv_modify_hdr_resource res;
9226                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9227                             sizeof(struct mlx5_modification_cmd) *
9228                             (MLX5_MAX_MODIFY_NUM + 1)];
9229         } mhdr_dummy;
9230         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9231         const struct rte_flow_action_count *count = NULL;
9232         const struct rte_flow_action_age *age = NULL;
9233         union flow_dv_attr flow_attr = { .attr = 0 };
9234         uint32_t tag_be;
9235         union mlx5_flow_tbl_key tbl_key;
9236         uint32_t modify_action_position = UINT32_MAX;
9237         void *match_mask = matcher.mask.buf;
9238         void *match_value = dev_flow->dv.value.buf;
9239         uint8_t next_protocol = 0xff;
9240         struct rte_vlan_hdr vlan = { 0 };
9241         struct mlx5_flow_dv_dest_array_resource mdest_res;
9242         struct mlx5_flow_dv_sample_resource sample_res;
9243         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9244         struct mlx5_flow_sub_actions_list *sample_act;
9245         uint32_t sample_act_pos = UINT32_MAX;
9246         uint32_t num_of_dest = 0;
9247         int tmp_actions_n = 0;
9248         uint32_t table;
9249         int ret = 0;
9250         const struct mlx5_flow_tunnel *tunnel;
9251         struct flow_grp_info grp_info = {
9252                 .external = !!dev_flow->external,
9253                 .transfer = !!attr->transfer,
9254                 .fdb_def_rule = !!priv->fdb_def_rule,
9255         };
9256
9257         MLX5_ASSERT(wks);
9258         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
9259         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9260         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9261         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9262                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9263         /* update normal path action resource into last index of array */
9264         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9265         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9266                  flow_items_to_tunnel(items) :
9267                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9268                  flow_actions_to_tunnel(actions) :
9269                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9270         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9271                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9272         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9273                                 (dev, tunnel, attr, items, actions);
9274         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9275                                        grp_info, error);
9276         if (ret)
9277                 return ret;
9278         dev_flow->dv.group = table;
9279         if (attr->transfer)
9280                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9281         if (priority == MLX5_FLOW_PRIO_RSVD)
9282                 priority = dev_conf->flow_prio - 1;
9283         /* number of actions must be set to 0 in case of dirty stack. */
9284         mhdr_res->actions_num = 0;
9285         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9286                 /*
9287                  * do not add decap action if match rule drops packet
9288                  * HW rejects rules with decap & drop
9289                  */
9290                 bool add_decap = true;
9291                 const struct rte_flow_action *ptr = actions;
9292                 struct mlx5_flow_tbl_resource *tbl;
9293
9294                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9295                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9296                                 add_decap = false;
9297                                 break;
9298                         }
9299                 }
9300                 if (add_decap) {
9301                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9302                                                            attr->transfer,
9303                                                            error))
9304                                 return -rte_errno;
9305                         dev_flow->dv.actions[actions_n++] =
9306                                         dev_flow->dv.encap_decap->action;
9307                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9308                 }
9309                 /*
9310                  * bind table_id with <group, table> for tunnel match rule.
9311                  * Tunnel set rule establishes that bind in JUMP action handler.
9312                  * Required for scenario when application creates tunnel match
9313                  * rule before tunnel set rule.
9314                  */
9315                 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9316                                                attr->transfer,
9317                                                !!dev_flow->external, tunnel,
9318                                                attr->group, error);
9319                 if (!tbl)
9320                         return rte_flow_error_set
9321                                (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
9322                                actions, "cannot register tunnel group");
9323         }
9324         for (; !actions_end ; actions++) {
9325                 const struct rte_flow_action_queue *queue;
9326                 const struct rte_flow_action_rss *rss;
9327                 const struct rte_flow_action *action = actions;
9328                 const uint8_t *rss_key;
9329                 const struct rte_flow_action_meter *mtr;
9330                 struct mlx5_flow_tbl_resource *tbl;
9331                 uint32_t port_id = 0;
9332                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9333                 int action_type = actions->type;
9334                 const struct rte_flow_action *found_action = NULL;
9335                 struct mlx5_flow_meter *fm = NULL;
9336                 uint32_t jump_group = 0;
9337
9338                 if (!mlx5_flow_os_action_supported(action_type))
9339                         return rte_flow_error_set(error, ENOTSUP,
9340                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9341                                                   actions,
9342                                                   "action not supported");
9343                 switch (action_type) {
9344                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9345                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9346                         break;
9347                 case RTE_FLOW_ACTION_TYPE_VOID:
9348                         break;
9349                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9350                         if (flow_dv_translate_action_port_id(dev, action,
9351                                                              &port_id, error))
9352                                 return -rte_errno;
9353                         port_id_resource.port_id = port_id;
9354                         MLX5_ASSERT(!handle->rix_port_id_action);
9355                         if (flow_dv_port_id_action_resource_register
9356                             (dev, &port_id_resource, dev_flow, error))
9357                                 return -rte_errno;
9358                         dev_flow->dv.actions[actions_n++] =
9359                                         dev_flow->dv.port_id_action->action;
9360                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9361                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9362                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9363                         num_of_dest++;
9364                         break;
9365                 case RTE_FLOW_ACTION_TYPE_FLAG:
9366                         action_flags |= MLX5_FLOW_ACTION_FLAG;
9367                         dev_flow->handle->mark = 1;
9368                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9369                                 struct rte_flow_action_mark mark = {
9370                                         .id = MLX5_FLOW_MARK_DEFAULT,
9371                                 };
9372
9373                                 if (flow_dv_convert_action_mark(dev, &mark,
9374                                                                 mhdr_res,
9375                                                                 error))
9376                                         return -rte_errno;
9377                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9378                                 break;
9379                         }
9380                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9381                         /*
9382                          * Only one FLAG or MARK is supported per device flow
9383                          * right now. So the pointer to the tag resource must be
9384                          * zero before the register process.
9385                          */
9386                         MLX5_ASSERT(!handle->dvh.rix_tag);
9387                         if (flow_dv_tag_resource_register(dev, tag_be,
9388                                                           dev_flow, error))
9389                                 return -rte_errno;
9390                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9391                         dev_flow->dv.actions[actions_n++] =
9392                                         dev_flow->dv.tag_resource->action;
9393                         break;
9394                 case RTE_FLOW_ACTION_TYPE_MARK:
9395                         action_flags |= MLX5_FLOW_ACTION_MARK;
9396                         dev_flow->handle->mark = 1;
9397                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9398                                 const struct rte_flow_action_mark *mark =
9399                                         (const struct rte_flow_action_mark *)
9400                                                 actions->conf;
9401
9402                                 if (flow_dv_convert_action_mark(dev, mark,
9403                                                                 mhdr_res,
9404                                                                 error))
9405                                         return -rte_errno;
9406                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9407                                 break;
9408                         }
9409                         /* Fall-through */
9410                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9411                         /* Legacy (non-extensive) MARK action. */
9412                         tag_be = mlx5_flow_mark_set
9413                               (((const struct rte_flow_action_mark *)
9414                                (actions->conf))->id);
9415                         MLX5_ASSERT(!handle->dvh.rix_tag);
9416                         if (flow_dv_tag_resource_register(dev, tag_be,
9417                                                           dev_flow, error))
9418                                 return -rte_errno;
9419                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9420                         dev_flow->dv.actions[actions_n++] =
9421                                         dev_flow->dv.tag_resource->action;
9422                         break;
9423                 case RTE_FLOW_ACTION_TYPE_SET_META:
9424                         if (flow_dv_convert_action_set_meta
9425                                 (dev, mhdr_res, attr,
9426                                  (const struct rte_flow_action_set_meta *)
9427                                   actions->conf, error))
9428                                 return -rte_errno;
9429                         action_flags |= MLX5_FLOW_ACTION_SET_META;
9430                         break;
9431                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9432                         if (flow_dv_convert_action_set_tag
9433                                 (dev, mhdr_res,
9434                                  (const struct rte_flow_action_set_tag *)
9435                                   actions->conf, error))
9436                                 return -rte_errno;
9437                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9438                         break;
9439                 case RTE_FLOW_ACTION_TYPE_DROP:
9440                         action_flags |= MLX5_FLOW_ACTION_DROP;
9441                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9442                         break;
9443                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9444                         queue = actions->conf;
9445                         rss_desc->queue_num = 1;
9446                         rss_desc->queue[0] = queue->index;
9447                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9448                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9449                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9450                         num_of_dest++;
9451                         break;
9452                 case RTE_FLOW_ACTION_TYPE_RSS:
9453                         rss = actions->conf;
9454                         memcpy(rss_desc->queue, rss->queue,
9455                                rss->queue_num * sizeof(uint16_t));
9456                         rss_desc->queue_num = rss->queue_num;
9457                         /* NULL RSS key indicates default RSS key. */
9458                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9459                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9460                         /*
9461                          * rss->level and rss.types should be set in advance
9462                          * when expanding items for RSS.
9463                          */
9464                         action_flags |= MLX5_FLOW_ACTION_RSS;
9465                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9466                         break;
9467                 case RTE_FLOW_ACTION_TYPE_AGE:
9468                 case RTE_FLOW_ACTION_TYPE_COUNT:
9469                         if (!dev_conf->devx) {
9470                                 return rte_flow_error_set
9471                                               (error, ENOTSUP,
9472                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9473                                                NULL,
9474                                                "count action not supported");
9475                         }
9476                         /* Save information first, will apply later. */
9477                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9478                                 count = action->conf;
9479                         else
9480                                 age = action->conf;
9481                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9482                         break;
9483                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9484                         dev_flow->dv.actions[actions_n++] =
9485                                                 priv->sh->pop_vlan_action;
9486                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9487                         break;
9488                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9489                         if (!(action_flags &
9490                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9491                                 flow_dev_get_vlan_info_from_items(items, &vlan);
9492                         vlan.eth_proto = rte_be_to_cpu_16
9493                              ((((const struct rte_flow_action_of_push_vlan *)
9494                                                    actions->conf)->ethertype));
9495                         found_action = mlx5_flow_find_action
9496                                         (actions + 1,
9497                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9498                         if (found_action)
9499                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9500                         found_action = mlx5_flow_find_action
9501                                         (actions + 1,
9502                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9503                         if (found_action)
9504                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9505                         if (flow_dv_create_action_push_vlan
9506                                             (dev, attr, &vlan, dev_flow, error))
9507                                 return -rte_errno;
9508                         dev_flow->dv.actions[actions_n++] =
9509                                         dev_flow->dv.push_vlan_res->action;
9510                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9511                         break;
9512                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9513                         /* of_vlan_push action handled this action */
9514                         MLX5_ASSERT(action_flags &
9515                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9516                         break;
9517                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9518                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9519                                 break;
9520                         flow_dev_get_vlan_info_from_items(items, &vlan);
9521                         mlx5_update_vlan_vid_pcp(actions, &vlan);
9522                         /* If no VLAN push - this is a modify header action */
9523                         if (flow_dv_convert_action_modify_vlan_vid
9524                                                 (mhdr_res, actions, error))
9525                                 return -rte_errno;
9526                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
9527                         break;
9528                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
9529                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
9530                         if (flow_dv_create_action_l2_encap(dev, actions,
9531                                                            dev_flow,
9532                                                            attr->transfer,
9533                                                            error))
9534                                 return -rte_errno;
9535                         dev_flow->dv.actions[actions_n++] =
9536                                         dev_flow->dv.encap_decap->action;
9537                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9538                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9539                                 sample_act->action_flags |=
9540                                                         MLX5_FLOW_ACTION_ENCAP;
9541                         break;
9542                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
9543                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
9544                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9545                                                            attr->transfer,
9546                                                            error))
9547                                 return -rte_errno;
9548                         dev_flow->dv.actions[actions_n++] =
9549                                         dev_flow->dv.encap_decap->action;
9550                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9551                         break;
9552                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9553                         /* Handle encap with preceding decap. */
9554                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
9555                                 if (flow_dv_create_action_raw_encap
9556                                         (dev, actions, dev_flow, attr, error))
9557                                         return -rte_errno;
9558                                 dev_flow->dv.actions[actions_n++] =
9559                                         dev_flow->dv.encap_decap->action;
9560                         } else {
9561                                 /* Handle encap without preceding decap. */
9562                                 if (flow_dv_create_action_l2_encap
9563                                     (dev, actions, dev_flow, attr->transfer,
9564                                      error))
9565                                         return -rte_errno;
9566                                 dev_flow->dv.actions[actions_n++] =
9567                                         dev_flow->dv.encap_decap->action;
9568                         }
9569                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9570                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9571                                 sample_act->action_flags |=
9572                                                         MLX5_FLOW_ACTION_ENCAP;
9573                         break;
9574                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
9575                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
9576                                 ;
9577                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
9578                                 if (flow_dv_create_action_l2_decap
9579                                     (dev, dev_flow, attr->transfer, error))
9580                                         return -rte_errno;
9581                                 dev_flow->dv.actions[actions_n++] =
9582                                         dev_flow->dv.encap_decap->action;
9583                         }
9584                         /* If decap is followed by encap, handle it at encap. */
9585                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9586                         break;
9587                 case RTE_FLOW_ACTION_TYPE_JUMP:
9588                         jump_group = ((const struct rte_flow_action_jump *)
9589                                                         action->conf)->group;
9590                         grp_info.std_tbl_fix = 0;
9591                         ret = mlx5_flow_group_to_table(dev, tunnel,
9592                                                        jump_group,
9593                                                        &table,
9594                                                        grp_info, error);
9595                         if (ret)
9596                                 return ret;
9597                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9598                                                        attr->transfer,
9599                                                        !!dev_flow->external,
9600                                                        tunnel, jump_group,
9601                                                        error);
9602                         if (!tbl)
9603                                 return rte_flow_error_set
9604                                                 (error, errno,
9605                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9606                                                  NULL,
9607                                                  "cannot create jump action.");
9608                         if (flow_dv_jump_tbl_resource_register
9609                             (dev, tbl, dev_flow, error)) {
9610                                 flow_dv_tbl_resource_release(dev, tbl);
9611                                 return rte_flow_error_set
9612                                                 (error, errno,
9613                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9614                                                  NULL,
9615                                                  "cannot create jump action.");
9616                         }
9617                         dev_flow->dv.actions[actions_n++] =
9618                                         dev_flow->dv.jump->action;
9619                         action_flags |= MLX5_FLOW_ACTION_JUMP;
9620                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
9621                         break;
9622                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
9623                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
9624                         if (flow_dv_convert_action_modify_mac
9625                                         (mhdr_res, actions, error))
9626                                 return -rte_errno;
9627                         action_flags |= actions->type ==
9628                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
9629                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
9630                                         MLX5_FLOW_ACTION_SET_MAC_DST;
9631                         break;
9632                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
9633                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
9634                         if (flow_dv_convert_action_modify_ipv4
9635                                         (mhdr_res, actions, error))
9636                                 return -rte_errno;
9637                         action_flags |= actions->type ==
9638                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
9639                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
9640                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
9641                         break;
9642                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
9643                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
9644                         if (flow_dv_convert_action_modify_ipv6
9645                                         (mhdr_res, actions, error))
9646                                 return -rte_errno;
9647                         action_flags |= actions->type ==
9648                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
9649                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
9650                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
9651                         break;
9652                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
9653                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
9654                         if (flow_dv_convert_action_modify_tp
9655                                         (mhdr_res, actions, items,
9656                                          &flow_attr, dev_flow, !!(action_flags &
9657                                          MLX5_FLOW_ACTION_DECAP), error))
9658                                 return -rte_errno;
9659                         action_flags |= actions->type ==
9660                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
9661                                         MLX5_FLOW_ACTION_SET_TP_SRC :
9662                                         MLX5_FLOW_ACTION_SET_TP_DST;
9663                         break;
9664                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
9665                         if (flow_dv_convert_action_modify_dec_ttl
9666                                         (mhdr_res, items, &flow_attr, dev_flow,
9667                                          !!(action_flags &
9668                                          MLX5_FLOW_ACTION_DECAP), error))
9669                                 return -rte_errno;
9670                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
9671                         break;
9672                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
9673                         if (flow_dv_convert_action_modify_ttl
9674                                         (mhdr_res, actions, items, &flow_attr,
9675                                          dev_flow, !!(action_flags &
9676                                          MLX5_FLOW_ACTION_DECAP), error))
9677                                 return -rte_errno;
9678                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
9679                         break;
9680                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
9681                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
9682                         if (flow_dv_convert_action_modify_tcp_seq
9683                                         (mhdr_res, actions, error))
9684                                 return -rte_errno;
9685                         action_flags |= actions->type ==
9686                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
9687                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
9688                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
9689                         break;
9690
9691                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
9692                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
9693                         if (flow_dv_convert_action_modify_tcp_ack
9694                                         (mhdr_res, actions, error))
9695                                 return -rte_errno;
9696                         action_flags |= actions->type ==
9697                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
9698                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
9699                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
9700                         break;
9701                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
9702                         if (flow_dv_convert_action_set_reg
9703                                         (mhdr_res, actions, error))
9704                                 return -rte_errno;
9705                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9706                         break;
9707                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
9708                         if (flow_dv_convert_action_copy_mreg
9709                                         (dev, mhdr_res, actions, error))
9710                                 return -rte_errno;
9711                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9712                         break;
9713                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
9714                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
9715                         dev_flow->handle->fate_action =
9716                                         MLX5_FLOW_FATE_DEFAULT_MISS;
9717                         break;
9718                 case RTE_FLOW_ACTION_TYPE_METER:
9719                         mtr = actions->conf;
9720                         if (!flow->meter) {
9721                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
9722                                                             attr, error);
9723                                 if (!fm)
9724                                         return rte_flow_error_set(error,
9725                                                 rte_errno,
9726                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9727                                                 NULL,
9728                                                 "meter not found "
9729                                                 "or invalid parameters");
9730                                 flow->meter = fm->idx;
9731                         }
9732                         /* Set the meter action. */
9733                         if (!fm) {
9734                                 fm = mlx5_ipool_get(priv->sh->ipool
9735                                                 [MLX5_IPOOL_MTR], flow->meter);
9736                                 if (!fm)
9737                                         return rte_flow_error_set(error,
9738                                                 rte_errno,
9739                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9740                                                 NULL,
9741                                                 "meter not found "
9742                                                 "or invalid parameters");
9743                         }
9744                         dev_flow->dv.actions[actions_n++] =
9745                                 fm->mfts->meter_action;
9746                         action_flags |= MLX5_FLOW_ACTION_METER;
9747                         break;
9748                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
9749                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
9750                                                               actions, error))
9751                                 return -rte_errno;
9752                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
9753                         break;
9754                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
9755                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
9756                                                               actions, error))
9757                                 return -rte_errno;
9758                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
9759                         break;
9760                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
9761                         sample_act_pos = actions_n;
9762                         ret = flow_dv_translate_action_sample(dev,
9763                                                               actions,
9764                                                               dev_flow, attr,
9765                                                               &num_of_dest,
9766                                                               sample_actions,
9767                                                               &sample_res,
9768                                                               error);
9769                         if (ret < 0)
9770                                 return ret;
9771                         actions_n++;
9772                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
9773                         /* put encap action into group if work with port id */
9774                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
9775                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
9776                                 sample_act->action_flags |=
9777                                                         MLX5_FLOW_ACTION_ENCAP;
9778                         break;
9779                 case RTE_FLOW_ACTION_TYPE_END:
9780                         actions_end = true;
9781                         if (mhdr_res->actions_num) {
9782                                 /* create modify action if needed. */
9783                                 if (flow_dv_modify_hdr_resource_register
9784                                         (dev, mhdr_res, dev_flow, error))
9785                                         return -rte_errno;
9786                                 dev_flow->dv.actions[modify_action_position] =
9787                                         handle->dvh.modify_hdr->action;
9788                         }
9789                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
9790                                 flow->counter =
9791                                         flow_dv_translate_create_counter(dev,
9792                                                 dev_flow, count, age);
9793
9794                                 if (!flow->counter)
9795                                         return rte_flow_error_set
9796                                                 (error, rte_errno,
9797                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9798                                                 NULL,
9799                                                 "cannot create counter"
9800                                                 " object.");
9801                                 dev_flow->dv.actions[actions_n] =
9802                                           (flow_dv_counter_get_by_idx(dev,
9803                                           flow->counter, NULL))->action;
9804                                 actions_n++;
9805                         }
9806                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
9807                                 ret = flow_dv_create_action_sample(dev,
9808                                                           dev_flow, attr,
9809                                                           num_of_dest,
9810                                                           &sample_res,
9811                                                           &mdest_res,
9812                                                           sample_actions,
9813                                                           action_flags,
9814                                                           error);
9815                                 if (ret < 0)
9816                                         return rte_flow_error_set
9817                                                 (error, rte_errno,
9818                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9819                                                 NULL,
9820                                                 "cannot create sample action");
9821                                 if (num_of_dest > 1) {
9822                                         dev_flow->dv.actions[sample_act_pos] =
9823                                         dev_flow->dv.dest_array_res->action;
9824                                 } else {
9825                                         dev_flow->dv.actions[sample_act_pos] =
9826                                         dev_flow->dv.sample_res->verbs_action;
9827                                 }
9828                         }
9829                         break;
9830                 default:
9831                         break;
9832                 }
9833                 if (mhdr_res->actions_num &&
9834                     modify_action_position == UINT32_MAX)
9835                         modify_action_position = actions_n++;
9836         }
9837         /*
9838          * For multiple destination (sample action with ratio=1), the encap
9839          * action and port id action will be combined into group action.
9840          * So need remove the original these actions in the flow and only
9841          * use the sample action instead of.
9842          */
9843         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
9844                 int i;
9845                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9846
9847                 for (i = 0; i < actions_n; i++) {
9848                         if ((sample_act->dr_encap_action &&
9849                                 sample_act->dr_encap_action ==
9850                                 dev_flow->dv.actions[i]) ||
9851                                 (sample_act->dr_port_id_action &&
9852                                 sample_act->dr_port_id_action ==
9853                                 dev_flow->dv.actions[i]))
9854                                 continue;
9855                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
9856                 }
9857                 memcpy((void *)dev_flow->dv.actions,
9858                                 (void *)temp_actions,
9859                                 tmp_actions_n * sizeof(void *));
9860                 actions_n = tmp_actions_n;
9861         }
9862         dev_flow->dv.actions_n = actions_n;
9863         dev_flow->act_flags = action_flags;
9864         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
9865                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
9866                 int item_type = items->type;
9867
9868                 if (!mlx5_flow_os_item_supported(item_type))
9869                         return rte_flow_error_set(error, ENOTSUP,
9870                                                   RTE_FLOW_ERROR_TYPE_ITEM,
9871                                                   NULL, "item not supported");
9872                 switch (item_type) {
9873                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
9874                         flow_dv_translate_item_port_id(dev, match_mask,
9875                                                        match_value, items);
9876                         last_item = MLX5_FLOW_ITEM_PORT_ID;
9877                         break;
9878                 case RTE_FLOW_ITEM_TYPE_ETH:
9879                         flow_dv_translate_item_eth(match_mask, match_value,
9880                                                    items, tunnel,
9881                                                    dev_flow->dv.group);
9882                         matcher.priority = action_flags &
9883                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
9884                                         !dev_flow->external ?
9885                                         MLX5_PRIORITY_MAP_L3 :
9886                                         MLX5_PRIORITY_MAP_L2;
9887                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
9888                                              MLX5_FLOW_LAYER_OUTER_L2;
9889                         break;
9890                 case RTE_FLOW_ITEM_TYPE_VLAN:
9891                         flow_dv_translate_item_vlan(dev_flow,
9892                                                     match_mask, match_value,
9893                                                     items, tunnel,
9894                                                     dev_flow->dv.group);
9895                         matcher.priority = MLX5_PRIORITY_MAP_L2;
9896                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
9897                                               MLX5_FLOW_LAYER_INNER_VLAN) :
9898                                              (MLX5_FLOW_LAYER_OUTER_L2 |
9899                                               MLX5_FLOW_LAYER_OUTER_VLAN);
9900                         break;
9901                 case RTE_FLOW_ITEM_TYPE_IPV4:
9902                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9903                                                   &item_flags, &tunnel);
9904                         flow_dv_translate_item_ipv4(match_mask, match_value,
9905                                                     items, tunnel,
9906                                                     dev_flow->dv.group);
9907                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9908                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
9909                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
9910                         if (items->mask != NULL &&
9911                             ((const struct rte_flow_item_ipv4 *)
9912                              items->mask)->hdr.next_proto_id) {
9913                                 next_protocol =
9914                                         ((const struct rte_flow_item_ipv4 *)
9915                                          (items->spec))->hdr.next_proto_id;
9916                                 next_protocol &=
9917                                         ((const struct rte_flow_item_ipv4 *)
9918                                          (items->mask))->hdr.next_proto_id;
9919                         } else {
9920                                 /* Reset for inner layer. */
9921                                 next_protocol = 0xff;
9922                         }
9923                         break;
9924                 case RTE_FLOW_ITEM_TYPE_IPV6:
9925                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9926                                                   &item_flags, &tunnel);
9927                         flow_dv_translate_item_ipv6(match_mask, match_value,
9928                                                     items, tunnel,
9929                                                     dev_flow->dv.group);
9930                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9931                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
9932                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
9933                         if (items->mask != NULL &&
9934                             ((const struct rte_flow_item_ipv6 *)
9935                              items->mask)->hdr.proto) {
9936                                 next_protocol =
9937                                         ((const struct rte_flow_item_ipv6 *)
9938                                          items->spec)->hdr.proto;
9939                                 next_protocol &=
9940                                         ((const struct rte_flow_item_ipv6 *)
9941                                          items->mask)->hdr.proto;
9942                         } else {
9943                                 /* Reset for inner layer. */
9944                                 next_protocol = 0xff;
9945                         }
9946                         break;
9947                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
9948                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
9949                                                              match_value,
9950                                                              items, tunnel);
9951                         last_item = tunnel ?
9952                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
9953                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
9954                         if (items->mask != NULL &&
9955                             ((const struct rte_flow_item_ipv6_frag_ext *)
9956                              items->mask)->hdr.next_header) {
9957                                 next_protocol =
9958                                 ((const struct rte_flow_item_ipv6_frag_ext *)
9959                                  items->spec)->hdr.next_header;
9960                                 next_protocol &=
9961                                 ((const struct rte_flow_item_ipv6_frag_ext *)
9962                                  items->mask)->hdr.next_header;
9963                         } else {
9964                                 /* Reset for inner layer. */
9965                                 next_protocol = 0xff;
9966                         }
9967                         break;
9968                 case RTE_FLOW_ITEM_TYPE_TCP:
9969                         flow_dv_translate_item_tcp(match_mask, match_value,
9970                                                    items, tunnel);
9971                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9972                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
9973                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
9974                         break;
9975                 case RTE_FLOW_ITEM_TYPE_UDP:
9976                         flow_dv_translate_item_udp(match_mask, match_value,
9977                                                    items, tunnel);
9978                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9979                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
9980                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
9981                         break;
9982                 case RTE_FLOW_ITEM_TYPE_GRE:
9983                         flow_dv_translate_item_gre(match_mask, match_value,
9984                                                    items, tunnel);
9985                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9986                         last_item = MLX5_FLOW_LAYER_GRE;
9987                         break;
9988                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
9989                         flow_dv_translate_item_gre_key(match_mask,
9990                                                        match_value, items);
9991                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
9992                         break;
9993                 case RTE_FLOW_ITEM_TYPE_NVGRE:
9994                         flow_dv_translate_item_nvgre(match_mask, match_value,
9995                                                      items, tunnel);
9996                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9997                         last_item = MLX5_FLOW_LAYER_GRE;
9998                         break;
9999                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10000                         flow_dv_translate_item_vxlan(match_mask, match_value,
10001                                                      items, tunnel);
10002                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10003                         last_item = MLX5_FLOW_LAYER_VXLAN;
10004                         break;
10005                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10006                         flow_dv_translate_item_vxlan_gpe(match_mask,
10007                                                          match_value, items,
10008                                                          tunnel);
10009                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10010                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10011                         break;
10012                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10013                         flow_dv_translate_item_geneve(match_mask, match_value,
10014                                                       items, tunnel);
10015                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10016                         last_item = MLX5_FLOW_LAYER_GENEVE;
10017                         break;
10018                 case RTE_FLOW_ITEM_TYPE_MPLS:
10019                         flow_dv_translate_item_mpls(match_mask, match_value,
10020                                                     items, last_item, tunnel);
10021                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10022                         last_item = MLX5_FLOW_LAYER_MPLS;
10023                         break;
10024                 case RTE_FLOW_ITEM_TYPE_MARK:
10025                         flow_dv_translate_item_mark(dev, match_mask,
10026                                                     match_value, items);
10027                         last_item = MLX5_FLOW_ITEM_MARK;
10028                         break;
10029                 case RTE_FLOW_ITEM_TYPE_META:
10030                         flow_dv_translate_item_meta(dev, match_mask,
10031                                                     match_value, attr, items);
10032                         last_item = MLX5_FLOW_ITEM_METADATA;
10033                         break;
10034                 case RTE_FLOW_ITEM_TYPE_ICMP:
10035                         flow_dv_translate_item_icmp(match_mask, match_value,
10036                                                     items, tunnel);
10037                         last_item = MLX5_FLOW_LAYER_ICMP;
10038                         break;
10039                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10040                         flow_dv_translate_item_icmp6(match_mask, match_value,
10041                                                       items, tunnel);
10042                         last_item = MLX5_FLOW_LAYER_ICMP6;
10043                         break;
10044                 case RTE_FLOW_ITEM_TYPE_TAG:
10045                         flow_dv_translate_item_tag(dev, match_mask,
10046                                                    match_value, items);
10047                         last_item = MLX5_FLOW_ITEM_TAG;
10048                         break;
10049                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10050                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10051                                                         match_value, items);
10052                         last_item = MLX5_FLOW_ITEM_TAG;
10053                         break;
10054                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10055                         flow_dv_translate_item_tx_queue(dev, match_mask,
10056                                                         match_value,
10057                                                         items);
10058                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10059                         break;
10060                 case RTE_FLOW_ITEM_TYPE_GTP:
10061                         flow_dv_translate_item_gtp(match_mask, match_value,
10062                                                    items, tunnel);
10063                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10064                         last_item = MLX5_FLOW_LAYER_GTP;
10065                         break;
10066                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10067                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10068                                 /* Create it only the first time to be used. */
10069                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10070                                 if (ret)
10071                                         return rte_flow_error_set
10072                                                 (error, -ret,
10073                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10074                                                 NULL,
10075                                                 "cannot create eCPRI parser");
10076                         }
10077                         /* Adjust the length matcher and device flow value. */
10078                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10079                         dev_flow->dv.value.size =
10080                                         MLX5_ST_SZ_BYTES(fte_match_param);
10081                         flow_dv_translate_item_ecpri(dev, match_mask,
10082                                                      match_value, items);
10083                         /* No other protocol should follow eCPRI layer. */
10084                         last_item = MLX5_FLOW_LAYER_ECPRI;
10085                         break;
10086                 default:
10087                         break;
10088                 }
10089                 item_flags |= last_item;
10090         }
10091         /*
10092          * When E-Switch mode is enabled, we have two cases where we need to
10093          * set the source port manually.
10094          * The first one, is in case of Nic steering rule, and the second is
10095          * E-Switch rule where no port_id item was found. In both cases
10096          * the source port is set according the current port in use.
10097          */
10098         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10099             (priv->representor || priv->master)) {
10100                 if (flow_dv_translate_item_port_id(dev, match_mask,
10101                                                    match_value, NULL))
10102                         return -rte_errno;
10103         }
10104 #ifdef RTE_LIBRTE_MLX5_DEBUG
10105         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10106                                               dev_flow->dv.value.buf));
10107 #endif
10108         /*
10109          * Layers may be already initialized from prefix flow if this dev_flow
10110          * is the suffix flow.
10111          */
10112         handle->layers |= item_flags;
10113         if (action_flags & MLX5_FLOW_ACTION_RSS)
10114                 flow_dv_hashfields_set(dev_flow, rss_desc);
10115         /* Register matcher. */
10116         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10117                                     matcher.mask.size);
10118         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
10119                                                      matcher.priority);
10120         /* reserved field no needs to be set to 0 here. */
10121         tbl_key.domain = attr->transfer;
10122         tbl_key.direction = attr->egress;
10123         tbl_key.table_id = dev_flow->dv.group;
10124         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
10125                 return -rte_errno;
10126         return 0;
10127 }
10128
10129 /**
10130  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10131  * and tunnel.
10132  *
10133  * @param[in, out] action
10134  *   Shred RSS action holding hash RX queue objects.
10135  * @param[in] hash_fields
10136  *   Defines combination of packet fields to participate in RX hash.
10137  * @param[in] tunnel
10138  *   Tunnel type
10139  * @param[in] hrxq_idx
10140  *   Hash RX queue index to set.
10141  *
10142  * @return
10143  *   0 on success, otherwise negative errno value.
10144  */
10145 static int
10146 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10147                               const uint64_t hash_fields,
10148                               const int tunnel,
10149                               uint32_t hrxq_idx)
10150 {
10151         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10152
10153         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10154         case MLX5_RSS_HASH_IPV4:
10155                 hrxqs[0] = hrxq_idx;
10156                 return 0;
10157         case MLX5_RSS_HASH_IPV4_TCP:
10158                 hrxqs[1] = hrxq_idx;
10159                 return 0;
10160         case MLX5_RSS_HASH_IPV4_UDP:
10161                 hrxqs[2] = hrxq_idx;
10162                 return 0;
10163         case MLX5_RSS_HASH_IPV6:
10164                 hrxqs[3] = hrxq_idx;
10165                 return 0;
10166         case MLX5_RSS_HASH_IPV6_TCP:
10167                 hrxqs[4] = hrxq_idx;
10168                 return 0;
10169         case MLX5_RSS_HASH_IPV6_UDP:
10170                 hrxqs[5] = hrxq_idx;
10171                 return 0;
10172         case MLX5_RSS_HASH_NONE:
10173                 hrxqs[6] = hrxq_idx;
10174                 return 0;
10175         default:
10176                 return -1;
10177         }
10178 }
10179
10180 /**
10181  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10182  * and tunnel.
10183  *
10184  * @param[in] action
10185  *   Shred RSS action holding hash RX queue objects.
10186  * @param[in] hash_fields
10187  *   Defines combination of packet fields to participate in RX hash.
10188  * @param[in] tunnel
10189  *   Tunnel type
10190  *
10191  * @return
10192  *   Valid hash RX queue index, otherwise 0.
10193  */
10194 static uint32_t
10195 __flow_dv_action_rss_hrxq_lookup(const struct mlx5_shared_action_rss *action,
10196                                  const uint64_t hash_fields,
10197                                  const int tunnel)
10198 {
10199         const uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10200
10201         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10202         case MLX5_RSS_HASH_IPV4:
10203                 return hrxqs[0];
10204         case MLX5_RSS_HASH_IPV4_TCP:
10205                 return hrxqs[1];
10206         case MLX5_RSS_HASH_IPV4_UDP:
10207                 return hrxqs[2];
10208         case MLX5_RSS_HASH_IPV6:
10209                 return hrxqs[3];
10210         case MLX5_RSS_HASH_IPV6_TCP:
10211                 return hrxqs[4];
10212         case MLX5_RSS_HASH_IPV6_UDP:
10213                 return hrxqs[5];
10214         case MLX5_RSS_HASH_NONE:
10215                 return hrxqs[6];
10216         default:
10217                 return 0;
10218         }
10219 }
10220
10221 /**
10222  * Retrieves hash RX queue suitable for the *flow*.
10223  * If shared action configured for *flow* suitable hash RX queue will be
10224  * retrieved from attached shared action.
10225  *
10226  * @param[in] flow
10227  *   Shred RSS action holding hash RX queue objects.
10228  * @param[in] dev_flow
10229  *   Pointer to the sub flow.
10230  * @param[out] hrxq
10231  *   Pointer to retrieved hash RX queue object.
10232  *
10233  * @return
10234  *   Valid hash RX queue index, otherwise 0 and rte_errno is set.
10235  */
10236 static uint32_t
10237 __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct rte_flow *flow,
10238                            struct mlx5_flow *dev_flow,
10239                            struct mlx5_hrxq **hrxq)
10240 {
10241         struct mlx5_priv *priv = dev->data->dev_private;
10242         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10243         uint32_t hrxq_idx;
10244
10245         if (flow->shared_rss) {
10246                 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
10247                                 (flow->shared_rss, dev_flow->hash_fields,
10248                                  !!(dev_flow->handle->layers &
10249                                     MLX5_FLOW_LAYER_TUNNEL));
10250                 if (hrxq_idx) {
10251                         *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10252                                                hrxq_idx);
10253                         __atomic_fetch_add(&(*hrxq)->refcnt, 1,
10254                                            __ATOMIC_RELAXED);
10255                 }
10256         } else {
10257                 struct mlx5_flow_rss_desc *rss_desc =
10258                                 &wks->rss_desc[!!wks->flow_nested_idx];
10259
10260                 MLX5_ASSERT(rss_desc->queue_num);
10261                 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
10262                                          MLX5_RSS_HASH_KEY_LEN,
10263                                          dev_flow->hash_fields,
10264                                          rss_desc->queue, rss_desc->queue_num);
10265                 if (!hrxq_idx) {
10266                         hrxq_idx = mlx5_hrxq_new(dev,
10267                                                  rss_desc->key,
10268                                                  MLX5_RSS_HASH_KEY_LEN,
10269                                                  dev_flow->hash_fields,
10270                                                  rss_desc->queue,
10271                                                  rss_desc->queue_num,
10272                                                  !!(dev_flow->handle->layers &
10273                                                  MLX5_FLOW_LAYER_TUNNEL),
10274                                                  false);
10275                 }
10276                 *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10277                                        hrxq_idx);
10278         }
10279         return hrxq_idx;
10280 }
10281
10282 /**
10283  * Apply the flow to the NIC, lock free,
10284  * (mutex should be acquired by caller).
10285  *
10286  * @param[in] dev
10287  *   Pointer to the Ethernet device structure.
10288  * @param[in, out] flow
10289  *   Pointer to flow structure.
10290  * @param[out] error
10291  *   Pointer to error structure.
10292  *
10293  * @return
10294  *   0 on success, a negative errno value otherwise and rte_errno is set.
10295  */
10296 static int
10297 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10298                 struct rte_flow_error *error)
10299 {
10300         struct mlx5_flow_dv_workspace *dv;
10301         struct mlx5_flow_handle *dh;
10302         struct mlx5_flow_handle_dv *dv_h;
10303         struct mlx5_flow *dev_flow;
10304         struct mlx5_priv *priv = dev->data->dev_private;
10305         uint32_t handle_idx;
10306         int n;
10307         int err;
10308         int idx;
10309         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10310
10311         MLX5_ASSERT(wks);
10312         for (idx = wks->flow_idx - 1; idx >= wks->flow_nested_idx; idx--) {
10313                 dev_flow = &wks->flows[idx];
10314                 dv = &dev_flow->dv;
10315                 dh = dev_flow->handle;
10316                 dv_h = &dh->dvh;
10317                 n = dv->actions_n;
10318                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10319                         if (dv->transfer) {
10320                                 dv->actions[n++] = priv->sh->esw_drop_action;
10321                         } else {
10322                                 MLX5_ASSERT(priv->drop_queue.hrxq);
10323                                 dv->actions[n++] =
10324                                                 priv->drop_queue.hrxq->action;
10325                         }
10326                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10327                            !dv_h->rix_sample && !dv_h->rix_dest_array) {
10328                         struct mlx5_hrxq *hrxq = NULL;
10329                         uint32_t hrxq_idx = __flow_dv_rss_get_hrxq
10330                                                 (dev, flow, dev_flow, &hrxq);
10331
10332                         if (!hrxq) {
10333                                 rte_flow_error_set
10334                                         (error, rte_errno,
10335                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10336                                          "cannot get hash queue");
10337                                 goto error;
10338                         }
10339                         dh->rix_hrxq = hrxq_idx;
10340                         dv->actions[n++] = hrxq->action;
10341                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10342                         if (!priv->sh->default_miss_action) {
10343                                 rte_flow_error_set
10344                                         (error, rte_errno,
10345                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10346                                          "default miss action not be created.");
10347                                 goto error;
10348                         }
10349                         dv->actions[n++] = priv->sh->default_miss_action;
10350                 }
10351                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10352                                                (void *)&dv->value, n,
10353                                                dv->actions, &dh->drv_flow);
10354                 if (err) {
10355                         rte_flow_error_set(error, errno,
10356                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10357                                            NULL,
10358                                            "hardware refuses to create flow");
10359                         goto error;
10360                 }
10361                 if (priv->vmwa_context &&
10362                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
10363                         /*
10364                          * The rule contains the VLAN pattern.
10365                          * For VF we are going to create VLAN
10366                          * interface to make hypervisor set correct
10367                          * e-Switch vport context.
10368                          */
10369                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10370                 }
10371         }
10372         return 0;
10373 error:
10374         err = rte_errno; /* Save rte_errno before cleanup. */
10375         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10376                        handle_idx, dh, next) {
10377                 /* hrxq is union, don't clear it if the flag is not set. */
10378                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
10379                         mlx5_hrxq_release(dev, dh->rix_hrxq);
10380                         dh->rix_hrxq = 0;
10381                 }
10382                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10383                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10384         }
10385         rte_errno = err; /* Restore rte_errno. */
10386         return -rte_errno;
10387 }
10388
10389 /**
10390  * Release the flow matcher.
10391  *
10392  * @param dev
10393  *   Pointer to Ethernet device.
10394  * @param handle
10395  *   Pointer to mlx5_flow_handle.
10396  *
10397  * @return
10398  *   1 while a reference on it exists, 0 when freed.
10399  */
10400 static int
10401 flow_dv_matcher_release(struct rte_eth_dev *dev,
10402                         struct mlx5_flow_handle *handle)
10403 {
10404         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10405
10406         MLX5_ASSERT(matcher->matcher_object);
10407         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
10408                 dev->data->port_id, (void *)matcher,
10409                 __atomic_load_n(&matcher->refcnt, __ATOMIC_RELAXED));
10410         if (__atomic_sub_fetch(&matcher->refcnt, 1, __ATOMIC_RELAXED) == 0) {
10411                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10412                            (matcher->matcher_object));
10413                 LIST_REMOVE(matcher, next);
10414                 /* table ref-- in release interface. */
10415                 flow_dv_tbl_resource_release(dev, matcher->tbl);
10416                 mlx5_free(matcher);
10417                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
10418                         dev->data->port_id, (void *)matcher);
10419                 return 0;
10420         }
10421         return 1;
10422 }
10423
10424 /**
10425  * Release an encap/decap resource.
10426  *
10427  * @param dev
10428  *   Pointer to Ethernet device.
10429  * @param encap_decap_idx
10430  *   Index of encap decap resource.
10431  *
10432  * @return
10433  *   1 while a reference on it exists, 0 when freed.
10434  */
10435 static int
10436 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10437                                      uint32_t encap_decap_idx)
10438 {
10439         struct mlx5_priv *priv = dev->data->dev_private;
10440         uint32_t idx = encap_decap_idx;
10441         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10442
10443         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10444                          idx);
10445         if (!cache_resource)
10446                 return 0;
10447         MLX5_ASSERT(cache_resource->action);
10448         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
10449                 (void *)cache_resource,
10450                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10451         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10452                                __ATOMIC_RELAXED) == 0) {
10453                 claim_zero(mlx5_flow_os_destroy_flow_action
10454                                                 (cache_resource->action));
10455                 mlx5_hlist_remove(priv->sh->encaps_decaps,
10456                                   &cache_resource->entry);
10457                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
10458                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
10459                         (void *)cache_resource);
10460                 return 0;
10461         }
10462         return 1;
10463 }
10464
10465 /**
10466  * Release an jump to table action resource.
10467  *
10468  * @param dev
10469  *   Pointer to Ethernet device.
10470  * @param handle
10471  *   Pointer to mlx5_flow_handle.
10472  *
10473  * @return
10474  *   1 while a reference on it exists, 0 when freed.
10475  */
10476 static int
10477 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10478                                   struct mlx5_flow_handle *handle)
10479 {
10480         struct mlx5_priv *priv = dev->data->dev_private;
10481         struct mlx5_flow_tbl_data_entry *tbl_data;
10482
10483         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10484                              handle->rix_jump);
10485         if (!tbl_data)
10486                 return 0;
10487         return flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
10488 }
10489
10490 /**
10491  * Release a modify-header resource.
10492  *
10493  * @param dev
10494  *   Pointer to Ethernet device.
10495  * @param handle
10496  *   Pointer to mlx5_flow_handle.
10497  *
10498  * @return
10499  *   1 while a reference on it exists, 0 when freed.
10500  */
10501 static int
10502 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10503                                     struct mlx5_flow_handle *handle)
10504 {
10505         struct mlx5_priv *priv = dev->data->dev_private;
10506         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
10507                                                         handle->dvh.modify_hdr;
10508
10509         MLX5_ASSERT(cache_resource->action);
10510         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
10511                 (void *)cache_resource,
10512                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10513         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10514                                 __ATOMIC_RELAXED) == 0) {
10515                 claim_zero(mlx5_flow_os_destroy_flow_action
10516                                                 (cache_resource->action));
10517                 mlx5_hlist_remove(priv->sh->modify_cmds,
10518                                   &cache_resource->entry);
10519                 mlx5_free(cache_resource);
10520                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
10521                         (void *)cache_resource);
10522                 return 0;
10523         }
10524         return 1;
10525 }
10526
10527 /**
10528  * Release port ID action resource.
10529  *
10530  * @param dev
10531  *   Pointer to Ethernet device.
10532  * @param handle
10533  *   Pointer to mlx5_flow_handle.
10534  *
10535  * @return
10536  *   1 while a reference on it exists, 0 when freed.
10537  */
10538 static int
10539 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
10540                                         uint32_t port_id)
10541 {
10542         struct mlx5_priv *priv = dev->data->dev_private;
10543         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
10544         uint32_t idx = port_id;
10545
10546         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10547                                         idx);
10548         if (!cache_resource)
10549                 return 0;
10550         MLX5_ASSERT(cache_resource->action);
10551         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
10552                 (void *)cache_resource,
10553                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10554         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10555                                __ATOMIC_RELAXED) == 0) {
10556                 claim_zero(mlx5_flow_os_destroy_flow_action
10557                                                 (cache_resource->action));
10558                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10559                              &priv->sh->port_id_action_list, idx,
10560                              cache_resource, next);
10561                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
10562                 DRV_LOG(DEBUG, "port id action resource %p: removed",
10563                         (void *)cache_resource);
10564                 return 0;
10565         }
10566         return 1;
10567 }
10568
10569 /**
10570  * Release push vlan action resource.
10571  *
10572  * @param dev
10573  *   Pointer to Ethernet device.
10574  * @param handle
10575  *   Pointer to mlx5_flow_handle.
10576  *
10577  * @return
10578  *   1 while a reference on it exists, 0 when freed.
10579  */
10580 static int
10581 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
10582                                           struct mlx5_flow_handle *handle)
10583 {
10584         struct mlx5_priv *priv = dev->data->dev_private;
10585         uint32_t idx = handle->dvh.rix_push_vlan;
10586         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
10587
10588         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10589                                         idx);
10590         if (!cache_resource)
10591                 return 0;
10592         MLX5_ASSERT(cache_resource->action);
10593         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
10594                 (void *)cache_resource,
10595                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10596         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10597                                __ATOMIC_RELAXED) == 0) {
10598                 claim_zero(mlx5_flow_os_destroy_flow_action
10599                                                 (cache_resource->action));
10600                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10601                              &priv->sh->push_vlan_action_list, idx,
10602                              cache_resource, next);
10603                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
10604                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
10605                         (void *)cache_resource);
10606                 return 0;
10607         }
10608         return 1;
10609 }
10610
10611 /**
10612  * Release the fate resource.
10613  *
10614  * @param dev
10615  *   Pointer to Ethernet device.
10616  * @param handle
10617  *   Pointer to mlx5_flow_handle.
10618  */
10619 static void
10620 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
10621                                struct mlx5_flow_handle *handle)
10622 {
10623         if (!handle->rix_fate)
10624                 return;
10625         switch (handle->fate_action) {
10626         case MLX5_FLOW_FATE_QUEUE:
10627                 mlx5_hrxq_release(dev, handle->rix_hrxq);
10628                 break;
10629         case MLX5_FLOW_FATE_JUMP:
10630                 flow_dv_jump_tbl_resource_release(dev, handle);
10631                 break;
10632         case MLX5_FLOW_FATE_PORT_ID:
10633                 flow_dv_port_id_action_resource_release(dev,
10634                                 handle->rix_port_id_action);
10635                 break;
10636         default:
10637                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
10638                 break;
10639         }
10640         handle->rix_fate = 0;
10641 }
10642
10643 /**
10644  * Release an sample resource.
10645  *
10646  * @param dev
10647  *   Pointer to Ethernet device.
10648  * @param handle
10649  *   Pointer to mlx5_flow_handle.
10650  *
10651  * @return
10652  *   1 while a reference on it exists, 0 when freed.
10653  */
10654 static int
10655 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
10656                                      struct mlx5_flow_handle *handle)
10657 {
10658         struct mlx5_priv *priv = dev->data->dev_private;
10659         uint32_t idx = handle->dvh.rix_sample;
10660         struct mlx5_flow_dv_sample_resource *cache_resource;
10661
10662         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10663                          idx);
10664         if (!cache_resource)
10665                 return 0;
10666         MLX5_ASSERT(cache_resource->verbs_action);
10667         DRV_LOG(DEBUG, "sample resource %p: refcnt %d--",
10668                 (void *)cache_resource,
10669                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10670         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10671                                __ATOMIC_RELAXED) == 0) {
10672                 if (cache_resource->verbs_action)
10673                         claim_zero(mlx5_glue->destroy_flow_action
10674                                         (cache_resource->verbs_action));
10675                 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10676                         if (cache_resource->default_miss)
10677                                 claim_zero(mlx5_glue->destroy_flow_action
10678                                   (cache_resource->default_miss));
10679                 }
10680                 if (cache_resource->normal_path_tbl)
10681                         flow_dv_tbl_resource_release(dev,
10682                                 cache_resource->normal_path_tbl);
10683         }
10684         if (cache_resource->sample_idx.rix_hrxq &&
10685                 !mlx5_hrxq_release(dev,
10686                         cache_resource->sample_idx.rix_hrxq))
10687                 cache_resource->sample_idx.rix_hrxq = 0;
10688         if (cache_resource->sample_idx.rix_tag &&
10689                 !flow_dv_tag_release(dev,
10690                         cache_resource->sample_idx.rix_tag))
10691                 cache_resource->sample_idx.rix_tag = 0;
10692         if (cache_resource->sample_idx.cnt) {
10693                 flow_dv_counter_release(dev,
10694                         cache_resource->sample_idx.cnt);
10695                 cache_resource->sample_idx.cnt = 0;
10696         }
10697         if (!__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED)) {
10698                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10699                              &priv->sh->sample_action_list, idx,
10700                              cache_resource, next);
10701                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10702                 DRV_LOG(DEBUG, "sample resource %p: removed",
10703                         (void *)cache_resource);
10704                 return 0;
10705         }
10706         return 1;
10707 }
10708
10709 /**
10710  * Release an destination array resource.
10711  *
10712  * @param dev
10713  *   Pointer to Ethernet device.
10714  * @param handle
10715  *   Pointer to mlx5_flow_handle.
10716  *
10717  * @return
10718  *   1 while a reference on it exists, 0 when freed.
10719  */
10720 static int
10721 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
10722                                      struct mlx5_flow_handle *handle)
10723 {
10724         struct mlx5_priv *priv = dev->data->dev_private;
10725         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10726         struct mlx5_flow_sub_actions_idx *mdest_act_res;
10727         uint32_t idx = handle->dvh.rix_dest_array;
10728         uint32_t i = 0;
10729
10730         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10731                          idx);
10732         if (!cache_resource)
10733                 return 0;
10734         MLX5_ASSERT(cache_resource->action);
10735         DRV_LOG(DEBUG, "destination array resource %p: refcnt %d--",
10736                 (void *)cache_resource,
10737                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10738         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10739                                __ATOMIC_RELAXED) == 0) {
10740                 if (cache_resource->action)
10741                         claim_zero(mlx5_glue->destroy_flow_action
10742                                                 (cache_resource->action));
10743                 for (; i < cache_resource->num_of_dest; i++) {
10744                         mdest_act_res = &cache_resource->sample_idx[i];
10745                         if (mdest_act_res->rix_hrxq) {
10746                                 mlx5_hrxq_release(dev,
10747                                         mdest_act_res->rix_hrxq);
10748                                 mdest_act_res->rix_hrxq = 0;
10749                         }
10750                         if (mdest_act_res->rix_encap_decap) {
10751                                 flow_dv_encap_decap_resource_release(dev,
10752                                         mdest_act_res->rix_encap_decap);
10753                                 mdest_act_res->rix_encap_decap = 0;
10754                         }
10755                         if (mdest_act_res->rix_port_id_action) {
10756                                 flow_dv_port_id_action_resource_release(dev,
10757                                         mdest_act_res->rix_port_id_action);
10758                                 mdest_act_res->rix_port_id_action = 0;
10759                         }
10760                         if (mdest_act_res->rix_tag) {
10761                                 flow_dv_tag_release(dev,
10762                                         mdest_act_res->rix_tag);
10763                                 mdest_act_res->rix_tag = 0;
10764                         }
10765                 }
10766                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10767                              &priv->sh->dest_array_list, idx,
10768                              cache_resource, next);
10769                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], idx);
10770                 DRV_LOG(DEBUG, "destination array resource %p: removed",
10771                         (void *)cache_resource);
10772                 return 0;
10773         }
10774         return 1;
10775 }
10776
10777 /**
10778  * Remove the flow from the NIC but keeps it in memory.
10779  * Lock free, (mutex should be acquired by caller).
10780  *
10781  * @param[in] dev
10782  *   Pointer to Ethernet device.
10783  * @param[in, out] flow
10784  *   Pointer to flow structure.
10785  */
10786 static void
10787 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10788 {
10789         struct mlx5_flow_handle *dh;
10790         uint32_t handle_idx;
10791         struct mlx5_priv *priv = dev->data->dev_private;
10792
10793         if (!flow)
10794                 return;
10795         handle_idx = flow->dev_handles;
10796         while (handle_idx) {
10797                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10798                                     handle_idx);
10799                 if (!dh)
10800                         return;
10801                 if (dh->drv_flow) {
10802                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
10803                         dh->drv_flow = NULL;
10804                 }
10805                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
10806                         flow_dv_fate_resource_release(dev, dh);
10807                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10808                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10809                 handle_idx = dh->next.next;
10810         }
10811 }
10812
10813 /**
10814  * Remove the flow from the NIC and the memory.
10815  * Lock free, (mutex should be acquired by caller).
10816  *
10817  * @param[in] dev
10818  *   Pointer to the Ethernet device structure.
10819  * @param[in, out] flow
10820  *   Pointer to flow structure.
10821  */
10822 static void
10823 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10824 {
10825         struct rte_flow_shared_action *shared;
10826         struct mlx5_flow_handle *dev_handle;
10827         struct mlx5_priv *priv = dev->data->dev_private;
10828
10829         if (!flow)
10830                 return;
10831         __flow_dv_remove(dev, flow);
10832         shared = mlx5_flow_get_shared_rss(flow);
10833         if (shared)
10834                 __atomic_sub_fetch(&shared->refcnt, 1, __ATOMIC_RELAXED);
10835         if (flow->counter) {
10836                 flow_dv_counter_release(dev, flow->counter);
10837                 flow->counter = 0;
10838         }
10839         if (flow->meter) {
10840                 struct mlx5_flow_meter *fm;
10841
10842                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
10843                                     flow->meter);
10844                 if (fm)
10845                         mlx5_flow_meter_detach(fm);
10846                 flow->meter = 0;
10847         }
10848         while (flow->dev_handles) {
10849                 uint32_t tmp_idx = flow->dev_handles;
10850
10851                 dev_handle = mlx5_ipool_get(priv->sh->ipool
10852                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
10853                 if (!dev_handle)
10854                         return;
10855                 flow->dev_handles = dev_handle->next.next;
10856                 if (dev_handle->dvh.matcher)
10857                         flow_dv_matcher_release(dev, dev_handle);
10858                 if (dev_handle->dvh.rix_sample)
10859                         flow_dv_sample_resource_release(dev, dev_handle);
10860                 if (dev_handle->dvh.rix_dest_array)
10861                         flow_dv_dest_array_resource_release(dev, dev_handle);
10862                 if (dev_handle->dvh.rix_encap_decap)
10863                         flow_dv_encap_decap_resource_release(dev,
10864                                 dev_handle->dvh.rix_encap_decap);
10865                 if (dev_handle->dvh.modify_hdr)
10866                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
10867                 if (dev_handle->dvh.rix_push_vlan)
10868                         flow_dv_push_vlan_action_resource_release(dev,
10869                                                                   dev_handle);
10870                 if (dev_handle->dvh.rix_tag)
10871                         flow_dv_tag_release(dev,
10872                                             dev_handle->dvh.rix_tag);
10873                 flow_dv_fate_resource_release(dev, dev_handle);
10874                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10875                            tmp_idx);
10876         }
10877 }
10878
10879 /**
10880  * Release array of hash RX queue objects.
10881  * Helper function.
10882  *
10883  * @param[in] dev
10884  *   Pointer to the Ethernet device structure.
10885  * @param[in, out] hrxqs
10886  *   Array of hash RX queue objects.
10887  *
10888  * @return
10889  *   Total number of references to hash RX queue objects in *hrxqs* array
10890  *   after this operation.
10891  */
10892 static int
10893 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
10894                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
10895 {
10896         size_t i;
10897         int remaining = 0;
10898
10899         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
10900                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
10901
10902                 if (!ret)
10903                         (*hrxqs)[i] = 0;
10904                 remaining += ret;
10905         }
10906         return remaining;
10907 }
10908
10909 /**
10910  * Release all hash RX queue objects representing shared RSS action.
10911  *
10912  * @param[in] dev
10913  *   Pointer to the Ethernet device structure.
10914  * @param[in, out] action
10915  *   Shared RSS action to remove hash RX queue objects from.
10916  *
10917  * @return
10918  *   Total number of references to hash RX queue objects stored in *action*
10919  *   after this operation.
10920  *   Expected to be 0 if no external references held.
10921  */
10922 static int
10923 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
10924                                  struct mlx5_shared_action_rss *action)
10925 {
10926         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
10927                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
10928 }
10929
10930 /**
10931  * Setup shared RSS action.
10932  * Prepare set of hash RX queue objects sufficient to handle all valid
10933  * hash_fields combinations (see enum ibv_rx_hash_fields).
10934  *
10935  * @param[in] dev
10936  *   Pointer to the Ethernet device structure.
10937  * @param[in, out] action
10938  *   Partially initialized shared RSS action.
10939  * @param[out] error
10940  *   Perform verbose error reporting if not NULL. Initialized in case of
10941  *   error only.
10942  *
10943  * @return
10944  *   0 on success, otherwise negative errno value.
10945  */
10946 static int
10947 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
10948                         struct mlx5_shared_action_rss *action,
10949                         struct rte_flow_error *error)
10950 {
10951         size_t i;
10952         int err;
10953
10954         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
10955                 uint32_t hrxq_idx;
10956                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
10957                 int tunnel;
10958
10959                 for (tunnel = 0; tunnel < 2; tunnel++) {
10960                         hrxq_idx = mlx5_hrxq_new(dev, action->origin.key,
10961                                         MLX5_RSS_HASH_KEY_LEN,
10962                                         hash_fields,
10963                                         action->origin.queue,
10964                                         action->origin.queue_num,
10965                                         tunnel, true);
10966                         if (!hrxq_idx) {
10967                                 rte_flow_error_set
10968                                         (error, rte_errno,
10969                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10970                                          "cannot get hash queue");
10971                                 goto error_hrxq_new;
10972                         }
10973                         err = __flow_dv_action_rss_hrxq_set
10974                                 (action, hash_fields, tunnel, hrxq_idx);
10975                         MLX5_ASSERT(!err);
10976                 }
10977         }
10978         return 0;
10979 error_hrxq_new:
10980         err = rte_errno;
10981         __flow_dv_action_rss_hrxqs_release(dev, action);
10982         rte_errno = err;
10983         return -rte_errno;
10984 }
10985
10986 /**
10987  * Create shared RSS action.
10988  *
10989  * @param[in] dev
10990  *   Pointer to the Ethernet device structure.
10991  * @param[in] conf
10992  *   Shared action configuration.
10993  * @param[in] rss
10994  *   RSS action specification used to create shared action.
10995  * @param[out] error
10996  *   Perform verbose error reporting if not NULL. Initialized in case of
10997  *   error only.
10998  *
10999  * @return
11000  *   A valid shared action handle in case of success, NULL otherwise and
11001  *   rte_errno is set.
11002  */
11003 static struct rte_flow_shared_action *
11004 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11005                             const struct rte_flow_shared_action_conf *conf,
11006                             const struct rte_flow_action_rss *rss,
11007                             struct rte_flow_error *error)
11008 {
11009         struct rte_flow_shared_action *shared_action = NULL;
11010         void *queue = NULL;
11011         struct mlx5_shared_action_rss *shared_rss;
11012         struct rte_flow_action_rss *origin;
11013         const uint8_t *rss_key;
11014         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11015
11016         RTE_SET_USED(conf);
11017         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11018                             0, SOCKET_ID_ANY);
11019         shared_action = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*shared_action), 0,
11020                                     SOCKET_ID_ANY);
11021         if (!shared_action || !queue) {
11022                 rte_flow_error_set(error, ENOMEM,
11023                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11024                                    "cannot allocate resource memory");
11025                 goto error_rss_init;
11026         }
11027         shared_rss = &shared_action->rss;
11028         shared_rss->queue = queue;
11029         origin = &shared_rss->origin;
11030         origin->func = rss->func;
11031         origin->level = rss->level;
11032         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11033         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11034         /* NULL RSS key indicates default RSS key. */
11035         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11036         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11037         origin->key = &shared_rss->key[0];
11038         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11039         memcpy(shared_rss->queue, rss->queue, queue_size);
11040         origin->queue = shared_rss->queue;
11041         origin->queue_num = rss->queue_num;
11042         if (__flow_dv_action_rss_setup(dev, shared_rss, error))
11043                 goto error_rss_init;
11044         shared_action->type = MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS;
11045         return shared_action;
11046 error_rss_init:
11047         mlx5_free(shared_action);
11048         mlx5_free(queue);
11049         return NULL;
11050 }
11051
11052 /**
11053  * Destroy the shared RSS action.
11054  * Release related hash RX queue objects.
11055  *
11056  * @param[in] dev
11057  *   Pointer to the Ethernet device structure.
11058  * @param[in] shared_rss
11059  *   The shared RSS action object to be removed.
11060  * @param[out] error
11061  *   Perform verbose error reporting if not NULL. Initialized in case of
11062  *   error only.
11063  *
11064  * @return
11065  *   0 on success, otherwise negative errno value.
11066  */
11067 static int
11068 __flow_dv_action_rss_release(struct rte_eth_dev *dev,
11069                          struct mlx5_shared_action_rss *shared_rss,
11070                          struct rte_flow_error *error)
11071 {
11072         struct rte_flow_shared_action *shared_action = NULL;
11073         uint32_t old_refcnt = 1;
11074         int remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11075
11076         if (remaining) {
11077                 return rte_flow_error_set(error, ETOOMANYREFS,
11078                                           RTE_FLOW_ERROR_TYPE_ACTION,
11079                                           NULL,
11080                                           "shared rss hrxq has references");
11081         }
11082         shared_action = container_of(shared_rss,
11083                                      struct rte_flow_shared_action, rss);
11084         if (!__atomic_compare_exchange_n(&shared_action->refcnt, &old_refcnt,
11085                                          0, 0,
11086                                          __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {
11087                 return rte_flow_error_set(error, ETOOMANYREFS,
11088                                           RTE_FLOW_ERROR_TYPE_ACTION,
11089                                           NULL,
11090                                           "shared rss has references");
11091         }
11092         rte_free(shared_rss->queue);
11093         return 0;
11094 }
11095
11096 /**
11097  * Create shared action, lock free,
11098  * (mutex should be acquired by caller).
11099  * Dispatcher for action type specific call.
11100  *
11101  * @param[in] dev
11102  *   Pointer to the Ethernet device structure.
11103  * @param[in] conf
11104  *   Shared action configuration.
11105  * @param[in] action
11106  *   Action specification used to create shared action.
11107  * @param[out] error
11108  *   Perform verbose error reporting if not NULL. Initialized in case of
11109  *   error only.
11110  *
11111  * @return
11112  *   A valid shared action handle in case of success, NULL otherwise and
11113  *   rte_errno is set.
11114  */
11115 static struct rte_flow_shared_action *
11116 __flow_dv_action_create(struct rte_eth_dev *dev,
11117                         const struct rte_flow_shared_action_conf *conf,
11118                         const struct rte_flow_action *action,
11119                         struct rte_flow_error *error)
11120 {
11121         struct rte_flow_shared_action *shared_action = NULL;
11122         struct mlx5_priv *priv = dev->data->dev_private;
11123
11124         switch (action->type) {
11125         case RTE_FLOW_ACTION_TYPE_RSS:
11126                 shared_action = __flow_dv_action_rss_create(dev, conf,
11127                                                             action->conf,
11128                                                             error);
11129                 break;
11130         default:
11131                 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11132                                    NULL, "action type not supported");
11133                 break;
11134         }
11135         if (shared_action) {
11136                 __atomic_add_fetch(&shared_action->refcnt, 1,
11137                                    __ATOMIC_RELAXED);
11138                 LIST_INSERT_HEAD(&priv->shared_actions, shared_action, next);
11139         }
11140         return shared_action;
11141 }
11142
11143 /**
11144  * Destroy the shared action.
11145  * Release action related resources on the NIC and the memory.
11146  * Lock free, (mutex should be acquired by caller).
11147  * Dispatcher for action type specific call.
11148  *
11149  * @param[in] dev
11150  *   Pointer to the Ethernet device structure.
11151  * @param[in] action
11152  *   The shared action object to be removed.
11153  * @param[out] error
11154  *   Perform verbose error reporting if not NULL. Initialized in case of
11155  *   error only.
11156  *
11157  * @return
11158  *   0 on success, otherwise negative errno value.
11159  */
11160 static int
11161 __flow_dv_action_destroy(struct rte_eth_dev *dev,
11162                          struct rte_flow_shared_action *action,
11163                          struct rte_flow_error *error)
11164 {
11165         int ret;
11166
11167         switch (action->type) {
11168         case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11169                 ret = __flow_dv_action_rss_release(dev, &action->rss, error);
11170                 break;
11171         default:
11172                 return rte_flow_error_set(error, ENOTSUP,
11173                                           RTE_FLOW_ERROR_TYPE_ACTION,
11174                                           NULL,
11175                                           "action type not supported");
11176         }
11177         if (ret)
11178                 return ret;
11179         LIST_REMOVE(action, next);
11180         rte_free(action);
11181         return 0;
11182 }
11183
11184 /**
11185  * Updates in place shared RSS action configuration.
11186  *
11187  * @param[in] dev
11188  *   Pointer to the Ethernet device structure.
11189  * @param[in] shared_rss
11190  *   The shared RSS action object to be updated.
11191  * @param[in] action_conf
11192  *   RSS action specification used to modify *shared_rss*.
11193  * @param[out] error
11194  *   Perform verbose error reporting if not NULL. Initialized in case of
11195  *   error only.
11196  *
11197  * @return
11198  *   0 on success, otherwise negative errno value.
11199  * @note: currently only support update of RSS queues.
11200  */
11201 static int
11202 __flow_dv_action_rss_update(struct rte_eth_dev *dev,
11203                             struct mlx5_shared_action_rss *shared_rss,
11204                             const struct rte_flow_action_rss *action_conf,
11205                             struct rte_flow_error *error)
11206 {
11207         size_t i;
11208         int ret;
11209         void *queue = NULL;
11210         const uint8_t *rss_key;
11211         uint32_t rss_key_len;
11212         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11213
11214         queue = mlx5_malloc(MLX5_MEM_ZERO,
11215                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11216                             0, SOCKET_ID_ANY);
11217         if (!queue)
11218                 return rte_flow_error_set(error, ENOMEM,
11219                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11220                                           NULL,
11221                                           "cannot allocate resource memory");
11222         if (action_conf->key) {
11223                 rss_key = action_conf->key;
11224                 rss_key_len = action_conf->key_len;
11225         } else {
11226                 rss_key = rss_hash_default_key;
11227                 rss_key_len = MLX5_RSS_HASH_KEY_LEN;
11228         }
11229         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11230                 uint32_t hrxq_idx;
11231                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11232                 int tunnel;
11233
11234                 for (tunnel = 0; tunnel < 2; tunnel++) {
11235                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup
11236                                         (shared_rss, hash_fields, tunnel);
11237                         MLX5_ASSERT(hrxq_idx);
11238                         ret = mlx5_hrxq_modify
11239                                 (dev, hrxq_idx,
11240                                  rss_key, rss_key_len,
11241                                  hash_fields,
11242                                  action_conf->queue, action_conf->queue_num);
11243                         if (ret) {
11244                                 mlx5_free(queue);
11245                                 return rte_flow_error_set
11246                                         (error, rte_errno,
11247                                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11248                                          "cannot update hash queue");
11249                         }
11250                 }
11251         }
11252         mlx5_free(shared_rss->queue);
11253         shared_rss->queue = queue;
11254         memcpy(shared_rss->queue, action_conf->queue, queue_size);
11255         shared_rss->origin.queue = shared_rss->queue;
11256         shared_rss->origin.queue_num = action_conf->queue_num;
11257         return 0;
11258 }
11259
11260 /**
11261  * Updates in place shared action configuration, lock free,
11262  * (mutex should be acquired by caller).
11263  *
11264  * @param[in] dev
11265  *   Pointer to the Ethernet device structure.
11266  * @param[in] action
11267  *   The shared action object to be updated.
11268  * @param[in] action_conf
11269  *   Action specification used to modify *action*.
11270  *   *action_conf* should be of type correlating with type of the *action*,
11271  *   otherwise considered as invalid.
11272  * @param[out] error
11273  *   Perform verbose error reporting if not NULL. Initialized in case of
11274  *   error only.
11275  *
11276  * @return
11277  *   0 on success, otherwise negative errno value.
11278  */
11279 static int
11280 __flow_dv_action_update(struct rte_eth_dev *dev,
11281                         struct rte_flow_shared_action *action,
11282                         const void *action_conf,
11283                         struct rte_flow_error *error)
11284 {
11285         switch (action->type) {
11286         case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11287                 return __flow_dv_action_rss_update(dev, &action->rss,
11288                                                    action_conf, error);
11289         default:
11290                 return rte_flow_error_set(error, ENOTSUP,
11291                                           RTE_FLOW_ERROR_TYPE_ACTION,
11292                                           NULL,
11293                                           "action type not supported");
11294         }
11295 }
11296 /**
11297  * Query a dv flow  rule for its statistics via devx.
11298  *
11299  * @param[in] dev
11300  *   Pointer to Ethernet device.
11301  * @param[in] flow
11302  *   Pointer to the sub flow.
11303  * @param[out] data
11304  *   data retrieved by the query.
11305  * @param[out] error
11306  *   Perform verbose error reporting if not NULL.
11307  *
11308  * @return
11309  *   0 on success, a negative errno value otherwise and rte_errno is set.
11310  */
11311 static int
11312 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11313                     void *data, struct rte_flow_error *error)
11314 {
11315         struct mlx5_priv *priv = dev->data->dev_private;
11316         struct rte_flow_query_count *qc = data;
11317
11318         if (!priv->config.devx)
11319                 return rte_flow_error_set(error, ENOTSUP,
11320                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11321                                           NULL,
11322                                           "counters are not supported");
11323         if (flow->counter) {
11324                 uint64_t pkts, bytes;
11325                 struct mlx5_flow_counter *cnt;
11326
11327                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11328                                                  NULL);
11329                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11330                                                &bytes);
11331
11332                 if (err)
11333                         return rte_flow_error_set(error, -err,
11334                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11335                                         NULL, "cannot read counters");
11336                 qc->hits_set = 1;
11337                 qc->bytes_set = 1;
11338                 qc->hits = pkts - cnt->hits;
11339                 qc->bytes = bytes - cnt->bytes;
11340                 if (qc->reset) {
11341                         cnt->hits = pkts;
11342                         cnt->bytes = bytes;
11343                 }
11344                 return 0;
11345         }
11346         return rte_flow_error_set(error, EINVAL,
11347                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11348                                   NULL,
11349                                   "counters are not available");
11350 }
11351
11352 /**
11353  * Query a flow rule AGE action for aging information.
11354  *
11355  * @param[in] dev
11356  *   Pointer to Ethernet device.
11357  * @param[in] flow
11358  *   Pointer to the sub flow.
11359  * @param[out] data
11360  *   data retrieved by the query.
11361  * @param[out] error
11362  *   Perform verbose error reporting if not NULL.
11363  *
11364  * @return
11365  *   0 on success, a negative errno value otherwise and rte_errno is set.
11366  */
11367 static int
11368 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11369                   void *data, struct rte_flow_error *error)
11370 {
11371         struct rte_flow_query_age *resp = data;
11372
11373         if (flow->counter) {
11374                 struct mlx5_age_param *age_param =
11375                                 flow_dv_counter_idx_get_age(dev, flow->counter);
11376
11377                 if (!age_param || !age_param->timeout)
11378                         return rte_flow_error_set
11379                                         (error, EINVAL,
11380                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11381                                          NULL, "cannot read age data");
11382                 resp->aged = __atomic_load_n(&age_param->state,
11383                                              __ATOMIC_RELAXED) ==
11384                                                         AGE_TMOUT ? 1 : 0;
11385                 resp->sec_since_last_hit_valid = !resp->aged;
11386                 if (resp->sec_since_last_hit_valid)
11387                         resp->sec_since_last_hit =
11388                                 __atomic_load_n(&age_param->sec_since_last_hit,
11389                                                 __ATOMIC_RELAXED);
11390                 return 0;
11391         }
11392         return rte_flow_error_set(error, EINVAL,
11393                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11394                                   NULL,
11395                                   "age data not available");
11396 }
11397
11398 /**
11399  * Query a flow.
11400  *
11401  * @see rte_flow_query()
11402  * @see rte_flow_ops
11403  */
11404 static int
11405 flow_dv_query(struct rte_eth_dev *dev,
11406               struct rte_flow *flow __rte_unused,
11407               const struct rte_flow_action *actions __rte_unused,
11408               void *data __rte_unused,
11409               struct rte_flow_error *error __rte_unused)
11410 {
11411         int ret = -EINVAL;
11412
11413         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11414                 switch (actions->type) {
11415                 case RTE_FLOW_ACTION_TYPE_VOID:
11416                         break;
11417                 case RTE_FLOW_ACTION_TYPE_COUNT:
11418                         ret = flow_dv_query_count(dev, flow, data, error);
11419                         break;
11420                 case RTE_FLOW_ACTION_TYPE_AGE:
11421                         ret = flow_dv_query_age(dev, flow, data, error);
11422                         break;
11423                 default:
11424                         return rte_flow_error_set(error, ENOTSUP,
11425                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11426                                                   actions,
11427                                                   "action not supported");
11428                 }
11429         }
11430         return ret;
11431 }
11432
11433 /**
11434  * Destroy the meter table set.
11435  * Lock free, (mutex should be acquired by caller).
11436  *
11437  * @param[in] dev
11438  *   Pointer to Ethernet device.
11439  * @param[in] tbl
11440  *   Pointer to the meter table set.
11441  *
11442  * @return
11443  *   Always 0.
11444  */
11445 static int
11446 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11447                         struct mlx5_meter_domains_infos *tbl)
11448 {
11449         struct mlx5_priv *priv = dev->data->dev_private;
11450         struct mlx5_meter_domains_infos *mtd =
11451                                 (struct mlx5_meter_domains_infos *)tbl;
11452
11453         if (!mtd || !priv->config.dv_flow_en)
11454                 return 0;
11455         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11456                 claim_zero(mlx5_flow_os_destroy_flow
11457                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11458         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11459                 claim_zero(mlx5_flow_os_destroy_flow
11460                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11461         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11462                 claim_zero(mlx5_flow_os_destroy_flow
11463                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
11464         if (mtd->egress.color_matcher)
11465                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11466                            (mtd->egress.color_matcher));
11467         if (mtd->egress.any_matcher)
11468                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11469                            (mtd->egress.any_matcher));
11470         if (mtd->egress.tbl)
11471                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
11472         if (mtd->egress.sfx_tbl)
11473                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
11474         if (mtd->ingress.color_matcher)
11475                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11476                            (mtd->ingress.color_matcher));
11477         if (mtd->ingress.any_matcher)
11478                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11479                            (mtd->ingress.any_matcher));
11480         if (mtd->ingress.tbl)
11481                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
11482         if (mtd->ingress.sfx_tbl)
11483                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
11484         if (mtd->transfer.color_matcher)
11485                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11486                            (mtd->transfer.color_matcher));
11487         if (mtd->transfer.any_matcher)
11488                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11489                            (mtd->transfer.any_matcher));
11490         if (mtd->transfer.tbl)
11491                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
11492         if (mtd->transfer.sfx_tbl)
11493                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
11494         if (mtd->drop_actn)
11495                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
11496         mlx5_free(mtd);
11497         return 0;
11498 }
11499
11500 /* Number of meter flow actions, count and jump or count and drop. */
11501 #define METER_ACTIONS 2
11502
11503 /**
11504  * Create specify domain meter table and suffix table.
11505  *
11506  * @param[in] dev
11507  *   Pointer to Ethernet device.
11508  * @param[in,out] mtb
11509  *   Pointer to DV meter table set.
11510  * @param[in] egress
11511  *   Table attribute.
11512  * @param[in] transfer
11513  *   Table attribute.
11514  * @param[in] color_reg_c_idx
11515  *   Reg C index for color match.
11516  *
11517  * @return
11518  *   0 on success, -1 otherwise and rte_errno is set.
11519  */
11520 static int
11521 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
11522                            struct mlx5_meter_domains_infos *mtb,
11523                            uint8_t egress, uint8_t transfer,
11524                            uint32_t color_reg_c_idx)
11525 {
11526         struct mlx5_priv *priv = dev->data->dev_private;
11527         struct mlx5_dev_ctx_shared *sh = priv->sh;
11528         struct mlx5_flow_dv_match_params mask = {
11529                 .size = sizeof(mask.buf),
11530         };
11531         struct mlx5_flow_dv_match_params value = {
11532                 .size = sizeof(value.buf),
11533         };
11534         struct mlx5dv_flow_matcher_attr dv_attr = {
11535                 .type = IBV_FLOW_ATTR_NORMAL,
11536                 .priority = 0,
11537                 .match_criteria_enable = 0,
11538                 .match_mask = (void *)&mask,
11539         };
11540         void *actions[METER_ACTIONS];
11541         struct mlx5_meter_domain_info *dtb;
11542         struct rte_flow_error error;
11543         int i = 0;
11544         int ret;
11545
11546         if (transfer)
11547                 dtb = &mtb->transfer;
11548         else if (egress)
11549                 dtb = &mtb->egress;
11550         else
11551                 dtb = &mtb->ingress;
11552         /* Create the meter table with METER level. */
11553         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
11554                                             egress, transfer, false, NULL, 0,
11555                                             &error);
11556         if (!dtb->tbl) {
11557                 DRV_LOG(ERR, "Failed to create meter policer table.");
11558                 return -1;
11559         }
11560         /* Create the meter suffix table with SUFFIX level. */
11561         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
11562                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
11563                                             egress, transfer, false, NULL, 0,
11564                                             &error);
11565         if (!dtb->sfx_tbl) {
11566                 DRV_LOG(ERR, "Failed to create meter suffix table.");
11567                 return -1;
11568         }
11569         /* Create matchers, Any and Color. */
11570         dv_attr.priority = 3;
11571         dv_attr.match_criteria_enable = 0;
11572         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11573                                                &dtb->any_matcher);
11574         if (ret) {
11575                 DRV_LOG(ERR, "Failed to create meter"
11576                              " policer default matcher.");
11577                 goto error_exit;
11578         }
11579         dv_attr.priority = 0;
11580         dv_attr.match_criteria_enable =
11581                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
11582         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
11583                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
11584         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11585                                                &dtb->color_matcher);
11586         if (ret) {
11587                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
11588                 goto error_exit;
11589         }
11590         if (mtb->count_actns[RTE_MTR_DROPPED])
11591                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
11592         actions[i++] = mtb->drop_actn;
11593         /* Default rule: lowest priority, match any, actions: drop. */
11594         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
11595                                        actions,
11596                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
11597         if (ret) {
11598                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
11599                 goto error_exit;
11600         }
11601         return 0;
11602 error_exit:
11603         return -1;
11604 }
11605
11606 /**
11607  * Create the needed meter and suffix tables.
11608  * Lock free, (mutex should be acquired by caller).
11609  *
11610  * @param[in] dev
11611  *   Pointer to Ethernet device.
11612  * @param[in] fm
11613  *   Pointer to the flow meter.
11614  *
11615  * @return
11616  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
11617  */
11618 static struct mlx5_meter_domains_infos *
11619 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
11620                        const struct mlx5_flow_meter *fm)
11621 {
11622         struct mlx5_priv *priv = dev->data->dev_private;
11623         struct mlx5_meter_domains_infos *mtb;
11624         int ret;
11625         int i;
11626
11627         if (!priv->mtr_en) {
11628                 rte_errno = ENOTSUP;
11629                 return NULL;
11630         }
11631         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
11632         if (!mtb) {
11633                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
11634                 return NULL;
11635         }
11636         /* Create meter count actions */
11637         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
11638                 struct mlx5_flow_counter *cnt;
11639                 if (!fm->policer_stats.cnt[i])
11640                         continue;
11641                 cnt = flow_dv_counter_get_by_idx(dev,
11642                       fm->policer_stats.cnt[i], NULL);
11643                 mtb->count_actns[i] = cnt->action;
11644         }
11645         /* Create drop action. */
11646         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
11647         if (ret) {
11648                 DRV_LOG(ERR, "Failed to create drop action.");
11649                 goto error_exit;
11650         }
11651         /* Egress meter table. */
11652         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
11653         if (ret) {
11654                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
11655                 goto error_exit;
11656         }
11657         /* Ingress meter table. */
11658         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
11659         if (ret) {
11660                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
11661                 goto error_exit;
11662         }
11663         /* FDB meter table. */
11664         if (priv->config.dv_esw_en) {
11665                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
11666                                                  priv->mtr_color_reg);
11667                 if (ret) {
11668                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
11669                         goto error_exit;
11670                 }
11671         }
11672         return mtb;
11673 error_exit:
11674         flow_dv_destroy_mtr_tbl(dev, mtb);
11675         return NULL;
11676 }
11677
11678 /**
11679  * Destroy domain policer rule.
11680  *
11681  * @param[in] dt
11682  *   Pointer to domain table.
11683  */
11684 static void
11685 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
11686 {
11687         int i;
11688
11689         for (i = 0; i < RTE_MTR_DROPPED; i++) {
11690                 if (dt->policer_rules[i]) {
11691                         claim_zero(mlx5_flow_os_destroy_flow
11692                                    (dt->policer_rules[i]));
11693                         dt->policer_rules[i] = NULL;
11694                 }
11695         }
11696         if (dt->jump_actn) {
11697                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
11698                 dt->jump_actn = NULL;
11699         }
11700 }
11701
11702 /**
11703  * Destroy policer rules.
11704  *
11705  * @param[in] dev
11706  *   Pointer to Ethernet device.
11707  * @param[in] fm
11708  *   Pointer to flow meter structure.
11709  * @param[in] attr
11710  *   Pointer to flow attributes.
11711  *
11712  * @return
11713  *   Always 0.
11714  */
11715 static int
11716 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
11717                               const struct mlx5_flow_meter *fm,
11718                               const struct rte_flow_attr *attr)
11719 {
11720         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
11721
11722         if (!mtb)
11723                 return 0;
11724         if (attr->egress)
11725                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
11726         if (attr->ingress)
11727                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
11728         if (attr->transfer)
11729                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
11730         return 0;
11731 }
11732
11733 /**
11734  * Create specify domain meter policer rule.
11735  *
11736  * @param[in] fm
11737  *   Pointer to flow meter structure.
11738  * @param[in] mtb
11739  *   Pointer to DV meter table set.
11740  * @param[in] mtr_reg_c
11741  *   Color match REG_C.
11742  *
11743  * @return
11744  *   0 on success, -1 otherwise.
11745  */
11746 static int
11747 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
11748                                     struct mlx5_meter_domain_info *dtb,
11749                                     uint8_t mtr_reg_c)
11750 {
11751         struct mlx5_flow_dv_match_params matcher = {
11752                 .size = sizeof(matcher.buf),
11753         };
11754         struct mlx5_flow_dv_match_params value = {
11755                 .size = sizeof(value.buf),
11756         };
11757         struct mlx5_meter_domains_infos *mtb = fm->mfts;
11758         void *actions[METER_ACTIONS];
11759         int i;
11760         int ret = 0;
11761
11762         /* Create jump action. */
11763         if (!dtb->jump_actn)
11764                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11765                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
11766         if (ret) {
11767                 DRV_LOG(ERR, "Failed to create policer jump action.");
11768                 goto error;
11769         }
11770         for (i = 0; i < RTE_MTR_DROPPED; i++) {
11771                 int j = 0;
11772
11773                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
11774                                        rte_col_2_mlx5_col(i), UINT8_MAX);
11775                 if (mtb->count_actns[i])
11776                         actions[j++] = mtb->count_actns[i];
11777                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
11778                         actions[j++] = mtb->drop_actn;
11779                 else
11780                         actions[j++] = dtb->jump_actn;
11781                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
11782                                                (void *)&value, j, actions,
11783                                                &dtb->policer_rules[i]);
11784                 if (ret) {
11785                         DRV_LOG(ERR, "Failed to create policer rule.");
11786                         goto error;
11787                 }
11788         }
11789         return 0;
11790 error:
11791         rte_errno = errno;
11792         return -1;
11793 }
11794
11795 /**
11796  * Create policer rules.
11797  *
11798  * @param[in] dev
11799  *   Pointer to Ethernet device.
11800  * @param[in] fm
11801  *   Pointer to flow meter structure.
11802  * @param[in] attr
11803  *   Pointer to flow attributes.
11804  *
11805  * @return
11806  *   0 on success, -1 otherwise.
11807  */
11808 static int
11809 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
11810                              struct mlx5_flow_meter *fm,
11811                              const struct rte_flow_attr *attr)
11812 {
11813         struct mlx5_priv *priv = dev->data->dev_private;
11814         struct mlx5_meter_domains_infos *mtb = fm->mfts;
11815         int ret;
11816
11817         if (attr->egress) {
11818                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
11819                                                 priv->mtr_color_reg);
11820                 if (ret) {
11821                         DRV_LOG(ERR, "Failed to create egress policer.");
11822                         goto error;
11823                 }
11824         }
11825         if (attr->ingress) {
11826                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
11827                                                 priv->mtr_color_reg);
11828                 if (ret) {
11829                         DRV_LOG(ERR, "Failed to create ingress policer.");
11830                         goto error;
11831                 }
11832         }
11833         if (attr->transfer) {
11834                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
11835                                                 priv->mtr_color_reg);
11836                 if (ret) {
11837                         DRV_LOG(ERR, "Failed to create transfer policer.");
11838                         goto error;
11839                 }
11840         }
11841         return 0;
11842 error:
11843         flow_dv_destroy_policer_rules(dev, fm, attr);
11844         return -1;
11845 }
11846
11847 /**
11848  * Validate the batch counter support in root table.
11849  *
11850  * Create a simple flow with invalid counter and drop action on root table to
11851  * validate if batch counter with offset on root table is supported or not.
11852  *
11853  * @param[in] dev
11854  *   Pointer to rte_eth_dev structure.
11855  *
11856  * @return
11857  *   0 on success, a negative errno value otherwise and rte_errno is set.
11858  */
11859 int
11860 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
11861 {
11862         struct mlx5_priv *priv = dev->data->dev_private;
11863         struct mlx5_dev_ctx_shared *sh = priv->sh;
11864         struct mlx5_flow_dv_match_params mask = {
11865                 .size = sizeof(mask.buf),
11866         };
11867         struct mlx5_flow_dv_match_params value = {
11868                 .size = sizeof(value.buf),
11869         };
11870         struct mlx5dv_flow_matcher_attr dv_attr = {
11871                 .type = IBV_FLOW_ATTR_NORMAL,
11872                 .priority = 0,
11873                 .match_criteria_enable = 0,
11874                 .match_mask = (void *)&mask,
11875         };
11876         void *actions[2] = { 0 };
11877         struct mlx5_flow_tbl_resource *tbl = NULL, *dest_tbl = NULL;
11878         struct mlx5_devx_obj *dcs = NULL;
11879         void *matcher = NULL;
11880         void *flow = NULL;
11881         int i, ret = -1;
11882
11883         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, NULL);
11884         if (!tbl)
11885                 goto err;
11886         dest_tbl = flow_dv_tbl_resource_get(dev, 1, 0, 0, false, NULL, 0, NULL);
11887         if (!dest_tbl)
11888                 goto err;
11889         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
11890         if (!dcs)
11891                 goto err;
11892         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
11893                                                     &actions[0]);
11894         if (ret)
11895                 goto err;
11896         ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11897                                 (dest_tbl->obj, &actions[1]);
11898         if (ret)
11899                 goto err;
11900         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
11901         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
11902                                                &matcher);
11903         if (ret)
11904                 goto err;
11905         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
11906                                        actions, &flow);
11907 err:
11908         /*
11909          * If batch counter with offset is not supported, the driver will not
11910          * validate the invalid offset value, flow create should success.
11911          * In this case, it means batch counter is not supported in root table.
11912          *
11913          * Otherwise, if flow create is failed, counter offset is supported.
11914          */
11915         if (flow) {
11916                 DRV_LOG(INFO, "Batch counter is not supported in root "
11917                               "table. Switch to fallback mode.");
11918                 rte_errno = ENOTSUP;
11919                 ret = -rte_errno;
11920                 claim_zero(mlx5_flow_os_destroy_flow(flow));
11921         } else {
11922                 /* Check matcher to make sure validate fail at flow create. */
11923                 if (!matcher || (matcher && errno != EINVAL))
11924                         DRV_LOG(ERR, "Unexpected error in counter offset "
11925                                      "support detection");
11926                 ret = 0;
11927         }
11928         for (i = 0; i < 2; i++) {
11929                 if (actions[i])
11930                         claim_zero(mlx5_flow_os_destroy_flow_action
11931                                    (actions[i]));
11932         }
11933         if (matcher)
11934                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
11935         if (tbl)
11936                 flow_dv_tbl_resource_release(dev, tbl);
11937         if (dest_tbl)
11938                 flow_dv_tbl_resource_release(dev, dest_tbl);
11939         if (dcs)
11940                 claim_zero(mlx5_devx_cmd_destroy(dcs));
11941         return ret;
11942 }
11943
11944 /**
11945  * Query a devx counter.
11946  *
11947  * @param[in] dev
11948  *   Pointer to the Ethernet device structure.
11949  * @param[in] cnt
11950  *   Index to the flow counter.
11951  * @param[in] clear
11952  *   Set to clear the counter statistics.
11953  * @param[out] pkts
11954  *   The statistics value of packets.
11955  * @param[out] bytes
11956  *   The statistics value of bytes.
11957  *
11958  * @return
11959  *   0 on success, otherwise return -1.
11960  */
11961 static int
11962 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
11963                       uint64_t *pkts, uint64_t *bytes)
11964 {
11965         struct mlx5_priv *priv = dev->data->dev_private;
11966         struct mlx5_flow_counter *cnt;
11967         uint64_t inn_pkts, inn_bytes;
11968         int ret;
11969
11970         if (!priv->config.devx)
11971                 return -1;
11972
11973         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
11974         if (ret)
11975                 return -1;
11976         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
11977         *pkts = inn_pkts - cnt->hits;
11978         *bytes = inn_bytes - cnt->bytes;
11979         if (clear) {
11980                 cnt->hits = inn_pkts;
11981                 cnt->bytes = inn_bytes;
11982         }
11983         return 0;
11984 }
11985
11986 /**
11987  * Get aged-out flows.
11988  *
11989  * @param[in] dev
11990  *   Pointer to the Ethernet device structure.
11991  * @param[in] context
11992  *   The address of an array of pointers to the aged-out flows contexts.
11993  * @param[in] nb_contexts
11994  *   The length of context array pointers.
11995  * @param[out] error
11996  *   Perform verbose error reporting if not NULL. Initialized in case of
11997  *   error only.
11998  *
11999  * @return
12000  *   how many contexts get in success, otherwise negative errno value.
12001  *   if nb_contexts is 0, return the amount of all aged contexts.
12002  *   if nb_contexts is not 0 , return the amount of aged flows reported
12003  *   in the context array.
12004  * @note: only stub for now
12005  */
12006 static int
12007 flow_get_aged_flows(struct rte_eth_dev *dev,
12008                     void **context,
12009                     uint32_t nb_contexts,
12010                     struct rte_flow_error *error)
12011 {
12012         struct mlx5_priv *priv = dev->data->dev_private;
12013         struct mlx5_age_info *age_info;
12014         struct mlx5_age_param *age_param;
12015         struct mlx5_flow_counter *counter;
12016         int nb_flows = 0;
12017
12018         if (nb_contexts && !context)
12019                 return rte_flow_error_set(error, EINVAL,
12020                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12021                                           NULL,
12022                                           "Should assign at least one flow or"
12023                                           " context to get if nb_contexts != 0");
12024         age_info = GET_PORT_AGE_INFO(priv);
12025         rte_spinlock_lock(&age_info->aged_sl);
12026         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12027                 nb_flows++;
12028                 if (nb_contexts) {
12029                         age_param = MLX5_CNT_TO_AGE(counter);
12030                         context[nb_flows - 1] = age_param->context;
12031                         if (!(--nb_contexts))
12032                                 break;
12033                 }
12034         }
12035         rte_spinlock_unlock(&age_info->aged_sl);
12036         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12037         return nb_flows;
12038 }
12039
12040 /*
12041  * Mutex-protected thunk to lock-free  __flow_dv_translate().
12042  */
12043 static int
12044 flow_dv_translate(struct rte_eth_dev *dev,
12045                   struct mlx5_flow *dev_flow,
12046                   const struct rte_flow_attr *attr,
12047                   const struct rte_flow_item items[],
12048                   const struct rte_flow_action actions[],
12049                   struct rte_flow_error *error)
12050 {
12051         int ret;
12052
12053         flow_dv_shared_lock(dev);
12054         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
12055         flow_dv_shared_unlock(dev);
12056         return ret;
12057 }
12058
12059 /*
12060  * Mutex-protected thunk to lock-free  __flow_dv_apply().
12061  */
12062 static int
12063 flow_dv_apply(struct rte_eth_dev *dev,
12064               struct rte_flow *flow,
12065               struct rte_flow_error *error)
12066 {
12067         int ret;
12068
12069         flow_dv_shared_lock(dev);
12070         ret = __flow_dv_apply(dev, flow, error);
12071         flow_dv_shared_unlock(dev);
12072         return ret;
12073 }
12074
12075 /*
12076  * Mutex-protected thunk to lock-free __flow_dv_remove().
12077  */
12078 static void
12079 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12080 {
12081         flow_dv_shared_lock(dev);
12082         __flow_dv_remove(dev, flow);
12083         flow_dv_shared_unlock(dev);
12084 }
12085
12086 /*
12087  * Mutex-protected thunk to lock-free __flow_dv_destroy().
12088  */
12089 static void
12090 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12091 {
12092         flow_dv_shared_lock(dev);
12093         __flow_dv_destroy(dev, flow);
12094         flow_dv_shared_unlock(dev);
12095 }
12096
12097 /*
12098  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12099  */
12100 static uint32_t
12101 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12102 {
12103         uint32_t cnt;
12104
12105         flow_dv_shared_lock(dev);
12106         cnt = flow_dv_counter_alloc(dev, 0);
12107         flow_dv_shared_unlock(dev);
12108         return cnt;
12109 }
12110
12111 /*
12112  * Mutex-protected thunk to lock-free flow_dv_counter_release().
12113  */
12114 static void
12115 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
12116 {
12117         flow_dv_shared_lock(dev);
12118         flow_dv_counter_release(dev, cnt);
12119         flow_dv_shared_unlock(dev);
12120 }
12121
12122 /**
12123  * Validate shared action.
12124  * Dispatcher for action type specific validation.
12125  *
12126  * @param[in] dev
12127  *   Pointer to the Ethernet device structure.
12128  * @param[in] conf
12129  *   Shared action configuration.
12130  * @param[in] action
12131  *   The shared action object to validate.
12132  * @param[out] error
12133  *   Perform verbose error reporting if not NULL. Initialized in case of
12134  *   error only.
12135  *
12136  * @return
12137  *   0 on success, otherwise negative errno value.
12138  */
12139 static int
12140 flow_dv_action_validate(struct rte_eth_dev *dev,
12141                         const struct rte_flow_shared_action_conf *conf,
12142                         const struct rte_flow_action *action,
12143                         struct rte_flow_error *error)
12144 {
12145         RTE_SET_USED(conf);
12146         switch (action->type) {
12147         case RTE_FLOW_ACTION_TYPE_RSS:
12148                 return mlx5_validate_action_rss(dev, action, error);
12149         default:
12150                 return rte_flow_error_set(error, ENOTSUP,
12151                                           RTE_FLOW_ERROR_TYPE_ACTION,
12152                                           NULL,
12153                                           "action type not supported");
12154         }
12155 }
12156
12157 /*
12158  * Mutex-protected thunk to lock-free  __flow_dv_action_create().
12159  */
12160 static struct rte_flow_shared_action *
12161 flow_dv_action_create(struct rte_eth_dev *dev,
12162                       const struct rte_flow_shared_action_conf *conf,
12163                       const struct rte_flow_action *action,
12164                       struct rte_flow_error *error)
12165 {
12166         struct rte_flow_shared_action *shared_action = NULL;
12167
12168         flow_dv_shared_lock(dev);
12169         shared_action = __flow_dv_action_create(dev, conf, action, error);
12170         flow_dv_shared_unlock(dev);
12171         return shared_action;
12172 }
12173
12174 /*
12175  * Mutex-protected thunk to lock-free  __flow_dv_action_destroy().
12176  */
12177 static int
12178 flow_dv_action_destroy(struct rte_eth_dev *dev,
12179                        struct rte_flow_shared_action *action,
12180                        struct rte_flow_error *error)
12181 {
12182         int ret;
12183
12184         flow_dv_shared_lock(dev);
12185         ret = __flow_dv_action_destroy(dev, action, error);
12186         flow_dv_shared_unlock(dev);
12187         return ret;
12188 }
12189
12190 /*
12191  * Mutex-protected thunk to lock-free  __flow_dv_action_update().
12192  */
12193 static int
12194 flow_dv_action_update(struct rte_eth_dev *dev,
12195                       struct rte_flow_shared_action *action,
12196                       const void *action_conf,
12197                       struct rte_flow_error *error)
12198 {
12199         int ret;
12200
12201         flow_dv_shared_lock(dev);
12202         ret = __flow_dv_action_update(dev, action, action_conf,
12203                                       error);
12204         flow_dv_shared_unlock(dev);
12205         return ret;
12206 }
12207
12208 static int
12209 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12210 {
12211         struct mlx5_priv *priv = dev->data->dev_private;
12212         int ret = 0;
12213
12214         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12215                 ret = mlx5_glue->dr_sync_domain(priv->sh->rx_domain,
12216                                                 flags);
12217                 if (ret != 0)
12218                         return ret;
12219         }
12220         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12221                 ret = mlx5_glue->dr_sync_domain(priv->sh->tx_domain, flags);
12222                 if (ret != 0)
12223                         return ret;
12224         }
12225         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12226                 ret = mlx5_glue->dr_sync_domain(priv->sh->fdb_domain, flags);
12227                 if (ret != 0)
12228                         return ret;
12229         }
12230         return 0;
12231 }
12232
12233 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12234         .validate = flow_dv_validate,
12235         .prepare = flow_dv_prepare,
12236         .translate = flow_dv_translate,
12237         .apply = flow_dv_apply,
12238         .remove = flow_dv_remove,
12239         .destroy = flow_dv_destroy,
12240         .query = flow_dv_query,
12241         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12242         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12243         .create_policer_rules = flow_dv_create_policer_rules,
12244         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12245         .counter_alloc = flow_dv_counter_allocate,
12246         .counter_free = flow_dv_counter_free,
12247         .counter_query = flow_dv_counter_query,
12248         .get_aged_flows = flow_get_aged_flows,
12249         .action_validate = flow_dv_action_validate,
12250         .action_create = flow_dv_action_create,
12251         .action_destroy = flow_dv_action_destroy,
12252         .action_update = flow_dv_action_update,
12253         .sync_domain = flow_dv_sync_domain,
12254 };
12255
12256 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12257