504d842c09f3c3a2fe7bb67d4ffc29c2f1868093
[dpdk.git] / drivers / net / mlx5 / mlx5_flow_dv.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2018 Mellanox Technologies, Ltd
3  */
4
5 #include <sys/queue.h>
6 #include <stdalign.h>
7 #include <stdint.h>
8 #include <string.h>
9 #include <unistd.h>
10
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
14 #include <rte_flow.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
18 #include <rte_ip.h>
19 #include <rte_gre.h>
20 #include <rte_vxlan.h>
21 #include <rte_gtp.h>
22 #include <rte_eal_paging.h>
23 #include <rte_mpls.h>
24
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
27 #include <mlx5_prm.h>
28 #include <mlx5_malloc.h>
29
30 #include "mlx5_defs.h"
31 #include "mlx5.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
36
37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
38
39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
41 #endif
42
43 #ifndef HAVE_MLX5DV_DR_ESWITCH
44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
46 #endif
47 #endif
48
49 #ifndef HAVE_MLX5DV_DR
50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
51 #endif
52
53 /* VLAN header definitions */
54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
59
60 union flow_dv_attr {
61         struct {
62                 uint32_t valid:1;
63                 uint32_t ipv4:1;
64                 uint32_t ipv6:1;
65                 uint32_t tcp:1;
66                 uint32_t udp:1;
67                 uint32_t reserved:27;
68         };
69         uint32_t attr;
70 };
71
72 static int
73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
74                              struct mlx5_flow_tbl_resource *tbl);
75
76 static int
77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
78
79 static int
80 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
81                                       uint32_t encap_decap_idx);
82
83 static int
84 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
85                                         uint32_t port_id);
86
87 /**
88  * Initialize flow attributes structure according to flow items' types.
89  *
90  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
91  * mode. For tunnel mode, the items to be modified are the outermost ones.
92  *
93  * @param[in] item
94  *   Pointer to item specification.
95  * @param[out] attr
96  *   Pointer to flow attributes structure.
97  * @param[in] dev_flow
98  *   Pointer to the sub flow.
99  * @param[in] tunnel_decap
100  *   Whether action is after tunnel decapsulation.
101  */
102 static void
103 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
104                   struct mlx5_flow *dev_flow, bool tunnel_decap)
105 {
106         uint64_t layers = dev_flow->handle->layers;
107
108         /*
109          * If layers is already initialized, it means this dev_flow is the
110          * suffix flow, the layers flags is set by the prefix flow. Need to
111          * use the layer flags from prefix flow as the suffix flow may not
112          * have the user defined items as the flow is split.
113          */
114         if (layers) {
115                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
116                         attr->ipv4 = 1;
117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
118                         attr->ipv6 = 1;
119                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
120                         attr->tcp = 1;
121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
122                         attr->udp = 1;
123                 attr->valid = 1;
124                 return;
125         }
126         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
127                 uint8_t next_protocol = 0xff;
128                 switch (item->type) {
129                 case RTE_FLOW_ITEM_TYPE_GRE:
130                 case RTE_FLOW_ITEM_TYPE_NVGRE:
131                 case RTE_FLOW_ITEM_TYPE_VXLAN:
132                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
133                 case RTE_FLOW_ITEM_TYPE_GENEVE:
134                 case RTE_FLOW_ITEM_TYPE_MPLS:
135                         if (tunnel_decap)
136                                 attr->attr = 0;
137                         break;
138                 case RTE_FLOW_ITEM_TYPE_IPV4:
139                         if (!attr->ipv6)
140                                 attr->ipv4 = 1;
141                         if (item->mask != NULL &&
142                             ((const struct rte_flow_item_ipv4 *)
143                             item->mask)->hdr.next_proto_id)
144                                 next_protocol =
145                                     ((const struct rte_flow_item_ipv4 *)
146                                       (item->spec))->hdr.next_proto_id &
147                                     ((const struct rte_flow_item_ipv4 *)
148                                       (item->mask))->hdr.next_proto_id;
149                         if ((next_protocol == IPPROTO_IPIP ||
150                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
151                                 attr->attr = 0;
152                         break;
153                 case RTE_FLOW_ITEM_TYPE_IPV6:
154                         if (!attr->ipv4)
155                                 attr->ipv6 = 1;
156                         if (item->mask != NULL &&
157                             ((const struct rte_flow_item_ipv6 *)
158                             item->mask)->hdr.proto)
159                                 next_protocol =
160                                     ((const struct rte_flow_item_ipv6 *)
161                                       (item->spec))->hdr.proto &
162                                     ((const struct rte_flow_item_ipv6 *)
163                                       (item->mask))->hdr.proto;
164                         if ((next_protocol == IPPROTO_IPIP ||
165                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
166                                 attr->attr = 0;
167                         break;
168                 case RTE_FLOW_ITEM_TYPE_UDP:
169                         if (!attr->tcp)
170                                 attr->udp = 1;
171                         break;
172                 case RTE_FLOW_ITEM_TYPE_TCP:
173                         if (!attr->udp)
174                                 attr->tcp = 1;
175                         break;
176                 default:
177                         break;
178                 }
179         }
180         attr->valid = 1;
181 }
182
183 /**
184  * Convert rte_mtr_color to mlx5 color.
185  *
186  * @param[in] rcol
187  *   rte_mtr_color.
188  *
189  * @return
190  *   mlx5 color.
191  */
192 static int
193 rte_col_2_mlx5_col(enum rte_color rcol)
194 {
195         switch (rcol) {
196         case RTE_COLOR_GREEN:
197                 return MLX5_FLOW_COLOR_GREEN;
198         case RTE_COLOR_YELLOW:
199                 return MLX5_FLOW_COLOR_YELLOW;
200         case RTE_COLOR_RED:
201                 return MLX5_FLOW_COLOR_RED;
202         default:
203                 break;
204         }
205         return MLX5_FLOW_COLOR_UNDEFINED;
206 }
207
208 struct field_modify_info {
209         uint32_t size; /* Size of field in protocol header, in bytes. */
210         uint32_t offset; /* Offset of field in protocol header, in bytes. */
211         enum mlx5_modification_field id;
212 };
213
214 struct field_modify_info modify_eth[] = {
215         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
216         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
217         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
218         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
219         {0, 0, 0},
220 };
221
222 struct field_modify_info modify_vlan_out_first_vid[] = {
223         /* Size in bits !!! */
224         {12, 0, MLX5_MODI_OUT_FIRST_VID},
225         {0, 0, 0},
226 };
227
228 struct field_modify_info modify_ipv4[] = {
229         {1,  1, MLX5_MODI_OUT_IP_DSCP},
230         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
231         {4, 12, MLX5_MODI_OUT_SIPV4},
232         {4, 16, MLX5_MODI_OUT_DIPV4},
233         {0, 0, 0},
234 };
235
236 struct field_modify_info modify_ipv6[] = {
237         {1,  0, MLX5_MODI_OUT_IP_DSCP},
238         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
239         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
240         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
241         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
242         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
243         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
244         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
245         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
246         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
247         {0, 0, 0},
248 };
249
250 struct field_modify_info modify_udp[] = {
251         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
252         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
253         {0, 0, 0},
254 };
255
256 struct field_modify_info modify_tcp[] = {
257         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
258         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
259         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
260         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
261         {0, 0, 0},
262 };
263
264 static void
265 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
266                           uint8_t next_protocol, uint64_t *item_flags,
267                           int *tunnel)
268 {
269         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
270                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
271         if (next_protocol == IPPROTO_IPIP) {
272                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
273                 *tunnel = 1;
274         }
275         if (next_protocol == IPPROTO_IPV6) {
276                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
277                 *tunnel = 1;
278         }
279 }
280
281 /**
282  * Acquire the synchronizing object to protect multithreaded access
283  * to shared dv context. Lock occurs only if context is actually
284  * shared, i.e. we have multiport IB device and representors are
285  * created.
286  *
287  * @param[in] dev
288  *   Pointer to the rte_eth_dev structure.
289  */
290 static void
291 flow_dv_shared_lock(struct rte_eth_dev *dev)
292 {
293         struct mlx5_priv *priv = dev->data->dev_private;
294         struct mlx5_dev_ctx_shared *sh = priv->sh;
295
296         if (sh->refcnt > 1) {
297                 int ret;
298
299                 ret = pthread_mutex_lock(&sh->dv_mutex);
300                 MLX5_ASSERT(!ret);
301                 (void)ret;
302         }
303 }
304
305 static void
306 flow_dv_shared_unlock(struct rte_eth_dev *dev)
307 {
308         struct mlx5_priv *priv = dev->data->dev_private;
309         struct mlx5_dev_ctx_shared *sh = priv->sh;
310
311         if (sh->refcnt > 1) {
312                 int ret;
313
314                 ret = pthread_mutex_unlock(&sh->dv_mutex);
315                 MLX5_ASSERT(!ret);
316                 (void)ret;
317         }
318 }
319
320 /* Update VLAN's VID/PCP based on input rte_flow_action.
321  *
322  * @param[in] action
323  *   Pointer to struct rte_flow_action.
324  * @param[out] vlan
325  *   Pointer to struct rte_vlan_hdr.
326  */
327 static void
328 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
329                          struct rte_vlan_hdr *vlan)
330 {
331         uint16_t vlan_tci;
332         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
333                 vlan_tci =
334                     ((const struct rte_flow_action_of_set_vlan_pcp *)
335                                                action->conf)->vlan_pcp;
336                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
337                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
338                 vlan->vlan_tci |= vlan_tci;
339         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
340                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
341                 vlan->vlan_tci |= rte_be_to_cpu_16
342                     (((const struct rte_flow_action_of_set_vlan_vid *)
343                                              action->conf)->vlan_vid);
344         }
345 }
346
347 /**
348  * Fetch 1, 2, 3 or 4 byte field from the byte array
349  * and return as unsigned integer in host-endian format.
350  *
351  * @param[in] data
352  *   Pointer to data array.
353  * @param[in] size
354  *   Size of field to extract.
355  *
356  * @return
357  *   converted field in host endian format.
358  */
359 static inline uint32_t
360 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
361 {
362         uint32_t ret;
363
364         switch (size) {
365         case 1:
366                 ret = *data;
367                 break;
368         case 2:
369                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
370                 break;
371         case 3:
372                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
373                 ret = (ret << 8) | *(data + sizeof(uint16_t));
374                 break;
375         case 4:
376                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
377                 break;
378         default:
379                 MLX5_ASSERT(false);
380                 ret = 0;
381                 break;
382         }
383         return ret;
384 }
385
386 /**
387  * Convert modify-header action to DV specification.
388  *
389  * Data length of each action is determined by provided field description
390  * and the item mask. Data bit offset and width of each action is determined
391  * by provided item mask.
392  *
393  * @param[in] item
394  *   Pointer to item specification.
395  * @param[in] field
396  *   Pointer to field modification information.
397  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
398  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
399  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
400  * @param[in] dcopy
401  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
402  *   Negative offset value sets the same offset as source offset.
403  *   size field is ignored, value is taken from source field.
404  * @param[in,out] resource
405  *   Pointer to the modify-header resource.
406  * @param[in] type
407  *   Type of modification.
408  * @param[out] error
409  *   Pointer to the error structure.
410  *
411  * @return
412  *   0 on success, a negative errno value otherwise and rte_errno is set.
413  */
414 static int
415 flow_dv_convert_modify_action(struct rte_flow_item *item,
416                               struct field_modify_info *field,
417                               struct field_modify_info *dcopy,
418                               struct mlx5_flow_dv_modify_hdr_resource *resource,
419                               uint32_t type, struct rte_flow_error *error)
420 {
421         uint32_t i = resource->actions_num;
422         struct mlx5_modification_cmd *actions = resource->actions;
423
424         /*
425          * The item and mask are provided in big-endian format.
426          * The fields should be presented as in big-endian format either.
427          * Mask must be always present, it defines the actual field width.
428          */
429         MLX5_ASSERT(item->mask);
430         MLX5_ASSERT(field->size);
431         do {
432                 unsigned int size_b;
433                 unsigned int off_b;
434                 uint32_t mask;
435                 uint32_t data;
436
437                 if (i >= MLX5_MAX_MODIFY_NUM)
438                         return rte_flow_error_set(error, EINVAL,
439                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
440                                  "too many items to modify");
441                 /* Fetch variable byte size mask from the array. */
442                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
443                                            field->offset, field->size);
444                 if (!mask) {
445                         ++field;
446                         continue;
447                 }
448                 /* Deduce actual data width in bits from mask value. */
449                 off_b = rte_bsf32(mask);
450                 size_b = sizeof(uint32_t) * CHAR_BIT -
451                          off_b - __builtin_clz(mask);
452                 MLX5_ASSERT(size_b);
453                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
454                 actions[i] = (struct mlx5_modification_cmd) {
455                         .action_type = type,
456                         .field = field->id,
457                         .offset = off_b,
458                         .length = size_b,
459                 };
460                 /* Convert entire record to expected big-endian format. */
461                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
462                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
463                         MLX5_ASSERT(dcopy);
464                         actions[i].dst_field = dcopy->id;
465                         actions[i].dst_offset =
466                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
467                         /* Convert entire record to big-endian format. */
468                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
469                 } else {
470                         MLX5_ASSERT(item->spec);
471                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
472                                                    field->offset, field->size);
473                         /* Shift out the trailing masked bits from data. */
474                         data = (data & mask) >> off_b;
475                         actions[i].data1 = rte_cpu_to_be_32(data);
476                 }
477                 ++i;
478                 ++field;
479         } while (field->size);
480         if (resource->actions_num == i)
481                 return rte_flow_error_set(error, EINVAL,
482                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
483                                           "invalid modification flow item");
484         resource->actions_num = i;
485         return 0;
486 }
487
488 /**
489  * Convert modify-header set IPv4 address action to DV specification.
490  *
491  * @param[in,out] resource
492  *   Pointer to the modify-header resource.
493  * @param[in] action
494  *   Pointer to action specification.
495  * @param[out] error
496  *   Pointer to the error structure.
497  *
498  * @return
499  *   0 on success, a negative errno value otherwise and rte_errno is set.
500  */
501 static int
502 flow_dv_convert_action_modify_ipv4
503                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
504                          const struct rte_flow_action *action,
505                          struct rte_flow_error *error)
506 {
507         const struct rte_flow_action_set_ipv4 *conf =
508                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
509         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
510         struct rte_flow_item_ipv4 ipv4;
511         struct rte_flow_item_ipv4 ipv4_mask;
512
513         memset(&ipv4, 0, sizeof(ipv4));
514         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
515         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
516                 ipv4.hdr.src_addr = conf->ipv4_addr;
517                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
518         } else {
519                 ipv4.hdr.dst_addr = conf->ipv4_addr;
520                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
521         }
522         item.spec = &ipv4;
523         item.mask = &ipv4_mask;
524         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
525                                              MLX5_MODIFICATION_TYPE_SET, error);
526 }
527
528 /**
529  * Convert modify-header set IPv6 address action to DV specification.
530  *
531  * @param[in,out] resource
532  *   Pointer to the modify-header resource.
533  * @param[in] action
534  *   Pointer to action specification.
535  * @param[out] error
536  *   Pointer to the error structure.
537  *
538  * @return
539  *   0 on success, a negative errno value otherwise and rte_errno is set.
540  */
541 static int
542 flow_dv_convert_action_modify_ipv6
543                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
544                          const struct rte_flow_action *action,
545                          struct rte_flow_error *error)
546 {
547         const struct rte_flow_action_set_ipv6 *conf =
548                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
549         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
550         struct rte_flow_item_ipv6 ipv6;
551         struct rte_flow_item_ipv6 ipv6_mask;
552
553         memset(&ipv6, 0, sizeof(ipv6));
554         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
555         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
556                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
557                        sizeof(ipv6.hdr.src_addr));
558                 memcpy(&ipv6_mask.hdr.src_addr,
559                        &rte_flow_item_ipv6_mask.hdr.src_addr,
560                        sizeof(ipv6.hdr.src_addr));
561         } else {
562                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
563                        sizeof(ipv6.hdr.dst_addr));
564                 memcpy(&ipv6_mask.hdr.dst_addr,
565                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
566                        sizeof(ipv6.hdr.dst_addr));
567         }
568         item.spec = &ipv6;
569         item.mask = &ipv6_mask;
570         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
571                                              MLX5_MODIFICATION_TYPE_SET, error);
572 }
573
574 /**
575  * Convert modify-header set MAC address action to DV specification.
576  *
577  * @param[in,out] resource
578  *   Pointer to the modify-header resource.
579  * @param[in] action
580  *   Pointer to action specification.
581  * @param[out] error
582  *   Pointer to the error structure.
583  *
584  * @return
585  *   0 on success, a negative errno value otherwise and rte_errno is set.
586  */
587 static int
588 flow_dv_convert_action_modify_mac
589                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
590                          const struct rte_flow_action *action,
591                          struct rte_flow_error *error)
592 {
593         const struct rte_flow_action_set_mac *conf =
594                 (const struct rte_flow_action_set_mac *)(action->conf);
595         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
596         struct rte_flow_item_eth eth;
597         struct rte_flow_item_eth eth_mask;
598
599         memset(&eth, 0, sizeof(eth));
600         memset(&eth_mask, 0, sizeof(eth_mask));
601         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
602                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
603                        sizeof(eth.src.addr_bytes));
604                 memcpy(&eth_mask.src.addr_bytes,
605                        &rte_flow_item_eth_mask.src.addr_bytes,
606                        sizeof(eth_mask.src.addr_bytes));
607         } else {
608                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
609                        sizeof(eth.dst.addr_bytes));
610                 memcpy(&eth_mask.dst.addr_bytes,
611                        &rte_flow_item_eth_mask.dst.addr_bytes,
612                        sizeof(eth_mask.dst.addr_bytes));
613         }
614         item.spec = &eth;
615         item.mask = &eth_mask;
616         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
617                                              MLX5_MODIFICATION_TYPE_SET, error);
618 }
619
620 /**
621  * Convert modify-header set VLAN VID action to DV specification.
622  *
623  * @param[in,out] resource
624  *   Pointer to the modify-header resource.
625  * @param[in] action
626  *   Pointer to action specification.
627  * @param[out] error
628  *   Pointer to the error structure.
629  *
630  * @return
631  *   0 on success, a negative errno value otherwise and rte_errno is set.
632  */
633 static int
634 flow_dv_convert_action_modify_vlan_vid
635                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
636                          const struct rte_flow_action *action,
637                          struct rte_flow_error *error)
638 {
639         const struct rte_flow_action_of_set_vlan_vid *conf =
640                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
641         int i = resource->actions_num;
642         struct mlx5_modification_cmd *actions = resource->actions;
643         struct field_modify_info *field = modify_vlan_out_first_vid;
644
645         if (i >= MLX5_MAX_MODIFY_NUM)
646                 return rte_flow_error_set(error, EINVAL,
647                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
648                          "too many items to modify");
649         actions[i] = (struct mlx5_modification_cmd) {
650                 .action_type = MLX5_MODIFICATION_TYPE_SET,
651                 .field = field->id,
652                 .length = field->size,
653                 .offset = field->offset,
654         };
655         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
656         actions[i].data1 = conf->vlan_vid;
657         actions[i].data1 = actions[i].data1 << 16;
658         resource->actions_num = ++i;
659         return 0;
660 }
661
662 /**
663  * Convert modify-header set TP action to DV specification.
664  *
665  * @param[in,out] resource
666  *   Pointer to the modify-header resource.
667  * @param[in] action
668  *   Pointer to action specification.
669  * @param[in] items
670  *   Pointer to rte_flow_item objects list.
671  * @param[in] attr
672  *   Pointer to flow attributes structure.
673  * @param[in] dev_flow
674  *   Pointer to the sub flow.
675  * @param[in] tunnel_decap
676  *   Whether action is after tunnel decapsulation.
677  * @param[out] error
678  *   Pointer to the error structure.
679  *
680  * @return
681  *   0 on success, a negative errno value otherwise and rte_errno is set.
682  */
683 static int
684 flow_dv_convert_action_modify_tp
685                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
686                          const struct rte_flow_action *action,
687                          const struct rte_flow_item *items,
688                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
689                          bool tunnel_decap, struct rte_flow_error *error)
690 {
691         const struct rte_flow_action_set_tp *conf =
692                 (const struct rte_flow_action_set_tp *)(action->conf);
693         struct rte_flow_item item;
694         struct rte_flow_item_udp udp;
695         struct rte_flow_item_udp udp_mask;
696         struct rte_flow_item_tcp tcp;
697         struct rte_flow_item_tcp tcp_mask;
698         struct field_modify_info *field;
699
700         if (!attr->valid)
701                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
702         if (attr->udp) {
703                 memset(&udp, 0, sizeof(udp));
704                 memset(&udp_mask, 0, sizeof(udp_mask));
705                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
706                         udp.hdr.src_port = conf->port;
707                         udp_mask.hdr.src_port =
708                                         rte_flow_item_udp_mask.hdr.src_port;
709                 } else {
710                         udp.hdr.dst_port = conf->port;
711                         udp_mask.hdr.dst_port =
712                                         rte_flow_item_udp_mask.hdr.dst_port;
713                 }
714                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
715                 item.spec = &udp;
716                 item.mask = &udp_mask;
717                 field = modify_udp;
718         } else {
719                 MLX5_ASSERT(attr->tcp);
720                 memset(&tcp, 0, sizeof(tcp));
721                 memset(&tcp_mask, 0, sizeof(tcp_mask));
722                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
723                         tcp.hdr.src_port = conf->port;
724                         tcp_mask.hdr.src_port =
725                                         rte_flow_item_tcp_mask.hdr.src_port;
726                 } else {
727                         tcp.hdr.dst_port = conf->port;
728                         tcp_mask.hdr.dst_port =
729                                         rte_flow_item_tcp_mask.hdr.dst_port;
730                 }
731                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
732                 item.spec = &tcp;
733                 item.mask = &tcp_mask;
734                 field = modify_tcp;
735         }
736         return flow_dv_convert_modify_action(&item, field, NULL, resource,
737                                              MLX5_MODIFICATION_TYPE_SET, error);
738 }
739
740 /**
741  * Convert modify-header set TTL action to DV specification.
742  *
743  * @param[in,out] resource
744  *   Pointer to the modify-header resource.
745  * @param[in] action
746  *   Pointer to action specification.
747  * @param[in] items
748  *   Pointer to rte_flow_item objects list.
749  * @param[in] attr
750  *   Pointer to flow attributes structure.
751  * @param[in] dev_flow
752  *   Pointer to the sub flow.
753  * @param[in] tunnel_decap
754  *   Whether action is after tunnel decapsulation.
755  * @param[out] error
756  *   Pointer to the error structure.
757  *
758  * @return
759  *   0 on success, a negative errno value otherwise and rte_errno is set.
760  */
761 static int
762 flow_dv_convert_action_modify_ttl
763                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
764                          const struct rte_flow_action *action,
765                          const struct rte_flow_item *items,
766                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
767                          bool tunnel_decap, struct rte_flow_error *error)
768 {
769         const struct rte_flow_action_set_ttl *conf =
770                 (const struct rte_flow_action_set_ttl *)(action->conf);
771         struct rte_flow_item item;
772         struct rte_flow_item_ipv4 ipv4;
773         struct rte_flow_item_ipv4 ipv4_mask;
774         struct rte_flow_item_ipv6 ipv6;
775         struct rte_flow_item_ipv6 ipv6_mask;
776         struct field_modify_info *field;
777
778         if (!attr->valid)
779                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
780         if (attr->ipv4) {
781                 memset(&ipv4, 0, sizeof(ipv4));
782                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
783                 ipv4.hdr.time_to_live = conf->ttl_value;
784                 ipv4_mask.hdr.time_to_live = 0xFF;
785                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
786                 item.spec = &ipv4;
787                 item.mask = &ipv4_mask;
788                 field = modify_ipv4;
789         } else {
790                 MLX5_ASSERT(attr->ipv6);
791                 memset(&ipv6, 0, sizeof(ipv6));
792                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
793                 ipv6.hdr.hop_limits = conf->ttl_value;
794                 ipv6_mask.hdr.hop_limits = 0xFF;
795                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
796                 item.spec = &ipv6;
797                 item.mask = &ipv6_mask;
798                 field = modify_ipv6;
799         }
800         return flow_dv_convert_modify_action(&item, field, NULL, resource,
801                                              MLX5_MODIFICATION_TYPE_SET, error);
802 }
803
804 /**
805  * Convert modify-header decrement TTL action to DV specification.
806  *
807  * @param[in,out] resource
808  *   Pointer to the modify-header resource.
809  * @param[in] action
810  *   Pointer to action specification.
811  * @param[in] items
812  *   Pointer to rte_flow_item objects list.
813  * @param[in] attr
814  *   Pointer to flow attributes structure.
815  * @param[in] dev_flow
816  *   Pointer to the sub flow.
817  * @param[in] tunnel_decap
818  *   Whether action is after tunnel decapsulation.
819  * @param[out] error
820  *   Pointer to the error structure.
821  *
822  * @return
823  *   0 on success, a negative errno value otherwise and rte_errno is set.
824  */
825 static int
826 flow_dv_convert_action_modify_dec_ttl
827                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
828                          const struct rte_flow_item *items,
829                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
830                          bool tunnel_decap, struct rte_flow_error *error)
831 {
832         struct rte_flow_item item;
833         struct rte_flow_item_ipv4 ipv4;
834         struct rte_flow_item_ipv4 ipv4_mask;
835         struct rte_flow_item_ipv6 ipv6;
836         struct rte_flow_item_ipv6 ipv6_mask;
837         struct field_modify_info *field;
838
839         if (!attr->valid)
840                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
841         if (attr->ipv4) {
842                 memset(&ipv4, 0, sizeof(ipv4));
843                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
844                 ipv4.hdr.time_to_live = 0xFF;
845                 ipv4_mask.hdr.time_to_live = 0xFF;
846                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
847                 item.spec = &ipv4;
848                 item.mask = &ipv4_mask;
849                 field = modify_ipv4;
850         } else {
851                 MLX5_ASSERT(attr->ipv6);
852                 memset(&ipv6, 0, sizeof(ipv6));
853                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
854                 ipv6.hdr.hop_limits = 0xFF;
855                 ipv6_mask.hdr.hop_limits = 0xFF;
856                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
857                 item.spec = &ipv6;
858                 item.mask = &ipv6_mask;
859                 field = modify_ipv6;
860         }
861         return flow_dv_convert_modify_action(&item, field, NULL, resource,
862                                              MLX5_MODIFICATION_TYPE_ADD, error);
863 }
864
865 /**
866  * Convert modify-header increment/decrement TCP Sequence number
867  * to DV specification.
868  *
869  * @param[in,out] resource
870  *   Pointer to the modify-header resource.
871  * @param[in] action
872  *   Pointer to action specification.
873  * @param[out] error
874  *   Pointer to the error structure.
875  *
876  * @return
877  *   0 on success, a negative errno value otherwise and rte_errno is set.
878  */
879 static int
880 flow_dv_convert_action_modify_tcp_seq
881                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
882                          const struct rte_flow_action *action,
883                          struct rte_flow_error *error)
884 {
885         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
886         uint64_t value = rte_be_to_cpu_32(*conf);
887         struct rte_flow_item item;
888         struct rte_flow_item_tcp tcp;
889         struct rte_flow_item_tcp tcp_mask;
890
891         memset(&tcp, 0, sizeof(tcp));
892         memset(&tcp_mask, 0, sizeof(tcp_mask));
893         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
894                 /*
895                  * The HW has no decrement operation, only increment operation.
896                  * To simulate decrement X from Y using increment operation
897                  * we need to add UINT32_MAX X times to Y.
898                  * Each adding of UINT32_MAX decrements Y by 1.
899                  */
900                 value *= UINT32_MAX;
901         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
902         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
903         item.type = RTE_FLOW_ITEM_TYPE_TCP;
904         item.spec = &tcp;
905         item.mask = &tcp_mask;
906         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
907                                              MLX5_MODIFICATION_TYPE_ADD, error);
908 }
909
910 /**
911  * Convert modify-header increment/decrement TCP Acknowledgment number
912  * to DV specification.
913  *
914  * @param[in,out] resource
915  *   Pointer to the modify-header resource.
916  * @param[in] action
917  *   Pointer to action specification.
918  * @param[out] error
919  *   Pointer to the error structure.
920  *
921  * @return
922  *   0 on success, a negative errno value otherwise and rte_errno is set.
923  */
924 static int
925 flow_dv_convert_action_modify_tcp_ack
926                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
927                          const struct rte_flow_action *action,
928                          struct rte_flow_error *error)
929 {
930         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
931         uint64_t value = rte_be_to_cpu_32(*conf);
932         struct rte_flow_item item;
933         struct rte_flow_item_tcp tcp;
934         struct rte_flow_item_tcp tcp_mask;
935
936         memset(&tcp, 0, sizeof(tcp));
937         memset(&tcp_mask, 0, sizeof(tcp_mask));
938         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
939                 /*
940                  * The HW has no decrement operation, only increment operation.
941                  * To simulate decrement X from Y using increment operation
942                  * we need to add UINT32_MAX X times to Y.
943                  * Each adding of UINT32_MAX decrements Y by 1.
944                  */
945                 value *= UINT32_MAX;
946         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
947         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
948         item.type = RTE_FLOW_ITEM_TYPE_TCP;
949         item.spec = &tcp;
950         item.mask = &tcp_mask;
951         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
952                                              MLX5_MODIFICATION_TYPE_ADD, error);
953 }
954
955 static enum mlx5_modification_field reg_to_field[] = {
956         [REG_NON] = MLX5_MODI_OUT_NONE,
957         [REG_A] = MLX5_MODI_META_DATA_REG_A,
958         [REG_B] = MLX5_MODI_META_DATA_REG_B,
959         [REG_C_0] = MLX5_MODI_META_REG_C_0,
960         [REG_C_1] = MLX5_MODI_META_REG_C_1,
961         [REG_C_2] = MLX5_MODI_META_REG_C_2,
962         [REG_C_3] = MLX5_MODI_META_REG_C_3,
963         [REG_C_4] = MLX5_MODI_META_REG_C_4,
964         [REG_C_5] = MLX5_MODI_META_REG_C_5,
965         [REG_C_6] = MLX5_MODI_META_REG_C_6,
966         [REG_C_7] = MLX5_MODI_META_REG_C_7,
967 };
968
969 /**
970  * Convert register set to DV specification.
971  *
972  * @param[in,out] resource
973  *   Pointer to the modify-header resource.
974  * @param[in] action
975  *   Pointer to action specification.
976  * @param[out] error
977  *   Pointer to the error structure.
978  *
979  * @return
980  *   0 on success, a negative errno value otherwise and rte_errno is set.
981  */
982 static int
983 flow_dv_convert_action_set_reg
984                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
985                          const struct rte_flow_action *action,
986                          struct rte_flow_error *error)
987 {
988         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
989         struct mlx5_modification_cmd *actions = resource->actions;
990         uint32_t i = resource->actions_num;
991
992         if (i >= MLX5_MAX_MODIFY_NUM)
993                 return rte_flow_error_set(error, EINVAL,
994                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
995                                           "too many items to modify");
996         MLX5_ASSERT(conf->id != REG_NON);
997         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
998         actions[i] = (struct mlx5_modification_cmd) {
999                 .action_type = MLX5_MODIFICATION_TYPE_SET,
1000                 .field = reg_to_field[conf->id],
1001         };
1002         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1003         actions[i].data1 = rte_cpu_to_be_32(conf->data);
1004         ++i;
1005         resource->actions_num = i;
1006         return 0;
1007 }
1008
1009 /**
1010  * Convert SET_TAG action to DV specification.
1011  *
1012  * @param[in] dev
1013  *   Pointer to the rte_eth_dev structure.
1014  * @param[in,out] resource
1015  *   Pointer to the modify-header resource.
1016  * @param[in] conf
1017  *   Pointer to action specification.
1018  * @param[out] error
1019  *   Pointer to the error structure.
1020  *
1021  * @return
1022  *   0 on success, a negative errno value otherwise and rte_errno is set.
1023  */
1024 static int
1025 flow_dv_convert_action_set_tag
1026                         (struct rte_eth_dev *dev,
1027                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1028                          const struct rte_flow_action_set_tag *conf,
1029                          struct rte_flow_error *error)
1030 {
1031         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1032         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1033         struct rte_flow_item item = {
1034                 .spec = &data,
1035                 .mask = &mask,
1036         };
1037         struct field_modify_info reg_c_x[] = {
1038                 [1] = {0, 0, 0},
1039         };
1040         enum mlx5_modification_field reg_type;
1041         int ret;
1042
1043         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1044         if (ret < 0)
1045                 return ret;
1046         MLX5_ASSERT(ret != REG_NON);
1047         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1048         reg_type = reg_to_field[ret];
1049         MLX5_ASSERT(reg_type > 0);
1050         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1051         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1052                                              MLX5_MODIFICATION_TYPE_SET, error);
1053 }
1054
1055 /**
1056  * Convert internal COPY_REG action to DV specification.
1057  *
1058  * @param[in] dev
1059  *   Pointer to the rte_eth_dev structure.
1060  * @param[in,out] res
1061  *   Pointer to the modify-header resource.
1062  * @param[in] action
1063  *   Pointer to action specification.
1064  * @param[out] error
1065  *   Pointer to the error structure.
1066  *
1067  * @return
1068  *   0 on success, a negative errno value otherwise and rte_errno is set.
1069  */
1070 static int
1071 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1072                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1073                                  const struct rte_flow_action *action,
1074                                  struct rte_flow_error *error)
1075 {
1076         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1077         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1078         struct rte_flow_item item = {
1079                 .spec = NULL,
1080                 .mask = &mask,
1081         };
1082         struct field_modify_info reg_src[] = {
1083                 {4, 0, reg_to_field[conf->src]},
1084                 {0, 0, 0},
1085         };
1086         struct field_modify_info reg_dst = {
1087                 .offset = 0,
1088                 .id = reg_to_field[conf->dst],
1089         };
1090         /* Adjust reg_c[0] usage according to reported mask. */
1091         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1092                 struct mlx5_priv *priv = dev->data->dev_private;
1093                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1094
1095                 MLX5_ASSERT(reg_c0);
1096                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1097                 if (conf->dst == REG_C_0) {
1098                         /* Copy to reg_c[0], within mask only. */
1099                         reg_dst.offset = rte_bsf32(reg_c0);
1100                         /*
1101                          * Mask is ignoring the enianness, because
1102                          * there is no conversion in datapath.
1103                          */
1104 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1105                         /* Copy from destination lower bits to reg_c[0]. */
1106                         mask = reg_c0 >> reg_dst.offset;
1107 #else
1108                         /* Copy from destination upper bits to reg_c[0]. */
1109                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1110                                           rte_fls_u32(reg_c0));
1111 #endif
1112                 } else {
1113                         mask = rte_cpu_to_be_32(reg_c0);
1114 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1115                         /* Copy from reg_c[0] to destination lower bits. */
1116                         reg_dst.offset = 0;
1117 #else
1118                         /* Copy from reg_c[0] to destination upper bits. */
1119                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1120                                          (rte_fls_u32(reg_c0) -
1121                                           rte_bsf32(reg_c0));
1122 #endif
1123                 }
1124         }
1125         return flow_dv_convert_modify_action(&item,
1126                                              reg_src, &reg_dst, res,
1127                                              MLX5_MODIFICATION_TYPE_COPY,
1128                                              error);
1129 }
1130
1131 /**
1132  * Convert MARK action to DV specification. This routine is used
1133  * in extensive metadata only and requires metadata register to be
1134  * handled. In legacy mode hardware tag resource is engaged.
1135  *
1136  * @param[in] dev
1137  *   Pointer to the rte_eth_dev structure.
1138  * @param[in] conf
1139  *   Pointer to MARK action specification.
1140  * @param[in,out] resource
1141  *   Pointer to the modify-header resource.
1142  * @param[out] error
1143  *   Pointer to the error structure.
1144  *
1145  * @return
1146  *   0 on success, a negative errno value otherwise and rte_errno is set.
1147  */
1148 static int
1149 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1150                             const struct rte_flow_action_mark *conf,
1151                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1152                             struct rte_flow_error *error)
1153 {
1154         struct mlx5_priv *priv = dev->data->dev_private;
1155         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1156                                            priv->sh->dv_mark_mask);
1157         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1158         struct rte_flow_item item = {
1159                 .spec = &data,
1160                 .mask = &mask,
1161         };
1162         struct field_modify_info reg_c_x[] = {
1163                 [1] = {0, 0, 0},
1164         };
1165         int reg;
1166
1167         if (!mask)
1168                 return rte_flow_error_set(error, EINVAL,
1169                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1170                                           NULL, "zero mark action mask");
1171         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1172         if (reg < 0)
1173                 return reg;
1174         MLX5_ASSERT(reg > 0);
1175         if (reg == REG_C_0) {
1176                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1177                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1178
1179                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1180                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1181                 mask = rte_cpu_to_be_32(mask << shl_c0);
1182         }
1183         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1184         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1185                                              MLX5_MODIFICATION_TYPE_SET, error);
1186 }
1187
1188 /**
1189  * Get metadata register index for specified steering domain.
1190  *
1191  * @param[in] dev
1192  *   Pointer to the rte_eth_dev structure.
1193  * @param[in] attr
1194  *   Attributes of flow to determine steering domain.
1195  * @param[out] error
1196  *   Pointer to the error structure.
1197  *
1198  * @return
1199  *   positive index on success, a negative errno value otherwise
1200  *   and rte_errno is set.
1201  */
1202 static enum modify_reg
1203 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1204                          const struct rte_flow_attr *attr,
1205                          struct rte_flow_error *error)
1206 {
1207         int reg =
1208                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1209                                           MLX5_METADATA_FDB :
1210                                             attr->egress ?
1211                                             MLX5_METADATA_TX :
1212                                             MLX5_METADATA_RX, 0, error);
1213         if (reg < 0)
1214                 return rte_flow_error_set(error,
1215                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1216                                           NULL, "unavailable "
1217                                           "metadata register");
1218         return reg;
1219 }
1220
1221 /**
1222  * Convert SET_META action to DV specification.
1223  *
1224  * @param[in] dev
1225  *   Pointer to the rte_eth_dev structure.
1226  * @param[in,out] resource
1227  *   Pointer to the modify-header resource.
1228  * @param[in] attr
1229  *   Attributes of flow that includes this item.
1230  * @param[in] conf
1231  *   Pointer to action specification.
1232  * @param[out] error
1233  *   Pointer to the error structure.
1234  *
1235  * @return
1236  *   0 on success, a negative errno value otherwise and rte_errno is set.
1237  */
1238 static int
1239 flow_dv_convert_action_set_meta
1240                         (struct rte_eth_dev *dev,
1241                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1242                          const struct rte_flow_attr *attr,
1243                          const struct rte_flow_action_set_meta *conf,
1244                          struct rte_flow_error *error)
1245 {
1246         uint32_t data = conf->data;
1247         uint32_t mask = conf->mask;
1248         struct rte_flow_item item = {
1249                 .spec = &data,
1250                 .mask = &mask,
1251         };
1252         struct field_modify_info reg_c_x[] = {
1253                 [1] = {0, 0, 0},
1254         };
1255         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1256
1257         if (reg < 0)
1258                 return reg;
1259         /*
1260          * In datapath code there is no endianness
1261          * coversions for perfromance reasons, all
1262          * pattern conversions are done in rte_flow.
1263          */
1264         if (reg == REG_C_0) {
1265                 struct mlx5_priv *priv = dev->data->dev_private;
1266                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1267                 uint32_t shl_c0;
1268
1269                 MLX5_ASSERT(msk_c0);
1270 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1271                 shl_c0 = rte_bsf32(msk_c0);
1272 #else
1273                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1274 #endif
1275                 mask <<= shl_c0;
1276                 data <<= shl_c0;
1277                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1278         }
1279         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1280         /* The routine expects parameters in memory as big-endian ones. */
1281         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1282                                              MLX5_MODIFICATION_TYPE_SET, error);
1283 }
1284
1285 /**
1286  * Convert modify-header set IPv4 DSCP action to DV specification.
1287  *
1288  * @param[in,out] resource
1289  *   Pointer to the modify-header resource.
1290  * @param[in] action
1291  *   Pointer to action specification.
1292  * @param[out] error
1293  *   Pointer to the error structure.
1294  *
1295  * @return
1296  *   0 on success, a negative errno value otherwise and rte_errno is set.
1297  */
1298 static int
1299 flow_dv_convert_action_modify_ipv4_dscp
1300                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1301                          const struct rte_flow_action *action,
1302                          struct rte_flow_error *error)
1303 {
1304         const struct rte_flow_action_set_dscp *conf =
1305                 (const struct rte_flow_action_set_dscp *)(action->conf);
1306         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1307         struct rte_flow_item_ipv4 ipv4;
1308         struct rte_flow_item_ipv4 ipv4_mask;
1309
1310         memset(&ipv4, 0, sizeof(ipv4));
1311         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1312         ipv4.hdr.type_of_service = conf->dscp;
1313         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1314         item.spec = &ipv4;
1315         item.mask = &ipv4_mask;
1316         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1317                                              MLX5_MODIFICATION_TYPE_SET, error);
1318 }
1319
1320 /**
1321  * Convert modify-header set IPv6 DSCP action to DV specification.
1322  *
1323  * @param[in,out] resource
1324  *   Pointer to the modify-header resource.
1325  * @param[in] action
1326  *   Pointer to action specification.
1327  * @param[out] error
1328  *   Pointer to the error structure.
1329  *
1330  * @return
1331  *   0 on success, a negative errno value otherwise and rte_errno is set.
1332  */
1333 static int
1334 flow_dv_convert_action_modify_ipv6_dscp
1335                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1336                          const struct rte_flow_action *action,
1337                          struct rte_flow_error *error)
1338 {
1339         const struct rte_flow_action_set_dscp *conf =
1340                 (const struct rte_flow_action_set_dscp *)(action->conf);
1341         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1342         struct rte_flow_item_ipv6 ipv6;
1343         struct rte_flow_item_ipv6 ipv6_mask;
1344
1345         memset(&ipv6, 0, sizeof(ipv6));
1346         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1347         /*
1348          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1349          * rdma-core only accept the DSCP bits byte aligned start from
1350          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1351          * bits in IPv6 case as rdma-core requires byte aligned value.
1352          */
1353         ipv6.hdr.vtc_flow = conf->dscp;
1354         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1355         item.spec = &ipv6;
1356         item.mask = &ipv6_mask;
1357         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1358                                              MLX5_MODIFICATION_TYPE_SET, error);
1359 }
1360
1361 /**
1362  * Validate MARK item.
1363  *
1364  * @param[in] dev
1365  *   Pointer to the rte_eth_dev structure.
1366  * @param[in] item
1367  *   Item specification.
1368  * @param[in] attr
1369  *   Attributes of flow that includes this item.
1370  * @param[out] error
1371  *   Pointer to error structure.
1372  *
1373  * @return
1374  *   0 on success, a negative errno value otherwise and rte_errno is set.
1375  */
1376 static int
1377 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1378                            const struct rte_flow_item *item,
1379                            const struct rte_flow_attr *attr __rte_unused,
1380                            struct rte_flow_error *error)
1381 {
1382         struct mlx5_priv *priv = dev->data->dev_private;
1383         struct mlx5_dev_config *config = &priv->config;
1384         const struct rte_flow_item_mark *spec = item->spec;
1385         const struct rte_flow_item_mark *mask = item->mask;
1386         const struct rte_flow_item_mark nic_mask = {
1387                 .id = priv->sh->dv_mark_mask,
1388         };
1389         int ret;
1390
1391         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata feature"
1395                                           " isn't enabled");
1396         if (!mlx5_flow_ext_mreg_supported(dev))
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't supported");
1401         if (!nic_mask.id)
1402                 return rte_flow_error_set(error, ENOTSUP,
1403                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1404                                           "extended metadata register"
1405                                           " isn't available");
1406         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1407         if (ret < 0)
1408                 return ret;
1409         if (!spec)
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1412                                           item->spec,
1413                                           "data cannot be empty");
1414         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1415                 return rte_flow_error_set(error, EINVAL,
1416                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1417                                           &spec->id,
1418                                           "mark id exceeds the limit");
1419         if (!mask)
1420                 mask = &nic_mask;
1421         if (!mask->id)
1422                 return rte_flow_error_set(error, EINVAL,
1423                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1424                                         "mask cannot be zero");
1425
1426         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1427                                         (const uint8_t *)&nic_mask,
1428                                         sizeof(struct rte_flow_item_mark),
1429                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1430         if (ret < 0)
1431                 return ret;
1432         return 0;
1433 }
1434
1435 /**
1436  * Validate META item.
1437  *
1438  * @param[in] dev
1439  *   Pointer to the rte_eth_dev structure.
1440  * @param[in] item
1441  *   Item specification.
1442  * @param[in] attr
1443  *   Attributes of flow that includes this item.
1444  * @param[out] error
1445  *   Pointer to error structure.
1446  *
1447  * @return
1448  *   0 on success, a negative errno value otherwise and rte_errno is set.
1449  */
1450 static int
1451 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1452                            const struct rte_flow_item *item,
1453                            const struct rte_flow_attr *attr,
1454                            struct rte_flow_error *error)
1455 {
1456         struct mlx5_priv *priv = dev->data->dev_private;
1457         struct mlx5_dev_config *config = &priv->config;
1458         const struct rte_flow_item_meta *spec = item->spec;
1459         const struct rte_flow_item_meta *mask = item->mask;
1460         struct rte_flow_item_meta nic_mask = {
1461                 .data = UINT32_MAX
1462         };
1463         int reg;
1464         int ret;
1465
1466         if (!spec)
1467                 return rte_flow_error_set(error, EINVAL,
1468                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1469                                           item->spec,
1470                                           "data cannot be empty");
1471         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1472                 if (!mlx5_flow_ext_mreg_supported(dev))
1473                         return rte_flow_error_set(error, ENOTSUP,
1474                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1475                                           "extended metadata register"
1476                                           " isn't supported");
1477                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1478                 if (reg < 0)
1479                         return reg;
1480                 if (reg == REG_B)
1481                         return rte_flow_error_set(error, ENOTSUP,
1482                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1483                                           "match on reg_b "
1484                                           "isn't supported");
1485                 if (reg != REG_A)
1486                         nic_mask.data = priv->sh->dv_meta_mask;
1487         } else if (attr->transfer) {
1488                 return rte_flow_error_set(error, ENOTSUP,
1489                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1490                                         "extended metadata feature "
1491                                         "should be enabled when "
1492                                         "meta item is requested "
1493                                         "with e-switch mode ");
1494         }
1495         if (!mask)
1496                 mask = &rte_flow_item_meta_mask;
1497         if (!mask->data)
1498                 return rte_flow_error_set(error, EINVAL,
1499                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1500                                         "mask cannot be zero");
1501
1502         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1503                                         (const uint8_t *)&nic_mask,
1504                                         sizeof(struct rte_flow_item_meta),
1505                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1506         return ret;
1507 }
1508
1509 /**
1510  * Validate TAG item.
1511  *
1512  * @param[in] dev
1513  *   Pointer to the rte_eth_dev structure.
1514  * @param[in] item
1515  *   Item specification.
1516  * @param[in] attr
1517  *   Attributes of flow that includes this item.
1518  * @param[out] error
1519  *   Pointer to error structure.
1520  *
1521  * @return
1522  *   0 on success, a negative errno value otherwise and rte_errno is set.
1523  */
1524 static int
1525 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1526                           const struct rte_flow_item *item,
1527                           const struct rte_flow_attr *attr __rte_unused,
1528                           struct rte_flow_error *error)
1529 {
1530         const struct rte_flow_item_tag *spec = item->spec;
1531         const struct rte_flow_item_tag *mask = item->mask;
1532         const struct rte_flow_item_tag nic_mask = {
1533                 .data = RTE_BE32(UINT32_MAX),
1534                 .index = 0xff,
1535         };
1536         int ret;
1537
1538         if (!mlx5_flow_ext_mreg_supported(dev))
1539                 return rte_flow_error_set(error, ENOTSUP,
1540                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1541                                           "extensive metadata register"
1542                                           " isn't supported");
1543         if (!spec)
1544                 return rte_flow_error_set(error, EINVAL,
1545                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1546                                           item->spec,
1547                                           "data cannot be empty");
1548         if (!mask)
1549                 mask = &rte_flow_item_tag_mask;
1550         if (!mask->data)
1551                 return rte_flow_error_set(error, EINVAL,
1552                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1553                                         "mask cannot be zero");
1554
1555         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1556                                         (const uint8_t *)&nic_mask,
1557                                         sizeof(struct rte_flow_item_tag),
1558                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1559         if (ret < 0)
1560                 return ret;
1561         if (mask->index != 0xff)
1562                 return rte_flow_error_set(error, EINVAL,
1563                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1564                                           "partial mask for tag index"
1565                                           " is not supported");
1566         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1567         if (ret < 0)
1568                 return ret;
1569         MLX5_ASSERT(ret != REG_NON);
1570         return 0;
1571 }
1572
1573 /**
1574  * Validate vport item.
1575  *
1576  * @param[in] dev
1577  *   Pointer to the rte_eth_dev structure.
1578  * @param[in] item
1579  *   Item specification.
1580  * @param[in] attr
1581  *   Attributes of flow that includes this item.
1582  * @param[in] item_flags
1583  *   Bit-fields that holds the items detected until now.
1584  * @param[out] error
1585  *   Pointer to error structure.
1586  *
1587  * @return
1588  *   0 on success, a negative errno value otherwise and rte_errno is set.
1589  */
1590 static int
1591 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1592                               const struct rte_flow_item *item,
1593                               const struct rte_flow_attr *attr,
1594                               uint64_t item_flags,
1595                               struct rte_flow_error *error)
1596 {
1597         const struct rte_flow_item_port_id *spec = item->spec;
1598         const struct rte_flow_item_port_id *mask = item->mask;
1599         const struct rte_flow_item_port_id switch_mask = {
1600                         .id = 0xffffffff,
1601         };
1602         struct mlx5_priv *esw_priv;
1603         struct mlx5_priv *dev_priv;
1604         int ret;
1605
1606         if (!attr->transfer)
1607                 return rte_flow_error_set(error, EINVAL,
1608                                           RTE_FLOW_ERROR_TYPE_ITEM,
1609                                           NULL,
1610                                           "match on port id is valid only"
1611                                           " when transfer flag is enabled");
1612         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1613                 return rte_flow_error_set(error, ENOTSUP,
1614                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1615                                           "multiple source ports are not"
1616                                           " supported");
1617         if (!mask)
1618                 mask = &switch_mask;
1619         if (mask->id != 0xffffffff)
1620                 return rte_flow_error_set(error, ENOTSUP,
1621                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1622                                            mask,
1623                                            "no support for partial mask on"
1624                                            " \"id\" field");
1625         ret = mlx5_flow_item_acceptable
1626                                 (item, (const uint8_t *)mask,
1627                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1628                                  sizeof(struct rte_flow_item_port_id),
1629                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1630         if (ret)
1631                 return ret;
1632         if (!spec)
1633                 return 0;
1634         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1635         if (!esw_priv)
1636                 return rte_flow_error_set(error, rte_errno,
1637                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1638                                           "failed to obtain E-Switch info for"
1639                                           " port");
1640         dev_priv = mlx5_dev_to_eswitch_info(dev);
1641         if (!dev_priv)
1642                 return rte_flow_error_set(error, rte_errno,
1643                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1644                                           NULL,
1645                                           "failed to obtain E-Switch info");
1646         if (esw_priv->domain_id != dev_priv->domain_id)
1647                 return rte_flow_error_set(error, EINVAL,
1648                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1649                                           "cannot match on a port from a"
1650                                           " different E-Switch");
1651         return 0;
1652 }
1653
1654 /**
1655  * Validate VLAN item.
1656  *
1657  * @param[in] item
1658  *   Item specification.
1659  * @param[in] item_flags
1660  *   Bit-fields that holds the items detected until now.
1661  * @param[in] dev
1662  *   Ethernet device flow is being created on.
1663  * @param[out] error
1664  *   Pointer to error structure.
1665  *
1666  * @return
1667  *   0 on success, a negative errno value otherwise and rte_errno is set.
1668  */
1669 static int
1670 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1671                            uint64_t item_flags,
1672                            struct rte_eth_dev *dev,
1673                            struct rte_flow_error *error)
1674 {
1675         const struct rte_flow_item_vlan *mask = item->mask;
1676         const struct rte_flow_item_vlan nic_mask = {
1677                 .tci = RTE_BE16(UINT16_MAX),
1678                 .inner_type = RTE_BE16(UINT16_MAX),
1679         };
1680         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1681         int ret;
1682         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1683                                         MLX5_FLOW_LAYER_INNER_L4) :
1684                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1685                                         MLX5_FLOW_LAYER_OUTER_L4);
1686         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1687                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1688
1689         if (item_flags & vlanm)
1690                 return rte_flow_error_set(error, EINVAL,
1691                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1692                                           "multiple VLAN layers not supported");
1693         else if ((item_flags & l34m) != 0)
1694                 return rte_flow_error_set(error, EINVAL,
1695                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1696                                           "VLAN cannot follow L3/L4 layer");
1697         if (!mask)
1698                 mask = &rte_flow_item_vlan_mask;
1699         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1700                                         (const uint8_t *)&nic_mask,
1701                                         sizeof(struct rte_flow_item_vlan),
1702                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1703         if (ret)
1704                 return ret;
1705         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1706                 struct mlx5_priv *priv = dev->data->dev_private;
1707
1708                 if (priv->vmwa_context) {
1709                         /*
1710                          * Non-NULL context means we have a virtual machine
1711                          * and SR-IOV enabled, we have to create VLAN interface
1712                          * to make hypervisor to setup E-Switch vport
1713                          * context correctly. We avoid creating the multiple
1714                          * VLAN interfaces, so we cannot support VLAN tag mask.
1715                          */
1716                         return rte_flow_error_set(error, EINVAL,
1717                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1718                                                   item,
1719                                                   "VLAN tag mask is not"
1720                                                   " supported in virtual"
1721                                                   " environment");
1722                 }
1723         }
1724         return 0;
1725 }
1726
1727 /*
1728  * GTP flags are contained in 1 byte of the format:
1729  * -------------------------------------------
1730  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1731  * |-----------------------------------------|
1732  * | value | Version | PT | Res | E | S | PN |
1733  * -------------------------------------------
1734  *
1735  * Matching is supported only for GTP flags E, S, PN.
1736  */
1737 #define MLX5_GTP_FLAGS_MASK     0x07
1738
1739 /**
1740  * Validate GTP item.
1741  *
1742  * @param[in] dev
1743  *   Pointer to the rte_eth_dev structure.
1744  * @param[in] item
1745  *   Item specification.
1746  * @param[in] item_flags
1747  *   Bit-fields that holds the items detected until now.
1748  * @param[out] error
1749  *   Pointer to error structure.
1750  *
1751  * @return
1752  *   0 on success, a negative errno value otherwise and rte_errno is set.
1753  */
1754 static int
1755 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1756                           const struct rte_flow_item *item,
1757                           uint64_t item_flags,
1758                           struct rte_flow_error *error)
1759 {
1760         struct mlx5_priv *priv = dev->data->dev_private;
1761         const struct rte_flow_item_gtp *spec = item->spec;
1762         const struct rte_flow_item_gtp *mask = item->mask;
1763         const struct rte_flow_item_gtp nic_mask = {
1764                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1765                 .msg_type = 0xff,
1766                 .teid = RTE_BE32(0xffffffff),
1767         };
1768
1769         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1770                 return rte_flow_error_set(error, ENOTSUP,
1771                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1772                                           "GTP support is not enabled");
1773         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1774                 return rte_flow_error_set(error, ENOTSUP,
1775                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1776                                           "multiple tunnel layers not"
1777                                           " supported");
1778         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1779                 return rte_flow_error_set(error, EINVAL,
1780                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1781                                           "no outer UDP layer found");
1782         if (!mask)
1783                 mask = &rte_flow_item_gtp_mask;
1784         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1785                 return rte_flow_error_set(error, ENOTSUP,
1786                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1787                                           "Match is supported for GTP"
1788                                           " flags only");
1789         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1790                                          (const uint8_t *)&nic_mask,
1791                                          sizeof(struct rte_flow_item_gtp),
1792                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1793 }
1794
1795 /**
1796  * Validate IPV4 item.
1797  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1798  * add specific validation of fragment_offset field,
1799  *
1800  * @param[in] item
1801  *   Item specification.
1802  * @param[in] item_flags
1803  *   Bit-fields that holds the items detected until now.
1804  * @param[out] error
1805  *   Pointer to error structure.
1806  *
1807  * @return
1808  *   0 on success, a negative errno value otherwise and rte_errno is set.
1809  */
1810 static int
1811 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1812                            uint64_t item_flags,
1813                            uint64_t last_item,
1814                            uint16_t ether_type,
1815                            struct rte_flow_error *error)
1816 {
1817         int ret;
1818         const struct rte_flow_item_ipv4 *spec = item->spec;
1819         const struct rte_flow_item_ipv4 *last = item->last;
1820         const struct rte_flow_item_ipv4 *mask = item->mask;
1821         rte_be16_t fragment_offset_spec = 0;
1822         rte_be16_t fragment_offset_last = 0;
1823         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1824                 .hdr = {
1825                         .src_addr = RTE_BE32(0xffffffff),
1826                         .dst_addr = RTE_BE32(0xffffffff),
1827                         .type_of_service = 0xff,
1828                         .fragment_offset = RTE_BE16(0xffff),
1829                         .next_proto_id = 0xff,
1830                         .time_to_live = 0xff,
1831                 },
1832         };
1833
1834         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1835                                            ether_type, &nic_ipv4_mask,
1836                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1837         if (ret < 0)
1838                 return ret;
1839         if (spec && mask)
1840                 fragment_offset_spec = spec->hdr.fragment_offset &
1841                                        mask->hdr.fragment_offset;
1842         if (!fragment_offset_spec)
1843                 return 0;
1844         /*
1845          * spec and mask are valid, enforce using full mask to make sure the
1846          * complete value is used correctly.
1847          */
1848         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1849                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1850                 return rte_flow_error_set(error, EINVAL,
1851                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1852                                           item, "must use full mask for"
1853                                           " fragment_offset");
1854         /*
1855          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1856          * indicating this is 1st fragment of fragmented packet.
1857          * This is not yet supported in MLX5, return appropriate error message.
1858          */
1859         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1860                 return rte_flow_error_set(error, ENOTSUP,
1861                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1862                                           "match on first fragment not "
1863                                           "supported");
1864         if (fragment_offset_spec && !last)
1865                 return rte_flow_error_set(error, ENOTSUP,
1866                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1867                                           "specified value not supported");
1868         /* spec and last are valid, validate the specified range. */
1869         fragment_offset_last = last->hdr.fragment_offset &
1870                                mask->hdr.fragment_offset;
1871         /*
1872          * Match on fragment_offset spec 0x2001 and last 0x3fff
1873          * means MF is 1 and frag-offset is > 0.
1874          * This packet is fragment 2nd and onward, excluding last.
1875          * This is not yet supported in MLX5, return appropriate
1876          * error message.
1877          */
1878         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1879             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1880                 return rte_flow_error_set(error, ENOTSUP,
1881                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1882                                           last, "match on following "
1883                                           "fragments not supported");
1884         /*
1885          * Match on fragment_offset spec 0x0001 and last 0x1fff
1886          * means MF is 0 and frag-offset is > 0.
1887          * This packet is last fragment of fragmented packet.
1888          * This is not yet supported in MLX5, return appropriate
1889          * error message.
1890          */
1891         if (fragment_offset_spec == RTE_BE16(1) &&
1892             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1893                 return rte_flow_error_set(error, ENOTSUP,
1894                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1895                                           last, "match on last "
1896                                           "fragment not supported");
1897         /*
1898          * Match on fragment_offset spec 0x0001 and last 0x3fff
1899          * means MF and/or frag-offset is not 0.
1900          * This is a fragmented packet.
1901          * Other range values are invalid and rejected.
1902          */
1903         if (!(fragment_offset_spec == RTE_BE16(1) &&
1904               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1905                 return rte_flow_error_set(error, ENOTSUP,
1906                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1907                                           "specified range not supported");
1908         return 0;
1909 }
1910
1911 /**
1912  * Validate IPV6 fragment extension item.
1913  *
1914  * @param[in] item
1915  *   Item specification.
1916  * @param[in] item_flags
1917  *   Bit-fields that holds the items detected until now.
1918  * @param[out] error
1919  *   Pointer to error structure.
1920  *
1921  * @return
1922  *   0 on success, a negative errno value otherwise and rte_errno is set.
1923  */
1924 static int
1925 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1926                                     uint64_t item_flags,
1927                                     struct rte_flow_error *error)
1928 {
1929         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1930         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1931         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1932         rte_be16_t frag_data_spec = 0;
1933         rte_be16_t frag_data_last = 0;
1934         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1935         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1936                                       MLX5_FLOW_LAYER_OUTER_L4;
1937         int ret = 0;
1938         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1939                 .hdr = {
1940                         .next_header = 0xff,
1941                         .frag_data = RTE_BE16(0xffff),
1942                 },
1943         };
1944
1945         if (item_flags & l4m)
1946                 return rte_flow_error_set(error, EINVAL,
1947                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1948                                           "ipv6 fragment extension item cannot "
1949                                           "follow L4 item.");
1950         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1951             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1952                 return rte_flow_error_set(error, EINVAL,
1953                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1954                                           "ipv6 fragment extension item must "
1955                                           "follow ipv6 item");
1956         if (spec && mask)
1957                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1958         if (!frag_data_spec)
1959                 return 0;
1960         /*
1961          * spec and mask are valid, enforce using full mask to make sure the
1962          * complete value is used correctly.
1963          */
1964         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1965                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1966                 return rte_flow_error_set(error, EINVAL,
1967                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1968                                           item, "must use full mask for"
1969                                           " frag_data");
1970         /*
1971          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1972          * This is 1st fragment of fragmented packet.
1973          */
1974         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1975                 return rte_flow_error_set(error, ENOTSUP,
1976                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1977                                           "match on first fragment not "
1978                                           "supported");
1979         if (frag_data_spec && !last)
1980                 return rte_flow_error_set(error, EINVAL,
1981                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1982                                           "specified value not supported");
1983         ret = mlx5_flow_item_acceptable
1984                                 (item, (const uint8_t *)mask,
1985                                  (const uint8_t *)&nic_mask,
1986                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
1987                                  MLX5_ITEM_RANGE_ACCEPTED, error);
1988         if (ret)
1989                 return ret;
1990         /* spec and last are valid, validate the specified range. */
1991         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1992         /*
1993          * Match on frag_data spec 0x0009 and last 0xfff9
1994          * means M is 1 and frag-offset is > 0.
1995          * This packet is fragment 2nd and onward, excluding last.
1996          * This is not yet supported in MLX5, return appropriate
1997          * error message.
1998          */
1999         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2000                                        RTE_IPV6_EHDR_MF_MASK) &&
2001             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2002                 return rte_flow_error_set(error, ENOTSUP,
2003                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2004                                           last, "match on following "
2005                                           "fragments not supported");
2006         /*
2007          * Match on frag_data spec 0x0008 and last 0xfff8
2008          * means M is 0 and frag-offset is > 0.
2009          * This packet is last fragment of fragmented packet.
2010          * This is not yet supported in MLX5, return appropriate
2011          * error message.
2012          */
2013         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2014             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2015                 return rte_flow_error_set(error, ENOTSUP,
2016                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2017                                           last, "match on last "
2018                                           "fragment not supported");
2019         /* Other range values are invalid and rejected. */
2020         return rte_flow_error_set(error, EINVAL,
2021                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2022                                   "specified range not supported");
2023 }
2024
2025 /**
2026  * Validate the pop VLAN action.
2027  *
2028  * @param[in] dev
2029  *   Pointer to the rte_eth_dev structure.
2030  * @param[in] action_flags
2031  *   Holds the actions detected until now.
2032  * @param[in] action
2033  *   Pointer to the pop vlan action.
2034  * @param[in] item_flags
2035  *   The items found in this flow rule.
2036  * @param[in] attr
2037  *   Pointer to flow attributes.
2038  * @param[out] error
2039  *   Pointer to error structure.
2040  *
2041  * @return
2042  *   0 on success, a negative errno value otherwise and rte_errno is set.
2043  */
2044 static int
2045 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2046                                  uint64_t action_flags,
2047                                  const struct rte_flow_action *action,
2048                                  uint64_t item_flags,
2049                                  const struct rte_flow_attr *attr,
2050                                  struct rte_flow_error *error)
2051 {
2052         const struct mlx5_priv *priv = dev->data->dev_private;
2053
2054         (void)action;
2055         (void)attr;
2056         if (!priv->sh->pop_vlan_action)
2057                 return rte_flow_error_set(error, ENOTSUP,
2058                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2059                                           NULL,
2060                                           "pop vlan action is not supported");
2061         if (attr->egress)
2062                 return rte_flow_error_set(error, ENOTSUP,
2063                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2064                                           NULL,
2065                                           "pop vlan action not supported for "
2066                                           "egress");
2067         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2068                 return rte_flow_error_set(error, ENOTSUP,
2069                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2070                                           "no support for multiple VLAN "
2071                                           "actions");
2072         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2073         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2074             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2075                 return rte_flow_error_set(error, ENOTSUP,
2076                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2077                                           NULL,
2078                                           "cannot pop vlan after decap without "
2079                                           "match on inner vlan in the flow");
2080         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2081         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2082             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2083                 return rte_flow_error_set(error, ENOTSUP,
2084                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2085                                           NULL,
2086                                           "cannot pop vlan without a "
2087                                           "match on (outer) vlan in the flow");
2088         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2089                 return rte_flow_error_set(error, EINVAL,
2090                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2091                                           "wrong action order, port_id should "
2092                                           "be after pop VLAN action");
2093         if (!attr->transfer && priv->representor)
2094                 return rte_flow_error_set(error, ENOTSUP,
2095                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2096                                           "pop vlan action for VF representor "
2097                                           "not supported on NIC table");
2098         return 0;
2099 }
2100
2101 /**
2102  * Get VLAN default info from vlan match info.
2103  *
2104  * @param[in] items
2105  *   the list of item specifications.
2106  * @param[out] vlan
2107  *   pointer VLAN info to fill to.
2108  *
2109  * @return
2110  *   0 on success, a negative errno value otherwise and rte_errno is set.
2111  */
2112 static void
2113 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2114                                   struct rte_vlan_hdr *vlan)
2115 {
2116         const struct rte_flow_item_vlan nic_mask = {
2117                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2118                                 MLX5DV_FLOW_VLAN_VID_MASK),
2119                 .inner_type = RTE_BE16(0xffff),
2120         };
2121
2122         if (items == NULL)
2123                 return;
2124         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2125                 int type = items->type;
2126
2127                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2128                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2129                         break;
2130         }
2131         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2132                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2133                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2134
2135                 /* If VLAN item in pattern doesn't contain data, return here. */
2136                 if (!vlan_v)
2137                         return;
2138                 if (!vlan_m)
2139                         vlan_m = &nic_mask;
2140                 /* Only full match values are accepted */
2141                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2142                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2143                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2144                         vlan->vlan_tci |=
2145                                 rte_be_to_cpu_16(vlan_v->tci &
2146                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2147                 }
2148                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2149                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2150                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2151                         vlan->vlan_tci |=
2152                                 rte_be_to_cpu_16(vlan_v->tci &
2153                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2154                 }
2155                 if (vlan_m->inner_type == nic_mask.inner_type)
2156                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2157                                                            vlan_m->inner_type);
2158         }
2159 }
2160
2161 /**
2162  * Validate the push VLAN action.
2163  *
2164  * @param[in] dev
2165  *   Pointer to the rte_eth_dev structure.
2166  * @param[in] action_flags
2167  *   Holds the actions detected until now.
2168  * @param[in] item_flags
2169  *   The items found in this flow rule.
2170  * @param[in] action
2171  *   Pointer to the action structure.
2172  * @param[in] attr
2173  *   Pointer to flow attributes
2174  * @param[out] error
2175  *   Pointer to error structure.
2176  *
2177  * @return
2178  *   0 on success, a negative errno value otherwise and rte_errno is set.
2179  */
2180 static int
2181 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2182                                   uint64_t action_flags,
2183                                   const struct rte_flow_item_vlan *vlan_m,
2184                                   const struct rte_flow_action *action,
2185                                   const struct rte_flow_attr *attr,
2186                                   struct rte_flow_error *error)
2187 {
2188         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2189         const struct mlx5_priv *priv = dev->data->dev_private;
2190
2191         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2192             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2193                 return rte_flow_error_set(error, EINVAL,
2194                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2195                                           "invalid vlan ethertype");
2196         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2197                 return rte_flow_error_set(error, EINVAL,
2198                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2199                                           "wrong action order, port_id should "
2200                                           "be after push VLAN");
2201         if (!attr->transfer && priv->representor)
2202                 return rte_flow_error_set(error, ENOTSUP,
2203                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2204                                           "push vlan action for VF representor "
2205                                           "not supported on NIC table");
2206         if (vlan_m &&
2207             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2208             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2209                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2210             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2211             !(mlx5_flow_find_action
2212                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2213                 return rte_flow_error_set(error, EINVAL,
2214                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2215                                           "not full match mask on VLAN PCP and "
2216                                           "there is no of_set_vlan_pcp action, "
2217                                           "push VLAN action cannot figure out "
2218                                           "PCP value");
2219         if (vlan_m &&
2220             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2221             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2222                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2223             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2224             !(mlx5_flow_find_action
2225                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2226                 return rte_flow_error_set(error, EINVAL,
2227                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2228                                           "not full match mask on VLAN VID and "
2229                                           "there is no of_set_vlan_vid action, "
2230                                           "push VLAN action cannot figure out "
2231                                           "VID value");
2232         (void)attr;
2233         return 0;
2234 }
2235
2236 /**
2237  * Validate the set VLAN PCP.
2238  *
2239  * @param[in] action_flags
2240  *   Holds the actions detected until now.
2241  * @param[in] actions
2242  *   Pointer to the list of actions remaining in the flow rule.
2243  * @param[out] error
2244  *   Pointer to error structure.
2245  *
2246  * @return
2247  *   0 on success, a negative errno value otherwise and rte_errno is set.
2248  */
2249 static int
2250 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2251                                      const struct rte_flow_action actions[],
2252                                      struct rte_flow_error *error)
2253 {
2254         const struct rte_flow_action *action = actions;
2255         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2256
2257         if (conf->vlan_pcp > 7)
2258                 return rte_flow_error_set(error, EINVAL,
2259                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2260                                           "VLAN PCP value is too big");
2261         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2262                 return rte_flow_error_set(error, ENOTSUP,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "set VLAN PCP action must follow "
2265                                           "the push VLAN action");
2266         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2267                 return rte_flow_error_set(error, ENOTSUP,
2268                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2269                                           "Multiple VLAN PCP modification are "
2270                                           "not supported");
2271         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2272                 return rte_flow_error_set(error, EINVAL,
2273                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2274                                           "wrong action order, port_id should "
2275                                           "be after set VLAN PCP");
2276         return 0;
2277 }
2278
2279 /**
2280  * Validate the set VLAN VID.
2281  *
2282  * @param[in] item_flags
2283  *   Holds the items detected in this rule.
2284  * @param[in] action_flags
2285  *   Holds the actions detected until now.
2286  * @param[in] actions
2287  *   Pointer to the list of actions remaining in the flow rule.
2288  * @param[out] error
2289  *   Pointer to error structure.
2290  *
2291  * @return
2292  *   0 on success, a negative errno value otherwise and rte_errno is set.
2293  */
2294 static int
2295 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2296                                      uint64_t action_flags,
2297                                      const struct rte_flow_action actions[],
2298                                      struct rte_flow_error *error)
2299 {
2300         const struct rte_flow_action *action = actions;
2301         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2302
2303         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2304                 return rte_flow_error_set(error, EINVAL,
2305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2306                                           "VLAN VID value is too big");
2307         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2308             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2309                 return rte_flow_error_set(error, ENOTSUP,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2311                                           "set VLAN VID action must follow push"
2312                                           " VLAN action or match on VLAN item");
2313         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2314                 return rte_flow_error_set(error, ENOTSUP,
2315                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2316                                           "Multiple VLAN VID modifications are "
2317                                           "not supported");
2318         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2319                 return rte_flow_error_set(error, EINVAL,
2320                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2321                                           "wrong action order, port_id should "
2322                                           "be after set VLAN VID");
2323         return 0;
2324 }
2325
2326 /*
2327  * Validate the FLAG action.
2328  *
2329  * @param[in] dev
2330  *   Pointer to the rte_eth_dev structure.
2331  * @param[in] action_flags
2332  *   Holds the actions detected until now.
2333  * @param[in] attr
2334  *   Pointer to flow attributes
2335  * @param[out] error
2336  *   Pointer to error structure.
2337  *
2338  * @return
2339  *   0 on success, a negative errno value otherwise and rte_errno is set.
2340  */
2341 static int
2342 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2343                              uint64_t action_flags,
2344                              const struct rte_flow_attr *attr,
2345                              struct rte_flow_error *error)
2346 {
2347         struct mlx5_priv *priv = dev->data->dev_private;
2348         struct mlx5_dev_config *config = &priv->config;
2349         int ret;
2350
2351         /* Fall back if no extended metadata register support. */
2352         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2353                 return mlx5_flow_validate_action_flag(action_flags, attr,
2354                                                       error);
2355         /* Extensive metadata mode requires registers. */
2356         if (!mlx5_flow_ext_mreg_supported(dev))
2357                 return rte_flow_error_set(error, ENOTSUP,
2358                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2359                                           "no metadata registers "
2360                                           "to support flag action");
2361         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2362                 return rte_flow_error_set(error, ENOTSUP,
2363                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2364                                           "extended metadata register"
2365                                           " isn't available");
2366         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2367         if (ret < 0)
2368                 return ret;
2369         MLX5_ASSERT(ret > 0);
2370         if (action_flags & MLX5_FLOW_ACTION_MARK)
2371                 return rte_flow_error_set(error, EINVAL,
2372                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2373                                           "can't mark and flag in same flow");
2374         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2375                 return rte_flow_error_set(error, EINVAL,
2376                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2377                                           "can't have 2 flag"
2378                                           " actions in same flow");
2379         return 0;
2380 }
2381
2382 /**
2383  * Validate MARK action.
2384  *
2385  * @param[in] dev
2386  *   Pointer to the rte_eth_dev structure.
2387  * @param[in] action
2388  *   Pointer to action.
2389  * @param[in] action_flags
2390  *   Holds the actions detected until now.
2391  * @param[in] attr
2392  *   Pointer to flow attributes
2393  * @param[out] error
2394  *   Pointer to error structure.
2395  *
2396  * @return
2397  *   0 on success, a negative errno value otherwise and rte_errno is set.
2398  */
2399 static int
2400 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2401                              const struct rte_flow_action *action,
2402                              uint64_t action_flags,
2403                              const struct rte_flow_attr *attr,
2404                              struct rte_flow_error *error)
2405 {
2406         struct mlx5_priv *priv = dev->data->dev_private;
2407         struct mlx5_dev_config *config = &priv->config;
2408         const struct rte_flow_action_mark *mark = action->conf;
2409         int ret;
2410
2411         /* Fall back if no extended metadata register support. */
2412         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2413                 return mlx5_flow_validate_action_mark(action, action_flags,
2414                                                       attr, error);
2415         /* Extensive metadata mode requires registers. */
2416         if (!mlx5_flow_ext_mreg_supported(dev))
2417                 return rte_flow_error_set(error, ENOTSUP,
2418                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2419                                           "no metadata registers "
2420                                           "to support mark action");
2421         if (!priv->sh->dv_mark_mask)
2422                 return rte_flow_error_set(error, ENOTSUP,
2423                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2424                                           "extended metadata register"
2425                                           " isn't available");
2426         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2427         if (ret < 0)
2428                 return ret;
2429         MLX5_ASSERT(ret > 0);
2430         if (!mark)
2431                 return rte_flow_error_set(error, EINVAL,
2432                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2433                                           "configuration cannot be null");
2434         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2435                 return rte_flow_error_set(error, EINVAL,
2436                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2437                                           &mark->id,
2438                                           "mark id exceeds the limit");
2439         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2440                 return rte_flow_error_set(error, EINVAL,
2441                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2442                                           "can't flag and mark in same flow");
2443         if (action_flags & MLX5_FLOW_ACTION_MARK)
2444                 return rte_flow_error_set(error, EINVAL,
2445                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2446                                           "can't have 2 mark actions in same"
2447                                           " flow");
2448         return 0;
2449 }
2450
2451 /**
2452  * Validate SET_META action.
2453  *
2454  * @param[in] dev
2455  *   Pointer to the rte_eth_dev structure.
2456  * @param[in] action
2457  *   Pointer to the action structure.
2458  * @param[in] action_flags
2459  *   Holds the actions detected until now.
2460  * @param[in] attr
2461  *   Pointer to flow attributes
2462  * @param[out] error
2463  *   Pointer to error structure.
2464  *
2465  * @return
2466  *   0 on success, a negative errno value otherwise and rte_errno is set.
2467  */
2468 static int
2469 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2470                                  const struct rte_flow_action *action,
2471                                  uint64_t action_flags __rte_unused,
2472                                  const struct rte_flow_attr *attr,
2473                                  struct rte_flow_error *error)
2474 {
2475         const struct rte_flow_action_set_meta *conf;
2476         uint32_t nic_mask = UINT32_MAX;
2477         int reg;
2478
2479         if (!mlx5_flow_ext_mreg_supported(dev))
2480                 return rte_flow_error_set(error, ENOTSUP,
2481                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2482                                           "extended metadata register"
2483                                           " isn't supported");
2484         reg = flow_dv_get_metadata_reg(dev, attr, error);
2485         if (reg < 0)
2486                 return reg;
2487         if (reg != REG_A && reg != REG_B) {
2488                 struct mlx5_priv *priv = dev->data->dev_private;
2489
2490                 nic_mask = priv->sh->dv_meta_mask;
2491         }
2492         if (!(action->conf))
2493                 return rte_flow_error_set(error, EINVAL,
2494                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2495                                           "configuration cannot be null");
2496         conf = (const struct rte_flow_action_set_meta *)action->conf;
2497         if (!conf->mask)
2498                 return rte_flow_error_set(error, EINVAL,
2499                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2500                                           "zero mask doesn't have any effect");
2501         if (conf->mask & ~nic_mask)
2502                 return rte_flow_error_set(error, EINVAL,
2503                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2504                                           "meta data must be within reg C0");
2505         return 0;
2506 }
2507
2508 /**
2509  * Validate SET_TAG action.
2510  *
2511  * @param[in] dev
2512  *   Pointer to the rte_eth_dev structure.
2513  * @param[in] action
2514  *   Pointer to the action structure.
2515  * @param[in] action_flags
2516  *   Holds the actions detected until now.
2517  * @param[in] attr
2518  *   Pointer to flow attributes
2519  * @param[out] error
2520  *   Pointer to error structure.
2521  *
2522  * @return
2523  *   0 on success, a negative errno value otherwise and rte_errno is set.
2524  */
2525 static int
2526 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2527                                 const struct rte_flow_action *action,
2528                                 uint64_t action_flags,
2529                                 const struct rte_flow_attr *attr,
2530                                 struct rte_flow_error *error)
2531 {
2532         const struct rte_flow_action_set_tag *conf;
2533         const uint64_t terminal_action_flags =
2534                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2535                 MLX5_FLOW_ACTION_RSS;
2536         int ret;
2537
2538         if (!mlx5_flow_ext_mreg_supported(dev))
2539                 return rte_flow_error_set(error, ENOTSUP,
2540                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2541                                           "extensive metadata register"
2542                                           " isn't supported");
2543         if (!(action->conf))
2544                 return rte_flow_error_set(error, EINVAL,
2545                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2546                                           "configuration cannot be null");
2547         conf = (const struct rte_flow_action_set_tag *)action->conf;
2548         if (!conf->mask)
2549                 return rte_flow_error_set(error, EINVAL,
2550                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2551                                           "zero mask doesn't have any effect");
2552         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2553         if (ret < 0)
2554                 return ret;
2555         if (!attr->transfer && attr->ingress &&
2556             (action_flags & terminal_action_flags))
2557                 return rte_flow_error_set(error, EINVAL,
2558                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2559                                           "set_tag has no effect"
2560                                           " with terminal actions");
2561         return 0;
2562 }
2563
2564 /**
2565  * Validate count action.
2566  *
2567  * @param[in] dev
2568  *   Pointer to rte_eth_dev structure.
2569  * @param[out] error
2570  *   Pointer to error structure.
2571  *
2572  * @return
2573  *   0 on success, a negative errno value otherwise and rte_errno is set.
2574  */
2575 static int
2576 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2577                               struct rte_flow_error *error)
2578 {
2579         struct mlx5_priv *priv = dev->data->dev_private;
2580
2581         if (!priv->config.devx)
2582                 goto notsup_err;
2583 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2584         return 0;
2585 #endif
2586 notsup_err:
2587         return rte_flow_error_set
2588                       (error, ENOTSUP,
2589                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2590                        NULL,
2591                        "count action not supported");
2592 }
2593
2594 /**
2595  * Validate the L2 encap action.
2596  *
2597  * @param[in] dev
2598  *   Pointer to the rte_eth_dev structure.
2599  * @param[in] action_flags
2600  *   Holds the actions detected until now.
2601  * @param[in] action
2602  *   Pointer to the action structure.
2603  * @param[in] attr
2604  *   Pointer to flow attributes.
2605  * @param[out] error
2606  *   Pointer to error structure.
2607  *
2608  * @return
2609  *   0 on success, a negative errno value otherwise and rte_errno is set.
2610  */
2611 static int
2612 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2613                                  uint64_t action_flags,
2614                                  const struct rte_flow_action *action,
2615                                  const struct rte_flow_attr *attr,
2616                                  struct rte_flow_error *error)
2617 {
2618         const struct mlx5_priv *priv = dev->data->dev_private;
2619
2620         if (!(action->conf))
2621                 return rte_flow_error_set(error, EINVAL,
2622                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2623                                           "configuration cannot be null");
2624         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2625                 return rte_flow_error_set(error, EINVAL,
2626                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2627                                           "can only have a single encap action "
2628                                           "in a flow");
2629         if (!attr->transfer && priv->representor)
2630                 return rte_flow_error_set(error, ENOTSUP,
2631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2632                                           "encap action for VF representor "
2633                                           "not supported on NIC table");
2634         return 0;
2635 }
2636
2637 /**
2638  * Validate a decap action.
2639  *
2640  * @param[in] dev
2641  *   Pointer to the rte_eth_dev structure.
2642  * @param[in] action_flags
2643  *   Holds the actions detected until now.
2644  * @param[in] attr
2645  *   Pointer to flow attributes
2646  * @param[out] error
2647  *   Pointer to error structure.
2648  *
2649  * @return
2650  *   0 on success, a negative errno value otherwise and rte_errno is set.
2651  */
2652 static int
2653 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2654                               uint64_t action_flags,
2655                               const struct rte_flow_attr *attr,
2656                               struct rte_flow_error *error)
2657 {
2658         const struct mlx5_priv *priv = dev->data->dev_private;
2659
2660         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2661             !priv->config.decap_en)
2662                 return rte_flow_error_set(error, ENOTSUP,
2663                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2664                                           "decap is not enabled");
2665         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2666                 return rte_flow_error_set(error, ENOTSUP,
2667                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2668                                           action_flags &
2669                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2670                                           "have a single decap action" : "decap "
2671                                           "after encap is not supported");
2672         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2673                 return rte_flow_error_set(error, EINVAL,
2674                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2675                                           "can't have decap action after"
2676                                           " modify action");
2677         if (attr->egress)
2678                 return rte_flow_error_set(error, ENOTSUP,
2679                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2680                                           NULL,
2681                                           "decap action not supported for "
2682                                           "egress");
2683         if (!attr->transfer && priv->representor)
2684                 return rte_flow_error_set(error, ENOTSUP,
2685                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2686                                           "decap action for VF representor "
2687                                           "not supported on NIC table");
2688         return 0;
2689 }
2690
2691 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2692
2693 /**
2694  * Validate the raw encap and decap actions.
2695  *
2696  * @param[in] dev
2697  *   Pointer to the rte_eth_dev structure.
2698  * @param[in] decap
2699  *   Pointer to the decap action.
2700  * @param[in] encap
2701  *   Pointer to the encap action.
2702  * @param[in] attr
2703  *   Pointer to flow attributes
2704  * @param[in/out] action_flags
2705  *   Holds the actions detected until now.
2706  * @param[out] actions_n
2707  *   pointer to the number of actions counter.
2708  * @param[out] error
2709  *   Pointer to error structure.
2710  *
2711  * @return
2712  *   0 on success, a negative errno value otherwise and rte_errno is set.
2713  */
2714 static int
2715 flow_dv_validate_action_raw_encap_decap
2716         (struct rte_eth_dev *dev,
2717          const struct rte_flow_action_raw_decap *decap,
2718          const struct rte_flow_action_raw_encap *encap,
2719          const struct rte_flow_attr *attr, uint64_t *action_flags,
2720          int *actions_n, struct rte_flow_error *error)
2721 {
2722         const struct mlx5_priv *priv = dev->data->dev_private;
2723         int ret;
2724
2725         if (encap && (!encap->size || !encap->data))
2726                 return rte_flow_error_set(error, EINVAL,
2727                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2728                                           "raw encap data cannot be empty");
2729         if (decap && encap) {
2730                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2731                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2732                         /* L3 encap. */
2733                         decap = NULL;
2734                 else if (encap->size <=
2735                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2736                            decap->size >
2737                            MLX5_ENCAPSULATION_DECISION_SIZE)
2738                         /* L3 decap. */
2739                         encap = NULL;
2740                 else if (encap->size >
2741                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2742                            decap->size >
2743                            MLX5_ENCAPSULATION_DECISION_SIZE)
2744                         /* 2 L2 actions: encap and decap. */
2745                         ;
2746                 else
2747                         return rte_flow_error_set(error,
2748                                 ENOTSUP,
2749                                 RTE_FLOW_ERROR_TYPE_ACTION,
2750                                 NULL, "unsupported too small "
2751                                 "raw decap and too small raw "
2752                                 "encap combination");
2753         }
2754         if (decap) {
2755                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2756                                                     error);
2757                 if (ret < 0)
2758                         return ret;
2759                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2760                 ++(*actions_n);
2761         }
2762         if (encap) {
2763                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2764                         return rte_flow_error_set(error, ENOTSUP,
2765                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2766                                                   NULL,
2767                                                   "small raw encap size");
2768                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2769                         return rte_flow_error_set(error, EINVAL,
2770                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2771                                                   NULL,
2772                                                   "more than one encap action");
2773                 if (!attr->transfer && priv->representor)
2774                         return rte_flow_error_set
2775                                         (error, ENOTSUP,
2776                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2777                                          "encap action for VF representor "
2778                                          "not supported on NIC table");
2779                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2780                 ++(*actions_n);
2781         }
2782         return 0;
2783 }
2784
2785 /**
2786  * Match encap_decap resource.
2787  *
2788  * @param entry
2789  *   Pointer to exist resource entry object.
2790  * @param ctx
2791  *   Pointer to new encap_decap resource.
2792  *
2793  * @return
2794  *   0 on matching, -1 otherwise.
2795  */
2796 static int
2797 flow_dv_encap_decap_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
2798 {
2799         struct mlx5_flow_dv_encap_decap_resource *resource;
2800         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2801
2802         resource = (struct mlx5_flow_dv_encap_decap_resource *)ctx;
2803         cache_resource = container_of(entry,
2804                                       struct mlx5_flow_dv_encap_decap_resource,
2805                                       entry);
2806         if (resource->entry.key == cache_resource->entry.key &&
2807             resource->reformat_type == cache_resource->reformat_type &&
2808             resource->ft_type == cache_resource->ft_type &&
2809             resource->flags == cache_resource->flags &&
2810             resource->size == cache_resource->size &&
2811             !memcmp((const void *)resource->buf,
2812                     (const void *)cache_resource->buf,
2813                     resource->size))
2814                 return 0;
2815         return -1;
2816 }
2817
2818 /**
2819  * Find existing encap/decap resource or create and register a new one.
2820  *
2821  * @param[in, out] dev
2822  *   Pointer to rte_eth_dev structure.
2823  * @param[in, out] resource
2824  *   Pointer to encap/decap resource.
2825  * @parm[in, out] dev_flow
2826  *   Pointer to the dev_flow.
2827  * @param[out] error
2828  *   pointer to error structure.
2829  *
2830  * @return
2831  *   0 on success otherwise -errno and errno is set.
2832  */
2833 static int
2834 flow_dv_encap_decap_resource_register
2835                         (struct rte_eth_dev *dev,
2836                          struct mlx5_flow_dv_encap_decap_resource *resource,
2837                          struct mlx5_flow *dev_flow,
2838                          struct rte_flow_error *error)
2839 {
2840         struct mlx5_priv *priv = dev->data->dev_private;
2841         struct mlx5_dev_ctx_shared *sh = priv->sh;
2842         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2843         struct mlx5dv_dr_domain *domain;
2844         struct mlx5_hlist_entry *entry;
2845         union mlx5_flow_encap_decap_key encap_decap_key = {
2846                 {
2847                         .ft_type = resource->ft_type,
2848                         .refmt_type = resource->reformat_type,
2849                         .buf_size = resource->size,
2850                         .table_level = !!dev_flow->dv.group,
2851                         .cksum = 0,
2852                 }
2853         };
2854         int ret;
2855
2856         resource->flags = dev_flow->dv.group ? 0 : 1;
2857         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2858                 domain = sh->fdb_domain;
2859         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2860                 domain = sh->rx_domain;
2861         else
2862                 domain = sh->tx_domain;
2863         encap_decap_key.cksum = __rte_raw_cksum(resource->buf,
2864                                                 resource->size, 0);
2865         resource->entry.key = encap_decap_key.v64;
2866         /* Lookup a matching resource from cache. */
2867         entry = mlx5_hlist_lookup_ex(sh->encaps_decaps, resource->entry.key,
2868                                      flow_dv_encap_decap_resource_match,
2869                                      (void *)resource);
2870         if (entry) {
2871                 cache_resource = container_of(entry,
2872                         struct mlx5_flow_dv_encap_decap_resource, entry);
2873                 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2874                         (void *)cache_resource,
2875                         rte_atomic32_read(&cache_resource->refcnt));
2876                 rte_atomic32_inc(&cache_resource->refcnt);
2877                 dev_flow->handle->dvh.rix_encap_decap = cache_resource->idx;
2878                 dev_flow->dv.encap_decap = cache_resource;
2879                 return 0;
2880         }
2881         /* Register new encap/decap resource. */
2882         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2883                                        &dev_flow->handle->dvh.rix_encap_decap);
2884         if (!cache_resource)
2885                 return rte_flow_error_set(error, ENOMEM,
2886                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2887                                           "cannot allocate resource memory");
2888         *cache_resource = *resource;
2889         cache_resource->idx = dev_flow->handle->dvh.rix_encap_decap;
2890         ret = mlx5_flow_os_create_flow_action_packet_reformat
2891                                         (sh->ctx, domain, cache_resource,
2892                                          &cache_resource->action);
2893         if (ret) {
2894                 mlx5_free(cache_resource);
2895                 return rte_flow_error_set(error, ENOMEM,
2896                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2897                                           NULL, "cannot create action");
2898         }
2899         rte_atomic32_init(&cache_resource->refcnt);
2900         rte_atomic32_inc(&cache_resource->refcnt);
2901         if (mlx5_hlist_insert_ex(sh->encaps_decaps, &cache_resource->entry,
2902                                  flow_dv_encap_decap_resource_match,
2903                                  (void *)cache_resource)) {
2904                 claim_zero(mlx5_flow_os_destroy_flow_action
2905                                                 (cache_resource->action));
2906                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2907                                 cache_resource->idx);
2908                 return rte_flow_error_set(error, EEXIST,
2909                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2910                                           NULL, "action exist");
2911         }
2912         dev_flow->dv.encap_decap = cache_resource;
2913         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2914                 (void *)cache_resource,
2915                 rte_atomic32_read(&cache_resource->refcnt));
2916         return 0;
2917 }
2918
2919 /**
2920  * Find existing table jump resource or create and register a new one.
2921  *
2922  * @param[in, out] dev
2923  *   Pointer to rte_eth_dev structure.
2924  * @param[in, out] tbl
2925  *   Pointer to flow table resource.
2926  * @parm[in, out] dev_flow
2927  *   Pointer to the dev_flow.
2928  * @param[out] error
2929  *   pointer to error structure.
2930  *
2931  * @return
2932  *   0 on success otherwise -errno and errno is set.
2933  */
2934 static int
2935 flow_dv_jump_tbl_resource_register
2936                         (struct rte_eth_dev *dev __rte_unused,
2937                          struct mlx5_flow_tbl_resource *tbl,
2938                          struct mlx5_flow *dev_flow,
2939                          struct rte_flow_error *error)
2940 {
2941         struct mlx5_flow_tbl_data_entry *tbl_data =
2942                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2943         int cnt, ret;
2944
2945         MLX5_ASSERT(tbl);
2946         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2947         if (!cnt) {
2948                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2949                                 (tbl->obj, &tbl_data->jump.action);
2950                 if (ret)
2951                         return rte_flow_error_set(error, ENOMEM,
2952                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2953                                         NULL, "cannot create jump action");
2954                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2955                         (void *)&tbl_data->jump, cnt);
2956         } else {
2957                 /* old jump should not make the table ref++. */
2958                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2959                 MLX5_ASSERT(tbl_data->jump.action);
2960                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2961                         (void *)&tbl_data->jump, cnt);
2962         }
2963         rte_atomic32_inc(&tbl_data->jump.refcnt);
2964         dev_flow->handle->rix_jump = tbl_data->idx;
2965         dev_flow->dv.jump = &tbl_data->jump;
2966         return 0;
2967 }
2968
2969 /**
2970  * Find existing default miss resource or create and register a new one.
2971  *
2972  * @param[in, out] dev
2973  *   Pointer to rte_eth_dev structure.
2974  * @param[out] error
2975  *   pointer to error structure.
2976  *
2977  * @return
2978  *   0 on success otherwise -errno and errno is set.
2979  */
2980 static int
2981 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2982                 struct rte_flow_error *error)
2983 {
2984         struct mlx5_priv *priv = dev->data->dev_private;
2985         struct mlx5_dev_ctx_shared *sh = priv->sh;
2986         struct mlx5_flow_default_miss_resource *cache_resource =
2987                         &sh->default_miss;
2988         int cnt = rte_atomic32_read(&cache_resource->refcnt);
2989
2990         if (!cnt) {
2991                 MLX5_ASSERT(cache_resource->action);
2992                 cache_resource->action =
2993                 mlx5_glue->dr_create_flow_action_default_miss();
2994                 if (!cache_resource->action)
2995                         return rte_flow_error_set(error, ENOMEM,
2996                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2997                                         "cannot create default miss action");
2998                 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2999                                 (void *)cache_resource->action, cnt);
3000         }
3001         rte_atomic32_inc(&cache_resource->refcnt);
3002         return 0;
3003 }
3004
3005 /**
3006  * Find existing table port ID resource or create and register a new one.
3007  *
3008  * @param[in, out] dev
3009  *   Pointer to rte_eth_dev structure.
3010  * @param[in, out] resource
3011  *   Pointer to port ID action resource.
3012  * @parm[in, out] dev_flow
3013  *   Pointer to the dev_flow.
3014  * @param[out] error
3015  *   pointer to error structure.
3016  *
3017  * @return
3018  *   0 on success otherwise -errno and errno is set.
3019  */
3020 static int
3021 flow_dv_port_id_action_resource_register
3022                         (struct rte_eth_dev *dev,
3023                          struct mlx5_flow_dv_port_id_action_resource *resource,
3024                          struct mlx5_flow *dev_flow,
3025                          struct rte_flow_error *error)
3026 {
3027         struct mlx5_priv *priv = dev->data->dev_private;
3028         struct mlx5_dev_ctx_shared *sh = priv->sh;
3029         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
3030         uint32_t idx = 0;
3031         int ret;
3032
3033         /* Lookup a matching resource from cache. */
3034         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
3035                       idx, cache_resource, next) {
3036                 if (resource->port_id == cache_resource->port_id) {
3037                         DRV_LOG(DEBUG, "port id action resource resource %p: "
3038                                 "refcnt %d++",
3039                                 (void *)cache_resource,
3040                                 rte_atomic32_read(&cache_resource->refcnt));
3041                         rte_atomic32_inc(&cache_resource->refcnt);
3042                         dev_flow->handle->rix_port_id_action = idx;
3043                         dev_flow->dv.port_id_action = cache_resource;
3044                         return 0;
3045                 }
3046         }
3047         /* Register new port id action resource. */
3048         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
3049                                        &dev_flow->handle->rix_port_id_action);
3050         if (!cache_resource)
3051                 return rte_flow_error_set(error, ENOMEM,
3052                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3053                                           "cannot allocate resource memory");
3054         *cache_resource = *resource;
3055         ret = mlx5_flow_os_create_flow_action_dest_port
3056                                 (priv->sh->fdb_domain, resource->port_id,
3057                                  &cache_resource->action);
3058         if (ret) {
3059                 mlx5_free(cache_resource);
3060                 return rte_flow_error_set(error, ENOMEM,
3061                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3062                                           NULL, "cannot create action");
3063         }
3064         rte_atomic32_init(&cache_resource->refcnt);
3065         rte_atomic32_inc(&cache_resource->refcnt);
3066         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
3067                      dev_flow->handle->rix_port_id_action, cache_resource,
3068                      next);
3069         dev_flow->dv.port_id_action = cache_resource;
3070         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
3071                 (void *)cache_resource,
3072                 rte_atomic32_read(&cache_resource->refcnt));
3073         return 0;
3074 }
3075
3076 /**
3077  * Find existing push vlan resource or create and register a new one.
3078  *
3079  * @param [in, out] dev
3080  *   Pointer to rte_eth_dev structure.
3081  * @param[in, out] resource
3082  *   Pointer to port ID action resource.
3083  * @parm[in, out] dev_flow
3084  *   Pointer to the dev_flow.
3085  * @param[out] error
3086  *   pointer to error structure.
3087  *
3088  * @return
3089  *   0 on success otherwise -errno and errno is set.
3090  */
3091 static int
3092 flow_dv_push_vlan_action_resource_register
3093                        (struct rte_eth_dev *dev,
3094                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3095                         struct mlx5_flow *dev_flow,
3096                         struct rte_flow_error *error)
3097 {
3098         struct mlx5_priv *priv = dev->data->dev_private;
3099         struct mlx5_dev_ctx_shared *sh = priv->sh;
3100         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
3101         struct mlx5dv_dr_domain *domain;
3102         uint32_t idx = 0;
3103         int ret;
3104
3105         /* Lookup a matching resource from cache. */
3106         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3107                       sh->push_vlan_action_list, idx, cache_resource, next) {
3108                 if (resource->vlan_tag == cache_resource->vlan_tag &&
3109                     resource->ft_type == cache_resource->ft_type) {
3110                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
3111                                 "refcnt %d++",
3112                                 (void *)cache_resource,
3113                                 rte_atomic32_read(&cache_resource->refcnt));
3114                         rte_atomic32_inc(&cache_resource->refcnt);
3115                         dev_flow->handle->dvh.rix_push_vlan = idx;
3116                         dev_flow->dv.push_vlan_res = cache_resource;
3117                         return 0;
3118                 }
3119         }
3120         /* Register new push_vlan action resource. */
3121         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3122                                        &dev_flow->handle->dvh.rix_push_vlan);
3123         if (!cache_resource)
3124                 return rte_flow_error_set(error, ENOMEM,
3125                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3126                                           "cannot allocate resource memory");
3127         *cache_resource = *resource;
3128         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3129                 domain = sh->fdb_domain;
3130         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3131                 domain = sh->rx_domain;
3132         else
3133                 domain = sh->tx_domain;
3134         ret = mlx5_flow_os_create_flow_action_push_vlan
3135                                         (domain, resource->vlan_tag,
3136                                          &cache_resource->action);
3137         if (ret) {
3138                 mlx5_free(cache_resource);
3139                 return rte_flow_error_set(error, ENOMEM,
3140                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3141                                           NULL, "cannot create action");
3142         }
3143         rte_atomic32_init(&cache_resource->refcnt);
3144         rte_atomic32_inc(&cache_resource->refcnt);
3145         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3146                      &sh->push_vlan_action_list,
3147                      dev_flow->handle->dvh.rix_push_vlan,
3148                      cache_resource, next);
3149         dev_flow->dv.push_vlan_res = cache_resource;
3150         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
3151                 (void *)cache_resource,
3152                 rte_atomic32_read(&cache_resource->refcnt));
3153         return 0;
3154 }
3155 /**
3156  * Get the size of specific rte_flow_item_type hdr size
3157  *
3158  * @param[in] item_type
3159  *   Tested rte_flow_item_type.
3160  *
3161  * @return
3162  *   sizeof struct item_type, 0 if void or irrelevant.
3163  */
3164 static size_t
3165 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3166 {
3167         size_t retval;
3168
3169         switch (item_type) {
3170         case RTE_FLOW_ITEM_TYPE_ETH:
3171                 retval = sizeof(struct rte_ether_hdr);
3172                 break;
3173         case RTE_FLOW_ITEM_TYPE_VLAN:
3174                 retval = sizeof(struct rte_vlan_hdr);
3175                 break;
3176         case RTE_FLOW_ITEM_TYPE_IPV4:
3177                 retval = sizeof(struct rte_ipv4_hdr);
3178                 break;
3179         case RTE_FLOW_ITEM_TYPE_IPV6:
3180                 retval = sizeof(struct rte_ipv6_hdr);
3181                 break;
3182         case RTE_FLOW_ITEM_TYPE_UDP:
3183                 retval = sizeof(struct rte_udp_hdr);
3184                 break;
3185         case RTE_FLOW_ITEM_TYPE_TCP:
3186                 retval = sizeof(struct rte_tcp_hdr);
3187                 break;
3188         case RTE_FLOW_ITEM_TYPE_VXLAN:
3189         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3190                 retval = sizeof(struct rte_vxlan_hdr);
3191                 break;
3192         case RTE_FLOW_ITEM_TYPE_GRE:
3193         case RTE_FLOW_ITEM_TYPE_NVGRE:
3194                 retval = sizeof(struct rte_gre_hdr);
3195                 break;
3196         case RTE_FLOW_ITEM_TYPE_MPLS:
3197                 retval = sizeof(struct rte_mpls_hdr);
3198                 break;
3199         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3200         default:
3201                 retval = 0;
3202                 break;
3203         }
3204         return retval;
3205 }
3206
3207 #define MLX5_ENCAP_IPV4_VERSION         0x40
3208 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3209 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3210 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3211 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3212 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3213 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3214
3215 /**
3216  * Convert the encap action data from list of rte_flow_item to raw buffer
3217  *
3218  * @param[in] items
3219  *   Pointer to rte_flow_item objects list.
3220  * @param[out] buf
3221  *   Pointer to the output buffer.
3222  * @param[out] size
3223  *   Pointer to the output buffer size.
3224  * @param[out] error
3225  *   Pointer to the error structure.
3226  *
3227  * @return
3228  *   0 on success, a negative errno value otherwise and rte_errno is set.
3229  */
3230 static int
3231 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3232                            size_t *size, struct rte_flow_error *error)
3233 {
3234         struct rte_ether_hdr *eth = NULL;
3235         struct rte_vlan_hdr *vlan = NULL;
3236         struct rte_ipv4_hdr *ipv4 = NULL;
3237         struct rte_ipv6_hdr *ipv6 = NULL;
3238         struct rte_udp_hdr *udp = NULL;
3239         struct rte_vxlan_hdr *vxlan = NULL;
3240         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3241         struct rte_gre_hdr *gre = NULL;
3242         size_t len;
3243         size_t temp_size = 0;
3244
3245         if (!items)
3246                 return rte_flow_error_set(error, EINVAL,
3247                                           RTE_FLOW_ERROR_TYPE_ACTION,
3248                                           NULL, "invalid empty data");
3249         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3250                 len = flow_dv_get_item_hdr_len(items->type);
3251                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3252                         return rte_flow_error_set(error, EINVAL,
3253                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3254                                                   (void *)items->type,
3255                                                   "items total size is too big"
3256                                                   " for encap action");
3257                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3258                 switch (items->type) {
3259                 case RTE_FLOW_ITEM_TYPE_ETH:
3260                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3261                         break;
3262                 case RTE_FLOW_ITEM_TYPE_VLAN:
3263                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3264                         if (!eth)
3265                                 return rte_flow_error_set(error, EINVAL,
3266                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3267                                                 (void *)items->type,
3268                                                 "eth header not found");
3269                         if (!eth->ether_type)
3270                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3271                         break;
3272                 case RTE_FLOW_ITEM_TYPE_IPV4:
3273                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3274                         if (!vlan && !eth)
3275                                 return rte_flow_error_set(error, EINVAL,
3276                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3277                                                 (void *)items->type,
3278                                                 "neither eth nor vlan"
3279                                                 " header found");
3280                         if (vlan && !vlan->eth_proto)
3281                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3282                         else if (eth && !eth->ether_type)
3283                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3284                         if (!ipv4->version_ihl)
3285                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3286                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3287                         if (!ipv4->time_to_live)
3288                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3289                         break;
3290                 case RTE_FLOW_ITEM_TYPE_IPV6:
3291                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3292                         if (!vlan && !eth)
3293                                 return rte_flow_error_set(error, EINVAL,
3294                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3295                                                 (void *)items->type,
3296                                                 "neither eth nor vlan"
3297                                                 " header found");
3298                         if (vlan && !vlan->eth_proto)
3299                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3300                         else if (eth && !eth->ether_type)
3301                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3302                         if (!ipv6->vtc_flow)
3303                                 ipv6->vtc_flow =
3304                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3305                         if (!ipv6->hop_limits)
3306                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3307                         break;
3308                 case RTE_FLOW_ITEM_TYPE_UDP:
3309                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3310                         if (!ipv4 && !ipv6)
3311                                 return rte_flow_error_set(error, EINVAL,
3312                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3313                                                 (void *)items->type,
3314                                                 "ip header not found");
3315                         if (ipv4 && !ipv4->next_proto_id)
3316                                 ipv4->next_proto_id = IPPROTO_UDP;
3317                         else if (ipv6 && !ipv6->proto)
3318                                 ipv6->proto = IPPROTO_UDP;
3319                         break;
3320                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3321                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3322                         if (!udp)
3323                                 return rte_flow_error_set(error, EINVAL,
3324                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3325                                                 (void *)items->type,
3326                                                 "udp header not found");
3327                         if (!udp->dst_port)
3328                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3329                         if (!vxlan->vx_flags)
3330                                 vxlan->vx_flags =
3331                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3332                         break;
3333                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3334                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3335                         if (!udp)
3336                                 return rte_flow_error_set(error, EINVAL,
3337                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3338                                                 (void *)items->type,
3339                                                 "udp header not found");
3340                         if (!vxlan_gpe->proto)
3341                                 return rte_flow_error_set(error, EINVAL,
3342                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3343                                                 (void *)items->type,
3344                                                 "next protocol not found");
3345                         if (!udp->dst_port)
3346                                 udp->dst_port =
3347                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3348                         if (!vxlan_gpe->vx_flags)
3349                                 vxlan_gpe->vx_flags =
3350                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3351                         break;
3352                 case RTE_FLOW_ITEM_TYPE_GRE:
3353                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3354                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3355                         if (!gre->proto)
3356                                 return rte_flow_error_set(error, EINVAL,
3357                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3358                                                 (void *)items->type,
3359                                                 "next protocol not found");
3360                         if (!ipv4 && !ipv6)
3361                                 return rte_flow_error_set(error, EINVAL,
3362                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3363                                                 (void *)items->type,
3364                                                 "ip header not found");
3365                         if (ipv4 && !ipv4->next_proto_id)
3366                                 ipv4->next_proto_id = IPPROTO_GRE;
3367                         else if (ipv6 && !ipv6->proto)
3368                                 ipv6->proto = IPPROTO_GRE;
3369                         break;
3370                 case RTE_FLOW_ITEM_TYPE_VOID:
3371                         break;
3372                 default:
3373                         return rte_flow_error_set(error, EINVAL,
3374                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3375                                                   (void *)items->type,
3376                                                   "unsupported item type");
3377                         break;
3378                 }
3379                 temp_size += len;
3380         }
3381         *size = temp_size;
3382         return 0;
3383 }
3384
3385 static int
3386 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3387 {
3388         struct rte_ether_hdr *eth = NULL;
3389         struct rte_vlan_hdr *vlan = NULL;
3390         struct rte_ipv6_hdr *ipv6 = NULL;
3391         struct rte_udp_hdr *udp = NULL;
3392         char *next_hdr;
3393         uint16_t proto;
3394
3395         eth = (struct rte_ether_hdr *)data;
3396         next_hdr = (char *)(eth + 1);
3397         proto = RTE_BE16(eth->ether_type);
3398
3399         /* VLAN skipping */
3400         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3401                 vlan = (struct rte_vlan_hdr *)next_hdr;
3402                 proto = RTE_BE16(vlan->eth_proto);
3403                 next_hdr += sizeof(struct rte_vlan_hdr);
3404         }
3405
3406         /* HW calculates IPv4 csum. no need to proceed */
3407         if (proto == RTE_ETHER_TYPE_IPV4)
3408                 return 0;
3409
3410         /* non IPv4/IPv6 header. not supported */
3411         if (proto != RTE_ETHER_TYPE_IPV6) {
3412                 return rte_flow_error_set(error, ENOTSUP,
3413                                           RTE_FLOW_ERROR_TYPE_ACTION,
3414                                           NULL, "Cannot offload non IPv4/IPv6");
3415         }
3416
3417         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3418
3419         /* ignore non UDP */
3420         if (ipv6->proto != IPPROTO_UDP)
3421                 return 0;
3422
3423         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3424         udp->dgram_cksum = 0;
3425
3426         return 0;
3427 }
3428
3429 /**
3430  * Convert L2 encap action to DV specification.
3431  *
3432  * @param[in] dev
3433  *   Pointer to rte_eth_dev structure.
3434  * @param[in] action
3435  *   Pointer to action structure.
3436  * @param[in, out] dev_flow
3437  *   Pointer to the mlx5_flow.
3438  * @param[in] transfer
3439  *   Mark if the flow is E-Switch flow.
3440  * @param[out] error
3441  *   Pointer to the error structure.
3442  *
3443  * @return
3444  *   0 on success, a negative errno value otherwise and rte_errno is set.
3445  */
3446 static int
3447 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3448                                const struct rte_flow_action *action,
3449                                struct mlx5_flow *dev_flow,
3450                                uint8_t transfer,
3451                                struct rte_flow_error *error)
3452 {
3453         const struct rte_flow_item *encap_data;
3454         const struct rte_flow_action_raw_encap *raw_encap_data;
3455         struct mlx5_flow_dv_encap_decap_resource res = {
3456                 .reformat_type =
3457                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3458                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3459                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3460         };
3461
3462         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3463                 raw_encap_data =
3464                         (const struct rte_flow_action_raw_encap *)action->conf;
3465                 res.size = raw_encap_data->size;
3466                 memcpy(res.buf, raw_encap_data->data, res.size);
3467         } else {
3468                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3469                         encap_data =
3470                                 ((const struct rte_flow_action_vxlan_encap *)
3471                                                 action->conf)->definition;
3472                 else
3473                         encap_data =
3474                                 ((const struct rte_flow_action_nvgre_encap *)
3475                                                 action->conf)->definition;
3476                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3477                                                &res.size, error))
3478                         return -rte_errno;
3479         }
3480         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3481                 return -rte_errno;
3482         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3483                 return rte_flow_error_set(error, EINVAL,
3484                                           RTE_FLOW_ERROR_TYPE_ACTION,
3485                                           NULL, "can't create L2 encap action");
3486         return 0;
3487 }
3488
3489 /**
3490  * Convert L2 decap action to DV specification.
3491  *
3492  * @param[in] dev
3493  *   Pointer to rte_eth_dev structure.
3494  * @param[in, out] dev_flow
3495  *   Pointer to the mlx5_flow.
3496  * @param[in] transfer
3497  *   Mark if the flow is E-Switch flow.
3498  * @param[out] error
3499  *   Pointer to the error structure.
3500  *
3501  * @return
3502  *   0 on success, a negative errno value otherwise and rte_errno is set.
3503  */
3504 static int
3505 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3506                                struct mlx5_flow *dev_flow,
3507                                uint8_t transfer,
3508                                struct rte_flow_error *error)
3509 {
3510         struct mlx5_flow_dv_encap_decap_resource res = {
3511                 .size = 0,
3512                 .reformat_type =
3513                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3514                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3515                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3516         };
3517
3518         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3519                 return rte_flow_error_set(error, EINVAL,
3520                                           RTE_FLOW_ERROR_TYPE_ACTION,
3521                                           NULL, "can't create L2 decap action");
3522         return 0;
3523 }
3524
3525 /**
3526  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3527  *
3528  * @param[in] dev
3529  *   Pointer to rte_eth_dev structure.
3530  * @param[in] action
3531  *   Pointer to action structure.
3532  * @param[in, out] dev_flow
3533  *   Pointer to the mlx5_flow.
3534  * @param[in] attr
3535  *   Pointer to the flow attributes.
3536  * @param[out] error
3537  *   Pointer to the error structure.
3538  *
3539  * @return
3540  *   0 on success, a negative errno value otherwise and rte_errno is set.
3541  */
3542 static int
3543 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3544                                 const struct rte_flow_action *action,
3545                                 struct mlx5_flow *dev_flow,
3546                                 const struct rte_flow_attr *attr,
3547                                 struct rte_flow_error *error)
3548 {
3549         const struct rte_flow_action_raw_encap *encap_data;
3550         struct mlx5_flow_dv_encap_decap_resource res;
3551
3552         memset(&res, 0, sizeof(res));
3553         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3554         res.size = encap_data->size;
3555         memcpy(res.buf, encap_data->data, res.size);
3556         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3557                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3558                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3559         if (attr->transfer)
3560                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3561         else
3562                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3563                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3564         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3565                 return rte_flow_error_set(error, EINVAL,
3566                                           RTE_FLOW_ERROR_TYPE_ACTION,
3567                                           NULL, "can't create encap action");
3568         return 0;
3569 }
3570
3571 /**
3572  * Create action push VLAN.
3573  *
3574  * @param[in] dev
3575  *   Pointer to rte_eth_dev structure.
3576  * @param[in] attr
3577  *   Pointer to the flow attributes.
3578  * @param[in] vlan
3579  *   Pointer to the vlan to push to the Ethernet header.
3580  * @param[in, out] dev_flow
3581  *   Pointer to the mlx5_flow.
3582  * @param[out] error
3583  *   Pointer to the error structure.
3584  *
3585  * @return
3586  *   0 on success, a negative errno value otherwise and rte_errno is set.
3587  */
3588 static int
3589 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3590                                 const struct rte_flow_attr *attr,
3591                                 const struct rte_vlan_hdr *vlan,
3592                                 struct mlx5_flow *dev_flow,
3593                                 struct rte_flow_error *error)
3594 {
3595         struct mlx5_flow_dv_push_vlan_action_resource res;
3596
3597         memset(&res, 0, sizeof(res));
3598         res.vlan_tag =
3599                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3600                                  vlan->vlan_tci);
3601         if (attr->transfer)
3602                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3603         else
3604                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3605                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3606         return flow_dv_push_vlan_action_resource_register
3607                                             (dev, &res, dev_flow, error);
3608 }
3609
3610 static int fdb_mirror;
3611
3612 /**
3613  * Validate the modify-header actions.
3614  *
3615  * @param[in] action_flags
3616  *   Holds the actions detected until now.
3617  * @param[in] action
3618  *   Pointer to the modify action.
3619  * @param[out] error
3620  *   Pointer to error structure.
3621  *
3622  * @return
3623  *   0 on success, a negative errno value otherwise and rte_errno is set.
3624  */
3625 static int
3626 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3627                                    const struct rte_flow_action *action,
3628                                    struct rte_flow_error *error)
3629 {
3630         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3631                 return rte_flow_error_set(error, EINVAL,
3632                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3633                                           NULL, "action configuration not set");
3634         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3635                 return rte_flow_error_set(error, EINVAL,
3636                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3637                                           "can't have encap action before"
3638                                           " modify action");
3639         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3640                 return rte_flow_error_set(error, EINVAL,
3641                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3642                                           "can't support sample action before"
3643                                           " modify action for E-Switch"
3644                                           " mirroring");
3645         return 0;
3646 }
3647
3648 /**
3649  * Validate the modify-header MAC address actions.
3650  *
3651  * @param[in] action_flags
3652  *   Holds the actions detected until now.
3653  * @param[in] action
3654  *   Pointer to the modify action.
3655  * @param[in] item_flags
3656  *   Holds the items detected.
3657  * @param[out] error
3658  *   Pointer to error structure.
3659  *
3660  * @return
3661  *   0 on success, a negative errno value otherwise and rte_errno is set.
3662  */
3663 static int
3664 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3665                                    const struct rte_flow_action *action,
3666                                    const uint64_t item_flags,
3667                                    struct rte_flow_error *error)
3668 {
3669         int ret = 0;
3670
3671         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3672         if (!ret) {
3673                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3674                         return rte_flow_error_set(error, EINVAL,
3675                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3676                                                   NULL,
3677                                                   "no L2 item in pattern");
3678         }
3679         return ret;
3680 }
3681
3682 /**
3683  * Validate the modify-header IPv4 address actions.
3684  *
3685  * @param[in] action_flags
3686  *   Holds the actions detected until now.
3687  * @param[in] action
3688  *   Pointer to the modify action.
3689  * @param[in] item_flags
3690  *   Holds the items detected.
3691  * @param[out] error
3692  *   Pointer to error structure.
3693  *
3694  * @return
3695  *   0 on success, a negative errno value otherwise and rte_errno is set.
3696  */
3697 static int
3698 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3699                                     const struct rte_flow_action *action,
3700                                     const uint64_t item_flags,
3701                                     struct rte_flow_error *error)
3702 {
3703         int ret = 0;
3704         uint64_t layer;
3705
3706         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3707         if (!ret) {
3708                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3709                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3710                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3711                 if (!(item_flags & layer))
3712                         return rte_flow_error_set(error, EINVAL,
3713                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3714                                                   NULL,
3715                                                   "no ipv4 item in pattern");
3716         }
3717         return ret;
3718 }
3719
3720 /**
3721  * Validate the modify-header IPv6 address actions.
3722  *
3723  * @param[in] action_flags
3724  *   Holds the actions detected until now.
3725  * @param[in] action
3726  *   Pointer to the modify action.
3727  * @param[in] item_flags
3728  *   Holds the items detected.
3729  * @param[out] error
3730  *   Pointer to error structure.
3731  *
3732  * @return
3733  *   0 on success, a negative errno value otherwise and rte_errno is set.
3734  */
3735 static int
3736 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3737                                     const struct rte_flow_action *action,
3738                                     const uint64_t item_flags,
3739                                     struct rte_flow_error *error)
3740 {
3741         int ret = 0;
3742         uint64_t layer;
3743
3744         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3745         if (!ret) {
3746                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3747                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3748                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3749                 if (!(item_flags & layer))
3750                         return rte_flow_error_set(error, EINVAL,
3751                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3752                                                   NULL,
3753                                                   "no ipv6 item in pattern");
3754         }
3755         return ret;
3756 }
3757
3758 /**
3759  * Validate the modify-header TP actions.
3760  *
3761  * @param[in] action_flags
3762  *   Holds the actions detected until now.
3763  * @param[in] action
3764  *   Pointer to the modify action.
3765  * @param[in] item_flags
3766  *   Holds the items detected.
3767  * @param[out] error
3768  *   Pointer to error structure.
3769  *
3770  * @return
3771  *   0 on success, a negative errno value otherwise and rte_errno is set.
3772  */
3773 static int
3774 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3775                                   const struct rte_flow_action *action,
3776                                   const uint64_t item_flags,
3777                                   struct rte_flow_error *error)
3778 {
3779         int ret = 0;
3780         uint64_t layer;
3781
3782         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3783         if (!ret) {
3784                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3785                                  MLX5_FLOW_LAYER_INNER_L4 :
3786                                  MLX5_FLOW_LAYER_OUTER_L4;
3787                 if (!(item_flags & layer))
3788                         return rte_flow_error_set(error, EINVAL,
3789                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3790                                                   NULL, "no transport layer "
3791                                                   "in pattern");
3792         }
3793         return ret;
3794 }
3795
3796 /**
3797  * Validate the modify-header actions of increment/decrement
3798  * TCP Sequence-number.
3799  *
3800  * @param[in] action_flags
3801  *   Holds the actions detected until now.
3802  * @param[in] action
3803  *   Pointer to the modify action.
3804  * @param[in] item_flags
3805  *   Holds the items detected.
3806  * @param[out] error
3807  *   Pointer to error structure.
3808  *
3809  * @return
3810  *   0 on success, a negative errno value otherwise and rte_errno is set.
3811  */
3812 static int
3813 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3814                                        const struct rte_flow_action *action,
3815                                        const uint64_t item_flags,
3816                                        struct rte_flow_error *error)
3817 {
3818         int ret = 0;
3819         uint64_t layer;
3820
3821         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3822         if (!ret) {
3823                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3824                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3825                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3826                 if (!(item_flags & layer))
3827                         return rte_flow_error_set(error, EINVAL,
3828                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3829                                                   NULL, "no TCP item in"
3830                                                   " pattern");
3831                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3832                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3833                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3834                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3835                         return rte_flow_error_set(error, EINVAL,
3836                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3837                                                   NULL,
3838                                                   "cannot decrease and increase"
3839                                                   " TCP sequence number"
3840                                                   " at the same time");
3841         }
3842         return ret;
3843 }
3844
3845 /**
3846  * Validate the modify-header actions of increment/decrement
3847  * TCP Acknowledgment number.
3848  *
3849  * @param[in] action_flags
3850  *   Holds the actions detected until now.
3851  * @param[in] action
3852  *   Pointer to the modify action.
3853  * @param[in] item_flags
3854  *   Holds the items detected.
3855  * @param[out] error
3856  *   Pointer to error structure.
3857  *
3858  * @return
3859  *   0 on success, a negative errno value otherwise and rte_errno is set.
3860  */
3861 static int
3862 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3863                                        const struct rte_flow_action *action,
3864                                        const uint64_t item_flags,
3865                                        struct rte_flow_error *error)
3866 {
3867         int ret = 0;
3868         uint64_t layer;
3869
3870         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3871         if (!ret) {
3872                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3873                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3874                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3875                 if (!(item_flags & layer))
3876                         return rte_flow_error_set(error, EINVAL,
3877                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3878                                                   NULL, "no TCP item in"
3879                                                   " pattern");
3880                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3881                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3882                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3883                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3884                         return rte_flow_error_set(error, EINVAL,
3885                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                   NULL,
3887                                                   "cannot decrease and increase"
3888                                                   " TCP acknowledgment number"
3889                                                   " at the same time");
3890         }
3891         return ret;
3892 }
3893
3894 /**
3895  * Validate the modify-header TTL actions.
3896  *
3897  * @param[in] action_flags
3898  *   Holds the actions detected until now.
3899  * @param[in] action
3900  *   Pointer to the modify action.
3901  * @param[in] item_flags
3902  *   Holds the items detected.
3903  * @param[out] error
3904  *   Pointer to error structure.
3905  *
3906  * @return
3907  *   0 on success, a negative errno value otherwise and rte_errno is set.
3908  */
3909 static int
3910 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3911                                    const struct rte_flow_action *action,
3912                                    const uint64_t item_flags,
3913                                    struct rte_flow_error *error)
3914 {
3915         int ret = 0;
3916         uint64_t layer;
3917
3918         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3919         if (!ret) {
3920                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3921                                  MLX5_FLOW_LAYER_INNER_L3 :
3922                                  MLX5_FLOW_LAYER_OUTER_L3;
3923                 if (!(item_flags & layer))
3924                         return rte_flow_error_set(error, EINVAL,
3925                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3926                                                   NULL,
3927                                                   "no IP protocol in pattern");
3928         }
3929         return ret;
3930 }
3931
3932 /**
3933  * Validate jump action.
3934  *
3935  * @param[in] action
3936  *   Pointer to the jump action.
3937  * @param[in] action_flags
3938  *   Holds the actions detected until now.
3939  * @param[in] attributes
3940  *   Pointer to flow attributes
3941  * @param[in] external
3942  *   Action belongs to flow rule created by request external to PMD.
3943  * @param[out] error
3944  *   Pointer to error structure.
3945  *
3946  * @return
3947  *   0 on success, a negative errno value otherwise and rte_errno is set.
3948  */
3949 static int
3950 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3951                              const struct mlx5_flow_tunnel *tunnel,
3952                              const struct rte_flow_action *action,
3953                              uint64_t action_flags,
3954                              const struct rte_flow_attr *attributes,
3955                              bool external, struct rte_flow_error *error)
3956 {
3957         uint32_t target_group, table;
3958         int ret = 0;
3959         struct flow_grp_info grp_info = {
3960                 .external = !!external,
3961                 .transfer = !!attributes->transfer,
3962                 .fdb_def_rule = 1,
3963                 .std_tbl_fix = 0
3964         };
3965         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3966                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3967                 return rte_flow_error_set(error, EINVAL,
3968                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3969                                           "can't have 2 fate actions in"
3970                                           " same flow");
3971         if (action_flags & MLX5_FLOW_ACTION_METER)
3972                 return rte_flow_error_set(error, ENOTSUP,
3973                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3974                                           "jump with meter not support");
3975         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3976                 return rte_flow_error_set(error, EINVAL,
3977                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3978                                           "E-Switch mirroring can't support"
3979                                           " Sample action and jump action in"
3980                                           " same flow now");
3981         if (!action->conf)
3982                 return rte_flow_error_set(error, EINVAL,
3983                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3984                                           NULL, "action configuration not set");
3985         target_group =
3986                 ((const struct rte_flow_action_jump *)action->conf)->group;
3987         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3988                                        grp_info, error);
3989         if (ret)
3990                 return ret;
3991         if (attributes->group == target_group &&
3992             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3993                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3994                 return rte_flow_error_set(error, EINVAL,
3995                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3996                                           "target group must be other than"
3997                                           " the current flow group");
3998         return 0;
3999 }
4000
4001 /*
4002  * Validate the port_id action.
4003  *
4004  * @param[in] dev
4005  *   Pointer to rte_eth_dev structure.
4006  * @param[in] action_flags
4007  *   Bit-fields that holds the actions detected until now.
4008  * @param[in] action
4009  *   Port_id RTE action structure.
4010  * @param[in] attr
4011  *   Attributes of flow that includes this action.
4012  * @param[out] error
4013  *   Pointer to error structure.
4014  *
4015  * @return
4016  *   0 on success, a negative errno value otherwise and rte_errno is set.
4017  */
4018 static int
4019 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4020                                 uint64_t action_flags,
4021                                 const struct rte_flow_action *action,
4022                                 const struct rte_flow_attr *attr,
4023                                 struct rte_flow_error *error)
4024 {
4025         const struct rte_flow_action_port_id *port_id;
4026         struct mlx5_priv *act_priv;
4027         struct mlx5_priv *dev_priv;
4028         uint16_t port;
4029
4030         if (!attr->transfer)
4031                 return rte_flow_error_set(error, ENOTSUP,
4032                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4033                                           NULL,
4034                                           "port id action is valid in transfer"
4035                                           " mode only");
4036         if (!action || !action->conf)
4037                 return rte_flow_error_set(error, ENOTSUP,
4038                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4039                                           NULL,
4040                                           "port id action parameters must be"
4041                                           " specified");
4042         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4043                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4044                 return rte_flow_error_set(error, EINVAL,
4045                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4046                                           "can have only one fate actions in"
4047                                           " a flow");
4048         dev_priv = mlx5_dev_to_eswitch_info(dev);
4049         if (!dev_priv)
4050                 return rte_flow_error_set(error, rte_errno,
4051                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4052                                           NULL,
4053                                           "failed to obtain E-Switch info");
4054         port_id = action->conf;
4055         port = port_id->original ? dev->data->port_id : port_id->id;
4056         act_priv = mlx5_port_to_eswitch_info(port, false);
4057         if (!act_priv)
4058                 return rte_flow_error_set
4059                                 (error, rte_errno,
4060                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4061                                  "failed to obtain E-Switch port id for port");
4062         if (act_priv->domain_id != dev_priv->domain_id)
4063                 return rte_flow_error_set
4064                                 (error, EINVAL,
4065                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4066                                  "port does not belong to"
4067                                  " E-Switch being configured");
4068         return 0;
4069 }
4070
4071 /**
4072  * Get the maximum number of modify header actions.
4073  *
4074  * @param dev
4075  *   Pointer to rte_eth_dev structure.
4076  * @param flags
4077  *   Flags bits to check if root level.
4078  *
4079  * @return
4080  *   Max number of modify header actions device can support.
4081  */
4082 static inline unsigned int
4083 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4084                               uint64_t flags)
4085 {
4086         /*
4087          * There's no way to directly query the max capacity from FW.
4088          * The maximal value on root table should be assumed to be supported.
4089          */
4090         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4091                 return MLX5_MAX_MODIFY_NUM;
4092         else
4093                 return MLX5_ROOT_TBL_MODIFY_NUM;
4094 }
4095
4096 /**
4097  * Validate the meter action.
4098  *
4099  * @param[in] dev
4100  *   Pointer to rte_eth_dev structure.
4101  * @param[in] action_flags
4102  *   Bit-fields that holds the actions detected until now.
4103  * @param[in] action
4104  *   Pointer to the meter action.
4105  * @param[in] attr
4106  *   Attributes of flow that includes this action.
4107  * @param[out] error
4108  *   Pointer to error structure.
4109  *
4110  * @return
4111  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4112  */
4113 static int
4114 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4115                                 uint64_t action_flags,
4116                                 const struct rte_flow_action *action,
4117                                 const struct rte_flow_attr *attr,
4118                                 struct rte_flow_error *error)
4119 {
4120         struct mlx5_priv *priv = dev->data->dev_private;
4121         const struct rte_flow_action_meter *am = action->conf;
4122         struct mlx5_flow_meter *fm;
4123
4124         if (!am)
4125                 return rte_flow_error_set(error, EINVAL,
4126                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4127                                           "meter action conf is NULL");
4128
4129         if (action_flags & MLX5_FLOW_ACTION_METER)
4130                 return rte_flow_error_set(error, ENOTSUP,
4131                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4132                                           "meter chaining not support");
4133         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4134                 return rte_flow_error_set(error, ENOTSUP,
4135                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4136                                           "meter with jump not support");
4137         if (!priv->mtr_en)
4138                 return rte_flow_error_set(error, ENOTSUP,
4139                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4140                                           NULL,
4141                                           "meter action not supported");
4142         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4143         if (!fm)
4144                 return rte_flow_error_set(error, EINVAL,
4145                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4146                                           "Meter not found");
4147         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4148               (!fm->ingress && !attr->ingress && attr->egress) ||
4149               (!fm->egress && !attr->egress && attr->ingress))))
4150                 return rte_flow_error_set(error, EINVAL,
4151                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4152                                           "Flow attributes are either invalid "
4153                                           "or have a conflict with current "
4154                                           "meter attributes");
4155         return 0;
4156 }
4157
4158 /**
4159  * Validate the age action.
4160  *
4161  * @param[in] action_flags
4162  *   Holds the actions detected until now.
4163  * @param[in] action
4164  *   Pointer to the age action.
4165  * @param[in] dev
4166  *   Pointer to the Ethernet device structure.
4167  * @param[out] error
4168  *   Pointer to error structure.
4169  *
4170  * @return
4171  *   0 on success, a negative errno value otherwise and rte_errno is set.
4172  */
4173 static int
4174 flow_dv_validate_action_age(uint64_t action_flags,
4175                             const struct rte_flow_action *action,
4176                             struct rte_eth_dev *dev,
4177                             struct rte_flow_error *error)
4178 {
4179         struct mlx5_priv *priv = dev->data->dev_private;
4180         const struct rte_flow_action_age *age = action->conf;
4181
4182         if (!priv->config.devx || priv->sh->cmng.counter_fallback)
4183                 return rte_flow_error_set(error, ENOTSUP,
4184                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4185                                           NULL,
4186                                           "age action not supported");
4187         if (!(action->conf))
4188                 return rte_flow_error_set(error, EINVAL,
4189                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4190                                           "configuration cannot be null");
4191         if (!(age->timeout))
4192                 return rte_flow_error_set(error, EINVAL,
4193                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4194                                           "invalid timeout value 0");
4195         if (action_flags & MLX5_FLOW_ACTION_AGE)
4196                 return rte_flow_error_set(error, EINVAL,
4197                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4198                                           "duplicate age actions set");
4199         return 0;
4200 }
4201
4202 /**
4203  * Validate the modify-header IPv4 DSCP actions.
4204  *
4205  * @param[in] action_flags
4206  *   Holds the actions detected until now.
4207  * @param[in] action
4208  *   Pointer to the modify action.
4209  * @param[in] item_flags
4210  *   Holds the items detected.
4211  * @param[out] error
4212  *   Pointer to error structure.
4213  *
4214  * @return
4215  *   0 on success, a negative errno value otherwise and rte_errno is set.
4216  */
4217 static int
4218 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4219                                          const struct rte_flow_action *action,
4220                                          const uint64_t item_flags,
4221                                          struct rte_flow_error *error)
4222 {
4223         int ret = 0;
4224
4225         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4226         if (!ret) {
4227                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4228                         return rte_flow_error_set(error, EINVAL,
4229                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4230                                                   NULL,
4231                                                   "no ipv4 item in pattern");
4232         }
4233         return ret;
4234 }
4235
4236 /**
4237  * Validate the modify-header IPv6 DSCP actions.
4238  *
4239  * @param[in] action_flags
4240  *   Holds the actions detected until now.
4241  * @param[in] action
4242  *   Pointer to the modify action.
4243  * @param[in] item_flags
4244  *   Holds the items detected.
4245  * @param[out] error
4246  *   Pointer to error structure.
4247  *
4248  * @return
4249  *   0 on success, a negative errno value otherwise and rte_errno is set.
4250  */
4251 static int
4252 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4253                                          const struct rte_flow_action *action,
4254                                          const uint64_t item_flags,
4255                                          struct rte_flow_error *error)
4256 {
4257         int ret = 0;
4258
4259         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4260         if (!ret) {
4261                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4262                         return rte_flow_error_set(error, EINVAL,
4263                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4264                                                   NULL,
4265                                                   "no ipv6 item in pattern");
4266         }
4267         return ret;
4268 }
4269
4270 /**
4271  * Match modify-header resource.
4272  *
4273  * @param entry
4274  *   Pointer to exist resource entry object.
4275  * @param ctx
4276  *   Pointer to new modify-header resource.
4277  *
4278  * @return
4279  *   0 on matching, -1 otherwise.
4280  */
4281 static int
4282 flow_dv_modify_hdr_resource_match(struct mlx5_hlist_entry *entry, void *ctx)
4283 {
4284         struct mlx5_flow_dv_modify_hdr_resource *resource;
4285         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4286         uint32_t actions_len;
4287
4288         resource = (struct mlx5_flow_dv_modify_hdr_resource *)ctx;
4289         cache_resource = container_of(entry,
4290                                       struct mlx5_flow_dv_modify_hdr_resource,
4291                                       entry);
4292         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4293         if (resource->entry.key == cache_resource->entry.key &&
4294             resource->ft_type == cache_resource->ft_type &&
4295             resource->actions_num == cache_resource->actions_num &&
4296             resource->flags == cache_resource->flags &&
4297             !memcmp((const void *)resource->actions,
4298                     (const void *)cache_resource->actions,
4299                     actions_len))
4300                 return 0;
4301         return -1;
4302 }
4303
4304 /**
4305  * Validate the sample action.
4306  *
4307  * @param[in] action_flags
4308  *   Holds the actions detected until now.
4309  * @param[in] action
4310  *   Pointer to the sample action.
4311  * @param[in] dev
4312  *   Pointer to the Ethernet device structure.
4313  * @param[in] attr
4314  *   Attributes of flow that includes this action.
4315  * @param[out] error
4316  *   Pointer to error structure.
4317  *
4318  * @return
4319  *   0 on success, a negative errno value otherwise and rte_errno is set.
4320  */
4321 static int
4322 flow_dv_validate_action_sample(uint64_t action_flags,
4323                                const struct rte_flow_action *action,
4324                                struct rte_eth_dev *dev,
4325                                const struct rte_flow_attr *attr,
4326                                struct rte_flow_error *error)
4327 {
4328         struct mlx5_priv *priv = dev->data->dev_private;
4329         struct mlx5_dev_config *dev_conf = &priv->config;
4330         const struct rte_flow_action_sample *sample = action->conf;
4331         const struct rte_flow_action *act;
4332         uint64_t sub_action_flags = 0;
4333         uint16_t queue_index = 0xFFFF;
4334         int actions_n = 0;
4335         int ret;
4336         fdb_mirror = 0;
4337
4338         if (!sample)
4339                 return rte_flow_error_set(error, EINVAL,
4340                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4341                                           "configuration cannot be NULL");
4342         if (sample->ratio == 0)
4343                 return rte_flow_error_set(error, EINVAL,
4344                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4345                                           "ratio value starts from 1");
4346         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4347                 return rte_flow_error_set(error, ENOTSUP,
4348                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4349                                           NULL,
4350                                           "sample action not supported");
4351         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4352                 return rte_flow_error_set(error, EINVAL,
4353                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4354                                           "Multiple sample actions not "
4355                                           "supported");
4356         if (action_flags & MLX5_FLOW_ACTION_METER)
4357                 return rte_flow_error_set(error, EINVAL,
4358                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4359                                           "wrong action order, meter should "
4360                                           "be after sample action");
4361         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4362                 return rte_flow_error_set(error, EINVAL,
4363                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4364                                           "wrong action order, jump should "
4365                                           "be after sample action");
4366         act = sample->actions;
4367         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4368                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4369                         return rte_flow_error_set(error, ENOTSUP,
4370                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4371                                                   act, "too many actions");
4372                 switch (act->type) {
4373                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4374                         ret = mlx5_flow_validate_action_queue(act,
4375                                                               sub_action_flags,
4376                                                               dev,
4377                                                               attr, error);
4378                         if (ret < 0)
4379                                 return ret;
4380                         queue_index = ((const struct rte_flow_action_queue *)
4381                                                         (act->conf))->index;
4382                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4383                         ++actions_n;
4384                         break;
4385                 case RTE_FLOW_ACTION_TYPE_MARK:
4386                         ret = flow_dv_validate_action_mark(dev, act,
4387                                                            sub_action_flags,
4388                                                            attr, error);
4389                         if (ret < 0)
4390                                 return ret;
4391                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4392                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4393                                                 MLX5_FLOW_ACTION_MARK_EXT;
4394                         else
4395                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4396                         ++actions_n;
4397                         break;
4398                 case RTE_FLOW_ACTION_TYPE_COUNT:
4399                         ret = flow_dv_validate_action_count(dev, error);
4400                         if (ret < 0)
4401                                 return ret;
4402                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4403                         ++actions_n;
4404                         break;
4405                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4406                         ret = flow_dv_validate_action_port_id(dev,
4407                                                               sub_action_flags,
4408                                                               act,
4409                                                               attr,
4410                                                               error);
4411                         if (ret)
4412                                 return ret;
4413                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4414                         ++actions_n;
4415                         break;
4416                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4417                         ret = flow_dv_validate_action_raw_encap_decap
4418                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4419                                  &actions_n, error);
4420                         if (ret < 0)
4421                                 return ret;
4422                         ++actions_n;
4423                         break;
4424                 default:
4425                         return rte_flow_error_set(error, ENOTSUP,
4426                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4427                                                   NULL,
4428                                                   "Doesn't support optional "
4429                                                   "action");
4430                 }
4431         }
4432         if (attr->ingress && !attr->transfer) {
4433                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4434                         return rte_flow_error_set(error, EINVAL,
4435                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4436                                                   NULL,
4437                                                   "Ingress must has a dest "
4438                                                   "QUEUE for Sample");
4439         } else if (attr->egress && !attr->transfer) {
4440                 return rte_flow_error_set(error, ENOTSUP,
4441                                           RTE_FLOW_ERROR_TYPE_ACTION,
4442                                           NULL,
4443                                           "Sample Only support Ingress "
4444                                           "or E-Switch");
4445         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4446                 MLX5_ASSERT(attr->transfer);
4447                 if (sample->ratio > 1)
4448                         return rte_flow_error_set(error, ENOTSUP,
4449                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4450                                                   NULL,
4451                                                   "E-Switch doesn't support "
4452                                                   "any optional action "
4453                                                   "for sampling");
4454                 fdb_mirror = 1;
4455                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4456                         return rte_flow_error_set(error, ENOTSUP,
4457                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4458                                                   NULL,
4459                                                   "unsupported action QUEUE");
4460                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4461                         return rte_flow_error_set(error, EINVAL,
4462                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4463                                                   NULL,
4464                                                   "E-Switch must has a dest "
4465                                                   "port for mirroring");
4466         }
4467         /* Continue validation for Xcap actions.*/
4468         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4469             (queue_index == 0xFFFF ||
4470              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4471                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4472                      MLX5_FLOW_XCAP_ACTIONS)
4473                         return rte_flow_error_set(error, ENOTSUP,
4474                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4475                                                   NULL, "encap and decap "
4476                                                   "combination aren't "
4477                                                   "supported");
4478                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4479                                                         MLX5_FLOW_ACTION_ENCAP))
4480                         return rte_flow_error_set(error, ENOTSUP,
4481                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4482                                                   NULL, "encap is not supported"
4483                                                   " for ingress traffic");
4484         }
4485         return 0;
4486 }
4487
4488 /**
4489  * Find existing modify-header resource or create and register a new one.
4490  *
4491  * @param dev[in, out]
4492  *   Pointer to rte_eth_dev structure.
4493  * @param[in, out] resource
4494  *   Pointer to modify-header resource.
4495  * @parm[in, out] dev_flow
4496  *   Pointer to the dev_flow.
4497  * @param[out] error
4498  *   pointer to error structure.
4499  *
4500  * @return
4501  *   0 on success otherwise -errno and errno is set.
4502  */
4503 static int
4504 flow_dv_modify_hdr_resource_register
4505                         (struct rte_eth_dev *dev,
4506                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4507                          struct mlx5_flow *dev_flow,
4508                          struct rte_flow_error *error)
4509 {
4510         struct mlx5_priv *priv = dev->data->dev_private;
4511         struct mlx5_dev_ctx_shared *sh = priv->sh;
4512         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
4513         struct mlx5dv_dr_domain *ns;
4514         uint32_t actions_len;
4515         struct mlx5_hlist_entry *entry;
4516         union mlx5_flow_modify_hdr_key hdr_mod_key = {
4517                 {
4518                         .ft_type = resource->ft_type,
4519                         .actions_num = resource->actions_num,
4520                         .group = dev_flow->dv.group,
4521                         .cksum = 0,
4522                 }
4523         };
4524         int ret;
4525
4526         resource->flags = dev_flow->dv.group ? 0 :
4527                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4528         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4529                                     resource->flags))
4530                 return rte_flow_error_set(error, EOVERFLOW,
4531                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4532                                           "too many modify header items");
4533         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4534                 ns = sh->fdb_domain;
4535         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4536                 ns = sh->tx_domain;
4537         else
4538                 ns = sh->rx_domain;
4539         /* Lookup a matching resource from cache. */
4540         actions_len = resource->actions_num * sizeof(resource->actions[0]);
4541         hdr_mod_key.cksum = __rte_raw_cksum(resource->actions, actions_len, 0);
4542         resource->entry.key = hdr_mod_key.v64;
4543         entry = mlx5_hlist_lookup_ex(sh->modify_cmds, resource->entry.key,
4544                                      flow_dv_modify_hdr_resource_match,
4545                                      (void *)resource);
4546         if (entry) {
4547                 cache_resource = container_of(entry,
4548                                         struct mlx5_flow_dv_modify_hdr_resource,
4549                                         entry);
4550                 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4551                         (void *)cache_resource,
4552                         rte_atomic32_read(&cache_resource->refcnt));
4553                 rte_atomic32_inc(&cache_resource->refcnt);
4554                 dev_flow->handle->dvh.modify_hdr = cache_resource;
4555                 return 0;
4556
4557         }
4558         /* Register new modify-header resource. */
4559         cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4560                                     sizeof(*cache_resource) + actions_len, 0,
4561                                     SOCKET_ID_ANY);
4562         if (!cache_resource)
4563                 return rte_flow_error_set(error, ENOMEM,
4564                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4565                                           "cannot allocate resource memory");
4566         *cache_resource = *resource;
4567         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4568         ret = mlx5_flow_os_create_flow_action_modify_header
4569                                         (sh->ctx, ns, cache_resource,
4570                                          actions_len, &cache_resource->action);
4571         if (ret) {
4572                 mlx5_free(cache_resource);
4573                 return rte_flow_error_set(error, ENOMEM,
4574                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4575                                           NULL, "cannot create action");
4576         }
4577         rte_atomic32_init(&cache_resource->refcnt);
4578         rte_atomic32_inc(&cache_resource->refcnt);
4579         if (mlx5_hlist_insert_ex(sh->modify_cmds, &cache_resource->entry,
4580                                  flow_dv_modify_hdr_resource_match,
4581                                  (void *)cache_resource)) {
4582                 claim_zero(mlx5_flow_os_destroy_flow_action
4583                                                 (cache_resource->action));
4584                 mlx5_free(cache_resource);
4585                 return rte_flow_error_set(error, EEXIST,
4586                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4587                                           NULL, "action exist");
4588         }
4589         dev_flow->handle->dvh.modify_hdr = cache_resource;
4590         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4591                 (void *)cache_resource,
4592                 rte_atomic32_read(&cache_resource->refcnt));
4593         return 0;
4594 }
4595
4596 /**
4597  * Get DV flow counter by index.
4598  *
4599  * @param[in] dev
4600  *   Pointer to the Ethernet device structure.
4601  * @param[in] idx
4602  *   mlx5 flow counter index in the container.
4603  * @param[out] ppool
4604  *   mlx5 flow counter pool in the container,
4605  *
4606  * @return
4607  *   Pointer to the counter, NULL otherwise.
4608  */
4609 static struct mlx5_flow_counter *
4610 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4611                            uint32_t idx,
4612                            struct mlx5_flow_counter_pool **ppool)
4613 {
4614         struct mlx5_priv *priv = dev->data->dev_private;
4615         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4616         struct mlx5_flow_counter_pool *pool;
4617
4618         /* Decrease to original index and clear shared bit. */
4619         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4620         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4621         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4622         MLX5_ASSERT(pool);
4623         if (ppool)
4624                 *ppool = pool;
4625         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4626 }
4627
4628 /**
4629  * Check the devx counter belongs to the pool.
4630  *
4631  * @param[in] pool
4632  *   Pointer to the counter pool.
4633  * @param[in] id
4634  *   The counter devx ID.
4635  *
4636  * @return
4637  *   True if counter belongs to the pool, false otherwise.
4638  */
4639 static bool
4640 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4641 {
4642         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4643                    MLX5_COUNTERS_PER_POOL;
4644
4645         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4646                 return true;
4647         return false;
4648 }
4649
4650 /**
4651  * Get a pool by devx counter ID.
4652  *
4653  * @param[in] cmng
4654  *   Pointer to the counter management.
4655  * @param[in] id
4656  *   The counter devx ID.
4657  *
4658  * @return
4659  *   The counter pool pointer if exists, NULL otherwise,
4660  */
4661 static struct mlx5_flow_counter_pool *
4662 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4663 {
4664         uint32_t i;
4665         struct mlx5_flow_counter_pool *pool = NULL;
4666
4667         rte_spinlock_lock(&cmng->pool_update_sl);
4668         /* Check last used pool. */
4669         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4670             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4671                 pool = cmng->pools[cmng->last_pool_idx];
4672                 goto out;
4673         }
4674         /* ID out of range means no suitable pool in the container. */
4675         if (id > cmng->max_id || id < cmng->min_id)
4676                 goto out;
4677         /*
4678          * Find the pool from the end of the container, since mostly counter
4679          * ID is sequence increasing, and the last pool should be the needed
4680          * one.
4681          */
4682         i = cmng->n_valid;
4683         while (i--) {
4684                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4685
4686                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4687                         pool = pool_tmp;
4688                         break;
4689                 }
4690         }
4691 out:
4692         rte_spinlock_unlock(&cmng->pool_update_sl);
4693         return pool;
4694 }
4695
4696 /**
4697  * Resize a counter container.
4698  *
4699  * @param[in] dev
4700  *   Pointer to the Ethernet device structure.
4701  *
4702  * @return
4703  *   0 on success, otherwise negative errno value and rte_errno is set.
4704  */
4705 static int
4706 flow_dv_container_resize(struct rte_eth_dev *dev)
4707 {
4708         struct mlx5_priv *priv = dev->data->dev_private;
4709         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4710         void *old_pools = cmng->pools;
4711         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4712         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4713         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4714
4715         if (!pools) {
4716                 rte_errno = ENOMEM;
4717                 return -ENOMEM;
4718         }
4719         if (old_pools)
4720                 memcpy(pools, old_pools, cmng->n *
4721                                        sizeof(struct mlx5_flow_counter_pool *));
4722         cmng->n = resize;
4723         cmng->pools = pools;
4724         if (old_pools)
4725                 mlx5_free(old_pools);
4726         return 0;
4727 }
4728
4729 /**
4730  * Query a devx flow counter.
4731  *
4732  * @param[in] dev
4733  *   Pointer to the Ethernet device structure.
4734  * @param[in] cnt
4735  *   Index to the flow counter.
4736  * @param[out] pkts
4737  *   The statistics value of packets.
4738  * @param[out] bytes
4739  *   The statistics value of bytes.
4740  *
4741  * @return
4742  *   0 on success, otherwise a negative errno value and rte_errno is set.
4743  */
4744 static inline int
4745 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4746                      uint64_t *bytes)
4747 {
4748         struct mlx5_priv *priv = dev->data->dev_private;
4749         struct mlx5_flow_counter_pool *pool = NULL;
4750         struct mlx5_flow_counter *cnt;
4751         int offset;
4752
4753         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4754         MLX5_ASSERT(pool);
4755         if (priv->sh->cmng.counter_fallback)
4756                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4757                                         0, pkts, bytes, 0, NULL, NULL, 0);
4758         rte_spinlock_lock(&pool->sl);
4759         if (!pool->raw) {
4760                 *pkts = 0;
4761                 *bytes = 0;
4762         } else {
4763                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4764                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4765                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4766         }
4767         rte_spinlock_unlock(&pool->sl);
4768         return 0;
4769 }
4770
4771 /**
4772  * Create and initialize a new counter pool.
4773  *
4774  * @param[in] dev
4775  *   Pointer to the Ethernet device structure.
4776  * @param[out] dcs
4777  *   The devX counter handle.
4778  * @param[in] age
4779  *   Whether the pool is for counter that was allocated for aging.
4780  * @param[in/out] cont_cur
4781  *   Pointer to the container pointer, it will be update in pool resize.
4782  *
4783  * @return
4784  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4785  */
4786 static struct mlx5_flow_counter_pool *
4787 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4788                     uint32_t age)
4789 {
4790         struct mlx5_priv *priv = dev->data->dev_private;
4791         struct mlx5_flow_counter_pool *pool;
4792         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4793         bool fallback = priv->sh->cmng.counter_fallback;
4794         uint32_t size = sizeof(*pool);
4795
4796         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4797         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4798         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4799         if (!pool) {
4800                 rte_errno = ENOMEM;
4801                 return NULL;
4802         }
4803         pool->raw = NULL;
4804         pool->is_aged = !!age;
4805         pool->query_gen = 0;
4806         pool->min_dcs = dcs;
4807         rte_spinlock_init(&pool->sl);
4808         rte_spinlock_init(&pool->csl);
4809         TAILQ_INIT(&pool->counters[0]);
4810         TAILQ_INIT(&pool->counters[1]);
4811         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4812         rte_spinlock_lock(&cmng->pool_update_sl);
4813         pool->index = cmng->n_valid;
4814         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4815                 mlx5_free(pool);
4816                 rte_spinlock_unlock(&cmng->pool_update_sl);
4817                 return NULL;
4818         }
4819         cmng->pools[pool->index] = pool;
4820         cmng->n_valid++;
4821         if (unlikely(fallback)) {
4822                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4823
4824                 if (base < cmng->min_id)
4825                         cmng->min_id = base;
4826                 if (base > cmng->max_id)
4827                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4828                 cmng->last_pool_idx = pool->index;
4829         }
4830         rte_spinlock_unlock(&cmng->pool_update_sl);
4831         return pool;
4832 }
4833
4834 /**
4835  * Prepare a new counter and/or a new counter pool.
4836  *
4837  * @param[in] dev
4838  *   Pointer to the Ethernet device structure.
4839  * @param[out] cnt_free
4840  *   Where to put the pointer of a new counter.
4841  * @param[in] age
4842  *   Whether the pool is for counter that was allocated for aging.
4843  *
4844  * @return
4845  *   The counter pool pointer and @p cnt_free is set on success,
4846  *   NULL otherwise and rte_errno is set.
4847  */
4848 static struct mlx5_flow_counter_pool *
4849 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4850                              struct mlx5_flow_counter **cnt_free,
4851                              uint32_t age)
4852 {
4853         struct mlx5_priv *priv = dev->data->dev_private;
4854         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4855         struct mlx5_flow_counter_pool *pool;
4856         struct mlx5_counters tmp_tq;
4857         struct mlx5_devx_obj *dcs = NULL;
4858         struct mlx5_flow_counter *cnt;
4859         enum mlx5_counter_type cnt_type =
4860                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4861         bool fallback = priv->sh->cmng.counter_fallback;
4862         uint32_t i;
4863
4864         if (fallback) {
4865                 /* bulk_bitmap must be 0 for single counter allocation. */
4866                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4867                 if (!dcs)
4868                         return NULL;
4869                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4870                 if (!pool) {
4871                         pool = flow_dv_pool_create(dev, dcs, age);
4872                         if (!pool) {
4873                                 mlx5_devx_cmd_destroy(dcs);
4874                                 return NULL;
4875                         }
4876                 }
4877                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4878                 cnt = MLX5_POOL_GET_CNT(pool, i);
4879                 cnt->pool = pool;
4880                 cnt->dcs_when_free = dcs;
4881                 *cnt_free = cnt;
4882                 return pool;
4883         }
4884         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4885         if (!dcs) {
4886                 rte_errno = ENODATA;
4887                 return NULL;
4888         }
4889         pool = flow_dv_pool_create(dev, dcs, age);
4890         if (!pool) {
4891                 mlx5_devx_cmd_destroy(dcs);
4892                 return NULL;
4893         }
4894         TAILQ_INIT(&tmp_tq);
4895         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4896                 cnt = MLX5_POOL_GET_CNT(pool, i);
4897                 cnt->pool = pool;
4898                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4899         }
4900         rte_spinlock_lock(&cmng->csl[cnt_type]);
4901         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4902         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4903         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4904         (*cnt_free)->pool = pool;
4905         return pool;
4906 }
4907
4908 /**
4909  * Allocate a flow counter.
4910  *
4911  * @param[in] dev
4912  *   Pointer to the Ethernet device structure.
4913  * @param[in] age
4914  *   Whether the counter was allocated for aging.
4915  *
4916  * @return
4917  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4918  */
4919 static uint32_t
4920 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4921 {
4922         struct mlx5_priv *priv = dev->data->dev_private;
4923         struct mlx5_flow_counter_pool *pool = NULL;
4924         struct mlx5_flow_counter *cnt_free = NULL;
4925         bool fallback = priv->sh->cmng.counter_fallback;
4926         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4927         enum mlx5_counter_type cnt_type =
4928                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4929         uint32_t cnt_idx;
4930
4931         if (!priv->config.devx) {
4932                 rte_errno = ENOTSUP;
4933                 return 0;
4934         }
4935         /* Get free counters from container. */
4936         rte_spinlock_lock(&cmng->csl[cnt_type]);
4937         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4938         if (cnt_free)
4939                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4940         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4941         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4942                 goto err;
4943         pool = cnt_free->pool;
4944         if (fallback)
4945                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4946         /* Create a DV counter action only in the first time usage. */
4947         if (!cnt_free->action) {
4948                 uint16_t offset;
4949                 struct mlx5_devx_obj *dcs;
4950                 int ret;
4951
4952                 if (!fallback) {
4953                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4954                         dcs = pool->min_dcs;
4955                 } else {
4956                         offset = 0;
4957                         dcs = cnt_free->dcs_when_free;
4958                 }
4959                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4960                                                             &cnt_free->action);
4961                 if (ret) {
4962                         rte_errno = errno;
4963                         goto err;
4964                 }
4965         }
4966         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4967                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4968         /* Update the counter reset values. */
4969         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4970                                  &cnt_free->bytes))
4971                 goto err;
4972         if (!fallback && !priv->sh->cmng.query_thread_on)
4973                 /* Start the asynchronous batch query by the host thread. */
4974                 mlx5_set_query_alarm(priv->sh);
4975         return cnt_idx;
4976 err:
4977         if (cnt_free) {
4978                 cnt_free->pool = pool;
4979                 if (fallback)
4980                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4981                 rte_spinlock_lock(&cmng->csl[cnt_type]);
4982                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4983                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4984         }
4985         return 0;
4986 }
4987
4988 /**
4989  * Allocate a shared flow counter.
4990  *
4991  * @param[in] ctx
4992  *   Pointer to the shared counter configuration.
4993  * @param[in] data
4994  *   Pointer to save the allocated counter index.
4995  *
4996  * @return
4997  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4998  */
4999
5000 static int32_t
5001 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5002 {
5003         struct mlx5_shared_counter_conf *conf = ctx;
5004         struct rte_eth_dev *dev = conf->dev;
5005         struct mlx5_flow_counter *cnt;
5006
5007         data->dword = flow_dv_counter_alloc(dev, 0);
5008         data->dword |= MLX5_CNT_SHARED_OFFSET;
5009         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5010         cnt->shared_info.id = conf->id;
5011         return 0;
5012 }
5013
5014 /**
5015  * Get a shared flow counter.
5016  *
5017  * @param[in] dev
5018  *   Pointer to the Ethernet device structure.
5019  * @param[in] id
5020  *   Counter identifier.
5021  *
5022  * @return
5023  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5024  */
5025 static uint32_t
5026 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5027 {
5028         struct mlx5_priv *priv = dev->data->dev_private;
5029         struct mlx5_shared_counter_conf conf = {
5030                 .dev = dev,
5031                 .id = id,
5032         };
5033         union mlx5_l3t_data data = {
5034                 .dword = 0,
5035         };
5036
5037         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5038                                flow_dv_counter_alloc_shared_cb, &conf);
5039         return data.dword;
5040 }
5041
5042 /**
5043  * Get age param from counter index.
5044  *
5045  * @param[in] dev
5046  *   Pointer to the Ethernet device structure.
5047  * @param[in] counter
5048  *   Index to the counter handler.
5049  *
5050  * @return
5051  *   The aging parameter specified for the counter index.
5052  */
5053 static struct mlx5_age_param*
5054 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5055                                 uint32_t counter)
5056 {
5057         struct mlx5_flow_counter *cnt;
5058         struct mlx5_flow_counter_pool *pool = NULL;
5059
5060         flow_dv_counter_get_by_idx(dev, counter, &pool);
5061         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5062         cnt = MLX5_POOL_GET_CNT(pool, counter);
5063         return MLX5_CNT_TO_AGE(cnt);
5064 }
5065
5066 /**
5067  * Remove a flow counter from aged counter list.
5068  *
5069  * @param[in] dev
5070  *   Pointer to the Ethernet device structure.
5071  * @param[in] counter
5072  *   Index to the counter handler.
5073  * @param[in] cnt
5074  *   Pointer to the counter handler.
5075  */
5076 static void
5077 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5078                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5079 {
5080         struct mlx5_age_info *age_info;
5081         struct mlx5_age_param *age_param;
5082         struct mlx5_priv *priv = dev->data->dev_private;
5083         uint16_t expected = AGE_CANDIDATE;
5084
5085         age_info = GET_PORT_AGE_INFO(priv);
5086         age_param = flow_dv_counter_idx_get_age(dev, counter);
5087         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5088                                          AGE_FREE, false, __ATOMIC_RELAXED,
5089                                          __ATOMIC_RELAXED)) {
5090                 /**
5091                  * We need the lock even it is age timeout,
5092                  * since counter may still in process.
5093                  */
5094                 rte_spinlock_lock(&age_info->aged_sl);
5095                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5096                 rte_spinlock_unlock(&age_info->aged_sl);
5097                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5098         }
5099 }
5100
5101 /**
5102  * Release a flow counter.
5103  *
5104  * @param[in] dev
5105  *   Pointer to the Ethernet device structure.
5106  * @param[in] counter
5107  *   Index to the counter handler.
5108  */
5109 static void
5110 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
5111 {
5112         struct mlx5_priv *priv = dev->data->dev_private;
5113         struct mlx5_flow_counter_pool *pool = NULL;
5114         struct mlx5_flow_counter *cnt;
5115         enum mlx5_counter_type cnt_type;
5116
5117         if (!counter)
5118                 return;
5119         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5120         MLX5_ASSERT(pool);
5121         if (IS_SHARED_CNT(counter) &&
5122             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5123                 return;
5124         if (pool->is_aged)
5125                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5126         cnt->pool = pool;
5127         /*
5128          * Put the counter back to list to be updated in none fallback mode.
5129          * Currently, we are using two list alternately, while one is in query,
5130          * add the freed counter to the other list based on the pool query_gen
5131          * value. After query finishes, add counter the list to the global
5132          * container counter list. The list changes while query starts. In
5133          * this case, lock will not be needed as query callback and release
5134          * function both operate with the different list.
5135          *
5136          */
5137         if (!priv->sh->cmng.counter_fallback) {
5138                 rte_spinlock_lock(&pool->csl);
5139                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5140                 rte_spinlock_unlock(&pool->csl);
5141         } else {
5142                 cnt->dcs_when_free = cnt->dcs_when_active;
5143                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5144                                            MLX5_COUNTER_TYPE_ORIGIN;
5145                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5146                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5147                                   cnt, next);
5148                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5149         }
5150 }
5151
5152 /**
5153  * Verify the @p attributes will be correctly understood by the NIC and store
5154  * them in the @p flow if everything is correct.
5155  *
5156  * @param[in] dev
5157  *   Pointer to dev struct.
5158  * @param[in] attributes
5159  *   Pointer to flow attributes
5160  * @param[in] external
5161  *   This flow rule is created by request external to PMD.
5162  * @param[out] error
5163  *   Pointer to error structure.
5164  *
5165  * @return
5166  *   - 0 on success and non root table.
5167  *   - 1 on success and root table.
5168  *   - a negative errno value otherwise and rte_errno is set.
5169  */
5170 static int
5171 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5172                             const struct mlx5_flow_tunnel *tunnel,
5173                             const struct rte_flow_attr *attributes,
5174                             struct flow_grp_info grp_info,
5175                             struct rte_flow_error *error)
5176 {
5177         struct mlx5_priv *priv = dev->data->dev_private;
5178         uint32_t priority_max = priv->config.flow_prio - 1;
5179         int ret = 0;
5180
5181 #ifndef HAVE_MLX5DV_DR
5182         RTE_SET_USED(tunnel);
5183         RTE_SET_USED(grp_info);
5184         if (attributes->group)
5185                 return rte_flow_error_set(error, ENOTSUP,
5186                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5187                                           NULL,
5188                                           "groups are not supported");
5189 #else
5190         uint32_t table = 0;
5191
5192         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5193                                        grp_info, error);
5194         if (ret)
5195                 return ret;
5196         if (!table)
5197                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5198 #endif
5199         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5200             attributes->priority >= priority_max)
5201                 return rte_flow_error_set(error, ENOTSUP,
5202                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5203                                           NULL,
5204                                           "priority out of range");
5205         if (attributes->transfer) {
5206                 if (!priv->config.dv_esw_en)
5207                         return rte_flow_error_set
5208                                 (error, ENOTSUP,
5209                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5210                                  "E-Switch dr is not supported");
5211                 if (!(priv->representor || priv->master))
5212                         return rte_flow_error_set
5213                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5214                                  NULL, "E-Switch configuration can only be"
5215                                  " done by a master or a representor device");
5216                 if (attributes->egress)
5217                         return rte_flow_error_set
5218                                 (error, ENOTSUP,
5219                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5220                                  "egress is not supported");
5221         }
5222         if (!(attributes->egress ^ attributes->ingress))
5223                 return rte_flow_error_set(error, ENOTSUP,
5224                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5225                                           "must specify exactly one of "
5226                                           "ingress or egress");
5227         return ret;
5228 }
5229
5230 /**
5231  * Internal validation function. For validating both actions and items.
5232  *
5233  * @param[in] dev
5234  *   Pointer to the rte_eth_dev structure.
5235  * @param[in] attr
5236  *   Pointer to the flow attributes.
5237  * @param[in] items
5238  *   Pointer to the list of items.
5239  * @param[in] actions
5240  *   Pointer to the list of actions.
5241  * @param[in] external
5242  *   This flow rule is created by request external to PMD.
5243  * @param[in] hairpin
5244  *   Number of hairpin TX actions, 0 means classic flow.
5245  * @param[out] error
5246  *   Pointer to the error structure.
5247  *
5248  * @return
5249  *   0 on success, a negative errno value otherwise and rte_errno is set.
5250  */
5251 static int
5252 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5253                  const struct rte_flow_item items[],
5254                  const struct rte_flow_action actions[],
5255                  bool external, int hairpin, struct rte_flow_error *error)
5256 {
5257         int ret;
5258         uint64_t action_flags = 0;
5259         uint64_t item_flags = 0;
5260         uint64_t last_item = 0;
5261         uint8_t next_protocol = 0xff;
5262         uint16_t ether_type = 0;
5263         int actions_n = 0;
5264         uint8_t item_ipv6_proto = 0;
5265         const struct rte_flow_item *gre_item = NULL;
5266         const struct rte_flow_action_raw_decap *decap;
5267         const struct rte_flow_action_raw_encap *encap;
5268         const struct rte_flow_action_rss *rss;
5269         const struct rte_flow_item_tcp nic_tcp_mask = {
5270                 .hdr = {
5271                         .tcp_flags = 0xFF,
5272                         .src_port = RTE_BE16(UINT16_MAX),
5273                         .dst_port = RTE_BE16(UINT16_MAX),
5274                 }
5275         };
5276         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5277                 .hdr = {
5278                         .src_addr =
5279                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5280                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5281                         .dst_addr =
5282                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5283                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5284                         .vtc_flow = RTE_BE32(0xffffffff),
5285                         .proto = 0xff,
5286                         .hop_limits = 0xff,
5287                 },
5288                 .has_frag_ext = 1,
5289         };
5290         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5291                 .hdr = {
5292                         .common = {
5293                                 .u32 =
5294                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5295                                         .type = 0xFF,
5296                                         }).u32),
5297                         },
5298                         .dummy[0] = 0xffffffff,
5299                 },
5300         };
5301         struct mlx5_priv *priv = dev->data->dev_private;
5302         struct mlx5_dev_config *dev_conf = &priv->config;
5303         uint16_t queue_index = 0xFFFF;
5304         const struct rte_flow_item_vlan *vlan_m = NULL;
5305         int16_t rw_act_num = 0;
5306         uint64_t is_root;
5307         const struct mlx5_flow_tunnel *tunnel;
5308         struct flow_grp_info grp_info = {
5309                 .external = !!external,
5310                 .transfer = !!attr->transfer,
5311                 .fdb_def_rule = !!priv->fdb_def_rule,
5312         };
5313
5314         if (items == NULL)
5315                 return -1;
5316         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5317                 tunnel = flow_items_to_tunnel(items);
5318                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5319                                 MLX5_FLOW_ACTION_DECAP;
5320         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5321                 tunnel = flow_actions_to_tunnel(actions);
5322                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5323         } else {
5324                 tunnel = NULL;
5325         }
5326         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5327                                 (dev, tunnel, attr, items, actions);
5328         ret = flow_dv_validate_attributes(dev, tunnel, attr, grp_info, error);
5329         if (ret < 0)
5330                 return ret;
5331         is_root = (uint64_t)ret;
5332         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5333                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5334                 int type = items->type;
5335
5336                 if (!mlx5_flow_os_item_supported(type))
5337                         return rte_flow_error_set(error, ENOTSUP,
5338                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5339                                                   NULL, "item not supported");
5340                 switch (type) {
5341                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5342                         if (items[0].type != (typeof(items[0].type))
5343                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5344                                 return rte_flow_error_set
5345                                                 (error, EINVAL,
5346                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5347                                                 NULL, "MLX5 private items "
5348                                                 "must be the first");
5349                         break;
5350                 case RTE_FLOW_ITEM_TYPE_VOID:
5351                         break;
5352                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5353                         ret = flow_dv_validate_item_port_id
5354                                         (dev, items, attr, item_flags, error);
5355                         if (ret < 0)
5356                                 return ret;
5357                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5358                         break;
5359                 case RTE_FLOW_ITEM_TYPE_ETH:
5360                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5361                                                           error);
5362                         if (ret < 0)
5363                                 return ret;
5364                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5365                                              MLX5_FLOW_LAYER_OUTER_L2;
5366                         if (items->mask != NULL && items->spec != NULL) {
5367                                 ether_type =
5368                                         ((const struct rte_flow_item_eth *)
5369                                          items->spec)->type;
5370                                 ether_type &=
5371                                         ((const struct rte_flow_item_eth *)
5372                                          items->mask)->type;
5373                                 ether_type = rte_be_to_cpu_16(ether_type);
5374                         } else {
5375                                 ether_type = 0;
5376                         }
5377                         break;
5378                 case RTE_FLOW_ITEM_TYPE_VLAN:
5379                         ret = flow_dv_validate_item_vlan(items, item_flags,
5380                                                          dev, error);
5381                         if (ret < 0)
5382                                 return ret;
5383                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5384                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5385                         if (items->mask != NULL && items->spec != NULL) {
5386                                 ether_type =
5387                                         ((const struct rte_flow_item_vlan *)
5388                                          items->spec)->inner_type;
5389                                 ether_type &=
5390                                         ((const struct rte_flow_item_vlan *)
5391                                          items->mask)->inner_type;
5392                                 ether_type = rte_be_to_cpu_16(ether_type);
5393                         } else {
5394                                 ether_type = 0;
5395                         }
5396                         /* Store outer VLAN mask for of_push_vlan action. */
5397                         if (!tunnel)
5398                                 vlan_m = items->mask;
5399                         break;
5400                 case RTE_FLOW_ITEM_TYPE_IPV4:
5401                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5402                                                   &item_flags, &tunnel);
5403                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5404                                                          last_item, ether_type,
5405                                                          error);
5406                         if (ret < 0)
5407                                 return ret;
5408                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5409                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5410                         if (items->mask != NULL &&
5411                             ((const struct rte_flow_item_ipv4 *)
5412                              items->mask)->hdr.next_proto_id) {
5413                                 next_protocol =
5414                                         ((const struct rte_flow_item_ipv4 *)
5415                                          (items->spec))->hdr.next_proto_id;
5416                                 next_protocol &=
5417                                         ((const struct rte_flow_item_ipv4 *)
5418                                          (items->mask))->hdr.next_proto_id;
5419                         } else {
5420                                 /* Reset for inner layer. */
5421                                 next_protocol = 0xff;
5422                         }
5423                         break;
5424                 case RTE_FLOW_ITEM_TYPE_IPV6:
5425                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5426                                                   &item_flags, &tunnel);
5427                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5428                                                            last_item,
5429                                                            ether_type,
5430                                                            &nic_ipv6_mask,
5431                                                            error);
5432                         if (ret < 0)
5433                                 return ret;
5434                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5435                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5436                         if (items->mask != NULL &&
5437                             ((const struct rte_flow_item_ipv6 *)
5438                              items->mask)->hdr.proto) {
5439                                 item_ipv6_proto =
5440                                         ((const struct rte_flow_item_ipv6 *)
5441                                          items->spec)->hdr.proto;
5442                                 next_protocol =
5443                                         ((const struct rte_flow_item_ipv6 *)
5444                                          items->spec)->hdr.proto;
5445                                 next_protocol &=
5446                                         ((const struct rte_flow_item_ipv6 *)
5447                                          items->mask)->hdr.proto;
5448                         } else {
5449                                 /* Reset for inner layer. */
5450                                 next_protocol = 0xff;
5451                         }
5452                         break;
5453                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5454                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5455                                                                   item_flags,
5456                                                                   error);
5457                         if (ret < 0)
5458                                 return ret;
5459                         last_item = tunnel ?
5460                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5461                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5462                         if (items->mask != NULL &&
5463                             ((const struct rte_flow_item_ipv6_frag_ext *)
5464                              items->mask)->hdr.next_header) {
5465                                 next_protocol =
5466                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5467                                  items->spec)->hdr.next_header;
5468                                 next_protocol &=
5469                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5470                                  items->mask)->hdr.next_header;
5471                         } else {
5472                                 /* Reset for inner layer. */
5473                                 next_protocol = 0xff;
5474                         }
5475                         break;
5476                 case RTE_FLOW_ITEM_TYPE_TCP:
5477                         ret = mlx5_flow_validate_item_tcp
5478                                                 (items, item_flags,
5479                                                  next_protocol,
5480                                                  &nic_tcp_mask,
5481                                                  error);
5482                         if (ret < 0)
5483                                 return ret;
5484                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5485                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5486                         break;
5487                 case RTE_FLOW_ITEM_TYPE_UDP:
5488                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5489                                                           next_protocol,
5490                                                           error);
5491                         if (ret < 0)
5492                                 return ret;
5493                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5494                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5495                         break;
5496                 case RTE_FLOW_ITEM_TYPE_GRE:
5497                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5498                                                           next_protocol, error);
5499                         if (ret < 0)
5500                                 return ret;
5501                         gre_item = items;
5502                         last_item = MLX5_FLOW_LAYER_GRE;
5503                         break;
5504                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5505                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5506                                                             next_protocol,
5507                                                             error);
5508                         if (ret < 0)
5509                                 return ret;
5510                         last_item = MLX5_FLOW_LAYER_NVGRE;
5511                         break;
5512                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5513                         ret = mlx5_flow_validate_item_gre_key
5514                                 (items, item_flags, gre_item, error);
5515                         if (ret < 0)
5516                                 return ret;
5517                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5518                         break;
5519                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5520                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5521                                                             error);
5522                         if (ret < 0)
5523                                 return ret;
5524                         last_item = MLX5_FLOW_LAYER_VXLAN;
5525                         break;
5526                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5527                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5528                                                                 item_flags, dev,
5529                                                                 error);
5530                         if (ret < 0)
5531                                 return ret;
5532                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5533                         break;
5534                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5535                         ret = mlx5_flow_validate_item_geneve(items,
5536                                                              item_flags, dev,
5537                                                              error);
5538                         if (ret < 0)
5539                                 return ret;
5540                         last_item = MLX5_FLOW_LAYER_GENEVE;
5541                         break;
5542                 case RTE_FLOW_ITEM_TYPE_MPLS:
5543                         ret = mlx5_flow_validate_item_mpls(dev, items,
5544                                                            item_flags,
5545                                                            last_item, error);
5546                         if (ret < 0)
5547                                 return ret;
5548                         last_item = MLX5_FLOW_LAYER_MPLS;
5549                         break;
5550
5551                 case RTE_FLOW_ITEM_TYPE_MARK:
5552                         ret = flow_dv_validate_item_mark(dev, items, attr,
5553                                                          error);
5554                         if (ret < 0)
5555                                 return ret;
5556                         last_item = MLX5_FLOW_ITEM_MARK;
5557                         break;
5558                 case RTE_FLOW_ITEM_TYPE_META:
5559                         ret = flow_dv_validate_item_meta(dev, items, attr,
5560                                                          error);
5561                         if (ret < 0)
5562                                 return ret;
5563                         last_item = MLX5_FLOW_ITEM_METADATA;
5564                         break;
5565                 case RTE_FLOW_ITEM_TYPE_ICMP:
5566                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5567                                                            next_protocol,
5568                                                            error);
5569                         if (ret < 0)
5570                                 return ret;
5571                         last_item = MLX5_FLOW_LAYER_ICMP;
5572                         break;
5573                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5574                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5575                                                             next_protocol,
5576                                                             error);
5577                         if (ret < 0)
5578                                 return ret;
5579                         item_ipv6_proto = IPPROTO_ICMPV6;
5580                         last_item = MLX5_FLOW_LAYER_ICMP6;
5581                         break;
5582                 case RTE_FLOW_ITEM_TYPE_TAG:
5583                         ret = flow_dv_validate_item_tag(dev, items,
5584                                                         attr, error);
5585                         if (ret < 0)
5586                                 return ret;
5587                         last_item = MLX5_FLOW_ITEM_TAG;
5588                         break;
5589                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5590                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5591                         break;
5592                 case RTE_FLOW_ITEM_TYPE_GTP:
5593                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5594                                                         error);
5595                         if (ret < 0)
5596                                 return ret;
5597                         last_item = MLX5_FLOW_LAYER_GTP;
5598                         break;
5599                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5600                         /* Capacity will be checked in the translate stage. */
5601                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5602                                                             last_item,
5603                                                             ether_type,
5604                                                             &nic_ecpri_mask,
5605                                                             error);
5606                         if (ret < 0)
5607                                 return ret;
5608                         last_item = MLX5_FLOW_LAYER_ECPRI;
5609                         break;
5610                 default:
5611                         return rte_flow_error_set(error, ENOTSUP,
5612                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5613                                                   NULL, "item not supported");
5614                 }
5615                 item_flags |= last_item;
5616         }
5617         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5618                 int type = actions->type;
5619
5620                 if (!mlx5_flow_os_action_supported(type))
5621                         return rte_flow_error_set(error, ENOTSUP,
5622                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5623                                                   actions,
5624                                                   "action not supported");
5625                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5626                         return rte_flow_error_set(error, ENOTSUP,
5627                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5628                                                   actions, "too many actions");
5629                 switch (type) {
5630                 case RTE_FLOW_ACTION_TYPE_VOID:
5631                         break;
5632                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5633                         ret = flow_dv_validate_action_port_id(dev,
5634                                                               action_flags,
5635                                                               actions,
5636                                                               attr,
5637                                                               error);
5638                         if (ret)
5639                                 return ret;
5640                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5641                         ++actions_n;
5642                         break;
5643                 case RTE_FLOW_ACTION_TYPE_FLAG:
5644                         ret = flow_dv_validate_action_flag(dev, action_flags,
5645                                                            attr, error);
5646                         if (ret < 0)
5647                                 return ret;
5648                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5649                                 /* Count all modify-header actions as one. */
5650                                 if (!(action_flags &
5651                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5652                                         ++actions_n;
5653                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5654                                                 MLX5_FLOW_ACTION_MARK_EXT;
5655                         } else {
5656                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5657                                 ++actions_n;
5658                         }
5659                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5660                         break;
5661                 case RTE_FLOW_ACTION_TYPE_MARK:
5662                         ret = flow_dv_validate_action_mark(dev, actions,
5663                                                            action_flags,
5664                                                            attr, error);
5665                         if (ret < 0)
5666                                 return ret;
5667                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5668                                 /* Count all modify-header actions as one. */
5669                                 if (!(action_flags &
5670                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5671                                         ++actions_n;
5672                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5673                                                 MLX5_FLOW_ACTION_MARK_EXT;
5674                         } else {
5675                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5676                                 ++actions_n;
5677                         }
5678                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5679                         break;
5680                 case RTE_FLOW_ACTION_TYPE_SET_META:
5681                         ret = flow_dv_validate_action_set_meta(dev, actions,
5682                                                                action_flags,
5683                                                                attr, error);
5684                         if (ret < 0)
5685                                 return ret;
5686                         /* Count all modify-header actions as one action. */
5687                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5688                                 ++actions_n;
5689                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5690                         rw_act_num += MLX5_ACT_NUM_SET_META;
5691                         break;
5692                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5693                         ret = flow_dv_validate_action_set_tag(dev, actions,
5694                                                               action_flags,
5695                                                               attr, error);
5696                         if (ret < 0)
5697                                 return ret;
5698                         /* Count all modify-header actions as one action. */
5699                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5700                                 ++actions_n;
5701                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5702                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5703                         break;
5704                 case RTE_FLOW_ACTION_TYPE_DROP:
5705                         ret = mlx5_flow_validate_action_drop(action_flags,
5706                                                              attr, error);
5707                         if (ret < 0)
5708                                 return ret;
5709                         action_flags |= MLX5_FLOW_ACTION_DROP;
5710                         ++actions_n;
5711                         break;
5712                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5713                         ret = mlx5_flow_validate_action_queue(actions,
5714                                                               action_flags, dev,
5715                                                               attr, error);
5716                         if (ret < 0)
5717                                 return ret;
5718                         queue_index = ((const struct rte_flow_action_queue *)
5719                                                         (actions->conf))->index;
5720                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5721                         ++actions_n;
5722                         break;
5723                 case RTE_FLOW_ACTION_TYPE_RSS:
5724                         rss = actions->conf;
5725                         ret = mlx5_flow_validate_action_rss(actions,
5726                                                             action_flags, dev,
5727                                                             attr, item_flags,
5728                                                             error);
5729                         if (ret < 0)
5730                                 return ret;
5731                         if (rss != NULL && rss->queue_num)
5732                                 queue_index = rss->queue[0];
5733                         action_flags |= MLX5_FLOW_ACTION_RSS;
5734                         ++actions_n;
5735                         break;
5736                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5737                         ret =
5738                         mlx5_flow_validate_action_default_miss(action_flags,
5739                                         attr, error);
5740                         if (ret < 0)
5741                                 return ret;
5742                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5743                         ++actions_n;
5744                         break;
5745                 case RTE_FLOW_ACTION_TYPE_COUNT:
5746                         ret = flow_dv_validate_action_count(dev, error);
5747                         if (ret < 0)
5748                                 return ret;
5749                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5750                         ++actions_n;
5751                         break;
5752                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5753                         if (flow_dv_validate_action_pop_vlan(dev,
5754                                                              action_flags,
5755                                                              actions,
5756                                                              item_flags, attr,
5757                                                              error))
5758                                 return -rte_errno;
5759                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5760                         ++actions_n;
5761                         break;
5762                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5763                         ret = flow_dv_validate_action_push_vlan(dev,
5764                                                                 action_flags,
5765                                                                 vlan_m,
5766                                                                 actions, attr,
5767                                                                 error);
5768                         if (ret < 0)
5769                                 return ret;
5770                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5771                         ++actions_n;
5772                         break;
5773                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5774                         ret = flow_dv_validate_action_set_vlan_pcp
5775                                                 (action_flags, actions, error);
5776                         if (ret < 0)
5777                                 return ret;
5778                         /* Count PCP with push_vlan command. */
5779                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5780                         break;
5781                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5782                         ret = flow_dv_validate_action_set_vlan_vid
5783                                                 (item_flags, action_flags,
5784                                                  actions, error);
5785                         if (ret < 0)
5786                                 return ret;
5787                         /* Count VID with push_vlan command. */
5788                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5789                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5790                         break;
5791                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5792                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5793                         ret = flow_dv_validate_action_l2_encap(dev,
5794                                                                action_flags,
5795                                                                actions, attr,
5796                                                                error);
5797                         if (ret < 0)
5798                                 return ret;
5799                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5800                         ++actions_n;
5801                         break;
5802                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5803                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5804                         ret = flow_dv_validate_action_decap(dev, action_flags,
5805                                                             attr, error);
5806                         if (ret < 0)
5807                                 return ret;
5808                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5809                         ++actions_n;
5810                         break;
5811                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5812                         ret = flow_dv_validate_action_raw_encap_decap
5813                                 (dev, NULL, actions->conf, attr, &action_flags,
5814                                  &actions_n, error);
5815                         if (ret < 0)
5816                                 return ret;
5817                         break;
5818                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5819                         decap = actions->conf;
5820                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5821                                 ;
5822                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5823                                 encap = NULL;
5824                                 actions--;
5825                         } else {
5826                                 encap = actions->conf;
5827                         }
5828                         ret = flow_dv_validate_action_raw_encap_decap
5829                                            (dev,
5830                                             decap ? decap : &empty_decap, encap,
5831                                             attr, &action_flags, &actions_n,
5832                                             error);
5833                         if (ret < 0)
5834                                 return ret;
5835                         break;
5836                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5837                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5838                         ret = flow_dv_validate_action_modify_mac(action_flags,
5839                                                                  actions,
5840                                                                  item_flags,
5841                                                                  error);
5842                         if (ret < 0)
5843                                 return ret;
5844                         /* Count all modify-header actions as one action. */
5845                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5846                                 ++actions_n;
5847                         action_flags |= actions->type ==
5848                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5849                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5850                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5851                         /*
5852                          * Even if the source and destination MAC addresses have
5853                          * overlap in the header with 4B alignment, the convert
5854                          * function will handle them separately and 4 SW actions
5855                          * will be created. And 2 actions will be added each
5856                          * time no matter how many bytes of address will be set.
5857                          */
5858                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5859                         break;
5860                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5861                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5862                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5863                                                                   actions,
5864                                                                   item_flags,
5865                                                                   error);
5866                         if (ret < 0)
5867                                 return ret;
5868                         /* Count all modify-header actions as one action. */
5869                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5870                                 ++actions_n;
5871                         action_flags |= actions->type ==
5872                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5873                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5874                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5875                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5876                         break;
5877                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5878                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5879                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5880                                                                   actions,
5881                                                                   item_flags,
5882                                                                   error);
5883                         if (ret < 0)
5884                                 return ret;
5885                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5886                                 return rte_flow_error_set(error, ENOTSUP,
5887                                         RTE_FLOW_ERROR_TYPE_ACTION,
5888                                         actions,
5889                                         "Can't change header "
5890                                         "with ICMPv6 proto");
5891                         /* Count all modify-header actions as one action. */
5892                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5893                                 ++actions_n;
5894                         action_flags |= actions->type ==
5895                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5896                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5897                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5898                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5899                         break;
5900                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5901                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5902                         ret = flow_dv_validate_action_modify_tp(action_flags,
5903                                                                 actions,
5904                                                                 item_flags,
5905                                                                 error);
5906                         if (ret < 0)
5907                                 return ret;
5908                         /* Count all modify-header actions as one action. */
5909                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5910                                 ++actions_n;
5911                         action_flags |= actions->type ==
5912                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5913                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5914                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5915                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5916                         break;
5917                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5918                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5919                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5920                                                                  actions,
5921                                                                  item_flags,
5922                                                                  error);
5923                         if (ret < 0)
5924                                 return ret;
5925                         /* Count all modify-header actions as one action. */
5926                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5927                                 ++actions_n;
5928                         action_flags |= actions->type ==
5929                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5930                                                 MLX5_FLOW_ACTION_SET_TTL :
5931                                                 MLX5_FLOW_ACTION_DEC_TTL;
5932                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5933                         break;
5934                 case RTE_FLOW_ACTION_TYPE_JUMP:
5935                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5936                                                            action_flags,
5937                                                            attr, external,
5938                                                            error);
5939                         if (ret)
5940                                 return ret;
5941                         ++actions_n;
5942                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5943                         break;
5944                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5945                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5946                         ret = flow_dv_validate_action_modify_tcp_seq
5947                                                                 (action_flags,
5948                                                                  actions,
5949                                                                  item_flags,
5950                                                                  error);
5951                         if (ret < 0)
5952                                 return ret;
5953                         /* Count all modify-header actions as one action. */
5954                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5955                                 ++actions_n;
5956                         action_flags |= actions->type ==
5957                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5958                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5959                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5960                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5961                         break;
5962                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5963                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5964                         ret = flow_dv_validate_action_modify_tcp_ack
5965                                                                 (action_flags,
5966                                                                  actions,
5967                                                                  item_flags,
5968                                                                  error);
5969                         if (ret < 0)
5970                                 return ret;
5971                         /* Count all modify-header actions as one action. */
5972                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5973                                 ++actions_n;
5974                         action_flags |= actions->type ==
5975                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5976                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5977                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5978                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5979                         break;
5980                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5981                         break;
5982                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5983                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5984                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5985                         break;
5986                 case RTE_FLOW_ACTION_TYPE_METER:
5987                         ret = mlx5_flow_validate_action_meter(dev,
5988                                                               action_flags,
5989                                                               actions, attr,
5990                                                               error);
5991                         if (ret < 0)
5992                                 return ret;
5993                         action_flags |= MLX5_FLOW_ACTION_METER;
5994                         ++actions_n;
5995                         /* Meter action will add one more TAG action. */
5996                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5997                         break;
5998                 case RTE_FLOW_ACTION_TYPE_AGE:
5999                         ret = flow_dv_validate_action_age(action_flags,
6000                                                           actions, dev,
6001                                                           error);
6002                         if (ret < 0)
6003                                 return ret;
6004                         action_flags |= MLX5_FLOW_ACTION_AGE;
6005                         ++actions_n;
6006                         break;
6007                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6008                         ret = flow_dv_validate_action_modify_ipv4_dscp
6009                                                          (action_flags,
6010                                                           actions,
6011                                                           item_flags,
6012                                                           error);
6013                         if (ret < 0)
6014                                 return ret;
6015                         /* Count all modify-header actions as one action. */
6016                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6017                                 ++actions_n;
6018                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6019                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6020                         break;
6021                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6022                         ret = flow_dv_validate_action_modify_ipv6_dscp
6023                                                                 (action_flags,
6024                                                                  actions,
6025                                                                  item_flags,
6026                                                                  error);
6027                         if (ret < 0)
6028                                 return ret;
6029                         /* Count all modify-header actions as one action. */
6030                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6031                                 ++actions_n;
6032                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6033                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6034                         break;
6035                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6036                         ret = flow_dv_validate_action_sample(action_flags,
6037                                                              actions, dev,
6038                                                              attr, error);
6039                         if (ret < 0)
6040                                 return ret;
6041                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6042                         ++actions_n;
6043                         break;
6044                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6045                         if (actions[0].type != (typeof(actions[0].type))
6046                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6047                                 return rte_flow_error_set
6048                                                 (error, EINVAL,
6049                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6050                                                 NULL, "MLX5 private action "
6051                                                 "must be the first");
6052
6053                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6054                         break;
6055                 default:
6056                         return rte_flow_error_set(error, ENOTSUP,
6057                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6058                                                   actions,
6059                                                   "action not supported");
6060                 }
6061         }
6062         /*
6063          * Validate actions in flow rules
6064          * - Explicit decap action is prohibited by the tunnel offload API.
6065          * - Drop action in tunnel steer rule is prohibited by the API.
6066          * - Application cannot use MARK action because it's value can mask
6067          *   tunnel default miss nitification.
6068          * - JUMP in tunnel match rule has no support in current PMD
6069          *   implementation.
6070          * - TAG & META are reserved for future uses.
6071          */
6072         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6073                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6074                                             MLX5_FLOW_ACTION_MARK     |
6075                                             MLX5_FLOW_ACTION_SET_TAG  |
6076                                             MLX5_FLOW_ACTION_SET_META |
6077                                             MLX5_FLOW_ACTION_DROP;
6078
6079                 if (action_flags & bad_actions_mask)
6080                         return rte_flow_error_set
6081                                         (error, EINVAL,
6082                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6083                                         "Invalid RTE action in tunnel "
6084                                         "set decap rule");
6085                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6086                         return rte_flow_error_set
6087                                         (error, EINVAL,
6088                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6089                                         "tunnel set decap rule must terminate "
6090                                         "with JUMP");
6091                 if (!attr->ingress)
6092                         return rte_flow_error_set
6093                                         (error, EINVAL,
6094                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6095                                         "tunnel flows for ingress traffic only");
6096         }
6097         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6098                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6099                                             MLX5_FLOW_ACTION_MARK    |
6100                                             MLX5_FLOW_ACTION_SET_TAG |
6101                                             MLX5_FLOW_ACTION_SET_META;
6102
6103                 if (action_flags & bad_actions_mask)
6104                         return rte_flow_error_set
6105                                         (error, EINVAL,
6106                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6107                                         "Invalid RTE action in tunnel "
6108                                         "set match rule");
6109         }
6110         /*
6111          * Validate the drop action mutual exclusion with other actions.
6112          * Drop action is mutually-exclusive with any other action, except for
6113          * Count action.
6114          */
6115         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6116             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6117                 return rte_flow_error_set(error, EINVAL,
6118                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6119                                           "Drop action is mutually-exclusive "
6120                                           "with any other action, except for "
6121                                           "Count action");
6122         /* Eswitch has few restrictions on using items and actions */
6123         if (attr->transfer) {
6124                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6125                     action_flags & MLX5_FLOW_ACTION_FLAG)
6126                         return rte_flow_error_set(error, ENOTSUP,
6127                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6128                                                   NULL,
6129                                                   "unsupported action FLAG");
6130                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6131                     action_flags & MLX5_FLOW_ACTION_MARK)
6132                         return rte_flow_error_set(error, ENOTSUP,
6133                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6134                                                   NULL,
6135                                                   "unsupported action MARK");
6136                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6137                         return rte_flow_error_set(error, ENOTSUP,
6138                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6139                                                   NULL,
6140                                                   "unsupported action QUEUE");
6141                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6142                         return rte_flow_error_set(error, ENOTSUP,
6143                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6144                                                   NULL,
6145                                                   "unsupported action RSS");
6146                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6147                         return rte_flow_error_set(error, EINVAL,
6148                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6149                                                   actions,
6150                                                   "no fate action is found");
6151         } else {
6152                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6153                         return rte_flow_error_set(error, EINVAL,
6154                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6155                                                   actions,
6156                                                   "no fate action is found");
6157         }
6158         /* Continue validation for Xcap and VLAN actions.*/
6159         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6160                              MLX5_FLOW_VLAN_ACTIONS)) &&
6161             (queue_index == 0xFFFF ||
6162              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
6163                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6164                     MLX5_FLOW_XCAP_ACTIONS)
6165                         return rte_flow_error_set(error, ENOTSUP,
6166                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6167                                                   NULL, "encap and decap "
6168                                                   "combination aren't supported");
6169                 if (!attr->transfer && attr->ingress) {
6170                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6171                                 return rte_flow_error_set
6172                                                 (error, ENOTSUP,
6173                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6174                                                  NULL, "encap is not supported"
6175                                                  " for ingress traffic");
6176                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6177                                 return rte_flow_error_set
6178                                                 (error, ENOTSUP,
6179                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6180                                                  NULL, "push VLAN action not "
6181                                                  "supported for ingress");
6182                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6183                                         MLX5_FLOW_VLAN_ACTIONS)
6184                                 return rte_flow_error_set
6185                                                 (error, ENOTSUP,
6186                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6187                                                  NULL, "no support for "
6188                                                  "multiple VLAN actions");
6189                 }
6190         }
6191         /* Hairpin flow will add one more TAG action. */
6192         if (hairpin > 0)
6193                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6194         /* extra metadata enabled: one more TAG action will be add. */
6195         if (dev_conf->dv_flow_en &&
6196             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6197             mlx5_flow_ext_mreg_supported(dev))
6198                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6199         if ((uint32_t)rw_act_num >
6200                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6201                 return rte_flow_error_set(error, ENOTSUP,
6202                                           RTE_FLOW_ERROR_TYPE_ACTION,
6203                                           NULL, "too many header modify"
6204                                           " actions to support");
6205         }
6206         return 0;
6207 }
6208
6209 /**
6210  * Internal preparation function. Allocates the DV flow size,
6211  * this size is constant.
6212  *
6213  * @param[in] dev
6214  *   Pointer to the rte_eth_dev structure.
6215  * @param[in] attr
6216  *   Pointer to the flow attributes.
6217  * @param[in] items
6218  *   Pointer to the list of items.
6219  * @param[in] actions
6220  *   Pointer to the list of actions.
6221  * @param[out] error
6222  *   Pointer to the error structure.
6223  *
6224  * @return
6225  *   Pointer to mlx5_flow object on success,
6226  *   otherwise NULL and rte_errno is set.
6227  */
6228 static struct mlx5_flow *
6229 flow_dv_prepare(struct rte_eth_dev *dev,
6230                 const struct rte_flow_attr *attr __rte_unused,
6231                 const struct rte_flow_item items[] __rte_unused,
6232                 const struct rte_flow_action actions[] __rte_unused,
6233                 struct rte_flow_error *error)
6234 {
6235         uint32_t handle_idx = 0;
6236         struct mlx5_flow *dev_flow;
6237         struct mlx5_flow_handle *dev_handle;
6238         struct mlx5_priv *priv = dev->data->dev_private;
6239
6240         /* In case of corrupting the memory. */
6241         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6242                 rte_flow_error_set(error, ENOSPC,
6243                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6244                                    "not free temporary device flow");
6245                 return NULL;
6246         }
6247         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6248                                    &handle_idx);
6249         if (!dev_handle) {
6250                 rte_flow_error_set(error, ENOMEM,
6251                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6252                                    "not enough memory to create flow handle");
6253                 return NULL;
6254         }
6255         /* No multi-thread supporting. */
6256         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
6257         dev_flow->handle = dev_handle;
6258         dev_flow->handle_idx = handle_idx;
6259         /*
6260          * In some old rdma-core releases, before continuing, a check of the
6261          * length of matching parameter will be done at first. It needs to use
6262          * the length without misc4 param. If the flow has misc4 support, then
6263          * the length needs to be adjusted accordingly. Each param member is
6264          * aligned with a 64B boundary naturally.
6265          */
6266         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6267                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6268         /*
6269          * The matching value needs to be cleared to 0 before using. In the
6270          * past, it will be automatically cleared when using rte_*alloc
6271          * API. The time consumption will be almost the same as before.
6272          */
6273         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6274         dev_flow->ingress = attr->ingress;
6275         dev_flow->dv.transfer = attr->transfer;
6276         return dev_flow;
6277 }
6278
6279 #ifdef RTE_LIBRTE_MLX5_DEBUG
6280 /**
6281  * Sanity check for match mask and value. Similar to check_valid_spec() in
6282  * kernel driver. If unmasked bit is present in value, it returns failure.
6283  *
6284  * @param match_mask
6285  *   pointer to match mask buffer.
6286  * @param match_value
6287  *   pointer to match value buffer.
6288  *
6289  * @return
6290  *   0 if valid, -EINVAL otherwise.
6291  */
6292 static int
6293 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6294 {
6295         uint8_t *m = match_mask;
6296         uint8_t *v = match_value;
6297         unsigned int i;
6298
6299         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6300                 if (v[i] & ~m[i]) {
6301                         DRV_LOG(ERR,
6302                                 "match_value differs from match_criteria"
6303                                 " %p[%u] != %p[%u]",
6304                                 match_value, i, match_mask, i);
6305                         return -EINVAL;
6306                 }
6307         }
6308         return 0;
6309 }
6310 #endif
6311
6312 /**
6313  * Add match of ip_version.
6314  *
6315  * @param[in] group
6316  *   Flow group.
6317  * @param[in] headers_v
6318  *   Values header pointer.
6319  * @param[in] headers_m
6320  *   Masks header pointer.
6321  * @param[in] ip_version
6322  *   The IP version to set.
6323  */
6324 static inline void
6325 flow_dv_set_match_ip_version(uint32_t group,
6326                              void *headers_v,
6327                              void *headers_m,
6328                              uint8_t ip_version)
6329 {
6330         if (group == 0)
6331                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6332         else
6333                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6334                          ip_version);
6335         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6336         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6337         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6338 }
6339
6340 /**
6341  * Add Ethernet item to matcher and to the value.
6342  *
6343  * @param[in, out] matcher
6344  *   Flow matcher.
6345  * @param[in, out] key
6346  *   Flow matcher value.
6347  * @param[in] item
6348  *   Flow pattern to translate.
6349  * @param[in] inner
6350  *   Item is inner pattern.
6351  */
6352 static void
6353 flow_dv_translate_item_eth(void *matcher, void *key,
6354                            const struct rte_flow_item *item, int inner,
6355                            uint32_t group)
6356 {
6357         const struct rte_flow_item_eth *eth_m = item->mask;
6358         const struct rte_flow_item_eth *eth_v = item->spec;
6359         const struct rte_flow_item_eth nic_mask = {
6360                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6361                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6362                 .type = RTE_BE16(0xffff),
6363         };
6364         void *headers_m;
6365         void *headers_v;
6366         char *l24_v;
6367         unsigned int i;
6368
6369         if (!eth_v)
6370                 return;
6371         if (!eth_m)
6372                 eth_m = &nic_mask;
6373         if (inner) {
6374                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6375                                          inner_headers);
6376                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6377         } else {
6378                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6379                                          outer_headers);
6380                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6381         }
6382         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
6383                &eth_m->dst, sizeof(eth_m->dst));
6384         /* The value must be in the range of the mask. */
6385         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
6386         for (i = 0; i < sizeof(eth_m->dst); ++i)
6387                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6388         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
6389                &eth_m->src, sizeof(eth_m->src));
6390         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
6391         /* The value must be in the range of the mask. */
6392         for (i = 0; i < sizeof(eth_m->dst); ++i)
6393                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6394         if (eth_v->type) {
6395                 /* When ethertype is present set mask for tagged VLAN. */
6396                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6397                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
6398                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
6399                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
6400                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
6401                                  1);
6402                         /* Return here to avoid setting match on ethertype. */
6403                         return;
6404                 }
6405         }
6406         /*
6407          * HW supports match on one Ethertype, the Ethertype following the last
6408          * VLAN tag of the packet (see PRM).
6409          * Set match on ethertype only if ETH header is not followed by VLAN.
6410          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6411          * ethertype, and use ip_version field instead.
6412          * eCPRI over Ether layer will use type value 0xAEFE.
6413          */
6414         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6415             eth_m->type == 0xFFFF) {
6416                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6417         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6418                    eth_m->type == 0xFFFF) {
6419                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6420         } else {
6421                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6422                          rte_be_to_cpu_16(eth_m->type));
6423                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6424                                      ethertype);
6425                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6426         }
6427 }
6428
6429 /**
6430  * Add VLAN item to matcher and to the value.
6431  *
6432  * @param[in, out] dev_flow
6433  *   Flow descriptor.
6434  * @param[in, out] matcher
6435  *   Flow matcher.
6436  * @param[in, out] key
6437  *   Flow matcher value.
6438  * @param[in] item
6439  *   Flow pattern to translate.
6440  * @param[in] inner
6441  *   Item is inner pattern.
6442  */
6443 static void
6444 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6445                             void *matcher, void *key,
6446                             const struct rte_flow_item *item,
6447                             int inner, uint32_t group)
6448 {
6449         const struct rte_flow_item_vlan *vlan_m = item->mask;
6450         const struct rte_flow_item_vlan *vlan_v = item->spec;
6451         void *headers_m;
6452         void *headers_v;
6453         uint16_t tci_m;
6454         uint16_t tci_v;
6455
6456         if (inner) {
6457                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6458                                          inner_headers);
6459                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6460         } else {
6461                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6462                                          outer_headers);
6463                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6464                 /*
6465                  * This is workaround, masks are not supported,
6466                  * and pre-validated.
6467                  */
6468                 if (vlan_v)
6469                         dev_flow->handle->vf_vlan.tag =
6470                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6471         }
6472         /*
6473          * When VLAN item exists in flow, mark packet as tagged,
6474          * even if TCI is not specified.
6475          */
6476         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6477         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
6478         if (!vlan_v)
6479                 return;
6480         if (!vlan_m)
6481                 vlan_m = &rte_flow_item_vlan_mask;
6482         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6483         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6484         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
6485         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
6486         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
6487         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
6488         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
6489         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
6490         /*
6491          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6492          * ethertype, and use ip_version field instead.
6493          */
6494         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6495             vlan_m->inner_type == 0xFFFF) {
6496                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6497         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6498                    vlan_m->inner_type == 0xFFFF) {
6499                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6500         } else {
6501                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6502                          rte_be_to_cpu_16(vlan_m->inner_type));
6503                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6504                          rte_be_to_cpu_16(vlan_m->inner_type &
6505                                           vlan_v->inner_type));
6506         }
6507 }
6508
6509 /**
6510  * Add IPV4 item to matcher and to the value.
6511  *
6512  * @param[in, out] matcher
6513  *   Flow matcher.
6514  * @param[in, out] key
6515  *   Flow matcher value.
6516  * @param[in] item
6517  *   Flow pattern to translate.
6518  * @param[in] item_flags
6519  *   Bit-fields that holds the items detected until now.
6520  * @param[in] inner
6521  *   Item is inner pattern.
6522  * @param[in] group
6523  *   The group to insert the rule.
6524  */
6525 static void
6526 flow_dv_translate_item_ipv4(void *matcher, void *key,
6527                             const struct rte_flow_item *item,
6528                             const uint64_t item_flags,
6529                             int inner, uint32_t group)
6530 {
6531         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6532         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6533         const struct rte_flow_item_ipv4 nic_mask = {
6534                 .hdr = {
6535                         .src_addr = RTE_BE32(0xffffffff),
6536                         .dst_addr = RTE_BE32(0xffffffff),
6537                         .type_of_service = 0xff,
6538                         .next_proto_id = 0xff,
6539                         .time_to_live = 0xff,
6540                 },
6541         };
6542         void *headers_m;
6543         void *headers_v;
6544         char *l24_m;
6545         char *l24_v;
6546         uint8_t tos;
6547
6548         if (inner) {
6549                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6550                                          inner_headers);
6551                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6552         } else {
6553                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6554                                          outer_headers);
6555                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6556         }
6557         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6558         /*
6559          * On outer header (which must contains L2), or inner header with L2,
6560          * set cvlan_tag mask bit to mark this packet as untagged.
6561          * This should be done even if item->spec is empty.
6562          */
6563         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6564                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6565         if (!ipv4_v)
6566                 return;
6567         if (!ipv4_m)
6568                 ipv4_m = &nic_mask;
6569         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6570                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6571         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6572                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6573         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6574         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6575         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6576                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6577         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6578                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6579         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6580         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6581         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6582         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6583                  ipv4_m->hdr.type_of_service);
6584         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6585         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6586                  ipv4_m->hdr.type_of_service >> 2);
6587         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6588         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6589                  ipv4_m->hdr.next_proto_id);
6590         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6591                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6592         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6593                  ipv4_m->hdr.time_to_live);
6594         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6595                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6596         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6597                  !!(ipv4_m->hdr.fragment_offset));
6598         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6599                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6600 }
6601
6602 /**
6603  * Add IPV6 item to matcher and to the value.
6604  *
6605  * @param[in, out] matcher
6606  *   Flow matcher.
6607  * @param[in, out] key
6608  *   Flow matcher value.
6609  * @param[in] item
6610  *   Flow pattern to translate.
6611  * @param[in] item_flags
6612  *   Bit-fields that holds the items detected until now.
6613  * @param[in] inner
6614  *   Item is inner pattern.
6615  * @param[in] group
6616  *   The group to insert the rule.
6617  */
6618 static void
6619 flow_dv_translate_item_ipv6(void *matcher, void *key,
6620                             const struct rte_flow_item *item,
6621                             const uint64_t item_flags,
6622                             int inner, uint32_t group)
6623 {
6624         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6625         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6626         const struct rte_flow_item_ipv6 nic_mask = {
6627                 .hdr = {
6628                         .src_addr =
6629                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6630                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6631                         .dst_addr =
6632                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6633                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6634                         .vtc_flow = RTE_BE32(0xffffffff),
6635                         .proto = 0xff,
6636                         .hop_limits = 0xff,
6637                 },
6638         };
6639         void *headers_m;
6640         void *headers_v;
6641         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6642         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6643         char *l24_m;
6644         char *l24_v;
6645         uint32_t vtc_m;
6646         uint32_t vtc_v;
6647         int i;
6648         int size;
6649
6650         if (inner) {
6651                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6652                                          inner_headers);
6653                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6654         } else {
6655                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6656                                          outer_headers);
6657                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6658         }
6659         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6660         /*
6661          * On outer header (which must contains L2), or inner header with L2,
6662          * set cvlan_tag mask bit to mark this packet as untagged.
6663          * This should be done even if item->spec is empty.
6664          */
6665         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6666                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6667         if (!ipv6_v)
6668                 return;
6669         if (!ipv6_m)
6670                 ipv6_m = &nic_mask;
6671         size = sizeof(ipv6_m->hdr.dst_addr);
6672         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6673                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6674         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6675                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6676         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6677         for (i = 0; i < size; ++i)
6678                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6679         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6680                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6681         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6682                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6683         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6684         for (i = 0; i < size; ++i)
6685                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6686         /* TOS. */
6687         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6688         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6689         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6690         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6691         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6692         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6693         /* Label. */
6694         if (inner) {
6695                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6696                          vtc_m);
6697                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6698                          vtc_v);
6699         } else {
6700                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6701                          vtc_m);
6702                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6703                          vtc_v);
6704         }
6705         /* Protocol. */
6706         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6707                  ipv6_m->hdr.proto);
6708         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6709                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6710         /* Hop limit. */
6711         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6712                  ipv6_m->hdr.hop_limits);
6713         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6714                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6715         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6716                  !!(ipv6_m->has_frag_ext));
6717         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6718                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6719 }
6720
6721 /**
6722  * Add IPV6 fragment extension item to matcher and to the value.
6723  *
6724  * @param[in, out] matcher
6725  *   Flow matcher.
6726  * @param[in, out] key
6727  *   Flow matcher value.
6728  * @param[in] item
6729  *   Flow pattern to translate.
6730  * @param[in] inner
6731  *   Item is inner pattern.
6732  */
6733 static void
6734 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6735                                      const struct rte_flow_item *item,
6736                                      int inner)
6737 {
6738         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6739         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6740         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6741                 .hdr = {
6742                         .next_header = 0xff,
6743                         .frag_data = RTE_BE16(0xffff),
6744                 },
6745         };
6746         void *headers_m;
6747         void *headers_v;
6748
6749         if (inner) {
6750                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6751                                          inner_headers);
6752                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6753         } else {
6754                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6755                                          outer_headers);
6756                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6757         }
6758         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6759         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6760         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6761         if (!ipv6_frag_ext_v)
6762                 return;
6763         if (!ipv6_frag_ext_m)
6764                 ipv6_frag_ext_m = &nic_mask;
6765         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6766                  ipv6_frag_ext_m->hdr.next_header);
6767         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6768                  ipv6_frag_ext_v->hdr.next_header &
6769                  ipv6_frag_ext_m->hdr.next_header);
6770 }
6771
6772 /**
6773  * Add TCP item to matcher and to the value.
6774  *
6775  * @param[in, out] matcher
6776  *   Flow matcher.
6777  * @param[in, out] key
6778  *   Flow matcher value.
6779  * @param[in] item
6780  *   Flow pattern to translate.
6781  * @param[in] inner
6782  *   Item is inner pattern.
6783  */
6784 static void
6785 flow_dv_translate_item_tcp(void *matcher, void *key,
6786                            const struct rte_flow_item *item,
6787                            int inner)
6788 {
6789         const struct rte_flow_item_tcp *tcp_m = item->mask;
6790         const struct rte_flow_item_tcp *tcp_v = item->spec;
6791         void *headers_m;
6792         void *headers_v;
6793
6794         if (inner) {
6795                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6796                                          inner_headers);
6797                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6798         } else {
6799                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6800                                          outer_headers);
6801                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6802         }
6803         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6804         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6805         if (!tcp_v)
6806                 return;
6807         if (!tcp_m)
6808                 tcp_m = &rte_flow_item_tcp_mask;
6809         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6810                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6811         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6812                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6813         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6814                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6815         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6816                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6817         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6818                  tcp_m->hdr.tcp_flags);
6819         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6820                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6821 }
6822
6823 /**
6824  * Add UDP item to matcher and to the value.
6825  *
6826  * @param[in, out] matcher
6827  *   Flow matcher.
6828  * @param[in, out] key
6829  *   Flow matcher value.
6830  * @param[in] item
6831  *   Flow pattern to translate.
6832  * @param[in] inner
6833  *   Item is inner pattern.
6834  */
6835 static void
6836 flow_dv_translate_item_udp(void *matcher, void *key,
6837                            const struct rte_flow_item *item,
6838                            int inner)
6839 {
6840         const struct rte_flow_item_udp *udp_m = item->mask;
6841         const struct rte_flow_item_udp *udp_v = item->spec;
6842         void *headers_m;
6843         void *headers_v;
6844
6845         if (inner) {
6846                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6847                                          inner_headers);
6848                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6849         } else {
6850                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6851                                          outer_headers);
6852                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6853         }
6854         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6855         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6856         if (!udp_v)
6857                 return;
6858         if (!udp_m)
6859                 udp_m = &rte_flow_item_udp_mask;
6860         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6861                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6862         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6863                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6864         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6865                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6866         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6867                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6868 }
6869
6870 /**
6871  * Add GRE optional Key item to matcher and to the value.
6872  *
6873  * @param[in, out] matcher
6874  *   Flow matcher.
6875  * @param[in, out] key
6876  *   Flow matcher value.
6877  * @param[in] item
6878  *   Flow pattern to translate.
6879  * @param[in] inner
6880  *   Item is inner pattern.
6881  */
6882 static void
6883 flow_dv_translate_item_gre_key(void *matcher, void *key,
6884                                    const struct rte_flow_item *item)
6885 {
6886         const rte_be32_t *key_m = item->mask;
6887         const rte_be32_t *key_v = item->spec;
6888         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6889         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6890         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6891
6892         /* GRE K bit must be on and should already be validated */
6893         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6894         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6895         if (!key_v)
6896                 return;
6897         if (!key_m)
6898                 key_m = &gre_key_default_mask;
6899         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6900                  rte_be_to_cpu_32(*key_m) >> 8);
6901         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6902                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6903         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6904                  rte_be_to_cpu_32(*key_m) & 0xFF);
6905         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6906                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6907 }
6908
6909 /**
6910  * Add GRE item to matcher and to the value.
6911  *
6912  * @param[in, out] matcher
6913  *   Flow matcher.
6914  * @param[in, out] key
6915  *   Flow matcher value.
6916  * @param[in] item
6917  *   Flow pattern to translate.
6918  * @param[in] inner
6919  *   Item is inner pattern.
6920  */
6921 static void
6922 flow_dv_translate_item_gre(void *matcher, void *key,
6923                            const struct rte_flow_item *item,
6924                            int inner)
6925 {
6926         const struct rte_flow_item_gre *gre_m = item->mask;
6927         const struct rte_flow_item_gre *gre_v = item->spec;
6928         void *headers_m;
6929         void *headers_v;
6930         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6931         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6932         struct {
6933                 union {
6934                         __extension__
6935                         struct {
6936                                 uint16_t version:3;
6937                                 uint16_t rsvd0:9;
6938                                 uint16_t s_present:1;
6939                                 uint16_t k_present:1;
6940                                 uint16_t rsvd_bit1:1;
6941                                 uint16_t c_present:1;
6942                         };
6943                         uint16_t value;
6944                 };
6945         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6946
6947         if (inner) {
6948                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6949                                          inner_headers);
6950                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6951         } else {
6952                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6953                                          outer_headers);
6954                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6955         }
6956         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6957         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6958         if (!gre_v)
6959                 return;
6960         if (!gre_m)
6961                 gre_m = &rte_flow_item_gre_mask;
6962         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6963                  rte_be_to_cpu_16(gre_m->protocol));
6964         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6965                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6966         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6967         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6968         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6969                  gre_crks_rsvd0_ver_m.c_present);
6970         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6971                  gre_crks_rsvd0_ver_v.c_present &
6972                  gre_crks_rsvd0_ver_m.c_present);
6973         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6974                  gre_crks_rsvd0_ver_m.k_present);
6975         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6976                  gre_crks_rsvd0_ver_v.k_present &
6977                  gre_crks_rsvd0_ver_m.k_present);
6978         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6979                  gre_crks_rsvd0_ver_m.s_present);
6980         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6981                  gre_crks_rsvd0_ver_v.s_present &
6982                  gre_crks_rsvd0_ver_m.s_present);
6983 }
6984
6985 /**
6986  * Add NVGRE item to matcher and to the value.
6987  *
6988  * @param[in, out] matcher
6989  *   Flow matcher.
6990  * @param[in, out] key
6991  *   Flow matcher value.
6992  * @param[in] item
6993  *   Flow pattern to translate.
6994  * @param[in] inner
6995  *   Item is inner pattern.
6996  */
6997 static void
6998 flow_dv_translate_item_nvgre(void *matcher, void *key,
6999                              const struct rte_flow_item *item,
7000                              int inner)
7001 {
7002         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7003         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7004         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7005         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7006         const char *tni_flow_id_m;
7007         const char *tni_flow_id_v;
7008         char *gre_key_m;
7009         char *gre_key_v;
7010         int size;
7011         int i;
7012
7013         /* For NVGRE, GRE header fields must be set with defined values. */
7014         const struct rte_flow_item_gre gre_spec = {
7015                 .c_rsvd0_ver = RTE_BE16(0x2000),
7016                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7017         };
7018         const struct rte_flow_item_gre gre_mask = {
7019                 .c_rsvd0_ver = RTE_BE16(0xB000),
7020                 .protocol = RTE_BE16(UINT16_MAX),
7021         };
7022         const struct rte_flow_item gre_item = {
7023                 .spec = &gre_spec,
7024                 .mask = &gre_mask,
7025                 .last = NULL,
7026         };
7027         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7028         if (!nvgre_v)
7029                 return;
7030         if (!nvgre_m)
7031                 nvgre_m = &rte_flow_item_nvgre_mask;
7032         tni_flow_id_m = (const char *)nvgre_m->tni;
7033         tni_flow_id_v = (const char *)nvgre_v->tni;
7034         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7035         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7036         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7037         memcpy(gre_key_m, tni_flow_id_m, size);
7038         for (i = 0; i < size; ++i)
7039                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7040 }
7041
7042 /**
7043  * Add VXLAN item to matcher and to the value.
7044  *
7045  * @param[in, out] matcher
7046  *   Flow matcher.
7047  * @param[in, out] key
7048  *   Flow matcher value.
7049  * @param[in] item
7050  *   Flow pattern to translate.
7051  * @param[in] inner
7052  *   Item is inner pattern.
7053  */
7054 static void
7055 flow_dv_translate_item_vxlan(void *matcher, void *key,
7056                              const struct rte_flow_item *item,
7057                              int inner)
7058 {
7059         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7060         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7061         void *headers_m;
7062         void *headers_v;
7063         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7064         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7065         char *vni_m;
7066         char *vni_v;
7067         uint16_t dport;
7068         int size;
7069         int i;
7070
7071         if (inner) {
7072                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7073                                          inner_headers);
7074                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7075         } else {
7076                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7077                                          outer_headers);
7078                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7079         }
7080         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7081                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7082         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7083                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7084                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7085         }
7086         if (!vxlan_v)
7087                 return;
7088         if (!vxlan_m)
7089                 vxlan_m = &rte_flow_item_vxlan_mask;
7090         size = sizeof(vxlan_m->vni);
7091         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7092         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7093         memcpy(vni_m, vxlan_m->vni, size);
7094         for (i = 0; i < size; ++i)
7095                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7096 }
7097
7098 /**
7099  * Add VXLAN-GPE item to matcher and to the value.
7100  *
7101  * @param[in, out] matcher
7102  *   Flow matcher.
7103  * @param[in, out] key
7104  *   Flow matcher value.
7105  * @param[in] item
7106  *   Flow pattern to translate.
7107  * @param[in] inner
7108  *   Item is inner pattern.
7109  */
7110
7111 static void
7112 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7113                                  const struct rte_flow_item *item, int inner)
7114 {
7115         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7116         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7117         void *headers_m;
7118         void *headers_v;
7119         void *misc_m =
7120                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7121         void *misc_v =
7122                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7123         char *vni_m;
7124         char *vni_v;
7125         uint16_t dport;
7126         int size;
7127         int i;
7128         uint8_t flags_m = 0xff;
7129         uint8_t flags_v = 0xc;
7130
7131         if (inner) {
7132                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7133                                          inner_headers);
7134                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7135         } else {
7136                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7137                                          outer_headers);
7138                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7139         }
7140         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7141                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7142         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7143                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7144                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7145         }
7146         if (!vxlan_v)
7147                 return;
7148         if (!vxlan_m)
7149                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7150         size = sizeof(vxlan_m->vni);
7151         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7152         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7153         memcpy(vni_m, vxlan_m->vni, size);
7154         for (i = 0; i < size; ++i)
7155                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7156         if (vxlan_m->flags) {
7157                 flags_m = vxlan_m->flags;
7158                 flags_v = vxlan_v->flags;
7159         }
7160         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7161         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7162         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7163                  vxlan_m->protocol);
7164         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7165                  vxlan_v->protocol);
7166 }
7167
7168 /**
7169  * Add Geneve item to matcher and to the value.
7170  *
7171  * @param[in, out] matcher
7172  *   Flow matcher.
7173  * @param[in, out] key
7174  *   Flow matcher value.
7175  * @param[in] item
7176  *   Flow pattern to translate.
7177  * @param[in] inner
7178  *   Item is inner pattern.
7179  */
7180
7181 static void
7182 flow_dv_translate_item_geneve(void *matcher, void *key,
7183                               const struct rte_flow_item *item, int inner)
7184 {
7185         const struct rte_flow_item_geneve *geneve_m = item->mask;
7186         const struct rte_flow_item_geneve *geneve_v = item->spec;
7187         void *headers_m;
7188         void *headers_v;
7189         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7190         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7191         uint16_t dport;
7192         uint16_t gbhdr_m;
7193         uint16_t gbhdr_v;
7194         char *vni_m;
7195         char *vni_v;
7196         size_t size, i;
7197
7198         if (inner) {
7199                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7200                                          inner_headers);
7201                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7202         } else {
7203                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7204                                          outer_headers);
7205                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7206         }
7207         dport = MLX5_UDP_PORT_GENEVE;
7208         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7209                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7210                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7211         }
7212         if (!geneve_v)
7213                 return;
7214         if (!geneve_m)
7215                 geneve_m = &rte_flow_item_geneve_mask;
7216         size = sizeof(geneve_m->vni);
7217         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7218         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7219         memcpy(vni_m, geneve_m->vni, size);
7220         for (i = 0; i < size; ++i)
7221                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7222         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7223                  rte_be_to_cpu_16(geneve_m->protocol));
7224         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7225                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7226         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7227         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7228         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7229                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7230         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7231                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7232         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7233                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7234         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7235                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7236                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7237 }
7238
7239 /**
7240  * Add MPLS item to matcher and to the value.
7241  *
7242  * @param[in, out] matcher
7243  *   Flow matcher.
7244  * @param[in, out] key
7245  *   Flow matcher value.
7246  * @param[in] item
7247  *   Flow pattern to translate.
7248  * @param[in] prev_layer
7249  *   The protocol layer indicated in previous item.
7250  * @param[in] inner
7251  *   Item is inner pattern.
7252  */
7253 static void
7254 flow_dv_translate_item_mpls(void *matcher, void *key,
7255                             const struct rte_flow_item *item,
7256                             uint64_t prev_layer,
7257                             int inner)
7258 {
7259         const uint32_t *in_mpls_m = item->mask;
7260         const uint32_t *in_mpls_v = item->spec;
7261         uint32_t *out_mpls_m = 0;
7262         uint32_t *out_mpls_v = 0;
7263         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7264         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7265         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7266                                      misc_parameters_2);
7267         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7268         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7269         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7270
7271         switch (prev_layer) {
7272         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7273                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7274                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7275                          MLX5_UDP_PORT_MPLS);
7276                 break;
7277         case MLX5_FLOW_LAYER_GRE:
7278                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7279                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7280                          RTE_ETHER_TYPE_MPLS);
7281                 break;
7282         default:
7283                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7284                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7285                          IPPROTO_MPLS);
7286                 break;
7287         }
7288         if (!in_mpls_v)
7289                 return;
7290         if (!in_mpls_m)
7291                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7292         switch (prev_layer) {
7293         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7294                 out_mpls_m =
7295                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7296                                                  outer_first_mpls_over_udp);
7297                 out_mpls_v =
7298                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7299                                                  outer_first_mpls_over_udp);
7300                 break;
7301         case MLX5_FLOW_LAYER_GRE:
7302                 out_mpls_m =
7303                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7304                                                  outer_first_mpls_over_gre);
7305                 out_mpls_v =
7306                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7307                                                  outer_first_mpls_over_gre);
7308                 break;
7309         default:
7310                 /* Inner MPLS not over GRE is not supported. */
7311                 if (!inner) {
7312                         out_mpls_m =
7313                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7314                                                          misc2_m,
7315                                                          outer_first_mpls);
7316                         out_mpls_v =
7317                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7318                                                          misc2_v,
7319                                                          outer_first_mpls);
7320                 }
7321                 break;
7322         }
7323         if (out_mpls_m && out_mpls_v) {
7324                 *out_mpls_m = *in_mpls_m;
7325                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7326         }
7327 }
7328
7329 /**
7330  * Add metadata register item to matcher
7331  *
7332  * @param[in, out] matcher
7333  *   Flow matcher.
7334  * @param[in, out] key
7335  *   Flow matcher value.
7336  * @param[in] reg_type
7337  *   Type of device metadata register
7338  * @param[in] value
7339  *   Register value
7340  * @param[in] mask
7341  *   Register mask
7342  */
7343 static void
7344 flow_dv_match_meta_reg(void *matcher, void *key,
7345                        enum modify_reg reg_type,
7346                        uint32_t data, uint32_t mask)
7347 {
7348         void *misc2_m =
7349                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7350         void *misc2_v =
7351                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7352         uint32_t temp;
7353
7354         data &= mask;
7355         switch (reg_type) {
7356         case REG_A:
7357                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7358                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7359                 break;
7360         case REG_B:
7361                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7362                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7363                 break;
7364         case REG_C_0:
7365                 /*
7366                  * The metadata register C0 field might be divided into
7367                  * source vport index and META item value, we should set
7368                  * this field according to specified mask, not as whole one.
7369                  */
7370                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7371                 temp |= mask;
7372                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7373                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7374                 temp &= ~mask;
7375                 temp |= data;
7376                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7377                 break;
7378         case REG_C_1:
7379                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7380                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7381                 break;
7382         case REG_C_2:
7383                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7384                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7385                 break;
7386         case REG_C_3:
7387                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7388                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7389                 break;
7390         case REG_C_4:
7391                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7392                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7393                 break;
7394         case REG_C_5:
7395                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7396                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7397                 break;
7398         case REG_C_6:
7399                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7400                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7401                 break;
7402         case REG_C_7:
7403                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7404                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7405                 break;
7406         default:
7407                 MLX5_ASSERT(false);
7408                 break;
7409         }
7410 }
7411
7412 /**
7413  * Add MARK item to matcher
7414  *
7415  * @param[in] dev
7416  *   The device to configure through.
7417  * @param[in, out] matcher
7418  *   Flow matcher.
7419  * @param[in, out] key
7420  *   Flow matcher value.
7421  * @param[in] item
7422  *   Flow pattern to translate.
7423  */
7424 static void
7425 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7426                             void *matcher, void *key,
7427                             const struct rte_flow_item *item)
7428 {
7429         struct mlx5_priv *priv = dev->data->dev_private;
7430         const struct rte_flow_item_mark *mark;
7431         uint32_t value;
7432         uint32_t mask;
7433
7434         mark = item->mask ? (const void *)item->mask :
7435                             &rte_flow_item_mark_mask;
7436         mask = mark->id & priv->sh->dv_mark_mask;
7437         mark = (const void *)item->spec;
7438         MLX5_ASSERT(mark);
7439         value = mark->id & priv->sh->dv_mark_mask & mask;
7440         if (mask) {
7441                 enum modify_reg reg;
7442
7443                 /* Get the metadata register index for the mark. */
7444                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7445                 MLX5_ASSERT(reg > 0);
7446                 if (reg == REG_C_0) {
7447                         struct mlx5_priv *priv = dev->data->dev_private;
7448                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7449                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7450
7451                         mask &= msk_c0;
7452                         mask <<= shl_c0;
7453                         value <<= shl_c0;
7454                 }
7455                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7456         }
7457 }
7458
7459 /**
7460  * Add META item to matcher
7461  *
7462  * @param[in] dev
7463  *   The devich to configure through.
7464  * @param[in, out] matcher
7465  *   Flow matcher.
7466  * @param[in, out] key
7467  *   Flow matcher value.
7468  * @param[in] attr
7469  *   Attributes of flow that includes this item.
7470  * @param[in] item
7471  *   Flow pattern to translate.
7472  */
7473 static void
7474 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7475                             void *matcher, void *key,
7476                             const struct rte_flow_attr *attr,
7477                             const struct rte_flow_item *item)
7478 {
7479         const struct rte_flow_item_meta *meta_m;
7480         const struct rte_flow_item_meta *meta_v;
7481
7482         meta_m = (const void *)item->mask;
7483         if (!meta_m)
7484                 meta_m = &rte_flow_item_meta_mask;
7485         meta_v = (const void *)item->spec;
7486         if (meta_v) {
7487                 int reg;
7488                 uint32_t value = meta_v->data;
7489                 uint32_t mask = meta_m->data;
7490
7491                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7492                 if (reg < 0)
7493                         return;
7494                 /*
7495                  * In datapath code there is no endianness
7496                  * coversions for perfromance reasons, all
7497                  * pattern conversions are done in rte_flow.
7498                  */
7499                 value = rte_cpu_to_be_32(value);
7500                 mask = rte_cpu_to_be_32(mask);
7501                 if (reg == REG_C_0) {
7502                         struct mlx5_priv *priv = dev->data->dev_private;
7503                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7504                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7505 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7506                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7507
7508                         value >>= shr_c0;
7509                         mask >>= shr_c0;
7510 #endif
7511                         value <<= shl_c0;
7512                         mask <<= shl_c0;
7513                         MLX5_ASSERT(msk_c0);
7514                         MLX5_ASSERT(!(~msk_c0 & mask));
7515                 }
7516                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7517         }
7518 }
7519
7520 /**
7521  * Add vport metadata Reg C0 item to matcher
7522  *
7523  * @param[in, out] matcher
7524  *   Flow matcher.
7525  * @param[in, out] key
7526  *   Flow matcher value.
7527  * @param[in] reg
7528  *   Flow pattern to translate.
7529  */
7530 static void
7531 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7532                                   uint32_t value, uint32_t mask)
7533 {
7534         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7535 }
7536
7537 /**
7538  * Add tag item to matcher
7539  *
7540  * @param[in] dev
7541  *   The devich to configure through.
7542  * @param[in, out] matcher
7543  *   Flow matcher.
7544  * @param[in, out] key
7545  *   Flow matcher value.
7546  * @param[in] item
7547  *   Flow pattern to translate.
7548  */
7549 static void
7550 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7551                                 void *matcher, void *key,
7552                                 const struct rte_flow_item *item)
7553 {
7554         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7555         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7556         uint32_t mask, value;
7557
7558         MLX5_ASSERT(tag_v);
7559         value = tag_v->data;
7560         mask = tag_m ? tag_m->data : UINT32_MAX;
7561         if (tag_v->id == REG_C_0) {
7562                 struct mlx5_priv *priv = dev->data->dev_private;
7563                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7564                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7565
7566                 mask &= msk_c0;
7567                 mask <<= shl_c0;
7568                 value <<= shl_c0;
7569         }
7570         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7571 }
7572
7573 /**
7574  * Add TAG item to matcher
7575  *
7576  * @param[in] dev
7577  *   The devich to configure through.
7578  * @param[in, out] matcher
7579  *   Flow matcher.
7580  * @param[in, out] key
7581  *   Flow matcher value.
7582  * @param[in] item
7583  *   Flow pattern to translate.
7584  */
7585 static void
7586 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7587                            void *matcher, void *key,
7588                            const struct rte_flow_item *item)
7589 {
7590         const struct rte_flow_item_tag *tag_v = item->spec;
7591         const struct rte_flow_item_tag *tag_m = item->mask;
7592         enum modify_reg reg;
7593
7594         MLX5_ASSERT(tag_v);
7595         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7596         /* Get the metadata register index for the tag. */
7597         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7598         MLX5_ASSERT(reg > 0);
7599         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7600 }
7601
7602 /**
7603  * Add source vport match to the specified matcher.
7604  *
7605  * @param[in, out] matcher
7606  *   Flow matcher.
7607  * @param[in, out] key
7608  *   Flow matcher value.
7609  * @param[in] port
7610  *   Source vport value to match
7611  * @param[in] mask
7612  *   Mask
7613  */
7614 static void
7615 flow_dv_translate_item_source_vport(void *matcher, void *key,
7616                                     int16_t port, uint16_t mask)
7617 {
7618         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7619         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7620
7621         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7622         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7623 }
7624
7625 /**
7626  * Translate port-id item to eswitch match on  port-id.
7627  *
7628  * @param[in] dev
7629  *   The devich to configure through.
7630  * @param[in, out] matcher
7631  *   Flow matcher.
7632  * @param[in, out] key
7633  *   Flow matcher value.
7634  * @param[in] item
7635  *   Flow pattern to translate.
7636  *
7637  * @return
7638  *   0 on success, a negative errno value otherwise.
7639  */
7640 static int
7641 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7642                                void *key, const struct rte_flow_item *item)
7643 {
7644         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7645         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7646         struct mlx5_priv *priv;
7647         uint16_t mask, id;
7648
7649         mask = pid_m ? pid_m->id : 0xffff;
7650         id = pid_v ? pid_v->id : dev->data->port_id;
7651         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7652         if (!priv)
7653                 return -rte_errno;
7654         /* Translate to vport field or to metadata, depending on mode. */
7655         if (priv->vport_meta_mask)
7656                 flow_dv_translate_item_meta_vport(matcher, key,
7657                                                   priv->vport_meta_tag,
7658                                                   priv->vport_meta_mask);
7659         else
7660                 flow_dv_translate_item_source_vport(matcher, key,
7661                                                     priv->vport_id, mask);
7662         return 0;
7663 }
7664
7665 /**
7666  * Add ICMP6 item to matcher and to the value.
7667  *
7668  * @param[in, out] matcher
7669  *   Flow matcher.
7670  * @param[in, out] key
7671  *   Flow matcher value.
7672  * @param[in] item
7673  *   Flow pattern to translate.
7674  * @param[in] inner
7675  *   Item is inner pattern.
7676  */
7677 static void
7678 flow_dv_translate_item_icmp6(void *matcher, void *key,
7679                               const struct rte_flow_item *item,
7680                               int inner)
7681 {
7682         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7683         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7684         void *headers_m;
7685         void *headers_v;
7686         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7687                                      misc_parameters_3);
7688         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7689         if (inner) {
7690                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7691                                          inner_headers);
7692                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7693         } else {
7694                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7695                                          outer_headers);
7696                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7697         }
7698         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7699         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7700         if (!icmp6_v)
7701                 return;
7702         if (!icmp6_m)
7703                 icmp6_m = &rte_flow_item_icmp6_mask;
7704         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7705         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7706                  icmp6_v->type & icmp6_m->type);
7707         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7708         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7709                  icmp6_v->code & icmp6_m->code);
7710 }
7711
7712 /**
7713  * Add ICMP item to matcher and to the value.
7714  *
7715  * @param[in, out] matcher
7716  *   Flow matcher.
7717  * @param[in, out] key
7718  *   Flow matcher value.
7719  * @param[in] item
7720  *   Flow pattern to translate.
7721  * @param[in] inner
7722  *   Item is inner pattern.
7723  */
7724 static void
7725 flow_dv_translate_item_icmp(void *matcher, void *key,
7726                             const struct rte_flow_item *item,
7727                             int inner)
7728 {
7729         const struct rte_flow_item_icmp *icmp_m = item->mask;
7730         const struct rte_flow_item_icmp *icmp_v = item->spec;
7731         uint32_t icmp_header_data_m = 0;
7732         uint32_t icmp_header_data_v = 0;
7733         void *headers_m;
7734         void *headers_v;
7735         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7736                                      misc_parameters_3);
7737         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7738         if (inner) {
7739                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7740                                          inner_headers);
7741                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7742         } else {
7743                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7744                                          outer_headers);
7745                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7746         }
7747         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7748         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7749         if (!icmp_v)
7750                 return;
7751         if (!icmp_m)
7752                 icmp_m = &rte_flow_item_icmp_mask;
7753         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7754                  icmp_m->hdr.icmp_type);
7755         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7756                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7757         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7758                  icmp_m->hdr.icmp_code);
7759         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7760                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7761         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7762         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7763         if (icmp_header_data_m) {
7764                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7765                 icmp_header_data_v |=
7766                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7767                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7768                          icmp_header_data_m);
7769                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7770                          icmp_header_data_v & icmp_header_data_m);
7771         }
7772 }
7773
7774 /**
7775  * Add GTP item to matcher and to the value.
7776  *
7777  * @param[in, out] matcher
7778  *   Flow matcher.
7779  * @param[in, out] key
7780  *   Flow matcher value.
7781  * @param[in] item
7782  *   Flow pattern to translate.
7783  * @param[in] inner
7784  *   Item is inner pattern.
7785  */
7786 static void
7787 flow_dv_translate_item_gtp(void *matcher, void *key,
7788                            const struct rte_flow_item *item, int inner)
7789 {
7790         const struct rte_flow_item_gtp *gtp_m = item->mask;
7791         const struct rte_flow_item_gtp *gtp_v = item->spec;
7792         void *headers_m;
7793         void *headers_v;
7794         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7795                                      misc_parameters_3);
7796         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7797         uint16_t dport = RTE_GTPU_UDP_PORT;
7798
7799         if (inner) {
7800                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7801                                          inner_headers);
7802                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7803         } else {
7804                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7805                                          outer_headers);
7806                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7807         }
7808         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7809                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7810                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7811         }
7812         if (!gtp_v)
7813                 return;
7814         if (!gtp_m)
7815                 gtp_m = &rte_flow_item_gtp_mask;
7816         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7817                  gtp_m->v_pt_rsv_flags);
7818         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7819                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7820         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7821         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7822                  gtp_v->msg_type & gtp_m->msg_type);
7823         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7824                  rte_be_to_cpu_32(gtp_m->teid));
7825         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7826                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7827 }
7828
7829 /**
7830  * Add eCPRI item to matcher and to the value.
7831  *
7832  * @param[in] dev
7833  *   The devich to configure through.
7834  * @param[in, out] matcher
7835  *   Flow matcher.
7836  * @param[in, out] key
7837  *   Flow matcher value.
7838  * @param[in] item
7839  *   Flow pattern to translate.
7840  * @param[in] samples
7841  *   Sample IDs to be used in the matching.
7842  */
7843 static void
7844 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7845                              void *key, const struct rte_flow_item *item)
7846 {
7847         struct mlx5_priv *priv = dev->data->dev_private;
7848         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7849         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7850         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7851                                      misc_parameters_4);
7852         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7853         uint32_t *samples;
7854         void *dw_m;
7855         void *dw_v;
7856
7857         if (!ecpri_v)
7858                 return;
7859         if (!ecpri_m)
7860                 ecpri_m = &rte_flow_item_ecpri_mask;
7861         /*
7862          * Maximal four DW samples are supported in a single matching now.
7863          * Two are used now for a eCPRI matching:
7864          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7865          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7866          *    if any.
7867          */
7868         if (!ecpri_m->hdr.common.u32)
7869                 return;
7870         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7871         /* Need to take the whole DW as the mask to fill the entry. */
7872         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7873                             prog_sample_field_value_0);
7874         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7875                             prog_sample_field_value_0);
7876         /* Already big endian (network order) in the header. */
7877         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7878         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7879         /* Sample#0, used for matching type, offset 0. */
7880         MLX5_SET(fte_match_set_misc4, misc4_m,
7881                  prog_sample_field_id_0, samples[0]);
7882         /* It makes no sense to set the sample ID in the mask field. */
7883         MLX5_SET(fte_match_set_misc4, misc4_v,
7884                  prog_sample_field_id_0, samples[0]);
7885         /*
7886          * Checking if message body part needs to be matched.
7887          * Some wildcard rules only matching type field should be supported.
7888          */
7889         if (ecpri_m->hdr.dummy[0]) {
7890                 switch (ecpri_v->hdr.common.type) {
7891                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7892                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7893                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7894                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7895                                             prog_sample_field_value_1);
7896                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7897                                             prog_sample_field_value_1);
7898                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7899                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7900                         /* Sample#1, to match message body, offset 4. */
7901                         MLX5_SET(fte_match_set_misc4, misc4_m,
7902                                  prog_sample_field_id_1, samples[1]);
7903                         MLX5_SET(fte_match_set_misc4, misc4_v,
7904                                  prog_sample_field_id_1, samples[1]);
7905                         break;
7906                 default:
7907                         /* Others, do not match any sample ID. */
7908                         break;
7909                 }
7910         }
7911 }
7912
7913 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7914
7915 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7916         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7917                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7918
7919 /**
7920  * Calculate flow matcher enable bitmap.
7921  *
7922  * @param match_criteria
7923  *   Pointer to flow matcher criteria.
7924  *
7925  * @return
7926  *   Bitmap of enabled fields.
7927  */
7928 static uint8_t
7929 flow_dv_matcher_enable(uint32_t *match_criteria)
7930 {
7931         uint8_t match_criteria_enable;
7932
7933         match_criteria_enable =
7934                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7935                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7936         match_criteria_enable |=
7937                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7938                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7939         match_criteria_enable |=
7940                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7941                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7942         match_criteria_enable |=
7943                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7944                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7945         match_criteria_enable |=
7946                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7947                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7948         match_criteria_enable |=
7949                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7950                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7951         return match_criteria_enable;
7952 }
7953
7954
7955 /**
7956  * Get a flow table.
7957  *
7958  * @param[in, out] dev
7959  *   Pointer to rte_eth_dev structure.
7960  * @param[in] table_id
7961  *   Table id to use.
7962  * @param[in] egress
7963  *   Direction of the table.
7964  * @param[in] transfer
7965  *   E-Switch or NIC flow.
7966  * @param[out] error
7967  *   pointer to error structure.
7968  *
7969  * @return
7970  *   Returns tables resource based on the index, NULL in case of failed.
7971  */
7972 static struct mlx5_flow_tbl_resource *
7973 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7974                          uint32_t table_id, uint8_t egress,
7975                          uint8_t transfer,
7976                          bool external,
7977                          const struct mlx5_flow_tunnel *tunnel,
7978                          uint32_t group_id,
7979                          struct rte_flow_error *error)
7980 {
7981         struct mlx5_priv *priv = dev->data->dev_private;
7982         struct mlx5_dev_ctx_shared *sh = priv->sh;
7983         struct mlx5_flow_tbl_resource *tbl;
7984         union mlx5_flow_tbl_key table_key = {
7985                 {
7986                         .table_id = table_id,
7987                         .reserved = 0,
7988                         .domain = !!transfer,
7989                         .direction = !!egress,
7990                 }
7991         };
7992         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7993                                                          table_key.v64);
7994         struct mlx5_flow_tbl_data_entry *tbl_data;
7995         uint32_t idx = 0;
7996         int ret;
7997         void *domain;
7998
7999         if (pos) {
8000                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
8001                                         entry);
8002                 tbl = &tbl_data->tbl;
8003                 rte_atomic32_inc(&tbl->refcnt);
8004                 return tbl;
8005         }
8006         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
8007         if (!tbl_data) {
8008                 rte_flow_error_set(error, ENOMEM,
8009                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8010                                    NULL,
8011                                    "cannot allocate flow table data entry");
8012                 return NULL;
8013         }
8014         tbl_data->idx = idx;
8015         tbl_data->tunnel = tunnel;
8016         tbl_data->group_id = group_id;
8017         tbl_data->external = external;
8018         tbl = &tbl_data->tbl;
8019         pos = &tbl_data->entry;
8020         if (transfer)
8021                 domain = sh->fdb_domain;
8022         else if (egress)
8023                 domain = sh->tx_domain;
8024         else
8025                 domain = sh->rx_domain;
8026         ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
8027         if (ret) {
8028                 rte_flow_error_set(error, ENOMEM,
8029                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8030                                    NULL, "cannot create flow table object");
8031                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8032                 return NULL;
8033         }
8034         /*
8035          * No multi-threads now, but still better to initialize the reference
8036          * count before insert it into the hash list.
8037          */
8038         rte_atomic32_init(&tbl->refcnt);
8039         /* Jump action reference count is initialized here. */
8040         rte_atomic32_init(&tbl_data->jump.refcnt);
8041         pos->key = table_key.v64;
8042         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
8043         if (ret < 0) {
8044                 rte_flow_error_set(error, -ret,
8045                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8046                                    "cannot insert flow table data entry");
8047                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8048                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
8049         }
8050         rte_atomic32_inc(&tbl->refcnt);
8051         return tbl;
8052 }
8053
8054 /**
8055  * Release a flow table.
8056  *
8057  * @param[in] dev
8058  *   Pointer to rte_eth_dev structure.
8059  * @param[in] tbl
8060  *   Table resource to be released.
8061  *
8062  * @return
8063  *   Returns 0 if table was released, else return 1;
8064  */
8065 static int
8066 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
8067                              struct mlx5_flow_tbl_resource *tbl)
8068 {
8069         struct mlx5_priv *priv = dev->data->dev_private;
8070         struct mlx5_dev_ctx_shared *sh = priv->sh;
8071         struct mlx5_flow_tbl_data_entry *tbl_data =
8072                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8073
8074         if (!tbl)
8075                 return 0;
8076         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
8077                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
8078
8079                 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
8080                 tbl->obj = NULL;
8081                 if (is_tunnel_offload_active(dev) && tbl_data->external) {
8082                         struct mlx5_hlist_entry *he;
8083                         struct mlx5_hlist *tunnel_grp_hash;
8084                         struct mlx5_flow_tunnel_hub *thub =
8085                                                         mlx5_tunnel_hub(dev);
8086                         union tunnel_tbl_key tunnel_key = {
8087                                 .tunnel_id = tbl_data->tunnel ?
8088                                                 tbl_data->tunnel->tunnel_id : 0,
8089                                 .group = tbl_data->group_id
8090                         };
8091                         union mlx5_flow_tbl_key table_key = {
8092                                 .v64 = pos->key
8093                         };
8094                         uint32_t table_id = table_key.table_id;
8095
8096                         tunnel_grp_hash = tbl_data->tunnel ?
8097                                                 tbl_data->tunnel->groups :
8098                                                 thub->groups;
8099                         he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val);
8100                         if (he) {
8101                                 struct tunnel_tbl_entry *tte;
8102                                 tte = container_of(he, typeof(*tte), hash);
8103                                 MLX5_ASSERT(tte->flow_table == table_id);
8104                                 mlx5_hlist_remove(tunnel_grp_hash, he);
8105                                 mlx5_free(tte);
8106                         }
8107                         mlx5_flow_id_release(mlx5_tunnel_hub(dev)->table_ids,
8108                                              tunnel_flow_tbl_to_id(table_id));
8109                         DRV_LOG(DEBUG,
8110                                 "port %u release table_id %#x tunnel %u group %u",
8111                                 dev->data->port_id, table_id,
8112                                 tbl_data->tunnel ?
8113                                 tbl_data->tunnel->tunnel_id : 0,
8114                                 tbl_data->group_id);
8115                 }
8116                 /* remove the entry from the hash list and free memory. */
8117                 mlx5_hlist_remove(sh->flow_tbls, pos);
8118                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
8119                                 tbl_data->idx);
8120                 return 0;
8121         }
8122         return 1;
8123 }
8124
8125 /**
8126  * Register the flow matcher.
8127  *
8128  * @param[in, out] dev
8129  *   Pointer to rte_eth_dev structure.
8130  * @param[in, out] matcher
8131  *   Pointer to flow matcher.
8132  * @param[in, out] key
8133  *   Pointer to flow table key.
8134  * @parm[in, out] dev_flow
8135  *   Pointer to the dev_flow.
8136  * @param[out] error
8137  *   pointer to error structure.
8138  *
8139  * @return
8140  *   0 on success otherwise -errno and errno is set.
8141  */
8142 static int
8143 flow_dv_matcher_register(struct rte_eth_dev *dev,
8144                          struct mlx5_flow_dv_matcher *matcher,
8145                          union mlx5_flow_tbl_key *key,
8146                          struct mlx5_flow *dev_flow,
8147                          struct rte_flow_error *error)
8148 {
8149         struct mlx5_priv *priv = dev->data->dev_private;
8150         struct mlx5_dev_ctx_shared *sh = priv->sh;
8151         struct mlx5_flow_dv_matcher *cache_matcher;
8152         struct mlx5dv_flow_matcher_attr dv_attr = {
8153                 .type = IBV_FLOW_ATTR_NORMAL,
8154                 .match_mask = (void *)&matcher->mask,
8155         };
8156         struct mlx5_flow_tbl_resource *tbl;
8157         struct mlx5_flow_tbl_data_entry *tbl_data;
8158         int ret;
8159
8160         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
8161                                        key->domain, false, NULL, 0, error);
8162         if (!tbl)
8163                 return -rte_errno;      /* No need to refill the error info */
8164         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8165         /* Lookup from cache. */
8166         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
8167                 if (matcher->crc == cache_matcher->crc &&
8168                     matcher->priority == cache_matcher->priority &&
8169                     !memcmp((const void *)matcher->mask.buf,
8170                             (const void *)cache_matcher->mask.buf,
8171                             cache_matcher->mask.size)) {
8172                         DRV_LOG(DEBUG,
8173                                 "%s group %u priority %hd use %s "
8174                                 "matcher %p: refcnt %d++",
8175                                 key->domain ? "FDB" : "NIC", key->table_id,
8176                                 cache_matcher->priority,
8177                                 key->direction ? "tx" : "rx",
8178                                 (void *)cache_matcher,
8179                                 rte_atomic32_read(&cache_matcher->refcnt));
8180                         rte_atomic32_inc(&cache_matcher->refcnt);
8181                         dev_flow->handle->dvh.matcher = cache_matcher;
8182                         /* old matcher should not make the table ref++. */
8183                         flow_dv_tbl_resource_release(dev, tbl);
8184                         return 0;
8185                 }
8186         }
8187         /* Register new matcher. */
8188         cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
8189                                     SOCKET_ID_ANY);
8190         if (!cache_matcher) {
8191                 flow_dv_tbl_resource_release(dev, tbl);
8192                 return rte_flow_error_set(error, ENOMEM,
8193                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8194                                           "cannot allocate matcher memory");
8195         }
8196         *cache_matcher = *matcher;
8197         dv_attr.match_criteria_enable =
8198                 flow_dv_matcher_enable(cache_matcher->mask.buf);
8199         dv_attr.priority = matcher->priority;
8200         if (key->direction)
8201                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8202         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
8203                                                &cache_matcher->matcher_object);
8204         if (ret) {
8205                 mlx5_free(cache_matcher);
8206 #ifdef HAVE_MLX5DV_DR
8207                 flow_dv_tbl_resource_release(dev, tbl);
8208 #endif
8209                 return rte_flow_error_set(error, ENOMEM,
8210                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8211                                           NULL, "cannot create matcher");
8212         }
8213         /* Save the table information */
8214         cache_matcher->tbl = tbl;
8215         rte_atomic32_init(&cache_matcher->refcnt);
8216         /* only matcher ref++, table ref++ already done above in get API. */
8217         rte_atomic32_inc(&cache_matcher->refcnt);
8218         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
8219         dev_flow->handle->dvh.matcher = cache_matcher;
8220         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
8221                 key->domain ? "FDB" : "NIC", key->table_id,
8222                 cache_matcher->priority,
8223                 key->direction ? "tx" : "rx", (void *)cache_matcher,
8224                 rte_atomic32_read(&cache_matcher->refcnt));
8225         return 0;
8226 }
8227
8228 /**
8229  * Find existing tag resource or create and register a new one.
8230  *
8231  * @param dev[in, out]
8232  *   Pointer to rte_eth_dev structure.
8233  * @param[in, out] tag_be24
8234  *   Tag value in big endian then R-shift 8.
8235  * @parm[in, out] dev_flow
8236  *   Pointer to the dev_flow.
8237  * @param[out] error
8238  *   pointer to error structure.
8239  *
8240  * @return
8241  *   0 on success otherwise -errno and errno is set.
8242  */
8243 static int
8244 flow_dv_tag_resource_register
8245                         (struct rte_eth_dev *dev,
8246                          uint32_t tag_be24,
8247                          struct mlx5_flow *dev_flow,
8248                          struct rte_flow_error *error)
8249 {
8250         struct mlx5_priv *priv = dev->data->dev_private;
8251         struct mlx5_dev_ctx_shared *sh = priv->sh;
8252         struct mlx5_flow_dv_tag_resource *cache_resource;
8253         struct mlx5_hlist_entry *entry;
8254         int ret;
8255
8256         /* Lookup a matching resource from cache. */
8257         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
8258         if (entry) {
8259                 cache_resource = container_of
8260                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8261                 rte_atomic32_inc(&cache_resource->refcnt);
8262                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8263                 dev_flow->dv.tag_resource = cache_resource;
8264                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
8265                         (void *)cache_resource,
8266                         rte_atomic32_read(&cache_resource->refcnt));
8267                 return 0;
8268         }
8269         /* Register new resource. */
8270         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
8271                                        &dev_flow->handle->dvh.rix_tag);
8272         if (!cache_resource)
8273                 return rte_flow_error_set(error, ENOMEM,
8274                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8275                                           "cannot allocate resource memory");
8276         cache_resource->entry.key = (uint64_t)tag_be24;
8277         ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
8278                                                   &cache_resource->action);
8279         if (ret) {
8280                 mlx5_free(cache_resource);
8281                 return rte_flow_error_set(error, ENOMEM,
8282                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8283                                           NULL, "cannot create action");
8284         }
8285         rte_atomic32_init(&cache_resource->refcnt);
8286         rte_atomic32_inc(&cache_resource->refcnt);
8287         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
8288                 mlx5_flow_os_destroy_flow_action(cache_resource->action);
8289                 mlx5_free(cache_resource);
8290                 return rte_flow_error_set(error, EEXIST,
8291                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8292                                           NULL, "cannot insert tag");
8293         }
8294         dev_flow->dv.tag_resource = cache_resource;
8295         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
8296                 (void *)cache_resource,
8297                 rte_atomic32_read(&cache_resource->refcnt));
8298         return 0;
8299 }
8300
8301 /**
8302  * Release the tag.
8303  *
8304  * @param dev
8305  *   Pointer to Ethernet device.
8306  * @param tag_idx
8307  *   Tag index.
8308  *
8309  * @return
8310  *   1 while a reference on it exists, 0 when freed.
8311  */
8312 static int
8313 flow_dv_tag_release(struct rte_eth_dev *dev,
8314                     uint32_t tag_idx)
8315 {
8316         struct mlx5_priv *priv = dev->data->dev_private;
8317         struct mlx5_dev_ctx_shared *sh = priv->sh;
8318         struct mlx5_flow_dv_tag_resource *tag;
8319
8320         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8321         if (!tag)
8322                 return 0;
8323         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8324                 dev->data->port_id, (void *)tag,
8325                 rte_atomic32_read(&tag->refcnt));
8326         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
8327                 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8328                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
8329                 DRV_LOG(DEBUG, "port %u tag %p: removed",
8330                         dev->data->port_id, (void *)tag);
8331                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8332                 return 0;
8333         }
8334         return 1;
8335 }
8336
8337 /**
8338  * Translate port ID action to vport.
8339  *
8340  * @param[in] dev
8341  *   Pointer to rte_eth_dev structure.
8342  * @param[in] action
8343  *   Pointer to the port ID action.
8344  * @param[out] dst_port_id
8345  *   The target port ID.
8346  * @param[out] error
8347  *   Pointer to the error structure.
8348  *
8349  * @return
8350  *   0 on success, a negative errno value otherwise and rte_errno is set.
8351  */
8352 static int
8353 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8354                                  const struct rte_flow_action *action,
8355                                  uint32_t *dst_port_id,
8356                                  struct rte_flow_error *error)
8357 {
8358         uint32_t port;
8359         struct mlx5_priv *priv;
8360         const struct rte_flow_action_port_id *conf =
8361                         (const struct rte_flow_action_port_id *)action->conf;
8362
8363         port = conf->original ? dev->data->port_id : conf->id;
8364         priv = mlx5_port_to_eswitch_info(port, false);
8365         if (!priv)
8366                 return rte_flow_error_set(error, -rte_errno,
8367                                           RTE_FLOW_ERROR_TYPE_ACTION,
8368                                           NULL,
8369                                           "No eswitch info was found for port");
8370 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8371         /*
8372          * This parameter is transferred to
8373          * mlx5dv_dr_action_create_dest_ib_port().
8374          */
8375         *dst_port_id = priv->dev_port;
8376 #else
8377         /*
8378          * Legacy mode, no LAG configurations is supported.
8379          * This parameter is transferred to
8380          * mlx5dv_dr_action_create_dest_vport().
8381          */
8382         *dst_port_id = priv->vport_id;
8383 #endif
8384         return 0;
8385 }
8386
8387 /**
8388  * Create a counter with aging configuration.
8389  *
8390  * @param[in] dev
8391  *   Pointer to rte_eth_dev structure.
8392  * @param[out] count
8393  *   Pointer to the counter action configuration.
8394  * @param[in] age
8395  *   Pointer to the aging action configuration.
8396  *
8397  * @return
8398  *   Index to flow counter on success, 0 otherwise.
8399  */
8400 static uint32_t
8401 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8402                                 struct mlx5_flow *dev_flow,
8403                                 const struct rte_flow_action_count *count,
8404                                 const struct rte_flow_action_age *age)
8405 {
8406         uint32_t counter;
8407         struct mlx5_age_param *age_param;
8408
8409         if (count && count->shared)
8410                 counter = flow_dv_counter_get_shared(dev, count->id);
8411         else
8412                 counter = flow_dv_counter_alloc(dev, !!age);
8413         if (!counter || age == NULL)
8414                 return counter;
8415         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8416         age_param->context = age->context ? age->context :
8417                 (void *)(uintptr_t)(dev_flow->flow_idx);
8418         age_param->timeout = age->timeout;
8419         age_param->port_id = dev->data->port_id;
8420         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8421         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8422         return counter;
8423 }
8424 /**
8425  * Add Tx queue matcher
8426  *
8427  * @param[in] dev
8428  *   Pointer to the dev struct.
8429  * @param[in, out] matcher
8430  *   Flow matcher.
8431  * @param[in, out] key
8432  *   Flow matcher value.
8433  * @param[in] item
8434  *   Flow pattern to translate.
8435  * @param[in] inner
8436  *   Item is inner pattern.
8437  */
8438 static void
8439 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8440                                 void *matcher, void *key,
8441                                 const struct rte_flow_item *item)
8442 {
8443         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8444         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8445         void *misc_m =
8446                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8447         void *misc_v =
8448                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8449         struct mlx5_txq_ctrl *txq;
8450         uint32_t queue;
8451
8452
8453         queue_m = (const void *)item->mask;
8454         if (!queue_m)
8455                 return;
8456         queue_v = (const void *)item->spec;
8457         if (!queue_v)
8458                 return;
8459         txq = mlx5_txq_get(dev, queue_v->queue);
8460         if (!txq)
8461                 return;
8462         queue = txq->obj->sq->id;
8463         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8464         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8465                  queue & queue_m->queue);
8466         mlx5_txq_release(dev, queue_v->queue);
8467 }
8468
8469 /**
8470  * Set the hash fields according to the @p flow information.
8471  *
8472  * @param[in] dev_flow
8473  *   Pointer to the mlx5_flow.
8474  * @param[in] rss_desc
8475  *   Pointer to the mlx5_flow_rss_desc.
8476  */
8477 static void
8478 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8479                        struct mlx5_flow_rss_desc *rss_desc)
8480 {
8481         uint64_t items = dev_flow->handle->layers;
8482         int rss_inner = 0;
8483         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8484
8485         dev_flow->hash_fields = 0;
8486 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8487         if (rss_desc->level >= 2) {
8488                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8489                 rss_inner = 1;
8490         }
8491 #endif
8492         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8493             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8494                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8495                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8496                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8497                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8498                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8499                         else
8500                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8501                 }
8502         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8503                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8504                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8505                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8506                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8507                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8508                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8509                         else
8510                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8511                 }
8512         }
8513         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8514             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8515                 if (rss_types & ETH_RSS_UDP) {
8516                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8517                                 dev_flow->hash_fields |=
8518                                                 IBV_RX_HASH_SRC_PORT_UDP;
8519                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8520                                 dev_flow->hash_fields |=
8521                                                 IBV_RX_HASH_DST_PORT_UDP;
8522                         else
8523                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8524                 }
8525         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8526                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8527                 if (rss_types & ETH_RSS_TCP) {
8528                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8529                                 dev_flow->hash_fields |=
8530                                                 IBV_RX_HASH_SRC_PORT_TCP;
8531                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8532                                 dev_flow->hash_fields |=
8533                                                 IBV_RX_HASH_DST_PORT_TCP;
8534                         else
8535                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8536                 }
8537         }
8538 }
8539
8540 /**
8541  * Create an Rx Hash queue.
8542  *
8543  * @param dev
8544  *   Pointer to Ethernet device.
8545  * @param[in] dev_flow
8546  *   Pointer to the mlx5_flow.
8547  * @param[in] rss_desc
8548  *   Pointer to the mlx5_flow_rss_desc.
8549  * @param[out] hrxq_idx
8550  *   Hash Rx queue index.
8551  *
8552  * @return
8553  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8554  */
8555 static struct mlx5_hrxq *
8556 flow_dv_handle_rx_queue(struct rte_eth_dev *dev,
8557                         struct mlx5_flow *dev_flow,
8558                         struct mlx5_flow_rss_desc *rss_desc,
8559                         uint32_t *hrxq_idx)
8560 {
8561         struct mlx5_priv *priv = dev->data->dev_private;
8562         struct mlx5_flow_handle *dh = dev_flow->handle;
8563         struct mlx5_hrxq *hrxq;
8564
8565         MLX5_ASSERT(rss_desc->queue_num);
8566         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8567                                   dev_flow->hash_fields,
8568                                   rss_desc->queue, rss_desc->queue_num);
8569         if (!*hrxq_idx) {
8570                 *hrxq_idx = mlx5_hrxq_new
8571                                 (dev, rss_desc->key, MLX5_RSS_HASH_KEY_LEN,
8572                                  dev_flow->hash_fields,
8573                                  rss_desc->queue, rss_desc->queue_num,
8574                                  !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL),
8575                                  false);
8576                 if (!*hrxq_idx)
8577                         return NULL;
8578         }
8579         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8580                               *hrxq_idx);
8581         return hrxq;
8582 }
8583
8584 /**
8585  * Find existing sample resource or create and register a new one.
8586  *
8587  * @param[in, out] dev
8588  *   Pointer to rte_eth_dev structure.
8589  * @param[in] attr
8590  *   Attributes of flow that includes this item.
8591  * @param[in] resource
8592  *   Pointer to sample resource.
8593  * @parm[in, out] dev_flow
8594  *   Pointer to the dev_flow.
8595  * @param[in, out] sample_dv_actions
8596  *   Pointer to sample actions list.
8597  * @param[out] error
8598  *   pointer to error structure.
8599  *
8600  * @return
8601  *   0 on success otherwise -errno and errno is set.
8602  */
8603 static int
8604 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8605                          const struct rte_flow_attr *attr,
8606                          struct mlx5_flow_dv_sample_resource *resource,
8607                          struct mlx5_flow *dev_flow,
8608                          void **sample_dv_actions,
8609                          struct rte_flow_error *error)
8610 {
8611         struct mlx5_flow_dv_sample_resource *cache_resource;
8612         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8613         struct mlx5_priv *priv = dev->data->dev_private;
8614         struct mlx5_dev_ctx_shared *sh = priv->sh;
8615         struct mlx5_flow_tbl_resource *tbl;
8616         uint32_t idx = 0;
8617         const uint32_t next_ft_step = 1;
8618         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8619
8620         /* Lookup a matching resource from cache. */
8621         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_SAMPLE], sh->sample_action_list,
8622                       idx, cache_resource, next) {
8623                 if (resource->ratio == cache_resource->ratio &&
8624                     resource->ft_type == cache_resource->ft_type &&
8625                     resource->ft_id == cache_resource->ft_id &&
8626                     resource->set_action == cache_resource->set_action &&
8627                     !memcmp((void *)&resource->sample_act,
8628                             (void *)&cache_resource->sample_act,
8629                             sizeof(struct mlx5_flow_sub_actions_list))) {
8630                         DRV_LOG(DEBUG, "sample resource %p: refcnt %d++",
8631                                 (void *)cache_resource,
8632                                 __atomic_load_n(&cache_resource->refcnt,
8633                                                 __ATOMIC_RELAXED));
8634                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8635                                            __ATOMIC_RELAXED);
8636                         dev_flow->handle->dvh.rix_sample = idx;
8637                         dev_flow->dv.sample_res = cache_resource;
8638                         return 0;
8639                 }
8640         }
8641         /* Register new sample resource. */
8642         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE],
8643                                        &dev_flow->handle->dvh.rix_sample);
8644         if (!cache_resource)
8645                 return rte_flow_error_set(error, ENOMEM,
8646                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8647                                           NULL,
8648                                           "cannot allocate resource memory");
8649         *cache_resource = *resource;
8650         /* Create normal path table level */
8651         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8652                                         attr->egress, attr->transfer,
8653                                         dev_flow->external, NULL, 0, error);
8654         if (!tbl) {
8655                 rte_flow_error_set(error, ENOMEM,
8656                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8657                                           NULL,
8658                                           "fail to create normal path table "
8659                                           "for sample");
8660                 goto error;
8661         }
8662         cache_resource->normal_path_tbl = tbl;
8663         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8664                 cache_resource->default_miss =
8665                                 mlx5_glue->dr_create_flow_action_default_miss();
8666                 if (!cache_resource->default_miss) {
8667                         rte_flow_error_set(error, ENOMEM,
8668                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8669                                                 NULL,
8670                                                 "cannot create default miss "
8671                                                 "action");
8672                         goto error;
8673                 }
8674                 sample_dv_actions[resource->sample_act.actions_num++] =
8675                                                 cache_resource->default_miss;
8676         }
8677         /* Create a DR sample action */
8678         sampler_attr.sample_ratio = cache_resource->ratio;
8679         sampler_attr.default_next_table = tbl->obj;
8680         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8681         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8682                                                         &sample_dv_actions[0];
8683         sampler_attr.action = cache_resource->set_action;
8684         cache_resource->verbs_action =
8685                 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8686         if (!cache_resource->verbs_action) {
8687                 rte_flow_error_set(error, ENOMEM,
8688                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8689                                         NULL, "cannot create sample action");
8690                 goto error;
8691         }
8692         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8693         ILIST_INSERT(sh->ipool[MLX5_IPOOL_SAMPLE], &sh->sample_action_list,
8694                      dev_flow->handle->dvh.rix_sample, cache_resource,
8695                      next);
8696         dev_flow->dv.sample_res = cache_resource;
8697         DRV_LOG(DEBUG, "new sample resource %p: refcnt %d++",
8698                 (void *)cache_resource,
8699                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8700         return 0;
8701 error:
8702         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8703                 if (cache_resource->default_miss)
8704                         claim_zero(mlx5_glue->destroy_flow_action
8705                                 (cache_resource->default_miss));
8706         } else {
8707                 if (cache_resource->sample_idx.rix_hrxq &&
8708                     !mlx5_hrxq_release(dev,
8709                                 cache_resource->sample_idx.rix_hrxq))
8710                         cache_resource->sample_idx.rix_hrxq = 0;
8711                 if (cache_resource->sample_idx.rix_tag &&
8712                     !flow_dv_tag_release(dev,
8713                                 cache_resource->sample_idx.rix_tag))
8714                         cache_resource->sample_idx.rix_tag = 0;
8715                 if (cache_resource->sample_idx.cnt) {
8716                         flow_dv_counter_release(dev,
8717                                 cache_resource->sample_idx.cnt);
8718                         cache_resource->sample_idx.cnt = 0;
8719                 }
8720         }
8721         if (cache_resource->normal_path_tbl)
8722                 flow_dv_tbl_resource_release(dev,
8723                                 cache_resource->normal_path_tbl);
8724         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE],
8725                                 dev_flow->handle->dvh.rix_sample);
8726         dev_flow->handle->dvh.rix_sample = 0;
8727         return -rte_errno;
8728 }
8729
8730 /**
8731  * Find existing destination array resource or create and register a new one.
8732  *
8733  * @param[in, out] dev
8734  *   Pointer to rte_eth_dev structure.
8735  * @param[in] attr
8736  *   Attributes of flow that includes this item.
8737  * @param[in] resource
8738  *   Pointer to destination array resource.
8739  * @parm[in, out] dev_flow
8740  *   Pointer to the dev_flow.
8741  * @param[out] error
8742  *   pointer to error structure.
8743  *
8744  * @return
8745  *   0 on success otherwise -errno and errno is set.
8746  */
8747 static int
8748 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
8749                          const struct rte_flow_attr *attr,
8750                          struct mlx5_flow_dv_dest_array_resource *resource,
8751                          struct mlx5_flow *dev_flow,
8752                          struct rte_flow_error *error)
8753 {
8754         struct mlx5_flow_dv_dest_array_resource *cache_resource;
8755         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8756         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8757         struct mlx5_priv *priv = dev->data->dev_private;
8758         struct mlx5_dev_ctx_shared *sh = priv->sh;
8759         struct mlx5_flow_sub_actions_list *sample_act;
8760         struct mlx5dv_dr_domain *domain;
8761         uint32_t idx = 0;
8762
8763         /* Lookup a matching resource from cache. */
8764         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8765                       sh->dest_array_list,
8766                       idx, cache_resource, next) {
8767                 if (resource->num_of_dest == cache_resource->num_of_dest &&
8768                     resource->ft_type == cache_resource->ft_type &&
8769                     !memcmp((void *)cache_resource->sample_act,
8770                             (void *)resource->sample_act,
8771                            (resource->num_of_dest *
8772                            sizeof(struct mlx5_flow_sub_actions_list)))) {
8773                         DRV_LOG(DEBUG, "dest array resource %p: refcnt %d++",
8774                                 (void *)cache_resource,
8775                                 __atomic_load_n(&cache_resource->refcnt,
8776                                                 __ATOMIC_RELAXED));
8777                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8778                                            __ATOMIC_RELAXED);
8779                         dev_flow->handle->dvh.rix_dest_array = idx;
8780                         dev_flow->dv.dest_array_res = cache_resource;
8781                         return 0;
8782                 }
8783         }
8784         /* Register new destination array resource. */
8785         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8786                                        &dev_flow->handle->dvh.rix_dest_array);
8787         if (!cache_resource)
8788                 return rte_flow_error_set(error, ENOMEM,
8789                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8790                                           NULL,
8791                                           "cannot allocate resource memory");
8792         *cache_resource = *resource;
8793         if (attr->transfer)
8794                 domain = sh->fdb_domain;
8795         else if (attr->ingress)
8796                 domain = sh->rx_domain;
8797         else
8798                 domain = sh->tx_domain;
8799         for (idx = 0; idx < resource->num_of_dest; idx++) {
8800                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8801                                  mlx5_malloc(MLX5_MEM_ZERO,
8802                                  sizeof(struct mlx5dv_dr_action_dest_attr),
8803                                  0, SOCKET_ID_ANY);
8804                 if (!dest_attr[idx]) {
8805                         rte_flow_error_set(error, ENOMEM,
8806                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8807                                            NULL,
8808                                            "cannot allocate resource memory");
8809                         goto error;
8810                 }
8811                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8812                 sample_act = &resource->sample_act[idx];
8813                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8814                         dest_attr[idx]->dest = sample_act->dr_queue_action;
8815                 } else if (sample_act->action_flags ==
8816                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8817                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8818                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8819                         dest_attr[idx]->dest_reformat->reformat =
8820                                         sample_act->dr_encap_action;
8821                         dest_attr[idx]->dest_reformat->dest =
8822                                         sample_act->dr_port_id_action;
8823                 } else if (sample_act->action_flags ==
8824                            MLX5_FLOW_ACTION_PORT_ID) {
8825                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
8826                 }
8827         }
8828         /* create a dest array actioin */
8829         cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8830                                                 (domain,
8831                                                  cache_resource->num_of_dest,
8832                                                  dest_attr);
8833         if (!cache_resource->action) {
8834                 rte_flow_error_set(error, ENOMEM,
8835                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8836                                    NULL,
8837                                    "cannot create destination array action");
8838                 goto error;
8839         }
8840         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8841         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8842                      &sh->dest_array_list,
8843                      dev_flow->handle->dvh.rix_dest_array, cache_resource,
8844                      next);
8845         dev_flow->dv.dest_array_res = cache_resource;
8846         DRV_LOG(DEBUG, "new destination array resource %p: refcnt %d++",
8847                 (void *)cache_resource,
8848                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8849         for (idx = 0; idx < resource->num_of_dest; idx++)
8850                 mlx5_free(dest_attr[idx]);
8851         return 0;
8852 error:
8853         for (idx = 0; idx < resource->num_of_dest; idx++) {
8854                 struct mlx5_flow_sub_actions_idx *act_res =
8855                                         &cache_resource->sample_idx[idx];
8856                 if (act_res->rix_hrxq &&
8857                     !mlx5_hrxq_release(dev,
8858                                 act_res->rix_hrxq))
8859                         act_res->rix_hrxq = 0;
8860                 if (act_res->rix_encap_decap &&
8861                         !flow_dv_encap_decap_resource_release(dev,
8862                                 act_res->rix_encap_decap))
8863                         act_res->rix_encap_decap = 0;
8864                 if (act_res->rix_port_id_action &&
8865                         !flow_dv_port_id_action_resource_release(dev,
8866                                 act_res->rix_port_id_action))
8867                         act_res->rix_port_id_action = 0;
8868                 if (dest_attr[idx])
8869                         mlx5_free(dest_attr[idx]);
8870         }
8871
8872         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8873                                 dev_flow->handle->dvh.rix_dest_array);
8874         dev_flow->handle->dvh.rix_dest_array = 0;
8875         return -rte_errno;
8876 }
8877
8878 /**
8879  * Convert Sample action to DV specification.
8880  *
8881  * @param[in] dev
8882  *   Pointer to rte_eth_dev structure.
8883  * @param[in] action
8884  *   Pointer to action structure.
8885  * @param[in, out] dev_flow
8886  *   Pointer to the mlx5_flow.
8887  * @param[in] attr
8888  *   Pointer to the flow attributes.
8889  * @param[in, out] num_of_dest
8890  *   Pointer to the num of destination.
8891  * @param[in, out] sample_actions
8892  *   Pointer to sample actions list.
8893  * @param[in, out] res
8894  *   Pointer to sample resource.
8895  * @param[out] error
8896  *   Pointer to the error structure.
8897  *
8898  * @return
8899  *   0 on success, a negative errno value otherwise and rte_errno is set.
8900  */
8901 static int
8902 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
8903                                 const struct rte_flow_action *action,
8904                                 struct mlx5_flow *dev_flow,
8905                                 const struct rte_flow_attr *attr,
8906                                 uint32_t *num_of_dest,
8907                                 void **sample_actions,
8908                                 struct mlx5_flow_dv_sample_resource *res,
8909                                 struct rte_flow_error *error)
8910 {
8911         struct mlx5_priv *priv = dev->data->dev_private;
8912         const struct rte_flow_action_sample *sample_action;
8913         const struct rte_flow_action *sub_actions;
8914         const struct rte_flow_action_queue *queue;
8915         struct mlx5_flow_sub_actions_list *sample_act;
8916         struct mlx5_flow_sub_actions_idx *sample_idx;
8917         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
8918                                               priv->rss_desc)
8919                                               [!!priv->flow_nested_idx];
8920         uint64_t action_flags = 0;
8921
8922         sample_act = &res->sample_act;
8923         sample_idx = &res->sample_idx;
8924         sample_action = (const struct rte_flow_action_sample *)action->conf;
8925         res->ratio = sample_action->ratio;
8926         sub_actions = sample_action->actions;
8927         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
8928                 int type = sub_actions->type;
8929                 uint32_t pre_rix = 0;
8930                 void *pre_r;
8931                 switch (type) {
8932                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8933                 {
8934                         struct mlx5_hrxq *hrxq;
8935                         uint32_t hrxq_idx;
8936
8937                         queue = sub_actions->conf;
8938                         rss_desc->queue_num = 1;
8939                         rss_desc->queue[0] = queue->index;
8940                         hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
8941                                         rss_desc, &hrxq_idx);
8942                         if (!hrxq)
8943                                 return rte_flow_error_set
8944                                         (error, rte_errno,
8945                                          RTE_FLOW_ERROR_TYPE_ACTION,
8946                                          NULL,
8947                                          "cannot create fate queue");
8948                         sample_act->dr_queue_action = hrxq->action;
8949                         sample_idx->rix_hrxq = hrxq_idx;
8950                         sample_actions[sample_act->actions_num++] =
8951                                                 hrxq->action;
8952                         (*num_of_dest)++;
8953                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8954                         if (action_flags & MLX5_FLOW_ACTION_MARK)
8955                                 dev_flow->handle->rix_hrxq = hrxq_idx;
8956                         dev_flow->handle->fate_action =
8957                                         MLX5_FLOW_FATE_QUEUE;
8958                         break;
8959                 }
8960                 case RTE_FLOW_ACTION_TYPE_MARK:
8961                 {
8962                         uint32_t tag_be = mlx5_flow_mark_set
8963                                 (((const struct rte_flow_action_mark *)
8964                                 (sub_actions->conf))->id);
8965
8966                         dev_flow->handle->mark = 1;
8967                         pre_rix = dev_flow->handle->dvh.rix_tag;
8968                         /* Save the mark resource before sample */
8969                         pre_r = dev_flow->dv.tag_resource;
8970                         if (flow_dv_tag_resource_register(dev, tag_be,
8971                                                   dev_flow, error))
8972                                 return -rte_errno;
8973                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8974                         sample_act->dr_tag_action =
8975                                 dev_flow->dv.tag_resource->action;
8976                         sample_idx->rix_tag =
8977                                 dev_flow->handle->dvh.rix_tag;
8978                         sample_actions[sample_act->actions_num++] =
8979                                                 sample_act->dr_tag_action;
8980                         /* Recover the mark resource after sample */
8981                         dev_flow->dv.tag_resource = pre_r;
8982                         dev_flow->handle->dvh.rix_tag = pre_rix;
8983                         action_flags |= MLX5_FLOW_ACTION_MARK;
8984                         break;
8985                 }
8986                 case RTE_FLOW_ACTION_TYPE_COUNT:
8987                 {
8988                         uint32_t counter;
8989
8990                         counter = flow_dv_translate_create_counter(dev,
8991                                         dev_flow, sub_actions->conf, 0);
8992                         if (!counter)
8993                                 return rte_flow_error_set
8994                                                 (error, rte_errno,
8995                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8996                                                  NULL,
8997                                                  "cannot create counter"
8998                                                  " object.");
8999                         sample_idx->cnt = counter;
9000                         sample_act->dr_cnt_action =
9001                                   (flow_dv_counter_get_by_idx(dev,
9002                                   counter, NULL))->action;
9003                         sample_actions[sample_act->actions_num++] =
9004                                                 sample_act->dr_cnt_action;
9005                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9006                         break;
9007                 }
9008                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9009                 {
9010                         struct mlx5_flow_dv_port_id_action_resource
9011                                         port_id_resource;
9012                         uint32_t port_id = 0;
9013
9014                         memset(&port_id_resource, 0, sizeof(port_id_resource));
9015                         /* Save the port id resource before sample */
9016                         pre_rix = dev_flow->handle->rix_port_id_action;
9017                         pre_r = dev_flow->dv.port_id_action;
9018                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9019                                                              &port_id, error))
9020                                 return -rte_errno;
9021                         port_id_resource.port_id = port_id;
9022                         if (flow_dv_port_id_action_resource_register
9023                             (dev, &port_id_resource, dev_flow, error))
9024                                 return -rte_errno;
9025                         sample_act->dr_port_id_action =
9026                                 dev_flow->dv.port_id_action->action;
9027                         sample_idx->rix_port_id_action =
9028                                 dev_flow->handle->rix_port_id_action;
9029                         sample_actions[sample_act->actions_num++] =
9030                                                 sample_act->dr_port_id_action;
9031                         /* Recover the port id resource after sample */
9032                         dev_flow->dv.port_id_action = pre_r;
9033                         dev_flow->handle->rix_port_id_action = pre_rix;
9034                         (*num_of_dest)++;
9035                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9036                         break;
9037                 }
9038                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9039                         /* Save the encap resource before sample */
9040                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9041                         pre_r = dev_flow->dv.encap_decap;
9042                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9043                                                            dev_flow,
9044                                                            attr->transfer,
9045                                                            error))
9046                                 return -rte_errno;
9047                         sample_act->dr_encap_action =
9048                                 dev_flow->dv.encap_decap->action;
9049                         sample_idx->rix_encap_decap =
9050                                 dev_flow->handle->dvh.rix_encap_decap;
9051                         sample_actions[sample_act->actions_num++] =
9052                                                 sample_act->dr_encap_action;
9053                         /* Recover the encap resource after sample */
9054                         dev_flow->dv.encap_decap = pre_r;
9055                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9056                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9057                         break;
9058                 default:
9059                         return rte_flow_error_set(error, EINVAL,
9060                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9061                                 NULL,
9062                                 "Not support for sampler action");
9063                 }
9064         }
9065         sample_act->action_flags = action_flags;
9066         res->ft_id = dev_flow->dv.group;
9067         if (attr->transfer) {
9068                 union {
9069                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9070                         uint64_t set_action;
9071                 } action_ctx = { .set_action = 0 };
9072
9073                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9074                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9075                          MLX5_MODIFICATION_TYPE_SET);
9076                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9077                          MLX5_MODI_META_REG_C_0);
9078                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9079                          priv->vport_meta_tag);
9080                 res->set_action = action_ctx.set_action;
9081         } else if (attr->ingress) {
9082                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9083         }
9084         return 0;
9085 }
9086
9087 /**
9088  * Convert Sample action to DV specification.
9089  *
9090  * @param[in] dev
9091  *   Pointer to rte_eth_dev structure.
9092  * @param[in, out] dev_flow
9093  *   Pointer to the mlx5_flow.
9094  * @param[in] attr
9095  *   Pointer to the flow attributes.
9096  * @param[in] num_of_dest
9097  *   The num of destination.
9098  * @param[in, out] res
9099  *   Pointer to sample resource.
9100  * @param[in, out] mdest_res
9101  *   Pointer to destination array resource.
9102  * @param[in] sample_actions
9103  *   Pointer to sample path actions list.
9104  * @param[in] action_flags
9105  *   Holds the actions detected until now.
9106  * @param[out] error
9107  *   Pointer to the error structure.
9108  *
9109  * @return
9110  *   0 on success, a negative errno value otherwise and rte_errno is set.
9111  */
9112 static int
9113 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9114                              struct mlx5_flow *dev_flow,
9115                              const struct rte_flow_attr *attr,
9116                              uint32_t num_of_dest,
9117                              struct mlx5_flow_dv_sample_resource *res,
9118                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9119                              void **sample_actions,
9120                              uint64_t action_flags,
9121                              struct rte_flow_error *error)
9122 {
9123         struct mlx5_priv *priv = dev->data->dev_private;
9124         /* update normal path action resource into last index of array */
9125         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9126         struct mlx5_flow_sub_actions_list *sample_act =
9127                                         &mdest_res->sample_act[dest_index];
9128         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
9129                                               priv->rss_desc)
9130                                               [!!priv->flow_nested_idx];
9131         uint32_t normal_idx = 0;
9132         struct mlx5_hrxq *hrxq;
9133         uint32_t hrxq_idx;
9134
9135         if (num_of_dest > 1) {
9136                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9137                         /* Handle QP action for mirroring */
9138                         hrxq = flow_dv_handle_rx_queue(dev, dev_flow,
9139                                                        rss_desc, &hrxq_idx);
9140                         if (!hrxq)
9141                                 return rte_flow_error_set
9142                                      (error, rte_errno,
9143                                       RTE_FLOW_ERROR_TYPE_ACTION,
9144                                       NULL,
9145                                       "cannot create rx queue");
9146                         normal_idx++;
9147                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9148                         sample_act->dr_queue_action = hrxq->action;
9149                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9150                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9151                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9152                 }
9153                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9154                         normal_idx++;
9155                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9156                                 dev_flow->handle->dvh.rix_encap_decap;
9157                         sample_act->dr_encap_action =
9158                                 dev_flow->dv.encap_decap->action;
9159                 }
9160                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9161                         normal_idx++;
9162                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9163                                 dev_flow->handle->rix_port_id_action;
9164                         sample_act->dr_port_id_action =
9165                                 dev_flow->dv.port_id_action->action;
9166                 }
9167                 sample_act->actions_num = normal_idx;
9168                 /* update sample action resource into first index of array */
9169                 mdest_res->ft_type = res->ft_type;
9170                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9171                                 sizeof(struct mlx5_flow_sub_actions_idx));
9172                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9173                                 sizeof(struct mlx5_flow_sub_actions_list));
9174                 mdest_res->num_of_dest = num_of_dest;
9175                 if (flow_dv_dest_array_resource_register(dev, attr, mdest_res,
9176                                                          dev_flow, error))
9177                         return rte_flow_error_set(error, EINVAL,
9178                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9179                                                   NULL, "can't create sample "
9180                                                   "action");
9181         } else {
9182                 if (flow_dv_sample_resource_register(dev, attr, res, dev_flow,
9183                                                      sample_actions, error))
9184                         return rte_flow_error_set(error, EINVAL,
9185                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9186                                                   NULL,
9187                                                   "can't create sample action");
9188         }
9189         return 0;
9190 }
9191
9192 /**
9193  * Fill the flow with DV spec, lock free
9194  * (mutex should be acquired by caller).
9195  *
9196  * @param[in] dev
9197  *   Pointer to rte_eth_dev structure.
9198  * @param[in, out] dev_flow
9199  *   Pointer to the sub flow.
9200  * @param[in] attr
9201  *   Pointer to the flow attributes.
9202  * @param[in] items
9203  *   Pointer to the list of items.
9204  * @param[in] actions
9205  *   Pointer to the list of actions.
9206  * @param[out] error
9207  *   Pointer to the error structure.
9208  *
9209  * @return
9210  *   0 on success, a negative errno value otherwise and rte_errno is set.
9211  */
9212 static int
9213 __flow_dv_translate(struct rte_eth_dev *dev,
9214                     struct mlx5_flow *dev_flow,
9215                     const struct rte_flow_attr *attr,
9216                     const struct rte_flow_item items[],
9217                     const struct rte_flow_action actions[],
9218                     struct rte_flow_error *error)
9219 {
9220         struct mlx5_priv *priv = dev->data->dev_private;
9221         struct mlx5_dev_config *dev_conf = &priv->config;
9222         struct rte_flow *flow = dev_flow->flow;
9223         struct mlx5_flow_handle *handle = dev_flow->handle;
9224         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
9225                                               priv->rss_desc)
9226                                               [!!priv->flow_nested_idx];
9227         uint64_t item_flags = 0;
9228         uint64_t last_item = 0;
9229         uint64_t action_flags = 0;
9230         uint64_t priority = attr->priority;
9231         struct mlx5_flow_dv_matcher matcher = {
9232                 .mask = {
9233                         .size = sizeof(matcher.mask.buf) -
9234                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9235                 },
9236         };
9237         int actions_n = 0;
9238         bool actions_end = false;
9239         union {
9240                 struct mlx5_flow_dv_modify_hdr_resource res;
9241                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9242                             sizeof(struct mlx5_modification_cmd) *
9243                             (MLX5_MAX_MODIFY_NUM + 1)];
9244         } mhdr_dummy;
9245         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9246         const struct rte_flow_action_count *count = NULL;
9247         const struct rte_flow_action_age *age = NULL;
9248         union flow_dv_attr flow_attr = { .attr = 0 };
9249         uint32_t tag_be;
9250         union mlx5_flow_tbl_key tbl_key;
9251         uint32_t modify_action_position = UINT32_MAX;
9252         void *match_mask = matcher.mask.buf;
9253         void *match_value = dev_flow->dv.value.buf;
9254         uint8_t next_protocol = 0xff;
9255         struct rte_vlan_hdr vlan = { 0 };
9256         struct mlx5_flow_dv_dest_array_resource mdest_res;
9257         struct mlx5_flow_dv_sample_resource sample_res;
9258         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9259         struct mlx5_flow_sub_actions_list *sample_act;
9260         uint32_t sample_act_pos = UINT32_MAX;
9261         uint32_t num_of_dest = 0;
9262         int tmp_actions_n = 0;
9263         uint32_t table;
9264         int ret = 0;
9265         const struct mlx5_flow_tunnel *tunnel;
9266         struct flow_grp_info grp_info = {
9267                 .external = !!dev_flow->external,
9268                 .transfer = !!attr->transfer,
9269                 .fdb_def_rule = !!priv->fdb_def_rule,
9270         };
9271
9272         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9273         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9274         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9275                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9276         /* update normal path action resource into last index of array */
9277         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9278         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9279                  flow_items_to_tunnel(items) :
9280                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9281                  flow_actions_to_tunnel(actions) :
9282                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9283         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9284                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9285         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9286                                 (dev, tunnel, attr, items, actions);
9287         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9288                                        grp_info, error);
9289         if (ret)
9290                 return ret;
9291         dev_flow->dv.group = table;
9292         if (attr->transfer)
9293                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9294         if (priority == MLX5_FLOW_PRIO_RSVD)
9295                 priority = dev_conf->flow_prio - 1;
9296         /* number of actions must be set to 0 in case of dirty stack. */
9297         mhdr_res->actions_num = 0;
9298         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9299                 /*
9300                  * do not add decap action if match rule drops packet
9301                  * HW rejects rules with decap & drop
9302                  */
9303                 bool add_decap = true;
9304                 const struct rte_flow_action *ptr = actions;
9305                 struct mlx5_flow_tbl_resource *tbl;
9306
9307                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9308                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9309                                 add_decap = false;
9310                                 break;
9311                         }
9312                 }
9313                 if (add_decap) {
9314                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9315                                                            attr->transfer,
9316                                                            error))
9317                                 return -rte_errno;
9318                         dev_flow->dv.actions[actions_n++] =
9319                                         dev_flow->dv.encap_decap->action;
9320                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9321                 }
9322                 /*
9323                  * bind table_id with <group, table> for tunnel match rule.
9324                  * Tunnel set rule establishes that bind in JUMP action handler.
9325                  * Required for scenario when application creates tunnel match
9326                  * rule before tunnel set rule.
9327                  */
9328                 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9329                                                attr->transfer,
9330                                                !!dev_flow->external, tunnel,
9331                                                attr->group, error);
9332                 if (!tbl)
9333                         return rte_flow_error_set
9334                                (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
9335                                actions, "cannot register tunnel group");
9336         }
9337         for (; !actions_end ; actions++) {
9338                 const struct rte_flow_action_queue *queue;
9339                 const struct rte_flow_action_rss *rss;
9340                 const struct rte_flow_action *action = actions;
9341                 const uint8_t *rss_key;
9342                 const struct rte_flow_action_meter *mtr;
9343                 struct mlx5_flow_tbl_resource *tbl;
9344                 uint32_t port_id = 0;
9345                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9346                 int action_type = actions->type;
9347                 const struct rte_flow_action *found_action = NULL;
9348                 struct mlx5_flow_meter *fm = NULL;
9349                 uint32_t jump_group = 0;
9350
9351                 if (!mlx5_flow_os_action_supported(action_type))
9352                         return rte_flow_error_set(error, ENOTSUP,
9353                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9354                                                   actions,
9355                                                   "action not supported");
9356                 switch (action_type) {
9357                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9358                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9359                         break;
9360                 case RTE_FLOW_ACTION_TYPE_VOID:
9361                         break;
9362                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9363                         if (flow_dv_translate_action_port_id(dev, action,
9364                                                              &port_id, error))
9365                                 return -rte_errno;
9366                         port_id_resource.port_id = port_id;
9367                         MLX5_ASSERT(!handle->rix_port_id_action);
9368                         if (flow_dv_port_id_action_resource_register
9369                             (dev, &port_id_resource, dev_flow, error))
9370                                 return -rte_errno;
9371                         dev_flow->dv.actions[actions_n++] =
9372                                         dev_flow->dv.port_id_action->action;
9373                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9374                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9375                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9376                         num_of_dest++;
9377                         break;
9378                 case RTE_FLOW_ACTION_TYPE_FLAG:
9379                         action_flags |= MLX5_FLOW_ACTION_FLAG;
9380                         dev_flow->handle->mark = 1;
9381                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9382                                 struct rte_flow_action_mark mark = {
9383                                         .id = MLX5_FLOW_MARK_DEFAULT,
9384                                 };
9385
9386                                 if (flow_dv_convert_action_mark(dev, &mark,
9387                                                                 mhdr_res,
9388                                                                 error))
9389                                         return -rte_errno;
9390                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9391                                 break;
9392                         }
9393                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9394                         /*
9395                          * Only one FLAG or MARK is supported per device flow
9396                          * right now. So the pointer to the tag resource must be
9397                          * zero before the register process.
9398                          */
9399                         MLX5_ASSERT(!handle->dvh.rix_tag);
9400                         if (flow_dv_tag_resource_register(dev, tag_be,
9401                                                           dev_flow, error))
9402                                 return -rte_errno;
9403                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9404                         dev_flow->dv.actions[actions_n++] =
9405                                         dev_flow->dv.tag_resource->action;
9406                         break;
9407                 case RTE_FLOW_ACTION_TYPE_MARK:
9408                         action_flags |= MLX5_FLOW_ACTION_MARK;
9409                         dev_flow->handle->mark = 1;
9410                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9411                                 const struct rte_flow_action_mark *mark =
9412                                         (const struct rte_flow_action_mark *)
9413                                                 actions->conf;
9414
9415                                 if (flow_dv_convert_action_mark(dev, mark,
9416                                                                 mhdr_res,
9417                                                                 error))
9418                                         return -rte_errno;
9419                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9420                                 break;
9421                         }
9422                         /* Fall-through */
9423                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9424                         /* Legacy (non-extensive) MARK action. */
9425                         tag_be = mlx5_flow_mark_set
9426                               (((const struct rte_flow_action_mark *)
9427                                (actions->conf))->id);
9428                         MLX5_ASSERT(!handle->dvh.rix_tag);
9429                         if (flow_dv_tag_resource_register(dev, tag_be,
9430                                                           dev_flow, error))
9431                                 return -rte_errno;
9432                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9433                         dev_flow->dv.actions[actions_n++] =
9434                                         dev_flow->dv.tag_resource->action;
9435                         break;
9436                 case RTE_FLOW_ACTION_TYPE_SET_META:
9437                         if (flow_dv_convert_action_set_meta
9438                                 (dev, mhdr_res, attr,
9439                                  (const struct rte_flow_action_set_meta *)
9440                                   actions->conf, error))
9441                                 return -rte_errno;
9442                         action_flags |= MLX5_FLOW_ACTION_SET_META;
9443                         break;
9444                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9445                         if (flow_dv_convert_action_set_tag
9446                                 (dev, mhdr_res,
9447                                  (const struct rte_flow_action_set_tag *)
9448                                   actions->conf, error))
9449                                 return -rte_errno;
9450                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9451                         break;
9452                 case RTE_FLOW_ACTION_TYPE_DROP:
9453                         action_flags |= MLX5_FLOW_ACTION_DROP;
9454                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9455                         break;
9456                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9457                         queue = actions->conf;
9458                         rss_desc->queue_num = 1;
9459                         rss_desc->queue[0] = queue->index;
9460                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9461                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9462                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9463                         num_of_dest++;
9464                         break;
9465                 case RTE_FLOW_ACTION_TYPE_RSS:
9466                         rss = actions->conf;
9467                         memcpy(rss_desc->queue, rss->queue,
9468                                rss->queue_num * sizeof(uint16_t));
9469                         rss_desc->queue_num = rss->queue_num;
9470                         /* NULL RSS key indicates default RSS key. */
9471                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9472                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9473                         /*
9474                          * rss->level and rss.types should be set in advance
9475                          * when expanding items for RSS.
9476                          */
9477                         action_flags |= MLX5_FLOW_ACTION_RSS;
9478                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9479                         break;
9480                 case RTE_FLOW_ACTION_TYPE_AGE:
9481                 case RTE_FLOW_ACTION_TYPE_COUNT:
9482                         if (!dev_conf->devx) {
9483                                 return rte_flow_error_set
9484                                               (error, ENOTSUP,
9485                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9486                                                NULL,
9487                                                "count action not supported");
9488                         }
9489                         /* Save information first, will apply later. */
9490                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9491                                 count = action->conf;
9492                         else
9493                                 age = action->conf;
9494                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9495                         break;
9496                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9497                         dev_flow->dv.actions[actions_n++] =
9498                                                 priv->sh->pop_vlan_action;
9499                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9500                         break;
9501                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9502                         if (!(action_flags &
9503                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9504                                 flow_dev_get_vlan_info_from_items(items, &vlan);
9505                         vlan.eth_proto = rte_be_to_cpu_16
9506                              ((((const struct rte_flow_action_of_push_vlan *)
9507                                                    actions->conf)->ethertype));
9508                         found_action = mlx5_flow_find_action
9509                                         (actions + 1,
9510                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9511                         if (found_action)
9512                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9513                         found_action = mlx5_flow_find_action
9514                                         (actions + 1,
9515                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9516                         if (found_action)
9517                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9518                         if (flow_dv_create_action_push_vlan
9519                                             (dev, attr, &vlan, dev_flow, error))
9520                                 return -rte_errno;
9521                         dev_flow->dv.actions[actions_n++] =
9522                                         dev_flow->dv.push_vlan_res->action;
9523                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9524                         break;
9525                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9526                         /* of_vlan_push action handled this action */
9527                         MLX5_ASSERT(action_flags &
9528                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9529                         break;
9530                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9531                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9532                                 break;
9533                         flow_dev_get_vlan_info_from_items(items, &vlan);
9534                         mlx5_update_vlan_vid_pcp(actions, &vlan);
9535                         /* If no VLAN push - this is a modify header action */
9536                         if (flow_dv_convert_action_modify_vlan_vid
9537                                                 (mhdr_res, actions, error))
9538                                 return -rte_errno;
9539                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
9540                         break;
9541                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
9542                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
9543                         if (flow_dv_create_action_l2_encap(dev, actions,
9544                                                            dev_flow,
9545                                                            attr->transfer,
9546                                                            error))
9547                                 return -rte_errno;
9548                         dev_flow->dv.actions[actions_n++] =
9549                                         dev_flow->dv.encap_decap->action;
9550                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9551                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9552                                 sample_act->action_flags |=
9553                                                         MLX5_FLOW_ACTION_ENCAP;
9554                         break;
9555                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
9556                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
9557                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9558                                                            attr->transfer,
9559                                                            error))
9560                                 return -rte_errno;
9561                         dev_flow->dv.actions[actions_n++] =
9562                                         dev_flow->dv.encap_decap->action;
9563                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9564                         break;
9565                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9566                         /* Handle encap with preceding decap. */
9567                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
9568                                 if (flow_dv_create_action_raw_encap
9569                                         (dev, actions, dev_flow, attr, error))
9570                                         return -rte_errno;
9571                                 dev_flow->dv.actions[actions_n++] =
9572                                         dev_flow->dv.encap_decap->action;
9573                         } else {
9574                                 /* Handle encap without preceding decap. */
9575                                 if (flow_dv_create_action_l2_encap
9576                                     (dev, actions, dev_flow, attr->transfer,
9577                                      error))
9578                                         return -rte_errno;
9579                                 dev_flow->dv.actions[actions_n++] =
9580                                         dev_flow->dv.encap_decap->action;
9581                         }
9582                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9583                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9584                                 sample_act->action_flags |=
9585                                                         MLX5_FLOW_ACTION_ENCAP;
9586                         break;
9587                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
9588                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
9589                                 ;
9590                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
9591                                 if (flow_dv_create_action_l2_decap
9592                                     (dev, dev_flow, attr->transfer, error))
9593                                         return -rte_errno;
9594                                 dev_flow->dv.actions[actions_n++] =
9595                                         dev_flow->dv.encap_decap->action;
9596                         }
9597                         /* If decap is followed by encap, handle it at encap. */
9598                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9599                         break;
9600                 case RTE_FLOW_ACTION_TYPE_JUMP:
9601                         jump_group = ((const struct rte_flow_action_jump *)
9602                                                         action->conf)->group;
9603                         grp_info.std_tbl_fix = 0;
9604                         ret = mlx5_flow_group_to_table(dev, tunnel,
9605                                                        jump_group,
9606                                                        &table,
9607                                                        grp_info, error);
9608                         if (ret)
9609                                 return ret;
9610                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9611                                                        attr->transfer,
9612                                                        !!dev_flow->external,
9613                                                        tunnel, jump_group,
9614                                                        error);
9615                         if (!tbl)
9616                                 return rte_flow_error_set
9617                                                 (error, errno,
9618                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9619                                                  NULL,
9620                                                  "cannot create jump action.");
9621                         if (flow_dv_jump_tbl_resource_register
9622                             (dev, tbl, dev_flow, error)) {
9623                                 flow_dv_tbl_resource_release(dev, tbl);
9624                                 return rte_flow_error_set
9625                                                 (error, errno,
9626                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9627                                                  NULL,
9628                                                  "cannot create jump action.");
9629                         }
9630                         dev_flow->dv.actions[actions_n++] =
9631                                         dev_flow->dv.jump->action;
9632                         action_flags |= MLX5_FLOW_ACTION_JUMP;
9633                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
9634                         break;
9635                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
9636                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
9637                         if (flow_dv_convert_action_modify_mac
9638                                         (mhdr_res, actions, error))
9639                                 return -rte_errno;
9640                         action_flags |= actions->type ==
9641                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
9642                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
9643                                         MLX5_FLOW_ACTION_SET_MAC_DST;
9644                         break;
9645                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
9646                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
9647                         if (flow_dv_convert_action_modify_ipv4
9648                                         (mhdr_res, actions, error))
9649                                 return -rte_errno;
9650                         action_flags |= actions->type ==
9651                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
9652                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
9653                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
9654                         break;
9655                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
9656                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
9657                         if (flow_dv_convert_action_modify_ipv6
9658                                         (mhdr_res, actions, error))
9659                                 return -rte_errno;
9660                         action_flags |= actions->type ==
9661                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
9662                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
9663                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
9664                         break;
9665                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
9666                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
9667                         if (flow_dv_convert_action_modify_tp
9668                                         (mhdr_res, actions, items,
9669                                          &flow_attr, dev_flow, !!(action_flags &
9670                                          MLX5_FLOW_ACTION_DECAP), error))
9671                                 return -rte_errno;
9672                         action_flags |= actions->type ==
9673                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
9674                                         MLX5_FLOW_ACTION_SET_TP_SRC :
9675                                         MLX5_FLOW_ACTION_SET_TP_DST;
9676                         break;
9677                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
9678                         if (flow_dv_convert_action_modify_dec_ttl
9679                                         (mhdr_res, items, &flow_attr, dev_flow,
9680                                          !!(action_flags &
9681                                          MLX5_FLOW_ACTION_DECAP), error))
9682                                 return -rte_errno;
9683                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
9684                         break;
9685                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
9686                         if (flow_dv_convert_action_modify_ttl
9687                                         (mhdr_res, actions, items, &flow_attr,
9688                                          dev_flow, !!(action_flags &
9689                                          MLX5_FLOW_ACTION_DECAP), error))
9690                                 return -rte_errno;
9691                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
9692                         break;
9693                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
9694                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
9695                         if (flow_dv_convert_action_modify_tcp_seq
9696                                         (mhdr_res, actions, error))
9697                                 return -rte_errno;
9698                         action_flags |= actions->type ==
9699                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
9700                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
9701                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
9702                         break;
9703
9704                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
9705                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
9706                         if (flow_dv_convert_action_modify_tcp_ack
9707                                         (mhdr_res, actions, error))
9708                                 return -rte_errno;
9709                         action_flags |= actions->type ==
9710                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
9711                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
9712                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
9713                         break;
9714                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
9715                         if (flow_dv_convert_action_set_reg
9716                                         (mhdr_res, actions, error))
9717                                 return -rte_errno;
9718                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9719                         break;
9720                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
9721                         if (flow_dv_convert_action_copy_mreg
9722                                         (dev, mhdr_res, actions, error))
9723                                 return -rte_errno;
9724                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9725                         break;
9726                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
9727                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
9728                         dev_flow->handle->fate_action =
9729                                         MLX5_FLOW_FATE_DEFAULT_MISS;
9730                         break;
9731                 case RTE_FLOW_ACTION_TYPE_METER:
9732                         mtr = actions->conf;
9733                         if (!flow->meter) {
9734                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
9735                                                             attr, error);
9736                                 if (!fm)
9737                                         return rte_flow_error_set(error,
9738                                                 rte_errno,
9739                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9740                                                 NULL,
9741                                                 "meter not found "
9742                                                 "or invalid parameters");
9743                                 flow->meter = fm->idx;
9744                         }
9745                         /* Set the meter action. */
9746                         if (!fm) {
9747                                 fm = mlx5_ipool_get(priv->sh->ipool
9748                                                 [MLX5_IPOOL_MTR], flow->meter);
9749                                 if (!fm)
9750                                         return rte_flow_error_set(error,
9751                                                 rte_errno,
9752                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9753                                                 NULL,
9754                                                 "meter not found "
9755                                                 "or invalid parameters");
9756                         }
9757                         dev_flow->dv.actions[actions_n++] =
9758                                 fm->mfts->meter_action;
9759                         action_flags |= MLX5_FLOW_ACTION_METER;
9760                         break;
9761                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
9762                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
9763                                                               actions, error))
9764                                 return -rte_errno;
9765                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
9766                         break;
9767                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
9768                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
9769                                                               actions, error))
9770                                 return -rte_errno;
9771                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
9772                         break;
9773                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
9774                         sample_act_pos = actions_n;
9775                         ret = flow_dv_translate_action_sample(dev,
9776                                                               actions,
9777                                                               dev_flow, attr,
9778                                                               &num_of_dest,
9779                                                               sample_actions,
9780                                                               &sample_res,
9781                                                               error);
9782                         if (ret < 0)
9783                                 return ret;
9784                         actions_n++;
9785                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
9786                         /* put encap action into group if work with port id */
9787                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
9788                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
9789                                 sample_act->action_flags |=
9790                                                         MLX5_FLOW_ACTION_ENCAP;
9791                         break;
9792                 case RTE_FLOW_ACTION_TYPE_END:
9793                         actions_end = true;
9794                         if (mhdr_res->actions_num) {
9795                                 /* create modify action if needed. */
9796                                 if (flow_dv_modify_hdr_resource_register
9797                                         (dev, mhdr_res, dev_flow, error))
9798                                         return -rte_errno;
9799                                 dev_flow->dv.actions[modify_action_position] =
9800                                         handle->dvh.modify_hdr->action;
9801                         }
9802                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
9803                                 flow->counter =
9804                                         flow_dv_translate_create_counter(dev,
9805                                                 dev_flow, count, age);
9806
9807                                 if (!flow->counter)
9808                                         return rte_flow_error_set
9809                                                 (error, rte_errno,
9810                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9811                                                 NULL,
9812                                                 "cannot create counter"
9813                                                 " object.");
9814                                 dev_flow->dv.actions[actions_n] =
9815                                           (flow_dv_counter_get_by_idx(dev,
9816                                           flow->counter, NULL))->action;
9817                                 actions_n++;
9818                         }
9819                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
9820                                 ret = flow_dv_create_action_sample(dev,
9821                                                           dev_flow, attr,
9822                                                           num_of_dest,
9823                                                           &sample_res,
9824                                                           &mdest_res,
9825                                                           sample_actions,
9826                                                           action_flags,
9827                                                           error);
9828                                 if (ret < 0)
9829                                         return rte_flow_error_set
9830                                                 (error, rte_errno,
9831                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9832                                                 NULL,
9833                                                 "cannot create sample action");
9834                                 if (num_of_dest > 1) {
9835                                         dev_flow->dv.actions[sample_act_pos] =
9836                                         dev_flow->dv.dest_array_res->action;
9837                                 } else {
9838                                         dev_flow->dv.actions[sample_act_pos] =
9839                                         dev_flow->dv.sample_res->verbs_action;
9840                                 }
9841                         }
9842                         break;
9843                 default:
9844                         break;
9845                 }
9846                 if (mhdr_res->actions_num &&
9847                     modify_action_position == UINT32_MAX)
9848                         modify_action_position = actions_n++;
9849         }
9850         /*
9851          * For multiple destination (sample action with ratio=1), the encap
9852          * action and port id action will be combined into group action.
9853          * So need remove the original these actions in the flow and only
9854          * use the sample action instead of.
9855          */
9856         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
9857                 int i;
9858                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9859
9860                 for (i = 0; i < actions_n; i++) {
9861                         if ((sample_act->dr_encap_action &&
9862                                 sample_act->dr_encap_action ==
9863                                 dev_flow->dv.actions[i]) ||
9864                                 (sample_act->dr_port_id_action &&
9865                                 sample_act->dr_port_id_action ==
9866                                 dev_flow->dv.actions[i]))
9867                                 continue;
9868                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
9869                 }
9870                 memcpy((void *)dev_flow->dv.actions,
9871                                 (void *)temp_actions,
9872                                 tmp_actions_n * sizeof(void *));
9873                 actions_n = tmp_actions_n;
9874         }
9875         dev_flow->dv.actions_n = actions_n;
9876         dev_flow->act_flags = action_flags;
9877         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
9878                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
9879                 int item_type = items->type;
9880
9881                 if (!mlx5_flow_os_item_supported(item_type))
9882                         return rte_flow_error_set(error, ENOTSUP,
9883                                                   RTE_FLOW_ERROR_TYPE_ITEM,
9884                                                   NULL, "item not supported");
9885                 switch (item_type) {
9886                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
9887                         flow_dv_translate_item_port_id(dev, match_mask,
9888                                                        match_value, items);
9889                         last_item = MLX5_FLOW_ITEM_PORT_ID;
9890                         break;
9891                 case RTE_FLOW_ITEM_TYPE_ETH:
9892                         flow_dv_translate_item_eth(match_mask, match_value,
9893                                                    items, tunnel,
9894                                                    dev_flow->dv.group);
9895                         matcher.priority = action_flags &
9896                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
9897                                         !dev_flow->external ?
9898                                         MLX5_PRIORITY_MAP_L3 :
9899                                         MLX5_PRIORITY_MAP_L2;
9900                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
9901                                              MLX5_FLOW_LAYER_OUTER_L2;
9902                         break;
9903                 case RTE_FLOW_ITEM_TYPE_VLAN:
9904                         flow_dv_translate_item_vlan(dev_flow,
9905                                                     match_mask, match_value,
9906                                                     items, tunnel,
9907                                                     dev_flow->dv.group);
9908                         matcher.priority = MLX5_PRIORITY_MAP_L2;
9909                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
9910                                               MLX5_FLOW_LAYER_INNER_VLAN) :
9911                                              (MLX5_FLOW_LAYER_OUTER_L2 |
9912                                               MLX5_FLOW_LAYER_OUTER_VLAN);
9913                         break;
9914                 case RTE_FLOW_ITEM_TYPE_IPV4:
9915                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9916                                                   &item_flags, &tunnel);
9917                         flow_dv_translate_item_ipv4(match_mask, match_value,
9918                                                     items, item_flags, tunnel,
9919                                                     dev_flow->dv.group);
9920                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9921                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
9922                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
9923                         if (items->mask != NULL &&
9924                             ((const struct rte_flow_item_ipv4 *)
9925                              items->mask)->hdr.next_proto_id) {
9926                                 next_protocol =
9927                                         ((const struct rte_flow_item_ipv4 *)
9928                                          (items->spec))->hdr.next_proto_id;
9929                                 next_protocol &=
9930                                         ((const struct rte_flow_item_ipv4 *)
9931                                          (items->mask))->hdr.next_proto_id;
9932                         } else {
9933                                 /* Reset for inner layer. */
9934                                 next_protocol = 0xff;
9935                         }
9936                         break;
9937                 case RTE_FLOW_ITEM_TYPE_IPV6:
9938                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9939                                                   &item_flags, &tunnel);
9940                         flow_dv_translate_item_ipv6(match_mask, match_value,
9941                                                     items, item_flags, tunnel,
9942                                                     dev_flow->dv.group);
9943                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9944                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
9945                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
9946                         if (items->mask != NULL &&
9947                             ((const struct rte_flow_item_ipv6 *)
9948                              items->mask)->hdr.proto) {
9949                                 next_protocol =
9950                                         ((const struct rte_flow_item_ipv6 *)
9951                                          items->spec)->hdr.proto;
9952                                 next_protocol &=
9953                                         ((const struct rte_flow_item_ipv6 *)
9954                                          items->mask)->hdr.proto;
9955                         } else {
9956                                 /* Reset for inner layer. */
9957                                 next_protocol = 0xff;
9958                         }
9959                         break;
9960                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
9961                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
9962                                                              match_value,
9963                                                              items, tunnel);
9964                         last_item = tunnel ?
9965                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
9966                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
9967                         if (items->mask != NULL &&
9968                             ((const struct rte_flow_item_ipv6_frag_ext *)
9969                              items->mask)->hdr.next_header) {
9970                                 next_protocol =
9971                                 ((const struct rte_flow_item_ipv6_frag_ext *)
9972                                  items->spec)->hdr.next_header;
9973                                 next_protocol &=
9974                                 ((const struct rte_flow_item_ipv6_frag_ext *)
9975                                  items->mask)->hdr.next_header;
9976                         } else {
9977                                 /* Reset for inner layer. */
9978                                 next_protocol = 0xff;
9979                         }
9980                         break;
9981                 case RTE_FLOW_ITEM_TYPE_TCP:
9982                         flow_dv_translate_item_tcp(match_mask, match_value,
9983                                                    items, tunnel);
9984                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9985                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
9986                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
9987                         break;
9988                 case RTE_FLOW_ITEM_TYPE_UDP:
9989                         flow_dv_translate_item_udp(match_mask, match_value,
9990                                                    items, tunnel);
9991                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9992                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
9993                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
9994                         break;
9995                 case RTE_FLOW_ITEM_TYPE_GRE:
9996                         flow_dv_translate_item_gre(match_mask, match_value,
9997                                                    items, tunnel);
9998                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9999                         last_item = MLX5_FLOW_LAYER_GRE;
10000                         break;
10001                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
10002                         flow_dv_translate_item_gre_key(match_mask,
10003                                                        match_value, items);
10004                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
10005                         break;
10006                 case RTE_FLOW_ITEM_TYPE_NVGRE:
10007                         flow_dv_translate_item_nvgre(match_mask, match_value,
10008                                                      items, tunnel);
10009                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10010                         last_item = MLX5_FLOW_LAYER_GRE;
10011                         break;
10012                 case RTE_FLOW_ITEM_TYPE_VXLAN:
10013                         flow_dv_translate_item_vxlan(match_mask, match_value,
10014                                                      items, tunnel);
10015                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10016                         last_item = MLX5_FLOW_LAYER_VXLAN;
10017                         break;
10018                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10019                         flow_dv_translate_item_vxlan_gpe(match_mask,
10020                                                          match_value, items,
10021                                                          tunnel);
10022                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10023                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10024                         break;
10025                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10026                         flow_dv_translate_item_geneve(match_mask, match_value,
10027                                                       items, tunnel);
10028                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10029                         last_item = MLX5_FLOW_LAYER_GENEVE;
10030                         break;
10031                 case RTE_FLOW_ITEM_TYPE_MPLS:
10032                         flow_dv_translate_item_mpls(match_mask, match_value,
10033                                                     items, last_item, tunnel);
10034                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10035                         last_item = MLX5_FLOW_LAYER_MPLS;
10036                         break;
10037                 case RTE_FLOW_ITEM_TYPE_MARK:
10038                         flow_dv_translate_item_mark(dev, match_mask,
10039                                                     match_value, items);
10040                         last_item = MLX5_FLOW_ITEM_MARK;
10041                         break;
10042                 case RTE_FLOW_ITEM_TYPE_META:
10043                         flow_dv_translate_item_meta(dev, match_mask,
10044                                                     match_value, attr, items);
10045                         last_item = MLX5_FLOW_ITEM_METADATA;
10046                         break;
10047                 case RTE_FLOW_ITEM_TYPE_ICMP:
10048                         flow_dv_translate_item_icmp(match_mask, match_value,
10049                                                     items, tunnel);
10050                         last_item = MLX5_FLOW_LAYER_ICMP;
10051                         break;
10052                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10053                         flow_dv_translate_item_icmp6(match_mask, match_value,
10054                                                       items, tunnel);
10055                         last_item = MLX5_FLOW_LAYER_ICMP6;
10056                         break;
10057                 case RTE_FLOW_ITEM_TYPE_TAG:
10058                         flow_dv_translate_item_tag(dev, match_mask,
10059                                                    match_value, items);
10060                         last_item = MLX5_FLOW_ITEM_TAG;
10061                         break;
10062                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10063                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10064                                                         match_value, items);
10065                         last_item = MLX5_FLOW_ITEM_TAG;
10066                         break;
10067                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10068                         flow_dv_translate_item_tx_queue(dev, match_mask,
10069                                                         match_value,
10070                                                         items);
10071                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10072                         break;
10073                 case RTE_FLOW_ITEM_TYPE_GTP:
10074                         flow_dv_translate_item_gtp(match_mask, match_value,
10075                                                    items, tunnel);
10076                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10077                         last_item = MLX5_FLOW_LAYER_GTP;
10078                         break;
10079                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10080                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10081                                 /* Create it only the first time to be used. */
10082                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10083                                 if (ret)
10084                                         return rte_flow_error_set
10085                                                 (error, -ret,
10086                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10087                                                 NULL,
10088                                                 "cannot create eCPRI parser");
10089                         }
10090                         /* Adjust the length matcher and device flow value. */
10091                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10092                         dev_flow->dv.value.size =
10093                                         MLX5_ST_SZ_BYTES(fte_match_param);
10094                         flow_dv_translate_item_ecpri(dev, match_mask,
10095                                                      match_value, items);
10096                         /* No other protocol should follow eCPRI layer. */
10097                         last_item = MLX5_FLOW_LAYER_ECPRI;
10098                         break;
10099                 default:
10100                         break;
10101                 }
10102                 item_flags |= last_item;
10103         }
10104         /*
10105          * When E-Switch mode is enabled, we have two cases where we need to
10106          * set the source port manually.
10107          * The first one, is in case of Nic steering rule, and the second is
10108          * E-Switch rule where no port_id item was found. In both cases
10109          * the source port is set according the current port in use.
10110          */
10111         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10112             (priv->representor || priv->master)) {
10113                 if (flow_dv_translate_item_port_id(dev, match_mask,
10114                                                    match_value, NULL))
10115                         return -rte_errno;
10116         }
10117 #ifdef RTE_LIBRTE_MLX5_DEBUG
10118         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10119                                               dev_flow->dv.value.buf));
10120 #endif
10121         /*
10122          * Layers may be already initialized from prefix flow if this dev_flow
10123          * is the suffix flow.
10124          */
10125         handle->layers |= item_flags;
10126         if (action_flags & MLX5_FLOW_ACTION_RSS)
10127                 flow_dv_hashfields_set(dev_flow, rss_desc);
10128         /* Register matcher. */
10129         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10130                                     matcher.mask.size);
10131         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
10132                                                      matcher.priority);
10133         /* reserved field no needs to be set to 0 here. */
10134         tbl_key.domain = attr->transfer;
10135         tbl_key.direction = attr->egress;
10136         tbl_key.table_id = dev_flow->dv.group;
10137         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
10138                 return -rte_errno;
10139         return 0;
10140 }
10141
10142 /**
10143  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10144  * and tunnel.
10145  *
10146  * @param[in, out] action
10147  *   Shred RSS action holding hash RX queue objects.
10148  * @param[in] hash_fields
10149  *   Defines combination of packet fields to participate in RX hash.
10150  * @param[in] tunnel
10151  *   Tunnel type
10152  * @param[in] hrxq_idx
10153  *   Hash RX queue index to set.
10154  *
10155  * @return
10156  *   0 on success, otherwise negative errno value.
10157  */
10158 static int
10159 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10160                               const uint64_t hash_fields,
10161                               const int tunnel,
10162                               uint32_t hrxq_idx)
10163 {
10164         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10165
10166         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10167         case MLX5_RSS_HASH_IPV4:
10168                 hrxqs[0] = hrxq_idx;
10169                 return 0;
10170         case MLX5_RSS_HASH_IPV4_TCP:
10171                 hrxqs[1] = hrxq_idx;
10172                 return 0;
10173         case MLX5_RSS_HASH_IPV4_UDP:
10174                 hrxqs[2] = hrxq_idx;
10175                 return 0;
10176         case MLX5_RSS_HASH_IPV6:
10177                 hrxqs[3] = hrxq_idx;
10178                 return 0;
10179         case MLX5_RSS_HASH_IPV6_TCP:
10180                 hrxqs[4] = hrxq_idx;
10181                 return 0;
10182         case MLX5_RSS_HASH_IPV6_UDP:
10183                 hrxqs[5] = hrxq_idx;
10184                 return 0;
10185         case MLX5_RSS_HASH_NONE:
10186                 hrxqs[6] = hrxq_idx;
10187                 return 0;
10188         default:
10189                 return -1;
10190         }
10191 }
10192
10193 /**
10194  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10195  * and tunnel.
10196  *
10197  * @param[in] action
10198  *   Shred RSS action holding hash RX queue objects.
10199  * @param[in] hash_fields
10200  *   Defines combination of packet fields to participate in RX hash.
10201  * @param[in] tunnel
10202  *   Tunnel type
10203  *
10204  * @return
10205  *   Valid hash RX queue index, otherwise 0.
10206  */
10207 static uint32_t
10208 __flow_dv_action_rss_hrxq_lookup(const struct mlx5_shared_action_rss *action,
10209                                  const uint64_t hash_fields,
10210                                  const int tunnel)
10211 {
10212         const uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10213
10214         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10215         case MLX5_RSS_HASH_IPV4:
10216                 return hrxqs[0];
10217         case MLX5_RSS_HASH_IPV4_TCP:
10218                 return hrxqs[1];
10219         case MLX5_RSS_HASH_IPV4_UDP:
10220                 return hrxqs[2];
10221         case MLX5_RSS_HASH_IPV6:
10222                 return hrxqs[3];
10223         case MLX5_RSS_HASH_IPV6_TCP:
10224                 return hrxqs[4];
10225         case MLX5_RSS_HASH_IPV6_UDP:
10226                 return hrxqs[5];
10227         case MLX5_RSS_HASH_NONE:
10228                 return hrxqs[6];
10229         default:
10230                 return 0;
10231         }
10232 }
10233
10234 /**
10235  * Retrieves hash RX queue suitable for the *flow*.
10236  * If shared action configured for *flow* suitable hash RX queue will be
10237  * retrieved from attached shared action.
10238  *
10239  * @param[in] flow
10240  *   Shred RSS action holding hash RX queue objects.
10241  * @param[in] dev_flow
10242  *   Pointer to the sub flow.
10243  * @param[out] hrxq
10244  *   Pointer to retrieved hash RX queue object.
10245  *
10246  * @return
10247  *   Valid hash RX queue index, otherwise 0 and rte_errno is set.
10248  */
10249 static uint32_t
10250 __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct rte_flow *flow,
10251                            struct mlx5_flow *dev_flow,
10252                            struct mlx5_hrxq **hrxq)
10253 {
10254         struct mlx5_priv *priv = dev->data->dev_private;
10255         uint32_t hrxq_idx;
10256
10257         if (flow->shared_rss) {
10258                 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
10259                                 (flow->shared_rss, dev_flow->hash_fields,
10260                                  !!(dev_flow->handle->layers &
10261                                     MLX5_FLOW_LAYER_TUNNEL));
10262                 if (hrxq_idx) {
10263                         *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10264                                                hrxq_idx);
10265                         rte_atomic32_inc(&(*hrxq)->refcnt);
10266                 }
10267         } else {
10268                 struct mlx5_flow_rss_desc *rss_desc =
10269                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
10270                                 [!!priv->flow_nested_idx];
10271
10272                 MLX5_ASSERT(rss_desc->queue_num);
10273                 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
10274                                          MLX5_RSS_HASH_KEY_LEN,
10275                                          dev_flow->hash_fields,
10276                                          rss_desc->queue, rss_desc->queue_num);
10277                 if (!hrxq_idx) {
10278                         hrxq_idx = mlx5_hrxq_new(dev,
10279                                                  rss_desc->key,
10280                                                  MLX5_RSS_HASH_KEY_LEN,
10281                                                  dev_flow->hash_fields,
10282                                                  rss_desc->queue,
10283                                                  rss_desc->queue_num,
10284                                                  !!(dev_flow->handle->layers &
10285                                                  MLX5_FLOW_LAYER_TUNNEL),
10286                                                  false);
10287                 }
10288                 *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10289                                        hrxq_idx);
10290         }
10291         return hrxq_idx;
10292 }
10293
10294 /**
10295  * Apply the flow to the NIC, lock free,
10296  * (mutex should be acquired by caller).
10297  *
10298  * @param[in] dev
10299  *   Pointer to the Ethernet device structure.
10300  * @param[in, out] flow
10301  *   Pointer to flow structure.
10302  * @param[out] error
10303  *   Pointer to error structure.
10304  *
10305  * @return
10306  *   0 on success, a negative errno value otherwise and rte_errno is set.
10307  */
10308 static int
10309 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10310                 struct rte_flow_error *error)
10311 {
10312         struct mlx5_flow_dv_workspace *dv;
10313         struct mlx5_flow_handle *dh;
10314         struct mlx5_flow_handle_dv *dv_h;
10315         struct mlx5_flow *dev_flow;
10316         struct mlx5_priv *priv = dev->data->dev_private;
10317         uint32_t handle_idx;
10318         int n;
10319         int err;
10320         int idx;
10321
10322         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
10323                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
10324                 dv = &dev_flow->dv;
10325                 dh = dev_flow->handle;
10326                 dv_h = &dh->dvh;
10327                 n = dv->actions_n;
10328                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10329                         if (dv->transfer) {
10330                                 dv->actions[n++] = priv->sh->esw_drop_action;
10331                         } else {
10332                                 struct mlx5_hrxq *drop_hrxq;
10333                                 drop_hrxq = mlx5_drop_action_create(dev);
10334                                 if (!drop_hrxq) {
10335                                         rte_flow_error_set
10336                                                 (error, errno,
10337                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10338                                                  NULL,
10339                                                  "cannot get drop hash queue");
10340                                         goto error;
10341                                 }
10342                                 /*
10343                                  * Drop queues will be released by the specify
10344                                  * mlx5_drop_action_destroy() function. Assign
10345                                  * the special index to hrxq to mark the queue
10346                                  * has been allocated.
10347                                  */
10348                                 dh->rix_hrxq = UINT32_MAX;
10349                                 dv->actions[n++] = drop_hrxq->action;
10350                         }
10351                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10352                            !dv_h->rix_sample && !dv_h->rix_dest_array) {
10353                         struct mlx5_hrxq *hrxq = NULL;
10354                         uint32_t hrxq_idx = __flow_dv_rss_get_hrxq
10355                                                 (dev, flow, dev_flow, &hrxq);
10356
10357                         if (!hrxq) {
10358                                 rte_flow_error_set
10359                                         (error, rte_errno,
10360                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10361                                          "cannot get hash queue");
10362                                 goto error;
10363                         }
10364                         dh->rix_hrxq = hrxq_idx;
10365                         dv->actions[n++] = hrxq->action;
10366                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10367                         if (flow_dv_default_miss_resource_register
10368                                         (dev, error)) {
10369                                 rte_flow_error_set
10370                                         (error, rte_errno,
10371                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10372                                          "cannot create default miss resource");
10373                                 goto error_default_miss;
10374                         }
10375                         dh->rix_default_fate =  MLX5_FLOW_FATE_DEFAULT_MISS;
10376                         dv->actions[n++] = priv->sh->default_miss.action;
10377                 }
10378                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10379                                                (void *)&dv->value, n,
10380                                                dv->actions, &dh->drv_flow);
10381                 if (err) {
10382                         rte_flow_error_set(error, errno,
10383                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10384                                            NULL,
10385                                            "hardware refuses to create flow");
10386                         goto error;
10387                 }
10388                 if (priv->vmwa_context &&
10389                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
10390                         /*
10391                          * The rule contains the VLAN pattern.
10392                          * For VF we are going to create VLAN
10393                          * interface to make hypervisor set correct
10394                          * e-Switch vport context.
10395                          */
10396                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10397                 }
10398         }
10399         return 0;
10400 error:
10401         if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
10402                 flow_dv_default_miss_resource_release(dev);
10403 error_default_miss:
10404         err = rte_errno; /* Save rte_errno before cleanup. */
10405         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10406                        handle_idx, dh, next) {
10407                 /* hrxq is union, don't clear it if the flag is not set. */
10408                 if (dh->rix_hrxq) {
10409                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10410                                 mlx5_drop_action_destroy(dev);
10411                                 dh->rix_hrxq = 0;
10412                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
10413                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
10414                                 dh->rix_hrxq = 0;
10415                         }
10416                 }
10417                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10418                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10419         }
10420         rte_errno = err; /* Restore rte_errno. */
10421         return -rte_errno;
10422 }
10423
10424 /**
10425  * Release the flow matcher.
10426  *
10427  * @param dev
10428  *   Pointer to Ethernet device.
10429  * @param handle
10430  *   Pointer to mlx5_flow_handle.
10431  *
10432  * @return
10433  *   1 while a reference on it exists, 0 when freed.
10434  */
10435 static int
10436 flow_dv_matcher_release(struct rte_eth_dev *dev,
10437                         struct mlx5_flow_handle *handle)
10438 {
10439         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10440
10441         MLX5_ASSERT(matcher->matcher_object);
10442         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
10443                 dev->data->port_id, (void *)matcher,
10444                 rte_atomic32_read(&matcher->refcnt));
10445         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
10446                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10447                            (matcher->matcher_object));
10448                 LIST_REMOVE(matcher, next);
10449                 /* table ref-- in release interface. */
10450                 flow_dv_tbl_resource_release(dev, matcher->tbl);
10451                 mlx5_free(matcher);
10452                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
10453                         dev->data->port_id, (void *)matcher);
10454                 return 0;
10455         }
10456         return 1;
10457 }
10458
10459 /**
10460  * Release an encap/decap resource.
10461  *
10462  * @param dev
10463  *   Pointer to Ethernet device.
10464  * @param encap_decap_idx
10465  *   Index of encap decap resource.
10466  *
10467  * @return
10468  *   1 while a reference on it exists, 0 when freed.
10469  */
10470 static int
10471 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10472                                      uint32_t encap_decap_idx)
10473 {
10474         struct mlx5_priv *priv = dev->data->dev_private;
10475         uint32_t idx = encap_decap_idx;
10476         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10477
10478         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10479                          idx);
10480         if (!cache_resource)
10481                 return 0;
10482         MLX5_ASSERT(cache_resource->action);
10483         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
10484                 (void *)cache_resource,
10485                 rte_atomic32_read(&cache_resource->refcnt));
10486         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10487                 claim_zero(mlx5_flow_os_destroy_flow_action
10488                                                 (cache_resource->action));
10489                 mlx5_hlist_remove(priv->sh->encaps_decaps,
10490                                   &cache_resource->entry);
10491                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
10492                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
10493                         (void *)cache_resource);
10494                 return 0;
10495         }
10496         return 1;
10497 }
10498
10499 /**
10500  * Release an jump to table action resource.
10501  *
10502  * @param dev
10503  *   Pointer to Ethernet device.
10504  * @param handle
10505  *   Pointer to mlx5_flow_handle.
10506  *
10507  * @return
10508  *   1 while a reference on it exists, 0 when freed.
10509  */
10510 static int
10511 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10512                                   struct mlx5_flow_handle *handle)
10513 {
10514         struct mlx5_priv *priv = dev->data->dev_private;
10515         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
10516         struct mlx5_flow_tbl_data_entry *tbl_data;
10517
10518         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10519                              handle->rix_jump);
10520         if (!tbl_data)
10521                 return 0;
10522         cache_resource = &tbl_data->jump;
10523         MLX5_ASSERT(cache_resource->action);
10524         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
10525                 (void *)cache_resource,
10526                 rte_atomic32_read(&cache_resource->refcnt));
10527         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10528                 claim_zero(mlx5_flow_os_destroy_flow_action
10529                                                 (cache_resource->action));
10530                 /* jump action memory free is inside the table release. */
10531                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
10532                 DRV_LOG(DEBUG, "jump table resource %p: removed",
10533                         (void *)cache_resource);
10534                 return 0;
10535         }
10536         return 1;
10537 }
10538
10539 /**
10540  * Release a default miss resource.
10541  *
10542  * @param dev
10543  *   Pointer to Ethernet device.
10544  * @return
10545  *   1 while a reference on it exists, 0 when freed.
10546  */
10547 static int
10548 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
10549 {
10550         struct mlx5_priv *priv = dev->data->dev_private;
10551         struct mlx5_dev_ctx_shared *sh = priv->sh;
10552         struct mlx5_flow_default_miss_resource *cache_resource =
10553                         &sh->default_miss;
10554
10555         MLX5_ASSERT(cache_resource->action);
10556         DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
10557                         (void *)cache_resource->action,
10558                         rte_atomic32_read(&cache_resource->refcnt));
10559         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10560                 claim_zero(mlx5_glue->destroy_flow_action
10561                                 (cache_resource->action));
10562                 DRV_LOG(DEBUG, "default miss resource %p: removed",
10563                                 (void *)cache_resource->action);
10564                 return 0;
10565         }
10566         return 1;
10567 }
10568
10569 /**
10570  * Release a modify-header resource.
10571  *
10572  * @param dev
10573  *   Pointer to Ethernet device.
10574  * @param handle
10575  *   Pointer to mlx5_flow_handle.
10576  *
10577  * @return
10578  *   1 while a reference on it exists, 0 when freed.
10579  */
10580 static int
10581 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10582                                     struct mlx5_flow_handle *handle)
10583 {
10584         struct mlx5_priv *priv = dev->data->dev_private;
10585         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
10586                                                         handle->dvh.modify_hdr;
10587
10588         MLX5_ASSERT(cache_resource->action);
10589         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
10590                 (void *)cache_resource,
10591                 rte_atomic32_read(&cache_resource->refcnt));
10592         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10593                 claim_zero(mlx5_flow_os_destroy_flow_action
10594                                                 (cache_resource->action));
10595                 mlx5_hlist_remove(priv->sh->modify_cmds,
10596                                   &cache_resource->entry);
10597                 mlx5_free(cache_resource);
10598                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
10599                         (void *)cache_resource);
10600                 return 0;
10601         }
10602         return 1;
10603 }
10604
10605 /**
10606  * Release port ID action resource.
10607  *
10608  * @param dev
10609  *   Pointer to Ethernet device.
10610  * @param handle
10611  *   Pointer to mlx5_flow_handle.
10612  *
10613  * @return
10614  *   1 while a reference on it exists, 0 when freed.
10615  */
10616 static int
10617 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
10618                                         uint32_t port_id)
10619 {
10620         struct mlx5_priv *priv = dev->data->dev_private;
10621         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
10622         uint32_t idx = port_id;
10623
10624         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10625                                         idx);
10626         if (!cache_resource)
10627                 return 0;
10628         MLX5_ASSERT(cache_resource->action);
10629         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
10630                 (void *)cache_resource,
10631                 rte_atomic32_read(&cache_resource->refcnt));
10632         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10633                 claim_zero(mlx5_flow_os_destroy_flow_action
10634                                                 (cache_resource->action));
10635                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10636                              &priv->sh->port_id_action_list, idx,
10637                              cache_resource, next);
10638                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
10639                 DRV_LOG(DEBUG, "port id action resource %p: removed",
10640                         (void *)cache_resource);
10641                 return 0;
10642         }
10643         return 1;
10644 }
10645
10646 /**
10647  * Release push vlan action resource.
10648  *
10649  * @param dev
10650  *   Pointer to Ethernet device.
10651  * @param handle
10652  *   Pointer to mlx5_flow_handle.
10653  *
10654  * @return
10655  *   1 while a reference on it exists, 0 when freed.
10656  */
10657 static int
10658 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
10659                                           struct mlx5_flow_handle *handle)
10660 {
10661         struct mlx5_priv *priv = dev->data->dev_private;
10662         uint32_t idx = handle->dvh.rix_push_vlan;
10663         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
10664
10665         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10666                                         idx);
10667         if (!cache_resource)
10668                 return 0;
10669         MLX5_ASSERT(cache_resource->action);
10670         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
10671                 (void *)cache_resource,
10672                 rte_atomic32_read(&cache_resource->refcnt));
10673         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
10674                 claim_zero(mlx5_flow_os_destroy_flow_action
10675                                                 (cache_resource->action));
10676                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10677                              &priv->sh->push_vlan_action_list, idx,
10678                              cache_resource, next);
10679                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
10680                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
10681                         (void *)cache_resource);
10682                 return 0;
10683         }
10684         return 1;
10685 }
10686
10687 /**
10688  * Release the fate resource.
10689  *
10690  * @param dev
10691  *   Pointer to Ethernet device.
10692  * @param handle
10693  *   Pointer to mlx5_flow_handle.
10694  */
10695 static void
10696 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
10697                                struct mlx5_flow_handle *handle)
10698 {
10699         if (!handle->rix_fate)
10700                 return;
10701         switch (handle->fate_action) {
10702         case MLX5_FLOW_FATE_DROP:
10703                 mlx5_drop_action_destroy(dev);
10704                 break;
10705         case MLX5_FLOW_FATE_QUEUE:
10706                 mlx5_hrxq_release(dev, handle->rix_hrxq);
10707                 break;
10708         case MLX5_FLOW_FATE_JUMP:
10709                 flow_dv_jump_tbl_resource_release(dev, handle);
10710                 break;
10711         case MLX5_FLOW_FATE_PORT_ID:
10712                 flow_dv_port_id_action_resource_release(dev,
10713                                 handle->rix_port_id_action);
10714                 break;
10715         case MLX5_FLOW_FATE_DEFAULT_MISS:
10716                 flow_dv_default_miss_resource_release(dev);
10717                 break;
10718         default:
10719                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
10720                 break;
10721         }
10722         handle->rix_fate = 0;
10723 }
10724
10725 /**
10726  * Release an sample resource.
10727  *
10728  * @param dev
10729  *   Pointer to Ethernet device.
10730  * @param handle
10731  *   Pointer to mlx5_flow_handle.
10732  *
10733  * @return
10734  *   1 while a reference on it exists, 0 when freed.
10735  */
10736 static int
10737 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
10738                                      struct mlx5_flow_handle *handle)
10739 {
10740         struct mlx5_priv *priv = dev->data->dev_private;
10741         uint32_t idx = handle->dvh.rix_sample;
10742         struct mlx5_flow_dv_sample_resource *cache_resource;
10743
10744         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10745                          idx);
10746         if (!cache_resource)
10747                 return 0;
10748         MLX5_ASSERT(cache_resource->verbs_action);
10749         DRV_LOG(DEBUG, "sample resource %p: refcnt %d--",
10750                 (void *)cache_resource,
10751                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10752         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10753                                __ATOMIC_RELAXED) == 0) {
10754                 if (cache_resource->verbs_action)
10755                         claim_zero(mlx5_glue->destroy_flow_action
10756                                         (cache_resource->verbs_action));
10757                 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10758                         if (cache_resource->default_miss)
10759                                 claim_zero(mlx5_glue->destroy_flow_action
10760                                   (cache_resource->default_miss));
10761                 }
10762                 if (cache_resource->normal_path_tbl)
10763                         flow_dv_tbl_resource_release(dev,
10764                                 cache_resource->normal_path_tbl);
10765         }
10766         if (cache_resource->sample_idx.rix_hrxq &&
10767                 !mlx5_hrxq_release(dev,
10768                         cache_resource->sample_idx.rix_hrxq))
10769                 cache_resource->sample_idx.rix_hrxq = 0;
10770         if (cache_resource->sample_idx.rix_tag &&
10771                 !flow_dv_tag_release(dev,
10772                         cache_resource->sample_idx.rix_tag))
10773                 cache_resource->sample_idx.rix_tag = 0;
10774         if (cache_resource->sample_idx.cnt) {
10775                 flow_dv_counter_release(dev,
10776                         cache_resource->sample_idx.cnt);
10777                 cache_resource->sample_idx.cnt = 0;
10778         }
10779         if (!__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED)) {
10780                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10781                              &priv->sh->sample_action_list, idx,
10782                              cache_resource, next);
10783                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10784                 DRV_LOG(DEBUG, "sample resource %p: removed",
10785                         (void *)cache_resource);
10786                 return 0;
10787         }
10788         return 1;
10789 }
10790
10791 /**
10792  * Release an destination array resource.
10793  *
10794  * @param dev
10795  *   Pointer to Ethernet device.
10796  * @param handle
10797  *   Pointer to mlx5_flow_handle.
10798  *
10799  * @return
10800  *   1 while a reference on it exists, 0 when freed.
10801  */
10802 static int
10803 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
10804                                      struct mlx5_flow_handle *handle)
10805 {
10806         struct mlx5_priv *priv = dev->data->dev_private;
10807         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10808         struct mlx5_flow_sub_actions_idx *mdest_act_res;
10809         uint32_t idx = handle->dvh.rix_dest_array;
10810         uint32_t i = 0;
10811
10812         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10813                          idx);
10814         if (!cache_resource)
10815                 return 0;
10816         MLX5_ASSERT(cache_resource->action);
10817         DRV_LOG(DEBUG, "destination array resource %p: refcnt %d--",
10818                 (void *)cache_resource,
10819                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10820         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10821                                __ATOMIC_RELAXED) == 0) {
10822                 if (cache_resource->action)
10823                         claim_zero(mlx5_glue->destroy_flow_action
10824                                                 (cache_resource->action));
10825                 for (; i < cache_resource->num_of_dest; i++) {
10826                         mdest_act_res = &cache_resource->sample_idx[i];
10827                         if (mdest_act_res->rix_hrxq) {
10828                                 mlx5_hrxq_release(dev,
10829                                         mdest_act_res->rix_hrxq);
10830                                 mdest_act_res->rix_hrxq = 0;
10831                         }
10832                         if (mdest_act_res->rix_encap_decap) {
10833                                 flow_dv_encap_decap_resource_release(dev,
10834                                         mdest_act_res->rix_encap_decap);
10835                                 mdest_act_res->rix_encap_decap = 0;
10836                         }
10837                         if (mdest_act_res->rix_port_id_action) {
10838                                 flow_dv_port_id_action_resource_release(dev,
10839                                         mdest_act_res->rix_port_id_action);
10840                                 mdest_act_res->rix_port_id_action = 0;
10841                         }
10842                         if (mdest_act_res->rix_tag) {
10843                                 flow_dv_tag_release(dev,
10844                                         mdest_act_res->rix_tag);
10845                                 mdest_act_res->rix_tag = 0;
10846                         }
10847                 }
10848                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10849                              &priv->sh->dest_array_list, idx,
10850                              cache_resource, next);
10851                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], idx);
10852                 DRV_LOG(DEBUG, "destination array resource %p: removed",
10853                         (void *)cache_resource);
10854                 return 0;
10855         }
10856         return 1;
10857 }
10858
10859 /**
10860  * Remove the flow from the NIC but keeps it in memory.
10861  * Lock free, (mutex should be acquired by caller).
10862  *
10863  * @param[in] dev
10864  *   Pointer to Ethernet device.
10865  * @param[in, out] flow
10866  *   Pointer to flow structure.
10867  */
10868 static void
10869 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10870 {
10871         struct mlx5_flow_handle *dh;
10872         uint32_t handle_idx;
10873         struct mlx5_priv *priv = dev->data->dev_private;
10874
10875         if (!flow)
10876                 return;
10877         handle_idx = flow->dev_handles;
10878         while (handle_idx) {
10879                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10880                                     handle_idx);
10881                 if (!dh)
10882                         return;
10883                 if (dh->drv_flow) {
10884                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
10885                         dh->drv_flow = NULL;
10886                 }
10887                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
10888                     dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
10889                     dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
10890                         flow_dv_fate_resource_release(dev, dh);
10891                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10892                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10893                 handle_idx = dh->next.next;
10894         }
10895 }
10896
10897 /**
10898  * Remove the flow from the NIC and the memory.
10899  * Lock free, (mutex should be acquired by caller).
10900  *
10901  * @param[in] dev
10902  *   Pointer to the Ethernet device structure.
10903  * @param[in, out] flow
10904  *   Pointer to flow structure.
10905  */
10906 static void
10907 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10908 {
10909         struct rte_flow_shared_action *shared;
10910         struct mlx5_flow_handle *dev_handle;
10911         struct mlx5_priv *priv = dev->data->dev_private;
10912
10913         if (!flow)
10914                 return;
10915         __flow_dv_remove(dev, flow);
10916         shared = mlx5_flow_get_shared_rss(flow);
10917         if (shared)
10918                 __atomic_sub_fetch(&shared->refcnt, 1, __ATOMIC_RELAXED);
10919         if (flow->counter) {
10920                 flow_dv_counter_release(dev, flow->counter);
10921                 flow->counter = 0;
10922         }
10923         if (flow->meter) {
10924                 struct mlx5_flow_meter *fm;
10925
10926                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
10927                                     flow->meter);
10928                 if (fm)
10929                         mlx5_flow_meter_detach(fm);
10930                 flow->meter = 0;
10931         }
10932         while (flow->dev_handles) {
10933                 uint32_t tmp_idx = flow->dev_handles;
10934
10935                 dev_handle = mlx5_ipool_get(priv->sh->ipool
10936                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
10937                 if (!dev_handle)
10938                         return;
10939                 flow->dev_handles = dev_handle->next.next;
10940                 if (dev_handle->dvh.matcher)
10941                         flow_dv_matcher_release(dev, dev_handle);
10942                 if (dev_handle->dvh.rix_sample)
10943                         flow_dv_sample_resource_release(dev, dev_handle);
10944                 if (dev_handle->dvh.rix_dest_array)
10945                         flow_dv_dest_array_resource_release(dev, dev_handle);
10946                 if (dev_handle->dvh.rix_encap_decap)
10947                         flow_dv_encap_decap_resource_release(dev,
10948                                 dev_handle->dvh.rix_encap_decap);
10949                 if (dev_handle->dvh.modify_hdr)
10950                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
10951                 if (dev_handle->dvh.rix_push_vlan)
10952                         flow_dv_push_vlan_action_resource_release(dev,
10953                                                                   dev_handle);
10954                 if (dev_handle->dvh.rix_tag)
10955                         flow_dv_tag_release(dev,
10956                                             dev_handle->dvh.rix_tag);
10957                 flow_dv_fate_resource_release(dev, dev_handle);
10958                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10959                            tmp_idx);
10960         }
10961 }
10962
10963 /**
10964  * Release array of hash RX queue objects.
10965  * Helper function.
10966  *
10967  * @param[in] dev
10968  *   Pointer to the Ethernet device structure.
10969  * @param[in, out] hrxqs
10970  *   Array of hash RX queue objects.
10971  *
10972  * @return
10973  *   Total number of references to hash RX queue objects in *hrxqs* array
10974  *   after this operation.
10975  */
10976 static int
10977 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
10978                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
10979 {
10980         size_t i;
10981         int remaining = 0;
10982
10983         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
10984                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
10985
10986                 if (!ret)
10987                         (*hrxqs)[i] = 0;
10988                 remaining += ret;
10989         }
10990         return remaining;
10991 }
10992
10993 /**
10994  * Release all hash RX queue objects representing shared RSS action.
10995  *
10996  * @param[in] dev
10997  *   Pointer to the Ethernet device structure.
10998  * @param[in, out] action
10999  *   Shared RSS action to remove hash RX queue objects from.
11000  *
11001  * @return
11002  *   Total number of references to hash RX queue objects stored in *action*
11003  *   after this operation.
11004  *   Expected to be 0 if no external references held.
11005  */
11006 static int
11007 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
11008                                  struct mlx5_shared_action_rss *action)
11009 {
11010         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
11011                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
11012 }
11013
11014 /**
11015  * Setup shared RSS action.
11016  * Prepare set of hash RX queue objects sufficient to handle all valid
11017  * hash_fields combinations (see enum ibv_rx_hash_fields).
11018  *
11019  * @param[in] dev
11020  *   Pointer to the Ethernet device structure.
11021  * @param[in, out] action
11022  *   Partially initialized shared RSS action.
11023  * @param[out] error
11024  *   Perform verbose error reporting if not NULL. Initialized in case of
11025  *   error only.
11026  *
11027  * @return
11028  *   0 on success, otherwise negative errno value.
11029  */
11030 static int
11031 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
11032                         struct mlx5_shared_action_rss *action,
11033                         struct rte_flow_error *error)
11034 {
11035         size_t i;
11036         int err;
11037
11038         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11039                 uint32_t hrxq_idx;
11040                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11041                 int tunnel;
11042
11043                 for (tunnel = 0; tunnel < 2; tunnel++) {
11044                         hrxq_idx = mlx5_hrxq_new(dev, action->origin.key,
11045                                         MLX5_RSS_HASH_KEY_LEN,
11046                                         hash_fields,
11047                                         action->origin.queue,
11048                                         action->origin.queue_num,
11049                                         tunnel, true);
11050                         if (!hrxq_idx) {
11051                                 rte_flow_error_set
11052                                         (error, rte_errno,
11053                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11054                                          "cannot get hash queue");
11055                                 goto error_hrxq_new;
11056                         }
11057                         err = __flow_dv_action_rss_hrxq_set
11058                                 (action, hash_fields, tunnel, hrxq_idx);
11059                         MLX5_ASSERT(!err);
11060                 }
11061         }
11062         return 0;
11063 error_hrxq_new:
11064         err = rte_errno;
11065         __flow_dv_action_rss_hrxqs_release(dev, action);
11066         rte_errno = err;
11067         return -rte_errno;
11068 }
11069
11070 /**
11071  * Create shared RSS action.
11072  *
11073  * @param[in] dev
11074  *   Pointer to the Ethernet device structure.
11075  * @param[in] conf
11076  *   Shared action configuration.
11077  * @param[in] rss
11078  *   RSS action specification used to create shared action.
11079  * @param[out] error
11080  *   Perform verbose error reporting if not NULL. Initialized in case of
11081  *   error only.
11082  *
11083  * @return
11084  *   A valid shared action handle in case of success, NULL otherwise and
11085  *   rte_errno is set.
11086  */
11087 static struct rte_flow_shared_action *
11088 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
11089                             const struct rte_flow_shared_action_conf *conf,
11090                             const struct rte_flow_action_rss *rss,
11091                             struct rte_flow_error *error)
11092 {
11093         struct rte_flow_shared_action *shared_action = NULL;
11094         void *queue = NULL;
11095         struct mlx5_shared_action_rss *shared_rss;
11096         struct rte_flow_action_rss *origin;
11097         const uint8_t *rss_key;
11098         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11099
11100         RTE_SET_USED(conf);
11101         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11102                             0, SOCKET_ID_ANY);
11103         shared_action = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*shared_action), 0,
11104                                     SOCKET_ID_ANY);
11105         if (!shared_action || !queue) {
11106                 rte_flow_error_set(error, ENOMEM,
11107                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11108                                    "cannot allocate resource memory");
11109                 goto error_rss_init;
11110         }
11111         shared_rss = &shared_action->rss;
11112         shared_rss->queue = queue;
11113         origin = &shared_rss->origin;
11114         origin->func = rss->func;
11115         origin->level = rss->level;
11116         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11117         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11118         /* NULL RSS key indicates default RSS key. */
11119         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11120         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11121         origin->key = &shared_rss->key[0];
11122         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11123         memcpy(shared_rss->queue, rss->queue, queue_size);
11124         origin->queue = shared_rss->queue;
11125         origin->queue_num = rss->queue_num;
11126         if (__flow_dv_action_rss_setup(dev, shared_rss, error))
11127                 goto error_rss_init;
11128         shared_action->type = MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS;
11129         return shared_action;
11130 error_rss_init:
11131         mlx5_free(shared_action);
11132         mlx5_free(queue);
11133         return NULL;
11134 }
11135
11136 /**
11137  * Destroy the shared RSS action.
11138  * Release related hash RX queue objects.
11139  *
11140  * @param[in] dev
11141  *   Pointer to the Ethernet device structure.
11142  * @param[in] shared_rss
11143  *   The shared RSS action object to be removed.
11144  * @param[out] error
11145  *   Perform verbose error reporting if not NULL. Initialized in case of
11146  *   error only.
11147  *
11148  * @return
11149  *   0 on success, otherwise negative errno value.
11150  */
11151 static int
11152 __flow_dv_action_rss_release(struct rte_eth_dev *dev,
11153                          struct mlx5_shared_action_rss *shared_rss,
11154                          struct rte_flow_error *error)
11155 {
11156         struct rte_flow_shared_action *shared_action = NULL;
11157         uint32_t old_refcnt = 1;
11158         int remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11159
11160         if (remaining) {
11161                 return rte_flow_error_set(error, ETOOMANYREFS,
11162                                           RTE_FLOW_ERROR_TYPE_ACTION,
11163                                           NULL,
11164                                           "shared rss hrxq has references");
11165         }
11166         shared_action = container_of(shared_rss,
11167                                      struct rte_flow_shared_action, rss);
11168         if (!__atomic_compare_exchange_n(&shared_action->refcnt, &old_refcnt,
11169                                          0, 0,
11170                                          __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {
11171                 return rte_flow_error_set(error, ETOOMANYREFS,
11172                                           RTE_FLOW_ERROR_TYPE_ACTION,
11173                                           NULL,
11174                                           "shared rss has references");
11175         }
11176         rte_free(shared_rss->queue);
11177         return 0;
11178 }
11179
11180 /**
11181  * Create shared action, lock free,
11182  * (mutex should be acquired by caller).
11183  * Dispatcher for action type specific call.
11184  *
11185  * @param[in] dev
11186  *   Pointer to the Ethernet device structure.
11187  * @param[in] conf
11188  *   Shared action configuration.
11189  * @param[in] action
11190  *   Action specification used to create shared action.
11191  * @param[out] error
11192  *   Perform verbose error reporting if not NULL. Initialized in case of
11193  *   error only.
11194  *
11195  * @return
11196  *   A valid shared action handle in case of success, NULL otherwise and
11197  *   rte_errno is set.
11198  */
11199 static struct rte_flow_shared_action *
11200 __flow_dv_action_create(struct rte_eth_dev *dev,
11201                         const struct rte_flow_shared_action_conf *conf,
11202                         const struct rte_flow_action *action,
11203                         struct rte_flow_error *error)
11204 {
11205         struct rte_flow_shared_action *shared_action = NULL;
11206         struct mlx5_priv *priv = dev->data->dev_private;
11207
11208         switch (action->type) {
11209         case RTE_FLOW_ACTION_TYPE_RSS:
11210                 shared_action = __flow_dv_action_rss_create(dev, conf,
11211                                                             action->conf,
11212                                                             error);
11213                 break;
11214         default:
11215                 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11216                                    NULL, "action type not supported");
11217                 break;
11218         }
11219         if (shared_action) {
11220                 __atomic_add_fetch(&shared_action->refcnt, 1,
11221                                    __ATOMIC_RELAXED);
11222                 LIST_INSERT_HEAD(&priv->shared_actions, shared_action, next);
11223         }
11224         return shared_action;
11225 }
11226
11227 /**
11228  * Destroy the shared action.
11229  * Release action related resources on the NIC and the memory.
11230  * Lock free, (mutex should be acquired by caller).
11231  * Dispatcher for action type specific call.
11232  *
11233  * @param[in] dev
11234  *   Pointer to the Ethernet device structure.
11235  * @param[in] action
11236  *   The shared action object to be removed.
11237  * @param[out] error
11238  *   Perform verbose error reporting if not NULL. Initialized in case of
11239  *   error only.
11240  *
11241  * @return
11242  *   0 on success, otherwise negative errno value.
11243  */
11244 static int
11245 __flow_dv_action_destroy(struct rte_eth_dev *dev,
11246                          struct rte_flow_shared_action *action,
11247                          struct rte_flow_error *error)
11248 {
11249         int ret;
11250
11251         switch (action->type) {
11252         case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11253                 ret = __flow_dv_action_rss_release(dev, &action->rss, error);
11254                 break;
11255         default:
11256                 return rte_flow_error_set(error, ENOTSUP,
11257                                           RTE_FLOW_ERROR_TYPE_ACTION,
11258                                           NULL,
11259                                           "action type not supported");
11260         }
11261         if (ret)
11262                 return ret;
11263         LIST_REMOVE(action, next);
11264         rte_free(action);
11265         return 0;
11266 }
11267
11268 /**
11269  * Updates in place shared RSS action configuration.
11270  *
11271  * @param[in] dev
11272  *   Pointer to the Ethernet device structure.
11273  * @param[in] shared_rss
11274  *   The shared RSS action object to be updated.
11275  * @param[in] action_conf
11276  *   RSS action specification used to modify *shared_rss*.
11277  * @param[out] error
11278  *   Perform verbose error reporting if not NULL. Initialized in case of
11279  *   error only.
11280  *
11281  * @return
11282  *   0 on success, otherwise negative errno value.
11283  * @note: currently only support update of RSS queues.
11284  */
11285 static int
11286 __flow_dv_action_rss_update(struct rte_eth_dev *dev,
11287                             struct mlx5_shared_action_rss *shared_rss,
11288                             const struct rte_flow_action_rss *action_conf,
11289                             struct rte_flow_error *error)
11290 {
11291         size_t i;
11292         int ret;
11293         void *queue = NULL;
11294         const uint8_t *rss_key;
11295         uint32_t rss_key_len;
11296         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11297
11298         queue = mlx5_malloc(MLX5_MEM_ZERO,
11299                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11300                             0, SOCKET_ID_ANY);
11301         if (!queue)
11302                 return rte_flow_error_set(error, ENOMEM,
11303                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11304                                           NULL,
11305                                           "cannot allocate resource memory");
11306         if (action_conf->key) {
11307                 rss_key = action_conf->key;
11308                 rss_key_len = action_conf->key_len;
11309         } else {
11310                 rss_key = rss_hash_default_key;
11311                 rss_key_len = MLX5_RSS_HASH_KEY_LEN;
11312         }
11313         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11314                 uint32_t hrxq_idx;
11315                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11316                 int tunnel;
11317
11318                 for (tunnel = 0; tunnel < 2; tunnel++) {
11319                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup
11320                                         (shared_rss, hash_fields, tunnel);
11321                         MLX5_ASSERT(hrxq_idx);
11322                         ret = mlx5_hrxq_modify
11323                                 (dev, hrxq_idx,
11324                                  rss_key, rss_key_len,
11325                                  hash_fields,
11326                                  action_conf->queue, action_conf->queue_num);
11327                         if (ret) {
11328                                 mlx5_free(queue);
11329                                 return rte_flow_error_set
11330                                         (error, rte_errno,
11331                                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11332                                          "cannot update hash queue");
11333                         }
11334                 }
11335         }
11336         mlx5_free(shared_rss->queue);
11337         shared_rss->queue = queue;
11338         memcpy(shared_rss->queue, action_conf->queue, queue_size);
11339         shared_rss->origin.queue = shared_rss->queue;
11340         shared_rss->origin.queue_num = action_conf->queue_num;
11341         return 0;
11342 }
11343
11344 /**
11345  * Updates in place shared action configuration, lock free,
11346  * (mutex should be acquired by caller).
11347  *
11348  * @param[in] dev
11349  *   Pointer to the Ethernet device structure.
11350  * @param[in] action
11351  *   The shared action object to be updated.
11352  * @param[in] action_conf
11353  *   Action specification used to modify *action*.
11354  *   *action_conf* should be of type correlating with type of the *action*,
11355  *   otherwise considered as invalid.
11356  * @param[out] error
11357  *   Perform verbose error reporting if not NULL. Initialized in case of
11358  *   error only.
11359  *
11360  * @return
11361  *   0 on success, otherwise negative errno value.
11362  */
11363 static int
11364 __flow_dv_action_update(struct rte_eth_dev *dev,
11365                         struct rte_flow_shared_action *action,
11366                         const void *action_conf,
11367                         struct rte_flow_error *error)
11368 {
11369         switch (action->type) {
11370         case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11371                 return __flow_dv_action_rss_update(dev, &action->rss,
11372                                                    action_conf, error);
11373         default:
11374                 return rte_flow_error_set(error, ENOTSUP,
11375                                           RTE_FLOW_ERROR_TYPE_ACTION,
11376                                           NULL,
11377                                           "action type not supported");
11378         }
11379 }
11380 /**
11381  * Query a dv flow  rule for its statistics via devx.
11382  *
11383  * @param[in] dev
11384  *   Pointer to Ethernet device.
11385  * @param[in] flow
11386  *   Pointer to the sub flow.
11387  * @param[out] data
11388  *   data retrieved by the query.
11389  * @param[out] error
11390  *   Perform verbose error reporting if not NULL.
11391  *
11392  * @return
11393  *   0 on success, a negative errno value otherwise and rte_errno is set.
11394  */
11395 static int
11396 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11397                     void *data, struct rte_flow_error *error)
11398 {
11399         struct mlx5_priv *priv = dev->data->dev_private;
11400         struct rte_flow_query_count *qc = data;
11401
11402         if (!priv->config.devx)
11403                 return rte_flow_error_set(error, ENOTSUP,
11404                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11405                                           NULL,
11406                                           "counters are not supported");
11407         if (flow->counter) {
11408                 uint64_t pkts, bytes;
11409                 struct mlx5_flow_counter *cnt;
11410
11411                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11412                                                  NULL);
11413                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11414                                                &bytes);
11415
11416                 if (err)
11417                         return rte_flow_error_set(error, -err,
11418                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11419                                         NULL, "cannot read counters");
11420                 qc->hits_set = 1;
11421                 qc->bytes_set = 1;
11422                 qc->hits = pkts - cnt->hits;
11423                 qc->bytes = bytes - cnt->bytes;
11424                 if (qc->reset) {
11425                         cnt->hits = pkts;
11426                         cnt->bytes = bytes;
11427                 }
11428                 return 0;
11429         }
11430         return rte_flow_error_set(error, EINVAL,
11431                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11432                                   NULL,
11433                                   "counters are not available");
11434 }
11435
11436 /**
11437  * Query a flow rule AGE action for aging information.
11438  *
11439  * @param[in] dev
11440  *   Pointer to Ethernet device.
11441  * @param[in] flow
11442  *   Pointer to the sub flow.
11443  * @param[out] data
11444  *   data retrieved by the query.
11445  * @param[out] error
11446  *   Perform verbose error reporting if not NULL.
11447  *
11448  * @return
11449  *   0 on success, a negative errno value otherwise and rte_errno is set.
11450  */
11451 static int
11452 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11453                   void *data, struct rte_flow_error *error)
11454 {
11455         struct rte_flow_query_age *resp = data;
11456
11457         if (flow->counter) {
11458                 struct mlx5_age_param *age_param =
11459                                 flow_dv_counter_idx_get_age(dev, flow->counter);
11460
11461                 if (!age_param || !age_param->timeout)
11462                         return rte_flow_error_set
11463                                         (error, EINVAL,
11464                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11465                                          NULL, "cannot read age data");
11466                 resp->aged = __atomic_load_n(&age_param->state,
11467                                              __ATOMIC_RELAXED) ==
11468                                                         AGE_TMOUT ? 1 : 0;
11469                 resp->sec_since_last_hit_valid = !resp->aged;
11470                 if (resp->sec_since_last_hit_valid)
11471                         resp->sec_since_last_hit =
11472                                 __atomic_load_n(&age_param->sec_since_last_hit,
11473                                                 __ATOMIC_RELAXED);
11474                 return 0;
11475         }
11476         return rte_flow_error_set(error, EINVAL,
11477                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11478                                   NULL,
11479                                   "age data not available");
11480 }
11481
11482 /**
11483  * Query a flow.
11484  *
11485  * @see rte_flow_query()
11486  * @see rte_flow_ops
11487  */
11488 static int
11489 flow_dv_query(struct rte_eth_dev *dev,
11490               struct rte_flow *flow __rte_unused,
11491               const struct rte_flow_action *actions __rte_unused,
11492               void *data __rte_unused,
11493               struct rte_flow_error *error __rte_unused)
11494 {
11495         int ret = -EINVAL;
11496
11497         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11498                 switch (actions->type) {
11499                 case RTE_FLOW_ACTION_TYPE_VOID:
11500                         break;
11501                 case RTE_FLOW_ACTION_TYPE_COUNT:
11502                         ret = flow_dv_query_count(dev, flow, data, error);
11503                         break;
11504                 case RTE_FLOW_ACTION_TYPE_AGE:
11505                         ret = flow_dv_query_age(dev, flow, data, error);
11506                         break;
11507                 default:
11508                         return rte_flow_error_set(error, ENOTSUP,
11509                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11510                                                   actions,
11511                                                   "action not supported");
11512                 }
11513         }
11514         return ret;
11515 }
11516
11517 /**
11518  * Destroy the meter table set.
11519  * Lock free, (mutex should be acquired by caller).
11520  *
11521  * @param[in] dev
11522  *   Pointer to Ethernet device.
11523  * @param[in] tbl
11524  *   Pointer to the meter table set.
11525  *
11526  * @return
11527  *   Always 0.
11528  */
11529 static int
11530 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11531                         struct mlx5_meter_domains_infos *tbl)
11532 {
11533         struct mlx5_priv *priv = dev->data->dev_private;
11534         struct mlx5_meter_domains_infos *mtd =
11535                                 (struct mlx5_meter_domains_infos *)tbl;
11536
11537         if (!mtd || !priv->config.dv_flow_en)
11538                 return 0;
11539         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11540                 claim_zero(mlx5_flow_os_destroy_flow
11541                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11542         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11543                 claim_zero(mlx5_flow_os_destroy_flow
11544                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11545         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11546                 claim_zero(mlx5_flow_os_destroy_flow
11547                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
11548         if (mtd->egress.color_matcher)
11549                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11550                            (mtd->egress.color_matcher));
11551         if (mtd->egress.any_matcher)
11552                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11553                            (mtd->egress.any_matcher));
11554         if (mtd->egress.tbl)
11555                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
11556         if (mtd->egress.sfx_tbl)
11557                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
11558         if (mtd->ingress.color_matcher)
11559                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11560                            (mtd->ingress.color_matcher));
11561         if (mtd->ingress.any_matcher)
11562                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11563                            (mtd->ingress.any_matcher));
11564         if (mtd->ingress.tbl)
11565                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
11566         if (mtd->ingress.sfx_tbl)
11567                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
11568         if (mtd->transfer.color_matcher)
11569                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11570                            (mtd->transfer.color_matcher));
11571         if (mtd->transfer.any_matcher)
11572                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11573                            (mtd->transfer.any_matcher));
11574         if (mtd->transfer.tbl)
11575                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
11576         if (mtd->transfer.sfx_tbl)
11577                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
11578         if (mtd->drop_actn)
11579                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
11580         mlx5_free(mtd);
11581         return 0;
11582 }
11583
11584 /* Number of meter flow actions, count and jump or count and drop. */
11585 #define METER_ACTIONS 2
11586
11587 /**
11588  * Create specify domain meter table and suffix table.
11589  *
11590  * @param[in] dev
11591  *   Pointer to Ethernet device.
11592  * @param[in,out] mtb
11593  *   Pointer to DV meter table set.
11594  * @param[in] egress
11595  *   Table attribute.
11596  * @param[in] transfer
11597  *   Table attribute.
11598  * @param[in] color_reg_c_idx
11599  *   Reg C index for color match.
11600  *
11601  * @return
11602  *   0 on success, -1 otherwise and rte_errno is set.
11603  */
11604 static int
11605 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
11606                            struct mlx5_meter_domains_infos *mtb,
11607                            uint8_t egress, uint8_t transfer,
11608                            uint32_t color_reg_c_idx)
11609 {
11610         struct mlx5_priv *priv = dev->data->dev_private;
11611         struct mlx5_dev_ctx_shared *sh = priv->sh;
11612         struct mlx5_flow_dv_match_params mask = {
11613                 .size = sizeof(mask.buf),
11614         };
11615         struct mlx5_flow_dv_match_params value = {
11616                 .size = sizeof(value.buf),
11617         };
11618         struct mlx5dv_flow_matcher_attr dv_attr = {
11619                 .type = IBV_FLOW_ATTR_NORMAL,
11620                 .priority = 0,
11621                 .match_criteria_enable = 0,
11622                 .match_mask = (void *)&mask,
11623         };
11624         void *actions[METER_ACTIONS];
11625         struct mlx5_meter_domain_info *dtb;
11626         struct rte_flow_error error;
11627         int i = 0;
11628         int ret;
11629
11630         if (transfer)
11631                 dtb = &mtb->transfer;
11632         else if (egress)
11633                 dtb = &mtb->egress;
11634         else
11635                 dtb = &mtb->ingress;
11636         /* Create the meter table with METER level. */
11637         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
11638                                             egress, transfer, false, NULL, 0,
11639                                             &error);
11640         if (!dtb->tbl) {
11641                 DRV_LOG(ERR, "Failed to create meter policer table.");
11642                 return -1;
11643         }
11644         /* Create the meter suffix table with SUFFIX level. */
11645         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
11646                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
11647                                             egress, transfer, false, NULL, 0,
11648                                             &error);
11649         if (!dtb->sfx_tbl) {
11650                 DRV_LOG(ERR, "Failed to create meter suffix table.");
11651                 return -1;
11652         }
11653         /* Create matchers, Any and Color. */
11654         dv_attr.priority = 3;
11655         dv_attr.match_criteria_enable = 0;
11656         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11657                                                &dtb->any_matcher);
11658         if (ret) {
11659                 DRV_LOG(ERR, "Failed to create meter"
11660                              " policer default matcher.");
11661                 goto error_exit;
11662         }
11663         dv_attr.priority = 0;
11664         dv_attr.match_criteria_enable =
11665                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
11666         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
11667                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
11668         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11669                                                &dtb->color_matcher);
11670         if (ret) {
11671                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
11672                 goto error_exit;
11673         }
11674         if (mtb->count_actns[RTE_MTR_DROPPED])
11675                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
11676         actions[i++] = mtb->drop_actn;
11677         /* Default rule: lowest priority, match any, actions: drop. */
11678         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
11679                                        actions,
11680                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
11681         if (ret) {
11682                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
11683                 goto error_exit;
11684         }
11685         return 0;
11686 error_exit:
11687         return -1;
11688 }
11689
11690 /**
11691  * Create the needed meter and suffix tables.
11692  * Lock free, (mutex should be acquired by caller).
11693  *
11694  * @param[in] dev
11695  *   Pointer to Ethernet device.
11696  * @param[in] fm
11697  *   Pointer to the flow meter.
11698  *
11699  * @return
11700  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
11701  */
11702 static struct mlx5_meter_domains_infos *
11703 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
11704                        const struct mlx5_flow_meter *fm)
11705 {
11706         struct mlx5_priv *priv = dev->data->dev_private;
11707         struct mlx5_meter_domains_infos *mtb;
11708         int ret;
11709         int i;
11710
11711         if (!priv->mtr_en) {
11712                 rte_errno = ENOTSUP;
11713                 return NULL;
11714         }
11715         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
11716         if (!mtb) {
11717                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
11718                 return NULL;
11719         }
11720         /* Create meter count actions */
11721         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
11722                 struct mlx5_flow_counter *cnt;
11723                 if (!fm->policer_stats.cnt[i])
11724                         continue;
11725                 cnt = flow_dv_counter_get_by_idx(dev,
11726                       fm->policer_stats.cnt[i], NULL);
11727                 mtb->count_actns[i] = cnt->action;
11728         }
11729         /* Create drop action. */
11730         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
11731         if (ret) {
11732                 DRV_LOG(ERR, "Failed to create drop action.");
11733                 goto error_exit;
11734         }
11735         /* Egress meter table. */
11736         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
11737         if (ret) {
11738                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
11739                 goto error_exit;
11740         }
11741         /* Ingress meter table. */
11742         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
11743         if (ret) {
11744                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
11745                 goto error_exit;
11746         }
11747         /* FDB meter table. */
11748         if (priv->config.dv_esw_en) {
11749                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
11750                                                  priv->mtr_color_reg);
11751                 if (ret) {
11752                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
11753                         goto error_exit;
11754                 }
11755         }
11756         return mtb;
11757 error_exit:
11758         flow_dv_destroy_mtr_tbl(dev, mtb);
11759         return NULL;
11760 }
11761
11762 /**
11763  * Destroy domain policer rule.
11764  *
11765  * @param[in] dt
11766  *   Pointer to domain table.
11767  */
11768 static void
11769 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
11770 {
11771         int i;
11772
11773         for (i = 0; i < RTE_MTR_DROPPED; i++) {
11774                 if (dt->policer_rules[i]) {
11775                         claim_zero(mlx5_flow_os_destroy_flow
11776                                    (dt->policer_rules[i]));
11777                         dt->policer_rules[i] = NULL;
11778                 }
11779         }
11780         if (dt->jump_actn) {
11781                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
11782                 dt->jump_actn = NULL;
11783         }
11784 }
11785
11786 /**
11787  * Destroy policer rules.
11788  *
11789  * @param[in] dev
11790  *   Pointer to Ethernet device.
11791  * @param[in] fm
11792  *   Pointer to flow meter structure.
11793  * @param[in] attr
11794  *   Pointer to flow attributes.
11795  *
11796  * @return
11797  *   Always 0.
11798  */
11799 static int
11800 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
11801                               const struct mlx5_flow_meter *fm,
11802                               const struct rte_flow_attr *attr)
11803 {
11804         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
11805
11806         if (!mtb)
11807                 return 0;
11808         if (attr->egress)
11809                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
11810         if (attr->ingress)
11811                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
11812         if (attr->transfer)
11813                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
11814         return 0;
11815 }
11816
11817 /**
11818  * Create specify domain meter policer rule.
11819  *
11820  * @param[in] fm
11821  *   Pointer to flow meter structure.
11822  * @param[in] mtb
11823  *   Pointer to DV meter table set.
11824  * @param[in] mtr_reg_c
11825  *   Color match REG_C.
11826  *
11827  * @return
11828  *   0 on success, -1 otherwise.
11829  */
11830 static int
11831 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
11832                                     struct mlx5_meter_domain_info *dtb,
11833                                     uint8_t mtr_reg_c)
11834 {
11835         struct mlx5_flow_dv_match_params matcher = {
11836                 .size = sizeof(matcher.buf),
11837         };
11838         struct mlx5_flow_dv_match_params value = {
11839                 .size = sizeof(value.buf),
11840         };
11841         struct mlx5_meter_domains_infos *mtb = fm->mfts;
11842         void *actions[METER_ACTIONS];
11843         int i;
11844         int ret = 0;
11845
11846         /* Create jump action. */
11847         if (!dtb->jump_actn)
11848                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11849                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
11850         if (ret) {
11851                 DRV_LOG(ERR, "Failed to create policer jump action.");
11852                 goto error;
11853         }
11854         for (i = 0; i < RTE_MTR_DROPPED; i++) {
11855                 int j = 0;
11856
11857                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
11858                                        rte_col_2_mlx5_col(i), UINT8_MAX);
11859                 if (mtb->count_actns[i])
11860                         actions[j++] = mtb->count_actns[i];
11861                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
11862                         actions[j++] = mtb->drop_actn;
11863                 else
11864                         actions[j++] = dtb->jump_actn;
11865                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
11866                                                (void *)&value, j, actions,
11867                                                &dtb->policer_rules[i]);
11868                 if (ret) {
11869                         DRV_LOG(ERR, "Failed to create policer rule.");
11870                         goto error;
11871                 }
11872         }
11873         return 0;
11874 error:
11875         rte_errno = errno;
11876         return -1;
11877 }
11878
11879 /**
11880  * Create policer rules.
11881  *
11882  * @param[in] dev
11883  *   Pointer to Ethernet device.
11884  * @param[in] fm
11885  *   Pointer to flow meter structure.
11886  * @param[in] attr
11887  *   Pointer to flow attributes.
11888  *
11889  * @return
11890  *   0 on success, -1 otherwise.
11891  */
11892 static int
11893 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
11894                              struct mlx5_flow_meter *fm,
11895                              const struct rte_flow_attr *attr)
11896 {
11897         struct mlx5_priv *priv = dev->data->dev_private;
11898         struct mlx5_meter_domains_infos *mtb = fm->mfts;
11899         int ret;
11900
11901         if (attr->egress) {
11902                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
11903                                                 priv->mtr_color_reg);
11904                 if (ret) {
11905                         DRV_LOG(ERR, "Failed to create egress policer.");
11906                         goto error;
11907                 }
11908         }
11909         if (attr->ingress) {
11910                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
11911                                                 priv->mtr_color_reg);
11912                 if (ret) {
11913                         DRV_LOG(ERR, "Failed to create ingress policer.");
11914                         goto error;
11915                 }
11916         }
11917         if (attr->transfer) {
11918                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
11919                                                 priv->mtr_color_reg);
11920                 if (ret) {
11921                         DRV_LOG(ERR, "Failed to create transfer policer.");
11922                         goto error;
11923                 }
11924         }
11925         return 0;
11926 error:
11927         flow_dv_destroy_policer_rules(dev, fm, attr);
11928         return -1;
11929 }
11930
11931 /**
11932  * Validate the batch counter support in root table.
11933  *
11934  * Create a simple flow with invalid counter and drop action on root table to
11935  * validate if batch counter with offset on root table is supported or not.
11936  *
11937  * @param[in] dev
11938  *   Pointer to rte_eth_dev structure.
11939  *
11940  * @return
11941  *   0 on success, a negative errno value otherwise and rte_errno is set.
11942  */
11943 int
11944 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
11945 {
11946         struct mlx5_priv *priv = dev->data->dev_private;
11947         struct mlx5_dev_ctx_shared *sh = priv->sh;
11948         struct mlx5_flow_dv_match_params mask = {
11949                 .size = sizeof(mask.buf),
11950         };
11951         struct mlx5_flow_dv_match_params value = {
11952                 .size = sizeof(value.buf),
11953         };
11954         struct mlx5dv_flow_matcher_attr dv_attr = {
11955                 .type = IBV_FLOW_ATTR_NORMAL,
11956                 .priority = 0,
11957                 .match_criteria_enable = 0,
11958                 .match_mask = (void *)&mask,
11959         };
11960         void *actions[2] = { 0 };
11961         struct mlx5_flow_tbl_resource *tbl = NULL, *dest_tbl = NULL;
11962         struct mlx5_devx_obj *dcs = NULL;
11963         void *matcher = NULL;
11964         void *flow = NULL;
11965         int i, ret = -1;
11966
11967         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, NULL);
11968         if (!tbl)
11969                 goto err;
11970         dest_tbl = flow_dv_tbl_resource_get(dev, 1, 0, 0, false, NULL, 0, NULL);
11971         if (!dest_tbl)
11972                 goto err;
11973         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
11974         if (!dcs)
11975                 goto err;
11976         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
11977                                                     &actions[0]);
11978         if (ret)
11979                 goto err;
11980         ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11981                                 (dest_tbl->obj, &actions[1]);
11982         if (ret)
11983                 goto err;
11984         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
11985         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
11986                                                &matcher);
11987         if (ret)
11988                 goto err;
11989         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
11990                                        actions, &flow);
11991 err:
11992         /*
11993          * If batch counter with offset is not supported, the driver will not
11994          * validate the invalid offset value, flow create should success.
11995          * In this case, it means batch counter is not supported in root table.
11996          *
11997          * Otherwise, if flow create is failed, counter offset is supported.
11998          */
11999         if (flow) {
12000                 DRV_LOG(INFO, "Batch counter is not supported in root "
12001                               "table. Switch to fallback mode.");
12002                 rte_errno = ENOTSUP;
12003                 ret = -rte_errno;
12004                 claim_zero(mlx5_flow_os_destroy_flow(flow));
12005         } else {
12006                 /* Check matcher to make sure validate fail at flow create. */
12007                 if (!matcher || (matcher && errno != EINVAL))
12008                         DRV_LOG(ERR, "Unexpected error in counter offset "
12009                                      "support detection");
12010                 ret = 0;
12011         }
12012         for (i = 0; i < 2; i++) {
12013                 if (actions[i])
12014                         claim_zero(mlx5_flow_os_destroy_flow_action
12015                                    (actions[i]));
12016         }
12017         if (matcher)
12018                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
12019         if (tbl)
12020                 flow_dv_tbl_resource_release(dev, tbl);
12021         if (dest_tbl)
12022                 flow_dv_tbl_resource_release(dev, dest_tbl);
12023         if (dcs)
12024                 claim_zero(mlx5_devx_cmd_destroy(dcs));
12025         return ret;
12026 }
12027
12028 /**
12029  * Query a devx counter.
12030  *
12031  * @param[in] dev
12032  *   Pointer to the Ethernet device structure.
12033  * @param[in] cnt
12034  *   Index to the flow counter.
12035  * @param[in] clear
12036  *   Set to clear the counter statistics.
12037  * @param[out] pkts
12038  *   The statistics value of packets.
12039  * @param[out] bytes
12040  *   The statistics value of bytes.
12041  *
12042  * @return
12043  *   0 on success, otherwise return -1.
12044  */
12045 static int
12046 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
12047                       uint64_t *pkts, uint64_t *bytes)
12048 {
12049         struct mlx5_priv *priv = dev->data->dev_private;
12050         struct mlx5_flow_counter *cnt;
12051         uint64_t inn_pkts, inn_bytes;
12052         int ret;
12053
12054         if (!priv->config.devx)
12055                 return -1;
12056
12057         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
12058         if (ret)
12059                 return -1;
12060         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
12061         *pkts = inn_pkts - cnt->hits;
12062         *bytes = inn_bytes - cnt->bytes;
12063         if (clear) {
12064                 cnt->hits = inn_pkts;
12065                 cnt->bytes = inn_bytes;
12066         }
12067         return 0;
12068 }
12069
12070 /**
12071  * Get aged-out flows.
12072  *
12073  * @param[in] dev
12074  *   Pointer to the Ethernet device structure.
12075  * @param[in] context
12076  *   The address of an array of pointers to the aged-out flows contexts.
12077  * @param[in] nb_contexts
12078  *   The length of context array pointers.
12079  * @param[out] error
12080  *   Perform verbose error reporting if not NULL. Initialized in case of
12081  *   error only.
12082  *
12083  * @return
12084  *   how many contexts get in success, otherwise negative errno value.
12085  *   if nb_contexts is 0, return the amount of all aged contexts.
12086  *   if nb_contexts is not 0 , return the amount of aged flows reported
12087  *   in the context array.
12088  * @note: only stub for now
12089  */
12090 static int
12091 flow_get_aged_flows(struct rte_eth_dev *dev,
12092                     void **context,
12093                     uint32_t nb_contexts,
12094                     struct rte_flow_error *error)
12095 {
12096         struct mlx5_priv *priv = dev->data->dev_private;
12097         struct mlx5_age_info *age_info;
12098         struct mlx5_age_param *age_param;
12099         struct mlx5_flow_counter *counter;
12100         int nb_flows = 0;
12101
12102         if (nb_contexts && !context)
12103                 return rte_flow_error_set(error, EINVAL,
12104                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12105                                           NULL,
12106                                           "Should assign at least one flow or"
12107                                           " context to get if nb_contexts != 0");
12108         age_info = GET_PORT_AGE_INFO(priv);
12109         rte_spinlock_lock(&age_info->aged_sl);
12110         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12111                 nb_flows++;
12112                 if (nb_contexts) {
12113                         age_param = MLX5_CNT_TO_AGE(counter);
12114                         context[nb_flows - 1] = age_param->context;
12115                         if (!(--nb_contexts))
12116                                 break;
12117                 }
12118         }
12119         rte_spinlock_unlock(&age_info->aged_sl);
12120         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12121         return nb_flows;
12122 }
12123
12124 /*
12125  * Mutex-protected thunk to lock-free  __flow_dv_translate().
12126  */
12127 static int
12128 flow_dv_translate(struct rte_eth_dev *dev,
12129                   struct mlx5_flow *dev_flow,
12130                   const struct rte_flow_attr *attr,
12131                   const struct rte_flow_item items[],
12132                   const struct rte_flow_action actions[],
12133                   struct rte_flow_error *error)
12134 {
12135         int ret;
12136
12137         flow_dv_shared_lock(dev);
12138         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
12139         flow_dv_shared_unlock(dev);
12140         return ret;
12141 }
12142
12143 /*
12144  * Mutex-protected thunk to lock-free  __flow_dv_apply().
12145  */
12146 static int
12147 flow_dv_apply(struct rte_eth_dev *dev,
12148               struct rte_flow *flow,
12149               struct rte_flow_error *error)
12150 {
12151         int ret;
12152
12153         flow_dv_shared_lock(dev);
12154         ret = __flow_dv_apply(dev, flow, error);
12155         flow_dv_shared_unlock(dev);
12156         return ret;
12157 }
12158
12159 /*
12160  * Mutex-protected thunk to lock-free __flow_dv_remove().
12161  */
12162 static void
12163 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12164 {
12165         flow_dv_shared_lock(dev);
12166         __flow_dv_remove(dev, flow);
12167         flow_dv_shared_unlock(dev);
12168 }
12169
12170 /*
12171  * Mutex-protected thunk to lock-free __flow_dv_destroy().
12172  */
12173 static void
12174 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12175 {
12176         flow_dv_shared_lock(dev);
12177         __flow_dv_destroy(dev, flow);
12178         flow_dv_shared_unlock(dev);
12179 }
12180
12181 /*
12182  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12183  */
12184 static uint32_t
12185 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12186 {
12187         uint32_t cnt;
12188
12189         flow_dv_shared_lock(dev);
12190         cnt = flow_dv_counter_alloc(dev, 0);
12191         flow_dv_shared_unlock(dev);
12192         return cnt;
12193 }
12194
12195 /*
12196  * Mutex-protected thunk to lock-free flow_dv_counter_release().
12197  */
12198 static void
12199 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
12200 {
12201         flow_dv_shared_lock(dev);
12202         flow_dv_counter_release(dev, cnt);
12203         flow_dv_shared_unlock(dev);
12204 }
12205
12206 /**
12207  * Validate shared action.
12208  * Dispatcher for action type specific validation.
12209  *
12210  * @param[in] dev
12211  *   Pointer to the Ethernet device structure.
12212  * @param[in] conf
12213  *   Shared action configuration.
12214  * @param[in] action
12215  *   The shared action object to validate.
12216  * @param[out] error
12217  *   Perform verbose error reporting if not NULL. Initialized in case of
12218  *   error only.
12219  *
12220  * @return
12221  *   0 on success, otherwise negative errno value.
12222  */
12223 static int
12224 flow_dv_action_validate(struct rte_eth_dev *dev,
12225                         const struct rte_flow_shared_action_conf *conf,
12226                         const struct rte_flow_action *action,
12227                         struct rte_flow_error *error)
12228 {
12229         RTE_SET_USED(conf);
12230         switch (action->type) {
12231         case RTE_FLOW_ACTION_TYPE_RSS:
12232                 return mlx5_validate_action_rss(dev, action, error);
12233         default:
12234                 return rte_flow_error_set(error, ENOTSUP,
12235                                           RTE_FLOW_ERROR_TYPE_ACTION,
12236                                           NULL,
12237                                           "action type not supported");
12238         }
12239 }
12240
12241 /*
12242  * Mutex-protected thunk to lock-free  __flow_dv_action_create().
12243  */
12244 static struct rte_flow_shared_action *
12245 flow_dv_action_create(struct rte_eth_dev *dev,
12246                       const struct rte_flow_shared_action_conf *conf,
12247                       const struct rte_flow_action *action,
12248                       struct rte_flow_error *error)
12249 {
12250         struct rte_flow_shared_action *shared_action = NULL;
12251
12252         flow_dv_shared_lock(dev);
12253         shared_action = __flow_dv_action_create(dev, conf, action, error);
12254         flow_dv_shared_unlock(dev);
12255         return shared_action;
12256 }
12257
12258 /*
12259  * Mutex-protected thunk to lock-free  __flow_dv_action_destroy().
12260  */
12261 static int
12262 flow_dv_action_destroy(struct rte_eth_dev *dev,
12263                        struct rte_flow_shared_action *action,
12264                        struct rte_flow_error *error)
12265 {
12266         int ret;
12267
12268         flow_dv_shared_lock(dev);
12269         ret = __flow_dv_action_destroy(dev, action, error);
12270         flow_dv_shared_unlock(dev);
12271         return ret;
12272 }
12273
12274 /*
12275  * Mutex-protected thunk to lock-free  __flow_dv_action_update().
12276  */
12277 static int
12278 flow_dv_action_update(struct rte_eth_dev *dev,
12279                       struct rte_flow_shared_action *action,
12280                       const void *action_conf,
12281                       struct rte_flow_error *error)
12282 {
12283         int ret;
12284
12285         flow_dv_shared_lock(dev);
12286         ret = __flow_dv_action_update(dev, action, action_conf,
12287                                       error);
12288         flow_dv_shared_unlock(dev);
12289         return ret;
12290 }
12291
12292 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12293         .validate = flow_dv_validate,
12294         .prepare = flow_dv_prepare,
12295         .translate = flow_dv_translate,
12296         .apply = flow_dv_apply,
12297         .remove = flow_dv_remove,
12298         .destroy = flow_dv_destroy,
12299         .query = flow_dv_query,
12300         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12301         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12302         .create_policer_rules = flow_dv_create_policer_rules,
12303         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12304         .counter_alloc = flow_dv_counter_allocate,
12305         .counter_free = flow_dv_counter_free,
12306         .counter_query = flow_dv_counter_query,
12307         .get_aged_flows = flow_get_aged_flows,
12308         .action_validate = flow_dv_action_validate,
12309         .action_create = flow_dv_action_create,
12310         .action_destroy = flow_dv_action_destroy,
12311         .action_update = flow_dv_action_update,
12312 };
12313
12314 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12315