drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_cycles.h>
  28 #include <rte_ip.h>
  29 #include <rte_gre.h>
  30 #include <rte_vxlan.h>
  31 #include <rte_gtp.h>
  32
  33 #include <mlx5_glue.h>
  34 #include <mlx5_devx_cmds.h>
  35 #include <mlx5_prm.h>
  36
  37 #include "mlx5_defs.h"
  38 #include "mlx5.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_rxtx.h"
  41
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43
  44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  46 #endif
  47
  48 #ifndef HAVE_MLX5DV_DR_ESWITCH
  49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  51 #endif
  52 #endif
  53
  54 #ifndef HAVE_MLX5DV_DR
  55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  56 #endif
  57
  58 /* VLAN header definitions */
  59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  64
  65 union flow_dv_attr {
  66         struct {
  67                 uint32_t valid:1;
  68                 uint32_t ipv4:1;
  69                 uint32_t ipv6:1;
  70                 uint32_t tcp:1;
  71                 uint32_t udp:1;
  72                 uint32_t reserved:27;
  73         };
  74         uint32_t attr;
  75 };
  76
  77 static int
  78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  79                              struct mlx5_flow_tbl_resource *tbl);
  80
  81 /**
  82  * Initialize flow attributes structure according to flow items' types.
  83  *
  84  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  85  * mode. For tunnel mode, the items to be modified are the outermost ones.
  86  *
  87  * @param[in] item
  88  *   Pointer to item specification.
  89  * @param[out] attr
  90  *   Pointer to flow attributes structure.
  91  * @param[in] dev_flow
  92  *   Pointer to the sub flow.
  93  * @param[in] tunnel_decap
  94  *   Whether action is after tunnel decapsulation.
  95  */
  96 static void
  97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  98                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  99 {
 100         uint64_t layers = dev_flow->handle->layers;
 101
 102         /*
 103          * If layers is already initialized, it means this dev_flow is the
 104          * suffix flow, the layers flags is set by the prefix flow. Need to
 105          * use the layer flags from prefix flow as the suffix flow may not
 106          * have the user defined items as the flow is split.
 107          */
 108         if (layers) {
 109                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 110                         attr->ipv4 = 1;
 111                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 112                         attr->ipv6 = 1;
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 114                         attr->tcp = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 116                         attr->udp = 1;
 117                 attr->valid = 1;
 118                 return;
 119         }
 120         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 121                 uint8_t next_protocol = 0xff;
 122                 switch (item->type) {
 123                 case RTE_FLOW_ITEM_TYPE_GRE:
 124                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 126                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 127                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 128                 case RTE_FLOW_ITEM_TYPE_MPLS:
 129                         if (tunnel_decap)
 130                                 attr->attr = 0;
 131                         break;
 132                 case RTE_FLOW_ITEM_TYPE_IPV4:
 133                         if (!attr->ipv6)
 134                                 attr->ipv4 = 1;
 135                         if (item->mask != NULL &&
 136                             ((const struct rte_flow_item_ipv4 *)
 137                             item->mask)->hdr.next_proto_id)
 138                                 next_protocol =
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->spec))->hdr.next_proto_id &
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->mask))->hdr.next_proto_id;
 143                         if ((next_protocol == IPPROTO_IPIP ||
 144                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 145                                 attr->attr = 0;
 146                         break;
 147                 case RTE_FLOW_ITEM_TYPE_IPV6:
 148                         if (!attr->ipv4)
 149                                 attr->ipv6 = 1;
 150                         if (item->mask != NULL &&
 151                             ((const struct rte_flow_item_ipv6 *)
 152                             item->mask)->hdr.proto)
 153                                 next_protocol =
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->spec))->hdr.proto &
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->mask))->hdr.proto;
 158                         if ((next_protocol == IPPROTO_IPIP ||
 159                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 160                                 attr->attr = 0;
 161                         break;
 162                 case RTE_FLOW_ITEM_TYPE_UDP:
 163                         if (!attr->tcp)
 164                                 attr->udp = 1;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_TCP:
 167                         if (!attr->udp)
 168                                 attr->tcp = 1;
 169                         break;
 170                 default:
 171                         break;
 172                 }
 173         }
 174         attr->valid = 1;
 175 }
 176
 177 /**
 178  * Convert rte_mtr_color to mlx5 color.
 179  *
 180  * @param[in] rcol
 181  *   rte_mtr_color.
 182  *
 183  * @return
 184  *   mlx5 color.
 185  */
 186 static int
 187 rte_col_2_mlx5_col(enum rte_color rcol)
 188 {
 189         switch (rcol) {
 190         case RTE_COLOR_GREEN:
 191                 return MLX5_FLOW_COLOR_GREEN;
 192         case RTE_COLOR_YELLOW:
 193                 return MLX5_FLOW_COLOR_YELLOW;
 194         case RTE_COLOR_RED:
 195                 return MLX5_FLOW_COLOR_RED;
 196         default:
 197                 break;
 198         }
 199         return MLX5_FLOW_COLOR_UNDEFINED;
 200 }
 201
 202 struct field_modify_info {
 203         uint32_t size; /* Size of field in protocol header, in bytes. */
 204         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 205         enum mlx5_modification_field id;
 206 };
 207
 208 struct field_modify_info modify_eth[] = {
 209         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 210         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 211         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 212         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_vlan_out_first_vid[] = {
 217         /* Size in bits !!! */
 218         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_ipv4[] = {
 223         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 224         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 225         {4, 12, MLX5_MODI_OUT_SIPV4},
 226         {4, 16, MLX5_MODI_OUT_DIPV4},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_ipv6[] = {
 231         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 232         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 233         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 234         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 235         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 236         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 237         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 238         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 239         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 240         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 241         {0, 0, 0},
 242 };
 243
 244 struct field_modify_info modify_udp[] = {
 245         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 246         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_tcp[] = {
 251         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 253         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 254         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 255         {0, 0, 0},
 256 };
 257
 258 static void
 259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 260                           uint8_t next_protocol, uint64_t *item_flags,
 261                           int *tunnel)
 262 {
 263         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 264                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 265         if (next_protocol == IPPROTO_IPIP) {
 266                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 267                 *tunnel = 1;
 268         }
 269         if (next_protocol == IPPROTO_IPV6) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 271                 *tunnel = 1;
 272         }
 273 }
 274
 275 /**
 276  * Acquire the synchronizing object to protect multithreaded access
 277  * to shared dv context. Lock occurs only if context is actually
 278  * shared, i.e. we have multiport IB device and representors are
 279  * created.
 280  *
 281  * @param[in] dev
 282  *   Pointer to the rte_eth_dev structure.
 283  */
 284 static void
 285 flow_dv_shared_lock(struct rte_eth_dev *dev)
 286 {
 287         struct mlx5_priv *priv = dev->data->dev_private;
 288         struct mlx5_ibv_shared *sh = priv->sh;
 289
 290         if (sh->dv_refcnt > 1) {
 291                 int ret;
 292
 293                 ret = pthread_mutex_lock(&sh->dv_mutex);
 294                 MLX5_ASSERT(!ret);
 295                 (void)ret;
 296         }
 297 }
 298
 299 static void
 300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 301 {
 302         struct mlx5_priv *priv = dev->data->dev_private;
 303         struct mlx5_ibv_shared *sh = priv->sh;
 304
 305         if (sh->dv_refcnt > 1) {
 306                 int ret;
 307
 308                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 309                 MLX5_ASSERT(!ret);
 310                 (void)ret;
 311         }
 312 }
 313
 314 /* Update VLAN's VID/PCP based on input rte_flow_action.
 315  *
 316  * @param[in] action
 317  *   Pointer to struct rte_flow_action.
 318  * @param[out] vlan
 319  *   Pointer to struct rte_vlan_hdr.
 320  */
 321 static void
 322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 323                          struct rte_vlan_hdr *vlan)
 324 {
 325         uint16_t vlan_tci;
 326         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 327                 vlan_tci =
 328                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 329                                                action->conf)->vlan_pcp;
 330                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 331                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 332                 vlan->vlan_tci |= vlan_tci;
 333         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 334                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 335                 vlan->vlan_tci |= rte_be_to_cpu_16
 336                     (((const struct rte_flow_action_of_set_vlan_vid *)
 337                                              action->conf)->vlan_vid);
 338         }
 339 }
 340
 341 /**
 342  * Fetch 1, 2, 3 or 4 byte field from the byte array
 343  * and return as unsigned integer in host-endian format.
 344  *
 345  * @param[in] data
 346  *   Pointer to data array.
 347  * @param[in] size
 348  *   Size of field to extract.
 349  *
 350  * @return
 351  *   converted field in host endian format.
 352  */
 353 static inline uint32_t
 354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 355 {
 356         uint32_t ret;
 357
 358         switch (size) {
 359         case 1:
 360                 ret = *data;
 361                 break;
 362         case 2:
 363                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 364                 break;
 365         case 3:
 366                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 367                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 368                 break;
 369         case 4:
 370                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 371                 break;
 372         default:
 373                 MLX5_ASSERT(false);
 374                 ret = 0;
 375                 break;
 376         }
 377         return ret;
 378 }
 379
 380 /**
 381  * Convert modify-header action to DV specification.
 382  *
 383  * Data length of each action is determined by provided field description
 384  * and the item mask. Data bit offset and width of each action is determined
 385  * by provided item mask.
 386  *
 387  * @param[in] item
 388  *   Pointer to item specification.
 389  * @param[in] field
 390  *   Pointer to field modification information.
 391  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 393  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 394  * @param[in] dcopy
 395  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 396  *   Negative offset value sets the same offset as source offset.
 397  *   size field is ignored, value is taken from source field.
 398  * @param[in,out] resource
 399  *   Pointer to the modify-header resource.
 400  * @param[in] type
 401  *   Type of modification.
 402  * @param[out] error
 403  *   Pointer to the error structure.
 404  *
 405  * @return
 406  *   0 on success, a negative errno value otherwise and rte_errno is set.
 407  */
 408 static int
 409 flow_dv_convert_modify_action(struct rte_flow_item *item,
 410                               struct field_modify_info *field,
 411                               struct field_modify_info *dcopy,
 412                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 413                               uint32_t type, struct rte_flow_error *error)
 414 {
 415         uint32_t i = resource->actions_num;
 416         struct mlx5_modification_cmd *actions = resource->actions;
 417
 418         /*
 419          * The item and mask are provided in big-endian format.
 420          * The fields should be presented as in big-endian format either.
 421          * Mask must be always present, it defines the actual field width.
 422          */
 423         MLX5_ASSERT(item->mask);
 424         MLX5_ASSERT(field->size);
 425         do {
 426                 unsigned int size_b;
 427                 unsigned int off_b;
 428                 uint32_t mask;
 429                 uint32_t data;
 430
 431                 if (i >= MLX5_MAX_MODIFY_NUM)
 432                         return rte_flow_error_set(error, EINVAL,
 433                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 434                                  "too many items to modify");
 435                 /* Fetch variable byte size mask from the array. */
 436                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 437                                            field->offset, field->size);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /**
1643  * Validate VLAN item.
1644  *
1645  * @param[in] item
1646  *   Item specification.
1647  * @param[in] item_flags
1648  *   Bit-fields that holds the items detected until now.
1649  * @param[in] dev
1650  *   Ethernet device flow is being created on.
1651  * @param[out] error
1652  *   Pointer to error structure.
1653  *
1654  * @return
1655  *   0 on success, a negative errno value otherwise and rte_errno is set.
1656  */
1657 static int
1658 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1659                            uint64_t item_flags,
1660                            struct rte_eth_dev *dev,
1661                            struct rte_flow_error *error)
1662 {
1663         const struct rte_flow_item_vlan *mask = item->mask;
1664         const struct rte_flow_item_vlan nic_mask = {
1665                 .tci = RTE_BE16(UINT16_MAX),
1666                 .inner_type = RTE_BE16(UINT16_MAX),
1667         };
1668         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1669         int ret;
1670         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1671                                         MLX5_FLOW_LAYER_INNER_L4) :
1672                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1673                                         MLX5_FLOW_LAYER_OUTER_L4);
1674         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1675                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1676
1677         if (item_flags & vlanm)
1678                 return rte_flow_error_set(error, EINVAL,
1679                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1680                                           "multiple VLAN layers not supported");
1681         else if ((item_flags & l34m) != 0)
1682                 return rte_flow_error_set(error, EINVAL,
1683                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1684                                           "VLAN cannot follow L3/L4 layer");
1685         if (!mask)
1686                 mask = &rte_flow_item_vlan_mask;
1687         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1688                                         (const uint8_t *)&nic_mask,
1689                                         sizeof(struct rte_flow_item_vlan),
1690                                         error);
1691         if (ret)
1692                 return ret;
1693         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1694                 struct mlx5_priv *priv = dev->data->dev_private;
1695
1696                 if (priv->vmwa_context) {
1697                         /*
1698                          * Non-NULL context means we have a virtual machine
1699                          * and SR-IOV enabled, we have to create VLAN interface
1700                          * to make hypervisor to setup E-Switch vport
1701                          * context correctly. We avoid creating the multiple
1702                          * VLAN interfaces, so we cannot support VLAN tag mask.
1703                          */
1704                         return rte_flow_error_set(error, EINVAL,
1705                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1706                                                   item,
1707                                                   "VLAN tag mask is not"
1708                                                   " supported in virtual"
1709                                                   " environment");
1710                 }
1711         }
1712         return 0;
1713 }
1714
1715 /**
1716  * Validate GTP item.
1717  *
1718  * @param[in] dev
1719  *   Pointer to the rte_eth_dev structure.
1720  * @param[in] item
1721  *   Item specification.
1722  * @param[in] item_flags
1723  *   Bit-fields that holds the items detected until now.
1724  * @param[out] error
1725  *   Pointer to error structure.
1726  *
1727  * @return
1728  *   0 on success, a negative errno value otherwise and rte_errno is set.
1729  */
1730 static int
1731 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1732                           const struct rte_flow_item *item,
1733                           uint64_t item_flags,
1734                           struct rte_flow_error *error)
1735 {
1736         struct mlx5_priv *priv = dev->data->dev_private;
1737         const struct rte_flow_item_gtp *mask = item->mask;
1738         const struct rte_flow_item_gtp nic_mask = {
1739                 .msg_type = 0xff,
1740                 .teid = RTE_BE32(0xffffffff),
1741         };
1742
1743         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1744                 return rte_flow_error_set(error, ENOTSUP,
1745                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1746                                           "GTP support is not enabled");
1747         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1748                 return rte_flow_error_set(error, ENOTSUP,
1749                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1750                                           "multiple tunnel layers not"
1751                                           " supported");
1752         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1753                 return rte_flow_error_set(error, EINVAL,
1754                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1755                                           "no outer UDP layer found");
1756         if (!mask)
1757                 mask = &rte_flow_item_gtp_mask;
1758         return mlx5_flow_item_acceptable
1759                 (item, (const uint8_t *)mask,
1760                  (const uint8_t *)&nic_mask,
1761                  sizeof(struct rte_flow_item_gtp),
1762                  error);
1763 }
1764
1765 /**
1766  * Validate the pop VLAN action.
1767  *
1768  * @param[in] dev
1769  *   Pointer to the rte_eth_dev structure.
1770  * @param[in] action_flags
1771  *   Holds the actions detected until now.
1772  * @param[in] action
1773  *   Pointer to the pop vlan action.
1774  * @param[in] item_flags
1775  *   The items found in this flow rule.
1776  * @param[in] attr
1777  *   Pointer to flow attributes.
1778  * @param[out] error
1779  *   Pointer to error structure.
1780  *
1781  * @return
1782  *   0 on success, a negative errno value otherwise and rte_errno is set.
1783  */
1784 static int
1785 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1786                                  uint64_t action_flags,
1787                                  const struct rte_flow_action *action,
1788                                  uint64_t item_flags,
1789                                  const struct rte_flow_attr *attr,
1790                                  struct rte_flow_error *error)
1791 {
1792         const struct mlx5_priv *priv = dev->data->dev_private;
1793
1794         (void)action;
1795         (void)attr;
1796         if (!priv->sh->pop_vlan_action)
1797                 return rte_flow_error_set(error, ENOTSUP,
1798                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1799                                           NULL,
1800                                           "pop vlan action is not supported");
1801         if (attr->egress)
1802                 return rte_flow_error_set(error, ENOTSUP,
1803                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1804                                           NULL,
1805                                           "pop vlan action not supported for "
1806                                           "egress");
1807         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1808                 return rte_flow_error_set(error, ENOTSUP,
1809                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1810                                           "no support for multiple VLAN "
1811                                           "actions");
1812         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1813                 return rte_flow_error_set(error, ENOTSUP,
1814                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1815                                           NULL,
1816                                           "cannot pop vlan without a "
1817                                           "match on (outer) vlan in the flow");
1818         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1819                 return rte_flow_error_set(error, EINVAL,
1820                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1821                                           "wrong action order, port_id should "
1822                                           "be after pop VLAN action");
1823         if (!attr->transfer && priv->representor)
1824                 return rte_flow_error_set(error, ENOTSUP,
1825                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1826                                           "pop vlan action for VF representor "
1827                                           "not supported on NIC table");
1828         return 0;
1829 }
1830
1831 /**
1832  * Get VLAN default info from vlan match info.
1833  *
1834  * @param[in] items
1835  *   the list of item specifications.
1836  * @param[out] vlan
1837  *   pointer VLAN info to fill to.
1838  *
1839  * @return
1840  *   0 on success, a negative errno value otherwise and rte_errno is set.
1841  */
1842 static void
1843 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1844                                   struct rte_vlan_hdr *vlan)
1845 {
1846         const struct rte_flow_item_vlan nic_mask = {
1847                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1848                                 MLX5DV_FLOW_VLAN_VID_MASK),
1849                 .inner_type = RTE_BE16(0xffff),
1850         };
1851
1852         if (items == NULL)
1853                 return;
1854         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1855                 int type = items->type;
1856
1857                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1858                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1859                         break;
1860         }
1861         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1862                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1863                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1864
1865                 if (!vlan_m)
1866                         vlan_m = &nic_mask;
1867                 /* Only full match values are accepted */
1868                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1869                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1870                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1871                         vlan->vlan_tci |=
1872                                 rte_be_to_cpu_16(vlan_v->tci &
1873                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1874                 }
1875                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1876                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1877                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1878                         vlan->vlan_tci |=
1879                                 rte_be_to_cpu_16(vlan_v->tci &
1880                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1881                 }
1882                 if (vlan_m->inner_type == nic_mask.inner_type)
1883                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1884                                                            vlan_m->inner_type);
1885         }
1886 }
1887
1888 /**
1889  * Validate the push VLAN action.
1890  *
1891  * @param[in] dev
1892  *   Pointer to the rte_eth_dev structure.
1893  * @param[in] action_flags
1894  *   Holds the actions detected until now.
1895  * @param[in] item_flags
1896  *   The items found in this flow rule.
1897  * @param[in] action
1898  *   Pointer to the action structure.
1899  * @param[in] attr
1900  *   Pointer to flow attributes
1901  * @param[out] error
1902  *   Pointer to error structure.
1903  *
1904  * @return
1905  *   0 on success, a negative errno value otherwise and rte_errno is set.
1906  */
1907 static int
1908 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1909                                   uint64_t action_flags,
1910                                   const struct rte_flow_item_vlan *vlan_m,
1911                                   const struct rte_flow_action *action,
1912                                   const struct rte_flow_attr *attr,
1913                                   struct rte_flow_error *error)
1914 {
1915         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1916         const struct mlx5_priv *priv = dev->data->dev_private;
1917
1918         if (!attr->transfer && attr->ingress)
1919                 return rte_flow_error_set(error, ENOTSUP,
1920                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1921                                           NULL,
1922                                           "push VLAN action not supported for "
1923                                           "ingress");
1924         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1925             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1926                 return rte_flow_error_set(error, EINVAL,
1927                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1928                                           "invalid vlan ethertype");
1929         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1930                 return rte_flow_error_set(error, ENOTSUP,
1931                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1932                                           "no support for multiple VLAN "
1933                                           "actions");
1934         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1935                 return rte_flow_error_set(error, EINVAL,
1936                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1937                                           "wrong action order, port_id should "
1938                                           "be after push VLAN");
1939         if (!attr->transfer && priv->representor)
1940                 return rte_flow_error_set(error, ENOTSUP,
1941                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1942                                           "push vlan action for VF representor "
1943                                           "not supported on NIC table");
1944         if (vlan_m &&
1945             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1946             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1947                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1948             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1949             !(mlx5_flow_find_action
1950                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1951                 return rte_flow_error_set(error, EINVAL,
1952                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1953                                           "not full match mask on VLAN PCP and "
1954                                           "there is no of_set_vlan_pcp action, "
1955                                           "push VLAN action cannot figure out "
1956                                           "PCP value");
1957         if (vlan_m &&
1958             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1959             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1960                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1961             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1962             !(mlx5_flow_find_action
1963                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1964                 return rte_flow_error_set(error, EINVAL,
1965                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1966                                           "not full match mask on VLAN VID and "
1967                                           "there is no of_set_vlan_vid action, "
1968                                           "push VLAN action cannot figure out "
1969                                           "VID value");
1970         (void)attr;
1971         return 0;
1972 }
1973
1974 /**
1975  * Validate the set VLAN PCP.
1976  *
1977  * @param[in] action_flags
1978  *   Holds the actions detected until now.
1979  * @param[in] actions
1980  *   Pointer to the list of actions remaining in the flow rule.
1981  * @param[out] error
1982  *   Pointer to error structure.
1983  *
1984  * @return
1985  *   0 on success, a negative errno value otherwise and rte_errno is set.
1986  */
1987 static int
1988 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1989                                      const struct rte_flow_action actions[],
1990                                      struct rte_flow_error *error)
1991 {
1992         const struct rte_flow_action *action = actions;
1993         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1994
1995         if (conf->vlan_pcp > 7)
1996                 return rte_flow_error_set(error, EINVAL,
1997                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1998                                           "VLAN PCP value is too big");
1999         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2000                 return rte_flow_error_set(error, ENOTSUP,
2001                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2002                                           "set VLAN PCP action must follow "
2003                                           "the push VLAN action");
2004         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2005                 return rte_flow_error_set(error, ENOTSUP,
2006                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2007                                           "Multiple VLAN PCP modification are "
2008                                           "not supported");
2009         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2010                 return rte_flow_error_set(error, EINVAL,
2011                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2012                                           "wrong action order, port_id should "
2013                                           "be after set VLAN PCP");
2014         return 0;
2015 }
2016
2017 /**
2018  * Validate the set VLAN VID.
2019  *
2020  * @param[in] item_flags
2021  *   Holds the items detected in this rule.
2022  * @param[in] action_flags
2023  *   Holds the actions detected until now.
2024  * @param[in] actions
2025  *   Pointer to the list of actions remaining in the flow rule.
2026  * @param[out] error
2027  *   Pointer to error structure.
2028  *
2029  * @return
2030  *   0 on success, a negative errno value otherwise and rte_errno is set.
2031  */
2032 static int
2033 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2034                                      uint64_t action_flags,
2035                                      const struct rte_flow_action actions[],
2036                                      struct rte_flow_error *error)
2037 {
2038         const struct rte_flow_action *action = actions;
2039         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2040
2041         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2042                 return rte_flow_error_set(error, EINVAL,
2043                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2044                                           "VLAN VID value is too big");
2045         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2046             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2047                 return rte_flow_error_set(error, ENOTSUP,
2048                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2049                                           "set VLAN VID action must follow push"
2050                                           " VLAN action or match on VLAN item");
2051         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2052                 return rte_flow_error_set(error, ENOTSUP,
2053                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2054                                           "Multiple VLAN VID modifications are "
2055                                           "not supported");
2056         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2057                 return rte_flow_error_set(error, EINVAL,
2058                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2059                                           "wrong action order, port_id should "
2060                                           "be after set VLAN VID");
2061         return 0;
2062 }
2063
2064 /*
2065  * Validate the FLAG action.
2066  *
2067  * @param[in] dev
2068  *   Pointer to the rte_eth_dev structure.
2069  * @param[in] action_flags
2070  *   Holds the actions detected until now.
2071  * @param[in] attr
2072  *   Pointer to flow attributes
2073  * @param[out] error
2074  *   Pointer to error structure.
2075  *
2076  * @return
2077  *   0 on success, a negative errno value otherwise and rte_errno is set.
2078  */
2079 static int
2080 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2081                              uint64_t action_flags,
2082                              const struct rte_flow_attr *attr,
2083                              struct rte_flow_error *error)
2084 {
2085         struct mlx5_priv *priv = dev->data->dev_private;
2086         struct mlx5_dev_config *config = &priv->config;
2087         int ret;
2088
2089         /* Fall back if no extended metadata register support. */
2090         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2091                 return mlx5_flow_validate_action_flag(action_flags, attr,
2092                                                       error);
2093         /* Extensive metadata mode requires registers. */
2094         if (!mlx5_flow_ext_mreg_supported(dev))
2095                 return rte_flow_error_set(error, ENOTSUP,
2096                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2097                                           "no metadata registers "
2098                                           "to support flag action");
2099         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2100                 return rte_flow_error_set(error, ENOTSUP,
2101                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2102                                           "extended metadata register"
2103                                           " isn't available");
2104         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2105         if (ret < 0)
2106                 return ret;
2107         MLX5_ASSERT(ret > 0);
2108         if (action_flags & MLX5_FLOW_ACTION_MARK)
2109                 return rte_flow_error_set(error, EINVAL,
2110                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2111                                           "can't mark and flag in same flow");
2112         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2113                 return rte_flow_error_set(error, EINVAL,
2114                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2115                                           "can't have 2 flag"
2116                                           " actions in same flow");
2117         return 0;
2118 }
2119
2120 /**
2121  * Validate MARK action.
2122  *
2123  * @param[in] dev
2124  *   Pointer to the rte_eth_dev structure.
2125  * @param[in] action
2126  *   Pointer to action.
2127  * @param[in] action_flags
2128  *   Holds the actions detected until now.
2129  * @param[in] attr
2130  *   Pointer to flow attributes
2131  * @param[out] error
2132  *   Pointer to error structure.
2133  *
2134  * @return
2135  *   0 on success, a negative errno value otherwise and rte_errno is set.
2136  */
2137 static int
2138 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2139                              const struct rte_flow_action *action,
2140                              uint64_t action_flags,
2141                              const struct rte_flow_attr *attr,
2142                              struct rte_flow_error *error)
2143 {
2144         struct mlx5_priv *priv = dev->data->dev_private;
2145         struct mlx5_dev_config *config = &priv->config;
2146         const struct rte_flow_action_mark *mark = action->conf;
2147         int ret;
2148
2149         /* Fall back if no extended metadata register support. */
2150         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2151                 return mlx5_flow_validate_action_mark(action, action_flags,
2152                                                       attr, error);
2153         /* Extensive metadata mode requires registers. */
2154         if (!mlx5_flow_ext_mreg_supported(dev))
2155                 return rte_flow_error_set(error, ENOTSUP,
2156                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2157                                           "no metadata registers "
2158                                           "to support mark action");
2159         if (!priv->sh->dv_mark_mask)
2160                 return rte_flow_error_set(error, ENOTSUP,
2161                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2162                                           "extended metadata register"
2163                                           " isn't available");
2164         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2165         if (ret < 0)
2166                 return ret;
2167         MLX5_ASSERT(ret > 0);
2168         if (!mark)
2169                 return rte_flow_error_set(error, EINVAL,
2170                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2171                                           "configuration cannot be null");
2172         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2173                 return rte_flow_error_set(error, EINVAL,
2174                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2175                                           &mark->id,
2176                                           "mark id exceeds the limit");
2177         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2178                 return rte_flow_error_set(error, EINVAL,
2179                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2180                                           "can't flag and mark in same flow");
2181         if (action_flags & MLX5_FLOW_ACTION_MARK)
2182                 return rte_flow_error_set(error, EINVAL,
2183                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2184                                           "can't have 2 mark actions in same"
2185                                           " flow");
2186         return 0;
2187 }
2188
2189 /**
2190  * Validate SET_META action.
2191  *
2192  * @param[in] dev
2193  *   Pointer to the rte_eth_dev structure.
2194  * @param[in] action
2195  *   Pointer to the action structure.
2196  * @param[in] action_flags
2197  *   Holds the actions detected until now.
2198  * @param[in] attr
2199  *   Pointer to flow attributes
2200  * @param[out] error
2201  *   Pointer to error structure.
2202  *
2203  * @return
2204  *   0 on success, a negative errno value otherwise and rte_errno is set.
2205  */
2206 static int
2207 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2208                                  const struct rte_flow_action *action,
2209                                  uint64_t action_flags __rte_unused,
2210                                  const struct rte_flow_attr *attr,
2211                                  struct rte_flow_error *error)
2212 {
2213         const struct rte_flow_action_set_meta *conf;
2214         uint32_t nic_mask = UINT32_MAX;
2215         int reg;
2216
2217         if (!mlx5_flow_ext_mreg_supported(dev))
2218                 return rte_flow_error_set(error, ENOTSUP,
2219                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2220                                           "extended metadata register"
2221                                           " isn't supported");
2222         reg = flow_dv_get_metadata_reg(dev, attr, error);
2223         if (reg < 0)
2224                 return reg;
2225         if (reg != REG_A && reg != REG_B) {
2226                 struct mlx5_priv *priv = dev->data->dev_private;
2227
2228                 nic_mask = priv->sh->dv_meta_mask;
2229         }
2230         if (!(action->conf))
2231                 return rte_flow_error_set(error, EINVAL,
2232                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2233                                           "configuration cannot be null");
2234         conf = (const struct rte_flow_action_set_meta *)action->conf;
2235         if (!conf->mask)
2236                 return rte_flow_error_set(error, EINVAL,
2237                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2238                                           "zero mask doesn't have any effect");
2239         if (conf->mask & ~nic_mask)
2240                 return rte_flow_error_set(error, EINVAL,
2241                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2242                                           "meta data must be within reg C0");
2243         return 0;
2244 }
2245
2246 /**
2247  * Validate SET_TAG action.
2248  *
2249  * @param[in] dev
2250  *   Pointer to the rte_eth_dev structure.
2251  * @param[in] action
2252  *   Pointer to the action structure.
2253  * @param[in] action_flags
2254  *   Holds the actions detected until now.
2255  * @param[in] attr
2256  *   Pointer to flow attributes
2257  * @param[out] error
2258  *   Pointer to error structure.
2259  *
2260  * @return
2261  *   0 on success, a negative errno value otherwise and rte_errno is set.
2262  */
2263 static int
2264 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2265                                 const struct rte_flow_action *action,
2266                                 uint64_t action_flags,
2267                                 const struct rte_flow_attr *attr,
2268                                 struct rte_flow_error *error)
2269 {
2270         const struct rte_flow_action_set_tag *conf;
2271         const uint64_t terminal_action_flags =
2272                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2273                 MLX5_FLOW_ACTION_RSS;
2274         int ret;
2275
2276         if (!mlx5_flow_ext_mreg_supported(dev))
2277                 return rte_flow_error_set(error, ENOTSUP,
2278                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2279                                           "extensive metadata register"
2280                                           " isn't supported");
2281         if (!(action->conf))
2282                 return rte_flow_error_set(error, EINVAL,
2283                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2284                                           "configuration cannot be null");
2285         conf = (const struct rte_flow_action_set_tag *)action->conf;
2286         if (!conf->mask)
2287                 return rte_flow_error_set(error, EINVAL,
2288                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2289                                           "zero mask doesn't have any effect");
2290         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2291         if (ret < 0)
2292                 return ret;
2293         if (!attr->transfer && attr->ingress &&
2294             (action_flags & terminal_action_flags))
2295                 return rte_flow_error_set(error, EINVAL,
2296                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2297                                           "set_tag has no effect"
2298                                           " with terminal actions");
2299         return 0;
2300 }
2301
2302 /**
2303  * Validate count action.
2304  *
2305  * @param[in] dev
2306  *   Pointer to rte_eth_dev structure.
2307  * @param[out] error
2308  *   Pointer to error structure.
2309  *
2310  * @return
2311  *   0 on success, a negative errno value otherwise and rte_errno is set.
2312  */
2313 static int
2314 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2315                               struct rte_flow_error *error)
2316 {
2317         struct mlx5_priv *priv = dev->data->dev_private;
2318
2319         if (!priv->config.devx)
2320                 goto notsup_err;
2321 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2322         return 0;
2323 #endif
2324 notsup_err:
2325         return rte_flow_error_set
2326                       (error, ENOTSUP,
2327                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2328                        NULL,
2329                        "count action not supported");
2330 }
2331
2332 /**
2333  * Validate the L2 encap action.
2334  *
2335  * @param[in] dev
2336  *   Pointer to the rte_eth_dev structure.
2337  * @param[in] action_flags
2338  *   Holds the actions detected until now.
2339  * @param[in] action
2340  *   Pointer to the action structure.
2341  * @param[in] attr
2342  *   Pointer to flow attributes.
2343  * @param[out] error
2344  *   Pointer to error structure.
2345  *
2346  * @return
2347  *   0 on success, a negative errno value otherwise and rte_errno is set.
2348  */
2349 static int
2350 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2351                                  uint64_t action_flags,
2352                                  const struct rte_flow_action *action,
2353                                  const struct rte_flow_attr *attr,
2354                                  struct rte_flow_error *error)
2355 {
2356         const struct mlx5_priv *priv = dev->data->dev_private;
2357
2358         if (!(action->conf))
2359                 return rte_flow_error_set(error, EINVAL,
2360                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2361                                           "configuration cannot be null");
2362         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2363                 return rte_flow_error_set(error, EINVAL,
2364                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2365                                           "can only have a single encap action "
2366                                           "in a flow");
2367         if (!attr->transfer && priv->representor)
2368                 return rte_flow_error_set(error, ENOTSUP,
2369                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2370                                           "encap action for VF representor "
2371                                           "not supported on NIC table");
2372         return 0;
2373 }
2374
2375 /**
2376  * Validate a decap action.
2377  *
2378  * @param[in] dev
2379  *   Pointer to the rte_eth_dev structure.
2380  * @param[in] action_flags
2381  *   Holds the actions detected until now.
2382  * @param[in] attr
2383  *   Pointer to flow attributes
2384  * @param[out] error
2385  *   Pointer to error structure.
2386  *
2387  * @return
2388  *   0 on success, a negative errno value otherwise and rte_errno is set.
2389  */
2390 static int
2391 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2392                               uint64_t action_flags,
2393                               const struct rte_flow_attr *attr,
2394                               struct rte_flow_error *error)
2395 {
2396         const struct mlx5_priv *priv = dev->data->dev_private;
2397
2398         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2399                 return rte_flow_error_set(error, ENOTSUP,
2400                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2401                                           action_flags &
2402                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2403                                           "have a single decap action" : "decap "
2404                                           "after encap is not supported");
2405         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2406                 return rte_flow_error_set(error, EINVAL,
2407                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2408                                           "can't have decap action after"
2409                                           " modify action");
2410         if (attr->egress)
2411                 return rte_flow_error_set(error, ENOTSUP,
2412                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2413                                           NULL,
2414                                           "decap action not supported for "
2415                                           "egress");
2416         if (!attr->transfer && priv->representor)
2417                 return rte_flow_error_set(error, ENOTSUP,
2418                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2419                                           "decap action for VF representor "
2420                                           "not supported on NIC table");
2421         return 0;
2422 }
2423
2424 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2425
2426 /**
2427  * Validate the raw encap and decap actions.
2428  *
2429  * @param[in] dev
2430  *   Pointer to the rte_eth_dev structure.
2431  * @param[in] decap
2432  *   Pointer to the decap action.
2433  * @param[in] encap
2434  *   Pointer to the encap action.
2435  * @param[in] attr
2436  *   Pointer to flow attributes
2437  * @param[in/out] action_flags
2438  *   Holds the actions detected until now.
2439  * @param[out] actions_n
2440  *   pointer to the number of actions counter.
2441  * @param[out] error
2442  *   Pointer to error structure.
2443  *
2444  * @return
2445  *   0 on success, a negative errno value otherwise and rte_errno is set.
2446  */
2447 static int
2448 flow_dv_validate_action_raw_encap_decap
2449         (struct rte_eth_dev *dev,
2450          const struct rte_flow_action_raw_decap *decap,
2451          const struct rte_flow_action_raw_encap *encap,
2452          const struct rte_flow_attr *attr, uint64_t *action_flags,
2453          int *actions_n, struct rte_flow_error *error)
2454 {
2455         const struct mlx5_priv *priv = dev->data->dev_private;
2456         int ret;
2457
2458         if (encap && (!encap->size || !encap->data))
2459                 return rte_flow_error_set(error, EINVAL,
2460                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2461                                           "raw encap data cannot be empty");
2462         if (decap && encap) {
2463                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2464                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2465                         /* L3 encap. */
2466                         decap = NULL;
2467                 else if (encap->size <=
2468                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2469                            decap->size >
2470                            MLX5_ENCAPSULATION_DECISION_SIZE)
2471                         /* L3 decap. */
2472                         encap = NULL;
2473                 else if (encap->size >
2474                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2475                            decap->size >
2476                            MLX5_ENCAPSULATION_DECISION_SIZE)
2477                         /* 2 L2 actions: encap and decap. */
2478                         ;
2479                 else
2480                         return rte_flow_error_set(error,
2481                                 ENOTSUP,
2482                                 RTE_FLOW_ERROR_TYPE_ACTION,
2483                                 NULL, "unsupported too small "
2484                                 "raw decap and too small raw "
2485                                 "encap combination");
2486         }
2487         if (decap) {
2488                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2489                                                     error);
2490                 if (ret < 0)
2491                         return ret;
2492                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2493                 ++(*actions_n);
2494         }
2495         if (encap) {
2496                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2497                         return rte_flow_error_set(error, ENOTSUP,
2498                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2499                                                   NULL,
2500                                                   "small raw encap size");
2501                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2502                         return rte_flow_error_set(error, EINVAL,
2503                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2504                                                   NULL,
2505                                                   "more than one encap action");
2506                 if (!attr->transfer && priv->representor)
2507                         return rte_flow_error_set
2508                                         (error, ENOTSUP,
2509                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2510                                          "encap action for VF representor "
2511                                          "not supported on NIC table");
2512                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2513                 ++(*actions_n);
2514         }
2515         return 0;
2516 }
2517
2518 /**
2519  * Find existing encap/decap resource or create and register a new one.
2520  *
2521  * @param[in, out] dev
2522  *   Pointer to rte_eth_dev structure.
2523  * @param[in, out] resource
2524  *   Pointer to encap/decap resource.
2525  * @parm[in, out] dev_flow
2526  *   Pointer to the dev_flow.
2527  * @param[out] error
2528  *   pointer to error structure.
2529  *
2530  * @return
2531  *   0 on success otherwise -errno and errno is set.
2532  */
2533 static int
2534 flow_dv_encap_decap_resource_register
2535                         (struct rte_eth_dev *dev,
2536                          struct mlx5_flow_dv_encap_decap_resource *resource,
2537                          struct mlx5_flow *dev_flow,
2538                          struct rte_flow_error *error)
2539 {
2540         struct mlx5_priv *priv = dev->data->dev_private;
2541         struct mlx5_ibv_shared *sh = priv->sh;
2542         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2543         struct mlx5dv_dr_domain *domain;
2544         uint32_t idx = 0;
2545
2546         resource->flags = dev_flow->dv.group ? 0 : 1;
2547         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2548                 domain = sh->fdb_domain;
2549         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2550                 domain = sh->rx_domain;
2551         else
2552                 domain = sh->tx_domain;
2553         /* Lookup a matching resource from cache. */
2554         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2555                       cache_resource, next) {
2556                 if (resource->reformat_type == cache_resource->reformat_type &&
2557                     resource->ft_type == cache_resource->ft_type &&
2558                     resource->flags == cache_resource->flags &&
2559                     resource->size == cache_resource->size &&
2560                     !memcmp((const void *)resource->buf,
2561                             (const void *)cache_resource->buf,
2562                             resource->size)) {
2563                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2564                                 (void *)cache_resource,
2565                                 rte_atomic32_read(&cache_resource->refcnt));
2566                         rte_atomic32_inc(&cache_resource->refcnt);
2567                         dev_flow->handle->dvh.rix_encap_decap = idx;
2568                         dev_flow->dv.encap_decap = cache_resource;
2569                         return 0;
2570                 }
2571         }
2572         /* Register new encap/decap resource. */
2573         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2574                                        &dev_flow->handle->dvh.rix_encap_decap);
2575         if (!cache_resource)
2576                 return rte_flow_error_set(error, ENOMEM,
2577                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2578                                           "cannot allocate resource memory");
2579         *cache_resource = *resource;
2580         cache_resource->verbs_action =
2581                 mlx5_glue->dv_create_flow_action_packet_reformat
2582                         (sh->ctx, cache_resource->reformat_type,
2583                          cache_resource->ft_type, domain, cache_resource->flags,
2584                          cache_resource->size,
2585                          (cache_resource->size ? cache_resource->buf : NULL));
2586         if (!cache_resource->verbs_action) {
2587                 rte_free(cache_resource);
2588                 return rte_flow_error_set(error, ENOMEM,
2589                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2590                                           NULL, "cannot create action");
2591         }
2592         rte_atomic32_init(&cache_resource->refcnt);
2593         rte_atomic32_inc(&cache_resource->refcnt);
2594         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2595                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2596                      next);
2597         dev_flow->dv.encap_decap = cache_resource;
2598         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2599                 (void *)cache_resource,
2600                 rte_atomic32_read(&cache_resource->refcnt));
2601         return 0;
2602 }
2603
2604 /**
2605  * Find existing table jump resource or create and register a new one.
2606  *
2607  * @param[in, out] dev
2608  *   Pointer to rte_eth_dev structure.
2609  * @param[in, out] tbl
2610  *   Pointer to flow table resource.
2611  * @parm[in, out] dev_flow
2612  *   Pointer to the dev_flow.
2613  * @param[out] error
2614  *   pointer to error structure.
2615  *
2616  * @return
2617  *   0 on success otherwise -errno and errno is set.
2618  */
2619 static int
2620 flow_dv_jump_tbl_resource_register
2621                         (struct rte_eth_dev *dev __rte_unused,
2622                          struct mlx5_flow_tbl_resource *tbl,
2623                          struct mlx5_flow *dev_flow,
2624                          struct rte_flow_error *error)
2625 {
2626         struct mlx5_flow_tbl_data_entry *tbl_data =
2627                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2628         int cnt;
2629
2630         MLX5_ASSERT(tbl);
2631         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2632         if (!cnt) {
2633                 tbl_data->jump.action =
2634                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2635                         (tbl->obj);
2636                 if (!tbl_data->jump.action)
2637                         return rte_flow_error_set(error, ENOMEM,
2638                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2639                                         NULL, "cannot create jump action");
2640                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2641                         (void *)&tbl_data->jump, cnt);
2642         } else {
2643                 /* old jump should not make the table ref++. */
2644                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2645                 MLX5_ASSERT(tbl_data->jump.action);
2646                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2647                         (void *)&tbl_data->jump, cnt);
2648         }
2649         rte_atomic32_inc(&tbl_data->jump.refcnt);
2650         dev_flow->handle->rix_jump = tbl_data->idx;
2651         dev_flow->dv.jump = &tbl_data->jump;
2652         return 0;
2653 }
2654
2655 /**
2656  * Find existing table port ID resource or create and register a new one.
2657  *
2658  * @param[in, out] dev
2659  *   Pointer to rte_eth_dev structure.
2660  * @param[in, out] resource
2661  *   Pointer to port ID action resource.
2662  * @parm[in, out] dev_flow
2663  *   Pointer to the dev_flow.
2664  * @param[out] error
2665  *   pointer to error structure.
2666  *
2667  * @return
2668  *   0 on success otherwise -errno and errno is set.
2669  */
2670 static int
2671 flow_dv_port_id_action_resource_register
2672                         (struct rte_eth_dev *dev,
2673                          struct mlx5_flow_dv_port_id_action_resource *resource,
2674                          struct mlx5_flow *dev_flow,
2675                          struct rte_flow_error *error)
2676 {
2677         struct mlx5_priv *priv = dev->data->dev_private;
2678         struct mlx5_ibv_shared *sh = priv->sh;
2679         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2680         uint32_t idx = 0;
2681
2682         /* Lookup a matching resource from cache. */
2683         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2684                       idx, cache_resource, next) {
2685                 if (resource->port_id == cache_resource->port_id) {
2686                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2687                                 "refcnt %d++",
2688                                 (void *)cache_resource,
2689                                 rte_atomic32_read(&cache_resource->refcnt));
2690                         rte_atomic32_inc(&cache_resource->refcnt);
2691                         dev_flow->handle->rix_port_id_action = idx;
2692                         dev_flow->dv.port_id_action = cache_resource;
2693                         return 0;
2694                 }
2695         }
2696         /* Register new port id action resource. */
2697         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2698                                        &dev_flow->handle->rix_port_id_action);
2699         if (!cache_resource)
2700                 return rte_flow_error_set(error, ENOMEM,
2701                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2702                                           "cannot allocate resource memory");
2703         *cache_resource = *resource;
2704         /*
2705          * Depending on rdma_core version the glue routine calls
2706          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2707          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2708          */
2709         cache_resource->action =
2710                 mlx5_glue->dr_create_flow_action_dest_port
2711                         (priv->sh->fdb_domain, resource->port_id);
2712         if (!cache_resource->action) {
2713                 rte_free(cache_resource);
2714                 return rte_flow_error_set(error, ENOMEM,
2715                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2716                                           NULL, "cannot create action");
2717         }
2718         rte_atomic32_init(&cache_resource->refcnt);
2719         rte_atomic32_inc(&cache_resource->refcnt);
2720         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2721                      dev_flow->handle->rix_port_id_action, cache_resource,
2722                      next);
2723         dev_flow->dv.port_id_action = cache_resource;
2724         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2725                 (void *)cache_resource,
2726                 rte_atomic32_read(&cache_resource->refcnt));
2727         return 0;
2728 }
2729
2730 /**
2731  * Find existing push vlan resource or create and register a new one.
2732  *
2733  * @param [in, out] dev
2734  *   Pointer to rte_eth_dev structure.
2735  * @param[in, out] resource
2736  *   Pointer to port ID action resource.
2737  * @parm[in, out] dev_flow
2738  *   Pointer to the dev_flow.
2739  * @param[out] error
2740  *   pointer to error structure.
2741  *
2742  * @return
2743  *   0 on success otherwise -errno and errno is set.
2744  */
2745 static int
2746 flow_dv_push_vlan_action_resource_register
2747                        (struct rte_eth_dev *dev,
2748                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2749                         struct mlx5_flow *dev_flow,
2750                         struct rte_flow_error *error)
2751 {
2752         struct mlx5_priv *priv = dev->data->dev_private;
2753         struct mlx5_ibv_shared *sh = priv->sh;
2754         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2755         struct mlx5dv_dr_domain *domain;
2756         uint32_t idx = 0;
2757
2758         /* Lookup a matching resource from cache. */
2759         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2760                       sh->push_vlan_action_list, idx, cache_resource, next) {
2761                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2762                     resource->ft_type == cache_resource->ft_type) {
2763                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2764                                 "refcnt %d++",
2765                                 (void *)cache_resource,
2766                                 rte_atomic32_read(&cache_resource->refcnt));
2767                         rte_atomic32_inc(&cache_resource->refcnt);
2768                         dev_flow->handle->dvh.rix_push_vlan = idx;
2769                         dev_flow->dv.push_vlan_res = cache_resource;
2770                         return 0;
2771                 }
2772         }
2773         /* Register new push_vlan action resource. */
2774         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2775                                        &dev_flow->handle->dvh.rix_push_vlan);
2776         if (!cache_resource)
2777                 return rte_flow_error_set(error, ENOMEM,
2778                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2779                                           "cannot allocate resource memory");
2780         *cache_resource = *resource;
2781         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2782                 domain = sh->fdb_domain;
2783         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2784                 domain = sh->rx_domain;
2785         else
2786                 domain = sh->tx_domain;
2787         cache_resource->action =
2788                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2789                                                            resource->vlan_tag);
2790         if (!cache_resource->action) {
2791                 rte_free(cache_resource);
2792                 return rte_flow_error_set(error, ENOMEM,
2793                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2794                                           NULL, "cannot create action");
2795         }
2796         rte_atomic32_init(&cache_resource->refcnt);
2797         rte_atomic32_inc(&cache_resource->refcnt);
2798         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2799                      &sh->push_vlan_action_list,
2800                      dev_flow->handle->dvh.rix_push_vlan,
2801                      cache_resource, next);
2802         dev_flow->dv.push_vlan_res = cache_resource;
2803         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2804                 (void *)cache_resource,
2805                 rte_atomic32_read(&cache_resource->refcnt));
2806         return 0;
2807 }
2808 /**
2809  * Get the size of specific rte_flow_item_type
2810  *
2811  * @param[in] item_type
2812  *   Tested rte_flow_item_type.
2813  *
2814  * @return
2815  *   sizeof struct item_type, 0 if void or irrelevant.
2816  */
2817 static size_t
2818 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2819 {
2820         size_t retval;
2821
2822         switch (item_type) {
2823         case RTE_FLOW_ITEM_TYPE_ETH:
2824                 retval = sizeof(struct rte_flow_item_eth);
2825                 break;
2826         case RTE_FLOW_ITEM_TYPE_VLAN:
2827                 retval = sizeof(struct rte_flow_item_vlan);
2828                 break;
2829         case RTE_FLOW_ITEM_TYPE_IPV4:
2830                 retval = sizeof(struct rte_flow_item_ipv4);
2831                 break;
2832         case RTE_FLOW_ITEM_TYPE_IPV6:
2833                 retval = sizeof(struct rte_flow_item_ipv6);
2834                 break;
2835         case RTE_FLOW_ITEM_TYPE_UDP:
2836                 retval = sizeof(struct rte_flow_item_udp);
2837                 break;
2838         case RTE_FLOW_ITEM_TYPE_TCP:
2839                 retval = sizeof(struct rte_flow_item_tcp);
2840                 break;
2841         case RTE_FLOW_ITEM_TYPE_VXLAN:
2842                 retval = sizeof(struct rte_flow_item_vxlan);
2843                 break;
2844         case RTE_FLOW_ITEM_TYPE_GRE:
2845                 retval = sizeof(struct rte_flow_item_gre);
2846                 break;
2847         case RTE_FLOW_ITEM_TYPE_NVGRE:
2848                 retval = sizeof(struct rte_flow_item_nvgre);
2849                 break;
2850         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2851                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2852                 break;
2853         case RTE_FLOW_ITEM_TYPE_MPLS:
2854                 retval = sizeof(struct rte_flow_item_mpls);
2855                 break;
2856         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2857         default:
2858                 retval = 0;
2859                 break;
2860         }
2861         return retval;
2862 }
2863
2864 #define MLX5_ENCAP_IPV4_VERSION         0x40
2865 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2866 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2867 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2868 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2869 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2870 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2871
2872 /**
2873  * Convert the encap action data from list of rte_flow_item to raw buffer
2874  *
2875  * @param[in] items
2876  *   Pointer to rte_flow_item objects list.
2877  * @param[out] buf
2878  *   Pointer to the output buffer.
2879  * @param[out] size
2880  *   Pointer to the output buffer size.
2881  * @param[out] error
2882  *   Pointer to the error structure.
2883  *
2884  * @return
2885  *   0 on success, a negative errno value otherwise and rte_errno is set.
2886  */
2887 static int
2888 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2889                            size_t *size, struct rte_flow_error *error)
2890 {
2891         struct rte_ether_hdr *eth = NULL;
2892         struct rte_vlan_hdr *vlan = NULL;
2893         struct rte_ipv4_hdr *ipv4 = NULL;
2894         struct rte_ipv6_hdr *ipv6 = NULL;
2895         struct rte_udp_hdr *udp = NULL;
2896         struct rte_vxlan_hdr *vxlan = NULL;
2897         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2898         struct rte_gre_hdr *gre = NULL;
2899         size_t len;
2900         size_t temp_size = 0;
2901
2902         if (!items)
2903                 return rte_flow_error_set(error, EINVAL,
2904                                           RTE_FLOW_ERROR_TYPE_ACTION,
2905                                           NULL, "invalid empty data");
2906         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2907                 len = flow_dv_get_item_len(items->type);
2908                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2909                         return rte_flow_error_set(error, EINVAL,
2910                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2911                                                   (void *)items->type,
2912                                                   "items total size is too big"
2913                                                   " for encap action");
2914                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2915                 switch (items->type) {
2916                 case RTE_FLOW_ITEM_TYPE_ETH:
2917                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2918                         break;
2919                 case RTE_FLOW_ITEM_TYPE_VLAN:
2920                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2921                         if (!eth)
2922                                 return rte_flow_error_set(error, EINVAL,
2923                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2924                                                 (void *)items->type,
2925                                                 "eth header not found");
2926                         if (!eth->ether_type)
2927                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2928                         break;
2929                 case RTE_FLOW_ITEM_TYPE_IPV4:
2930                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2931                         if (!vlan && !eth)
2932                                 return rte_flow_error_set(error, EINVAL,
2933                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2934                                                 (void *)items->type,
2935                                                 "neither eth nor vlan"
2936                                                 " header found");
2937                         if (vlan && !vlan->eth_proto)
2938                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2939                         else if (eth && !eth->ether_type)
2940                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2941                         if (!ipv4->version_ihl)
2942                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2943                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2944                         if (!ipv4->time_to_live)
2945                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2946                         break;
2947                 case RTE_FLOW_ITEM_TYPE_IPV6:
2948                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2949                         if (!vlan && !eth)
2950                                 return rte_flow_error_set(error, EINVAL,
2951                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2952                                                 (void *)items->type,
2953                                                 "neither eth nor vlan"
2954                                                 " header found");
2955                         if (vlan && !vlan->eth_proto)
2956                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2957                         else if (eth && !eth->ether_type)
2958                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2959                         if (!ipv6->vtc_flow)
2960                                 ipv6->vtc_flow =
2961                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2962                         if (!ipv6->hop_limits)
2963                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2964                         break;
2965                 case RTE_FLOW_ITEM_TYPE_UDP:
2966                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2967                         if (!ipv4 && !ipv6)
2968                                 return rte_flow_error_set(error, EINVAL,
2969                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2970                                                 (void *)items->type,
2971                                                 "ip header not found");
2972                         if (ipv4 && !ipv4->next_proto_id)
2973                                 ipv4->next_proto_id = IPPROTO_UDP;
2974                         else if (ipv6 && !ipv6->proto)
2975                                 ipv6->proto = IPPROTO_UDP;
2976                         break;
2977                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2978                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2979                         if (!udp)
2980                                 return rte_flow_error_set(error, EINVAL,
2981                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2982                                                 (void *)items->type,
2983                                                 "udp header not found");
2984                         if (!udp->dst_port)
2985                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2986                         if (!vxlan->vx_flags)
2987                                 vxlan->vx_flags =
2988                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2989                         break;
2990                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2991                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2992                         if (!udp)
2993                                 return rte_flow_error_set(error, EINVAL,
2994                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2995                                                 (void *)items->type,
2996                                                 "udp header not found");
2997                         if (!vxlan_gpe->proto)
2998                                 return rte_flow_error_set(error, EINVAL,
2999                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3000                                                 (void *)items->type,
3001                                                 "next protocol not found");
3002                         if (!udp->dst_port)
3003                                 udp->dst_port =
3004                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3005                         if (!vxlan_gpe->vx_flags)
3006                                 vxlan_gpe->vx_flags =
3007                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3008                         break;
3009                 case RTE_FLOW_ITEM_TYPE_GRE:
3010                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3011                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3012                         if (!gre->proto)
3013                                 return rte_flow_error_set(error, EINVAL,
3014                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3015                                                 (void *)items->type,
3016                                                 "next protocol not found");
3017                         if (!ipv4 && !ipv6)
3018                                 return rte_flow_error_set(error, EINVAL,
3019                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3020                                                 (void *)items->type,
3021                                                 "ip header not found");
3022                         if (ipv4 && !ipv4->next_proto_id)
3023                                 ipv4->next_proto_id = IPPROTO_GRE;
3024                         else if (ipv6 && !ipv6->proto)
3025                                 ipv6->proto = IPPROTO_GRE;
3026                         break;
3027                 case RTE_FLOW_ITEM_TYPE_VOID:
3028                         break;
3029                 default:
3030                         return rte_flow_error_set(error, EINVAL,
3031                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3032                                                   (void *)items->type,
3033                                                   "unsupported item type");
3034                         break;
3035                 }
3036                 temp_size += len;
3037         }
3038         *size = temp_size;
3039         return 0;
3040 }
3041
3042 static int
3043 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3044 {
3045         struct rte_ether_hdr *eth = NULL;
3046         struct rte_vlan_hdr *vlan = NULL;
3047         struct rte_ipv6_hdr *ipv6 = NULL;
3048         struct rte_udp_hdr *udp = NULL;
3049         char *next_hdr;
3050         uint16_t proto;
3051
3052         eth = (struct rte_ether_hdr *)data;
3053         next_hdr = (char *)(eth + 1);
3054         proto = RTE_BE16(eth->ether_type);
3055
3056         /* VLAN skipping */
3057         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3058                 vlan = (struct rte_vlan_hdr *)next_hdr;
3059                 proto = RTE_BE16(vlan->eth_proto);
3060                 next_hdr += sizeof(struct rte_vlan_hdr);
3061         }
3062
3063         /* HW calculates IPv4 csum. no need to proceed */
3064         if (proto == RTE_ETHER_TYPE_IPV4)
3065                 return 0;
3066
3067         /* non IPv4/IPv6 header. not supported */
3068         if (proto != RTE_ETHER_TYPE_IPV6) {
3069                 return rte_flow_error_set(error, ENOTSUP,
3070                                           RTE_FLOW_ERROR_TYPE_ACTION,
3071                                           NULL, "Cannot offload non IPv4/IPv6");
3072         }
3073
3074         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3075
3076         /* ignore non UDP */
3077         if (ipv6->proto != IPPROTO_UDP)
3078                 return 0;
3079
3080         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3081         udp->dgram_cksum = 0;
3082
3083         return 0;
3084 }
3085
3086 /**
3087  * Convert L2 encap action to DV specification.
3088  *
3089  * @param[in] dev
3090  *   Pointer to rte_eth_dev structure.
3091  * @param[in] action
3092  *   Pointer to action structure.
3093  * @param[in, out] dev_flow
3094  *   Pointer to the mlx5_flow.
3095  * @param[in] transfer
3096  *   Mark if the flow is E-Switch flow.
3097  * @param[out] error
3098  *   Pointer to the error structure.
3099  *
3100  * @return
3101  *   0 on success, a negative errno value otherwise and rte_errno is set.
3102  */
3103 static int
3104 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3105                                const struct rte_flow_action *action,
3106                                struct mlx5_flow *dev_flow,
3107                                uint8_t transfer,
3108                                struct rte_flow_error *error)
3109 {
3110         const struct rte_flow_item *encap_data;
3111         const struct rte_flow_action_raw_encap *raw_encap_data;
3112         struct mlx5_flow_dv_encap_decap_resource res = {
3113                 .reformat_type =
3114                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3115                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3116                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3117         };
3118
3119         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3120                 raw_encap_data =
3121                         (const struct rte_flow_action_raw_encap *)action->conf;
3122                 res.size = raw_encap_data->size;
3123                 memcpy(res.buf, raw_encap_data->data, res.size);
3124         } else {
3125                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3126                         encap_data =
3127                                 ((const struct rte_flow_action_vxlan_encap *)
3128                                                 action->conf)->definition;
3129                 else
3130                         encap_data =
3131                                 ((const struct rte_flow_action_nvgre_encap *)
3132                                                 action->conf)->definition;
3133                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3134                                                &res.size, error))
3135                         return -rte_errno;
3136         }
3137         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3138                 return -rte_errno;
3139         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3140                 return rte_flow_error_set(error, EINVAL,
3141                                           RTE_FLOW_ERROR_TYPE_ACTION,
3142                                           NULL, "can't create L2 encap action");
3143         return 0;
3144 }
3145
3146 /**
3147  * Convert L2 decap action to DV specification.
3148  *
3149  * @param[in] dev
3150  *   Pointer to rte_eth_dev structure.
3151  * @param[in, out] dev_flow
3152  *   Pointer to the mlx5_flow.
3153  * @param[in] transfer
3154  *   Mark if the flow is E-Switch flow.
3155  * @param[out] error
3156  *   Pointer to the error structure.
3157  *
3158  * @return
3159  *   0 on success, a negative errno value otherwise and rte_errno is set.
3160  */
3161 static int
3162 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3163                                struct mlx5_flow *dev_flow,
3164                                uint8_t transfer,
3165                                struct rte_flow_error *error)
3166 {
3167         struct mlx5_flow_dv_encap_decap_resource res = {
3168                 .size = 0,
3169                 .reformat_type =
3170                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3171                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3172                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3173         };
3174
3175         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3176                 return rte_flow_error_set(error, EINVAL,
3177                                           RTE_FLOW_ERROR_TYPE_ACTION,
3178                                           NULL, "can't create L2 decap action");
3179         return 0;
3180 }
3181
3182 /**
3183  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3184  *
3185  * @param[in] dev
3186  *   Pointer to rte_eth_dev structure.
3187  * @param[in] action
3188  *   Pointer to action structure.
3189  * @param[in, out] dev_flow
3190  *   Pointer to the mlx5_flow.
3191  * @param[in] attr
3192  *   Pointer to the flow attributes.
3193  * @param[out] error
3194  *   Pointer to the error structure.
3195  *
3196  * @return
3197  *   0 on success, a negative errno value otherwise and rte_errno is set.
3198  */
3199 static int
3200 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3201                                 const struct rte_flow_action *action,
3202                                 struct mlx5_flow *dev_flow,
3203                                 const struct rte_flow_attr *attr,
3204                                 struct rte_flow_error *error)
3205 {
3206         const struct rte_flow_action_raw_encap *encap_data;
3207         struct mlx5_flow_dv_encap_decap_resource res;
3208
3209         memset(&res, 0, sizeof(res));
3210         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3211         res.size = encap_data->size;
3212         memcpy(res.buf, encap_data->data, res.size);
3213         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3214                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3215                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3216         if (attr->transfer)
3217                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3218         else
3219                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3220                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3221         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3222                 return rte_flow_error_set(error, EINVAL,
3223                                           RTE_FLOW_ERROR_TYPE_ACTION,
3224                                           NULL, "can't create encap action");
3225         return 0;
3226 }
3227
3228 /**
3229  * Create action push VLAN.
3230  *
3231  * @param[in] dev
3232  *   Pointer to rte_eth_dev structure.
3233  * @param[in] attr
3234  *   Pointer to the flow attributes.
3235  * @param[in] vlan
3236  *   Pointer to the vlan to push to the Ethernet header.
3237  * @param[in, out] dev_flow
3238  *   Pointer to the mlx5_flow.
3239  * @param[out] error
3240  *   Pointer to the error structure.
3241  *
3242  * @return
3243  *   0 on success, a negative errno value otherwise and rte_errno is set.
3244  */
3245 static int
3246 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3247                                 const struct rte_flow_attr *attr,
3248                                 const struct rte_vlan_hdr *vlan,
3249                                 struct mlx5_flow *dev_flow,
3250                                 struct rte_flow_error *error)
3251 {
3252         struct mlx5_flow_dv_push_vlan_action_resource res;
3253
3254         memset(&res, 0, sizeof(res));
3255         res.vlan_tag =
3256                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3257                                  vlan->vlan_tci);
3258         if (attr->transfer)
3259                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3260         else
3261                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3262                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3263         return flow_dv_push_vlan_action_resource_register
3264                                             (dev, &res, dev_flow, error);
3265 }
3266
3267 /**
3268  * Validate the modify-header actions.
3269  *
3270  * @param[in] action_flags
3271  *   Holds the actions detected until now.
3272  * @param[in] action
3273  *   Pointer to the modify action.
3274  * @param[out] error
3275  *   Pointer to error structure.
3276  *
3277  * @return
3278  *   0 on success, a negative errno value otherwise and rte_errno is set.
3279  */
3280 static int
3281 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3282                                    const struct rte_flow_action *action,
3283                                    struct rte_flow_error *error)
3284 {
3285         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3286                 return rte_flow_error_set(error, EINVAL,
3287                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3288                                           NULL, "action configuration not set");
3289         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3290                 return rte_flow_error_set(error, EINVAL,
3291                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3292                                           "can't have encap action before"
3293                                           " modify action");
3294         return 0;
3295 }
3296
3297 /**
3298  * Validate the modify-header MAC address actions.
3299  *
3300  * @param[in] action_flags
3301  *   Holds the actions detected until now.
3302  * @param[in] action
3303  *   Pointer to the modify action.
3304  * @param[in] item_flags
3305  *   Holds the items detected.
3306  * @param[out] error
3307  *   Pointer to error structure.
3308  *
3309  * @return
3310  *   0 on success, a negative errno value otherwise and rte_errno is set.
3311  */
3312 static int
3313 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3314                                    const struct rte_flow_action *action,
3315                                    const uint64_t item_flags,
3316                                    struct rte_flow_error *error)
3317 {
3318         int ret = 0;
3319
3320         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3321         if (!ret) {
3322                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3323                         return rte_flow_error_set(error, EINVAL,
3324                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3325                                                   NULL,
3326                                                   "no L2 item in pattern");
3327         }
3328         return ret;
3329 }
3330
3331 /**
3332  * Validate the modify-header IPv4 address actions.
3333  *
3334  * @param[in] action_flags
3335  *   Holds the actions detected until now.
3336  * @param[in] action
3337  *   Pointer to the modify action.
3338  * @param[in] item_flags
3339  *   Holds the items detected.
3340  * @param[out] error
3341  *   Pointer to error structure.
3342  *
3343  * @return
3344  *   0 on success, a negative errno value otherwise and rte_errno is set.
3345  */
3346 static int
3347 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3348                                     const struct rte_flow_action *action,
3349                                     const uint64_t item_flags,
3350                                     struct rte_flow_error *error)
3351 {
3352         int ret = 0;
3353         uint64_t layer;
3354
3355         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3356         if (!ret) {
3357                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3358                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3359                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3360                 if (!(item_flags & layer))
3361                         return rte_flow_error_set(error, EINVAL,
3362                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3363                                                   NULL,
3364                                                   "no ipv4 item in pattern");
3365         }
3366         return ret;
3367 }
3368
3369 /**
3370  * Validate the modify-header IPv6 address actions.
3371  *
3372  * @param[in] action_flags
3373  *   Holds the actions detected until now.
3374  * @param[in] action
3375  *   Pointer to the modify action.
3376  * @param[in] item_flags
3377  *   Holds the items detected.
3378  * @param[out] error
3379  *   Pointer to error structure.
3380  *
3381  * @return
3382  *   0 on success, a negative errno value otherwise and rte_errno is set.
3383  */
3384 static int
3385 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3386                                     const struct rte_flow_action *action,
3387                                     const uint64_t item_flags,
3388                                     struct rte_flow_error *error)
3389 {
3390         int ret = 0;
3391         uint64_t layer;
3392
3393         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3394         if (!ret) {
3395                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3396                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3397                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3398                 if (!(item_flags & layer))
3399                         return rte_flow_error_set(error, EINVAL,
3400                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3401                                                   NULL,
3402                                                   "no ipv6 item in pattern");
3403         }
3404         return ret;
3405 }
3406
3407 /**
3408  * Validate the modify-header TP actions.
3409  *
3410  * @param[in] action_flags
3411  *   Holds the actions detected until now.
3412  * @param[in] action
3413  *   Pointer to the modify action.
3414  * @param[in] item_flags
3415  *   Holds the items detected.
3416  * @param[out] error
3417  *   Pointer to error structure.
3418  *
3419  * @return
3420  *   0 on success, a negative errno value otherwise and rte_errno is set.
3421  */
3422 static int
3423 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3424                                   const struct rte_flow_action *action,
3425                                   const uint64_t item_flags,
3426                                   struct rte_flow_error *error)
3427 {
3428         int ret = 0;
3429         uint64_t layer;
3430
3431         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3432         if (!ret) {
3433                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3434                                  MLX5_FLOW_LAYER_INNER_L4 :
3435                                  MLX5_FLOW_LAYER_OUTER_L4;
3436                 if (!(item_flags & layer))
3437                         return rte_flow_error_set(error, EINVAL,
3438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3439                                                   NULL, "no transport layer "
3440                                                   "in pattern");
3441         }
3442         return ret;
3443 }
3444
3445 /**
3446  * Validate the modify-header actions of increment/decrement
3447  * TCP Sequence-number.
3448  *
3449  * @param[in] action_flags
3450  *   Holds the actions detected until now.
3451  * @param[in] action
3452  *   Pointer to the modify action.
3453  * @param[in] item_flags
3454  *   Holds the items detected.
3455  * @param[out] error
3456  *   Pointer to error structure.
3457  *
3458  * @return
3459  *   0 on success, a negative errno value otherwise and rte_errno is set.
3460  */
3461 static int
3462 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3463                                        const struct rte_flow_action *action,
3464                                        const uint64_t item_flags,
3465                                        struct rte_flow_error *error)
3466 {
3467         int ret = 0;
3468         uint64_t layer;
3469
3470         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3471         if (!ret) {
3472                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3473                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3474                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3475                 if (!(item_flags & layer))
3476                         return rte_flow_error_set(error, EINVAL,
3477                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3478                                                   NULL, "no TCP item in"
3479                                                   " pattern");
3480                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3481                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3482                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3483                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3484                         return rte_flow_error_set(error, EINVAL,
3485                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3486                                                   NULL,
3487                                                   "cannot decrease and increase"
3488                                                   " TCP sequence number"
3489                                                   " at the same time");
3490         }
3491         return ret;
3492 }
3493
3494 /**
3495  * Validate the modify-header actions of increment/decrement
3496  * TCP Acknowledgment number.
3497  *
3498  * @param[in] action_flags
3499  *   Holds the actions detected until now.
3500  * @param[in] action
3501  *   Pointer to the modify action.
3502  * @param[in] item_flags
3503  *   Holds the items detected.
3504  * @param[out] error
3505  *   Pointer to error structure.
3506  *
3507  * @return
3508  *   0 on success, a negative errno value otherwise and rte_errno is set.
3509  */
3510 static int
3511 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3512                                        const struct rte_flow_action *action,
3513                                        const uint64_t item_flags,
3514                                        struct rte_flow_error *error)
3515 {
3516         int ret = 0;
3517         uint64_t layer;
3518
3519         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3520         if (!ret) {
3521                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3522                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3523                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3524                 if (!(item_flags & layer))
3525                         return rte_flow_error_set(error, EINVAL,
3526                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3527                                                   NULL, "no TCP item in"
3528                                                   " pattern");
3529                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3530                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3531                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3532                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3533                         return rte_flow_error_set(error, EINVAL,
3534                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3535                                                   NULL,
3536                                                   "cannot decrease and increase"
3537                                                   " TCP acknowledgment number"
3538                                                   " at the same time");
3539         }
3540         return ret;
3541 }
3542
3543 /**
3544  * Validate the modify-header TTL actions.
3545  *
3546  * @param[in] action_flags
3547  *   Holds the actions detected until now.
3548  * @param[in] action
3549  *   Pointer to the modify action.
3550  * @param[in] item_flags
3551  *   Holds the items detected.
3552  * @param[out] error
3553  *   Pointer to error structure.
3554  *
3555  * @return
3556  *   0 on success, a negative errno value otherwise and rte_errno is set.
3557  */
3558 static int
3559 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3560                                    const struct rte_flow_action *action,
3561                                    const uint64_t item_flags,
3562                                    struct rte_flow_error *error)
3563 {
3564         int ret = 0;
3565         uint64_t layer;
3566
3567         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3568         if (!ret) {
3569                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3570                                  MLX5_FLOW_LAYER_INNER_L3 :
3571                                  MLX5_FLOW_LAYER_OUTER_L3;
3572                 if (!(item_flags & layer))
3573                         return rte_flow_error_set(error, EINVAL,
3574                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3575                                                   NULL,
3576                                                   "no IP protocol in pattern");
3577         }
3578         return ret;
3579 }
3580
3581 /**
3582  * Validate jump action.
3583  *
3584  * @param[in] action
3585  *   Pointer to the jump action.
3586  * @param[in] action_flags
3587  *   Holds the actions detected until now.
3588  * @param[in] attributes
3589  *   Pointer to flow attributes
3590  * @param[in] external
3591  *   Action belongs to flow rule created by request external to PMD.
3592  * @param[out] error
3593  *   Pointer to error structure.
3594  *
3595  * @return
3596  *   0 on success, a negative errno value otherwise and rte_errno is set.
3597  */
3598 static int
3599 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3600                              uint64_t action_flags,
3601                              const struct rte_flow_attr *attributes,
3602                              bool external, struct rte_flow_error *error)
3603 {
3604         uint32_t target_group, table;
3605         int ret = 0;
3606
3607         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3608                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3609                 return rte_flow_error_set(error, EINVAL,
3610                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3611                                           "can't have 2 fate actions in"
3612                                           " same flow");
3613         if (action_flags & MLX5_FLOW_ACTION_METER)
3614                 return rte_flow_error_set(error, ENOTSUP,
3615                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3616                                           "jump with meter not support");
3617         if (!action->conf)
3618                 return rte_flow_error_set(error, EINVAL,
3619                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3620                                           NULL, "action configuration not set");
3621         target_group =
3622                 ((const struct rte_flow_action_jump *)action->conf)->group;
3623         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3624                                        true, &table, error);
3625         if (ret)
3626                 return ret;
3627         if (attributes->group == target_group)
3628                 return rte_flow_error_set(error, EINVAL,
3629                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3630                                           "target group must be other than"
3631                                           " the current flow group");
3632         return 0;
3633 }
3634
3635 /*
3636  * Validate the port_id action.
3637  *
3638  * @param[in] dev
3639  *   Pointer to rte_eth_dev structure.
3640  * @param[in] action_flags
3641  *   Bit-fields that holds the actions detected until now.
3642  * @param[in] action
3643  *   Port_id RTE action structure.
3644  * @param[in] attr
3645  *   Attributes of flow that includes this action.
3646  * @param[out] error
3647  *   Pointer to error structure.
3648  *
3649  * @return
3650  *   0 on success, a negative errno value otherwise and rte_errno is set.
3651  */
3652 static int
3653 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3654                                 uint64_t action_flags,
3655                                 const struct rte_flow_action *action,
3656                                 const struct rte_flow_attr *attr,
3657                                 struct rte_flow_error *error)
3658 {
3659         const struct rte_flow_action_port_id *port_id;
3660         struct mlx5_priv *act_priv;
3661         struct mlx5_priv *dev_priv;
3662         uint16_t port;
3663
3664         if (!attr->transfer)
3665                 return rte_flow_error_set(error, ENOTSUP,
3666                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3667                                           NULL,
3668                                           "port id action is valid in transfer"
3669                                           " mode only");
3670         if (!action || !action->conf)
3671                 return rte_flow_error_set(error, ENOTSUP,
3672                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3673                                           NULL,
3674                                           "port id action parameters must be"
3675                                           " specified");
3676         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3677                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3678                 return rte_flow_error_set(error, EINVAL,
3679                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3680                                           "can have only one fate actions in"
3681                                           " a flow");
3682         dev_priv = mlx5_dev_to_eswitch_info(dev);
3683         if (!dev_priv)
3684                 return rte_flow_error_set(error, rte_errno,
3685                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3686                                           NULL,
3687                                           "failed to obtain E-Switch info");
3688         port_id = action->conf;
3689         port = port_id->original ? dev->data->port_id : port_id->id;
3690         act_priv = mlx5_port_to_eswitch_info(port, false);
3691         if (!act_priv)
3692                 return rte_flow_error_set
3693                                 (error, rte_errno,
3694                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3695                                  "failed to obtain E-Switch port id for port");
3696         if (act_priv->domain_id != dev_priv->domain_id)
3697                 return rte_flow_error_set
3698                                 (error, EINVAL,
3699                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3700                                  "port does not belong to"
3701                                  " E-Switch being configured");
3702         return 0;
3703 }
3704
3705 /**
3706  * Get the maximum number of modify header actions.
3707  *
3708  * @param dev
3709  *   Pointer to rte_eth_dev structure.
3710  * @param flags
3711  *   Flags bits to check if root level.
3712  *
3713  * @return
3714  *   Max number of modify header actions device can support.
3715  */
3716 static inline unsigned int
3717 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3718                               uint64_t flags)
3719 {
3720         /*
3721          * There's no way to directly query the max capacity from FW.
3722          * The maximal value on root table should be assumed to be supported.
3723          */
3724         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3725                 return MLX5_MAX_MODIFY_NUM;
3726         else
3727                 return MLX5_ROOT_TBL_MODIFY_NUM;
3728 }
3729
3730 /**
3731  * Validate the meter action.
3732  *
3733  * @param[in] dev
3734  *   Pointer to rte_eth_dev structure.
3735  * @param[in] action_flags
3736  *   Bit-fields that holds the actions detected until now.
3737  * @param[in] action
3738  *   Pointer to the meter action.
3739  * @param[in] attr
3740  *   Attributes of flow that includes this action.
3741  * @param[out] error
3742  *   Pointer to error structure.
3743  *
3744  * @return
3745  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3746  */
3747 static int
3748 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3749                                 uint64_t action_flags,
3750                                 const struct rte_flow_action *action,
3751                                 const struct rte_flow_attr *attr,
3752                                 struct rte_flow_error *error)
3753 {
3754         struct mlx5_priv *priv = dev->data->dev_private;
3755         const struct rte_flow_action_meter *am = action->conf;
3756         struct mlx5_flow_meter *fm;
3757
3758         if (!am)
3759                 return rte_flow_error_set(error, EINVAL,
3760                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3761                                           "meter action conf is NULL");
3762
3763         if (action_flags & MLX5_FLOW_ACTION_METER)
3764                 return rte_flow_error_set(error, ENOTSUP,
3765                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3766                                           "meter chaining not support");
3767         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3768                 return rte_flow_error_set(error, ENOTSUP,
3769                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3770                                           "meter with jump not support");
3771         if (!priv->mtr_en)
3772                 return rte_flow_error_set(error, ENOTSUP,
3773                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3774                                           NULL,
3775                                           "meter action not supported");
3776         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3777         if (!fm)
3778                 return rte_flow_error_set(error, EINVAL,
3779                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3780                                           "Meter not found");
3781         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3782               (!fm->ingress && !attr->ingress && attr->egress) ||
3783               (!fm->egress && !attr->egress && attr->ingress))))
3784                 return rte_flow_error_set(error, EINVAL,
3785                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3786                                           "Flow attributes are either invalid "
3787                                           "or have a conflict with current "
3788                                           "meter attributes");
3789         return 0;
3790 }
3791
3792 /**
3793  * Validate the age action.
3794  *
3795  * @param[in] action_flags
3796  *   Holds the actions detected until now.
3797  * @param[in] action
3798  *   Pointer to the age action.
3799  * @param[in] dev
3800  *   Pointer to the Ethernet device structure.
3801  * @param[out] error
3802  *   Pointer to error structure.
3803  *
3804  * @return
3805  *   0 on success, a negative errno value otherwise and rte_errno is set.
3806  */
3807 static int
3808 flow_dv_validate_action_age(uint64_t action_flags,
3809                             const struct rte_flow_action *action,
3810                             struct rte_eth_dev *dev,
3811                             struct rte_flow_error *error)
3812 {
3813         struct mlx5_priv *priv = dev->data->dev_private;
3814         const struct rte_flow_action_age *age = action->conf;
3815
3816         if (!priv->config.devx || priv->counter_fallback)
3817                 return rte_flow_error_set(error, ENOTSUP,
3818                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3819                                           NULL,
3820                                           "age action not supported");
3821         if (!(action->conf))
3822                 return rte_flow_error_set(error, EINVAL,
3823                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3824                                           "configuration cannot be null");
3825         if (age->timeout >= UINT16_MAX / 2 / 10)
3826                 return rte_flow_error_set(error, ENOTSUP,
3827                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3828                                           "Max age time: 3275 seconds");
3829         if (action_flags & MLX5_FLOW_ACTION_AGE)
3830                 return rte_flow_error_set(error, EINVAL,
3831                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3832                                           "Duplicate age ctions set");
3833         return 0;
3834 }
3835
3836 /**
3837  * Validate the modify-header IPv4 DSCP actions.
3838  *
3839  * @param[in] action_flags
3840  *   Holds the actions detected until now.
3841  * @param[in] action
3842  *   Pointer to the modify action.
3843  * @param[in] item_flags
3844  *   Holds the items detected.
3845  * @param[out] error
3846  *   Pointer to error structure.
3847  *
3848  * @return
3849  *   0 on success, a negative errno value otherwise and rte_errno is set.
3850  */
3851 static int
3852 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3853                                          const struct rte_flow_action *action,
3854                                          const uint64_t item_flags,
3855                                          struct rte_flow_error *error)
3856 {
3857         int ret = 0;
3858
3859         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3860         if (!ret) {
3861                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3862                         return rte_flow_error_set(error, EINVAL,
3863                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3864                                                   NULL,
3865                                                   "no ipv4 item in pattern");
3866         }
3867         return ret;
3868 }
3869
3870 /**
3871  * Validate the modify-header IPv6 DSCP actions.
3872  *
3873  * @param[in] action_flags
3874  *   Holds the actions detected until now.
3875  * @param[in] action
3876  *   Pointer to the modify action.
3877  * @param[in] item_flags
3878  *   Holds the items detected.
3879  * @param[out] error
3880  *   Pointer to error structure.
3881  *
3882  * @return
3883  *   0 on success, a negative errno value otherwise and rte_errno is set.
3884  */
3885 static int
3886 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3887                                          const struct rte_flow_action *action,
3888                                          const uint64_t item_flags,
3889                                          struct rte_flow_error *error)
3890 {
3891         int ret = 0;
3892
3893         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3894         if (!ret) {
3895                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3896                         return rte_flow_error_set(error, EINVAL,
3897                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3898                                                   NULL,
3899                                                   "no ipv6 item in pattern");
3900         }
3901         return ret;
3902 }
3903
3904 /**
3905  * Find existing modify-header resource or create and register a new one.
3906  *
3907  * @param dev[in, out]
3908  *   Pointer to rte_eth_dev structure.
3909  * @param[in, out] resource
3910  *   Pointer to modify-header resource.
3911  * @parm[in, out] dev_flow
3912  *   Pointer to the dev_flow.
3913  * @param[out] error
3914  *   pointer to error structure.
3915  *
3916  * @return
3917  *   0 on success otherwise -errno and errno is set.
3918  */
3919 static int
3920 flow_dv_modify_hdr_resource_register
3921                         (struct rte_eth_dev *dev,
3922                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3923                          struct mlx5_flow *dev_flow,
3924                          struct rte_flow_error *error)
3925 {
3926         struct mlx5_priv *priv = dev->data->dev_private;
3927         struct mlx5_ibv_shared *sh = priv->sh;
3928         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3929         struct mlx5dv_dr_domain *ns;
3930         uint32_t actions_len;
3931
3932         resource->flags = dev_flow->dv.group ? 0 :
3933                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3934         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3935                                     resource->flags))
3936                 return rte_flow_error_set(error, EOVERFLOW,
3937                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3938                                           "too many modify header items");
3939         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3940                 ns = sh->fdb_domain;
3941         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3942                 ns = sh->tx_domain;
3943         else
3944                 ns = sh->rx_domain;
3945         /* Lookup a matching resource from cache. */
3946         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3947         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3948                 if (resource->ft_type == cache_resource->ft_type &&
3949                     resource->actions_num == cache_resource->actions_num &&
3950                     resource->flags == cache_resource->flags &&
3951                     !memcmp((const void *)resource->actions,
3952                             (const void *)cache_resource->actions,
3953                             actions_len)) {
3954                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3955                                 (void *)cache_resource,
3956                                 rte_atomic32_read(&cache_resource->refcnt));
3957                         rte_atomic32_inc(&cache_resource->refcnt);
3958                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3959                         return 0;
3960                 }
3961         }
3962         /* Register new modify-header resource. */
3963         cache_resource = rte_calloc(__func__, 1,
3964                                     sizeof(*cache_resource) + actions_len, 0);
3965         if (!cache_resource)
3966                 return rte_flow_error_set(error, ENOMEM,
3967                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3968                                           "cannot allocate resource memory");
3969         *cache_resource = *resource;
3970         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3971         cache_resource->verbs_action =
3972                 mlx5_glue->dv_create_flow_action_modify_header
3973                                         (sh->ctx, cache_resource->ft_type, ns,
3974                                          cache_resource->flags, actions_len,
3975                                          (uint64_t *)cache_resource->actions);
3976         if (!cache_resource->verbs_action) {
3977                 rte_free(cache_resource);
3978                 return rte_flow_error_set(error, ENOMEM,
3979                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3980                                           NULL, "cannot create action");
3981         }
3982         rte_atomic32_init(&cache_resource->refcnt);
3983         rte_atomic32_inc(&cache_resource->refcnt);
3984         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3985         dev_flow->handle->dvh.modify_hdr = cache_resource;
3986         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3987                 (void *)cache_resource,
3988                 rte_atomic32_read(&cache_resource->refcnt));
3989         return 0;
3990 }
3991
3992 /**
3993  * Get DV flow counter by index.
3994  *
3995  * @param[in] dev
3996  *   Pointer to the Ethernet device structure.
3997  * @param[in] idx
3998  *   mlx5 flow counter index in the container.
3999  * @param[out] ppool
4000  *   mlx5 flow counter pool in the container,
4001  *
4002  * @return
4003  *   Pointer to the counter, NULL otherwise.
4004  */
4005 static struct mlx5_flow_counter *
4006 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4007                            uint32_t idx,
4008                            struct mlx5_flow_counter_pool **ppool)
4009 {
4010         struct mlx5_priv *priv = dev->data->dev_private;
4011         struct mlx5_pools_container *cont;
4012         struct mlx5_flow_counter_pool *pool;
4013         uint32_t batch = 0, age = 0;
4014
4015         idx--;
4016         age = MLX_CNT_IS_AGE(idx);
4017         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4018         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4019                 idx -= MLX5_CNT_BATCH_OFFSET;
4020                 batch = 1;
4021         }
4022         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4023         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4024         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4025         MLX5_ASSERT(pool);
4026         if (ppool)
4027                 *ppool = pool;
4028         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4029 }
4030
4031 /**
4032  * Get a pool by devx counter ID.
4033  *
4034  * @param[in] cont
4035  *   Pointer to the counter container.
4036  * @param[in] id
4037  *   The counter devx ID.
4038  *
4039  * @return
4040  *   The counter pool pointer if exists, NULL otherwise,
4041  */
4042 static struct mlx5_flow_counter_pool *
4043 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4044 {
4045         uint32_t i;
4046         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4047
4048         for (i = 0; i < n_valid; i++) {
4049                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4050                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4051                            MLX5_COUNTERS_PER_POOL;
4052
4053                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
4054                         /*
4055                          * Move the pool to the head, as counter allocate
4056                          * always gets the first pool in the container.
4057                          */
4058                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
4059                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4060                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4061                         }
4062                         return pool;
4063                 }
4064         }
4065         return NULL;
4066 }
4067
4068 /**
4069  * Allocate a new memory for the counter values wrapped by all the needed
4070  * management.
4071  *
4072  * @param[in] dev
4073  *   Pointer to the Ethernet device structure.
4074  * @param[in] raws_n
4075  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4076  *
4077  * @return
4078  *   The new memory management pointer on success, otherwise NULL and rte_errno
4079  *   is set.
4080  */
4081 static struct mlx5_counter_stats_mem_mng *
4082 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4083 {
4084         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
4085                                         (dev->data->dev_private))->sh;
4086         struct mlx5_devx_mkey_attr mkey_attr;
4087         struct mlx5_counter_stats_mem_mng *mem_mng;
4088         volatile struct flow_counter_stats *raw_data;
4089         int size = (sizeof(struct flow_counter_stats) *
4090                         MLX5_COUNTERS_PER_POOL +
4091                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4092                         sizeof(struct mlx5_counter_stats_mem_mng);
4093         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4094         int i;
4095
4096         if (!mem) {
4097                 rte_errno = ENOMEM;
4098                 return NULL;
4099         }
4100         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4101         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4102         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4103                                                  IBV_ACCESS_LOCAL_WRITE);
4104         if (!mem_mng->umem) {
4105                 rte_errno = errno;
4106                 rte_free(mem);
4107                 return NULL;
4108         }
4109         mkey_attr.addr = (uintptr_t)mem;
4110         mkey_attr.size = size;
4111         mkey_attr.umem_id = mem_mng->umem->umem_id;
4112         mkey_attr.pd = sh->pdn;
4113         mkey_attr.log_entity_size = 0;
4114         mkey_attr.pg_access = 0;
4115         mkey_attr.klm_array = NULL;
4116         mkey_attr.klm_num = 0;
4117         mkey_attr.relaxed_ordering = 1;
4118         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4119         if (!mem_mng->dm) {
4120                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4121                 rte_errno = errno;
4122                 rte_free(mem);
4123                 return NULL;
4124         }
4125         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4126         raw_data = (volatile struct flow_counter_stats *)mem;
4127         for (i = 0; i < raws_n; ++i) {
4128                 mem_mng->raws[i].mem_mng = mem_mng;
4129                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4130         }
4131         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4132         return mem_mng;
4133 }
4134
4135 /**
4136  * Resize a counter container.
4137  *
4138  * @param[in] dev
4139  *   Pointer to the Ethernet device structure.
4140  * @param[in] batch
4141  *   Whether the pool is for counter that was allocated by batch command.
4142  * @param[in] age
4143  *   Whether the pool is for Aging counter.
4144  *
4145  * @return
4146  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4147  */
4148 static struct mlx5_pools_container *
4149 flow_dv_container_resize(struct rte_eth_dev *dev,
4150                                 uint32_t batch, uint32_t age)
4151 {
4152         struct mlx5_priv *priv = dev->data->dev_private;
4153         struct mlx5_pools_container *cont =
4154                         MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4155         struct mlx5_pools_container *new_cont =
4156                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0, age);
4157         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4158         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4159         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4160         int i;
4161
4162         /* Fallback mode has no background thread. Skip the check. */
4163         if (!priv->counter_fallback &&
4164             cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1, age)) {
4165                 /* The last resize still hasn't detected by the host thread. */
4166                 rte_errno = EAGAIN;
4167                 return NULL;
4168         }
4169         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4170         if (!new_cont->pools) {
4171                 rte_errno = ENOMEM;
4172                 return NULL;
4173         }
4174         if (cont->n)
4175                 memcpy(new_cont->pools, cont->pools, cont->n *
4176                        sizeof(struct mlx5_flow_counter_pool *));
4177         /*
4178          * Fallback mode query the counter directly, no background query
4179          * resources are needed.
4180          */
4181         if (!priv->counter_fallback) {
4182                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4183                         MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4184                 if (!mem_mng) {
4185                         rte_free(new_cont->pools);
4186                         return NULL;
4187                 }
4188                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4189                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4190                                          mem_mng->raws +
4191                                          MLX5_CNT_CONTAINER_RESIZE +
4192                                          i, next);
4193         } else {
4194                 /*
4195                  * Release the old container pools directly as no background
4196                  * thread helps that.
4197                  */
4198                 rte_free(cont->pools);
4199         }
4200         new_cont->n = resize;
4201         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4202         TAILQ_INIT(&new_cont->pool_list);
4203         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4204         new_cont->init_mem_mng = mem_mng;
4205         rte_cio_wmb();
4206          /* Flip the master container. */
4207         priv->sh->cmng.mhi[batch][age] ^= (uint8_t)1;
4208         return new_cont;
4209 }
4210
4211 /**
4212  * Query a devx flow counter.
4213  *
4214  * @param[in] dev
4215  *   Pointer to the Ethernet device structure.
4216  * @param[in] cnt
4217  *   Index to the flow counter.
4218  * @param[out] pkts
4219  *   The statistics value of packets.
4220  * @param[out] bytes
4221  *   The statistics value of bytes.
4222  *
4223  * @return
4224  *   0 on success, otherwise a negative errno value and rte_errno is set.
4225  */
4226 static inline int
4227 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4228                      uint64_t *bytes)
4229 {
4230         struct mlx5_priv *priv = dev->data->dev_private;
4231         struct mlx5_flow_counter_pool *pool = NULL;
4232         struct mlx5_flow_counter *cnt;
4233         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4234         int offset;
4235
4236         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4237         MLX5_ASSERT(pool);
4238         if (counter < MLX5_CNT_BATCH_OFFSET) {
4239                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4240                 if (priv->counter_fallback)
4241                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4242                                         0, pkts, bytes, 0, NULL, NULL, 0);
4243         }
4244
4245         rte_spinlock_lock(&pool->sl);
4246         /*
4247          * The single counters allocation may allocate smaller ID than the
4248          * current allocated in parallel to the host reading.
4249          * In this case the new counter values must be reported as 0.
4250          */
4251         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4252                 *pkts = 0;
4253                 *bytes = 0;
4254         } else {
4255                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4256                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4257                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4258         }
4259         rte_spinlock_unlock(&pool->sl);
4260         return 0;
4261 }
4262
4263 /**
4264  * Create and initialize a new counter pool.
4265  *
4266  * @param[in] dev
4267  *   Pointer to the Ethernet device structure.
4268  * @param[out] dcs
4269  *   The devX counter handle.
4270  * @param[in] batch
4271  *   Whether the pool is for counter that was allocated by batch command.
4272  * @param[in] age
4273  *   Whether the pool is for counter that was allocated for aging.
4274  * @param[in/out] cont_cur
4275  *   Pointer to the container pointer, it will be update in pool resize.
4276  *
4277  * @return
4278  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4279  */
4280 static struct mlx5_pools_container *
4281 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4282                     uint32_t batch, uint32_t age)
4283 {
4284         struct mlx5_priv *priv = dev->data->dev_private;
4285         struct mlx5_flow_counter_pool *pool;
4286         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4287                                                                0, age);
4288         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4289         uint32_t size = sizeof(*pool);
4290
4291         if (cont->n == n_valid) {
4292                 cont = flow_dv_container_resize(dev, batch, age);
4293                 if (!cont)
4294                         return NULL;
4295         }
4296         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4297         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4298         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4299         pool = rte_calloc(__func__, 1, size, 0);
4300         if (!pool) {
4301                 rte_errno = ENOMEM;
4302                 return NULL;
4303         }
4304         pool->min_dcs = dcs;
4305         if (!priv->counter_fallback)
4306                 pool->raw = cont->init_mem_mng->raws + n_valid %
4307                                                      MLX5_CNT_CONTAINER_RESIZE;
4308         pool->raw_hw = NULL;
4309         pool->type = 0;
4310         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4311         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4312         rte_spinlock_init(&pool->sl);
4313         /*
4314          * The generation of the new allocated counters in this pool is 0, 2 in
4315          * the pool generation makes all the counters valid for allocation.
4316          * The start and end query generation protect the counters be released
4317          * between the query and update gap period will not be reallocated
4318          * without the last query finished and stats updated to the memory.
4319          */
4320         rte_atomic64_set(&pool->start_query_gen, 0x2);
4321         /*
4322          * There's no background query thread for fallback mode, set the
4323          * end_query_gen to the maximum value since no need to wait for
4324          * statistics update.
4325          */
4326         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4327                          INT64_MAX : 0x2);
4328         TAILQ_INIT(&pool->counters);
4329         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4330         pool->index = n_valid;
4331         cont->pools[n_valid] = pool;
4332         /* Pool initialization must be updated before host thread access. */
4333         rte_cio_wmb();
4334         rte_atomic16_add(&cont->n_valid, 1);
4335         return cont;
4336 }
4337
4338 /**
4339  * Update the minimum dcs-id for aged or no-aged counter pool.
4340  *
4341  * @param[in] dev
4342  *   Pointer to the Ethernet device structure.
4343  * @param[in] pool
4344  *   Current counter pool.
4345  * @param[in] batch
4346  *   Whether the pool is for counter that was allocated by batch command.
4347  * @param[in] age
4348  *   Whether the counter is for aging.
4349  */
4350 static void
4351 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4352                         struct mlx5_flow_counter_pool *pool,
4353                         uint32_t batch, uint32_t age)
4354 {
4355         struct mlx5_priv *priv = dev->data->dev_private;
4356         struct mlx5_flow_counter_pool *other;
4357         struct mlx5_pools_container *cont;
4358
4359         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, (age ^ 0x1));
4360         other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4361         if (!other)
4362                 return;
4363         if (pool->min_dcs->id < other->min_dcs->id) {
4364                 rte_atomic64_set(&other->a64_dcs,
4365                         rte_atomic64_read(&pool->a64_dcs));
4366         } else {
4367                 rte_atomic64_set(&pool->a64_dcs,
4368                         rte_atomic64_read(&other->a64_dcs));
4369         }
4370 }
4371 /**
4372  * Prepare a new counter and/or a new counter pool.
4373  *
4374  * @param[in] dev
4375  *   Pointer to the Ethernet device structure.
4376  * @param[out] cnt_free
4377  *   Where to put the pointer of a new counter.
4378  * @param[in] batch
4379  *   Whether the pool is for counter that was allocated by batch command.
4380  * @param[in] age
4381  *   Whether the pool is for counter that was allocated for aging.
4382  *
4383  * @return
4384  *   The counter container pointer and @p cnt_free is set on success,
4385  *   NULL otherwise and rte_errno is set.
4386  */
4387 static struct mlx5_pools_container *
4388 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4389                              struct mlx5_flow_counter **cnt_free,
4390                              uint32_t batch, uint32_t age)
4391 {
4392         struct mlx5_priv *priv = dev->data->dev_private;
4393         struct mlx5_pools_container *cont;
4394         struct mlx5_flow_counter_pool *pool;
4395         struct mlx5_devx_obj *dcs = NULL;
4396         struct mlx5_flow_counter *cnt;
4397         uint32_t i;
4398
4399         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4400         if (!batch) {
4401                 /* bulk_bitmap must be 0 for single counter allocation. */
4402                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4403                 if (!dcs)
4404                         return NULL;
4405                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4406                 if (!pool) {
4407                         cont = flow_dv_pool_create(dev, dcs, batch, age);
4408                         if (!cont) {
4409                                 mlx5_devx_cmd_destroy(dcs);
4410                                 return NULL;
4411                         }
4412                         pool = TAILQ_FIRST(&cont->pool_list);
4413                 } else if (dcs->id < pool->min_dcs->id) {
4414                         rte_atomic64_set(&pool->a64_dcs,
4415                                          (int64_t)(uintptr_t)dcs);
4416                 }
4417                 flow_dv_counter_update_min_dcs(dev,
4418                                                 pool, batch, age);
4419                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4420                 cnt = MLX5_POOL_GET_CNT(pool, i);
4421                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4422                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4423                 *cnt_free = cnt;
4424                 return cont;
4425         }
4426         /* bulk_bitmap is in 128 counters units. */
4427         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4428                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4429         if (!dcs) {
4430                 rte_errno = ENODATA;
4431                 return NULL;
4432         }
4433         cont = flow_dv_pool_create(dev, dcs, batch, age);
4434         if (!cont) {
4435                 mlx5_devx_cmd_destroy(dcs);
4436                 return NULL;
4437         }
4438         pool = TAILQ_FIRST(&cont->pool_list);
4439         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4440                 cnt = MLX5_POOL_GET_CNT(pool, i);
4441                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4442         }
4443         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4444         return cont;
4445 }
4446
4447 /**
4448  * Search for existed shared counter.
4449  *
4450  * @param[in] cont
4451  *   Pointer to the relevant counter pool container.
4452  * @param[in] id
4453  *   The shared counter ID to search.
4454  * @param[out] ppool
4455  *   mlx5 flow counter pool in the container,
4456  *
4457  * @return
4458  *   NULL if not existed, otherwise pointer to the shared extend counter.
4459  */
4460 static struct mlx5_flow_counter_ext *
4461 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4462                               struct mlx5_flow_counter_pool **ppool)
4463 {
4464         static struct mlx5_flow_counter_ext *cnt;
4465         struct mlx5_flow_counter_pool *pool;
4466         uint32_t i;
4467         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4468
4469         for (i = 0; i < n_valid; i++) {
4470                 pool = cont->pools[i];
4471                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4472                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4473                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4474                                 if (ppool)
4475                                         *ppool = cont->pools[i];
4476                                 return cnt;
4477                         }
4478                 }
4479         }
4480         return NULL;
4481 }
4482
4483 /**
4484  * Allocate a flow counter.
4485  *
4486  * @param[in] dev
4487  *   Pointer to the Ethernet device structure.
4488  * @param[in] shared
4489  *   Indicate if this counter is shared with other flows.
4490  * @param[in] id
4491  *   Counter identifier.
4492  * @param[in] group
4493  *   Counter flow group.
4494  * @param[in] age
4495  *   Whether the counter was allocated for aging.
4496  *
4497  * @return
4498  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4499  */
4500 static uint32_t
4501 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4502                       uint16_t group, uint32_t age)
4503 {
4504         struct mlx5_priv *priv = dev->data->dev_private;
4505         struct mlx5_flow_counter_pool *pool = NULL;
4506         struct mlx5_flow_counter *cnt_free = NULL;
4507         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4508         /*
4509          * Currently group 0 flow counter cannot be assigned to a flow if it is
4510          * not the first one in the batch counter allocation, so it is better
4511          * to allocate counters one by one for these flows in a separate
4512          * container.
4513          * A counter can be shared between different groups so need to take
4514          * shared counters from the single container.
4515          */
4516         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4517         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4518                                                                0, age);
4519         uint32_t cnt_idx;
4520
4521         if (!priv->config.devx) {
4522                 rte_errno = ENOTSUP;
4523                 return 0;
4524         }
4525         if (shared) {
4526                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4527                 if (cnt_ext) {
4528                         if (cnt_ext->ref_cnt + 1 == 0) {
4529                                 rte_errno = E2BIG;
4530                                 return 0;
4531                         }
4532                         cnt_ext->ref_cnt++;
4533                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4534                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4535                                   + 1;
4536                         return cnt_idx;
4537                 }
4538         }
4539         /* Pools which has a free counters are in the start. */
4540         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4541                 /*
4542                  * The free counter reset values must be updated between the
4543                  * counter release to the counter allocation, so, at least one
4544                  * query must be done in this time. ensure it by saving the
4545                  * query generation in the release time.
4546                  * The free list is sorted according to the generation - so if
4547                  * the first one is not updated, all the others are not
4548                  * updated too.
4549                  */
4550                 cnt_free = TAILQ_FIRST(&pool->counters);
4551                 if (cnt_free && cnt_free->query_gen <
4552                     rte_atomic64_read(&pool->end_query_gen))
4553                         break;
4554                 cnt_free = NULL;
4555         }
4556         if (!cnt_free) {
4557                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4558                 if (!cont)
4559                         return 0;
4560                 pool = TAILQ_FIRST(&cont->pool_list);
4561         }
4562         if (!batch)
4563                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4564         /* Create a DV counter action only in the first time usage. */
4565         if (!cnt_free->action) {
4566                 uint16_t offset;
4567                 struct mlx5_devx_obj *dcs;
4568
4569                 if (batch) {
4570                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4571                         dcs = pool->min_dcs;
4572                 } else {
4573                         offset = 0;
4574                         dcs = cnt_ext->dcs;
4575                 }
4576                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4577                                         (dcs->obj, offset);
4578                 if (!cnt_free->action) {
4579                         rte_errno = errno;
4580                         return 0;
4581                 }
4582         }
4583         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4584                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4585         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4586         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4587         /* Update the counter reset values. */
4588         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4589                                  &cnt_free->bytes))
4590                 return 0;
4591         if (cnt_ext) {
4592                 cnt_ext->shared = shared;
4593                 cnt_ext->ref_cnt = 1;
4594                 cnt_ext->id = id;
4595         }
4596         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4597                 /* Start the asynchronous batch query by the host thread. */
4598                 mlx5_set_query_alarm(priv->sh);
4599         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4600         if (TAILQ_EMPTY(&pool->counters)) {
4601                 /* Move the pool to the end of the container pool list. */
4602                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4603                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4604         }
4605         return cnt_idx;
4606 }
4607
4608 /**
4609  * Get age param from counter index.
4610  *
4611  * @param[in] dev
4612  *   Pointer to the Ethernet device structure.
4613  * @param[in] counter
4614  *   Index to the counter handler.
4615  *
4616  * @return
4617  *   The aging parameter specified for the counter index.
4618  */
4619 static struct mlx5_age_param*
4620 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4621                                 uint32_t counter)
4622 {
4623         struct mlx5_flow_counter *cnt;
4624         struct mlx5_flow_counter_pool *pool = NULL;
4625
4626         flow_dv_counter_get_by_idx(dev, counter, &pool);
4627         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4628         cnt = MLX5_POOL_GET_CNT(pool, counter);
4629         return MLX5_CNT_TO_AGE(cnt);
4630 }
4631
4632 /**
4633  * Remove a flow counter from aged counter list.
4634  *
4635  * @param[in] dev
4636  *   Pointer to the Ethernet device structure.
4637  * @param[in] counter
4638  *   Index to the counter handler.
4639  * @param[in] cnt
4640  *   Pointer to the counter handler.
4641  */
4642 static void
4643 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4644                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4645 {
4646         struct mlx5_age_info *age_info;
4647         struct mlx5_age_param *age_param;
4648         struct mlx5_priv *priv = dev->data->dev_private;
4649
4650         age_info = GET_PORT_AGE_INFO(priv);
4651         age_param = flow_dv_counter_idx_get_age(dev, counter);
4652         if (rte_atomic16_cmpset((volatile uint16_t *)
4653                         &age_param->state,
4654                         AGE_CANDIDATE, AGE_FREE)
4655                         != AGE_CANDIDATE) {
4656                 /**
4657                  * We need the lock even it is age timeout,
4658                  * since counter may still in process.
4659                  */
4660                 rte_spinlock_lock(&age_info->aged_sl);
4661                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4662                 rte_spinlock_unlock(&age_info->aged_sl);
4663         }
4664         rte_atomic16_set(&age_param->state, AGE_FREE);
4665 }
4666 /**
4667  * Release a flow counter.
4668  *
4669  * @param[in] dev
4670  *   Pointer to the Ethernet device structure.
4671  * @param[in] counter
4672  *   Index to the counter handler.
4673  */
4674 static void
4675 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4676 {
4677         struct mlx5_flow_counter_pool *pool = NULL;
4678         struct mlx5_flow_counter *cnt;
4679         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4680
4681         if (!counter)
4682                 return;
4683         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4684         MLX5_ASSERT(pool);
4685         if (counter < MLX5_CNT_BATCH_OFFSET) {
4686                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4687                 if (cnt_ext && --cnt_ext->ref_cnt)
4688                         return;
4689         }
4690         if (IS_AGE_POOL(pool))
4691                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4692         /* Put the counter in the end - the last updated one. */
4693         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4694         /*
4695          * Counters released between query trigger and handler need
4696          * to wait the next round of query. Since the packets arrive
4697          * in the gap period will not be taken into account to the
4698          * old counter.
4699          */
4700         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4701 }
4702
4703 /**
4704  * Verify the @p attributes will be correctly understood by the NIC and store
4705  * them in the @p flow if everything is correct.
4706  *
4707  * @param[in] dev
4708  *   Pointer to dev struct.
4709  * @param[in] attributes
4710  *   Pointer to flow attributes
4711  * @param[in] external
4712  *   This flow rule is created by request external to PMD.
4713  * @param[out] error
4714  *   Pointer to error structure.
4715  *
4716  * @return
4717  *   - 0 on success and non root table.
4718  *   - 1 on success and root table.
4719  *   - a negative errno value otherwise and rte_errno is set.
4720  */
4721 static int
4722 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4723                             const struct rte_flow_attr *attributes,
4724                             bool external __rte_unused,
4725                             struct rte_flow_error *error)
4726 {
4727         struct mlx5_priv *priv = dev->data->dev_private;
4728         uint32_t priority_max = priv->config.flow_prio - 1;
4729         int ret = 0;
4730
4731 #ifndef HAVE_MLX5DV_DR
4732         if (attributes->group)
4733                 return rte_flow_error_set(error, ENOTSUP,
4734                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4735                                           NULL,
4736                                           "groups are not supported");
4737 #else
4738         uint32_t table = 0;
4739
4740         ret = mlx5_flow_group_to_table(attributes, external,
4741                                        attributes->group, !!priv->fdb_def_rule,
4742                                        &table, error);
4743         if (ret)
4744                 return ret;
4745         if (!table)
4746                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4747 #endif
4748         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4749             attributes->priority >= priority_max)
4750                 return rte_flow_error_set(error, ENOTSUP,
4751                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4752                                           NULL,
4753                                           "priority out of range");
4754         if (attributes->transfer) {
4755                 if (!priv->config.dv_esw_en)
4756                         return rte_flow_error_set
4757                                 (error, ENOTSUP,
4758                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4759                                  "E-Switch dr is not supported");
4760                 if (!(priv->representor || priv->master))
4761                         return rte_flow_error_set
4762                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4763                                  NULL, "E-Switch configuration can only be"
4764                                  " done by a master or a representor device");
4765                 if (attributes->egress)
4766                         return rte_flow_error_set
4767                                 (error, ENOTSUP,
4768                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4769                                  "egress is not supported");
4770         }
4771         if (!(attributes->egress ^ attributes->ingress))
4772                 return rte_flow_error_set(error, ENOTSUP,
4773                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4774                                           "must specify exactly one of "
4775                                           "ingress or egress");
4776         return ret;
4777 }
4778
4779 /**
4780  * Internal validation function. For validating both actions and items.
4781  *
4782  * @param[in] dev
4783  *   Pointer to the rte_eth_dev structure.
4784  * @param[in] attr
4785  *   Pointer to the flow attributes.
4786  * @param[in] items
4787  *   Pointer to the list of items.
4788  * @param[in] actions
4789  *   Pointer to the list of actions.
4790  * @param[in] external
4791  *   This flow rule is created by request external to PMD.
4792  * @param[in] hairpin
4793  *   Number of hairpin TX actions, 0 means classic flow.
4794  * @param[out] error
4795  *   Pointer to the error structure.
4796  *
4797  * @return
4798  *   0 on success, a negative errno value otherwise and rte_errno is set.
4799  */
4800 static int
4801 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4802                  const struct rte_flow_item items[],
4803                  const struct rte_flow_action actions[],
4804                  bool external, int hairpin, struct rte_flow_error *error)
4805 {
4806         int ret;
4807         uint64_t action_flags = 0;
4808         uint64_t item_flags = 0;
4809         uint64_t last_item = 0;
4810         uint8_t next_protocol = 0xff;
4811         uint16_t ether_type = 0;
4812         int actions_n = 0;
4813         uint8_t item_ipv6_proto = 0;
4814         const struct rte_flow_item *gre_item = NULL;
4815         const struct rte_flow_action_raw_decap *decap;
4816         const struct rte_flow_action_raw_encap *encap;
4817         const struct rte_flow_action_rss *rss;
4818         const struct rte_flow_item_tcp nic_tcp_mask = {
4819                 .hdr = {
4820                         .tcp_flags = 0xFF,
4821                         .src_port = RTE_BE16(UINT16_MAX),
4822                         .dst_port = RTE_BE16(UINT16_MAX),
4823                 }
4824         };
4825         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4826                 .hdr = {
4827                         .src_addr = RTE_BE32(0xffffffff),
4828                         .dst_addr = RTE_BE32(0xffffffff),
4829                         .type_of_service = 0xff,
4830                         .next_proto_id = 0xff,
4831                         .time_to_live = 0xff,
4832                 },
4833         };
4834         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4835                 .hdr = {
4836                         .src_addr =
4837                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4838                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4839                         .dst_addr =
4840                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4841                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4842                         .vtc_flow = RTE_BE32(0xffffffff),
4843                         .proto = 0xff,
4844                         .hop_limits = 0xff,
4845                 },
4846         };
4847         struct mlx5_priv *priv = dev->data->dev_private;
4848         struct mlx5_dev_config *dev_conf = &priv->config;
4849         uint16_t queue_index = 0xFFFF;
4850         const struct rte_flow_item_vlan *vlan_m = NULL;
4851         int16_t rw_act_num = 0;
4852         uint64_t is_root;
4853
4854         if (items == NULL)
4855                 return -1;
4856         ret = flow_dv_validate_attributes(dev, attr, external, error);
4857         if (ret < 0)
4858                 return ret;
4859         is_root = (uint64_t)ret;
4860         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4861                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4862                 int type = items->type;
4863
4864                 switch (type) {
4865                 case RTE_FLOW_ITEM_TYPE_VOID:
4866                         break;
4867                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4868                         ret = flow_dv_validate_item_port_id
4869                                         (dev, items, attr, item_flags, error);
4870                         if (ret < 0)
4871                                 return ret;
4872                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4873                         break;
4874                 case RTE_FLOW_ITEM_TYPE_ETH:
4875                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4876                                                           error);
4877                         if (ret < 0)
4878                                 return ret;
4879                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4880                                              MLX5_FLOW_LAYER_OUTER_L2;
4881                         if (items->mask != NULL && items->spec != NULL) {
4882                                 ether_type =
4883                                         ((const struct rte_flow_item_eth *)
4884                                          items->spec)->type;
4885                                 ether_type &=
4886                                         ((const struct rte_flow_item_eth *)
4887                                          items->mask)->type;
4888                                 ether_type = rte_be_to_cpu_16(ether_type);
4889                         } else {
4890                                 ether_type = 0;
4891                         }
4892                         break;
4893                 case RTE_FLOW_ITEM_TYPE_VLAN:
4894                         ret = flow_dv_validate_item_vlan(items, item_flags,
4895                                                          dev, error);
4896                         if (ret < 0)
4897                                 return ret;
4898                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4899                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4900                         if (items->mask != NULL && items->spec != NULL) {
4901                                 ether_type =
4902                                         ((const struct rte_flow_item_vlan *)
4903                                          items->spec)->inner_type;
4904                                 ether_type &=
4905                                         ((const struct rte_flow_item_vlan *)
4906                                          items->mask)->inner_type;
4907                                 ether_type = rte_be_to_cpu_16(ether_type);
4908                         } else {
4909                                 ether_type = 0;
4910                         }
4911                         /* Store outer VLAN mask for of_push_vlan action. */
4912                         if (!tunnel)
4913                                 vlan_m = items->mask;
4914                         break;
4915                 case RTE_FLOW_ITEM_TYPE_IPV4:
4916                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4917                                                   &item_flags, &tunnel);
4918                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4919                                                            last_item,
4920                                                            ether_type,
4921                                                            &nic_ipv4_mask,
4922                                                            error);
4923                         if (ret < 0)
4924                                 return ret;
4925                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4926                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4927                         if (items->mask != NULL &&
4928                             ((const struct rte_flow_item_ipv4 *)
4929                              items->mask)->hdr.next_proto_id) {
4930                                 next_protocol =
4931                                         ((const struct rte_flow_item_ipv4 *)
4932                                          (items->spec))->hdr.next_proto_id;
4933                                 next_protocol &=
4934                                         ((const struct rte_flow_item_ipv4 *)
4935                                          (items->mask))->hdr.next_proto_id;
4936                         } else {
4937                                 /* Reset for inner layer. */
4938                                 next_protocol = 0xff;
4939                         }
4940                         break;
4941                 case RTE_FLOW_ITEM_TYPE_IPV6:
4942                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4943                                                   &item_flags, &tunnel);
4944                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4945                                                            last_item,
4946                                                            ether_type,
4947                                                            &nic_ipv6_mask,
4948                                                            error);
4949                         if (ret < 0)
4950                                 return ret;
4951                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4952                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4953                         if (items->mask != NULL &&
4954                             ((const struct rte_flow_item_ipv6 *)
4955                              items->mask)->hdr.proto) {
4956                                 item_ipv6_proto =
4957                                         ((const struct rte_flow_item_ipv6 *)
4958                                          items->spec)->hdr.proto;
4959                                 next_protocol =
4960                                         ((const struct rte_flow_item_ipv6 *)
4961                                          items->spec)->hdr.proto;
4962                                 next_protocol &=
4963                                         ((const struct rte_flow_item_ipv6 *)
4964                                          items->mask)->hdr.proto;
4965                         } else {
4966                                 /* Reset for inner layer. */
4967                                 next_protocol = 0xff;
4968                         }
4969                         break;
4970                 case RTE_FLOW_ITEM_TYPE_TCP:
4971                         ret = mlx5_flow_validate_item_tcp
4972                                                 (items, item_flags,
4973                                                  next_protocol,
4974                                                  &nic_tcp_mask,
4975                                                  error);
4976                         if (ret < 0)
4977                                 return ret;
4978                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4979                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4980                         break;
4981                 case RTE_FLOW_ITEM_TYPE_UDP:
4982                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4983                                                           next_protocol,
4984                                                           error);
4985                         if (ret < 0)
4986                                 return ret;
4987                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4988                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4989                         break;
4990                 case RTE_FLOW_ITEM_TYPE_GRE:
4991                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4992                                                           next_protocol, error);
4993                         if (ret < 0)
4994                                 return ret;
4995                         gre_item = items;
4996                         last_item = MLX5_FLOW_LAYER_GRE;
4997                         break;
4998                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4999                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5000                                                             next_protocol,
5001                                                             error);
5002                         if (ret < 0)
5003                                 return ret;
5004                         last_item = MLX5_FLOW_LAYER_NVGRE;
5005                         break;
5006                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5007                         ret = mlx5_flow_validate_item_gre_key
5008                                 (items, item_flags, gre_item, error);
5009                         if (ret < 0)
5010                                 return ret;
5011                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5012                         break;
5013                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5014                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5015                                                             error);
5016                         if (ret < 0)
5017                                 return ret;
5018                         last_item = MLX5_FLOW_LAYER_VXLAN;
5019                         break;
5020                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5021                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5022                                                                 item_flags, dev,
5023                                                                 error);
5024                         if (ret < 0)
5025                                 return ret;
5026                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5027                         break;
5028                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5029                         ret = mlx5_flow_validate_item_geneve(items,
5030                                                              item_flags, dev,
5031                                                              error);
5032                         if (ret < 0)
5033                                 return ret;
5034                         last_item = MLX5_FLOW_LAYER_GENEVE;
5035                         break;
5036                 case RTE_FLOW_ITEM_TYPE_MPLS:
5037                         ret = mlx5_flow_validate_item_mpls(dev, items,
5038                                                            item_flags,
5039                                                            last_item, error);
5040                         if (ret < 0)
5041                                 return ret;
5042                         last_item = MLX5_FLOW_LAYER_MPLS;
5043                         break;
5044
5045                 case RTE_FLOW_ITEM_TYPE_MARK:
5046                         ret = flow_dv_validate_item_mark(dev, items, attr,
5047                                                          error);
5048                         if (ret < 0)
5049                                 return ret;
5050                         last_item = MLX5_FLOW_ITEM_MARK;
5051                         break;
5052                 case RTE_FLOW_ITEM_TYPE_META:
5053                         ret = flow_dv_validate_item_meta(dev, items, attr,
5054                                                          error);
5055                         if (ret < 0)
5056                                 return ret;
5057                         last_item = MLX5_FLOW_ITEM_METADATA;
5058                         break;
5059                 case RTE_FLOW_ITEM_TYPE_ICMP:
5060                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5061                                                            next_protocol,
5062                                                            error);
5063                         if (ret < 0)
5064                                 return ret;
5065                         last_item = MLX5_FLOW_LAYER_ICMP;
5066                         break;
5067                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5068                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5069                                                             next_protocol,
5070                                                             error);
5071                         if (ret < 0)
5072                                 return ret;
5073                         item_ipv6_proto = IPPROTO_ICMPV6;
5074                         last_item = MLX5_FLOW_LAYER_ICMP6;
5075                         break;
5076                 case RTE_FLOW_ITEM_TYPE_TAG:
5077                         ret = flow_dv_validate_item_tag(dev, items,
5078                                                         attr, error);
5079                         if (ret < 0)
5080                                 return ret;
5081                         last_item = MLX5_FLOW_ITEM_TAG;
5082                         break;
5083                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5084                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5085                         break;
5086                 case RTE_FLOW_ITEM_TYPE_GTP:
5087                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5088                                                         error);
5089                         if (ret < 0)
5090                                 return ret;
5091                         last_item = MLX5_FLOW_LAYER_GTP;
5092                         break;
5093                 default:
5094                         return rte_flow_error_set(error, ENOTSUP,
5095                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5096                                                   NULL, "item not supported");
5097                 }
5098                 item_flags |= last_item;
5099         }
5100         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5101                 int type = actions->type;
5102                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5103                         return rte_flow_error_set(error, ENOTSUP,
5104                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5105                                                   actions, "too many actions");
5106                 switch (type) {
5107                 case RTE_FLOW_ACTION_TYPE_VOID:
5108                         break;
5109                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5110                         ret = flow_dv_validate_action_port_id(dev,
5111                                                               action_flags,
5112                                                               actions,
5113                                                               attr,
5114                                                               error);
5115                         if (ret)
5116                                 return ret;
5117                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5118                         ++actions_n;
5119                         break;
5120                 case RTE_FLOW_ACTION_TYPE_FLAG:
5121                         ret = flow_dv_validate_action_flag(dev, action_flags,
5122                                                            attr, error);
5123                         if (ret < 0)
5124                                 return ret;
5125                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5126                                 /* Count all modify-header actions as one. */
5127                                 if (!(action_flags &
5128                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5129                                         ++actions_n;
5130                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5131                                                 MLX5_FLOW_ACTION_MARK_EXT;
5132                         } else {
5133                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5134                                 ++actions_n;
5135                         }
5136                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5137                         break;
5138                 case RTE_FLOW_ACTION_TYPE_MARK:
5139                         ret = flow_dv_validate_action_mark(dev, actions,
5140                                                            action_flags,
5141                                                            attr, error);
5142                         if (ret < 0)
5143                                 return ret;
5144                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5145                                 /* Count all modify-header actions as one. */
5146                                 if (!(action_flags &
5147                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5148                                         ++actions_n;
5149                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5150                                                 MLX5_FLOW_ACTION_MARK_EXT;
5151                         } else {
5152                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5153                                 ++actions_n;
5154                         }
5155                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5156                         break;
5157                 case RTE_FLOW_ACTION_TYPE_SET_META:
5158                         ret = flow_dv_validate_action_set_meta(dev, actions,
5159                                                                action_flags,
5160                                                                attr, error);
5161                         if (ret < 0)
5162                                 return ret;
5163                         /* Count all modify-header actions as one action. */
5164                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5165                                 ++actions_n;
5166                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5167                         rw_act_num += MLX5_ACT_NUM_SET_META;
5168                         break;
5169                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5170                         ret = flow_dv_validate_action_set_tag(dev, actions,
5171                                                               action_flags,
5172                                                               attr, error);
5173                         if (ret < 0)
5174                                 return ret;
5175                         /* Count all modify-header actions as one action. */
5176                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5177                                 ++actions_n;
5178                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5179                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5180                         break;
5181                 case RTE_FLOW_ACTION_TYPE_DROP:
5182                         ret = mlx5_flow_validate_action_drop(action_flags,
5183                                                              attr, error);
5184                         if (ret < 0)
5185                                 return ret;
5186                         action_flags |= MLX5_FLOW_ACTION_DROP;
5187                         ++actions_n;
5188                         break;
5189                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5190                         ret = mlx5_flow_validate_action_queue(actions,
5191                                                               action_flags, dev,
5192                                                               attr, error);
5193                         if (ret < 0)
5194                                 return ret;
5195                         queue_index = ((const struct rte_flow_action_queue *)
5196                                                         (actions->conf))->index;
5197                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5198                         ++actions_n;
5199                         break;
5200                 case RTE_FLOW_ACTION_TYPE_RSS:
5201                         rss = actions->conf;
5202                         ret = mlx5_flow_validate_action_rss(actions,
5203                                                             action_flags, dev,
5204                                                             attr, item_flags,
5205                                                             error);
5206                         if (ret < 0)
5207                                 return ret;
5208                         if (rss != NULL && rss->queue_num)
5209                                 queue_index = rss->queue[0];
5210                         action_flags |= MLX5_FLOW_ACTION_RSS;
5211                         ++actions_n;
5212                         break;
5213                 case RTE_FLOW_ACTION_TYPE_COUNT:
5214                         ret = flow_dv_validate_action_count(dev, error);
5215                         if (ret < 0)
5216                                 return ret;
5217                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5218                         ++actions_n;
5219                         break;
5220                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5221                         if (flow_dv_validate_action_pop_vlan(dev,
5222                                                              action_flags,
5223                                                              actions,
5224                                                              item_flags, attr,
5225                                                              error))
5226                                 return -rte_errno;
5227                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5228                         ++actions_n;
5229                         break;
5230                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5231                         ret = flow_dv_validate_action_push_vlan(dev,
5232                                                                 action_flags,
5233                                                                 vlan_m,
5234                                                                 actions, attr,
5235                                                                 error);
5236                         if (ret < 0)
5237                                 return ret;
5238                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5239                         ++actions_n;
5240                         break;
5241                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5242                         ret = flow_dv_validate_action_set_vlan_pcp
5243                                                 (action_flags, actions, error);
5244                         if (ret < 0)
5245                                 return ret;
5246                         /* Count PCP with push_vlan command. */
5247                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5248                         break;
5249                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5250                         ret = flow_dv_validate_action_set_vlan_vid
5251                                                 (item_flags, action_flags,
5252                                                  actions, error);
5253                         if (ret < 0)
5254                                 return ret;
5255                         /* Count VID with push_vlan command. */
5256                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5257                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5258                         break;
5259                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5260                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5261                         ret = flow_dv_validate_action_l2_encap(dev,
5262                                                                action_flags,
5263                                                                actions, attr,
5264                                                                error);
5265                         if (ret < 0)
5266                                 return ret;
5267                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5268                         ++actions_n;
5269                         break;
5270                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5271                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5272                         ret = flow_dv_validate_action_decap(dev, action_flags,
5273                                                             attr, error);
5274                         if (ret < 0)
5275                                 return ret;
5276                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5277                         ++actions_n;
5278                         break;
5279                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5280                         ret = flow_dv_validate_action_raw_encap_decap
5281                                 (dev, NULL, actions->conf, attr, &action_flags,
5282                                  &actions_n, error);
5283                         if (ret < 0)
5284                                 return ret;
5285                         break;
5286                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5287                         decap = actions->conf;
5288                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5289                                 ;
5290                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5291                                 encap = NULL;
5292                                 actions--;
5293                         } else {
5294                                 encap = actions->conf;
5295                         }
5296                         ret = flow_dv_validate_action_raw_encap_decap
5297                                            (dev,
5298                                             decap ? decap : &empty_decap, encap,
5299                                             attr, &action_flags, &actions_n,
5300                                             error);
5301                         if (ret < 0)
5302                                 return ret;
5303                         break;
5304                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5305                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5306                         ret = flow_dv_validate_action_modify_mac(action_flags,
5307                                                                  actions,
5308                                                                  item_flags,
5309                                                                  error);
5310                         if (ret < 0)
5311                                 return ret;
5312                         /* Count all modify-header actions as one action. */
5313                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5314                                 ++actions_n;
5315                         action_flags |= actions->type ==
5316                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5317                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5318                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5319                         /*
5320                          * Even if the source and destination MAC addresses have
5321                          * overlap in the header with 4B alignment, the convert
5322                          * function will handle them separately and 4 SW actions
5323                          * will be created. And 2 actions will be added each
5324                          * time no matter how many bytes of address will be set.
5325                          */
5326                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5327                         break;
5328                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5329                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5330                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5331                                                                   actions,
5332                                                                   item_flags,
5333                                                                   error);
5334                         if (ret < 0)
5335                                 return ret;
5336                         /* Count all modify-header actions as one action. */
5337                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5338                                 ++actions_n;
5339                         action_flags |= actions->type ==
5340                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5341                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5342                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5343                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5344                         break;
5345                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5346                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5347                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5348                                                                   actions,
5349                                                                   item_flags,
5350                                                                   error);
5351                         if (ret < 0)
5352                                 return ret;
5353                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5354                                 return rte_flow_error_set(error, ENOTSUP,
5355                                         RTE_FLOW_ERROR_TYPE_ACTION,
5356                                         actions,
5357                                         "Can't change header "
5358                                         "with ICMPv6 proto");
5359                         /* Count all modify-header actions as one action. */
5360                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5361                                 ++actions_n;
5362                         action_flags |= actions->type ==
5363                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5364                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5365                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5366                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5367                         break;
5368                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5369                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5370                         ret = flow_dv_validate_action_modify_tp(action_flags,
5371                                                                 actions,
5372                                                                 item_flags,
5373                                                                 error);
5374                         if (ret < 0)
5375                                 return ret;
5376                         /* Count all modify-header actions as one action. */
5377                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5378                                 ++actions_n;
5379                         action_flags |= actions->type ==
5380                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5381                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5382                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5383                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5384                         break;
5385                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5386                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5387                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5388                                                                  actions,
5389                                                                  item_flags,
5390                                                                  error);
5391                         if (ret < 0)
5392                                 return ret;
5393                         /* Count all modify-header actions as one action. */
5394                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5395                                 ++actions_n;
5396                         action_flags |= actions->type ==
5397                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5398                                                 MLX5_FLOW_ACTION_SET_TTL :
5399                                                 MLX5_FLOW_ACTION_DEC_TTL;
5400                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5401                         break;
5402                 case RTE_FLOW_ACTION_TYPE_JUMP:
5403                         ret = flow_dv_validate_action_jump(actions,
5404                                                            action_flags,
5405                                                            attr, external,
5406                                                            error);
5407                         if (ret)
5408                                 return ret;
5409                         ++actions_n;
5410                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5411                         break;
5412                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5413                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5414                         ret = flow_dv_validate_action_modify_tcp_seq
5415                                                                 (action_flags,
5416                                                                  actions,
5417                                                                  item_flags,
5418                                                                  error);
5419                         if (ret < 0)
5420                                 return ret;
5421                         /* Count all modify-header actions as one action. */
5422                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5423                                 ++actions_n;
5424                         action_flags |= actions->type ==
5425                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5426                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5427                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5428                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5429                         break;
5430                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5431                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5432                         ret = flow_dv_validate_action_modify_tcp_ack
5433                                                                 (action_flags,
5434                                                                  actions,
5435                                                                  item_flags,
5436                                                                  error);
5437                         if (ret < 0)
5438                                 return ret;
5439                         /* Count all modify-header actions as one action. */
5440                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5441                                 ++actions_n;
5442                         action_flags |= actions->type ==
5443                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5444                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5445                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5446                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5447                         break;
5448                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5449                         break;
5450                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5451                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5452                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5453                         break;
5454                 case RTE_FLOW_ACTION_TYPE_METER:
5455                         ret = mlx5_flow_validate_action_meter(dev,
5456                                                               action_flags,
5457                                                               actions, attr,
5458                                                               error);
5459                         if (ret < 0)
5460                                 return ret;
5461                         action_flags |= MLX5_FLOW_ACTION_METER;
5462                         ++actions_n;
5463                         /* Meter action will add one more TAG action. */
5464                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5465                         break;
5466                 case RTE_FLOW_ACTION_TYPE_AGE:
5467                         ret = flow_dv_validate_action_age(action_flags,
5468                                                           actions, dev,
5469                                                           error);
5470                         if (ret < 0)
5471                                 return ret;
5472                         action_flags |= MLX5_FLOW_ACTION_AGE;
5473                         ++actions_n;
5474                         break;
5475                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5476                         ret = flow_dv_validate_action_modify_ipv4_dscp
5477                                                          (action_flags,
5478                                                           actions,
5479                                                           item_flags,
5480                                                           error);
5481                         if (ret < 0)
5482                                 return ret;
5483                         /* Count all modify-header actions as one action. */
5484                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5485                                 ++actions_n;
5486                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5487                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5488                         break;
5489                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5490                         ret = flow_dv_validate_action_modify_ipv6_dscp
5491                                                                 (action_flags,
5492                                                                  actions,
5493                                                                  item_flags,
5494                                                                  error);
5495                         if (ret < 0)
5496                                 return ret;
5497                         /* Count all modify-header actions as one action. */
5498                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5499                                 ++actions_n;
5500                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5501                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5502                         break;
5503                 default:
5504                         return rte_flow_error_set(error, ENOTSUP,
5505                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5506                                                   actions,
5507                                                   "action not supported");
5508                 }
5509         }
5510         /*
5511          * Validate the drop action mutual exclusion with other actions.
5512          * Drop action is mutually-exclusive with any other action, except for
5513          * Count action.
5514          */
5515         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5516             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5517                 return rte_flow_error_set(error, EINVAL,
5518                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5519                                           "Drop action is mutually-exclusive "
5520                                           "with any other action, except for "
5521                                           "Count action");
5522         /* Eswitch has few restrictions on using items and actions */
5523         if (attr->transfer) {
5524                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5525                     action_flags & MLX5_FLOW_ACTION_FLAG)
5526                         return rte_flow_error_set(error, ENOTSUP,
5527                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5528                                                   NULL,
5529                                                   "unsupported action FLAG");
5530                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5531                     action_flags & MLX5_FLOW_ACTION_MARK)
5532                         return rte_flow_error_set(error, ENOTSUP,
5533                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5534                                                   NULL,
5535                                                   "unsupported action MARK");
5536                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5537                         return rte_flow_error_set(error, ENOTSUP,
5538                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5539                                                   NULL,
5540                                                   "unsupported action QUEUE");
5541                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5542                         return rte_flow_error_set(error, ENOTSUP,
5543                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5544                                                   NULL,
5545                                                   "unsupported action RSS");
5546                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5547                         return rte_flow_error_set(error, EINVAL,
5548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5549                                                   actions,
5550                                                   "no fate action is found");
5551         } else {
5552                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5553                         return rte_flow_error_set(error, EINVAL,
5554                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5555                                                   actions,
5556                                                   "no fate action is found");
5557         }
5558         /* Continue validation for Xcap actions.*/
5559         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5560             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5561                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5562                     MLX5_FLOW_XCAP_ACTIONS)
5563                         return rte_flow_error_set(error, ENOTSUP,
5564                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5565                                                   NULL, "encap and decap "
5566                                                   "combination aren't supported");
5567                 if (!attr->transfer && attr->ingress && (action_flags &
5568                                                         MLX5_FLOW_ACTION_ENCAP))
5569                         return rte_flow_error_set(error, ENOTSUP,
5570                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5571                                                   NULL, "encap is not supported"
5572                                                   " for ingress traffic");
5573         }
5574         /* Hairpin flow will add one more TAG action. */
5575         if (hairpin > 0)
5576                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5577         /* extra metadata enabled: one more TAG action will be add. */
5578         if (dev_conf->dv_flow_en &&
5579             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5580             mlx5_flow_ext_mreg_supported(dev))
5581                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5582         if ((uint32_t)rw_act_num >
5583                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5584                 return rte_flow_error_set(error, ENOTSUP,
5585                                           RTE_FLOW_ERROR_TYPE_ACTION,
5586                                           NULL, "too many header modify"
5587                                           " actions to support");
5588         }
5589         return 0;
5590 }
5591
5592 /**
5593  * Internal preparation function. Allocates the DV flow size,
5594  * this size is constant.
5595  *
5596  * @param[in] dev
5597  *   Pointer to the rte_eth_dev structure.
5598  * @param[in] attr
5599  *   Pointer to the flow attributes.
5600  * @param[in] items
5601  *   Pointer to the list of items.
5602  * @param[in] actions
5603  *   Pointer to the list of actions.
5604  * @param[out] error
5605  *   Pointer to the error structure.
5606  *
5607  * @return
5608  *   Pointer to mlx5_flow object on success,
5609  *   otherwise NULL and rte_errno is set.
5610  */
5611 static struct mlx5_flow *
5612 flow_dv_prepare(struct rte_eth_dev *dev,
5613                 const struct rte_flow_attr *attr __rte_unused,
5614                 const struct rte_flow_item items[] __rte_unused,
5615                 const struct rte_flow_action actions[] __rte_unused,
5616                 struct rte_flow_error *error)
5617 {
5618         uint32_t handle_idx = 0;
5619         struct mlx5_flow *dev_flow;
5620         struct mlx5_flow_handle *dev_handle;
5621         struct mlx5_priv *priv = dev->data->dev_private;
5622
5623         /* In case of corrupting the memory. */
5624         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5625                 rte_flow_error_set(error, ENOSPC,
5626                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5627                                    "not free temporary device flow");
5628                 return NULL;
5629         }
5630         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5631                                    &handle_idx);
5632         if (!dev_handle) {
5633                 rte_flow_error_set(error, ENOMEM,
5634                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5635                                    "not enough memory to create flow handle");
5636                 return NULL;
5637         }
5638         /* No multi-thread supporting. */
5639         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5640         dev_flow->handle = dev_handle;
5641         dev_flow->handle_idx = handle_idx;
5642         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5643         /*
5644          * The matching value needs to be cleared to 0 before using. In the
5645          * past, it will be automatically cleared when using rte_*alloc
5646          * API. The time consumption will be almost the same as before.
5647          */
5648         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5649         dev_flow->ingress = attr->ingress;
5650         dev_flow->dv.transfer = attr->transfer;
5651         return dev_flow;
5652 }
5653
5654 #ifdef RTE_LIBRTE_MLX5_DEBUG
5655 /**
5656  * Sanity check for match mask and value. Similar to check_valid_spec() in
5657  * kernel driver. If unmasked bit is present in value, it returns failure.
5658  *
5659  * @param match_mask
5660  *   pointer to match mask buffer.
5661  * @param match_value
5662  *   pointer to match value buffer.
5663  *
5664  * @return
5665  *   0 if valid, -EINVAL otherwise.
5666  */
5667 static int
5668 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5669 {
5670         uint8_t *m = match_mask;
5671         uint8_t *v = match_value;
5672         unsigned int i;
5673
5674         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5675                 if (v[i] & ~m[i]) {
5676                         DRV_LOG(ERR,
5677                                 "match_value differs from match_criteria"
5678                                 " %p[%u] != %p[%u]",
5679                                 match_value, i, match_mask, i);
5680                         return -EINVAL;
5681                 }
5682         }
5683         return 0;
5684 }
5685 #endif
5686
5687 /**
5688  * Add match of ip_version.
5689  *
5690  * @param[in] group
5691  *   Flow group.
5692  * @param[in] headers_v
5693  *   Values header pointer.
5694  * @param[in] headers_m
5695  *   Masks header pointer.
5696  * @param[in] ip_version
5697  *   The IP version to set.
5698  */
5699 static inline void
5700 flow_dv_set_match_ip_version(uint32_t group,
5701                              void *headers_v,
5702                              void *headers_m,
5703                              uint8_t ip_version)
5704 {
5705         if (group == 0)
5706                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5707         else
5708                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5709                          ip_version);
5710         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5711         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5712         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5713 }
5714
5715 /**
5716  * Add Ethernet item to matcher and to the value.
5717  *
5718  * @param[in, out] matcher
5719  *   Flow matcher.
5720  * @param[in, out] key
5721  *   Flow matcher value.
5722  * @param[in] item
5723  *   Flow pattern to translate.
5724  * @param[in] inner
5725  *   Item is inner pattern.
5726  */
5727 static void
5728 flow_dv_translate_item_eth(void *matcher, void *key,
5729                            const struct rte_flow_item *item, int inner,
5730                            uint32_t group)
5731 {
5732         const struct rte_flow_item_eth *eth_m = item->mask;
5733         const struct rte_flow_item_eth *eth_v = item->spec;
5734         const struct rte_flow_item_eth nic_mask = {
5735                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5736                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5737                 .type = RTE_BE16(0xffff),
5738         };
5739         void *headers_m;
5740         void *headers_v;
5741         char *l24_v;
5742         unsigned int i;
5743
5744         if (!eth_v)
5745                 return;
5746         if (!eth_m)
5747                 eth_m = &nic_mask;
5748         if (inner) {
5749                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5750                                          inner_headers);
5751                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5752         } else {
5753                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5754                                          outer_headers);
5755                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5756         }
5757         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5758                &eth_m->dst, sizeof(eth_m->dst));
5759         /* The value must be in the range of the mask. */
5760         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5761         for (i = 0; i < sizeof(eth_m->dst); ++i)
5762                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5763         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5764                &eth_m->src, sizeof(eth_m->src));
5765         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5766         /* The value must be in the range of the mask. */
5767         for (i = 0; i < sizeof(eth_m->dst); ++i)
5768                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5769         if (eth_v->type) {
5770                 /* When ethertype is present set mask for tagged VLAN. */
5771                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5772                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5773                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5774                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5775                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5776                                  1);
5777                         /* Return here to avoid setting match on ethertype. */
5778                         return;
5779                 }
5780         }
5781         /*
5782          * HW supports match on one Ethertype, the Ethertype following the last
5783          * VLAN tag of the packet (see PRM).
5784          * Set match on ethertype only if ETH header is not followed by VLAN.
5785          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5786          * ethertype, and use ip_version field instead.
5787          */
5788         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5789             eth_m->type == 0xFFFF) {
5790                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5791         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5792                    eth_m->type == 0xFFFF) {
5793                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5794         } else {
5795                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5796                          rte_be_to_cpu_16(eth_m->type));
5797                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5798                                      ethertype);
5799                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5800         }
5801 }
5802
5803 /**
5804  * Add VLAN item to matcher and to the value.
5805  *
5806  * @param[in, out] dev_flow
5807  *   Flow descriptor.
5808  * @param[in, out] matcher
5809  *   Flow matcher.
5810  * @param[in, out] key
5811  *   Flow matcher value.
5812  * @param[in] item
5813  *   Flow pattern to translate.
5814  * @param[in] inner
5815  *   Item is inner pattern.
5816  */
5817 static void
5818 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5819                             void *matcher, void *key,
5820                             const struct rte_flow_item *item,
5821                             int inner, uint32_t group)
5822 {
5823         const struct rte_flow_item_vlan *vlan_m = item->mask;
5824         const struct rte_flow_item_vlan *vlan_v = item->spec;
5825         void *headers_m;
5826         void *headers_v;
5827         uint16_t tci_m;
5828         uint16_t tci_v;
5829
5830         if (inner) {
5831                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5832                                          inner_headers);
5833                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5834         } else {
5835                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5836                                          outer_headers);
5837                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5838                 /*
5839                  * This is workaround, masks are not supported,
5840                  * and pre-validated.
5841                  */
5842                 if (vlan_v)
5843                         dev_flow->handle->vf_vlan.tag =
5844                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5845         }
5846         /*
5847          * When VLAN item exists in flow, mark packet as tagged,
5848          * even if TCI is not specified.
5849          */
5850         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5851         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5852         if (!vlan_v)
5853                 return;
5854         if (!vlan_m)
5855                 vlan_m = &rte_flow_item_vlan_mask;
5856         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5857         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5858         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5859         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5860         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5861         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5862         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5863         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5864         /*
5865          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5866          * ethertype, and use ip_version field instead.
5867          */
5868         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5869             vlan_m->inner_type == 0xFFFF) {
5870                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5871         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5872                    vlan_m->inner_type == 0xFFFF) {
5873                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5874         } else {
5875                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5876                          rte_be_to_cpu_16(vlan_m->inner_type));
5877                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5878                          rte_be_to_cpu_16(vlan_m->inner_type &
5879                                           vlan_v->inner_type));
5880         }
5881 }
5882
5883 /**
5884  * Add IPV4 item to matcher and to the value.
5885  *
5886  * @param[in, out] matcher
5887  *   Flow matcher.
5888  * @param[in, out] key
5889  *   Flow matcher value.
5890  * @param[in] item
5891  *   Flow pattern to translate.
5892  * @param[in] item_flags
5893  *   Bit-fields that holds the items detected until now.
5894  * @param[in] inner
5895  *   Item is inner pattern.
5896  * @param[in] group
5897  *   The group to insert the rule.
5898  */
5899 static void
5900 flow_dv_translate_item_ipv4(void *matcher, void *key,
5901                             const struct rte_flow_item *item,
5902                             const uint64_t item_flags,
5903                             int inner, uint32_t group)
5904 {
5905         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5906         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5907         const struct rte_flow_item_ipv4 nic_mask = {
5908                 .hdr = {
5909                         .src_addr = RTE_BE32(0xffffffff),
5910                         .dst_addr = RTE_BE32(0xffffffff),
5911                         .type_of_service = 0xff,
5912                         .next_proto_id = 0xff,
5913                         .time_to_live = 0xff,
5914                 },
5915         };
5916         void *headers_m;
5917         void *headers_v;
5918         char *l24_m;
5919         char *l24_v;
5920         uint8_t tos;
5921
5922         if (inner) {
5923                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5924                                          inner_headers);
5925                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5926         } else {
5927                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5928                                          outer_headers);
5929                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5930         }
5931         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5932         /*
5933          * On outer header (which must contains L2), or inner header with L2,
5934          * set cvlan_tag mask bit to mark this packet as untagged.
5935          * This should be done even if item->spec is empty.
5936          */
5937         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5938                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5939         if (!ipv4_v)
5940                 return;
5941         if (!ipv4_m)
5942                 ipv4_m = &nic_mask;
5943         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5944                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5945         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5946                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5947         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5948         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5949         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5950                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5951         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5952                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5953         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5954         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5955         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5956         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5957                  ipv4_m->hdr.type_of_service);
5958         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5959         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5960                  ipv4_m->hdr.type_of_service >> 2);
5961         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5962         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5963                  ipv4_m->hdr.next_proto_id);
5964         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5965                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5966         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5967                  ipv4_m->hdr.time_to_live);
5968         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5969                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5970 }
5971
5972 /**
5973  * Add IPV6 item to matcher and to the value.
5974  *
5975  * @param[in, out] matcher
5976  *   Flow matcher.
5977  * @param[in, out] key
5978  *   Flow matcher value.
5979  * @param[in] item
5980  *   Flow pattern to translate.
5981  * @param[in] item_flags
5982  *   Bit-fields that holds the items detected until now.
5983  * @param[in] inner
5984  *   Item is inner pattern.
5985  * @param[in] group
5986  *   The group to insert the rule.
5987  */
5988 static void
5989 flow_dv_translate_item_ipv6(void *matcher, void *key,
5990                             const struct rte_flow_item *item,
5991                             const uint64_t item_flags,
5992                             int inner, uint32_t group)
5993 {
5994         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5995         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5996         const struct rte_flow_item_ipv6 nic_mask = {
5997                 .hdr = {
5998                         .src_addr =
5999                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6000                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6001                         .dst_addr =
6002                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6003                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6004                         .vtc_flow = RTE_BE32(0xffffffff),
6005                         .proto = 0xff,
6006                         .hop_limits = 0xff,
6007                 },
6008         };
6009         void *headers_m;
6010         void *headers_v;
6011         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6012         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6013         char *l24_m;
6014         char *l24_v;
6015         uint32_t vtc_m;
6016         uint32_t vtc_v;
6017         int i;
6018         int size;
6019
6020         if (inner) {
6021                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6022                                          inner_headers);
6023                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6024         } else {
6025                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6026                                          outer_headers);
6027                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6028         }
6029         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6030         /*
6031          * On outer header (which must contains L2), or inner header with L2,
6032          * set cvlan_tag mask bit to mark this packet as untagged.
6033          * This should be done even if item->spec is empty.
6034          */
6035         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6036                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6037         if (!ipv6_v)
6038                 return;
6039         if (!ipv6_m)
6040                 ipv6_m = &nic_mask;
6041         size = sizeof(ipv6_m->hdr.dst_addr);
6042         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6043                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6044         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6045                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6046         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6047         for (i = 0; i < size; ++i)
6048                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6049         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6050                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6051         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6052                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6053         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6054         for (i = 0; i < size; ++i)
6055                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6056         /* TOS. */
6057         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6058         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6059         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6060         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6061         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6062         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6063         /* Label. */
6064         if (inner) {
6065                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6066                          vtc_m);
6067                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6068                          vtc_v);
6069         } else {
6070                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6071                          vtc_m);
6072                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6073                          vtc_v);
6074         }
6075         /* Protocol. */
6076         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6077                  ipv6_m->hdr.proto);
6078         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6079                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6080         /* Hop limit. */
6081         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6082                  ipv6_m->hdr.hop_limits);
6083         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6084                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6085 }
6086
6087 /**
6088  * Add TCP item to matcher and to the value.
6089  *
6090  * @param[in, out] matcher
6091  *   Flow matcher.
6092  * @param[in, out] key
6093  *   Flow matcher value.
6094  * @param[in] item
6095  *   Flow pattern to translate.
6096  * @param[in] inner
6097  *   Item is inner pattern.
6098  */
6099 static void
6100 flow_dv_translate_item_tcp(void *matcher, void *key,
6101                            const struct rte_flow_item *item,
6102                            int inner)
6103 {
6104         const struct rte_flow_item_tcp *tcp_m = item->mask;
6105         const struct rte_flow_item_tcp *tcp_v = item->spec;
6106         void *headers_m;
6107         void *headers_v;
6108
6109         if (inner) {
6110                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6111                                          inner_headers);
6112                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6113         } else {
6114                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6115                                          outer_headers);
6116                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6117         }
6118         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6119         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6120         if (!tcp_v)
6121                 return;
6122         if (!tcp_m)
6123                 tcp_m = &rte_flow_item_tcp_mask;
6124         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6125                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6126         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6127                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6128         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6129                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6130         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6131                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6132         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6133                  tcp_m->hdr.tcp_flags);
6134         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6135                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6136 }
6137
6138 /**
6139  * Add UDP item to matcher and to the value.
6140  *
6141  * @param[in, out] matcher
6142  *   Flow matcher.
6143  * @param[in, out] key
6144  *   Flow matcher value.
6145  * @param[in] item
6146  *   Flow pattern to translate.
6147  * @param[in] inner
6148  *   Item is inner pattern.
6149  */
6150 static void
6151 flow_dv_translate_item_udp(void *matcher, void *key,
6152                            const struct rte_flow_item *item,
6153                            int inner)
6154 {
6155         const struct rte_flow_item_udp *udp_m = item->mask;
6156         const struct rte_flow_item_udp *udp_v = item->spec;
6157         void *headers_m;
6158         void *headers_v;
6159
6160         if (inner) {
6161                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6162                                          inner_headers);
6163                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6164         } else {
6165                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6166                                          outer_headers);
6167                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6168         }
6169         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6170         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6171         if (!udp_v)
6172                 return;
6173         if (!udp_m)
6174                 udp_m = &rte_flow_item_udp_mask;
6175         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6176                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6177         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6178                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6179         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6180                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6181         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6182                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6183 }
6184
6185 /**
6186  * Add GRE optional Key item to matcher and to the value.
6187  *
6188  * @param[in, out] matcher
6189  *   Flow matcher.
6190  * @param[in, out] key
6191  *   Flow matcher value.
6192  * @param[in] item
6193  *   Flow pattern to translate.
6194  * @param[in] inner
6195  *   Item is inner pattern.
6196  */
6197 static void
6198 flow_dv_translate_item_gre_key(void *matcher, void *key,
6199                                    const struct rte_flow_item *item)
6200 {
6201         const rte_be32_t *key_m = item->mask;
6202         const rte_be32_t *key_v = item->spec;
6203         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6204         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6205         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6206
6207         /* GRE K bit must be on and should already be validated */
6208         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6209         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6210         if (!key_v)
6211                 return;
6212         if (!key_m)
6213                 key_m = &gre_key_default_mask;
6214         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6215                  rte_be_to_cpu_32(*key_m) >> 8);
6216         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6217                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6218         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6219                  rte_be_to_cpu_32(*key_m) & 0xFF);
6220         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6221                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6222 }
6223
6224 /**
6225  * Add GRE item to matcher and to the value.
6226  *
6227  * @param[in, out] matcher
6228  *   Flow matcher.
6229  * @param[in, out] key
6230  *   Flow matcher value.
6231  * @param[in] item
6232  *   Flow pattern to translate.
6233  * @param[in] inner
6234  *   Item is inner pattern.
6235  */
6236 static void
6237 flow_dv_translate_item_gre(void *matcher, void *key,
6238                            const struct rte_flow_item *item,
6239                            int inner)
6240 {
6241         const struct rte_flow_item_gre *gre_m = item->mask;
6242         const struct rte_flow_item_gre *gre_v = item->spec;
6243         void *headers_m;
6244         void *headers_v;
6245         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6246         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6247         struct {
6248                 union {
6249                         __extension__
6250                         struct {
6251                                 uint16_t version:3;
6252                                 uint16_t rsvd0:9;
6253                                 uint16_t s_present:1;
6254                                 uint16_t k_present:1;
6255                                 uint16_t rsvd_bit1:1;
6256                                 uint16_t c_present:1;
6257                         };
6258                         uint16_t value;
6259                 };
6260         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6261
6262         if (inner) {
6263                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6264                                          inner_headers);
6265                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6266         } else {
6267                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6268                                          outer_headers);
6269                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6270         }
6271         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6272         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6273         if (!gre_v)
6274                 return;
6275         if (!gre_m)
6276                 gre_m = &rte_flow_item_gre_mask;
6277         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6278                  rte_be_to_cpu_16(gre_m->protocol));
6279         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6280                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6281         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6282         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6283         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6284                  gre_crks_rsvd0_ver_m.c_present);
6285         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6286                  gre_crks_rsvd0_ver_v.c_present &
6287                  gre_crks_rsvd0_ver_m.c_present);
6288         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6289                  gre_crks_rsvd0_ver_m.k_present);
6290         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6291                  gre_crks_rsvd0_ver_v.k_present &
6292                  gre_crks_rsvd0_ver_m.k_present);
6293         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6294                  gre_crks_rsvd0_ver_m.s_present);
6295         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6296                  gre_crks_rsvd0_ver_v.s_present &
6297                  gre_crks_rsvd0_ver_m.s_present);
6298 }
6299
6300 /**
6301  * Add NVGRE item to matcher and to the value.
6302  *
6303  * @param[in, out] matcher
6304  *   Flow matcher.
6305  * @param[in, out] key
6306  *   Flow matcher value.
6307  * @param[in] item
6308  *   Flow pattern to translate.
6309  * @param[in] inner
6310  *   Item is inner pattern.
6311  */
6312 static void
6313 flow_dv_translate_item_nvgre(void *matcher, void *key,
6314                              const struct rte_flow_item *item,
6315                              int inner)
6316 {
6317         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6318         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6319         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6320         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6321         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6322         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6323         char *gre_key_m;
6324         char *gre_key_v;
6325         int size;
6326         int i;
6327
6328         /* For NVGRE, GRE header fields must be set with defined values. */
6329         const struct rte_flow_item_gre gre_spec = {
6330                 .c_rsvd0_ver = RTE_BE16(0x2000),
6331                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6332         };
6333         const struct rte_flow_item_gre gre_mask = {
6334                 .c_rsvd0_ver = RTE_BE16(0xB000),
6335                 .protocol = RTE_BE16(UINT16_MAX),
6336         };
6337         const struct rte_flow_item gre_item = {
6338                 .spec = &gre_spec,
6339                 .mask = &gre_mask,
6340                 .last = NULL,
6341         };
6342         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6343         if (!nvgre_v)
6344                 return;
6345         if (!nvgre_m)
6346                 nvgre_m = &rte_flow_item_nvgre_mask;
6347         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6348         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6349         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6350         memcpy(gre_key_m, tni_flow_id_m, size);
6351         for (i = 0; i < size; ++i)
6352                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6353 }
6354
6355 /**
6356  * Add VXLAN item to matcher and to the value.
6357  *
6358  * @param[in, out] matcher
6359  *   Flow matcher.
6360  * @param[in, out] key
6361  *   Flow matcher value.
6362  * @param[in] item
6363  *   Flow pattern to translate.
6364  * @param[in] inner
6365  *   Item is inner pattern.
6366  */
6367 static void
6368 flow_dv_translate_item_vxlan(void *matcher, void *key,
6369                              const struct rte_flow_item *item,
6370                              int inner)
6371 {
6372         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6373         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6374         void *headers_m;
6375         void *headers_v;
6376         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6377         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6378         char *vni_m;
6379         char *vni_v;
6380         uint16_t dport;
6381         int size;
6382         int i;
6383
6384         if (inner) {
6385                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6386                                          inner_headers);
6387                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6388         } else {
6389                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6390                                          outer_headers);
6391                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6392         }
6393         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6394                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6395         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6396                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6397                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6398         }
6399         if (!vxlan_v)
6400                 return;
6401         if (!vxlan_m)
6402                 vxlan_m = &rte_flow_item_vxlan_mask;
6403         size = sizeof(vxlan_m->vni);
6404         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6405         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6406         memcpy(vni_m, vxlan_m->vni, size);
6407         for (i = 0; i < size; ++i)
6408                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6409 }
6410
6411 /**
6412  * Add VXLAN-GPE item to matcher and to the value.
6413  *
6414  * @param[in, out] matcher
6415  *   Flow matcher.
6416  * @param[in, out] key
6417  *   Flow matcher value.
6418  * @param[in] item
6419  *   Flow pattern to translate.
6420  * @param[in] inner
6421  *   Item is inner pattern.
6422  */
6423
6424 static void
6425 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6426                                  const struct rte_flow_item *item, int inner)
6427 {
6428         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6429         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6430         void *headers_m;
6431         void *headers_v;
6432         void *misc_m =
6433                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6434         void *misc_v =
6435                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6436         char *vni_m;
6437         char *vni_v;
6438         uint16_t dport;
6439         int size;
6440         int i;
6441         uint8_t flags_m = 0xff;
6442         uint8_t flags_v = 0xc;
6443
6444         if (inner) {
6445                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6446                                          inner_headers);
6447                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6448         } else {
6449                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6450                                          outer_headers);
6451                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6452         }
6453         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6454                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6455         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6456                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6457                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6458         }
6459         if (!vxlan_v)
6460                 return;
6461         if (!vxlan_m)
6462                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6463         size = sizeof(vxlan_m->vni);
6464         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6465         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6466         memcpy(vni_m, vxlan_m->vni, size);
6467         for (i = 0; i < size; ++i)
6468                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6469         if (vxlan_m->flags) {
6470                 flags_m = vxlan_m->flags;
6471                 flags_v = vxlan_v->flags;
6472         }
6473         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6474         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6475         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6476                  vxlan_m->protocol);
6477         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6478                  vxlan_v->protocol);
6479 }
6480
6481 /**
6482  * Add Geneve item to matcher and to the value.
6483  *
6484  * @param[in, out] matcher
6485  *   Flow matcher.
6486  * @param[in, out] key
6487  *   Flow matcher value.
6488  * @param[in] item
6489  *   Flow pattern to translate.
6490  * @param[in] inner
6491  *   Item is inner pattern.
6492  */
6493
6494 static void
6495 flow_dv_translate_item_geneve(void *matcher, void *key,
6496                               const struct rte_flow_item *item, int inner)
6497 {
6498         const struct rte_flow_item_geneve *geneve_m = item->mask;
6499         const struct rte_flow_item_geneve *geneve_v = item->spec;
6500         void *headers_m;
6501         void *headers_v;
6502         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6503         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6504         uint16_t dport;
6505         uint16_t gbhdr_m;
6506         uint16_t gbhdr_v;
6507         char *vni_m;
6508         char *vni_v;
6509         size_t size, i;
6510
6511         if (inner) {
6512                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6513                                          inner_headers);
6514                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6515         } else {
6516                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6517                                          outer_headers);
6518                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6519         }
6520         dport = MLX5_UDP_PORT_GENEVE;
6521         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6522                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6523                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6524         }
6525         if (!geneve_v)
6526                 return;
6527         if (!geneve_m)
6528                 geneve_m = &rte_flow_item_geneve_mask;
6529         size = sizeof(geneve_m->vni);
6530         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6531         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6532         memcpy(vni_m, geneve_m->vni, size);
6533         for (i = 0; i < size; ++i)
6534                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6535         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6536                  rte_be_to_cpu_16(geneve_m->protocol));
6537         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6538                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6539         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6540         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6541         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6542                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6543         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6544                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6545         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6546                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6547         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6548                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6549                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6550 }
6551
6552 /**
6553  * Add MPLS item to matcher and to the value.
6554  *
6555  * @param[in, out] matcher
6556  *   Flow matcher.
6557  * @param[in, out] key
6558  *   Flow matcher value.
6559  * @param[in] item
6560  *   Flow pattern to translate.
6561  * @param[in] prev_layer
6562  *   The protocol layer indicated in previous item.
6563  * @param[in] inner
6564  *   Item is inner pattern.
6565  */
6566 static void
6567 flow_dv_translate_item_mpls(void *matcher, void *key,
6568                             const struct rte_flow_item *item,
6569                             uint64_t prev_layer,
6570                             int inner)
6571 {
6572         const uint32_t *in_mpls_m = item->mask;
6573         const uint32_t *in_mpls_v = item->spec;
6574         uint32_t *out_mpls_m = 0;
6575         uint32_t *out_mpls_v = 0;
6576         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6577         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6578         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6579                                      misc_parameters_2);
6580         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6581         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6582         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6583
6584         switch (prev_layer) {
6585         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6586                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6587                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6588                          MLX5_UDP_PORT_MPLS);
6589                 break;
6590         case MLX5_FLOW_LAYER_GRE:
6591                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6592                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6593                          RTE_ETHER_TYPE_MPLS);
6594                 break;
6595         default:
6596                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6597                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6598                          IPPROTO_MPLS);
6599                 break;
6600         }
6601         if (!in_mpls_v)
6602                 return;
6603         if (!in_mpls_m)
6604                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6605         switch (prev_layer) {
6606         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6607                 out_mpls_m =
6608                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6609                                                  outer_first_mpls_over_udp);
6610                 out_mpls_v =
6611                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6612                                                  outer_first_mpls_over_udp);
6613                 break;
6614         case MLX5_FLOW_LAYER_GRE:
6615                 out_mpls_m =
6616                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6617                                                  outer_first_mpls_over_gre);
6618                 out_mpls_v =
6619                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6620                                                  outer_first_mpls_over_gre);
6621                 break;
6622         default:
6623                 /* Inner MPLS not over GRE is not supported. */
6624                 if (!inner) {
6625                         out_mpls_m =
6626                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6627                                                          misc2_m,
6628                                                          outer_first_mpls);
6629                         out_mpls_v =
6630                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6631                                                          misc2_v,
6632                                                          outer_first_mpls);
6633                 }
6634                 break;
6635         }
6636         if (out_mpls_m && out_mpls_v) {
6637                 *out_mpls_m = *in_mpls_m;
6638                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6639         }
6640 }
6641
6642 /**
6643  * Add metadata register item to matcher
6644  *
6645  * @param[in, out] matcher
6646  *   Flow matcher.
6647  * @param[in, out] key
6648  *   Flow matcher value.
6649  * @param[in] reg_type
6650  *   Type of device metadata register
6651  * @param[in] value
6652  *   Register value
6653  * @param[in] mask
6654  *   Register mask
6655  */
6656 static void
6657 flow_dv_match_meta_reg(void *matcher, void *key,
6658                        enum modify_reg reg_type,
6659                        uint32_t data, uint32_t mask)
6660 {
6661         void *misc2_m =
6662                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6663         void *misc2_v =
6664                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6665         uint32_t temp;
6666
6667         data &= mask;
6668         switch (reg_type) {
6669         case REG_A:
6670                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6671                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6672                 break;
6673         case REG_B:
6674                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6675                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6676                 break;
6677         case REG_C_0:
6678                 /*
6679                  * The metadata register C0 field might be divided into
6680                  * source vport index and META item value, we should set
6681                  * this field according to specified mask, not as whole one.
6682                  */
6683                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6684                 temp |= mask;
6685                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6686                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6687                 temp &= ~mask;
6688                 temp |= data;
6689                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6690                 break;
6691         case REG_C_1:
6692                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6693                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6694                 break;
6695         case REG_C_2:
6696                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6697                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6698                 break;
6699         case REG_C_3:
6700                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6701                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6702                 break;
6703         case REG_C_4:
6704                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6705                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6706                 break;
6707         case REG_C_5:
6708                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6709                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6710                 break;
6711         case REG_C_6:
6712                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6713                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6714                 break;
6715         case REG_C_7:
6716                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6717                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6718                 break;
6719         default:
6720                 MLX5_ASSERT(false);
6721                 break;
6722         }
6723 }
6724
6725 /**
6726  * Add MARK item to matcher
6727  *
6728  * @param[in] dev
6729  *   The device to configure through.
6730  * @param[in, out] matcher
6731  *   Flow matcher.
6732  * @param[in, out] key
6733  *   Flow matcher value.
6734  * @param[in] item
6735  *   Flow pattern to translate.
6736  */
6737 static void
6738 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6739                             void *matcher, void *key,
6740                             const struct rte_flow_item *item)
6741 {
6742         struct mlx5_priv *priv = dev->data->dev_private;
6743         const struct rte_flow_item_mark *mark;
6744         uint32_t value;
6745         uint32_t mask;
6746
6747         mark = item->mask ? (const void *)item->mask :
6748                             &rte_flow_item_mark_mask;
6749         mask = mark->id & priv->sh->dv_mark_mask;
6750         mark = (const void *)item->spec;
6751         MLX5_ASSERT(mark);
6752         value = mark->id & priv->sh->dv_mark_mask & mask;
6753         if (mask) {
6754                 enum modify_reg reg;
6755
6756                 /* Get the metadata register index for the mark. */
6757                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6758                 MLX5_ASSERT(reg > 0);
6759                 if (reg == REG_C_0) {
6760                         struct mlx5_priv *priv = dev->data->dev_private;
6761                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6762                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6763
6764                         mask &= msk_c0;
6765                         mask <<= shl_c0;
6766                         value <<= shl_c0;
6767                 }
6768                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6769         }
6770 }
6771
6772 /**
6773  * Add META item to matcher
6774  *
6775  * @param[in] dev
6776  *   The devich to configure through.
6777  * @param[in, out] matcher
6778  *   Flow matcher.
6779  * @param[in, out] key
6780  *   Flow matcher value.
6781  * @param[in] attr
6782  *   Attributes of flow that includes this item.
6783  * @param[in] item
6784  *   Flow pattern to translate.
6785  */
6786 static void
6787 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6788                             void *matcher, void *key,
6789                             const struct rte_flow_attr *attr,
6790                             const struct rte_flow_item *item)
6791 {
6792         const struct rte_flow_item_meta *meta_m;
6793         const struct rte_flow_item_meta *meta_v;
6794
6795         meta_m = (const void *)item->mask;
6796         if (!meta_m)
6797                 meta_m = &rte_flow_item_meta_mask;
6798         meta_v = (const void *)item->spec;
6799         if (meta_v) {
6800                 int reg;
6801                 uint32_t value = meta_v->data;
6802                 uint32_t mask = meta_m->data;
6803
6804                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6805                 if (reg < 0)
6806                         return;
6807                 /*
6808                  * In datapath code there is no endianness
6809                  * coversions for perfromance reasons, all
6810                  * pattern conversions are done in rte_flow.
6811                  */
6812                 value = rte_cpu_to_be_32(value);
6813                 mask = rte_cpu_to_be_32(mask);
6814                 if (reg == REG_C_0) {
6815                         struct mlx5_priv *priv = dev->data->dev_private;
6816                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6817                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6818 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6819                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6820
6821                         value >>= shr_c0;
6822                         mask >>= shr_c0;
6823 #endif
6824                         value <<= shl_c0;
6825                         mask <<= shl_c0;
6826                         MLX5_ASSERT(msk_c0);
6827                         MLX5_ASSERT(!(~msk_c0 & mask));
6828                 }
6829                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6830         }
6831 }
6832
6833 /**
6834  * Add vport metadata Reg C0 item to matcher
6835  *
6836  * @param[in, out] matcher
6837  *   Flow matcher.
6838  * @param[in, out] key
6839  *   Flow matcher value.
6840  * @param[in] reg
6841  *   Flow pattern to translate.
6842  */
6843 static void
6844 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6845                                   uint32_t value, uint32_t mask)
6846 {
6847         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6848 }
6849
6850 /**
6851  * Add tag item to matcher
6852  *
6853  * @param[in] dev
6854  *   The devich to configure through.
6855  * @param[in, out] matcher
6856  *   Flow matcher.
6857  * @param[in, out] key
6858  *   Flow matcher value.
6859  * @param[in] item
6860  *   Flow pattern to translate.
6861  */
6862 static void
6863 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6864                                 void *matcher, void *key,
6865                                 const struct rte_flow_item *item)
6866 {
6867         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6868         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6869         uint32_t mask, value;
6870
6871         MLX5_ASSERT(tag_v);
6872         value = tag_v->data;
6873         mask = tag_m ? tag_m->data : UINT32_MAX;
6874         if (tag_v->id == REG_C_0) {
6875                 struct mlx5_priv *priv = dev->data->dev_private;
6876                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6877                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6878
6879                 mask &= msk_c0;
6880                 mask <<= shl_c0;
6881                 value <<= shl_c0;
6882         }
6883         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6884 }
6885
6886 /**
6887  * Add TAG item to matcher
6888  *
6889  * @param[in] dev
6890  *   The devich to configure through.
6891  * @param[in, out] matcher
6892  *   Flow matcher.
6893  * @param[in, out] key
6894  *   Flow matcher value.
6895  * @param[in] item
6896  *   Flow pattern to translate.
6897  */
6898 static void
6899 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6900                            void *matcher, void *key,
6901                            const struct rte_flow_item *item)
6902 {
6903         const struct rte_flow_item_tag *tag_v = item->spec;
6904         const struct rte_flow_item_tag *tag_m = item->mask;
6905         enum modify_reg reg;
6906
6907         MLX5_ASSERT(tag_v);
6908         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6909         /* Get the metadata register index for the tag. */
6910         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6911         MLX5_ASSERT(reg > 0);
6912         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6913 }
6914
6915 /**
6916  * Add source vport match to the specified matcher.
6917  *
6918  * @param[in, out] matcher
6919  *   Flow matcher.
6920  * @param[in, out] key
6921  *   Flow matcher value.
6922  * @param[in] port
6923  *   Source vport value to match
6924  * @param[in] mask
6925  *   Mask
6926  */
6927 static void
6928 flow_dv_translate_item_source_vport(void *matcher, void *key,
6929                                     int16_t port, uint16_t mask)
6930 {
6931         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6932         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6933
6934         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6935         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6936 }
6937
6938 /**
6939  * Translate port-id item to eswitch match on  port-id.
6940  *
6941  * @param[in] dev
6942  *   The devich to configure through.
6943  * @param[in, out] matcher
6944  *   Flow matcher.
6945  * @param[in, out] key
6946  *   Flow matcher value.
6947  * @param[in] item
6948  *   Flow pattern to translate.
6949  *
6950  * @return
6951  *   0 on success, a negative errno value otherwise.
6952  */
6953 static int
6954 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6955                                void *key, const struct rte_flow_item *item)
6956 {
6957         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6958         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6959         struct mlx5_priv *priv;
6960         uint16_t mask, id;
6961
6962         mask = pid_m ? pid_m->id : 0xffff;
6963         id = pid_v ? pid_v->id : dev->data->port_id;
6964         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6965         if (!priv)
6966                 return -rte_errno;
6967         /* Translate to vport field or to metadata, depending on mode. */
6968         if (priv->vport_meta_mask)
6969                 flow_dv_translate_item_meta_vport(matcher, key,
6970                                                   priv->vport_meta_tag,
6971                                                   priv->vport_meta_mask);
6972         else
6973                 flow_dv_translate_item_source_vport(matcher, key,
6974                                                     priv->vport_id, mask);
6975         return 0;
6976 }
6977
6978 /**
6979  * Add ICMP6 item to matcher and to the value.
6980  *
6981  * @param[in, out] matcher
6982  *   Flow matcher.
6983  * @param[in, out] key
6984  *   Flow matcher value.
6985  * @param[in] item
6986  *   Flow pattern to translate.
6987  * @param[in] inner
6988  *   Item is inner pattern.
6989  */
6990 static void
6991 flow_dv_translate_item_icmp6(void *matcher, void *key,
6992                               const struct rte_flow_item *item,
6993                               int inner)
6994 {
6995         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6996         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6997         void *headers_m;
6998         void *headers_v;
6999         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7000                                      misc_parameters_3);
7001         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7002         if (inner) {
7003                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7004                                          inner_headers);
7005                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7006         } else {
7007                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7008                                          outer_headers);
7009                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7010         }
7011         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7012         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7013         if (!icmp6_v)
7014                 return;
7015         if (!icmp6_m)
7016                 icmp6_m = &rte_flow_item_icmp6_mask;
7017         /*
7018          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7019          * If only the protocol is specified, no need to match the frag.
7020          */
7021         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7022         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7023         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7024         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7025                  icmp6_v->type & icmp6_m->type);
7026         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7027         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7028                  icmp6_v->code & icmp6_m->code);
7029 }
7030
7031 /**
7032  * Add ICMP item to matcher and to the value.
7033  *
7034  * @param[in, out] matcher
7035  *   Flow matcher.
7036  * @param[in, out] key
7037  *   Flow matcher value.
7038  * @param[in] item
7039  *   Flow pattern to translate.
7040  * @param[in] inner
7041  *   Item is inner pattern.
7042  */
7043 static void
7044 flow_dv_translate_item_icmp(void *matcher, void *key,
7045                             const struct rte_flow_item *item,
7046                             int inner)
7047 {
7048         const struct rte_flow_item_icmp *icmp_m = item->mask;
7049         const struct rte_flow_item_icmp *icmp_v = item->spec;
7050         void *headers_m;
7051         void *headers_v;
7052         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7053                                      misc_parameters_3);
7054         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7055         if (inner) {
7056                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7057                                          inner_headers);
7058                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7059         } else {
7060                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7061                                          outer_headers);
7062                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7063         }
7064         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7065         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7066         if (!icmp_v)
7067                 return;
7068         if (!icmp_m)
7069                 icmp_m = &rte_flow_item_icmp_mask;
7070         /*
7071          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7072          * If only the protocol is specified, no need to match the frag.
7073          */
7074         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7075         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7076         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7077                  icmp_m->hdr.icmp_type);
7078         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7079                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7080         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7081                  icmp_m->hdr.icmp_code);
7082         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7083                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7084 }
7085
7086 /**
7087  * Add GTP item to matcher and to the value.
7088  *
7089  * @param[in, out] matcher
7090  *   Flow matcher.
7091  * @param[in, out] key
7092  *   Flow matcher value.
7093  * @param[in] item
7094  *   Flow pattern to translate.
7095  * @param[in] inner
7096  *   Item is inner pattern.
7097  */
7098 static void
7099 flow_dv_translate_item_gtp(void *matcher, void *key,
7100                            const struct rte_flow_item *item, int inner)
7101 {
7102         const struct rte_flow_item_gtp *gtp_m = item->mask;
7103         const struct rte_flow_item_gtp *gtp_v = item->spec;
7104         void *headers_m;
7105         void *headers_v;
7106         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7107                                      misc_parameters_3);
7108         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7109         uint16_t dport = RTE_GTPU_UDP_PORT;
7110
7111         if (inner) {
7112                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7113                                          inner_headers);
7114                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7115         } else {
7116                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7117                                          outer_headers);
7118                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7119         }
7120         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7121                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7122                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7123         }
7124         if (!gtp_v)
7125                 return;
7126         if (!gtp_m)
7127                 gtp_m = &rte_flow_item_gtp_mask;
7128         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7129         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7130                  gtp_v->msg_type & gtp_m->msg_type);
7131         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7132                  rte_be_to_cpu_32(gtp_m->teid));
7133         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7134                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7135 }
7136
7137 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7138
7139 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7140         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7141                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7142
7143 /**
7144  * Calculate flow matcher enable bitmap.
7145  *
7146  * @param match_criteria
7147  *   Pointer to flow matcher criteria.
7148  *
7149  * @return
7150  *   Bitmap of enabled fields.
7151  */
7152 static uint8_t
7153 flow_dv_matcher_enable(uint32_t *match_criteria)
7154 {
7155         uint8_t match_criteria_enable;
7156
7157         match_criteria_enable =
7158                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7159                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7160         match_criteria_enable |=
7161                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7162                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7163         match_criteria_enable |=
7164                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7165                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7166         match_criteria_enable |=
7167                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7168                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7169         match_criteria_enable |=
7170                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7171                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7172         return match_criteria_enable;
7173 }
7174
7175
7176 /**
7177  * Get a flow table.
7178  *
7179  * @param[in, out] dev
7180  *   Pointer to rte_eth_dev structure.
7181  * @param[in] table_id
7182  *   Table id to use.
7183  * @param[in] egress
7184  *   Direction of the table.
7185  * @param[in] transfer
7186  *   E-Switch or NIC flow.
7187  * @param[out] error
7188  *   pointer to error structure.
7189  *
7190  * @return
7191  *   Returns tables resource based on the index, NULL in case of failed.
7192  */
7193 static struct mlx5_flow_tbl_resource *
7194 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7195                          uint32_t table_id, uint8_t egress,
7196                          uint8_t transfer,
7197                          struct rte_flow_error *error)
7198 {
7199         struct mlx5_priv *priv = dev->data->dev_private;
7200         struct mlx5_ibv_shared *sh = priv->sh;
7201         struct mlx5_flow_tbl_resource *tbl;
7202         union mlx5_flow_tbl_key table_key = {
7203                 {
7204                         .table_id = table_id,
7205                         .reserved = 0,
7206                         .domain = !!transfer,
7207                         .direction = !!egress,
7208                 }
7209         };
7210         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7211                                                          table_key.v64);
7212         struct mlx5_flow_tbl_data_entry *tbl_data;
7213         uint32_t idx = 0;
7214         int ret;
7215         void *domain;
7216
7217         if (pos) {
7218                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7219                                         entry);
7220                 tbl = &tbl_data->tbl;
7221                 rte_atomic32_inc(&tbl->refcnt);
7222                 return tbl;
7223         }
7224         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7225         if (!tbl_data) {
7226                 rte_flow_error_set(error, ENOMEM,
7227                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7228                                    NULL,
7229                                    "cannot allocate flow table data entry");
7230                 return NULL;
7231         }
7232         tbl_data->idx = idx;
7233         tbl = &tbl_data->tbl;
7234         pos = &tbl_data->entry;
7235         if (transfer)
7236                 domain = sh->fdb_domain;
7237         else if (egress)
7238                 domain = sh->tx_domain;
7239         else
7240                 domain = sh->rx_domain;
7241         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7242         if (!tbl->obj) {
7243                 rte_flow_error_set(error, ENOMEM,
7244                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7245                                    NULL, "cannot create flow table object");
7246                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7247                 return NULL;
7248         }
7249         /*
7250          * No multi-threads now, but still better to initialize the reference
7251          * count before insert it into the hash list.
7252          */
7253         rte_atomic32_init(&tbl->refcnt);
7254         /* Jump action reference count is initialized here. */
7255         rte_atomic32_init(&tbl_data->jump.refcnt);
7256         pos->key = table_key.v64;
7257         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7258         if (ret < 0) {
7259                 rte_flow_error_set(error, -ret,
7260                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7261                                    "cannot insert flow table data entry");
7262                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7263                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7264         }
7265         rte_atomic32_inc(&tbl->refcnt);
7266         return tbl;
7267 }
7268
7269 /**
7270  * Release a flow table.
7271  *
7272  * @param[in] dev
7273  *   Pointer to rte_eth_dev structure.
7274  * @param[in] tbl
7275  *   Table resource to be released.
7276  *
7277  * @return
7278  *   Returns 0 if table was released, else return 1;
7279  */
7280 static int
7281 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7282                              struct mlx5_flow_tbl_resource *tbl)
7283 {
7284         struct mlx5_priv *priv = dev->data->dev_private;
7285         struct mlx5_ibv_shared *sh = priv->sh;
7286         struct mlx5_flow_tbl_data_entry *tbl_data =
7287                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7288
7289         if (!tbl)
7290                 return 0;
7291         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7292                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7293
7294                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7295                 tbl->obj = NULL;
7296                 /* remove the entry from the hash list and free memory. */
7297                 mlx5_hlist_remove(sh->flow_tbls, pos);
7298                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7299                                 tbl_data->idx);
7300                 return 0;
7301         }
7302         return 1;
7303 }
7304
7305 /**
7306  * Register the flow matcher.
7307  *
7308  * @param[in, out] dev
7309  *   Pointer to rte_eth_dev structure.
7310  * @param[in, out] matcher
7311  *   Pointer to flow matcher.
7312  * @param[in, out] key
7313  *   Pointer to flow table key.
7314  * @parm[in, out] dev_flow
7315  *   Pointer to the dev_flow.
7316  * @param[out] error
7317  *   pointer to error structure.
7318  *
7319  * @return
7320  *   0 on success otherwise -errno and errno is set.
7321  */
7322 static int
7323 flow_dv_matcher_register(struct rte_eth_dev *dev,
7324                          struct mlx5_flow_dv_matcher *matcher,
7325                          union mlx5_flow_tbl_key *key,
7326                          struct mlx5_flow *dev_flow,
7327                          struct rte_flow_error *error)
7328 {
7329         struct mlx5_priv *priv = dev->data->dev_private;
7330         struct mlx5_ibv_shared *sh = priv->sh;
7331         struct mlx5_flow_dv_matcher *cache_matcher;
7332         struct mlx5dv_flow_matcher_attr dv_attr = {
7333                 .type = IBV_FLOW_ATTR_NORMAL,
7334                 .match_mask = (void *)&matcher->mask,
7335         };
7336         struct mlx5_flow_tbl_resource *tbl;
7337         struct mlx5_flow_tbl_data_entry *tbl_data;
7338
7339         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7340                                        key->domain, error);
7341         if (!tbl)
7342                 return -rte_errno;      /* No need to refill the error info */
7343         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7344         /* Lookup from cache. */
7345         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7346                 if (matcher->crc == cache_matcher->crc &&
7347                     matcher->priority == cache_matcher->priority &&
7348                     !memcmp((const void *)matcher->mask.buf,
7349                             (const void *)cache_matcher->mask.buf,
7350                             cache_matcher->mask.size)) {
7351                         DRV_LOG(DEBUG,
7352                                 "%s group %u priority %hd use %s "
7353                                 "matcher %p: refcnt %d++",
7354                                 key->domain ? "FDB" : "NIC", key->table_id,
7355                                 cache_matcher->priority,
7356                                 key->direction ? "tx" : "rx",
7357                                 (void *)cache_matcher,
7358                                 rte_atomic32_read(&cache_matcher->refcnt));
7359                         rte_atomic32_inc(&cache_matcher->refcnt);
7360                         dev_flow->handle->dvh.matcher = cache_matcher;
7361                         /* old matcher should not make the table ref++. */
7362                         flow_dv_tbl_resource_release(dev, tbl);
7363                         return 0;
7364                 }
7365         }
7366         /* Register new matcher. */
7367         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7368         if (!cache_matcher) {
7369                 flow_dv_tbl_resource_release(dev, tbl);
7370                 return rte_flow_error_set(error, ENOMEM,
7371                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7372                                           "cannot allocate matcher memory");
7373         }
7374         *cache_matcher = *matcher;
7375         dv_attr.match_criteria_enable =
7376                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7377         dv_attr.priority = matcher->priority;
7378         if (key->direction)
7379                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7380         cache_matcher->matcher_object =
7381                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7382         if (!cache_matcher->matcher_object) {
7383                 rte_free(cache_matcher);
7384 #ifdef HAVE_MLX5DV_DR
7385                 flow_dv_tbl_resource_release(dev, tbl);
7386 #endif
7387                 return rte_flow_error_set(error, ENOMEM,
7388                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7389                                           NULL, "cannot create matcher");
7390         }
7391         /* Save the table information */
7392         cache_matcher->tbl = tbl;
7393         rte_atomic32_init(&cache_matcher->refcnt);
7394         /* only matcher ref++, table ref++ already done above in get API. */
7395         rte_atomic32_inc(&cache_matcher->refcnt);
7396         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7397         dev_flow->handle->dvh.matcher = cache_matcher;
7398         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7399                 key->domain ? "FDB" : "NIC", key->table_id,
7400                 cache_matcher->priority,
7401                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7402                 rte_atomic32_read(&cache_matcher->refcnt));
7403         return 0;
7404 }
7405
7406 /**
7407  * Find existing tag resource or create and register a new one.
7408  *
7409  * @param dev[in, out]
7410  *   Pointer to rte_eth_dev structure.
7411  * @param[in, out] tag_be24
7412  *   Tag value in big endian then R-shift 8.
7413  * @parm[in, out] dev_flow
7414  *   Pointer to the dev_flow.
7415  * @param[out] error
7416  *   pointer to error structure.
7417  *
7418  * @return
7419  *   0 on success otherwise -errno and errno is set.
7420  */
7421 static int
7422 flow_dv_tag_resource_register
7423                         (struct rte_eth_dev *dev,
7424                          uint32_t tag_be24,
7425                          struct mlx5_flow *dev_flow,
7426                          struct rte_flow_error *error)
7427 {
7428         struct mlx5_priv *priv = dev->data->dev_private;
7429         struct mlx5_ibv_shared *sh = priv->sh;
7430         struct mlx5_flow_dv_tag_resource *cache_resource;
7431         struct mlx5_hlist_entry *entry;
7432
7433         /* Lookup a matching resource from cache. */
7434         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7435         if (entry) {
7436                 cache_resource = container_of
7437                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7438                 rte_atomic32_inc(&cache_resource->refcnt);
7439                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7440                 dev_flow->dv.tag_resource = cache_resource;
7441                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7442                         (void *)cache_resource,
7443                         rte_atomic32_read(&cache_resource->refcnt));
7444                 return 0;
7445         }
7446         /* Register new resource. */
7447         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7448                                        &dev_flow->handle->dvh.rix_tag);
7449         if (!cache_resource)
7450                 return rte_flow_error_set(error, ENOMEM,
7451                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7452                                           "cannot allocate resource memory");
7453         cache_resource->entry.key = (uint64_t)tag_be24;
7454         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7455         if (!cache_resource->action) {
7456                 rte_free(cache_resource);
7457                 return rte_flow_error_set(error, ENOMEM,
7458                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7459                                           NULL, "cannot create action");
7460         }
7461         rte_atomic32_init(&cache_resource->refcnt);
7462         rte_atomic32_inc(&cache_resource->refcnt);
7463         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7464                 mlx5_glue->destroy_flow_action(cache_resource->action);
7465                 rte_free(cache_resource);
7466                 return rte_flow_error_set(error, EEXIST,
7467                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7468                                           NULL, "cannot insert tag");
7469         }
7470         dev_flow->dv.tag_resource = cache_resource;
7471         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7472                 (void *)cache_resource,
7473                 rte_atomic32_read(&cache_resource->refcnt));
7474         return 0;
7475 }
7476
7477 /**
7478  * Release the tag.
7479  *
7480  * @param dev
7481  *   Pointer to Ethernet device.
7482  * @param tag_idx
7483  *   Tag index.
7484  *
7485  * @return
7486  *   1 while a reference on it exists, 0 when freed.
7487  */
7488 static int
7489 flow_dv_tag_release(struct rte_eth_dev *dev,
7490                     uint32_t tag_idx)
7491 {
7492         struct mlx5_priv *priv = dev->data->dev_private;
7493         struct mlx5_ibv_shared *sh = priv->sh;
7494         struct mlx5_flow_dv_tag_resource *tag;
7495
7496         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7497         if (!tag)
7498                 return 0;
7499         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7500                 dev->data->port_id, (void *)tag,
7501                 rte_atomic32_read(&tag->refcnt));
7502         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7503                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7504                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7505                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7506                         dev->data->port_id, (void *)tag);
7507                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7508                 return 0;
7509         }
7510         return 1;
7511 }
7512
7513 /**
7514  * Translate port ID action to vport.
7515  *
7516  * @param[in] dev
7517  *   Pointer to rte_eth_dev structure.
7518  * @param[in] action
7519  *   Pointer to the port ID action.
7520  * @param[out] dst_port_id
7521  *   The target port ID.
7522  * @param[out] error
7523  *   Pointer to the error structure.
7524  *
7525  * @return
7526  *   0 on success, a negative errno value otherwise and rte_errno is set.
7527  */
7528 static int
7529 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7530                                  const struct rte_flow_action *action,
7531                                  uint32_t *dst_port_id,
7532                                  struct rte_flow_error *error)
7533 {
7534         uint32_t port;
7535         struct mlx5_priv *priv;
7536         const struct rte_flow_action_port_id *conf =
7537                         (const struct rte_flow_action_port_id *)action->conf;
7538
7539         port = conf->original ? dev->data->port_id : conf->id;
7540         priv = mlx5_port_to_eswitch_info(port, false);
7541         if (!priv)
7542                 return rte_flow_error_set(error, -rte_errno,
7543                                           RTE_FLOW_ERROR_TYPE_ACTION,
7544                                           NULL,
7545                                           "No eswitch info was found for port");
7546 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7547         /*
7548          * This parameter is transferred to
7549          * mlx5dv_dr_action_create_dest_ib_port().
7550          */
7551         *dst_port_id = priv->ibv_port;
7552 #else
7553         /*
7554          * Legacy mode, no LAG configurations is supported.
7555          * This parameter is transferred to
7556          * mlx5dv_dr_action_create_dest_vport().
7557          */
7558         *dst_port_id = priv->vport_id;
7559 #endif
7560         return 0;
7561 }
7562
7563 /**
7564  * Create a counter with aging configuration.
7565  *
7566  * @param[in] dev
7567  *   Pointer to rte_eth_dev structure.
7568  * @param[out] count
7569  *   Pointer to the counter action configuration.
7570  * @param[in] age
7571  *   Pointer to the aging action configuration.
7572  *
7573  * @return
7574  *   Index to flow counter on success, 0 otherwise.
7575  */
7576 static uint32_t
7577 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7578                                 struct mlx5_flow *dev_flow,
7579                                 const struct rte_flow_action_count *count,
7580                                 const struct rte_flow_action_age *age)
7581 {
7582         uint32_t counter;
7583         struct mlx5_age_param *age_param;
7584
7585         counter = flow_dv_counter_alloc(dev,
7586                                 count ? count->shared : 0,
7587                                 count ? count->id : 0,
7588                                 dev_flow->dv.group, !!age);
7589         if (!counter || age == NULL)
7590                 return counter;
7591         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7592         /*
7593          * The counter age accuracy may have a bit delay. Have 3/4
7594          * second bias on the timeount in order to let it age in time.
7595          */
7596         age_param->context = age->context ? age->context :
7597                 (void *)(uintptr_t)(dev_flow->flow_idx);
7598         /*
7599          * The counter age accuracy may have a bit delay. Have 3/4
7600          * second bias on the timeount in order to let it age in time.
7601          */
7602         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7603         /* Set expire time in unit of 0.1 sec. */
7604         age_param->port_id = dev->data->port_id;
7605         age_param->expire = age_param->timeout +
7606                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7607         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7608         return counter;
7609 }
7610 /**
7611  * Add Tx queue matcher
7612  *
7613  * @param[in] dev
7614  *   Pointer to the dev struct.
7615  * @param[in, out] matcher
7616  *   Flow matcher.
7617  * @param[in, out] key
7618  *   Flow matcher value.
7619  * @param[in] item
7620  *   Flow pattern to translate.
7621  * @param[in] inner
7622  *   Item is inner pattern.
7623  */
7624 static void
7625 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7626                                 void *matcher, void *key,
7627                                 const struct rte_flow_item *item)
7628 {
7629         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7630         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7631         void *misc_m =
7632                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7633         void *misc_v =
7634                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7635         struct mlx5_txq_ctrl *txq;
7636         uint32_t queue;
7637
7638
7639         queue_m = (const void *)item->mask;
7640         if (!queue_m)
7641                 return;
7642         queue_v = (const void *)item->spec;
7643         if (!queue_v)
7644                 return;
7645         txq = mlx5_txq_get(dev, queue_v->queue);
7646         if (!txq)
7647                 return;
7648         queue = txq->obj->sq->id;
7649         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7650         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7651                  queue & queue_m->queue);
7652         mlx5_txq_release(dev, queue_v->queue);
7653 }
7654
7655 /**
7656  * Set the hash fields according to the @p flow information.
7657  *
7658  * @param[in] dev_flow
7659  *   Pointer to the mlx5_flow.
7660  * @param[in] rss_desc
7661  *   Pointer to the mlx5_flow_rss_desc.
7662  */
7663 static void
7664 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7665                        struct mlx5_flow_rss_desc *rss_desc)
7666 {
7667         uint64_t items = dev_flow->handle->layers;
7668         int rss_inner = 0;
7669         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7670
7671         dev_flow->hash_fields = 0;
7672 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7673         if (rss_desc->level >= 2) {
7674                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7675                 rss_inner = 1;
7676         }
7677 #endif
7678         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7679             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7680                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7681                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7682                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7683                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7684                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7685                         else
7686                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7687                 }
7688         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7689                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7690                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7691                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7692                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7693                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7694                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7695                         else
7696                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7697                 }
7698         }
7699         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7700             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7701                 if (rss_types & ETH_RSS_UDP) {
7702                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7703                                 dev_flow->hash_fields |=
7704                                                 IBV_RX_HASH_SRC_PORT_UDP;
7705                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7706                                 dev_flow->hash_fields |=
7707                                                 IBV_RX_HASH_DST_PORT_UDP;
7708                         else
7709                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7710                 }
7711         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7712                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7713                 if (rss_types & ETH_RSS_TCP) {
7714                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7715                                 dev_flow->hash_fields |=
7716                                                 IBV_RX_HASH_SRC_PORT_TCP;
7717                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7718                                 dev_flow->hash_fields |=
7719                                                 IBV_RX_HASH_DST_PORT_TCP;
7720                         else
7721                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7722                 }
7723         }
7724 }
7725
7726 /**
7727  * Fill the flow with DV spec, lock free
7728  * (mutex should be acquired by caller).
7729  *
7730  * @param[in] dev
7731  *   Pointer to rte_eth_dev structure.
7732  * @param[in, out] dev_flow
7733  *   Pointer to the sub flow.
7734  * @param[in] attr
7735  *   Pointer to the flow attributes.
7736  * @param[in] items
7737  *   Pointer to the list of items.
7738  * @param[in] actions
7739  *   Pointer to the list of actions.
7740  * @param[out] error
7741  *   Pointer to the error structure.
7742  *
7743  * @return
7744  *   0 on success, a negative errno value otherwise and rte_errno is set.
7745  */
7746 static int
7747 __flow_dv_translate(struct rte_eth_dev *dev,
7748                     struct mlx5_flow *dev_flow,
7749                     const struct rte_flow_attr *attr,
7750                     const struct rte_flow_item items[],
7751                     const struct rte_flow_action actions[],
7752                     struct rte_flow_error *error)
7753 {
7754         struct mlx5_priv *priv = dev->data->dev_private;
7755         struct mlx5_dev_config *dev_conf = &priv->config;
7756         struct rte_flow *flow = dev_flow->flow;
7757         struct mlx5_flow_handle *handle = dev_flow->handle;
7758         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7759                                               priv->rss_desc)
7760                                               [!!priv->flow_nested_idx];
7761         uint64_t item_flags = 0;
7762         uint64_t last_item = 0;
7763         uint64_t action_flags = 0;
7764         uint64_t priority = attr->priority;
7765         struct mlx5_flow_dv_matcher matcher = {
7766                 .mask = {
7767                         .size = sizeof(matcher.mask.buf),
7768                 },
7769         };
7770         int actions_n = 0;
7771         bool actions_end = false;
7772         union {
7773                 struct mlx5_flow_dv_modify_hdr_resource res;
7774                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7775                             sizeof(struct mlx5_modification_cmd) *
7776                             (MLX5_MAX_MODIFY_NUM + 1)];
7777         } mhdr_dummy;
7778         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7779         const struct rte_flow_action_count *count = NULL;
7780         const struct rte_flow_action_age *age = NULL;
7781         union flow_dv_attr flow_attr = { .attr = 0 };
7782         uint32_t tag_be;
7783         union mlx5_flow_tbl_key tbl_key;
7784         uint32_t modify_action_position = UINT32_MAX;
7785         void *match_mask = matcher.mask.buf;
7786         void *match_value = dev_flow->dv.value.buf;
7787         uint8_t next_protocol = 0xff;
7788         struct rte_vlan_hdr vlan = { 0 };
7789         uint32_t table;
7790         int ret = 0;
7791
7792         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7793                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7794         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7795                                        !!priv->fdb_def_rule, &table, error);
7796         if (ret)
7797                 return ret;
7798         dev_flow->dv.group = table;
7799         if (attr->transfer)
7800                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7801         if (priority == MLX5_FLOW_PRIO_RSVD)
7802                 priority = dev_conf->flow_prio - 1;
7803         /* number of actions must be set to 0 in case of dirty stack. */
7804         mhdr_res->actions_num = 0;
7805         for (; !actions_end ; actions++) {
7806                 const struct rte_flow_action_queue *queue;
7807                 const struct rte_flow_action_rss *rss;
7808                 const struct rte_flow_action *action = actions;
7809                 const uint8_t *rss_key;
7810                 const struct rte_flow_action_jump *jump_data;
7811                 const struct rte_flow_action_meter *mtr;
7812                 struct mlx5_flow_tbl_resource *tbl;
7813                 uint32_t port_id = 0;
7814                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7815                 int action_type = actions->type;
7816                 const struct rte_flow_action *found_action = NULL;
7817                 struct mlx5_flow_meter *fm = NULL;
7818
7819                 switch (action_type) {
7820                 case RTE_FLOW_ACTION_TYPE_VOID:
7821                         break;
7822                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7823                         if (flow_dv_translate_action_port_id(dev, action,
7824                                                              &port_id, error))
7825                                 return -rte_errno;
7826                         memset(&port_id_resource, 0, sizeof(port_id_resource));
7827                         port_id_resource.port_id = port_id;
7828                         if (flow_dv_port_id_action_resource_register
7829                             (dev, &port_id_resource, dev_flow, error))
7830                                 return -rte_errno;
7831                         MLX5_ASSERT(!handle->rix_port_id_action);
7832                         dev_flow->dv.actions[actions_n++] =
7833                                         dev_flow->dv.port_id_action->action;
7834                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7835                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7836                         break;
7837                 case RTE_FLOW_ACTION_TYPE_FLAG:
7838                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7839                         dev_flow->handle->mark = 1;
7840                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7841                                 struct rte_flow_action_mark mark = {
7842                                         .id = MLX5_FLOW_MARK_DEFAULT,
7843                                 };
7844
7845                                 if (flow_dv_convert_action_mark(dev, &mark,
7846                                                                 mhdr_res,
7847                                                                 error))
7848                                         return -rte_errno;
7849                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7850                                 break;
7851                         }
7852                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7853                         /*
7854                          * Only one FLAG or MARK is supported per device flow
7855                          * right now. So the pointer to the tag resource must be
7856                          * zero before the register process.
7857                          */
7858                         MLX5_ASSERT(!handle->dvh.rix_tag);
7859                         if (flow_dv_tag_resource_register(dev, tag_be,
7860                                                           dev_flow, error))
7861                                 return -rte_errno;
7862                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7863                         dev_flow->dv.actions[actions_n++] =
7864                                         dev_flow->dv.tag_resource->action;
7865                         break;
7866                 case RTE_FLOW_ACTION_TYPE_MARK:
7867                         action_flags |= MLX5_FLOW_ACTION_MARK;
7868                         dev_flow->handle->mark = 1;
7869                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7870                                 const struct rte_flow_action_mark *mark =
7871                                         (const struct rte_flow_action_mark *)
7872                                                 actions->conf;
7873
7874                                 if (flow_dv_convert_action_mark(dev, mark,
7875                                                                 mhdr_res,
7876                                                                 error))
7877                                         return -rte_errno;
7878                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7879                                 break;
7880                         }
7881                         /* Fall-through */
7882                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7883                         /* Legacy (non-extensive) MARK action. */
7884                         tag_be = mlx5_flow_mark_set
7885                               (((const struct rte_flow_action_mark *)
7886                                (actions->conf))->id);
7887                         MLX5_ASSERT(!handle->dvh.rix_tag);
7888                         if (flow_dv_tag_resource_register(dev, tag_be,
7889                                                           dev_flow, error))
7890                                 return -rte_errno;
7891                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7892                         dev_flow->dv.actions[actions_n++] =
7893                                         dev_flow->dv.tag_resource->action;
7894                         break;
7895                 case RTE_FLOW_ACTION_TYPE_SET_META:
7896                         if (flow_dv_convert_action_set_meta
7897                                 (dev, mhdr_res, attr,
7898                                  (const struct rte_flow_action_set_meta *)
7899                                   actions->conf, error))
7900                                 return -rte_errno;
7901                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7902                         break;
7903                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7904                         if (flow_dv_convert_action_set_tag
7905                                 (dev, mhdr_res,
7906                                  (const struct rte_flow_action_set_tag *)
7907                                   actions->conf, error))
7908                                 return -rte_errno;
7909                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7910                         break;
7911                 case RTE_FLOW_ACTION_TYPE_DROP:
7912                         action_flags |= MLX5_FLOW_ACTION_DROP;
7913                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7914                         break;
7915                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7916                         queue = actions->conf;
7917                         rss_desc->queue_num = 1;
7918                         rss_desc->queue[0] = queue->index;
7919                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7920                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7921                         break;
7922                 case RTE_FLOW_ACTION_TYPE_RSS:
7923                         rss = actions->conf;
7924                         memcpy(rss_desc->queue, rss->queue,
7925                                rss->queue_num * sizeof(uint16_t));
7926                         rss_desc->queue_num = rss->queue_num;
7927                         /* NULL RSS key indicates default RSS key. */
7928                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7929                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7930                         /*
7931                          * rss->level and rss.types should be set in advance
7932                          * when expanding items for RSS.
7933                          */
7934                         action_flags |= MLX5_FLOW_ACTION_RSS;
7935                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7936                         break;
7937                 case RTE_FLOW_ACTION_TYPE_AGE:
7938                 case RTE_FLOW_ACTION_TYPE_COUNT:
7939                         if (!dev_conf->devx) {
7940                                 return rte_flow_error_set
7941                                               (error, ENOTSUP,
7942                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7943                                                NULL,
7944                                                "count action not supported");
7945                         }
7946                         /* Save information first, will apply later. */
7947                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7948                                 count = action->conf;
7949                         else
7950                                 age = action->conf;
7951                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7952                         break;
7953                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7954                         dev_flow->dv.actions[actions_n++] =
7955                                                 priv->sh->pop_vlan_action;
7956                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7957                         break;
7958                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7959                         if (!(action_flags &
7960                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7961                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7962                         vlan.eth_proto = rte_be_to_cpu_16
7963                              ((((const struct rte_flow_action_of_push_vlan *)
7964                                                    actions->conf)->ethertype));
7965                         found_action = mlx5_flow_find_action
7966                                         (actions + 1,
7967                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7968                         if (found_action)
7969                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7970                         found_action = mlx5_flow_find_action
7971                                         (actions + 1,
7972                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7973                         if (found_action)
7974                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7975                         if (flow_dv_create_action_push_vlan
7976                                             (dev, attr, &vlan, dev_flow, error))
7977                                 return -rte_errno;
7978                         dev_flow->dv.actions[actions_n++] =
7979                                         dev_flow->dv.push_vlan_res->action;
7980                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7981                         break;
7982                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7983                         /* of_vlan_push action handled this action */
7984                         MLX5_ASSERT(action_flags &
7985                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7986                         break;
7987                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7988                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7989                                 break;
7990                         flow_dev_get_vlan_info_from_items(items, &vlan);
7991                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7992                         /* If no VLAN push - this is a modify header action */
7993                         if (flow_dv_convert_action_modify_vlan_vid
7994                                                 (mhdr_res, actions, error))
7995                                 return -rte_errno;
7996                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7997                         break;
7998                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7999                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8000                         if (flow_dv_create_action_l2_encap(dev, actions,
8001                                                            dev_flow,
8002                                                            attr->transfer,
8003                                                            error))
8004                                 return -rte_errno;
8005                         dev_flow->dv.actions[actions_n++] =
8006                                         dev_flow->dv.encap_decap->verbs_action;
8007                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8008                         break;
8009                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8010                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8011                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8012                                                            attr->transfer,
8013                                                            error))
8014                                 return -rte_errno;
8015                         dev_flow->dv.actions[actions_n++] =
8016                                         dev_flow->dv.encap_decap->verbs_action;
8017                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8018                         break;
8019                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8020                         /* Handle encap with preceding decap. */
8021                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8022                                 if (flow_dv_create_action_raw_encap
8023                                         (dev, actions, dev_flow, attr, error))
8024                                         return -rte_errno;
8025                                 dev_flow->dv.actions[actions_n++] =
8026                                         dev_flow->dv.encap_decap->verbs_action;
8027                         } else {
8028                                 /* Handle encap without preceding decap. */
8029                                 if (flow_dv_create_action_l2_encap
8030                                     (dev, actions, dev_flow, attr->transfer,
8031                                      error))
8032                                         return -rte_errno;
8033                                 dev_flow->dv.actions[actions_n++] =
8034                                         dev_flow->dv.encap_decap->verbs_action;
8035                         }
8036                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8037                         break;
8038                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8039                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8040                                 ;
8041                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8042                                 if (flow_dv_create_action_l2_decap
8043                                     (dev, dev_flow, attr->transfer, error))
8044                                         return -rte_errno;
8045                                 dev_flow->dv.actions[actions_n++] =
8046                                         dev_flow->dv.encap_decap->verbs_action;
8047                         }
8048                         /* If decap is followed by encap, handle it at encap. */
8049                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8050                         break;
8051                 case RTE_FLOW_ACTION_TYPE_JUMP:
8052                         jump_data = action->conf;
8053                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8054                                                        jump_data->group,
8055                                                        !!priv->fdb_def_rule,
8056                                                        &table, error);
8057                         if (ret)
8058                                 return ret;
8059                         tbl = flow_dv_tbl_resource_get(dev, table,
8060                                                        attr->egress,
8061                                                        attr->transfer, error);
8062                         if (!tbl)
8063                                 return rte_flow_error_set
8064                                                 (error, errno,
8065                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8066                                                  NULL,
8067                                                  "cannot create jump action.");
8068                         if (flow_dv_jump_tbl_resource_register
8069                             (dev, tbl, dev_flow, error)) {
8070                                 flow_dv_tbl_resource_release(dev, tbl);
8071                                 return rte_flow_error_set
8072                                                 (error, errno,
8073                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8074                                                  NULL,
8075                                                  "cannot create jump action.");
8076                         }
8077                         dev_flow->dv.actions[actions_n++] =
8078                                         dev_flow->dv.jump->action;
8079                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8080                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8081                         break;
8082                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8083                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8084                         if (flow_dv_convert_action_modify_mac
8085                                         (mhdr_res, actions, error))
8086                                 return -rte_errno;
8087                         action_flags |= actions->type ==
8088                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8089                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8090                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8091                         break;
8092                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8093                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8094                         if (flow_dv_convert_action_modify_ipv4
8095                                         (mhdr_res, actions, error))
8096                                 return -rte_errno;
8097                         action_flags |= actions->type ==
8098                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8099                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8100                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8101                         break;
8102                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8103                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8104                         if (flow_dv_convert_action_modify_ipv6
8105                                         (mhdr_res, actions, error))
8106                                 return -rte_errno;
8107                         action_flags |= actions->type ==
8108                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8109                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8110                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8111                         break;
8112                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8113                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8114                         if (flow_dv_convert_action_modify_tp
8115                                         (mhdr_res, actions, items,
8116                                          &flow_attr, dev_flow, !!(action_flags &
8117                                          MLX5_FLOW_ACTION_DECAP), error))
8118                                 return -rte_errno;
8119                         action_flags |= actions->type ==
8120                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8121                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8122                                         MLX5_FLOW_ACTION_SET_TP_DST;
8123                         break;
8124                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8125                         if (flow_dv_convert_action_modify_dec_ttl
8126                                         (mhdr_res, items, &flow_attr, dev_flow,
8127                                          !!(action_flags &
8128                                          MLX5_FLOW_ACTION_DECAP), error))
8129                                 return -rte_errno;
8130                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8131                         break;
8132                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8133                         if (flow_dv_convert_action_modify_ttl
8134                                         (mhdr_res, actions, items, &flow_attr,
8135                                          dev_flow, !!(action_flags &
8136                                          MLX5_FLOW_ACTION_DECAP), error))
8137                                 return -rte_errno;
8138                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8139                         break;
8140                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8141                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8142                         if (flow_dv_convert_action_modify_tcp_seq
8143                                         (mhdr_res, actions, error))
8144                                 return -rte_errno;
8145                         action_flags |= actions->type ==
8146                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8147                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8148                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8149                         break;
8150
8151                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8152                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8153                         if (flow_dv_convert_action_modify_tcp_ack
8154                                         (mhdr_res, actions, error))
8155                                 return -rte_errno;
8156                         action_flags |= actions->type ==
8157                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8158                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8159                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8160                         break;
8161                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8162                         if (flow_dv_convert_action_set_reg
8163                                         (mhdr_res, actions, error))
8164                                 return -rte_errno;
8165                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8166                         break;
8167                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8168                         if (flow_dv_convert_action_copy_mreg
8169                                         (dev, mhdr_res, actions, error))
8170                                 return -rte_errno;
8171                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8172                         break;
8173                 case RTE_FLOW_ACTION_TYPE_METER:
8174                         mtr = actions->conf;
8175                         if (!flow->meter) {
8176                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8177                                                             attr, error);
8178                                 if (!fm)
8179                                         return rte_flow_error_set(error,
8180                                                 rte_errno,
8181                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8182                                                 NULL,
8183                                                 "meter not found "
8184                                                 "or invalid parameters");
8185                                 flow->meter = fm->idx;
8186                         }
8187                         /* Set the meter action. */
8188                         if (!fm) {
8189                                 fm = mlx5_ipool_get(priv->sh->ipool
8190                                                 [MLX5_IPOOL_MTR], flow->meter);
8191                                 if (!fm)
8192                                         return rte_flow_error_set(error,
8193                                                 rte_errno,
8194                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8195                                                 NULL,
8196                                                 "meter not found "
8197                                                 "or invalid parameters");
8198                         }
8199                         dev_flow->dv.actions[actions_n++] =
8200                                 fm->mfts->meter_action;
8201                         action_flags |= MLX5_FLOW_ACTION_METER;
8202                         break;
8203                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8204                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8205                                                               actions, error))
8206                                 return -rte_errno;
8207                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8208                         break;
8209                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8210                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8211                                                               actions, error))
8212                                 return -rte_errno;
8213                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8214                         break;
8215                 case RTE_FLOW_ACTION_TYPE_END:
8216                         actions_end = true;
8217                         if (mhdr_res->actions_num) {
8218                                 /* create modify action if needed. */
8219                                 if (flow_dv_modify_hdr_resource_register
8220                                         (dev, mhdr_res, dev_flow, error))
8221                                         return -rte_errno;
8222                                 dev_flow->dv.actions[modify_action_position] =
8223                                         handle->dvh.modify_hdr->verbs_action;
8224                         }
8225                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8226                                 flow->counter =
8227                                         flow_dv_translate_create_counter(dev,
8228                                                 dev_flow, count, age);
8229
8230                                 if (!flow->counter)
8231                                         return rte_flow_error_set
8232                                                 (error, rte_errno,
8233                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8234                                                 NULL,
8235                                                 "cannot create counter"
8236                                                 " object.");
8237                                 dev_flow->dv.actions[actions_n++] =
8238                                           (flow_dv_counter_get_by_idx(dev,
8239                                           flow->counter, NULL))->action;
8240                         }
8241                         break;
8242                 default:
8243                         break;
8244                 }
8245                 if (mhdr_res->actions_num &&
8246                     modify_action_position == UINT32_MAX)
8247                         modify_action_position = actions_n++;
8248         }
8249         dev_flow->dv.actions_n = actions_n;
8250         dev_flow->act_flags = action_flags;
8251         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8252                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8253                 int item_type = items->type;
8254
8255                 switch (item_type) {
8256                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8257                         flow_dv_translate_item_port_id(dev, match_mask,
8258                                                        match_value, items);
8259                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8260                         break;
8261                 case RTE_FLOW_ITEM_TYPE_ETH:
8262                         flow_dv_translate_item_eth(match_mask, match_value,
8263                                                    items, tunnel,
8264                                                    dev_flow->dv.group);
8265                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8266                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8267                                              MLX5_FLOW_LAYER_OUTER_L2;
8268                         break;
8269                 case RTE_FLOW_ITEM_TYPE_VLAN:
8270                         flow_dv_translate_item_vlan(dev_flow,
8271                                                     match_mask, match_value,
8272                                                     items, tunnel,
8273                                                     dev_flow->dv.group);
8274                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8275                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8276                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8277                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8278                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8279                         break;
8280                 case RTE_FLOW_ITEM_TYPE_IPV4:
8281                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8282                                                   &item_flags, &tunnel);
8283                         flow_dv_translate_item_ipv4(match_mask, match_value,
8284                                                     items, item_flags, tunnel,
8285                                                     dev_flow->dv.group);
8286                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8287                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8288                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8289                         if (items->mask != NULL &&
8290                             ((const struct rte_flow_item_ipv4 *)
8291                              items->mask)->hdr.next_proto_id) {
8292                                 next_protocol =
8293                                         ((const struct rte_flow_item_ipv4 *)
8294                                          (items->spec))->hdr.next_proto_id;
8295                                 next_protocol &=
8296                                         ((const struct rte_flow_item_ipv4 *)
8297                                          (items->mask))->hdr.next_proto_id;
8298                         } else {
8299                                 /* Reset for inner layer. */
8300                                 next_protocol = 0xff;
8301                         }
8302                         break;
8303                 case RTE_FLOW_ITEM_TYPE_IPV6:
8304                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8305                                                   &item_flags, &tunnel);
8306                         flow_dv_translate_item_ipv6(match_mask, match_value,
8307                                                     items, item_flags, tunnel,
8308                                                     dev_flow->dv.group);
8309                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8310                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8311                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8312                         if (items->mask != NULL &&
8313                             ((const struct rte_flow_item_ipv6 *)
8314                              items->mask)->hdr.proto) {
8315                                 next_protocol =
8316                                         ((const struct rte_flow_item_ipv6 *)
8317                                          items->spec)->hdr.proto;
8318                                 next_protocol &=
8319                                         ((const struct rte_flow_item_ipv6 *)
8320                                          items->mask)->hdr.proto;
8321                         } else {
8322                                 /* Reset for inner layer. */
8323                                 next_protocol = 0xff;
8324                         }
8325                         break;
8326                 case RTE_FLOW_ITEM_TYPE_TCP:
8327                         flow_dv_translate_item_tcp(match_mask, match_value,
8328                                                    items, tunnel);
8329                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8330                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8331                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8332                         break;
8333                 case RTE_FLOW_ITEM_TYPE_UDP:
8334                         flow_dv_translate_item_udp(match_mask, match_value,
8335                                                    items, tunnel);
8336                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8337                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8338                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8339                         break;
8340                 case RTE_FLOW_ITEM_TYPE_GRE:
8341                         flow_dv_translate_item_gre(match_mask, match_value,
8342                                                    items, tunnel);
8343                         matcher.priority = rss_desc->level >= 2 ?
8344                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8345                         last_item = MLX5_FLOW_LAYER_GRE;
8346                         break;
8347                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8348                         flow_dv_translate_item_gre_key(match_mask,
8349                                                        match_value, items);
8350                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8351                         break;
8352                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8353                         flow_dv_translate_item_nvgre(match_mask, match_value,
8354                                                      items, tunnel);
8355                         matcher.priority = rss_desc->level >= 2 ?
8356                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8357                         last_item = MLX5_FLOW_LAYER_GRE;
8358                         break;
8359                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8360                         flow_dv_translate_item_vxlan(match_mask, match_value,
8361                                                      items, tunnel);
8362                         matcher.priority = rss_desc->level >= 2 ?
8363                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8364                         last_item = MLX5_FLOW_LAYER_VXLAN;
8365                         break;
8366                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8367                         flow_dv_translate_item_vxlan_gpe(match_mask,
8368                                                          match_value, items,
8369                                                          tunnel);
8370                         matcher.priority = rss_desc->level >= 2 ?
8371                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8372                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8373                         break;
8374                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8375                         flow_dv_translate_item_geneve(match_mask, match_value,
8376                                                       items, tunnel);
8377                         matcher.priority = rss_desc->level >= 2 ?
8378                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8379                         last_item = MLX5_FLOW_LAYER_GENEVE;
8380                         break;
8381                 case RTE_FLOW_ITEM_TYPE_MPLS:
8382                         flow_dv_translate_item_mpls(match_mask, match_value,
8383                                                     items, last_item, tunnel);
8384                         matcher.priority = rss_desc->level >= 2 ?
8385                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8386                         last_item = MLX5_FLOW_LAYER_MPLS;
8387                         break;
8388                 case RTE_FLOW_ITEM_TYPE_MARK:
8389                         flow_dv_translate_item_mark(dev, match_mask,
8390                                                     match_value, items);
8391                         last_item = MLX5_FLOW_ITEM_MARK;
8392                         break;
8393                 case RTE_FLOW_ITEM_TYPE_META:
8394                         flow_dv_translate_item_meta(dev, match_mask,
8395                                                     match_value, attr, items);
8396                         last_item = MLX5_FLOW_ITEM_METADATA;
8397                         break;
8398                 case RTE_FLOW_ITEM_TYPE_ICMP:
8399                         flow_dv_translate_item_icmp(match_mask, match_value,
8400                                                     items, tunnel);
8401                         last_item = MLX5_FLOW_LAYER_ICMP;
8402                         break;
8403                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8404                         flow_dv_translate_item_icmp6(match_mask, match_value,
8405                                                       items, tunnel);
8406                         last_item = MLX5_FLOW_LAYER_ICMP6;
8407                         break;
8408                 case RTE_FLOW_ITEM_TYPE_TAG:
8409                         flow_dv_translate_item_tag(dev, match_mask,
8410                                                    match_value, items);
8411                         last_item = MLX5_FLOW_ITEM_TAG;
8412                         break;
8413                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8414                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8415                                                         match_value, items);
8416                         last_item = MLX5_FLOW_ITEM_TAG;
8417                         break;
8418                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8419                         flow_dv_translate_item_tx_queue(dev, match_mask,
8420                                                         match_value,
8421                                                         items);
8422                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8423                         break;
8424                 case RTE_FLOW_ITEM_TYPE_GTP:
8425                         flow_dv_translate_item_gtp(match_mask, match_value,
8426                                                    items, tunnel);
8427                         matcher.priority = rss_desc->level >= 2 ?
8428                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8429                         last_item = MLX5_FLOW_LAYER_GTP;
8430                         break;
8431                 default:
8432                         break;
8433                 }
8434                 item_flags |= last_item;
8435         }
8436         /*
8437          * When E-Switch mode is enabled, we have two cases where we need to
8438          * set the source port manually.
8439          * The first one, is in case of Nic steering rule, and the second is
8440          * E-Switch rule where no port_id item was found. In both cases
8441          * the source port is set according the current port in use.
8442          */
8443         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8444             (priv->representor || priv->master)) {
8445                 if (flow_dv_translate_item_port_id(dev, match_mask,
8446                                                    match_value, NULL))
8447                         return -rte_errno;
8448         }
8449 #ifdef RTE_LIBRTE_MLX5_DEBUG
8450         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8451                                               dev_flow->dv.value.buf));
8452 #endif
8453         /*
8454          * Layers may be already initialized from prefix flow if this dev_flow
8455          * is the suffix flow.
8456          */
8457         handle->layers |= item_flags;
8458         if (action_flags & MLX5_FLOW_ACTION_RSS)
8459                 flow_dv_hashfields_set(dev_flow, rss_desc);
8460         /* Register matcher. */
8461         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8462                                     matcher.mask.size);
8463         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8464                                                      matcher.priority);
8465         /* reserved field no needs to be set to 0 here. */
8466         tbl_key.domain = attr->transfer;
8467         tbl_key.direction = attr->egress;
8468         tbl_key.table_id = dev_flow->dv.group;
8469         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8470                 return -rte_errno;
8471         return 0;
8472 }
8473
8474 /**
8475  * Apply the flow to the NIC, lock free,
8476  * (mutex should be acquired by caller).
8477  *
8478  * @param[in] dev
8479  *   Pointer to the Ethernet device structure.
8480  * @param[in, out] flow
8481  *   Pointer to flow structure.
8482  * @param[out] error
8483  *   Pointer to error structure.
8484  *
8485  * @return
8486  *   0 on success, a negative errno value otherwise and rte_errno is set.
8487  */
8488 static int
8489 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8490                 struct rte_flow_error *error)
8491 {
8492         struct mlx5_flow_dv_workspace *dv;
8493         struct mlx5_flow_handle *dh;
8494         struct mlx5_flow_handle_dv *dv_h;
8495         struct mlx5_flow *dev_flow;
8496         struct mlx5_priv *priv = dev->data->dev_private;
8497         uint32_t handle_idx;
8498         int n;
8499         int err;
8500         int idx;
8501
8502         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8503                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8504                 dv = &dev_flow->dv;
8505                 dh = dev_flow->handle;
8506                 dv_h = &dh->dvh;
8507                 n = dv->actions_n;
8508                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8509                         if (dv->transfer) {
8510                                 dv->actions[n++] = priv->sh->esw_drop_action;
8511                         } else {
8512                                 struct mlx5_hrxq *drop_hrxq;
8513                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8514                                 if (!drop_hrxq) {
8515                                         rte_flow_error_set
8516                                                 (error, errno,
8517                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8518                                                  NULL,
8519                                                  "cannot get drop hash queue");
8520                                         goto error;
8521                                 }
8522                                 /*
8523                                  * Drop queues will be released by the specify
8524                                  * mlx5_hrxq_drop_release() function. Assign
8525                                  * the special index to hrxq to mark the queue
8526                                  * has been allocated.
8527                                  */
8528                                 dh->rix_hrxq = UINT32_MAX;
8529                                 dv->actions[n++] = drop_hrxq->action;
8530                         }
8531                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8532                         struct mlx5_hrxq *hrxq;
8533                         uint32_t hrxq_idx;
8534                         struct mlx5_flow_rss_desc *rss_desc =
8535                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8536                                 [!!priv->flow_nested_idx];
8537
8538                         MLX5_ASSERT(rss_desc->queue_num);
8539                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8540                                                  MLX5_RSS_HASH_KEY_LEN,
8541                                                  dev_flow->hash_fields,
8542                                                  rss_desc->queue,
8543                                                  rss_desc->queue_num);
8544                         if (!hrxq_idx) {
8545                                 hrxq_idx = mlx5_hrxq_new
8546                                                 (dev, rss_desc->key,
8547                                                 MLX5_RSS_HASH_KEY_LEN,
8548                                                 dev_flow->hash_fields,
8549                                                 rss_desc->queue,
8550                                                 rss_desc->queue_num,
8551                                                 !!(dh->layers &
8552                                                 MLX5_FLOW_LAYER_TUNNEL));
8553                         }
8554                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8555                                               hrxq_idx);
8556                         if (!hrxq) {
8557                                 rte_flow_error_set
8558                                         (error, rte_errno,
8559                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8560                                          "cannot get hash queue");
8561                                 goto error;
8562                         }
8563                         dh->rix_hrxq = hrxq_idx;
8564                         dv->actions[n++] = hrxq->action;
8565                 }
8566                 dh->ib_flow =
8567                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8568                                                   (void *)&dv->value, n,
8569                                                   dv->actions);
8570                 if (!dh->ib_flow) {
8571                         rte_flow_error_set(error, errno,
8572                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8573                                            NULL,
8574                                            "hardware refuses to create flow");
8575                         goto error;
8576                 }
8577                 if (priv->vmwa_context &&
8578                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8579                         /*
8580                          * The rule contains the VLAN pattern.
8581                          * For VF we are going to create VLAN
8582                          * interface to make hypervisor set correct
8583                          * e-Switch vport context.
8584                          */
8585                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8586                 }
8587         }
8588         return 0;
8589 error:
8590         err = rte_errno; /* Save rte_errno before cleanup. */
8591         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8592                        handle_idx, dh, next) {
8593                 /* hrxq is union, don't clear it if the flag is not set. */
8594                 if (dh->rix_hrxq) {
8595                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8596                                 mlx5_hrxq_drop_release(dev);
8597                                 dh->rix_hrxq = 0;
8598                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8599                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8600                                 dh->rix_hrxq = 0;
8601                         }
8602                 }
8603                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8604                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8605         }
8606         rte_errno = err; /* Restore rte_errno. */
8607         return -rte_errno;
8608 }
8609
8610 /**
8611  * Release the flow matcher.
8612  *
8613  * @param dev
8614  *   Pointer to Ethernet device.
8615  * @param handle
8616  *   Pointer to mlx5_flow_handle.
8617  *
8618  * @return
8619  *   1 while a reference on it exists, 0 when freed.
8620  */
8621 static int
8622 flow_dv_matcher_release(struct rte_eth_dev *dev,
8623                         struct mlx5_flow_handle *handle)
8624 {
8625         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8626
8627         MLX5_ASSERT(matcher->matcher_object);
8628         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8629                 dev->data->port_id, (void *)matcher,
8630                 rte_atomic32_read(&matcher->refcnt));
8631         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8632                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8633                            (matcher->matcher_object));
8634                 LIST_REMOVE(matcher, next);
8635                 /* table ref-- in release interface. */
8636                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8637                 rte_free(matcher);
8638                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8639                         dev->data->port_id, (void *)matcher);
8640                 return 0;
8641         }
8642         return 1;
8643 }
8644
8645 /**
8646  * Release an encap/decap resource.
8647  *
8648  * @param dev
8649  *   Pointer to Ethernet device.
8650  * @param handle
8651  *   Pointer to mlx5_flow_handle.
8652  *
8653  * @return
8654  *   1 while a reference on it exists, 0 when freed.
8655  */
8656 static int
8657 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8658                                      struct mlx5_flow_handle *handle)
8659 {
8660         struct mlx5_priv *priv = dev->data->dev_private;
8661         uint32_t idx = handle->dvh.rix_encap_decap;
8662         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8663
8664         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8665                          idx);
8666         if (!cache_resource)
8667                 return 0;
8668         MLX5_ASSERT(cache_resource->verbs_action);
8669         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8670                 (void *)cache_resource,
8671                 rte_atomic32_read(&cache_resource->refcnt));
8672         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8673                 claim_zero(mlx5_glue->destroy_flow_action
8674                                 (cache_resource->verbs_action));
8675                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8676                              &priv->sh->encaps_decaps, idx,
8677                              cache_resource, next);
8678                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8679                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8680                         (void *)cache_resource);
8681                 return 0;
8682         }
8683         return 1;
8684 }
8685
8686 /**
8687  * Release an jump to table action resource.
8688  *
8689  * @param dev
8690  *   Pointer to Ethernet device.
8691  * @param handle
8692  *   Pointer to mlx5_flow_handle.
8693  *
8694  * @return
8695  *   1 while a reference on it exists, 0 when freed.
8696  */
8697 static int
8698 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8699                                   struct mlx5_flow_handle *handle)
8700 {
8701         struct mlx5_priv *priv = dev->data->dev_private;
8702         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8703         struct mlx5_flow_tbl_data_entry *tbl_data;
8704
8705         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8706                              handle->rix_jump);
8707         if (!tbl_data)
8708                 return 0;
8709         cache_resource = &tbl_data->jump;
8710         MLX5_ASSERT(cache_resource->action);
8711         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8712                 (void *)cache_resource,
8713                 rte_atomic32_read(&cache_resource->refcnt));
8714         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8715                 claim_zero(mlx5_glue->destroy_flow_action
8716                                 (cache_resource->action));
8717                 /* jump action memory free is inside the table release. */
8718                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8719                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8720                         (void *)cache_resource);
8721                 return 0;
8722         }
8723         return 1;
8724 }
8725
8726 /**
8727  * Release a modify-header resource.
8728  *
8729  * @param handle
8730  *   Pointer to mlx5_flow_handle.
8731  *
8732  * @return
8733  *   1 while a reference on it exists, 0 when freed.
8734  */
8735 static int
8736 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8737 {
8738         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8739                                                         handle->dvh.modify_hdr;
8740
8741         MLX5_ASSERT(cache_resource->verbs_action);
8742         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8743                 (void *)cache_resource,
8744                 rte_atomic32_read(&cache_resource->refcnt));
8745         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8746                 claim_zero(mlx5_glue->destroy_flow_action
8747                                 (cache_resource->verbs_action));
8748                 LIST_REMOVE(cache_resource, next);
8749                 rte_free(cache_resource);
8750                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8751                         (void *)cache_resource);
8752                 return 0;
8753         }
8754         return 1;
8755 }
8756
8757 /**
8758  * Release port ID action resource.
8759  *
8760  * @param dev
8761  *   Pointer to Ethernet device.
8762  * @param handle
8763  *   Pointer to mlx5_flow_handle.
8764  *
8765  * @return
8766  *   1 while a reference on it exists, 0 when freed.
8767  */
8768 static int
8769 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8770                                         struct mlx5_flow_handle *handle)
8771 {
8772         struct mlx5_priv *priv = dev->data->dev_private;
8773         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8774         uint32_t idx = handle->rix_port_id_action;
8775
8776         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8777                                         idx);
8778         if (!cache_resource)
8779                 return 0;
8780         MLX5_ASSERT(cache_resource->action);
8781         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8782                 (void *)cache_resource,
8783                 rte_atomic32_read(&cache_resource->refcnt));
8784         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8785                 claim_zero(mlx5_glue->destroy_flow_action
8786                                 (cache_resource->action));
8787                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8788                              &priv->sh->port_id_action_list, idx,
8789                              cache_resource, next);
8790                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8791                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8792                         (void *)cache_resource);
8793                 return 0;
8794         }
8795         return 1;
8796 }
8797
8798 /**
8799  * Release push vlan action resource.
8800  *
8801  * @param dev
8802  *   Pointer to Ethernet device.
8803  * @param handle
8804  *   Pointer to mlx5_flow_handle.
8805  *
8806  * @return
8807  *   1 while a reference on it exists, 0 when freed.
8808  */
8809 static int
8810 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8811                                           struct mlx5_flow_handle *handle)
8812 {
8813         struct mlx5_priv *priv = dev->data->dev_private;
8814         uint32_t idx = handle->dvh.rix_push_vlan;
8815         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8816
8817         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8818                                         idx);
8819         if (!cache_resource)
8820                 return 0;
8821         MLX5_ASSERT(cache_resource->action);
8822         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8823                 (void *)cache_resource,
8824                 rte_atomic32_read(&cache_resource->refcnt));
8825         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8826                 claim_zero(mlx5_glue->destroy_flow_action
8827                                 (cache_resource->action));
8828                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8829                              &priv->sh->push_vlan_action_list, idx,
8830                              cache_resource, next);
8831                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8832                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8833                         (void *)cache_resource);
8834                 return 0;
8835         }
8836         return 1;
8837 }
8838
8839 /**
8840  * Release the fate resource.
8841  *
8842  * @param dev
8843  *   Pointer to Ethernet device.
8844  * @param handle
8845  *   Pointer to mlx5_flow_handle.
8846  */
8847 static void
8848 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8849                                struct mlx5_flow_handle *handle)
8850 {
8851         if (!handle->rix_fate)
8852                 return;
8853         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8854                 mlx5_hrxq_drop_release(dev);
8855         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8856                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8857         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8858                 flow_dv_jump_tbl_resource_release(dev, handle);
8859         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8860                 flow_dv_port_id_action_resource_release(dev, handle);
8861         else
8862                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8863         handle->rix_fate = 0;
8864 }
8865
8866 /**
8867  * Remove the flow from the NIC but keeps it in memory.
8868  * Lock free, (mutex should be acquired by caller).
8869  *
8870  * @param[in] dev
8871  *   Pointer to Ethernet device.
8872  * @param[in, out] flow
8873  *   Pointer to flow structure.
8874  */
8875 static void
8876 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8877 {
8878         struct mlx5_flow_handle *dh;
8879         uint32_t handle_idx;
8880         struct mlx5_priv *priv = dev->data->dev_private;
8881
8882         if (!flow)
8883                 return;
8884         handle_idx = flow->dev_handles;
8885         while (handle_idx) {
8886                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8887                                     handle_idx);
8888                 if (!dh)
8889                         return;
8890                 if (dh->ib_flow) {
8891                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8892                         dh->ib_flow = NULL;
8893                 }
8894                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8895                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8896                         flow_dv_fate_resource_release(dev, dh);
8897                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8898                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8899                 handle_idx = dh->next.next;
8900         }
8901 }
8902
8903 /**
8904  * Remove the flow from the NIC and the memory.
8905  * Lock free, (mutex should be acquired by caller).
8906  *
8907  * @param[in] dev
8908  *   Pointer to the Ethernet device structure.
8909  * @param[in, out] flow
8910  *   Pointer to flow structure.
8911  */
8912 static void
8913 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8914 {
8915         struct mlx5_flow_handle *dev_handle;
8916         struct mlx5_priv *priv = dev->data->dev_private;
8917
8918         if (!flow)
8919                 return;
8920         __flow_dv_remove(dev, flow);
8921         if (flow->counter) {
8922                 flow_dv_counter_release(dev, flow->counter);
8923                 flow->counter = 0;
8924         }
8925         if (flow->meter) {
8926                 struct mlx5_flow_meter *fm;
8927
8928                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8929                                     flow->meter);
8930                 if (fm)
8931                         mlx5_flow_meter_detach(fm);
8932                 flow->meter = 0;
8933         }
8934         while (flow->dev_handles) {
8935                 uint32_t tmp_idx = flow->dev_handles;
8936
8937                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8938                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8939                 if (!dev_handle)
8940                         return;
8941                 flow->dev_handles = dev_handle->next.next;
8942                 if (dev_handle->dvh.matcher)
8943                         flow_dv_matcher_release(dev, dev_handle);
8944                 if (dev_handle->dvh.rix_encap_decap)
8945                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8946                 if (dev_handle->dvh.modify_hdr)
8947                         flow_dv_modify_hdr_resource_release(dev_handle);
8948                 if (dev_handle->dvh.rix_push_vlan)
8949                         flow_dv_push_vlan_action_resource_release(dev,
8950                                                                   dev_handle);
8951                 if (dev_handle->dvh.rix_tag)
8952                         flow_dv_tag_release(dev,
8953                                             dev_handle->dvh.rix_tag);
8954                 flow_dv_fate_resource_release(dev, dev_handle);
8955                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8956                            tmp_idx);
8957         }
8958 }
8959
8960 /**
8961  * Query a dv flow  rule for its statistics via devx.
8962  *
8963  * @param[in] dev
8964  *   Pointer to Ethernet device.
8965  * @param[in] flow
8966  *   Pointer to the sub flow.
8967  * @param[out] data
8968  *   data retrieved by the query.
8969  * @param[out] error
8970  *   Perform verbose error reporting if not NULL.
8971  *
8972  * @return
8973  *   0 on success, a negative errno value otherwise and rte_errno is set.
8974  */
8975 static int
8976 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8977                     void *data, struct rte_flow_error *error)
8978 {
8979         struct mlx5_priv *priv = dev->data->dev_private;
8980         struct rte_flow_query_count *qc = data;
8981
8982         if (!priv->config.devx)
8983                 return rte_flow_error_set(error, ENOTSUP,
8984                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8985                                           NULL,
8986                                           "counters are not supported");
8987         if (flow->counter) {
8988                 uint64_t pkts, bytes;
8989                 struct mlx5_flow_counter *cnt;
8990
8991                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8992                                                  NULL);
8993                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8994                                                &bytes);
8995
8996                 if (err)
8997                         return rte_flow_error_set(error, -err,
8998                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8999                                         NULL, "cannot read counters");
9000                 qc->hits_set = 1;
9001                 qc->bytes_set = 1;
9002                 qc->hits = pkts - cnt->hits;
9003                 qc->bytes = bytes - cnt->bytes;
9004                 if (qc->reset) {
9005                         cnt->hits = pkts;
9006                         cnt->bytes = bytes;
9007                 }
9008                 return 0;
9009         }
9010         return rte_flow_error_set(error, EINVAL,
9011                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9012                                   NULL,
9013                                   "counters are not available");
9014 }
9015
9016 /**
9017  * Query a flow.
9018  *
9019  * @see rte_flow_query()
9020  * @see rte_flow_ops
9021  */
9022 static int
9023 flow_dv_query(struct rte_eth_dev *dev,
9024               struct rte_flow *flow __rte_unused,
9025               const struct rte_flow_action *actions __rte_unused,
9026               void *data __rte_unused,
9027               struct rte_flow_error *error __rte_unused)
9028 {
9029         int ret = -EINVAL;
9030
9031         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9032                 switch (actions->type) {
9033                 case RTE_FLOW_ACTION_TYPE_VOID:
9034                         break;
9035                 case RTE_FLOW_ACTION_TYPE_COUNT:
9036                         ret = flow_dv_query_count(dev, flow, data, error);
9037                         break;
9038                 default:
9039                         return rte_flow_error_set(error, ENOTSUP,
9040                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9041                                                   actions,
9042                                                   "action not supported");
9043                 }
9044         }
9045         return ret;
9046 }
9047
9048 /**
9049  * Destroy the meter table set.
9050  * Lock free, (mutex should be acquired by caller).
9051  *
9052  * @param[in] dev
9053  *   Pointer to Ethernet device.
9054  * @param[in] tbl
9055  *   Pointer to the meter table set.
9056  *
9057  * @return
9058  *   Always 0.
9059  */
9060 static int
9061 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9062                         struct mlx5_meter_domains_infos *tbl)
9063 {
9064         struct mlx5_priv *priv = dev->data->dev_private;
9065         struct mlx5_meter_domains_infos *mtd =
9066                                 (struct mlx5_meter_domains_infos *)tbl;
9067
9068         if (!mtd || !priv->config.dv_flow_en)
9069                 return 0;
9070         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9071                 claim_zero(mlx5_glue->dv_destroy_flow
9072                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9073         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9074                 claim_zero(mlx5_glue->dv_destroy_flow
9075                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9076         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9077                 claim_zero(mlx5_glue->dv_destroy_flow
9078                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9079         if (mtd->egress.color_matcher)
9080                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9081                           (mtd->egress.color_matcher));
9082         if (mtd->egress.any_matcher)
9083                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9084                           (mtd->egress.any_matcher));
9085         if (mtd->egress.tbl)
9086                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9087         if (mtd->egress.sfx_tbl)
9088                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9089         if (mtd->ingress.color_matcher)
9090                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9091                           (mtd->ingress.color_matcher));
9092         if (mtd->ingress.any_matcher)
9093                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9094                           (mtd->ingress.any_matcher));
9095         if (mtd->ingress.tbl)
9096                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9097         if (mtd->ingress.sfx_tbl)
9098                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9099         if (mtd->transfer.color_matcher)
9100                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9101                           (mtd->transfer.color_matcher));
9102         if (mtd->transfer.any_matcher)
9103                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9104                           (mtd->transfer.any_matcher));
9105         if (mtd->transfer.tbl)
9106                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9107         if (mtd->transfer.sfx_tbl)
9108                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9109         if (mtd->drop_actn)
9110                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9111         rte_free(mtd);
9112         return 0;
9113 }
9114
9115 /* Number of meter flow actions, count and jump or count and drop. */
9116 #define METER_ACTIONS 2
9117
9118 /**
9119  * Create specify domain meter table and suffix table.
9120  *
9121  * @param[in] dev
9122  *   Pointer to Ethernet device.
9123  * @param[in,out] mtb
9124  *   Pointer to DV meter table set.
9125  * @param[in] egress
9126  *   Table attribute.
9127  * @param[in] transfer
9128  *   Table attribute.
9129  * @param[in] color_reg_c_idx
9130  *   Reg C index for color match.
9131  *
9132  * @return
9133  *   0 on success, -1 otherwise and rte_errno is set.
9134  */
9135 static int
9136 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9137                            struct mlx5_meter_domains_infos *mtb,
9138                            uint8_t egress, uint8_t transfer,
9139                            uint32_t color_reg_c_idx)
9140 {
9141         struct mlx5_priv *priv = dev->data->dev_private;
9142         struct mlx5_ibv_shared *sh = priv->sh;
9143         struct mlx5_flow_dv_match_params mask = {
9144                 .size = sizeof(mask.buf),
9145         };
9146         struct mlx5_flow_dv_match_params value = {
9147                 .size = sizeof(value.buf),
9148         };
9149         struct mlx5dv_flow_matcher_attr dv_attr = {
9150                 .type = IBV_FLOW_ATTR_NORMAL,
9151                 .priority = 0,
9152                 .match_criteria_enable = 0,
9153                 .match_mask = (void *)&mask,
9154         };
9155         void *actions[METER_ACTIONS];
9156         struct mlx5_meter_domain_info *dtb;
9157         struct rte_flow_error error;
9158         int i = 0;
9159
9160         if (transfer)
9161                 dtb = &mtb->transfer;
9162         else if (egress)
9163                 dtb = &mtb->egress;
9164         else
9165                 dtb = &mtb->ingress;
9166         /* Create the meter table with METER level. */
9167         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9168                                             egress, transfer, &error);
9169         if (!dtb->tbl) {
9170                 DRV_LOG(ERR, "Failed to create meter policer table.");
9171                 return -1;
9172         }
9173         /* Create the meter suffix table with SUFFIX level. */
9174         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9175                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9176                                             egress, transfer, &error);
9177         if (!dtb->sfx_tbl) {
9178                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9179                 return -1;
9180         }
9181         /* Create matchers, Any and Color. */
9182         dv_attr.priority = 3;
9183         dv_attr.match_criteria_enable = 0;
9184         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9185                                                              &dv_attr,
9186                                                              dtb->tbl->obj);
9187         if (!dtb->any_matcher) {
9188                 DRV_LOG(ERR, "Failed to create meter"
9189                              " policer default matcher.");
9190                 goto error_exit;
9191         }
9192         dv_attr.priority = 0;
9193         dv_attr.match_criteria_enable =
9194                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9195         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9196                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9197         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9198                                                                &dv_attr,
9199                                                                dtb->tbl->obj);
9200         if (!dtb->color_matcher) {
9201                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9202                 goto error_exit;
9203         }
9204         if (mtb->count_actns[RTE_MTR_DROPPED])
9205                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9206         actions[i++] = mtb->drop_actn;
9207         /* Default rule: lowest priority, match any, actions: drop. */
9208         dtb->policer_rules[RTE_MTR_DROPPED] =
9209                         mlx5_glue->dv_create_flow(dtb->any_matcher,
9210                                                  (void *)&value, i, actions);
9211         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9212                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9213                 goto error_exit;
9214         }
9215         return 0;
9216 error_exit:
9217         return -1;
9218 }
9219
9220 /**
9221  * Create the needed meter and suffix tables.
9222  * Lock free, (mutex should be acquired by caller).
9223  *
9224  * @param[in] dev
9225  *   Pointer to Ethernet device.
9226  * @param[in] fm
9227  *   Pointer to the flow meter.
9228  *
9229  * @return
9230  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9231  */
9232 static struct mlx5_meter_domains_infos *
9233 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9234                        const struct mlx5_flow_meter *fm)
9235 {
9236         struct mlx5_priv *priv = dev->data->dev_private;
9237         struct mlx5_meter_domains_infos *mtb;
9238         int ret;
9239         int i;
9240
9241         if (!priv->mtr_en) {
9242                 rte_errno = ENOTSUP;
9243                 return NULL;
9244         }
9245         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9246         if (!mtb) {
9247                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9248                 return NULL;
9249         }
9250         /* Create meter count actions */
9251         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9252                 struct mlx5_flow_counter *cnt;
9253                 if (!fm->policer_stats.cnt[i])
9254                         continue;
9255                 cnt = flow_dv_counter_get_by_idx(dev,
9256                       fm->policer_stats.cnt[i], NULL);
9257                 mtb->count_actns[i] = cnt->action;
9258         }
9259         /* Create drop action. */
9260         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9261         if (!mtb->drop_actn) {
9262                 DRV_LOG(ERR, "Failed to create drop action.");
9263                 goto error_exit;
9264         }
9265         /* Egress meter table. */
9266         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9267         if (ret) {
9268                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9269                 goto error_exit;
9270         }
9271         /* Ingress meter table. */
9272         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9273         if (ret) {
9274                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9275                 goto error_exit;
9276         }
9277         /* FDB meter table. */
9278         if (priv->config.dv_esw_en) {
9279                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9280                                                  priv->mtr_color_reg);
9281                 if (ret) {
9282                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9283                         goto error_exit;
9284                 }
9285         }
9286         return mtb;
9287 error_exit:
9288         flow_dv_destroy_mtr_tbl(dev, mtb);
9289         return NULL;
9290 }
9291
9292 /**
9293  * Destroy domain policer rule.
9294  *
9295  * @param[in] dt
9296  *   Pointer to domain table.
9297  */
9298 static void
9299 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9300 {
9301         int i;
9302
9303         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9304                 if (dt->policer_rules[i]) {
9305                         claim_zero(mlx5_glue->dv_destroy_flow
9306                                   (dt->policer_rules[i]));
9307                         dt->policer_rules[i] = NULL;
9308                 }
9309         }
9310         if (dt->jump_actn) {
9311                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9312                 dt->jump_actn = NULL;
9313         }
9314 }
9315
9316 /**
9317  * Destroy policer rules.
9318  *
9319  * @param[in] dev
9320  *   Pointer to Ethernet device.
9321  * @param[in] fm
9322  *   Pointer to flow meter structure.
9323  * @param[in] attr
9324  *   Pointer to flow attributes.
9325  *
9326  * @return
9327  *   Always 0.
9328  */
9329 static int
9330 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9331                               const struct mlx5_flow_meter *fm,
9332                               const struct rte_flow_attr *attr)
9333 {
9334         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9335
9336         if (!mtb)
9337                 return 0;
9338         if (attr->egress)
9339                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9340         if (attr->ingress)
9341                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9342         if (attr->transfer)
9343                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9344         return 0;
9345 }
9346
9347 /**
9348  * Create specify domain meter policer rule.
9349  *
9350  * @param[in] fm
9351  *   Pointer to flow meter structure.
9352  * @param[in] mtb
9353  *   Pointer to DV meter table set.
9354  * @param[in] mtr_reg_c
9355  *   Color match REG_C.
9356  *
9357  * @return
9358  *   0 on success, -1 otherwise.
9359  */
9360 static int
9361 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9362                                     struct mlx5_meter_domain_info *dtb,
9363                                     uint8_t mtr_reg_c)
9364 {
9365         struct mlx5_flow_dv_match_params matcher = {
9366                 .size = sizeof(matcher.buf),
9367         };
9368         struct mlx5_flow_dv_match_params value = {
9369                 .size = sizeof(value.buf),
9370         };
9371         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9372         void *actions[METER_ACTIONS];
9373         int i;
9374
9375         /* Create jump action. */
9376         if (!dtb->jump_actn)
9377                 dtb->jump_actn =
9378                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9379                                                         (dtb->sfx_tbl->obj);
9380         if (!dtb->jump_actn) {
9381                 DRV_LOG(ERR, "Failed to create policer jump action.");
9382                 goto error;
9383         }
9384         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9385                 int j = 0;
9386
9387                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9388                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9389                 if (mtb->count_actns[i])
9390                         actions[j++] = mtb->count_actns[i];
9391                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9392                         actions[j++] = mtb->drop_actn;
9393                 else
9394                         actions[j++] = dtb->jump_actn;
9395                 dtb->policer_rules[i] =
9396                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9397                                                  (void *)&value,
9398                                                   j, actions);
9399                 if (!dtb->policer_rules[i]) {
9400                         DRV_LOG(ERR, "Failed to create policer rule.");
9401                         goto error;
9402                 }
9403         }
9404         return 0;
9405 error:
9406         rte_errno = errno;
9407         return -1;
9408 }
9409
9410 /**
9411  * Create policer rules.
9412  *
9413  * @param[in] dev
9414  *   Pointer to Ethernet device.
9415  * @param[in] fm
9416  *   Pointer to flow meter structure.
9417  * @param[in] attr
9418  *   Pointer to flow attributes.
9419  *
9420  * @return
9421  *   0 on success, -1 otherwise.
9422  */
9423 static int
9424 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9425                              struct mlx5_flow_meter *fm,
9426                              const struct rte_flow_attr *attr)
9427 {
9428         struct mlx5_priv *priv = dev->data->dev_private;
9429         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9430         int ret;
9431
9432         if (attr->egress) {
9433                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9434                                                 priv->mtr_color_reg);
9435                 if (ret) {
9436                         DRV_LOG(ERR, "Failed to create egress policer.");
9437                         goto error;
9438                 }
9439         }
9440         if (attr->ingress) {
9441                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9442                                                 priv->mtr_color_reg);
9443                 if (ret) {
9444                         DRV_LOG(ERR, "Failed to create ingress policer.");
9445                         goto error;
9446                 }
9447         }
9448         if (attr->transfer) {
9449                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9450                                                 priv->mtr_color_reg);
9451                 if (ret) {
9452                         DRV_LOG(ERR, "Failed to create transfer policer.");
9453                         goto error;
9454                 }
9455         }
9456         return 0;
9457 error:
9458         flow_dv_destroy_policer_rules(dev, fm, attr);
9459         return -1;
9460 }
9461
9462 /**
9463  * Query a devx counter.
9464  *
9465  * @param[in] dev
9466  *   Pointer to the Ethernet device structure.
9467  * @param[in] cnt
9468  *   Index to the flow counter.
9469  * @param[in] clear
9470  *   Set to clear the counter statistics.
9471  * @param[out] pkts
9472  *   The statistics value of packets.
9473  * @param[out] bytes
9474  *   The statistics value of bytes.
9475  *
9476  * @return
9477  *   0 on success, otherwise return -1.
9478  */
9479 static int
9480 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9481                       uint64_t *pkts, uint64_t *bytes)
9482 {
9483         struct mlx5_priv *priv = dev->data->dev_private;
9484         struct mlx5_flow_counter *cnt;
9485         uint64_t inn_pkts, inn_bytes;
9486         int ret;
9487
9488         if (!priv->config.devx)
9489                 return -1;
9490
9491         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9492         if (ret)
9493                 return -1;
9494         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9495         *pkts = inn_pkts - cnt->hits;
9496         *bytes = inn_bytes - cnt->bytes;
9497         if (clear) {
9498                 cnt->hits = inn_pkts;
9499                 cnt->bytes = inn_bytes;
9500         }
9501         return 0;
9502 }
9503
9504 /**
9505  * Get aged-out flows.
9506  *
9507  * @param[in] dev
9508  *   Pointer to the Ethernet device structure.
9509  * @param[in] context
9510  *   The address of an array of pointers to the aged-out flows contexts.
9511  * @param[in] nb_contexts
9512  *   The length of context array pointers.
9513  * @param[out] error
9514  *   Perform verbose error reporting if not NULL. Initialized in case of
9515  *   error only.
9516  *
9517  * @return
9518  *   how many contexts get in success, otherwise negative errno value.
9519  *   if nb_contexts is 0, return the amount of all aged contexts.
9520  *   if nb_contexts is not 0 , return the amount of aged flows reported
9521  *   in the context array.
9522  * @note: only stub for now
9523  */
9524 static int
9525 flow_get_aged_flows(struct rte_eth_dev *dev,
9526                     void **context,
9527                     uint32_t nb_contexts,
9528                     struct rte_flow_error *error)
9529 {
9530         struct mlx5_priv *priv = dev->data->dev_private;
9531         struct mlx5_age_info *age_info;
9532         struct mlx5_age_param *age_param;
9533         struct mlx5_flow_counter *counter;
9534         int nb_flows = 0;
9535
9536         if (nb_contexts && !context)
9537                 return rte_flow_error_set(error, EINVAL,
9538                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9539                                           NULL,
9540                                           "Should assign at least one flow or"
9541                                           " context to get if nb_contexts != 0");
9542         age_info = GET_PORT_AGE_INFO(priv);
9543         rte_spinlock_lock(&age_info->aged_sl);
9544         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9545                 nb_flows++;
9546                 if (nb_contexts) {
9547                         age_param = MLX5_CNT_TO_AGE(counter);
9548                         context[nb_flows - 1] = age_param->context;
9549                         if (!(--nb_contexts))
9550                                 break;
9551                 }
9552         }
9553         rte_spinlock_unlock(&age_info->aged_sl);
9554         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9555         return nb_flows;
9556 }
9557
9558 /*
9559  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9560  */
9561 static int
9562 flow_dv_translate(struct rte_eth_dev *dev,
9563                   struct mlx5_flow *dev_flow,
9564                   const struct rte_flow_attr *attr,
9565                   const struct rte_flow_item items[],
9566                   const struct rte_flow_action actions[],
9567                   struct rte_flow_error *error)
9568 {
9569         int ret;
9570
9571         flow_dv_shared_lock(dev);
9572         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9573         flow_dv_shared_unlock(dev);
9574         return ret;
9575 }
9576
9577 /*
9578  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9579  */
9580 static int
9581 flow_dv_apply(struct rte_eth_dev *dev,
9582               struct rte_flow *flow,
9583               struct rte_flow_error *error)
9584 {
9585         int ret;
9586
9587         flow_dv_shared_lock(dev);
9588         ret = __flow_dv_apply(dev, flow, error);
9589         flow_dv_shared_unlock(dev);
9590         return ret;
9591 }
9592
9593 /*
9594  * Mutex-protected thunk to lock-free __flow_dv_remove().
9595  */
9596 static void
9597 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9598 {
9599         flow_dv_shared_lock(dev);
9600         __flow_dv_remove(dev, flow);
9601         flow_dv_shared_unlock(dev);
9602 }
9603
9604 /*
9605  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9606  */
9607 static void
9608 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9609 {
9610         flow_dv_shared_lock(dev);
9611         __flow_dv_destroy(dev, flow);
9612         flow_dv_shared_unlock(dev);
9613 }
9614
9615 /*
9616  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9617  */
9618 static uint32_t
9619 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9620 {
9621         uint32_t cnt;
9622
9623         flow_dv_shared_lock(dev);
9624         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9625         flow_dv_shared_unlock(dev);
9626         return cnt;
9627 }
9628
9629 /*
9630  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9631  */
9632 static void
9633 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9634 {
9635         flow_dv_shared_lock(dev);
9636         flow_dv_counter_release(dev, cnt);
9637         flow_dv_shared_unlock(dev);
9638 }
9639
9640 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9641         .validate = flow_dv_validate,
9642         .prepare = flow_dv_prepare,
9643         .translate = flow_dv_translate,
9644         .apply = flow_dv_apply,
9645         .remove = flow_dv_remove,
9646         .destroy = flow_dv_destroy,
9647         .query = flow_dv_query,
9648         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9649         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9650         .create_policer_rules = flow_dv_create_policer_rules,
9651         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9652         .counter_alloc = flow_dv_counter_allocate,
9653         .counter_free = flow_dv_counter_free,
9654         .counter_query = flow_dv_counter_query,
9655         .get_aged_flows = flow_get_aged_flows,
9656 };
9657
9658 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */