drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30
  31 #include "mlx5.h"
  32 #include "mlx5_defs.h"
  33 #include "mlx5_glue.h"
  34 #include "mlx5_flow.h"
  35 #include "mlx5_prm.h"
  36 #include "mlx5_rxtx.h"
  37
  38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 /**
  74  * Initialize flow attributes structure according to flow items' types.
  75  *
  76  * @param[in] item
  77  *   Pointer to item specification.
  78  * @param[out] attr
  79  *   Pointer to flow attributes structure.
  80  */
  81 static void
  82 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
  83 {
  84         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
  85                 switch (item->type) {
  86                 case RTE_FLOW_ITEM_TYPE_IPV4:
  87                         attr->ipv4 = 1;
  88                         break;
  89                 case RTE_FLOW_ITEM_TYPE_IPV6:
  90                         attr->ipv6 = 1;
  91                         break;
  92                 case RTE_FLOW_ITEM_TYPE_UDP:
  93                         attr->udp = 1;
  94                         break;
  95                 case RTE_FLOW_ITEM_TYPE_TCP:
  96                         attr->tcp = 1;
  97                         break;
  98                 default:
  99                         break;
 100                 }
 101         }
 102         attr->valid = 1;
 103 }
 104
 105 struct field_modify_info {
 106         uint32_t size; /* Size of field in protocol header, in bytes. */
 107         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 108         enum mlx5_modification_field id;
 109 };
 110
 111 struct field_modify_info modify_eth[] = {
 112         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 113         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 114         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 115         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 116         {0, 0, 0},
 117 };
 118
 119 struct field_modify_info modify_vlan_out_first_vid[] = {
 120         /* Size in bits !!! */
 121         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 122         {0, 0, 0},
 123 };
 124
 125 struct field_modify_info modify_ipv4[] = {
 126         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 127         {4, 12, MLX5_MODI_OUT_SIPV4},
 128         {4, 16, MLX5_MODI_OUT_DIPV4},
 129         {0, 0, 0},
 130 };
 131
 132 struct field_modify_info modify_ipv6[] = {
 133         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 134         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 135         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 136         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 137         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 138         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 139         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 140         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 141         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 142         {0, 0, 0},
 143 };
 144
 145 struct field_modify_info modify_udp[] = {
 146         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 147         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 148         {0, 0, 0},
 149 };
 150
 151 struct field_modify_info modify_tcp[] = {
 152         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 153         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 154         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 155         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 156         {0, 0, 0},
 157 };
 158
 159 static void
 160 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 161                           uint8_t next_protocol, uint64_t *item_flags,
 162                           int *tunnel)
 163 {
 164         assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 165                item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 166         if (next_protocol == IPPROTO_IPIP) {
 167                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 168                 *tunnel = 1;
 169         }
 170         if (next_protocol == IPPROTO_IPV6) {
 171                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 172                 *tunnel = 1;
 173         }
 174 }
 175
 176 /**
 177  * Acquire the synchronizing object to protect multithreaded access
 178  * to shared dv context. Lock occurs only if context is actually
 179  * shared, i.e. we have multiport IB device and representors are
 180  * created.
 181  *
 182  * @param[in] dev
 183  *   Pointer to the rte_eth_dev structure.
 184  */
 185 static void
 186 flow_dv_shared_lock(struct rte_eth_dev *dev)
 187 {
 188         struct mlx5_priv *priv = dev->data->dev_private;
 189         struct mlx5_ibv_shared *sh = priv->sh;
 190
 191         if (sh->dv_refcnt > 1) {
 192                 int ret;
 193
 194                 ret = pthread_mutex_lock(&sh->dv_mutex);
 195                 assert(!ret);
 196                 (void)ret;
 197         }
 198 }
 199
 200 static void
 201 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 202 {
 203         struct mlx5_priv *priv = dev->data->dev_private;
 204         struct mlx5_ibv_shared *sh = priv->sh;
 205
 206         if (sh->dv_refcnt > 1) {
 207                 int ret;
 208
 209                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 210                 assert(!ret);
 211                 (void)ret;
 212         }
 213 }
 214
 215 /* Update VLAN's VID/PCP based on input rte_flow_action.
 216  *
 217  * @param[in] action
 218  *   Pointer to struct rte_flow_action.
 219  * @param[out] vlan
 220  *   Pointer to struct rte_vlan_hdr.
 221  */
 222 static void
 223 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 224                          struct rte_vlan_hdr *vlan)
 225 {
 226         uint16_t vlan_tci;
 227         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 228                 vlan_tci =
 229                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 230                                                action->conf)->vlan_pcp;
 231                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 232                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 233                 vlan->vlan_tci |= vlan_tci;
 234         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 235                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 236                 vlan->vlan_tci |= rte_be_to_cpu_16
 237                     (((const struct rte_flow_action_of_set_vlan_vid *)
 238                                              action->conf)->vlan_vid);
 239         }
 240 }
 241
 242 /**
 243  * Fetch 1, 2, 3 or 4 byte field from the byte array
 244  * and return as unsigned integer in host-endian format.
 245  *
 246  * @param[in] data
 247  *   Pointer to data array.
 248  * @param[in] size
 249  *   Size of field to extract.
 250  *
 251  * @return
 252  *   converted field in host endian format.
 253  */
 254 static inline uint32_t
 255 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 256 {
 257         uint32_t ret;
 258
 259         switch (size) {
 260         case 1:
 261                 ret = *data;
 262                 break;
 263         case 2:
 264                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 265                 break;
 266         case 3:
 267                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 268                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 269                 break;
 270         case 4:
 271                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 272                 break;
 273         default:
 274                 assert(false);
 275                 ret = 0;
 276                 break;
 277         }
 278         return ret;
 279 }
 280
 281 /**
 282  * Convert modify-header action to DV specification.
 283  *
 284  * Data length of each action is determined by provided field description
 285  * and the item mask. Data bit offset and width of each action is determined
 286  * by provided item mask.
 287  *
 288  * @param[in] item
 289  *   Pointer to item specification.
 290  * @param[in] field
 291  *   Pointer to field modification information.
 292  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 293  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 294  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 295  * @param[in] dcopy
 296  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 297  *   Negative offset value sets the same offset as source offset.
 298  *   size field is ignored, value is taken from source field.
 299  * @param[in,out] resource
 300  *   Pointer to the modify-header resource.
 301  * @param[in] type
 302  *   Type of modification.
 303  * @param[out] error
 304  *   Pointer to the error structure.
 305  *
 306  * @return
 307  *   0 on success, a negative errno value otherwise and rte_errno is set.
 308  */
 309 static int
 310 flow_dv_convert_modify_action(struct rte_flow_item *item,
 311                               struct field_modify_info *field,
 312                               struct field_modify_info *dcopy,
 313                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 314                               uint32_t type, struct rte_flow_error *error)
 315 {
 316         uint32_t i = resource->actions_num;
 317         struct mlx5_modification_cmd *actions = resource->actions;
 318
 319         /*
 320          * The item and mask are provided in big-endian format.
 321          * The fields should be presented as in big-endian format either.
 322          * Mask must be always present, it defines the actual field width.
 323          */
 324         assert(item->mask);
 325         assert(field->size);
 326         do {
 327                 unsigned int size_b;
 328                 unsigned int off_b;
 329                 uint32_t mask;
 330                 uint32_t data;
 331
 332                 if (i >= MLX5_MODIFY_NUM)
 333                         return rte_flow_error_set(error, EINVAL,
 334                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 335                                  "too many items to modify");
 336                 /* Fetch variable byte size mask from the array. */
 337                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 338                                            field->offset, field->size);
 339                 if (!mask) {
 340                         ++field;
 341                         continue;
 342                 }
 343                 /* Deduce actual data width in bits from mask value. */
 344                 off_b = rte_bsf32(mask);
 345                 size_b = sizeof(uint32_t) * CHAR_BIT -
 346                          off_b - __builtin_clz(mask);
 347                 assert(size_b);
 348                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 349                 actions[i].action_type = type;
 350                 actions[i].field = field->id;
 351                 actions[i].offset = off_b;
 352                 actions[i].length = size_b;
 353                 /* Convert entire record to expected big-endian format. */
 354                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 355                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 356                         assert(dcopy);
 357                         actions[i].dst_field = dcopy->id;
 358                         actions[i].dst_offset =
 359                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 360                         /* Convert entire record to big-endian format. */
 361                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 362                 } else {
 363                         assert(item->spec);
 364                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 365                                                    field->offset, field->size);
 366                         /* Shift out the trailing masked bits from data. */
 367                         data = (data & mask) >> off_b;
 368                         actions[i].data1 = rte_cpu_to_be_32(data);
 369                 }
 370                 ++i;
 371                 ++field;
 372         } while (field->size);
 373         resource->actions_num = i;
 374         if (!resource->actions_num)
 375                 return rte_flow_error_set(error, EINVAL,
 376                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 377                                           "invalid modification flow item");
 378         return 0;
 379 }
 380
 381 /**
 382  * Convert modify-header set IPv4 address action to DV specification.
 383  *
 384  * @param[in,out] resource
 385  *   Pointer to the modify-header resource.
 386  * @param[in] action
 387  *   Pointer to action specification.
 388  * @param[out] error
 389  *   Pointer to the error structure.
 390  *
 391  * @return
 392  *   0 on success, a negative errno value otherwise and rte_errno is set.
 393  */
 394 static int
 395 flow_dv_convert_action_modify_ipv4
 396                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 397                          const struct rte_flow_action *action,
 398                          struct rte_flow_error *error)
 399 {
 400         const struct rte_flow_action_set_ipv4 *conf =
 401                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 402         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 403         struct rte_flow_item_ipv4 ipv4;
 404         struct rte_flow_item_ipv4 ipv4_mask;
 405
 406         memset(&ipv4, 0, sizeof(ipv4));
 407         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 408         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 409                 ipv4.hdr.src_addr = conf->ipv4_addr;
 410                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 411         } else {
 412                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 413                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 414         }
 415         item.spec = &ipv4;
 416         item.mask = &ipv4_mask;
 417         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 418                                              MLX5_MODIFICATION_TYPE_SET, error);
 419 }
 420
 421 /**
 422  * Convert modify-header set IPv6 address action to DV specification.
 423  *
 424  * @param[in,out] resource
 425  *   Pointer to the modify-header resource.
 426  * @param[in] action
 427  *   Pointer to action specification.
 428  * @param[out] error
 429  *   Pointer to the error structure.
 430  *
 431  * @return
 432  *   0 on success, a negative errno value otherwise and rte_errno is set.
 433  */
 434 static int
 435 flow_dv_convert_action_modify_ipv6
 436                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 437                          const struct rte_flow_action *action,
 438                          struct rte_flow_error *error)
 439 {
 440         const struct rte_flow_action_set_ipv6 *conf =
 441                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 442         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 443         struct rte_flow_item_ipv6 ipv6;
 444         struct rte_flow_item_ipv6 ipv6_mask;
 445
 446         memset(&ipv6, 0, sizeof(ipv6));
 447         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 448         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 449                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 450                        sizeof(ipv6.hdr.src_addr));
 451                 memcpy(&ipv6_mask.hdr.src_addr,
 452                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 453                        sizeof(ipv6.hdr.src_addr));
 454         } else {
 455                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 456                        sizeof(ipv6.hdr.dst_addr));
 457                 memcpy(&ipv6_mask.hdr.dst_addr,
 458                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 459                        sizeof(ipv6.hdr.dst_addr));
 460         }
 461         item.spec = &ipv6;
 462         item.mask = &ipv6_mask;
 463         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 464                                              MLX5_MODIFICATION_TYPE_SET, error);
 465 }
 466
 467 /**
 468  * Convert modify-header set MAC address action to DV specification.
 469  *
 470  * @param[in,out] resource
 471  *   Pointer to the modify-header resource.
 472  * @param[in] action
 473  *   Pointer to action specification.
 474  * @param[out] error
 475  *   Pointer to the error structure.
 476  *
 477  * @return
 478  *   0 on success, a negative errno value otherwise and rte_errno is set.
 479  */
 480 static int
 481 flow_dv_convert_action_modify_mac
 482                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 483                          const struct rte_flow_action *action,
 484                          struct rte_flow_error *error)
 485 {
 486         const struct rte_flow_action_set_mac *conf =
 487                 (const struct rte_flow_action_set_mac *)(action->conf);
 488         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 489         struct rte_flow_item_eth eth;
 490         struct rte_flow_item_eth eth_mask;
 491
 492         memset(&eth, 0, sizeof(eth));
 493         memset(&eth_mask, 0, sizeof(eth_mask));
 494         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 495                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 496                        sizeof(eth.src.addr_bytes));
 497                 memcpy(&eth_mask.src.addr_bytes,
 498                        &rte_flow_item_eth_mask.src.addr_bytes,
 499                        sizeof(eth_mask.src.addr_bytes));
 500         } else {
 501                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 502                        sizeof(eth.dst.addr_bytes));
 503                 memcpy(&eth_mask.dst.addr_bytes,
 504                        &rte_flow_item_eth_mask.dst.addr_bytes,
 505                        sizeof(eth_mask.dst.addr_bytes));
 506         }
 507         item.spec = &eth;
 508         item.mask = &eth_mask;
 509         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 510                                              MLX5_MODIFICATION_TYPE_SET, error);
 511 }
 512
 513 /**
 514  * Convert modify-header set VLAN VID action to DV specification.
 515  *
 516  * @param[in,out] resource
 517  *   Pointer to the modify-header resource.
 518  * @param[in] action
 519  *   Pointer to action specification.
 520  * @param[out] error
 521  *   Pointer to the error structure.
 522  *
 523  * @return
 524  *   0 on success, a negative errno value otherwise and rte_errno is set.
 525  */
 526 static int
 527 flow_dv_convert_action_modify_vlan_vid
 528                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 529                          const struct rte_flow_action *action,
 530                          struct rte_flow_error *error)
 531 {
 532         const struct rte_flow_action_of_set_vlan_vid *conf =
 533                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 534         int i = resource->actions_num;
 535         struct mlx5_modification_cmd *actions = &resource->actions[i];
 536         struct field_modify_info *field = modify_vlan_out_first_vid;
 537
 538         if (i >= MLX5_MODIFY_NUM)
 539                 return rte_flow_error_set(error, EINVAL,
 540                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 541                          "too many items to modify");
 542         actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
 543         actions[i].field = field->id;
 544         actions[i].length = field->size;
 545         actions[i].offset = field->offset;
 546         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 547         actions[i].data1 = conf->vlan_vid;
 548         actions[i].data1 = actions[i].data1 << 16;
 549         resource->actions_num = ++i;
 550         return 0;
 551 }
 552
 553 /**
 554  * Convert modify-header set TP action to DV specification.
 555  *
 556  * @param[in,out] resource
 557  *   Pointer to the modify-header resource.
 558  * @param[in] action
 559  *   Pointer to action specification.
 560  * @param[in] items
 561  *   Pointer to rte_flow_item objects list.
 562  * @param[in] attr
 563  *   Pointer to flow attributes structure.
 564  * @param[out] error
 565  *   Pointer to the error structure.
 566  *
 567  * @return
 568  *   0 on success, a negative errno value otherwise and rte_errno is set.
 569  */
 570 static int
 571 flow_dv_convert_action_modify_tp
 572                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 573                          const struct rte_flow_action *action,
 574                          const struct rte_flow_item *items,
 575                          union flow_dv_attr *attr,
 576                          struct rte_flow_error *error)
 577 {
 578         const struct rte_flow_action_set_tp *conf =
 579                 (const struct rte_flow_action_set_tp *)(action->conf);
 580         struct rte_flow_item item;
 581         struct rte_flow_item_udp udp;
 582         struct rte_flow_item_udp udp_mask;
 583         struct rte_flow_item_tcp tcp;
 584         struct rte_flow_item_tcp tcp_mask;
 585         struct field_modify_info *field;
 586
 587         if (!attr->valid)
 588                 flow_dv_attr_init(items, attr);
 589         if (attr->udp) {
 590                 memset(&udp, 0, sizeof(udp));
 591                 memset(&udp_mask, 0, sizeof(udp_mask));
 592                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 593                         udp.hdr.src_port = conf->port;
 594                         udp_mask.hdr.src_port =
 595                                         rte_flow_item_udp_mask.hdr.src_port;
 596                 } else {
 597                         udp.hdr.dst_port = conf->port;
 598                         udp_mask.hdr.dst_port =
 599                                         rte_flow_item_udp_mask.hdr.dst_port;
 600                 }
 601                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 602                 item.spec = &udp;
 603                 item.mask = &udp_mask;
 604                 field = modify_udp;
 605         }
 606         if (attr->tcp) {
 607                 memset(&tcp, 0, sizeof(tcp));
 608                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 609                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 610                         tcp.hdr.src_port = conf->port;
 611                         tcp_mask.hdr.src_port =
 612                                         rte_flow_item_tcp_mask.hdr.src_port;
 613                 } else {
 614                         tcp.hdr.dst_port = conf->port;
 615                         tcp_mask.hdr.dst_port =
 616                                         rte_flow_item_tcp_mask.hdr.dst_port;
 617                 }
 618                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 619                 item.spec = &tcp;
 620                 item.mask = &tcp_mask;
 621                 field = modify_tcp;
 622         }
 623         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 624                                              MLX5_MODIFICATION_TYPE_SET, error);
 625 }
 626
 627 /**
 628  * Convert modify-header set TTL action to DV specification.
 629  *
 630  * @param[in,out] resource
 631  *   Pointer to the modify-header resource.
 632  * @param[in] action
 633  *   Pointer to action specification.
 634  * @param[in] items
 635  *   Pointer to rte_flow_item objects list.
 636  * @param[in] attr
 637  *   Pointer to flow attributes structure.
 638  * @param[out] error
 639  *   Pointer to the error structure.
 640  *
 641  * @return
 642  *   0 on success, a negative errno value otherwise and rte_errno is set.
 643  */
 644 static int
 645 flow_dv_convert_action_modify_ttl
 646                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 647                          const struct rte_flow_action *action,
 648                          const struct rte_flow_item *items,
 649                          union flow_dv_attr *attr,
 650                          struct rte_flow_error *error)
 651 {
 652         const struct rte_flow_action_set_ttl *conf =
 653                 (const struct rte_flow_action_set_ttl *)(action->conf);
 654         struct rte_flow_item item;
 655         struct rte_flow_item_ipv4 ipv4;
 656         struct rte_flow_item_ipv4 ipv4_mask;
 657         struct rte_flow_item_ipv6 ipv6;
 658         struct rte_flow_item_ipv6 ipv6_mask;
 659         struct field_modify_info *field;
 660
 661         if (!attr->valid)
 662                 flow_dv_attr_init(items, attr);
 663         if (attr->ipv4) {
 664                 memset(&ipv4, 0, sizeof(ipv4));
 665                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 666                 ipv4.hdr.time_to_live = conf->ttl_value;
 667                 ipv4_mask.hdr.time_to_live = 0xFF;
 668                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 669                 item.spec = &ipv4;
 670                 item.mask = &ipv4_mask;
 671                 field = modify_ipv4;
 672         }
 673         if (attr->ipv6) {
 674                 memset(&ipv6, 0, sizeof(ipv6));
 675                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 676                 ipv6.hdr.hop_limits = conf->ttl_value;
 677                 ipv6_mask.hdr.hop_limits = 0xFF;
 678                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 679                 item.spec = &ipv6;
 680                 item.mask = &ipv6_mask;
 681                 field = modify_ipv6;
 682         }
 683         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 684                                              MLX5_MODIFICATION_TYPE_SET, error);
 685 }
 686
 687 /**
 688  * Convert modify-header decrement TTL action to DV specification.
 689  *
 690  * @param[in,out] resource
 691  *   Pointer to the modify-header resource.
 692  * @param[in] action
 693  *   Pointer to action specification.
 694  * @param[in] items
 695  *   Pointer to rte_flow_item objects list.
 696  * @param[in] attr
 697  *   Pointer to flow attributes structure.
 698  * @param[out] error
 699  *   Pointer to the error structure.
 700  *
 701  * @return
 702  *   0 on success, a negative errno value otherwise and rte_errno is set.
 703  */
 704 static int
 705 flow_dv_convert_action_modify_dec_ttl
 706                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 707                          const struct rte_flow_item *items,
 708                          union flow_dv_attr *attr,
 709                          struct rte_flow_error *error)
 710 {
 711         struct rte_flow_item item;
 712         struct rte_flow_item_ipv4 ipv4;
 713         struct rte_flow_item_ipv4 ipv4_mask;
 714         struct rte_flow_item_ipv6 ipv6;
 715         struct rte_flow_item_ipv6 ipv6_mask;
 716         struct field_modify_info *field;
 717
 718         if (!attr->valid)
 719                 flow_dv_attr_init(items, attr);
 720         if (attr->ipv4) {
 721                 memset(&ipv4, 0, sizeof(ipv4));
 722                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 723                 ipv4.hdr.time_to_live = 0xFF;
 724                 ipv4_mask.hdr.time_to_live = 0xFF;
 725                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 726                 item.spec = &ipv4;
 727                 item.mask = &ipv4_mask;
 728                 field = modify_ipv4;
 729         }
 730         if (attr->ipv6) {
 731                 memset(&ipv6, 0, sizeof(ipv6));
 732                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 733                 ipv6.hdr.hop_limits = 0xFF;
 734                 ipv6_mask.hdr.hop_limits = 0xFF;
 735                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 736                 item.spec = &ipv6;
 737                 item.mask = &ipv6_mask;
 738                 field = modify_ipv6;
 739         }
 740         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 741                                              MLX5_MODIFICATION_TYPE_ADD, error);
 742 }
 743
 744 /**
 745  * Convert modify-header increment/decrement TCP Sequence number
 746  * to DV specification.
 747  *
 748  * @param[in,out] resource
 749  *   Pointer to the modify-header resource.
 750  * @param[in] action
 751  *   Pointer to action specification.
 752  * @param[out] error
 753  *   Pointer to the error structure.
 754  *
 755  * @return
 756  *   0 on success, a negative errno value otherwise and rte_errno is set.
 757  */
 758 static int
 759 flow_dv_convert_action_modify_tcp_seq
 760                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 761                          const struct rte_flow_action *action,
 762                          struct rte_flow_error *error)
 763 {
 764         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 765         uint64_t value = rte_be_to_cpu_32(*conf);
 766         struct rte_flow_item item;
 767         struct rte_flow_item_tcp tcp;
 768         struct rte_flow_item_tcp tcp_mask;
 769
 770         memset(&tcp, 0, sizeof(tcp));
 771         memset(&tcp_mask, 0, sizeof(tcp_mask));
 772         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 773                 /*
 774                  * The HW has no decrement operation, only increment operation.
 775                  * To simulate decrement X from Y using increment operation
 776                  * we need to add UINT32_MAX X times to Y.
 777                  * Each adding of UINT32_MAX decrements Y by 1.
 778                  */
 779                 value *= UINT32_MAX;
 780         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 781         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 782         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 783         item.spec = &tcp;
 784         item.mask = &tcp_mask;
 785         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 786                                              MLX5_MODIFICATION_TYPE_ADD, error);
 787 }
 788
 789 /**
 790  * Convert modify-header increment/decrement TCP Acknowledgment number
 791  * to DV specification.
 792  *
 793  * @param[in,out] resource
 794  *   Pointer to the modify-header resource.
 795  * @param[in] action
 796  *   Pointer to action specification.
 797  * @param[out] error
 798  *   Pointer to the error structure.
 799  *
 800  * @return
 801  *   0 on success, a negative errno value otherwise and rte_errno is set.
 802  */
 803 static int
 804 flow_dv_convert_action_modify_tcp_ack
 805                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 806                          const struct rte_flow_action *action,
 807                          struct rte_flow_error *error)
 808 {
 809         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 810         uint64_t value = rte_be_to_cpu_32(*conf);
 811         struct rte_flow_item item;
 812         struct rte_flow_item_tcp tcp;
 813         struct rte_flow_item_tcp tcp_mask;
 814
 815         memset(&tcp, 0, sizeof(tcp));
 816         memset(&tcp_mask, 0, sizeof(tcp_mask));
 817         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 818                 /*
 819                  * The HW has no decrement operation, only increment operation.
 820                  * To simulate decrement X from Y using increment operation
 821                  * we need to add UINT32_MAX X times to Y.
 822                  * Each adding of UINT32_MAX decrements Y by 1.
 823                  */
 824                 value *= UINT32_MAX;
 825         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 826         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 827         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 828         item.spec = &tcp;
 829         item.mask = &tcp_mask;
 830         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 831                                              MLX5_MODIFICATION_TYPE_ADD, error);
 832 }
 833
 834 static enum mlx5_modification_field reg_to_field[] = {
 835         [REG_NONE] = MLX5_MODI_OUT_NONE,
 836         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 837         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 838         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 839         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 840         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 841         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 842         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 843         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 844         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 845         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 846 };
 847
 848 /**
 849  * Convert register set to DV specification.
 850  *
 851  * @param[in,out] resource
 852  *   Pointer to the modify-header resource.
 853  * @param[in] action
 854  *   Pointer to action specification.
 855  * @param[out] error
 856  *   Pointer to the error structure.
 857  *
 858  * @return
 859  *   0 on success, a negative errno value otherwise and rte_errno is set.
 860  */
 861 static int
 862 flow_dv_convert_action_set_reg
 863                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 864                          const struct rte_flow_action *action,
 865                          struct rte_flow_error *error)
 866 {
 867         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 868         struct mlx5_modification_cmd *actions = resource->actions;
 869         uint32_t i = resource->actions_num;
 870
 871         if (i >= MLX5_MODIFY_NUM)
 872                 return rte_flow_error_set(error, EINVAL,
 873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 874                                           "too many items to modify");
 875         actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
 876         actions[i].field = reg_to_field[conf->id];
 877         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 878         actions[i].data1 = conf->data;
 879         ++i;
 880         resource->actions_num = i;
 881         if (!resource->actions_num)
 882                 return rte_flow_error_set(error, EINVAL,
 883                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 884                                           "invalid modification flow item");
 885         return 0;
 886 }
 887
 888 /**
 889  * Convert internal COPY_REG action to DV specification.
 890  *
 891  * @param[in] dev
 892  *   Pointer to the rte_eth_dev structure.
 893  * @param[in,out] res
 894  *   Pointer to the modify-header resource.
 895  * @param[in] action
 896  *   Pointer to action specification.
 897  * @param[out] error
 898  *   Pointer to the error structure.
 899  *
 900  * @return
 901  *   0 on success, a negative errno value otherwise and rte_errno is set.
 902  */
 903 static int
 904 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
 905                                  struct mlx5_flow_dv_modify_hdr_resource *res,
 906                                  const struct rte_flow_action *action,
 907                                  struct rte_flow_error *error)
 908 {
 909         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
 910         rte_be32_t mask = RTE_BE32(UINT32_MAX);
 911         struct rte_flow_item item = {
 912                 .spec = NULL,
 913                 .mask = &mask,
 914         };
 915         struct field_modify_info reg_src[] = {
 916                 {4, 0, reg_to_field[conf->src]},
 917                 {0, 0, 0},
 918         };
 919         struct field_modify_info reg_dst = {
 920                 .offset = 0,
 921                 .id = reg_to_field[conf->dst],
 922         };
 923         /* Adjust reg_c[0] usage according to reported mask. */
 924         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
 925                 struct mlx5_priv *priv = dev->data->dev_private;
 926                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
 927
 928                 assert(reg_c0);
 929                 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
 930                 if (conf->dst == REG_C_0) {
 931                         /* Copy to reg_c[0], within mask only. */
 932                         reg_dst.offset = rte_bsf32(reg_c0);
 933                         /*
 934                          * Mask is ignoring the enianness, because
 935                          * there is no conversion in datapath.
 936                          */
 937 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 938                         /* Copy from destination lower bits to reg_c[0]. */
 939                         mask = reg_c0 >> reg_dst.offset;
 940 #else
 941                         /* Copy from destination upper bits to reg_c[0]. */
 942                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
 943                                           rte_fls_u32(reg_c0));
 944 #endif
 945                 } else {
 946                         mask = rte_cpu_to_be_32(reg_c0);
 947 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
 948                         /* Copy from reg_c[0] to destination lower bits. */
 949                         reg_dst.offset = 0;
 950 #else
 951                         /* Copy from reg_c[0] to destination upper bits. */
 952                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
 953                                          (rte_fls_u32(reg_c0) -
 954                                           rte_bsf32(reg_c0));
 955 #endif
 956                 }
 957         }
 958         return flow_dv_convert_modify_action(&item,
 959                                              reg_src, &reg_dst, res,
 960                                              MLX5_MODIFICATION_TYPE_COPY,
 961                                              error);
 962 }
 963
 964 /**
 965  * Validate META item.
 966  *
 967  * @param[in] dev
 968  *   Pointer to the rte_eth_dev structure.
 969  * @param[in] item
 970  *   Item specification.
 971  * @param[in] attr
 972  *   Attributes of flow that includes this item.
 973  * @param[out] error
 974  *   Pointer to error structure.
 975  *
 976  * @return
 977  *   0 on success, a negative errno value otherwise and rte_errno is set.
 978  */
 979 static int
 980 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
 981                            const struct rte_flow_item *item,
 982                            const struct rte_flow_attr *attr,
 983                            struct rte_flow_error *error)
 984 {
 985         const struct rte_flow_item_meta *spec = item->spec;
 986         const struct rte_flow_item_meta *mask = item->mask;
 987         const struct rte_flow_item_meta nic_mask = {
 988                 .data = UINT32_MAX
 989         };
 990         int ret;
 991
 992         if (!spec)
 993                 return rte_flow_error_set(error, EINVAL,
 994                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
 995                                           item->spec,
 996                                           "data cannot be empty");
 997         if (!spec->data)
 998                 return rte_flow_error_set(error, EINVAL,
 999                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1000                                           NULL,
1001                                           "data cannot be zero");
1002         if (!mask)
1003                 mask = &rte_flow_item_meta_mask;
1004         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1005                                         (const uint8_t *)&nic_mask,
1006                                         sizeof(struct rte_flow_item_meta),
1007                                         error);
1008         if (ret < 0)
1009                 return ret;
1010         if (attr->ingress)
1011                 return rte_flow_error_set(error, ENOTSUP,
1012                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1013                                           NULL,
1014                                           "pattern not supported for ingress");
1015         return 0;
1016 }
1017
1018 /**
1019  * Validate vport item.
1020  *
1021  * @param[in] dev
1022  *   Pointer to the rte_eth_dev structure.
1023  * @param[in] item
1024  *   Item specification.
1025  * @param[in] attr
1026  *   Attributes of flow that includes this item.
1027  * @param[in] item_flags
1028  *   Bit-fields that holds the items detected until now.
1029  * @param[out] error
1030  *   Pointer to error structure.
1031  *
1032  * @return
1033  *   0 on success, a negative errno value otherwise and rte_errno is set.
1034  */
1035 static int
1036 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1037                               const struct rte_flow_item *item,
1038                               const struct rte_flow_attr *attr,
1039                               uint64_t item_flags,
1040                               struct rte_flow_error *error)
1041 {
1042         const struct rte_flow_item_port_id *spec = item->spec;
1043         const struct rte_flow_item_port_id *mask = item->mask;
1044         const struct rte_flow_item_port_id switch_mask = {
1045                         .id = 0xffffffff,
1046         };
1047         struct mlx5_priv *esw_priv;
1048         struct mlx5_priv *dev_priv;
1049         int ret;
1050
1051         if (!attr->transfer)
1052                 return rte_flow_error_set(error, EINVAL,
1053                                           RTE_FLOW_ERROR_TYPE_ITEM,
1054                                           NULL,
1055                                           "match on port id is valid only"
1056                                           " when transfer flag is enabled");
1057         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1058                 return rte_flow_error_set(error, ENOTSUP,
1059                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1060                                           "multiple source ports are not"
1061                                           " supported");
1062         if (!mask)
1063                 mask = &switch_mask;
1064         if (mask->id != 0xffffffff)
1065                 return rte_flow_error_set(error, ENOTSUP,
1066                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1067                                            mask,
1068                                            "no support for partial mask on"
1069                                            " \"id\" field");
1070         ret = mlx5_flow_item_acceptable
1071                                 (item, (const uint8_t *)mask,
1072                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1073                                  sizeof(struct rte_flow_item_port_id),
1074                                  error);
1075         if (ret)
1076                 return ret;
1077         if (!spec)
1078                 return 0;
1079         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1080         if (!esw_priv)
1081                 return rte_flow_error_set(error, rte_errno,
1082                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1083                                           "failed to obtain E-Switch info for"
1084                                           " port");
1085         dev_priv = mlx5_dev_to_eswitch_info(dev);
1086         if (!dev_priv)
1087                 return rte_flow_error_set(error, rte_errno,
1088                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1089                                           NULL,
1090                                           "failed to obtain E-Switch info");
1091         if (esw_priv->domain_id != dev_priv->domain_id)
1092                 return rte_flow_error_set(error, EINVAL,
1093                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1094                                           "cannot match on a port from a"
1095                                           " different E-Switch");
1096         return 0;
1097 }
1098
1099 /**
1100  * Validate the pop VLAN action.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] action_flags
1105  *   Holds the actions detected until now.
1106  * @param[in] action
1107  *   Pointer to the pop vlan action.
1108  * @param[in] item_flags
1109  *   The items found in this flow rule.
1110  * @param[in] attr
1111  *   Pointer to flow attributes.
1112  * @param[out] error
1113  *   Pointer to error structure.
1114  *
1115  * @return
1116  *   0 on success, a negative errno value otherwise and rte_errno is set.
1117  */
1118 static int
1119 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1120                                  uint64_t action_flags,
1121                                  const struct rte_flow_action *action,
1122                                  uint64_t item_flags,
1123                                  const struct rte_flow_attr *attr,
1124                                  struct rte_flow_error *error)
1125 {
1126         struct mlx5_priv *priv = dev->data->dev_private;
1127
1128         (void)action;
1129         (void)attr;
1130         if (!priv->sh->pop_vlan_action)
1131                 return rte_flow_error_set(error, ENOTSUP,
1132                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1133                                           NULL,
1134                                           "pop vlan action is not supported");
1135         /*
1136          * Check for inconsistencies:
1137          *  fail strip_vlan in a flow that matches packets without VLAN tags.
1138          *  fail strip_vlan in a flow that matches packets without explicitly a
1139          *  matching on VLAN tag ?
1140          */
1141         if (action_flags & MLX5_FLOW_ACTION_OF_POP_VLAN)
1142                 return rte_flow_error_set(error, ENOTSUP,
1143                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1144                                           NULL,
1145                                           "no support for multiple vlan pop "
1146                                           "actions");
1147         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1148                 return rte_flow_error_set(error, ENOTSUP,
1149                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1150                                           NULL,
1151                                           "cannot pop vlan without a "
1152                                           "match on (outer) vlan in the flow");
1153         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1154                 return rte_flow_error_set(error, EINVAL,
1155                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1156                                           "wrong action order, port_id should "
1157                                           "be after pop VLAN action");
1158         return 0;
1159 }
1160
1161 /**
1162  * Get VLAN default info from vlan match info.
1163  *
1164  * @param[in] dev
1165  *   Pointer to the rte_eth_dev structure.
1166  * @param[in] item
1167  *   the list of item specifications.
1168  * @param[out] vlan
1169  *   pointer VLAN info to fill to.
1170  * @param[out] error
1171  *   Pointer to error structure.
1172  *
1173  * @return
1174  *   0 on success, a negative errno value otherwise and rte_errno is set.
1175  */
1176 static void
1177 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1178                                   struct rte_vlan_hdr *vlan)
1179 {
1180         const struct rte_flow_item_vlan nic_mask = {
1181                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1182                                 MLX5DV_FLOW_VLAN_VID_MASK),
1183                 .inner_type = RTE_BE16(0xffff),
1184         };
1185
1186         if (items == NULL)
1187                 return;
1188         for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1189                items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1190                 ;
1191         if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1192                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1193                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1194
1195                 if (!vlan_m)
1196                         vlan_m = &nic_mask;
1197                 /* Only full match values are accepted */
1198                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1199                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1200                         vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1201                         vlan->vlan_tci |=
1202                                 rte_be_to_cpu_16(vlan_v->tci &
1203                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1204                 }
1205                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1206                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1207                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1208                         vlan->vlan_tci |=
1209                                 rte_be_to_cpu_16(vlan_v->tci &
1210                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1211                 }
1212                 if (vlan_m->inner_type == nic_mask.inner_type)
1213                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1214                                                            vlan_m->inner_type);
1215         }
1216 }
1217
1218 /**
1219  * Validate the push VLAN action.
1220  *
1221  * @param[in] action_flags
1222  *   Holds the actions detected until now.
1223  * @param[in] action
1224  *   Pointer to the encap action.
1225  * @param[in] attr
1226  *   Pointer to flow attributes
1227  * @param[out] error
1228  *   Pointer to error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1235                                   uint64_t item_flags,
1236                                   const struct rte_flow_action *action,
1237                                   const struct rte_flow_attr *attr,
1238                                   struct rte_flow_error *error)
1239 {
1240         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1241
1242         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1243             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1244                 return rte_flow_error_set(error, EINVAL,
1245                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1246                                           "invalid vlan ethertype");
1247         if (action_flags &
1248                 (MLX5_FLOW_ACTION_OF_POP_VLAN | MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1249                 return rte_flow_error_set(error, ENOTSUP,
1250                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1251                                           "no support for multiple VLAN "
1252                                           "actions");
1253         if (!mlx5_flow_find_action
1254                         (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) &&
1255             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1256                 return rte_flow_error_set(error, ENOTSUP,
1257                                 RTE_FLOW_ERROR_TYPE_ACTION, action,
1258                                 "push VLAN needs to match on VLAN in order to "
1259                                 "get VLAN VID information because there is "
1260                                 "no followed set VLAN VID action");
1261         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1262                 return rte_flow_error_set(error, EINVAL,
1263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1264                                           "wrong action order, port_id should "
1265                                           "be after push VLAN");
1266         (void)attr;
1267         return 0;
1268 }
1269
1270 /**
1271  * Validate the set VLAN PCP.
1272  *
1273  * @param[in] action_flags
1274  *   Holds the actions detected until now.
1275  * @param[in] actions
1276  *   Pointer to the list of actions remaining in the flow rule.
1277  * @param[in] attr
1278  *   Pointer to flow attributes
1279  * @param[out] error
1280  *   Pointer to error structure.
1281  *
1282  * @return
1283  *   0 on success, a negative errno value otherwise and rte_errno is set.
1284  */
1285 static int
1286 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1287                                      const struct rte_flow_action actions[],
1288                                      struct rte_flow_error *error)
1289 {
1290         const struct rte_flow_action *action = actions;
1291         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1292
1293         if (conf->vlan_pcp > 7)
1294                 return rte_flow_error_set(error, EINVAL,
1295                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1296                                           "VLAN PCP value is too big");
1297         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1298                 return rte_flow_error_set(error, ENOTSUP,
1299                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1300                                           "set VLAN PCP action must follow "
1301                                           "the push VLAN action");
1302         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1303                 return rte_flow_error_set(error, ENOTSUP,
1304                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1305                                           "Multiple VLAN PCP modification are "
1306                                           "not supported");
1307         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1308                 return rte_flow_error_set(error, EINVAL,
1309                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1310                                           "wrong action order, port_id should "
1311                                           "be after set VLAN PCP");
1312         return 0;
1313 }
1314
1315 /**
1316  * Validate the set VLAN VID.
1317  *
1318  * @param[in] item_flags
1319  *   Holds the items detected in this rule.
1320  * @param[in] actions
1321  *   Pointer to the list of actions remaining in the flow rule.
1322  * @param[in] attr
1323  *   Pointer to flow attributes
1324  * @param[out] error
1325  *   Pointer to error structure.
1326  *
1327  * @return
1328  *   0 on success, a negative errno value otherwise and rte_errno is set.
1329  */
1330 static int
1331 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1332                                      uint64_t action_flags,
1333                                      const struct rte_flow_action actions[],
1334                                      struct rte_flow_error *error)
1335 {
1336         const struct rte_flow_action *action = actions;
1337         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1338
1339         if (conf->vlan_vid > RTE_BE16(0xFFE))
1340                 return rte_flow_error_set(error, EINVAL,
1341                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1342                                           "VLAN VID value is too big");
1343         /* there is an of_push_vlan action before us */
1344         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) {
1345                 if (mlx5_flow_find_action(actions + 1,
1346                                           RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID))
1347                         return rte_flow_error_set(error, ENOTSUP,
1348                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
1349                                         "Multiple VLAN VID modifications are "
1350                                         "not supported");
1351                 else
1352                         return 0;
1353         }
1354
1355         /*
1356          * Action is on an existing VLAN header:
1357          *    Need to verify this is a single modify CID action.
1358          *   Rule mast include a match on outer VLAN.
1359          */
1360         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1361                 return rte_flow_error_set(error, ENOTSUP,
1362                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1363                                           "Multiple VLAN VID modifications are "
1364                                           "not supported");
1365         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1366                 return rte_flow_error_set(error, EINVAL,
1367                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1368                                           "match on VLAN is required in order "
1369                                           "to set VLAN VID");
1370         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1371                 return rte_flow_error_set(error, EINVAL,
1372                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1373                                           "wrong action order, port_id should "
1374                                           "be after set VLAN VID");
1375         return 0;
1376 }
1377
1378 /**
1379  * Validate count action.
1380  *
1381  * @param[in] dev
1382  *   device otr.
1383  * @param[out] error
1384  *   Pointer to error structure.
1385  *
1386  * @return
1387  *   0 on success, a negative errno value otherwise and rte_errno is set.
1388  */
1389 static int
1390 flow_dv_validate_action_count(struct rte_eth_dev *dev,
1391                               struct rte_flow_error *error)
1392 {
1393         struct mlx5_priv *priv = dev->data->dev_private;
1394
1395         if (!priv->config.devx)
1396                 goto notsup_err;
1397 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
1398         return 0;
1399 #endif
1400 notsup_err:
1401         return rte_flow_error_set
1402                       (error, ENOTSUP,
1403                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1404                        NULL,
1405                        "count action not supported");
1406 }
1407
1408 /**
1409  * Validate the L2 encap action.
1410  *
1411  * @param[in] action_flags
1412  *   Holds the actions detected until now.
1413  * @param[in] action
1414  *   Pointer to the encap action.
1415  * @param[in] attr
1416  *   Pointer to flow attributes
1417  * @param[out] error
1418  *   Pointer to error structure.
1419  *
1420  * @return
1421  *   0 on success, a negative errno value otherwise and rte_errno is set.
1422  */
1423 static int
1424 flow_dv_validate_action_l2_encap(uint64_t action_flags,
1425                                  const struct rte_flow_action *action,
1426                                  const struct rte_flow_attr *attr,
1427                                  struct rte_flow_error *error)
1428 {
1429         if (!(action->conf))
1430                 return rte_flow_error_set(error, EINVAL,
1431                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1432                                           "configuration cannot be null");
1433         if (action_flags & MLX5_FLOW_ACTION_DROP)
1434                 return rte_flow_error_set(error, EINVAL,
1435                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1436                                           "can't drop and encap in same flow");
1437         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1438                 return rte_flow_error_set(error, EINVAL,
1439                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1440                                           "can only have a single encap or"
1441                                           " decap action in a flow");
1442         if (!attr->transfer && attr->ingress)
1443                 return rte_flow_error_set(error, ENOTSUP,
1444                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1445                                           NULL,
1446                                           "encap action not supported for "
1447                                           "ingress");
1448         return 0;
1449 }
1450
1451 /**
1452  * Validate the L2 decap action.
1453  *
1454  * @param[in] action_flags
1455  *   Holds the actions detected until now.
1456  * @param[in] attr
1457  *   Pointer to flow attributes
1458  * @param[out] error
1459  *   Pointer to error structure.
1460  *
1461  * @return
1462  *   0 on success, a negative errno value otherwise and rte_errno is set.
1463  */
1464 static int
1465 flow_dv_validate_action_l2_decap(uint64_t action_flags,
1466                                  const struct rte_flow_attr *attr,
1467                                  struct rte_flow_error *error)
1468 {
1469         if (action_flags & MLX5_FLOW_ACTION_DROP)
1470                 return rte_flow_error_set(error, EINVAL,
1471                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1472                                           "can't drop and decap in same flow");
1473         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
1474                 return rte_flow_error_set(error, EINVAL,
1475                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1476                                           "can only have a single encap or"
1477                                           " decap action in a flow");
1478         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1479                 return rte_flow_error_set(error, EINVAL,
1480                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1481                                           "can't have decap action after"
1482                                           " modify action");
1483         if (attr->egress)
1484                 return rte_flow_error_set(error, ENOTSUP,
1485                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1486                                           NULL,
1487                                           "decap action not supported for "
1488                                           "egress");
1489         return 0;
1490 }
1491
1492 /**
1493  * Validate the raw encap action.
1494  *
1495  * @param[in] action_flags
1496  *   Holds the actions detected until now.
1497  * @param[in] action
1498  *   Pointer to the encap action.
1499  * @param[in] attr
1500  *   Pointer to flow attributes
1501  * @param[out] error
1502  *   Pointer to error structure.
1503  *
1504  * @return
1505  *   0 on success, a negative errno value otherwise and rte_errno is set.
1506  */
1507 static int
1508 flow_dv_validate_action_raw_encap(uint64_t action_flags,
1509                                   const struct rte_flow_action *action,
1510                                   const struct rte_flow_attr *attr,
1511                                   struct rte_flow_error *error)
1512 {
1513         const struct rte_flow_action_raw_encap *raw_encap =
1514                 (const struct rte_flow_action_raw_encap *)action->conf;
1515         if (!(action->conf))
1516                 return rte_flow_error_set(error, EINVAL,
1517                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1518                                           "configuration cannot be null");
1519         if (action_flags & MLX5_FLOW_ACTION_DROP)
1520                 return rte_flow_error_set(error, EINVAL,
1521                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1522                                           "can't drop and encap in same flow");
1523         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1524                 return rte_flow_error_set(error, EINVAL,
1525                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1526                                           "can only have a single encap"
1527                                           " action in a flow");
1528         /* encap without preceding decap is not supported for ingress */
1529         if (!attr->transfer &&  attr->ingress &&
1530             !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
1531                 return rte_flow_error_set(error, ENOTSUP,
1532                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1533                                           NULL,
1534                                           "encap action not supported for "
1535                                           "ingress");
1536         if (!raw_encap->size || !raw_encap->data)
1537                 return rte_flow_error_set(error, EINVAL,
1538                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1539                                           "raw encap data cannot be empty");
1540         return 0;
1541 }
1542
1543 /**
1544  * Validate the raw decap action.
1545  *
1546  * @param[in] action_flags
1547  *   Holds the actions detected until now.
1548  * @param[in] action
1549  *   Pointer to the encap action.
1550  * @param[in] attr
1551  *   Pointer to flow attributes
1552  * @param[out] error
1553  *   Pointer to error structure.
1554  *
1555  * @return
1556  *   0 on success, a negative errno value otherwise and rte_errno is set.
1557  */
1558 static int
1559 flow_dv_validate_action_raw_decap(uint64_t action_flags,
1560                                   const struct rte_flow_action *action,
1561                                   const struct rte_flow_attr *attr,
1562                                   struct rte_flow_error *error)
1563 {
1564         if (action_flags & MLX5_FLOW_ACTION_DROP)
1565                 return rte_flow_error_set(error, EINVAL,
1566                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1567                                           "can't drop and decap in same flow");
1568         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
1569                 return rte_flow_error_set(error, EINVAL,
1570                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1571                                           "can't have encap action before"
1572                                           " decap action");
1573         if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
1574                 return rte_flow_error_set(error, EINVAL,
1575                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1576                                           "can only have a single decap"
1577                                           " action in a flow");
1578         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
1579                 return rte_flow_error_set(error, EINVAL,
1580                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1581                                           "can't have decap action after"
1582                                           " modify action");
1583         /* decap action is valid on egress only if it is followed by encap */
1584         if (attr->egress) {
1585                 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
1586                        action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1587                        action++) {
1588                 }
1589                 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
1590                         return rte_flow_error_set
1591                                         (error, ENOTSUP,
1592                                          RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1593                                          NULL, "decap action not supported"
1594                                          " for egress");
1595         }
1596         return 0;
1597 }
1598
1599 /**
1600  * Find existing encap/decap resource or create and register a new one.
1601  *
1602  * @param dev[in, out]
1603  *   Pointer to rte_eth_dev structure.
1604  * @param[in, out] resource
1605  *   Pointer to encap/decap resource.
1606  * @parm[in, out] dev_flow
1607  *   Pointer to the dev_flow.
1608  * @param[out] error
1609  *   pointer to error structure.
1610  *
1611  * @return
1612  *   0 on success otherwise -errno and errno is set.
1613  */
1614 static int
1615 flow_dv_encap_decap_resource_register
1616                         (struct rte_eth_dev *dev,
1617                          struct mlx5_flow_dv_encap_decap_resource *resource,
1618                          struct mlx5_flow *dev_flow,
1619                          struct rte_flow_error *error)
1620 {
1621         struct mlx5_priv *priv = dev->data->dev_private;
1622         struct mlx5_ibv_shared *sh = priv->sh;
1623         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
1624         struct mlx5dv_dr_domain *domain;
1625
1626         resource->flags = dev_flow->group ? 0 : 1;
1627         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1628                 domain = sh->fdb_domain;
1629         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1630                 domain = sh->rx_domain;
1631         else
1632                 domain = sh->tx_domain;
1633
1634         /* Lookup a matching resource from cache. */
1635         LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
1636                 if (resource->reformat_type == cache_resource->reformat_type &&
1637                     resource->ft_type == cache_resource->ft_type &&
1638                     resource->flags == cache_resource->flags &&
1639                     resource->size == cache_resource->size &&
1640                     !memcmp((const void *)resource->buf,
1641                             (const void *)cache_resource->buf,
1642                             resource->size)) {
1643                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
1644                                 (void *)cache_resource,
1645                                 rte_atomic32_read(&cache_resource->refcnt));
1646                         rte_atomic32_inc(&cache_resource->refcnt);
1647                         dev_flow->dv.encap_decap = cache_resource;
1648                         return 0;
1649                 }
1650         }
1651         /* Register new encap/decap resource. */
1652         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1653         if (!cache_resource)
1654                 return rte_flow_error_set(error, ENOMEM,
1655                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1656                                           "cannot allocate resource memory");
1657         *cache_resource = *resource;
1658         cache_resource->verbs_action =
1659                 mlx5_glue->dv_create_flow_action_packet_reformat
1660                         (sh->ctx, cache_resource->reformat_type,
1661                          cache_resource->ft_type, domain, cache_resource->flags,
1662                          cache_resource->size,
1663                          (cache_resource->size ? cache_resource->buf : NULL));
1664         if (!cache_resource->verbs_action) {
1665                 rte_free(cache_resource);
1666                 return rte_flow_error_set(error, ENOMEM,
1667                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1668                                           NULL, "cannot create action");
1669         }
1670         rte_atomic32_init(&cache_resource->refcnt);
1671         rte_atomic32_inc(&cache_resource->refcnt);
1672         LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
1673         dev_flow->dv.encap_decap = cache_resource;
1674         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
1675                 (void *)cache_resource,
1676                 rte_atomic32_read(&cache_resource->refcnt));
1677         return 0;
1678 }
1679
1680 /**
1681  * Find existing table jump resource or create and register a new one.
1682  *
1683  * @param dev[in, out]
1684  *   Pointer to rte_eth_dev structure.
1685  * @param[in, out] resource
1686  *   Pointer to jump table resource.
1687  * @parm[in, out] dev_flow
1688  *   Pointer to the dev_flow.
1689  * @param[out] error
1690  *   pointer to error structure.
1691  *
1692  * @return
1693  *   0 on success otherwise -errno and errno is set.
1694  */
1695 static int
1696 flow_dv_jump_tbl_resource_register
1697                         (struct rte_eth_dev *dev,
1698                          struct mlx5_flow_dv_jump_tbl_resource *resource,
1699                          struct mlx5_flow *dev_flow,
1700                          struct rte_flow_error *error)
1701 {
1702         struct mlx5_priv *priv = dev->data->dev_private;
1703         struct mlx5_ibv_shared *sh = priv->sh;
1704         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
1705
1706         /* Lookup a matching resource from cache. */
1707         LIST_FOREACH(cache_resource, &sh->jump_tbl, next) {
1708                 if (resource->tbl == cache_resource->tbl) {
1709                         DRV_LOG(DEBUG, "jump table resource resource %p: refcnt %d++",
1710                                 (void *)cache_resource,
1711                                 rte_atomic32_read(&cache_resource->refcnt));
1712                         rte_atomic32_inc(&cache_resource->refcnt);
1713                         dev_flow->dv.jump = cache_resource;
1714                         return 0;
1715                 }
1716         }
1717         /* Register new jump table resource. */
1718         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1719         if (!cache_resource)
1720                 return rte_flow_error_set(error, ENOMEM,
1721                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1722                                           "cannot allocate resource memory");
1723         *cache_resource = *resource;
1724         cache_resource->action =
1725                 mlx5_glue->dr_create_flow_action_dest_flow_tbl
1726                 (resource->tbl->obj);
1727         if (!cache_resource->action) {
1728                 rte_free(cache_resource);
1729                 return rte_flow_error_set(error, ENOMEM,
1730                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1731                                           NULL, "cannot create action");
1732         }
1733         rte_atomic32_init(&cache_resource->refcnt);
1734         rte_atomic32_inc(&cache_resource->refcnt);
1735         LIST_INSERT_HEAD(&sh->jump_tbl, cache_resource, next);
1736         dev_flow->dv.jump = cache_resource;
1737         DRV_LOG(DEBUG, "new jump table  resource %p: refcnt %d++",
1738                 (void *)cache_resource,
1739                 rte_atomic32_read(&cache_resource->refcnt));
1740         return 0;
1741 }
1742
1743 /**
1744  * Find existing table port ID resource or create and register a new one.
1745  *
1746  * @param dev[in, out]
1747  *   Pointer to rte_eth_dev structure.
1748  * @param[in, out] resource
1749  *   Pointer to port ID action resource.
1750  * @parm[in, out] dev_flow
1751  *   Pointer to the dev_flow.
1752  * @param[out] error
1753  *   pointer to error structure.
1754  *
1755  * @return
1756  *   0 on success otherwise -errno and errno is set.
1757  */
1758 static int
1759 flow_dv_port_id_action_resource_register
1760                         (struct rte_eth_dev *dev,
1761                          struct mlx5_flow_dv_port_id_action_resource *resource,
1762                          struct mlx5_flow *dev_flow,
1763                          struct rte_flow_error *error)
1764 {
1765         struct mlx5_priv *priv = dev->data->dev_private;
1766         struct mlx5_ibv_shared *sh = priv->sh;
1767         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
1768
1769         /* Lookup a matching resource from cache. */
1770         LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
1771                 if (resource->port_id == cache_resource->port_id) {
1772                         DRV_LOG(DEBUG, "port id action resource resource %p: "
1773                                 "refcnt %d++",
1774                                 (void *)cache_resource,
1775                                 rte_atomic32_read(&cache_resource->refcnt));
1776                         rte_atomic32_inc(&cache_resource->refcnt);
1777                         dev_flow->dv.port_id_action = cache_resource;
1778                         return 0;
1779                 }
1780         }
1781         /* Register new port id action resource. */
1782         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1783         if (!cache_resource)
1784                 return rte_flow_error_set(error, ENOMEM,
1785                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1786                                           "cannot allocate resource memory");
1787         *cache_resource = *resource;
1788         cache_resource->action =
1789                 mlx5_glue->dr_create_flow_action_dest_vport
1790                         (priv->sh->fdb_domain, resource->port_id);
1791         if (!cache_resource->action) {
1792                 rte_free(cache_resource);
1793                 return rte_flow_error_set(error, ENOMEM,
1794                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1795                                           NULL, "cannot create action");
1796         }
1797         rte_atomic32_init(&cache_resource->refcnt);
1798         rte_atomic32_inc(&cache_resource->refcnt);
1799         LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
1800         dev_flow->dv.port_id_action = cache_resource;
1801         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
1802                 (void *)cache_resource,
1803                 rte_atomic32_read(&cache_resource->refcnt));
1804         return 0;
1805 }
1806
1807 /**
1808  * Find existing push vlan resource or create and register a new one.
1809  *
1810  * @param dev[in, out]
1811  *   Pointer to rte_eth_dev structure.
1812  * @param[in, out] resource
1813  *   Pointer to port ID action resource.
1814  * @parm[in, out] dev_flow
1815  *   Pointer to the dev_flow.
1816  * @param[out] error
1817  *   pointer to error structure.
1818  *
1819  * @return
1820  *   0 on success otherwise -errno and errno is set.
1821  */
1822 static int
1823 flow_dv_push_vlan_action_resource_register
1824                        (struct rte_eth_dev *dev,
1825                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
1826                         struct mlx5_flow *dev_flow,
1827                         struct rte_flow_error *error)
1828 {
1829         struct mlx5_priv *priv = dev->data->dev_private;
1830         struct mlx5_ibv_shared *sh = priv->sh;
1831         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
1832         struct mlx5dv_dr_domain *domain;
1833
1834         /* Lookup a matching resource from cache. */
1835         LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
1836                 if (resource->vlan_tag == cache_resource->vlan_tag &&
1837                     resource->ft_type == cache_resource->ft_type) {
1838                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
1839                                 "refcnt %d++",
1840                                 (void *)cache_resource,
1841                                 rte_atomic32_read(&cache_resource->refcnt));
1842                         rte_atomic32_inc(&cache_resource->refcnt);
1843                         dev_flow->dv.push_vlan_res = cache_resource;
1844                         return 0;
1845                 }
1846         }
1847         /* Register new push_vlan action resource. */
1848         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
1849         if (!cache_resource)
1850                 return rte_flow_error_set(error, ENOMEM,
1851                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1852                                           "cannot allocate resource memory");
1853         *cache_resource = *resource;
1854         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
1855                 domain = sh->fdb_domain;
1856         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
1857                 domain = sh->rx_domain;
1858         else
1859                 domain = sh->tx_domain;
1860         cache_resource->action =
1861                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
1862                                                            resource->vlan_tag);
1863         if (!cache_resource->action) {
1864                 rte_free(cache_resource);
1865                 return rte_flow_error_set(error, ENOMEM,
1866                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1867                                           NULL, "cannot create action");
1868         }
1869         rte_atomic32_init(&cache_resource->refcnt);
1870         rte_atomic32_inc(&cache_resource->refcnt);
1871         LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
1872         dev_flow->dv.push_vlan_res = cache_resource;
1873         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
1874                 (void *)cache_resource,
1875                 rte_atomic32_read(&cache_resource->refcnt));
1876         return 0;
1877 }
1878 /**
1879  * Get the size of specific rte_flow_item_type
1880  *
1881  * @param[in] item_type
1882  *   Tested rte_flow_item_type.
1883  *
1884  * @return
1885  *   sizeof struct item_type, 0 if void or irrelevant.
1886  */
1887 static size_t
1888 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
1889 {
1890         size_t retval;
1891
1892         switch (item_type) {
1893         case RTE_FLOW_ITEM_TYPE_ETH:
1894                 retval = sizeof(struct rte_flow_item_eth);
1895                 break;
1896         case RTE_FLOW_ITEM_TYPE_VLAN:
1897                 retval = sizeof(struct rte_flow_item_vlan);
1898                 break;
1899         case RTE_FLOW_ITEM_TYPE_IPV4:
1900                 retval = sizeof(struct rte_flow_item_ipv4);
1901                 break;
1902         case RTE_FLOW_ITEM_TYPE_IPV6:
1903                 retval = sizeof(struct rte_flow_item_ipv6);
1904                 break;
1905         case RTE_FLOW_ITEM_TYPE_UDP:
1906                 retval = sizeof(struct rte_flow_item_udp);
1907                 break;
1908         case RTE_FLOW_ITEM_TYPE_TCP:
1909                 retval = sizeof(struct rte_flow_item_tcp);
1910                 break;
1911         case RTE_FLOW_ITEM_TYPE_VXLAN:
1912                 retval = sizeof(struct rte_flow_item_vxlan);
1913                 break;
1914         case RTE_FLOW_ITEM_TYPE_GRE:
1915                 retval = sizeof(struct rte_flow_item_gre);
1916                 break;
1917         case RTE_FLOW_ITEM_TYPE_NVGRE:
1918                 retval = sizeof(struct rte_flow_item_nvgre);
1919                 break;
1920         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1921                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
1922                 break;
1923         case RTE_FLOW_ITEM_TYPE_MPLS:
1924                 retval = sizeof(struct rte_flow_item_mpls);
1925                 break;
1926         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
1927         default:
1928                 retval = 0;
1929                 break;
1930         }
1931         return retval;
1932 }
1933
1934 #define MLX5_ENCAP_IPV4_VERSION         0x40
1935 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
1936 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
1937 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
1938 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
1939 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
1940 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
1941
1942 /**
1943  * Convert the encap action data from list of rte_flow_item to raw buffer
1944  *
1945  * @param[in] items
1946  *   Pointer to rte_flow_item objects list.
1947  * @param[out] buf
1948  *   Pointer to the output buffer.
1949  * @param[out] size
1950  *   Pointer to the output buffer size.
1951  * @param[out] error
1952  *   Pointer to the error structure.
1953  *
1954  * @return
1955  *   0 on success, a negative errno value otherwise and rte_errno is set.
1956  */
1957 static int
1958 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
1959                            size_t *size, struct rte_flow_error *error)
1960 {
1961         struct rte_ether_hdr *eth = NULL;
1962         struct rte_vlan_hdr *vlan = NULL;
1963         struct rte_ipv4_hdr *ipv4 = NULL;
1964         struct rte_ipv6_hdr *ipv6 = NULL;
1965         struct rte_udp_hdr *udp = NULL;
1966         struct rte_vxlan_hdr *vxlan = NULL;
1967         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
1968         struct rte_gre_hdr *gre = NULL;
1969         size_t len;
1970         size_t temp_size = 0;
1971
1972         if (!items)
1973                 return rte_flow_error_set(error, EINVAL,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION,
1975                                           NULL, "invalid empty data");
1976         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1977                 len = flow_dv_get_item_len(items->type);
1978                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
1979                         return rte_flow_error_set(error, EINVAL,
1980                                                   RTE_FLOW_ERROR_TYPE_ACTION,
1981                                                   (void *)items->type,
1982                                                   "items total size is too big"
1983                                                   " for encap action");
1984                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
1985                 switch (items->type) {
1986                 case RTE_FLOW_ITEM_TYPE_ETH:
1987                         eth = (struct rte_ether_hdr *)&buf[temp_size];
1988                         break;
1989                 case RTE_FLOW_ITEM_TYPE_VLAN:
1990                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
1991                         if (!eth)
1992                                 return rte_flow_error_set(error, EINVAL,
1993                                                 RTE_FLOW_ERROR_TYPE_ACTION,
1994                                                 (void *)items->type,
1995                                                 "eth header not found");
1996                         if (!eth->ether_type)
1997                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
1998                         break;
1999                 case RTE_FLOW_ITEM_TYPE_IPV4:
2000                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2001                         if (!vlan && !eth)
2002                                 return rte_flow_error_set(error, EINVAL,
2003                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2004                                                 (void *)items->type,
2005                                                 "neither eth nor vlan"
2006                                                 " header found");
2007                         if (vlan && !vlan->eth_proto)
2008                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2009                         else if (eth && !eth->ether_type)
2010                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2011                         if (!ipv4->version_ihl)
2012                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2013                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2014                         if (!ipv4->time_to_live)
2015                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2016                         break;
2017                 case RTE_FLOW_ITEM_TYPE_IPV6:
2018                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2019                         if (!vlan && !eth)
2020                                 return rte_flow_error_set(error, EINVAL,
2021                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2022                                                 (void *)items->type,
2023                                                 "neither eth nor vlan"
2024                                                 " header found");
2025                         if (vlan && !vlan->eth_proto)
2026                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2027                         else if (eth && !eth->ether_type)
2028                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2029                         if (!ipv6->vtc_flow)
2030                                 ipv6->vtc_flow =
2031                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2032                         if (!ipv6->hop_limits)
2033                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2034                         break;
2035                 case RTE_FLOW_ITEM_TYPE_UDP:
2036                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2037                         if (!ipv4 && !ipv6)
2038                                 return rte_flow_error_set(error, EINVAL,
2039                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2040                                                 (void *)items->type,
2041                                                 "ip header not found");
2042                         if (ipv4 && !ipv4->next_proto_id)
2043                                 ipv4->next_proto_id = IPPROTO_UDP;
2044                         else if (ipv6 && !ipv6->proto)
2045                                 ipv6->proto = IPPROTO_UDP;
2046                         break;
2047                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2048                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2049                         if (!udp)
2050                                 return rte_flow_error_set(error, EINVAL,
2051                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2052                                                 (void *)items->type,
2053                                                 "udp header not found");
2054                         if (!udp->dst_port)
2055                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2056                         if (!vxlan->vx_flags)
2057                                 vxlan->vx_flags =
2058                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2059                         break;
2060                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2061                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2062                         if (!udp)
2063                                 return rte_flow_error_set(error, EINVAL,
2064                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2065                                                 (void *)items->type,
2066                                                 "udp header not found");
2067                         if (!vxlan_gpe->proto)
2068                                 return rte_flow_error_set(error, EINVAL,
2069                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2070                                                 (void *)items->type,
2071                                                 "next protocol not found");
2072                         if (!udp->dst_port)
2073                                 udp->dst_port =
2074                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2075                         if (!vxlan_gpe->vx_flags)
2076                                 vxlan_gpe->vx_flags =
2077                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2078                         break;
2079                 case RTE_FLOW_ITEM_TYPE_GRE:
2080                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2081                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2082                         if (!gre->proto)
2083                                 return rte_flow_error_set(error, EINVAL,
2084                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2085                                                 (void *)items->type,
2086                                                 "next protocol not found");
2087                         if (!ipv4 && !ipv6)
2088                                 return rte_flow_error_set(error, EINVAL,
2089                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2090                                                 (void *)items->type,
2091                                                 "ip header not found");
2092                         if (ipv4 && !ipv4->next_proto_id)
2093                                 ipv4->next_proto_id = IPPROTO_GRE;
2094                         else if (ipv6 && !ipv6->proto)
2095                                 ipv6->proto = IPPROTO_GRE;
2096                         break;
2097                 case RTE_FLOW_ITEM_TYPE_VOID:
2098                         break;
2099                 default:
2100                         return rte_flow_error_set(error, EINVAL,
2101                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2102                                                   (void *)items->type,
2103                                                   "unsupported item type");
2104                         break;
2105                 }
2106                 temp_size += len;
2107         }
2108         *size = temp_size;
2109         return 0;
2110 }
2111
2112 static int
2113 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2114 {
2115         struct rte_ether_hdr *eth = NULL;
2116         struct rte_vlan_hdr *vlan = NULL;
2117         struct rte_ipv6_hdr *ipv6 = NULL;
2118         struct rte_udp_hdr *udp = NULL;
2119         char *next_hdr;
2120         uint16_t proto;
2121
2122         eth = (struct rte_ether_hdr *)data;
2123         next_hdr = (char *)(eth + 1);
2124         proto = RTE_BE16(eth->ether_type);
2125
2126         /* VLAN skipping */
2127         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2128                 vlan = (struct rte_vlan_hdr *)next_hdr;
2129                 proto = RTE_BE16(vlan->eth_proto);
2130                 next_hdr += sizeof(struct rte_vlan_hdr);
2131         }
2132
2133         /* HW calculates IPv4 csum. no need to proceed */
2134         if (proto == RTE_ETHER_TYPE_IPV4)
2135                 return 0;
2136
2137         /* non IPv4/IPv6 header. not supported */
2138         if (proto != RTE_ETHER_TYPE_IPV6) {
2139                 return rte_flow_error_set(error, ENOTSUP,
2140                                           RTE_FLOW_ERROR_TYPE_ACTION,
2141                                           NULL, "Cannot offload non IPv4/IPv6");
2142         }
2143
2144         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2145
2146         /* ignore non UDP */
2147         if (ipv6->proto != IPPROTO_UDP)
2148                 return 0;
2149
2150         udp = (struct rte_udp_hdr *)(ipv6 + 1);
2151         udp->dgram_cksum = 0;
2152
2153         return 0;
2154 }
2155
2156 /**
2157  * Convert L2 encap action to DV specification.
2158  *
2159  * @param[in] dev
2160  *   Pointer to rte_eth_dev structure.
2161  * @param[in] action
2162  *   Pointer to action structure.
2163  * @param[in, out] dev_flow
2164  *   Pointer to the mlx5_flow.
2165  * @param[in] transfer
2166  *   Mark if the flow is E-Switch flow.
2167  * @param[out] error
2168  *   Pointer to the error structure.
2169  *
2170  * @return
2171  *   0 on success, a negative errno value otherwise and rte_errno is set.
2172  */
2173 static int
2174 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2175                                const struct rte_flow_action *action,
2176                                struct mlx5_flow *dev_flow,
2177                                uint8_t transfer,
2178                                struct rte_flow_error *error)
2179 {
2180         const struct rte_flow_item *encap_data;
2181         const struct rte_flow_action_raw_encap *raw_encap_data;
2182         struct mlx5_flow_dv_encap_decap_resource res = {
2183                 .reformat_type =
2184                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2185                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2186                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2187         };
2188
2189         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2190                 raw_encap_data =
2191                         (const struct rte_flow_action_raw_encap *)action->conf;
2192                 res.size = raw_encap_data->size;
2193                 memcpy(res.buf, raw_encap_data->data, res.size);
2194                 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2195                         return -rte_errno;
2196         } else {
2197                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2198                         encap_data =
2199                                 ((const struct rte_flow_action_vxlan_encap *)
2200                                                 action->conf)->definition;
2201                 else
2202                         encap_data =
2203                                 ((const struct rte_flow_action_nvgre_encap *)
2204                                                 action->conf)->definition;
2205                 if (flow_dv_convert_encap_data(encap_data, res.buf,
2206                                                &res.size, error))
2207                         return -rte_errno;
2208         }
2209         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2210                 return rte_flow_error_set(error, EINVAL,
2211                                           RTE_FLOW_ERROR_TYPE_ACTION,
2212                                           NULL, "can't create L2 encap action");
2213         return 0;
2214 }
2215
2216 /**
2217  * Convert L2 decap action to DV specification.
2218  *
2219  * @param[in] dev
2220  *   Pointer to rte_eth_dev structure.
2221  * @param[in, out] dev_flow
2222  *   Pointer to the mlx5_flow.
2223  * @param[in] transfer
2224  *   Mark if the flow is E-Switch flow.
2225  * @param[out] error
2226  *   Pointer to the error structure.
2227  *
2228  * @return
2229  *   0 on success, a negative errno value otherwise and rte_errno is set.
2230  */
2231 static int
2232 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2233                                struct mlx5_flow *dev_flow,
2234                                uint8_t transfer,
2235                                struct rte_flow_error *error)
2236 {
2237         struct mlx5_flow_dv_encap_decap_resource res = {
2238                 .size = 0,
2239                 .reformat_type =
2240                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2241                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2242                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2243         };
2244
2245         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2246                 return rte_flow_error_set(error, EINVAL,
2247                                           RTE_FLOW_ERROR_TYPE_ACTION,
2248                                           NULL, "can't create L2 decap action");
2249         return 0;
2250 }
2251
2252 /**
2253  * Convert raw decap/encap (L3 tunnel) action to DV specification.
2254  *
2255  * @param[in] dev
2256  *   Pointer to rte_eth_dev structure.
2257  * @param[in] action
2258  *   Pointer to action structure.
2259  * @param[in, out] dev_flow
2260  *   Pointer to the mlx5_flow.
2261  * @param[in] attr
2262  *   Pointer to the flow attributes.
2263  * @param[out] error
2264  *   Pointer to the error structure.
2265  *
2266  * @return
2267  *   0 on success, a negative errno value otherwise and rte_errno is set.
2268  */
2269 static int
2270 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2271                                 const struct rte_flow_action *action,
2272                                 struct mlx5_flow *dev_flow,
2273                                 const struct rte_flow_attr *attr,
2274                                 struct rte_flow_error *error)
2275 {
2276         const struct rte_flow_action_raw_encap *encap_data;
2277         struct mlx5_flow_dv_encap_decap_resource res;
2278
2279         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2280         res.size = encap_data->size;
2281         memcpy(res.buf, encap_data->data, res.size);
2282         res.reformat_type = attr->egress ?
2283                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
2284                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
2285         if (attr->transfer)
2286                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2287         else
2288                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2289                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2290         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2291                 return rte_flow_error_set(error, EINVAL,
2292                                           RTE_FLOW_ERROR_TYPE_ACTION,
2293                                           NULL, "can't create encap action");
2294         return 0;
2295 }
2296
2297 /**
2298  * Create action push VLAN.
2299  *
2300  * @param[in] dev
2301  *   Pointer to rte_eth_dev structure.
2302  * @param[in] vlan_tag
2303  *   the vlan tag to push to the Ethernet header.
2304  * @param[in, out] dev_flow
2305  *   Pointer to the mlx5_flow.
2306  * @param[in] attr
2307  *   Pointer to the flow attributes.
2308  * @param[out] error
2309  *   Pointer to the error structure.
2310  *
2311  * @return
2312  *   0 on success, a negative errno value otherwise and rte_errno is set.
2313  */
2314 static int
2315 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
2316                                 const struct rte_flow_attr *attr,
2317                                 const struct rte_vlan_hdr *vlan,
2318                                 struct mlx5_flow *dev_flow,
2319                                 struct rte_flow_error *error)
2320 {
2321         struct mlx5_flow_dv_push_vlan_action_resource res;
2322
2323         res.vlan_tag =
2324                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
2325                                  vlan->vlan_tci);
2326         if (attr->transfer)
2327                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2328         else
2329                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2330                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2331         return flow_dv_push_vlan_action_resource_register
2332                                             (dev, &res, dev_flow, error);
2333 }
2334
2335 /**
2336  * Validate the modify-header actions.
2337  *
2338  * @param[in] action_flags
2339  *   Holds the actions detected until now.
2340  * @param[in] action
2341  *   Pointer to the modify action.
2342  * @param[out] error
2343  *   Pointer to error structure.
2344  *
2345  * @return
2346  *   0 on success, a negative errno value otherwise and rte_errno is set.
2347  */
2348 static int
2349 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
2350                                    const struct rte_flow_action *action,
2351                                    struct rte_flow_error *error)
2352 {
2353         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
2354                 return rte_flow_error_set(error, EINVAL,
2355                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2356                                           NULL, "action configuration not set");
2357         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2358                 return rte_flow_error_set(error, EINVAL,
2359                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2360                                           "can't have encap action before"
2361                                           " modify action");
2362         return 0;
2363 }
2364
2365 /**
2366  * Validate the modify-header MAC address actions.
2367  *
2368  * @param[in] action_flags
2369  *   Holds the actions detected until now.
2370  * @param[in] action
2371  *   Pointer to the modify action.
2372  * @param[in] item_flags
2373  *   Holds the items detected.
2374  * @param[out] error
2375  *   Pointer to error structure.
2376  *
2377  * @return
2378  *   0 on success, a negative errno value otherwise and rte_errno is set.
2379  */
2380 static int
2381 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
2382                                    const struct rte_flow_action *action,
2383                                    const uint64_t item_flags,
2384                                    struct rte_flow_error *error)
2385 {
2386         int ret = 0;
2387
2388         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2389         if (!ret) {
2390                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
2391                         return rte_flow_error_set(error, EINVAL,
2392                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2393                                                   NULL,
2394                                                   "no L2 item in pattern");
2395         }
2396         return ret;
2397 }
2398
2399 /**
2400  * Validate the modify-header IPv4 address actions.
2401  *
2402  * @param[in] action_flags
2403  *   Holds the actions detected until now.
2404  * @param[in] action
2405  *   Pointer to the modify action.
2406  * @param[in] item_flags
2407  *   Holds the items detected.
2408  * @param[out] error
2409  *   Pointer to error structure.
2410  *
2411  * @return
2412  *   0 on success, a negative errno value otherwise and rte_errno is set.
2413  */
2414 static int
2415 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
2416                                     const struct rte_flow_action *action,
2417                                     const uint64_t item_flags,
2418                                     struct rte_flow_error *error)
2419 {
2420         int ret = 0;
2421
2422         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2423         if (!ret) {
2424                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
2425                         return rte_flow_error_set(error, EINVAL,
2426                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2427                                                   NULL,
2428                                                   "no ipv4 item in pattern");
2429         }
2430         return ret;
2431 }
2432
2433 /**
2434  * Validate the modify-header IPv6 address actions.
2435  *
2436  * @param[in] action_flags
2437  *   Holds the actions detected until now.
2438  * @param[in] action
2439  *   Pointer to the modify action.
2440  * @param[in] item_flags
2441  *   Holds the items detected.
2442  * @param[out] error
2443  *   Pointer to error structure.
2444  *
2445  * @return
2446  *   0 on success, a negative errno value otherwise and rte_errno is set.
2447  */
2448 static int
2449 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
2450                                     const struct rte_flow_action *action,
2451                                     const uint64_t item_flags,
2452                                     struct rte_flow_error *error)
2453 {
2454         int ret = 0;
2455
2456         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2457         if (!ret) {
2458                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
2459                         return rte_flow_error_set(error, EINVAL,
2460                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2461                                                   NULL,
2462                                                   "no ipv6 item in pattern");
2463         }
2464         return ret;
2465 }
2466
2467 /**
2468  * Validate the modify-header TP actions.
2469  *
2470  * @param[in] action_flags
2471  *   Holds the actions detected until now.
2472  * @param[in] action
2473  *   Pointer to the modify action.
2474  * @param[in] item_flags
2475  *   Holds the items detected.
2476  * @param[out] error
2477  *   Pointer to error structure.
2478  *
2479  * @return
2480  *   0 on success, a negative errno value otherwise and rte_errno is set.
2481  */
2482 static int
2483 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
2484                                   const struct rte_flow_action *action,
2485                                   const uint64_t item_flags,
2486                                   struct rte_flow_error *error)
2487 {
2488         int ret = 0;
2489
2490         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2491         if (!ret) {
2492                 if (!(item_flags & MLX5_FLOW_LAYER_L4))
2493                         return rte_flow_error_set(error, EINVAL,
2494                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2495                                                   NULL, "no transport layer "
2496                                                   "in pattern");
2497         }
2498         return ret;
2499 }
2500
2501 /**
2502  * Validate the modify-header actions of increment/decrement
2503  * TCP Sequence-number.
2504  *
2505  * @param[in] action_flags
2506  *   Holds the actions detected until now.
2507  * @param[in] action
2508  *   Pointer to the modify action.
2509  * @param[in] item_flags
2510  *   Holds the items detected.
2511  * @param[out] error
2512  *   Pointer to error structure.
2513  *
2514  * @return
2515  *   0 on success, a negative errno value otherwise and rte_errno is set.
2516  */
2517 static int
2518 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
2519                                        const struct rte_flow_action *action,
2520                                        const uint64_t item_flags,
2521                                        struct rte_flow_error *error)
2522 {
2523         int ret = 0;
2524
2525         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2526         if (!ret) {
2527                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2528                         return rte_flow_error_set(error, EINVAL,
2529                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2530                                                   NULL, "no TCP item in"
2531                                                   " pattern");
2532                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
2533                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
2534                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
2535                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
2536                         return rte_flow_error_set(error, EINVAL,
2537                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2538                                                   NULL,
2539                                                   "cannot decrease and increase"
2540                                                   " TCP sequence number"
2541                                                   " at the same time");
2542         }
2543         return ret;
2544 }
2545
2546 /**
2547  * Validate the modify-header actions of increment/decrement
2548  * TCP Acknowledgment number.
2549  *
2550  * @param[in] action_flags
2551  *   Holds the actions detected until now.
2552  * @param[in] action
2553  *   Pointer to the modify action.
2554  * @param[in] item_flags
2555  *   Holds the items detected.
2556  * @param[out] error
2557  *   Pointer to error structure.
2558  *
2559  * @return
2560  *   0 on success, a negative errno value otherwise and rte_errno is set.
2561  */
2562 static int
2563 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
2564                                        const struct rte_flow_action *action,
2565                                        const uint64_t item_flags,
2566                                        struct rte_flow_error *error)
2567 {
2568         int ret = 0;
2569
2570         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2571         if (!ret) {
2572                 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
2573                         return rte_flow_error_set(error, EINVAL,
2574                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2575                                                   NULL, "no TCP item in"
2576                                                   " pattern");
2577                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
2578                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
2579                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
2580                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
2581                         return rte_flow_error_set(error, EINVAL,
2582                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2583                                                   NULL,
2584                                                   "cannot decrease and increase"
2585                                                   " TCP acknowledgment number"
2586                                                   " at the same time");
2587         }
2588         return ret;
2589 }
2590
2591 /**
2592  * Validate the modify-header TTL actions.
2593  *
2594  * @param[in] action_flags
2595  *   Holds the actions detected until now.
2596  * @param[in] action
2597  *   Pointer to the modify action.
2598  * @param[in] item_flags
2599  *   Holds the items detected.
2600  * @param[out] error
2601  *   Pointer to error structure.
2602  *
2603  * @return
2604  *   0 on success, a negative errno value otherwise and rte_errno is set.
2605  */
2606 static int
2607 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
2608                                    const struct rte_flow_action *action,
2609                                    const uint64_t item_flags,
2610                                    struct rte_flow_error *error)
2611 {
2612         int ret = 0;
2613
2614         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
2615         if (!ret) {
2616                 if (!(item_flags & MLX5_FLOW_LAYER_L3))
2617                         return rte_flow_error_set(error, EINVAL,
2618                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2619                                                   NULL,
2620                                                   "no IP protocol in pattern");
2621         }
2622         return ret;
2623 }
2624
2625 /**
2626  * Validate jump action.
2627  *
2628  * @param[in] action
2629  *   Pointer to the jump action.
2630  * @param[in] action_flags
2631  *   Holds the actions detected until now.
2632  * @param[in] attributes
2633  *   Pointer to flow attributes
2634  * @param[in] external
2635  *   Action belongs to flow rule created by request external to PMD.
2636  * @param[out] error
2637  *   Pointer to error structure.
2638  *
2639  * @return
2640  *   0 on success, a negative errno value otherwise and rte_errno is set.
2641  */
2642 static int
2643 flow_dv_validate_action_jump(const struct rte_flow_action *action,
2644                              uint64_t action_flags,
2645                              const struct rte_flow_attr *attributes,
2646                              bool external, struct rte_flow_error *error)
2647 {
2648         uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
2649                                                     MLX5_MAX_TABLES;
2650         uint32_t target_group, table;
2651         int ret = 0;
2652
2653         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2654                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2655                 return rte_flow_error_set(error, EINVAL,
2656                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2657                                           "can't have 2 fate actions in"
2658                                           " same flow");
2659         if (!action->conf)
2660                 return rte_flow_error_set(error, EINVAL,
2661                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2662                                           NULL, "action configuration not set");
2663         target_group =
2664                 ((const struct rte_flow_action_jump *)action->conf)->group;
2665         ret = mlx5_flow_group_to_table(attributes, external, target_group,
2666                                        &table, error);
2667         if (ret)
2668                 return ret;
2669         if (table >= max_group)
2670                 return rte_flow_error_set(error, EINVAL,
2671                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
2672                                           "target group index out of range");
2673         if (attributes->group >= target_group)
2674                 return rte_flow_error_set(error, EINVAL,
2675                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2676                                           "target group must be higher than"
2677                                           " the current flow group");
2678         return 0;
2679 }
2680
2681 /*
2682  * Validate the port_id action.
2683  *
2684  * @param[in] dev
2685  *   Pointer to rte_eth_dev structure.
2686  * @param[in] action_flags
2687  *   Bit-fields that holds the actions detected until now.
2688  * @param[in] action
2689  *   Port_id RTE action structure.
2690  * @param[in] attr
2691  *   Attributes of flow that includes this action.
2692  * @param[out] error
2693  *   Pointer to error structure.
2694  *
2695  * @return
2696  *   0 on success, a negative errno value otherwise and rte_errno is set.
2697  */
2698 static int
2699 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
2700                                 uint64_t action_flags,
2701                                 const struct rte_flow_action *action,
2702                                 const struct rte_flow_attr *attr,
2703                                 struct rte_flow_error *error)
2704 {
2705         const struct rte_flow_action_port_id *port_id;
2706         struct mlx5_priv *act_priv;
2707         struct mlx5_priv *dev_priv;
2708         uint16_t port;
2709
2710         if (!attr->transfer)
2711                 return rte_flow_error_set(error, ENOTSUP,
2712                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2713                                           NULL,
2714                                           "port id action is valid in transfer"
2715                                           " mode only");
2716         if (!action || !action->conf)
2717                 return rte_flow_error_set(error, ENOTSUP,
2718                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2719                                           NULL,
2720                                           "port id action parameters must be"
2721                                           " specified");
2722         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
2723                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
2724                 return rte_flow_error_set(error, EINVAL,
2725                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2726                                           "can have only one fate actions in"
2727                                           " a flow");
2728         dev_priv = mlx5_dev_to_eswitch_info(dev);
2729         if (!dev_priv)
2730                 return rte_flow_error_set(error, rte_errno,
2731                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2732                                           NULL,
2733                                           "failed to obtain E-Switch info");
2734         port_id = action->conf;
2735         port = port_id->original ? dev->data->port_id : port_id->id;
2736         act_priv = mlx5_port_to_eswitch_info(port, false);
2737         if (!act_priv)
2738                 return rte_flow_error_set
2739                                 (error, rte_errno,
2740                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
2741                                  "failed to obtain E-Switch port id for port");
2742         if (act_priv->domain_id != dev_priv->domain_id)
2743                 return rte_flow_error_set
2744                                 (error, EINVAL,
2745                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2746                                  "port does not belong to"
2747                                  " E-Switch being configured");
2748         return 0;
2749 }
2750
2751 /**
2752  * Get the maximum number of modify header actions.
2753  *
2754  * @param dev
2755  *   Pointer to rte_eth_dev structure.
2756  *
2757  * @return
2758  *   Max number of modify header actions device can support.
2759  */
2760 static unsigned int
2761 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev)
2762 {
2763         /*
2764          * There's no way to directly query the max cap. Although it has to be
2765          * acquried by iterative trial, it is a safe assumption that more
2766          * actions are supported by FW if extensive metadata register is
2767          * supported.
2768          */
2769         return mlx5_flow_ext_mreg_supported(dev) ? MLX5_MODIFY_NUM :
2770                                                    MLX5_MODIFY_NUM_NO_MREG;
2771 }
2772 /**
2773  * Find existing modify-header resource or create and register a new one.
2774  *
2775  * @param dev[in, out]
2776  *   Pointer to rte_eth_dev structure.
2777  * @param[in, out] resource
2778  *   Pointer to modify-header resource.
2779  * @parm[in, out] dev_flow
2780  *   Pointer to the dev_flow.
2781  * @param[out] error
2782  *   pointer to error structure.
2783  *
2784  * @return
2785  *   0 on success otherwise -errno and errno is set.
2786  */
2787 static int
2788 flow_dv_modify_hdr_resource_register
2789                         (struct rte_eth_dev *dev,
2790                          struct mlx5_flow_dv_modify_hdr_resource *resource,
2791                          struct mlx5_flow *dev_flow,
2792                          struct rte_flow_error *error)
2793 {
2794         struct mlx5_priv *priv = dev->data->dev_private;
2795         struct mlx5_ibv_shared *sh = priv->sh;
2796         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
2797         struct mlx5dv_dr_domain *ns;
2798
2799         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev))
2800                 return rte_flow_error_set(error, EOVERFLOW,
2801                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2802                                           "too many modify header items");
2803         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2804                 ns = sh->fdb_domain;
2805         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
2806                 ns = sh->tx_domain;
2807         else
2808                 ns = sh->rx_domain;
2809         resource->flags =
2810                 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
2811         /* Lookup a matching resource from cache. */
2812         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
2813                 if (resource->ft_type == cache_resource->ft_type &&
2814                     resource->actions_num == cache_resource->actions_num &&
2815                     resource->flags == cache_resource->flags &&
2816                     !memcmp((const void *)resource->actions,
2817                             (const void *)cache_resource->actions,
2818                             (resource->actions_num *
2819                                             sizeof(resource->actions[0])))) {
2820                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
2821                                 (void *)cache_resource,
2822                                 rte_atomic32_read(&cache_resource->refcnt));
2823                         rte_atomic32_inc(&cache_resource->refcnt);
2824                         dev_flow->dv.modify_hdr = cache_resource;
2825                         return 0;
2826                 }
2827         }
2828         /* Register new modify-header resource. */
2829         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2830         if (!cache_resource)
2831                 return rte_flow_error_set(error, ENOMEM,
2832                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2833                                           "cannot allocate resource memory");
2834         *cache_resource = *resource;
2835         cache_resource->verbs_action =
2836                 mlx5_glue->dv_create_flow_action_modify_header
2837                                         (sh->ctx, cache_resource->ft_type,
2838                                          ns, cache_resource->flags,
2839                                          cache_resource->actions_num *
2840                                          sizeof(cache_resource->actions[0]),
2841                                          (uint64_t *)cache_resource->actions);
2842         if (!cache_resource->verbs_action) {
2843                 rte_free(cache_resource);
2844                 return rte_flow_error_set(error, ENOMEM,
2845                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2846                                           NULL, "cannot create action");
2847         }
2848         rte_atomic32_init(&cache_resource->refcnt);
2849         rte_atomic32_inc(&cache_resource->refcnt);
2850         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
2851         dev_flow->dv.modify_hdr = cache_resource;
2852         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
2853                 (void *)cache_resource,
2854                 rte_atomic32_read(&cache_resource->refcnt));
2855         return 0;
2856 }
2857
2858 #define MLX5_CNT_CONTAINER_RESIZE 64
2859
2860 /**
2861  * Get or create a flow counter.
2862  *
2863  * @param[in] dev
2864  *   Pointer to the Ethernet device structure.
2865  * @param[in] shared
2866  *   Indicate if this counter is shared with other flows.
2867  * @param[in] id
2868  *   Counter identifier.
2869  *
2870  * @return
2871  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
2872  */
2873 static struct mlx5_flow_counter *
2874 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
2875                                uint32_t id)
2876 {
2877         struct mlx5_priv *priv = dev->data->dev_private;
2878         struct mlx5_flow_counter *cnt = NULL;
2879         struct mlx5_devx_obj *dcs = NULL;
2880
2881         if (!priv->config.devx) {
2882                 rte_errno = ENOTSUP;
2883                 return NULL;
2884         }
2885         if (shared) {
2886                 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
2887                         if (cnt->shared && cnt->id == id) {
2888                                 cnt->ref_cnt++;
2889                                 return cnt;
2890                         }
2891                 }
2892         }
2893         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
2894         if (!dcs)
2895                 return NULL;
2896         cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
2897         if (!cnt) {
2898                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2899                 rte_errno = ENOMEM;
2900                 return NULL;
2901         }
2902         struct mlx5_flow_counter tmpl = {
2903                 .shared = shared,
2904                 .ref_cnt = 1,
2905                 .id = id,
2906                 .dcs = dcs,
2907         };
2908         tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
2909         if (!tmpl.action) {
2910                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
2911                 rte_errno = errno;
2912                 rte_free(cnt);
2913                 return NULL;
2914         }
2915         *cnt = tmpl;
2916         TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
2917         return cnt;
2918 }
2919
2920 /**
2921  * Release a flow counter.
2922  *
2923  * @param[in] dev
2924  *   Pointer to the Ethernet device structure.
2925  * @param[in] counter
2926  *   Pointer to the counter handler.
2927  */
2928 static void
2929 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
2930                                  struct mlx5_flow_counter *counter)
2931 {
2932         struct mlx5_priv *priv = dev->data->dev_private;
2933
2934         if (!counter)
2935                 return;
2936         if (--counter->ref_cnt == 0) {
2937                 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
2938                 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
2939                 rte_free(counter);
2940         }
2941 }
2942
2943 /**
2944  * Query a devx flow counter.
2945  *
2946  * @param[in] dev
2947  *   Pointer to the Ethernet device structure.
2948  * @param[in] cnt
2949  *   Pointer to the flow counter.
2950  * @param[out] pkts
2951  *   The statistics value of packets.
2952  * @param[out] bytes
2953  *   The statistics value of bytes.
2954  *
2955  * @return
2956  *   0 on success, otherwise a negative errno value and rte_errno is set.
2957  */
2958 static inline int
2959 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
2960                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
2961                      uint64_t *bytes)
2962 {
2963         return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
2964                                                 0, NULL, NULL, 0);
2965 }
2966
2967 /**
2968  * Get a pool by a counter.
2969  *
2970  * @param[in] cnt
2971  *   Pointer to the counter.
2972  *
2973  * @return
2974  *   The counter pool.
2975  */
2976 static struct mlx5_flow_counter_pool *
2977 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
2978 {
2979         if (!cnt->batch) {
2980                 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
2981                 return (struct mlx5_flow_counter_pool *)cnt - 1;
2982         }
2983         return cnt->pool;
2984 }
2985
2986 /**
2987  * Get a pool by devx counter ID.
2988  *
2989  * @param[in] cont
2990  *   Pointer to the counter container.
2991  * @param[in] id
2992  *   The counter devx ID.
2993  *
2994  * @return
2995  *   The counter pool pointer if exists, NULL otherwise,
2996  */
2997 static struct mlx5_flow_counter_pool *
2998 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
2999 {
3000         struct mlx5_flow_counter_pool *pool;
3001
3002         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3003                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3004                                 MLX5_COUNTERS_PER_POOL;
3005
3006                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3007                         return pool;
3008         };
3009         return NULL;
3010 }
3011
3012 /**
3013  * Allocate a new memory for the counter values wrapped by all the needed
3014  * management.
3015  *
3016  * @param[in] dev
3017  *   Pointer to the Ethernet device structure.
3018  * @param[in] raws_n
3019  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3020  *
3021  * @return
3022  *   The new memory management pointer on success, otherwise NULL and rte_errno
3023  *   is set.
3024  */
3025 static struct mlx5_counter_stats_mem_mng *
3026 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3027 {
3028         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3029                                         (dev->data->dev_private))->sh;
3030         struct mlx5_devx_mkey_attr mkey_attr;
3031         struct mlx5_counter_stats_mem_mng *mem_mng;
3032         volatile struct flow_counter_stats *raw_data;
3033         int size = (sizeof(struct flow_counter_stats) *
3034                         MLX5_COUNTERS_PER_POOL +
3035                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3036                         sizeof(struct mlx5_counter_stats_mem_mng);
3037         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3038         int i;
3039
3040         if (!mem) {
3041                 rte_errno = ENOMEM;
3042                 return NULL;
3043         }
3044         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3045         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3046         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3047                                                  IBV_ACCESS_LOCAL_WRITE);
3048         if (!mem_mng->umem) {
3049                 rte_errno = errno;
3050                 rte_free(mem);
3051                 return NULL;
3052         }
3053         mkey_attr.addr = (uintptr_t)mem;
3054         mkey_attr.size = size;
3055         mkey_attr.umem_id = mem_mng->umem->umem_id;
3056         mkey_attr.pd = sh->pdn;
3057         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3058         if (!mem_mng->dm) {
3059                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3060                 rte_errno = errno;
3061                 rte_free(mem);
3062                 return NULL;
3063         }
3064         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3065         raw_data = (volatile struct flow_counter_stats *)mem;
3066         for (i = 0; i < raws_n; ++i) {
3067                 mem_mng->raws[i].mem_mng = mem_mng;
3068                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3069         }
3070         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3071         return mem_mng;
3072 }
3073
3074 /**
3075  * Resize a counter container.
3076  *
3077  * @param[in] dev
3078  *   Pointer to the Ethernet device structure.
3079  * @param[in] batch
3080  *   Whether the pool is for counter that was allocated by batch command.
3081  *
3082  * @return
3083  *   The new container pointer on success, otherwise NULL and rte_errno is set.
3084  */
3085 static struct mlx5_pools_container *
3086 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3087 {
3088         struct mlx5_priv *priv = dev->data->dev_private;
3089         struct mlx5_pools_container *cont =
3090                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3091         struct mlx5_pools_container *new_cont =
3092                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3093         struct mlx5_counter_stats_mem_mng *mem_mng;
3094         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3095         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3096         int i;
3097
3098         if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3099                 /* The last resize still hasn't detected by the host thread. */
3100                 rte_errno = EAGAIN;
3101                 return NULL;
3102         }
3103         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3104         if (!new_cont->pools) {
3105                 rte_errno = ENOMEM;
3106                 return NULL;
3107         }
3108         if (cont->n)
3109                 memcpy(new_cont->pools, cont->pools, cont->n *
3110                        sizeof(struct mlx5_flow_counter_pool *));
3111         mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3112                 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3113         if (!mem_mng) {
3114                 rte_free(new_cont->pools);
3115                 return NULL;
3116         }
3117         for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3118                 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3119                                  mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3120                                  i, next);
3121         new_cont->n = resize;
3122         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3123         TAILQ_INIT(&new_cont->pool_list);
3124         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3125         new_cont->init_mem_mng = mem_mng;
3126         rte_cio_wmb();
3127          /* Flip the master container. */
3128         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3129         return new_cont;
3130 }
3131
3132 /**
3133  * Query a devx flow counter.
3134  *
3135  * @param[in] dev
3136  *   Pointer to the Ethernet device structure.
3137  * @param[in] cnt
3138  *   Pointer to the flow counter.
3139  * @param[out] pkts
3140  *   The statistics value of packets.
3141  * @param[out] bytes
3142  *   The statistics value of bytes.
3143  *
3144  * @return
3145  *   0 on success, otherwise a negative errno value and rte_errno is set.
3146  */
3147 static inline int
3148 _flow_dv_query_count(struct rte_eth_dev *dev,
3149                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
3150                      uint64_t *bytes)
3151 {
3152         struct mlx5_priv *priv = dev->data->dev_private;
3153         struct mlx5_flow_counter_pool *pool =
3154                         flow_dv_counter_pool_get(cnt);
3155         int offset = cnt - &pool->counters_raw[0];
3156
3157         if (priv->counter_fallback)
3158                 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3159
3160         rte_spinlock_lock(&pool->sl);
3161         /*
3162          * The single counters allocation may allocate smaller ID than the
3163          * current allocated in parallel to the host reading.
3164          * In this case the new counter values must be reported as 0.
3165          */
3166         if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3167                 *pkts = 0;
3168                 *bytes = 0;
3169         } else {
3170                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
3171                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
3172         }
3173         rte_spinlock_unlock(&pool->sl);
3174         return 0;
3175 }
3176
3177 /**
3178  * Create and initialize a new counter pool.
3179  *
3180  * @param[in] dev
3181  *   Pointer to the Ethernet device structure.
3182  * @param[out] dcs
3183  *   The devX counter handle.
3184  * @param[in] batch
3185  *   Whether the pool is for counter that was allocated by batch command.
3186  *
3187  * @return
3188  *   A new pool pointer on success, NULL otherwise and rte_errno is set.
3189  */
3190 static struct mlx5_flow_counter_pool *
3191 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
3192                     uint32_t batch)
3193 {
3194         struct mlx5_priv *priv = dev->data->dev_private;
3195         struct mlx5_flow_counter_pool *pool;
3196         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3197                                                                0);
3198         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
3199         uint32_t size;
3200
3201         if (cont->n == n_valid) {
3202                 cont = flow_dv_container_resize(dev, batch);
3203                 if (!cont)
3204                         return NULL;
3205         }
3206         size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
3207                         sizeof(struct mlx5_flow_counter);
3208         pool = rte_calloc(__func__, 1, size, 0);
3209         if (!pool) {
3210                 rte_errno = ENOMEM;
3211                 return NULL;
3212         }
3213         pool->min_dcs = dcs;
3214         pool->raw = cont->init_mem_mng->raws + n_valid %
3215                                                      MLX5_CNT_CONTAINER_RESIZE;
3216         pool->raw_hw = NULL;
3217         rte_spinlock_init(&pool->sl);
3218         /*
3219          * The generation of the new allocated counters in this pool is 0, 2 in
3220          * the pool generation makes all the counters valid for allocation.
3221          */
3222         rte_atomic64_set(&pool->query_gen, 0x2);
3223         TAILQ_INIT(&pool->counters);
3224         TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3225         cont->pools[n_valid] = pool;
3226         /* Pool initialization must be updated before host thread access. */
3227         rte_cio_wmb();
3228         rte_atomic16_add(&cont->n_valid, 1);
3229         return pool;
3230 }
3231
3232 /**
3233  * Prepare a new counter and/or a new counter pool.
3234  *
3235  * @param[in] dev
3236  *   Pointer to the Ethernet device structure.
3237  * @param[out] cnt_free
3238  *   Where to put the pointer of a new counter.
3239  * @param[in] batch
3240  *   Whether the pool is for counter that was allocated by batch command.
3241  *
3242  * @return
3243  *   The free counter pool pointer and @p cnt_free is set on success,
3244  *   NULL otherwise and rte_errno is set.
3245  */
3246 static struct mlx5_flow_counter_pool *
3247 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
3248                              struct mlx5_flow_counter **cnt_free,
3249                              uint32_t batch)
3250 {
3251         struct mlx5_priv *priv = dev->data->dev_private;
3252         struct mlx5_flow_counter_pool *pool;
3253         struct mlx5_devx_obj *dcs = NULL;
3254         struct mlx5_flow_counter *cnt;
3255         uint32_t i;
3256
3257         if (!batch) {
3258                 /* bulk_bitmap must be 0 for single counter allocation. */
3259                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3260                 if (!dcs)
3261                         return NULL;
3262                 pool = flow_dv_find_pool_by_id
3263                         (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
3264                 if (!pool) {
3265                         pool = flow_dv_pool_create(dev, dcs, batch);
3266                         if (!pool) {
3267                                 mlx5_devx_cmd_destroy(dcs);
3268                                 return NULL;
3269                         }
3270                 } else if (dcs->id < pool->min_dcs->id) {
3271                         rte_atomic64_set(&pool->a64_dcs,
3272                                          (int64_t)(uintptr_t)dcs);
3273                 }
3274                 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
3275                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3276                 cnt->dcs = dcs;
3277                 *cnt_free = cnt;
3278                 return pool;
3279         }
3280         /* bulk_bitmap is in 128 counters units. */
3281         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
3282                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
3283         if (!dcs) {
3284                 rte_errno = ENODATA;
3285                 return NULL;
3286         }
3287         pool = flow_dv_pool_create(dev, dcs, batch);
3288         if (!pool) {
3289                 mlx5_devx_cmd_destroy(dcs);
3290                 return NULL;
3291         }
3292         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3293                 cnt = &pool->counters_raw[i];
3294                 cnt->pool = pool;
3295                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
3296         }
3297         *cnt_free = &pool->counters_raw[0];
3298         return pool;
3299 }
3300
3301 /**
3302  * Search for existed shared counter.
3303  *
3304  * @param[in] cont
3305  *   Pointer to the relevant counter pool container.
3306  * @param[in] id
3307  *   The shared counter ID to search.
3308  *
3309  * @return
3310  *   NULL if not existed, otherwise pointer to the shared counter.
3311  */
3312 static struct mlx5_flow_counter *
3313 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
3314                               uint32_t id)
3315 {
3316         static struct mlx5_flow_counter *cnt;
3317         struct mlx5_flow_counter_pool *pool;
3318         int i;
3319
3320         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3321                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
3322                         cnt = &pool->counters_raw[i];
3323                         if (cnt->ref_cnt && cnt->shared && cnt->id == id)
3324                                 return cnt;
3325                 }
3326         }
3327         return NULL;
3328 }
3329
3330 /**
3331  * Allocate a flow counter.
3332  *
3333  * @param[in] dev
3334  *   Pointer to the Ethernet device structure.
3335  * @param[in] shared
3336  *   Indicate if this counter is shared with other flows.
3337  * @param[in] id
3338  *   Counter identifier.
3339  * @param[in] group
3340  *   Counter flow group.
3341  *
3342  * @return
3343  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
3344  */
3345 static struct mlx5_flow_counter *
3346 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
3347                       uint16_t group)
3348 {
3349         struct mlx5_priv *priv = dev->data->dev_private;
3350         struct mlx5_flow_counter_pool *pool = NULL;
3351         struct mlx5_flow_counter *cnt_free = NULL;
3352         /*
3353          * Currently group 0 flow counter cannot be assigned to a flow if it is
3354          * not the first one in the batch counter allocation, so it is better
3355          * to allocate counters one by one for these flows in a separate
3356          * container.
3357          * A counter can be shared between different groups so need to take
3358          * shared counters from the single container.
3359          */
3360         uint32_t batch = (group && !shared) ? 1 : 0;
3361         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
3362                                                                0);
3363
3364         if (priv->counter_fallback)
3365                 return flow_dv_counter_alloc_fallback(dev, shared, id);
3366         if (!priv->config.devx) {
3367                 rte_errno = ENOTSUP;
3368                 return NULL;
3369         }
3370         if (shared) {
3371                 cnt_free = flow_dv_counter_shared_search(cont, id);
3372                 if (cnt_free) {
3373                         if (cnt_free->ref_cnt + 1 == 0) {
3374                                 rte_errno = E2BIG;
3375                                 return NULL;
3376                         }
3377                         cnt_free->ref_cnt++;
3378                         return cnt_free;
3379                 }
3380         }
3381         /* Pools which has a free counters are in the start. */
3382         TAILQ_FOREACH(pool, &cont->pool_list, next) {
3383                 /*
3384                  * The free counter reset values must be updated between the
3385                  * counter release to the counter allocation, so, at least one
3386                  * query must be done in this time. ensure it by saving the
3387                  * query generation in the release time.
3388                  * The free list is sorted according to the generation - so if
3389                  * the first one is not updated, all the others are not
3390                  * updated too.
3391                  */
3392                 cnt_free = TAILQ_FIRST(&pool->counters);
3393                 if (cnt_free && cnt_free->query_gen + 1 <
3394                     rte_atomic64_read(&pool->query_gen))
3395                         break;
3396                 cnt_free = NULL;
3397         }
3398         if (!cnt_free) {
3399                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
3400                 if (!pool)
3401                         return NULL;
3402         }
3403         cnt_free->batch = batch;
3404         /* Create a DV counter action only in the first time usage. */
3405         if (!cnt_free->action) {
3406                 uint16_t offset;
3407                 struct mlx5_devx_obj *dcs;
3408
3409                 if (batch) {
3410                         offset = cnt_free - &pool->counters_raw[0];
3411                         dcs = pool->min_dcs;
3412                 } else {
3413                         offset = 0;
3414                         dcs = cnt_free->dcs;
3415                 }
3416                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
3417                                         (dcs->obj, offset);
3418                 if (!cnt_free->action) {
3419                         rte_errno = errno;
3420                         return NULL;
3421                 }
3422         }
3423         /* Update the counter reset values. */
3424         if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
3425                                  &cnt_free->bytes))
3426                 return NULL;
3427         cnt_free->shared = shared;
3428         cnt_free->ref_cnt = 1;
3429         cnt_free->id = id;
3430         if (!priv->sh->cmng.query_thread_on)
3431                 /* Start the asynchronous batch query by the host thread. */
3432                 mlx5_set_query_alarm(priv->sh);
3433         TAILQ_REMOVE(&pool->counters, cnt_free, next);
3434         if (TAILQ_EMPTY(&pool->counters)) {
3435                 /* Move the pool to the end of the container pool list. */
3436                 TAILQ_REMOVE(&cont->pool_list, pool, next);
3437                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
3438         }
3439         return cnt_free;
3440 }
3441
3442 /**
3443  * Release a flow counter.
3444  *
3445  * @param[in] dev
3446  *   Pointer to the Ethernet device structure.
3447  * @param[in] counter
3448  *   Pointer to the counter handler.
3449  */
3450 static void
3451 flow_dv_counter_release(struct rte_eth_dev *dev,
3452                         struct mlx5_flow_counter *counter)
3453 {
3454         struct mlx5_priv *priv = dev->data->dev_private;
3455
3456         if (!counter)
3457                 return;
3458         if (priv->counter_fallback) {
3459                 flow_dv_counter_release_fallback(dev, counter);
3460                 return;
3461         }
3462         if (--counter->ref_cnt == 0) {
3463                 struct mlx5_flow_counter_pool *pool =
3464                                 flow_dv_counter_pool_get(counter);
3465
3466                 /* Put the counter in the end - the last updated one. */
3467                 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
3468                 counter->query_gen = rte_atomic64_read(&pool->query_gen);
3469         }
3470 }
3471
3472 /**
3473  * Verify the @p attributes will be correctly understood by the NIC and store
3474  * them in the @p flow if everything is correct.
3475  *
3476  * @param[in] dev
3477  *   Pointer to dev struct.
3478  * @param[in] attributes
3479  *   Pointer to flow attributes
3480  * @param[in] external
3481  *   This flow rule is created by request external to PMD.
3482  * @param[out] error
3483  *   Pointer to error structure.
3484  *
3485  * @return
3486  *   0 on success, a negative errno value otherwise and rte_errno is set.
3487  */
3488 static int
3489 flow_dv_validate_attributes(struct rte_eth_dev *dev,
3490                             const struct rte_flow_attr *attributes,
3491                             bool external __rte_unused,
3492                             struct rte_flow_error *error)
3493 {
3494         struct mlx5_priv *priv = dev->data->dev_private;
3495         uint32_t priority_max = priv->config.flow_prio - 1;
3496
3497 #ifndef HAVE_MLX5DV_DR
3498         if (attributes->group)
3499                 return rte_flow_error_set(error, ENOTSUP,
3500                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
3501                                           NULL,
3502                                           "groups are not supported");
3503 #else
3504         uint32_t max_group = attributes->transfer ? MLX5_MAX_TABLES_FDB :
3505                                                     MLX5_MAX_TABLES;
3506         uint32_t table;
3507         int ret;
3508
3509         ret = mlx5_flow_group_to_table(attributes, external,
3510                                        attributes->group,
3511                                        &table, error);
3512         if (ret)
3513                 return ret;
3514         if (table >= max_group)
3515                 return rte_flow_error_set(error, EINVAL,
3516                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL,
3517                                           "group index out of range");
3518 #endif
3519         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
3520             attributes->priority >= priority_max)
3521                 return rte_flow_error_set(error, ENOTSUP,
3522                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
3523                                           NULL,
3524                                           "priority out of range");
3525         if (attributes->transfer) {
3526                 if (!priv->config.dv_esw_en)
3527                         return rte_flow_error_set
3528                                 (error, ENOTSUP,
3529                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3530                                  "E-Switch dr is not supported");
3531                 if (!(priv->representor || priv->master))
3532                         return rte_flow_error_set
3533                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3534                                  NULL, "E-Switch configuration can only be"
3535                                  " done by a master or a representor device");
3536                 if (attributes->egress)
3537                         return rte_flow_error_set
3538                                 (error, ENOTSUP,
3539                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
3540                                  "egress is not supported");
3541         }
3542         if (!(attributes->egress ^ attributes->ingress))
3543                 return rte_flow_error_set(error, ENOTSUP,
3544                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
3545                                           "must specify exactly one of "
3546                                           "ingress or egress");
3547         return 0;
3548 }
3549
3550 /**
3551  * Internal validation function. For validating both actions and items.
3552  *
3553  * @param[in] dev
3554  *   Pointer to the rte_eth_dev structure.
3555  * @param[in] attr
3556  *   Pointer to the flow attributes.
3557  * @param[in] items
3558  *   Pointer to the list of items.
3559  * @param[in] actions
3560  *   Pointer to the list of actions.
3561  * @param[in] external
3562  *   This flow rule is created by request external to PMD.
3563  * @param[out] error
3564  *   Pointer to the error structure.
3565  *
3566  * @return
3567  *   0 on success, a negative errno value otherwise and rte_errno is set.
3568  */
3569 static int
3570 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
3571                  const struct rte_flow_item items[],
3572                  const struct rte_flow_action actions[],
3573                  bool external, struct rte_flow_error *error)
3574 {
3575         int ret;
3576         uint64_t action_flags = 0;
3577         uint64_t item_flags = 0;
3578         uint64_t last_item = 0;
3579         uint8_t next_protocol = 0xff;
3580         uint16_t ether_type = 0;
3581         int actions_n = 0;
3582         const struct rte_flow_item *gre_item = NULL;
3583         struct rte_flow_item_tcp nic_tcp_mask = {
3584                 .hdr = {
3585                         .tcp_flags = 0xFF,
3586                         .src_port = RTE_BE16(UINT16_MAX),
3587                         .dst_port = RTE_BE16(UINT16_MAX),
3588                 }
3589         };
3590
3591         if (items == NULL)
3592                 return -1;
3593         ret = flow_dv_validate_attributes(dev, attr, external, error);
3594         if (ret < 0)
3595                 return ret;
3596         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3597                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
3598                 int type = items->type;
3599
3600                 switch (type) {
3601                 case RTE_FLOW_ITEM_TYPE_VOID:
3602                         break;
3603                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
3604                         ret = flow_dv_validate_item_port_id
3605                                         (dev, items, attr, item_flags, error);
3606                         if (ret < 0)
3607                                 return ret;
3608                         last_item = MLX5_FLOW_ITEM_PORT_ID;
3609                         break;
3610                 case RTE_FLOW_ITEM_TYPE_ETH:
3611                         ret = mlx5_flow_validate_item_eth(items, item_flags,
3612                                                           error);
3613                         if (ret < 0)
3614                                 return ret;
3615                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
3616                                              MLX5_FLOW_LAYER_OUTER_L2;
3617                         if (items->mask != NULL && items->spec != NULL) {
3618                                 ether_type =
3619                                         ((const struct rte_flow_item_eth *)
3620                                          items->spec)->type;
3621                                 ether_type &=
3622                                         ((const struct rte_flow_item_eth *)
3623                                          items->mask)->type;
3624                                 ether_type = rte_be_to_cpu_16(ether_type);
3625                         } else {
3626                                 ether_type = 0;
3627                         }
3628                         break;
3629                 case RTE_FLOW_ITEM_TYPE_VLAN:
3630                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
3631                                                            dev, error);
3632                         if (ret < 0)
3633                                 return ret;
3634                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
3635                                              MLX5_FLOW_LAYER_OUTER_VLAN;
3636                         if (items->mask != NULL && items->spec != NULL) {
3637                                 ether_type =
3638                                         ((const struct rte_flow_item_vlan *)
3639                                          items->spec)->inner_type;
3640                                 ether_type &=
3641                                         ((const struct rte_flow_item_vlan *)
3642                                          items->mask)->inner_type;
3643                                 ether_type = rte_be_to_cpu_16(ether_type);
3644                         } else {
3645                                 ether_type = 0;
3646                         }
3647                         break;
3648                 case RTE_FLOW_ITEM_TYPE_IPV4:
3649                         mlx5_flow_tunnel_ip_check(items, next_protocol,
3650                                                   &item_flags, &tunnel);
3651                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
3652                                                            last_item,
3653                                                            ether_type, NULL,
3654                                                            error);
3655                         if (ret < 0)
3656                                 return ret;
3657                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3658                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3659                         if (items->mask != NULL &&
3660                             ((const struct rte_flow_item_ipv4 *)
3661                              items->mask)->hdr.next_proto_id) {
3662                                 next_protocol =
3663                                         ((const struct rte_flow_item_ipv4 *)
3664                                          (items->spec))->hdr.next_proto_id;
3665                                 next_protocol &=
3666                                         ((const struct rte_flow_item_ipv4 *)
3667                                          (items->mask))->hdr.next_proto_id;
3668                         } else {
3669                                 /* Reset for inner layer. */
3670                                 next_protocol = 0xff;
3671                         }
3672                         break;
3673                 case RTE_FLOW_ITEM_TYPE_IPV6:
3674                         mlx5_flow_tunnel_ip_check(items, next_protocol,
3675                                                   &item_flags, &tunnel);
3676                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
3677                                                            last_item,
3678                                                            ether_type, NULL,
3679                                                            error);
3680                         if (ret < 0)
3681                                 return ret;
3682                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3683                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3684                         if (items->mask != NULL &&
3685                             ((const struct rte_flow_item_ipv6 *)
3686                              items->mask)->hdr.proto) {
3687                                 next_protocol =
3688                                         ((const struct rte_flow_item_ipv6 *)
3689                                          items->spec)->hdr.proto;
3690                                 next_protocol &=
3691                                         ((const struct rte_flow_item_ipv6 *)
3692                                          items->mask)->hdr.proto;
3693                         } else {
3694                                 /* Reset for inner layer. */
3695                                 next_protocol = 0xff;
3696                         }
3697                         break;
3698                 case RTE_FLOW_ITEM_TYPE_TCP:
3699                         ret = mlx5_flow_validate_item_tcp
3700                                                 (items, item_flags,
3701                                                  next_protocol,
3702                                                  &nic_tcp_mask,
3703                                                  error);
3704                         if (ret < 0)
3705                                 return ret;
3706                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
3707                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
3708                         break;
3709                 case RTE_FLOW_ITEM_TYPE_UDP:
3710                         ret = mlx5_flow_validate_item_udp(items, item_flags,
3711                                                           next_protocol,
3712                                                           error);
3713                         if (ret < 0)
3714                                 return ret;
3715                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
3716                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
3717                         break;
3718                 case RTE_FLOW_ITEM_TYPE_GRE:
3719                         ret = mlx5_flow_validate_item_gre(items, item_flags,
3720                                                           next_protocol, error);
3721                         if (ret < 0)
3722                                 return ret;
3723                         gre_item = items;
3724                         last_item = MLX5_FLOW_LAYER_GRE;
3725                         break;
3726                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3727                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
3728                                                             next_protocol,
3729                                                             error);
3730                         if (ret < 0)
3731                                 return ret;
3732                         last_item = MLX5_FLOW_LAYER_NVGRE;
3733                         break;
3734                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
3735                         ret = mlx5_flow_validate_item_gre_key
3736                                 (items, item_flags, gre_item, error);
3737                         if (ret < 0)
3738                                 return ret;
3739                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
3740                         break;
3741                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3742                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
3743                                                             error);
3744                         if (ret < 0)
3745                                 return ret;
3746                         last_item = MLX5_FLOW_LAYER_VXLAN;
3747                         break;
3748                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3749                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
3750                                                                 item_flags, dev,
3751                                                                 error);
3752                         if (ret < 0)
3753                                 return ret;
3754                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3755                         break;
3756                 case RTE_FLOW_ITEM_TYPE_GENEVE:
3757                         ret = mlx5_flow_validate_item_geneve(items,
3758                                                              item_flags, dev,
3759                                                              error);
3760                         if (ret < 0)
3761                                 return ret;
3762                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
3763                         break;
3764                 case RTE_FLOW_ITEM_TYPE_MPLS:
3765                         ret = mlx5_flow_validate_item_mpls(dev, items,
3766                                                            item_flags,
3767                                                            last_item, error);
3768                         if (ret < 0)
3769                                 return ret;
3770                         last_item = MLX5_FLOW_LAYER_MPLS;
3771                         break;
3772                 case RTE_FLOW_ITEM_TYPE_META:
3773                         ret = flow_dv_validate_item_meta(dev, items, attr,
3774                                                          error);
3775                         if (ret < 0)
3776                                 return ret;
3777                         last_item = MLX5_FLOW_ITEM_METADATA;
3778                         break;
3779                 case RTE_FLOW_ITEM_TYPE_ICMP:
3780                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
3781                                                            next_protocol,
3782                                                            error);
3783                         if (ret < 0)
3784                                 return ret;
3785                         last_item = MLX5_FLOW_LAYER_ICMP;
3786                         break;
3787                 case RTE_FLOW_ITEM_TYPE_ICMP6:
3788                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
3789                                                             next_protocol,
3790                                                             error);
3791                         if (ret < 0)
3792                                 return ret;
3793                         last_item = MLX5_FLOW_LAYER_ICMP6;
3794                         break;
3795                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
3796                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
3797                         break;
3798                 default:
3799                         return rte_flow_error_set(error, ENOTSUP,
3800                                                   RTE_FLOW_ERROR_TYPE_ITEM,
3801                                                   NULL, "item not supported");
3802                 }
3803                 item_flags |= last_item;
3804         }
3805         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
3806                 int type = actions->type;
3807                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
3808                         return rte_flow_error_set(error, ENOTSUP,
3809                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3810                                                   actions, "too many actions");
3811                 switch (type) {
3812                 case RTE_FLOW_ACTION_TYPE_VOID:
3813                         break;
3814                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
3815                         ret = flow_dv_validate_action_port_id(dev,
3816                                                               action_flags,
3817                                                               actions,
3818                                                               attr,
3819                                                               error);
3820                         if (ret)
3821                                 return ret;
3822                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
3823                         ++actions_n;
3824                         break;
3825                 case RTE_FLOW_ACTION_TYPE_FLAG:
3826                         ret = mlx5_flow_validate_action_flag(action_flags,
3827                                                              attr, error);
3828                         if (ret < 0)
3829                                 return ret;
3830                         action_flags |= MLX5_FLOW_ACTION_FLAG;
3831                         ++actions_n;
3832                         break;
3833                 case RTE_FLOW_ACTION_TYPE_MARK:
3834                         ret = mlx5_flow_validate_action_mark(actions,
3835                                                              action_flags,
3836                                                              attr, error);
3837                         if (ret < 0)
3838                                 return ret;
3839                         action_flags |= MLX5_FLOW_ACTION_MARK;
3840                         ++actions_n;
3841                         break;
3842                 case RTE_FLOW_ACTION_TYPE_DROP:
3843                         ret = mlx5_flow_validate_action_drop(action_flags,
3844                                                              attr, error);
3845                         if (ret < 0)
3846                                 return ret;
3847                         action_flags |= MLX5_FLOW_ACTION_DROP;
3848                         ++actions_n;
3849                         break;
3850                 case RTE_FLOW_ACTION_TYPE_QUEUE:
3851                         ret = mlx5_flow_validate_action_queue(actions,
3852                                                               action_flags, dev,
3853                                                               attr, error);
3854                         if (ret < 0)
3855                                 return ret;
3856                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
3857                         ++actions_n;
3858                         break;
3859                 case RTE_FLOW_ACTION_TYPE_RSS:
3860                         ret = mlx5_flow_validate_action_rss(actions,
3861                                                             action_flags, dev,
3862                                                             attr, item_flags,
3863                                                             error);
3864                         if (ret < 0)
3865                                 return ret;
3866                         action_flags |= MLX5_FLOW_ACTION_RSS;
3867                         ++actions_n;
3868                         break;
3869                 case RTE_FLOW_ACTION_TYPE_COUNT:
3870                         ret = flow_dv_validate_action_count(dev, error);
3871                         if (ret < 0)
3872                                 return ret;
3873                         action_flags |= MLX5_FLOW_ACTION_COUNT;
3874                         ++actions_n;
3875                         break;
3876                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
3877                         if (flow_dv_validate_action_pop_vlan(dev,
3878                                                              action_flags,
3879                                                              actions,
3880                                                              item_flags, attr,
3881                                                              error))
3882                                 return -rte_errno;
3883                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
3884                         ++actions_n;
3885                         break;
3886                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
3887                         ret = flow_dv_validate_action_push_vlan(action_flags,
3888                                                                 item_flags,
3889                                                                 actions, attr,
3890                                                                 error);
3891                         if (ret < 0)
3892                                 return ret;
3893                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
3894                         ++actions_n;
3895                         break;
3896                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
3897                         ret = flow_dv_validate_action_set_vlan_pcp
3898                                                 (action_flags, actions, error);
3899                         if (ret < 0)
3900                                 return ret;
3901                         /* Count PCP with push_vlan command. */
3902                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
3903                         break;
3904                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
3905                         ret = flow_dv_validate_action_set_vlan_vid
3906                                                 (item_flags, action_flags,
3907                                                  actions, error);
3908                         if (ret < 0)
3909                                 return ret;
3910                         /* Count VID with push_vlan command. */
3911                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
3912                         break;
3913                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
3914                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
3915                         ret = flow_dv_validate_action_l2_encap(action_flags,
3916                                                                actions, attr,
3917                                                                error);
3918                         if (ret < 0)
3919                                 return ret;
3920                         action_flags |= actions->type ==
3921                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
3922                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
3923                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
3924                         ++actions_n;
3925                         break;
3926                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
3927                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
3928                         ret = flow_dv_validate_action_l2_decap(action_flags,
3929                                                                attr, error);
3930                         if (ret < 0)
3931                                 return ret;
3932                         action_flags |= actions->type ==
3933                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
3934                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
3935                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
3936                         ++actions_n;
3937                         break;
3938                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
3939                         ret = flow_dv_validate_action_raw_encap(action_flags,
3940                                                                 actions, attr,
3941                                                                 error);
3942                         if (ret < 0)
3943                                 return ret;
3944                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
3945                         ++actions_n;
3946                         break;
3947                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
3948                         ret = flow_dv_validate_action_raw_decap(action_flags,
3949                                                                 actions, attr,
3950                                                                 error);
3951                         if (ret < 0)
3952                                 return ret;
3953                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
3954                         ++actions_n;
3955                         break;
3956                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
3957                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
3958                         ret = flow_dv_validate_action_modify_mac(action_flags,
3959                                                                  actions,
3960                                                                  item_flags,
3961                                                                  error);
3962                         if (ret < 0)
3963                                 return ret;
3964                         /* Count all modify-header actions as one action. */
3965                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3966                                 ++actions_n;
3967                         action_flags |= actions->type ==
3968                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
3969                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
3970                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
3971                         break;
3972
3973                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
3974                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
3975                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
3976                                                                   actions,
3977                                                                   item_flags,
3978                                                                   error);
3979                         if (ret < 0)
3980                                 return ret;
3981                         /* Count all modify-header actions as one action. */
3982                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3983                                 ++actions_n;
3984                         action_flags |= actions->type ==
3985                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
3986                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
3987                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
3988                         break;
3989                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
3990                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
3991                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
3992                                                                   actions,
3993                                                                   item_flags,
3994                                                                   error);
3995                         if (ret < 0)
3996                                 return ret;
3997                         /* Count all modify-header actions as one action. */
3998                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
3999                                 ++actions_n;
4000                         action_flags |= actions->type ==
4001                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4002                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4003                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
4004                         break;
4005                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4006                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4007                         ret = flow_dv_validate_action_modify_tp(action_flags,
4008                                                                 actions,
4009                                                                 item_flags,
4010                                                                 error);
4011                         if (ret < 0)
4012                                 return ret;
4013                         /* Count all modify-header actions as one action. */
4014                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4015                                 ++actions_n;
4016                         action_flags |= actions->type ==
4017                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4018                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
4019                                                 MLX5_FLOW_ACTION_SET_TP_DST;
4020                         break;
4021                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4022                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4023                         ret = flow_dv_validate_action_modify_ttl(action_flags,
4024                                                                  actions,
4025                                                                  item_flags,
4026                                                                  error);
4027                         if (ret < 0)
4028                                 return ret;
4029                         /* Count all modify-header actions as one action. */
4030                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4031                                 ++actions_n;
4032                         action_flags |= actions->type ==
4033                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
4034                                                 MLX5_FLOW_ACTION_SET_TTL :
4035                                                 MLX5_FLOW_ACTION_DEC_TTL;
4036                         break;
4037                 case RTE_FLOW_ACTION_TYPE_JUMP:
4038                         ret = flow_dv_validate_action_jump(actions,
4039                                                            action_flags,
4040                                                            attr, external,
4041                                                            error);
4042                         if (ret)
4043                                 return ret;
4044                         ++actions_n;
4045                         action_flags |= MLX5_FLOW_ACTION_JUMP;
4046                         break;
4047                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4048                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4049                         ret = flow_dv_validate_action_modify_tcp_seq
4050                                                                 (action_flags,
4051                                                                  actions,
4052                                                                  item_flags,
4053                                                                  error);
4054                         if (ret < 0)
4055                                 return ret;
4056                         /* Count all modify-header actions as one action. */
4057                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4058                                 ++actions_n;
4059                         action_flags |= actions->type ==
4060                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4061                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4062                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4063                         break;
4064                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4065                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4066                         ret = flow_dv_validate_action_modify_tcp_ack
4067                                                                 (action_flags,
4068                                                                  actions,
4069                                                                  item_flags,
4070                                                                  error);
4071                         if (ret < 0)
4072                                 return ret;
4073                         /* Count all modify-header actions as one action. */
4074                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4075                                 ++actions_n;
4076                         action_flags |= actions->type ==
4077                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4078                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
4079                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4080                         break;
4081                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4082                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4083                         break;
4084                 default:
4085                         return rte_flow_error_set(error, ENOTSUP,
4086                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4087                                                   actions,
4088                                                   "action not supported");
4089                 }
4090         }
4091         if ((action_flags & MLX5_FLOW_LAYER_TUNNEL) &&
4092             (action_flags & MLX5_FLOW_VLAN_ACTIONS))
4093                 return rte_flow_error_set(error, ENOTSUP,
4094                                           RTE_FLOW_ERROR_TYPE_ACTION,
4095                                           actions,
4096                                           "can't have vxlan and vlan"
4097                                           " actions in the same rule");
4098         /* Eswitch has few restrictions on using items and actions */
4099         if (attr->transfer) {
4100                 if (action_flags & MLX5_FLOW_ACTION_FLAG)
4101                         return rte_flow_error_set(error, ENOTSUP,
4102                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4103                                                   NULL,
4104                                                   "unsupported action FLAG");
4105                 if (action_flags & MLX5_FLOW_ACTION_MARK)
4106                         return rte_flow_error_set(error, ENOTSUP,
4107                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4108                                                   NULL,
4109                                                   "unsupported action MARK");
4110                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
4111                         return rte_flow_error_set(error, ENOTSUP,
4112                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4113                                                   NULL,
4114                                                   "unsupported action QUEUE");
4115                 if (action_flags & MLX5_FLOW_ACTION_RSS)
4116                         return rte_flow_error_set(error, ENOTSUP,
4117                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4118                                                   NULL,
4119                                                   "unsupported action RSS");
4120                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4121                         return rte_flow_error_set(error, EINVAL,
4122                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4123                                                   actions,
4124                                                   "no fate action is found");
4125         } else {
4126                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
4127                         return rte_flow_error_set(error, EINVAL,
4128                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4129                                                   actions,
4130                                                   "no fate action is found");
4131         }
4132         return 0;
4133 }
4134
4135 /**
4136  * Internal preparation function. Allocates the DV flow size,
4137  * this size is constant.
4138  *
4139  * @param[in] attr
4140  *   Pointer to the flow attributes.
4141  * @param[in] items
4142  *   Pointer to the list of items.
4143  * @param[in] actions
4144  *   Pointer to the list of actions.
4145  * @param[out] error
4146  *   Pointer to the error structure.
4147  *
4148  * @return
4149  *   Pointer to mlx5_flow object on success,
4150  *   otherwise NULL and rte_errno is set.
4151  */
4152 static struct mlx5_flow *
4153 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
4154                 const struct rte_flow_item items[] __rte_unused,
4155                 const struct rte_flow_action actions[] __rte_unused,
4156                 struct rte_flow_error *error)
4157 {
4158         size_t size = sizeof(struct mlx5_flow);
4159         struct mlx5_flow *dev_flow;
4160
4161         dev_flow = rte_calloc(__func__, 1, size, 0);
4162         if (!dev_flow) {
4163                 rte_flow_error_set(error, ENOMEM,
4164                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4165                                    "not enough memory to create flow");
4166                 return NULL;
4167         }
4168         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
4169         dev_flow->ingress = attr->ingress;
4170         dev_flow->transfer = attr->transfer;
4171         return dev_flow;
4172 }
4173
4174 #ifndef NDEBUG
4175 /**
4176  * Sanity check for match mask and value. Similar to check_valid_spec() in
4177  * kernel driver. If unmasked bit is present in value, it returns failure.
4178  *
4179  * @param match_mask
4180  *   pointer to match mask buffer.
4181  * @param match_value
4182  *   pointer to match value buffer.
4183  *
4184  * @return
4185  *   0 if valid, -EINVAL otherwise.
4186  */
4187 static int
4188 flow_dv_check_valid_spec(void *match_mask, void *match_value)
4189 {
4190         uint8_t *m = match_mask;
4191         uint8_t *v = match_value;
4192         unsigned int i;
4193
4194         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
4195                 if (v[i] & ~m[i]) {
4196                         DRV_LOG(ERR,
4197                                 "match_value differs from match_criteria"
4198                                 " %p[%u] != %p[%u]",
4199                                 match_value, i, match_mask, i);
4200                         return -EINVAL;
4201                 }
4202         }
4203         return 0;
4204 }
4205 #endif
4206
4207 /**
4208  * Add Ethernet item to matcher and to the value.
4209  *
4210  * @param[in, out] matcher
4211  *   Flow matcher.
4212  * @param[in, out] key
4213  *   Flow matcher value.
4214  * @param[in] item
4215  *   Flow pattern to translate.
4216  * @param[in] inner
4217  *   Item is inner pattern.
4218  */
4219 static void
4220 flow_dv_translate_item_eth(void *matcher, void *key,
4221                            const struct rte_flow_item *item, int inner)
4222 {
4223         const struct rte_flow_item_eth *eth_m = item->mask;
4224         const struct rte_flow_item_eth *eth_v = item->spec;
4225         const struct rte_flow_item_eth nic_mask = {
4226                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4227                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
4228                 .type = RTE_BE16(0xffff),
4229         };
4230         void *headers_m;
4231         void *headers_v;
4232         char *l24_v;
4233         unsigned int i;
4234
4235         if (!eth_v)
4236                 return;
4237         if (!eth_m)
4238                 eth_m = &nic_mask;
4239         if (inner) {
4240                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4241                                          inner_headers);
4242                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4243         } else {
4244                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4245                                          outer_headers);
4246                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4247         }
4248         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
4249                &eth_m->dst, sizeof(eth_m->dst));
4250         /* The value must be in the range of the mask. */
4251         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
4252         for (i = 0; i < sizeof(eth_m->dst); ++i)
4253                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
4254         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
4255                &eth_m->src, sizeof(eth_m->src));
4256         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
4257         /* The value must be in the range of the mask. */
4258         for (i = 0; i < sizeof(eth_m->dst); ++i)
4259                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
4260         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4261                  rte_be_to_cpu_16(eth_m->type));
4262         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
4263         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
4264 }
4265
4266 /**
4267  * Add VLAN item to matcher and to the value.
4268  *
4269  * @param[in, out] dev_flow
4270  *   Flow descriptor.
4271  * @param[in, out] matcher
4272  *   Flow matcher.
4273  * @param[in, out] key
4274  *   Flow matcher value.
4275  * @param[in] item
4276  *   Flow pattern to translate.
4277  * @param[in] inner
4278  *   Item is inner pattern.
4279  */
4280 static void
4281 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
4282                             void *matcher, void *key,
4283                             const struct rte_flow_item *item,
4284                             int inner)
4285 {
4286         const struct rte_flow_item_vlan *vlan_m = item->mask;
4287         const struct rte_flow_item_vlan *vlan_v = item->spec;
4288         void *headers_m;
4289         void *headers_v;
4290         uint16_t tci_m;
4291         uint16_t tci_v;
4292
4293         if (!vlan_v)
4294                 return;
4295         if (!vlan_m)
4296                 vlan_m = &rte_flow_item_vlan_mask;
4297         if (inner) {
4298                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4299                                          inner_headers);
4300                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4301         } else {
4302                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4303                                          outer_headers);
4304                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4305                 /*
4306                  * This is workaround, masks are not supported,
4307                  * and pre-validated.
4308                  */
4309                 dev_flow->dv.vf_vlan.tag =
4310                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
4311         }
4312         tci_m = rte_be_to_cpu_16(vlan_m->tci);
4313         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
4314         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
4315         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
4316         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
4317         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
4318         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
4319         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
4320         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
4321         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
4322         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
4323                  rte_be_to_cpu_16(vlan_m->inner_type));
4324         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
4325                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
4326 }
4327
4328 /**
4329  * Add IPV4 item to matcher and to the value.
4330  *
4331  * @param[in, out] matcher
4332  *   Flow matcher.
4333  * @param[in, out] key
4334  *   Flow matcher value.
4335  * @param[in] item
4336  *   Flow pattern to translate.
4337  * @param[in] inner
4338  *   Item is inner pattern.
4339  * @param[in] group
4340  *   The group to insert the rule.
4341  */
4342 static void
4343 flow_dv_translate_item_ipv4(void *matcher, void *key,
4344                             const struct rte_flow_item *item,
4345                             int inner, uint32_t group)
4346 {
4347         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
4348         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
4349         const struct rte_flow_item_ipv4 nic_mask = {
4350                 .hdr = {
4351                         .src_addr = RTE_BE32(0xffffffff),
4352                         .dst_addr = RTE_BE32(0xffffffff),
4353                         .type_of_service = 0xff,
4354                         .next_proto_id = 0xff,
4355                 },
4356         };
4357         void *headers_m;
4358         void *headers_v;
4359         char *l24_m;
4360         char *l24_v;
4361         uint8_t tos;
4362
4363         if (inner) {
4364                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4365                                          inner_headers);
4366                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4367         } else {
4368                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4369                                          outer_headers);
4370                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4371         }
4372         if (group == 0)
4373                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4374         else
4375                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
4376         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
4377         if (!ipv4_v)
4378                 return;
4379         if (!ipv4_m)
4380                 ipv4_m = &nic_mask;
4381         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4382                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4383         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4384                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
4385         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
4386         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
4387         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4388                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
4389         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4390                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
4391         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
4392         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
4393         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
4394         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
4395                  ipv4_m->hdr.type_of_service);
4396         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
4397         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
4398                  ipv4_m->hdr.type_of_service >> 2);
4399         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
4400         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4401                  ipv4_m->hdr.next_proto_id);
4402         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4403                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
4404 }
4405
4406 /**
4407  * Add IPV6 item to matcher and to the value.
4408  *
4409  * @param[in, out] matcher
4410  *   Flow matcher.
4411  * @param[in, out] key
4412  *   Flow matcher value.
4413  * @param[in] item
4414  *   Flow pattern to translate.
4415  * @param[in] inner
4416  *   Item is inner pattern.
4417  * @param[in] group
4418  *   The group to insert the rule.
4419  */
4420 static void
4421 flow_dv_translate_item_ipv6(void *matcher, void *key,
4422                             const struct rte_flow_item *item,
4423                             int inner, uint32_t group)
4424 {
4425         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
4426         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
4427         const struct rte_flow_item_ipv6 nic_mask = {
4428                 .hdr = {
4429                         .src_addr =
4430                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
4431                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
4432                         .dst_addr =
4433                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
4434                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
4435                         .vtc_flow = RTE_BE32(0xffffffff),
4436                         .proto = 0xff,
4437                         .hop_limits = 0xff,
4438                 },
4439         };
4440         void *headers_m;
4441         void *headers_v;
4442         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4443         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4444         char *l24_m;
4445         char *l24_v;
4446         uint32_t vtc_m;
4447         uint32_t vtc_v;
4448         int i;
4449         int size;
4450
4451         if (inner) {
4452                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4453                                          inner_headers);
4454                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4455         } else {
4456                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4457                                          outer_headers);
4458                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4459         }
4460         if (group == 0)
4461                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
4462         else
4463                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
4464         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
4465         if (!ipv6_v)
4466                 return;
4467         if (!ipv6_m)
4468                 ipv6_m = &nic_mask;
4469         size = sizeof(ipv6_m->hdr.dst_addr);
4470         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4471                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4472         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4473                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
4474         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
4475         for (i = 0; i < size; ++i)
4476                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
4477         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
4478                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
4479         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
4480                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
4481         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
4482         for (i = 0; i < size; ++i)
4483                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
4484         /* TOS. */
4485         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
4486         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
4487         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
4488         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
4489         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
4490         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
4491         /* Label. */
4492         if (inner) {
4493                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
4494                          vtc_m);
4495                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
4496                          vtc_v);
4497         } else {
4498                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
4499                          vtc_m);
4500                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
4501                          vtc_v);
4502         }
4503         /* Protocol. */
4504         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
4505                  ipv6_m->hdr.proto);
4506         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4507                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
4508 }
4509
4510 /**
4511  * Add TCP item to matcher and to the value.
4512  *
4513  * @param[in, out] matcher
4514  *   Flow matcher.
4515  * @param[in, out] key
4516  *   Flow matcher value.
4517  * @param[in] item
4518  *   Flow pattern to translate.
4519  * @param[in] inner
4520  *   Item is inner pattern.
4521  */
4522 static void
4523 flow_dv_translate_item_tcp(void *matcher, void *key,
4524                            const struct rte_flow_item *item,
4525                            int inner)
4526 {
4527         const struct rte_flow_item_tcp *tcp_m = item->mask;
4528         const struct rte_flow_item_tcp *tcp_v = item->spec;
4529         void *headers_m;
4530         void *headers_v;
4531
4532         if (inner) {
4533                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4534                                          inner_headers);
4535                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4536         } else {
4537                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4538                                          outer_headers);
4539                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4540         }
4541         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4542         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
4543         if (!tcp_v)
4544                 return;
4545         if (!tcp_m)
4546                 tcp_m = &rte_flow_item_tcp_mask;
4547         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
4548                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
4549         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
4550                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
4551         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
4552                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
4553         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
4554                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
4555         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
4556                  tcp_m->hdr.tcp_flags);
4557         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
4558                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
4559 }
4560
4561 /**
4562  * Add UDP item to matcher and to the value.
4563  *
4564  * @param[in, out] matcher
4565  *   Flow matcher.
4566  * @param[in, out] key
4567  *   Flow matcher value.
4568  * @param[in] item
4569  *   Flow pattern to translate.
4570  * @param[in] inner
4571  *   Item is inner pattern.
4572  */
4573 static void
4574 flow_dv_translate_item_udp(void *matcher, void *key,
4575                            const struct rte_flow_item *item,
4576                            int inner)
4577 {
4578         const struct rte_flow_item_udp *udp_m = item->mask;
4579         const struct rte_flow_item_udp *udp_v = item->spec;
4580         void *headers_m;
4581         void *headers_v;
4582
4583         if (inner) {
4584                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4585                                          inner_headers);
4586                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4587         } else {
4588                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4589                                          outer_headers);
4590                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4591         }
4592         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4593         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
4594         if (!udp_v)
4595                 return;
4596         if (!udp_m)
4597                 udp_m = &rte_flow_item_udp_mask;
4598         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
4599                  rte_be_to_cpu_16(udp_m->hdr.src_port));
4600         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
4601                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
4602         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
4603                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
4604         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4605                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
4606 }
4607
4608 /**
4609  * Add GRE optional Key item to matcher and to the value.
4610  *
4611  * @param[in, out] matcher
4612  *   Flow matcher.
4613  * @param[in, out] key
4614  *   Flow matcher value.
4615  * @param[in] item
4616  *   Flow pattern to translate.
4617  * @param[in] inner
4618  *   Item is inner pattern.
4619  */
4620 static void
4621 flow_dv_translate_item_gre_key(void *matcher, void *key,
4622                                    const struct rte_flow_item *item)
4623 {
4624         const rte_be32_t *key_m = item->mask;
4625         const rte_be32_t *key_v = item->spec;
4626         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4627         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4628         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
4629
4630         if (!key_v)
4631                 return;
4632         if (!key_m)
4633                 key_m = &gre_key_default_mask;
4634         /* GRE K bit must be on and should already be validated */
4635         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
4636         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
4637         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
4638                  rte_be_to_cpu_32(*key_m) >> 8);
4639         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
4640                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
4641         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
4642                  rte_be_to_cpu_32(*key_m) & 0xFF);
4643         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
4644                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
4645 }
4646
4647 /**
4648  * Add GRE item to matcher and to the value.
4649  *
4650  * @param[in, out] matcher
4651  *   Flow matcher.
4652  * @param[in, out] key
4653  *   Flow matcher value.
4654  * @param[in] item
4655  *   Flow pattern to translate.
4656  * @param[in] inner
4657  *   Item is inner pattern.
4658  */
4659 static void
4660 flow_dv_translate_item_gre(void *matcher, void *key,
4661                            const struct rte_flow_item *item,
4662                            int inner)
4663 {
4664         const struct rte_flow_item_gre *gre_m = item->mask;
4665         const struct rte_flow_item_gre *gre_v = item->spec;
4666         void *headers_m;
4667         void *headers_v;
4668         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4669         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4670         struct {
4671                 union {
4672                         __extension__
4673                         struct {
4674                                 uint16_t version:3;
4675                                 uint16_t rsvd0:9;
4676                                 uint16_t s_present:1;
4677                                 uint16_t k_present:1;
4678                                 uint16_t rsvd_bit1:1;
4679                                 uint16_t c_present:1;
4680                         };
4681                         uint16_t value;
4682                 };
4683         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
4684
4685         if (inner) {
4686                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4687                                          inner_headers);
4688                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4689         } else {
4690                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4691                                          outer_headers);
4692                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4693         }
4694         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4695         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
4696         if (!gre_v)
4697                 return;
4698         if (!gre_m)
4699                 gre_m = &rte_flow_item_gre_mask;
4700         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
4701                  rte_be_to_cpu_16(gre_m->protocol));
4702         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4703                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
4704         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
4705         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
4706         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
4707                  gre_crks_rsvd0_ver_m.c_present);
4708         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
4709                  gre_crks_rsvd0_ver_v.c_present &
4710                  gre_crks_rsvd0_ver_m.c_present);
4711         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
4712                  gre_crks_rsvd0_ver_m.k_present);
4713         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
4714                  gre_crks_rsvd0_ver_v.k_present &
4715                  gre_crks_rsvd0_ver_m.k_present);
4716         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
4717                  gre_crks_rsvd0_ver_m.s_present);
4718         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
4719                  gre_crks_rsvd0_ver_v.s_present &
4720                  gre_crks_rsvd0_ver_m.s_present);
4721 }
4722
4723 /**
4724  * Add NVGRE item to matcher and to the value.
4725  *
4726  * @param[in, out] matcher
4727  *   Flow matcher.
4728  * @param[in, out] key
4729  *   Flow matcher value.
4730  * @param[in] item
4731  *   Flow pattern to translate.
4732  * @param[in] inner
4733  *   Item is inner pattern.
4734  */
4735 static void
4736 flow_dv_translate_item_nvgre(void *matcher, void *key,
4737                              const struct rte_flow_item *item,
4738                              int inner)
4739 {
4740         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
4741         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
4742         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4743         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4744         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
4745         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
4746         char *gre_key_m;
4747         char *gre_key_v;
4748         int size;
4749         int i;
4750
4751         /* For NVGRE, GRE header fields must be set with defined values. */
4752         const struct rte_flow_item_gre gre_spec = {
4753                 .c_rsvd0_ver = RTE_BE16(0x2000),
4754                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
4755         };
4756         const struct rte_flow_item_gre gre_mask = {
4757                 .c_rsvd0_ver = RTE_BE16(0xB000),
4758                 .protocol = RTE_BE16(UINT16_MAX),
4759         };
4760         const struct rte_flow_item gre_item = {
4761                 .spec = &gre_spec,
4762                 .mask = &gre_mask,
4763                 .last = NULL,
4764         };
4765         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
4766         if (!nvgre_v)
4767                 return;
4768         if (!nvgre_m)
4769                 nvgre_m = &rte_flow_item_nvgre_mask;
4770         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
4771         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
4772         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
4773         memcpy(gre_key_m, tni_flow_id_m, size);
4774         for (i = 0; i < size; ++i)
4775                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
4776 }
4777
4778 /**
4779  * Add VXLAN item to matcher and to the value.
4780  *
4781  * @param[in, out] matcher
4782  *   Flow matcher.
4783  * @param[in, out] key
4784  *   Flow matcher value.
4785  * @param[in] item
4786  *   Flow pattern to translate.
4787  * @param[in] inner
4788  *   Item is inner pattern.
4789  */
4790 static void
4791 flow_dv_translate_item_vxlan(void *matcher, void *key,
4792                              const struct rte_flow_item *item,
4793                              int inner)
4794 {
4795         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
4796         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
4797         void *headers_m;
4798         void *headers_v;
4799         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4800         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4801         char *vni_m;
4802         char *vni_v;
4803         uint16_t dport;
4804         int size;
4805         int i;
4806
4807         if (inner) {
4808                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4809                                          inner_headers);
4810                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4811         } else {
4812                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4813                                          outer_headers);
4814                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4815         }
4816         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
4817                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
4818         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4819                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4820                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4821         }
4822         if (!vxlan_v)
4823                 return;
4824         if (!vxlan_m)
4825                 vxlan_m = &rte_flow_item_vxlan_mask;
4826         size = sizeof(vxlan_m->vni);
4827         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
4828         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
4829         memcpy(vni_m, vxlan_m->vni, size);
4830         for (i = 0; i < size; ++i)
4831                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
4832 }
4833
4834 /**
4835  * Add Geneve item to matcher and to the value.
4836  *
4837  * @param[in, out] matcher
4838  *   Flow matcher.
4839  * @param[in, out] key
4840  *   Flow matcher value.
4841  * @param[in] item
4842  *   Flow pattern to translate.
4843  * @param[in] inner
4844  *   Item is inner pattern.
4845  */
4846
4847 static void
4848 flow_dv_translate_item_geneve(void *matcher, void *key,
4849                               const struct rte_flow_item *item, int inner)
4850 {
4851         const struct rte_flow_item_geneve *geneve_m = item->mask;
4852         const struct rte_flow_item_geneve *geneve_v = item->spec;
4853         void *headers_m;
4854         void *headers_v;
4855         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4856         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4857         uint16_t dport;
4858         uint16_t gbhdr_m;
4859         uint16_t gbhdr_v;
4860         char *vni_m;
4861         char *vni_v;
4862         size_t size, i;
4863
4864         if (inner) {
4865                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4866                                          inner_headers);
4867                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
4868         } else {
4869                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
4870                                          outer_headers);
4871                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4872         }
4873         dport = MLX5_UDP_PORT_GENEVE;
4874         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
4875                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
4876                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
4877         }
4878         if (!geneve_v)
4879                 return;
4880         if (!geneve_m)
4881                 geneve_m = &rte_flow_item_geneve_mask;
4882         size = sizeof(geneve_m->vni);
4883         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
4884         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
4885         memcpy(vni_m, geneve_m->vni, size);
4886         for (i = 0; i < size; ++i)
4887                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
4888         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
4889                  rte_be_to_cpu_16(geneve_m->protocol));
4890         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
4891                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
4892         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
4893         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
4894         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
4895                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4896         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
4897                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
4898         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
4899                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4900         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
4901                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
4902                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
4903 }
4904
4905 /**
4906  * Add MPLS item to matcher and to the value.
4907  *
4908  * @param[in, out] matcher
4909  *   Flow matcher.
4910  * @param[in, out] key
4911  *   Flow matcher value.
4912  * @param[in] item
4913  *   Flow pattern to translate.
4914  * @param[in] prev_layer
4915  *   The protocol layer indicated in previous item.
4916  * @param[in] inner
4917  *   Item is inner pattern.
4918  */
4919 static void
4920 flow_dv_translate_item_mpls(void *matcher, void *key,
4921                             const struct rte_flow_item *item,
4922                             uint64_t prev_layer,
4923                             int inner)
4924 {
4925         const uint32_t *in_mpls_m = item->mask;
4926         const uint32_t *in_mpls_v = item->spec;
4927         uint32_t *out_mpls_m = 0;
4928         uint32_t *out_mpls_v = 0;
4929         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
4930         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
4931         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
4932                                      misc_parameters_2);
4933         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
4934         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
4935         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
4936
4937         switch (prev_layer) {
4938         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4939                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
4940                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
4941                          MLX5_UDP_PORT_MPLS);
4942                 break;
4943         case MLX5_FLOW_LAYER_GRE:
4944                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
4945                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
4946                          RTE_ETHER_TYPE_MPLS);
4947                 break;
4948         default:
4949                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
4950                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
4951                          IPPROTO_MPLS);
4952                 break;
4953         }
4954         if (!in_mpls_v)
4955                 return;
4956         if (!in_mpls_m)
4957                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
4958         switch (prev_layer) {
4959         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
4960                 out_mpls_m =
4961                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4962                                                  outer_first_mpls_over_udp);
4963                 out_mpls_v =
4964                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4965                                                  outer_first_mpls_over_udp);
4966                 break;
4967         case MLX5_FLOW_LAYER_GRE:
4968                 out_mpls_m =
4969                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
4970                                                  outer_first_mpls_over_gre);
4971                 out_mpls_v =
4972                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
4973                                                  outer_first_mpls_over_gre);
4974                 break;
4975         default:
4976                 /* Inner MPLS not over GRE is not supported. */
4977                 if (!inner) {
4978                         out_mpls_m =
4979                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4980                                                          misc2_m,
4981                                                          outer_first_mpls);
4982                         out_mpls_v =
4983                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
4984                                                          misc2_v,
4985                                                          outer_first_mpls);
4986                 }
4987                 break;
4988         }
4989         if (out_mpls_m && out_mpls_v) {
4990                 *out_mpls_m = *in_mpls_m;
4991                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
4992         }
4993 }
4994
4995 /**
4996  * Add metadata register item to matcher
4997  *
4998  * @param[in, out] matcher
4999  *   Flow matcher.
5000  * @param[in, out] key
5001  *   Flow matcher value.
5002  * @param[in] reg_type
5003  *   Type of device metadata register
5004  * @param[in] value
5005  *   Register value
5006  * @param[in] mask
5007  *   Register mask
5008  */
5009 static void
5010 flow_dv_match_meta_reg(void *matcher, void *key,
5011                        enum modify_reg reg_type,
5012                        uint32_t data, uint32_t mask)
5013 {
5014         void *misc2_m =
5015                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5016         void *misc2_v =
5017                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5018
5019         data &= mask;
5020         switch (reg_type) {
5021         case REG_A:
5022                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5023                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5024                 break;
5025         case REG_B:
5026                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5027                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5028                 break;
5029         case REG_C_0:
5030                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, mask);
5031                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, data);
5032                 break;
5033         case REG_C_1:
5034                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
5035                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
5036                 break;
5037         case REG_C_2:
5038                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
5039                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
5040                 break;
5041         case REG_C_3:
5042                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
5043                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
5044                 break;
5045         case REG_C_4:
5046                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
5047                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
5048                 break;
5049         case REG_C_5:
5050                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
5051                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
5052                 break;
5053         case REG_C_6:
5054                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
5055                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
5056                 break;
5057         case REG_C_7:
5058                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
5059                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
5060                 break;
5061         default:
5062                 assert(false);
5063                 break;
5064         }
5065 }
5066
5067 /**
5068  * Add META item to matcher
5069  *
5070  * @param[in, out] matcher
5071  *   Flow matcher.
5072  * @param[in, out] key
5073  *   Flow matcher value.
5074  * @param[in] item
5075  *   Flow pattern to translate.
5076  * @param[in] inner
5077  *   Item is inner pattern.
5078  */
5079 static void
5080 flow_dv_translate_item_meta(void *matcher, void *key,
5081                             const struct rte_flow_item *item)
5082 {
5083         const struct rte_flow_item_meta *meta_m;
5084         const struct rte_flow_item_meta *meta_v;
5085
5086         meta_m = (const void *)item->mask;
5087         if (!meta_m)
5088                 meta_m = &rte_flow_item_meta_mask;
5089         meta_v = (const void *)item->spec;
5090         if (meta_v)
5091                 flow_dv_match_meta_reg(matcher, key, REG_A,
5092                                        rte_cpu_to_be_32(meta_v->data),
5093                                        rte_cpu_to_be_32(meta_m->data));
5094 }
5095
5096 /**
5097  * Add vport metadata Reg C0 item to matcher
5098  *
5099  * @param[in, out] matcher
5100  *   Flow matcher.
5101  * @param[in, out] key
5102  *   Flow matcher value.
5103  * @param[in] reg
5104  *   Flow pattern to translate.
5105  */
5106 static void
5107 flow_dv_translate_item_meta_vport(void *matcher, void *key,
5108                                   uint32_t value, uint32_t mask)
5109 {
5110         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
5111 }
5112
5113 /**
5114  * Add tag item to matcher
5115  *
5116  * @param[in, out] matcher
5117  *   Flow matcher.
5118  * @param[in, out] key
5119  *   Flow matcher value.
5120  * @param[in] item
5121  *   Flow pattern to translate.
5122  */
5123 static void
5124 flow_dv_translate_mlx5_item_tag(void *matcher, void *key,
5125                                 const struct rte_flow_item *item)
5126 {
5127         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
5128         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
5129         enum modify_reg reg = tag_v->id;
5130
5131         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
5132 }
5133
5134 /**
5135  * Add source vport match to the specified matcher.
5136  *
5137  * @param[in, out] matcher
5138  *   Flow matcher.
5139  * @param[in, out] key
5140  *   Flow matcher value.
5141  * @param[in] port
5142  *   Source vport value to match
5143  * @param[in] mask
5144  *   Mask
5145  */
5146 static void
5147 flow_dv_translate_item_source_vport(void *matcher, void *key,
5148                                     int16_t port, uint16_t mask)
5149 {
5150         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5151         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5152
5153         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
5154         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
5155 }
5156
5157 /**
5158  * Translate port-id item to eswitch match on  port-id.
5159  *
5160  * @param[in] dev
5161  *   The devich to configure through.
5162  * @param[in, out] matcher
5163  *   Flow matcher.
5164  * @param[in, out] key
5165  *   Flow matcher value.
5166  * @param[in] item
5167  *   Flow pattern to translate.
5168  *
5169  * @return
5170  *   0 on success, a negative errno value otherwise.
5171  */
5172 static int
5173 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
5174                                void *key, const struct rte_flow_item *item)
5175 {
5176         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
5177         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
5178         struct mlx5_priv *priv;
5179         uint16_t mask, id;
5180
5181         mask = pid_m ? pid_m->id : 0xffff;
5182         id = pid_v ? pid_v->id : dev->data->port_id;
5183         priv = mlx5_port_to_eswitch_info(id, item == NULL);
5184         if (!priv)
5185                 return -rte_errno;
5186         /* Translate to vport field or to metadata, depending on mode. */
5187         if (priv->vport_meta_mask)
5188                 flow_dv_translate_item_meta_vport(matcher, key,
5189                                                   priv->vport_meta_tag,
5190                                                   priv->vport_meta_mask);
5191         else
5192                 flow_dv_translate_item_source_vport(matcher, key,
5193                                                     priv->vport_id, mask);
5194         return 0;
5195 }
5196
5197 /**
5198  * Add ICMP6 item to matcher and to the value.
5199  *
5200  * @param[in, out] matcher
5201  *   Flow matcher.
5202  * @param[in, out] key
5203  *   Flow matcher value.
5204  * @param[in] item
5205  *   Flow pattern to translate.
5206  * @param[in] inner
5207  *   Item is inner pattern.
5208  */
5209 static void
5210 flow_dv_translate_item_icmp6(void *matcher, void *key,
5211                               const struct rte_flow_item *item,
5212                               int inner)
5213 {
5214         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
5215         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
5216         void *headers_m;
5217         void *headers_v;
5218         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5219                                      misc_parameters_3);
5220         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5221         if (inner) {
5222                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5223                                          inner_headers);
5224                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5225         } else {
5226                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5227                                          outer_headers);
5228                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5229         }
5230         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5231         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
5232         if (!icmp6_v)
5233                 return;
5234         if (!icmp6_m)
5235                 icmp6_m = &rte_flow_item_icmp6_mask;
5236         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
5237         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
5238                  icmp6_v->type & icmp6_m->type);
5239         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
5240         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
5241                  icmp6_v->code & icmp6_m->code);
5242 }
5243
5244 /**
5245  * Add ICMP item to matcher and to the value.
5246  *
5247  * @param[in, out] matcher
5248  *   Flow matcher.
5249  * @param[in, out] key
5250  *   Flow matcher value.
5251  * @param[in] item
5252  *   Flow pattern to translate.
5253  * @param[in] inner
5254  *   Item is inner pattern.
5255  */
5256 static void
5257 flow_dv_translate_item_icmp(void *matcher, void *key,
5258                             const struct rte_flow_item *item,
5259                             int inner)
5260 {
5261         const struct rte_flow_item_icmp *icmp_m = item->mask;
5262         const struct rte_flow_item_icmp *icmp_v = item->spec;
5263         void *headers_m;
5264         void *headers_v;
5265         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
5266                                      misc_parameters_3);
5267         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
5268         if (inner) {
5269                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5270                                          inner_headers);
5271                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5272         } else {
5273                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5274                                          outer_headers);
5275                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5276         }
5277         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
5278         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
5279         if (!icmp_v)
5280                 return;
5281         if (!icmp_m)
5282                 icmp_m = &rte_flow_item_icmp_mask;
5283         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
5284                  icmp_m->hdr.icmp_type);
5285         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
5286                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
5287         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
5288                  icmp_m->hdr.icmp_code);
5289         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
5290                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
5291 }
5292
5293 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
5294
5295 #define HEADER_IS_ZERO(match_criteria, headers)                              \
5296         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
5297                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
5298
5299 /**
5300  * Calculate flow matcher enable bitmap.
5301  *
5302  * @param match_criteria
5303  *   Pointer to flow matcher criteria.
5304  *
5305  * @return
5306  *   Bitmap of enabled fields.
5307  */
5308 static uint8_t
5309 flow_dv_matcher_enable(uint32_t *match_criteria)
5310 {
5311         uint8_t match_criteria_enable;
5312
5313         match_criteria_enable =
5314                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
5315                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
5316         match_criteria_enable |=
5317                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
5318                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
5319         match_criteria_enable |=
5320                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
5321                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
5322         match_criteria_enable |=
5323                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
5324                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
5325         match_criteria_enable |=
5326                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
5327                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
5328         return match_criteria_enable;
5329 }
5330
5331
5332 /**
5333  * Get a flow table.
5334  *
5335  * @param dev[in, out]
5336  *   Pointer to rte_eth_dev structure.
5337  * @param[in] table_id
5338  *   Table id to use.
5339  * @param[in] egress
5340  *   Direction of the table.
5341  * @param[in] transfer
5342  *   E-Switch or NIC flow.
5343  * @param[out] error
5344  *   pointer to error structure.
5345  *
5346  * @return
5347  *   Returns tables resource based on the index, NULL in case of failed.
5348  */
5349 static struct mlx5_flow_tbl_resource *
5350 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
5351                          uint32_t table_id, uint8_t egress,
5352                          uint8_t transfer,
5353                          struct rte_flow_error *error)
5354 {
5355         struct mlx5_priv *priv = dev->data->dev_private;
5356         struct mlx5_ibv_shared *sh = priv->sh;
5357         struct mlx5_flow_tbl_resource *tbl;
5358
5359 #ifdef HAVE_MLX5DV_DR
5360         if (transfer) {
5361                 tbl = &sh->fdb_tbl[table_id];
5362                 if (!tbl->obj)
5363                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5364                                 (sh->fdb_domain, table_id);
5365         } else if (egress) {
5366                 tbl = &sh->tx_tbl[table_id];
5367                 if (!tbl->obj)
5368                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5369                                 (sh->tx_domain, table_id);
5370         } else {
5371                 tbl = &sh->rx_tbl[table_id];
5372                 if (!tbl->obj)
5373                         tbl->obj = mlx5_glue->dr_create_flow_tbl
5374                                 (sh->rx_domain, table_id);
5375         }
5376         if (!tbl->obj) {
5377                 rte_flow_error_set(error, ENOMEM,
5378                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5379                                    NULL, "cannot create table");
5380                 return NULL;
5381         }
5382         rte_atomic32_inc(&tbl->refcnt);
5383         return tbl;
5384 #else
5385         (void)error;
5386         (void)tbl;
5387         if (transfer)
5388                 return &sh->fdb_tbl[table_id];
5389         else if (egress)
5390                 return &sh->tx_tbl[table_id];
5391         else
5392                 return &sh->rx_tbl[table_id];
5393 #endif
5394 }
5395
5396 /**
5397  * Release a flow table.
5398  *
5399  * @param[in] tbl
5400  *   Table resource to be released.
5401  *
5402  * @return
5403  *   Returns 0 if table was released, else return 1;
5404  */
5405 static int
5406 flow_dv_tbl_resource_release(struct mlx5_flow_tbl_resource *tbl)
5407 {
5408         if (!tbl)
5409                 return 0;
5410         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
5411                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
5412                 tbl->obj = NULL;
5413                 return 0;
5414         }
5415         return 1;
5416 }
5417
5418 /**
5419  * Register the flow matcher.
5420  *
5421  * @param dev[in, out]
5422  *   Pointer to rte_eth_dev structure.
5423  * @param[in, out] matcher
5424  *   Pointer to flow matcher.
5425  * @parm[in, out] dev_flow
5426  *   Pointer to the dev_flow.
5427  * @param[out] error
5428  *   pointer to error structure.
5429  *
5430  * @return
5431  *   0 on success otherwise -errno and errno is set.
5432  */
5433 static int
5434 flow_dv_matcher_register(struct rte_eth_dev *dev,
5435                          struct mlx5_flow_dv_matcher *matcher,
5436                          struct mlx5_flow *dev_flow,
5437                          struct rte_flow_error *error)
5438 {
5439         struct mlx5_priv *priv = dev->data->dev_private;
5440         struct mlx5_ibv_shared *sh = priv->sh;
5441         struct mlx5_flow_dv_matcher *cache_matcher;
5442         struct mlx5dv_flow_matcher_attr dv_attr = {
5443                 .type = IBV_FLOW_ATTR_NORMAL,
5444                 .match_mask = (void *)&matcher->mask,
5445         };
5446         struct mlx5_flow_tbl_resource *tbl = NULL;
5447
5448         /* Lookup from cache. */
5449         LIST_FOREACH(cache_matcher, &sh->matchers, next) {
5450                 if (matcher->crc == cache_matcher->crc &&
5451                     matcher->priority == cache_matcher->priority &&
5452                     matcher->egress == cache_matcher->egress &&
5453                     matcher->group == cache_matcher->group &&
5454                     matcher->transfer == cache_matcher->transfer &&
5455                     !memcmp((const void *)matcher->mask.buf,
5456                             (const void *)cache_matcher->mask.buf,
5457                             cache_matcher->mask.size)) {
5458                         DRV_LOG(DEBUG,
5459                                 "priority %hd use %s matcher %p: refcnt %d++",
5460                                 cache_matcher->priority,
5461                                 cache_matcher->egress ? "tx" : "rx",
5462                                 (void *)cache_matcher,
5463                                 rte_atomic32_read(&cache_matcher->refcnt));
5464                         rte_atomic32_inc(&cache_matcher->refcnt);
5465                         dev_flow->dv.matcher = cache_matcher;
5466                         return 0;
5467                 }
5468         }
5469         /* Register new matcher. */
5470         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
5471         if (!cache_matcher)
5472                 return rte_flow_error_set(error, ENOMEM,
5473                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5474                                           "cannot allocate matcher memory");
5475         tbl = flow_dv_tbl_resource_get(dev, matcher->group,
5476                                        matcher->egress, matcher->transfer,
5477                                        error);
5478         if (!tbl) {
5479                 rte_free(cache_matcher);
5480                 return rte_flow_error_set(error, ENOMEM,
5481                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5482                                           NULL, "cannot create table");
5483         }
5484         *cache_matcher = *matcher;
5485         dv_attr.match_criteria_enable =
5486                 flow_dv_matcher_enable(cache_matcher->mask.buf);
5487         dv_attr.priority = matcher->priority;
5488         if (matcher->egress)
5489                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
5490         cache_matcher->matcher_object =
5491                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
5492         if (!cache_matcher->matcher_object) {
5493                 rte_free(cache_matcher);
5494 #ifdef HAVE_MLX5DV_DR
5495                 flow_dv_tbl_resource_release(tbl);
5496 #endif
5497                 return rte_flow_error_set(error, ENOMEM,
5498                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5499                                           NULL, "cannot create matcher");
5500         }
5501         rte_atomic32_inc(&cache_matcher->refcnt);
5502         LIST_INSERT_HEAD(&sh->matchers, cache_matcher, next);
5503         dev_flow->dv.matcher = cache_matcher;
5504         DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
5505                 cache_matcher->priority,
5506                 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
5507                 rte_atomic32_read(&cache_matcher->refcnt));
5508         rte_atomic32_inc(&tbl->refcnt);
5509         return 0;
5510 }
5511
5512 /**
5513  * Find existing tag resource or create and register a new one.
5514  *
5515  * @param dev[in, out]
5516  *   Pointer to rte_eth_dev structure.
5517  * @param[in, out] resource
5518  *   Pointer to tag resource.
5519  * @parm[in, out] dev_flow
5520  *   Pointer to the dev_flow.
5521  * @param[out] error
5522  *   pointer to error structure.
5523  *
5524  * @return
5525  *   0 on success otherwise -errno and errno is set.
5526  */
5527 static int
5528 flow_dv_tag_resource_register
5529                         (struct rte_eth_dev *dev,
5530                          struct mlx5_flow_dv_tag_resource *resource,
5531                          struct mlx5_flow *dev_flow,
5532                          struct rte_flow_error *error)
5533 {
5534         struct mlx5_priv *priv = dev->data->dev_private;
5535         struct mlx5_ibv_shared *sh = priv->sh;
5536         struct mlx5_flow_dv_tag_resource *cache_resource;
5537
5538         /* Lookup a matching resource from cache. */
5539         LIST_FOREACH(cache_resource, &sh->tags, next) {
5540                 if (resource->tag == cache_resource->tag) {
5541                         DRV_LOG(DEBUG, "tag resource %p: refcnt %d++",
5542                                 (void *)cache_resource,
5543                                 rte_atomic32_read(&cache_resource->refcnt));
5544                         rte_atomic32_inc(&cache_resource->refcnt);
5545                         dev_flow->dv.tag_resource = cache_resource;
5546                         return 0;
5547                 }
5548         }
5549         /* Register new  resource. */
5550         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
5551         if (!cache_resource)
5552                 return rte_flow_error_set(error, ENOMEM,
5553                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5554                                           "cannot allocate resource memory");
5555         *cache_resource = *resource;
5556         cache_resource->action = mlx5_glue->dv_create_flow_action_tag
5557                 (resource->tag);
5558         if (!cache_resource->action) {
5559                 rte_free(cache_resource);
5560                 return rte_flow_error_set(error, ENOMEM,
5561                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5562                                           NULL, "cannot create action");
5563         }
5564         rte_atomic32_init(&cache_resource->refcnt);
5565         rte_atomic32_inc(&cache_resource->refcnt);
5566         LIST_INSERT_HEAD(&sh->tags, cache_resource, next);
5567         dev_flow->dv.tag_resource = cache_resource;
5568         DRV_LOG(DEBUG, "new tag resource %p: refcnt %d++",
5569                 (void *)cache_resource,
5570                 rte_atomic32_read(&cache_resource->refcnt));
5571         return 0;
5572 }
5573
5574 /**
5575  * Release the tag.
5576  *
5577  * @param dev
5578  *   Pointer to Ethernet device.
5579  * @param flow
5580  *   Pointer to mlx5_flow.
5581  *
5582  * @return
5583  *   1 while a reference on it exists, 0 when freed.
5584  */
5585 static int
5586 flow_dv_tag_release(struct rte_eth_dev *dev,
5587                     struct mlx5_flow_dv_tag_resource *tag)
5588 {
5589         assert(tag);
5590         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
5591                 dev->data->port_id, (void *)tag,
5592                 rte_atomic32_read(&tag->refcnt));
5593         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
5594                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
5595                 LIST_REMOVE(tag, next);
5596                 DRV_LOG(DEBUG, "port %u tag %p: removed",
5597                         dev->data->port_id, (void *)tag);
5598                 rte_free(tag);
5599                 return 0;
5600         }
5601         return 1;
5602 }
5603
5604 /**
5605  * Translate port ID action to vport.
5606  *
5607  * @param[in] dev
5608  *   Pointer to rte_eth_dev structure.
5609  * @param[in] action
5610  *   Pointer to the port ID action.
5611  * @param[out] dst_port_id
5612  *   The target port ID.
5613  * @param[out] error
5614  *   Pointer to the error structure.
5615  *
5616  * @return
5617  *   0 on success, a negative errno value otherwise and rte_errno is set.
5618  */
5619 static int
5620 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
5621                                  const struct rte_flow_action *action,
5622                                  uint32_t *dst_port_id,
5623                                  struct rte_flow_error *error)
5624 {
5625         uint32_t port;
5626         struct mlx5_priv *priv;
5627         const struct rte_flow_action_port_id *conf =
5628                         (const struct rte_flow_action_port_id *)action->conf;
5629
5630         port = conf->original ? dev->data->port_id : conf->id;
5631         priv = mlx5_port_to_eswitch_info(port, false);
5632         if (!priv)
5633                 return rte_flow_error_set(error, -rte_errno,
5634                                           RTE_FLOW_ERROR_TYPE_ACTION,
5635                                           NULL,
5636                                           "No eswitch info was found for port");
5637         if (priv->vport_meta_mask)
5638                 *dst_port_id = priv->vport_meta_tag;
5639         else
5640                 *dst_port_id = priv->vport_id;
5641         return 0;
5642 }
5643
5644 /**
5645  * Add Tx queue matcher
5646  *
5647  * @param[in] dev
5648  *   Pointer to the dev struct.
5649  * @param[in, out] matcher
5650  *   Flow matcher.
5651  * @param[in, out] key
5652  *   Flow matcher value.
5653  * @param[in] item
5654  *   Flow pattern to translate.
5655  * @param[in] inner
5656  *   Item is inner pattern.
5657  */
5658 static void
5659 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
5660                                 void *matcher, void *key,
5661                                 const struct rte_flow_item *item)
5662 {
5663         const struct mlx5_rte_flow_item_tx_queue *queue_m;
5664         const struct mlx5_rte_flow_item_tx_queue *queue_v;
5665         void *misc_m =
5666                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5667         void *misc_v =
5668                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5669         struct mlx5_txq_ctrl *txq;
5670         uint32_t queue;
5671
5672
5673         queue_m = (const void *)item->mask;
5674         if (!queue_m)
5675                 return;
5676         queue_v = (const void *)item->spec;
5677         if (!queue_v)
5678                 return;
5679         txq = mlx5_txq_get(dev, queue_v->queue);
5680         if (!txq)
5681                 return;
5682         queue = txq->obj->sq->id;
5683         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
5684         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
5685                  queue & queue_m->queue);
5686         mlx5_txq_release(dev, queue_v->queue);
5687 }
5688
5689 /**
5690  * Fill the flow with DV spec, lock free
5691  * (mutex should be acquired by caller).
5692  *
5693  * @param[in] dev
5694  *   Pointer to rte_eth_dev structure.
5695  * @param[in, out] dev_flow
5696  *   Pointer to the sub flow.
5697  * @param[in] attr
5698  *   Pointer to the flow attributes.
5699  * @param[in] items
5700  *   Pointer to the list of items.
5701  * @param[in] actions
5702  *   Pointer to the list of actions.
5703  * @param[out] error
5704  *   Pointer to the error structure.
5705  *
5706  * @return
5707  *   0 on success, a negative errno value otherwise and rte_errno is set.
5708  */
5709 static int
5710 __flow_dv_translate(struct rte_eth_dev *dev,
5711                     struct mlx5_flow *dev_flow,
5712                     const struct rte_flow_attr *attr,
5713                     const struct rte_flow_item items[],
5714                     const struct rte_flow_action actions[],
5715                     struct rte_flow_error *error)
5716 {
5717         struct mlx5_priv *priv = dev->data->dev_private;
5718         struct rte_flow *flow = dev_flow->flow;
5719         uint64_t item_flags = 0;
5720         uint64_t last_item = 0;
5721         uint64_t action_flags = 0;
5722         uint64_t priority = attr->priority;
5723         struct mlx5_flow_dv_matcher matcher = {
5724                 .mask = {
5725                         .size = sizeof(matcher.mask.buf),
5726                 },
5727         };
5728         int actions_n = 0;
5729         bool actions_end = false;
5730         struct mlx5_flow_dv_modify_hdr_resource mhdr_res = {
5731                 .ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
5732                                           MLX5DV_FLOW_TABLE_TYPE_NIC_RX
5733         };
5734         union flow_dv_attr flow_attr = { .attr = 0 };
5735         struct mlx5_flow_dv_tag_resource tag_resource;
5736         uint32_t modify_action_position = UINT32_MAX;
5737         void *match_mask = matcher.mask.buf;
5738         void *match_value = dev_flow->dv.value.buf;
5739         uint8_t next_protocol = 0xff;
5740         struct rte_vlan_hdr vlan = { 0 };
5741         uint32_t table;
5742         int ret = 0;
5743
5744         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
5745                                        &table, error);
5746         if (ret)
5747                 return ret;
5748         dev_flow->group = table;
5749         if (attr->transfer)
5750                 mhdr_res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
5751         if (priority == MLX5_FLOW_PRIO_RSVD)
5752                 priority = priv->config.flow_prio - 1;
5753         for (; !actions_end ; actions++) {
5754                 const struct rte_flow_action_queue *queue;
5755                 const struct rte_flow_action_rss *rss;
5756                 const struct rte_flow_action *action = actions;
5757                 const struct rte_flow_action_count *count = action->conf;
5758                 const uint8_t *rss_key;
5759                 const struct rte_flow_action_jump *jump_data;
5760                 struct mlx5_flow_dv_jump_tbl_resource jump_tbl_resource;
5761                 struct mlx5_flow_tbl_resource *tbl;
5762                 uint32_t port_id = 0;
5763                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
5764                 int action_type = actions->type;
5765                 const struct rte_flow_action *found_action = NULL;
5766
5767                 switch (action_type) {
5768                 case RTE_FLOW_ACTION_TYPE_VOID:
5769                         break;
5770                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5771                         if (flow_dv_translate_action_port_id(dev, action,
5772                                                              &port_id, error))
5773                                 return -rte_errno;
5774                         port_id_resource.port_id = port_id;
5775                         if (flow_dv_port_id_action_resource_register
5776                             (dev, &port_id_resource, dev_flow, error))
5777                                 return -rte_errno;
5778                         dev_flow->dv.actions[actions_n++] =
5779                                 dev_flow->dv.port_id_action->action;
5780                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5781                         break;
5782                 case RTE_FLOW_ACTION_TYPE_FLAG:
5783                         tag_resource.tag =
5784                                 mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
5785                         if (!dev_flow->dv.tag_resource)
5786                                 if (flow_dv_tag_resource_register
5787                                     (dev, &tag_resource, dev_flow, error))
5788                                         return errno;
5789                         dev_flow->dv.actions[actions_n++] =
5790                                 dev_flow->dv.tag_resource->action;
5791                         action_flags |= MLX5_FLOW_ACTION_FLAG;
5792                         break;
5793                 case RTE_FLOW_ACTION_TYPE_MARK:
5794                         tag_resource.tag = mlx5_flow_mark_set
5795                               (((const struct rte_flow_action_mark *)
5796                                (actions->conf))->id);
5797                         if (!dev_flow->dv.tag_resource)
5798                                 if (flow_dv_tag_resource_register
5799                                     (dev, &tag_resource, dev_flow, error))
5800                                         return errno;
5801                         dev_flow->dv.actions[actions_n++] =
5802                                 dev_flow->dv.tag_resource->action;
5803                         action_flags |= MLX5_FLOW_ACTION_MARK;
5804                         break;
5805                 case RTE_FLOW_ACTION_TYPE_DROP:
5806                         action_flags |= MLX5_FLOW_ACTION_DROP;
5807                         break;
5808                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5809                         assert(flow->rss.queue);
5810                         queue = actions->conf;
5811                         flow->rss.queue_num = 1;
5812                         (*flow->rss.queue)[0] = queue->index;
5813                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5814                         break;
5815                 case RTE_FLOW_ACTION_TYPE_RSS:
5816                         assert(flow->rss.queue);
5817                         rss = actions->conf;
5818                         if (flow->rss.queue)
5819                                 memcpy((*flow->rss.queue), rss->queue,
5820                                        rss->queue_num * sizeof(uint16_t));
5821                         flow->rss.queue_num = rss->queue_num;
5822                         /* NULL RSS key indicates default RSS key. */
5823                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
5824                         memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
5825                         /*
5826                          * rss->level and rss.types should be set in advance
5827                          * when expanding items for RSS.
5828                          */
5829                         action_flags |= MLX5_FLOW_ACTION_RSS;
5830                         break;
5831                 case RTE_FLOW_ACTION_TYPE_COUNT:
5832                         if (!priv->config.devx) {
5833                                 rte_errno = ENOTSUP;
5834                                 goto cnt_err;
5835                         }
5836                         flow->counter = flow_dv_counter_alloc(dev,
5837                                                               count->shared,
5838                                                               count->id,
5839                                                               dev_flow->group);
5840                         if (flow->counter == NULL)
5841                                 goto cnt_err;
5842                         dev_flow->dv.actions[actions_n++] =
5843                                 flow->counter->action;
5844                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5845                         break;
5846 cnt_err:
5847                         if (rte_errno == ENOTSUP)
5848                                 return rte_flow_error_set
5849                                               (error, ENOTSUP,
5850                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5851                                                NULL,
5852                                                "count action not supported");
5853                         else
5854                                 return rte_flow_error_set
5855                                                 (error, rte_errno,
5856                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5857                                                  action,
5858                                                  "cannot create counter"
5859                                                   " object.");
5860                         break;
5861                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5862                         dev_flow->dv.actions[actions_n++] =
5863                                                 priv->sh->pop_vlan_action;
5864                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5865                         break;
5866                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5867                         flow_dev_get_vlan_info_from_items(items, &vlan);
5868                         vlan.eth_proto = rte_be_to_cpu_16
5869                              ((((const struct rte_flow_action_of_push_vlan *)
5870                                                    actions->conf)->ethertype));
5871                         found_action = mlx5_flow_find_action
5872                                         (actions + 1,
5873                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
5874                         if (found_action)
5875                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5876                         found_action = mlx5_flow_find_action
5877                                         (actions + 1,
5878                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
5879                         if (found_action)
5880                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
5881                         if (flow_dv_create_action_push_vlan
5882                                             (dev, attr, &vlan, dev_flow, error))
5883                                 return -rte_errno;
5884                         dev_flow->dv.actions[actions_n++] =
5885                                            dev_flow->dv.push_vlan_res->action;
5886                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5887                         break;
5888                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5889                         /* of_vlan_push action handled this action */
5890                         assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
5891                         break;
5892                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5893                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5894                                 break;
5895                         flow_dev_get_vlan_info_from_items(items, &vlan);
5896                         mlx5_update_vlan_vid_pcp(actions, &vlan);
5897                         /* If no VLAN push - this is a modify header action */
5898                         if (flow_dv_convert_action_modify_vlan_vid
5899                                                 (&mhdr_res, actions, error))
5900                                 return -rte_errno;
5901                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5902                         break;
5903                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5904                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5905                         if (flow_dv_create_action_l2_encap(dev, actions,
5906                                                            dev_flow,
5907                                                            attr->transfer,
5908                                                            error))
5909                                 return -rte_errno;
5910                         dev_flow->dv.actions[actions_n++] =
5911                                 dev_flow->dv.encap_decap->verbs_action;
5912                         action_flags |= actions->type ==
5913                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
5914                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
5915                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
5916                         break;
5917                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5918                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5919                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
5920                                                            attr->transfer,
5921                                                            error))
5922                                 return -rte_errno;
5923                         dev_flow->dv.actions[actions_n++] =
5924                                 dev_flow->dv.encap_decap->verbs_action;
5925                         action_flags |= actions->type ==
5926                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
5927                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
5928                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
5929                         break;
5930                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5931                         /* Handle encap with preceding decap. */
5932                         if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
5933                                 if (flow_dv_create_action_raw_encap
5934                                         (dev, actions, dev_flow, attr, error))
5935                                         return -rte_errno;
5936                                 dev_flow->dv.actions[actions_n++] =
5937                                         dev_flow->dv.encap_decap->verbs_action;
5938                         } else {
5939                                 /* Handle encap without preceding decap. */
5940                                 if (flow_dv_create_action_l2_encap
5941                                     (dev, actions, dev_flow, attr->transfer,
5942                                      error))
5943                                         return -rte_errno;
5944                                 dev_flow->dv.actions[actions_n++] =
5945                                         dev_flow->dv.encap_decap->verbs_action;
5946                         }
5947                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
5948                         break;
5949                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5950                         /* Check if this decap is followed by encap. */
5951                         for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
5952                                action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
5953                                action++) {
5954                         }
5955                         /* Handle decap only if it isn't followed by encap. */
5956                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5957                                 if (flow_dv_create_action_l2_decap
5958                                     (dev, dev_flow, attr->transfer, error))
5959                                         return -rte_errno;
5960                                 dev_flow->dv.actions[actions_n++] =
5961                                         dev_flow->dv.encap_decap->verbs_action;
5962                         }
5963                         /* If decap is followed by encap, handle it at encap. */
5964                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
5965                         break;
5966                 case RTE_FLOW_ACTION_TYPE_JUMP:
5967                         jump_data = action->conf;
5968                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
5969                                                        jump_data->group, &table,
5970                                                        error);
5971                         if (ret)
5972                                 return ret;
5973                         tbl = flow_dv_tbl_resource_get(dev, table,
5974                                                        attr->egress,
5975                                                        attr->transfer, error);
5976                         if (!tbl)
5977                                 return rte_flow_error_set
5978                                                 (error, errno,
5979                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5980                                                  NULL,
5981                                                  "cannot create jump action.");
5982                         jump_tbl_resource.tbl = tbl;
5983                         if (flow_dv_jump_tbl_resource_register
5984                             (dev, &jump_tbl_resource, dev_flow, error)) {
5985                                 flow_dv_tbl_resource_release(tbl);
5986                                 return rte_flow_error_set
5987                                                 (error, errno,
5988                                                  RTE_FLOW_ERROR_TYPE_ACTION,
5989                                                  NULL,
5990                                                  "cannot create jump action.");
5991                         }
5992                         dev_flow->dv.actions[actions_n++] =
5993                                 dev_flow->dv.jump->action;
5994                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5995                         break;
5996                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5997                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5998                         if (flow_dv_convert_action_modify_mac
5999                                         (&mhdr_res, actions, error))
6000                                 return -rte_errno;
6001                         action_flags |= actions->type ==
6002                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6003                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
6004                                         MLX5_FLOW_ACTION_SET_MAC_DST;
6005                         break;
6006                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6007                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6008                         if (flow_dv_convert_action_modify_ipv4
6009                                         (&mhdr_res, actions, error))
6010                                 return -rte_errno;
6011                         action_flags |= actions->type ==
6012                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6013                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
6014                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
6015                         break;
6016                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6017                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6018                         if (flow_dv_convert_action_modify_ipv6
6019                                         (&mhdr_res, actions, error))
6020                                 return -rte_errno;
6021                         action_flags |= actions->type ==
6022                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6023                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
6024                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
6025                         break;
6026                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6027                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6028                         if (flow_dv_convert_action_modify_tp
6029                                         (&mhdr_res, actions, items,
6030                                          &flow_attr, error))
6031                                 return -rte_errno;
6032                         action_flags |= actions->type ==
6033                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6034                                         MLX5_FLOW_ACTION_SET_TP_SRC :
6035                                         MLX5_FLOW_ACTION_SET_TP_DST;
6036                         break;
6037                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6038                         if (flow_dv_convert_action_modify_dec_ttl
6039                                         (&mhdr_res, items, &flow_attr, error))
6040                                 return -rte_errno;
6041                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
6042                         break;
6043                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6044                         if (flow_dv_convert_action_modify_ttl
6045                                         (&mhdr_res, actions, items,
6046                                          &flow_attr, error))
6047                                 return -rte_errno;
6048                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
6049                         break;
6050                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6051                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6052                         if (flow_dv_convert_action_modify_tcp_seq
6053                                         (&mhdr_res, actions, error))
6054                                 return -rte_errno;
6055                         action_flags |= actions->type ==
6056                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6057                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
6058                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6059                         break;
6060
6061                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6062                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6063                         if (flow_dv_convert_action_modify_tcp_ack
6064                                         (&mhdr_res, actions, error))
6065                                 return -rte_errno;
6066                         action_flags |= actions->type ==
6067                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6068                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
6069                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
6070                         break;
6071                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6072                         if (flow_dv_convert_action_set_reg
6073                                         (&mhdr_res, actions, error))
6074                                 return -rte_errno;
6075                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6076                         break;
6077                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6078                         if (flow_dv_convert_action_copy_mreg
6079                                         (dev, &mhdr_res, actions, error))
6080                                 return -rte_errno;
6081                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6082                         break;
6083                 case RTE_FLOW_ACTION_TYPE_END:
6084                         actions_end = true;
6085                         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) {
6086                                 /* create modify action if needed. */
6087                                 if (flow_dv_modify_hdr_resource_register
6088                                         (dev, &mhdr_res, dev_flow, error))
6089                                         return -rte_errno;
6090                                 dev_flow->dv.actions[modify_action_position] =
6091                                         dev_flow->dv.modify_hdr->verbs_action;
6092                         }
6093                         break;
6094                 default:
6095                         break;
6096                 }
6097                 if ((action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS) &&
6098                     modify_action_position == UINT32_MAX)
6099                         modify_action_position = actions_n++;
6100         }
6101         dev_flow->dv.actions_n = actions_n;
6102         dev_flow->actions = action_flags;
6103         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6104                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6105                 int item_type = items->type;
6106
6107                 switch (item_type) {
6108                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6109                         flow_dv_translate_item_port_id(dev, match_mask,
6110                                                        match_value, items);
6111                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6112                         break;
6113                 case RTE_FLOW_ITEM_TYPE_ETH:
6114                         flow_dv_translate_item_eth(match_mask, match_value,
6115                                                    items, tunnel);
6116                         matcher.priority = MLX5_PRIORITY_MAP_L2;
6117                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6118                                              MLX5_FLOW_LAYER_OUTER_L2;
6119                         break;
6120                 case RTE_FLOW_ITEM_TYPE_VLAN:
6121                         flow_dv_translate_item_vlan(dev_flow,
6122                                                     match_mask, match_value,
6123                                                     items, tunnel);
6124                         matcher.priority = MLX5_PRIORITY_MAP_L2;
6125                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
6126                                               MLX5_FLOW_LAYER_INNER_VLAN) :
6127                                              (MLX5_FLOW_LAYER_OUTER_L2 |
6128                                               MLX5_FLOW_LAYER_OUTER_VLAN);
6129                         break;
6130                 case RTE_FLOW_ITEM_TYPE_IPV4:
6131                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6132                                                   &item_flags, &tunnel);
6133                         flow_dv_translate_item_ipv4(match_mask, match_value,
6134                                                     items, tunnel,
6135                                                     dev_flow->group);
6136                         matcher.priority = MLX5_PRIORITY_MAP_L3;
6137                         dev_flow->hash_fields |=
6138                                 mlx5_flow_hashfields_adjust
6139                                         (dev_flow, tunnel,
6140                                          MLX5_IPV4_LAYER_TYPES,
6141                                          MLX5_IPV4_IBV_RX_HASH);
6142                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6143                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6144                         if (items->mask != NULL &&
6145                             ((const struct rte_flow_item_ipv4 *)
6146                              items->mask)->hdr.next_proto_id) {
6147                                 next_protocol =
6148                                         ((const struct rte_flow_item_ipv4 *)
6149                                          (items->spec))->hdr.next_proto_id;
6150                                 next_protocol &=
6151                                         ((const struct rte_flow_item_ipv4 *)
6152                                          (items->mask))->hdr.next_proto_id;
6153                         } else {
6154                                 /* Reset for inner layer. */
6155                                 next_protocol = 0xff;
6156                         }
6157                         break;
6158                 case RTE_FLOW_ITEM_TYPE_IPV6:
6159                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6160                                                   &item_flags, &tunnel);
6161                         flow_dv_translate_item_ipv6(match_mask, match_value,
6162                                                     items, tunnel,
6163                                                     dev_flow->group);
6164                         matcher.priority = MLX5_PRIORITY_MAP_L3;
6165                         dev_flow->hash_fields |=
6166                                 mlx5_flow_hashfields_adjust
6167                                         (dev_flow, tunnel,
6168                                          MLX5_IPV6_LAYER_TYPES,
6169                                          MLX5_IPV6_IBV_RX_HASH);
6170                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6171                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6172                         if (items->mask != NULL &&
6173                             ((const struct rte_flow_item_ipv6 *)
6174                              items->mask)->hdr.proto) {
6175                                 next_protocol =
6176                                         ((const struct rte_flow_item_ipv6 *)
6177                                          items->spec)->hdr.proto;
6178                                 next_protocol &=
6179                                         ((const struct rte_flow_item_ipv6 *)
6180                                          items->mask)->hdr.proto;
6181                         } else {
6182                                 /* Reset for inner layer. */
6183                                 next_protocol = 0xff;
6184                         }
6185                         break;
6186                 case RTE_FLOW_ITEM_TYPE_TCP:
6187                         flow_dv_translate_item_tcp(match_mask, match_value,
6188                                                    items, tunnel);
6189                         matcher.priority = MLX5_PRIORITY_MAP_L4;
6190                         dev_flow->hash_fields |=
6191                                 mlx5_flow_hashfields_adjust
6192                                         (dev_flow, tunnel, ETH_RSS_TCP,
6193                                          IBV_RX_HASH_SRC_PORT_TCP |
6194                                          IBV_RX_HASH_DST_PORT_TCP);
6195                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6196                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6197                         break;
6198                 case RTE_FLOW_ITEM_TYPE_UDP:
6199                         flow_dv_translate_item_udp(match_mask, match_value,
6200                                                    items, tunnel);
6201                         matcher.priority = MLX5_PRIORITY_MAP_L4;
6202                         dev_flow->hash_fields |=
6203                                 mlx5_flow_hashfields_adjust
6204                                         (dev_flow, tunnel, ETH_RSS_UDP,
6205                                          IBV_RX_HASH_SRC_PORT_UDP |
6206                                          IBV_RX_HASH_DST_PORT_UDP);
6207                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6208                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6209                         break;
6210                 case RTE_FLOW_ITEM_TYPE_GRE:
6211                         flow_dv_translate_item_gre(match_mask, match_value,
6212                                                    items, tunnel);
6213                         last_item = MLX5_FLOW_LAYER_GRE;
6214                         break;
6215                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6216                         flow_dv_translate_item_gre_key(match_mask,
6217                                                        match_value, items);
6218                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6219                         break;
6220                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6221                         flow_dv_translate_item_nvgre(match_mask, match_value,
6222                                                      items, tunnel);
6223                         last_item = MLX5_FLOW_LAYER_GRE;
6224                         break;
6225                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6226                         flow_dv_translate_item_vxlan(match_mask, match_value,
6227                                                      items, tunnel);
6228                         last_item = MLX5_FLOW_LAYER_VXLAN;
6229                         break;
6230                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6231                         flow_dv_translate_item_vxlan(match_mask, match_value,
6232                                                      items, tunnel);
6233                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6234                         break;
6235                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6236                         flow_dv_translate_item_geneve(match_mask, match_value,
6237                                                       items, tunnel);
6238                         last_item = MLX5_FLOW_LAYER_GENEVE;
6239                         break;
6240                 case RTE_FLOW_ITEM_TYPE_MPLS:
6241                         flow_dv_translate_item_mpls(match_mask, match_value,
6242                                                     items, last_item, tunnel);
6243                         last_item = MLX5_FLOW_LAYER_MPLS;
6244                         break;
6245                 case RTE_FLOW_ITEM_TYPE_META:
6246                         flow_dv_translate_item_meta(match_mask, match_value,
6247                                                     items);
6248                         last_item = MLX5_FLOW_ITEM_METADATA;
6249                         break;
6250                 case RTE_FLOW_ITEM_TYPE_ICMP:
6251                         flow_dv_translate_item_icmp(match_mask, match_value,
6252                                                     items, tunnel);
6253                         last_item = MLX5_FLOW_LAYER_ICMP;
6254                         break;
6255                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6256                         flow_dv_translate_item_icmp6(match_mask, match_value,
6257                                                       items, tunnel);
6258                         last_item = MLX5_FLOW_LAYER_ICMP6;
6259                         break;
6260                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6261                         flow_dv_translate_mlx5_item_tag(match_mask,
6262                                                         match_value, items);
6263                         last_item = MLX5_FLOW_ITEM_TAG;
6264                         break;
6265                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6266                         flow_dv_translate_item_tx_queue(dev, match_mask,
6267                                                         match_value,
6268                                                         items);
6269                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
6270                         break;
6271                 default:
6272                         break;
6273                 }
6274                 item_flags |= last_item;
6275         }
6276         /*
6277          * In case of ingress traffic when E-Switch mode is enabled,
6278          * we have two cases where we need to set the source port manually.
6279          * The first one, is in case of Nic steering rule, and the second is
6280          * E-Switch rule where no port_id item was found. In both cases
6281          * the source port is set according the current port in use.
6282          */
6283         if ((attr->ingress && !(item_flags & MLX5_FLOW_ITEM_PORT_ID)) &&
6284             (priv->representor || priv->master)) {
6285                 if (flow_dv_translate_item_port_id(dev, match_mask,
6286                                                    match_value, NULL))
6287                         return -rte_errno;
6288         }
6289         assert(!flow_dv_check_valid_spec(matcher.mask.buf,
6290                                          dev_flow->dv.value.buf));
6291         dev_flow->layers = item_flags;
6292         /* Register matcher. */
6293         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
6294                                     matcher.mask.size);
6295         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
6296                                                      matcher.priority);
6297         matcher.egress = attr->egress;
6298         matcher.group = dev_flow->group;
6299         matcher.transfer = attr->transfer;
6300         if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
6301                 return -rte_errno;
6302         return 0;
6303 }
6304
6305 /**
6306  * Apply the flow to the NIC, lock free,
6307  * (mutex should be acquired by caller).
6308  *
6309  * @param[in] dev
6310  *   Pointer to the Ethernet device structure.
6311  * @param[in, out] flow
6312  *   Pointer to flow structure.
6313  * @param[out] error
6314  *   Pointer to error structure.
6315  *
6316  * @return
6317  *   0 on success, a negative errno value otherwise and rte_errno is set.
6318  */
6319 static int
6320 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
6321                 struct rte_flow_error *error)
6322 {
6323         struct mlx5_flow_dv *dv;
6324         struct mlx5_flow *dev_flow;
6325         struct mlx5_priv *priv = dev->data->dev_private;
6326         int n;
6327         int err;
6328
6329         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6330                 dv = &dev_flow->dv;
6331                 n = dv->actions_n;
6332                 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
6333                         if (dev_flow->transfer) {
6334                                 dv->actions[n++] = priv->sh->esw_drop_action;
6335                         } else {
6336                                 dv->hrxq = mlx5_hrxq_drop_new(dev);
6337                                 if (!dv->hrxq) {
6338                                         rte_flow_error_set
6339                                                 (error, errno,
6340                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6341                                                  NULL,
6342                                                  "cannot get drop hash queue");
6343                                         goto error;
6344                                 }
6345                                 dv->actions[n++] = dv->hrxq->action;
6346                         }
6347                 } else if (dev_flow->actions &
6348                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
6349                         struct mlx5_hrxq *hrxq;
6350
6351                         assert(flow->rss.queue);
6352                         hrxq = mlx5_hrxq_get(dev, flow->rss.key,
6353                                              MLX5_RSS_HASH_KEY_LEN,
6354                                              dev_flow->hash_fields,
6355                                              (*flow->rss.queue),
6356                                              flow->rss.queue_num);
6357                         if (!hrxq) {
6358                                 hrxq = mlx5_hrxq_new
6359                                         (dev, flow->rss.key,
6360                                          MLX5_RSS_HASH_KEY_LEN,
6361                                          dev_flow->hash_fields,
6362                                          (*flow->rss.queue),
6363                                          flow->rss.queue_num,
6364                                          !!(dev_flow->layers &
6365                                             MLX5_FLOW_LAYER_TUNNEL));
6366                         }
6367                         if (!hrxq) {
6368                                 rte_flow_error_set
6369                                         (error, rte_errno,
6370                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6371                                          "cannot get hash queue");
6372                                 goto error;
6373                         }
6374                         dv->hrxq = hrxq;
6375                         dv->actions[n++] = dv->hrxq->action;
6376                 }
6377                 dv->flow =
6378                         mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
6379                                                   (void *)&dv->value, n,
6380                                                   dv->actions);
6381                 if (!dv->flow) {
6382                         rte_flow_error_set(error, errno,
6383                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6384                                            NULL,
6385                                            "hardware refuses to create flow");
6386                         goto error;
6387                 }
6388                 if (priv->vmwa_context &&
6389                     dev_flow->dv.vf_vlan.tag &&
6390                     !dev_flow->dv.vf_vlan.created) {
6391                         /*
6392                          * The rule contains the VLAN pattern.
6393                          * For VF we are going to create VLAN
6394                          * interface to make hypervisor set correct
6395                          * e-Switch vport context.
6396                          */
6397                         mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
6398                 }
6399         }
6400         return 0;
6401 error:
6402         err = rte_errno; /* Save rte_errno before cleanup. */
6403         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6404                 struct mlx5_flow_dv *dv = &dev_flow->dv;
6405                 if (dv->hrxq) {
6406                         if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6407                                 mlx5_hrxq_drop_release(dev);
6408                         else
6409                                 mlx5_hrxq_release(dev, dv->hrxq);
6410                         dv->hrxq = NULL;
6411                 }
6412                 if (dev_flow->dv.vf_vlan.tag &&
6413                     dev_flow->dv.vf_vlan.created)
6414                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6415         }
6416         rte_errno = err; /* Restore rte_errno. */
6417         return -rte_errno;
6418 }
6419
6420 /**
6421  * Release the flow matcher.
6422  *
6423  * @param dev
6424  *   Pointer to Ethernet device.
6425  * @param flow
6426  *   Pointer to mlx5_flow.
6427  *
6428  * @return
6429  *   1 while a reference on it exists, 0 when freed.
6430  */
6431 static int
6432 flow_dv_matcher_release(struct rte_eth_dev *dev,
6433                         struct mlx5_flow *flow)
6434 {
6435         struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
6436         struct mlx5_priv *priv = dev->data->dev_private;
6437         struct mlx5_ibv_shared *sh = priv->sh;
6438         struct mlx5_flow_tbl_resource *tbl;
6439
6440         assert(matcher->matcher_object);
6441         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
6442                 dev->data->port_id, (void *)matcher,
6443                 rte_atomic32_read(&matcher->refcnt));
6444         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
6445                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
6446                            (matcher->matcher_object));
6447                 LIST_REMOVE(matcher, next);
6448                 if (matcher->egress)
6449                         tbl = &sh->tx_tbl[matcher->group];
6450                 else
6451                         tbl = &sh->rx_tbl[matcher->group];
6452                 flow_dv_tbl_resource_release(tbl);
6453                 rte_free(matcher);
6454                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
6455                         dev->data->port_id, (void *)matcher);
6456                 return 0;
6457         }
6458         return 1;
6459 }
6460
6461 /**
6462  * Release an encap/decap resource.
6463  *
6464  * @param flow
6465  *   Pointer to mlx5_flow.
6466  *
6467  * @return
6468  *   1 while a reference on it exists, 0 when freed.
6469  */
6470 static int
6471 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
6472 {
6473         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
6474                                                 flow->dv.encap_decap;
6475
6476         assert(cache_resource->verbs_action);
6477         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
6478                 (void *)cache_resource,
6479                 rte_atomic32_read(&cache_resource->refcnt));
6480         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6481                 claim_zero(mlx5_glue->destroy_flow_action
6482                                 (cache_resource->verbs_action));
6483                 LIST_REMOVE(cache_resource, next);
6484                 rte_free(cache_resource);
6485                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
6486                         (void *)cache_resource);
6487                 return 0;
6488         }
6489         return 1;
6490 }
6491
6492 /**
6493  * Release an jump to table action resource.
6494  *
6495  * @param flow
6496  *   Pointer to mlx5_flow.
6497  *
6498  * @return
6499  *   1 while a reference on it exists, 0 when freed.
6500  */
6501 static int
6502 flow_dv_jump_tbl_resource_release(struct mlx5_flow *flow)
6503 {
6504         struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
6505                                                 flow->dv.jump;
6506
6507         assert(cache_resource->action);
6508         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
6509                 (void *)cache_resource,
6510                 rte_atomic32_read(&cache_resource->refcnt));
6511         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6512                 claim_zero(mlx5_glue->destroy_flow_action
6513                                 (cache_resource->action));
6514                 LIST_REMOVE(cache_resource, next);
6515                 flow_dv_tbl_resource_release(cache_resource->tbl);
6516                 rte_free(cache_resource);
6517                 DRV_LOG(DEBUG, "jump table resource %p: removed",
6518                         (void *)cache_resource);
6519                 return 0;
6520         }
6521         return 1;
6522 }
6523
6524 /**
6525  * Release a modify-header resource.
6526  *
6527  * @param flow
6528  *   Pointer to mlx5_flow.
6529  *
6530  * @return
6531  *   1 while a reference on it exists, 0 when freed.
6532  */
6533 static int
6534 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
6535 {
6536         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
6537                                                 flow->dv.modify_hdr;
6538
6539         assert(cache_resource->verbs_action);
6540         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
6541                 (void *)cache_resource,
6542                 rte_atomic32_read(&cache_resource->refcnt));
6543         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6544                 claim_zero(mlx5_glue->destroy_flow_action
6545                                 (cache_resource->verbs_action));
6546                 LIST_REMOVE(cache_resource, next);
6547                 rte_free(cache_resource);
6548                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
6549                         (void *)cache_resource);
6550                 return 0;
6551         }
6552         return 1;
6553 }
6554
6555 /**
6556  * Release port ID action resource.
6557  *
6558  * @param flow
6559  *   Pointer to mlx5_flow.
6560  *
6561  * @return
6562  *   1 while a reference on it exists, 0 when freed.
6563  */
6564 static int
6565 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
6566 {
6567         struct mlx5_flow_dv_port_id_action_resource *cache_resource =
6568                 flow->dv.port_id_action;
6569
6570         assert(cache_resource->action);
6571         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
6572                 (void *)cache_resource,
6573                 rte_atomic32_read(&cache_resource->refcnt));
6574         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6575                 claim_zero(mlx5_glue->destroy_flow_action
6576                                 (cache_resource->action));
6577                 LIST_REMOVE(cache_resource, next);
6578                 rte_free(cache_resource);
6579                 DRV_LOG(DEBUG, "port id action resource %p: removed",
6580                         (void *)cache_resource);
6581                 return 0;
6582         }
6583         return 1;
6584 }
6585
6586 /**
6587  * Release push vlan action resource.
6588  *
6589  * @param flow
6590  *   Pointer to mlx5_flow.
6591  *
6592  * @return
6593  *   1 while a reference on it exists, 0 when freed.
6594  */
6595 static int
6596 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
6597 {
6598         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
6599                 flow->dv.push_vlan_res;
6600
6601         assert(cache_resource->action);
6602         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
6603                 (void *)cache_resource,
6604                 rte_atomic32_read(&cache_resource->refcnt));
6605         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
6606                 claim_zero(mlx5_glue->destroy_flow_action
6607                                 (cache_resource->action));
6608                 LIST_REMOVE(cache_resource, next);
6609                 rte_free(cache_resource);
6610                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
6611                         (void *)cache_resource);
6612                 return 0;
6613         }
6614         return 1;
6615 }
6616
6617 /**
6618  * Remove the flow from the NIC but keeps it in memory.
6619  * Lock free, (mutex should be acquired by caller).
6620  *
6621  * @param[in] dev
6622  *   Pointer to Ethernet device.
6623  * @param[in, out] flow
6624  *   Pointer to flow structure.
6625  */
6626 static void
6627 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6628 {
6629         struct mlx5_flow_dv *dv;
6630         struct mlx5_flow *dev_flow;
6631
6632         if (!flow)
6633                 return;
6634         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
6635                 dv = &dev_flow->dv;
6636                 if (dv->flow) {
6637                         claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
6638                         dv->flow = NULL;
6639                 }
6640                 if (dv->hrxq) {
6641                         if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
6642                                 mlx5_hrxq_drop_release(dev);
6643                         else
6644                                 mlx5_hrxq_release(dev, dv->hrxq);
6645                         dv->hrxq = NULL;
6646                 }
6647                 if (dev_flow->dv.vf_vlan.tag &&
6648                     dev_flow->dv.vf_vlan.created)
6649                         mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
6650         }
6651 }
6652
6653 /**
6654  * Remove the flow from the NIC and the memory.
6655  * Lock free, (mutex should be acquired by caller).
6656  *
6657  * @param[in] dev
6658  *   Pointer to the Ethernet device structure.
6659  * @param[in, out] flow
6660  *   Pointer to flow structure.
6661  */
6662 static void
6663 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6664 {
6665         struct mlx5_flow *dev_flow;
6666
6667         if (!flow)
6668                 return;
6669         __flow_dv_remove(dev, flow);
6670         if (flow->counter) {
6671                 flow_dv_counter_release(dev, flow->counter);
6672                 flow->counter = NULL;
6673         }
6674         while (!LIST_EMPTY(&flow->dev_flows)) {
6675                 dev_flow = LIST_FIRST(&flow->dev_flows);
6676                 LIST_REMOVE(dev_flow, next);
6677                 if (dev_flow->dv.matcher)
6678                         flow_dv_matcher_release(dev, dev_flow);
6679                 if (dev_flow->dv.encap_decap)
6680                         flow_dv_encap_decap_resource_release(dev_flow);
6681                 if (dev_flow->dv.modify_hdr)
6682                         flow_dv_modify_hdr_resource_release(dev_flow);
6683                 if (dev_flow->dv.jump)
6684                         flow_dv_jump_tbl_resource_release(dev_flow);
6685                 if (dev_flow->dv.port_id_action)
6686                         flow_dv_port_id_action_resource_release(dev_flow);
6687                 if (dev_flow->dv.push_vlan_res)
6688                         flow_dv_push_vlan_action_resource_release(dev_flow);
6689                 if (dev_flow->dv.tag_resource)
6690                         flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
6691                 rte_free(dev_flow);
6692         }
6693 }
6694
6695 /**
6696  * Query a dv flow  rule for its statistics via devx.
6697  *
6698  * @param[in] dev
6699  *   Pointer to Ethernet device.
6700  * @param[in] flow
6701  *   Pointer to the sub flow.
6702  * @param[out] data
6703  *   data retrieved by the query.
6704  * @param[out] error
6705  *   Perform verbose error reporting if not NULL.
6706  *
6707  * @return
6708  *   0 on success, a negative errno value otherwise and rte_errno is set.
6709  */
6710 static int
6711 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
6712                     void *data, struct rte_flow_error *error)
6713 {
6714         struct mlx5_priv *priv = dev->data->dev_private;
6715         struct rte_flow_query_count *qc = data;
6716
6717         if (!priv->config.devx)
6718                 return rte_flow_error_set(error, ENOTSUP,
6719                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6720                                           NULL,
6721                                           "counters are not supported");
6722         if (flow->counter) {
6723                 uint64_t pkts, bytes;
6724                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
6725                                                &bytes);
6726
6727                 if (err)
6728                         return rte_flow_error_set(error, -err,
6729                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6730                                         NULL, "cannot read counters");
6731                 qc->hits_set = 1;
6732                 qc->bytes_set = 1;
6733                 qc->hits = pkts - flow->counter->hits;
6734                 qc->bytes = bytes - flow->counter->bytes;
6735                 if (qc->reset) {
6736                         flow->counter->hits = pkts;
6737                         flow->counter->bytes = bytes;
6738                 }
6739                 return 0;
6740         }
6741         return rte_flow_error_set(error, EINVAL,
6742                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6743                                   NULL,
6744                                   "counters are not available");
6745 }
6746
6747 /**
6748  * Query a flow.
6749  *
6750  * @see rte_flow_query()
6751  * @see rte_flow_ops
6752  */
6753 static int
6754 flow_dv_query(struct rte_eth_dev *dev,
6755               struct rte_flow *flow __rte_unused,
6756               const struct rte_flow_action *actions __rte_unused,
6757               void *data __rte_unused,
6758               struct rte_flow_error *error __rte_unused)
6759 {
6760         int ret = -EINVAL;
6761
6762         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6763                 switch (actions->type) {
6764                 case RTE_FLOW_ACTION_TYPE_VOID:
6765                         break;
6766                 case RTE_FLOW_ACTION_TYPE_COUNT:
6767                         ret = flow_dv_query_count(dev, flow, data, error);
6768                         break;
6769                 default:
6770                         return rte_flow_error_set(error, ENOTSUP,
6771                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6772                                                   actions,
6773                                                   "action not supported");
6774                 }
6775         }
6776         return ret;
6777 }
6778
6779 /*
6780  * Mutex-protected thunk to lock-free  __flow_dv_translate().
6781  */
6782 static int
6783 flow_dv_translate(struct rte_eth_dev *dev,
6784                   struct mlx5_flow *dev_flow,
6785                   const struct rte_flow_attr *attr,
6786                   const struct rte_flow_item items[],
6787                   const struct rte_flow_action actions[],
6788                   struct rte_flow_error *error)
6789 {
6790         int ret;
6791
6792         flow_dv_shared_lock(dev);
6793         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
6794         flow_dv_shared_unlock(dev);
6795         return ret;
6796 }
6797
6798 /*
6799  * Mutex-protected thunk to lock-free  __flow_dv_apply().
6800  */
6801 static int
6802 flow_dv_apply(struct rte_eth_dev *dev,
6803               struct rte_flow *flow,
6804               struct rte_flow_error *error)
6805 {
6806         int ret;
6807
6808         flow_dv_shared_lock(dev);
6809         ret = __flow_dv_apply(dev, flow, error);
6810         flow_dv_shared_unlock(dev);
6811         return ret;
6812 }
6813
6814 /*
6815  * Mutex-protected thunk to lock-free __flow_dv_remove().
6816  */
6817 static void
6818 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
6819 {
6820         flow_dv_shared_lock(dev);
6821         __flow_dv_remove(dev, flow);
6822         flow_dv_shared_unlock(dev);
6823 }
6824
6825 /*
6826  * Mutex-protected thunk to lock-free __flow_dv_destroy().
6827  */
6828 static void
6829 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
6830 {
6831         flow_dv_shared_lock(dev);
6832         __flow_dv_destroy(dev, flow);
6833         flow_dv_shared_unlock(dev);
6834 }
6835
6836 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
6837         .validate = flow_dv_validate,
6838         .prepare = flow_dv_prepare,
6839         .translate = flow_dv_translate,
6840         .apply = flow_dv_apply,
6841         .remove = flow_dv_remove,
6842         .destroy = flow_dv_destroy,
6843         .query = flow_dv_query,
6844 };
6845
6846 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */