1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
32 #include <mlx5_glue.h>
33 #include <mlx5_devx_cmds.h>
36 #include "mlx5_defs.h"
38 #include "mlx5_flow.h"
39 #include "mlx5_rxtx.h"
41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
47 #ifndef HAVE_MLX5DV_DR_ESWITCH
48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
53 #ifndef HAVE_MLX5DV_DR
54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
78 struct mlx5_flow_tbl_resource *tbl);
81 * Initialize flow attributes structure according to flow items' types.
83 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
84 * mode. For tunnel mode, the items to be modified are the outermost ones.
87 * Pointer to item specification.
89 * Pointer to flow attributes structure.
91 * Pointer to the sub flow.
92 * @param[in] tunnel_decap
93 * Whether action is after tunnel decapsulation.
96 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
97 struct mlx5_flow *dev_flow, bool tunnel_decap)
99 uint64_t layers = dev_flow->handle->layers;
102 * If layers is already initialized, it means this dev_flow is the
103 * suffix flow, the layers flags is set by the prefix flow. Need to
104 * use the layer flags from prefix flow as the suffix flow may not
105 * have the user defined items as the flow is split.
108 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
110 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
112 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
114 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
119 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
120 uint8_t next_protocol = 0xff;
121 switch (item->type) {
122 case RTE_FLOW_ITEM_TYPE_GRE:
123 case RTE_FLOW_ITEM_TYPE_NVGRE:
124 case RTE_FLOW_ITEM_TYPE_VXLAN:
125 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
126 case RTE_FLOW_ITEM_TYPE_GENEVE:
127 case RTE_FLOW_ITEM_TYPE_MPLS:
131 case RTE_FLOW_ITEM_TYPE_IPV4:
134 if (item->mask != NULL &&
135 ((const struct rte_flow_item_ipv4 *)
136 item->mask)->hdr.next_proto_id)
138 ((const struct rte_flow_item_ipv4 *)
139 (item->spec))->hdr.next_proto_id &
140 ((const struct rte_flow_item_ipv4 *)
141 (item->mask))->hdr.next_proto_id;
142 if ((next_protocol == IPPROTO_IPIP ||
143 next_protocol == IPPROTO_IPV6) && tunnel_decap)
146 case RTE_FLOW_ITEM_TYPE_IPV6:
149 if (item->mask != NULL &&
150 ((const struct rte_flow_item_ipv6 *)
151 item->mask)->hdr.proto)
153 ((const struct rte_flow_item_ipv6 *)
154 (item->spec))->hdr.proto &
155 ((const struct rte_flow_item_ipv6 *)
156 (item->mask))->hdr.proto;
157 if ((next_protocol == IPPROTO_IPIP ||
158 next_protocol == IPPROTO_IPV6) && tunnel_decap)
161 case RTE_FLOW_ITEM_TYPE_UDP:
165 case RTE_FLOW_ITEM_TYPE_TCP:
177 * Convert rte_mtr_color to mlx5 color.
186 rte_col_2_mlx5_col(enum rte_color rcol)
189 case RTE_COLOR_GREEN:
190 return MLX5_FLOW_COLOR_GREEN;
191 case RTE_COLOR_YELLOW:
192 return MLX5_FLOW_COLOR_YELLOW;
194 return MLX5_FLOW_COLOR_RED;
198 return MLX5_FLOW_COLOR_UNDEFINED;
201 struct field_modify_info {
202 uint32_t size; /* Size of field in protocol header, in bytes. */
203 uint32_t offset; /* Offset of field in protocol header, in bytes. */
204 enum mlx5_modification_field id;
207 struct field_modify_info modify_eth[] = {
208 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
209 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
210 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
211 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
215 struct field_modify_info modify_vlan_out_first_vid[] = {
216 /* Size in bits !!! */
217 {12, 0, MLX5_MODI_OUT_FIRST_VID},
221 struct field_modify_info modify_ipv4[] = {
222 {1, 1, MLX5_MODI_OUT_IP_DSCP},
223 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
224 {4, 12, MLX5_MODI_OUT_SIPV4},
225 {4, 16, MLX5_MODI_OUT_DIPV4},
229 struct field_modify_info modify_ipv6[] = {
230 {1, 0, MLX5_MODI_OUT_IP_DSCP},
231 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
232 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
233 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
234 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
235 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
236 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
237 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
238 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
239 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
243 struct field_modify_info modify_udp[] = {
244 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
245 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
249 struct field_modify_info modify_tcp[] = {
250 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
251 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
252 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
253 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
258 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
259 uint8_t next_protocol, uint64_t *item_flags,
262 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
263 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
264 if (next_protocol == IPPROTO_IPIP) {
265 *item_flags |= MLX5_FLOW_LAYER_IPIP;
268 if (next_protocol == IPPROTO_IPV6) {
269 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
275 * Acquire the synchronizing object to protect multithreaded access
276 * to shared dv context. Lock occurs only if context is actually
277 * shared, i.e. we have multiport IB device and representors are
281 * Pointer to the rte_eth_dev structure.
284 flow_dv_shared_lock(struct rte_eth_dev *dev)
286 struct mlx5_priv *priv = dev->data->dev_private;
287 struct mlx5_ibv_shared *sh = priv->sh;
289 if (sh->dv_refcnt > 1) {
292 ret = pthread_mutex_lock(&sh->dv_mutex);
299 flow_dv_shared_unlock(struct rte_eth_dev *dev)
301 struct mlx5_priv *priv = dev->data->dev_private;
302 struct mlx5_ibv_shared *sh = priv->sh;
304 if (sh->dv_refcnt > 1) {
307 ret = pthread_mutex_unlock(&sh->dv_mutex);
313 /* Update VLAN's VID/PCP based on input rte_flow_action.
316 * Pointer to struct rte_flow_action.
318 * Pointer to struct rte_vlan_hdr.
321 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
322 struct rte_vlan_hdr *vlan)
325 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
327 ((const struct rte_flow_action_of_set_vlan_pcp *)
328 action->conf)->vlan_pcp;
329 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
330 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
331 vlan->vlan_tci |= vlan_tci;
332 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
333 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
334 vlan->vlan_tci |= rte_be_to_cpu_16
335 (((const struct rte_flow_action_of_set_vlan_vid *)
336 action->conf)->vlan_vid);
341 * Fetch 1, 2, 3 or 4 byte field from the byte array
342 * and return as unsigned integer in host-endian format.
345 * Pointer to data array.
347 * Size of field to extract.
350 * converted field in host endian format.
352 static inline uint32_t
353 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
362 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
365 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
366 ret = (ret << 8) | *(data + sizeof(uint16_t));
369 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
380 * Convert modify-header action to DV specification.
382 * Data length of each action is determined by provided field description
383 * and the item mask. Data bit offset and width of each action is determined
384 * by provided item mask.
387 * Pointer to item specification.
389 * Pointer to field modification information.
390 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
391 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
392 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
394 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
395 * Negative offset value sets the same offset as source offset.
396 * size field is ignored, value is taken from source field.
397 * @param[in,out] resource
398 * Pointer to the modify-header resource.
400 * Type of modification.
402 * Pointer to the error structure.
405 * 0 on success, a negative errno value otherwise and rte_errno is set.
408 flow_dv_convert_modify_action(struct rte_flow_item *item,
409 struct field_modify_info *field,
410 struct field_modify_info *dcopy,
411 struct mlx5_flow_dv_modify_hdr_resource *resource,
412 uint32_t type, struct rte_flow_error *error)
414 uint32_t i = resource->actions_num;
415 struct mlx5_modification_cmd *actions = resource->actions;
418 * The item and mask are provided in big-endian format.
419 * The fields should be presented as in big-endian format either.
420 * Mask must be always present, it defines the actual field width.
422 MLX5_ASSERT(item->mask);
423 MLX5_ASSERT(field->size);
430 if (i >= MLX5_MAX_MODIFY_NUM)
431 return rte_flow_error_set(error, EINVAL,
432 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
433 "too many items to modify");
434 /* Fetch variable byte size mask from the array. */
435 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
436 field->offset, field->size);
441 /* Deduce actual data width in bits from mask value. */
442 off_b = rte_bsf32(mask);
443 size_b = sizeof(uint32_t) * CHAR_BIT -
444 off_b - __builtin_clz(mask);
446 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
447 actions[i] = (struct mlx5_modification_cmd) {
453 /* Convert entire record to expected big-endian format. */
454 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
455 if (type == MLX5_MODIFICATION_TYPE_COPY) {
457 actions[i].dst_field = dcopy->id;
458 actions[i].dst_offset =
459 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
460 /* Convert entire record to big-endian format. */
461 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
463 MLX5_ASSERT(item->spec);
464 data = flow_dv_fetch_field((const uint8_t *)item->spec +
465 field->offset, field->size);
466 /* Shift out the trailing masked bits from data. */
467 data = (data & mask) >> off_b;
468 actions[i].data1 = rte_cpu_to_be_32(data);
472 } while (field->size);
473 if (resource->actions_num == i)
474 return rte_flow_error_set(error, EINVAL,
475 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
476 "invalid modification flow item");
477 resource->actions_num = i;
482 * Convert modify-header set IPv4 address action to DV specification.
484 * @param[in,out] resource
485 * Pointer to the modify-header resource.
487 * Pointer to action specification.
489 * Pointer to the error structure.
492 * 0 on success, a negative errno value otherwise and rte_errno is set.
495 flow_dv_convert_action_modify_ipv4
496 (struct mlx5_flow_dv_modify_hdr_resource *resource,
497 const struct rte_flow_action *action,
498 struct rte_flow_error *error)
500 const struct rte_flow_action_set_ipv4 *conf =
501 (const struct rte_flow_action_set_ipv4 *)(action->conf);
502 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
503 struct rte_flow_item_ipv4 ipv4;
504 struct rte_flow_item_ipv4 ipv4_mask;
506 memset(&ipv4, 0, sizeof(ipv4));
507 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
508 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
509 ipv4.hdr.src_addr = conf->ipv4_addr;
510 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
512 ipv4.hdr.dst_addr = conf->ipv4_addr;
513 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
516 item.mask = &ipv4_mask;
517 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
518 MLX5_MODIFICATION_TYPE_SET, error);
522 * Convert modify-header set IPv6 address action to DV specification.
524 * @param[in,out] resource
525 * Pointer to the modify-header resource.
527 * Pointer to action specification.
529 * Pointer to the error structure.
532 * 0 on success, a negative errno value otherwise and rte_errno is set.
535 flow_dv_convert_action_modify_ipv6
536 (struct mlx5_flow_dv_modify_hdr_resource *resource,
537 const struct rte_flow_action *action,
538 struct rte_flow_error *error)
540 const struct rte_flow_action_set_ipv6 *conf =
541 (const struct rte_flow_action_set_ipv6 *)(action->conf);
542 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
543 struct rte_flow_item_ipv6 ipv6;
544 struct rte_flow_item_ipv6 ipv6_mask;
546 memset(&ipv6, 0, sizeof(ipv6));
547 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
548 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
549 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
550 sizeof(ipv6.hdr.src_addr));
551 memcpy(&ipv6_mask.hdr.src_addr,
552 &rte_flow_item_ipv6_mask.hdr.src_addr,
553 sizeof(ipv6.hdr.src_addr));
555 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
556 sizeof(ipv6.hdr.dst_addr));
557 memcpy(&ipv6_mask.hdr.dst_addr,
558 &rte_flow_item_ipv6_mask.hdr.dst_addr,
559 sizeof(ipv6.hdr.dst_addr));
562 item.mask = &ipv6_mask;
563 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
564 MLX5_MODIFICATION_TYPE_SET, error);
568 * Convert modify-header set MAC address action to DV specification.
570 * @param[in,out] resource
571 * Pointer to the modify-header resource.
573 * Pointer to action specification.
575 * Pointer to the error structure.
578 * 0 on success, a negative errno value otherwise and rte_errno is set.
581 flow_dv_convert_action_modify_mac
582 (struct mlx5_flow_dv_modify_hdr_resource *resource,
583 const struct rte_flow_action *action,
584 struct rte_flow_error *error)
586 const struct rte_flow_action_set_mac *conf =
587 (const struct rte_flow_action_set_mac *)(action->conf);
588 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
589 struct rte_flow_item_eth eth;
590 struct rte_flow_item_eth eth_mask;
592 memset(ð, 0, sizeof(eth));
593 memset(ð_mask, 0, sizeof(eth_mask));
594 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
595 memcpy(ð.src.addr_bytes, &conf->mac_addr,
596 sizeof(eth.src.addr_bytes));
597 memcpy(ð_mask.src.addr_bytes,
598 &rte_flow_item_eth_mask.src.addr_bytes,
599 sizeof(eth_mask.src.addr_bytes));
601 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
602 sizeof(eth.dst.addr_bytes));
603 memcpy(ð_mask.dst.addr_bytes,
604 &rte_flow_item_eth_mask.dst.addr_bytes,
605 sizeof(eth_mask.dst.addr_bytes));
608 item.mask = ð_mask;
609 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
610 MLX5_MODIFICATION_TYPE_SET, error);
614 * Convert modify-header set VLAN VID action to DV specification.
616 * @param[in,out] resource
617 * Pointer to the modify-header resource.
619 * Pointer to action specification.
621 * Pointer to the error structure.
624 * 0 on success, a negative errno value otherwise and rte_errno is set.
627 flow_dv_convert_action_modify_vlan_vid
628 (struct mlx5_flow_dv_modify_hdr_resource *resource,
629 const struct rte_flow_action *action,
630 struct rte_flow_error *error)
632 const struct rte_flow_action_of_set_vlan_vid *conf =
633 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
634 int i = resource->actions_num;
635 struct mlx5_modification_cmd *actions = resource->actions;
636 struct field_modify_info *field = modify_vlan_out_first_vid;
638 if (i >= MLX5_MAX_MODIFY_NUM)
639 return rte_flow_error_set(error, EINVAL,
640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
641 "too many items to modify");
642 actions[i] = (struct mlx5_modification_cmd) {
643 .action_type = MLX5_MODIFICATION_TYPE_SET,
645 .length = field->size,
646 .offset = field->offset,
648 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
649 actions[i].data1 = conf->vlan_vid;
650 actions[i].data1 = actions[i].data1 << 16;
651 resource->actions_num = ++i;
656 * Convert modify-header set TP action to DV specification.
658 * @param[in,out] resource
659 * Pointer to the modify-header resource.
661 * Pointer to action specification.
663 * Pointer to rte_flow_item objects list.
665 * Pointer to flow attributes structure.
666 * @param[in] dev_flow
667 * Pointer to the sub flow.
668 * @param[in] tunnel_decap
669 * Whether action is after tunnel decapsulation.
671 * Pointer to the error structure.
674 * 0 on success, a negative errno value otherwise and rte_errno is set.
677 flow_dv_convert_action_modify_tp
678 (struct mlx5_flow_dv_modify_hdr_resource *resource,
679 const struct rte_flow_action *action,
680 const struct rte_flow_item *items,
681 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
682 bool tunnel_decap, struct rte_flow_error *error)
684 const struct rte_flow_action_set_tp *conf =
685 (const struct rte_flow_action_set_tp *)(action->conf);
686 struct rte_flow_item item;
687 struct rte_flow_item_udp udp;
688 struct rte_flow_item_udp udp_mask;
689 struct rte_flow_item_tcp tcp;
690 struct rte_flow_item_tcp tcp_mask;
691 struct field_modify_info *field;
694 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
696 memset(&udp, 0, sizeof(udp));
697 memset(&udp_mask, 0, sizeof(udp_mask));
698 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
699 udp.hdr.src_port = conf->port;
700 udp_mask.hdr.src_port =
701 rte_flow_item_udp_mask.hdr.src_port;
703 udp.hdr.dst_port = conf->port;
704 udp_mask.hdr.dst_port =
705 rte_flow_item_udp_mask.hdr.dst_port;
707 item.type = RTE_FLOW_ITEM_TYPE_UDP;
709 item.mask = &udp_mask;
712 MLX5_ASSERT(attr->tcp);
713 memset(&tcp, 0, sizeof(tcp));
714 memset(&tcp_mask, 0, sizeof(tcp_mask));
715 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
716 tcp.hdr.src_port = conf->port;
717 tcp_mask.hdr.src_port =
718 rte_flow_item_tcp_mask.hdr.src_port;
720 tcp.hdr.dst_port = conf->port;
721 tcp_mask.hdr.dst_port =
722 rte_flow_item_tcp_mask.hdr.dst_port;
724 item.type = RTE_FLOW_ITEM_TYPE_TCP;
726 item.mask = &tcp_mask;
729 return flow_dv_convert_modify_action(&item, field, NULL, resource,
730 MLX5_MODIFICATION_TYPE_SET, error);
734 * Convert modify-header set TTL action to DV specification.
736 * @param[in,out] resource
737 * Pointer to the modify-header resource.
739 * Pointer to action specification.
741 * Pointer to rte_flow_item objects list.
743 * Pointer to flow attributes structure.
744 * @param[in] dev_flow
745 * Pointer to the sub flow.
746 * @param[in] tunnel_decap
747 * Whether action is after tunnel decapsulation.
749 * Pointer to the error structure.
752 * 0 on success, a negative errno value otherwise and rte_errno is set.
755 flow_dv_convert_action_modify_ttl
756 (struct mlx5_flow_dv_modify_hdr_resource *resource,
757 const struct rte_flow_action *action,
758 const struct rte_flow_item *items,
759 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
760 bool tunnel_decap, struct rte_flow_error *error)
762 const struct rte_flow_action_set_ttl *conf =
763 (const struct rte_flow_action_set_ttl *)(action->conf);
764 struct rte_flow_item item;
765 struct rte_flow_item_ipv4 ipv4;
766 struct rte_flow_item_ipv4 ipv4_mask;
767 struct rte_flow_item_ipv6 ipv6;
768 struct rte_flow_item_ipv6 ipv6_mask;
769 struct field_modify_info *field;
772 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
774 memset(&ipv4, 0, sizeof(ipv4));
775 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
776 ipv4.hdr.time_to_live = conf->ttl_value;
777 ipv4_mask.hdr.time_to_live = 0xFF;
778 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
780 item.mask = &ipv4_mask;
783 MLX5_ASSERT(attr->ipv6);
784 memset(&ipv6, 0, sizeof(ipv6));
785 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
786 ipv6.hdr.hop_limits = conf->ttl_value;
787 ipv6_mask.hdr.hop_limits = 0xFF;
788 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
790 item.mask = &ipv6_mask;
793 return flow_dv_convert_modify_action(&item, field, NULL, resource,
794 MLX5_MODIFICATION_TYPE_SET, error);
798 * Convert modify-header decrement TTL action to DV specification.
800 * @param[in,out] resource
801 * Pointer to the modify-header resource.
803 * Pointer to action specification.
805 * Pointer to rte_flow_item objects list.
807 * Pointer to flow attributes structure.
808 * @param[in] dev_flow
809 * Pointer to the sub flow.
810 * @param[in] tunnel_decap
811 * Whether action is after tunnel decapsulation.
813 * Pointer to the error structure.
816 * 0 on success, a negative errno value otherwise and rte_errno is set.
819 flow_dv_convert_action_modify_dec_ttl
820 (struct mlx5_flow_dv_modify_hdr_resource *resource,
821 const struct rte_flow_item *items,
822 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
823 bool tunnel_decap, struct rte_flow_error *error)
825 struct rte_flow_item item;
826 struct rte_flow_item_ipv4 ipv4;
827 struct rte_flow_item_ipv4 ipv4_mask;
828 struct rte_flow_item_ipv6 ipv6;
829 struct rte_flow_item_ipv6 ipv6_mask;
830 struct field_modify_info *field;
833 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
835 memset(&ipv4, 0, sizeof(ipv4));
836 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
837 ipv4.hdr.time_to_live = 0xFF;
838 ipv4_mask.hdr.time_to_live = 0xFF;
839 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
841 item.mask = &ipv4_mask;
844 MLX5_ASSERT(attr->ipv6);
845 memset(&ipv6, 0, sizeof(ipv6));
846 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
847 ipv6.hdr.hop_limits = 0xFF;
848 ipv6_mask.hdr.hop_limits = 0xFF;
849 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
851 item.mask = &ipv6_mask;
854 return flow_dv_convert_modify_action(&item, field, NULL, resource,
855 MLX5_MODIFICATION_TYPE_ADD, error);
859 * Convert modify-header increment/decrement TCP Sequence number
860 * to DV specification.
862 * @param[in,out] resource
863 * Pointer to the modify-header resource.
865 * Pointer to action specification.
867 * Pointer to the error structure.
870 * 0 on success, a negative errno value otherwise and rte_errno is set.
873 flow_dv_convert_action_modify_tcp_seq
874 (struct mlx5_flow_dv_modify_hdr_resource *resource,
875 const struct rte_flow_action *action,
876 struct rte_flow_error *error)
878 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
879 uint64_t value = rte_be_to_cpu_32(*conf);
880 struct rte_flow_item item;
881 struct rte_flow_item_tcp tcp;
882 struct rte_flow_item_tcp tcp_mask;
884 memset(&tcp, 0, sizeof(tcp));
885 memset(&tcp_mask, 0, sizeof(tcp_mask));
886 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
888 * The HW has no decrement operation, only increment operation.
889 * To simulate decrement X from Y using increment operation
890 * we need to add UINT32_MAX X times to Y.
891 * Each adding of UINT32_MAX decrements Y by 1.
894 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
895 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
896 item.type = RTE_FLOW_ITEM_TYPE_TCP;
898 item.mask = &tcp_mask;
899 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
900 MLX5_MODIFICATION_TYPE_ADD, error);
904 * Convert modify-header increment/decrement TCP Acknowledgment number
905 * to DV specification.
907 * @param[in,out] resource
908 * Pointer to the modify-header resource.
910 * Pointer to action specification.
912 * Pointer to the error structure.
915 * 0 on success, a negative errno value otherwise and rte_errno is set.
918 flow_dv_convert_action_modify_tcp_ack
919 (struct mlx5_flow_dv_modify_hdr_resource *resource,
920 const struct rte_flow_action *action,
921 struct rte_flow_error *error)
923 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
924 uint64_t value = rte_be_to_cpu_32(*conf);
925 struct rte_flow_item item;
926 struct rte_flow_item_tcp tcp;
927 struct rte_flow_item_tcp tcp_mask;
929 memset(&tcp, 0, sizeof(tcp));
930 memset(&tcp_mask, 0, sizeof(tcp_mask));
931 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
933 * The HW has no decrement operation, only increment operation.
934 * To simulate decrement X from Y using increment operation
935 * we need to add UINT32_MAX X times to Y.
936 * Each adding of UINT32_MAX decrements Y by 1.
939 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
940 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
941 item.type = RTE_FLOW_ITEM_TYPE_TCP;
943 item.mask = &tcp_mask;
944 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
945 MLX5_MODIFICATION_TYPE_ADD, error);
948 static enum mlx5_modification_field reg_to_field[] = {
949 [REG_NONE] = MLX5_MODI_OUT_NONE,
950 [REG_A] = MLX5_MODI_META_DATA_REG_A,
951 [REG_B] = MLX5_MODI_META_DATA_REG_B,
952 [REG_C_0] = MLX5_MODI_META_REG_C_0,
953 [REG_C_1] = MLX5_MODI_META_REG_C_1,
954 [REG_C_2] = MLX5_MODI_META_REG_C_2,
955 [REG_C_3] = MLX5_MODI_META_REG_C_3,
956 [REG_C_4] = MLX5_MODI_META_REG_C_4,
957 [REG_C_5] = MLX5_MODI_META_REG_C_5,
958 [REG_C_6] = MLX5_MODI_META_REG_C_6,
959 [REG_C_7] = MLX5_MODI_META_REG_C_7,
963 * Convert register set to DV specification.
965 * @param[in,out] resource
966 * Pointer to the modify-header resource.
968 * Pointer to action specification.
970 * Pointer to the error structure.
973 * 0 on success, a negative errno value otherwise and rte_errno is set.
976 flow_dv_convert_action_set_reg
977 (struct mlx5_flow_dv_modify_hdr_resource *resource,
978 const struct rte_flow_action *action,
979 struct rte_flow_error *error)
981 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
982 struct mlx5_modification_cmd *actions = resource->actions;
983 uint32_t i = resource->actions_num;
985 if (i >= MLX5_MAX_MODIFY_NUM)
986 return rte_flow_error_set(error, EINVAL,
987 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
988 "too many items to modify");
989 MLX5_ASSERT(conf->id != REG_NONE);
990 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
991 actions[i] = (struct mlx5_modification_cmd) {
992 .action_type = MLX5_MODIFICATION_TYPE_SET,
993 .field = reg_to_field[conf->id],
995 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
996 actions[i].data1 = rte_cpu_to_be_32(conf->data);
998 resource->actions_num = i;
1003 * Convert SET_TAG action to DV specification.
1006 * Pointer to the rte_eth_dev structure.
1007 * @param[in,out] resource
1008 * Pointer to the modify-header resource.
1010 * Pointer to action specification.
1012 * Pointer to the error structure.
1015 * 0 on success, a negative errno value otherwise and rte_errno is set.
1018 flow_dv_convert_action_set_tag
1019 (struct rte_eth_dev *dev,
1020 struct mlx5_flow_dv_modify_hdr_resource *resource,
1021 const struct rte_flow_action_set_tag *conf,
1022 struct rte_flow_error *error)
1024 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1025 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1026 struct rte_flow_item item = {
1030 struct field_modify_info reg_c_x[] = {
1033 enum mlx5_modification_field reg_type;
1036 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1039 MLX5_ASSERT(ret != REG_NONE);
1040 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1041 reg_type = reg_to_field[ret];
1042 MLX5_ASSERT(reg_type > 0);
1043 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1044 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1045 MLX5_MODIFICATION_TYPE_SET, error);
1049 * Convert internal COPY_REG action to DV specification.
1052 * Pointer to the rte_eth_dev structure.
1053 * @param[in,out] res
1054 * Pointer to the modify-header resource.
1056 * Pointer to action specification.
1058 * Pointer to the error structure.
1061 * 0 on success, a negative errno value otherwise and rte_errno is set.
1064 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1065 struct mlx5_flow_dv_modify_hdr_resource *res,
1066 const struct rte_flow_action *action,
1067 struct rte_flow_error *error)
1069 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1070 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1071 struct rte_flow_item item = {
1075 struct field_modify_info reg_src[] = {
1076 {4, 0, reg_to_field[conf->src]},
1079 struct field_modify_info reg_dst = {
1081 .id = reg_to_field[conf->dst],
1083 /* Adjust reg_c[0] usage according to reported mask. */
1084 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1085 struct mlx5_priv *priv = dev->data->dev_private;
1086 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088 MLX5_ASSERT(reg_c0);
1089 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1090 if (conf->dst == REG_C_0) {
1091 /* Copy to reg_c[0], within mask only. */
1092 reg_dst.offset = rte_bsf32(reg_c0);
1094 * Mask is ignoring the enianness, because
1095 * there is no conversion in datapath.
1097 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1098 /* Copy from destination lower bits to reg_c[0]. */
1099 mask = reg_c0 >> reg_dst.offset;
1101 /* Copy from destination upper bits to reg_c[0]. */
1102 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1103 rte_fls_u32(reg_c0));
1106 mask = rte_cpu_to_be_32(reg_c0);
1107 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1108 /* Copy from reg_c[0] to destination lower bits. */
1111 /* Copy from reg_c[0] to destination upper bits. */
1112 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1113 (rte_fls_u32(reg_c0) -
1118 return flow_dv_convert_modify_action(&item,
1119 reg_src, ®_dst, res,
1120 MLX5_MODIFICATION_TYPE_COPY,
1125 * Convert MARK action to DV specification. This routine is used
1126 * in extensive metadata only and requires metadata register to be
1127 * handled. In legacy mode hardware tag resource is engaged.
1130 * Pointer to the rte_eth_dev structure.
1132 * Pointer to MARK action specification.
1133 * @param[in,out] resource
1134 * Pointer to the modify-header resource.
1136 * Pointer to the error structure.
1139 * 0 on success, a negative errno value otherwise and rte_errno is set.
1142 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1143 const struct rte_flow_action_mark *conf,
1144 struct mlx5_flow_dv_modify_hdr_resource *resource,
1145 struct rte_flow_error *error)
1147 struct mlx5_priv *priv = dev->data->dev_private;
1148 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1149 priv->sh->dv_mark_mask);
1150 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1151 struct rte_flow_item item = {
1155 struct field_modify_info reg_c_x[] = {
1156 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1162 return rte_flow_error_set(error, EINVAL,
1163 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1164 NULL, "zero mark action mask");
1165 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1168 MLX5_ASSERT(reg > 0);
1169 if (reg == REG_C_0) {
1170 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1171 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1174 mask = rte_cpu_to_be_32(mask) & msk_c0;
1175 mask = rte_cpu_to_be_32(mask << shl_c0);
1177 reg_c_x[0].id = reg_to_field[reg];
1178 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1179 MLX5_MODIFICATION_TYPE_SET, error);
1183 * Get metadata register index for specified steering domain.
1186 * Pointer to the rte_eth_dev structure.
1188 * Attributes of flow to determine steering domain.
1190 * Pointer to the error structure.
1193 * positive index on success, a negative errno value otherwise
1194 * and rte_errno is set.
1196 static enum modify_reg
1197 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1198 const struct rte_flow_attr *attr,
1199 struct rte_flow_error *error)
1202 mlx5_flow_get_reg_id(dev, attr->transfer ?
1206 MLX5_METADATA_RX, 0, error);
1208 return rte_flow_error_set(error,
1209 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1210 NULL, "unavailable "
1211 "metadata register");
1216 * Convert SET_META action to DV specification.
1219 * Pointer to the rte_eth_dev structure.
1220 * @param[in,out] resource
1221 * Pointer to the modify-header resource.
1223 * Attributes of flow that includes this item.
1225 * Pointer to action specification.
1227 * Pointer to the error structure.
1230 * 0 on success, a negative errno value otherwise and rte_errno is set.
1233 flow_dv_convert_action_set_meta
1234 (struct rte_eth_dev *dev,
1235 struct mlx5_flow_dv_modify_hdr_resource *resource,
1236 const struct rte_flow_attr *attr,
1237 const struct rte_flow_action_set_meta *conf,
1238 struct rte_flow_error *error)
1240 uint32_t data = conf->data;
1241 uint32_t mask = conf->mask;
1242 struct rte_flow_item item = {
1246 struct field_modify_info reg_c_x[] = {
1249 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1254 * In datapath code there is no endianness
1255 * coversions for perfromance reasons, all
1256 * pattern conversions are done in rte_flow.
1258 if (reg == REG_C_0) {
1259 struct mlx5_priv *priv = dev->data->dev_private;
1260 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1263 MLX5_ASSERT(msk_c0);
1264 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1265 shl_c0 = rte_bsf32(msk_c0);
1267 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1271 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1274 /* The routine expects parameters in memory as big-endian ones. */
1275 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1276 MLX5_MODIFICATION_TYPE_SET, error);
1280 * Convert modify-header set IPv4 DSCP action to DV specification.
1282 * @param[in,out] resource
1283 * Pointer to the modify-header resource.
1285 * Pointer to action specification.
1287 * Pointer to the error structure.
1290 * 0 on success, a negative errno value otherwise and rte_errno is set.
1293 flow_dv_convert_action_modify_ipv4_dscp
1294 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1295 const struct rte_flow_action *action,
1296 struct rte_flow_error *error)
1298 const struct rte_flow_action_set_dscp *conf =
1299 (const struct rte_flow_action_set_dscp *)(action->conf);
1300 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1301 struct rte_flow_item_ipv4 ipv4;
1302 struct rte_flow_item_ipv4 ipv4_mask;
1304 memset(&ipv4, 0, sizeof(ipv4));
1305 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1306 ipv4.hdr.type_of_service = conf->dscp;
1307 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309 item.mask = &ipv4_mask;
1310 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1311 MLX5_MODIFICATION_TYPE_SET, error);
1315 * Convert modify-header set IPv6 DSCP action to DV specification.
1317 * @param[in,out] resource
1318 * Pointer to the modify-header resource.
1320 * Pointer to action specification.
1322 * Pointer to the error structure.
1325 * 0 on success, a negative errno value otherwise and rte_errno is set.
1328 flow_dv_convert_action_modify_ipv6_dscp
1329 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1330 const struct rte_flow_action *action,
1331 struct rte_flow_error *error)
1333 const struct rte_flow_action_set_dscp *conf =
1334 (const struct rte_flow_action_set_dscp *)(action->conf);
1335 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1336 struct rte_flow_item_ipv6 ipv6;
1337 struct rte_flow_item_ipv6 ipv6_mask;
1339 memset(&ipv6, 0, sizeof(ipv6));
1340 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1343 * rdma-core only accept the DSCP bits byte aligned start from
1344 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1345 * bits in IPv6 case as rdma-core requires byte aligned value.
1347 ipv6.hdr.vtc_flow = conf->dscp;
1348 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350 item.mask = &ipv6_mask;
1351 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1352 MLX5_MODIFICATION_TYPE_SET, error);
1356 * Validate MARK item.
1359 * Pointer to the rte_eth_dev structure.
1361 * Item specification.
1363 * Attributes of flow that includes this item.
1365 * Pointer to error structure.
1368 * 0 on success, a negative errno value otherwise and rte_errno is set.
1371 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1372 const struct rte_flow_item *item,
1373 const struct rte_flow_attr *attr __rte_unused,
1374 struct rte_flow_error *error)
1376 struct mlx5_priv *priv = dev->data->dev_private;
1377 struct mlx5_dev_config *config = &priv->config;
1378 const struct rte_flow_item_mark *spec = item->spec;
1379 const struct rte_flow_item_mark *mask = item->mask;
1380 const struct rte_flow_item_mark nic_mask = {
1381 .id = priv->sh->dv_mark_mask,
1385 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1386 return rte_flow_error_set(error, ENOTSUP,
1387 RTE_FLOW_ERROR_TYPE_ITEM, item,
1388 "extended metadata feature"
1390 if (!mlx5_flow_ext_mreg_supported(dev))
1391 return rte_flow_error_set(error, ENOTSUP,
1392 RTE_FLOW_ERROR_TYPE_ITEM, item,
1393 "extended metadata register"
1394 " isn't supported");
1396 return rte_flow_error_set(error, ENOTSUP,
1397 RTE_FLOW_ERROR_TYPE_ITEM, item,
1398 "extended metadata register"
1399 " isn't available");
1400 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1404 return rte_flow_error_set(error, EINVAL,
1405 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407 "data cannot be empty");
1408 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1409 return rte_flow_error_set(error, EINVAL,
1410 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412 "mark id exceeds the limit");
1416 return rte_flow_error_set(error, EINVAL,
1417 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1418 "mask cannot be zero");
1420 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1421 (const uint8_t *)&nic_mask,
1422 sizeof(struct rte_flow_item_mark),
1430 * Validate META item.
1433 * Pointer to the rte_eth_dev structure.
1435 * Item specification.
1437 * Attributes of flow that includes this item.
1439 * Pointer to error structure.
1442 * 0 on success, a negative errno value otherwise and rte_errno is set.
1445 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1446 const struct rte_flow_item *item,
1447 const struct rte_flow_attr *attr,
1448 struct rte_flow_error *error)
1450 struct mlx5_priv *priv = dev->data->dev_private;
1451 struct mlx5_dev_config *config = &priv->config;
1452 const struct rte_flow_item_meta *spec = item->spec;
1453 const struct rte_flow_item_meta *mask = item->mask;
1454 struct rte_flow_item_meta nic_mask = {
1461 return rte_flow_error_set(error, EINVAL,
1462 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464 "data cannot be empty");
1465 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1466 if (!mlx5_flow_ext_mreg_supported(dev))
1467 return rte_flow_error_set(error, ENOTSUP,
1468 RTE_FLOW_ERROR_TYPE_ITEM, item,
1469 "extended metadata register"
1470 " isn't supported");
1471 reg = flow_dv_get_metadata_reg(dev, attr, error);
1475 return rte_flow_error_set(error, ENOTSUP,
1476 RTE_FLOW_ERROR_TYPE_ITEM, item,
1480 nic_mask.data = priv->sh->dv_meta_mask;
1483 mask = &rte_flow_item_meta_mask;
1485 return rte_flow_error_set(error, EINVAL,
1486 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1487 "mask cannot be zero");
1489 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1490 (const uint8_t *)&nic_mask,
1491 sizeof(struct rte_flow_item_meta),
1497 * Validate TAG item.
1500 * Pointer to the rte_eth_dev structure.
1502 * Item specification.
1504 * Attributes of flow that includes this item.
1506 * Pointer to error structure.
1509 * 0 on success, a negative errno value otherwise and rte_errno is set.
1512 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1513 const struct rte_flow_item *item,
1514 const struct rte_flow_attr *attr __rte_unused,
1515 struct rte_flow_error *error)
1517 const struct rte_flow_item_tag *spec = item->spec;
1518 const struct rte_flow_item_tag *mask = item->mask;
1519 const struct rte_flow_item_tag nic_mask = {
1520 .data = RTE_BE32(UINT32_MAX),
1525 if (!mlx5_flow_ext_mreg_supported(dev))
1526 return rte_flow_error_set(error, ENOTSUP,
1527 RTE_FLOW_ERROR_TYPE_ITEM, item,
1528 "extensive metadata register"
1529 " isn't supported");
1531 return rte_flow_error_set(error, EINVAL,
1532 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534 "data cannot be empty");
1536 mask = &rte_flow_item_tag_mask;
1538 return rte_flow_error_set(error, EINVAL,
1539 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1540 "mask cannot be zero");
1542 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1543 (const uint8_t *)&nic_mask,
1544 sizeof(struct rte_flow_item_tag),
1548 if (mask->index != 0xff)
1549 return rte_flow_error_set(error, EINVAL,
1550 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551 "partial mask for tag index"
1552 " is not supported");
1553 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1556 MLX5_ASSERT(ret != REG_NONE);
1561 * Validate vport item.
1564 * Pointer to the rte_eth_dev structure.
1566 * Item specification.
1568 * Attributes of flow that includes this item.
1569 * @param[in] item_flags
1570 * Bit-fields that holds the items detected until now.
1572 * Pointer to error structure.
1575 * 0 on success, a negative errno value otherwise and rte_errno is set.
1578 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1579 const struct rte_flow_item *item,
1580 const struct rte_flow_attr *attr,
1581 uint64_t item_flags,
1582 struct rte_flow_error *error)
1584 const struct rte_flow_item_port_id *spec = item->spec;
1585 const struct rte_flow_item_port_id *mask = item->mask;
1586 const struct rte_flow_item_port_id switch_mask = {
1589 struct mlx5_priv *esw_priv;
1590 struct mlx5_priv *dev_priv;
1593 if (!attr->transfer)
1594 return rte_flow_error_set(error, EINVAL,
1595 RTE_FLOW_ERROR_TYPE_ITEM,
1597 "match on port id is valid only"
1598 " when transfer flag is enabled");
1599 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1600 return rte_flow_error_set(error, ENOTSUP,
1601 RTE_FLOW_ERROR_TYPE_ITEM, item,
1602 "multiple source ports are not"
1605 mask = &switch_mask;
1606 if (mask->id != 0xffffffff)
1607 return rte_flow_error_set(error, ENOTSUP,
1608 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610 "no support for partial mask on"
1612 ret = mlx5_flow_item_acceptable
1613 (item, (const uint8_t *)mask,
1614 (const uint8_t *)&rte_flow_item_port_id_mask,
1615 sizeof(struct rte_flow_item_port_id),
1621 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623 return rte_flow_error_set(error, rte_errno,
1624 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1625 "failed to obtain E-Switch info for"
1627 dev_priv = mlx5_dev_to_eswitch_info(dev);
1629 return rte_flow_error_set(error, rte_errno,
1630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632 "failed to obtain E-Switch info");
1633 if (esw_priv->domain_id != dev_priv->domain_id)
1634 return rte_flow_error_set(error, EINVAL,
1635 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636 "cannot match on a port from a"
1637 " different E-Switch");
1642 * Validate GTP item.
1645 * Pointer to the rte_eth_dev structure.
1647 * Item specification.
1648 * @param[in] item_flags
1649 * Bit-fields that holds the items detected until now.
1651 * Pointer to error structure.
1654 * 0 on success, a negative errno value otherwise and rte_errno is set.
1657 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1658 const struct rte_flow_item *item,
1659 uint64_t item_flags,
1660 struct rte_flow_error *error)
1662 struct mlx5_priv *priv = dev->data->dev_private;
1663 const struct rte_flow_item_gtp *mask = item->mask;
1664 const struct rte_flow_item_gtp nic_mask = {
1666 .teid = RTE_BE32(0xffffffff),
1669 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1670 return rte_flow_error_set(error, ENOTSUP,
1671 RTE_FLOW_ERROR_TYPE_ITEM, item,
1672 "GTP support is not enabled");
1673 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1674 return rte_flow_error_set(error, ENOTSUP,
1675 RTE_FLOW_ERROR_TYPE_ITEM, item,
1676 "multiple tunnel layers not"
1678 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1679 return rte_flow_error_set(error, EINVAL,
1680 RTE_FLOW_ERROR_TYPE_ITEM, item,
1681 "no outer UDP layer found");
1683 mask = &rte_flow_item_gtp_mask;
1684 return mlx5_flow_item_acceptable
1685 (item, (const uint8_t *)mask,
1686 (const uint8_t *)&nic_mask,
1687 sizeof(struct rte_flow_item_gtp),
1692 * Validate the pop VLAN action.
1695 * Pointer to the rte_eth_dev structure.
1696 * @param[in] action_flags
1697 * Holds the actions detected until now.
1699 * Pointer to the pop vlan action.
1700 * @param[in] item_flags
1701 * The items found in this flow rule.
1703 * Pointer to flow attributes.
1705 * Pointer to error structure.
1708 * 0 on success, a negative errno value otherwise and rte_errno is set.
1711 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1712 uint64_t action_flags,
1713 const struct rte_flow_action *action,
1714 uint64_t item_flags,
1715 const struct rte_flow_attr *attr,
1716 struct rte_flow_error *error)
1718 const struct mlx5_priv *priv = dev->data->dev_private;
1722 if (!priv->sh->pop_vlan_action)
1723 return rte_flow_error_set(error, ENOTSUP,
1724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1726 "pop vlan action is not supported");
1728 return rte_flow_error_set(error, ENOTSUP,
1729 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1731 "pop vlan action not supported for "
1733 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1734 return rte_flow_error_set(error, ENOTSUP,
1735 RTE_FLOW_ERROR_TYPE_ACTION, action,
1736 "no support for multiple VLAN "
1738 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1739 return rte_flow_error_set(error, ENOTSUP,
1740 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1742 "cannot pop vlan without a "
1743 "match on (outer) vlan in the flow");
1744 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1745 return rte_flow_error_set(error, EINVAL,
1746 RTE_FLOW_ERROR_TYPE_ACTION, action,
1747 "wrong action order, port_id should "
1748 "be after pop VLAN action");
1749 if (!attr->transfer && priv->representor)
1750 return rte_flow_error_set(error, ENOTSUP,
1751 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1752 "pop vlan action for VF representor "
1753 "not supported on NIC table");
1758 * Get VLAN default info from vlan match info.
1761 * the list of item specifications.
1763 * pointer VLAN info to fill to.
1766 * 0 on success, a negative errno value otherwise and rte_errno is set.
1769 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1770 struct rte_vlan_hdr *vlan)
1772 const struct rte_flow_item_vlan nic_mask = {
1773 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1774 MLX5DV_FLOW_VLAN_VID_MASK),
1775 .inner_type = RTE_BE16(0xffff),
1780 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1781 int type = items->type;
1783 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1784 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1787 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1788 const struct rte_flow_item_vlan *vlan_m = items->mask;
1789 const struct rte_flow_item_vlan *vlan_v = items->spec;
1793 /* Only full match values are accepted */
1794 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1795 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1796 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1798 rte_be_to_cpu_16(vlan_v->tci &
1799 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1801 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1802 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1803 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1805 rte_be_to_cpu_16(vlan_v->tci &
1806 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1808 if (vlan_m->inner_type == nic_mask.inner_type)
1809 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1810 vlan_m->inner_type);
1815 * Validate the push VLAN action.
1818 * Pointer to the rte_eth_dev structure.
1819 * @param[in] action_flags
1820 * Holds the actions detected until now.
1821 * @param[in] item_flags
1822 * The items found in this flow rule.
1824 * Pointer to the action structure.
1826 * Pointer to flow attributes
1828 * Pointer to error structure.
1831 * 0 on success, a negative errno value otherwise and rte_errno is set.
1834 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1835 uint64_t action_flags,
1836 const struct rte_flow_item_vlan *vlan_m,
1837 const struct rte_flow_action *action,
1838 const struct rte_flow_attr *attr,
1839 struct rte_flow_error *error)
1841 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1842 const struct mlx5_priv *priv = dev->data->dev_private;
1844 if (!attr->transfer && attr->ingress)
1845 return rte_flow_error_set(error, ENOTSUP,
1846 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1848 "push VLAN action not supported for "
1850 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1851 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1852 return rte_flow_error_set(error, EINVAL,
1853 RTE_FLOW_ERROR_TYPE_ACTION, action,
1854 "invalid vlan ethertype");
1855 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1856 return rte_flow_error_set(error, ENOTSUP,
1857 RTE_FLOW_ERROR_TYPE_ACTION, action,
1858 "no support for multiple VLAN "
1860 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1861 return rte_flow_error_set(error, EINVAL,
1862 RTE_FLOW_ERROR_TYPE_ACTION, action,
1863 "wrong action order, port_id should "
1864 "be after push VLAN");
1865 if (!attr->transfer && priv->representor)
1866 return rte_flow_error_set(error, ENOTSUP,
1867 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1868 "push vlan action for VF representor "
1869 "not supported on NIC table");
1871 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1872 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1873 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1874 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1875 !(mlx5_flow_find_action
1876 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1877 return rte_flow_error_set(error, EINVAL,
1878 RTE_FLOW_ERROR_TYPE_ACTION, action,
1879 "not full match mask on VLAN PCP and "
1880 "there is no of_set_vlan_pcp action, "
1881 "push VLAN action cannot figure out "
1884 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1885 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1886 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1887 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1888 !(mlx5_flow_find_action
1889 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1890 return rte_flow_error_set(error, EINVAL,
1891 RTE_FLOW_ERROR_TYPE_ACTION, action,
1892 "not full match mask on VLAN VID and "
1893 "there is no of_set_vlan_vid action, "
1894 "push VLAN action cannot figure out "
1901 * Validate the set VLAN PCP.
1903 * @param[in] action_flags
1904 * Holds the actions detected until now.
1905 * @param[in] actions
1906 * Pointer to the list of actions remaining in the flow rule.
1908 * Pointer to error structure.
1911 * 0 on success, a negative errno value otherwise and rte_errno is set.
1914 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1915 const struct rte_flow_action actions[],
1916 struct rte_flow_error *error)
1918 const struct rte_flow_action *action = actions;
1919 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1921 if (conf->vlan_pcp > 7)
1922 return rte_flow_error_set(error, EINVAL,
1923 RTE_FLOW_ERROR_TYPE_ACTION, action,
1924 "VLAN PCP value is too big");
1925 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1926 return rte_flow_error_set(error, ENOTSUP,
1927 RTE_FLOW_ERROR_TYPE_ACTION, action,
1928 "set VLAN PCP action must follow "
1929 "the push VLAN action");
1930 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1931 return rte_flow_error_set(error, ENOTSUP,
1932 RTE_FLOW_ERROR_TYPE_ACTION, action,
1933 "Multiple VLAN PCP modification are "
1935 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1936 return rte_flow_error_set(error, EINVAL,
1937 RTE_FLOW_ERROR_TYPE_ACTION, action,
1938 "wrong action order, port_id should "
1939 "be after set VLAN PCP");
1944 * Validate the set VLAN VID.
1946 * @param[in] item_flags
1947 * Holds the items detected in this rule.
1948 * @param[in] action_flags
1949 * Holds the actions detected until now.
1950 * @param[in] actions
1951 * Pointer to the list of actions remaining in the flow rule.
1953 * Pointer to error structure.
1956 * 0 on success, a negative errno value otherwise and rte_errno is set.
1959 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1960 uint64_t action_flags,
1961 const struct rte_flow_action actions[],
1962 struct rte_flow_error *error)
1964 const struct rte_flow_action *action = actions;
1965 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1967 if (conf->vlan_vid > RTE_BE16(0xFFE))
1968 return rte_flow_error_set(error, EINVAL,
1969 RTE_FLOW_ERROR_TYPE_ACTION, action,
1970 "VLAN VID value is too big");
1971 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1972 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1973 return rte_flow_error_set(error, ENOTSUP,
1974 RTE_FLOW_ERROR_TYPE_ACTION, action,
1975 "set VLAN VID action must follow push"
1976 " VLAN action or match on VLAN item");
1977 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1978 return rte_flow_error_set(error, ENOTSUP,
1979 RTE_FLOW_ERROR_TYPE_ACTION, action,
1980 "Multiple VLAN VID modifications are "
1982 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1983 return rte_flow_error_set(error, EINVAL,
1984 RTE_FLOW_ERROR_TYPE_ACTION, action,
1985 "wrong action order, port_id should "
1986 "be after set VLAN VID");
1991 * Validate the FLAG action.
1994 * Pointer to the rte_eth_dev structure.
1995 * @param[in] action_flags
1996 * Holds the actions detected until now.
1998 * Pointer to flow attributes
2000 * Pointer to error structure.
2003 * 0 on success, a negative errno value otherwise and rte_errno is set.
2006 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2007 uint64_t action_flags,
2008 const struct rte_flow_attr *attr,
2009 struct rte_flow_error *error)
2011 struct mlx5_priv *priv = dev->data->dev_private;
2012 struct mlx5_dev_config *config = &priv->config;
2015 /* Fall back if no extended metadata register support. */
2016 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2017 return mlx5_flow_validate_action_flag(action_flags, attr,
2019 /* Extensive metadata mode requires registers. */
2020 if (!mlx5_flow_ext_mreg_supported(dev))
2021 return rte_flow_error_set(error, ENOTSUP,
2022 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2023 "no metadata registers "
2024 "to support flag action");
2025 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2028 "extended metadata register"
2029 " isn't available");
2030 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2033 MLX5_ASSERT(ret > 0);
2034 if (action_flags & MLX5_FLOW_ACTION_MARK)
2035 return rte_flow_error_set(error, EINVAL,
2036 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2037 "can't mark and flag in same flow");
2038 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2039 return rte_flow_error_set(error, EINVAL,
2040 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2042 " actions in same flow");
2047 * Validate MARK action.
2050 * Pointer to the rte_eth_dev structure.
2052 * Pointer to action.
2053 * @param[in] action_flags
2054 * Holds the actions detected until now.
2056 * Pointer to flow attributes
2058 * Pointer to error structure.
2061 * 0 on success, a negative errno value otherwise and rte_errno is set.
2064 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2065 const struct rte_flow_action *action,
2066 uint64_t action_flags,
2067 const struct rte_flow_attr *attr,
2068 struct rte_flow_error *error)
2070 struct mlx5_priv *priv = dev->data->dev_private;
2071 struct mlx5_dev_config *config = &priv->config;
2072 const struct rte_flow_action_mark *mark = action->conf;
2075 /* Fall back if no extended metadata register support. */
2076 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2077 return mlx5_flow_validate_action_mark(action, action_flags,
2079 /* Extensive metadata mode requires registers. */
2080 if (!mlx5_flow_ext_mreg_supported(dev))
2081 return rte_flow_error_set(error, ENOTSUP,
2082 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2083 "no metadata registers "
2084 "to support mark action");
2085 if (!priv->sh->dv_mark_mask)
2086 return rte_flow_error_set(error, ENOTSUP,
2087 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2088 "extended metadata register"
2089 " isn't available");
2090 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2093 MLX5_ASSERT(ret > 0);
2095 return rte_flow_error_set(error, EINVAL,
2096 RTE_FLOW_ERROR_TYPE_ACTION, action,
2097 "configuration cannot be null");
2098 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2099 return rte_flow_error_set(error, EINVAL,
2100 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2102 "mark id exceeds the limit");
2103 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2104 return rte_flow_error_set(error, EINVAL,
2105 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2106 "can't flag and mark in same flow");
2107 if (action_flags & MLX5_FLOW_ACTION_MARK)
2108 return rte_flow_error_set(error, EINVAL,
2109 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2110 "can't have 2 mark actions in same"
2116 * Validate SET_META action.
2119 * Pointer to the rte_eth_dev structure.
2121 * Pointer to the action structure.
2122 * @param[in] action_flags
2123 * Holds the actions detected until now.
2125 * Pointer to flow attributes
2127 * Pointer to error structure.
2130 * 0 on success, a negative errno value otherwise and rte_errno is set.
2133 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2134 const struct rte_flow_action *action,
2135 uint64_t action_flags __rte_unused,
2136 const struct rte_flow_attr *attr,
2137 struct rte_flow_error *error)
2139 const struct rte_flow_action_set_meta *conf;
2140 uint32_t nic_mask = UINT32_MAX;
2143 if (!mlx5_flow_ext_mreg_supported(dev))
2144 return rte_flow_error_set(error, ENOTSUP,
2145 RTE_FLOW_ERROR_TYPE_ACTION, action,
2146 "extended metadata register"
2147 " isn't supported");
2148 reg = flow_dv_get_metadata_reg(dev, attr, error);
2151 if (reg != REG_A && reg != REG_B) {
2152 struct mlx5_priv *priv = dev->data->dev_private;
2154 nic_mask = priv->sh->dv_meta_mask;
2156 if (!(action->conf))
2157 return rte_flow_error_set(error, EINVAL,
2158 RTE_FLOW_ERROR_TYPE_ACTION, action,
2159 "configuration cannot be null");
2160 conf = (const struct rte_flow_action_set_meta *)action->conf;
2162 return rte_flow_error_set(error, EINVAL,
2163 RTE_FLOW_ERROR_TYPE_ACTION, action,
2164 "zero mask doesn't have any effect");
2165 if (conf->mask & ~nic_mask)
2166 return rte_flow_error_set(error, EINVAL,
2167 RTE_FLOW_ERROR_TYPE_ACTION, action,
2168 "meta data must be within reg C0");
2173 * Validate SET_TAG action.
2176 * Pointer to the rte_eth_dev structure.
2178 * Pointer to the action structure.
2179 * @param[in] action_flags
2180 * Holds the actions detected until now.
2182 * Pointer to flow attributes
2184 * Pointer to error structure.
2187 * 0 on success, a negative errno value otherwise and rte_errno is set.
2190 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2191 const struct rte_flow_action *action,
2192 uint64_t action_flags,
2193 const struct rte_flow_attr *attr,
2194 struct rte_flow_error *error)
2196 const struct rte_flow_action_set_tag *conf;
2197 const uint64_t terminal_action_flags =
2198 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2199 MLX5_FLOW_ACTION_RSS;
2202 if (!mlx5_flow_ext_mreg_supported(dev))
2203 return rte_flow_error_set(error, ENOTSUP,
2204 RTE_FLOW_ERROR_TYPE_ACTION, action,
2205 "extensive metadata register"
2206 " isn't supported");
2207 if (!(action->conf))
2208 return rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ACTION, action,
2210 "configuration cannot be null");
2211 conf = (const struct rte_flow_action_set_tag *)action->conf;
2213 return rte_flow_error_set(error, EINVAL,
2214 RTE_FLOW_ERROR_TYPE_ACTION, action,
2215 "zero mask doesn't have any effect");
2216 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2219 if (!attr->transfer && attr->ingress &&
2220 (action_flags & terminal_action_flags))
2221 return rte_flow_error_set(error, EINVAL,
2222 RTE_FLOW_ERROR_TYPE_ACTION, action,
2223 "set_tag has no effect"
2224 " with terminal actions");
2229 * Validate count action.
2232 * Pointer to rte_eth_dev structure.
2234 * Pointer to error structure.
2237 * 0 on success, a negative errno value otherwise and rte_errno is set.
2240 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2241 struct rte_flow_error *error)
2243 struct mlx5_priv *priv = dev->data->dev_private;
2245 if (!priv->config.devx)
2247 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2251 return rte_flow_error_set
2253 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2255 "count action not supported");
2259 * Validate the L2 encap action.
2262 * Pointer to the rte_eth_dev structure.
2263 * @param[in] action_flags
2264 * Holds the actions detected until now.
2266 * Pointer to the action structure.
2268 * Pointer to flow attributes.
2270 * Pointer to error structure.
2273 * 0 on success, a negative errno value otherwise and rte_errno is set.
2276 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2277 uint64_t action_flags,
2278 const struct rte_flow_action *action,
2279 const struct rte_flow_attr *attr,
2280 struct rte_flow_error *error)
2282 const struct mlx5_priv *priv = dev->data->dev_private;
2284 if (!(action->conf))
2285 return rte_flow_error_set(error, EINVAL,
2286 RTE_FLOW_ERROR_TYPE_ACTION, action,
2287 "configuration cannot be null");
2288 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2289 return rte_flow_error_set(error, EINVAL,
2290 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2291 "can only have a single encap action "
2293 if (!attr->transfer && priv->representor)
2294 return rte_flow_error_set(error, ENOTSUP,
2295 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2296 "encap action for VF representor "
2297 "not supported on NIC table");
2302 * Validate a decap action.
2305 * Pointer to the rte_eth_dev structure.
2306 * @param[in] action_flags
2307 * Holds the actions detected until now.
2309 * Pointer to flow attributes
2311 * Pointer to error structure.
2314 * 0 on success, a negative errno value otherwise and rte_errno is set.
2317 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2318 uint64_t action_flags,
2319 const struct rte_flow_attr *attr,
2320 struct rte_flow_error *error)
2322 const struct mlx5_priv *priv = dev->data->dev_private;
2324 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2325 return rte_flow_error_set(error, ENOTSUP,
2326 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2328 MLX5_FLOW_ACTION_DECAP ? "can only "
2329 "have a single decap action" : "decap "
2330 "after encap is not supported");
2331 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2332 return rte_flow_error_set(error, EINVAL,
2333 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2334 "can't have decap action after"
2337 return rte_flow_error_set(error, ENOTSUP,
2338 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2340 "decap action not supported for "
2342 if (!attr->transfer && priv->representor)
2343 return rte_flow_error_set(error, ENOTSUP,
2344 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2345 "decap action for VF representor "
2346 "not supported on NIC table");
2350 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2353 * Validate the raw encap and decap actions.
2356 * Pointer to the rte_eth_dev structure.
2358 * Pointer to the decap action.
2360 * Pointer to the encap action.
2362 * Pointer to flow attributes
2363 * @param[in/out] action_flags
2364 * Holds the actions detected until now.
2365 * @param[out] actions_n
2366 * pointer to the number of actions counter.
2368 * Pointer to error structure.
2371 * 0 on success, a negative errno value otherwise and rte_errno is set.
2374 flow_dv_validate_action_raw_encap_decap
2375 (struct rte_eth_dev *dev,
2376 const struct rte_flow_action_raw_decap *decap,
2377 const struct rte_flow_action_raw_encap *encap,
2378 const struct rte_flow_attr *attr, uint64_t *action_flags,
2379 int *actions_n, struct rte_flow_error *error)
2381 const struct mlx5_priv *priv = dev->data->dev_private;
2384 if (encap && (!encap->size || !encap->data))
2385 return rte_flow_error_set(error, EINVAL,
2386 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387 "raw encap data cannot be empty");
2388 if (decap && encap) {
2389 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2390 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2393 else if (encap->size <=
2394 MLX5_ENCAPSULATION_DECISION_SIZE &&
2396 MLX5_ENCAPSULATION_DECISION_SIZE)
2399 else if (encap->size >
2400 MLX5_ENCAPSULATION_DECISION_SIZE &&
2402 MLX5_ENCAPSULATION_DECISION_SIZE)
2403 /* 2 L2 actions: encap and decap. */
2406 return rte_flow_error_set(error,
2408 RTE_FLOW_ERROR_TYPE_ACTION,
2409 NULL, "unsupported too small "
2410 "raw decap and too small raw "
2411 "encap combination");
2414 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2418 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2422 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2423 return rte_flow_error_set(error, ENOTSUP,
2424 RTE_FLOW_ERROR_TYPE_ACTION,
2426 "small raw encap size");
2427 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2428 return rte_flow_error_set(error, EINVAL,
2429 RTE_FLOW_ERROR_TYPE_ACTION,
2431 "more than one encap action");
2432 if (!attr->transfer && priv->representor)
2433 return rte_flow_error_set
2435 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2436 "encap action for VF representor "
2437 "not supported on NIC table");
2438 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2445 * Find existing encap/decap resource or create and register a new one.
2447 * @param[in, out] dev
2448 * Pointer to rte_eth_dev structure.
2449 * @param[in, out] resource
2450 * Pointer to encap/decap resource.
2451 * @parm[in, out] dev_flow
2452 * Pointer to the dev_flow.
2454 * pointer to error structure.
2457 * 0 on success otherwise -errno and errno is set.
2460 flow_dv_encap_decap_resource_register
2461 (struct rte_eth_dev *dev,
2462 struct mlx5_flow_dv_encap_decap_resource *resource,
2463 struct mlx5_flow *dev_flow,
2464 struct rte_flow_error *error)
2466 struct mlx5_priv *priv = dev->data->dev_private;
2467 struct mlx5_ibv_shared *sh = priv->sh;
2468 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2469 struct mlx5dv_dr_domain *domain;
2472 resource->flags = dev_flow->dv.group ? 0 : 1;
2473 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2474 domain = sh->fdb_domain;
2475 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2476 domain = sh->rx_domain;
2478 domain = sh->tx_domain;
2479 /* Lookup a matching resource from cache. */
2480 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2481 cache_resource, next) {
2482 if (resource->reformat_type == cache_resource->reformat_type &&
2483 resource->ft_type == cache_resource->ft_type &&
2484 resource->flags == cache_resource->flags &&
2485 resource->size == cache_resource->size &&
2486 !memcmp((const void *)resource->buf,
2487 (const void *)cache_resource->buf,
2489 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2490 (void *)cache_resource,
2491 rte_atomic32_read(&cache_resource->refcnt));
2492 rte_atomic32_inc(&cache_resource->refcnt);
2493 dev_flow->handle->dvh.encap_decap = idx;
2494 dev_flow->dv.encap_decap = cache_resource;
2498 /* Register new encap/decap resource. */
2499 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2500 &dev_flow->handle->dvh.encap_decap);
2501 if (!cache_resource)
2502 return rte_flow_error_set(error, ENOMEM,
2503 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2504 "cannot allocate resource memory");
2505 *cache_resource = *resource;
2506 cache_resource->verbs_action =
2507 mlx5_glue->dv_create_flow_action_packet_reformat
2508 (sh->ctx, cache_resource->reformat_type,
2509 cache_resource->ft_type, domain, cache_resource->flags,
2510 cache_resource->size,
2511 (cache_resource->size ? cache_resource->buf : NULL));
2512 if (!cache_resource->verbs_action) {
2513 rte_free(cache_resource);
2514 return rte_flow_error_set(error, ENOMEM,
2515 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2516 NULL, "cannot create action");
2518 rte_atomic32_init(&cache_resource->refcnt);
2519 rte_atomic32_inc(&cache_resource->refcnt);
2520 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2521 dev_flow->handle->dvh.encap_decap, cache_resource, next);
2522 dev_flow->dv.encap_decap = cache_resource;
2523 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2524 (void *)cache_resource,
2525 rte_atomic32_read(&cache_resource->refcnt));
2530 * Find existing table jump resource or create and register a new one.
2532 * @param[in, out] dev
2533 * Pointer to rte_eth_dev structure.
2534 * @param[in, out] tbl
2535 * Pointer to flow table resource.
2536 * @parm[in, out] dev_flow
2537 * Pointer to the dev_flow.
2539 * pointer to error structure.
2542 * 0 on success otherwise -errno and errno is set.
2545 flow_dv_jump_tbl_resource_register
2546 (struct rte_eth_dev *dev __rte_unused,
2547 struct mlx5_flow_tbl_resource *tbl,
2548 struct mlx5_flow *dev_flow,
2549 struct rte_flow_error *error)
2551 struct mlx5_flow_tbl_data_entry *tbl_data =
2552 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2556 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2558 tbl_data->jump.action =
2559 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2561 if (!tbl_data->jump.action)
2562 return rte_flow_error_set(error, ENOMEM,
2563 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2564 NULL, "cannot create jump action");
2565 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2566 (void *)&tbl_data->jump, cnt);
2568 /* old jump should not make the table ref++. */
2569 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2570 MLX5_ASSERT(tbl_data->jump.action);
2571 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2572 (void *)&tbl_data->jump, cnt);
2574 rte_atomic32_inc(&tbl_data->jump.refcnt);
2575 dev_flow->handle->dvh.jump = tbl_data->idx;
2576 dev_flow->dv.jump = &tbl_data->jump;
2581 * Find existing table port ID resource or create and register a new one.
2583 * @param[in, out] dev
2584 * Pointer to rte_eth_dev structure.
2585 * @param[in, out] resource
2586 * Pointer to port ID action resource.
2587 * @parm[in, out] dev_flow
2588 * Pointer to the dev_flow.
2590 * pointer to error structure.
2593 * 0 on success otherwise -errno and errno is set.
2596 flow_dv_port_id_action_resource_register
2597 (struct rte_eth_dev *dev,
2598 struct mlx5_flow_dv_port_id_action_resource *resource,
2599 struct mlx5_flow *dev_flow,
2600 struct rte_flow_error *error)
2602 struct mlx5_priv *priv = dev->data->dev_private;
2603 struct mlx5_ibv_shared *sh = priv->sh;
2604 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2607 /* Lookup a matching resource from cache. */
2608 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2609 idx, cache_resource, next) {
2610 if (resource->port_id == cache_resource->port_id) {
2611 DRV_LOG(DEBUG, "port id action resource resource %p: "
2613 (void *)cache_resource,
2614 rte_atomic32_read(&cache_resource->refcnt));
2615 rte_atomic32_inc(&cache_resource->refcnt);
2616 dev_flow->handle->dvh.port_id_action = idx;
2617 dev_flow->dv.port_id_action = cache_resource;
2621 /* Register new port id action resource. */
2622 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2623 &dev_flow->handle->dvh.port_id_action);
2624 if (!cache_resource)
2625 return rte_flow_error_set(error, ENOMEM,
2626 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2627 "cannot allocate resource memory");
2628 *cache_resource = *resource;
2630 * Depending on rdma_core version the glue routine calls
2631 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2632 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2634 cache_resource->action =
2635 mlx5_glue->dr_create_flow_action_dest_port
2636 (priv->sh->fdb_domain, resource->port_id);
2637 if (!cache_resource->action) {
2638 rte_free(cache_resource);
2639 return rte_flow_error_set(error, ENOMEM,
2640 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2641 NULL, "cannot create action");
2643 rte_atomic32_init(&cache_resource->refcnt);
2644 rte_atomic32_inc(&cache_resource->refcnt);
2645 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2646 dev_flow->handle->dvh.port_id_action, cache_resource,
2648 dev_flow->dv.port_id_action = cache_resource;
2649 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2650 (void *)cache_resource,
2651 rte_atomic32_read(&cache_resource->refcnt));
2656 * Find existing push vlan resource or create and register a new one.
2658 * @param [in, out] dev
2659 * Pointer to rte_eth_dev structure.
2660 * @param[in, out] resource
2661 * Pointer to port ID action resource.
2662 * @parm[in, out] dev_flow
2663 * Pointer to the dev_flow.
2665 * pointer to error structure.
2668 * 0 on success otherwise -errno and errno is set.
2671 flow_dv_push_vlan_action_resource_register
2672 (struct rte_eth_dev *dev,
2673 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2674 struct mlx5_flow *dev_flow,
2675 struct rte_flow_error *error)
2677 struct mlx5_priv *priv = dev->data->dev_private;
2678 struct mlx5_ibv_shared *sh = priv->sh;
2679 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2680 struct mlx5dv_dr_domain *domain;
2683 /* Lookup a matching resource from cache. */
2684 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2685 sh->push_vlan_action_list, idx, cache_resource, next) {
2686 if (resource->vlan_tag == cache_resource->vlan_tag &&
2687 resource->ft_type == cache_resource->ft_type) {
2688 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2690 (void *)cache_resource,
2691 rte_atomic32_read(&cache_resource->refcnt));
2692 rte_atomic32_inc(&cache_resource->refcnt);
2693 dev_flow->handle->dvh.push_vlan_res = idx;
2694 dev_flow->dv.push_vlan_res = cache_resource;
2698 /* Register new push_vlan action resource. */
2699 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2700 &dev_flow->handle->dvh.push_vlan_res);
2701 if (!cache_resource)
2702 return rte_flow_error_set(error, ENOMEM,
2703 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2704 "cannot allocate resource memory");
2705 *cache_resource = *resource;
2706 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2707 domain = sh->fdb_domain;
2708 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2709 domain = sh->rx_domain;
2711 domain = sh->tx_domain;
2712 cache_resource->action =
2713 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2714 resource->vlan_tag);
2715 if (!cache_resource->action) {
2716 rte_free(cache_resource);
2717 return rte_flow_error_set(error, ENOMEM,
2718 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2719 NULL, "cannot create action");
2721 rte_atomic32_init(&cache_resource->refcnt);
2722 rte_atomic32_inc(&cache_resource->refcnt);
2723 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2724 &sh->push_vlan_action_list,
2725 dev_flow->handle->dvh.push_vlan_res,
2726 cache_resource, next);
2727 dev_flow->dv.push_vlan_res = cache_resource;
2728 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2729 (void *)cache_resource,
2730 rte_atomic32_read(&cache_resource->refcnt));
2734 * Get the size of specific rte_flow_item_type
2736 * @param[in] item_type
2737 * Tested rte_flow_item_type.
2740 * sizeof struct item_type, 0 if void or irrelevant.
2743 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2747 switch (item_type) {
2748 case RTE_FLOW_ITEM_TYPE_ETH:
2749 retval = sizeof(struct rte_flow_item_eth);
2751 case RTE_FLOW_ITEM_TYPE_VLAN:
2752 retval = sizeof(struct rte_flow_item_vlan);
2754 case RTE_FLOW_ITEM_TYPE_IPV4:
2755 retval = sizeof(struct rte_flow_item_ipv4);
2757 case RTE_FLOW_ITEM_TYPE_IPV6:
2758 retval = sizeof(struct rte_flow_item_ipv6);
2760 case RTE_FLOW_ITEM_TYPE_UDP:
2761 retval = sizeof(struct rte_flow_item_udp);
2763 case RTE_FLOW_ITEM_TYPE_TCP:
2764 retval = sizeof(struct rte_flow_item_tcp);
2766 case RTE_FLOW_ITEM_TYPE_VXLAN:
2767 retval = sizeof(struct rte_flow_item_vxlan);
2769 case RTE_FLOW_ITEM_TYPE_GRE:
2770 retval = sizeof(struct rte_flow_item_gre);
2772 case RTE_FLOW_ITEM_TYPE_NVGRE:
2773 retval = sizeof(struct rte_flow_item_nvgre);
2775 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2776 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2778 case RTE_FLOW_ITEM_TYPE_MPLS:
2779 retval = sizeof(struct rte_flow_item_mpls);
2781 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2789 #define MLX5_ENCAP_IPV4_VERSION 0x40
2790 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2791 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2792 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2793 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2794 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2795 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2798 * Convert the encap action data from list of rte_flow_item to raw buffer
2801 * Pointer to rte_flow_item objects list.
2803 * Pointer to the output buffer.
2805 * Pointer to the output buffer size.
2807 * Pointer to the error structure.
2810 * 0 on success, a negative errno value otherwise and rte_errno is set.
2813 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2814 size_t *size, struct rte_flow_error *error)
2816 struct rte_ether_hdr *eth = NULL;
2817 struct rte_vlan_hdr *vlan = NULL;
2818 struct rte_ipv4_hdr *ipv4 = NULL;
2819 struct rte_ipv6_hdr *ipv6 = NULL;
2820 struct rte_udp_hdr *udp = NULL;
2821 struct rte_vxlan_hdr *vxlan = NULL;
2822 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2823 struct rte_gre_hdr *gre = NULL;
2825 size_t temp_size = 0;
2828 return rte_flow_error_set(error, EINVAL,
2829 RTE_FLOW_ERROR_TYPE_ACTION,
2830 NULL, "invalid empty data");
2831 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2832 len = flow_dv_get_item_len(items->type);
2833 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2834 return rte_flow_error_set(error, EINVAL,
2835 RTE_FLOW_ERROR_TYPE_ACTION,
2836 (void *)items->type,
2837 "items total size is too big"
2838 " for encap action");
2839 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2840 switch (items->type) {
2841 case RTE_FLOW_ITEM_TYPE_ETH:
2842 eth = (struct rte_ether_hdr *)&buf[temp_size];
2844 case RTE_FLOW_ITEM_TYPE_VLAN:
2845 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2847 return rte_flow_error_set(error, EINVAL,
2848 RTE_FLOW_ERROR_TYPE_ACTION,
2849 (void *)items->type,
2850 "eth header not found");
2851 if (!eth->ether_type)
2852 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2854 case RTE_FLOW_ITEM_TYPE_IPV4:
2855 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2857 return rte_flow_error_set(error, EINVAL,
2858 RTE_FLOW_ERROR_TYPE_ACTION,
2859 (void *)items->type,
2860 "neither eth nor vlan"
2862 if (vlan && !vlan->eth_proto)
2863 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2864 else if (eth && !eth->ether_type)
2865 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2866 if (!ipv4->version_ihl)
2867 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2868 MLX5_ENCAP_IPV4_IHL_MIN;
2869 if (!ipv4->time_to_live)
2870 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2872 case RTE_FLOW_ITEM_TYPE_IPV6:
2873 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2875 return rte_flow_error_set(error, EINVAL,
2876 RTE_FLOW_ERROR_TYPE_ACTION,
2877 (void *)items->type,
2878 "neither eth nor vlan"
2880 if (vlan && !vlan->eth_proto)
2881 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2882 else if (eth && !eth->ether_type)
2883 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2884 if (!ipv6->vtc_flow)
2886 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2887 if (!ipv6->hop_limits)
2888 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2890 case RTE_FLOW_ITEM_TYPE_UDP:
2891 udp = (struct rte_udp_hdr *)&buf[temp_size];
2893 return rte_flow_error_set(error, EINVAL,
2894 RTE_FLOW_ERROR_TYPE_ACTION,
2895 (void *)items->type,
2896 "ip header not found");
2897 if (ipv4 && !ipv4->next_proto_id)
2898 ipv4->next_proto_id = IPPROTO_UDP;
2899 else if (ipv6 && !ipv6->proto)
2900 ipv6->proto = IPPROTO_UDP;
2902 case RTE_FLOW_ITEM_TYPE_VXLAN:
2903 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2905 return rte_flow_error_set(error, EINVAL,
2906 RTE_FLOW_ERROR_TYPE_ACTION,
2907 (void *)items->type,
2908 "udp header not found");
2910 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2911 if (!vxlan->vx_flags)
2913 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2915 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2916 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2918 return rte_flow_error_set(error, EINVAL,
2919 RTE_FLOW_ERROR_TYPE_ACTION,
2920 (void *)items->type,
2921 "udp header not found");
2922 if (!vxlan_gpe->proto)
2923 return rte_flow_error_set(error, EINVAL,
2924 RTE_FLOW_ERROR_TYPE_ACTION,
2925 (void *)items->type,
2926 "next protocol not found");
2929 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2930 if (!vxlan_gpe->vx_flags)
2931 vxlan_gpe->vx_flags =
2932 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2934 case RTE_FLOW_ITEM_TYPE_GRE:
2935 case RTE_FLOW_ITEM_TYPE_NVGRE:
2936 gre = (struct rte_gre_hdr *)&buf[temp_size];
2938 return rte_flow_error_set(error, EINVAL,
2939 RTE_FLOW_ERROR_TYPE_ACTION,
2940 (void *)items->type,
2941 "next protocol not found");
2943 return rte_flow_error_set(error, EINVAL,
2944 RTE_FLOW_ERROR_TYPE_ACTION,
2945 (void *)items->type,
2946 "ip header not found");
2947 if (ipv4 && !ipv4->next_proto_id)
2948 ipv4->next_proto_id = IPPROTO_GRE;
2949 else if (ipv6 && !ipv6->proto)
2950 ipv6->proto = IPPROTO_GRE;
2952 case RTE_FLOW_ITEM_TYPE_VOID:
2955 return rte_flow_error_set(error, EINVAL,
2956 RTE_FLOW_ERROR_TYPE_ACTION,
2957 (void *)items->type,
2958 "unsupported item type");
2968 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2970 struct rte_ether_hdr *eth = NULL;
2971 struct rte_vlan_hdr *vlan = NULL;
2972 struct rte_ipv6_hdr *ipv6 = NULL;
2973 struct rte_udp_hdr *udp = NULL;
2977 eth = (struct rte_ether_hdr *)data;
2978 next_hdr = (char *)(eth + 1);
2979 proto = RTE_BE16(eth->ether_type);
2982 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2983 vlan = (struct rte_vlan_hdr *)next_hdr;
2984 proto = RTE_BE16(vlan->eth_proto);
2985 next_hdr += sizeof(struct rte_vlan_hdr);
2988 /* HW calculates IPv4 csum. no need to proceed */
2989 if (proto == RTE_ETHER_TYPE_IPV4)
2992 /* non IPv4/IPv6 header. not supported */
2993 if (proto != RTE_ETHER_TYPE_IPV6) {
2994 return rte_flow_error_set(error, ENOTSUP,
2995 RTE_FLOW_ERROR_TYPE_ACTION,
2996 NULL, "Cannot offload non IPv4/IPv6");
2999 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3001 /* ignore non UDP */
3002 if (ipv6->proto != IPPROTO_UDP)
3005 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3006 udp->dgram_cksum = 0;
3012 * Convert L2 encap action to DV specification.
3015 * Pointer to rte_eth_dev structure.
3017 * Pointer to action structure.
3018 * @param[in, out] dev_flow
3019 * Pointer to the mlx5_flow.
3020 * @param[in] transfer
3021 * Mark if the flow is E-Switch flow.
3023 * Pointer to the error structure.
3026 * 0 on success, a negative errno value otherwise and rte_errno is set.
3029 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3030 const struct rte_flow_action *action,
3031 struct mlx5_flow *dev_flow,
3033 struct rte_flow_error *error)
3035 const struct rte_flow_item *encap_data;
3036 const struct rte_flow_action_raw_encap *raw_encap_data;
3037 struct mlx5_flow_dv_encap_decap_resource res = {
3039 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3040 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3041 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3044 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3046 (const struct rte_flow_action_raw_encap *)action->conf;
3047 res.size = raw_encap_data->size;
3048 memcpy(res.buf, raw_encap_data->data, res.size);
3050 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3052 ((const struct rte_flow_action_vxlan_encap *)
3053 action->conf)->definition;
3056 ((const struct rte_flow_action_nvgre_encap *)
3057 action->conf)->definition;
3058 if (flow_dv_convert_encap_data(encap_data, res.buf,
3062 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3064 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3065 return rte_flow_error_set(error, EINVAL,
3066 RTE_FLOW_ERROR_TYPE_ACTION,
3067 NULL, "can't create L2 encap action");
3072 * Convert L2 decap action to DV specification.
3075 * Pointer to rte_eth_dev structure.
3076 * @param[in, out] dev_flow
3077 * Pointer to the mlx5_flow.
3078 * @param[in] transfer
3079 * Mark if the flow is E-Switch flow.
3081 * Pointer to the error structure.
3084 * 0 on success, a negative errno value otherwise and rte_errno is set.
3087 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3088 struct mlx5_flow *dev_flow,
3090 struct rte_flow_error *error)
3092 struct mlx5_flow_dv_encap_decap_resource res = {
3095 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3096 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3097 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3100 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3101 return rte_flow_error_set(error, EINVAL,
3102 RTE_FLOW_ERROR_TYPE_ACTION,
3103 NULL, "can't create L2 decap action");
3108 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3111 * Pointer to rte_eth_dev structure.
3113 * Pointer to action structure.
3114 * @param[in, out] dev_flow
3115 * Pointer to the mlx5_flow.
3117 * Pointer to the flow attributes.
3119 * Pointer to the error structure.
3122 * 0 on success, a negative errno value otherwise and rte_errno is set.
3125 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3126 const struct rte_flow_action *action,
3127 struct mlx5_flow *dev_flow,
3128 const struct rte_flow_attr *attr,
3129 struct rte_flow_error *error)
3131 const struct rte_flow_action_raw_encap *encap_data;
3132 struct mlx5_flow_dv_encap_decap_resource res;
3134 memset(&res, 0, sizeof(res));
3135 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3136 res.size = encap_data->size;
3137 memcpy(res.buf, encap_data->data, res.size);
3138 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3139 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3140 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3142 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3144 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3145 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3146 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3147 return rte_flow_error_set(error, EINVAL,
3148 RTE_FLOW_ERROR_TYPE_ACTION,
3149 NULL, "can't create encap action");
3154 * Create action push VLAN.
3157 * Pointer to rte_eth_dev structure.
3159 * Pointer to the flow attributes.
3161 * Pointer to the vlan to push to the Ethernet header.
3162 * @param[in, out] dev_flow
3163 * Pointer to the mlx5_flow.
3165 * Pointer to the error structure.
3168 * 0 on success, a negative errno value otherwise and rte_errno is set.
3171 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3172 const struct rte_flow_attr *attr,
3173 const struct rte_vlan_hdr *vlan,
3174 struct mlx5_flow *dev_flow,
3175 struct rte_flow_error *error)
3177 struct mlx5_flow_dv_push_vlan_action_resource res;
3179 memset(&res, 0, sizeof(res));
3181 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3184 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3186 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3187 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3188 return flow_dv_push_vlan_action_resource_register
3189 (dev, &res, dev_flow, error);
3193 * Validate the modify-header actions.
3195 * @param[in] action_flags
3196 * Holds the actions detected until now.
3198 * Pointer to the modify action.
3200 * Pointer to error structure.
3203 * 0 on success, a negative errno value otherwise and rte_errno is set.
3206 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3207 const struct rte_flow_action *action,
3208 struct rte_flow_error *error)
3210 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3211 return rte_flow_error_set(error, EINVAL,
3212 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3213 NULL, "action configuration not set");
3214 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3215 return rte_flow_error_set(error, EINVAL,
3216 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3217 "can't have encap action before"
3223 * Validate the modify-header MAC address actions.
3225 * @param[in] action_flags
3226 * Holds the actions detected until now.
3228 * Pointer to the modify action.
3229 * @param[in] item_flags
3230 * Holds the items detected.
3232 * Pointer to error structure.
3235 * 0 on success, a negative errno value otherwise and rte_errno is set.
3238 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3239 const struct rte_flow_action *action,
3240 const uint64_t item_flags,
3241 struct rte_flow_error *error)
3245 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3247 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3248 return rte_flow_error_set(error, EINVAL,
3249 RTE_FLOW_ERROR_TYPE_ACTION,
3251 "no L2 item in pattern");
3257 * Validate the modify-header IPv4 address actions.
3259 * @param[in] action_flags
3260 * Holds the actions detected until now.
3262 * Pointer to the modify action.
3263 * @param[in] item_flags
3264 * Holds the items detected.
3266 * Pointer to error structure.
3269 * 0 on success, a negative errno value otherwise and rte_errno is set.
3272 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3273 const struct rte_flow_action *action,
3274 const uint64_t item_flags,
3275 struct rte_flow_error *error)
3280 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3282 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3283 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3284 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3285 if (!(item_flags & layer))
3286 return rte_flow_error_set(error, EINVAL,
3287 RTE_FLOW_ERROR_TYPE_ACTION,
3289 "no ipv4 item in pattern");
3295 * Validate the modify-header IPv6 address actions.
3297 * @param[in] action_flags
3298 * Holds the actions detected until now.
3300 * Pointer to the modify action.
3301 * @param[in] item_flags
3302 * Holds the items detected.
3304 * Pointer to error structure.
3307 * 0 on success, a negative errno value otherwise and rte_errno is set.
3310 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3311 const struct rte_flow_action *action,
3312 const uint64_t item_flags,
3313 struct rte_flow_error *error)
3318 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3320 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3321 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3322 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3323 if (!(item_flags & layer))
3324 return rte_flow_error_set(error, EINVAL,
3325 RTE_FLOW_ERROR_TYPE_ACTION,
3327 "no ipv6 item in pattern");
3333 * Validate the modify-header TP actions.
3335 * @param[in] action_flags
3336 * Holds the actions detected until now.
3338 * Pointer to the modify action.
3339 * @param[in] item_flags
3340 * Holds the items detected.
3342 * Pointer to error structure.
3345 * 0 on success, a negative errno value otherwise and rte_errno is set.
3348 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3349 const struct rte_flow_action *action,
3350 const uint64_t item_flags,
3351 struct rte_flow_error *error)
3356 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3358 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3359 MLX5_FLOW_LAYER_INNER_L4 :
3360 MLX5_FLOW_LAYER_OUTER_L4;
3361 if (!(item_flags & layer))
3362 return rte_flow_error_set(error, EINVAL,
3363 RTE_FLOW_ERROR_TYPE_ACTION,
3364 NULL, "no transport layer "
3371 * Validate the modify-header actions of increment/decrement
3372 * TCP Sequence-number.
3374 * @param[in] action_flags
3375 * Holds the actions detected until now.
3377 * Pointer to the modify action.
3378 * @param[in] item_flags
3379 * Holds the items detected.
3381 * Pointer to error structure.
3384 * 0 on success, a negative errno value otherwise and rte_errno is set.
3387 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3388 const struct rte_flow_action *action,
3389 const uint64_t item_flags,
3390 struct rte_flow_error *error)
3395 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3397 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3398 MLX5_FLOW_LAYER_INNER_L4_TCP :
3399 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3400 if (!(item_flags & layer))
3401 return rte_flow_error_set(error, EINVAL,
3402 RTE_FLOW_ERROR_TYPE_ACTION,
3403 NULL, "no TCP item in"
3405 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3406 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3407 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3408 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3409 return rte_flow_error_set(error, EINVAL,
3410 RTE_FLOW_ERROR_TYPE_ACTION,
3412 "cannot decrease and increase"
3413 " TCP sequence number"
3414 " at the same time");
3420 * Validate the modify-header actions of increment/decrement
3421 * TCP Acknowledgment number.
3423 * @param[in] action_flags
3424 * Holds the actions detected until now.
3426 * Pointer to the modify action.
3427 * @param[in] item_flags
3428 * Holds the items detected.
3430 * Pointer to error structure.
3433 * 0 on success, a negative errno value otherwise and rte_errno is set.
3436 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3437 const struct rte_flow_action *action,
3438 const uint64_t item_flags,
3439 struct rte_flow_error *error)
3444 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3446 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3447 MLX5_FLOW_LAYER_INNER_L4_TCP :
3448 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3449 if (!(item_flags & layer))
3450 return rte_flow_error_set(error, EINVAL,
3451 RTE_FLOW_ERROR_TYPE_ACTION,
3452 NULL, "no TCP item in"
3454 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3455 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3456 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3457 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3458 return rte_flow_error_set(error, EINVAL,
3459 RTE_FLOW_ERROR_TYPE_ACTION,
3461 "cannot decrease and increase"
3462 " TCP acknowledgment number"
3463 " at the same time");
3469 * Validate the modify-header TTL actions.
3471 * @param[in] action_flags
3472 * Holds the actions detected until now.
3474 * Pointer to the modify action.
3475 * @param[in] item_flags
3476 * Holds the items detected.
3478 * Pointer to error structure.
3481 * 0 on success, a negative errno value otherwise and rte_errno is set.
3484 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3485 const struct rte_flow_action *action,
3486 const uint64_t item_flags,
3487 struct rte_flow_error *error)
3492 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3494 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3495 MLX5_FLOW_LAYER_INNER_L3 :
3496 MLX5_FLOW_LAYER_OUTER_L3;
3497 if (!(item_flags & layer))
3498 return rte_flow_error_set(error, EINVAL,
3499 RTE_FLOW_ERROR_TYPE_ACTION,
3501 "no IP protocol in pattern");
3507 * Validate jump action.
3510 * Pointer to the jump action.
3511 * @param[in] action_flags
3512 * Holds the actions detected until now.
3513 * @param[in] attributes
3514 * Pointer to flow attributes
3515 * @param[in] external
3516 * Action belongs to flow rule created by request external to PMD.
3518 * Pointer to error structure.
3521 * 0 on success, a negative errno value otherwise and rte_errno is set.
3524 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3525 uint64_t action_flags,
3526 const struct rte_flow_attr *attributes,
3527 bool external, struct rte_flow_error *error)
3529 uint32_t target_group, table;
3532 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3533 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3534 return rte_flow_error_set(error, EINVAL,
3535 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3536 "can't have 2 fate actions in"
3538 if (action_flags & MLX5_FLOW_ACTION_METER)
3539 return rte_flow_error_set(error, ENOTSUP,
3540 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3541 "jump with meter not support");
3543 return rte_flow_error_set(error, EINVAL,
3544 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3545 NULL, "action configuration not set");
3547 ((const struct rte_flow_action_jump *)action->conf)->group;
3548 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3549 true, &table, error);
3552 if (attributes->group == target_group)
3553 return rte_flow_error_set(error, EINVAL,
3554 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3555 "target group must be other than"
3556 " the current flow group");
3561 * Validate the port_id action.
3564 * Pointer to rte_eth_dev structure.
3565 * @param[in] action_flags
3566 * Bit-fields that holds the actions detected until now.
3568 * Port_id RTE action structure.
3570 * Attributes of flow that includes this action.
3572 * Pointer to error structure.
3575 * 0 on success, a negative errno value otherwise and rte_errno is set.
3578 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3579 uint64_t action_flags,
3580 const struct rte_flow_action *action,
3581 const struct rte_flow_attr *attr,
3582 struct rte_flow_error *error)
3584 const struct rte_flow_action_port_id *port_id;
3585 struct mlx5_priv *act_priv;
3586 struct mlx5_priv *dev_priv;
3589 if (!attr->transfer)
3590 return rte_flow_error_set(error, ENOTSUP,
3591 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3593 "port id action is valid in transfer"
3595 if (!action || !action->conf)
3596 return rte_flow_error_set(error, ENOTSUP,
3597 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3599 "port id action parameters must be"
3601 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3602 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3603 return rte_flow_error_set(error, EINVAL,
3604 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3605 "can have only one fate actions in"
3607 dev_priv = mlx5_dev_to_eswitch_info(dev);
3609 return rte_flow_error_set(error, rte_errno,
3610 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3612 "failed to obtain E-Switch info");
3613 port_id = action->conf;
3614 port = port_id->original ? dev->data->port_id : port_id->id;
3615 act_priv = mlx5_port_to_eswitch_info(port, false);
3617 return rte_flow_error_set
3619 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3620 "failed to obtain E-Switch port id for port");
3621 if (act_priv->domain_id != dev_priv->domain_id)
3622 return rte_flow_error_set
3624 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3625 "port does not belong to"
3626 " E-Switch being configured");
3631 * Get the maximum number of modify header actions.
3634 * Pointer to rte_eth_dev structure.
3636 * Flags bits to check if root level.
3639 * Max number of modify header actions device can support.
3642 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3645 * There's no way to directly query the max cap. Although it has to be
3646 * acquried by iterative trial, it is a safe assumption that more
3647 * actions are supported by FW if extensive metadata register is
3648 * supported. (Only in the root table)
3650 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3651 return MLX5_MAX_MODIFY_NUM;
3653 return mlx5_flow_ext_mreg_supported(dev) ?
3654 MLX5_ROOT_TBL_MODIFY_NUM :
3655 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3659 * Validate the meter action.
3662 * Pointer to rte_eth_dev structure.
3663 * @param[in] action_flags
3664 * Bit-fields that holds the actions detected until now.
3666 * Pointer to the meter action.
3668 * Attributes of flow that includes this action.
3670 * Pointer to error structure.
3673 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3676 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3677 uint64_t action_flags,
3678 const struct rte_flow_action *action,
3679 const struct rte_flow_attr *attr,
3680 struct rte_flow_error *error)
3682 struct mlx5_priv *priv = dev->data->dev_private;
3683 const struct rte_flow_action_meter *am = action->conf;
3684 struct mlx5_flow_meter *fm;
3687 return rte_flow_error_set(error, EINVAL,
3688 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3689 "meter action conf is NULL");
3691 if (action_flags & MLX5_FLOW_ACTION_METER)
3692 return rte_flow_error_set(error, ENOTSUP,
3693 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3694 "meter chaining not support");
3695 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3696 return rte_flow_error_set(error, ENOTSUP,
3697 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3698 "meter with jump not support");
3700 return rte_flow_error_set(error, ENOTSUP,
3701 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3703 "meter action not supported");
3704 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3706 return rte_flow_error_set(error, EINVAL,
3707 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3709 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3710 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3711 (!fm->attr.egress && !attr->egress && attr->ingress))))
3712 return rte_flow_error_set(error, EINVAL,
3713 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3714 "Flow attributes are either invalid "
3715 "or have a conflict with current "
3716 "meter attributes");
3721 * Validate the modify-header IPv4 DSCP actions.
3723 * @param[in] action_flags
3724 * Holds the actions detected until now.
3726 * Pointer to the modify action.
3727 * @param[in] item_flags
3728 * Holds the items detected.
3730 * Pointer to error structure.
3733 * 0 on success, a negative errno value otherwise and rte_errno is set.
3736 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3737 const struct rte_flow_action *action,
3738 const uint64_t item_flags,
3739 struct rte_flow_error *error)
3743 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3745 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3746 return rte_flow_error_set(error, EINVAL,
3747 RTE_FLOW_ERROR_TYPE_ACTION,
3749 "no ipv4 item in pattern");
3755 * Validate the modify-header IPv6 DSCP actions.
3757 * @param[in] action_flags
3758 * Holds the actions detected until now.
3760 * Pointer to the modify action.
3761 * @param[in] item_flags
3762 * Holds the items detected.
3764 * Pointer to error structure.
3767 * 0 on success, a negative errno value otherwise and rte_errno is set.
3770 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3771 const struct rte_flow_action *action,
3772 const uint64_t item_flags,
3773 struct rte_flow_error *error)
3777 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3779 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3780 return rte_flow_error_set(error, EINVAL,
3781 RTE_FLOW_ERROR_TYPE_ACTION,
3783 "no ipv6 item in pattern");
3789 * Find existing modify-header resource or create and register a new one.
3791 * @param dev[in, out]
3792 * Pointer to rte_eth_dev structure.
3793 * @param[in, out] resource
3794 * Pointer to modify-header resource.
3795 * @parm[in, out] dev_flow
3796 * Pointer to the dev_flow.
3798 * pointer to error structure.
3801 * 0 on success otherwise -errno and errno is set.
3804 flow_dv_modify_hdr_resource_register
3805 (struct rte_eth_dev *dev,
3806 struct mlx5_flow_dv_modify_hdr_resource *resource,
3807 struct mlx5_flow *dev_flow,
3808 struct rte_flow_error *error)
3810 struct mlx5_priv *priv = dev->data->dev_private;
3811 struct mlx5_ibv_shared *sh = priv->sh;
3812 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3813 struct mlx5dv_dr_domain *ns;
3814 uint32_t actions_len;
3816 resource->flags = dev_flow->dv.group ? 0 :
3817 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3818 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3820 return rte_flow_error_set(error, EOVERFLOW,
3821 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3822 "too many modify header items");
3823 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3824 ns = sh->fdb_domain;
3825 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3829 /* Lookup a matching resource from cache. */
3830 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3831 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3832 if (resource->ft_type == cache_resource->ft_type &&
3833 resource->actions_num == cache_resource->actions_num &&
3834 resource->flags == cache_resource->flags &&
3835 !memcmp((const void *)resource->actions,
3836 (const void *)cache_resource->actions,
3838 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3839 (void *)cache_resource,
3840 rte_atomic32_read(&cache_resource->refcnt));
3841 rte_atomic32_inc(&cache_resource->refcnt);
3842 dev_flow->handle->dvh.modify_hdr = cache_resource;
3846 /* Register new modify-header resource. */
3847 cache_resource = rte_calloc(__func__, 1,
3848 sizeof(*cache_resource) + actions_len, 0);
3849 if (!cache_resource)
3850 return rte_flow_error_set(error, ENOMEM,
3851 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3852 "cannot allocate resource memory");
3853 *cache_resource = *resource;
3854 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3855 cache_resource->verbs_action =
3856 mlx5_glue->dv_create_flow_action_modify_header
3857 (sh->ctx, cache_resource->ft_type, ns,
3858 cache_resource->flags, actions_len,
3859 (uint64_t *)cache_resource->actions);
3860 if (!cache_resource->verbs_action) {
3861 rte_free(cache_resource);
3862 return rte_flow_error_set(error, ENOMEM,
3863 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3864 NULL, "cannot create action");
3866 rte_atomic32_init(&cache_resource->refcnt);
3867 rte_atomic32_inc(&cache_resource->refcnt);
3868 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3869 dev_flow->handle->dvh.modify_hdr = cache_resource;
3870 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3871 (void *)cache_resource,
3872 rte_atomic32_read(&cache_resource->refcnt));
3877 * Get DV flow counter by index.
3880 * Pointer to the Ethernet device structure.
3882 * mlx5 flow counter index in the container.
3884 * mlx5 flow counter pool in the container,
3887 * Pointer to the counter, NULL otherwise.
3889 static struct mlx5_flow_counter *
3890 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3892 struct mlx5_flow_counter_pool **ppool)
3894 struct mlx5_priv *priv = dev->data->dev_private;
3895 struct mlx5_pools_container *cont;
3896 struct mlx5_flow_counter_pool *pool;
3900 if (idx >= MLX5_CNT_BATCH_OFFSET) {
3901 idx -= MLX5_CNT_BATCH_OFFSET;
3904 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3905 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3906 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3910 return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3914 * Get a pool by devx counter ID.
3917 * Pointer to the counter container.
3919 * The counter devx ID.
3922 * The counter pool pointer if exists, NULL otherwise,
3924 static struct mlx5_flow_counter_pool *
3925 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3928 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
3930 for (i = 0; i < n_valid; i++) {
3931 struct mlx5_flow_counter_pool *pool = cont->pools[i];
3932 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3933 MLX5_COUNTERS_PER_POOL;
3935 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
3937 * Move the pool to the head, as counter allocate
3938 * always gets the first pool in the container.
3940 if (pool != TAILQ_FIRST(&cont->pool_list)) {
3941 TAILQ_REMOVE(&cont->pool_list, pool, next);
3942 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
3951 * Allocate a new memory for the counter values wrapped by all the needed
3955 * Pointer to the Ethernet device structure.
3957 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3960 * The new memory management pointer on success, otherwise NULL and rte_errno
3963 static struct mlx5_counter_stats_mem_mng *
3964 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3966 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3967 (dev->data->dev_private))->sh;
3968 struct mlx5_devx_mkey_attr mkey_attr;
3969 struct mlx5_counter_stats_mem_mng *mem_mng;
3970 volatile struct flow_counter_stats *raw_data;
3971 int size = (sizeof(struct flow_counter_stats) *
3972 MLX5_COUNTERS_PER_POOL +
3973 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3974 sizeof(struct mlx5_counter_stats_mem_mng);
3975 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3982 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3983 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3984 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3985 IBV_ACCESS_LOCAL_WRITE);
3986 if (!mem_mng->umem) {
3991 mkey_attr.addr = (uintptr_t)mem;
3992 mkey_attr.size = size;
3993 mkey_attr.umem_id = mem_mng->umem->umem_id;
3994 mkey_attr.pd = sh->pdn;
3995 mkey_attr.log_entity_size = 0;
3996 mkey_attr.pg_access = 0;
3997 mkey_attr.klm_array = NULL;
3998 mkey_attr.klm_num = 0;
3999 mkey_attr.relaxed_ordering = 1;
4000 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4002 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4007 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4008 raw_data = (volatile struct flow_counter_stats *)mem;
4009 for (i = 0; i < raws_n; ++i) {
4010 mem_mng->raws[i].mem_mng = mem_mng;
4011 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4013 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4018 * Resize a counter container.
4021 * Pointer to the Ethernet device structure.
4023 * Whether the pool is for counter that was allocated by batch command.
4026 * The new container pointer on success, otherwise NULL and rte_errno is set.
4028 static struct mlx5_pools_container *
4029 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4031 struct mlx5_priv *priv = dev->data->dev_private;
4032 struct mlx5_pools_container *cont =
4033 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4034 struct mlx5_pools_container *new_cont =
4035 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4036 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4037 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4038 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4041 /* Fallback mode has no background thread. Skip the check. */
4042 if (!priv->counter_fallback &&
4043 cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4044 /* The last resize still hasn't detected by the host thread. */
4048 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4049 if (!new_cont->pools) {
4054 memcpy(new_cont->pools, cont->pools, cont->n *
4055 sizeof(struct mlx5_flow_counter_pool *));
4057 * Fallback mode query the counter directly, no background query
4058 * resources are needed.
4060 if (!priv->counter_fallback) {
4061 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4062 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4064 rte_free(new_cont->pools);
4067 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4068 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4070 MLX5_CNT_CONTAINER_RESIZE +
4074 * Release the old container pools directly as no background
4075 * thread helps that.
4077 rte_free(cont->pools);
4079 new_cont->n = resize;
4080 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4081 TAILQ_INIT(&new_cont->pool_list);
4082 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4083 new_cont->init_mem_mng = mem_mng;
4085 /* Flip the master container. */
4086 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4091 * Query a devx flow counter.
4094 * Pointer to the Ethernet device structure.
4096 * Index to the flow counter.
4098 * The statistics value of packets.
4100 * The statistics value of bytes.
4103 * 0 on success, otherwise a negative errno value and rte_errno is set.
4106 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4109 struct mlx5_priv *priv = dev->data->dev_private;
4110 struct mlx5_flow_counter_pool *pool = NULL;
4111 struct mlx5_flow_counter *cnt;
4112 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4115 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4117 if (counter < MLX5_CNT_BATCH_OFFSET) {
4118 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4119 if (priv->counter_fallback)
4120 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4121 0, pkts, bytes, 0, NULL, NULL, 0);
4124 rte_spinlock_lock(&pool->sl);
4126 * The single counters allocation may allocate smaller ID than the
4127 * current allocated in parallel to the host reading.
4128 * In this case the new counter values must be reported as 0.
4130 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4134 offset = cnt - &pool->counters_raw[0];
4135 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4136 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4138 rte_spinlock_unlock(&pool->sl);
4143 * Create and initialize a new counter pool.
4146 * Pointer to the Ethernet device structure.
4148 * The devX counter handle.
4150 * Whether the pool is for counter that was allocated by batch command.
4151 * @param[in/out] cont_cur
4152 * Pointer to the container pointer, it will be update in pool resize.
4155 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4157 static struct mlx5_pools_container *
4158 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4161 struct mlx5_priv *priv = dev->data->dev_private;
4162 struct mlx5_flow_counter_pool *pool;
4163 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4165 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4168 if (cont->n == n_valid) {
4169 cont = flow_dv_container_resize(dev, batch);
4173 size = sizeof(*pool);
4175 size += MLX5_COUNTERS_PER_POOL *
4176 sizeof(struct mlx5_flow_counter_ext);
4177 pool = rte_calloc(__func__, 1, size, 0);
4182 pool->min_dcs = dcs;
4183 if (!priv->counter_fallback)
4184 pool->raw = cont->init_mem_mng->raws + n_valid %
4185 MLX5_CNT_CONTAINER_RESIZE;
4186 pool->raw_hw = NULL;
4187 rte_spinlock_init(&pool->sl);
4189 * The generation of the new allocated counters in this pool is 0, 2 in
4190 * the pool generation makes all the counters valid for allocation.
4191 * The start and end query generation protect the counters be released
4192 * between the query and update gap period will not be reallocated
4193 * without the last query finished and stats updated to the memory.
4195 rte_atomic64_set(&pool->start_query_gen, 0x2);
4197 * There's no background query thread for fallback mode, set the
4198 * end_query_gen to the maximum value since no need to wait for
4199 * statistics update.
4201 rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4203 TAILQ_INIT(&pool->counters);
4204 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4205 pool->index = n_valid;
4206 cont->pools[n_valid] = pool;
4207 /* Pool initialization must be updated before host thread access. */
4209 rte_atomic16_add(&cont->n_valid, 1);
4214 * Prepare a new counter and/or a new counter pool.
4217 * Pointer to the Ethernet device structure.
4218 * @param[out] cnt_free
4219 * Where to put the pointer of a new counter.
4221 * Whether the pool is for counter that was allocated by batch command.
4224 * The counter container pointer and @p cnt_free is set on success,
4225 * NULL otherwise and rte_errno is set.
4227 static struct mlx5_pools_container *
4228 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4229 struct mlx5_flow_counter **cnt_free,
4232 struct mlx5_priv *priv = dev->data->dev_private;
4233 struct mlx5_pools_container *cont;
4234 struct mlx5_flow_counter_pool *pool;
4235 struct mlx5_devx_obj *dcs = NULL;
4236 struct mlx5_flow_counter *cnt;
4239 cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4241 /* bulk_bitmap must be 0 for single counter allocation. */
4242 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4245 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4247 cont = flow_dv_pool_create(dev, dcs, batch);
4249 mlx5_devx_cmd_destroy(dcs);
4252 pool = TAILQ_FIRST(&cont->pool_list);
4253 } else if (dcs->id < pool->min_dcs->id) {
4254 rte_atomic64_set(&pool->a64_dcs,
4255 (int64_t)(uintptr_t)dcs);
4257 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4258 cnt = &pool->counters_raw[i];
4259 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4260 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4264 /* bulk_bitmap is in 128 counters units. */
4265 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4266 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4268 rte_errno = ENODATA;
4271 cont = flow_dv_pool_create(dev, dcs, batch);
4273 mlx5_devx_cmd_destroy(dcs);
4276 pool = TAILQ_FIRST(&cont->pool_list);
4277 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4278 cnt = &pool->counters_raw[i];
4279 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4281 *cnt_free = &pool->counters_raw[0];
4286 * Search for existed shared counter.
4289 * Pointer to the relevant counter pool container.
4291 * The shared counter ID to search.
4293 * mlx5 flow counter pool in the container,
4296 * NULL if not existed, otherwise pointer to the shared extend counter.
4298 static struct mlx5_flow_counter_ext *
4299 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4300 struct mlx5_flow_counter_pool **ppool)
4302 static struct mlx5_flow_counter_ext *cnt;
4303 struct mlx5_flow_counter_pool *pool;
4305 uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4307 for (i = 0; i < n_valid; i++) {
4308 pool = cont->pools[i];
4309 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4310 cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4311 if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4313 *ppool = cont->pools[i];
4322 * Allocate a flow counter.
4325 * Pointer to the Ethernet device structure.
4327 * Indicate if this counter is shared with other flows.
4329 * Counter identifier.
4331 * Counter flow group.
4334 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4337 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4340 struct mlx5_priv *priv = dev->data->dev_private;
4341 struct mlx5_flow_counter_pool *pool = NULL;
4342 struct mlx5_flow_counter *cnt_free = NULL;
4343 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4345 * Currently group 0 flow counter cannot be assigned to a flow if it is
4346 * not the first one in the batch counter allocation, so it is better
4347 * to allocate counters one by one for these flows in a separate
4349 * A counter can be shared between different groups so need to take
4350 * shared counters from the single container.
4352 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4353 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4357 if (!priv->config.devx) {
4358 rte_errno = ENOTSUP;
4362 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4364 if (cnt_ext->ref_cnt + 1 == 0) {
4369 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4370 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4375 /* Pools which has a free counters are in the start. */
4376 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4378 * The free counter reset values must be updated between the
4379 * counter release to the counter allocation, so, at least one
4380 * query must be done in this time. ensure it by saving the
4381 * query generation in the release time.
4382 * The free list is sorted according to the generation - so if
4383 * the first one is not updated, all the others are not
4386 cnt_free = TAILQ_FIRST(&pool->counters);
4387 if (cnt_free && cnt_free->query_gen <
4388 rte_atomic64_read(&pool->end_query_gen))
4393 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4396 pool = TAILQ_FIRST(&cont->pool_list);
4399 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4400 /* Create a DV counter action only in the first time usage. */
4401 if (!cnt_free->action) {
4403 struct mlx5_devx_obj *dcs;
4406 offset = cnt_free - &pool->counters_raw[0];
4407 dcs = pool->min_dcs;
4412 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4414 if (!cnt_free->action) {
4419 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4420 (cnt_free - pool->counters_raw));
4421 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4422 /* Update the counter reset values. */
4423 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4427 cnt_ext->shared = shared;
4428 cnt_ext->ref_cnt = 1;
4431 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4432 /* Start the asynchronous batch query by the host thread. */
4433 mlx5_set_query_alarm(priv->sh);
4434 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4435 if (TAILQ_EMPTY(&pool->counters)) {
4436 /* Move the pool to the end of the container pool list. */
4437 TAILQ_REMOVE(&cont->pool_list, pool, next);
4438 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4444 * Release a flow counter.
4447 * Pointer to the Ethernet device structure.
4448 * @param[in] counter
4449 * Index to the counter handler.
4452 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4454 struct mlx5_flow_counter_pool *pool = NULL;
4455 struct mlx5_flow_counter *cnt;
4456 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4460 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4462 if (counter < MLX5_CNT_BATCH_OFFSET) {
4463 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4464 if (cnt_ext && --cnt_ext->ref_cnt)
4467 /* Put the counter in the end - the last updated one. */
4468 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4470 * Counters released between query trigger and handler need
4471 * to wait the next round of query. Since the packets arrive
4472 * in the gap period will not be taken into account to the
4475 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4479 * Verify the @p attributes will be correctly understood by the NIC and store
4480 * them in the @p flow if everything is correct.
4483 * Pointer to dev struct.
4484 * @param[in] attributes
4485 * Pointer to flow attributes
4486 * @param[in] external
4487 * This flow rule is created by request external to PMD.
4489 * Pointer to error structure.
4492 * 0 on success, a negative errno value otherwise and rte_errno is set.
4495 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4496 const struct rte_flow_attr *attributes,
4497 bool external __rte_unused,
4498 struct rte_flow_error *error)
4500 struct mlx5_priv *priv = dev->data->dev_private;
4501 uint32_t priority_max = priv->config.flow_prio - 1;
4503 #ifndef HAVE_MLX5DV_DR
4504 if (attributes->group)
4505 return rte_flow_error_set(error, ENOTSUP,
4506 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4508 "groups are not supported");
4513 ret = mlx5_flow_group_to_table(attributes, external,
4514 attributes->group, !!priv->fdb_def_rule,
4519 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4520 attributes->priority >= priority_max)
4521 return rte_flow_error_set(error, ENOTSUP,
4522 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4524 "priority out of range");
4525 if (attributes->transfer) {
4526 if (!priv->config.dv_esw_en)
4527 return rte_flow_error_set
4529 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4530 "E-Switch dr is not supported");
4531 if (!(priv->representor || priv->master))
4532 return rte_flow_error_set
4533 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4534 NULL, "E-Switch configuration can only be"
4535 " done by a master or a representor device");
4536 if (attributes->egress)
4537 return rte_flow_error_set
4539 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4540 "egress is not supported");
4542 if (!(attributes->egress ^ attributes->ingress))
4543 return rte_flow_error_set(error, ENOTSUP,
4544 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4545 "must specify exactly one of "
4546 "ingress or egress");
4551 * Internal validation function. For validating both actions and items.
4554 * Pointer to the rte_eth_dev structure.
4556 * Pointer to the flow attributes.
4558 * Pointer to the list of items.
4559 * @param[in] actions
4560 * Pointer to the list of actions.
4561 * @param[in] external
4562 * This flow rule is created by request external to PMD.
4564 * Pointer to the error structure.
4567 * 0 on success, a negative errno value otherwise and rte_errno is set.
4570 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4571 const struct rte_flow_item items[],
4572 const struct rte_flow_action actions[],
4573 bool external, struct rte_flow_error *error)
4576 uint64_t action_flags = 0;
4577 uint64_t item_flags = 0;
4578 uint64_t last_item = 0;
4579 uint8_t next_protocol = 0xff;
4580 uint16_t ether_type = 0;
4582 uint8_t item_ipv6_proto = 0;
4583 const struct rte_flow_item *gre_item = NULL;
4584 const struct rte_flow_action_raw_decap *decap;
4585 const struct rte_flow_action_raw_encap *encap;
4586 const struct rte_flow_action_rss *rss;
4587 const struct rte_flow_item_tcp nic_tcp_mask = {
4590 .src_port = RTE_BE16(UINT16_MAX),
4591 .dst_port = RTE_BE16(UINT16_MAX),
4594 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4596 .src_addr = RTE_BE32(0xffffffff),
4597 .dst_addr = RTE_BE32(0xffffffff),
4598 .type_of_service = 0xff,
4599 .next_proto_id = 0xff,
4600 .time_to_live = 0xff,
4603 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4606 "\xff\xff\xff\xff\xff\xff\xff\xff"
4607 "\xff\xff\xff\xff\xff\xff\xff\xff",
4609 "\xff\xff\xff\xff\xff\xff\xff\xff"
4610 "\xff\xff\xff\xff\xff\xff\xff\xff",
4611 .vtc_flow = RTE_BE32(0xffffffff),
4616 struct mlx5_priv *priv = dev->data->dev_private;
4617 struct mlx5_dev_config *dev_conf = &priv->config;
4618 uint16_t queue_index = 0xFFFF;
4619 const struct rte_flow_item_vlan *vlan_m = NULL;
4623 ret = flow_dv_validate_attributes(dev, attr, external, error);
4626 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4627 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4628 int type = items->type;
4631 case RTE_FLOW_ITEM_TYPE_VOID:
4633 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4634 ret = flow_dv_validate_item_port_id
4635 (dev, items, attr, item_flags, error);
4638 last_item = MLX5_FLOW_ITEM_PORT_ID;
4640 case RTE_FLOW_ITEM_TYPE_ETH:
4641 ret = mlx5_flow_validate_item_eth(items, item_flags,
4645 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4646 MLX5_FLOW_LAYER_OUTER_L2;
4647 if (items->mask != NULL && items->spec != NULL) {
4649 ((const struct rte_flow_item_eth *)
4652 ((const struct rte_flow_item_eth *)
4654 ether_type = rte_be_to_cpu_16(ether_type);
4659 case RTE_FLOW_ITEM_TYPE_VLAN:
4660 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4664 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4665 MLX5_FLOW_LAYER_OUTER_VLAN;
4666 if (items->mask != NULL && items->spec != NULL) {
4668 ((const struct rte_flow_item_vlan *)
4669 items->spec)->inner_type;
4671 ((const struct rte_flow_item_vlan *)
4672 items->mask)->inner_type;
4673 ether_type = rte_be_to_cpu_16(ether_type);
4677 /* Store outer VLAN mask for of_push_vlan action. */
4679 vlan_m = items->mask;
4681 case RTE_FLOW_ITEM_TYPE_IPV4:
4682 mlx5_flow_tunnel_ip_check(items, next_protocol,
4683 &item_flags, &tunnel);
4684 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4691 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4692 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4693 if (items->mask != NULL &&
4694 ((const struct rte_flow_item_ipv4 *)
4695 items->mask)->hdr.next_proto_id) {
4697 ((const struct rte_flow_item_ipv4 *)
4698 (items->spec))->hdr.next_proto_id;
4700 ((const struct rte_flow_item_ipv4 *)
4701 (items->mask))->hdr.next_proto_id;
4703 /* Reset for inner layer. */
4704 next_protocol = 0xff;
4707 case RTE_FLOW_ITEM_TYPE_IPV6:
4708 mlx5_flow_tunnel_ip_check(items, next_protocol,
4709 &item_flags, &tunnel);
4710 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4717 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4718 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4719 if (items->mask != NULL &&
4720 ((const struct rte_flow_item_ipv6 *)
4721 items->mask)->hdr.proto) {
4723 ((const struct rte_flow_item_ipv6 *)
4724 items->spec)->hdr.proto;
4726 ((const struct rte_flow_item_ipv6 *)
4727 items->spec)->hdr.proto;
4729 ((const struct rte_flow_item_ipv6 *)
4730 items->mask)->hdr.proto;
4732 /* Reset for inner layer. */
4733 next_protocol = 0xff;
4736 case RTE_FLOW_ITEM_TYPE_TCP:
4737 ret = mlx5_flow_validate_item_tcp
4744 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4745 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4747 case RTE_FLOW_ITEM_TYPE_UDP:
4748 ret = mlx5_flow_validate_item_udp(items, item_flags,
4753 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4754 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4756 case RTE_FLOW_ITEM_TYPE_GRE:
4757 ret = mlx5_flow_validate_item_gre(items, item_flags,
4758 next_protocol, error);
4762 last_item = MLX5_FLOW_LAYER_GRE;
4764 case RTE_FLOW_ITEM_TYPE_NVGRE:
4765 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4770 last_item = MLX5_FLOW_LAYER_NVGRE;
4772 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4773 ret = mlx5_flow_validate_item_gre_key
4774 (items, item_flags, gre_item, error);
4777 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4779 case RTE_FLOW_ITEM_TYPE_VXLAN:
4780 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4784 last_item = MLX5_FLOW_LAYER_VXLAN;
4786 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4787 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4792 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4794 case RTE_FLOW_ITEM_TYPE_GENEVE:
4795 ret = mlx5_flow_validate_item_geneve(items,
4800 last_item = MLX5_FLOW_LAYER_GENEVE;
4802 case RTE_FLOW_ITEM_TYPE_MPLS:
4803 ret = mlx5_flow_validate_item_mpls(dev, items,
4808 last_item = MLX5_FLOW_LAYER_MPLS;
4811 case RTE_FLOW_ITEM_TYPE_MARK:
4812 ret = flow_dv_validate_item_mark(dev, items, attr,
4816 last_item = MLX5_FLOW_ITEM_MARK;
4818 case RTE_FLOW_ITEM_TYPE_META:
4819 ret = flow_dv_validate_item_meta(dev, items, attr,
4823 last_item = MLX5_FLOW_ITEM_METADATA;
4825 case RTE_FLOW_ITEM_TYPE_ICMP:
4826 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4831 last_item = MLX5_FLOW_LAYER_ICMP;
4833 case RTE_FLOW_ITEM_TYPE_ICMP6:
4834 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4839 item_ipv6_proto = IPPROTO_ICMPV6;
4840 last_item = MLX5_FLOW_LAYER_ICMP6;
4842 case RTE_FLOW_ITEM_TYPE_TAG:
4843 ret = flow_dv_validate_item_tag(dev, items,
4847 last_item = MLX5_FLOW_ITEM_TAG;
4849 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4850 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4852 case RTE_FLOW_ITEM_TYPE_GTP:
4853 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4857 last_item = MLX5_FLOW_LAYER_GTP;
4860 return rte_flow_error_set(error, ENOTSUP,
4861 RTE_FLOW_ERROR_TYPE_ITEM,
4862 NULL, "item not supported");
4864 item_flags |= last_item;
4866 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4867 int type = actions->type;
4868 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4869 return rte_flow_error_set(error, ENOTSUP,
4870 RTE_FLOW_ERROR_TYPE_ACTION,
4871 actions, "too many actions");
4873 case RTE_FLOW_ACTION_TYPE_VOID:
4875 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4876 ret = flow_dv_validate_action_port_id(dev,
4883 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4886 case RTE_FLOW_ACTION_TYPE_FLAG:
4887 ret = flow_dv_validate_action_flag(dev, action_flags,
4891 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4892 /* Count all modify-header actions as one. */
4893 if (!(action_flags &
4894 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4896 action_flags |= MLX5_FLOW_ACTION_FLAG |
4897 MLX5_FLOW_ACTION_MARK_EXT;
4899 action_flags |= MLX5_FLOW_ACTION_FLAG;
4903 case RTE_FLOW_ACTION_TYPE_MARK:
4904 ret = flow_dv_validate_action_mark(dev, actions,
4909 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4910 /* Count all modify-header actions as one. */
4911 if (!(action_flags &
4912 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4914 action_flags |= MLX5_FLOW_ACTION_MARK |
4915 MLX5_FLOW_ACTION_MARK_EXT;
4917 action_flags |= MLX5_FLOW_ACTION_MARK;
4921 case RTE_FLOW_ACTION_TYPE_SET_META:
4922 ret = flow_dv_validate_action_set_meta(dev, actions,
4927 /* Count all modify-header actions as one action. */
4928 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4930 action_flags |= MLX5_FLOW_ACTION_SET_META;
4932 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4933 ret = flow_dv_validate_action_set_tag(dev, actions,
4938 /* Count all modify-header actions as one action. */
4939 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4941 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4943 case RTE_FLOW_ACTION_TYPE_DROP:
4944 ret = mlx5_flow_validate_action_drop(action_flags,
4948 action_flags |= MLX5_FLOW_ACTION_DROP;
4951 case RTE_FLOW_ACTION_TYPE_QUEUE:
4952 ret = mlx5_flow_validate_action_queue(actions,
4957 queue_index = ((const struct rte_flow_action_queue *)
4958 (actions->conf))->index;
4959 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4962 case RTE_FLOW_ACTION_TYPE_RSS:
4963 rss = actions->conf;
4964 ret = mlx5_flow_validate_action_rss(actions,
4970 if (rss != NULL && rss->queue_num)
4971 queue_index = rss->queue[0];
4972 action_flags |= MLX5_FLOW_ACTION_RSS;
4975 case RTE_FLOW_ACTION_TYPE_COUNT:
4976 ret = flow_dv_validate_action_count(dev, error);
4979 action_flags |= MLX5_FLOW_ACTION_COUNT;
4982 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4983 if (flow_dv_validate_action_pop_vlan(dev,
4989 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4992 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4993 ret = flow_dv_validate_action_push_vlan(dev,
5000 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5003 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5004 ret = flow_dv_validate_action_set_vlan_pcp
5005 (action_flags, actions, error);
5008 /* Count PCP with push_vlan command. */
5009 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5011 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5012 ret = flow_dv_validate_action_set_vlan_vid
5013 (item_flags, action_flags,
5017 /* Count VID with push_vlan command. */
5018 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5020 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5021 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5022 ret = flow_dv_validate_action_l2_encap(dev,
5028 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5031 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5032 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5033 ret = flow_dv_validate_action_decap(dev, action_flags,
5037 action_flags |= MLX5_FLOW_ACTION_DECAP;
5040 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5041 ret = flow_dv_validate_action_raw_encap_decap
5042 (dev, NULL, actions->conf, attr, &action_flags,
5047 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5048 decap = actions->conf;
5049 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5051 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5055 encap = actions->conf;
5057 ret = flow_dv_validate_action_raw_encap_decap
5059 decap ? decap : &empty_decap, encap,
5060 attr, &action_flags, &actions_n,
5065 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5066 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5067 ret = flow_dv_validate_action_modify_mac(action_flags,
5073 /* Count all modify-header actions as one action. */
5074 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5076 action_flags |= actions->type ==
5077 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5078 MLX5_FLOW_ACTION_SET_MAC_SRC :
5079 MLX5_FLOW_ACTION_SET_MAC_DST;
5082 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5083 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5084 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5090 /* Count all modify-header actions as one action. */
5091 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5093 action_flags |= actions->type ==
5094 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5095 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5096 MLX5_FLOW_ACTION_SET_IPV4_DST;
5098 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5099 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5100 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5106 if (item_ipv6_proto == IPPROTO_ICMPV6)
5107 return rte_flow_error_set(error, ENOTSUP,
5108 RTE_FLOW_ERROR_TYPE_ACTION,
5110 "Can't change header "
5111 "with ICMPv6 proto");
5112 /* Count all modify-header actions as one action. */
5113 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5115 action_flags |= actions->type ==
5116 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5117 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5118 MLX5_FLOW_ACTION_SET_IPV6_DST;
5120 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5121 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5122 ret = flow_dv_validate_action_modify_tp(action_flags,
5128 /* Count all modify-header actions as one action. */
5129 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5131 action_flags |= actions->type ==
5132 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5133 MLX5_FLOW_ACTION_SET_TP_SRC :
5134 MLX5_FLOW_ACTION_SET_TP_DST;
5136 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5137 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5138 ret = flow_dv_validate_action_modify_ttl(action_flags,
5144 /* Count all modify-header actions as one action. */
5145 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5147 action_flags |= actions->type ==
5148 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5149 MLX5_FLOW_ACTION_SET_TTL :
5150 MLX5_FLOW_ACTION_DEC_TTL;
5152 case RTE_FLOW_ACTION_TYPE_JUMP:
5153 ret = flow_dv_validate_action_jump(actions,
5160 action_flags |= MLX5_FLOW_ACTION_JUMP;
5162 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5163 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5164 ret = flow_dv_validate_action_modify_tcp_seq
5171 /* Count all modify-header actions as one action. */
5172 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5174 action_flags |= actions->type ==
5175 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5176 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5177 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5179 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5180 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5181 ret = flow_dv_validate_action_modify_tcp_ack
5188 /* Count all modify-header actions as one action. */
5189 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5191 action_flags |= actions->type ==
5192 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5193 MLX5_FLOW_ACTION_INC_TCP_ACK :
5194 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5196 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5197 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5198 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5200 case RTE_FLOW_ACTION_TYPE_METER:
5201 ret = mlx5_flow_validate_action_meter(dev,
5207 action_flags |= MLX5_FLOW_ACTION_METER;
5210 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5211 ret = flow_dv_validate_action_modify_ipv4_dscp
5218 /* Count all modify-header actions as one action. */
5219 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5221 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5223 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5224 ret = flow_dv_validate_action_modify_ipv6_dscp
5231 /* Count all modify-header actions as one action. */
5232 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5234 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5237 return rte_flow_error_set(error, ENOTSUP,
5238 RTE_FLOW_ERROR_TYPE_ACTION,
5240 "action not supported");
5244 * Validate the drop action mutual exclusion with other actions.
5245 * Drop action is mutually-exclusive with any other action, except for
5248 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5249 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5250 return rte_flow_error_set(error, EINVAL,
5251 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5252 "Drop action is mutually-exclusive "
5253 "with any other action, except for "
5255 /* Eswitch has few restrictions on using items and actions */
5256 if (attr->transfer) {
5257 if (!mlx5_flow_ext_mreg_supported(dev) &&
5258 action_flags & MLX5_FLOW_ACTION_FLAG)
5259 return rte_flow_error_set(error, ENOTSUP,
5260 RTE_FLOW_ERROR_TYPE_ACTION,
5262 "unsupported action FLAG");
5263 if (!mlx5_flow_ext_mreg_supported(dev) &&
5264 action_flags & MLX5_FLOW_ACTION_MARK)
5265 return rte_flow_error_set(error, ENOTSUP,
5266 RTE_FLOW_ERROR_TYPE_ACTION,
5268 "unsupported action MARK");
5269 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5270 return rte_flow_error_set(error, ENOTSUP,
5271 RTE_FLOW_ERROR_TYPE_ACTION,
5273 "unsupported action QUEUE");
5274 if (action_flags & MLX5_FLOW_ACTION_RSS)
5275 return rte_flow_error_set(error, ENOTSUP,
5276 RTE_FLOW_ERROR_TYPE_ACTION,
5278 "unsupported action RSS");
5279 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5280 return rte_flow_error_set(error, EINVAL,
5281 RTE_FLOW_ERROR_TYPE_ACTION,
5283 "no fate action is found");
5285 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5286 return rte_flow_error_set(error, EINVAL,
5287 RTE_FLOW_ERROR_TYPE_ACTION,
5289 "no fate action is found");
5291 /* Continue validation for Xcap actions.*/
5292 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5293 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5294 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5295 MLX5_FLOW_XCAP_ACTIONS)
5296 return rte_flow_error_set(error, ENOTSUP,
5297 RTE_FLOW_ERROR_TYPE_ACTION,
5298 NULL, "encap and decap "
5299 "combination aren't supported");
5300 if (!attr->transfer && attr->ingress && (action_flags &
5301 MLX5_FLOW_ACTION_ENCAP))
5302 return rte_flow_error_set(error, ENOTSUP,
5303 RTE_FLOW_ERROR_TYPE_ACTION,
5304 NULL, "encap is not supported"
5305 " for ingress traffic");
5311 * Internal preparation function. Allocates the DV flow size,
5312 * this size is constant.
5315 * Pointer to the rte_eth_dev structure.
5317 * Pointer to the flow attributes.
5319 * Pointer to the list of items.
5320 * @param[in] actions
5321 * Pointer to the list of actions.
5323 * Pointer to the error structure.
5326 * Pointer to mlx5_flow object on success,
5327 * otherwise NULL and rte_errno is set.
5329 static struct mlx5_flow *
5330 flow_dv_prepare(struct rte_eth_dev *dev,
5331 const struct rte_flow_attr *attr __rte_unused,
5332 const struct rte_flow_item items[] __rte_unused,
5333 const struct rte_flow_action actions[] __rte_unused,
5334 struct rte_flow_error *error)
5336 size_t size = sizeof(struct mlx5_flow_handle);
5337 struct mlx5_flow *dev_flow;
5338 struct mlx5_flow_handle *dev_handle;
5339 struct mlx5_priv *priv = dev->data->dev_private;
5341 /* In case of corrupting the memory. */
5342 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5343 rte_flow_error_set(error, ENOSPC,
5344 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5345 "not free temporary device flow");
5348 dev_handle = rte_calloc(__func__, 1, size, 0);
5350 rte_flow_error_set(error, ENOMEM,
5351 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5352 "not enough memory to create flow handle");
5355 /* No multi-thread supporting. */
5356 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5357 dev_flow->handle = dev_handle;
5358 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5360 * The matching value needs to be cleared to 0 before using. In the
5361 * past, it will be automatically cleared when using rte_*alloc
5362 * API. The time consumption will be almost the same as before.
5364 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5365 dev_flow->ingress = attr->ingress;
5366 dev_flow->dv.transfer = attr->transfer;
5370 #ifdef RTE_LIBRTE_MLX5_DEBUG
5372 * Sanity check for match mask and value. Similar to check_valid_spec() in
5373 * kernel driver. If unmasked bit is present in value, it returns failure.
5376 * pointer to match mask buffer.
5377 * @param match_value
5378 * pointer to match value buffer.
5381 * 0 if valid, -EINVAL otherwise.
5384 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5386 uint8_t *m = match_mask;
5387 uint8_t *v = match_value;
5390 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5393 "match_value differs from match_criteria"
5394 " %p[%u] != %p[%u]",
5395 match_value, i, match_mask, i);
5404 * Add Ethernet item to matcher and to the value.
5406 * @param[in, out] matcher
5408 * @param[in, out] key
5409 * Flow matcher value.
5411 * Flow pattern to translate.
5413 * Item is inner pattern.
5416 flow_dv_translate_item_eth(void *matcher, void *key,
5417 const struct rte_flow_item *item, int inner)
5419 const struct rte_flow_item_eth *eth_m = item->mask;
5420 const struct rte_flow_item_eth *eth_v = item->spec;
5421 const struct rte_flow_item_eth nic_mask = {
5422 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5423 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5424 .type = RTE_BE16(0xffff),
5436 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5438 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5440 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5442 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5444 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5445 ð_m->dst, sizeof(eth_m->dst));
5446 /* The value must be in the range of the mask. */
5447 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5448 for (i = 0; i < sizeof(eth_m->dst); ++i)
5449 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5450 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5451 ð_m->src, sizeof(eth_m->src));
5452 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5453 /* The value must be in the range of the mask. */
5454 for (i = 0; i < sizeof(eth_m->dst); ++i)
5455 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5457 /* When ethertype is present set mask for tagged VLAN. */
5458 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5459 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5460 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5461 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5462 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5464 /* Return here to avoid setting match on ethertype. */
5469 * HW supports match on one Ethertype, the Ethertype following the last
5470 * VLAN tag of the packet (see PRM).
5471 * Set match on ethertype only if ETH header is not followed by VLAN.
5473 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5474 rte_be_to_cpu_16(eth_m->type));
5475 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5476 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5480 * Add VLAN item to matcher and to the value.
5482 * @param[in, out] dev_flow
5484 * @param[in, out] matcher
5486 * @param[in, out] key
5487 * Flow matcher value.
5489 * Flow pattern to translate.
5491 * Item is inner pattern.
5494 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5495 void *matcher, void *key,
5496 const struct rte_flow_item *item,
5499 const struct rte_flow_item_vlan *vlan_m = item->mask;
5500 const struct rte_flow_item_vlan *vlan_v = item->spec;
5509 vlan_m = &rte_flow_item_vlan_mask;
5511 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5513 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5515 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5517 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5519 * This is workaround, masks are not supported,
5520 * and pre-validated.
5522 dev_flow->handle->vf_vlan.tag =
5523 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5525 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5526 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5527 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5528 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5529 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5530 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5531 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5532 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5533 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5534 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5535 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5536 rte_be_to_cpu_16(vlan_m->inner_type));
5537 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5538 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5542 * Add IPV4 item to matcher and to the value.
5544 * @param[in, out] matcher
5546 * @param[in, out] key
5547 * Flow matcher value.
5549 * Flow pattern to translate.
5550 * @param[in] item_flags
5551 * Bit-fields that holds the items detected until now.
5553 * Item is inner pattern.
5555 * The group to insert the rule.
5558 flow_dv_translate_item_ipv4(void *matcher, void *key,
5559 const struct rte_flow_item *item,
5560 const uint64_t item_flags,
5561 int inner, uint32_t group)
5563 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5564 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5565 const struct rte_flow_item_ipv4 nic_mask = {
5567 .src_addr = RTE_BE32(0xffffffff),
5568 .dst_addr = RTE_BE32(0xffffffff),
5569 .type_of_service = 0xff,
5570 .next_proto_id = 0xff,
5571 .time_to_live = 0xff,
5581 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5583 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5585 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5587 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5590 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5592 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5593 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5595 * On outer header (which must contains L2), or inner header with L2,
5596 * set cvlan_tag mask bit to mark this packet as untagged.
5597 * This should be done even if item->spec is empty.
5599 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5600 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5605 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5606 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5607 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5608 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5609 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5610 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5611 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5612 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5613 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5614 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5615 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5616 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5617 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5618 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5619 ipv4_m->hdr.type_of_service);
5620 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5621 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5622 ipv4_m->hdr.type_of_service >> 2);
5623 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5624 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5625 ipv4_m->hdr.next_proto_id);
5626 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5627 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5628 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5629 ipv4_m->hdr.time_to_live);
5630 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5631 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5635 * Add IPV6 item to matcher and to the value.
5637 * @param[in, out] matcher
5639 * @param[in, out] key
5640 * Flow matcher value.
5642 * Flow pattern to translate.
5643 * @param[in] item_flags
5644 * Bit-fields that holds the items detected until now.
5646 * Item is inner pattern.
5648 * The group to insert the rule.
5651 flow_dv_translate_item_ipv6(void *matcher, void *key,
5652 const struct rte_flow_item *item,
5653 const uint64_t item_flags,
5654 int inner, uint32_t group)
5656 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5657 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5658 const struct rte_flow_item_ipv6 nic_mask = {
5661 "\xff\xff\xff\xff\xff\xff\xff\xff"
5662 "\xff\xff\xff\xff\xff\xff\xff\xff",
5664 "\xff\xff\xff\xff\xff\xff\xff\xff"
5665 "\xff\xff\xff\xff\xff\xff\xff\xff",
5666 .vtc_flow = RTE_BE32(0xffffffff),
5673 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5674 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5683 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5685 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5687 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5689 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5692 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5694 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5695 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5697 * On outer header (which must contains L2), or inner header with L2,
5698 * set cvlan_tag mask bit to mark this packet as untagged.
5699 * This should be done even if item->spec is empty.
5701 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5702 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5707 size = sizeof(ipv6_m->hdr.dst_addr);
5708 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5709 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5710 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5711 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5712 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5713 for (i = 0; i < size; ++i)
5714 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5715 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5716 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5717 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5718 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5719 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5720 for (i = 0; i < size; ++i)
5721 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5723 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5724 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5725 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5726 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5727 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5728 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5731 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5733 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5736 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5738 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5742 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5744 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5745 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5747 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5748 ipv6_m->hdr.hop_limits);
5749 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5750 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5754 * Add TCP item to matcher and to the value.
5756 * @param[in, out] matcher
5758 * @param[in, out] key
5759 * Flow matcher value.
5761 * Flow pattern to translate.
5763 * Item is inner pattern.
5766 flow_dv_translate_item_tcp(void *matcher, void *key,
5767 const struct rte_flow_item *item,
5770 const struct rte_flow_item_tcp *tcp_m = item->mask;
5771 const struct rte_flow_item_tcp *tcp_v = item->spec;
5776 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5778 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5780 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5782 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5784 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5785 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5789 tcp_m = &rte_flow_item_tcp_mask;
5790 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5791 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5792 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5793 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5794 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5795 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5796 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5797 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5798 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5799 tcp_m->hdr.tcp_flags);
5800 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5801 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5805 * Add UDP item to matcher and to the value.
5807 * @param[in, out] matcher
5809 * @param[in, out] key
5810 * Flow matcher value.
5812 * Flow pattern to translate.
5814 * Item is inner pattern.
5817 flow_dv_translate_item_udp(void *matcher, void *key,
5818 const struct rte_flow_item *item,
5821 const struct rte_flow_item_udp *udp_m = item->mask;
5822 const struct rte_flow_item_udp *udp_v = item->spec;
5827 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5829 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5831 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5833 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5835 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5836 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5840 udp_m = &rte_flow_item_udp_mask;
5841 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5842 rte_be_to_cpu_16(udp_m->hdr.src_port));
5843 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5844 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5845 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5846 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5847 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5848 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5852 * Add GRE optional Key item to matcher and to the value.
5854 * @param[in, out] matcher
5856 * @param[in, out] key
5857 * Flow matcher value.
5859 * Flow pattern to translate.
5861 * Item is inner pattern.
5864 flow_dv_translate_item_gre_key(void *matcher, void *key,
5865 const struct rte_flow_item *item)
5867 const rte_be32_t *key_m = item->mask;
5868 const rte_be32_t *key_v = item->spec;
5869 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5870 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5871 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5873 /* GRE K bit must be on and should already be validated */
5874 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5875 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5879 key_m = &gre_key_default_mask;
5880 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5881 rte_be_to_cpu_32(*key_m) >> 8);
5882 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5883 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5884 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5885 rte_be_to_cpu_32(*key_m) & 0xFF);
5886 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5887 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5891 * Add GRE item to matcher and to the value.
5893 * @param[in, out] matcher
5895 * @param[in, out] key
5896 * Flow matcher value.
5898 * Flow pattern to translate.
5900 * Item is inner pattern.
5903 flow_dv_translate_item_gre(void *matcher, void *key,
5904 const struct rte_flow_item *item,
5907 const struct rte_flow_item_gre *gre_m = item->mask;
5908 const struct rte_flow_item_gre *gre_v = item->spec;
5911 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5912 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5919 uint16_t s_present:1;
5920 uint16_t k_present:1;
5921 uint16_t rsvd_bit1:1;
5922 uint16_t c_present:1;
5926 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5929 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5931 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5933 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5935 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5937 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5938 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5942 gre_m = &rte_flow_item_gre_mask;
5943 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5944 rte_be_to_cpu_16(gre_m->protocol));
5945 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5946 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5947 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5948 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5949 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5950 gre_crks_rsvd0_ver_m.c_present);
5951 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5952 gre_crks_rsvd0_ver_v.c_present &
5953 gre_crks_rsvd0_ver_m.c_present);
5954 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5955 gre_crks_rsvd0_ver_m.k_present);
5956 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5957 gre_crks_rsvd0_ver_v.k_present &
5958 gre_crks_rsvd0_ver_m.k_present);
5959 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5960 gre_crks_rsvd0_ver_m.s_present);
5961 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5962 gre_crks_rsvd0_ver_v.s_present &
5963 gre_crks_rsvd0_ver_m.s_present);
5967 * Add NVGRE item to matcher and to the value.
5969 * @param[in, out] matcher
5971 * @param[in, out] key
5972 * Flow matcher value.
5974 * Flow pattern to translate.
5976 * Item is inner pattern.
5979 flow_dv_translate_item_nvgre(void *matcher, void *key,
5980 const struct rte_flow_item *item,
5983 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5984 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5985 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5986 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5987 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5988 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5994 /* For NVGRE, GRE header fields must be set with defined values. */
5995 const struct rte_flow_item_gre gre_spec = {
5996 .c_rsvd0_ver = RTE_BE16(0x2000),
5997 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5999 const struct rte_flow_item_gre gre_mask = {
6000 .c_rsvd0_ver = RTE_BE16(0xB000),
6001 .protocol = RTE_BE16(UINT16_MAX),
6003 const struct rte_flow_item gre_item = {
6008 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6012 nvgre_m = &rte_flow_item_nvgre_mask;
6013 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6014 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6015 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6016 memcpy(gre_key_m, tni_flow_id_m, size);
6017 for (i = 0; i < size; ++i)
6018 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6022 * Add VXLAN item to matcher and to the value.
6024 * @param[in, out] matcher
6026 * @param[in, out] key
6027 * Flow matcher value.
6029 * Flow pattern to translate.
6031 * Item is inner pattern.
6034 flow_dv_translate_item_vxlan(void *matcher, void *key,
6035 const struct rte_flow_item *item,
6038 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6039 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6042 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6043 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6051 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6053 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6055 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6057 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6059 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6060 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6061 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6062 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6063 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6068 vxlan_m = &rte_flow_item_vxlan_mask;
6069 size = sizeof(vxlan_m->vni);
6070 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6071 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6072 memcpy(vni_m, vxlan_m->vni, size);
6073 for (i = 0; i < size; ++i)
6074 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6078 * Add VXLAN-GPE item to matcher and to the value.
6080 * @param[in, out] matcher
6082 * @param[in, out] key
6083 * Flow matcher value.
6085 * Flow pattern to translate.
6087 * Item is inner pattern.
6091 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6092 const struct rte_flow_item *item, int inner)
6094 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6095 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6099 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6101 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6107 uint8_t flags_m = 0xff;
6108 uint8_t flags_v = 0xc;
6111 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6113 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6115 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6117 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6119 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6120 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6121 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6122 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6123 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6128 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6129 size = sizeof(vxlan_m->vni);
6130 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6131 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6132 memcpy(vni_m, vxlan_m->vni, size);
6133 for (i = 0; i < size; ++i)
6134 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6135 if (vxlan_m->flags) {
6136 flags_m = vxlan_m->flags;
6137 flags_v = vxlan_v->flags;
6139 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6140 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6141 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6143 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6148 * Add Geneve item to matcher and to the value.
6150 * @param[in, out] matcher
6152 * @param[in, out] key
6153 * Flow matcher value.
6155 * Flow pattern to translate.
6157 * Item is inner pattern.
6161 flow_dv_translate_item_geneve(void *matcher, void *key,
6162 const struct rte_flow_item *item, int inner)
6164 const struct rte_flow_item_geneve *geneve_m = item->mask;
6165 const struct rte_flow_item_geneve *geneve_v = item->spec;
6168 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6169 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6178 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6180 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6182 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6184 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6186 dport = MLX5_UDP_PORT_GENEVE;
6187 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6188 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6189 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6194 geneve_m = &rte_flow_item_geneve_mask;
6195 size = sizeof(geneve_m->vni);
6196 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6197 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6198 memcpy(vni_m, geneve_m->vni, size);
6199 for (i = 0; i < size; ++i)
6200 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6201 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6202 rte_be_to_cpu_16(geneve_m->protocol));
6203 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6204 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6205 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6206 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6207 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6208 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6209 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6210 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6211 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6212 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6213 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6214 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6215 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6219 * Add MPLS item to matcher and to the value.
6221 * @param[in, out] matcher
6223 * @param[in, out] key
6224 * Flow matcher value.
6226 * Flow pattern to translate.
6227 * @param[in] prev_layer
6228 * The protocol layer indicated in previous item.
6230 * Item is inner pattern.
6233 flow_dv_translate_item_mpls(void *matcher, void *key,
6234 const struct rte_flow_item *item,
6235 uint64_t prev_layer,
6238 const uint32_t *in_mpls_m = item->mask;
6239 const uint32_t *in_mpls_v = item->spec;
6240 uint32_t *out_mpls_m = 0;
6241 uint32_t *out_mpls_v = 0;
6242 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6243 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6244 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6246 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6247 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6248 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6250 switch (prev_layer) {
6251 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6252 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6253 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6254 MLX5_UDP_PORT_MPLS);
6256 case MLX5_FLOW_LAYER_GRE:
6257 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6258 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6259 RTE_ETHER_TYPE_MPLS);
6262 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6263 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6270 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6271 switch (prev_layer) {
6272 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6274 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6275 outer_first_mpls_over_udp);
6277 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6278 outer_first_mpls_over_udp);
6280 case MLX5_FLOW_LAYER_GRE:
6282 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6283 outer_first_mpls_over_gre);
6285 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6286 outer_first_mpls_over_gre);
6289 /* Inner MPLS not over GRE is not supported. */
6292 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6296 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6302 if (out_mpls_m && out_mpls_v) {
6303 *out_mpls_m = *in_mpls_m;
6304 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6309 * Add metadata register item to matcher
6311 * @param[in, out] matcher
6313 * @param[in, out] key
6314 * Flow matcher value.
6315 * @param[in] reg_type
6316 * Type of device metadata register
6323 flow_dv_match_meta_reg(void *matcher, void *key,
6324 enum modify_reg reg_type,
6325 uint32_t data, uint32_t mask)
6328 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6330 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6336 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6337 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6340 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6341 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6345 * The metadata register C0 field might be divided into
6346 * source vport index and META item value, we should set
6347 * this field according to specified mask, not as whole one.
6349 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6351 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6352 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6355 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6358 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6359 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6362 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6363 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6366 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6367 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6370 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6371 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6374 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6375 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6378 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6379 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6382 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6383 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6392 * Add MARK item to matcher
6395 * The device to configure through.
6396 * @param[in, out] matcher
6398 * @param[in, out] key
6399 * Flow matcher value.
6401 * Flow pattern to translate.
6404 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6405 void *matcher, void *key,
6406 const struct rte_flow_item *item)
6408 struct mlx5_priv *priv = dev->data->dev_private;
6409 const struct rte_flow_item_mark *mark;
6413 mark = item->mask ? (const void *)item->mask :
6414 &rte_flow_item_mark_mask;
6415 mask = mark->id & priv->sh->dv_mark_mask;
6416 mark = (const void *)item->spec;
6418 value = mark->id & priv->sh->dv_mark_mask & mask;
6420 enum modify_reg reg;
6422 /* Get the metadata register index for the mark. */
6423 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6424 MLX5_ASSERT(reg > 0);
6425 if (reg == REG_C_0) {
6426 struct mlx5_priv *priv = dev->data->dev_private;
6427 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6428 uint32_t shl_c0 = rte_bsf32(msk_c0);
6434 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6439 * Add META item to matcher
6442 * The devich to configure through.
6443 * @param[in, out] matcher
6445 * @param[in, out] key
6446 * Flow matcher value.
6448 * Attributes of flow that includes this item.
6450 * Flow pattern to translate.
6453 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6454 void *matcher, void *key,
6455 const struct rte_flow_attr *attr,
6456 const struct rte_flow_item *item)
6458 const struct rte_flow_item_meta *meta_m;
6459 const struct rte_flow_item_meta *meta_v;
6461 meta_m = (const void *)item->mask;
6463 meta_m = &rte_flow_item_meta_mask;
6464 meta_v = (const void *)item->spec;
6467 uint32_t value = meta_v->data;
6468 uint32_t mask = meta_m->data;
6470 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6474 * In datapath code there is no endianness
6475 * coversions for perfromance reasons, all
6476 * pattern conversions are done in rte_flow.
6478 value = rte_cpu_to_be_32(value);
6479 mask = rte_cpu_to_be_32(mask);
6480 if (reg == REG_C_0) {
6481 struct mlx5_priv *priv = dev->data->dev_private;
6482 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6483 uint32_t shl_c0 = rte_bsf32(msk_c0);
6484 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6485 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6492 MLX5_ASSERT(msk_c0);
6493 MLX5_ASSERT(!(~msk_c0 & mask));
6495 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6500 * Add vport metadata Reg C0 item to matcher
6502 * @param[in, out] matcher
6504 * @param[in, out] key
6505 * Flow matcher value.
6507 * Flow pattern to translate.
6510 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6511 uint32_t value, uint32_t mask)
6513 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6517 * Add tag item to matcher
6520 * The devich to configure through.
6521 * @param[in, out] matcher
6523 * @param[in, out] key
6524 * Flow matcher value.
6526 * Flow pattern to translate.
6529 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6530 void *matcher, void *key,
6531 const struct rte_flow_item *item)
6533 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6534 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6535 uint32_t mask, value;
6538 value = tag_v->data;
6539 mask = tag_m ? tag_m->data : UINT32_MAX;
6540 if (tag_v->id == REG_C_0) {
6541 struct mlx5_priv *priv = dev->data->dev_private;
6542 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6543 uint32_t shl_c0 = rte_bsf32(msk_c0);
6549 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6553 * Add TAG item to matcher
6556 * The devich to configure through.
6557 * @param[in, out] matcher
6559 * @param[in, out] key
6560 * Flow matcher value.
6562 * Flow pattern to translate.
6565 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6566 void *matcher, void *key,
6567 const struct rte_flow_item *item)
6569 const struct rte_flow_item_tag *tag_v = item->spec;
6570 const struct rte_flow_item_tag *tag_m = item->mask;
6571 enum modify_reg reg;
6574 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6575 /* Get the metadata register index for the tag. */
6576 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6577 MLX5_ASSERT(reg > 0);
6578 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6582 * Add source vport match to the specified matcher.
6584 * @param[in, out] matcher
6586 * @param[in, out] key
6587 * Flow matcher value.
6589 * Source vport value to match
6594 flow_dv_translate_item_source_vport(void *matcher, void *key,
6595 int16_t port, uint16_t mask)
6597 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6598 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6600 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6601 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6605 * Translate port-id item to eswitch match on port-id.
6608 * The devich to configure through.
6609 * @param[in, out] matcher
6611 * @param[in, out] key
6612 * Flow matcher value.
6614 * Flow pattern to translate.
6617 * 0 on success, a negative errno value otherwise.
6620 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6621 void *key, const struct rte_flow_item *item)
6623 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6624 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6625 struct mlx5_priv *priv;
6628 mask = pid_m ? pid_m->id : 0xffff;
6629 id = pid_v ? pid_v->id : dev->data->port_id;
6630 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6633 /* Translate to vport field or to metadata, depending on mode. */
6634 if (priv->vport_meta_mask)
6635 flow_dv_translate_item_meta_vport(matcher, key,
6636 priv->vport_meta_tag,
6637 priv->vport_meta_mask);
6639 flow_dv_translate_item_source_vport(matcher, key,
6640 priv->vport_id, mask);
6645 * Add ICMP6 item to matcher and to the value.
6647 * @param[in, out] matcher
6649 * @param[in, out] key
6650 * Flow matcher value.
6652 * Flow pattern to translate.
6654 * Item is inner pattern.
6657 flow_dv_translate_item_icmp6(void *matcher, void *key,
6658 const struct rte_flow_item *item,
6661 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6662 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6665 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6667 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6669 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6671 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6673 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6675 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6677 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6678 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6682 icmp6_m = &rte_flow_item_icmp6_mask;
6684 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6685 * If only the protocol is specified, no need to match the frag.
6687 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6688 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6689 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6690 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6691 icmp6_v->type & icmp6_m->type);
6692 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6693 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6694 icmp6_v->code & icmp6_m->code);
6698 * Add ICMP item to matcher and to the value.
6700 * @param[in, out] matcher
6702 * @param[in, out] key
6703 * Flow matcher value.
6705 * Flow pattern to translate.
6707 * Item is inner pattern.
6710 flow_dv_translate_item_icmp(void *matcher, void *key,
6711 const struct rte_flow_item *item,
6714 const struct rte_flow_item_icmp *icmp_m = item->mask;
6715 const struct rte_flow_item_icmp *icmp_v = item->spec;
6718 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6720 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6722 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6724 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6726 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6728 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6730 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6731 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6735 icmp_m = &rte_flow_item_icmp_mask;
6737 * Force flow only to match the non-fragmented IPv4 ICMP packets.
6738 * If only the protocol is specified, no need to match the frag.
6740 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6741 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6742 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6743 icmp_m->hdr.icmp_type);
6744 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6745 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6746 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6747 icmp_m->hdr.icmp_code);
6748 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6749 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6753 * Add GTP item to matcher and to the value.
6755 * @param[in, out] matcher
6757 * @param[in, out] key
6758 * Flow matcher value.
6760 * Flow pattern to translate.
6762 * Item is inner pattern.
6765 flow_dv_translate_item_gtp(void *matcher, void *key,
6766 const struct rte_flow_item *item, int inner)
6768 const struct rte_flow_item_gtp *gtp_m = item->mask;
6769 const struct rte_flow_item_gtp *gtp_v = item->spec;
6772 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6774 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6775 uint16_t dport = RTE_GTPU_UDP_PORT;
6778 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6780 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6782 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6784 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6786 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6787 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6788 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6793 gtp_m = &rte_flow_item_gtp_mask;
6794 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6795 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6796 gtp_v->msg_type & gtp_m->msg_type);
6797 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6798 rte_be_to_cpu_32(gtp_m->teid));
6799 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6800 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6803 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6805 #define HEADER_IS_ZERO(match_criteria, headers) \
6806 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6807 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6810 * Calculate flow matcher enable bitmap.
6812 * @param match_criteria
6813 * Pointer to flow matcher criteria.
6816 * Bitmap of enabled fields.
6819 flow_dv_matcher_enable(uint32_t *match_criteria)
6821 uint8_t match_criteria_enable;
6823 match_criteria_enable =
6824 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6825 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6826 match_criteria_enable |=
6827 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6828 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6829 match_criteria_enable |=
6830 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6831 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6832 match_criteria_enable |=
6833 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6834 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6835 match_criteria_enable |=
6836 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6837 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6838 return match_criteria_enable;
6845 * @param[in, out] dev
6846 * Pointer to rte_eth_dev structure.
6847 * @param[in] table_id
6850 * Direction of the table.
6851 * @param[in] transfer
6852 * E-Switch or NIC flow.
6854 * pointer to error structure.
6857 * Returns tables resource based on the index, NULL in case of failed.
6859 static struct mlx5_flow_tbl_resource *
6860 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6861 uint32_t table_id, uint8_t egress,
6863 struct rte_flow_error *error)
6865 struct mlx5_priv *priv = dev->data->dev_private;
6866 struct mlx5_ibv_shared *sh = priv->sh;
6867 struct mlx5_flow_tbl_resource *tbl;
6868 union mlx5_flow_tbl_key table_key = {
6870 .table_id = table_id,
6872 .domain = !!transfer,
6873 .direction = !!egress,
6876 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6878 struct mlx5_flow_tbl_data_entry *tbl_data;
6884 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6886 tbl = &tbl_data->tbl;
6887 rte_atomic32_inc(&tbl->refcnt);
6890 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
6892 rte_flow_error_set(error, ENOMEM,
6893 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6895 "cannot allocate flow table data entry");
6898 tbl_data->idx = idx;
6899 tbl = &tbl_data->tbl;
6900 pos = &tbl_data->entry;
6902 domain = sh->fdb_domain;
6904 domain = sh->tx_domain;
6906 domain = sh->rx_domain;
6907 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6909 rte_flow_error_set(error, ENOMEM,
6910 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6911 NULL, "cannot create flow table object");
6912 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6916 * No multi-threads now, but still better to initialize the reference
6917 * count before insert it into the hash list.
6919 rte_atomic32_init(&tbl->refcnt);
6920 /* Jump action reference count is initialized here. */
6921 rte_atomic32_init(&tbl_data->jump.refcnt);
6922 pos->key = table_key.v64;
6923 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6925 rte_flow_error_set(error, -ret,
6926 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6927 "cannot insert flow table data entry");
6928 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6929 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
6931 rte_atomic32_inc(&tbl->refcnt);
6936 * Release a flow table.
6939 * Pointer to rte_eth_dev structure.
6941 * Table resource to be released.
6944 * Returns 0 if table was released, else return 1;
6947 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6948 struct mlx5_flow_tbl_resource *tbl)
6950 struct mlx5_priv *priv = dev->data->dev_private;
6951 struct mlx5_ibv_shared *sh = priv->sh;
6952 struct mlx5_flow_tbl_data_entry *tbl_data =
6953 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6957 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6958 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6960 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6962 /* remove the entry from the hash list and free memory. */
6963 mlx5_hlist_remove(sh->flow_tbls, pos);
6964 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
6972 * Register the flow matcher.
6974 * @param[in, out] dev
6975 * Pointer to rte_eth_dev structure.
6976 * @param[in, out] matcher
6977 * Pointer to flow matcher.
6978 * @param[in, out] key
6979 * Pointer to flow table key.
6980 * @parm[in, out] dev_flow
6981 * Pointer to the dev_flow.
6983 * pointer to error structure.
6986 * 0 on success otherwise -errno and errno is set.
6989 flow_dv_matcher_register(struct rte_eth_dev *dev,
6990 struct mlx5_flow_dv_matcher *matcher,
6991 union mlx5_flow_tbl_key *key,
6992 struct mlx5_flow *dev_flow,
6993 struct rte_flow_error *error)
6995 struct mlx5_priv *priv = dev->data->dev_private;
6996 struct mlx5_ibv_shared *sh = priv->sh;
6997 struct mlx5_flow_dv_matcher *cache_matcher;
6998 struct mlx5dv_flow_matcher_attr dv_attr = {
6999 .type = IBV_FLOW_ATTR_NORMAL,
7000 .match_mask = (void *)&matcher->mask,
7002 struct mlx5_flow_tbl_resource *tbl;
7003 struct mlx5_flow_tbl_data_entry *tbl_data;
7005 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7006 key->domain, error);
7008 return -rte_errno; /* No need to refill the error info */
7009 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7010 /* Lookup from cache. */
7011 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7012 if (matcher->crc == cache_matcher->crc &&
7013 matcher->priority == cache_matcher->priority &&
7014 !memcmp((const void *)matcher->mask.buf,
7015 (const void *)cache_matcher->mask.buf,
7016 cache_matcher->mask.size)) {
7018 "%s group %u priority %hd use %s "
7019 "matcher %p: refcnt %d++",
7020 key->domain ? "FDB" : "NIC", key->table_id,
7021 cache_matcher->priority,
7022 key->direction ? "tx" : "rx",
7023 (void *)cache_matcher,
7024 rte_atomic32_read(&cache_matcher->refcnt));
7025 rte_atomic32_inc(&cache_matcher->refcnt);
7026 dev_flow->handle->dvh.matcher = cache_matcher;
7027 /* old matcher should not make the table ref++. */
7028 flow_dv_tbl_resource_release(dev, tbl);
7032 /* Register new matcher. */
7033 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7034 if (!cache_matcher) {
7035 flow_dv_tbl_resource_release(dev, tbl);
7036 return rte_flow_error_set(error, ENOMEM,
7037 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7038 "cannot allocate matcher memory");
7040 *cache_matcher = *matcher;
7041 dv_attr.match_criteria_enable =
7042 flow_dv_matcher_enable(cache_matcher->mask.buf);
7043 dv_attr.priority = matcher->priority;
7045 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7046 cache_matcher->matcher_object =
7047 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7048 if (!cache_matcher->matcher_object) {
7049 rte_free(cache_matcher);
7050 #ifdef HAVE_MLX5DV_DR
7051 flow_dv_tbl_resource_release(dev, tbl);
7053 return rte_flow_error_set(error, ENOMEM,
7054 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7055 NULL, "cannot create matcher");
7057 /* Save the table information */
7058 cache_matcher->tbl = tbl;
7059 rte_atomic32_init(&cache_matcher->refcnt);
7060 /* only matcher ref++, table ref++ already done above in get API. */
7061 rte_atomic32_inc(&cache_matcher->refcnt);
7062 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7063 dev_flow->handle->dvh.matcher = cache_matcher;
7064 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7065 key->domain ? "FDB" : "NIC", key->table_id,
7066 cache_matcher->priority,
7067 key->direction ? "tx" : "rx", (void *)cache_matcher,
7068 rte_atomic32_read(&cache_matcher->refcnt));
7073 * Find existing tag resource or create and register a new one.
7075 * @param dev[in, out]
7076 * Pointer to rte_eth_dev structure.
7077 * @param[in, out] tag_be24
7078 * Tag value in big endian then R-shift 8.
7079 * @parm[in, out] dev_flow
7080 * Pointer to the dev_flow.
7082 * pointer to error structure.
7085 * 0 on success otherwise -errno and errno is set.
7088 flow_dv_tag_resource_register
7089 (struct rte_eth_dev *dev,
7091 struct mlx5_flow *dev_flow,
7092 struct rte_flow_error *error)
7094 struct mlx5_priv *priv = dev->data->dev_private;
7095 struct mlx5_ibv_shared *sh = priv->sh;
7096 struct mlx5_flow_dv_tag_resource *cache_resource;
7097 struct mlx5_hlist_entry *entry;
7099 /* Lookup a matching resource from cache. */
7100 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7102 cache_resource = container_of
7103 (entry, struct mlx5_flow_dv_tag_resource, entry);
7104 rte_atomic32_inc(&cache_resource->refcnt);
7105 dev_flow->handle->dvh.tag_resource = cache_resource->idx;
7106 dev_flow->dv.tag_resource = cache_resource;
7107 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7108 (void *)cache_resource,
7109 rte_atomic32_read(&cache_resource->refcnt));
7112 /* Register new resource. */
7113 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7114 &dev_flow->handle->dvh.tag_resource);
7115 if (!cache_resource)
7116 return rte_flow_error_set(error, ENOMEM,
7117 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7118 "cannot allocate resource memory");
7119 cache_resource->entry.key = (uint64_t)tag_be24;
7120 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7121 if (!cache_resource->action) {
7122 rte_free(cache_resource);
7123 return rte_flow_error_set(error, ENOMEM,
7124 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7125 NULL, "cannot create action");
7127 rte_atomic32_init(&cache_resource->refcnt);
7128 rte_atomic32_inc(&cache_resource->refcnt);
7129 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7130 mlx5_glue->destroy_flow_action(cache_resource->action);
7131 rte_free(cache_resource);
7132 return rte_flow_error_set(error, EEXIST,
7133 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7134 NULL, "cannot insert tag");
7136 dev_flow->dv.tag_resource = cache_resource;
7137 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7138 (void *)cache_resource,
7139 rte_atomic32_read(&cache_resource->refcnt));
7147 * Pointer to Ethernet device.
7152 * 1 while a reference on it exists, 0 when freed.
7155 flow_dv_tag_release(struct rte_eth_dev *dev,
7158 struct mlx5_priv *priv = dev->data->dev_private;
7159 struct mlx5_ibv_shared *sh = priv->sh;
7160 struct mlx5_flow_dv_tag_resource *tag;
7162 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7165 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7166 dev->data->port_id, (void *)tag,
7167 rte_atomic32_read(&tag->refcnt));
7168 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7169 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7170 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7171 DRV_LOG(DEBUG, "port %u tag %p: removed",
7172 dev->data->port_id, (void *)tag);
7173 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7180 * Translate port ID action to vport.
7183 * Pointer to rte_eth_dev structure.
7185 * Pointer to the port ID action.
7186 * @param[out] dst_port_id
7187 * The target port ID.
7189 * Pointer to the error structure.
7192 * 0 on success, a negative errno value otherwise and rte_errno is set.
7195 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7196 const struct rte_flow_action *action,
7197 uint32_t *dst_port_id,
7198 struct rte_flow_error *error)
7201 struct mlx5_priv *priv;
7202 const struct rte_flow_action_port_id *conf =
7203 (const struct rte_flow_action_port_id *)action->conf;
7205 port = conf->original ? dev->data->port_id : conf->id;
7206 priv = mlx5_port_to_eswitch_info(port, false);
7208 return rte_flow_error_set(error, -rte_errno,
7209 RTE_FLOW_ERROR_TYPE_ACTION,
7211 "No eswitch info was found for port");
7212 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7214 * This parameter is transferred to
7215 * mlx5dv_dr_action_create_dest_ib_port().
7217 *dst_port_id = priv->ibv_port;
7220 * Legacy mode, no LAG configurations is supported.
7221 * This parameter is transferred to
7222 * mlx5dv_dr_action_create_dest_vport().
7224 *dst_port_id = priv->vport_id;
7230 * Add Tx queue matcher
7233 * Pointer to the dev struct.
7234 * @param[in, out] matcher
7236 * @param[in, out] key
7237 * Flow matcher value.
7239 * Flow pattern to translate.
7241 * Item is inner pattern.
7244 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7245 void *matcher, void *key,
7246 const struct rte_flow_item *item)
7248 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7249 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7251 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7253 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7254 struct mlx5_txq_ctrl *txq;
7258 queue_m = (const void *)item->mask;
7261 queue_v = (const void *)item->spec;
7264 txq = mlx5_txq_get(dev, queue_v->queue);
7267 queue = txq->obj->sq->id;
7268 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7269 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7270 queue & queue_m->queue);
7271 mlx5_txq_release(dev, queue_v->queue);
7275 * Set the hash fields according to the @p flow information.
7277 * @param[in] dev_flow
7278 * Pointer to the mlx5_flow.
7281 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7283 struct rte_flow *flow = dev_flow->flow;
7284 uint64_t items = dev_flow->handle->layers;
7286 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7288 dev_flow->hash_fields = 0;
7289 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7290 if (flow->rss.level >= 2) {
7291 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7295 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7296 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7297 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7298 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7299 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7300 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7301 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7303 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7305 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7306 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7307 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7308 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7309 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7310 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7311 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7313 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7316 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7317 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7318 if (rss_types & ETH_RSS_UDP) {
7319 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7320 dev_flow->hash_fields |=
7321 IBV_RX_HASH_SRC_PORT_UDP;
7322 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7323 dev_flow->hash_fields |=
7324 IBV_RX_HASH_DST_PORT_UDP;
7326 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7328 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7329 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7330 if (rss_types & ETH_RSS_TCP) {
7331 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7332 dev_flow->hash_fields |=
7333 IBV_RX_HASH_SRC_PORT_TCP;
7334 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7335 dev_flow->hash_fields |=
7336 IBV_RX_HASH_DST_PORT_TCP;
7338 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7344 * Fill the flow with DV spec, lock free
7345 * (mutex should be acquired by caller).
7348 * Pointer to rte_eth_dev structure.
7349 * @param[in, out] dev_flow
7350 * Pointer to the sub flow.
7352 * Pointer to the flow attributes.
7354 * Pointer to the list of items.
7355 * @param[in] actions
7356 * Pointer to the list of actions.
7358 * Pointer to the error structure.
7361 * 0 on success, a negative errno value otherwise and rte_errno is set.
7364 __flow_dv_translate(struct rte_eth_dev *dev,
7365 struct mlx5_flow *dev_flow,
7366 const struct rte_flow_attr *attr,
7367 const struct rte_flow_item items[],
7368 const struct rte_flow_action actions[],
7369 struct rte_flow_error *error)
7371 struct mlx5_priv *priv = dev->data->dev_private;
7372 struct mlx5_dev_config *dev_conf = &priv->config;
7373 struct rte_flow *flow = dev_flow->flow;
7374 struct mlx5_flow_handle *handle = dev_flow->handle;
7375 uint64_t item_flags = 0;
7376 uint64_t last_item = 0;
7377 uint64_t action_flags = 0;
7378 uint64_t priority = attr->priority;
7379 struct mlx5_flow_dv_matcher matcher = {
7381 .size = sizeof(matcher.mask.buf),
7385 bool actions_end = false;
7387 struct mlx5_flow_dv_modify_hdr_resource res;
7388 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7389 sizeof(struct mlx5_modification_cmd) *
7390 (MLX5_MAX_MODIFY_NUM + 1)];
7392 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7393 union flow_dv_attr flow_attr = { .attr = 0 };
7395 union mlx5_flow_tbl_key tbl_key;
7396 uint32_t modify_action_position = UINT32_MAX;
7397 void *match_mask = matcher.mask.buf;
7398 void *match_value = dev_flow->dv.value.buf;
7399 uint8_t next_protocol = 0xff;
7400 struct rte_vlan_hdr vlan = { 0 };
7404 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7405 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7406 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7407 !!priv->fdb_def_rule, &table, error);
7410 dev_flow->dv.group = table;
7412 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7413 if (priority == MLX5_FLOW_PRIO_RSVD)
7414 priority = dev_conf->flow_prio - 1;
7415 /* number of actions must be set to 0 in case of dirty stack. */
7416 mhdr_res->actions_num = 0;
7417 for (; !actions_end ; actions++) {
7418 const struct rte_flow_action_queue *queue;
7419 const struct rte_flow_action_rss *rss;
7420 const struct rte_flow_action *action = actions;
7421 const struct rte_flow_action_count *count = action->conf;
7422 const uint8_t *rss_key;
7423 const struct rte_flow_action_jump *jump_data;
7424 const struct rte_flow_action_meter *mtr;
7425 struct mlx5_flow_tbl_resource *tbl;
7426 uint32_t port_id = 0;
7427 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7428 int action_type = actions->type;
7429 const struct rte_flow_action *found_action = NULL;
7431 switch (action_type) {
7432 case RTE_FLOW_ACTION_TYPE_VOID:
7434 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7435 if (flow_dv_translate_action_port_id(dev, action,
7438 memset(&port_id_resource, 0, sizeof(port_id_resource));
7439 port_id_resource.port_id = port_id;
7440 if (flow_dv_port_id_action_resource_register
7441 (dev, &port_id_resource, dev_flow, error))
7443 MLX5_ASSERT(!handle->dvh.port_id_action);
7444 dev_flow->dv.actions[actions_n++] =
7445 dev_flow->dv.port_id_action->action;
7446 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7448 case RTE_FLOW_ACTION_TYPE_FLAG:
7449 action_flags |= MLX5_FLOW_ACTION_FLAG;
7450 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7451 struct rte_flow_action_mark mark = {
7452 .id = MLX5_FLOW_MARK_DEFAULT,
7455 if (flow_dv_convert_action_mark(dev, &mark,
7459 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7462 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7464 * Only one FLAG or MARK is supported per device flow
7465 * right now. So the pointer to the tag resource must be
7466 * zero before the register process.
7468 MLX5_ASSERT(!handle->dvh.tag_resource);
7469 if (flow_dv_tag_resource_register(dev, tag_be,
7472 MLX5_ASSERT(dev_flow->dv.tag_resource);
7473 dev_flow->dv.actions[actions_n++] =
7474 dev_flow->dv.tag_resource->action;
7476 case RTE_FLOW_ACTION_TYPE_MARK:
7477 action_flags |= MLX5_FLOW_ACTION_MARK;
7478 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7479 const struct rte_flow_action_mark *mark =
7480 (const struct rte_flow_action_mark *)
7483 if (flow_dv_convert_action_mark(dev, mark,
7487 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7491 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7492 /* Legacy (non-extensive) MARK action. */
7493 tag_be = mlx5_flow_mark_set
7494 (((const struct rte_flow_action_mark *)
7495 (actions->conf))->id);
7496 MLX5_ASSERT(!handle->dvh.tag_resource);
7497 if (flow_dv_tag_resource_register(dev, tag_be,
7500 MLX5_ASSERT(dev_flow->dv.tag_resource);
7501 dev_flow->dv.actions[actions_n++] =
7502 dev_flow->dv.tag_resource->action;
7504 case RTE_FLOW_ACTION_TYPE_SET_META:
7505 if (flow_dv_convert_action_set_meta
7506 (dev, mhdr_res, attr,
7507 (const struct rte_flow_action_set_meta *)
7508 actions->conf, error))
7510 action_flags |= MLX5_FLOW_ACTION_SET_META;
7512 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7513 if (flow_dv_convert_action_set_tag
7515 (const struct rte_flow_action_set_tag *)
7516 actions->conf, error))
7518 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7520 case RTE_FLOW_ACTION_TYPE_DROP:
7521 action_flags |= MLX5_FLOW_ACTION_DROP;
7523 case RTE_FLOW_ACTION_TYPE_QUEUE:
7524 MLX5_ASSERT(flow->rss.queue);
7525 queue = actions->conf;
7526 flow->rss.queue_num = 1;
7527 (*flow->rss.queue)[0] = queue->index;
7528 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7530 case RTE_FLOW_ACTION_TYPE_RSS:
7531 MLX5_ASSERT(flow->rss.queue);
7532 rss = actions->conf;
7533 if (flow->rss.queue)
7534 memcpy((*flow->rss.queue), rss->queue,
7535 rss->queue_num * sizeof(uint16_t));
7536 flow->rss.queue_num = rss->queue_num;
7537 /* NULL RSS key indicates default RSS key. */
7538 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7539 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7541 * rss->level and rss.types should be set in advance
7542 * when expanding items for RSS.
7544 action_flags |= MLX5_FLOW_ACTION_RSS;
7546 case RTE_FLOW_ACTION_TYPE_COUNT:
7547 if (!dev_conf->devx) {
7548 rte_errno = ENOTSUP;
7551 flow->counter = flow_dv_counter_alloc(dev,
7554 dev_flow->dv.group);
7557 dev_flow->dv.actions[actions_n++] =
7558 (flow_dv_counter_get_by_idx(dev,
7559 flow->counter, NULL))->action;
7560 action_flags |= MLX5_FLOW_ACTION_COUNT;
7563 if (rte_errno == ENOTSUP)
7564 return rte_flow_error_set
7566 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7568 "count action not supported");
7570 return rte_flow_error_set
7572 RTE_FLOW_ERROR_TYPE_ACTION,
7574 "cannot create counter"
7577 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7578 dev_flow->dv.actions[actions_n++] =
7579 priv->sh->pop_vlan_action;
7580 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7582 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7583 if (!(action_flags &
7584 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7585 flow_dev_get_vlan_info_from_items(items, &vlan);
7586 vlan.eth_proto = rte_be_to_cpu_16
7587 ((((const struct rte_flow_action_of_push_vlan *)
7588 actions->conf)->ethertype));
7589 found_action = mlx5_flow_find_action
7591 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7593 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7594 found_action = mlx5_flow_find_action
7596 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7598 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7599 if (flow_dv_create_action_push_vlan
7600 (dev, attr, &vlan, dev_flow, error))
7602 dev_flow->dv.actions[actions_n++] =
7603 dev_flow->dv.push_vlan_res->action;
7604 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7606 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7607 /* of_vlan_push action handled this action */
7608 MLX5_ASSERT(action_flags &
7609 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7611 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7612 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7614 flow_dev_get_vlan_info_from_items(items, &vlan);
7615 mlx5_update_vlan_vid_pcp(actions, &vlan);
7616 /* If no VLAN push - this is a modify header action */
7617 if (flow_dv_convert_action_modify_vlan_vid
7618 (mhdr_res, actions, error))
7620 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7622 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7623 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7624 if (flow_dv_create_action_l2_encap(dev, actions,
7629 dev_flow->dv.actions[actions_n++] =
7630 dev_flow->dv.encap_decap->verbs_action;
7631 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7633 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7634 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7635 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7639 dev_flow->dv.actions[actions_n++] =
7640 dev_flow->dv.encap_decap->verbs_action;
7641 action_flags |= MLX5_FLOW_ACTION_DECAP;
7643 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7644 /* Handle encap with preceding decap. */
7645 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7646 if (flow_dv_create_action_raw_encap
7647 (dev, actions, dev_flow, attr, error))
7649 dev_flow->dv.actions[actions_n++] =
7650 dev_flow->dv.encap_decap->verbs_action;
7652 /* Handle encap without preceding decap. */
7653 if (flow_dv_create_action_l2_encap
7654 (dev, actions, dev_flow, attr->transfer,
7657 dev_flow->dv.actions[actions_n++] =
7658 dev_flow->dv.encap_decap->verbs_action;
7660 action_flags |= MLX5_FLOW_ACTION_ENCAP;
7662 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7663 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7665 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7666 if (flow_dv_create_action_l2_decap
7667 (dev, dev_flow, attr->transfer, error))
7669 dev_flow->dv.actions[actions_n++] =
7670 dev_flow->dv.encap_decap->verbs_action;
7672 /* If decap is followed by encap, handle it at encap. */
7673 action_flags |= MLX5_FLOW_ACTION_DECAP;
7675 case RTE_FLOW_ACTION_TYPE_JUMP:
7676 jump_data = action->conf;
7677 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7679 !!priv->fdb_def_rule,
7683 tbl = flow_dv_tbl_resource_get(dev, table,
7685 attr->transfer, error);
7687 return rte_flow_error_set
7689 RTE_FLOW_ERROR_TYPE_ACTION,
7691 "cannot create jump action.");
7692 if (flow_dv_jump_tbl_resource_register
7693 (dev, tbl, dev_flow, error)) {
7694 flow_dv_tbl_resource_release(dev, tbl);
7695 return rte_flow_error_set
7697 RTE_FLOW_ERROR_TYPE_ACTION,
7699 "cannot create jump action.");
7701 dev_flow->dv.actions[actions_n++] =
7702 dev_flow->dv.jump->action;
7703 action_flags |= MLX5_FLOW_ACTION_JUMP;
7705 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7706 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7707 if (flow_dv_convert_action_modify_mac
7708 (mhdr_res, actions, error))
7710 action_flags |= actions->type ==
7711 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7712 MLX5_FLOW_ACTION_SET_MAC_SRC :
7713 MLX5_FLOW_ACTION_SET_MAC_DST;
7715 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7716 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7717 if (flow_dv_convert_action_modify_ipv4
7718 (mhdr_res, actions, error))
7720 action_flags |= actions->type ==
7721 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7722 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7723 MLX5_FLOW_ACTION_SET_IPV4_DST;
7725 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7726 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7727 if (flow_dv_convert_action_modify_ipv6
7728 (mhdr_res, actions, error))
7730 action_flags |= actions->type ==
7731 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7732 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7733 MLX5_FLOW_ACTION_SET_IPV6_DST;
7735 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7736 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7737 if (flow_dv_convert_action_modify_tp
7738 (mhdr_res, actions, items,
7739 &flow_attr, dev_flow, !!(action_flags &
7740 MLX5_FLOW_ACTION_DECAP), error))
7742 action_flags |= actions->type ==
7743 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7744 MLX5_FLOW_ACTION_SET_TP_SRC :
7745 MLX5_FLOW_ACTION_SET_TP_DST;
7747 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7748 if (flow_dv_convert_action_modify_dec_ttl
7749 (mhdr_res, items, &flow_attr, dev_flow,
7751 MLX5_FLOW_ACTION_DECAP), error))
7753 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7755 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7756 if (flow_dv_convert_action_modify_ttl
7757 (mhdr_res, actions, items, &flow_attr,
7758 dev_flow, !!(action_flags &
7759 MLX5_FLOW_ACTION_DECAP), error))
7761 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7763 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7764 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7765 if (flow_dv_convert_action_modify_tcp_seq
7766 (mhdr_res, actions, error))
7768 action_flags |= actions->type ==
7769 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7770 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7771 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7774 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7775 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7776 if (flow_dv_convert_action_modify_tcp_ack
7777 (mhdr_res, actions, error))
7779 action_flags |= actions->type ==
7780 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7781 MLX5_FLOW_ACTION_INC_TCP_ACK :
7782 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7784 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7785 if (flow_dv_convert_action_set_reg
7786 (mhdr_res, actions, error))
7788 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7790 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7791 if (flow_dv_convert_action_copy_mreg
7792 (dev, mhdr_res, actions, error))
7794 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7796 case RTE_FLOW_ACTION_TYPE_METER:
7797 mtr = actions->conf;
7799 flow->meter = mlx5_flow_meter_attach(priv,
7803 return rte_flow_error_set(error,
7805 RTE_FLOW_ERROR_TYPE_ACTION,
7808 "or invalid parameters");
7810 /* Set the meter action. */
7811 dev_flow->dv.actions[actions_n++] =
7812 flow->meter->mfts->meter_action;
7813 action_flags |= MLX5_FLOW_ACTION_METER;
7815 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7816 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7819 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7821 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7822 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7825 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7827 case RTE_FLOW_ACTION_TYPE_END:
7829 if (mhdr_res->actions_num) {
7830 /* create modify action if needed. */
7831 if (flow_dv_modify_hdr_resource_register
7832 (dev, mhdr_res, dev_flow, error))
7834 dev_flow->dv.actions[modify_action_position] =
7835 handle->dvh.modify_hdr->verbs_action;
7841 if (mhdr_res->actions_num &&
7842 modify_action_position == UINT32_MAX)
7843 modify_action_position = actions_n++;
7845 dev_flow->dv.actions_n = actions_n;
7846 handle->act_flags = action_flags;
7847 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7848 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7849 int item_type = items->type;
7851 switch (item_type) {
7852 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7853 flow_dv_translate_item_port_id(dev, match_mask,
7854 match_value, items);
7855 last_item = MLX5_FLOW_ITEM_PORT_ID;
7857 case RTE_FLOW_ITEM_TYPE_ETH:
7858 flow_dv_translate_item_eth(match_mask, match_value,
7860 matcher.priority = MLX5_PRIORITY_MAP_L2;
7861 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7862 MLX5_FLOW_LAYER_OUTER_L2;
7864 case RTE_FLOW_ITEM_TYPE_VLAN:
7865 flow_dv_translate_item_vlan(dev_flow,
7866 match_mask, match_value,
7868 matcher.priority = MLX5_PRIORITY_MAP_L2;
7869 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7870 MLX5_FLOW_LAYER_INNER_VLAN) :
7871 (MLX5_FLOW_LAYER_OUTER_L2 |
7872 MLX5_FLOW_LAYER_OUTER_VLAN);
7874 case RTE_FLOW_ITEM_TYPE_IPV4:
7875 mlx5_flow_tunnel_ip_check(items, next_protocol,
7876 &item_flags, &tunnel);
7877 flow_dv_translate_item_ipv4(match_mask, match_value,
7878 items, item_flags, tunnel,
7879 dev_flow->dv.group);
7880 matcher.priority = MLX5_PRIORITY_MAP_L3;
7881 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7882 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7883 if (items->mask != NULL &&
7884 ((const struct rte_flow_item_ipv4 *)
7885 items->mask)->hdr.next_proto_id) {
7887 ((const struct rte_flow_item_ipv4 *)
7888 (items->spec))->hdr.next_proto_id;
7890 ((const struct rte_flow_item_ipv4 *)
7891 (items->mask))->hdr.next_proto_id;
7893 /* Reset for inner layer. */
7894 next_protocol = 0xff;
7897 case RTE_FLOW_ITEM_TYPE_IPV6:
7898 mlx5_flow_tunnel_ip_check(items, next_protocol,
7899 &item_flags, &tunnel);
7900 flow_dv_translate_item_ipv6(match_mask, match_value,
7901 items, item_flags, tunnel,
7902 dev_flow->dv.group);
7903 matcher.priority = MLX5_PRIORITY_MAP_L3;
7904 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7905 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7906 if (items->mask != NULL &&
7907 ((const struct rte_flow_item_ipv6 *)
7908 items->mask)->hdr.proto) {
7910 ((const struct rte_flow_item_ipv6 *)
7911 items->spec)->hdr.proto;
7913 ((const struct rte_flow_item_ipv6 *)
7914 items->mask)->hdr.proto;
7916 /* Reset for inner layer. */
7917 next_protocol = 0xff;
7920 case RTE_FLOW_ITEM_TYPE_TCP:
7921 flow_dv_translate_item_tcp(match_mask, match_value,
7923 matcher.priority = MLX5_PRIORITY_MAP_L4;
7924 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7925 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7927 case RTE_FLOW_ITEM_TYPE_UDP:
7928 flow_dv_translate_item_udp(match_mask, match_value,
7930 matcher.priority = MLX5_PRIORITY_MAP_L4;
7931 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7932 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7934 case RTE_FLOW_ITEM_TYPE_GRE:
7935 flow_dv_translate_item_gre(match_mask, match_value,
7937 matcher.priority = flow->rss.level >= 2 ?
7938 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7939 last_item = MLX5_FLOW_LAYER_GRE;
7941 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7942 flow_dv_translate_item_gre_key(match_mask,
7943 match_value, items);
7944 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7946 case RTE_FLOW_ITEM_TYPE_NVGRE:
7947 flow_dv_translate_item_nvgre(match_mask, match_value,
7949 matcher.priority = flow->rss.level >= 2 ?
7950 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7951 last_item = MLX5_FLOW_LAYER_GRE;
7953 case RTE_FLOW_ITEM_TYPE_VXLAN:
7954 flow_dv_translate_item_vxlan(match_mask, match_value,
7956 matcher.priority = flow->rss.level >= 2 ?
7957 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7958 last_item = MLX5_FLOW_LAYER_VXLAN;
7960 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7961 flow_dv_translate_item_vxlan_gpe(match_mask,
7964 matcher.priority = flow->rss.level >= 2 ?
7965 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7966 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7968 case RTE_FLOW_ITEM_TYPE_GENEVE:
7969 flow_dv_translate_item_geneve(match_mask, match_value,
7971 matcher.priority = flow->rss.level >= 2 ?
7972 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7973 last_item = MLX5_FLOW_LAYER_GENEVE;
7975 case RTE_FLOW_ITEM_TYPE_MPLS:
7976 flow_dv_translate_item_mpls(match_mask, match_value,
7977 items, last_item, tunnel);
7978 matcher.priority = flow->rss.level >= 2 ?
7979 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7980 last_item = MLX5_FLOW_LAYER_MPLS;
7982 case RTE_FLOW_ITEM_TYPE_MARK:
7983 flow_dv_translate_item_mark(dev, match_mask,
7984 match_value, items);
7985 last_item = MLX5_FLOW_ITEM_MARK;
7987 case RTE_FLOW_ITEM_TYPE_META:
7988 flow_dv_translate_item_meta(dev, match_mask,
7989 match_value, attr, items);
7990 last_item = MLX5_FLOW_ITEM_METADATA;
7992 case RTE_FLOW_ITEM_TYPE_ICMP:
7993 flow_dv_translate_item_icmp(match_mask, match_value,
7995 last_item = MLX5_FLOW_LAYER_ICMP;
7997 case RTE_FLOW_ITEM_TYPE_ICMP6:
7998 flow_dv_translate_item_icmp6(match_mask, match_value,
8000 last_item = MLX5_FLOW_LAYER_ICMP6;
8002 case RTE_FLOW_ITEM_TYPE_TAG:
8003 flow_dv_translate_item_tag(dev, match_mask,
8004 match_value, items);
8005 last_item = MLX5_FLOW_ITEM_TAG;
8007 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8008 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8009 match_value, items);
8010 last_item = MLX5_FLOW_ITEM_TAG;
8012 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8013 flow_dv_translate_item_tx_queue(dev, match_mask,
8016 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8018 case RTE_FLOW_ITEM_TYPE_GTP:
8019 flow_dv_translate_item_gtp(match_mask, match_value,
8021 matcher.priority = flow->rss.level >= 2 ?
8022 MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8023 last_item = MLX5_FLOW_LAYER_GTP;
8028 item_flags |= last_item;
8031 * When E-Switch mode is enabled, we have two cases where we need to
8032 * set the source port manually.
8033 * The first one, is in case of Nic steering rule, and the second is
8034 * E-Switch rule where no port_id item was found. In both cases
8035 * the source port is set according the current port in use.
8037 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8038 (priv->representor || priv->master)) {
8039 if (flow_dv_translate_item_port_id(dev, match_mask,
8043 #ifdef RTE_LIBRTE_MLX5_DEBUG
8044 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8045 dev_flow->dv.value.buf));
8048 * Layers may be already initialized from prefix flow if this dev_flow
8049 * is the suffix flow.
8051 handle->layers |= item_flags;
8052 if (action_flags & MLX5_FLOW_ACTION_RSS)
8053 flow_dv_hashfields_set(dev_flow);
8054 /* Register matcher. */
8055 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8057 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8059 /* reserved field no needs to be set to 0 here. */
8060 tbl_key.domain = attr->transfer;
8061 tbl_key.direction = attr->egress;
8062 tbl_key.table_id = dev_flow->dv.group;
8063 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8069 * Apply the flow to the NIC, lock free,
8070 * (mutex should be acquired by caller).
8073 * Pointer to the Ethernet device structure.
8074 * @param[in, out] flow
8075 * Pointer to flow structure.
8077 * Pointer to error structure.
8080 * 0 on success, a negative errno value otherwise and rte_errno is set.
8083 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8084 struct rte_flow_error *error)
8086 struct mlx5_flow_dv_workspace *dv;
8087 struct mlx5_flow_handle *dh;
8088 struct mlx5_flow_handle_dv *dv_h;
8089 struct mlx5_flow *dev_flow;
8090 struct mlx5_priv *priv = dev->data->dev_private;
8095 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8096 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8098 dh = dev_flow->handle;
8101 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8103 dv->actions[n++] = priv->sh->esw_drop_action;
8105 dh->hrxq = mlx5_hrxq_drop_new(dev);
8109 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8111 "cannot get drop hash queue");
8114 dv->actions[n++] = dh->hrxq->action;
8116 } else if (dh->act_flags &
8117 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8118 struct mlx5_hrxq *hrxq;
8120 MLX5_ASSERT(flow->rss.queue);
8121 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8122 MLX5_RSS_HASH_KEY_LEN,
8123 dev_flow->hash_fields,
8125 flow->rss.queue_num);
8127 hrxq = mlx5_hrxq_new
8128 (dev, flow->rss.key,
8129 MLX5_RSS_HASH_KEY_LEN,
8130 dev_flow->hash_fields,
8132 flow->rss.queue_num,
8134 MLX5_FLOW_LAYER_TUNNEL));
8139 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8140 "cannot get hash queue");
8144 dv->actions[n++] = dh->hrxq->action;
8147 mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8148 (void *)&dv->value, n,
8151 rte_flow_error_set(error, errno,
8152 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8154 "hardware refuses to create flow");
8157 if (priv->vmwa_context &&
8158 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8160 * The rule contains the VLAN pattern.
8161 * For VF we are going to create VLAN
8162 * interface to make hypervisor set correct
8163 * e-Switch vport context.
8165 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8170 err = rte_errno; /* Save rte_errno before cleanup. */
8171 LIST_FOREACH(dh, &flow->dev_handles, next) {
8173 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8174 mlx5_hrxq_drop_release(dev);
8176 mlx5_hrxq_release(dev, dh->hrxq);
8179 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8180 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8182 rte_errno = err; /* Restore rte_errno. */
8187 * Release the flow matcher.
8190 * Pointer to Ethernet device.
8192 * Pointer to mlx5_flow_handle.
8195 * 1 while a reference on it exists, 0 when freed.
8198 flow_dv_matcher_release(struct rte_eth_dev *dev,
8199 struct mlx5_flow_handle *handle)
8201 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8203 MLX5_ASSERT(matcher->matcher_object);
8204 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8205 dev->data->port_id, (void *)matcher,
8206 rte_atomic32_read(&matcher->refcnt));
8207 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8208 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8209 (matcher->matcher_object));
8210 LIST_REMOVE(matcher, next);
8211 /* table ref-- in release interface. */
8212 flow_dv_tbl_resource_release(dev, matcher->tbl);
8214 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8215 dev->data->port_id, (void *)matcher);
8222 * Release an encap/decap resource.
8225 * Pointer to Ethernet device.
8227 * Pointer to mlx5_flow_handle.
8230 * 1 while a reference on it exists, 0 when freed.
8233 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8234 struct mlx5_flow_handle *handle)
8236 struct mlx5_priv *priv = dev->data->dev_private;
8237 uint32_t idx = handle->dvh.encap_decap;
8238 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8240 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8242 if (!cache_resource)
8244 MLX5_ASSERT(cache_resource->verbs_action);
8245 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8246 (void *)cache_resource,
8247 rte_atomic32_read(&cache_resource->refcnt));
8248 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8249 claim_zero(mlx5_glue->destroy_flow_action
8250 (cache_resource->verbs_action));
8251 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8252 &priv->sh->encaps_decaps, idx,
8253 cache_resource, next);
8254 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8255 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8256 (void *)cache_resource);
8263 * Release an jump to table action resource.
8266 * Pointer to Ethernet device.
8268 * Pointer to mlx5_flow_handle.
8271 * 1 while a reference on it exists, 0 when freed.
8274 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8275 struct mlx5_flow_handle *handle)
8277 struct mlx5_priv *priv = dev->data->dev_private;
8278 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8279 struct mlx5_flow_tbl_data_entry *tbl_data;
8281 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8285 cache_resource = &tbl_data->jump;
8286 MLX5_ASSERT(cache_resource->action);
8287 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8288 (void *)cache_resource,
8289 rte_atomic32_read(&cache_resource->refcnt));
8290 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8291 claim_zero(mlx5_glue->destroy_flow_action
8292 (cache_resource->action));
8293 /* jump action memory free is inside the table release. */
8294 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8295 DRV_LOG(DEBUG, "jump table resource %p: removed",
8296 (void *)cache_resource);
8303 * Release a modify-header resource.
8306 * Pointer to mlx5_flow_handle.
8309 * 1 while a reference on it exists, 0 when freed.
8312 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8314 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8315 handle->dvh.modify_hdr;
8317 MLX5_ASSERT(cache_resource->verbs_action);
8318 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8319 (void *)cache_resource,
8320 rte_atomic32_read(&cache_resource->refcnt));
8321 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8322 claim_zero(mlx5_glue->destroy_flow_action
8323 (cache_resource->verbs_action));
8324 LIST_REMOVE(cache_resource, next);
8325 rte_free(cache_resource);
8326 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8327 (void *)cache_resource);
8334 * Release port ID action resource.
8337 * Pointer to Ethernet device.
8339 * Pointer to mlx5_flow_handle.
8342 * 1 while a reference on it exists, 0 when freed.
8345 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8346 struct mlx5_flow_handle *handle)
8348 struct mlx5_priv *priv = dev->data->dev_private;
8349 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8350 uint32_t idx = handle->dvh.port_id_action;
8352 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8354 if (!cache_resource)
8356 MLX5_ASSERT(cache_resource->action);
8357 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8358 (void *)cache_resource,
8359 rte_atomic32_read(&cache_resource->refcnt));
8360 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8361 claim_zero(mlx5_glue->destroy_flow_action
8362 (cache_resource->action));
8363 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8364 &priv->sh->port_id_action_list, idx,
8365 cache_resource, next);
8366 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8367 DRV_LOG(DEBUG, "port id action resource %p: removed",
8368 (void *)cache_resource);
8375 * Release push vlan action resource.
8378 * Pointer to Ethernet device.
8380 * Pointer to mlx5_flow_handle.
8383 * 1 while a reference on it exists, 0 when freed.
8386 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8387 struct mlx5_flow_handle *handle)
8389 struct mlx5_priv *priv = dev->data->dev_private;
8390 uint32_t idx = handle->dvh.push_vlan_res;
8391 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8393 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8395 if (!cache_resource)
8397 MLX5_ASSERT(cache_resource->action);
8398 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8399 (void *)cache_resource,
8400 rte_atomic32_read(&cache_resource->refcnt));
8401 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8402 claim_zero(mlx5_glue->destroy_flow_action
8403 (cache_resource->action));
8404 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8405 &priv->sh->push_vlan_action_list, idx,
8406 cache_resource, next);
8407 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8408 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8409 (void *)cache_resource);
8416 * Remove the flow from the NIC but keeps it in memory.
8417 * Lock free, (mutex should be acquired by caller).
8420 * Pointer to Ethernet device.
8421 * @param[in, out] flow
8422 * Pointer to flow structure.
8425 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8427 struct mlx5_flow_handle *dh;
8431 LIST_FOREACH(dh, &flow->dev_handles, next) {
8433 claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8437 if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8438 mlx5_hrxq_drop_release(dev);
8440 mlx5_hrxq_release(dev, dh->hrxq);
8443 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8444 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8449 * Remove the flow from the NIC and the memory.
8450 * Lock free, (mutex should be acquired by caller).
8453 * Pointer to the Ethernet device structure.
8454 * @param[in, out] flow
8455 * Pointer to flow structure.
8458 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8460 struct mlx5_flow_handle *dev_handle;
8464 __flow_dv_remove(dev, flow);
8465 if (flow->counter) {
8466 flow_dv_counter_release(dev, flow->counter);
8470 mlx5_flow_meter_detach(flow->meter);
8473 while (!LIST_EMPTY(&flow->dev_handles)) {
8474 dev_handle = LIST_FIRST(&flow->dev_handles);
8475 LIST_REMOVE(dev_handle, next);
8476 if (dev_handle->dvh.matcher)
8477 flow_dv_matcher_release(dev, dev_handle);
8478 if (dev_handle->dvh.encap_decap)
8479 flow_dv_encap_decap_resource_release(dev, dev_handle);
8480 if (dev_handle->dvh.modify_hdr)
8481 flow_dv_modify_hdr_resource_release(dev_handle);
8482 if (dev_handle->dvh.jump)
8483 flow_dv_jump_tbl_resource_release(dev, dev_handle);
8484 if (dev_handle->dvh.port_id_action)
8485 flow_dv_port_id_action_resource_release(dev,
8487 if (dev_handle->dvh.push_vlan_res)
8488 flow_dv_push_vlan_action_resource_release(dev,
8490 if (dev_handle->dvh.tag_resource)
8491 flow_dv_tag_release(dev,
8492 dev_handle->dvh.tag_resource);
8493 rte_free(dev_handle);
8498 * Query a dv flow rule for its statistics via devx.
8501 * Pointer to Ethernet device.
8503 * Pointer to the sub flow.
8505 * data retrieved by the query.
8507 * Perform verbose error reporting if not NULL.
8510 * 0 on success, a negative errno value otherwise and rte_errno is set.
8513 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8514 void *data, struct rte_flow_error *error)
8516 struct mlx5_priv *priv = dev->data->dev_private;
8517 struct rte_flow_query_count *qc = data;
8519 if (!priv->config.devx)
8520 return rte_flow_error_set(error, ENOTSUP,
8521 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8523 "counters are not supported");
8524 if (flow->counter) {
8525 uint64_t pkts, bytes;
8526 struct mlx5_flow_counter *cnt;
8528 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
8530 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8534 return rte_flow_error_set(error, -err,
8535 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8536 NULL, "cannot read counters");
8539 qc->hits = pkts - cnt->hits;
8540 qc->bytes = bytes - cnt->bytes;
8547 return rte_flow_error_set(error, EINVAL,
8548 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8550 "counters are not available");
8556 * @see rte_flow_query()
8560 flow_dv_query(struct rte_eth_dev *dev,
8561 struct rte_flow *flow __rte_unused,
8562 const struct rte_flow_action *actions __rte_unused,
8563 void *data __rte_unused,
8564 struct rte_flow_error *error __rte_unused)
8568 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8569 switch (actions->type) {
8570 case RTE_FLOW_ACTION_TYPE_VOID:
8572 case RTE_FLOW_ACTION_TYPE_COUNT:
8573 ret = flow_dv_query_count(dev, flow, data, error);
8576 return rte_flow_error_set(error, ENOTSUP,
8577 RTE_FLOW_ERROR_TYPE_ACTION,
8579 "action not supported");
8586 * Destroy the meter table set.
8587 * Lock free, (mutex should be acquired by caller).
8590 * Pointer to Ethernet device.
8592 * Pointer to the meter table set.
8598 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8599 struct mlx5_meter_domains_infos *tbl)
8601 struct mlx5_priv *priv = dev->data->dev_private;
8602 struct mlx5_meter_domains_infos *mtd =
8603 (struct mlx5_meter_domains_infos *)tbl;
8605 if (!mtd || !priv->config.dv_flow_en)
8607 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8608 claim_zero(mlx5_glue->dv_destroy_flow
8609 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8610 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8611 claim_zero(mlx5_glue->dv_destroy_flow
8612 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8613 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8614 claim_zero(mlx5_glue->dv_destroy_flow
8615 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8616 if (mtd->egress.color_matcher)
8617 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8618 (mtd->egress.color_matcher));
8619 if (mtd->egress.any_matcher)
8620 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8621 (mtd->egress.any_matcher));
8622 if (mtd->egress.tbl)
8623 claim_zero(flow_dv_tbl_resource_release(dev,
8625 if (mtd->egress.sfx_tbl)
8626 claim_zero(flow_dv_tbl_resource_release(dev,
8627 mtd->egress.sfx_tbl));
8628 if (mtd->ingress.color_matcher)
8629 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8630 (mtd->ingress.color_matcher));
8631 if (mtd->ingress.any_matcher)
8632 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8633 (mtd->ingress.any_matcher));
8634 if (mtd->ingress.tbl)
8635 claim_zero(flow_dv_tbl_resource_release(dev,
8637 if (mtd->ingress.sfx_tbl)
8638 claim_zero(flow_dv_tbl_resource_release(dev,
8639 mtd->ingress.sfx_tbl));
8640 if (mtd->transfer.color_matcher)
8641 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8642 (mtd->transfer.color_matcher));
8643 if (mtd->transfer.any_matcher)
8644 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8645 (mtd->transfer.any_matcher));
8646 if (mtd->transfer.tbl)
8647 claim_zero(flow_dv_tbl_resource_release(dev,
8648 mtd->transfer.tbl));
8649 if (mtd->transfer.sfx_tbl)
8650 claim_zero(flow_dv_tbl_resource_release(dev,
8651 mtd->transfer.sfx_tbl));
8653 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8658 /* Number of meter flow actions, count and jump or count and drop. */
8659 #define METER_ACTIONS 2
8662 * Create specify domain meter table and suffix table.
8665 * Pointer to Ethernet device.
8666 * @param[in,out] mtb
8667 * Pointer to DV meter table set.
8670 * @param[in] transfer
8672 * @param[in] color_reg_c_idx
8673 * Reg C index for color match.
8676 * 0 on success, -1 otherwise and rte_errno is set.
8679 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8680 struct mlx5_meter_domains_infos *mtb,
8681 uint8_t egress, uint8_t transfer,
8682 uint32_t color_reg_c_idx)
8684 struct mlx5_priv *priv = dev->data->dev_private;
8685 struct mlx5_ibv_shared *sh = priv->sh;
8686 struct mlx5_flow_dv_match_params mask = {
8687 .size = sizeof(mask.buf),
8689 struct mlx5_flow_dv_match_params value = {
8690 .size = sizeof(value.buf),
8692 struct mlx5dv_flow_matcher_attr dv_attr = {
8693 .type = IBV_FLOW_ATTR_NORMAL,
8695 .match_criteria_enable = 0,
8696 .match_mask = (void *)&mask,
8698 void *actions[METER_ACTIONS];
8699 struct mlx5_meter_domain_info *dtb;
8700 struct rte_flow_error error;
8704 dtb = &mtb->transfer;
8708 dtb = &mtb->ingress;
8709 /* Create the meter table with METER level. */
8710 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8711 egress, transfer, &error);
8713 DRV_LOG(ERR, "Failed to create meter policer table.");
8716 /* Create the meter suffix table with SUFFIX level. */
8717 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
8718 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8719 egress, transfer, &error);
8720 if (!dtb->sfx_tbl) {
8721 DRV_LOG(ERR, "Failed to create meter suffix table.");
8724 /* Create matchers, Any and Color. */
8725 dv_attr.priority = 3;
8726 dv_attr.match_criteria_enable = 0;
8727 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8730 if (!dtb->any_matcher) {
8731 DRV_LOG(ERR, "Failed to create meter"
8732 " policer default matcher.");
8735 dv_attr.priority = 0;
8736 dv_attr.match_criteria_enable =
8737 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8738 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8739 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8740 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8743 if (!dtb->color_matcher) {
8744 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8747 if (mtb->count_actns[RTE_MTR_DROPPED])
8748 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8749 actions[i++] = mtb->drop_actn;
8750 /* Default rule: lowest priority, match any, actions: drop. */
8751 dtb->policer_rules[RTE_MTR_DROPPED] =
8752 mlx5_glue->dv_create_flow(dtb->any_matcher,
8753 (void *)&value, i, actions);
8754 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8755 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8764 * Create the needed meter and suffix tables.
8765 * Lock free, (mutex should be acquired by caller).
8768 * Pointer to Ethernet device.
8770 * Pointer to the flow meter.
8773 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8775 static struct mlx5_meter_domains_infos *
8776 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8777 const struct mlx5_flow_meter *fm)
8779 struct mlx5_priv *priv = dev->data->dev_private;
8780 struct mlx5_meter_domains_infos *mtb;
8784 if (!priv->mtr_en) {
8785 rte_errno = ENOTSUP;
8788 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8790 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8793 /* Create meter count actions */
8794 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8795 struct mlx5_flow_counter *cnt;
8796 if (!fm->policer_stats.cnt[i])
8798 cnt = flow_dv_counter_get_by_idx(dev,
8799 fm->policer_stats.cnt[i], NULL);
8800 mtb->count_actns[i] = cnt->action;
8802 /* Create drop action. */
8803 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8804 if (!mtb->drop_actn) {
8805 DRV_LOG(ERR, "Failed to create drop action.");
8808 /* Egress meter table. */
8809 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8811 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8814 /* Ingress meter table. */
8815 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8817 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8820 /* FDB meter table. */
8821 if (priv->config.dv_esw_en) {
8822 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8823 priv->mtr_color_reg);
8825 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8831 flow_dv_destroy_mtr_tbl(dev, mtb);
8836 * Destroy domain policer rule.
8839 * Pointer to domain table.
8842 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8846 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8847 if (dt->policer_rules[i]) {
8848 claim_zero(mlx5_glue->dv_destroy_flow
8849 (dt->policer_rules[i]));
8850 dt->policer_rules[i] = NULL;
8853 if (dt->jump_actn) {
8854 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8855 dt->jump_actn = NULL;
8860 * Destroy policer rules.
8863 * Pointer to Ethernet device.
8865 * Pointer to flow meter structure.
8867 * Pointer to flow attributes.
8873 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8874 const struct mlx5_flow_meter *fm,
8875 const struct rte_flow_attr *attr)
8877 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8882 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8884 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8886 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8891 * Create specify domain meter policer rule.
8894 * Pointer to flow meter structure.
8896 * Pointer to DV meter table set.
8897 * @param[in] mtr_reg_c
8898 * Color match REG_C.
8901 * 0 on success, -1 otherwise.
8904 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8905 struct mlx5_meter_domain_info *dtb,
8908 struct mlx5_flow_dv_match_params matcher = {
8909 .size = sizeof(matcher.buf),
8911 struct mlx5_flow_dv_match_params value = {
8912 .size = sizeof(value.buf),
8914 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8915 void *actions[METER_ACTIONS];
8918 /* Create jump action. */
8919 if (!dtb->jump_actn)
8921 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8922 (dtb->sfx_tbl->obj);
8923 if (!dtb->jump_actn) {
8924 DRV_LOG(ERR, "Failed to create policer jump action.");
8927 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8930 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8931 rte_col_2_mlx5_col(i), UINT8_MAX);
8932 if (mtb->count_actns[i])
8933 actions[j++] = mtb->count_actns[i];
8934 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8935 actions[j++] = mtb->drop_actn;
8937 actions[j++] = dtb->jump_actn;
8938 dtb->policer_rules[i] =
8939 mlx5_glue->dv_create_flow(dtb->color_matcher,
8942 if (!dtb->policer_rules[i]) {
8943 DRV_LOG(ERR, "Failed to create policer rule.");
8954 * Create policer rules.
8957 * Pointer to Ethernet device.
8959 * Pointer to flow meter structure.
8961 * Pointer to flow attributes.
8964 * 0 on success, -1 otherwise.
8967 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8968 struct mlx5_flow_meter *fm,
8969 const struct rte_flow_attr *attr)
8971 struct mlx5_priv *priv = dev->data->dev_private;
8972 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8976 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8977 priv->mtr_color_reg);
8979 DRV_LOG(ERR, "Failed to create egress policer.");
8983 if (attr->ingress) {
8984 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8985 priv->mtr_color_reg);
8987 DRV_LOG(ERR, "Failed to create ingress policer.");
8991 if (attr->transfer) {
8992 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8993 priv->mtr_color_reg);
8995 DRV_LOG(ERR, "Failed to create transfer policer.");
9001 flow_dv_destroy_policer_rules(dev, fm, attr);
9006 * Query a devx counter.
9009 * Pointer to the Ethernet device structure.
9011 * Index to the flow counter.
9013 * Set to clear the counter statistics.
9015 * The statistics value of packets.
9017 * The statistics value of bytes.
9020 * 0 on success, otherwise return -1.
9023 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9024 uint64_t *pkts, uint64_t *bytes)
9026 struct mlx5_priv *priv = dev->data->dev_private;
9027 struct mlx5_flow_counter *cnt;
9028 uint64_t inn_pkts, inn_bytes;
9031 if (!priv->config.devx)
9034 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9037 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9038 *pkts = inn_pkts - cnt->hits;
9039 *bytes = inn_bytes - cnt->bytes;
9041 cnt->hits = inn_pkts;
9042 cnt->bytes = inn_bytes;
9048 * Mutex-protected thunk to lock-free __flow_dv_translate().
9051 flow_dv_translate(struct rte_eth_dev *dev,
9052 struct mlx5_flow *dev_flow,
9053 const struct rte_flow_attr *attr,
9054 const struct rte_flow_item items[],
9055 const struct rte_flow_action actions[],
9056 struct rte_flow_error *error)
9060 flow_dv_shared_lock(dev);
9061 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9062 flow_dv_shared_unlock(dev);
9067 * Mutex-protected thunk to lock-free __flow_dv_apply().
9070 flow_dv_apply(struct rte_eth_dev *dev,
9071 struct rte_flow *flow,
9072 struct rte_flow_error *error)
9076 flow_dv_shared_lock(dev);
9077 ret = __flow_dv_apply(dev, flow, error);
9078 flow_dv_shared_unlock(dev);
9083 * Mutex-protected thunk to lock-free __flow_dv_remove().
9086 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9088 flow_dv_shared_lock(dev);
9089 __flow_dv_remove(dev, flow);
9090 flow_dv_shared_unlock(dev);
9094 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9097 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9099 flow_dv_shared_lock(dev);
9100 __flow_dv_destroy(dev, flow);
9101 flow_dv_shared_unlock(dev);
9105 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9108 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9112 flow_dv_shared_lock(dev);
9113 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9114 flow_dv_shared_unlock(dev);
9119 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9122 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9124 flow_dv_shared_lock(dev);
9125 flow_dv_counter_release(dev, cnt);
9126 flow_dv_shared_unlock(dev);
9129 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9130 .validate = flow_dv_validate,
9131 .prepare = flow_dv_prepare,
9132 .translate = flow_dv_translate,
9133 .apply = flow_dv_apply,
9134 .remove = flow_dv_remove,
9135 .destroy = flow_dv_destroy,
9136 .query = flow_dv_query,
9137 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9138 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9139 .create_policer_rules = flow_dv_create_policer_rules,
9140 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9141 .counter_alloc = flow_dv_counter_allocate,
9142 .counter_free = flow_dv_counter_free,
9143 .counter_query = flow_dv_counter_query,
9146 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */