drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_cycles.h>
  28 #include <rte_ip.h>
  29 #include <rte_gre.h>
  30 #include <rte_vxlan.h>
  31 #include <rte_gtp.h>
  32
  33 #include <mlx5_glue.h>
  34 #include <mlx5_devx_cmds.h>
  35 #include <mlx5_prm.h>
  36
  37 #include "mlx5_defs.h"
  38 #include "mlx5.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_rxtx.h"
  41
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43
  44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  46 #endif
  47
  48 #ifndef HAVE_MLX5DV_DR_ESWITCH
  49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  51 #endif
  52 #endif
  53
  54 #ifndef HAVE_MLX5DV_DR
  55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  56 #endif
  57
  58 /* VLAN header definitions */
  59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  64
  65 union flow_dv_attr {
  66         struct {
  67                 uint32_t valid:1;
  68                 uint32_t ipv4:1;
  69                 uint32_t ipv6:1;
  70                 uint32_t tcp:1;
  71                 uint32_t udp:1;
  72                 uint32_t reserved:27;
  73         };
  74         uint32_t attr;
  75 };
  76
  77 static int
  78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  79                              struct mlx5_flow_tbl_resource *tbl);
  80
  81 /**
  82  * Initialize flow attributes structure according to flow items' types.
  83  *
  84  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  85  * mode. For tunnel mode, the items to be modified are the outermost ones.
  86  *
  87  * @param[in] item
  88  *   Pointer to item specification.
  89  * @param[out] attr
  90  *   Pointer to flow attributes structure.
  91  * @param[in] dev_flow
  92  *   Pointer to the sub flow.
  93  * @param[in] tunnel_decap
  94  *   Whether action is after tunnel decapsulation.
  95  */
  96 static void
  97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  98                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  99 {
 100         uint64_t layers = dev_flow->handle->layers;
 101
 102         /*
 103          * If layers is already initialized, it means this dev_flow is the
 104          * suffix flow, the layers flags is set by the prefix flow. Need to
 105          * use the layer flags from prefix flow as the suffix flow may not
 106          * have the user defined items as the flow is split.
 107          */
 108         if (layers) {
 109                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 110                         attr->ipv4 = 1;
 111                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 112                         attr->ipv6 = 1;
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 114                         attr->tcp = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 116                         attr->udp = 1;
 117                 attr->valid = 1;
 118                 return;
 119         }
 120         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 121                 uint8_t next_protocol = 0xff;
 122                 switch (item->type) {
 123                 case RTE_FLOW_ITEM_TYPE_GRE:
 124                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 126                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 127                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 128                 case RTE_FLOW_ITEM_TYPE_MPLS:
 129                         if (tunnel_decap)
 130                                 attr->attr = 0;
 131                         break;
 132                 case RTE_FLOW_ITEM_TYPE_IPV4:
 133                         if (!attr->ipv6)
 134                                 attr->ipv4 = 1;
 135                         if (item->mask != NULL &&
 136                             ((const struct rte_flow_item_ipv4 *)
 137                             item->mask)->hdr.next_proto_id)
 138                                 next_protocol =
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->spec))->hdr.next_proto_id &
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->mask))->hdr.next_proto_id;
 143                         if ((next_protocol == IPPROTO_IPIP ||
 144                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 145                                 attr->attr = 0;
 146                         break;
 147                 case RTE_FLOW_ITEM_TYPE_IPV6:
 148                         if (!attr->ipv4)
 149                                 attr->ipv6 = 1;
 150                         if (item->mask != NULL &&
 151                             ((const struct rte_flow_item_ipv6 *)
 152                             item->mask)->hdr.proto)
 153                                 next_protocol =
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->spec))->hdr.proto &
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->mask))->hdr.proto;
 158                         if ((next_protocol == IPPROTO_IPIP ||
 159                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 160                                 attr->attr = 0;
 161                         break;
 162                 case RTE_FLOW_ITEM_TYPE_UDP:
 163                         if (!attr->tcp)
 164                                 attr->udp = 1;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_TCP:
 167                         if (!attr->udp)
 168                                 attr->tcp = 1;
 169                         break;
 170                 default:
 171                         break;
 172                 }
 173         }
 174         attr->valid = 1;
 175 }
 176
 177 /**
 178  * Convert rte_mtr_color to mlx5 color.
 179  *
 180  * @param[in] rcol
 181  *   rte_mtr_color.
 182  *
 183  * @return
 184  *   mlx5 color.
 185  */
 186 static int
 187 rte_col_2_mlx5_col(enum rte_color rcol)
 188 {
 189         switch (rcol) {
 190         case RTE_COLOR_GREEN:
 191                 return MLX5_FLOW_COLOR_GREEN;
 192         case RTE_COLOR_YELLOW:
 193                 return MLX5_FLOW_COLOR_YELLOW;
 194         case RTE_COLOR_RED:
 195                 return MLX5_FLOW_COLOR_RED;
 196         default:
 197                 break;
 198         }
 199         return MLX5_FLOW_COLOR_UNDEFINED;
 200 }
 201
 202 struct field_modify_info {
 203         uint32_t size; /* Size of field in protocol header, in bytes. */
 204         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 205         enum mlx5_modification_field id;
 206 };
 207
 208 struct field_modify_info modify_eth[] = {
 209         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 210         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 211         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 212         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_vlan_out_first_vid[] = {
 217         /* Size in bits !!! */
 218         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_ipv4[] = {
 223         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 224         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 225         {4, 12, MLX5_MODI_OUT_SIPV4},
 226         {4, 16, MLX5_MODI_OUT_DIPV4},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_ipv6[] = {
 231         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 232         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 233         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 234         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 235         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 236         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 237         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 238         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 239         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 240         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 241         {0, 0, 0},
 242 };
 243
 244 struct field_modify_info modify_udp[] = {
 245         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 246         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_tcp[] = {
 251         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 253         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 254         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 255         {0, 0, 0},
 256 };
 257
 258 static void
 259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 260                           uint8_t next_protocol, uint64_t *item_flags,
 261                           int *tunnel)
 262 {
 263         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 264                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 265         if (next_protocol == IPPROTO_IPIP) {
 266                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 267                 *tunnel = 1;
 268         }
 269         if (next_protocol == IPPROTO_IPV6) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 271                 *tunnel = 1;
 272         }
 273 }
 274
 275 /**
 276  * Acquire the synchronizing object to protect multithreaded access
 277  * to shared dv context. Lock occurs only if context is actually
 278  * shared, i.e. we have multiport IB device and representors are
 279  * created.
 280  *
 281  * @param[in] dev
 282  *   Pointer to the rte_eth_dev structure.
 283  */
 284 static void
 285 flow_dv_shared_lock(struct rte_eth_dev *dev)
 286 {
 287         struct mlx5_priv *priv = dev->data->dev_private;
 288         struct mlx5_dev_ctx_shared *sh = priv->sh;
 289
 290         if (sh->dv_refcnt > 1) {
 291                 int ret;
 292
 293                 ret = pthread_mutex_lock(&sh->dv_mutex);
 294                 MLX5_ASSERT(!ret);
 295                 (void)ret;
 296         }
 297 }
 298
 299 static void
 300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 301 {
 302         struct mlx5_priv *priv = dev->data->dev_private;
 303         struct mlx5_dev_ctx_shared *sh = priv->sh;
 304
 305         if (sh->dv_refcnt > 1) {
 306                 int ret;
 307
 308                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 309                 MLX5_ASSERT(!ret);
 310                 (void)ret;
 311         }
 312 }
 313
 314 /* Update VLAN's VID/PCP based on input rte_flow_action.
 315  *
 316  * @param[in] action
 317  *   Pointer to struct rte_flow_action.
 318  * @param[out] vlan
 319  *   Pointer to struct rte_vlan_hdr.
 320  */
 321 static void
 322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 323                          struct rte_vlan_hdr *vlan)
 324 {
 325         uint16_t vlan_tci;
 326         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 327                 vlan_tci =
 328                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 329                                                action->conf)->vlan_pcp;
 330                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 331                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 332                 vlan->vlan_tci |= vlan_tci;
 333         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 334                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 335                 vlan->vlan_tci |= rte_be_to_cpu_16
 336                     (((const struct rte_flow_action_of_set_vlan_vid *)
 337                                              action->conf)->vlan_vid);
 338         }
 339 }
 340
 341 /**
 342  * Fetch 1, 2, 3 or 4 byte field from the byte array
 343  * and return as unsigned integer in host-endian format.
 344  *
 345  * @param[in] data
 346  *   Pointer to data array.
 347  * @param[in] size
 348  *   Size of field to extract.
 349  *
 350  * @return
 351  *   converted field in host endian format.
 352  */
 353 static inline uint32_t
 354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 355 {
 356         uint32_t ret;
 357
 358         switch (size) {
 359         case 1:
 360                 ret = *data;
 361                 break;
 362         case 2:
 363                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 364                 break;
 365         case 3:
 366                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 367                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 368                 break;
 369         case 4:
 370                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 371                 break;
 372         default:
 373                 MLX5_ASSERT(false);
 374                 ret = 0;
 375                 break;
 376         }
 377         return ret;
 378 }
 379
 380 /**
 381  * Convert modify-header action to DV specification.
 382  *
 383  * Data length of each action is determined by provided field description
 384  * and the item mask. Data bit offset and width of each action is determined
 385  * by provided item mask.
 386  *
 387  * @param[in] item
 388  *   Pointer to item specification.
 389  * @param[in] field
 390  *   Pointer to field modification information.
 391  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 393  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 394  * @param[in] dcopy
 395  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 396  *   Negative offset value sets the same offset as source offset.
 397  *   size field is ignored, value is taken from source field.
 398  * @param[in,out] resource
 399  *   Pointer to the modify-header resource.
 400  * @param[in] type
 401  *   Type of modification.
 402  * @param[out] error
 403  *   Pointer to the error structure.
 404  *
 405  * @return
 406  *   0 on success, a negative errno value otherwise and rte_errno is set.
 407  */
 408 static int
 409 flow_dv_convert_modify_action(struct rte_flow_item *item,
 410                               struct field_modify_info *field,
 411                               struct field_modify_info *dcopy,
 412                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 413                               uint32_t type, struct rte_flow_error *error)
 414 {
 415         uint32_t i = resource->actions_num;
 416         struct mlx5_modification_cmd *actions = resource->actions;
 417
 418         /*
 419          * The item and mask are provided in big-endian format.
 420          * The fields should be presented as in big-endian format either.
 421          * Mask must be always present, it defines the actual field width.
 422          */
 423         MLX5_ASSERT(item->mask);
 424         MLX5_ASSERT(field->size);
 425         do {
 426                 unsigned int size_b;
 427                 unsigned int off_b;
 428                 uint32_t mask;
 429                 uint32_t data;
 430
 431                 if (i >= MLX5_MAX_MODIFY_NUM)
 432                         return rte_flow_error_set(error, EINVAL,
 433                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 434                                  "too many items to modify");
 435                 /* Fetch variable byte size mask from the array. */
 436                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 437                                            field->offset, field->size);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /**
1643  * Validate VLAN item.
1644  *
1645  * @param[in] item
1646  *   Item specification.
1647  * @param[in] item_flags
1648  *   Bit-fields that holds the items detected until now.
1649  * @param[in] dev
1650  *   Ethernet device flow is being created on.
1651  * @param[out] error
1652  *   Pointer to error structure.
1653  *
1654  * @return
1655  *   0 on success, a negative errno value otherwise and rte_errno is set.
1656  */
1657 static int
1658 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1659                            uint64_t item_flags,
1660                            struct rte_eth_dev *dev,
1661                            struct rte_flow_error *error)
1662 {
1663         const struct rte_flow_item_vlan *mask = item->mask;
1664         const struct rte_flow_item_vlan nic_mask = {
1665                 .tci = RTE_BE16(UINT16_MAX),
1666                 .inner_type = RTE_BE16(UINT16_MAX),
1667         };
1668         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1669         int ret;
1670         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1671                                         MLX5_FLOW_LAYER_INNER_L4) :
1672                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1673                                         MLX5_FLOW_LAYER_OUTER_L4);
1674         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1675                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1676
1677         if (item_flags & vlanm)
1678                 return rte_flow_error_set(error, EINVAL,
1679                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1680                                           "multiple VLAN layers not supported");
1681         else if ((item_flags & l34m) != 0)
1682                 return rte_flow_error_set(error, EINVAL,
1683                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1684                                           "VLAN cannot follow L3/L4 layer");
1685         if (!mask)
1686                 mask = &rte_flow_item_vlan_mask;
1687         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1688                                         (const uint8_t *)&nic_mask,
1689                                         sizeof(struct rte_flow_item_vlan),
1690                                         error);
1691         if (ret)
1692                 return ret;
1693         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1694                 struct mlx5_priv *priv = dev->data->dev_private;
1695
1696                 if (priv->vmwa_context) {
1697                         /*
1698                          * Non-NULL context means we have a virtual machine
1699                          * and SR-IOV enabled, we have to create VLAN interface
1700                          * to make hypervisor to setup E-Switch vport
1701                          * context correctly. We avoid creating the multiple
1702                          * VLAN interfaces, so we cannot support VLAN tag mask.
1703                          */
1704                         return rte_flow_error_set(error, EINVAL,
1705                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1706                                                   item,
1707                                                   "VLAN tag mask is not"
1708                                                   " supported in virtual"
1709                                                   " environment");
1710                 }
1711         }
1712         return 0;
1713 }
1714
1715 /*
1716  * GTP flags are contained in 1 byte of the format:
1717  * -------------------------------------------
1718  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1719  * |-----------------------------------------|
1720  * | value | Version | PT | Res | E | S | PN |
1721  * -------------------------------------------
1722  *
1723  * Matching is supported only for GTP flags E, S, PN.
1724  */
1725 #define MLX5_GTP_FLAGS_MASK     0x07
1726
1727 /**
1728  * Validate GTP item.
1729  *
1730  * @param[in] dev
1731  *   Pointer to the rte_eth_dev structure.
1732  * @param[in] item
1733  *   Item specification.
1734  * @param[in] item_flags
1735  *   Bit-fields that holds the items detected until now.
1736  * @param[out] error
1737  *   Pointer to error structure.
1738  *
1739  * @return
1740  *   0 on success, a negative errno value otherwise and rte_errno is set.
1741  */
1742 static int
1743 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1744                           const struct rte_flow_item *item,
1745                           uint64_t item_flags,
1746                           struct rte_flow_error *error)
1747 {
1748         struct mlx5_priv *priv = dev->data->dev_private;
1749         const struct rte_flow_item_gtp *spec = item->spec;
1750         const struct rte_flow_item_gtp *mask = item->mask;
1751         const struct rte_flow_item_gtp nic_mask = {
1752                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1753                 .msg_type = 0xff,
1754                 .teid = RTE_BE32(0xffffffff),
1755         };
1756
1757         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1758                 return rte_flow_error_set(error, ENOTSUP,
1759                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1760                                           "GTP support is not enabled");
1761         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1762                 return rte_flow_error_set(error, ENOTSUP,
1763                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1764                                           "multiple tunnel layers not"
1765                                           " supported");
1766         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1767                 return rte_flow_error_set(error, EINVAL,
1768                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1769                                           "no outer UDP layer found");
1770         if (!mask)
1771                 mask = &rte_flow_item_gtp_mask;
1772         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "Match is supported for GTP"
1776                                           " flags only");
1777         return mlx5_flow_item_acceptable
1778                 (item, (const uint8_t *)mask,
1779                  (const uint8_t *)&nic_mask,
1780                  sizeof(struct rte_flow_item_gtp),
1781                  error);
1782 }
1783
1784 /**
1785  * Validate the pop VLAN action.
1786  *
1787  * @param[in] dev
1788  *   Pointer to the rte_eth_dev structure.
1789  * @param[in] action_flags
1790  *   Holds the actions detected until now.
1791  * @param[in] action
1792  *   Pointer to the pop vlan action.
1793  * @param[in] item_flags
1794  *   The items found in this flow rule.
1795  * @param[in] attr
1796  *   Pointer to flow attributes.
1797  * @param[out] error
1798  *   Pointer to error structure.
1799  *
1800  * @return
1801  *   0 on success, a negative errno value otherwise and rte_errno is set.
1802  */
1803 static int
1804 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1805                                  uint64_t action_flags,
1806                                  const struct rte_flow_action *action,
1807                                  uint64_t item_flags,
1808                                  const struct rte_flow_attr *attr,
1809                                  struct rte_flow_error *error)
1810 {
1811         const struct mlx5_priv *priv = dev->data->dev_private;
1812
1813         (void)action;
1814         (void)attr;
1815         if (!priv->sh->pop_vlan_action)
1816                 return rte_flow_error_set(error, ENOTSUP,
1817                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1818                                           NULL,
1819                                           "pop vlan action is not supported");
1820         if (attr->egress)
1821                 return rte_flow_error_set(error, ENOTSUP,
1822                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1823                                           NULL,
1824                                           "pop vlan action not supported for "
1825                                           "egress");
1826         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1829                                           "no support for multiple VLAN "
1830                                           "actions");
1831         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1834                                           NULL,
1835                                           "cannot pop vlan without a "
1836                                           "match on (outer) vlan in the flow");
1837         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1838                 return rte_flow_error_set(error, EINVAL,
1839                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1840                                           "wrong action order, port_id should "
1841                                           "be after pop VLAN action");
1842         if (!attr->transfer && priv->representor)
1843                 return rte_flow_error_set(error, ENOTSUP,
1844                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1845                                           "pop vlan action for VF representor "
1846                                           "not supported on NIC table");
1847         return 0;
1848 }
1849
1850 /**
1851  * Get VLAN default info from vlan match info.
1852  *
1853  * @param[in] items
1854  *   the list of item specifications.
1855  * @param[out] vlan
1856  *   pointer VLAN info to fill to.
1857  *
1858  * @return
1859  *   0 on success, a negative errno value otherwise and rte_errno is set.
1860  */
1861 static void
1862 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1863                                   struct rte_vlan_hdr *vlan)
1864 {
1865         const struct rte_flow_item_vlan nic_mask = {
1866                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1867                                 MLX5DV_FLOW_VLAN_VID_MASK),
1868                 .inner_type = RTE_BE16(0xffff),
1869         };
1870
1871         if (items == NULL)
1872                 return;
1873         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1874                 int type = items->type;
1875
1876                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1877                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1878                         break;
1879         }
1880         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1881                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1882                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1883
1884                 /* If VLAN item in pattern doesn't contain data, return here. */
1885                 if (!vlan_v)
1886                         return;
1887                 if (!vlan_m)
1888                         vlan_m = &nic_mask;
1889                 /* Only full match values are accepted */
1890                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1891                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1892                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1893                         vlan->vlan_tci |=
1894                                 rte_be_to_cpu_16(vlan_v->tci &
1895                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1896                 }
1897                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1898                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1899                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1900                         vlan->vlan_tci |=
1901                                 rte_be_to_cpu_16(vlan_v->tci &
1902                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1903                 }
1904                 if (vlan_m->inner_type == nic_mask.inner_type)
1905                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1906                                                            vlan_m->inner_type);
1907         }
1908 }
1909
1910 /**
1911  * Validate the push VLAN action.
1912  *
1913  * @param[in] dev
1914  *   Pointer to the rte_eth_dev structure.
1915  * @param[in] action_flags
1916  *   Holds the actions detected until now.
1917  * @param[in] item_flags
1918  *   The items found in this flow rule.
1919  * @param[in] action
1920  *   Pointer to the action structure.
1921  * @param[in] attr
1922  *   Pointer to flow attributes
1923  * @param[out] error
1924  *   Pointer to error structure.
1925  *
1926  * @return
1927  *   0 on success, a negative errno value otherwise and rte_errno is set.
1928  */
1929 static int
1930 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1931                                   uint64_t action_flags,
1932                                   const struct rte_flow_item_vlan *vlan_m,
1933                                   const struct rte_flow_action *action,
1934                                   const struct rte_flow_attr *attr,
1935                                   struct rte_flow_error *error)
1936 {
1937         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1938         const struct mlx5_priv *priv = dev->data->dev_private;
1939
1940         if (!attr->transfer && attr->ingress)
1941                 return rte_flow_error_set(error, ENOTSUP,
1942                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1943                                           NULL,
1944                                           "push VLAN action not supported for "
1945                                           "ingress");
1946         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1947             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1948                 return rte_flow_error_set(error, EINVAL,
1949                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1950                                           "invalid vlan ethertype");
1951         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1952                 return rte_flow_error_set(error, ENOTSUP,
1953                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1954                                           "no support for multiple VLAN "
1955                                           "actions");
1956         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1957                 return rte_flow_error_set(error, EINVAL,
1958                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1959                                           "wrong action order, port_id should "
1960                                           "be after push VLAN");
1961         if (!attr->transfer && priv->representor)
1962                 return rte_flow_error_set(error, ENOTSUP,
1963                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1964                                           "push vlan action for VF representor "
1965                                           "not supported on NIC table");
1966         if (vlan_m &&
1967             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1968             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1969                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1970             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1971             !(mlx5_flow_find_action
1972                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1973                 return rte_flow_error_set(error, EINVAL,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1975                                           "not full match mask on VLAN PCP and "
1976                                           "there is no of_set_vlan_pcp action, "
1977                                           "push VLAN action cannot figure out "
1978                                           "PCP value");
1979         if (vlan_m &&
1980             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1981             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1982                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1983             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1984             !(mlx5_flow_find_action
1985                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1986                 return rte_flow_error_set(error, EINVAL,
1987                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1988                                           "not full match mask on VLAN VID and "
1989                                           "there is no of_set_vlan_vid action, "
1990                                           "push VLAN action cannot figure out "
1991                                           "VID value");
1992         (void)attr;
1993         return 0;
1994 }
1995
1996 /**
1997  * Validate the set VLAN PCP.
1998  *
1999  * @param[in] action_flags
2000  *   Holds the actions detected until now.
2001  * @param[in] actions
2002  *   Pointer to the list of actions remaining in the flow rule.
2003  * @param[out] error
2004  *   Pointer to error structure.
2005  *
2006  * @return
2007  *   0 on success, a negative errno value otherwise and rte_errno is set.
2008  */
2009 static int
2010 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2011                                      const struct rte_flow_action actions[],
2012                                      struct rte_flow_error *error)
2013 {
2014         const struct rte_flow_action *action = actions;
2015         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2016
2017         if (conf->vlan_pcp > 7)
2018                 return rte_flow_error_set(error, EINVAL,
2019                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2020                                           "VLAN PCP value is too big");
2021         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2022                 return rte_flow_error_set(error, ENOTSUP,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2024                                           "set VLAN PCP action must follow "
2025                                           "the push VLAN action");
2026         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2027                 return rte_flow_error_set(error, ENOTSUP,
2028                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2029                                           "Multiple VLAN PCP modification are "
2030                                           "not supported");
2031         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2032                 return rte_flow_error_set(error, EINVAL,
2033                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2034                                           "wrong action order, port_id should "
2035                                           "be after set VLAN PCP");
2036         return 0;
2037 }
2038
2039 /**
2040  * Validate the set VLAN VID.
2041  *
2042  * @param[in] item_flags
2043  *   Holds the items detected in this rule.
2044  * @param[in] action_flags
2045  *   Holds the actions detected until now.
2046  * @param[in] actions
2047  *   Pointer to the list of actions remaining in the flow rule.
2048  * @param[out] error
2049  *   Pointer to error structure.
2050  *
2051  * @return
2052  *   0 on success, a negative errno value otherwise and rte_errno is set.
2053  */
2054 static int
2055 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2056                                      uint64_t action_flags,
2057                                      const struct rte_flow_action actions[],
2058                                      struct rte_flow_error *error)
2059 {
2060         const struct rte_flow_action *action = actions;
2061         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2062
2063         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2064                 return rte_flow_error_set(error, EINVAL,
2065                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2066                                           "VLAN VID value is too big");
2067         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2068             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2069                 return rte_flow_error_set(error, ENOTSUP,
2070                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2071                                           "set VLAN VID action must follow push"
2072                                           " VLAN action or match on VLAN item");
2073         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2074                 return rte_flow_error_set(error, ENOTSUP,
2075                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2076                                           "Multiple VLAN VID modifications are "
2077                                           "not supported");
2078         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2079                 return rte_flow_error_set(error, EINVAL,
2080                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2081                                           "wrong action order, port_id should "
2082                                           "be after set VLAN VID");
2083         return 0;
2084 }
2085
2086 /*
2087  * Validate the FLAG action.
2088  *
2089  * @param[in] dev
2090  *   Pointer to the rte_eth_dev structure.
2091  * @param[in] action_flags
2092  *   Holds the actions detected until now.
2093  * @param[in] attr
2094  *   Pointer to flow attributes
2095  * @param[out] error
2096  *   Pointer to error structure.
2097  *
2098  * @return
2099  *   0 on success, a negative errno value otherwise and rte_errno is set.
2100  */
2101 static int
2102 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2103                              uint64_t action_flags,
2104                              const struct rte_flow_attr *attr,
2105                              struct rte_flow_error *error)
2106 {
2107         struct mlx5_priv *priv = dev->data->dev_private;
2108         struct mlx5_dev_config *config = &priv->config;
2109         int ret;
2110
2111         /* Fall back if no extended metadata register support. */
2112         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2113                 return mlx5_flow_validate_action_flag(action_flags, attr,
2114                                                       error);
2115         /* Extensive metadata mode requires registers. */
2116         if (!mlx5_flow_ext_mreg_supported(dev))
2117                 return rte_flow_error_set(error, ENOTSUP,
2118                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2119                                           "no metadata registers "
2120                                           "to support flag action");
2121         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2122                 return rte_flow_error_set(error, ENOTSUP,
2123                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2124                                           "extended metadata register"
2125                                           " isn't available");
2126         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2127         if (ret < 0)
2128                 return ret;
2129         MLX5_ASSERT(ret > 0);
2130         if (action_flags & MLX5_FLOW_ACTION_MARK)
2131                 return rte_flow_error_set(error, EINVAL,
2132                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2133                                           "can't mark and flag in same flow");
2134         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2135                 return rte_flow_error_set(error, EINVAL,
2136                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137                                           "can't have 2 flag"
2138                                           " actions in same flow");
2139         return 0;
2140 }
2141
2142 /**
2143  * Validate MARK action.
2144  *
2145  * @param[in] dev
2146  *   Pointer to the rte_eth_dev structure.
2147  * @param[in] action
2148  *   Pointer to action.
2149  * @param[in] action_flags
2150  *   Holds the actions detected until now.
2151  * @param[in] attr
2152  *   Pointer to flow attributes
2153  * @param[out] error
2154  *   Pointer to error structure.
2155  *
2156  * @return
2157  *   0 on success, a negative errno value otherwise and rte_errno is set.
2158  */
2159 static int
2160 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2161                              const struct rte_flow_action *action,
2162                              uint64_t action_flags,
2163                              const struct rte_flow_attr *attr,
2164                              struct rte_flow_error *error)
2165 {
2166         struct mlx5_priv *priv = dev->data->dev_private;
2167         struct mlx5_dev_config *config = &priv->config;
2168         const struct rte_flow_action_mark *mark = action->conf;
2169         int ret;
2170
2171         /* Fall back if no extended metadata register support. */
2172         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2173                 return mlx5_flow_validate_action_mark(action, action_flags,
2174                                                       attr, error);
2175         /* Extensive metadata mode requires registers. */
2176         if (!mlx5_flow_ext_mreg_supported(dev))
2177                 return rte_flow_error_set(error, ENOTSUP,
2178                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2179                                           "no metadata registers "
2180                                           "to support mark action");
2181         if (!priv->sh->dv_mark_mask)
2182                 return rte_flow_error_set(error, ENOTSUP,
2183                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2184                                           "extended metadata register"
2185                                           " isn't available");
2186         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2187         if (ret < 0)
2188                 return ret;
2189         MLX5_ASSERT(ret > 0);
2190         if (!mark)
2191                 return rte_flow_error_set(error, EINVAL,
2192                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2193                                           "configuration cannot be null");
2194         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2195                 return rte_flow_error_set(error, EINVAL,
2196                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2197                                           &mark->id,
2198                                           "mark id exceeds the limit");
2199         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2200                 return rte_flow_error_set(error, EINVAL,
2201                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2202                                           "can't flag and mark in same flow");
2203         if (action_flags & MLX5_FLOW_ACTION_MARK)
2204                 return rte_flow_error_set(error, EINVAL,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206                                           "can't have 2 mark actions in same"
2207                                           " flow");
2208         return 0;
2209 }
2210
2211 /**
2212  * Validate SET_META action.
2213  *
2214  * @param[in] dev
2215  *   Pointer to the rte_eth_dev structure.
2216  * @param[in] action
2217  *   Pointer to the action structure.
2218  * @param[in] action_flags
2219  *   Holds the actions detected until now.
2220  * @param[in] attr
2221  *   Pointer to flow attributes
2222  * @param[out] error
2223  *   Pointer to error structure.
2224  *
2225  * @return
2226  *   0 on success, a negative errno value otherwise and rte_errno is set.
2227  */
2228 static int
2229 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2230                                  const struct rte_flow_action *action,
2231                                  uint64_t action_flags __rte_unused,
2232                                  const struct rte_flow_attr *attr,
2233                                  struct rte_flow_error *error)
2234 {
2235         const struct rte_flow_action_set_meta *conf;
2236         uint32_t nic_mask = UINT32_MAX;
2237         int reg;
2238
2239         if (!mlx5_flow_ext_mreg_supported(dev))
2240                 return rte_flow_error_set(error, ENOTSUP,
2241                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2242                                           "extended metadata register"
2243                                           " isn't supported");
2244         reg = flow_dv_get_metadata_reg(dev, attr, error);
2245         if (reg < 0)
2246                 return reg;
2247         if (reg != REG_A && reg != REG_B) {
2248                 struct mlx5_priv *priv = dev->data->dev_private;
2249
2250                 nic_mask = priv->sh->dv_meta_mask;
2251         }
2252         if (!(action->conf))
2253                 return rte_flow_error_set(error, EINVAL,
2254                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2255                                           "configuration cannot be null");
2256         conf = (const struct rte_flow_action_set_meta *)action->conf;
2257         if (!conf->mask)
2258                 return rte_flow_error_set(error, EINVAL,
2259                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2260                                           "zero mask doesn't have any effect");
2261         if (conf->mask & ~nic_mask)
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "meta data must be within reg C0");
2265         return 0;
2266 }
2267
2268 /**
2269  * Validate SET_TAG action.
2270  *
2271  * @param[in] dev
2272  *   Pointer to the rte_eth_dev structure.
2273  * @param[in] action
2274  *   Pointer to the action structure.
2275  * @param[in] action_flags
2276  *   Holds the actions detected until now.
2277  * @param[in] attr
2278  *   Pointer to flow attributes
2279  * @param[out] error
2280  *   Pointer to error structure.
2281  *
2282  * @return
2283  *   0 on success, a negative errno value otherwise and rte_errno is set.
2284  */
2285 static int
2286 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2287                                 const struct rte_flow_action *action,
2288                                 uint64_t action_flags,
2289                                 const struct rte_flow_attr *attr,
2290                                 struct rte_flow_error *error)
2291 {
2292         const struct rte_flow_action_set_tag *conf;
2293         const uint64_t terminal_action_flags =
2294                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2295                 MLX5_FLOW_ACTION_RSS;
2296         int ret;
2297
2298         if (!mlx5_flow_ext_mreg_supported(dev))
2299                 return rte_flow_error_set(error, ENOTSUP,
2300                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2301                                           "extensive metadata register"
2302                                           " isn't supported");
2303         if (!(action->conf))
2304                 return rte_flow_error_set(error, EINVAL,
2305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2306                                           "configuration cannot be null");
2307         conf = (const struct rte_flow_action_set_tag *)action->conf;
2308         if (!conf->mask)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2311                                           "zero mask doesn't have any effect");
2312         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2313         if (ret < 0)
2314                 return ret;
2315         if (!attr->transfer && attr->ingress &&
2316             (action_flags & terminal_action_flags))
2317                 return rte_flow_error_set(error, EINVAL,
2318                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2319                                           "set_tag has no effect"
2320                                           " with terminal actions");
2321         return 0;
2322 }
2323
2324 /**
2325  * Validate count action.
2326  *
2327  * @param[in] dev
2328  *   Pointer to rte_eth_dev structure.
2329  * @param[out] error
2330  *   Pointer to error structure.
2331  *
2332  * @return
2333  *   0 on success, a negative errno value otherwise and rte_errno is set.
2334  */
2335 static int
2336 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2337                               struct rte_flow_error *error)
2338 {
2339         struct mlx5_priv *priv = dev->data->dev_private;
2340
2341         if (!priv->config.devx)
2342                 goto notsup_err;
2343 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2344         return 0;
2345 #endif
2346 notsup_err:
2347         return rte_flow_error_set
2348                       (error, ENOTSUP,
2349                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2350                        NULL,
2351                        "count action not supported");
2352 }
2353
2354 /**
2355  * Validate the L2 encap action.
2356  *
2357  * @param[in] dev
2358  *   Pointer to the rte_eth_dev structure.
2359  * @param[in] action_flags
2360  *   Holds the actions detected until now.
2361  * @param[in] action
2362  *   Pointer to the action structure.
2363  * @param[in] attr
2364  *   Pointer to flow attributes.
2365  * @param[out] error
2366  *   Pointer to error structure.
2367  *
2368  * @return
2369  *   0 on success, a negative errno value otherwise and rte_errno is set.
2370  */
2371 static int
2372 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2373                                  uint64_t action_flags,
2374                                  const struct rte_flow_action *action,
2375                                  const struct rte_flow_attr *attr,
2376                                  struct rte_flow_error *error)
2377 {
2378         const struct mlx5_priv *priv = dev->data->dev_private;
2379
2380         if (!(action->conf))
2381                 return rte_flow_error_set(error, EINVAL,
2382                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2383                                           "configuration cannot be null");
2384         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387                                           "can only have a single encap action "
2388                                           "in a flow");
2389         if (!attr->transfer && priv->representor)
2390                 return rte_flow_error_set(error, ENOTSUP,
2391                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2392                                           "encap action for VF representor "
2393                                           "not supported on NIC table");
2394         return 0;
2395 }
2396
2397 /**
2398  * Validate a decap action.
2399  *
2400  * @param[in] dev
2401  *   Pointer to the rte_eth_dev structure.
2402  * @param[in] action_flags
2403  *   Holds the actions detected until now.
2404  * @param[in] attr
2405  *   Pointer to flow attributes
2406  * @param[out] error
2407  *   Pointer to error structure.
2408  *
2409  * @return
2410  *   0 on success, a negative errno value otherwise and rte_errno is set.
2411  */
2412 static int
2413 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2414                               uint64_t action_flags,
2415                               const struct rte_flow_attr *attr,
2416                               struct rte_flow_error *error)
2417 {
2418         const struct mlx5_priv *priv = dev->data->dev_private;
2419
2420         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2421                 return rte_flow_error_set(error, ENOTSUP,
2422                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2423                                           action_flags &
2424                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2425                                           "have a single decap action" : "decap "
2426                                           "after encap is not supported");
2427         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2428                 return rte_flow_error_set(error, EINVAL,
2429                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2430                                           "can't have decap action after"
2431                                           " modify action");
2432         if (attr->egress)
2433                 return rte_flow_error_set(error, ENOTSUP,
2434                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2435                                           NULL,
2436                                           "decap action not supported for "
2437                                           "egress");
2438         if (!attr->transfer && priv->representor)
2439                 return rte_flow_error_set(error, ENOTSUP,
2440                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2441                                           "decap action for VF representor "
2442                                           "not supported on NIC table");
2443         return 0;
2444 }
2445
2446 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2447
2448 /**
2449  * Validate the raw encap and decap actions.
2450  *
2451  * @param[in] dev
2452  *   Pointer to the rte_eth_dev structure.
2453  * @param[in] decap
2454  *   Pointer to the decap action.
2455  * @param[in] encap
2456  *   Pointer to the encap action.
2457  * @param[in] attr
2458  *   Pointer to flow attributes
2459  * @param[in/out] action_flags
2460  *   Holds the actions detected until now.
2461  * @param[out] actions_n
2462  *   pointer to the number of actions counter.
2463  * @param[out] error
2464  *   Pointer to error structure.
2465  *
2466  * @return
2467  *   0 on success, a negative errno value otherwise and rte_errno is set.
2468  */
2469 static int
2470 flow_dv_validate_action_raw_encap_decap
2471         (struct rte_eth_dev *dev,
2472          const struct rte_flow_action_raw_decap *decap,
2473          const struct rte_flow_action_raw_encap *encap,
2474          const struct rte_flow_attr *attr, uint64_t *action_flags,
2475          int *actions_n, struct rte_flow_error *error)
2476 {
2477         const struct mlx5_priv *priv = dev->data->dev_private;
2478         int ret;
2479
2480         if (encap && (!encap->size || !encap->data))
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2483                                           "raw encap data cannot be empty");
2484         if (decap && encap) {
2485                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2486                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2487                         /* L3 encap. */
2488                         decap = NULL;
2489                 else if (encap->size <=
2490                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2491                            decap->size >
2492                            MLX5_ENCAPSULATION_DECISION_SIZE)
2493                         /* L3 decap. */
2494                         encap = NULL;
2495                 else if (encap->size >
2496                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2497                            decap->size >
2498                            MLX5_ENCAPSULATION_DECISION_SIZE)
2499                         /* 2 L2 actions: encap and decap. */
2500                         ;
2501                 else
2502                         return rte_flow_error_set(error,
2503                                 ENOTSUP,
2504                                 RTE_FLOW_ERROR_TYPE_ACTION,
2505                                 NULL, "unsupported too small "
2506                                 "raw decap and too small raw "
2507                                 "encap combination");
2508         }
2509         if (decap) {
2510                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2511                                                     error);
2512                 if (ret < 0)
2513                         return ret;
2514                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2515                 ++(*actions_n);
2516         }
2517         if (encap) {
2518                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2519                         return rte_flow_error_set(error, ENOTSUP,
2520                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2521                                                   NULL,
2522                                                   "small raw encap size");
2523                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2524                         return rte_flow_error_set(error, EINVAL,
2525                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2526                                                   NULL,
2527                                                   "more than one encap action");
2528                 if (!attr->transfer && priv->representor)
2529                         return rte_flow_error_set
2530                                         (error, ENOTSUP,
2531                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2532                                          "encap action for VF representor "
2533                                          "not supported on NIC table");
2534                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2535                 ++(*actions_n);
2536         }
2537         return 0;
2538 }
2539
2540 /**
2541  * Find existing encap/decap resource or create and register a new one.
2542  *
2543  * @param[in, out] dev
2544  *   Pointer to rte_eth_dev structure.
2545  * @param[in, out] resource
2546  *   Pointer to encap/decap resource.
2547  * @parm[in, out] dev_flow
2548  *   Pointer to the dev_flow.
2549  * @param[out] error
2550  *   pointer to error structure.
2551  *
2552  * @return
2553  *   0 on success otherwise -errno and errno is set.
2554  */
2555 static int
2556 flow_dv_encap_decap_resource_register
2557                         (struct rte_eth_dev *dev,
2558                          struct mlx5_flow_dv_encap_decap_resource *resource,
2559                          struct mlx5_flow *dev_flow,
2560                          struct rte_flow_error *error)
2561 {
2562         struct mlx5_priv *priv = dev->data->dev_private;
2563         struct mlx5_dev_ctx_shared *sh = priv->sh;
2564         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2565         struct mlx5dv_dr_domain *domain;
2566         uint32_t idx = 0;
2567
2568         resource->flags = dev_flow->dv.group ? 0 : 1;
2569         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2570                 domain = sh->fdb_domain;
2571         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2572                 domain = sh->rx_domain;
2573         else
2574                 domain = sh->tx_domain;
2575         /* Lookup a matching resource from cache. */
2576         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2577                       cache_resource, next) {
2578                 if (resource->reformat_type == cache_resource->reformat_type &&
2579                     resource->ft_type == cache_resource->ft_type &&
2580                     resource->flags == cache_resource->flags &&
2581                     resource->size == cache_resource->size &&
2582                     !memcmp((const void *)resource->buf,
2583                             (const void *)cache_resource->buf,
2584                             resource->size)) {
2585                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2586                                 (void *)cache_resource,
2587                                 rte_atomic32_read(&cache_resource->refcnt));
2588                         rte_atomic32_inc(&cache_resource->refcnt);
2589                         dev_flow->handle->dvh.rix_encap_decap = idx;
2590                         dev_flow->dv.encap_decap = cache_resource;
2591                         return 0;
2592                 }
2593         }
2594         /* Register new encap/decap resource. */
2595         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2596                                        &dev_flow->handle->dvh.rix_encap_decap);
2597         if (!cache_resource)
2598                 return rte_flow_error_set(error, ENOMEM,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2600                                           "cannot allocate resource memory");
2601         *cache_resource = *resource;
2602         cache_resource->verbs_action =
2603                 mlx5_glue->dv_create_flow_action_packet_reformat
2604                         (sh->ctx, cache_resource->reformat_type,
2605                          cache_resource->ft_type, domain, cache_resource->flags,
2606                          cache_resource->size,
2607                          (cache_resource->size ? cache_resource->buf : NULL));
2608         if (!cache_resource->verbs_action) {
2609                 rte_free(cache_resource);
2610                 return rte_flow_error_set(error, ENOMEM,
2611                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2612                                           NULL, "cannot create action");
2613         }
2614         rte_atomic32_init(&cache_resource->refcnt);
2615         rte_atomic32_inc(&cache_resource->refcnt);
2616         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2617                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2618                      next);
2619         dev_flow->dv.encap_decap = cache_resource;
2620         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2621                 (void *)cache_resource,
2622                 rte_atomic32_read(&cache_resource->refcnt));
2623         return 0;
2624 }
2625
2626 /**
2627  * Find existing table jump resource or create and register a new one.
2628  *
2629  * @param[in, out] dev
2630  *   Pointer to rte_eth_dev structure.
2631  * @param[in, out] tbl
2632  *   Pointer to flow table resource.
2633  * @parm[in, out] dev_flow
2634  *   Pointer to the dev_flow.
2635  * @param[out] error
2636  *   pointer to error structure.
2637  *
2638  * @return
2639  *   0 on success otherwise -errno and errno is set.
2640  */
2641 static int
2642 flow_dv_jump_tbl_resource_register
2643                         (struct rte_eth_dev *dev __rte_unused,
2644                          struct mlx5_flow_tbl_resource *tbl,
2645                          struct mlx5_flow *dev_flow,
2646                          struct rte_flow_error *error)
2647 {
2648         struct mlx5_flow_tbl_data_entry *tbl_data =
2649                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2650         int cnt;
2651
2652         MLX5_ASSERT(tbl);
2653         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2654         if (!cnt) {
2655                 tbl_data->jump.action =
2656                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2657                         (tbl->obj);
2658                 if (!tbl_data->jump.action)
2659                         return rte_flow_error_set(error, ENOMEM,
2660                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2661                                         NULL, "cannot create jump action");
2662                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2663                         (void *)&tbl_data->jump, cnt);
2664         } else {
2665                 /* old jump should not make the table ref++. */
2666                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2667                 MLX5_ASSERT(tbl_data->jump.action);
2668                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2669                         (void *)&tbl_data->jump, cnt);
2670         }
2671         rte_atomic32_inc(&tbl_data->jump.refcnt);
2672         dev_flow->handle->rix_jump = tbl_data->idx;
2673         dev_flow->dv.jump = &tbl_data->jump;
2674         return 0;
2675 }
2676
2677 /**
2678  * Find existing table port ID resource or create and register a new one.
2679  *
2680  * @param[in, out] dev
2681  *   Pointer to rte_eth_dev structure.
2682  * @param[in, out] resource
2683  *   Pointer to port ID action resource.
2684  * @parm[in, out] dev_flow
2685  *   Pointer to the dev_flow.
2686  * @param[out] error
2687  *   pointer to error structure.
2688  *
2689  * @return
2690  *   0 on success otherwise -errno and errno is set.
2691  */
2692 static int
2693 flow_dv_port_id_action_resource_register
2694                         (struct rte_eth_dev *dev,
2695                          struct mlx5_flow_dv_port_id_action_resource *resource,
2696                          struct mlx5_flow *dev_flow,
2697                          struct rte_flow_error *error)
2698 {
2699         struct mlx5_priv *priv = dev->data->dev_private;
2700         struct mlx5_dev_ctx_shared *sh = priv->sh;
2701         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2702         uint32_t idx = 0;
2703
2704         /* Lookup a matching resource from cache. */
2705         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2706                       idx, cache_resource, next) {
2707                 if (resource->port_id == cache_resource->port_id) {
2708                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2709                                 "refcnt %d++",
2710                                 (void *)cache_resource,
2711                                 rte_atomic32_read(&cache_resource->refcnt));
2712                         rte_atomic32_inc(&cache_resource->refcnt);
2713                         dev_flow->handle->rix_port_id_action = idx;
2714                         dev_flow->dv.port_id_action = cache_resource;
2715                         return 0;
2716                 }
2717         }
2718         /* Register new port id action resource. */
2719         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2720                                        &dev_flow->handle->rix_port_id_action);
2721         if (!cache_resource)
2722                 return rte_flow_error_set(error, ENOMEM,
2723                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2724                                           "cannot allocate resource memory");
2725         *cache_resource = *resource;
2726         /*
2727          * Depending on rdma_core version the glue routine calls
2728          * either mlx5dv_dr_action_create_dest_ib_port(domain, dev_port)
2729          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2730          */
2731         cache_resource->action =
2732                 mlx5_glue->dr_create_flow_action_dest_port
2733                         (priv->sh->fdb_domain, resource->port_id);
2734         if (!cache_resource->action) {
2735                 rte_free(cache_resource);
2736                 return rte_flow_error_set(error, ENOMEM,
2737                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2738                                           NULL, "cannot create action");
2739         }
2740         rte_atomic32_init(&cache_resource->refcnt);
2741         rte_atomic32_inc(&cache_resource->refcnt);
2742         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2743                      dev_flow->handle->rix_port_id_action, cache_resource,
2744                      next);
2745         dev_flow->dv.port_id_action = cache_resource;
2746         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2747                 (void *)cache_resource,
2748                 rte_atomic32_read(&cache_resource->refcnt));
2749         return 0;
2750 }
2751
2752 /**
2753  * Find existing push vlan resource or create and register a new one.
2754  *
2755  * @param [in, out] dev
2756  *   Pointer to rte_eth_dev structure.
2757  * @param[in, out] resource
2758  *   Pointer to port ID action resource.
2759  * @parm[in, out] dev_flow
2760  *   Pointer to the dev_flow.
2761  * @param[out] error
2762  *   pointer to error structure.
2763  *
2764  * @return
2765  *   0 on success otherwise -errno and errno is set.
2766  */
2767 static int
2768 flow_dv_push_vlan_action_resource_register
2769                        (struct rte_eth_dev *dev,
2770                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2771                         struct mlx5_flow *dev_flow,
2772                         struct rte_flow_error *error)
2773 {
2774         struct mlx5_priv *priv = dev->data->dev_private;
2775         struct mlx5_dev_ctx_shared *sh = priv->sh;
2776         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2777         struct mlx5dv_dr_domain *domain;
2778         uint32_t idx = 0;
2779
2780         /* Lookup a matching resource from cache. */
2781         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2782                       sh->push_vlan_action_list, idx, cache_resource, next) {
2783                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2784                     resource->ft_type == cache_resource->ft_type) {
2785                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2786                                 "refcnt %d++",
2787                                 (void *)cache_resource,
2788                                 rte_atomic32_read(&cache_resource->refcnt));
2789                         rte_atomic32_inc(&cache_resource->refcnt);
2790                         dev_flow->handle->dvh.rix_push_vlan = idx;
2791                         dev_flow->dv.push_vlan_res = cache_resource;
2792                         return 0;
2793                 }
2794         }
2795         /* Register new push_vlan action resource. */
2796         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2797                                        &dev_flow->handle->dvh.rix_push_vlan);
2798         if (!cache_resource)
2799                 return rte_flow_error_set(error, ENOMEM,
2800                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2801                                           "cannot allocate resource memory");
2802         *cache_resource = *resource;
2803         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2804                 domain = sh->fdb_domain;
2805         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2806                 domain = sh->rx_domain;
2807         else
2808                 domain = sh->tx_domain;
2809         cache_resource->action =
2810                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2811                                                            resource->vlan_tag);
2812         if (!cache_resource->action) {
2813                 rte_free(cache_resource);
2814                 return rte_flow_error_set(error, ENOMEM,
2815                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2816                                           NULL, "cannot create action");
2817         }
2818         rte_atomic32_init(&cache_resource->refcnt);
2819         rte_atomic32_inc(&cache_resource->refcnt);
2820         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821                      &sh->push_vlan_action_list,
2822                      dev_flow->handle->dvh.rix_push_vlan,
2823                      cache_resource, next);
2824         dev_flow->dv.push_vlan_res = cache_resource;
2825         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2826                 (void *)cache_resource,
2827                 rte_atomic32_read(&cache_resource->refcnt));
2828         return 0;
2829 }
2830 /**
2831  * Get the size of specific rte_flow_item_type
2832  *
2833  * @param[in] item_type
2834  *   Tested rte_flow_item_type.
2835  *
2836  * @return
2837  *   sizeof struct item_type, 0 if void or irrelevant.
2838  */
2839 static size_t
2840 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2841 {
2842         size_t retval;
2843
2844         switch (item_type) {
2845         case RTE_FLOW_ITEM_TYPE_ETH:
2846                 retval = sizeof(struct rte_flow_item_eth);
2847                 break;
2848         case RTE_FLOW_ITEM_TYPE_VLAN:
2849                 retval = sizeof(struct rte_flow_item_vlan);
2850                 break;
2851         case RTE_FLOW_ITEM_TYPE_IPV4:
2852                 retval = sizeof(struct rte_flow_item_ipv4);
2853                 break;
2854         case RTE_FLOW_ITEM_TYPE_IPV6:
2855                 retval = sizeof(struct rte_flow_item_ipv6);
2856                 break;
2857         case RTE_FLOW_ITEM_TYPE_UDP:
2858                 retval = sizeof(struct rte_flow_item_udp);
2859                 break;
2860         case RTE_FLOW_ITEM_TYPE_TCP:
2861                 retval = sizeof(struct rte_flow_item_tcp);
2862                 break;
2863         case RTE_FLOW_ITEM_TYPE_VXLAN:
2864                 retval = sizeof(struct rte_flow_item_vxlan);
2865                 break;
2866         case RTE_FLOW_ITEM_TYPE_GRE:
2867                 retval = sizeof(struct rte_flow_item_gre);
2868                 break;
2869         case RTE_FLOW_ITEM_TYPE_NVGRE:
2870                 retval = sizeof(struct rte_flow_item_nvgre);
2871                 break;
2872         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2873                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2874                 break;
2875         case RTE_FLOW_ITEM_TYPE_MPLS:
2876                 retval = sizeof(struct rte_flow_item_mpls);
2877                 break;
2878         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2879         default:
2880                 retval = 0;
2881                 break;
2882         }
2883         return retval;
2884 }
2885
2886 #define MLX5_ENCAP_IPV4_VERSION         0x40
2887 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2888 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2889 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2890 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2891 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2892 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2893
2894 /**
2895  * Convert the encap action data from list of rte_flow_item to raw buffer
2896  *
2897  * @param[in] items
2898  *   Pointer to rte_flow_item objects list.
2899  * @param[out] buf
2900  *   Pointer to the output buffer.
2901  * @param[out] size
2902  *   Pointer to the output buffer size.
2903  * @param[out] error
2904  *   Pointer to the error structure.
2905  *
2906  * @return
2907  *   0 on success, a negative errno value otherwise and rte_errno is set.
2908  */
2909 static int
2910 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2911                            size_t *size, struct rte_flow_error *error)
2912 {
2913         struct rte_ether_hdr *eth = NULL;
2914         struct rte_vlan_hdr *vlan = NULL;
2915         struct rte_ipv4_hdr *ipv4 = NULL;
2916         struct rte_ipv6_hdr *ipv6 = NULL;
2917         struct rte_udp_hdr *udp = NULL;
2918         struct rte_vxlan_hdr *vxlan = NULL;
2919         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2920         struct rte_gre_hdr *gre = NULL;
2921         size_t len;
2922         size_t temp_size = 0;
2923
2924         if (!items)
2925                 return rte_flow_error_set(error, EINVAL,
2926                                           RTE_FLOW_ERROR_TYPE_ACTION,
2927                                           NULL, "invalid empty data");
2928         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2929                 len = flow_dv_get_item_len(items->type);
2930                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2931                         return rte_flow_error_set(error, EINVAL,
2932                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2933                                                   (void *)items->type,
2934                                                   "items total size is too big"
2935                                                   " for encap action");
2936                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2937                 switch (items->type) {
2938                 case RTE_FLOW_ITEM_TYPE_ETH:
2939                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2940                         break;
2941                 case RTE_FLOW_ITEM_TYPE_VLAN:
2942                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2943                         if (!eth)
2944                                 return rte_flow_error_set(error, EINVAL,
2945                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2946                                                 (void *)items->type,
2947                                                 "eth header not found");
2948                         if (!eth->ether_type)
2949                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2950                         break;
2951                 case RTE_FLOW_ITEM_TYPE_IPV4:
2952                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2953                         if (!vlan && !eth)
2954                                 return rte_flow_error_set(error, EINVAL,
2955                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2956                                                 (void *)items->type,
2957                                                 "neither eth nor vlan"
2958                                                 " header found");
2959                         if (vlan && !vlan->eth_proto)
2960                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2961                         else if (eth && !eth->ether_type)
2962                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2963                         if (!ipv4->version_ihl)
2964                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2965                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2966                         if (!ipv4->time_to_live)
2967                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2968                         break;
2969                 case RTE_FLOW_ITEM_TYPE_IPV6:
2970                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2971                         if (!vlan && !eth)
2972                                 return rte_flow_error_set(error, EINVAL,
2973                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2974                                                 (void *)items->type,
2975                                                 "neither eth nor vlan"
2976                                                 " header found");
2977                         if (vlan && !vlan->eth_proto)
2978                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2979                         else if (eth && !eth->ether_type)
2980                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2981                         if (!ipv6->vtc_flow)
2982                                 ipv6->vtc_flow =
2983                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2984                         if (!ipv6->hop_limits)
2985                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2986                         break;
2987                 case RTE_FLOW_ITEM_TYPE_UDP:
2988                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2989                         if (!ipv4 && !ipv6)
2990                                 return rte_flow_error_set(error, EINVAL,
2991                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2992                                                 (void *)items->type,
2993                                                 "ip header not found");
2994                         if (ipv4 && !ipv4->next_proto_id)
2995                                 ipv4->next_proto_id = IPPROTO_UDP;
2996                         else if (ipv6 && !ipv6->proto)
2997                                 ipv6->proto = IPPROTO_UDP;
2998                         break;
2999                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3000                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3001                         if (!udp)
3002                                 return rte_flow_error_set(error, EINVAL,
3003                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3004                                                 (void *)items->type,
3005                                                 "udp header not found");
3006                         if (!udp->dst_port)
3007                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3008                         if (!vxlan->vx_flags)
3009                                 vxlan->vx_flags =
3010                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3011                         break;
3012                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3013                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3014                         if (!udp)
3015                                 return rte_flow_error_set(error, EINVAL,
3016                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3017                                                 (void *)items->type,
3018                                                 "udp header not found");
3019                         if (!vxlan_gpe->proto)
3020                                 return rte_flow_error_set(error, EINVAL,
3021                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3022                                                 (void *)items->type,
3023                                                 "next protocol not found");
3024                         if (!udp->dst_port)
3025                                 udp->dst_port =
3026                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3027                         if (!vxlan_gpe->vx_flags)
3028                                 vxlan_gpe->vx_flags =
3029                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3030                         break;
3031                 case RTE_FLOW_ITEM_TYPE_GRE:
3032                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3033                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3034                         if (!gre->proto)
3035                                 return rte_flow_error_set(error, EINVAL,
3036                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3037                                                 (void *)items->type,
3038                                                 "next protocol not found");
3039                         if (!ipv4 && !ipv6)
3040                                 return rte_flow_error_set(error, EINVAL,
3041                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3042                                                 (void *)items->type,
3043                                                 "ip header not found");
3044                         if (ipv4 && !ipv4->next_proto_id)
3045                                 ipv4->next_proto_id = IPPROTO_GRE;
3046                         else if (ipv6 && !ipv6->proto)
3047                                 ipv6->proto = IPPROTO_GRE;
3048                         break;
3049                 case RTE_FLOW_ITEM_TYPE_VOID:
3050                         break;
3051                 default:
3052                         return rte_flow_error_set(error, EINVAL,
3053                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3054                                                   (void *)items->type,
3055                                                   "unsupported item type");
3056                         break;
3057                 }
3058                 temp_size += len;
3059         }
3060         *size = temp_size;
3061         return 0;
3062 }
3063
3064 static int
3065 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3066 {
3067         struct rte_ether_hdr *eth = NULL;
3068         struct rte_vlan_hdr *vlan = NULL;
3069         struct rte_ipv6_hdr *ipv6 = NULL;
3070         struct rte_udp_hdr *udp = NULL;
3071         char *next_hdr;
3072         uint16_t proto;
3073
3074         eth = (struct rte_ether_hdr *)data;
3075         next_hdr = (char *)(eth + 1);
3076         proto = RTE_BE16(eth->ether_type);
3077
3078         /* VLAN skipping */
3079         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3080                 vlan = (struct rte_vlan_hdr *)next_hdr;
3081                 proto = RTE_BE16(vlan->eth_proto);
3082                 next_hdr += sizeof(struct rte_vlan_hdr);
3083         }
3084
3085         /* HW calculates IPv4 csum. no need to proceed */
3086         if (proto == RTE_ETHER_TYPE_IPV4)
3087                 return 0;
3088
3089         /* non IPv4/IPv6 header. not supported */
3090         if (proto != RTE_ETHER_TYPE_IPV6) {
3091                 return rte_flow_error_set(error, ENOTSUP,
3092                                           RTE_FLOW_ERROR_TYPE_ACTION,
3093                                           NULL, "Cannot offload non IPv4/IPv6");
3094         }
3095
3096         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3097
3098         /* ignore non UDP */
3099         if (ipv6->proto != IPPROTO_UDP)
3100                 return 0;
3101
3102         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3103         udp->dgram_cksum = 0;
3104
3105         return 0;
3106 }
3107
3108 /**
3109  * Convert L2 encap action to DV specification.
3110  *
3111  * @param[in] dev
3112  *   Pointer to rte_eth_dev structure.
3113  * @param[in] action
3114  *   Pointer to action structure.
3115  * @param[in, out] dev_flow
3116  *   Pointer to the mlx5_flow.
3117  * @param[in] transfer
3118  *   Mark if the flow is E-Switch flow.
3119  * @param[out] error
3120  *   Pointer to the error structure.
3121  *
3122  * @return
3123  *   0 on success, a negative errno value otherwise and rte_errno is set.
3124  */
3125 static int
3126 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3127                                const struct rte_flow_action *action,
3128                                struct mlx5_flow *dev_flow,
3129                                uint8_t transfer,
3130                                struct rte_flow_error *error)
3131 {
3132         const struct rte_flow_item *encap_data;
3133         const struct rte_flow_action_raw_encap *raw_encap_data;
3134         struct mlx5_flow_dv_encap_decap_resource res = {
3135                 .reformat_type =
3136                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3137                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3138                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3139         };
3140
3141         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3142                 raw_encap_data =
3143                         (const struct rte_flow_action_raw_encap *)action->conf;
3144                 res.size = raw_encap_data->size;
3145                 memcpy(res.buf, raw_encap_data->data, res.size);
3146         } else {
3147                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3148                         encap_data =
3149                                 ((const struct rte_flow_action_vxlan_encap *)
3150                                                 action->conf)->definition;
3151                 else
3152                         encap_data =
3153                                 ((const struct rte_flow_action_nvgre_encap *)
3154                                                 action->conf)->definition;
3155                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3156                                                &res.size, error))
3157                         return -rte_errno;
3158         }
3159         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3160                 return -rte_errno;
3161         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3162                 return rte_flow_error_set(error, EINVAL,
3163                                           RTE_FLOW_ERROR_TYPE_ACTION,
3164                                           NULL, "can't create L2 encap action");
3165         return 0;
3166 }
3167
3168 /**
3169  * Convert L2 decap action to DV specification.
3170  *
3171  * @param[in] dev
3172  *   Pointer to rte_eth_dev structure.
3173  * @param[in, out] dev_flow
3174  *   Pointer to the mlx5_flow.
3175  * @param[in] transfer
3176  *   Mark if the flow is E-Switch flow.
3177  * @param[out] error
3178  *   Pointer to the error structure.
3179  *
3180  * @return
3181  *   0 on success, a negative errno value otherwise and rte_errno is set.
3182  */
3183 static int
3184 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3185                                struct mlx5_flow *dev_flow,
3186                                uint8_t transfer,
3187                                struct rte_flow_error *error)
3188 {
3189         struct mlx5_flow_dv_encap_decap_resource res = {
3190                 .size = 0,
3191                 .reformat_type =
3192                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3193                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3194                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3195         };
3196
3197         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3198                 return rte_flow_error_set(error, EINVAL,
3199                                           RTE_FLOW_ERROR_TYPE_ACTION,
3200                                           NULL, "can't create L2 decap action");
3201         return 0;
3202 }
3203
3204 /**
3205  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3206  *
3207  * @param[in] dev
3208  *   Pointer to rte_eth_dev structure.
3209  * @param[in] action
3210  *   Pointer to action structure.
3211  * @param[in, out] dev_flow
3212  *   Pointer to the mlx5_flow.
3213  * @param[in] attr
3214  *   Pointer to the flow attributes.
3215  * @param[out] error
3216  *   Pointer to the error structure.
3217  *
3218  * @return
3219  *   0 on success, a negative errno value otherwise and rte_errno is set.
3220  */
3221 static int
3222 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3223                                 const struct rte_flow_action *action,
3224                                 struct mlx5_flow *dev_flow,
3225                                 const struct rte_flow_attr *attr,
3226                                 struct rte_flow_error *error)
3227 {
3228         const struct rte_flow_action_raw_encap *encap_data;
3229         struct mlx5_flow_dv_encap_decap_resource res;
3230
3231         memset(&res, 0, sizeof(res));
3232         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3233         res.size = encap_data->size;
3234         memcpy(res.buf, encap_data->data, res.size);
3235         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3236                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3237                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3238         if (attr->transfer)
3239                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3240         else
3241                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3242                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3243         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3244                 return rte_flow_error_set(error, EINVAL,
3245                                           RTE_FLOW_ERROR_TYPE_ACTION,
3246                                           NULL, "can't create encap action");
3247         return 0;
3248 }
3249
3250 /**
3251  * Create action push VLAN.
3252  *
3253  * @param[in] dev
3254  *   Pointer to rte_eth_dev structure.
3255  * @param[in] attr
3256  *   Pointer to the flow attributes.
3257  * @param[in] vlan
3258  *   Pointer to the vlan to push to the Ethernet header.
3259  * @param[in, out] dev_flow
3260  *   Pointer to the mlx5_flow.
3261  * @param[out] error
3262  *   Pointer to the error structure.
3263  *
3264  * @return
3265  *   0 on success, a negative errno value otherwise and rte_errno is set.
3266  */
3267 static int
3268 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3269                                 const struct rte_flow_attr *attr,
3270                                 const struct rte_vlan_hdr *vlan,
3271                                 struct mlx5_flow *dev_flow,
3272                                 struct rte_flow_error *error)
3273 {
3274         struct mlx5_flow_dv_push_vlan_action_resource res;
3275
3276         memset(&res, 0, sizeof(res));
3277         res.vlan_tag =
3278                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3279                                  vlan->vlan_tci);
3280         if (attr->transfer)
3281                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3282         else
3283                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3284                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3285         return flow_dv_push_vlan_action_resource_register
3286                                             (dev, &res, dev_flow, error);
3287 }
3288
3289 /**
3290  * Validate the modify-header actions.
3291  *
3292  * @param[in] action_flags
3293  *   Holds the actions detected until now.
3294  * @param[in] action
3295  *   Pointer to the modify action.
3296  * @param[out] error
3297  *   Pointer to error structure.
3298  *
3299  * @return
3300  *   0 on success, a negative errno value otherwise and rte_errno is set.
3301  */
3302 static int
3303 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3304                                    const struct rte_flow_action *action,
3305                                    struct rte_flow_error *error)
3306 {
3307         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3308                 return rte_flow_error_set(error, EINVAL,
3309                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3310                                           NULL, "action configuration not set");
3311         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3312                 return rte_flow_error_set(error, EINVAL,
3313                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3314                                           "can't have encap action before"
3315                                           " modify action");
3316         return 0;
3317 }
3318
3319 /**
3320  * Validate the modify-header MAC address actions.
3321  *
3322  * @param[in] action_flags
3323  *   Holds the actions detected until now.
3324  * @param[in] action
3325  *   Pointer to the modify action.
3326  * @param[in] item_flags
3327  *   Holds the items detected.
3328  * @param[out] error
3329  *   Pointer to error structure.
3330  *
3331  * @return
3332  *   0 on success, a negative errno value otherwise and rte_errno is set.
3333  */
3334 static int
3335 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3336                                    const struct rte_flow_action *action,
3337                                    const uint64_t item_flags,
3338                                    struct rte_flow_error *error)
3339 {
3340         int ret = 0;
3341
3342         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3343         if (!ret) {
3344                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3345                         return rte_flow_error_set(error, EINVAL,
3346                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3347                                                   NULL,
3348                                                   "no L2 item in pattern");
3349         }
3350         return ret;
3351 }
3352
3353 /**
3354  * Validate the modify-header IPv4 address actions.
3355  *
3356  * @param[in] action_flags
3357  *   Holds the actions detected until now.
3358  * @param[in] action
3359  *   Pointer to the modify action.
3360  * @param[in] item_flags
3361  *   Holds the items detected.
3362  * @param[out] error
3363  *   Pointer to error structure.
3364  *
3365  * @return
3366  *   0 on success, a negative errno value otherwise and rte_errno is set.
3367  */
3368 static int
3369 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3370                                     const struct rte_flow_action *action,
3371                                     const uint64_t item_flags,
3372                                     struct rte_flow_error *error)
3373 {
3374         int ret = 0;
3375         uint64_t layer;
3376
3377         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3378         if (!ret) {
3379                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3380                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3381                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3382                 if (!(item_flags & layer))
3383                         return rte_flow_error_set(error, EINVAL,
3384                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3385                                                   NULL,
3386                                                   "no ipv4 item in pattern");
3387         }
3388         return ret;
3389 }
3390
3391 /**
3392  * Validate the modify-header IPv6 address actions.
3393  *
3394  * @param[in] action_flags
3395  *   Holds the actions detected until now.
3396  * @param[in] action
3397  *   Pointer to the modify action.
3398  * @param[in] item_flags
3399  *   Holds the items detected.
3400  * @param[out] error
3401  *   Pointer to error structure.
3402  *
3403  * @return
3404  *   0 on success, a negative errno value otherwise and rte_errno is set.
3405  */
3406 static int
3407 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3408                                     const struct rte_flow_action *action,
3409                                     const uint64_t item_flags,
3410                                     struct rte_flow_error *error)
3411 {
3412         int ret = 0;
3413         uint64_t layer;
3414
3415         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3416         if (!ret) {
3417                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3418                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3419                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3420                 if (!(item_flags & layer))
3421                         return rte_flow_error_set(error, EINVAL,
3422                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3423                                                   NULL,
3424                                                   "no ipv6 item in pattern");
3425         }
3426         return ret;
3427 }
3428
3429 /**
3430  * Validate the modify-header TP actions.
3431  *
3432  * @param[in] action_flags
3433  *   Holds the actions detected until now.
3434  * @param[in] action
3435  *   Pointer to the modify action.
3436  * @param[in] item_flags
3437  *   Holds the items detected.
3438  * @param[out] error
3439  *   Pointer to error structure.
3440  *
3441  * @return
3442  *   0 on success, a negative errno value otherwise and rte_errno is set.
3443  */
3444 static int
3445 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3446                                   const struct rte_flow_action *action,
3447                                   const uint64_t item_flags,
3448                                   struct rte_flow_error *error)
3449 {
3450         int ret = 0;
3451         uint64_t layer;
3452
3453         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3454         if (!ret) {
3455                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3456                                  MLX5_FLOW_LAYER_INNER_L4 :
3457                                  MLX5_FLOW_LAYER_OUTER_L4;
3458                 if (!(item_flags & layer))
3459                         return rte_flow_error_set(error, EINVAL,
3460                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3461                                                   NULL, "no transport layer "
3462                                                   "in pattern");
3463         }
3464         return ret;
3465 }
3466
3467 /**
3468  * Validate the modify-header actions of increment/decrement
3469  * TCP Sequence-number.
3470  *
3471  * @param[in] action_flags
3472  *   Holds the actions detected until now.
3473  * @param[in] action
3474  *   Pointer to the modify action.
3475  * @param[in] item_flags
3476  *   Holds the items detected.
3477  * @param[out] error
3478  *   Pointer to error structure.
3479  *
3480  * @return
3481  *   0 on success, a negative errno value otherwise and rte_errno is set.
3482  */
3483 static int
3484 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3485                                        const struct rte_flow_action *action,
3486                                        const uint64_t item_flags,
3487                                        struct rte_flow_error *error)
3488 {
3489         int ret = 0;
3490         uint64_t layer;
3491
3492         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3493         if (!ret) {
3494                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3495                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3496                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3497                 if (!(item_flags & layer))
3498                         return rte_flow_error_set(error, EINVAL,
3499                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3500                                                   NULL, "no TCP item in"
3501                                                   " pattern");
3502                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3503                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3504                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3505                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3506                         return rte_flow_error_set(error, EINVAL,
3507                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3508                                                   NULL,
3509                                                   "cannot decrease and increase"
3510                                                   " TCP sequence number"
3511                                                   " at the same time");
3512         }
3513         return ret;
3514 }
3515
3516 /**
3517  * Validate the modify-header actions of increment/decrement
3518  * TCP Acknowledgment number.
3519  *
3520  * @param[in] action_flags
3521  *   Holds the actions detected until now.
3522  * @param[in] action
3523  *   Pointer to the modify action.
3524  * @param[in] item_flags
3525  *   Holds the items detected.
3526  * @param[out] error
3527  *   Pointer to error structure.
3528  *
3529  * @return
3530  *   0 on success, a negative errno value otherwise and rte_errno is set.
3531  */
3532 static int
3533 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3534                                        const struct rte_flow_action *action,
3535                                        const uint64_t item_flags,
3536                                        struct rte_flow_error *error)
3537 {
3538         int ret = 0;
3539         uint64_t layer;
3540
3541         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3542         if (!ret) {
3543                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3544                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3545                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3546                 if (!(item_flags & layer))
3547                         return rte_flow_error_set(error, EINVAL,
3548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3549                                                   NULL, "no TCP item in"
3550                                                   " pattern");
3551                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3552                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3553                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3554                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3555                         return rte_flow_error_set(error, EINVAL,
3556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3557                                                   NULL,
3558                                                   "cannot decrease and increase"
3559                                                   " TCP acknowledgment number"
3560                                                   " at the same time");
3561         }
3562         return ret;
3563 }
3564
3565 /**
3566  * Validate the modify-header TTL actions.
3567  *
3568  * @param[in] action_flags
3569  *   Holds the actions detected until now.
3570  * @param[in] action
3571  *   Pointer to the modify action.
3572  * @param[in] item_flags
3573  *   Holds the items detected.
3574  * @param[out] error
3575  *   Pointer to error structure.
3576  *
3577  * @return
3578  *   0 on success, a negative errno value otherwise and rte_errno is set.
3579  */
3580 static int
3581 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3582                                    const struct rte_flow_action *action,
3583                                    const uint64_t item_flags,
3584                                    struct rte_flow_error *error)
3585 {
3586         int ret = 0;
3587         uint64_t layer;
3588
3589         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3590         if (!ret) {
3591                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3592                                  MLX5_FLOW_LAYER_INNER_L3 :
3593                                  MLX5_FLOW_LAYER_OUTER_L3;
3594                 if (!(item_flags & layer))
3595                         return rte_flow_error_set(error, EINVAL,
3596                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3597                                                   NULL,
3598                                                   "no IP protocol in pattern");
3599         }
3600         return ret;
3601 }
3602
3603 /**
3604  * Validate jump action.
3605  *
3606  * @param[in] action
3607  *   Pointer to the jump action.
3608  * @param[in] action_flags
3609  *   Holds the actions detected until now.
3610  * @param[in] attributes
3611  *   Pointer to flow attributes
3612  * @param[in] external
3613  *   Action belongs to flow rule created by request external to PMD.
3614  * @param[out] error
3615  *   Pointer to error structure.
3616  *
3617  * @return
3618  *   0 on success, a negative errno value otherwise and rte_errno is set.
3619  */
3620 static int
3621 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3622                              uint64_t action_flags,
3623                              const struct rte_flow_attr *attributes,
3624                              bool external, struct rte_flow_error *error)
3625 {
3626         uint32_t target_group, table;
3627         int ret = 0;
3628
3629         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3630                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3631                 return rte_flow_error_set(error, EINVAL,
3632                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3633                                           "can't have 2 fate actions in"
3634                                           " same flow");
3635         if (action_flags & MLX5_FLOW_ACTION_METER)
3636                 return rte_flow_error_set(error, ENOTSUP,
3637                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3638                                           "jump with meter not support");
3639         if (!action->conf)
3640                 return rte_flow_error_set(error, EINVAL,
3641                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3642                                           NULL, "action configuration not set");
3643         target_group =
3644                 ((const struct rte_flow_action_jump *)action->conf)->group;
3645         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3646                                        true, &table, error);
3647         if (ret)
3648                 return ret;
3649         if (attributes->group == target_group)
3650                 return rte_flow_error_set(error, EINVAL,
3651                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3652                                           "target group must be other than"
3653                                           " the current flow group");
3654         return 0;
3655 }
3656
3657 /*
3658  * Validate the port_id action.
3659  *
3660  * @param[in] dev
3661  *   Pointer to rte_eth_dev structure.
3662  * @param[in] action_flags
3663  *   Bit-fields that holds the actions detected until now.
3664  * @param[in] action
3665  *   Port_id RTE action structure.
3666  * @param[in] attr
3667  *   Attributes of flow that includes this action.
3668  * @param[out] error
3669  *   Pointer to error structure.
3670  *
3671  * @return
3672  *   0 on success, a negative errno value otherwise and rte_errno is set.
3673  */
3674 static int
3675 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3676                                 uint64_t action_flags,
3677                                 const struct rte_flow_action *action,
3678                                 const struct rte_flow_attr *attr,
3679                                 struct rte_flow_error *error)
3680 {
3681         const struct rte_flow_action_port_id *port_id;
3682         struct mlx5_priv *act_priv;
3683         struct mlx5_priv *dev_priv;
3684         uint16_t port;
3685
3686         if (!attr->transfer)
3687                 return rte_flow_error_set(error, ENOTSUP,
3688                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3689                                           NULL,
3690                                           "port id action is valid in transfer"
3691                                           " mode only");
3692         if (!action || !action->conf)
3693                 return rte_flow_error_set(error, ENOTSUP,
3694                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3695                                           NULL,
3696                                           "port id action parameters must be"
3697                                           " specified");
3698         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3699                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3700                 return rte_flow_error_set(error, EINVAL,
3701                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3702                                           "can have only one fate actions in"
3703                                           " a flow");
3704         dev_priv = mlx5_dev_to_eswitch_info(dev);
3705         if (!dev_priv)
3706                 return rte_flow_error_set(error, rte_errno,
3707                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3708                                           NULL,
3709                                           "failed to obtain E-Switch info");
3710         port_id = action->conf;
3711         port = port_id->original ? dev->data->port_id : port_id->id;
3712         act_priv = mlx5_port_to_eswitch_info(port, false);
3713         if (!act_priv)
3714                 return rte_flow_error_set
3715                                 (error, rte_errno,
3716                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3717                                  "failed to obtain E-Switch port id for port");
3718         if (act_priv->domain_id != dev_priv->domain_id)
3719                 return rte_flow_error_set
3720                                 (error, EINVAL,
3721                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3722                                  "port does not belong to"
3723                                  " E-Switch being configured");
3724         return 0;
3725 }
3726
3727 /**
3728  * Get the maximum number of modify header actions.
3729  *
3730  * @param dev
3731  *   Pointer to rte_eth_dev structure.
3732  * @param flags
3733  *   Flags bits to check if root level.
3734  *
3735  * @return
3736  *   Max number of modify header actions device can support.
3737  */
3738 static inline unsigned int
3739 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3740                               uint64_t flags)
3741 {
3742         /*
3743          * There's no way to directly query the max capacity from FW.
3744          * The maximal value on root table should be assumed to be supported.
3745          */
3746         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3747                 return MLX5_MAX_MODIFY_NUM;
3748         else
3749                 return MLX5_ROOT_TBL_MODIFY_NUM;
3750 }
3751
3752 /**
3753  * Validate the meter action.
3754  *
3755  * @param[in] dev
3756  *   Pointer to rte_eth_dev structure.
3757  * @param[in] action_flags
3758  *   Bit-fields that holds the actions detected until now.
3759  * @param[in] action
3760  *   Pointer to the meter action.
3761  * @param[in] attr
3762  *   Attributes of flow that includes this action.
3763  * @param[out] error
3764  *   Pointer to error structure.
3765  *
3766  * @return
3767  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3768  */
3769 static int
3770 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3771                                 uint64_t action_flags,
3772                                 const struct rte_flow_action *action,
3773                                 const struct rte_flow_attr *attr,
3774                                 struct rte_flow_error *error)
3775 {
3776         struct mlx5_priv *priv = dev->data->dev_private;
3777         const struct rte_flow_action_meter *am = action->conf;
3778         struct mlx5_flow_meter *fm;
3779
3780         if (!am)
3781                 return rte_flow_error_set(error, EINVAL,
3782                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3783                                           "meter action conf is NULL");
3784
3785         if (action_flags & MLX5_FLOW_ACTION_METER)
3786                 return rte_flow_error_set(error, ENOTSUP,
3787                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3788                                           "meter chaining not support");
3789         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3790                 return rte_flow_error_set(error, ENOTSUP,
3791                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3792                                           "meter with jump not support");
3793         if (!priv->mtr_en)
3794                 return rte_flow_error_set(error, ENOTSUP,
3795                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3796                                           NULL,
3797                                           "meter action not supported");
3798         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3799         if (!fm)
3800                 return rte_flow_error_set(error, EINVAL,
3801                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3802                                           "Meter not found");
3803         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3804               (!fm->ingress && !attr->ingress && attr->egress) ||
3805               (!fm->egress && !attr->egress && attr->ingress))))
3806                 return rte_flow_error_set(error, EINVAL,
3807                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3808                                           "Flow attributes are either invalid "
3809                                           "or have a conflict with current "
3810                                           "meter attributes");
3811         return 0;
3812 }
3813
3814 /**
3815  * Validate the age action.
3816  *
3817  * @param[in] action_flags
3818  *   Holds the actions detected until now.
3819  * @param[in] action
3820  *   Pointer to the age action.
3821  * @param[in] dev
3822  *   Pointer to the Ethernet device structure.
3823  * @param[out] error
3824  *   Pointer to error structure.
3825  *
3826  * @return
3827  *   0 on success, a negative errno value otherwise and rte_errno is set.
3828  */
3829 static int
3830 flow_dv_validate_action_age(uint64_t action_flags,
3831                             const struct rte_flow_action *action,
3832                             struct rte_eth_dev *dev,
3833                             struct rte_flow_error *error)
3834 {
3835         struct mlx5_priv *priv = dev->data->dev_private;
3836         const struct rte_flow_action_age *age = action->conf;
3837
3838         if (!priv->config.devx || priv->counter_fallback)
3839                 return rte_flow_error_set(error, ENOTSUP,
3840                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3841                                           NULL,
3842                                           "age action not supported");
3843         if (!(action->conf))
3844                 return rte_flow_error_set(error, EINVAL,
3845                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3846                                           "configuration cannot be null");
3847         if (age->timeout >= UINT16_MAX / 2 / 10)
3848                 return rte_flow_error_set(error, ENOTSUP,
3849                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3850                                           "Max age time: 3275 seconds");
3851         if (action_flags & MLX5_FLOW_ACTION_AGE)
3852                 return rte_flow_error_set(error, EINVAL,
3853                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3854                                           "Duplicate age ctions set");
3855         return 0;
3856 }
3857
3858 /**
3859  * Validate the modify-header IPv4 DSCP actions.
3860  *
3861  * @param[in] action_flags
3862  *   Holds the actions detected until now.
3863  * @param[in] action
3864  *   Pointer to the modify action.
3865  * @param[in] item_flags
3866  *   Holds the items detected.
3867  * @param[out] error
3868  *   Pointer to error structure.
3869  *
3870  * @return
3871  *   0 on success, a negative errno value otherwise and rte_errno is set.
3872  */
3873 static int
3874 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3875                                          const struct rte_flow_action *action,
3876                                          const uint64_t item_flags,
3877                                          struct rte_flow_error *error)
3878 {
3879         int ret = 0;
3880
3881         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3882         if (!ret) {
3883                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3884                         return rte_flow_error_set(error, EINVAL,
3885                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                   NULL,
3887                                                   "no ipv4 item in pattern");
3888         }
3889         return ret;
3890 }
3891
3892 /**
3893  * Validate the modify-header IPv6 DSCP actions.
3894  *
3895  * @param[in] action_flags
3896  *   Holds the actions detected until now.
3897  * @param[in] action
3898  *   Pointer to the modify action.
3899  * @param[in] item_flags
3900  *   Holds the items detected.
3901  * @param[out] error
3902  *   Pointer to error structure.
3903  *
3904  * @return
3905  *   0 on success, a negative errno value otherwise and rte_errno is set.
3906  */
3907 static int
3908 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3909                                          const struct rte_flow_action *action,
3910                                          const uint64_t item_flags,
3911                                          struct rte_flow_error *error)
3912 {
3913         int ret = 0;
3914
3915         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3916         if (!ret) {
3917                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3918                         return rte_flow_error_set(error, EINVAL,
3919                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3920                                                   NULL,
3921                                                   "no ipv6 item in pattern");
3922         }
3923         return ret;
3924 }
3925
3926 /**
3927  * Find existing modify-header resource or create and register a new one.
3928  *
3929  * @param dev[in, out]
3930  *   Pointer to rte_eth_dev structure.
3931  * @param[in, out] resource
3932  *   Pointer to modify-header resource.
3933  * @parm[in, out] dev_flow
3934  *   Pointer to the dev_flow.
3935  * @param[out] error
3936  *   pointer to error structure.
3937  *
3938  * @return
3939  *   0 on success otherwise -errno and errno is set.
3940  */
3941 static int
3942 flow_dv_modify_hdr_resource_register
3943                         (struct rte_eth_dev *dev,
3944                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3945                          struct mlx5_flow *dev_flow,
3946                          struct rte_flow_error *error)
3947 {
3948         struct mlx5_priv *priv = dev->data->dev_private;
3949         struct mlx5_dev_ctx_shared *sh = priv->sh;
3950         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3951         struct mlx5dv_dr_domain *ns;
3952         uint32_t actions_len;
3953
3954         resource->flags = dev_flow->dv.group ? 0 :
3955                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3956         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3957                                     resource->flags))
3958                 return rte_flow_error_set(error, EOVERFLOW,
3959                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3960                                           "too many modify header items");
3961         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3962                 ns = sh->fdb_domain;
3963         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3964                 ns = sh->tx_domain;
3965         else
3966                 ns = sh->rx_domain;
3967         /* Lookup a matching resource from cache. */
3968         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3969         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3970                 if (resource->ft_type == cache_resource->ft_type &&
3971                     resource->actions_num == cache_resource->actions_num &&
3972                     resource->flags == cache_resource->flags &&
3973                     !memcmp((const void *)resource->actions,
3974                             (const void *)cache_resource->actions,
3975                             actions_len)) {
3976                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3977                                 (void *)cache_resource,
3978                                 rte_atomic32_read(&cache_resource->refcnt));
3979                         rte_atomic32_inc(&cache_resource->refcnt);
3980                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3981                         return 0;
3982                 }
3983         }
3984         /* Register new modify-header resource. */
3985         cache_resource = rte_calloc(__func__, 1,
3986                                     sizeof(*cache_resource) + actions_len, 0);
3987         if (!cache_resource)
3988                 return rte_flow_error_set(error, ENOMEM,
3989                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3990                                           "cannot allocate resource memory");
3991         *cache_resource = *resource;
3992         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3993         cache_resource->verbs_action =
3994                 mlx5_glue->dv_create_flow_action_modify_header
3995                                         (sh->ctx, cache_resource->ft_type, ns,
3996                                          cache_resource->flags, actions_len,
3997                                          (uint64_t *)cache_resource->actions);
3998         if (!cache_resource->verbs_action) {
3999                 rte_free(cache_resource);
4000                 return rte_flow_error_set(error, ENOMEM,
4001                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4002                                           NULL, "cannot create action");
4003         }
4004         rte_atomic32_init(&cache_resource->refcnt);
4005         rte_atomic32_inc(&cache_resource->refcnt);
4006         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4007         dev_flow->handle->dvh.modify_hdr = cache_resource;
4008         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4009                 (void *)cache_resource,
4010                 rte_atomic32_read(&cache_resource->refcnt));
4011         return 0;
4012 }
4013
4014 /**
4015  * Get DV flow counter by index.
4016  *
4017  * @param[in] dev
4018  *   Pointer to the Ethernet device structure.
4019  * @param[in] idx
4020  *   mlx5 flow counter index in the container.
4021  * @param[out] ppool
4022  *   mlx5 flow counter pool in the container,
4023  *
4024  * @return
4025  *   Pointer to the counter, NULL otherwise.
4026  */
4027 static struct mlx5_flow_counter *
4028 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4029                            uint32_t idx,
4030                            struct mlx5_flow_counter_pool **ppool)
4031 {
4032         struct mlx5_priv *priv = dev->data->dev_private;
4033         struct mlx5_pools_container *cont;
4034         struct mlx5_flow_counter_pool *pool;
4035         uint32_t batch = 0, age = 0;
4036
4037         idx--;
4038         age = MLX_CNT_IS_AGE(idx);
4039         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4040         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4041                 idx -= MLX5_CNT_BATCH_OFFSET;
4042                 batch = 1;
4043         }
4044         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4045         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4046         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4047         MLX5_ASSERT(pool);
4048         if (ppool)
4049                 *ppool = pool;
4050         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4051 }
4052
4053 /**
4054  * Check the devx counter belongs to the pool.
4055  *
4056  * @param[in] pool
4057  *   Pointer to the counter pool.
4058  * @param[in] id
4059  *   The counter devx ID.
4060  *
4061  * @return
4062  *   True if counter belongs to the pool, false otherwise.
4063  */
4064 static bool
4065 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4066 {
4067         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4068                    MLX5_COUNTERS_PER_POOL;
4069
4070         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4071                 return true;
4072         return false;
4073 }
4074
4075 /**
4076  * Get a pool by devx counter ID.
4077  *
4078  * @param[in] cont
4079  *   Pointer to the counter container.
4080  * @param[in] id
4081  *   The counter devx ID.
4082  *
4083  * @return
4084  *   The counter pool pointer if exists, NULL otherwise,
4085  */
4086 static struct mlx5_flow_counter_pool *
4087 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4088 {
4089         uint32_t i;
4090
4091         /* Check last used pool. */
4092         if (cont->last_pool_idx != POOL_IDX_INVALID &&
4093             flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4094                 return cont->pools[cont->last_pool_idx];
4095         /* ID out of range means no suitable pool in the container. */
4096         if (id > cont->max_id || id < cont->min_id)
4097                 return NULL;
4098         /*
4099          * Find the pool from the end of the container, since mostly counter
4100          * ID is sequence increasing, and the last pool should be the needed
4101          * one.
4102          */
4103         i = rte_atomic16_read(&cont->n_valid);
4104         while (i--) {
4105                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4106
4107                 if (flow_dv_is_counter_in_pool(pool, id))
4108                         return pool;
4109         }
4110         return NULL;
4111 }
4112
4113 /**
4114  * Allocate a new memory for the counter values wrapped by all the needed
4115  * management.
4116  *
4117  * @param[in] dev
4118  *   Pointer to the Ethernet device structure.
4119  * @param[in] raws_n
4120  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4121  *
4122  * @return
4123  *   The new memory management pointer on success, otherwise NULL and rte_errno
4124  *   is set.
4125  */
4126 static struct mlx5_counter_stats_mem_mng *
4127 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4128 {
4129         struct mlx5_priv *priv = dev->data->dev_private;
4130         struct mlx5_dev_ctx_shared *sh = priv->sh;
4131         struct mlx5_devx_mkey_attr mkey_attr;
4132         struct mlx5_counter_stats_mem_mng *mem_mng;
4133         volatile struct flow_counter_stats *raw_data;
4134         int size = (sizeof(struct flow_counter_stats) *
4135                         MLX5_COUNTERS_PER_POOL +
4136                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4137                         sizeof(struct mlx5_counter_stats_mem_mng);
4138         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4139         int i;
4140
4141         if (!mem) {
4142                 rte_errno = ENOMEM;
4143                 return NULL;
4144         }
4145         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4146         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4147         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4148                                                  IBV_ACCESS_LOCAL_WRITE);
4149         if (!mem_mng->umem) {
4150                 rte_errno = errno;
4151                 rte_free(mem);
4152                 return NULL;
4153         }
4154         mkey_attr.addr = (uintptr_t)mem;
4155         mkey_attr.size = size;
4156         mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4157         mkey_attr.pd = sh->pdn;
4158         mkey_attr.log_entity_size = 0;
4159         mkey_attr.pg_access = 0;
4160         mkey_attr.klm_array = NULL;
4161         mkey_attr.klm_num = 0;
4162         if (priv->config.hca_attr.relaxed_ordering_write &&
4163                 priv->config.hca_attr.relaxed_ordering_read  &&
4164                 !haswell_broadwell_cpu)
4165                 mkey_attr.relaxed_ordering = 1;
4166         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4167         if (!mem_mng->dm) {
4168                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4169                 rte_errno = errno;
4170                 rte_free(mem);
4171                 return NULL;
4172         }
4173         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4174         raw_data = (volatile struct flow_counter_stats *)mem;
4175         for (i = 0; i < raws_n; ++i) {
4176                 mem_mng->raws[i].mem_mng = mem_mng;
4177                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4178         }
4179         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4180         return mem_mng;
4181 }
4182
4183 /**
4184  * Resize a counter container.
4185  *
4186  * @param[in] dev
4187  *   Pointer to the Ethernet device structure.
4188  * @param[in] batch
4189  *   Whether the pool is for counter that was allocated by batch command.
4190  * @param[in] age
4191  *   Whether the pool is for Aging counter.
4192  *
4193  * @return
4194  *   0 on success, otherwise negative errno value and rte_errno is set.
4195  */
4196 static int
4197 flow_dv_container_resize(struct rte_eth_dev *dev,
4198                                 uint32_t batch, uint32_t age)
4199 {
4200         struct mlx5_priv *priv = dev->data->dev_private;
4201         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4202                                                                age);
4203         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4204         void *old_pools = cont->pools;
4205         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4206         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4207         void *pools = rte_calloc(__func__, 1, mem_size, 0);
4208
4209         if (!pools) {
4210                 rte_errno = ENOMEM;
4211                 return -ENOMEM;
4212         }
4213         if (old_pools)
4214                 memcpy(pools, old_pools, cont->n *
4215                                        sizeof(struct mlx5_flow_counter_pool *));
4216         /*
4217          * Fallback mode query the counter directly, no background query
4218          * resources are needed.
4219          */
4220         if (!priv->counter_fallback) {
4221                 int i;
4222
4223                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4224                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4225                 if (!mem_mng) {
4226                         rte_free(pools);
4227                         return -ENOMEM;
4228                 }
4229                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4230                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4231                                          mem_mng->raws +
4232                                          MLX5_CNT_CONTAINER_RESIZE +
4233                                          i, next);
4234         }
4235         rte_spinlock_lock(&cont->resize_sl);
4236         cont->n = resize;
4237         cont->mem_mng = mem_mng;
4238         cont->pools = pools;
4239         rte_spinlock_unlock(&cont->resize_sl);
4240         if (old_pools)
4241                 rte_free(old_pools);
4242         return 0;
4243 }
4244
4245 /**
4246  * Query a devx flow counter.
4247  *
4248  * @param[in] dev
4249  *   Pointer to the Ethernet device structure.
4250  * @param[in] cnt
4251  *   Index to the flow counter.
4252  * @param[out] pkts
4253  *   The statistics value of packets.
4254  * @param[out] bytes
4255  *   The statistics value of bytes.
4256  *
4257  * @return
4258  *   0 on success, otherwise a negative errno value and rte_errno is set.
4259  */
4260 static inline int
4261 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4262                      uint64_t *bytes)
4263 {
4264         struct mlx5_priv *priv = dev->data->dev_private;
4265         struct mlx5_flow_counter_pool *pool = NULL;
4266         struct mlx5_flow_counter *cnt;
4267         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4268         int offset;
4269
4270         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4271         MLX5_ASSERT(pool);
4272         if (counter < MLX5_CNT_BATCH_OFFSET) {
4273                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4274                 if (priv->counter_fallback)
4275                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4276                                         0, pkts, bytes, 0, NULL, NULL, 0);
4277         }
4278
4279         rte_spinlock_lock(&pool->sl);
4280         /*
4281          * The single counters allocation may allocate smaller ID than the
4282          * current allocated in parallel to the host reading.
4283          * In this case the new counter values must be reported as 0.
4284          */
4285         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4286                 *pkts = 0;
4287                 *bytes = 0;
4288         } else {
4289                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4290                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4291                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4292         }
4293         rte_spinlock_unlock(&pool->sl);
4294         return 0;
4295 }
4296
4297 /**
4298  * Create and initialize a new counter pool.
4299  *
4300  * @param[in] dev
4301  *   Pointer to the Ethernet device structure.
4302  * @param[out] dcs
4303  *   The devX counter handle.
4304  * @param[in] batch
4305  *   Whether the pool is for counter that was allocated by batch command.
4306  * @param[in] age
4307  *   Whether the pool is for counter that was allocated for aging.
4308  * @param[in/out] cont_cur
4309  *   Pointer to the container pointer, it will be update in pool resize.
4310  *
4311  * @return
4312  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4313  */
4314 static struct mlx5_flow_counter_pool *
4315 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4316                     uint32_t batch, uint32_t age)
4317 {
4318         struct mlx5_priv *priv = dev->data->dev_private;
4319         struct mlx5_flow_counter_pool *pool;
4320         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4321                                                                age);
4322         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4323         uint32_t size = sizeof(*pool);
4324
4325         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4326                 return NULL;
4327         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4328         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4329         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4330         pool = rte_calloc(__func__, 1, size, 0);
4331         if (!pool) {
4332                 rte_errno = ENOMEM;
4333                 return NULL;
4334         }
4335         pool->min_dcs = dcs;
4336         if (!priv->counter_fallback)
4337                 pool->raw = cont->mem_mng->raws + n_valid %
4338                                                       MLX5_CNT_CONTAINER_RESIZE;
4339         pool->raw_hw = NULL;
4340         pool->type = 0;
4341         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4342         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4343         pool->query_gen = 0;
4344         rte_spinlock_init(&pool->sl);
4345         TAILQ_INIT(&pool->counters[0]);
4346         TAILQ_INIT(&pool->counters[1]);
4347         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4348         pool->index = n_valid;
4349         cont->pools[n_valid] = pool;
4350         if (!batch) {
4351                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4352
4353                 if (base < cont->min_id)
4354                         cont->min_id = base;
4355                 if (base > cont->max_id)
4356                         cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4357                 cont->last_pool_idx = pool->index;
4358         }
4359         /* Pool initialization must be updated before host thread access. */
4360         rte_cio_wmb();
4361         rte_atomic16_add(&cont->n_valid, 1);
4362         return pool;
4363 }
4364
4365 /**
4366  * Update the minimum dcs-id for aged or no-aged counter pool.
4367  *
4368  * @param[in] dev
4369  *   Pointer to the Ethernet device structure.
4370  * @param[in] pool
4371  *   Current counter pool.
4372  * @param[in] batch
4373  *   Whether the pool is for counter that was allocated by batch command.
4374  * @param[in] age
4375  *   Whether the counter is for aging.
4376  */
4377 static void
4378 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4379                         struct mlx5_flow_counter_pool *pool,
4380                         uint32_t batch, uint32_t age)
4381 {
4382         struct mlx5_priv *priv = dev->data->dev_private;
4383         struct mlx5_flow_counter_pool *other;
4384         struct mlx5_pools_container *cont;
4385
4386         cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4387         other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4388         if (!other)
4389                 return;
4390         if (pool->min_dcs->id < other->min_dcs->id) {
4391                 rte_atomic64_set(&other->a64_dcs,
4392                         rte_atomic64_read(&pool->a64_dcs));
4393         } else {
4394                 rte_atomic64_set(&pool->a64_dcs,
4395                         rte_atomic64_read(&other->a64_dcs));
4396         }
4397 }
4398 /**
4399  * Prepare a new counter and/or a new counter pool.
4400  *
4401  * @param[in] dev
4402  *   Pointer to the Ethernet device structure.
4403  * @param[out] cnt_free
4404  *   Where to put the pointer of a new counter.
4405  * @param[in] batch
4406  *   Whether the pool is for counter that was allocated by batch command.
4407  * @param[in] age
4408  *   Whether the pool is for counter that was allocated for aging.
4409  *
4410  * @return
4411  *   The counter pool pointer and @p cnt_free is set on success,
4412  *   NULL otherwise and rte_errno is set.
4413  */
4414 static struct mlx5_flow_counter_pool *
4415 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4416                              struct mlx5_flow_counter **cnt_free,
4417                              uint32_t batch, uint32_t age)
4418 {
4419         struct mlx5_priv *priv = dev->data->dev_private;
4420         struct mlx5_pools_container *cont;
4421         struct mlx5_flow_counter_pool *pool;
4422         struct mlx5_counters tmp_tq;
4423         struct mlx5_devx_obj *dcs = NULL;
4424         struct mlx5_flow_counter *cnt;
4425         uint32_t i;
4426
4427         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4428         if (!batch) {
4429                 /* bulk_bitmap must be 0 for single counter allocation. */
4430                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4431                 if (!dcs)
4432                         return NULL;
4433                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4434                 if (!pool) {
4435                         pool = flow_dv_pool_create(dev, dcs, batch, age);
4436                         if (!pool) {
4437                                 mlx5_devx_cmd_destroy(dcs);
4438                                 return NULL;
4439                         }
4440                 } else if (dcs->id < pool->min_dcs->id) {
4441                         rte_atomic64_set(&pool->a64_dcs,
4442                                          (int64_t)(uintptr_t)dcs);
4443                 }
4444                 flow_dv_counter_update_min_dcs(dev,
4445                                                 pool, batch, age);
4446                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4447                 cnt = MLX5_POOL_GET_CNT(pool, i);
4448                 cnt->pool = pool;
4449                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4450                 *cnt_free = cnt;
4451                 return pool;
4452         }
4453         /* bulk_bitmap is in 128 counters units. */
4454         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4455                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4456         if (!dcs) {
4457                 rte_errno = ENODATA;
4458                 return NULL;
4459         }
4460         pool = flow_dv_pool_create(dev, dcs, batch, age);
4461         if (!pool) {
4462                 mlx5_devx_cmd_destroy(dcs);
4463                 return NULL;
4464         }
4465         TAILQ_INIT(&tmp_tq);
4466         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4467                 cnt = MLX5_POOL_GET_CNT(pool, i);
4468                 cnt->pool = pool;
4469                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4470         }
4471         rte_spinlock_lock(&cont->csl);
4472         TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4473         rte_spinlock_unlock(&cont->csl);
4474         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4475         (*cnt_free)->pool = pool;
4476         return pool;
4477 }
4478
4479 /**
4480  * Search for existed shared counter.
4481  *
4482  * @param[in] dev
4483  *   Pointer to the Ethernet device structure.
4484  * @param[in] id
4485  *   The shared counter ID to search.
4486  * @param[out] ppool
4487  *   mlx5 flow counter pool in the container,
4488  *
4489  * @return
4490  *   NULL if not existed, otherwise pointer to the shared extend counter.
4491  */
4492 static struct mlx5_flow_counter_ext *
4493 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4494                               struct mlx5_flow_counter_pool **ppool)
4495 {
4496         struct mlx5_priv *priv = dev->data->dev_private;
4497         union mlx5_l3t_data data;
4498         uint32_t cnt_idx;
4499
4500         if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4501                 return NULL;
4502         cnt_idx = data.dword;
4503         /*
4504          * Shared counters don't have age info. The counter extend is after
4505          * the counter datat structure.
4506          */
4507         return (struct mlx5_flow_counter_ext *)
4508                ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4509 }
4510
4511 /**
4512  * Allocate a flow counter.
4513  *
4514  * @param[in] dev
4515  *   Pointer to the Ethernet device structure.
4516  * @param[in] shared
4517  *   Indicate if this counter is shared with other flows.
4518  * @param[in] id
4519  *   Counter identifier.
4520  * @param[in] group
4521  *   Counter flow group.
4522  * @param[in] age
4523  *   Whether the counter was allocated for aging.
4524  *
4525  * @return
4526  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4527  */
4528 static uint32_t
4529 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4530                       uint16_t group, uint32_t age)
4531 {
4532         struct mlx5_priv *priv = dev->data->dev_private;
4533         struct mlx5_flow_counter_pool *pool = NULL;
4534         struct mlx5_flow_counter *cnt_free = NULL;
4535         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4536         /*
4537          * Currently group 0 flow counter cannot be assigned to a flow if it is
4538          * not the first one in the batch counter allocation, so it is better
4539          * to allocate counters one by one for these flows in a separate
4540          * container.
4541          * A counter can be shared between different groups so need to take
4542          * shared counters from the single container.
4543          */
4544         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4545         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4546                                                                age);
4547         uint32_t cnt_idx;
4548
4549         if (!priv->config.devx) {
4550                 rte_errno = ENOTSUP;
4551                 return 0;
4552         }
4553         if (shared) {
4554                 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4555                 if (cnt_ext) {
4556                         if (cnt_ext->ref_cnt + 1 == 0) {
4557                                 rte_errno = E2BIG;
4558                                 return 0;
4559                         }
4560                         cnt_ext->ref_cnt++;
4561                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4562                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4563                                   + 1;
4564                         return cnt_idx;
4565                 }
4566         }
4567         /* Get free counters from container. */
4568         rte_spinlock_lock(&cont->csl);
4569         cnt_free = TAILQ_FIRST(&cont->counters);
4570         if (cnt_free)
4571                 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4572         rte_spinlock_unlock(&cont->csl);
4573         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4574                                                        batch, age))
4575                 goto err;
4576         pool = cnt_free->pool;
4577         if (!batch)
4578                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4579         /* Create a DV counter action only in the first time usage. */
4580         if (!cnt_free->action) {
4581                 uint16_t offset;
4582                 struct mlx5_devx_obj *dcs;
4583
4584                 if (batch) {
4585                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4586                         dcs = pool->min_dcs;
4587                 } else {
4588                         offset = 0;
4589                         dcs = cnt_ext->dcs;
4590                 }
4591                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4592                                         (dcs->obj, offset);
4593                 if (!cnt_free->action) {
4594                         rte_errno = errno;
4595                         goto err;
4596                 }
4597         }
4598         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4599                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4600         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4601         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4602         /* Update the counter reset values. */
4603         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4604                                  &cnt_free->bytes))
4605                 goto err;
4606         if (cnt_ext) {
4607                 cnt_ext->shared = shared;
4608                 cnt_ext->ref_cnt = 1;
4609                 cnt_ext->id = id;
4610                 if (shared) {
4611                         union mlx5_l3t_data data;
4612
4613                         data.dword = cnt_idx;
4614                         if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4615                                 return 0;
4616                 }
4617         }
4618         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4619                 /* Start the asynchronous batch query by the host thread. */
4620                 mlx5_set_query_alarm(priv->sh);
4621         return cnt_idx;
4622 err:
4623         if (cnt_free) {
4624                 cnt_free->pool = pool;
4625                 rte_spinlock_lock(&cont->csl);
4626                 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4627                 rte_spinlock_unlock(&cont->csl);
4628         }
4629         return 0;
4630 }
4631
4632 /**
4633  * Get age param from counter index.
4634  *
4635  * @param[in] dev
4636  *   Pointer to the Ethernet device structure.
4637  * @param[in] counter
4638  *   Index to the counter handler.
4639  *
4640  * @return
4641  *   The aging parameter specified for the counter index.
4642  */
4643 static struct mlx5_age_param*
4644 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4645                                 uint32_t counter)
4646 {
4647         struct mlx5_flow_counter *cnt;
4648         struct mlx5_flow_counter_pool *pool = NULL;
4649
4650         flow_dv_counter_get_by_idx(dev, counter, &pool);
4651         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4652         cnt = MLX5_POOL_GET_CNT(pool, counter);
4653         return MLX5_CNT_TO_AGE(cnt);
4654 }
4655
4656 /**
4657  * Remove a flow counter from aged counter list.
4658  *
4659  * @param[in] dev
4660  *   Pointer to the Ethernet device structure.
4661  * @param[in] counter
4662  *   Index to the counter handler.
4663  * @param[in] cnt
4664  *   Pointer to the counter handler.
4665  */
4666 static void
4667 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4668                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4669 {
4670         struct mlx5_age_info *age_info;
4671         struct mlx5_age_param *age_param;
4672         struct mlx5_priv *priv = dev->data->dev_private;
4673
4674         age_info = GET_PORT_AGE_INFO(priv);
4675         age_param = flow_dv_counter_idx_get_age(dev, counter);
4676         if (rte_atomic16_cmpset((volatile uint16_t *)
4677                         &age_param->state,
4678                         AGE_CANDIDATE, AGE_FREE)
4679                         != AGE_CANDIDATE) {
4680                 /**
4681                  * We need the lock even it is age timeout,
4682                  * since counter may still in process.
4683                  */
4684                 rte_spinlock_lock(&age_info->aged_sl);
4685                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4686                 rte_spinlock_unlock(&age_info->aged_sl);
4687         }
4688         rte_atomic16_set(&age_param->state, AGE_FREE);
4689 }
4690 /**
4691  * Release a flow counter.
4692  *
4693  * @param[in] dev
4694  *   Pointer to the Ethernet device structure.
4695  * @param[in] counter
4696  *   Index to the counter handler.
4697  */
4698 static void
4699 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4700 {
4701         struct mlx5_priv *priv = dev->data->dev_private;
4702         struct mlx5_flow_counter_pool *pool = NULL;
4703         struct mlx5_flow_counter *cnt;
4704         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4705
4706         if (!counter)
4707                 return;
4708         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4709         MLX5_ASSERT(pool);
4710         if (counter < MLX5_CNT_BATCH_OFFSET) {
4711                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4712                 if (cnt_ext) {
4713                         if (--cnt_ext->ref_cnt)
4714                                 return;
4715                         if (cnt_ext->shared)
4716                                 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4717                                                      cnt_ext->id);
4718                 }
4719         }
4720         if (IS_AGE_POOL(pool))
4721                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4722         cnt->pool = pool;
4723         /*
4724          * Put the counter back to list to be updated in none fallback mode.
4725          * Currently, we are using two list alternately, while one is in query,
4726          * add the freed counter to the other list based on the pool query_gen
4727          * value. After query finishes, add counter the list to the global
4728          * container counter list. The list changes while query starts. In
4729          * this case, lock will not be needed as query callback and release
4730          * function both operate with the different list.
4731          *
4732          */
4733         if (!priv->counter_fallback)
4734                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4735         else
4736                 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4737                                   (priv->sh, 0, 0))->counters),
4738                                   cnt, next);
4739 }
4740
4741 /**
4742  * Verify the @p attributes will be correctly understood by the NIC and store
4743  * them in the @p flow if everything is correct.
4744  *
4745  * @param[in] dev
4746  *   Pointer to dev struct.
4747  * @param[in] attributes
4748  *   Pointer to flow attributes
4749  * @param[in] external
4750  *   This flow rule is created by request external to PMD.
4751  * @param[out] error
4752  *   Pointer to error structure.
4753  *
4754  * @return
4755  *   - 0 on success and non root table.
4756  *   - 1 on success and root table.
4757  *   - a negative errno value otherwise and rte_errno is set.
4758  */
4759 static int
4760 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4761                             const struct rte_flow_attr *attributes,
4762                             bool external __rte_unused,
4763                             struct rte_flow_error *error)
4764 {
4765         struct mlx5_priv *priv = dev->data->dev_private;
4766         uint32_t priority_max = priv->config.flow_prio - 1;
4767         int ret = 0;
4768
4769 #ifndef HAVE_MLX5DV_DR
4770         if (attributes->group)
4771                 return rte_flow_error_set(error, ENOTSUP,
4772                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4773                                           NULL,
4774                                           "groups are not supported");
4775 #else
4776         uint32_t table = 0;
4777
4778         ret = mlx5_flow_group_to_table(attributes, external,
4779                                        attributes->group, !!priv->fdb_def_rule,
4780                                        &table, error);
4781         if (ret)
4782                 return ret;
4783         if (!table)
4784                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4785 #endif
4786         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4787             attributes->priority >= priority_max)
4788                 return rte_flow_error_set(error, ENOTSUP,
4789                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4790                                           NULL,
4791                                           "priority out of range");
4792         if (attributes->transfer) {
4793                 if (!priv->config.dv_esw_en)
4794                         return rte_flow_error_set
4795                                 (error, ENOTSUP,
4796                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4797                                  "E-Switch dr is not supported");
4798                 if (!(priv->representor || priv->master))
4799                         return rte_flow_error_set
4800                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4801                                  NULL, "E-Switch configuration can only be"
4802                                  " done by a master or a representor device");
4803                 if (attributes->egress)
4804                         return rte_flow_error_set
4805                                 (error, ENOTSUP,
4806                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4807                                  "egress is not supported");
4808         }
4809         if (!(attributes->egress ^ attributes->ingress))
4810                 return rte_flow_error_set(error, ENOTSUP,
4811                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4812                                           "must specify exactly one of "
4813                                           "ingress or egress");
4814         return ret;
4815 }
4816
4817 /**
4818  * Internal validation function. For validating both actions and items.
4819  *
4820  * @param[in] dev
4821  *   Pointer to the rte_eth_dev structure.
4822  * @param[in] attr
4823  *   Pointer to the flow attributes.
4824  * @param[in] items
4825  *   Pointer to the list of items.
4826  * @param[in] actions
4827  *   Pointer to the list of actions.
4828  * @param[in] external
4829  *   This flow rule is created by request external to PMD.
4830  * @param[in] hairpin
4831  *   Number of hairpin TX actions, 0 means classic flow.
4832  * @param[out] error
4833  *   Pointer to the error structure.
4834  *
4835  * @return
4836  *   0 on success, a negative errno value otherwise and rte_errno is set.
4837  */
4838 static int
4839 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4840                  const struct rte_flow_item items[],
4841                  const struct rte_flow_action actions[],
4842                  bool external, int hairpin, struct rte_flow_error *error)
4843 {
4844         int ret;
4845         uint64_t action_flags = 0;
4846         uint64_t item_flags = 0;
4847         uint64_t last_item = 0;
4848         uint8_t next_protocol = 0xff;
4849         uint16_t ether_type = 0;
4850         int actions_n = 0;
4851         uint8_t item_ipv6_proto = 0;
4852         const struct rte_flow_item *gre_item = NULL;
4853         const struct rte_flow_action_raw_decap *decap;
4854         const struct rte_flow_action_raw_encap *encap;
4855         const struct rte_flow_action_rss *rss;
4856         const struct rte_flow_item_tcp nic_tcp_mask = {
4857                 .hdr = {
4858                         .tcp_flags = 0xFF,
4859                         .src_port = RTE_BE16(UINT16_MAX),
4860                         .dst_port = RTE_BE16(UINT16_MAX),
4861                 }
4862         };
4863         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4864                 .hdr = {
4865                         .src_addr = RTE_BE32(0xffffffff),
4866                         .dst_addr = RTE_BE32(0xffffffff),
4867                         .type_of_service = 0xff,
4868                         .next_proto_id = 0xff,
4869                         .time_to_live = 0xff,
4870                 },
4871         };
4872         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4873                 .hdr = {
4874                         .src_addr =
4875                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4876                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4877                         .dst_addr =
4878                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4879                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4880                         .vtc_flow = RTE_BE32(0xffffffff),
4881                         .proto = 0xff,
4882                         .hop_limits = 0xff,
4883                 },
4884         };
4885         struct mlx5_priv *priv = dev->data->dev_private;
4886         struct mlx5_dev_config *dev_conf = &priv->config;
4887         uint16_t queue_index = 0xFFFF;
4888         const struct rte_flow_item_vlan *vlan_m = NULL;
4889         int16_t rw_act_num = 0;
4890         uint64_t is_root;
4891
4892         if (items == NULL)
4893                 return -1;
4894         ret = flow_dv_validate_attributes(dev, attr, external, error);
4895         if (ret < 0)
4896                 return ret;
4897         is_root = (uint64_t)ret;
4898         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4899                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4900                 int type = items->type;
4901
4902                 switch (type) {
4903                 case RTE_FLOW_ITEM_TYPE_VOID:
4904                         break;
4905                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4906                         ret = flow_dv_validate_item_port_id
4907                                         (dev, items, attr, item_flags, error);
4908                         if (ret < 0)
4909                                 return ret;
4910                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4911                         break;
4912                 case RTE_FLOW_ITEM_TYPE_ETH:
4913                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4914                                                           error);
4915                         if (ret < 0)
4916                                 return ret;
4917                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4918                                              MLX5_FLOW_LAYER_OUTER_L2;
4919                         if (items->mask != NULL && items->spec != NULL) {
4920                                 ether_type =
4921                                         ((const struct rte_flow_item_eth *)
4922                                          items->spec)->type;
4923                                 ether_type &=
4924                                         ((const struct rte_flow_item_eth *)
4925                                          items->mask)->type;
4926                                 ether_type = rte_be_to_cpu_16(ether_type);
4927                         } else {
4928                                 ether_type = 0;
4929                         }
4930                         break;
4931                 case RTE_FLOW_ITEM_TYPE_VLAN:
4932                         ret = flow_dv_validate_item_vlan(items, item_flags,
4933                                                          dev, error);
4934                         if (ret < 0)
4935                                 return ret;
4936                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4937                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4938                         if (items->mask != NULL && items->spec != NULL) {
4939                                 ether_type =
4940                                         ((const struct rte_flow_item_vlan *)
4941                                          items->spec)->inner_type;
4942                                 ether_type &=
4943                                         ((const struct rte_flow_item_vlan *)
4944                                          items->mask)->inner_type;
4945                                 ether_type = rte_be_to_cpu_16(ether_type);
4946                         } else {
4947                                 ether_type = 0;
4948                         }
4949                         /* Store outer VLAN mask for of_push_vlan action. */
4950                         if (!tunnel)
4951                                 vlan_m = items->mask;
4952                         break;
4953                 case RTE_FLOW_ITEM_TYPE_IPV4:
4954                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4955                                                   &item_flags, &tunnel);
4956                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4957                                                            last_item,
4958                                                            ether_type,
4959                                                            &nic_ipv4_mask,
4960                                                            error);
4961                         if (ret < 0)
4962                                 return ret;
4963                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4964                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4965                         if (items->mask != NULL &&
4966                             ((const struct rte_flow_item_ipv4 *)
4967                              items->mask)->hdr.next_proto_id) {
4968                                 next_protocol =
4969                                         ((const struct rte_flow_item_ipv4 *)
4970                                          (items->spec))->hdr.next_proto_id;
4971                                 next_protocol &=
4972                                         ((const struct rte_flow_item_ipv4 *)
4973                                          (items->mask))->hdr.next_proto_id;
4974                         } else {
4975                                 /* Reset for inner layer. */
4976                                 next_protocol = 0xff;
4977                         }
4978                         break;
4979                 case RTE_FLOW_ITEM_TYPE_IPV6:
4980                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4981                                                   &item_flags, &tunnel);
4982                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4983                                                            last_item,
4984                                                            ether_type,
4985                                                            &nic_ipv6_mask,
4986                                                            error);
4987                         if (ret < 0)
4988                                 return ret;
4989                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4990                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4991                         if (items->mask != NULL &&
4992                             ((const struct rte_flow_item_ipv6 *)
4993                              items->mask)->hdr.proto) {
4994                                 item_ipv6_proto =
4995                                         ((const struct rte_flow_item_ipv6 *)
4996                                          items->spec)->hdr.proto;
4997                                 next_protocol =
4998                                         ((const struct rte_flow_item_ipv6 *)
4999                                          items->spec)->hdr.proto;
5000                                 next_protocol &=
5001                                         ((const struct rte_flow_item_ipv6 *)
5002                                          items->mask)->hdr.proto;
5003                         } else {
5004                                 /* Reset for inner layer. */
5005                                 next_protocol = 0xff;
5006                         }
5007                         break;
5008                 case RTE_FLOW_ITEM_TYPE_TCP:
5009                         ret = mlx5_flow_validate_item_tcp
5010                                                 (items, item_flags,
5011                                                  next_protocol,
5012                                                  &nic_tcp_mask,
5013                                                  error);
5014                         if (ret < 0)
5015                                 return ret;
5016                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5017                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5018                         break;
5019                 case RTE_FLOW_ITEM_TYPE_UDP:
5020                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5021                                                           next_protocol,
5022                                                           error);
5023                         if (ret < 0)
5024                                 return ret;
5025                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5026                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5027                         break;
5028                 case RTE_FLOW_ITEM_TYPE_GRE:
5029                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5030                                                           next_protocol, error);
5031                         if (ret < 0)
5032                                 return ret;
5033                         gre_item = items;
5034                         last_item = MLX5_FLOW_LAYER_GRE;
5035                         break;
5036                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5037                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5038                                                             next_protocol,
5039                                                             error);
5040                         if (ret < 0)
5041                                 return ret;
5042                         last_item = MLX5_FLOW_LAYER_NVGRE;
5043                         break;
5044                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5045                         ret = mlx5_flow_validate_item_gre_key
5046                                 (items, item_flags, gre_item, error);
5047                         if (ret < 0)
5048                                 return ret;
5049                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5050                         break;
5051                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5052                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5053                                                             error);
5054                         if (ret < 0)
5055                                 return ret;
5056                         last_item = MLX5_FLOW_LAYER_VXLAN;
5057                         break;
5058                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5059                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5060                                                                 item_flags, dev,
5061                                                                 error);
5062                         if (ret < 0)
5063                                 return ret;
5064                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5065                         break;
5066                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5067                         ret = mlx5_flow_validate_item_geneve(items,
5068                                                              item_flags, dev,
5069                                                              error);
5070                         if (ret < 0)
5071                                 return ret;
5072                         last_item = MLX5_FLOW_LAYER_GENEVE;
5073                         break;
5074                 case RTE_FLOW_ITEM_TYPE_MPLS:
5075                         ret = mlx5_flow_validate_item_mpls(dev, items,
5076                                                            item_flags,
5077                                                            last_item, error);
5078                         if (ret < 0)
5079                                 return ret;
5080                         last_item = MLX5_FLOW_LAYER_MPLS;
5081                         break;
5082
5083                 case RTE_FLOW_ITEM_TYPE_MARK:
5084                         ret = flow_dv_validate_item_mark(dev, items, attr,
5085                                                          error);
5086                         if (ret < 0)
5087                                 return ret;
5088                         last_item = MLX5_FLOW_ITEM_MARK;
5089                         break;
5090                 case RTE_FLOW_ITEM_TYPE_META:
5091                         ret = flow_dv_validate_item_meta(dev, items, attr,
5092                                                          error);
5093                         if (ret < 0)
5094                                 return ret;
5095                         last_item = MLX5_FLOW_ITEM_METADATA;
5096                         break;
5097                 case RTE_FLOW_ITEM_TYPE_ICMP:
5098                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5099                                                            next_protocol,
5100                                                            error);
5101                         if (ret < 0)
5102                                 return ret;
5103                         last_item = MLX5_FLOW_LAYER_ICMP;
5104                         break;
5105                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5106                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5107                                                             next_protocol,
5108                                                             error);
5109                         if (ret < 0)
5110                                 return ret;
5111                         item_ipv6_proto = IPPROTO_ICMPV6;
5112                         last_item = MLX5_FLOW_LAYER_ICMP6;
5113                         break;
5114                 case RTE_FLOW_ITEM_TYPE_TAG:
5115                         ret = flow_dv_validate_item_tag(dev, items,
5116                                                         attr, error);
5117                         if (ret < 0)
5118                                 return ret;
5119                         last_item = MLX5_FLOW_ITEM_TAG;
5120                         break;
5121                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5122                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5123                         break;
5124                 case RTE_FLOW_ITEM_TYPE_GTP:
5125                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5126                                                         error);
5127                         if (ret < 0)
5128                                 return ret;
5129                         last_item = MLX5_FLOW_LAYER_GTP;
5130                         break;
5131                 default:
5132                         return rte_flow_error_set(error, ENOTSUP,
5133                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5134                                                   NULL, "item not supported");
5135                 }
5136                 item_flags |= last_item;
5137         }
5138         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5139                 int type = actions->type;
5140                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5141                         return rte_flow_error_set(error, ENOTSUP,
5142                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5143                                                   actions, "too many actions");
5144                 switch (type) {
5145                 case RTE_FLOW_ACTION_TYPE_VOID:
5146                         break;
5147                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5148                         ret = flow_dv_validate_action_port_id(dev,
5149                                                               action_flags,
5150                                                               actions,
5151                                                               attr,
5152                                                               error);
5153                         if (ret)
5154                                 return ret;
5155                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5156                         ++actions_n;
5157                         break;
5158                 case RTE_FLOW_ACTION_TYPE_FLAG:
5159                         ret = flow_dv_validate_action_flag(dev, action_flags,
5160                                                            attr, error);
5161                         if (ret < 0)
5162                                 return ret;
5163                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5164                                 /* Count all modify-header actions as one. */
5165                                 if (!(action_flags &
5166                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5167                                         ++actions_n;
5168                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5169                                                 MLX5_FLOW_ACTION_MARK_EXT;
5170                         } else {
5171                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5172                                 ++actions_n;
5173                         }
5174                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5175                         break;
5176                 case RTE_FLOW_ACTION_TYPE_MARK:
5177                         ret = flow_dv_validate_action_mark(dev, actions,
5178                                                            action_flags,
5179                                                            attr, error);
5180                         if (ret < 0)
5181                                 return ret;
5182                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5183                                 /* Count all modify-header actions as one. */
5184                                 if (!(action_flags &
5185                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5186                                         ++actions_n;
5187                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5188                                                 MLX5_FLOW_ACTION_MARK_EXT;
5189                         } else {
5190                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5191                                 ++actions_n;
5192                         }
5193                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5194                         break;
5195                 case RTE_FLOW_ACTION_TYPE_SET_META:
5196                         ret = flow_dv_validate_action_set_meta(dev, actions,
5197                                                                action_flags,
5198                                                                attr, error);
5199                         if (ret < 0)
5200                                 return ret;
5201                         /* Count all modify-header actions as one action. */
5202                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5203                                 ++actions_n;
5204                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5205                         rw_act_num += MLX5_ACT_NUM_SET_META;
5206                         break;
5207                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5208                         ret = flow_dv_validate_action_set_tag(dev, actions,
5209                                                               action_flags,
5210                                                               attr, error);
5211                         if (ret < 0)
5212                                 return ret;
5213                         /* Count all modify-header actions as one action. */
5214                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5215                                 ++actions_n;
5216                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5217                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5218                         break;
5219                 case RTE_FLOW_ACTION_TYPE_DROP:
5220                         ret = mlx5_flow_validate_action_drop(action_flags,
5221                                                              attr, error);
5222                         if (ret < 0)
5223                                 return ret;
5224                         action_flags |= MLX5_FLOW_ACTION_DROP;
5225                         ++actions_n;
5226                         break;
5227                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5228                         ret = mlx5_flow_validate_action_queue(actions,
5229                                                               action_flags, dev,
5230                                                               attr, error);
5231                         if (ret < 0)
5232                                 return ret;
5233                         queue_index = ((const struct rte_flow_action_queue *)
5234                                                         (actions->conf))->index;
5235                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5236                         ++actions_n;
5237                         break;
5238                 case RTE_FLOW_ACTION_TYPE_RSS:
5239                         rss = actions->conf;
5240                         ret = mlx5_flow_validate_action_rss(actions,
5241                                                             action_flags, dev,
5242                                                             attr, item_flags,
5243                                                             error);
5244                         if (ret < 0)
5245                                 return ret;
5246                         if (rss != NULL && rss->queue_num)
5247                                 queue_index = rss->queue[0];
5248                         action_flags |= MLX5_FLOW_ACTION_RSS;
5249                         ++actions_n;
5250                         break;
5251                 case RTE_FLOW_ACTION_TYPE_COUNT:
5252                         ret = flow_dv_validate_action_count(dev, error);
5253                         if (ret < 0)
5254                                 return ret;
5255                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5256                         ++actions_n;
5257                         break;
5258                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5259                         if (flow_dv_validate_action_pop_vlan(dev,
5260                                                              action_flags,
5261                                                              actions,
5262                                                              item_flags, attr,
5263                                                              error))
5264                                 return -rte_errno;
5265                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5266                         ++actions_n;
5267                         break;
5268                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5269                         ret = flow_dv_validate_action_push_vlan(dev,
5270                                                                 action_flags,
5271                                                                 vlan_m,
5272                                                                 actions, attr,
5273                                                                 error);
5274                         if (ret < 0)
5275                                 return ret;
5276                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5277                         ++actions_n;
5278                         break;
5279                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5280                         ret = flow_dv_validate_action_set_vlan_pcp
5281                                                 (action_flags, actions, error);
5282                         if (ret < 0)
5283                                 return ret;
5284                         /* Count PCP with push_vlan command. */
5285                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5286                         break;
5287                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5288                         ret = flow_dv_validate_action_set_vlan_vid
5289                                                 (item_flags, action_flags,
5290                                                  actions, error);
5291                         if (ret < 0)
5292                                 return ret;
5293                         /* Count VID with push_vlan command. */
5294                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5295                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5296                         break;
5297                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5298                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5299                         ret = flow_dv_validate_action_l2_encap(dev,
5300                                                                action_flags,
5301                                                                actions, attr,
5302                                                                error);
5303                         if (ret < 0)
5304                                 return ret;
5305                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5306                         ++actions_n;
5307                         break;
5308                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5309                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5310                         ret = flow_dv_validate_action_decap(dev, action_flags,
5311                                                             attr, error);
5312                         if (ret < 0)
5313                                 return ret;
5314                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5315                         ++actions_n;
5316                         break;
5317                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5318                         ret = flow_dv_validate_action_raw_encap_decap
5319                                 (dev, NULL, actions->conf, attr, &action_flags,
5320                                  &actions_n, error);
5321                         if (ret < 0)
5322                                 return ret;
5323                         break;
5324                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5325                         decap = actions->conf;
5326                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5327                                 ;
5328                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5329                                 encap = NULL;
5330                                 actions--;
5331                         } else {
5332                                 encap = actions->conf;
5333                         }
5334                         ret = flow_dv_validate_action_raw_encap_decap
5335                                            (dev,
5336                                             decap ? decap : &empty_decap, encap,
5337                                             attr, &action_flags, &actions_n,
5338                                             error);
5339                         if (ret < 0)
5340                                 return ret;
5341                         break;
5342                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5343                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5344                         ret = flow_dv_validate_action_modify_mac(action_flags,
5345                                                                  actions,
5346                                                                  item_flags,
5347                                                                  error);
5348                         if (ret < 0)
5349                                 return ret;
5350                         /* Count all modify-header actions as one action. */
5351                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5352                                 ++actions_n;
5353                         action_flags |= actions->type ==
5354                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5355                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5356                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5357                         /*
5358                          * Even if the source and destination MAC addresses have
5359                          * overlap in the header with 4B alignment, the convert
5360                          * function will handle them separately and 4 SW actions
5361                          * will be created. And 2 actions will be added each
5362                          * time no matter how many bytes of address will be set.
5363                          */
5364                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5365                         break;
5366                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5367                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5368                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5369                                                                   actions,
5370                                                                   item_flags,
5371                                                                   error);
5372                         if (ret < 0)
5373                                 return ret;
5374                         /* Count all modify-header actions as one action. */
5375                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5376                                 ++actions_n;
5377                         action_flags |= actions->type ==
5378                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5379                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5380                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5381                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5382                         break;
5383                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5384                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5385                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5386                                                                   actions,
5387                                                                   item_flags,
5388                                                                   error);
5389                         if (ret < 0)
5390                                 return ret;
5391                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5392                                 return rte_flow_error_set(error, ENOTSUP,
5393                                         RTE_FLOW_ERROR_TYPE_ACTION,
5394                                         actions,
5395                                         "Can't change header "
5396                                         "with ICMPv6 proto");
5397                         /* Count all modify-header actions as one action. */
5398                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5399                                 ++actions_n;
5400                         action_flags |= actions->type ==
5401                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5402                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5403                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5404                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5405                         break;
5406                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5407                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5408                         ret = flow_dv_validate_action_modify_tp(action_flags,
5409                                                                 actions,
5410                                                                 item_flags,
5411                                                                 error);
5412                         if (ret < 0)
5413                                 return ret;
5414                         /* Count all modify-header actions as one action. */
5415                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5416                                 ++actions_n;
5417                         action_flags |= actions->type ==
5418                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5419                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5420                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5421                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5422                         break;
5423                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5424                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5425                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5426                                                                  actions,
5427                                                                  item_flags,
5428                                                                  error);
5429                         if (ret < 0)
5430                                 return ret;
5431                         /* Count all modify-header actions as one action. */
5432                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5433                                 ++actions_n;
5434                         action_flags |= actions->type ==
5435                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5436                                                 MLX5_FLOW_ACTION_SET_TTL :
5437                                                 MLX5_FLOW_ACTION_DEC_TTL;
5438                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5439                         break;
5440                 case RTE_FLOW_ACTION_TYPE_JUMP:
5441                         ret = flow_dv_validate_action_jump(actions,
5442                                                            action_flags,
5443                                                            attr, external,
5444                                                            error);
5445                         if (ret)
5446                                 return ret;
5447                         ++actions_n;
5448                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5449                         break;
5450                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5451                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5452                         ret = flow_dv_validate_action_modify_tcp_seq
5453                                                                 (action_flags,
5454                                                                  actions,
5455                                                                  item_flags,
5456                                                                  error);
5457                         if (ret < 0)
5458                                 return ret;
5459                         /* Count all modify-header actions as one action. */
5460                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5461                                 ++actions_n;
5462                         action_flags |= actions->type ==
5463                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5464                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5465                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5466                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5467                         break;
5468                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5469                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5470                         ret = flow_dv_validate_action_modify_tcp_ack
5471                                                                 (action_flags,
5472                                                                  actions,
5473                                                                  item_flags,
5474                                                                  error);
5475                         if (ret < 0)
5476                                 return ret;
5477                         /* Count all modify-header actions as one action. */
5478                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5479                                 ++actions_n;
5480                         action_flags |= actions->type ==
5481                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5482                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5483                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5484                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5485                         break;
5486                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5487                         break;
5488                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5489                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5490                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5491                         break;
5492                 case RTE_FLOW_ACTION_TYPE_METER:
5493                         ret = mlx5_flow_validate_action_meter(dev,
5494                                                               action_flags,
5495                                                               actions, attr,
5496                                                               error);
5497                         if (ret < 0)
5498                                 return ret;
5499                         action_flags |= MLX5_FLOW_ACTION_METER;
5500                         ++actions_n;
5501                         /* Meter action will add one more TAG action. */
5502                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5503                         break;
5504                 case RTE_FLOW_ACTION_TYPE_AGE:
5505                         ret = flow_dv_validate_action_age(action_flags,
5506                                                           actions, dev,
5507                                                           error);
5508                         if (ret < 0)
5509                                 return ret;
5510                         action_flags |= MLX5_FLOW_ACTION_AGE;
5511                         ++actions_n;
5512                         break;
5513                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5514                         ret = flow_dv_validate_action_modify_ipv4_dscp
5515                                                          (action_flags,
5516                                                           actions,
5517                                                           item_flags,
5518                                                           error);
5519                         if (ret < 0)
5520                                 return ret;
5521                         /* Count all modify-header actions as one action. */
5522                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5523                                 ++actions_n;
5524                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5525                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5526                         break;
5527                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5528                         ret = flow_dv_validate_action_modify_ipv6_dscp
5529                                                                 (action_flags,
5530                                                                  actions,
5531                                                                  item_flags,
5532                                                                  error);
5533                         if (ret < 0)
5534                                 return ret;
5535                         /* Count all modify-header actions as one action. */
5536                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5537                                 ++actions_n;
5538                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5539                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5540                         break;
5541                 default:
5542                         return rte_flow_error_set(error, ENOTSUP,
5543                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5544                                                   actions,
5545                                                   "action not supported");
5546                 }
5547         }
5548         /*
5549          * Validate the drop action mutual exclusion with other actions.
5550          * Drop action is mutually-exclusive with any other action, except for
5551          * Count action.
5552          */
5553         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5554             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5555                 return rte_flow_error_set(error, EINVAL,
5556                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5557                                           "Drop action is mutually-exclusive "
5558                                           "with any other action, except for "
5559                                           "Count action");
5560         /* Eswitch has few restrictions on using items and actions */
5561         if (attr->transfer) {
5562                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5563                     action_flags & MLX5_FLOW_ACTION_FLAG)
5564                         return rte_flow_error_set(error, ENOTSUP,
5565                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5566                                                   NULL,
5567                                                   "unsupported action FLAG");
5568                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5569                     action_flags & MLX5_FLOW_ACTION_MARK)
5570                         return rte_flow_error_set(error, ENOTSUP,
5571                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5572                                                   NULL,
5573                                                   "unsupported action MARK");
5574                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5575                         return rte_flow_error_set(error, ENOTSUP,
5576                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5577                                                   NULL,
5578                                                   "unsupported action QUEUE");
5579                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5580                         return rte_flow_error_set(error, ENOTSUP,
5581                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5582                                                   NULL,
5583                                                   "unsupported action RSS");
5584                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5585                         return rte_flow_error_set(error, EINVAL,
5586                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5587                                                   actions,
5588                                                   "no fate action is found");
5589         } else {
5590                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5591                         return rte_flow_error_set(error, EINVAL,
5592                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5593                                                   actions,
5594                                                   "no fate action is found");
5595         }
5596         /* Continue validation for Xcap actions.*/
5597         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5598             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5599                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5600                     MLX5_FLOW_XCAP_ACTIONS)
5601                         return rte_flow_error_set(error, ENOTSUP,
5602                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5603                                                   NULL, "encap and decap "
5604                                                   "combination aren't supported");
5605                 if (!attr->transfer && attr->ingress && (action_flags &
5606                                                         MLX5_FLOW_ACTION_ENCAP))
5607                         return rte_flow_error_set(error, ENOTSUP,
5608                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5609                                                   NULL, "encap is not supported"
5610                                                   " for ingress traffic");
5611         }
5612         /* Hairpin flow will add one more TAG action. */
5613         if (hairpin > 0)
5614                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5615         /* extra metadata enabled: one more TAG action will be add. */
5616         if (dev_conf->dv_flow_en &&
5617             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5618             mlx5_flow_ext_mreg_supported(dev))
5619                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5620         if ((uint32_t)rw_act_num >
5621                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5622                 return rte_flow_error_set(error, ENOTSUP,
5623                                           RTE_FLOW_ERROR_TYPE_ACTION,
5624                                           NULL, "too many header modify"
5625                                           " actions to support");
5626         }
5627         return 0;
5628 }
5629
5630 /**
5631  * Internal preparation function. Allocates the DV flow size,
5632  * this size is constant.
5633  *
5634  * @param[in] dev
5635  *   Pointer to the rte_eth_dev structure.
5636  * @param[in] attr
5637  *   Pointer to the flow attributes.
5638  * @param[in] items
5639  *   Pointer to the list of items.
5640  * @param[in] actions
5641  *   Pointer to the list of actions.
5642  * @param[out] error
5643  *   Pointer to the error structure.
5644  *
5645  * @return
5646  *   Pointer to mlx5_flow object on success,
5647  *   otherwise NULL and rte_errno is set.
5648  */
5649 static struct mlx5_flow *
5650 flow_dv_prepare(struct rte_eth_dev *dev,
5651                 const struct rte_flow_attr *attr __rte_unused,
5652                 const struct rte_flow_item items[] __rte_unused,
5653                 const struct rte_flow_action actions[] __rte_unused,
5654                 struct rte_flow_error *error)
5655 {
5656         uint32_t handle_idx = 0;
5657         struct mlx5_flow *dev_flow;
5658         struct mlx5_flow_handle *dev_handle;
5659         struct mlx5_priv *priv = dev->data->dev_private;
5660
5661         /* In case of corrupting the memory. */
5662         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5663                 rte_flow_error_set(error, ENOSPC,
5664                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5665                                    "not free temporary device flow");
5666                 return NULL;
5667         }
5668         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5669                                    &handle_idx);
5670         if (!dev_handle) {
5671                 rte_flow_error_set(error, ENOMEM,
5672                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5673                                    "not enough memory to create flow handle");
5674                 return NULL;
5675         }
5676         /* No multi-thread supporting. */
5677         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5678         dev_flow->handle = dev_handle;
5679         dev_flow->handle_idx = handle_idx;
5680         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5681         /*
5682          * The matching value needs to be cleared to 0 before using. In the
5683          * past, it will be automatically cleared when using rte_*alloc
5684          * API. The time consumption will be almost the same as before.
5685          */
5686         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5687         dev_flow->ingress = attr->ingress;
5688         dev_flow->dv.transfer = attr->transfer;
5689         return dev_flow;
5690 }
5691
5692 #ifdef RTE_LIBRTE_MLX5_DEBUG
5693 /**
5694  * Sanity check for match mask and value. Similar to check_valid_spec() in
5695  * kernel driver. If unmasked bit is present in value, it returns failure.
5696  *
5697  * @param match_mask
5698  *   pointer to match mask buffer.
5699  * @param match_value
5700  *   pointer to match value buffer.
5701  *
5702  * @return
5703  *   0 if valid, -EINVAL otherwise.
5704  */
5705 static int
5706 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5707 {
5708         uint8_t *m = match_mask;
5709         uint8_t *v = match_value;
5710         unsigned int i;
5711
5712         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5713                 if (v[i] & ~m[i]) {
5714                         DRV_LOG(ERR,
5715                                 "match_value differs from match_criteria"
5716                                 " %p[%u] != %p[%u]",
5717                                 match_value, i, match_mask, i);
5718                         return -EINVAL;
5719                 }
5720         }
5721         return 0;
5722 }
5723 #endif
5724
5725 /**
5726  * Add match of ip_version.
5727  *
5728  * @param[in] group
5729  *   Flow group.
5730  * @param[in] headers_v
5731  *   Values header pointer.
5732  * @param[in] headers_m
5733  *   Masks header pointer.
5734  * @param[in] ip_version
5735  *   The IP version to set.
5736  */
5737 static inline void
5738 flow_dv_set_match_ip_version(uint32_t group,
5739                              void *headers_v,
5740                              void *headers_m,
5741                              uint8_t ip_version)
5742 {
5743         if (group == 0)
5744                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5745         else
5746                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5747                          ip_version);
5748         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5749         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5750         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5751 }
5752
5753 /**
5754  * Add Ethernet item to matcher and to the value.
5755  *
5756  * @param[in, out] matcher
5757  *   Flow matcher.
5758  * @param[in, out] key
5759  *   Flow matcher value.
5760  * @param[in] item
5761  *   Flow pattern to translate.
5762  * @param[in] inner
5763  *   Item is inner pattern.
5764  */
5765 static void
5766 flow_dv_translate_item_eth(void *matcher, void *key,
5767                            const struct rte_flow_item *item, int inner,
5768                            uint32_t group)
5769 {
5770         const struct rte_flow_item_eth *eth_m = item->mask;
5771         const struct rte_flow_item_eth *eth_v = item->spec;
5772         const struct rte_flow_item_eth nic_mask = {
5773                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5774                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5775                 .type = RTE_BE16(0xffff),
5776         };
5777         void *headers_m;
5778         void *headers_v;
5779         char *l24_v;
5780         unsigned int i;
5781
5782         if (!eth_v)
5783                 return;
5784         if (!eth_m)
5785                 eth_m = &nic_mask;
5786         if (inner) {
5787                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5788                                          inner_headers);
5789                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5790         } else {
5791                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5792                                          outer_headers);
5793                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5794         }
5795         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5796                &eth_m->dst, sizeof(eth_m->dst));
5797         /* The value must be in the range of the mask. */
5798         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5799         for (i = 0; i < sizeof(eth_m->dst); ++i)
5800                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5801         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5802                &eth_m->src, sizeof(eth_m->src));
5803         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5804         /* The value must be in the range of the mask. */
5805         for (i = 0; i < sizeof(eth_m->dst); ++i)
5806                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5807         if (eth_v->type) {
5808                 /* When ethertype is present set mask for tagged VLAN. */
5809                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5810                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5811                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5812                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5813                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5814                                  1);
5815                         /* Return here to avoid setting match on ethertype. */
5816                         return;
5817                 }
5818         }
5819         /*
5820          * HW supports match on one Ethertype, the Ethertype following the last
5821          * VLAN tag of the packet (see PRM).
5822          * Set match on ethertype only if ETH header is not followed by VLAN.
5823          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5824          * ethertype, and use ip_version field instead.
5825          */
5826         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5827             eth_m->type == 0xFFFF) {
5828                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5829         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5830                    eth_m->type == 0xFFFF) {
5831                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5832         } else {
5833                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5834                          rte_be_to_cpu_16(eth_m->type));
5835                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5836                                      ethertype);
5837                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5838         }
5839 }
5840
5841 /**
5842  * Add VLAN item to matcher and to the value.
5843  *
5844  * @param[in, out] dev_flow
5845  *   Flow descriptor.
5846  * @param[in, out] matcher
5847  *   Flow matcher.
5848  * @param[in, out] key
5849  *   Flow matcher value.
5850  * @param[in] item
5851  *   Flow pattern to translate.
5852  * @param[in] inner
5853  *   Item is inner pattern.
5854  */
5855 static void
5856 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5857                             void *matcher, void *key,
5858                             const struct rte_flow_item *item,
5859                             int inner, uint32_t group)
5860 {
5861         const struct rte_flow_item_vlan *vlan_m = item->mask;
5862         const struct rte_flow_item_vlan *vlan_v = item->spec;
5863         void *headers_m;
5864         void *headers_v;
5865         uint16_t tci_m;
5866         uint16_t tci_v;
5867
5868         if (inner) {
5869                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5870                                          inner_headers);
5871                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5872         } else {
5873                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5874                                          outer_headers);
5875                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5876                 /*
5877                  * This is workaround, masks are not supported,
5878                  * and pre-validated.
5879                  */
5880                 if (vlan_v)
5881                         dev_flow->handle->vf_vlan.tag =
5882                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5883         }
5884         /*
5885          * When VLAN item exists in flow, mark packet as tagged,
5886          * even if TCI is not specified.
5887          */
5888         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5889         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5890         if (!vlan_v)
5891                 return;
5892         if (!vlan_m)
5893                 vlan_m = &rte_flow_item_vlan_mask;
5894         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5895         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5896         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5897         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5898         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5899         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5900         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5901         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5902         /*
5903          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5904          * ethertype, and use ip_version field instead.
5905          */
5906         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5907             vlan_m->inner_type == 0xFFFF) {
5908                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5909         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5910                    vlan_m->inner_type == 0xFFFF) {
5911                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5912         } else {
5913                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5914                          rte_be_to_cpu_16(vlan_m->inner_type));
5915                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5916                          rte_be_to_cpu_16(vlan_m->inner_type &
5917                                           vlan_v->inner_type));
5918         }
5919 }
5920
5921 /**
5922  * Add IPV4 item to matcher and to the value.
5923  *
5924  * @param[in, out] matcher
5925  *   Flow matcher.
5926  * @param[in, out] key
5927  *   Flow matcher value.
5928  * @param[in] item
5929  *   Flow pattern to translate.
5930  * @param[in] item_flags
5931  *   Bit-fields that holds the items detected until now.
5932  * @param[in] inner
5933  *   Item is inner pattern.
5934  * @param[in] group
5935  *   The group to insert the rule.
5936  */
5937 static void
5938 flow_dv_translate_item_ipv4(void *matcher, void *key,
5939                             const struct rte_flow_item *item,
5940                             const uint64_t item_flags,
5941                             int inner, uint32_t group)
5942 {
5943         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5944         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5945         const struct rte_flow_item_ipv4 nic_mask = {
5946                 .hdr = {
5947                         .src_addr = RTE_BE32(0xffffffff),
5948                         .dst_addr = RTE_BE32(0xffffffff),
5949                         .type_of_service = 0xff,
5950                         .next_proto_id = 0xff,
5951                         .time_to_live = 0xff,
5952                 },
5953         };
5954         void *headers_m;
5955         void *headers_v;
5956         char *l24_m;
5957         char *l24_v;
5958         uint8_t tos;
5959
5960         if (inner) {
5961                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5962                                          inner_headers);
5963                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5964         } else {
5965                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5966                                          outer_headers);
5967                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5968         }
5969         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5970         /*
5971          * On outer header (which must contains L2), or inner header with L2,
5972          * set cvlan_tag mask bit to mark this packet as untagged.
5973          * This should be done even if item->spec is empty.
5974          */
5975         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5976                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5977         if (!ipv4_v)
5978                 return;
5979         if (!ipv4_m)
5980                 ipv4_m = &nic_mask;
5981         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5982                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5983         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5984                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5985         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5986         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5987         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5988                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5989         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5990                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5991         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5992         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5993         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5994         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5995                  ipv4_m->hdr.type_of_service);
5996         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5997         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5998                  ipv4_m->hdr.type_of_service >> 2);
5999         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6000         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6001                  ipv4_m->hdr.next_proto_id);
6002         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6003                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6004         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6005                  ipv4_m->hdr.time_to_live);
6006         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6007                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6008 }
6009
6010 /**
6011  * Add IPV6 item to matcher and to the value.
6012  *
6013  * @param[in, out] matcher
6014  *   Flow matcher.
6015  * @param[in, out] key
6016  *   Flow matcher value.
6017  * @param[in] item
6018  *   Flow pattern to translate.
6019  * @param[in] item_flags
6020  *   Bit-fields that holds the items detected until now.
6021  * @param[in] inner
6022  *   Item is inner pattern.
6023  * @param[in] group
6024  *   The group to insert the rule.
6025  */
6026 static void
6027 flow_dv_translate_item_ipv6(void *matcher, void *key,
6028                             const struct rte_flow_item *item,
6029                             const uint64_t item_flags,
6030                             int inner, uint32_t group)
6031 {
6032         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6033         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6034         const struct rte_flow_item_ipv6 nic_mask = {
6035                 .hdr = {
6036                         .src_addr =
6037                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6038                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6039                         .dst_addr =
6040                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6041                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6042                         .vtc_flow = RTE_BE32(0xffffffff),
6043                         .proto = 0xff,
6044                         .hop_limits = 0xff,
6045                 },
6046         };
6047         void *headers_m;
6048         void *headers_v;
6049         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6050         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6051         char *l24_m;
6052         char *l24_v;
6053         uint32_t vtc_m;
6054         uint32_t vtc_v;
6055         int i;
6056         int size;
6057
6058         if (inner) {
6059                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6060                                          inner_headers);
6061                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6062         } else {
6063                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6064                                          outer_headers);
6065                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6066         }
6067         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6068         /*
6069          * On outer header (which must contains L2), or inner header with L2,
6070          * set cvlan_tag mask bit to mark this packet as untagged.
6071          * This should be done even if item->spec is empty.
6072          */
6073         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6074                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6075         if (!ipv6_v)
6076                 return;
6077         if (!ipv6_m)
6078                 ipv6_m = &nic_mask;
6079         size = sizeof(ipv6_m->hdr.dst_addr);
6080         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6081                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6082         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6083                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6084         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6085         for (i = 0; i < size; ++i)
6086                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6087         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6088                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6089         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6090                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6091         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6092         for (i = 0; i < size; ++i)
6093                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6094         /* TOS. */
6095         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6096         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6097         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6098         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6099         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6100         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6101         /* Label. */
6102         if (inner) {
6103                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6104                          vtc_m);
6105                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6106                          vtc_v);
6107         } else {
6108                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6109                          vtc_m);
6110                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6111                          vtc_v);
6112         }
6113         /* Protocol. */
6114         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6115                  ipv6_m->hdr.proto);
6116         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6117                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6118         /* Hop limit. */
6119         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6120                  ipv6_m->hdr.hop_limits);
6121         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6122                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6123 }
6124
6125 /**
6126  * Add TCP item to matcher and to the value.
6127  *
6128  * @param[in, out] matcher
6129  *   Flow matcher.
6130  * @param[in, out] key
6131  *   Flow matcher value.
6132  * @param[in] item
6133  *   Flow pattern to translate.
6134  * @param[in] inner
6135  *   Item is inner pattern.
6136  */
6137 static void
6138 flow_dv_translate_item_tcp(void *matcher, void *key,
6139                            const struct rte_flow_item *item,
6140                            int inner)
6141 {
6142         const struct rte_flow_item_tcp *tcp_m = item->mask;
6143         const struct rte_flow_item_tcp *tcp_v = item->spec;
6144         void *headers_m;
6145         void *headers_v;
6146
6147         if (inner) {
6148                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6149                                          inner_headers);
6150                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6151         } else {
6152                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6153                                          outer_headers);
6154                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6155         }
6156         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6157         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6158         if (!tcp_v)
6159                 return;
6160         if (!tcp_m)
6161                 tcp_m = &rte_flow_item_tcp_mask;
6162         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6163                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6164         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6165                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6166         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6167                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6168         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6169                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6170         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6171                  tcp_m->hdr.tcp_flags);
6172         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6173                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6174 }
6175
6176 /**
6177  * Add UDP item to matcher and to the value.
6178  *
6179  * @param[in, out] matcher
6180  *   Flow matcher.
6181  * @param[in, out] key
6182  *   Flow matcher value.
6183  * @param[in] item
6184  *   Flow pattern to translate.
6185  * @param[in] inner
6186  *   Item is inner pattern.
6187  */
6188 static void
6189 flow_dv_translate_item_udp(void *matcher, void *key,
6190                            const struct rte_flow_item *item,
6191                            int inner)
6192 {
6193         const struct rte_flow_item_udp *udp_m = item->mask;
6194         const struct rte_flow_item_udp *udp_v = item->spec;
6195         void *headers_m;
6196         void *headers_v;
6197
6198         if (inner) {
6199                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6200                                          inner_headers);
6201                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6202         } else {
6203                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6204                                          outer_headers);
6205                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6206         }
6207         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6208         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6209         if (!udp_v)
6210                 return;
6211         if (!udp_m)
6212                 udp_m = &rte_flow_item_udp_mask;
6213         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6214                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6215         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6216                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6217         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6218                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6219         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6220                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6221 }
6222
6223 /**
6224  * Add GRE optional Key item to matcher and to the value.
6225  *
6226  * @param[in, out] matcher
6227  *   Flow matcher.
6228  * @param[in, out] key
6229  *   Flow matcher value.
6230  * @param[in] item
6231  *   Flow pattern to translate.
6232  * @param[in] inner
6233  *   Item is inner pattern.
6234  */
6235 static void
6236 flow_dv_translate_item_gre_key(void *matcher, void *key,
6237                                    const struct rte_flow_item *item)
6238 {
6239         const rte_be32_t *key_m = item->mask;
6240         const rte_be32_t *key_v = item->spec;
6241         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6242         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6243         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6244
6245         /* GRE K bit must be on and should already be validated */
6246         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6247         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6248         if (!key_v)
6249                 return;
6250         if (!key_m)
6251                 key_m = &gre_key_default_mask;
6252         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6253                  rte_be_to_cpu_32(*key_m) >> 8);
6254         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6255                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6256         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6257                  rte_be_to_cpu_32(*key_m) & 0xFF);
6258         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6259                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6260 }
6261
6262 /**
6263  * Add GRE item to matcher and to the value.
6264  *
6265  * @param[in, out] matcher
6266  *   Flow matcher.
6267  * @param[in, out] key
6268  *   Flow matcher value.
6269  * @param[in] item
6270  *   Flow pattern to translate.
6271  * @param[in] inner
6272  *   Item is inner pattern.
6273  */
6274 static void
6275 flow_dv_translate_item_gre(void *matcher, void *key,
6276                            const struct rte_flow_item *item,
6277                            int inner)
6278 {
6279         const struct rte_flow_item_gre *gre_m = item->mask;
6280         const struct rte_flow_item_gre *gre_v = item->spec;
6281         void *headers_m;
6282         void *headers_v;
6283         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6284         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6285         struct {
6286                 union {
6287                         __extension__
6288                         struct {
6289                                 uint16_t version:3;
6290                                 uint16_t rsvd0:9;
6291                                 uint16_t s_present:1;
6292                                 uint16_t k_present:1;
6293                                 uint16_t rsvd_bit1:1;
6294                                 uint16_t c_present:1;
6295                         };
6296                         uint16_t value;
6297                 };
6298         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6299
6300         if (inner) {
6301                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6302                                          inner_headers);
6303                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6304         } else {
6305                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6306                                          outer_headers);
6307                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6308         }
6309         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6310         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6311         if (!gre_v)
6312                 return;
6313         if (!gre_m)
6314                 gre_m = &rte_flow_item_gre_mask;
6315         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6316                  rte_be_to_cpu_16(gre_m->protocol));
6317         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6318                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6319         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6320         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6321         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6322                  gre_crks_rsvd0_ver_m.c_present);
6323         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6324                  gre_crks_rsvd0_ver_v.c_present &
6325                  gre_crks_rsvd0_ver_m.c_present);
6326         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6327                  gre_crks_rsvd0_ver_m.k_present);
6328         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6329                  gre_crks_rsvd0_ver_v.k_present &
6330                  gre_crks_rsvd0_ver_m.k_present);
6331         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6332                  gre_crks_rsvd0_ver_m.s_present);
6333         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6334                  gre_crks_rsvd0_ver_v.s_present &
6335                  gre_crks_rsvd0_ver_m.s_present);
6336 }
6337
6338 /**
6339  * Add NVGRE item to matcher and to the value.
6340  *
6341  * @param[in, out] matcher
6342  *   Flow matcher.
6343  * @param[in, out] key
6344  *   Flow matcher value.
6345  * @param[in] item
6346  *   Flow pattern to translate.
6347  * @param[in] inner
6348  *   Item is inner pattern.
6349  */
6350 static void
6351 flow_dv_translate_item_nvgre(void *matcher, void *key,
6352                              const struct rte_flow_item *item,
6353                              int inner)
6354 {
6355         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6356         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6357         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6358         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6359         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6360         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6361         char *gre_key_m;
6362         char *gre_key_v;
6363         int size;
6364         int i;
6365
6366         /* For NVGRE, GRE header fields must be set with defined values. */
6367         const struct rte_flow_item_gre gre_spec = {
6368                 .c_rsvd0_ver = RTE_BE16(0x2000),
6369                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6370         };
6371         const struct rte_flow_item_gre gre_mask = {
6372                 .c_rsvd0_ver = RTE_BE16(0xB000),
6373                 .protocol = RTE_BE16(UINT16_MAX),
6374         };
6375         const struct rte_flow_item gre_item = {
6376                 .spec = &gre_spec,
6377                 .mask = &gre_mask,
6378                 .last = NULL,
6379         };
6380         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6381         if (!nvgre_v)
6382                 return;
6383         if (!nvgre_m)
6384                 nvgre_m = &rte_flow_item_nvgre_mask;
6385         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6386         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6387         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6388         memcpy(gre_key_m, tni_flow_id_m, size);
6389         for (i = 0; i < size; ++i)
6390                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6391 }
6392
6393 /**
6394  * Add VXLAN item to matcher and to the value.
6395  *
6396  * @param[in, out] matcher
6397  *   Flow matcher.
6398  * @param[in, out] key
6399  *   Flow matcher value.
6400  * @param[in] item
6401  *   Flow pattern to translate.
6402  * @param[in] inner
6403  *   Item is inner pattern.
6404  */
6405 static void
6406 flow_dv_translate_item_vxlan(void *matcher, void *key,
6407                              const struct rte_flow_item *item,
6408                              int inner)
6409 {
6410         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6411         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6412         void *headers_m;
6413         void *headers_v;
6414         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6415         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6416         char *vni_m;
6417         char *vni_v;
6418         uint16_t dport;
6419         int size;
6420         int i;
6421
6422         if (inner) {
6423                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6424                                          inner_headers);
6425                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6426         } else {
6427                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6428                                          outer_headers);
6429                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6430         }
6431         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6432                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6433         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6434                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6435                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6436         }
6437         if (!vxlan_v)
6438                 return;
6439         if (!vxlan_m)
6440                 vxlan_m = &rte_flow_item_vxlan_mask;
6441         size = sizeof(vxlan_m->vni);
6442         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6443         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6444         memcpy(vni_m, vxlan_m->vni, size);
6445         for (i = 0; i < size; ++i)
6446                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6447 }
6448
6449 /**
6450  * Add VXLAN-GPE item to matcher and to the value.
6451  *
6452  * @param[in, out] matcher
6453  *   Flow matcher.
6454  * @param[in, out] key
6455  *   Flow matcher value.
6456  * @param[in] item
6457  *   Flow pattern to translate.
6458  * @param[in] inner
6459  *   Item is inner pattern.
6460  */
6461
6462 static void
6463 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6464                                  const struct rte_flow_item *item, int inner)
6465 {
6466         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6467         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6468         void *headers_m;
6469         void *headers_v;
6470         void *misc_m =
6471                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6472         void *misc_v =
6473                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6474         char *vni_m;
6475         char *vni_v;
6476         uint16_t dport;
6477         int size;
6478         int i;
6479         uint8_t flags_m = 0xff;
6480         uint8_t flags_v = 0xc;
6481
6482         if (inner) {
6483                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6484                                          inner_headers);
6485                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6486         } else {
6487                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6488                                          outer_headers);
6489                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6490         }
6491         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6492                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6493         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6494                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6495                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6496         }
6497         if (!vxlan_v)
6498                 return;
6499         if (!vxlan_m)
6500                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6501         size = sizeof(vxlan_m->vni);
6502         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6503         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6504         memcpy(vni_m, vxlan_m->vni, size);
6505         for (i = 0; i < size; ++i)
6506                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6507         if (vxlan_m->flags) {
6508                 flags_m = vxlan_m->flags;
6509                 flags_v = vxlan_v->flags;
6510         }
6511         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6512         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6513         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6514                  vxlan_m->protocol);
6515         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6516                  vxlan_v->protocol);
6517 }
6518
6519 /**
6520  * Add Geneve item to matcher and to the value.
6521  *
6522  * @param[in, out] matcher
6523  *   Flow matcher.
6524  * @param[in, out] key
6525  *   Flow matcher value.
6526  * @param[in] item
6527  *   Flow pattern to translate.
6528  * @param[in] inner
6529  *   Item is inner pattern.
6530  */
6531
6532 static void
6533 flow_dv_translate_item_geneve(void *matcher, void *key,
6534                               const struct rte_flow_item *item, int inner)
6535 {
6536         const struct rte_flow_item_geneve *geneve_m = item->mask;
6537         const struct rte_flow_item_geneve *geneve_v = item->spec;
6538         void *headers_m;
6539         void *headers_v;
6540         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6541         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6542         uint16_t dport;
6543         uint16_t gbhdr_m;
6544         uint16_t gbhdr_v;
6545         char *vni_m;
6546         char *vni_v;
6547         size_t size, i;
6548
6549         if (inner) {
6550                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6551                                          inner_headers);
6552                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6553         } else {
6554                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6555                                          outer_headers);
6556                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6557         }
6558         dport = MLX5_UDP_PORT_GENEVE;
6559         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6560                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6561                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6562         }
6563         if (!geneve_v)
6564                 return;
6565         if (!geneve_m)
6566                 geneve_m = &rte_flow_item_geneve_mask;
6567         size = sizeof(geneve_m->vni);
6568         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6569         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6570         memcpy(vni_m, geneve_m->vni, size);
6571         for (i = 0; i < size; ++i)
6572                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6573         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6574                  rte_be_to_cpu_16(geneve_m->protocol));
6575         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6576                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6577         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6578         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6579         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6580                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6581         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6582                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6583         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6584                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6585         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6586                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6587                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6588 }
6589
6590 /**
6591  * Add MPLS item to matcher and to the value.
6592  *
6593  * @param[in, out] matcher
6594  *   Flow matcher.
6595  * @param[in, out] key
6596  *   Flow matcher value.
6597  * @param[in] item
6598  *   Flow pattern to translate.
6599  * @param[in] prev_layer
6600  *   The protocol layer indicated in previous item.
6601  * @param[in] inner
6602  *   Item is inner pattern.
6603  */
6604 static void
6605 flow_dv_translate_item_mpls(void *matcher, void *key,
6606                             const struct rte_flow_item *item,
6607                             uint64_t prev_layer,
6608                             int inner)
6609 {
6610         const uint32_t *in_mpls_m = item->mask;
6611         const uint32_t *in_mpls_v = item->spec;
6612         uint32_t *out_mpls_m = 0;
6613         uint32_t *out_mpls_v = 0;
6614         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6615         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6616         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6617                                      misc_parameters_2);
6618         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6619         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6620         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6621
6622         switch (prev_layer) {
6623         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6624                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6625                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6626                          MLX5_UDP_PORT_MPLS);
6627                 break;
6628         case MLX5_FLOW_LAYER_GRE:
6629                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6630                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6631                          RTE_ETHER_TYPE_MPLS);
6632                 break;
6633         default:
6634                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6635                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6636                          IPPROTO_MPLS);
6637                 break;
6638         }
6639         if (!in_mpls_v)
6640                 return;
6641         if (!in_mpls_m)
6642                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6643         switch (prev_layer) {
6644         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6645                 out_mpls_m =
6646                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6647                                                  outer_first_mpls_over_udp);
6648                 out_mpls_v =
6649                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6650                                                  outer_first_mpls_over_udp);
6651                 break;
6652         case MLX5_FLOW_LAYER_GRE:
6653                 out_mpls_m =
6654                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6655                                                  outer_first_mpls_over_gre);
6656                 out_mpls_v =
6657                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6658                                                  outer_first_mpls_over_gre);
6659                 break;
6660         default:
6661                 /* Inner MPLS not over GRE is not supported. */
6662                 if (!inner) {
6663                         out_mpls_m =
6664                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6665                                                          misc2_m,
6666                                                          outer_first_mpls);
6667                         out_mpls_v =
6668                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6669                                                          misc2_v,
6670                                                          outer_first_mpls);
6671                 }
6672                 break;
6673         }
6674         if (out_mpls_m && out_mpls_v) {
6675                 *out_mpls_m = *in_mpls_m;
6676                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6677         }
6678 }
6679
6680 /**
6681  * Add metadata register item to matcher
6682  *
6683  * @param[in, out] matcher
6684  *   Flow matcher.
6685  * @param[in, out] key
6686  *   Flow matcher value.
6687  * @param[in] reg_type
6688  *   Type of device metadata register
6689  * @param[in] value
6690  *   Register value
6691  * @param[in] mask
6692  *   Register mask
6693  */
6694 static void
6695 flow_dv_match_meta_reg(void *matcher, void *key,
6696                        enum modify_reg reg_type,
6697                        uint32_t data, uint32_t mask)
6698 {
6699         void *misc2_m =
6700                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6701         void *misc2_v =
6702                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6703         uint32_t temp;
6704
6705         data &= mask;
6706         switch (reg_type) {
6707         case REG_A:
6708                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6709                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6710                 break;
6711         case REG_B:
6712                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6713                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6714                 break;
6715         case REG_C_0:
6716                 /*
6717                  * The metadata register C0 field might be divided into
6718                  * source vport index and META item value, we should set
6719                  * this field according to specified mask, not as whole one.
6720                  */
6721                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6722                 temp |= mask;
6723                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6724                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6725                 temp &= ~mask;
6726                 temp |= data;
6727                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6728                 break;
6729         case REG_C_1:
6730                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6731                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6732                 break;
6733         case REG_C_2:
6734                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6735                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6736                 break;
6737         case REG_C_3:
6738                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6739                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6740                 break;
6741         case REG_C_4:
6742                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6743                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6744                 break;
6745         case REG_C_5:
6746                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6747                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6748                 break;
6749         case REG_C_6:
6750                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6751                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6752                 break;
6753         case REG_C_7:
6754                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6755                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6756                 break;
6757         default:
6758                 MLX5_ASSERT(false);
6759                 break;
6760         }
6761 }
6762
6763 /**
6764  * Add MARK item to matcher
6765  *
6766  * @param[in] dev
6767  *   The device to configure through.
6768  * @param[in, out] matcher
6769  *   Flow matcher.
6770  * @param[in, out] key
6771  *   Flow matcher value.
6772  * @param[in] item
6773  *   Flow pattern to translate.
6774  */
6775 static void
6776 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6777                             void *matcher, void *key,
6778                             const struct rte_flow_item *item)
6779 {
6780         struct mlx5_priv *priv = dev->data->dev_private;
6781         const struct rte_flow_item_mark *mark;
6782         uint32_t value;
6783         uint32_t mask;
6784
6785         mark = item->mask ? (const void *)item->mask :
6786                             &rte_flow_item_mark_mask;
6787         mask = mark->id & priv->sh->dv_mark_mask;
6788         mark = (const void *)item->spec;
6789         MLX5_ASSERT(mark);
6790         value = mark->id & priv->sh->dv_mark_mask & mask;
6791         if (mask) {
6792                 enum modify_reg reg;
6793
6794                 /* Get the metadata register index for the mark. */
6795                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6796                 MLX5_ASSERT(reg > 0);
6797                 if (reg == REG_C_0) {
6798                         struct mlx5_priv *priv = dev->data->dev_private;
6799                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6800                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6801
6802                         mask &= msk_c0;
6803                         mask <<= shl_c0;
6804                         value <<= shl_c0;
6805                 }
6806                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6807         }
6808 }
6809
6810 /**
6811  * Add META item to matcher
6812  *
6813  * @param[in] dev
6814  *   The devich to configure through.
6815  * @param[in, out] matcher
6816  *   Flow matcher.
6817  * @param[in, out] key
6818  *   Flow matcher value.
6819  * @param[in] attr
6820  *   Attributes of flow that includes this item.
6821  * @param[in] item
6822  *   Flow pattern to translate.
6823  */
6824 static void
6825 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6826                             void *matcher, void *key,
6827                             const struct rte_flow_attr *attr,
6828                             const struct rte_flow_item *item)
6829 {
6830         const struct rte_flow_item_meta *meta_m;
6831         const struct rte_flow_item_meta *meta_v;
6832
6833         meta_m = (const void *)item->mask;
6834         if (!meta_m)
6835                 meta_m = &rte_flow_item_meta_mask;
6836         meta_v = (const void *)item->spec;
6837         if (meta_v) {
6838                 int reg;
6839                 uint32_t value = meta_v->data;
6840                 uint32_t mask = meta_m->data;
6841
6842                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6843                 if (reg < 0)
6844                         return;
6845                 /*
6846                  * In datapath code there is no endianness
6847                  * coversions for perfromance reasons, all
6848                  * pattern conversions are done in rte_flow.
6849                  */
6850                 value = rte_cpu_to_be_32(value);
6851                 mask = rte_cpu_to_be_32(mask);
6852                 if (reg == REG_C_0) {
6853                         struct mlx5_priv *priv = dev->data->dev_private;
6854                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6855                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6856 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6857                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6858
6859                         value >>= shr_c0;
6860                         mask >>= shr_c0;
6861 #endif
6862                         value <<= shl_c0;
6863                         mask <<= shl_c0;
6864                         MLX5_ASSERT(msk_c0);
6865                         MLX5_ASSERT(!(~msk_c0 & mask));
6866                 }
6867                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6868         }
6869 }
6870
6871 /**
6872  * Add vport metadata Reg C0 item to matcher
6873  *
6874  * @param[in, out] matcher
6875  *   Flow matcher.
6876  * @param[in, out] key
6877  *   Flow matcher value.
6878  * @param[in] reg
6879  *   Flow pattern to translate.
6880  */
6881 static void
6882 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6883                                   uint32_t value, uint32_t mask)
6884 {
6885         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6886 }
6887
6888 /**
6889  * Add tag item to matcher
6890  *
6891  * @param[in] dev
6892  *   The devich to configure through.
6893  * @param[in, out] matcher
6894  *   Flow matcher.
6895  * @param[in, out] key
6896  *   Flow matcher value.
6897  * @param[in] item
6898  *   Flow pattern to translate.
6899  */
6900 static void
6901 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6902                                 void *matcher, void *key,
6903                                 const struct rte_flow_item *item)
6904 {
6905         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6906         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6907         uint32_t mask, value;
6908
6909         MLX5_ASSERT(tag_v);
6910         value = tag_v->data;
6911         mask = tag_m ? tag_m->data : UINT32_MAX;
6912         if (tag_v->id == REG_C_0) {
6913                 struct mlx5_priv *priv = dev->data->dev_private;
6914                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6915                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6916
6917                 mask &= msk_c0;
6918                 mask <<= shl_c0;
6919                 value <<= shl_c0;
6920         }
6921         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6922 }
6923
6924 /**
6925  * Add TAG item to matcher
6926  *
6927  * @param[in] dev
6928  *   The devich to configure through.
6929  * @param[in, out] matcher
6930  *   Flow matcher.
6931  * @param[in, out] key
6932  *   Flow matcher value.
6933  * @param[in] item
6934  *   Flow pattern to translate.
6935  */
6936 static void
6937 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6938                            void *matcher, void *key,
6939                            const struct rte_flow_item *item)
6940 {
6941         const struct rte_flow_item_tag *tag_v = item->spec;
6942         const struct rte_flow_item_tag *tag_m = item->mask;
6943         enum modify_reg reg;
6944
6945         MLX5_ASSERT(tag_v);
6946         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6947         /* Get the metadata register index for the tag. */
6948         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6949         MLX5_ASSERT(reg > 0);
6950         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6951 }
6952
6953 /**
6954  * Add source vport match to the specified matcher.
6955  *
6956  * @param[in, out] matcher
6957  *   Flow matcher.
6958  * @param[in, out] key
6959  *   Flow matcher value.
6960  * @param[in] port
6961  *   Source vport value to match
6962  * @param[in] mask
6963  *   Mask
6964  */
6965 static void
6966 flow_dv_translate_item_source_vport(void *matcher, void *key,
6967                                     int16_t port, uint16_t mask)
6968 {
6969         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6970         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6971
6972         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6973         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6974 }
6975
6976 /**
6977  * Translate port-id item to eswitch match on  port-id.
6978  *
6979  * @param[in] dev
6980  *   The devich to configure through.
6981  * @param[in, out] matcher
6982  *   Flow matcher.
6983  * @param[in, out] key
6984  *   Flow matcher value.
6985  * @param[in] item
6986  *   Flow pattern to translate.
6987  *
6988  * @return
6989  *   0 on success, a negative errno value otherwise.
6990  */
6991 static int
6992 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6993                                void *key, const struct rte_flow_item *item)
6994 {
6995         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6996         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6997         struct mlx5_priv *priv;
6998         uint16_t mask, id;
6999
7000         mask = pid_m ? pid_m->id : 0xffff;
7001         id = pid_v ? pid_v->id : dev->data->port_id;
7002         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7003         if (!priv)
7004                 return -rte_errno;
7005         /* Translate to vport field or to metadata, depending on mode. */
7006         if (priv->vport_meta_mask)
7007                 flow_dv_translate_item_meta_vport(matcher, key,
7008                                                   priv->vport_meta_tag,
7009                                                   priv->vport_meta_mask);
7010         else
7011                 flow_dv_translate_item_source_vport(matcher, key,
7012                                                     priv->vport_id, mask);
7013         return 0;
7014 }
7015
7016 /**
7017  * Add ICMP6 item to matcher and to the value.
7018  *
7019  * @param[in, out] matcher
7020  *   Flow matcher.
7021  * @param[in, out] key
7022  *   Flow matcher value.
7023  * @param[in] item
7024  *   Flow pattern to translate.
7025  * @param[in] inner
7026  *   Item is inner pattern.
7027  */
7028 static void
7029 flow_dv_translate_item_icmp6(void *matcher, void *key,
7030                               const struct rte_flow_item *item,
7031                               int inner)
7032 {
7033         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7034         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7035         void *headers_m;
7036         void *headers_v;
7037         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7038                                      misc_parameters_3);
7039         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7040         if (inner) {
7041                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7042                                          inner_headers);
7043                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7044         } else {
7045                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7046                                          outer_headers);
7047                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7048         }
7049         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7050         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7051         if (!icmp6_v)
7052                 return;
7053         if (!icmp6_m)
7054                 icmp6_m = &rte_flow_item_icmp6_mask;
7055         /*
7056          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7057          * If only the protocol is specified, no need to match the frag.
7058          */
7059         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7060         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7061         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7062         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7063                  icmp6_v->type & icmp6_m->type);
7064         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7065         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7066                  icmp6_v->code & icmp6_m->code);
7067 }
7068
7069 /**
7070  * Add ICMP item to matcher and to the value.
7071  *
7072  * @param[in, out] matcher
7073  *   Flow matcher.
7074  * @param[in, out] key
7075  *   Flow matcher value.
7076  * @param[in] item
7077  *   Flow pattern to translate.
7078  * @param[in] inner
7079  *   Item is inner pattern.
7080  */
7081 static void
7082 flow_dv_translate_item_icmp(void *matcher, void *key,
7083                             const struct rte_flow_item *item,
7084                             int inner)
7085 {
7086         const struct rte_flow_item_icmp *icmp_m = item->mask;
7087         const struct rte_flow_item_icmp *icmp_v = item->spec;
7088         void *headers_m;
7089         void *headers_v;
7090         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7091                                      misc_parameters_3);
7092         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7093         if (inner) {
7094                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7095                                          inner_headers);
7096                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7097         } else {
7098                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7099                                          outer_headers);
7100                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7101         }
7102         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7103         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7104         if (!icmp_v)
7105                 return;
7106         if (!icmp_m)
7107                 icmp_m = &rte_flow_item_icmp_mask;
7108         /*
7109          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7110          * If only the protocol is specified, no need to match the frag.
7111          */
7112         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7113         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7114         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7115                  icmp_m->hdr.icmp_type);
7116         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7117                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7118         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7119                  icmp_m->hdr.icmp_code);
7120         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7121                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7122 }
7123
7124 /**
7125  * Add GTP item to matcher and to the value.
7126  *
7127  * @param[in, out] matcher
7128  *   Flow matcher.
7129  * @param[in, out] key
7130  *   Flow matcher value.
7131  * @param[in] item
7132  *   Flow pattern to translate.
7133  * @param[in] inner
7134  *   Item is inner pattern.
7135  */
7136 static void
7137 flow_dv_translate_item_gtp(void *matcher, void *key,
7138                            const struct rte_flow_item *item, int inner)
7139 {
7140         const struct rte_flow_item_gtp *gtp_m = item->mask;
7141         const struct rte_flow_item_gtp *gtp_v = item->spec;
7142         void *headers_m;
7143         void *headers_v;
7144         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7145                                      misc_parameters_3);
7146         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7147         uint16_t dport = RTE_GTPU_UDP_PORT;
7148
7149         if (inner) {
7150                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7151                                          inner_headers);
7152                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7153         } else {
7154                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7155                                          outer_headers);
7156                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7157         }
7158         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7159                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7160                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7161         }
7162         if (!gtp_v)
7163                 return;
7164         if (!gtp_m)
7165                 gtp_m = &rte_flow_item_gtp_mask;
7166         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7167                  gtp_m->v_pt_rsv_flags);
7168         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7169                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7170         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7171         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7172                  gtp_v->msg_type & gtp_m->msg_type);
7173         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7174                  rte_be_to_cpu_32(gtp_m->teid));
7175         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7176                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7177 }
7178
7179 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7180
7181 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7182         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7183                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7184
7185 /**
7186  * Calculate flow matcher enable bitmap.
7187  *
7188  * @param match_criteria
7189  *   Pointer to flow matcher criteria.
7190  *
7191  * @return
7192  *   Bitmap of enabled fields.
7193  */
7194 static uint8_t
7195 flow_dv_matcher_enable(uint32_t *match_criteria)
7196 {
7197         uint8_t match_criteria_enable;
7198
7199         match_criteria_enable =
7200                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7201                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7202         match_criteria_enable |=
7203                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7204                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7205         match_criteria_enable |=
7206                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7207                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7208         match_criteria_enable |=
7209                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7210                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7211         match_criteria_enable |=
7212                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7213                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7214         return match_criteria_enable;
7215 }
7216
7217
7218 /**
7219  * Get a flow table.
7220  *
7221  * @param[in, out] dev
7222  *   Pointer to rte_eth_dev structure.
7223  * @param[in] table_id
7224  *   Table id to use.
7225  * @param[in] egress
7226  *   Direction of the table.
7227  * @param[in] transfer
7228  *   E-Switch or NIC flow.
7229  * @param[out] error
7230  *   pointer to error structure.
7231  *
7232  * @return
7233  *   Returns tables resource based on the index, NULL in case of failed.
7234  */
7235 static struct mlx5_flow_tbl_resource *
7236 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7237                          uint32_t table_id, uint8_t egress,
7238                          uint8_t transfer,
7239                          struct rte_flow_error *error)
7240 {
7241         struct mlx5_priv *priv = dev->data->dev_private;
7242         struct mlx5_dev_ctx_shared *sh = priv->sh;
7243         struct mlx5_flow_tbl_resource *tbl;
7244         union mlx5_flow_tbl_key table_key = {
7245                 {
7246                         .table_id = table_id,
7247                         .reserved = 0,
7248                         .domain = !!transfer,
7249                         .direction = !!egress,
7250                 }
7251         };
7252         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7253                                                          table_key.v64);
7254         struct mlx5_flow_tbl_data_entry *tbl_data;
7255         uint32_t idx = 0;
7256         int ret;
7257         void *domain;
7258
7259         if (pos) {
7260                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7261                                         entry);
7262                 tbl = &tbl_data->tbl;
7263                 rte_atomic32_inc(&tbl->refcnt);
7264                 return tbl;
7265         }
7266         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7267         if (!tbl_data) {
7268                 rte_flow_error_set(error, ENOMEM,
7269                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7270                                    NULL,
7271                                    "cannot allocate flow table data entry");
7272                 return NULL;
7273         }
7274         tbl_data->idx = idx;
7275         tbl = &tbl_data->tbl;
7276         pos = &tbl_data->entry;
7277         if (transfer)
7278                 domain = sh->fdb_domain;
7279         else if (egress)
7280                 domain = sh->tx_domain;
7281         else
7282                 domain = sh->rx_domain;
7283         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7284         if (!tbl->obj) {
7285                 rte_flow_error_set(error, ENOMEM,
7286                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7287                                    NULL, "cannot create flow table object");
7288                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7289                 return NULL;
7290         }
7291         /*
7292          * No multi-threads now, but still better to initialize the reference
7293          * count before insert it into the hash list.
7294          */
7295         rte_atomic32_init(&tbl->refcnt);
7296         /* Jump action reference count is initialized here. */
7297         rte_atomic32_init(&tbl_data->jump.refcnt);
7298         pos->key = table_key.v64;
7299         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7300         if (ret < 0) {
7301                 rte_flow_error_set(error, -ret,
7302                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7303                                    "cannot insert flow table data entry");
7304                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7305                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7306         }
7307         rte_atomic32_inc(&tbl->refcnt);
7308         return tbl;
7309 }
7310
7311 /**
7312  * Release a flow table.
7313  *
7314  * @param[in] dev
7315  *   Pointer to rte_eth_dev structure.
7316  * @param[in] tbl
7317  *   Table resource to be released.
7318  *
7319  * @return
7320  *   Returns 0 if table was released, else return 1;
7321  */
7322 static int
7323 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7324                              struct mlx5_flow_tbl_resource *tbl)
7325 {
7326         struct mlx5_priv *priv = dev->data->dev_private;
7327         struct mlx5_dev_ctx_shared *sh = priv->sh;
7328         struct mlx5_flow_tbl_data_entry *tbl_data =
7329                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7330
7331         if (!tbl)
7332                 return 0;
7333         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7334                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7335
7336                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7337                 tbl->obj = NULL;
7338                 /* remove the entry from the hash list and free memory. */
7339                 mlx5_hlist_remove(sh->flow_tbls, pos);
7340                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7341                                 tbl_data->idx);
7342                 return 0;
7343         }
7344         return 1;
7345 }
7346
7347 /**
7348  * Register the flow matcher.
7349  *
7350  * @param[in, out] dev
7351  *   Pointer to rte_eth_dev structure.
7352  * @param[in, out] matcher
7353  *   Pointer to flow matcher.
7354  * @param[in, out] key
7355  *   Pointer to flow table key.
7356  * @parm[in, out] dev_flow
7357  *   Pointer to the dev_flow.
7358  * @param[out] error
7359  *   pointer to error structure.
7360  *
7361  * @return
7362  *   0 on success otherwise -errno and errno is set.
7363  */
7364 static int
7365 flow_dv_matcher_register(struct rte_eth_dev *dev,
7366                          struct mlx5_flow_dv_matcher *matcher,
7367                          union mlx5_flow_tbl_key *key,
7368                          struct mlx5_flow *dev_flow,
7369                          struct rte_flow_error *error)
7370 {
7371         struct mlx5_priv *priv = dev->data->dev_private;
7372         struct mlx5_dev_ctx_shared *sh = priv->sh;
7373         struct mlx5_flow_dv_matcher *cache_matcher;
7374         struct mlx5dv_flow_matcher_attr dv_attr = {
7375                 .type = IBV_FLOW_ATTR_NORMAL,
7376                 .match_mask = (void *)&matcher->mask,
7377         };
7378         struct mlx5_flow_tbl_resource *tbl;
7379         struct mlx5_flow_tbl_data_entry *tbl_data;
7380
7381         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7382                                        key->domain, error);
7383         if (!tbl)
7384                 return -rte_errno;      /* No need to refill the error info */
7385         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7386         /* Lookup from cache. */
7387         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7388                 if (matcher->crc == cache_matcher->crc &&
7389                     matcher->priority == cache_matcher->priority &&
7390                     !memcmp((const void *)matcher->mask.buf,
7391                             (const void *)cache_matcher->mask.buf,
7392                             cache_matcher->mask.size)) {
7393                         DRV_LOG(DEBUG,
7394                                 "%s group %u priority %hd use %s "
7395                                 "matcher %p: refcnt %d++",
7396                                 key->domain ? "FDB" : "NIC", key->table_id,
7397                                 cache_matcher->priority,
7398                                 key->direction ? "tx" : "rx",
7399                                 (void *)cache_matcher,
7400                                 rte_atomic32_read(&cache_matcher->refcnt));
7401                         rte_atomic32_inc(&cache_matcher->refcnt);
7402                         dev_flow->handle->dvh.matcher = cache_matcher;
7403                         /* old matcher should not make the table ref++. */
7404                         flow_dv_tbl_resource_release(dev, tbl);
7405                         return 0;
7406                 }
7407         }
7408         /* Register new matcher. */
7409         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7410         if (!cache_matcher) {
7411                 flow_dv_tbl_resource_release(dev, tbl);
7412                 return rte_flow_error_set(error, ENOMEM,
7413                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7414                                           "cannot allocate matcher memory");
7415         }
7416         *cache_matcher = *matcher;
7417         dv_attr.match_criteria_enable =
7418                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7419         dv_attr.priority = matcher->priority;
7420         if (key->direction)
7421                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7422         cache_matcher->matcher_object =
7423                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7424         if (!cache_matcher->matcher_object) {
7425                 rte_free(cache_matcher);
7426 #ifdef HAVE_MLX5DV_DR
7427                 flow_dv_tbl_resource_release(dev, tbl);
7428 #endif
7429                 return rte_flow_error_set(error, ENOMEM,
7430                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7431                                           NULL, "cannot create matcher");
7432         }
7433         /* Save the table information */
7434         cache_matcher->tbl = tbl;
7435         rte_atomic32_init(&cache_matcher->refcnt);
7436         /* only matcher ref++, table ref++ already done above in get API. */
7437         rte_atomic32_inc(&cache_matcher->refcnt);
7438         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7439         dev_flow->handle->dvh.matcher = cache_matcher;
7440         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7441                 key->domain ? "FDB" : "NIC", key->table_id,
7442                 cache_matcher->priority,
7443                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7444                 rte_atomic32_read(&cache_matcher->refcnt));
7445         return 0;
7446 }
7447
7448 /**
7449  * Find existing tag resource or create and register a new one.
7450  *
7451  * @param dev[in, out]
7452  *   Pointer to rte_eth_dev structure.
7453  * @param[in, out] tag_be24
7454  *   Tag value in big endian then R-shift 8.
7455  * @parm[in, out] dev_flow
7456  *   Pointer to the dev_flow.
7457  * @param[out] error
7458  *   pointer to error structure.
7459  *
7460  * @return
7461  *   0 on success otherwise -errno and errno is set.
7462  */
7463 static int
7464 flow_dv_tag_resource_register
7465                         (struct rte_eth_dev *dev,
7466                          uint32_t tag_be24,
7467                          struct mlx5_flow *dev_flow,
7468                          struct rte_flow_error *error)
7469 {
7470         struct mlx5_priv *priv = dev->data->dev_private;
7471         struct mlx5_dev_ctx_shared *sh = priv->sh;
7472         struct mlx5_flow_dv_tag_resource *cache_resource;
7473         struct mlx5_hlist_entry *entry;
7474
7475         /* Lookup a matching resource from cache. */
7476         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7477         if (entry) {
7478                 cache_resource = container_of
7479                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7480                 rte_atomic32_inc(&cache_resource->refcnt);
7481                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7482                 dev_flow->dv.tag_resource = cache_resource;
7483                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7484                         (void *)cache_resource,
7485                         rte_atomic32_read(&cache_resource->refcnt));
7486                 return 0;
7487         }
7488         /* Register new resource. */
7489         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7490                                        &dev_flow->handle->dvh.rix_tag);
7491         if (!cache_resource)
7492                 return rte_flow_error_set(error, ENOMEM,
7493                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7494                                           "cannot allocate resource memory");
7495         cache_resource->entry.key = (uint64_t)tag_be24;
7496         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7497         if (!cache_resource->action) {
7498                 rte_free(cache_resource);
7499                 return rte_flow_error_set(error, ENOMEM,
7500                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7501                                           NULL, "cannot create action");
7502         }
7503         rte_atomic32_init(&cache_resource->refcnt);
7504         rte_atomic32_inc(&cache_resource->refcnt);
7505         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7506                 mlx5_glue->destroy_flow_action(cache_resource->action);
7507                 rte_free(cache_resource);
7508                 return rte_flow_error_set(error, EEXIST,
7509                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7510                                           NULL, "cannot insert tag");
7511         }
7512         dev_flow->dv.tag_resource = cache_resource;
7513         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7514                 (void *)cache_resource,
7515                 rte_atomic32_read(&cache_resource->refcnt));
7516         return 0;
7517 }
7518
7519 /**
7520  * Release the tag.
7521  *
7522  * @param dev
7523  *   Pointer to Ethernet device.
7524  * @param tag_idx
7525  *   Tag index.
7526  *
7527  * @return
7528  *   1 while a reference on it exists, 0 when freed.
7529  */
7530 static int
7531 flow_dv_tag_release(struct rte_eth_dev *dev,
7532                     uint32_t tag_idx)
7533 {
7534         struct mlx5_priv *priv = dev->data->dev_private;
7535         struct mlx5_dev_ctx_shared *sh = priv->sh;
7536         struct mlx5_flow_dv_tag_resource *tag;
7537
7538         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7539         if (!tag)
7540                 return 0;
7541         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7542                 dev->data->port_id, (void *)tag,
7543                 rte_atomic32_read(&tag->refcnt));
7544         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7545                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7546                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7547                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7548                         dev->data->port_id, (void *)tag);
7549                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7550                 return 0;
7551         }
7552         return 1;
7553 }
7554
7555 /**
7556  * Translate port ID action to vport.
7557  *
7558  * @param[in] dev
7559  *   Pointer to rte_eth_dev structure.
7560  * @param[in] action
7561  *   Pointer to the port ID action.
7562  * @param[out] dst_port_id
7563  *   The target port ID.
7564  * @param[out] error
7565  *   Pointer to the error structure.
7566  *
7567  * @return
7568  *   0 on success, a negative errno value otherwise and rte_errno is set.
7569  */
7570 static int
7571 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7572                                  const struct rte_flow_action *action,
7573                                  uint32_t *dst_port_id,
7574                                  struct rte_flow_error *error)
7575 {
7576         uint32_t port;
7577         struct mlx5_priv *priv;
7578         const struct rte_flow_action_port_id *conf =
7579                         (const struct rte_flow_action_port_id *)action->conf;
7580
7581         port = conf->original ? dev->data->port_id : conf->id;
7582         priv = mlx5_port_to_eswitch_info(port, false);
7583         if (!priv)
7584                 return rte_flow_error_set(error, -rte_errno,
7585                                           RTE_FLOW_ERROR_TYPE_ACTION,
7586                                           NULL,
7587                                           "No eswitch info was found for port");
7588 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7589         /*
7590          * This parameter is transferred to
7591          * mlx5dv_dr_action_create_dest_ib_port().
7592          */
7593         *dst_port_id = priv->dev_port;
7594 #else
7595         /*
7596          * Legacy mode, no LAG configurations is supported.
7597          * This parameter is transferred to
7598          * mlx5dv_dr_action_create_dest_vport().
7599          */
7600         *dst_port_id = priv->vport_id;
7601 #endif
7602         return 0;
7603 }
7604
7605 /**
7606  * Create a counter with aging configuration.
7607  *
7608  * @param[in] dev
7609  *   Pointer to rte_eth_dev structure.
7610  * @param[out] count
7611  *   Pointer to the counter action configuration.
7612  * @param[in] age
7613  *   Pointer to the aging action configuration.
7614  *
7615  * @return
7616  *   Index to flow counter on success, 0 otherwise.
7617  */
7618 static uint32_t
7619 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7620                                 struct mlx5_flow *dev_flow,
7621                                 const struct rte_flow_action_count *count,
7622                                 const struct rte_flow_action_age *age)
7623 {
7624         uint32_t counter;
7625         struct mlx5_age_param *age_param;
7626
7627         counter = flow_dv_counter_alloc(dev,
7628                                 count ? count->shared : 0,
7629                                 count ? count->id : 0,
7630                                 dev_flow->dv.group, !!age);
7631         if (!counter || age == NULL)
7632                 return counter;
7633         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7634         /*
7635          * The counter age accuracy may have a bit delay. Have 3/4
7636          * second bias on the timeount in order to let it age in time.
7637          */
7638         age_param->context = age->context ? age->context :
7639                 (void *)(uintptr_t)(dev_flow->flow_idx);
7640         /*
7641          * The counter age accuracy may have a bit delay. Have 3/4
7642          * second bias on the timeount in order to let it age in time.
7643          */
7644         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7645         /* Set expire time in unit of 0.1 sec. */
7646         age_param->port_id = dev->data->port_id;
7647         age_param->expire = age_param->timeout +
7648                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7649         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7650         return counter;
7651 }
7652 /**
7653  * Add Tx queue matcher
7654  *
7655  * @param[in] dev
7656  *   Pointer to the dev struct.
7657  * @param[in, out] matcher
7658  *   Flow matcher.
7659  * @param[in, out] key
7660  *   Flow matcher value.
7661  * @param[in] item
7662  *   Flow pattern to translate.
7663  * @param[in] inner
7664  *   Item is inner pattern.
7665  */
7666 static void
7667 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7668                                 void *matcher, void *key,
7669                                 const struct rte_flow_item *item)
7670 {
7671         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7672         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7673         void *misc_m =
7674                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7675         void *misc_v =
7676                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7677         struct mlx5_txq_ctrl *txq;
7678         uint32_t queue;
7679
7680
7681         queue_m = (const void *)item->mask;
7682         if (!queue_m)
7683                 return;
7684         queue_v = (const void *)item->spec;
7685         if (!queue_v)
7686                 return;
7687         txq = mlx5_txq_get(dev, queue_v->queue);
7688         if (!txq)
7689                 return;
7690         queue = txq->obj->sq->id;
7691         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7692         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7693                  queue & queue_m->queue);
7694         mlx5_txq_release(dev, queue_v->queue);
7695 }
7696
7697 /**
7698  * Set the hash fields according to the @p flow information.
7699  *
7700  * @param[in] dev_flow
7701  *   Pointer to the mlx5_flow.
7702  * @param[in] rss_desc
7703  *   Pointer to the mlx5_flow_rss_desc.
7704  */
7705 static void
7706 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7707                        struct mlx5_flow_rss_desc *rss_desc)
7708 {
7709         uint64_t items = dev_flow->handle->layers;
7710         int rss_inner = 0;
7711         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7712
7713         dev_flow->hash_fields = 0;
7714 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7715         if (rss_desc->level >= 2) {
7716                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7717                 rss_inner = 1;
7718         }
7719 #endif
7720         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7721             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7722                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7723                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7724                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7725                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7726                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7727                         else
7728                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7729                 }
7730         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7731                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7732                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7733                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7734                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7735                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7736                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7737                         else
7738                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7739                 }
7740         }
7741         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7742             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7743                 if (rss_types & ETH_RSS_UDP) {
7744                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7745                                 dev_flow->hash_fields |=
7746                                                 IBV_RX_HASH_SRC_PORT_UDP;
7747                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7748                                 dev_flow->hash_fields |=
7749                                                 IBV_RX_HASH_DST_PORT_UDP;
7750                         else
7751                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7752                 }
7753         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7754                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7755                 if (rss_types & ETH_RSS_TCP) {
7756                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7757                                 dev_flow->hash_fields |=
7758                                                 IBV_RX_HASH_SRC_PORT_TCP;
7759                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7760                                 dev_flow->hash_fields |=
7761                                                 IBV_RX_HASH_DST_PORT_TCP;
7762                         else
7763                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7764                 }
7765         }
7766 }
7767
7768 /**
7769  * Fill the flow with DV spec, lock free
7770  * (mutex should be acquired by caller).
7771  *
7772  * @param[in] dev
7773  *   Pointer to rte_eth_dev structure.
7774  * @param[in, out] dev_flow
7775  *   Pointer to the sub flow.
7776  * @param[in] attr
7777  *   Pointer to the flow attributes.
7778  * @param[in] items
7779  *   Pointer to the list of items.
7780  * @param[in] actions
7781  *   Pointer to the list of actions.
7782  * @param[out] error
7783  *   Pointer to the error structure.
7784  *
7785  * @return
7786  *   0 on success, a negative errno value otherwise and rte_errno is set.
7787  */
7788 static int
7789 __flow_dv_translate(struct rte_eth_dev *dev,
7790                     struct mlx5_flow *dev_flow,
7791                     const struct rte_flow_attr *attr,
7792                     const struct rte_flow_item items[],
7793                     const struct rte_flow_action actions[],
7794                     struct rte_flow_error *error)
7795 {
7796         struct mlx5_priv *priv = dev->data->dev_private;
7797         struct mlx5_dev_config *dev_conf = &priv->config;
7798         struct rte_flow *flow = dev_flow->flow;
7799         struct mlx5_flow_handle *handle = dev_flow->handle;
7800         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7801                                               priv->rss_desc)
7802                                               [!!priv->flow_nested_idx];
7803         uint64_t item_flags = 0;
7804         uint64_t last_item = 0;
7805         uint64_t action_flags = 0;
7806         uint64_t priority = attr->priority;
7807         struct mlx5_flow_dv_matcher matcher = {
7808                 .mask = {
7809                         .size = sizeof(matcher.mask.buf),
7810                 },
7811         };
7812         int actions_n = 0;
7813         bool actions_end = false;
7814         union {
7815                 struct mlx5_flow_dv_modify_hdr_resource res;
7816                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7817                             sizeof(struct mlx5_modification_cmd) *
7818                             (MLX5_MAX_MODIFY_NUM + 1)];
7819         } mhdr_dummy;
7820         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7821         const struct rte_flow_action_count *count = NULL;
7822         const struct rte_flow_action_age *age = NULL;
7823         union flow_dv_attr flow_attr = { .attr = 0 };
7824         uint32_t tag_be;
7825         union mlx5_flow_tbl_key tbl_key;
7826         uint32_t modify_action_position = UINT32_MAX;
7827         void *match_mask = matcher.mask.buf;
7828         void *match_value = dev_flow->dv.value.buf;
7829         uint8_t next_protocol = 0xff;
7830         struct rte_vlan_hdr vlan = { 0 };
7831         uint32_t table;
7832         int ret = 0;
7833
7834         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7835                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7836         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7837                                        !!priv->fdb_def_rule, &table, error);
7838         if (ret)
7839                 return ret;
7840         dev_flow->dv.group = table;
7841         if (attr->transfer)
7842                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7843         if (priority == MLX5_FLOW_PRIO_RSVD)
7844                 priority = dev_conf->flow_prio - 1;
7845         /* number of actions must be set to 0 in case of dirty stack. */
7846         mhdr_res->actions_num = 0;
7847         for (; !actions_end ; actions++) {
7848                 const struct rte_flow_action_queue *queue;
7849                 const struct rte_flow_action_rss *rss;
7850                 const struct rte_flow_action *action = actions;
7851                 const uint8_t *rss_key;
7852                 const struct rte_flow_action_jump *jump_data;
7853                 const struct rte_flow_action_meter *mtr;
7854                 struct mlx5_flow_tbl_resource *tbl;
7855                 uint32_t port_id = 0;
7856                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7857                 int action_type = actions->type;
7858                 const struct rte_flow_action *found_action = NULL;
7859                 struct mlx5_flow_meter *fm = NULL;
7860
7861                 switch (action_type) {
7862                 case RTE_FLOW_ACTION_TYPE_VOID:
7863                         break;
7864                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7865                         if (flow_dv_translate_action_port_id(dev, action,
7866                                                              &port_id, error))
7867                                 return -rte_errno;
7868                         port_id_resource.port_id = port_id;
7869                         MLX5_ASSERT(!handle->rix_port_id_action);
7870                         if (flow_dv_port_id_action_resource_register
7871                             (dev, &port_id_resource, dev_flow, error))
7872                                 return -rte_errno;
7873                         dev_flow->dv.actions[actions_n++] =
7874                                         dev_flow->dv.port_id_action->action;
7875                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7876                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7877                         break;
7878                 case RTE_FLOW_ACTION_TYPE_FLAG:
7879                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7880                         dev_flow->handle->mark = 1;
7881                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7882                                 struct rte_flow_action_mark mark = {
7883                                         .id = MLX5_FLOW_MARK_DEFAULT,
7884                                 };
7885
7886                                 if (flow_dv_convert_action_mark(dev, &mark,
7887                                                                 mhdr_res,
7888                                                                 error))
7889                                         return -rte_errno;
7890                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7891                                 break;
7892                         }
7893                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7894                         /*
7895                          * Only one FLAG or MARK is supported per device flow
7896                          * right now. So the pointer to the tag resource must be
7897                          * zero before the register process.
7898                          */
7899                         MLX5_ASSERT(!handle->dvh.rix_tag);
7900                         if (flow_dv_tag_resource_register(dev, tag_be,
7901                                                           dev_flow, error))
7902                                 return -rte_errno;
7903                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7904                         dev_flow->dv.actions[actions_n++] =
7905                                         dev_flow->dv.tag_resource->action;
7906                         break;
7907                 case RTE_FLOW_ACTION_TYPE_MARK:
7908                         action_flags |= MLX5_FLOW_ACTION_MARK;
7909                         dev_flow->handle->mark = 1;
7910                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7911                                 const struct rte_flow_action_mark *mark =
7912                                         (const struct rte_flow_action_mark *)
7913                                                 actions->conf;
7914
7915                                 if (flow_dv_convert_action_mark(dev, mark,
7916                                                                 mhdr_res,
7917                                                                 error))
7918                                         return -rte_errno;
7919                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7920                                 break;
7921                         }
7922                         /* Fall-through */
7923                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7924                         /* Legacy (non-extensive) MARK action. */
7925                         tag_be = mlx5_flow_mark_set
7926                               (((const struct rte_flow_action_mark *)
7927                                (actions->conf))->id);
7928                         MLX5_ASSERT(!handle->dvh.rix_tag);
7929                         if (flow_dv_tag_resource_register(dev, tag_be,
7930                                                           dev_flow, error))
7931                                 return -rte_errno;
7932                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7933                         dev_flow->dv.actions[actions_n++] =
7934                                         dev_flow->dv.tag_resource->action;
7935                         break;
7936                 case RTE_FLOW_ACTION_TYPE_SET_META:
7937                         if (flow_dv_convert_action_set_meta
7938                                 (dev, mhdr_res, attr,
7939                                  (const struct rte_flow_action_set_meta *)
7940                                   actions->conf, error))
7941                                 return -rte_errno;
7942                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7943                         break;
7944                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7945                         if (flow_dv_convert_action_set_tag
7946                                 (dev, mhdr_res,
7947                                  (const struct rte_flow_action_set_tag *)
7948                                   actions->conf, error))
7949                                 return -rte_errno;
7950                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7951                         break;
7952                 case RTE_FLOW_ACTION_TYPE_DROP:
7953                         action_flags |= MLX5_FLOW_ACTION_DROP;
7954                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7955                         break;
7956                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7957                         queue = actions->conf;
7958                         rss_desc->queue_num = 1;
7959                         rss_desc->queue[0] = queue->index;
7960                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7961                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7962                         break;
7963                 case RTE_FLOW_ACTION_TYPE_RSS:
7964                         rss = actions->conf;
7965                         memcpy(rss_desc->queue, rss->queue,
7966                                rss->queue_num * sizeof(uint16_t));
7967                         rss_desc->queue_num = rss->queue_num;
7968                         /* NULL RSS key indicates default RSS key. */
7969                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7970                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7971                         /*
7972                          * rss->level and rss.types should be set in advance
7973                          * when expanding items for RSS.
7974                          */
7975                         action_flags |= MLX5_FLOW_ACTION_RSS;
7976                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7977                         break;
7978                 case RTE_FLOW_ACTION_TYPE_AGE:
7979                 case RTE_FLOW_ACTION_TYPE_COUNT:
7980                         if (!dev_conf->devx) {
7981                                 return rte_flow_error_set
7982                                               (error, ENOTSUP,
7983                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7984                                                NULL,
7985                                                "count action not supported");
7986                         }
7987                         /* Save information first, will apply later. */
7988                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7989                                 count = action->conf;
7990                         else
7991                                 age = action->conf;
7992                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7993                         break;
7994                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7995                         dev_flow->dv.actions[actions_n++] =
7996                                                 priv->sh->pop_vlan_action;
7997                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7998                         break;
7999                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8000                         if (!(action_flags &
8001                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8002                                 flow_dev_get_vlan_info_from_items(items, &vlan);
8003                         vlan.eth_proto = rte_be_to_cpu_16
8004                              ((((const struct rte_flow_action_of_push_vlan *)
8005                                                    actions->conf)->ethertype));
8006                         found_action = mlx5_flow_find_action
8007                                         (actions + 1,
8008                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8009                         if (found_action)
8010                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8011                         found_action = mlx5_flow_find_action
8012                                         (actions + 1,
8013                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8014                         if (found_action)
8015                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8016                         if (flow_dv_create_action_push_vlan
8017                                             (dev, attr, &vlan, dev_flow, error))
8018                                 return -rte_errno;
8019                         dev_flow->dv.actions[actions_n++] =
8020                                         dev_flow->dv.push_vlan_res->action;
8021                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8022                         break;
8023                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8024                         /* of_vlan_push action handled this action */
8025                         MLX5_ASSERT(action_flags &
8026                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8027                         break;
8028                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8029                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8030                                 break;
8031                         flow_dev_get_vlan_info_from_items(items, &vlan);
8032                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8033                         /* If no VLAN push - this is a modify header action */
8034                         if (flow_dv_convert_action_modify_vlan_vid
8035                                                 (mhdr_res, actions, error))
8036                                 return -rte_errno;
8037                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8038                         break;
8039                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8040                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8041                         if (flow_dv_create_action_l2_encap(dev, actions,
8042                                                            dev_flow,
8043                                                            attr->transfer,
8044                                                            error))
8045                                 return -rte_errno;
8046                         dev_flow->dv.actions[actions_n++] =
8047                                         dev_flow->dv.encap_decap->verbs_action;
8048                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8049                         break;
8050                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8051                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8052                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8053                                                            attr->transfer,
8054                                                            error))
8055                                 return -rte_errno;
8056                         dev_flow->dv.actions[actions_n++] =
8057                                         dev_flow->dv.encap_decap->verbs_action;
8058                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8059                         break;
8060                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8061                         /* Handle encap with preceding decap. */
8062                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8063                                 if (flow_dv_create_action_raw_encap
8064                                         (dev, actions, dev_flow, attr, error))
8065                                         return -rte_errno;
8066                                 dev_flow->dv.actions[actions_n++] =
8067                                         dev_flow->dv.encap_decap->verbs_action;
8068                         } else {
8069                                 /* Handle encap without preceding decap. */
8070                                 if (flow_dv_create_action_l2_encap
8071                                     (dev, actions, dev_flow, attr->transfer,
8072                                      error))
8073                                         return -rte_errno;
8074                                 dev_flow->dv.actions[actions_n++] =
8075                                         dev_flow->dv.encap_decap->verbs_action;
8076                         }
8077                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8078                         break;
8079                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8080                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8081                                 ;
8082                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8083                                 if (flow_dv_create_action_l2_decap
8084                                     (dev, dev_flow, attr->transfer, error))
8085                                         return -rte_errno;
8086                                 dev_flow->dv.actions[actions_n++] =
8087                                         dev_flow->dv.encap_decap->verbs_action;
8088                         }
8089                         /* If decap is followed by encap, handle it at encap. */
8090                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8091                         break;
8092                 case RTE_FLOW_ACTION_TYPE_JUMP:
8093                         jump_data = action->conf;
8094                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8095                                                        jump_data->group,
8096                                                        !!priv->fdb_def_rule,
8097                                                        &table, error);
8098                         if (ret)
8099                                 return ret;
8100                         tbl = flow_dv_tbl_resource_get(dev, table,
8101                                                        attr->egress,
8102                                                        attr->transfer, error);
8103                         if (!tbl)
8104                                 return rte_flow_error_set
8105                                                 (error, errno,
8106                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8107                                                  NULL,
8108                                                  "cannot create jump action.");
8109                         if (flow_dv_jump_tbl_resource_register
8110                             (dev, tbl, dev_flow, error)) {
8111                                 flow_dv_tbl_resource_release(dev, tbl);
8112                                 return rte_flow_error_set
8113                                                 (error, errno,
8114                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8115                                                  NULL,
8116                                                  "cannot create jump action.");
8117                         }
8118                         dev_flow->dv.actions[actions_n++] =
8119                                         dev_flow->dv.jump->action;
8120                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8121                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8122                         break;
8123                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8124                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8125                         if (flow_dv_convert_action_modify_mac
8126                                         (mhdr_res, actions, error))
8127                                 return -rte_errno;
8128                         action_flags |= actions->type ==
8129                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8130                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8131                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8132                         break;
8133                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8134                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8135                         if (flow_dv_convert_action_modify_ipv4
8136                                         (mhdr_res, actions, error))
8137                                 return -rte_errno;
8138                         action_flags |= actions->type ==
8139                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8140                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8141                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8142                         break;
8143                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8144                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8145                         if (flow_dv_convert_action_modify_ipv6
8146                                         (mhdr_res, actions, error))
8147                                 return -rte_errno;
8148                         action_flags |= actions->type ==
8149                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8150                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8151                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8152                         break;
8153                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8154                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8155                         if (flow_dv_convert_action_modify_tp
8156                                         (mhdr_res, actions, items,
8157                                          &flow_attr, dev_flow, !!(action_flags &
8158                                          MLX5_FLOW_ACTION_DECAP), error))
8159                                 return -rte_errno;
8160                         action_flags |= actions->type ==
8161                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8162                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8163                                         MLX5_FLOW_ACTION_SET_TP_DST;
8164                         break;
8165                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8166                         if (flow_dv_convert_action_modify_dec_ttl
8167                                         (mhdr_res, items, &flow_attr, dev_flow,
8168                                          !!(action_flags &
8169                                          MLX5_FLOW_ACTION_DECAP), error))
8170                                 return -rte_errno;
8171                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8172                         break;
8173                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8174                         if (flow_dv_convert_action_modify_ttl
8175                                         (mhdr_res, actions, items, &flow_attr,
8176                                          dev_flow, !!(action_flags &
8177                                          MLX5_FLOW_ACTION_DECAP), error))
8178                                 return -rte_errno;
8179                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8180                         break;
8181                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8182                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8183                         if (flow_dv_convert_action_modify_tcp_seq
8184                                         (mhdr_res, actions, error))
8185                                 return -rte_errno;
8186                         action_flags |= actions->type ==
8187                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8188                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8189                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8190                         break;
8191
8192                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8193                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8194                         if (flow_dv_convert_action_modify_tcp_ack
8195                                         (mhdr_res, actions, error))
8196                                 return -rte_errno;
8197                         action_flags |= actions->type ==
8198                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8199                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8200                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8201                         break;
8202                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8203                         if (flow_dv_convert_action_set_reg
8204                                         (mhdr_res, actions, error))
8205                                 return -rte_errno;
8206                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8207                         break;
8208                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8209                         if (flow_dv_convert_action_copy_mreg
8210                                         (dev, mhdr_res, actions, error))
8211                                 return -rte_errno;
8212                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8213                         break;
8214                 case RTE_FLOW_ACTION_TYPE_METER:
8215                         mtr = actions->conf;
8216                         if (!flow->meter) {
8217                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8218                                                             attr, error);
8219                                 if (!fm)
8220                                         return rte_flow_error_set(error,
8221                                                 rte_errno,
8222                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8223                                                 NULL,
8224                                                 "meter not found "
8225                                                 "or invalid parameters");
8226                                 flow->meter = fm->idx;
8227                         }
8228                         /* Set the meter action. */
8229                         if (!fm) {
8230                                 fm = mlx5_ipool_get(priv->sh->ipool
8231                                                 [MLX5_IPOOL_MTR], flow->meter);
8232                                 if (!fm)
8233                                         return rte_flow_error_set(error,
8234                                                 rte_errno,
8235                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8236                                                 NULL,
8237                                                 "meter not found "
8238                                                 "or invalid parameters");
8239                         }
8240                         dev_flow->dv.actions[actions_n++] =
8241                                 fm->mfts->meter_action;
8242                         action_flags |= MLX5_FLOW_ACTION_METER;
8243                         break;
8244                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8245                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8246                                                               actions, error))
8247                                 return -rte_errno;
8248                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8249                         break;
8250                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8251                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8252                                                               actions, error))
8253                                 return -rte_errno;
8254                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8255                         break;
8256                 case RTE_FLOW_ACTION_TYPE_END:
8257                         actions_end = true;
8258                         if (mhdr_res->actions_num) {
8259                                 /* create modify action if needed. */
8260                                 if (flow_dv_modify_hdr_resource_register
8261                                         (dev, mhdr_res, dev_flow, error))
8262                                         return -rte_errno;
8263                                 dev_flow->dv.actions[modify_action_position] =
8264                                         handle->dvh.modify_hdr->verbs_action;
8265                         }
8266                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8267                                 flow->counter =
8268                                         flow_dv_translate_create_counter(dev,
8269                                                 dev_flow, count, age);
8270
8271                                 if (!flow->counter)
8272                                         return rte_flow_error_set
8273                                                 (error, rte_errno,
8274                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8275                                                 NULL,
8276                                                 "cannot create counter"
8277                                                 " object.");
8278                                 dev_flow->dv.actions[actions_n++] =
8279                                           (flow_dv_counter_get_by_idx(dev,
8280                                           flow->counter, NULL))->action;
8281                         }
8282                         break;
8283                 default:
8284                         break;
8285                 }
8286                 if (mhdr_res->actions_num &&
8287                     modify_action_position == UINT32_MAX)
8288                         modify_action_position = actions_n++;
8289         }
8290         dev_flow->dv.actions_n = actions_n;
8291         dev_flow->act_flags = action_flags;
8292         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8293                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8294                 int item_type = items->type;
8295
8296                 switch (item_type) {
8297                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8298                         flow_dv_translate_item_port_id(dev, match_mask,
8299                                                        match_value, items);
8300                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8301                         break;
8302                 case RTE_FLOW_ITEM_TYPE_ETH:
8303                         flow_dv_translate_item_eth(match_mask, match_value,
8304                                                    items, tunnel,
8305                                                    dev_flow->dv.group);
8306                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8307                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8308                                              MLX5_FLOW_LAYER_OUTER_L2;
8309                         break;
8310                 case RTE_FLOW_ITEM_TYPE_VLAN:
8311                         flow_dv_translate_item_vlan(dev_flow,
8312                                                     match_mask, match_value,
8313                                                     items, tunnel,
8314                                                     dev_flow->dv.group);
8315                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8316                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8317                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8318                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8319                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8320                         break;
8321                 case RTE_FLOW_ITEM_TYPE_IPV4:
8322                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8323                                                   &item_flags, &tunnel);
8324                         flow_dv_translate_item_ipv4(match_mask, match_value,
8325                                                     items, item_flags, tunnel,
8326                                                     dev_flow->dv.group);
8327                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8328                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8329                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8330                         if (items->mask != NULL &&
8331                             ((const struct rte_flow_item_ipv4 *)
8332                              items->mask)->hdr.next_proto_id) {
8333                                 next_protocol =
8334                                         ((const struct rte_flow_item_ipv4 *)
8335                                          (items->spec))->hdr.next_proto_id;
8336                                 next_protocol &=
8337                                         ((const struct rte_flow_item_ipv4 *)
8338                                          (items->mask))->hdr.next_proto_id;
8339                         } else {
8340                                 /* Reset for inner layer. */
8341                                 next_protocol = 0xff;
8342                         }
8343                         break;
8344                 case RTE_FLOW_ITEM_TYPE_IPV6:
8345                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8346                                                   &item_flags, &tunnel);
8347                         flow_dv_translate_item_ipv6(match_mask, match_value,
8348                                                     items, item_flags, tunnel,
8349                                                     dev_flow->dv.group);
8350                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8351                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8352                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8353                         if (items->mask != NULL &&
8354                             ((const struct rte_flow_item_ipv6 *)
8355                              items->mask)->hdr.proto) {
8356                                 next_protocol =
8357                                         ((const struct rte_flow_item_ipv6 *)
8358                                          items->spec)->hdr.proto;
8359                                 next_protocol &=
8360                                         ((const struct rte_flow_item_ipv6 *)
8361                                          items->mask)->hdr.proto;
8362                         } else {
8363                                 /* Reset for inner layer. */
8364                                 next_protocol = 0xff;
8365                         }
8366                         break;
8367                 case RTE_FLOW_ITEM_TYPE_TCP:
8368                         flow_dv_translate_item_tcp(match_mask, match_value,
8369                                                    items, tunnel);
8370                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8371                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8372                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8373                         break;
8374                 case RTE_FLOW_ITEM_TYPE_UDP:
8375                         flow_dv_translate_item_udp(match_mask, match_value,
8376                                                    items, tunnel);
8377                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8378                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8379                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8380                         break;
8381                 case RTE_FLOW_ITEM_TYPE_GRE:
8382                         flow_dv_translate_item_gre(match_mask, match_value,
8383                                                    items, tunnel);
8384                         matcher.priority = rss_desc->level >= 2 ?
8385                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8386                         last_item = MLX5_FLOW_LAYER_GRE;
8387                         break;
8388                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8389                         flow_dv_translate_item_gre_key(match_mask,
8390                                                        match_value, items);
8391                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8392                         break;
8393                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8394                         flow_dv_translate_item_nvgre(match_mask, match_value,
8395                                                      items, tunnel);
8396                         matcher.priority = rss_desc->level >= 2 ?
8397                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8398                         last_item = MLX5_FLOW_LAYER_GRE;
8399                         break;
8400                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8401                         flow_dv_translate_item_vxlan(match_mask, match_value,
8402                                                      items, tunnel);
8403                         matcher.priority = rss_desc->level >= 2 ?
8404                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8405                         last_item = MLX5_FLOW_LAYER_VXLAN;
8406                         break;
8407                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8408                         flow_dv_translate_item_vxlan_gpe(match_mask,
8409                                                          match_value, items,
8410                                                          tunnel);
8411                         matcher.priority = rss_desc->level >= 2 ?
8412                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8413                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8414                         break;
8415                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8416                         flow_dv_translate_item_geneve(match_mask, match_value,
8417                                                       items, tunnel);
8418                         matcher.priority = rss_desc->level >= 2 ?
8419                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8420                         last_item = MLX5_FLOW_LAYER_GENEVE;
8421                         break;
8422                 case RTE_FLOW_ITEM_TYPE_MPLS:
8423                         flow_dv_translate_item_mpls(match_mask, match_value,
8424                                                     items, last_item, tunnel);
8425                         matcher.priority = rss_desc->level >= 2 ?
8426                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8427                         last_item = MLX5_FLOW_LAYER_MPLS;
8428                         break;
8429                 case RTE_FLOW_ITEM_TYPE_MARK:
8430                         flow_dv_translate_item_mark(dev, match_mask,
8431                                                     match_value, items);
8432                         last_item = MLX5_FLOW_ITEM_MARK;
8433                         break;
8434                 case RTE_FLOW_ITEM_TYPE_META:
8435                         flow_dv_translate_item_meta(dev, match_mask,
8436                                                     match_value, attr, items);
8437                         last_item = MLX5_FLOW_ITEM_METADATA;
8438                         break;
8439                 case RTE_FLOW_ITEM_TYPE_ICMP:
8440                         flow_dv_translate_item_icmp(match_mask, match_value,
8441                                                     items, tunnel);
8442                         last_item = MLX5_FLOW_LAYER_ICMP;
8443                         break;
8444                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8445                         flow_dv_translate_item_icmp6(match_mask, match_value,
8446                                                       items, tunnel);
8447                         last_item = MLX5_FLOW_LAYER_ICMP6;
8448                         break;
8449                 case RTE_FLOW_ITEM_TYPE_TAG:
8450                         flow_dv_translate_item_tag(dev, match_mask,
8451                                                    match_value, items);
8452                         last_item = MLX5_FLOW_ITEM_TAG;
8453                         break;
8454                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8455                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8456                                                         match_value, items);
8457                         last_item = MLX5_FLOW_ITEM_TAG;
8458                         break;
8459                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8460                         flow_dv_translate_item_tx_queue(dev, match_mask,
8461                                                         match_value,
8462                                                         items);
8463                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8464                         break;
8465                 case RTE_FLOW_ITEM_TYPE_GTP:
8466                         flow_dv_translate_item_gtp(match_mask, match_value,
8467                                                    items, tunnel);
8468                         matcher.priority = rss_desc->level >= 2 ?
8469                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8470                         last_item = MLX5_FLOW_LAYER_GTP;
8471                         break;
8472                 default:
8473                         break;
8474                 }
8475                 item_flags |= last_item;
8476         }
8477         /*
8478          * When E-Switch mode is enabled, we have two cases where we need to
8479          * set the source port manually.
8480          * The first one, is in case of Nic steering rule, and the second is
8481          * E-Switch rule where no port_id item was found. In both cases
8482          * the source port is set according the current port in use.
8483          */
8484         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8485             (priv->representor || priv->master)) {
8486                 if (flow_dv_translate_item_port_id(dev, match_mask,
8487                                                    match_value, NULL))
8488                         return -rte_errno;
8489         }
8490 #ifdef RTE_LIBRTE_MLX5_DEBUG
8491         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8492                                               dev_flow->dv.value.buf));
8493 #endif
8494         /*
8495          * Layers may be already initialized from prefix flow if this dev_flow
8496          * is the suffix flow.
8497          */
8498         handle->layers |= item_flags;
8499         if (action_flags & MLX5_FLOW_ACTION_RSS)
8500                 flow_dv_hashfields_set(dev_flow, rss_desc);
8501         /* Register matcher. */
8502         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8503                                     matcher.mask.size);
8504         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8505                                                      matcher.priority);
8506         /* reserved field no needs to be set to 0 here. */
8507         tbl_key.domain = attr->transfer;
8508         tbl_key.direction = attr->egress;
8509         tbl_key.table_id = dev_flow->dv.group;
8510         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8511                 return -rte_errno;
8512         return 0;
8513 }
8514
8515 /**
8516  * Apply the flow to the NIC, lock free,
8517  * (mutex should be acquired by caller).
8518  *
8519  * @param[in] dev
8520  *   Pointer to the Ethernet device structure.
8521  * @param[in, out] flow
8522  *   Pointer to flow structure.
8523  * @param[out] error
8524  *   Pointer to error structure.
8525  *
8526  * @return
8527  *   0 on success, a negative errno value otherwise and rte_errno is set.
8528  */
8529 static int
8530 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8531                 struct rte_flow_error *error)
8532 {
8533         struct mlx5_flow_dv_workspace *dv;
8534         struct mlx5_flow_handle *dh;
8535         struct mlx5_flow_handle_dv *dv_h;
8536         struct mlx5_flow *dev_flow;
8537         struct mlx5_priv *priv = dev->data->dev_private;
8538         uint32_t handle_idx;
8539         int n;
8540         int err;
8541         int idx;
8542
8543         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8544                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8545                 dv = &dev_flow->dv;
8546                 dh = dev_flow->handle;
8547                 dv_h = &dh->dvh;
8548                 n = dv->actions_n;
8549                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8550                         if (dv->transfer) {
8551                                 dv->actions[n++] = priv->sh->esw_drop_action;
8552                         } else {
8553                                 struct mlx5_hrxq *drop_hrxq;
8554                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8555                                 if (!drop_hrxq) {
8556                                         rte_flow_error_set
8557                                                 (error, errno,
8558                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8559                                                  NULL,
8560                                                  "cannot get drop hash queue");
8561                                         goto error;
8562                                 }
8563                                 /*
8564                                  * Drop queues will be released by the specify
8565                                  * mlx5_hrxq_drop_release() function. Assign
8566                                  * the special index to hrxq to mark the queue
8567                                  * has been allocated.
8568                                  */
8569                                 dh->rix_hrxq = UINT32_MAX;
8570                                 dv->actions[n++] = drop_hrxq->action;
8571                         }
8572                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8573                         struct mlx5_hrxq *hrxq;
8574                         uint32_t hrxq_idx;
8575                         struct mlx5_flow_rss_desc *rss_desc =
8576                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8577                                 [!!priv->flow_nested_idx];
8578
8579                         MLX5_ASSERT(rss_desc->queue_num);
8580                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8581                                                  MLX5_RSS_HASH_KEY_LEN,
8582                                                  dev_flow->hash_fields,
8583                                                  rss_desc->queue,
8584                                                  rss_desc->queue_num);
8585                         if (!hrxq_idx) {
8586                                 hrxq_idx = mlx5_hrxq_new
8587                                                 (dev, rss_desc->key,
8588                                                 MLX5_RSS_HASH_KEY_LEN,
8589                                                 dev_flow->hash_fields,
8590                                                 rss_desc->queue,
8591                                                 rss_desc->queue_num,
8592                                                 !!(dh->layers &
8593                                                 MLX5_FLOW_LAYER_TUNNEL));
8594                         }
8595                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8596                                               hrxq_idx);
8597                         if (!hrxq) {
8598                                 rte_flow_error_set
8599                                         (error, rte_errno,
8600                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8601                                          "cannot get hash queue");
8602                                 goto error;
8603                         }
8604                         dh->rix_hrxq = hrxq_idx;
8605                         dv->actions[n++] = hrxq->action;
8606                 }
8607                 dh->ib_flow =
8608                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8609                                                   (void *)&dv->value, n,
8610                                                   dv->actions);
8611                 if (!dh->ib_flow) {
8612                         rte_flow_error_set(error, errno,
8613                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8614                                            NULL,
8615                                            "hardware refuses to create flow");
8616                         goto error;
8617                 }
8618                 if (priv->vmwa_context &&
8619                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8620                         /*
8621                          * The rule contains the VLAN pattern.
8622                          * For VF we are going to create VLAN
8623                          * interface to make hypervisor set correct
8624                          * e-Switch vport context.
8625                          */
8626                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8627                 }
8628         }
8629         return 0;
8630 error:
8631         err = rte_errno; /* Save rte_errno before cleanup. */
8632         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8633                        handle_idx, dh, next) {
8634                 /* hrxq is union, don't clear it if the flag is not set. */
8635                 if (dh->rix_hrxq) {
8636                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8637                                 mlx5_hrxq_drop_release(dev);
8638                                 dh->rix_hrxq = 0;
8639                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8640                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8641                                 dh->rix_hrxq = 0;
8642                         }
8643                 }
8644                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8645                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8646         }
8647         rte_errno = err; /* Restore rte_errno. */
8648         return -rte_errno;
8649 }
8650
8651 /**
8652  * Release the flow matcher.
8653  *
8654  * @param dev
8655  *   Pointer to Ethernet device.
8656  * @param handle
8657  *   Pointer to mlx5_flow_handle.
8658  *
8659  * @return
8660  *   1 while a reference on it exists, 0 when freed.
8661  */
8662 static int
8663 flow_dv_matcher_release(struct rte_eth_dev *dev,
8664                         struct mlx5_flow_handle *handle)
8665 {
8666         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8667
8668         MLX5_ASSERT(matcher->matcher_object);
8669         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8670                 dev->data->port_id, (void *)matcher,
8671                 rte_atomic32_read(&matcher->refcnt));
8672         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8673                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8674                            (matcher->matcher_object));
8675                 LIST_REMOVE(matcher, next);
8676                 /* table ref-- in release interface. */
8677                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8678                 rte_free(matcher);
8679                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8680                         dev->data->port_id, (void *)matcher);
8681                 return 0;
8682         }
8683         return 1;
8684 }
8685
8686 /**
8687  * Release an encap/decap resource.
8688  *
8689  * @param dev
8690  *   Pointer to Ethernet device.
8691  * @param handle
8692  *   Pointer to mlx5_flow_handle.
8693  *
8694  * @return
8695  *   1 while a reference on it exists, 0 when freed.
8696  */
8697 static int
8698 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8699                                      struct mlx5_flow_handle *handle)
8700 {
8701         struct mlx5_priv *priv = dev->data->dev_private;
8702         uint32_t idx = handle->dvh.rix_encap_decap;
8703         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8704
8705         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8706                          idx);
8707         if (!cache_resource)
8708                 return 0;
8709         MLX5_ASSERT(cache_resource->verbs_action);
8710         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8711                 (void *)cache_resource,
8712                 rte_atomic32_read(&cache_resource->refcnt));
8713         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8714                 claim_zero(mlx5_glue->destroy_flow_action
8715                                 (cache_resource->verbs_action));
8716                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8717                              &priv->sh->encaps_decaps, idx,
8718                              cache_resource, next);
8719                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8720                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8721                         (void *)cache_resource);
8722                 return 0;
8723         }
8724         return 1;
8725 }
8726
8727 /**
8728  * Release an jump to table action resource.
8729  *
8730  * @param dev
8731  *   Pointer to Ethernet device.
8732  * @param handle
8733  *   Pointer to mlx5_flow_handle.
8734  *
8735  * @return
8736  *   1 while a reference on it exists, 0 when freed.
8737  */
8738 static int
8739 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8740                                   struct mlx5_flow_handle *handle)
8741 {
8742         struct mlx5_priv *priv = dev->data->dev_private;
8743         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8744         struct mlx5_flow_tbl_data_entry *tbl_data;
8745
8746         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8747                              handle->rix_jump);
8748         if (!tbl_data)
8749                 return 0;
8750         cache_resource = &tbl_data->jump;
8751         MLX5_ASSERT(cache_resource->action);
8752         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8753                 (void *)cache_resource,
8754                 rte_atomic32_read(&cache_resource->refcnt));
8755         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8756                 claim_zero(mlx5_glue->destroy_flow_action
8757                                 (cache_resource->action));
8758                 /* jump action memory free is inside the table release. */
8759                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8760                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8761                         (void *)cache_resource);
8762                 return 0;
8763         }
8764         return 1;
8765 }
8766
8767 /**
8768  * Release a modify-header resource.
8769  *
8770  * @param handle
8771  *   Pointer to mlx5_flow_handle.
8772  *
8773  * @return
8774  *   1 while a reference on it exists, 0 when freed.
8775  */
8776 static int
8777 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8778 {
8779         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8780                                                         handle->dvh.modify_hdr;
8781
8782         MLX5_ASSERT(cache_resource->verbs_action);
8783         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8784                 (void *)cache_resource,
8785                 rte_atomic32_read(&cache_resource->refcnt));
8786         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8787                 claim_zero(mlx5_glue->destroy_flow_action
8788                                 (cache_resource->verbs_action));
8789                 LIST_REMOVE(cache_resource, next);
8790                 rte_free(cache_resource);
8791                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8792                         (void *)cache_resource);
8793                 return 0;
8794         }
8795         return 1;
8796 }
8797
8798 /**
8799  * Release port ID action resource.
8800  *
8801  * @param dev
8802  *   Pointer to Ethernet device.
8803  * @param handle
8804  *   Pointer to mlx5_flow_handle.
8805  *
8806  * @return
8807  *   1 while a reference on it exists, 0 when freed.
8808  */
8809 static int
8810 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8811                                         struct mlx5_flow_handle *handle)
8812 {
8813         struct mlx5_priv *priv = dev->data->dev_private;
8814         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8815         uint32_t idx = handle->rix_port_id_action;
8816
8817         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8818                                         idx);
8819         if (!cache_resource)
8820                 return 0;
8821         MLX5_ASSERT(cache_resource->action);
8822         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8823                 (void *)cache_resource,
8824                 rte_atomic32_read(&cache_resource->refcnt));
8825         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8826                 claim_zero(mlx5_glue->destroy_flow_action
8827                                 (cache_resource->action));
8828                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8829                              &priv->sh->port_id_action_list, idx,
8830                              cache_resource, next);
8831                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8832                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8833                         (void *)cache_resource);
8834                 return 0;
8835         }
8836         return 1;
8837 }
8838
8839 /**
8840  * Release push vlan action resource.
8841  *
8842  * @param dev
8843  *   Pointer to Ethernet device.
8844  * @param handle
8845  *   Pointer to mlx5_flow_handle.
8846  *
8847  * @return
8848  *   1 while a reference on it exists, 0 when freed.
8849  */
8850 static int
8851 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8852                                           struct mlx5_flow_handle *handle)
8853 {
8854         struct mlx5_priv *priv = dev->data->dev_private;
8855         uint32_t idx = handle->dvh.rix_push_vlan;
8856         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8857
8858         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8859                                         idx);
8860         if (!cache_resource)
8861                 return 0;
8862         MLX5_ASSERT(cache_resource->action);
8863         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8864                 (void *)cache_resource,
8865                 rte_atomic32_read(&cache_resource->refcnt));
8866         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8867                 claim_zero(mlx5_glue->destroy_flow_action
8868                                 (cache_resource->action));
8869                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8870                              &priv->sh->push_vlan_action_list, idx,
8871                              cache_resource, next);
8872                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8873                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8874                         (void *)cache_resource);
8875                 return 0;
8876         }
8877         return 1;
8878 }
8879
8880 /**
8881  * Release the fate resource.
8882  *
8883  * @param dev
8884  *   Pointer to Ethernet device.
8885  * @param handle
8886  *   Pointer to mlx5_flow_handle.
8887  */
8888 static void
8889 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8890                                struct mlx5_flow_handle *handle)
8891 {
8892         if (!handle->rix_fate)
8893                 return;
8894         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8895                 mlx5_hrxq_drop_release(dev);
8896         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8897                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8898         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8899                 flow_dv_jump_tbl_resource_release(dev, handle);
8900         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8901                 flow_dv_port_id_action_resource_release(dev, handle);
8902         else
8903                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8904         handle->rix_fate = 0;
8905 }
8906
8907 /**
8908  * Remove the flow from the NIC but keeps it in memory.
8909  * Lock free, (mutex should be acquired by caller).
8910  *
8911  * @param[in] dev
8912  *   Pointer to Ethernet device.
8913  * @param[in, out] flow
8914  *   Pointer to flow structure.
8915  */
8916 static void
8917 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8918 {
8919         struct mlx5_flow_handle *dh;
8920         uint32_t handle_idx;
8921         struct mlx5_priv *priv = dev->data->dev_private;
8922
8923         if (!flow)
8924                 return;
8925         handle_idx = flow->dev_handles;
8926         while (handle_idx) {
8927                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8928                                     handle_idx);
8929                 if (!dh)
8930                         return;
8931                 if (dh->ib_flow) {
8932                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8933                         dh->ib_flow = NULL;
8934                 }
8935                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8936                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8937                         flow_dv_fate_resource_release(dev, dh);
8938                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8939                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8940                 handle_idx = dh->next.next;
8941         }
8942 }
8943
8944 /**
8945  * Remove the flow from the NIC and the memory.
8946  * Lock free, (mutex should be acquired by caller).
8947  *
8948  * @param[in] dev
8949  *   Pointer to the Ethernet device structure.
8950  * @param[in, out] flow
8951  *   Pointer to flow structure.
8952  */
8953 static void
8954 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8955 {
8956         struct mlx5_flow_handle *dev_handle;
8957         struct mlx5_priv *priv = dev->data->dev_private;
8958
8959         if (!flow)
8960                 return;
8961         __flow_dv_remove(dev, flow);
8962         if (flow->counter) {
8963                 flow_dv_counter_release(dev, flow->counter);
8964                 flow->counter = 0;
8965         }
8966         if (flow->meter) {
8967                 struct mlx5_flow_meter *fm;
8968
8969                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8970                                     flow->meter);
8971                 if (fm)
8972                         mlx5_flow_meter_detach(fm);
8973                 flow->meter = 0;
8974         }
8975         while (flow->dev_handles) {
8976                 uint32_t tmp_idx = flow->dev_handles;
8977
8978                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8979                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8980                 if (!dev_handle)
8981                         return;
8982                 flow->dev_handles = dev_handle->next.next;
8983                 if (dev_handle->dvh.matcher)
8984                         flow_dv_matcher_release(dev, dev_handle);
8985                 if (dev_handle->dvh.rix_encap_decap)
8986                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8987                 if (dev_handle->dvh.modify_hdr)
8988                         flow_dv_modify_hdr_resource_release(dev_handle);
8989                 if (dev_handle->dvh.rix_push_vlan)
8990                         flow_dv_push_vlan_action_resource_release(dev,
8991                                                                   dev_handle);
8992                 if (dev_handle->dvh.rix_tag)
8993                         flow_dv_tag_release(dev,
8994                                             dev_handle->dvh.rix_tag);
8995                 flow_dv_fate_resource_release(dev, dev_handle);
8996                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8997                            tmp_idx);
8998         }
8999 }
9000
9001 /**
9002  * Query a dv flow  rule for its statistics via devx.
9003  *
9004  * @param[in] dev
9005  *   Pointer to Ethernet device.
9006  * @param[in] flow
9007  *   Pointer to the sub flow.
9008  * @param[out] data
9009  *   data retrieved by the query.
9010  * @param[out] error
9011  *   Perform verbose error reporting if not NULL.
9012  *
9013  * @return
9014  *   0 on success, a negative errno value otherwise and rte_errno is set.
9015  */
9016 static int
9017 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9018                     void *data, struct rte_flow_error *error)
9019 {
9020         struct mlx5_priv *priv = dev->data->dev_private;
9021         struct rte_flow_query_count *qc = data;
9022
9023         if (!priv->config.devx)
9024                 return rte_flow_error_set(error, ENOTSUP,
9025                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9026                                           NULL,
9027                                           "counters are not supported");
9028         if (flow->counter) {
9029                 uint64_t pkts, bytes;
9030                 struct mlx5_flow_counter *cnt;
9031
9032                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9033                                                  NULL);
9034                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9035                                                &bytes);
9036
9037                 if (err)
9038                         return rte_flow_error_set(error, -err,
9039                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9040                                         NULL, "cannot read counters");
9041                 qc->hits_set = 1;
9042                 qc->bytes_set = 1;
9043                 qc->hits = pkts - cnt->hits;
9044                 qc->bytes = bytes - cnt->bytes;
9045                 if (qc->reset) {
9046                         cnt->hits = pkts;
9047                         cnt->bytes = bytes;
9048                 }
9049                 return 0;
9050         }
9051         return rte_flow_error_set(error, EINVAL,
9052                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9053                                   NULL,
9054                                   "counters are not available");
9055 }
9056
9057 /**
9058  * Query a flow.
9059  *
9060  * @see rte_flow_query()
9061  * @see rte_flow_ops
9062  */
9063 static int
9064 flow_dv_query(struct rte_eth_dev *dev,
9065               struct rte_flow *flow __rte_unused,
9066               const struct rte_flow_action *actions __rte_unused,
9067               void *data __rte_unused,
9068               struct rte_flow_error *error __rte_unused)
9069 {
9070         int ret = -EINVAL;
9071
9072         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9073                 switch (actions->type) {
9074                 case RTE_FLOW_ACTION_TYPE_VOID:
9075                         break;
9076                 case RTE_FLOW_ACTION_TYPE_COUNT:
9077                         ret = flow_dv_query_count(dev, flow, data, error);
9078                         break;
9079                 default:
9080                         return rte_flow_error_set(error, ENOTSUP,
9081                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9082                                                   actions,
9083                                                   "action not supported");
9084                 }
9085         }
9086         return ret;
9087 }
9088
9089 /**
9090  * Destroy the meter table set.
9091  * Lock free, (mutex should be acquired by caller).
9092  *
9093  * @param[in] dev
9094  *   Pointer to Ethernet device.
9095  * @param[in] tbl
9096  *   Pointer to the meter table set.
9097  *
9098  * @return
9099  *   Always 0.
9100  */
9101 static int
9102 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9103                         struct mlx5_meter_domains_infos *tbl)
9104 {
9105         struct mlx5_priv *priv = dev->data->dev_private;
9106         struct mlx5_meter_domains_infos *mtd =
9107                                 (struct mlx5_meter_domains_infos *)tbl;
9108
9109         if (!mtd || !priv->config.dv_flow_en)
9110                 return 0;
9111         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9112                 claim_zero(mlx5_glue->dv_destroy_flow
9113                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9114         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9115                 claim_zero(mlx5_glue->dv_destroy_flow
9116                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9117         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9118                 claim_zero(mlx5_glue->dv_destroy_flow
9119                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9120         if (mtd->egress.color_matcher)
9121                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9122                           (mtd->egress.color_matcher));
9123         if (mtd->egress.any_matcher)
9124                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9125                           (mtd->egress.any_matcher));
9126         if (mtd->egress.tbl)
9127                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9128         if (mtd->egress.sfx_tbl)
9129                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9130         if (mtd->ingress.color_matcher)
9131                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9132                           (mtd->ingress.color_matcher));
9133         if (mtd->ingress.any_matcher)
9134                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9135                           (mtd->ingress.any_matcher));
9136         if (mtd->ingress.tbl)
9137                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9138         if (mtd->ingress.sfx_tbl)
9139                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9140         if (mtd->transfer.color_matcher)
9141                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9142                           (mtd->transfer.color_matcher));
9143         if (mtd->transfer.any_matcher)
9144                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9145                           (mtd->transfer.any_matcher));
9146         if (mtd->transfer.tbl)
9147                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9148         if (mtd->transfer.sfx_tbl)
9149                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9150         if (mtd->drop_actn)
9151                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9152         rte_free(mtd);
9153         return 0;
9154 }
9155
9156 /* Number of meter flow actions, count and jump or count and drop. */
9157 #define METER_ACTIONS 2
9158
9159 /**
9160  * Create specify domain meter table and suffix table.
9161  *
9162  * @param[in] dev
9163  *   Pointer to Ethernet device.
9164  * @param[in,out] mtb
9165  *   Pointer to DV meter table set.
9166  * @param[in] egress
9167  *   Table attribute.
9168  * @param[in] transfer
9169  *   Table attribute.
9170  * @param[in] color_reg_c_idx
9171  *   Reg C index for color match.
9172  *
9173  * @return
9174  *   0 on success, -1 otherwise and rte_errno is set.
9175  */
9176 static int
9177 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9178                            struct mlx5_meter_domains_infos *mtb,
9179                            uint8_t egress, uint8_t transfer,
9180                            uint32_t color_reg_c_idx)
9181 {
9182         struct mlx5_priv *priv = dev->data->dev_private;
9183         struct mlx5_dev_ctx_shared *sh = priv->sh;
9184         struct mlx5_flow_dv_match_params mask = {
9185                 .size = sizeof(mask.buf),
9186         };
9187         struct mlx5_flow_dv_match_params value = {
9188                 .size = sizeof(value.buf),
9189         };
9190         struct mlx5dv_flow_matcher_attr dv_attr = {
9191                 .type = IBV_FLOW_ATTR_NORMAL,
9192                 .priority = 0,
9193                 .match_criteria_enable = 0,
9194                 .match_mask = (void *)&mask,
9195         };
9196         void *actions[METER_ACTIONS];
9197         struct mlx5_meter_domain_info *dtb;
9198         struct rte_flow_error error;
9199         int i = 0;
9200
9201         if (transfer)
9202                 dtb = &mtb->transfer;
9203         else if (egress)
9204                 dtb = &mtb->egress;
9205         else
9206                 dtb = &mtb->ingress;
9207         /* Create the meter table with METER level. */
9208         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9209                                             egress, transfer, &error);
9210         if (!dtb->tbl) {
9211                 DRV_LOG(ERR, "Failed to create meter policer table.");
9212                 return -1;
9213         }
9214         /* Create the meter suffix table with SUFFIX level. */
9215         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9216                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9217                                             egress, transfer, &error);
9218         if (!dtb->sfx_tbl) {
9219                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9220                 return -1;
9221         }
9222         /* Create matchers, Any and Color. */
9223         dv_attr.priority = 3;
9224         dv_attr.match_criteria_enable = 0;
9225         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9226                                                              &dv_attr,
9227                                                              dtb->tbl->obj);
9228         if (!dtb->any_matcher) {
9229                 DRV_LOG(ERR, "Failed to create meter"
9230                              " policer default matcher.");
9231                 goto error_exit;
9232         }
9233         dv_attr.priority = 0;
9234         dv_attr.match_criteria_enable =
9235                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9236         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9237                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9238         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9239                                                                &dv_attr,
9240                                                                dtb->tbl->obj);
9241         if (!dtb->color_matcher) {
9242                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9243                 goto error_exit;
9244         }
9245         if (mtb->count_actns[RTE_MTR_DROPPED])
9246                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9247         actions[i++] = mtb->drop_actn;
9248         /* Default rule: lowest priority, match any, actions: drop. */
9249         dtb->policer_rules[RTE_MTR_DROPPED] =
9250                         mlx5_glue->dv_create_flow(dtb->any_matcher,
9251                                                  (void *)&value, i, actions);
9252         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9253                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9254                 goto error_exit;
9255         }
9256         return 0;
9257 error_exit:
9258         return -1;
9259 }
9260
9261 /**
9262  * Create the needed meter and suffix tables.
9263  * Lock free, (mutex should be acquired by caller).
9264  *
9265  * @param[in] dev
9266  *   Pointer to Ethernet device.
9267  * @param[in] fm
9268  *   Pointer to the flow meter.
9269  *
9270  * @return
9271  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9272  */
9273 static struct mlx5_meter_domains_infos *
9274 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9275                        const struct mlx5_flow_meter *fm)
9276 {
9277         struct mlx5_priv *priv = dev->data->dev_private;
9278         struct mlx5_meter_domains_infos *mtb;
9279         int ret;
9280         int i;
9281
9282         if (!priv->mtr_en) {
9283                 rte_errno = ENOTSUP;
9284                 return NULL;
9285         }
9286         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9287         if (!mtb) {
9288                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9289                 return NULL;
9290         }
9291         /* Create meter count actions */
9292         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9293                 struct mlx5_flow_counter *cnt;
9294                 if (!fm->policer_stats.cnt[i])
9295                         continue;
9296                 cnt = flow_dv_counter_get_by_idx(dev,
9297                       fm->policer_stats.cnt[i], NULL);
9298                 mtb->count_actns[i] = cnt->action;
9299         }
9300         /* Create drop action. */
9301         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9302         if (!mtb->drop_actn) {
9303                 DRV_LOG(ERR, "Failed to create drop action.");
9304                 goto error_exit;
9305         }
9306         /* Egress meter table. */
9307         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9308         if (ret) {
9309                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9310                 goto error_exit;
9311         }
9312         /* Ingress meter table. */
9313         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9314         if (ret) {
9315                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9316                 goto error_exit;
9317         }
9318         /* FDB meter table. */
9319         if (priv->config.dv_esw_en) {
9320                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9321                                                  priv->mtr_color_reg);
9322                 if (ret) {
9323                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9324                         goto error_exit;
9325                 }
9326         }
9327         return mtb;
9328 error_exit:
9329         flow_dv_destroy_mtr_tbl(dev, mtb);
9330         return NULL;
9331 }
9332
9333 /**
9334  * Destroy domain policer rule.
9335  *
9336  * @param[in] dt
9337  *   Pointer to domain table.
9338  */
9339 static void
9340 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9341 {
9342         int i;
9343
9344         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9345                 if (dt->policer_rules[i]) {
9346                         claim_zero(mlx5_glue->dv_destroy_flow
9347                                   (dt->policer_rules[i]));
9348                         dt->policer_rules[i] = NULL;
9349                 }
9350         }
9351         if (dt->jump_actn) {
9352                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9353                 dt->jump_actn = NULL;
9354         }
9355 }
9356
9357 /**
9358  * Destroy policer rules.
9359  *
9360  * @param[in] dev
9361  *   Pointer to Ethernet device.
9362  * @param[in] fm
9363  *   Pointer to flow meter structure.
9364  * @param[in] attr
9365  *   Pointer to flow attributes.
9366  *
9367  * @return
9368  *   Always 0.
9369  */
9370 static int
9371 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9372                               const struct mlx5_flow_meter *fm,
9373                               const struct rte_flow_attr *attr)
9374 {
9375         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9376
9377         if (!mtb)
9378                 return 0;
9379         if (attr->egress)
9380                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9381         if (attr->ingress)
9382                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9383         if (attr->transfer)
9384                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9385         return 0;
9386 }
9387
9388 /**
9389  * Create specify domain meter policer rule.
9390  *
9391  * @param[in] fm
9392  *   Pointer to flow meter structure.
9393  * @param[in] mtb
9394  *   Pointer to DV meter table set.
9395  * @param[in] mtr_reg_c
9396  *   Color match REG_C.
9397  *
9398  * @return
9399  *   0 on success, -1 otherwise.
9400  */
9401 static int
9402 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9403                                     struct mlx5_meter_domain_info *dtb,
9404                                     uint8_t mtr_reg_c)
9405 {
9406         struct mlx5_flow_dv_match_params matcher = {
9407                 .size = sizeof(matcher.buf),
9408         };
9409         struct mlx5_flow_dv_match_params value = {
9410                 .size = sizeof(value.buf),
9411         };
9412         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9413         void *actions[METER_ACTIONS];
9414         int i;
9415
9416         /* Create jump action. */
9417         if (!dtb->jump_actn)
9418                 dtb->jump_actn =
9419                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9420                                                         (dtb->sfx_tbl->obj);
9421         if (!dtb->jump_actn) {
9422                 DRV_LOG(ERR, "Failed to create policer jump action.");
9423                 goto error;
9424         }
9425         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9426                 int j = 0;
9427
9428                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9429                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9430                 if (mtb->count_actns[i])
9431                         actions[j++] = mtb->count_actns[i];
9432                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9433                         actions[j++] = mtb->drop_actn;
9434                 else
9435                         actions[j++] = dtb->jump_actn;
9436                 dtb->policer_rules[i] =
9437                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9438                                                  (void *)&value,
9439                                                   j, actions);
9440                 if (!dtb->policer_rules[i]) {
9441                         DRV_LOG(ERR, "Failed to create policer rule.");
9442                         goto error;
9443                 }
9444         }
9445         return 0;
9446 error:
9447         rte_errno = errno;
9448         return -1;
9449 }
9450
9451 /**
9452  * Create policer rules.
9453  *
9454  * @param[in] dev
9455  *   Pointer to Ethernet device.
9456  * @param[in] fm
9457  *   Pointer to flow meter structure.
9458  * @param[in] attr
9459  *   Pointer to flow attributes.
9460  *
9461  * @return
9462  *   0 on success, -1 otherwise.
9463  */
9464 static int
9465 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9466                              struct mlx5_flow_meter *fm,
9467                              const struct rte_flow_attr *attr)
9468 {
9469         struct mlx5_priv *priv = dev->data->dev_private;
9470         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9471         int ret;
9472
9473         if (attr->egress) {
9474                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9475                                                 priv->mtr_color_reg);
9476                 if (ret) {
9477                         DRV_LOG(ERR, "Failed to create egress policer.");
9478                         goto error;
9479                 }
9480         }
9481         if (attr->ingress) {
9482                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9483                                                 priv->mtr_color_reg);
9484                 if (ret) {
9485                         DRV_LOG(ERR, "Failed to create ingress policer.");
9486                         goto error;
9487                 }
9488         }
9489         if (attr->transfer) {
9490                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9491                                                 priv->mtr_color_reg);
9492                 if (ret) {
9493                         DRV_LOG(ERR, "Failed to create transfer policer.");
9494                         goto error;
9495                 }
9496         }
9497         return 0;
9498 error:
9499         flow_dv_destroy_policer_rules(dev, fm, attr);
9500         return -1;
9501 }
9502
9503 /**
9504  * Query a devx counter.
9505  *
9506  * @param[in] dev
9507  *   Pointer to the Ethernet device structure.
9508  * @param[in] cnt
9509  *   Index to the flow counter.
9510  * @param[in] clear
9511  *   Set to clear the counter statistics.
9512  * @param[out] pkts
9513  *   The statistics value of packets.
9514  * @param[out] bytes
9515  *   The statistics value of bytes.
9516  *
9517  * @return
9518  *   0 on success, otherwise return -1.
9519  */
9520 static int
9521 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9522                       uint64_t *pkts, uint64_t *bytes)
9523 {
9524         struct mlx5_priv *priv = dev->data->dev_private;
9525         struct mlx5_flow_counter *cnt;
9526         uint64_t inn_pkts, inn_bytes;
9527         int ret;
9528
9529         if (!priv->config.devx)
9530                 return -1;
9531
9532         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9533         if (ret)
9534                 return -1;
9535         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9536         *pkts = inn_pkts - cnt->hits;
9537         *bytes = inn_bytes - cnt->bytes;
9538         if (clear) {
9539                 cnt->hits = inn_pkts;
9540                 cnt->bytes = inn_bytes;
9541         }
9542         return 0;
9543 }
9544
9545 /**
9546  * Get aged-out flows.
9547  *
9548  * @param[in] dev
9549  *   Pointer to the Ethernet device structure.
9550  * @param[in] context
9551  *   The address of an array of pointers to the aged-out flows contexts.
9552  * @param[in] nb_contexts
9553  *   The length of context array pointers.
9554  * @param[out] error
9555  *   Perform verbose error reporting if not NULL. Initialized in case of
9556  *   error only.
9557  *
9558  * @return
9559  *   how many contexts get in success, otherwise negative errno value.
9560  *   if nb_contexts is 0, return the amount of all aged contexts.
9561  *   if nb_contexts is not 0 , return the amount of aged flows reported
9562  *   in the context array.
9563  * @note: only stub for now
9564  */
9565 static int
9566 flow_get_aged_flows(struct rte_eth_dev *dev,
9567                     void **context,
9568                     uint32_t nb_contexts,
9569                     struct rte_flow_error *error)
9570 {
9571         struct mlx5_priv *priv = dev->data->dev_private;
9572         struct mlx5_age_info *age_info;
9573         struct mlx5_age_param *age_param;
9574         struct mlx5_flow_counter *counter;
9575         int nb_flows = 0;
9576
9577         if (nb_contexts && !context)
9578                 return rte_flow_error_set(error, EINVAL,
9579                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9580                                           NULL,
9581                                           "Should assign at least one flow or"
9582                                           " context to get if nb_contexts != 0");
9583         age_info = GET_PORT_AGE_INFO(priv);
9584         rte_spinlock_lock(&age_info->aged_sl);
9585         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9586                 nb_flows++;
9587                 if (nb_contexts) {
9588                         age_param = MLX5_CNT_TO_AGE(counter);
9589                         context[nb_flows - 1] = age_param->context;
9590                         if (!(--nb_contexts))
9591                                 break;
9592                 }
9593         }
9594         rte_spinlock_unlock(&age_info->aged_sl);
9595         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9596         return nb_flows;
9597 }
9598
9599 /*
9600  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9601  */
9602 static int
9603 flow_dv_translate(struct rte_eth_dev *dev,
9604                   struct mlx5_flow *dev_flow,
9605                   const struct rte_flow_attr *attr,
9606                   const struct rte_flow_item items[],
9607                   const struct rte_flow_action actions[],
9608                   struct rte_flow_error *error)
9609 {
9610         int ret;
9611
9612         flow_dv_shared_lock(dev);
9613         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9614         flow_dv_shared_unlock(dev);
9615         return ret;
9616 }
9617
9618 /*
9619  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9620  */
9621 static int
9622 flow_dv_apply(struct rte_eth_dev *dev,
9623               struct rte_flow *flow,
9624               struct rte_flow_error *error)
9625 {
9626         int ret;
9627
9628         flow_dv_shared_lock(dev);
9629         ret = __flow_dv_apply(dev, flow, error);
9630         flow_dv_shared_unlock(dev);
9631         return ret;
9632 }
9633
9634 /*
9635  * Mutex-protected thunk to lock-free __flow_dv_remove().
9636  */
9637 static void
9638 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9639 {
9640         flow_dv_shared_lock(dev);
9641         __flow_dv_remove(dev, flow);
9642         flow_dv_shared_unlock(dev);
9643 }
9644
9645 /*
9646  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9647  */
9648 static void
9649 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9650 {
9651         flow_dv_shared_lock(dev);
9652         __flow_dv_destroy(dev, flow);
9653         flow_dv_shared_unlock(dev);
9654 }
9655
9656 /*
9657  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9658  */
9659 static uint32_t
9660 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9661 {
9662         uint32_t cnt;
9663
9664         flow_dv_shared_lock(dev);
9665         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9666         flow_dv_shared_unlock(dev);
9667         return cnt;
9668 }
9669
9670 /*
9671  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9672  */
9673 static void
9674 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9675 {
9676         flow_dv_shared_lock(dev);
9677         flow_dv_counter_release(dev, cnt);
9678         flow_dv_shared_unlock(dev);
9679 }
9680
9681 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9682         .validate = flow_dv_validate,
9683         .prepare = flow_dv_prepare,
9684         .translate = flow_dv_translate,
9685         .apply = flow_dv_apply,
9686         .remove = flow_dv_remove,
9687         .destroy = flow_dv_destroy,
9688         .query = flow_dv_query,
9689         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9690         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9691         .create_policer_rules = flow_dv_create_policer_rules,
9692         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9693         .counter_alloc = flow_dv_counter_allocate,
9694         .counter_free = flow_dv_counter_free,
9695         .counter_query = flow_dv_counter_query,
9696         .get_aged_flows = flow_get_aged_flows,
9697 };
9698
9699 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */