drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_cycles.h>
  28 #include <rte_ip.h>
  29 #include <rte_gre.h>
  30 #include <rte_vxlan.h>
  31 #include <rte_gtp.h>
  32
  33 #include <mlx5_glue.h>
  34 #include <mlx5_devx_cmds.h>
  35 #include <mlx5_prm.h>
  36
  37 #include "mlx5_defs.h"
  38 #include "mlx5.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_rxtx.h"
  41
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43
  44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  46 #endif
  47
  48 #ifndef HAVE_MLX5DV_DR_ESWITCH
  49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  51 #endif
  52 #endif
  53
  54 #ifndef HAVE_MLX5DV_DR
  55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  56 #endif
  57
  58 /* VLAN header definitions */
  59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  64
  65 union flow_dv_attr {
  66         struct {
  67                 uint32_t valid:1;
  68                 uint32_t ipv4:1;
  69                 uint32_t ipv6:1;
  70                 uint32_t tcp:1;
  71                 uint32_t udp:1;
  72                 uint32_t reserved:27;
  73         };
  74         uint32_t attr;
  75 };
  76
  77 static int
  78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  79                              struct mlx5_flow_tbl_resource *tbl);
  80
  81 /**
  82  * Initialize flow attributes structure according to flow items' types.
  83  *
  84  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  85  * mode. For tunnel mode, the items to be modified are the outermost ones.
  86  *
  87  * @param[in] item
  88  *   Pointer to item specification.
  89  * @param[out] attr
  90  *   Pointer to flow attributes structure.
  91  * @param[in] dev_flow
  92  *   Pointer to the sub flow.
  93  * @param[in] tunnel_decap
  94  *   Whether action is after tunnel decapsulation.
  95  */
  96 static void
  97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  98                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  99 {
 100         uint64_t layers = dev_flow->handle->layers;
 101
 102         /*
 103          * If layers is already initialized, it means this dev_flow is the
 104          * suffix flow, the layers flags is set by the prefix flow. Need to
 105          * use the layer flags from prefix flow as the suffix flow may not
 106          * have the user defined items as the flow is split.
 107          */
 108         if (layers) {
 109                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 110                         attr->ipv4 = 1;
 111                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 112                         attr->ipv6 = 1;
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 114                         attr->tcp = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 116                         attr->udp = 1;
 117                 attr->valid = 1;
 118                 return;
 119         }
 120         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 121                 uint8_t next_protocol = 0xff;
 122                 switch (item->type) {
 123                 case RTE_FLOW_ITEM_TYPE_GRE:
 124                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 126                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 127                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 128                 case RTE_FLOW_ITEM_TYPE_MPLS:
 129                         if (tunnel_decap)
 130                                 attr->attr = 0;
 131                         break;
 132                 case RTE_FLOW_ITEM_TYPE_IPV4:
 133                         if (!attr->ipv6)
 134                                 attr->ipv4 = 1;
 135                         if (item->mask != NULL &&
 136                             ((const struct rte_flow_item_ipv4 *)
 137                             item->mask)->hdr.next_proto_id)
 138                                 next_protocol =
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->spec))->hdr.next_proto_id &
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->mask))->hdr.next_proto_id;
 143                         if ((next_protocol == IPPROTO_IPIP ||
 144                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 145                                 attr->attr = 0;
 146                         break;
 147                 case RTE_FLOW_ITEM_TYPE_IPV6:
 148                         if (!attr->ipv4)
 149                                 attr->ipv6 = 1;
 150                         if (item->mask != NULL &&
 151                             ((const struct rte_flow_item_ipv6 *)
 152                             item->mask)->hdr.proto)
 153                                 next_protocol =
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->spec))->hdr.proto &
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->mask))->hdr.proto;
 158                         if ((next_protocol == IPPROTO_IPIP ||
 159                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 160                                 attr->attr = 0;
 161                         break;
 162                 case RTE_FLOW_ITEM_TYPE_UDP:
 163                         if (!attr->tcp)
 164                                 attr->udp = 1;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_TCP:
 167                         if (!attr->udp)
 168                                 attr->tcp = 1;
 169                         break;
 170                 default:
 171                         break;
 172                 }
 173         }
 174         attr->valid = 1;
 175 }
 176
 177 /**
 178  * Convert rte_mtr_color to mlx5 color.
 179  *
 180  * @param[in] rcol
 181  *   rte_mtr_color.
 182  *
 183  * @return
 184  *   mlx5 color.
 185  */
 186 static int
 187 rte_col_2_mlx5_col(enum rte_color rcol)
 188 {
 189         switch (rcol) {
 190         case RTE_COLOR_GREEN:
 191                 return MLX5_FLOW_COLOR_GREEN;
 192         case RTE_COLOR_YELLOW:
 193                 return MLX5_FLOW_COLOR_YELLOW;
 194         case RTE_COLOR_RED:
 195                 return MLX5_FLOW_COLOR_RED;
 196         default:
 197                 break;
 198         }
 199         return MLX5_FLOW_COLOR_UNDEFINED;
 200 }
 201
 202 struct field_modify_info {
 203         uint32_t size; /* Size of field in protocol header, in bytes. */
 204         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 205         enum mlx5_modification_field id;
 206 };
 207
 208 struct field_modify_info modify_eth[] = {
 209         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 210         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 211         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 212         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_vlan_out_first_vid[] = {
 217         /* Size in bits !!! */
 218         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_ipv4[] = {
 223         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 224         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 225         {4, 12, MLX5_MODI_OUT_SIPV4},
 226         {4, 16, MLX5_MODI_OUT_DIPV4},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_ipv6[] = {
 231         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 232         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 233         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 234         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 235         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 236         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 237         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 238         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 239         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 240         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 241         {0, 0, 0},
 242 };
 243
 244 struct field_modify_info modify_udp[] = {
 245         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 246         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_tcp[] = {
 251         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 253         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 254         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 255         {0, 0, 0},
 256 };
 257
 258 static void
 259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 260                           uint8_t next_protocol, uint64_t *item_flags,
 261                           int *tunnel)
 262 {
 263         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 264                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 265         if (next_protocol == IPPROTO_IPIP) {
 266                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 267                 *tunnel = 1;
 268         }
 269         if (next_protocol == IPPROTO_IPV6) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 271                 *tunnel = 1;
 272         }
 273 }
 274
 275 /**
 276  * Acquire the synchronizing object to protect multithreaded access
 277  * to shared dv context. Lock occurs only if context is actually
 278  * shared, i.e. we have multiport IB device and representors are
 279  * created.
 280  *
 281  * @param[in] dev
 282  *   Pointer to the rte_eth_dev structure.
 283  */
 284 static void
 285 flow_dv_shared_lock(struct rte_eth_dev *dev)
 286 {
 287         struct mlx5_priv *priv = dev->data->dev_private;
 288         struct mlx5_dev_ctx_shared *sh = priv->sh;
 289
 290         if (sh->dv_refcnt > 1) {
 291                 int ret;
 292
 293                 ret = pthread_mutex_lock(&sh->dv_mutex);
 294                 MLX5_ASSERT(!ret);
 295                 (void)ret;
 296         }
 297 }
 298
 299 static void
 300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 301 {
 302         struct mlx5_priv *priv = dev->data->dev_private;
 303         struct mlx5_dev_ctx_shared *sh = priv->sh;
 304
 305         if (sh->dv_refcnt > 1) {
 306                 int ret;
 307
 308                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 309                 MLX5_ASSERT(!ret);
 310                 (void)ret;
 311         }
 312 }
 313
 314 /* Update VLAN's VID/PCP based on input rte_flow_action.
 315  *
 316  * @param[in] action
 317  *   Pointer to struct rte_flow_action.
 318  * @param[out] vlan
 319  *   Pointer to struct rte_vlan_hdr.
 320  */
 321 static void
 322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 323                          struct rte_vlan_hdr *vlan)
 324 {
 325         uint16_t vlan_tci;
 326         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 327                 vlan_tci =
 328                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 329                                                action->conf)->vlan_pcp;
 330                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 331                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 332                 vlan->vlan_tci |= vlan_tci;
 333         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 334                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 335                 vlan->vlan_tci |= rte_be_to_cpu_16
 336                     (((const struct rte_flow_action_of_set_vlan_vid *)
 337                                              action->conf)->vlan_vid);
 338         }
 339 }
 340
 341 /**
 342  * Fetch 1, 2, 3 or 4 byte field from the byte array
 343  * and return as unsigned integer in host-endian format.
 344  *
 345  * @param[in] data
 346  *   Pointer to data array.
 347  * @param[in] size
 348  *   Size of field to extract.
 349  *
 350  * @return
 351  *   converted field in host endian format.
 352  */
 353 static inline uint32_t
 354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 355 {
 356         uint32_t ret;
 357
 358         switch (size) {
 359         case 1:
 360                 ret = *data;
 361                 break;
 362         case 2:
 363                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 364                 break;
 365         case 3:
 366                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 367                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 368                 break;
 369         case 4:
 370                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 371                 break;
 372         default:
 373                 MLX5_ASSERT(false);
 374                 ret = 0;
 375                 break;
 376         }
 377         return ret;
 378 }
 379
 380 /**
 381  * Convert modify-header action to DV specification.
 382  *
 383  * Data length of each action is determined by provided field description
 384  * and the item mask. Data bit offset and width of each action is determined
 385  * by provided item mask.
 386  *
 387  * @param[in] item
 388  *   Pointer to item specification.
 389  * @param[in] field
 390  *   Pointer to field modification information.
 391  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 393  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 394  * @param[in] dcopy
 395  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 396  *   Negative offset value sets the same offset as source offset.
 397  *   size field is ignored, value is taken from source field.
 398  * @param[in,out] resource
 399  *   Pointer to the modify-header resource.
 400  * @param[in] type
 401  *   Type of modification.
 402  * @param[out] error
 403  *   Pointer to the error structure.
 404  *
 405  * @return
 406  *   0 on success, a negative errno value otherwise and rte_errno is set.
 407  */
 408 static int
 409 flow_dv_convert_modify_action(struct rte_flow_item *item,
 410                               struct field_modify_info *field,
 411                               struct field_modify_info *dcopy,
 412                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 413                               uint32_t type, struct rte_flow_error *error)
 414 {
 415         uint32_t i = resource->actions_num;
 416         struct mlx5_modification_cmd *actions = resource->actions;
 417
 418         /*
 419          * The item and mask are provided in big-endian format.
 420          * The fields should be presented as in big-endian format either.
 421          * Mask must be always present, it defines the actual field width.
 422          */
 423         MLX5_ASSERT(item->mask);
 424         MLX5_ASSERT(field->size);
 425         do {
 426                 unsigned int size_b;
 427                 unsigned int off_b;
 428                 uint32_t mask;
 429                 uint32_t data;
 430
 431                 if (i >= MLX5_MAX_MODIFY_NUM)
 432                         return rte_flow_error_set(error, EINVAL,
 433                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 434                                  "too many items to modify");
 435                 /* Fetch variable byte size mask from the array. */
 436                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 437                                            field->offset, field->size);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /**
1643  * Validate VLAN item.
1644  *
1645  * @param[in] item
1646  *   Item specification.
1647  * @param[in] item_flags
1648  *   Bit-fields that holds the items detected until now.
1649  * @param[in] dev
1650  *   Ethernet device flow is being created on.
1651  * @param[out] error
1652  *   Pointer to error structure.
1653  *
1654  * @return
1655  *   0 on success, a negative errno value otherwise and rte_errno is set.
1656  */
1657 static int
1658 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1659                            uint64_t item_flags,
1660                            struct rte_eth_dev *dev,
1661                            struct rte_flow_error *error)
1662 {
1663         const struct rte_flow_item_vlan *mask = item->mask;
1664         const struct rte_flow_item_vlan nic_mask = {
1665                 .tci = RTE_BE16(UINT16_MAX),
1666                 .inner_type = RTE_BE16(UINT16_MAX),
1667         };
1668         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1669         int ret;
1670         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1671                                         MLX5_FLOW_LAYER_INNER_L4) :
1672                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1673                                         MLX5_FLOW_LAYER_OUTER_L4);
1674         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1675                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1676
1677         if (item_flags & vlanm)
1678                 return rte_flow_error_set(error, EINVAL,
1679                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1680                                           "multiple VLAN layers not supported");
1681         else if ((item_flags & l34m) != 0)
1682                 return rte_flow_error_set(error, EINVAL,
1683                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1684                                           "VLAN cannot follow L3/L4 layer");
1685         if (!mask)
1686                 mask = &rte_flow_item_vlan_mask;
1687         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1688                                         (const uint8_t *)&nic_mask,
1689                                         sizeof(struct rte_flow_item_vlan),
1690                                         error);
1691         if (ret)
1692                 return ret;
1693         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1694                 struct mlx5_priv *priv = dev->data->dev_private;
1695
1696                 if (priv->vmwa_context) {
1697                         /*
1698                          * Non-NULL context means we have a virtual machine
1699                          * and SR-IOV enabled, we have to create VLAN interface
1700                          * to make hypervisor to setup E-Switch vport
1701                          * context correctly. We avoid creating the multiple
1702                          * VLAN interfaces, so we cannot support VLAN tag mask.
1703                          */
1704                         return rte_flow_error_set(error, EINVAL,
1705                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1706                                                   item,
1707                                                   "VLAN tag mask is not"
1708                                                   " supported in virtual"
1709                                                   " environment");
1710                 }
1711         }
1712         return 0;
1713 }
1714
1715 /*
1716  * GTP flags are contained in 1 byte of the format:
1717  * -------------------------------------------
1718  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1719  * |-----------------------------------------|
1720  * | value | Version | PT | Res | E | S | PN |
1721  * -------------------------------------------
1722  *
1723  * Matching is supported only for GTP flags E, S, PN.
1724  */
1725 #define MLX5_GTP_FLAGS_MASK     0x07
1726
1727 /**
1728  * Validate GTP item.
1729  *
1730  * @param[in] dev
1731  *   Pointer to the rte_eth_dev structure.
1732  * @param[in] item
1733  *   Item specification.
1734  * @param[in] item_flags
1735  *   Bit-fields that holds the items detected until now.
1736  * @param[out] error
1737  *   Pointer to error structure.
1738  *
1739  * @return
1740  *   0 on success, a negative errno value otherwise and rte_errno is set.
1741  */
1742 static int
1743 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1744                           const struct rte_flow_item *item,
1745                           uint64_t item_flags,
1746                           struct rte_flow_error *error)
1747 {
1748         struct mlx5_priv *priv = dev->data->dev_private;
1749         const struct rte_flow_item_gtp *spec = item->spec;
1750         const struct rte_flow_item_gtp *mask = item->mask;
1751         const struct rte_flow_item_gtp nic_mask = {
1752                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1753                 .msg_type = 0xff,
1754                 .teid = RTE_BE32(0xffffffff),
1755         };
1756
1757         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1758                 return rte_flow_error_set(error, ENOTSUP,
1759                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1760                                           "GTP support is not enabled");
1761         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1762                 return rte_flow_error_set(error, ENOTSUP,
1763                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1764                                           "multiple tunnel layers not"
1765                                           " supported");
1766         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1767                 return rte_flow_error_set(error, EINVAL,
1768                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1769                                           "no outer UDP layer found");
1770         if (!mask)
1771                 mask = &rte_flow_item_gtp_mask;
1772         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "Match is supported for GTP"
1776                                           " flags only");
1777         return mlx5_flow_item_acceptable
1778                 (item, (const uint8_t *)mask,
1779                  (const uint8_t *)&nic_mask,
1780                  sizeof(struct rte_flow_item_gtp),
1781                  error);
1782 }
1783
1784 /**
1785  * Validate the pop VLAN action.
1786  *
1787  * @param[in] dev
1788  *   Pointer to the rte_eth_dev structure.
1789  * @param[in] action_flags
1790  *   Holds the actions detected until now.
1791  * @param[in] action
1792  *   Pointer to the pop vlan action.
1793  * @param[in] item_flags
1794  *   The items found in this flow rule.
1795  * @param[in] attr
1796  *   Pointer to flow attributes.
1797  * @param[out] error
1798  *   Pointer to error structure.
1799  *
1800  * @return
1801  *   0 on success, a negative errno value otherwise and rte_errno is set.
1802  */
1803 static int
1804 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1805                                  uint64_t action_flags,
1806                                  const struct rte_flow_action *action,
1807                                  uint64_t item_flags,
1808                                  const struct rte_flow_attr *attr,
1809                                  struct rte_flow_error *error)
1810 {
1811         const struct mlx5_priv *priv = dev->data->dev_private;
1812
1813         (void)action;
1814         (void)attr;
1815         if (!priv->sh->pop_vlan_action)
1816                 return rte_flow_error_set(error, ENOTSUP,
1817                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1818                                           NULL,
1819                                           "pop vlan action is not supported");
1820         if (attr->egress)
1821                 return rte_flow_error_set(error, ENOTSUP,
1822                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1823                                           NULL,
1824                                           "pop vlan action not supported for "
1825                                           "egress");
1826         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1829                                           "no support for multiple VLAN "
1830                                           "actions");
1831         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1834                                           NULL,
1835                                           "cannot pop vlan without a "
1836                                           "match on (outer) vlan in the flow");
1837         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1838                 return rte_flow_error_set(error, EINVAL,
1839                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1840                                           "wrong action order, port_id should "
1841                                           "be after pop VLAN action");
1842         if (!attr->transfer && priv->representor)
1843                 return rte_flow_error_set(error, ENOTSUP,
1844                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1845                                           "pop vlan action for VF representor "
1846                                           "not supported on NIC table");
1847         return 0;
1848 }
1849
1850 /**
1851  * Get VLAN default info from vlan match info.
1852  *
1853  * @param[in] items
1854  *   the list of item specifications.
1855  * @param[out] vlan
1856  *   pointer VLAN info to fill to.
1857  *
1858  * @return
1859  *   0 on success, a negative errno value otherwise and rte_errno is set.
1860  */
1861 static void
1862 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1863                                   struct rte_vlan_hdr *vlan)
1864 {
1865         const struct rte_flow_item_vlan nic_mask = {
1866                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1867                                 MLX5DV_FLOW_VLAN_VID_MASK),
1868                 .inner_type = RTE_BE16(0xffff),
1869         };
1870
1871         if (items == NULL)
1872                 return;
1873         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1874                 int type = items->type;
1875
1876                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1877                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1878                         break;
1879         }
1880         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1881                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1882                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1883
1884                 /* If VLAN item in pattern doesn't contain data, return here. */
1885                 if (!vlan_v)
1886                         return;
1887                 if (!vlan_m)
1888                         vlan_m = &nic_mask;
1889                 /* Only full match values are accepted */
1890                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1891                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1892                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1893                         vlan->vlan_tci |=
1894                                 rte_be_to_cpu_16(vlan_v->tci &
1895                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1896                 }
1897                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1898                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1899                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1900                         vlan->vlan_tci |=
1901                                 rte_be_to_cpu_16(vlan_v->tci &
1902                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1903                 }
1904                 if (vlan_m->inner_type == nic_mask.inner_type)
1905                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1906                                                            vlan_m->inner_type);
1907         }
1908 }
1909
1910 /**
1911  * Validate the push VLAN action.
1912  *
1913  * @param[in] dev
1914  *   Pointer to the rte_eth_dev structure.
1915  * @param[in] action_flags
1916  *   Holds the actions detected until now.
1917  * @param[in] item_flags
1918  *   The items found in this flow rule.
1919  * @param[in] action
1920  *   Pointer to the action structure.
1921  * @param[in] attr
1922  *   Pointer to flow attributes
1923  * @param[out] error
1924  *   Pointer to error structure.
1925  *
1926  * @return
1927  *   0 on success, a negative errno value otherwise and rte_errno is set.
1928  */
1929 static int
1930 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1931                                   uint64_t action_flags,
1932                                   const struct rte_flow_item_vlan *vlan_m,
1933                                   const struct rte_flow_action *action,
1934                                   const struct rte_flow_attr *attr,
1935                                   struct rte_flow_error *error)
1936 {
1937         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1938         const struct mlx5_priv *priv = dev->data->dev_private;
1939
1940         if (!attr->transfer && attr->ingress)
1941                 return rte_flow_error_set(error, ENOTSUP,
1942                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1943                                           NULL,
1944                                           "push VLAN action not supported for "
1945                                           "ingress");
1946         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1947             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1948                 return rte_flow_error_set(error, EINVAL,
1949                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1950                                           "invalid vlan ethertype");
1951         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1952                 return rte_flow_error_set(error, ENOTSUP,
1953                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1954                                           "no support for multiple VLAN "
1955                                           "actions");
1956         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1957                 return rte_flow_error_set(error, EINVAL,
1958                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1959                                           "wrong action order, port_id should "
1960                                           "be after push VLAN");
1961         if (!attr->transfer && priv->representor)
1962                 return rte_flow_error_set(error, ENOTSUP,
1963                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1964                                           "push vlan action for VF representor "
1965                                           "not supported on NIC table");
1966         if (vlan_m &&
1967             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1968             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1969                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1970             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1971             !(mlx5_flow_find_action
1972                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1973                 return rte_flow_error_set(error, EINVAL,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1975                                           "not full match mask on VLAN PCP and "
1976                                           "there is no of_set_vlan_pcp action, "
1977                                           "push VLAN action cannot figure out "
1978                                           "PCP value");
1979         if (vlan_m &&
1980             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1981             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1982                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1983             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1984             !(mlx5_flow_find_action
1985                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1986                 return rte_flow_error_set(error, EINVAL,
1987                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1988                                           "not full match mask on VLAN VID and "
1989                                           "there is no of_set_vlan_vid action, "
1990                                           "push VLAN action cannot figure out "
1991                                           "VID value");
1992         (void)attr;
1993         return 0;
1994 }
1995
1996 /**
1997  * Validate the set VLAN PCP.
1998  *
1999  * @param[in] action_flags
2000  *   Holds the actions detected until now.
2001  * @param[in] actions
2002  *   Pointer to the list of actions remaining in the flow rule.
2003  * @param[out] error
2004  *   Pointer to error structure.
2005  *
2006  * @return
2007  *   0 on success, a negative errno value otherwise and rte_errno is set.
2008  */
2009 static int
2010 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2011                                      const struct rte_flow_action actions[],
2012                                      struct rte_flow_error *error)
2013 {
2014         const struct rte_flow_action *action = actions;
2015         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2016
2017         if (conf->vlan_pcp > 7)
2018                 return rte_flow_error_set(error, EINVAL,
2019                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2020                                           "VLAN PCP value is too big");
2021         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2022                 return rte_flow_error_set(error, ENOTSUP,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2024                                           "set VLAN PCP action must follow "
2025                                           "the push VLAN action");
2026         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2027                 return rte_flow_error_set(error, ENOTSUP,
2028                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2029                                           "Multiple VLAN PCP modification are "
2030                                           "not supported");
2031         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2032                 return rte_flow_error_set(error, EINVAL,
2033                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2034                                           "wrong action order, port_id should "
2035                                           "be after set VLAN PCP");
2036         return 0;
2037 }
2038
2039 /**
2040  * Validate the set VLAN VID.
2041  *
2042  * @param[in] item_flags
2043  *   Holds the items detected in this rule.
2044  * @param[in] action_flags
2045  *   Holds the actions detected until now.
2046  * @param[in] actions
2047  *   Pointer to the list of actions remaining in the flow rule.
2048  * @param[out] error
2049  *   Pointer to error structure.
2050  *
2051  * @return
2052  *   0 on success, a negative errno value otherwise and rte_errno is set.
2053  */
2054 static int
2055 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2056                                      uint64_t action_flags,
2057                                      const struct rte_flow_action actions[],
2058                                      struct rte_flow_error *error)
2059 {
2060         const struct rte_flow_action *action = actions;
2061         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2062
2063         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2064                 return rte_flow_error_set(error, EINVAL,
2065                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2066                                           "VLAN VID value is too big");
2067         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2068             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2069                 return rte_flow_error_set(error, ENOTSUP,
2070                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2071                                           "set VLAN VID action must follow push"
2072                                           " VLAN action or match on VLAN item");
2073         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2074                 return rte_flow_error_set(error, ENOTSUP,
2075                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2076                                           "Multiple VLAN VID modifications are "
2077                                           "not supported");
2078         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2079                 return rte_flow_error_set(error, EINVAL,
2080                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2081                                           "wrong action order, port_id should "
2082                                           "be after set VLAN VID");
2083         return 0;
2084 }
2085
2086 /*
2087  * Validate the FLAG action.
2088  *
2089  * @param[in] dev
2090  *   Pointer to the rte_eth_dev structure.
2091  * @param[in] action_flags
2092  *   Holds the actions detected until now.
2093  * @param[in] attr
2094  *   Pointer to flow attributes
2095  * @param[out] error
2096  *   Pointer to error structure.
2097  *
2098  * @return
2099  *   0 on success, a negative errno value otherwise and rte_errno is set.
2100  */
2101 static int
2102 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2103                              uint64_t action_flags,
2104                              const struct rte_flow_attr *attr,
2105                              struct rte_flow_error *error)
2106 {
2107         struct mlx5_priv *priv = dev->data->dev_private;
2108         struct mlx5_dev_config *config = &priv->config;
2109         int ret;
2110
2111         /* Fall back if no extended metadata register support. */
2112         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2113                 return mlx5_flow_validate_action_flag(action_flags, attr,
2114                                                       error);
2115         /* Extensive metadata mode requires registers. */
2116         if (!mlx5_flow_ext_mreg_supported(dev))
2117                 return rte_flow_error_set(error, ENOTSUP,
2118                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2119                                           "no metadata registers "
2120                                           "to support flag action");
2121         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2122                 return rte_flow_error_set(error, ENOTSUP,
2123                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2124                                           "extended metadata register"
2125                                           " isn't available");
2126         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2127         if (ret < 0)
2128                 return ret;
2129         MLX5_ASSERT(ret > 0);
2130         if (action_flags & MLX5_FLOW_ACTION_MARK)
2131                 return rte_flow_error_set(error, EINVAL,
2132                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2133                                           "can't mark and flag in same flow");
2134         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2135                 return rte_flow_error_set(error, EINVAL,
2136                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137                                           "can't have 2 flag"
2138                                           " actions in same flow");
2139         return 0;
2140 }
2141
2142 /**
2143  * Validate MARK action.
2144  *
2145  * @param[in] dev
2146  *   Pointer to the rte_eth_dev structure.
2147  * @param[in] action
2148  *   Pointer to action.
2149  * @param[in] action_flags
2150  *   Holds the actions detected until now.
2151  * @param[in] attr
2152  *   Pointer to flow attributes
2153  * @param[out] error
2154  *   Pointer to error structure.
2155  *
2156  * @return
2157  *   0 on success, a negative errno value otherwise and rte_errno is set.
2158  */
2159 static int
2160 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2161                              const struct rte_flow_action *action,
2162                              uint64_t action_flags,
2163                              const struct rte_flow_attr *attr,
2164                              struct rte_flow_error *error)
2165 {
2166         struct mlx5_priv *priv = dev->data->dev_private;
2167         struct mlx5_dev_config *config = &priv->config;
2168         const struct rte_flow_action_mark *mark = action->conf;
2169         int ret;
2170
2171         /* Fall back if no extended metadata register support. */
2172         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2173                 return mlx5_flow_validate_action_mark(action, action_flags,
2174                                                       attr, error);
2175         /* Extensive metadata mode requires registers. */
2176         if (!mlx5_flow_ext_mreg_supported(dev))
2177                 return rte_flow_error_set(error, ENOTSUP,
2178                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2179                                           "no metadata registers "
2180                                           "to support mark action");
2181         if (!priv->sh->dv_mark_mask)
2182                 return rte_flow_error_set(error, ENOTSUP,
2183                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2184                                           "extended metadata register"
2185                                           " isn't available");
2186         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2187         if (ret < 0)
2188                 return ret;
2189         MLX5_ASSERT(ret > 0);
2190         if (!mark)
2191                 return rte_flow_error_set(error, EINVAL,
2192                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2193                                           "configuration cannot be null");
2194         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2195                 return rte_flow_error_set(error, EINVAL,
2196                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2197                                           &mark->id,
2198                                           "mark id exceeds the limit");
2199         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2200                 return rte_flow_error_set(error, EINVAL,
2201                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2202                                           "can't flag and mark in same flow");
2203         if (action_flags & MLX5_FLOW_ACTION_MARK)
2204                 return rte_flow_error_set(error, EINVAL,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206                                           "can't have 2 mark actions in same"
2207                                           " flow");
2208         return 0;
2209 }
2210
2211 /**
2212  * Validate SET_META action.
2213  *
2214  * @param[in] dev
2215  *   Pointer to the rte_eth_dev structure.
2216  * @param[in] action
2217  *   Pointer to the action structure.
2218  * @param[in] action_flags
2219  *   Holds the actions detected until now.
2220  * @param[in] attr
2221  *   Pointer to flow attributes
2222  * @param[out] error
2223  *   Pointer to error structure.
2224  *
2225  * @return
2226  *   0 on success, a negative errno value otherwise and rte_errno is set.
2227  */
2228 static int
2229 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2230                                  const struct rte_flow_action *action,
2231                                  uint64_t action_flags __rte_unused,
2232                                  const struct rte_flow_attr *attr,
2233                                  struct rte_flow_error *error)
2234 {
2235         const struct rte_flow_action_set_meta *conf;
2236         uint32_t nic_mask = UINT32_MAX;
2237         int reg;
2238
2239         if (!mlx5_flow_ext_mreg_supported(dev))
2240                 return rte_flow_error_set(error, ENOTSUP,
2241                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2242                                           "extended metadata register"
2243                                           " isn't supported");
2244         reg = flow_dv_get_metadata_reg(dev, attr, error);
2245         if (reg < 0)
2246                 return reg;
2247         if (reg != REG_A && reg != REG_B) {
2248                 struct mlx5_priv *priv = dev->data->dev_private;
2249
2250                 nic_mask = priv->sh->dv_meta_mask;
2251         }
2252         if (!(action->conf))
2253                 return rte_flow_error_set(error, EINVAL,
2254                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2255                                           "configuration cannot be null");
2256         conf = (const struct rte_flow_action_set_meta *)action->conf;
2257         if (!conf->mask)
2258                 return rte_flow_error_set(error, EINVAL,
2259                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2260                                           "zero mask doesn't have any effect");
2261         if (conf->mask & ~nic_mask)
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "meta data must be within reg C0");
2265         return 0;
2266 }
2267
2268 /**
2269  * Validate SET_TAG action.
2270  *
2271  * @param[in] dev
2272  *   Pointer to the rte_eth_dev structure.
2273  * @param[in] action
2274  *   Pointer to the action structure.
2275  * @param[in] action_flags
2276  *   Holds the actions detected until now.
2277  * @param[in] attr
2278  *   Pointer to flow attributes
2279  * @param[out] error
2280  *   Pointer to error structure.
2281  *
2282  * @return
2283  *   0 on success, a negative errno value otherwise and rte_errno is set.
2284  */
2285 static int
2286 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2287                                 const struct rte_flow_action *action,
2288                                 uint64_t action_flags,
2289                                 const struct rte_flow_attr *attr,
2290                                 struct rte_flow_error *error)
2291 {
2292         const struct rte_flow_action_set_tag *conf;
2293         const uint64_t terminal_action_flags =
2294                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2295                 MLX5_FLOW_ACTION_RSS;
2296         int ret;
2297
2298         if (!mlx5_flow_ext_mreg_supported(dev))
2299                 return rte_flow_error_set(error, ENOTSUP,
2300                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2301                                           "extensive metadata register"
2302                                           " isn't supported");
2303         if (!(action->conf))
2304                 return rte_flow_error_set(error, EINVAL,
2305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2306                                           "configuration cannot be null");
2307         conf = (const struct rte_flow_action_set_tag *)action->conf;
2308         if (!conf->mask)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2311                                           "zero mask doesn't have any effect");
2312         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2313         if (ret < 0)
2314                 return ret;
2315         if (!attr->transfer && attr->ingress &&
2316             (action_flags & terminal_action_flags))
2317                 return rte_flow_error_set(error, EINVAL,
2318                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2319                                           "set_tag has no effect"
2320                                           " with terminal actions");
2321         return 0;
2322 }
2323
2324 /**
2325  * Validate count action.
2326  *
2327  * @param[in] dev
2328  *   Pointer to rte_eth_dev structure.
2329  * @param[out] error
2330  *   Pointer to error structure.
2331  *
2332  * @return
2333  *   0 on success, a negative errno value otherwise and rte_errno is set.
2334  */
2335 static int
2336 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2337                               struct rte_flow_error *error)
2338 {
2339         struct mlx5_priv *priv = dev->data->dev_private;
2340
2341         if (!priv->config.devx)
2342                 goto notsup_err;
2343 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2344         return 0;
2345 #endif
2346 notsup_err:
2347         return rte_flow_error_set
2348                       (error, ENOTSUP,
2349                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2350                        NULL,
2351                        "count action not supported");
2352 }
2353
2354 /**
2355  * Validate the L2 encap action.
2356  *
2357  * @param[in] dev
2358  *   Pointer to the rte_eth_dev structure.
2359  * @param[in] action_flags
2360  *   Holds the actions detected until now.
2361  * @param[in] action
2362  *   Pointer to the action structure.
2363  * @param[in] attr
2364  *   Pointer to flow attributes.
2365  * @param[out] error
2366  *   Pointer to error structure.
2367  *
2368  * @return
2369  *   0 on success, a negative errno value otherwise and rte_errno is set.
2370  */
2371 static int
2372 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2373                                  uint64_t action_flags,
2374                                  const struct rte_flow_action *action,
2375                                  const struct rte_flow_attr *attr,
2376                                  struct rte_flow_error *error)
2377 {
2378         const struct mlx5_priv *priv = dev->data->dev_private;
2379
2380         if (!(action->conf))
2381                 return rte_flow_error_set(error, EINVAL,
2382                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2383                                           "configuration cannot be null");
2384         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387                                           "can only have a single encap action "
2388                                           "in a flow");
2389         if (!attr->transfer && priv->representor)
2390                 return rte_flow_error_set(error, ENOTSUP,
2391                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2392                                           "encap action for VF representor "
2393                                           "not supported on NIC table");
2394         return 0;
2395 }
2396
2397 /**
2398  * Validate a decap action.
2399  *
2400  * @param[in] dev
2401  *   Pointer to the rte_eth_dev structure.
2402  * @param[in] action_flags
2403  *   Holds the actions detected until now.
2404  * @param[in] attr
2405  *   Pointer to flow attributes
2406  * @param[out] error
2407  *   Pointer to error structure.
2408  *
2409  * @return
2410  *   0 on success, a negative errno value otherwise and rte_errno is set.
2411  */
2412 static int
2413 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2414                               uint64_t action_flags,
2415                               const struct rte_flow_attr *attr,
2416                               struct rte_flow_error *error)
2417 {
2418         const struct mlx5_priv *priv = dev->data->dev_private;
2419
2420         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2421                 return rte_flow_error_set(error, ENOTSUP,
2422                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2423                                           action_flags &
2424                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2425                                           "have a single decap action" : "decap "
2426                                           "after encap is not supported");
2427         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2428                 return rte_flow_error_set(error, EINVAL,
2429                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2430                                           "can't have decap action after"
2431                                           " modify action");
2432         if (attr->egress)
2433                 return rte_flow_error_set(error, ENOTSUP,
2434                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2435                                           NULL,
2436                                           "decap action not supported for "
2437                                           "egress");
2438         if (!attr->transfer && priv->representor)
2439                 return rte_flow_error_set(error, ENOTSUP,
2440                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2441                                           "decap action for VF representor "
2442                                           "not supported on NIC table");
2443         return 0;
2444 }
2445
2446 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2447
2448 /**
2449  * Validate the raw encap and decap actions.
2450  *
2451  * @param[in] dev
2452  *   Pointer to the rte_eth_dev structure.
2453  * @param[in] decap
2454  *   Pointer to the decap action.
2455  * @param[in] encap
2456  *   Pointer to the encap action.
2457  * @param[in] attr
2458  *   Pointer to flow attributes
2459  * @param[in/out] action_flags
2460  *   Holds the actions detected until now.
2461  * @param[out] actions_n
2462  *   pointer to the number of actions counter.
2463  * @param[out] error
2464  *   Pointer to error structure.
2465  *
2466  * @return
2467  *   0 on success, a negative errno value otherwise and rte_errno is set.
2468  */
2469 static int
2470 flow_dv_validate_action_raw_encap_decap
2471         (struct rte_eth_dev *dev,
2472          const struct rte_flow_action_raw_decap *decap,
2473          const struct rte_flow_action_raw_encap *encap,
2474          const struct rte_flow_attr *attr, uint64_t *action_flags,
2475          int *actions_n, struct rte_flow_error *error)
2476 {
2477         const struct mlx5_priv *priv = dev->data->dev_private;
2478         int ret;
2479
2480         if (encap && (!encap->size || !encap->data))
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2483                                           "raw encap data cannot be empty");
2484         if (decap && encap) {
2485                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2486                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2487                         /* L3 encap. */
2488                         decap = NULL;
2489                 else if (encap->size <=
2490                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2491                            decap->size >
2492                            MLX5_ENCAPSULATION_DECISION_SIZE)
2493                         /* L3 decap. */
2494                         encap = NULL;
2495                 else if (encap->size >
2496                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2497                            decap->size >
2498                            MLX5_ENCAPSULATION_DECISION_SIZE)
2499                         /* 2 L2 actions: encap and decap. */
2500                         ;
2501                 else
2502                         return rte_flow_error_set(error,
2503                                 ENOTSUP,
2504                                 RTE_FLOW_ERROR_TYPE_ACTION,
2505                                 NULL, "unsupported too small "
2506                                 "raw decap and too small raw "
2507                                 "encap combination");
2508         }
2509         if (decap) {
2510                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2511                                                     error);
2512                 if (ret < 0)
2513                         return ret;
2514                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2515                 ++(*actions_n);
2516         }
2517         if (encap) {
2518                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2519                         return rte_flow_error_set(error, ENOTSUP,
2520                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2521                                                   NULL,
2522                                                   "small raw encap size");
2523                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2524                         return rte_flow_error_set(error, EINVAL,
2525                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2526                                                   NULL,
2527                                                   "more than one encap action");
2528                 if (!attr->transfer && priv->representor)
2529                         return rte_flow_error_set
2530                                         (error, ENOTSUP,
2531                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2532                                          "encap action for VF representor "
2533                                          "not supported on NIC table");
2534                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2535                 ++(*actions_n);
2536         }
2537         return 0;
2538 }
2539
2540 /**
2541  * Find existing encap/decap resource or create and register a new one.
2542  *
2543  * @param[in, out] dev
2544  *   Pointer to rte_eth_dev structure.
2545  * @param[in, out] resource
2546  *   Pointer to encap/decap resource.
2547  * @parm[in, out] dev_flow
2548  *   Pointer to the dev_flow.
2549  * @param[out] error
2550  *   pointer to error structure.
2551  *
2552  * @return
2553  *   0 on success otherwise -errno and errno is set.
2554  */
2555 static int
2556 flow_dv_encap_decap_resource_register
2557                         (struct rte_eth_dev *dev,
2558                          struct mlx5_flow_dv_encap_decap_resource *resource,
2559                          struct mlx5_flow *dev_flow,
2560                          struct rte_flow_error *error)
2561 {
2562         struct mlx5_priv *priv = dev->data->dev_private;
2563         struct mlx5_dev_ctx_shared *sh = priv->sh;
2564         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2565         struct mlx5dv_dr_domain *domain;
2566         uint32_t idx = 0;
2567
2568         resource->flags = dev_flow->dv.group ? 0 : 1;
2569         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2570                 domain = sh->fdb_domain;
2571         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2572                 domain = sh->rx_domain;
2573         else
2574                 domain = sh->tx_domain;
2575         /* Lookup a matching resource from cache. */
2576         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2577                       cache_resource, next) {
2578                 if (resource->reformat_type == cache_resource->reformat_type &&
2579                     resource->ft_type == cache_resource->ft_type &&
2580                     resource->flags == cache_resource->flags &&
2581                     resource->size == cache_resource->size &&
2582                     !memcmp((const void *)resource->buf,
2583                             (const void *)cache_resource->buf,
2584                             resource->size)) {
2585                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2586                                 (void *)cache_resource,
2587                                 rte_atomic32_read(&cache_resource->refcnt));
2588                         rte_atomic32_inc(&cache_resource->refcnt);
2589                         dev_flow->handle->dvh.rix_encap_decap = idx;
2590                         dev_flow->dv.encap_decap = cache_resource;
2591                         return 0;
2592                 }
2593         }
2594         /* Register new encap/decap resource. */
2595         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2596                                        &dev_flow->handle->dvh.rix_encap_decap);
2597         if (!cache_resource)
2598                 return rte_flow_error_set(error, ENOMEM,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2600                                           "cannot allocate resource memory");
2601         *cache_resource = *resource;
2602         cache_resource->verbs_action =
2603                 mlx5_glue->dv_create_flow_action_packet_reformat
2604                         (sh->ctx, cache_resource->reformat_type,
2605                          cache_resource->ft_type, domain, cache_resource->flags,
2606                          cache_resource->size,
2607                          (cache_resource->size ? cache_resource->buf : NULL));
2608         if (!cache_resource->verbs_action) {
2609                 rte_free(cache_resource);
2610                 return rte_flow_error_set(error, ENOMEM,
2611                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2612                                           NULL, "cannot create action");
2613         }
2614         rte_atomic32_init(&cache_resource->refcnt);
2615         rte_atomic32_inc(&cache_resource->refcnt);
2616         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2617                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2618                      next);
2619         dev_flow->dv.encap_decap = cache_resource;
2620         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2621                 (void *)cache_resource,
2622                 rte_atomic32_read(&cache_resource->refcnt));
2623         return 0;
2624 }
2625
2626 /**
2627  * Find existing table jump resource or create and register a new one.
2628  *
2629  * @param[in, out] dev
2630  *   Pointer to rte_eth_dev structure.
2631  * @param[in, out] tbl
2632  *   Pointer to flow table resource.
2633  * @parm[in, out] dev_flow
2634  *   Pointer to the dev_flow.
2635  * @param[out] error
2636  *   pointer to error structure.
2637  *
2638  * @return
2639  *   0 on success otherwise -errno and errno is set.
2640  */
2641 static int
2642 flow_dv_jump_tbl_resource_register
2643                         (struct rte_eth_dev *dev __rte_unused,
2644                          struct mlx5_flow_tbl_resource *tbl,
2645                          struct mlx5_flow *dev_flow,
2646                          struct rte_flow_error *error)
2647 {
2648         struct mlx5_flow_tbl_data_entry *tbl_data =
2649                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2650         int cnt;
2651
2652         MLX5_ASSERT(tbl);
2653         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2654         if (!cnt) {
2655                 tbl_data->jump.action =
2656                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2657                         (tbl->obj);
2658                 if (!tbl_data->jump.action)
2659                         return rte_flow_error_set(error, ENOMEM,
2660                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2661                                         NULL, "cannot create jump action");
2662                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2663                         (void *)&tbl_data->jump, cnt);
2664         } else {
2665                 /* old jump should not make the table ref++. */
2666                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2667                 MLX5_ASSERT(tbl_data->jump.action);
2668                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2669                         (void *)&tbl_data->jump, cnt);
2670         }
2671         rte_atomic32_inc(&tbl_data->jump.refcnt);
2672         dev_flow->handle->rix_jump = tbl_data->idx;
2673         dev_flow->dv.jump = &tbl_data->jump;
2674         return 0;
2675 }
2676
2677 /**
2678  * Find existing table port ID resource or create and register a new one.
2679  *
2680  * @param[in, out] dev
2681  *   Pointer to rte_eth_dev structure.
2682  * @param[in, out] resource
2683  *   Pointer to port ID action resource.
2684  * @parm[in, out] dev_flow
2685  *   Pointer to the dev_flow.
2686  * @param[out] error
2687  *   pointer to error structure.
2688  *
2689  * @return
2690  *   0 on success otherwise -errno and errno is set.
2691  */
2692 static int
2693 flow_dv_port_id_action_resource_register
2694                         (struct rte_eth_dev *dev,
2695                          struct mlx5_flow_dv_port_id_action_resource *resource,
2696                          struct mlx5_flow *dev_flow,
2697                          struct rte_flow_error *error)
2698 {
2699         struct mlx5_priv *priv = dev->data->dev_private;
2700         struct mlx5_dev_ctx_shared *sh = priv->sh;
2701         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2702         uint32_t idx = 0;
2703
2704         /* Lookup a matching resource from cache. */
2705         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2706                       idx, cache_resource, next) {
2707                 if (resource->port_id == cache_resource->port_id) {
2708                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2709                                 "refcnt %d++",
2710                                 (void *)cache_resource,
2711                                 rte_atomic32_read(&cache_resource->refcnt));
2712                         rte_atomic32_inc(&cache_resource->refcnt);
2713                         dev_flow->handle->rix_port_id_action = idx;
2714                         dev_flow->dv.port_id_action = cache_resource;
2715                         return 0;
2716                 }
2717         }
2718         /* Register new port id action resource. */
2719         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2720                                        &dev_flow->handle->rix_port_id_action);
2721         if (!cache_resource)
2722                 return rte_flow_error_set(error, ENOMEM,
2723                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2724                                           "cannot allocate resource memory");
2725         *cache_resource = *resource;
2726         /*
2727          * Depending on rdma_core version the glue routine calls
2728          * either mlx5dv_dr_action_create_dest_ib_port(domain, dev_port)
2729          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2730          */
2731         cache_resource->action =
2732                 mlx5_glue->dr_create_flow_action_dest_port
2733                         (priv->sh->fdb_domain, resource->port_id);
2734         if (!cache_resource->action) {
2735                 rte_free(cache_resource);
2736                 return rte_flow_error_set(error, ENOMEM,
2737                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2738                                           NULL, "cannot create action");
2739         }
2740         rte_atomic32_init(&cache_resource->refcnt);
2741         rte_atomic32_inc(&cache_resource->refcnt);
2742         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2743                      dev_flow->handle->rix_port_id_action, cache_resource,
2744                      next);
2745         dev_flow->dv.port_id_action = cache_resource;
2746         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2747                 (void *)cache_resource,
2748                 rte_atomic32_read(&cache_resource->refcnt));
2749         return 0;
2750 }
2751
2752 /**
2753  * Find existing push vlan resource or create and register a new one.
2754  *
2755  * @param [in, out] dev
2756  *   Pointer to rte_eth_dev structure.
2757  * @param[in, out] resource
2758  *   Pointer to port ID action resource.
2759  * @parm[in, out] dev_flow
2760  *   Pointer to the dev_flow.
2761  * @param[out] error
2762  *   pointer to error structure.
2763  *
2764  * @return
2765  *   0 on success otherwise -errno and errno is set.
2766  */
2767 static int
2768 flow_dv_push_vlan_action_resource_register
2769                        (struct rte_eth_dev *dev,
2770                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2771                         struct mlx5_flow *dev_flow,
2772                         struct rte_flow_error *error)
2773 {
2774         struct mlx5_priv *priv = dev->data->dev_private;
2775         struct mlx5_dev_ctx_shared *sh = priv->sh;
2776         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2777         struct mlx5dv_dr_domain *domain;
2778         uint32_t idx = 0;
2779
2780         /* Lookup a matching resource from cache. */
2781         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2782                       sh->push_vlan_action_list, idx, cache_resource, next) {
2783                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2784                     resource->ft_type == cache_resource->ft_type) {
2785                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2786                                 "refcnt %d++",
2787                                 (void *)cache_resource,
2788                                 rte_atomic32_read(&cache_resource->refcnt));
2789                         rte_atomic32_inc(&cache_resource->refcnt);
2790                         dev_flow->handle->dvh.rix_push_vlan = idx;
2791                         dev_flow->dv.push_vlan_res = cache_resource;
2792                         return 0;
2793                 }
2794         }
2795         /* Register new push_vlan action resource. */
2796         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2797                                        &dev_flow->handle->dvh.rix_push_vlan);
2798         if (!cache_resource)
2799                 return rte_flow_error_set(error, ENOMEM,
2800                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2801                                           "cannot allocate resource memory");
2802         *cache_resource = *resource;
2803         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2804                 domain = sh->fdb_domain;
2805         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2806                 domain = sh->rx_domain;
2807         else
2808                 domain = sh->tx_domain;
2809         cache_resource->action =
2810                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2811                                                            resource->vlan_tag);
2812         if (!cache_resource->action) {
2813                 rte_free(cache_resource);
2814                 return rte_flow_error_set(error, ENOMEM,
2815                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2816                                           NULL, "cannot create action");
2817         }
2818         rte_atomic32_init(&cache_resource->refcnt);
2819         rte_atomic32_inc(&cache_resource->refcnt);
2820         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821                      &sh->push_vlan_action_list,
2822                      dev_flow->handle->dvh.rix_push_vlan,
2823                      cache_resource, next);
2824         dev_flow->dv.push_vlan_res = cache_resource;
2825         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2826                 (void *)cache_resource,
2827                 rte_atomic32_read(&cache_resource->refcnt));
2828         return 0;
2829 }
2830 /**
2831  * Get the size of specific rte_flow_item_type
2832  *
2833  * @param[in] item_type
2834  *   Tested rte_flow_item_type.
2835  *
2836  * @return
2837  *   sizeof struct item_type, 0 if void or irrelevant.
2838  */
2839 static size_t
2840 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2841 {
2842         size_t retval;
2843
2844         switch (item_type) {
2845         case RTE_FLOW_ITEM_TYPE_ETH:
2846                 retval = sizeof(struct rte_flow_item_eth);
2847                 break;
2848         case RTE_FLOW_ITEM_TYPE_VLAN:
2849                 retval = sizeof(struct rte_flow_item_vlan);
2850                 break;
2851         case RTE_FLOW_ITEM_TYPE_IPV4:
2852                 retval = sizeof(struct rte_flow_item_ipv4);
2853                 break;
2854         case RTE_FLOW_ITEM_TYPE_IPV6:
2855                 retval = sizeof(struct rte_flow_item_ipv6);
2856                 break;
2857         case RTE_FLOW_ITEM_TYPE_UDP:
2858                 retval = sizeof(struct rte_flow_item_udp);
2859                 break;
2860         case RTE_FLOW_ITEM_TYPE_TCP:
2861                 retval = sizeof(struct rte_flow_item_tcp);
2862                 break;
2863         case RTE_FLOW_ITEM_TYPE_VXLAN:
2864                 retval = sizeof(struct rte_flow_item_vxlan);
2865                 break;
2866         case RTE_FLOW_ITEM_TYPE_GRE:
2867                 retval = sizeof(struct rte_flow_item_gre);
2868                 break;
2869         case RTE_FLOW_ITEM_TYPE_NVGRE:
2870                 retval = sizeof(struct rte_flow_item_nvgre);
2871                 break;
2872         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2873                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2874                 break;
2875         case RTE_FLOW_ITEM_TYPE_MPLS:
2876                 retval = sizeof(struct rte_flow_item_mpls);
2877                 break;
2878         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2879         default:
2880                 retval = 0;
2881                 break;
2882         }
2883         return retval;
2884 }
2885
2886 #define MLX5_ENCAP_IPV4_VERSION         0x40
2887 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2888 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2889 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2890 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2891 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2892 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2893
2894 /**
2895  * Convert the encap action data from list of rte_flow_item to raw buffer
2896  *
2897  * @param[in] items
2898  *   Pointer to rte_flow_item objects list.
2899  * @param[out] buf
2900  *   Pointer to the output buffer.
2901  * @param[out] size
2902  *   Pointer to the output buffer size.
2903  * @param[out] error
2904  *   Pointer to the error structure.
2905  *
2906  * @return
2907  *   0 on success, a negative errno value otherwise and rte_errno is set.
2908  */
2909 static int
2910 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2911                            size_t *size, struct rte_flow_error *error)
2912 {
2913         struct rte_ether_hdr *eth = NULL;
2914         struct rte_vlan_hdr *vlan = NULL;
2915         struct rte_ipv4_hdr *ipv4 = NULL;
2916         struct rte_ipv6_hdr *ipv6 = NULL;
2917         struct rte_udp_hdr *udp = NULL;
2918         struct rte_vxlan_hdr *vxlan = NULL;
2919         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2920         struct rte_gre_hdr *gre = NULL;
2921         size_t len;
2922         size_t temp_size = 0;
2923
2924         if (!items)
2925                 return rte_flow_error_set(error, EINVAL,
2926                                           RTE_FLOW_ERROR_TYPE_ACTION,
2927                                           NULL, "invalid empty data");
2928         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2929                 len = flow_dv_get_item_len(items->type);
2930                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2931                         return rte_flow_error_set(error, EINVAL,
2932                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2933                                                   (void *)items->type,
2934                                                   "items total size is too big"
2935                                                   " for encap action");
2936                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2937                 switch (items->type) {
2938                 case RTE_FLOW_ITEM_TYPE_ETH:
2939                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2940                         break;
2941                 case RTE_FLOW_ITEM_TYPE_VLAN:
2942                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2943                         if (!eth)
2944                                 return rte_flow_error_set(error, EINVAL,
2945                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2946                                                 (void *)items->type,
2947                                                 "eth header not found");
2948                         if (!eth->ether_type)
2949                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2950                         break;
2951                 case RTE_FLOW_ITEM_TYPE_IPV4:
2952                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2953                         if (!vlan && !eth)
2954                                 return rte_flow_error_set(error, EINVAL,
2955                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2956                                                 (void *)items->type,
2957                                                 "neither eth nor vlan"
2958                                                 " header found");
2959                         if (vlan && !vlan->eth_proto)
2960                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2961                         else if (eth && !eth->ether_type)
2962                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2963                         if (!ipv4->version_ihl)
2964                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2965                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2966                         if (!ipv4->time_to_live)
2967                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2968                         break;
2969                 case RTE_FLOW_ITEM_TYPE_IPV6:
2970                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2971                         if (!vlan && !eth)
2972                                 return rte_flow_error_set(error, EINVAL,
2973                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2974                                                 (void *)items->type,
2975                                                 "neither eth nor vlan"
2976                                                 " header found");
2977                         if (vlan && !vlan->eth_proto)
2978                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2979                         else if (eth && !eth->ether_type)
2980                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2981                         if (!ipv6->vtc_flow)
2982                                 ipv6->vtc_flow =
2983                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2984                         if (!ipv6->hop_limits)
2985                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2986                         break;
2987                 case RTE_FLOW_ITEM_TYPE_UDP:
2988                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2989                         if (!ipv4 && !ipv6)
2990                                 return rte_flow_error_set(error, EINVAL,
2991                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2992                                                 (void *)items->type,
2993                                                 "ip header not found");
2994                         if (ipv4 && !ipv4->next_proto_id)
2995                                 ipv4->next_proto_id = IPPROTO_UDP;
2996                         else if (ipv6 && !ipv6->proto)
2997                                 ipv6->proto = IPPROTO_UDP;
2998                         break;
2999                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3000                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3001                         if (!udp)
3002                                 return rte_flow_error_set(error, EINVAL,
3003                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3004                                                 (void *)items->type,
3005                                                 "udp header not found");
3006                         if (!udp->dst_port)
3007                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3008                         if (!vxlan->vx_flags)
3009                                 vxlan->vx_flags =
3010                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3011                         break;
3012                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3013                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3014                         if (!udp)
3015                                 return rte_flow_error_set(error, EINVAL,
3016                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3017                                                 (void *)items->type,
3018                                                 "udp header not found");
3019                         if (!vxlan_gpe->proto)
3020                                 return rte_flow_error_set(error, EINVAL,
3021                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3022                                                 (void *)items->type,
3023                                                 "next protocol not found");
3024                         if (!udp->dst_port)
3025                                 udp->dst_port =
3026                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3027                         if (!vxlan_gpe->vx_flags)
3028                                 vxlan_gpe->vx_flags =
3029                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3030                         break;
3031                 case RTE_FLOW_ITEM_TYPE_GRE:
3032                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3033                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3034                         if (!gre->proto)
3035                                 return rte_flow_error_set(error, EINVAL,
3036                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3037                                                 (void *)items->type,
3038                                                 "next protocol not found");
3039                         if (!ipv4 && !ipv6)
3040                                 return rte_flow_error_set(error, EINVAL,
3041                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3042                                                 (void *)items->type,
3043                                                 "ip header not found");
3044                         if (ipv4 && !ipv4->next_proto_id)
3045                                 ipv4->next_proto_id = IPPROTO_GRE;
3046                         else if (ipv6 && !ipv6->proto)
3047                                 ipv6->proto = IPPROTO_GRE;
3048                         break;
3049                 case RTE_FLOW_ITEM_TYPE_VOID:
3050                         break;
3051                 default:
3052                         return rte_flow_error_set(error, EINVAL,
3053                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3054                                                   (void *)items->type,
3055                                                   "unsupported item type");
3056                         break;
3057                 }
3058                 temp_size += len;
3059         }
3060         *size = temp_size;
3061         return 0;
3062 }
3063
3064 static int
3065 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3066 {
3067         struct rte_ether_hdr *eth = NULL;
3068         struct rte_vlan_hdr *vlan = NULL;
3069         struct rte_ipv6_hdr *ipv6 = NULL;
3070         struct rte_udp_hdr *udp = NULL;
3071         char *next_hdr;
3072         uint16_t proto;
3073
3074         eth = (struct rte_ether_hdr *)data;
3075         next_hdr = (char *)(eth + 1);
3076         proto = RTE_BE16(eth->ether_type);
3077
3078         /* VLAN skipping */
3079         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3080                 vlan = (struct rte_vlan_hdr *)next_hdr;
3081                 proto = RTE_BE16(vlan->eth_proto);
3082                 next_hdr += sizeof(struct rte_vlan_hdr);
3083         }
3084
3085         /* HW calculates IPv4 csum. no need to proceed */
3086         if (proto == RTE_ETHER_TYPE_IPV4)
3087                 return 0;
3088
3089         /* non IPv4/IPv6 header. not supported */
3090         if (proto != RTE_ETHER_TYPE_IPV6) {
3091                 return rte_flow_error_set(error, ENOTSUP,
3092                                           RTE_FLOW_ERROR_TYPE_ACTION,
3093                                           NULL, "Cannot offload non IPv4/IPv6");
3094         }
3095
3096         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3097
3098         /* ignore non UDP */
3099         if (ipv6->proto != IPPROTO_UDP)
3100                 return 0;
3101
3102         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3103         udp->dgram_cksum = 0;
3104
3105         return 0;
3106 }
3107
3108 /**
3109  * Convert L2 encap action to DV specification.
3110  *
3111  * @param[in] dev
3112  *   Pointer to rte_eth_dev structure.
3113  * @param[in] action
3114  *   Pointer to action structure.
3115  * @param[in, out] dev_flow
3116  *   Pointer to the mlx5_flow.
3117  * @param[in] transfer
3118  *   Mark if the flow is E-Switch flow.
3119  * @param[out] error
3120  *   Pointer to the error structure.
3121  *
3122  * @return
3123  *   0 on success, a negative errno value otherwise and rte_errno is set.
3124  */
3125 static int
3126 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3127                                const struct rte_flow_action *action,
3128                                struct mlx5_flow *dev_flow,
3129                                uint8_t transfer,
3130                                struct rte_flow_error *error)
3131 {
3132         const struct rte_flow_item *encap_data;
3133         const struct rte_flow_action_raw_encap *raw_encap_data;
3134         struct mlx5_flow_dv_encap_decap_resource res = {
3135                 .reformat_type =
3136                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3137                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3138                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3139         };
3140
3141         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3142                 raw_encap_data =
3143                         (const struct rte_flow_action_raw_encap *)action->conf;
3144                 res.size = raw_encap_data->size;
3145                 memcpy(res.buf, raw_encap_data->data, res.size);
3146         } else {
3147                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3148                         encap_data =
3149                                 ((const struct rte_flow_action_vxlan_encap *)
3150                                                 action->conf)->definition;
3151                 else
3152                         encap_data =
3153                                 ((const struct rte_flow_action_nvgre_encap *)
3154                                                 action->conf)->definition;
3155                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3156                                                &res.size, error))
3157                         return -rte_errno;
3158         }
3159         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3160                 return -rte_errno;
3161         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3162                 return rte_flow_error_set(error, EINVAL,
3163                                           RTE_FLOW_ERROR_TYPE_ACTION,
3164                                           NULL, "can't create L2 encap action");
3165         return 0;
3166 }
3167
3168 /**
3169  * Convert L2 decap action to DV specification.
3170  *
3171  * @param[in] dev
3172  *   Pointer to rte_eth_dev structure.
3173  * @param[in, out] dev_flow
3174  *   Pointer to the mlx5_flow.
3175  * @param[in] transfer
3176  *   Mark if the flow is E-Switch flow.
3177  * @param[out] error
3178  *   Pointer to the error structure.
3179  *
3180  * @return
3181  *   0 on success, a negative errno value otherwise and rte_errno is set.
3182  */
3183 static int
3184 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3185                                struct mlx5_flow *dev_flow,
3186                                uint8_t transfer,
3187                                struct rte_flow_error *error)
3188 {
3189         struct mlx5_flow_dv_encap_decap_resource res = {
3190                 .size = 0,
3191                 .reformat_type =
3192                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3193                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3194                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3195         };
3196
3197         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3198                 return rte_flow_error_set(error, EINVAL,
3199                                           RTE_FLOW_ERROR_TYPE_ACTION,
3200                                           NULL, "can't create L2 decap action");
3201         return 0;
3202 }
3203
3204 /**
3205  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3206  *
3207  * @param[in] dev
3208  *   Pointer to rte_eth_dev structure.
3209  * @param[in] action
3210  *   Pointer to action structure.
3211  * @param[in, out] dev_flow
3212  *   Pointer to the mlx5_flow.
3213  * @param[in] attr
3214  *   Pointer to the flow attributes.
3215  * @param[out] error
3216  *   Pointer to the error structure.
3217  *
3218  * @return
3219  *   0 on success, a negative errno value otherwise and rte_errno is set.
3220  */
3221 static int
3222 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3223                                 const struct rte_flow_action *action,
3224                                 struct mlx5_flow *dev_flow,
3225                                 const struct rte_flow_attr *attr,
3226                                 struct rte_flow_error *error)
3227 {
3228         const struct rte_flow_action_raw_encap *encap_data;
3229         struct mlx5_flow_dv_encap_decap_resource res;
3230
3231         memset(&res, 0, sizeof(res));
3232         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3233         res.size = encap_data->size;
3234         memcpy(res.buf, encap_data->data, res.size);
3235         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3236                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3237                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3238         if (attr->transfer)
3239                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3240         else
3241                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3242                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3243         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3244                 return rte_flow_error_set(error, EINVAL,
3245                                           RTE_FLOW_ERROR_TYPE_ACTION,
3246                                           NULL, "can't create encap action");
3247         return 0;
3248 }
3249
3250 /**
3251  * Create action push VLAN.
3252  *
3253  * @param[in] dev
3254  *   Pointer to rte_eth_dev structure.
3255  * @param[in] attr
3256  *   Pointer to the flow attributes.
3257  * @param[in] vlan
3258  *   Pointer to the vlan to push to the Ethernet header.
3259  * @param[in, out] dev_flow
3260  *   Pointer to the mlx5_flow.
3261  * @param[out] error
3262  *   Pointer to the error structure.
3263  *
3264  * @return
3265  *   0 on success, a negative errno value otherwise and rte_errno is set.
3266  */
3267 static int
3268 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3269                                 const struct rte_flow_attr *attr,
3270                                 const struct rte_vlan_hdr *vlan,
3271                                 struct mlx5_flow *dev_flow,
3272                                 struct rte_flow_error *error)
3273 {
3274         struct mlx5_flow_dv_push_vlan_action_resource res;
3275
3276         memset(&res, 0, sizeof(res));
3277         res.vlan_tag =
3278                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3279                                  vlan->vlan_tci);
3280         if (attr->transfer)
3281                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3282         else
3283                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3284                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3285         return flow_dv_push_vlan_action_resource_register
3286                                             (dev, &res, dev_flow, error);
3287 }
3288
3289 /**
3290  * Validate the modify-header actions.
3291  *
3292  * @param[in] action_flags
3293  *   Holds the actions detected until now.
3294  * @param[in] action
3295  *   Pointer to the modify action.
3296  * @param[out] error
3297  *   Pointer to error structure.
3298  *
3299  * @return
3300  *   0 on success, a negative errno value otherwise and rte_errno is set.
3301  */
3302 static int
3303 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3304                                    const struct rte_flow_action *action,
3305                                    struct rte_flow_error *error)
3306 {
3307         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3308                 return rte_flow_error_set(error, EINVAL,
3309                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3310                                           NULL, "action configuration not set");
3311         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3312                 return rte_flow_error_set(error, EINVAL,
3313                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3314                                           "can't have encap action before"
3315                                           " modify action");
3316         return 0;
3317 }
3318
3319 /**
3320  * Validate the modify-header MAC address actions.
3321  *
3322  * @param[in] action_flags
3323  *   Holds the actions detected until now.
3324  * @param[in] action
3325  *   Pointer to the modify action.
3326  * @param[in] item_flags
3327  *   Holds the items detected.
3328  * @param[out] error
3329  *   Pointer to error structure.
3330  *
3331  * @return
3332  *   0 on success, a negative errno value otherwise and rte_errno is set.
3333  */
3334 static int
3335 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3336                                    const struct rte_flow_action *action,
3337                                    const uint64_t item_flags,
3338                                    struct rte_flow_error *error)
3339 {
3340         int ret = 0;
3341
3342         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3343         if (!ret) {
3344                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3345                         return rte_flow_error_set(error, EINVAL,
3346                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3347                                                   NULL,
3348                                                   "no L2 item in pattern");
3349         }
3350         return ret;
3351 }
3352
3353 /**
3354  * Validate the modify-header IPv4 address actions.
3355  *
3356  * @param[in] action_flags
3357  *   Holds the actions detected until now.
3358  * @param[in] action
3359  *   Pointer to the modify action.
3360  * @param[in] item_flags
3361  *   Holds the items detected.
3362  * @param[out] error
3363  *   Pointer to error structure.
3364  *
3365  * @return
3366  *   0 on success, a negative errno value otherwise and rte_errno is set.
3367  */
3368 static int
3369 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3370                                     const struct rte_flow_action *action,
3371                                     const uint64_t item_flags,
3372                                     struct rte_flow_error *error)
3373 {
3374         int ret = 0;
3375         uint64_t layer;
3376
3377         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3378         if (!ret) {
3379                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3380                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3381                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3382                 if (!(item_flags & layer))
3383                         return rte_flow_error_set(error, EINVAL,
3384                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3385                                                   NULL,
3386                                                   "no ipv4 item in pattern");
3387         }
3388         return ret;
3389 }
3390
3391 /**
3392  * Validate the modify-header IPv6 address actions.
3393  *
3394  * @param[in] action_flags
3395  *   Holds the actions detected until now.
3396  * @param[in] action
3397  *   Pointer to the modify action.
3398  * @param[in] item_flags
3399  *   Holds the items detected.
3400  * @param[out] error
3401  *   Pointer to error structure.
3402  *
3403  * @return
3404  *   0 on success, a negative errno value otherwise and rte_errno is set.
3405  */
3406 static int
3407 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3408                                     const struct rte_flow_action *action,
3409                                     const uint64_t item_flags,
3410                                     struct rte_flow_error *error)
3411 {
3412         int ret = 0;
3413         uint64_t layer;
3414
3415         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3416         if (!ret) {
3417                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3418                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3419                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3420                 if (!(item_flags & layer))
3421                         return rte_flow_error_set(error, EINVAL,
3422                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3423                                                   NULL,
3424                                                   "no ipv6 item in pattern");
3425         }
3426         return ret;
3427 }
3428
3429 /**
3430  * Validate the modify-header TP actions.
3431  *
3432  * @param[in] action_flags
3433  *   Holds the actions detected until now.
3434  * @param[in] action
3435  *   Pointer to the modify action.
3436  * @param[in] item_flags
3437  *   Holds the items detected.
3438  * @param[out] error
3439  *   Pointer to error structure.
3440  *
3441  * @return
3442  *   0 on success, a negative errno value otherwise and rte_errno is set.
3443  */
3444 static int
3445 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3446                                   const struct rte_flow_action *action,
3447                                   const uint64_t item_flags,
3448                                   struct rte_flow_error *error)
3449 {
3450         int ret = 0;
3451         uint64_t layer;
3452
3453         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3454         if (!ret) {
3455                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3456                                  MLX5_FLOW_LAYER_INNER_L4 :
3457                                  MLX5_FLOW_LAYER_OUTER_L4;
3458                 if (!(item_flags & layer))
3459                         return rte_flow_error_set(error, EINVAL,
3460                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3461                                                   NULL, "no transport layer "
3462                                                   "in pattern");
3463         }
3464         return ret;
3465 }
3466
3467 /**
3468  * Validate the modify-header actions of increment/decrement
3469  * TCP Sequence-number.
3470  *
3471  * @param[in] action_flags
3472  *   Holds the actions detected until now.
3473  * @param[in] action
3474  *   Pointer to the modify action.
3475  * @param[in] item_flags
3476  *   Holds the items detected.
3477  * @param[out] error
3478  *   Pointer to error structure.
3479  *
3480  * @return
3481  *   0 on success, a negative errno value otherwise and rte_errno is set.
3482  */
3483 static int
3484 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3485                                        const struct rte_flow_action *action,
3486                                        const uint64_t item_flags,
3487                                        struct rte_flow_error *error)
3488 {
3489         int ret = 0;
3490         uint64_t layer;
3491
3492         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3493         if (!ret) {
3494                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3495                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3496                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3497                 if (!(item_flags & layer))
3498                         return rte_flow_error_set(error, EINVAL,
3499                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3500                                                   NULL, "no TCP item in"
3501                                                   " pattern");
3502                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3503                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3504                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3505                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3506                         return rte_flow_error_set(error, EINVAL,
3507                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3508                                                   NULL,
3509                                                   "cannot decrease and increase"
3510                                                   " TCP sequence number"
3511                                                   " at the same time");
3512         }
3513         return ret;
3514 }
3515
3516 /**
3517  * Validate the modify-header actions of increment/decrement
3518  * TCP Acknowledgment number.
3519  *
3520  * @param[in] action_flags
3521  *   Holds the actions detected until now.
3522  * @param[in] action
3523  *   Pointer to the modify action.
3524  * @param[in] item_flags
3525  *   Holds the items detected.
3526  * @param[out] error
3527  *   Pointer to error structure.
3528  *
3529  * @return
3530  *   0 on success, a negative errno value otherwise and rte_errno is set.
3531  */
3532 static int
3533 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3534                                        const struct rte_flow_action *action,
3535                                        const uint64_t item_flags,
3536                                        struct rte_flow_error *error)
3537 {
3538         int ret = 0;
3539         uint64_t layer;
3540
3541         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3542         if (!ret) {
3543                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3544                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3545                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3546                 if (!(item_flags & layer))
3547                         return rte_flow_error_set(error, EINVAL,
3548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3549                                                   NULL, "no TCP item in"
3550                                                   " pattern");
3551                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3552                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3553                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3554                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3555                         return rte_flow_error_set(error, EINVAL,
3556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3557                                                   NULL,
3558                                                   "cannot decrease and increase"
3559                                                   " TCP acknowledgment number"
3560                                                   " at the same time");
3561         }
3562         return ret;
3563 }
3564
3565 /**
3566  * Validate the modify-header TTL actions.
3567  *
3568  * @param[in] action_flags
3569  *   Holds the actions detected until now.
3570  * @param[in] action
3571  *   Pointer to the modify action.
3572  * @param[in] item_flags
3573  *   Holds the items detected.
3574  * @param[out] error
3575  *   Pointer to error structure.
3576  *
3577  * @return
3578  *   0 on success, a negative errno value otherwise and rte_errno is set.
3579  */
3580 static int
3581 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3582                                    const struct rte_flow_action *action,
3583                                    const uint64_t item_flags,
3584                                    struct rte_flow_error *error)
3585 {
3586         int ret = 0;
3587         uint64_t layer;
3588
3589         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3590         if (!ret) {
3591                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3592                                  MLX5_FLOW_LAYER_INNER_L3 :
3593                                  MLX5_FLOW_LAYER_OUTER_L3;
3594                 if (!(item_flags & layer))
3595                         return rte_flow_error_set(error, EINVAL,
3596                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3597                                                   NULL,
3598                                                   "no IP protocol in pattern");
3599         }
3600         return ret;
3601 }
3602
3603 /**
3604  * Validate jump action.
3605  *
3606  * @param[in] action
3607  *   Pointer to the jump action.
3608  * @param[in] action_flags
3609  *   Holds the actions detected until now.
3610  * @param[in] attributes
3611  *   Pointer to flow attributes
3612  * @param[in] external
3613  *   Action belongs to flow rule created by request external to PMD.
3614  * @param[out] error
3615  *   Pointer to error structure.
3616  *
3617  * @return
3618  *   0 on success, a negative errno value otherwise and rte_errno is set.
3619  */
3620 static int
3621 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3622                              uint64_t action_flags,
3623                              const struct rte_flow_attr *attributes,
3624                              bool external, struct rte_flow_error *error)
3625 {
3626         uint32_t target_group, table;
3627         int ret = 0;
3628
3629         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3630                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3631                 return rte_flow_error_set(error, EINVAL,
3632                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3633                                           "can't have 2 fate actions in"
3634                                           " same flow");
3635         if (action_flags & MLX5_FLOW_ACTION_METER)
3636                 return rte_flow_error_set(error, ENOTSUP,
3637                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3638                                           "jump with meter not support");
3639         if (!action->conf)
3640                 return rte_flow_error_set(error, EINVAL,
3641                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3642                                           NULL, "action configuration not set");
3643         target_group =
3644                 ((const struct rte_flow_action_jump *)action->conf)->group;
3645         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3646                                        true, &table, error);
3647         if (ret)
3648                 return ret;
3649         if (attributes->group == target_group)
3650                 return rte_flow_error_set(error, EINVAL,
3651                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3652                                           "target group must be other than"
3653                                           " the current flow group");
3654         return 0;
3655 }
3656
3657 /*
3658  * Validate the port_id action.
3659  *
3660  * @param[in] dev
3661  *   Pointer to rte_eth_dev structure.
3662  * @param[in] action_flags
3663  *   Bit-fields that holds the actions detected until now.
3664  * @param[in] action
3665  *   Port_id RTE action structure.
3666  * @param[in] attr
3667  *   Attributes of flow that includes this action.
3668  * @param[out] error
3669  *   Pointer to error structure.
3670  *
3671  * @return
3672  *   0 on success, a negative errno value otherwise and rte_errno is set.
3673  */
3674 static int
3675 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3676                                 uint64_t action_flags,
3677                                 const struct rte_flow_action *action,
3678                                 const struct rte_flow_attr *attr,
3679                                 struct rte_flow_error *error)
3680 {
3681         const struct rte_flow_action_port_id *port_id;
3682         struct mlx5_priv *act_priv;
3683         struct mlx5_priv *dev_priv;
3684         uint16_t port;
3685
3686         if (!attr->transfer)
3687                 return rte_flow_error_set(error, ENOTSUP,
3688                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3689                                           NULL,
3690                                           "port id action is valid in transfer"
3691                                           " mode only");
3692         if (!action || !action->conf)
3693                 return rte_flow_error_set(error, ENOTSUP,
3694                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3695                                           NULL,
3696                                           "port id action parameters must be"
3697                                           " specified");
3698         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3699                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3700                 return rte_flow_error_set(error, EINVAL,
3701                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3702                                           "can have only one fate actions in"
3703                                           " a flow");
3704         dev_priv = mlx5_dev_to_eswitch_info(dev);
3705         if (!dev_priv)
3706                 return rte_flow_error_set(error, rte_errno,
3707                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3708                                           NULL,
3709                                           "failed to obtain E-Switch info");
3710         port_id = action->conf;
3711         port = port_id->original ? dev->data->port_id : port_id->id;
3712         act_priv = mlx5_port_to_eswitch_info(port, false);
3713         if (!act_priv)
3714                 return rte_flow_error_set
3715                                 (error, rte_errno,
3716                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3717                                  "failed to obtain E-Switch port id for port");
3718         if (act_priv->domain_id != dev_priv->domain_id)
3719                 return rte_flow_error_set
3720                                 (error, EINVAL,
3721                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3722                                  "port does not belong to"
3723                                  " E-Switch being configured");
3724         return 0;
3725 }
3726
3727 /**
3728  * Get the maximum number of modify header actions.
3729  *
3730  * @param dev
3731  *   Pointer to rte_eth_dev structure.
3732  * @param flags
3733  *   Flags bits to check if root level.
3734  *
3735  * @return
3736  *   Max number of modify header actions device can support.
3737  */
3738 static inline unsigned int
3739 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3740                               uint64_t flags)
3741 {
3742         /*
3743          * There's no way to directly query the max capacity from FW.
3744          * The maximal value on root table should be assumed to be supported.
3745          */
3746         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3747                 return MLX5_MAX_MODIFY_NUM;
3748         else
3749                 return MLX5_ROOT_TBL_MODIFY_NUM;
3750 }
3751
3752 /**
3753  * Validate the meter action.
3754  *
3755  * @param[in] dev
3756  *   Pointer to rte_eth_dev structure.
3757  * @param[in] action_flags
3758  *   Bit-fields that holds the actions detected until now.
3759  * @param[in] action
3760  *   Pointer to the meter action.
3761  * @param[in] attr
3762  *   Attributes of flow that includes this action.
3763  * @param[out] error
3764  *   Pointer to error structure.
3765  *
3766  * @return
3767  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3768  */
3769 static int
3770 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3771                                 uint64_t action_flags,
3772                                 const struct rte_flow_action *action,
3773                                 const struct rte_flow_attr *attr,
3774                                 struct rte_flow_error *error)
3775 {
3776         struct mlx5_priv *priv = dev->data->dev_private;
3777         const struct rte_flow_action_meter *am = action->conf;
3778         struct mlx5_flow_meter *fm;
3779
3780         if (!am)
3781                 return rte_flow_error_set(error, EINVAL,
3782                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3783                                           "meter action conf is NULL");
3784
3785         if (action_flags & MLX5_FLOW_ACTION_METER)
3786                 return rte_flow_error_set(error, ENOTSUP,
3787                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3788                                           "meter chaining not support");
3789         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3790                 return rte_flow_error_set(error, ENOTSUP,
3791                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3792                                           "meter with jump not support");
3793         if (!priv->mtr_en)
3794                 return rte_flow_error_set(error, ENOTSUP,
3795                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3796                                           NULL,
3797                                           "meter action not supported");
3798         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3799         if (!fm)
3800                 return rte_flow_error_set(error, EINVAL,
3801                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3802                                           "Meter not found");
3803         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3804               (!fm->ingress && !attr->ingress && attr->egress) ||
3805               (!fm->egress && !attr->egress && attr->ingress))))
3806                 return rte_flow_error_set(error, EINVAL,
3807                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3808                                           "Flow attributes are either invalid "
3809                                           "or have a conflict with current "
3810                                           "meter attributes");
3811         return 0;
3812 }
3813
3814 /**
3815  * Validate the age action.
3816  *
3817  * @param[in] action_flags
3818  *   Holds the actions detected until now.
3819  * @param[in] action
3820  *   Pointer to the age action.
3821  * @param[in] dev
3822  *   Pointer to the Ethernet device structure.
3823  * @param[out] error
3824  *   Pointer to error structure.
3825  *
3826  * @return
3827  *   0 on success, a negative errno value otherwise and rte_errno is set.
3828  */
3829 static int
3830 flow_dv_validate_action_age(uint64_t action_flags,
3831                             const struct rte_flow_action *action,
3832                             struct rte_eth_dev *dev,
3833                             struct rte_flow_error *error)
3834 {
3835         struct mlx5_priv *priv = dev->data->dev_private;
3836         const struct rte_flow_action_age *age = action->conf;
3837
3838         if (!priv->config.devx || priv->counter_fallback)
3839                 return rte_flow_error_set(error, ENOTSUP,
3840                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3841                                           NULL,
3842                                           "age action not supported");
3843         if (!(action->conf))
3844                 return rte_flow_error_set(error, EINVAL,
3845                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3846                                           "configuration cannot be null");
3847         if (age->timeout >= UINT16_MAX / 2 / 10)
3848                 return rte_flow_error_set(error, ENOTSUP,
3849                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3850                                           "Max age time: 3275 seconds");
3851         if (action_flags & MLX5_FLOW_ACTION_AGE)
3852                 return rte_flow_error_set(error, EINVAL,
3853                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3854                                           "Duplicate age ctions set");
3855         return 0;
3856 }
3857
3858 /**
3859  * Validate the modify-header IPv4 DSCP actions.
3860  *
3861  * @param[in] action_flags
3862  *   Holds the actions detected until now.
3863  * @param[in] action
3864  *   Pointer to the modify action.
3865  * @param[in] item_flags
3866  *   Holds the items detected.
3867  * @param[out] error
3868  *   Pointer to error structure.
3869  *
3870  * @return
3871  *   0 on success, a negative errno value otherwise and rte_errno is set.
3872  */
3873 static int
3874 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3875                                          const struct rte_flow_action *action,
3876                                          const uint64_t item_flags,
3877                                          struct rte_flow_error *error)
3878 {
3879         int ret = 0;
3880
3881         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3882         if (!ret) {
3883                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3884                         return rte_flow_error_set(error, EINVAL,
3885                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                   NULL,
3887                                                   "no ipv4 item in pattern");
3888         }
3889         return ret;
3890 }
3891
3892 /**
3893  * Validate the modify-header IPv6 DSCP actions.
3894  *
3895  * @param[in] action_flags
3896  *   Holds the actions detected until now.
3897  * @param[in] action
3898  *   Pointer to the modify action.
3899  * @param[in] item_flags
3900  *   Holds the items detected.
3901  * @param[out] error
3902  *   Pointer to error structure.
3903  *
3904  * @return
3905  *   0 on success, a negative errno value otherwise and rte_errno is set.
3906  */
3907 static int
3908 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3909                                          const struct rte_flow_action *action,
3910                                          const uint64_t item_flags,
3911                                          struct rte_flow_error *error)
3912 {
3913         int ret = 0;
3914
3915         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3916         if (!ret) {
3917                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3918                         return rte_flow_error_set(error, EINVAL,
3919                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3920                                                   NULL,
3921                                                   "no ipv6 item in pattern");
3922         }
3923         return ret;
3924 }
3925
3926 /**
3927  * Find existing modify-header resource or create and register a new one.
3928  *
3929  * @param dev[in, out]
3930  *   Pointer to rte_eth_dev structure.
3931  * @param[in, out] resource
3932  *   Pointer to modify-header resource.
3933  * @parm[in, out] dev_flow
3934  *   Pointer to the dev_flow.
3935  * @param[out] error
3936  *   pointer to error structure.
3937  *
3938  * @return
3939  *   0 on success otherwise -errno and errno is set.
3940  */
3941 static int
3942 flow_dv_modify_hdr_resource_register
3943                         (struct rte_eth_dev *dev,
3944                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3945                          struct mlx5_flow *dev_flow,
3946                          struct rte_flow_error *error)
3947 {
3948         struct mlx5_priv *priv = dev->data->dev_private;
3949         struct mlx5_dev_ctx_shared *sh = priv->sh;
3950         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3951         struct mlx5dv_dr_domain *ns;
3952         uint32_t actions_len;
3953
3954         resource->flags = dev_flow->dv.group ? 0 :
3955                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3956         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3957                                     resource->flags))
3958                 return rte_flow_error_set(error, EOVERFLOW,
3959                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3960                                           "too many modify header items");
3961         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3962                 ns = sh->fdb_domain;
3963         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3964                 ns = sh->tx_domain;
3965         else
3966                 ns = sh->rx_domain;
3967         /* Lookup a matching resource from cache. */
3968         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3969         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3970                 if (resource->ft_type == cache_resource->ft_type &&
3971                     resource->actions_num == cache_resource->actions_num &&
3972                     resource->flags == cache_resource->flags &&
3973                     !memcmp((const void *)resource->actions,
3974                             (const void *)cache_resource->actions,
3975                             actions_len)) {
3976                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3977                                 (void *)cache_resource,
3978                                 rte_atomic32_read(&cache_resource->refcnt));
3979                         rte_atomic32_inc(&cache_resource->refcnt);
3980                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3981                         return 0;
3982                 }
3983         }
3984         /* Register new modify-header resource. */
3985         cache_resource = rte_calloc(__func__, 1,
3986                                     sizeof(*cache_resource) + actions_len, 0);
3987         if (!cache_resource)
3988                 return rte_flow_error_set(error, ENOMEM,
3989                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3990                                           "cannot allocate resource memory");
3991         *cache_resource = *resource;
3992         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3993         cache_resource->verbs_action =
3994                 mlx5_glue->dv_create_flow_action_modify_header
3995                                         (sh->ctx, cache_resource->ft_type, ns,
3996                                          cache_resource->flags, actions_len,
3997                                          (uint64_t *)cache_resource->actions);
3998         if (!cache_resource->verbs_action) {
3999                 rte_free(cache_resource);
4000                 return rte_flow_error_set(error, ENOMEM,
4001                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4002                                           NULL, "cannot create action");
4003         }
4004         rte_atomic32_init(&cache_resource->refcnt);
4005         rte_atomic32_inc(&cache_resource->refcnt);
4006         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4007         dev_flow->handle->dvh.modify_hdr = cache_resource;
4008         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4009                 (void *)cache_resource,
4010                 rte_atomic32_read(&cache_resource->refcnt));
4011         return 0;
4012 }
4013
4014 /**
4015  * Get DV flow counter by index.
4016  *
4017  * @param[in] dev
4018  *   Pointer to the Ethernet device structure.
4019  * @param[in] idx
4020  *   mlx5 flow counter index in the container.
4021  * @param[out] ppool
4022  *   mlx5 flow counter pool in the container,
4023  *
4024  * @return
4025  *   Pointer to the counter, NULL otherwise.
4026  */
4027 static struct mlx5_flow_counter *
4028 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4029                            uint32_t idx,
4030                            struct mlx5_flow_counter_pool **ppool)
4031 {
4032         struct mlx5_priv *priv = dev->data->dev_private;
4033         struct mlx5_pools_container *cont;
4034         struct mlx5_flow_counter_pool *pool;
4035         uint32_t batch = 0, age = 0;
4036
4037         idx--;
4038         age = MLX_CNT_IS_AGE(idx);
4039         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4040         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4041                 idx -= MLX5_CNT_BATCH_OFFSET;
4042                 batch = 1;
4043         }
4044         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4045         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4046         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4047         MLX5_ASSERT(pool);
4048         if (ppool)
4049                 *ppool = pool;
4050         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4051 }
4052
4053 /**
4054  * Get a pool by devx counter ID.
4055  *
4056  * @param[in] cont
4057  *   Pointer to the counter container.
4058  * @param[in] id
4059  *   The counter devx ID.
4060  *
4061  * @return
4062  *   The counter pool pointer if exists, NULL otherwise,
4063  */
4064 static struct mlx5_flow_counter_pool *
4065 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4066 {
4067         uint32_t i;
4068         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4069
4070         for (i = 0; i < n_valid; i++) {
4071                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4072                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4073                            MLX5_COUNTERS_PER_POOL;
4074
4075                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
4076                         /*
4077                          * Move the pool to the head, as counter allocate
4078                          * always gets the first pool in the container.
4079                          */
4080                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
4081                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4082                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4083                         }
4084                         return pool;
4085                 }
4086         }
4087         return NULL;
4088 }
4089
4090 /**
4091  * Allocate a new memory for the counter values wrapped by all the needed
4092  * management.
4093  *
4094  * @param[in] dev
4095  *   Pointer to the Ethernet device structure.
4096  * @param[in] raws_n
4097  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4098  *
4099  * @return
4100  *   The new memory management pointer on success, otherwise NULL and rte_errno
4101  *   is set.
4102  */
4103 static struct mlx5_counter_stats_mem_mng *
4104 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4105 {
4106         struct mlx5_priv *priv = dev->data->dev_private;
4107         struct mlx5_dev_ctx_shared *sh = priv->sh;
4108         struct mlx5_devx_mkey_attr mkey_attr;
4109         struct mlx5_counter_stats_mem_mng *mem_mng;
4110         volatile struct flow_counter_stats *raw_data;
4111         int size = (sizeof(struct flow_counter_stats) *
4112                         MLX5_COUNTERS_PER_POOL +
4113                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4114                         sizeof(struct mlx5_counter_stats_mem_mng);
4115         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4116         int i;
4117
4118         if (!mem) {
4119                 rte_errno = ENOMEM;
4120                 return NULL;
4121         }
4122         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4123         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4124         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4125                                                  IBV_ACCESS_LOCAL_WRITE);
4126         if (!mem_mng->umem) {
4127                 rte_errno = errno;
4128                 rte_free(mem);
4129                 return NULL;
4130         }
4131         mkey_attr.addr = (uintptr_t)mem;
4132         mkey_attr.size = size;
4133         mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4134         mkey_attr.pd = sh->pdn;
4135         mkey_attr.log_entity_size = 0;
4136         mkey_attr.pg_access = 0;
4137         mkey_attr.klm_array = NULL;
4138         mkey_attr.klm_num = 0;
4139         if (priv->config.hca_attr.relaxed_ordering_write &&
4140                 priv->config.hca_attr.relaxed_ordering_read  &&
4141                 !haswell_broadwell_cpu)
4142                 mkey_attr.relaxed_ordering = 1;
4143         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4144         if (!mem_mng->dm) {
4145                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4146                 rte_errno = errno;
4147                 rte_free(mem);
4148                 return NULL;
4149         }
4150         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4151         raw_data = (volatile struct flow_counter_stats *)mem;
4152         for (i = 0; i < raws_n; ++i) {
4153                 mem_mng->raws[i].mem_mng = mem_mng;
4154                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4155         }
4156         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4157         return mem_mng;
4158 }
4159
4160 /**
4161  * Resize a counter container.
4162  *
4163  * @param[in] dev
4164  *   Pointer to the Ethernet device structure.
4165  * @param[in] batch
4166  *   Whether the pool is for counter that was allocated by batch command.
4167  * @param[in] age
4168  *   Whether the pool is for Aging counter.
4169  *
4170  * @return
4171  *   0 on success, otherwise negative errno value and rte_errno is set.
4172  */
4173 static int
4174 flow_dv_container_resize(struct rte_eth_dev *dev,
4175                                 uint32_t batch, uint32_t age)
4176 {
4177         struct mlx5_priv *priv = dev->data->dev_private;
4178         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4179                                                                age);
4180         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4181         void *old_pools = cont->pools;
4182         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4183         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4184         void *pools = rte_calloc(__func__, 1, mem_size, 0);
4185
4186         if (!pools) {
4187                 rte_errno = ENOMEM;
4188                 return -ENOMEM;
4189         }
4190         if (old_pools)
4191                 memcpy(pools, old_pools, cont->n *
4192                                        sizeof(struct mlx5_flow_counter_pool *));
4193         /*
4194          * Fallback mode query the counter directly, no background query
4195          * resources are needed.
4196          */
4197         if (!priv->counter_fallback) {
4198                 int i;
4199
4200                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4201                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4202                 if (!mem_mng) {
4203                         rte_free(pools);
4204                         return -ENOMEM;
4205                 }
4206                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4207                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4208                                          mem_mng->raws +
4209                                          MLX5_CNT_CONTAINER_RESIZE +
4210                                          i, next);
4211         }
4212         rte_spinlock_lock(&cont->resize_sl);
4213         cont->n = resize;
4214         cont->mem_mng = mem_mng;
4215         cont->pools = pools;
4216         rte_spinlock_unlock(&cont->resize_sl);
4217         if (old_pools)
4218                 rte_free(old_pools);
4219         return 0;
4220 }
4221
4222 /**
4223  * Query a devx flow counter.
4224  *
4225  * @param[in] dev
4226  *   Pointer to the Ethernet device structure.
4227  * @param[in] cnt
4228  *   Index to the flow counter.
4229  * @param[out] pkts
4230  *   The statistics value of packets.
4231  * @param[out] bytes
4232  *   The statistics value of bytes.
4233  *
4234  * @return
4235  *   0 on success, otherwise a negative errno value and rte_errno is set.
4236  */
4237 static inline int
4238 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4239                      uint64_t *bytes)
4240 {
4241         struct mlx5_priv *priv = dev->data->dev_private;
4242         struct mlx5_flow_counter_pool *pool = NULL;
4243         struct mlx5_flow_counter *cnt;
4244         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4245         int offset;
4246
4247         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4248         MLX5_ASSERT(pool);
4249         if (counter < MLX5_CNT_BATCH_OFFSET) {
4250                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4251                 if (priv->counter_fallback)
4252                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4253                                         0, pkts, bytes, 0, NULL, NULL, 0);
4254         }
4255
4256         rte_spinlock_lock(&pool->sl);
4257         /*
4258          * The single counters allocation may allocate smaller ID than the
4259          * current allocated in parallel to the host reading.
4260          * In this case the new counter values must be reported as 0.
4261          */
4262         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4263                 *pkts = 0;
4264                 *bytes = 0;
4265         } else {
4266                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4267                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4268                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4269         }
4270         rte_spinlock_unlock(&pool->sl);
4271         return 0;
4272 }
4273
4274 /**
4275  * Create and initialize a new counter pool.
4276  *
4277  * @param[in] dev
4278  *   Pointer to the Ethernet device structure.
4279  * @param[out] dcs
4280  *   The devX counter handle.
4281  * @param[in] batch
4282  *   Whether the pool is for counter that was allocated by batch command.
4283  * @param[in] age
4284  *   Whether the pool is for counter that was allocated for aging.
4285  * @param[in/out] cont_cur
4286  *   Pointer to the container pointer, it will be update in pool resize.
4287  *
4288  * @return
4289  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4290  */
4291 static struct mlx5_flow_counter_pool *
4292 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4293                     uint32_t batch, uint32_t age)
4294 {
4295         struct mlx5_priv *priv = dev->data->dev_private;
4296         struct mlx5_flow_counter_pool *pool;
4297         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4298                                                                age);
4299         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4300         uint32_t size = sizeof(*pool);
4301
4302         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4303                 return NULL;
4304         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4305         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4306         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4307         pool = rte_calloc(__func__, 1, size, 0);
4308         if (!pool) {
4309                 rte_errno = ENOMEM;
4310                 return NULL;
4311         }
4312         pool->min_dcs = dcs;
4313         if (!priv->counter_fallback)
4314                 pool->raw = cont->mem_mng->raws + n_valid %
4315                                                       MLX5_CNT_CONTAINER_RESIZE;
4316         pool->raw_hw = NULL;
4317         pool->type = 0;
4318         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4319         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4320         rte_spinlock_init(&pool->sl);
4321         /*
4322          * The generation of the new allocated counters in this pool is 0, 2 in
4323          * the pool generation makes all the counters valid for allocation.
4324          * The start and end query generation protect the counters be released
4325          * between the query and update gap period will not be reallocated
4326          * without the last query finished and stats updated to the memory.
4327          */
4328         rte_atomic64_set(&pool->start_query_gen, 0x2);
4329         /*
4330          * There's no background query thread for fallback mode, set the
4331          * end_query_gen to the maximum value since no need to wait for
4332          * statistics update.
4333          */
4334         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4335                          INT64_MAX : 0x2);
4336         TAILQ_INIT(&pool->counters);
4337         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4338         pool->index = n_valid;
4339         cont->pools[n_valid] = pool;
4340         /* Pool initialization must be updated before host thread access. */
4341         rte_cio_wmb();
4342         rte_atomic16_add(&cont->n_valid, 1);
4343         return pool;
4344 }
4345
4346 /**
4347  * Update the minimum dcs-id for aged or no-aged counter pool.
4348  *
4349  * @param[in] dev
4350  *   Pointer to the Ethernet device structure.
4351  * @param[in] pool
4352  *   Current counter pool.
4353  * @param[in] batch
4354  *   Whether the pool is for counter that was allocated by batch command.
4355  * @param[in] age
4356  *   Whether the counter is for aging.
4357  */
4358 static void
4359 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4360                         struct mlx5_flow_counter_pool *pool,
4361                         uint32_t batch, uint32_t age)
4362 {
4363         struct mlx5_priv *priv = dev->data->dev_private;
4364         struct mlx5_flow_counter_pool *other;
4365         struct mlx5_pools_container *cont;
4366
4367         cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4368         other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4369         if (!other)
4370                 return;
4371         if (pool->min_dcs->id < other->min_dcs->id) {
4372                 rte_atomic64_set(&other->a64_dcs,
4373                         rte_atomic64_read(&pool->a64_dcs));
4374         } else {
4375                 rte_atomic64_set(&pool->a64_dcs,
4376                         rte_atomic64_read(&other->a64_dcs));
4377         }
4378 }
4379 /**
4380  * Prepare a new counter and/or a new counter pool.
4381  *
4382  * @param[in] dev
4383  *   Pointer to the Ethernet device structure.
4384  * @param[out] cnt_free
4385  *   Where to put the pointer of a new counter.
4386  * @param[in] batch
4387  *   Whether the pool is for counter that was allocated by batch command.
4388  * @param[in] age
4389  *   Whether the pool is for counter that was allocated for aging.
4390  *
4391  * @return
4392  *   The counter pool pointer and @p cnt_free is set on success,
4393  *   NULL otherwise and rte_errno is set.
4394  */
4395 static struct mlx5_flow_counter_pool *
4396 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4397                              struct mlx5_flow_counter **cnt_free,
4398                              uint32_t batch, uint32_t age)
4399 {
4400         struct mlx5_priv *priv = dev->data->dev_private;
4401         struct mlx5_pools_container *cont;
4402         struct mlx5_flow_counter_pool *pool;
4403         struct mlx5_devx_obj *dcs = NULL;
4404         struct mlx5_flow_counter *cnt;
4405         uint32_t i;
4406
4407         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4408         if (!batch) {
4409                 /* bulk_bitmap must be 0 for single counter allocation. */
4410                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4411                 if (!dcs)
4412                         return NULL;
4413                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4414                 if (!pool) {
4415                         pool = flow_dv_pool_create(dev, dcs, batch, age);
4416                         if (!pool) {
4417                                 mlx5_devx_cmd_destroy(dcs);
4418                                 return NULL;
4419                         }
4420                 } else if (dcs->id < pool->min_dcs->id) {
4421                         rte_atomic64_set(&pool->a64_dcs,
4422                                          (int64_t)(uintptr_t)dcs);
4423                 }
4424                 flow_dv_counter_update_min_dcs(dev,
4425                                                 pool, batch, age);
4426                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4427                 cnt = MLX5_POOL_GET_CNT(pool, i);
4428                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4429                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4430                 *cnt_free = cnt;
4431                 return pool;
4432         }
4433         /* bulk_bitmap is in 128 counters units. */
4434         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4435                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4436         if (!dcs) {
4437                 rte_errno = ENODATA;
4438                 return NULL;
4439         }
4440         pool = flow_dv_pool_create(dev, dcs, batch, age);
4441         if (!pool) {
4442                 mlx5_devx_cmd_destroy(dcs);
4443                 return NULL;
4444         }
4445         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4446                 cnt = MLX5_POOL_GET_CNT(pool, i);
4447                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4448         }
4449         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4450         return pool;
4451 }
4452
4453 /**
4454  * Search for existed shared counter.
4455  *
4456  * @param[in] dev
4457  *   Pointer to the Ethernet device structure.
4458  * @param[in] id
4459  *   The shared counter ID to search.
4460  * @param[out] ppool
4461  *   mlx5 flow counter pool in the container,
4462  *
4463  * @return
4464  *   NULL if not existed, otherwise pointer to the shared extend counter.
4465  */
4466 static struct mlx5_flow_counter_ext *
4467 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4468                               struct mlx5_flow_counter_pool **ppool)
4469 {
4470         struct mlx5_priv *priv = dev->data->dev_private;
4471         union mlx5_l3t_data data;
4472         uint32_t cnt_idx;
4473
4474         if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4475                 return NULL;
4476         cnt_idx = data.dword;
4477         /*
4478          * Shared counters don't have age info. The counter extend is after
4479          * the counter datat structure.
4480          */
4481         return (struct mlx5_flow_counter_ext *)
4482                ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4483 }
4484
4485 /**
4486  * Allocate a flow counter.
4487  *
4488  * @param[in] dev
4489  *   Pointer to the Ethernet device structure.
4490  * @param[in] shared
4491  *   Indicate if this counter is shared with other flows.
4492  * @param[in] id
4493  *   Counter identifier.
4494  * @param[in] group
4495  *   Counter flow group.
4496  * @param[in] age
4497  *   Whether the counter was allocated for aging.
4498  *
4499  * @return
4500  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4501  */
4502 static uint32_t
4503 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4504                       uint16_t group, uint32_t age)
4505 {
4506         struct mlx5_priv *priv = dev->data->dev_private;
4507         struct mlx5_flow_counter_pool *pool = NULL;
4508         struct mlx5_flow_counter *cnt_free = NULL;
4509         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4510         /*
4511          * Currently group 0 flow counter cannot be assigned to a flow if it is
4512          * not the first one in the batch counter allocation, so it is better
4513          * to allocate counters one by one for these flows in a separate
4514          * container.
4515          * A counter can be shared between different groups so need to take
4516          * shared counters from the single container.
4517          */
4518         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4519         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4520                                                                age);
4521         uint32_t cnt_idx;
4522
4523         if (!priv->config.devx) {
4524                 rte_errno = ENOTSUP;
4525                 return 0;
4526         }
4527         if (shared) {
4528                 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4529                 if (cnt_ext) {
4530                         if (cnt_ext->ref_cnt + 1 == 0) {
4531                                 rte_errno = E2BIG;
4532                                 return 0;
4533                         }
4534                         cnt_ext->ref_cnt++;
4535                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4536                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4537                                   + 1;
4538                         return cnt_idx;
4539                 }
4540         }
4541         /* Pools which has a free counters are in the start. */
4542         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4543                 /*
4544                  * The free counter reset values must be updated between the
4545                  * counter release to the counter allocation, so, at least one
4546                  * query must be done in this time. ensure it by saving the
4547                  * query generation in the release time.
4548                  * The free list is sorted according to the generation - so if
4549                  * the first one is not updated, all the others are not
4550                  * updated too.
4551                  */
4552                 cnt_free = TAILQ_FIRST(&pool->counters);
4553                 if (cnt_free && cnt_free->query_gen <
4554                     rte_atomic64_read(&pool->end_query_gen))
4555                         break;
4556                 cnt_free = NULL;
4557         }
4558         if (!cnt_free) {
4559                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4560                 if (!pool)
4561                         return 0;
4562         }
4563         if (!batch)
4564                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4565         /* Create a DV counter action only in the first time usage. */
4566         if (!cnt_free->action) {
4567                 uint16_t offset;
4568                 struct mlx5_devx_obj *dcs;
4569
4570                 if (batch) {
4571                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4572                         dcs = pool->min_dcs;
4573                 } else {
4574                         offset = 0;
4575                         dcs = cnt_ext->dcs;
4576                 }
4577                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4578                                         (dcs->obj, offset);
4579                 if (!cnt_free->action) {
4580                         rte_errno = errno;
4581                         return 0;
4582                 }
4583         }
4584         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4585                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4586         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4587         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4588         /* Update the counter reset values. */
4589         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4590                                  &cnt_free->bytes))
4591                 return 0;
4592         if (cnt_ext) {
4593                 cnt_ext->shared = shared;
4594                 cnt_ext->ref_cnt = 1;
4595                 cnt_ext->id = id;
4596                 if (shared) {
4597                         union mlx5_l3t_data data;
4598
4599                         data.dword = cnt_idx;
4600                         if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4601                                 return 0;
4602                 }
4603         }
4604         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4605                 /* Start the asynchronous batch query by the host thread. */
4606                 mlx5_set_query_alarm(priv->sh);
4607         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4608         if (TAILQ_EMPTY(&pool->counters)) {
4609                 /* Move the pool to the end of the container pool list. */
4610                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4611                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4612         }
4613         return cnt_idx;
4614 }
4615
4616 /**
4617  * Get age param from counter index.
4618  *
4619  * @param[in] dev
4620  *   Pointer to the Ethernet device structure.
4621  * @param[in] counter
4622  *   Index to the counter handler.
4623  *
4624  * @return
4625  *   The aging parameter specified for the counter index.
4626  */
4627 static struct mlx5_age_param*
4628 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4629                                 uint32_t counter)
4630 {
4631         struct mlx5_flow_counter *cnt;
4632         struct mlx5_flow_counter_pool *pool = NULL;
4633
4634         flow_dv_counter_get_by_idx(dev, counter, &pool);
4635         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4636         cnt = MLX5_POOL_GET_CNT(pool, counter);
4637         return MLX5_CNT_TO_AGE(cnt);
4638 }
4639
4640 /**
4641  * Remove a flow counter from aged counter list.
4642  *
4643  * @param[in] dev
4644  *   Pointer to the Ethernet device structure.
4645  * @param[in] counter
4646  *   Index to the counter handler.
4647  * @param[in] cnt
4648  *   Pointer to the counter handler.
4649  */
4650 static void
4651 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4652                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4653 {
4654         struct mlx5_age_info *age_info;
4655         struct mlx5_age_param *age_param;
4656         struct mlx5_priv *priv = dev->data->dev_private;
4657
4658         age_info = GET_PORT_AGE_INFO(priv);
4659         age_param = flow_dv_counter_idx_get_age(dev, counter);
4660         if (rte_atomic16_cmpset((volatile uint16_t *)
4661                         &age_param->state,
4662                         AGE_CANDIDATE, AGE_FREE)
4663                         != AGE_CANDIDATE) {
4664                 /**
4665                  * We need the lock even it is age timeout,
4666                  * since counter may still in process.
4667                  */
4668                 rte_spinlock_lock(&age_info->aged_sl);
4669                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4670                 rte_spinlock_unlock(&age_info->aged_sl);
4671         }
4672         rte_atomic16_set(&age_param->state, AGE_FREE);
4673 }
4674 /**
4675  * Release a flow counter.
4676  *
4677  * @param[in] dev
4678  *   Pointer to the Ethernet device structure.
4679  * @param[in] counter
4680  *   Index to the counter handler.
4681  */
4682 static void
4683 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4684 {
4685         struct mlx5_priv *priv = dev->data->dev_private;
4686         struct mlx5_flow_counter_pool *pool = NULL;
4687         struct mlx5_flow_counter *cnt;
4688         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4689
4690         if (!counter)
4691                 return;
4692         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4693         MLX5_ASSERT(pool);
4694         if (counter < MLX5_CNT_BATCH_OFFSET) {
4695                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4696                 if (cnt_ext) {
4697                         if (--cnt_ext->ref_cnt)
4698                                 return;
4699                         if (cnt_ext->shared)
4700                                 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4701                                                      cnt_ext->id);
4702                 }
4703         }
4704         if (IS_AGE_POOL(pool))
4705                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4706         /* Put the counter in the end - the last updated one. */
4707         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4708         /*
4709          * Counters released between query trigger and handler need
4710          * to wait the next round of query. Since the packets arrive
4711          * in the gap period will not be taken into account to the
4712          * old counter.
4713          */
4714         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4715 }
4716
4717 /**
4718  * Verify the @p attributes will be correctly understood by the NIC and store
4719  * them in the @p flow if everything is correct.
4720  *
4721  * @param[in] dev
4722  *   Pointer to dev struct.
4723  * @param[in] attributes
4724  *   Pointer to flow attributes
4725  * @param[in] external
4726  *   This flow rule is created by request external to PMD.
4727  * @param[out] error
4728  *   Pointer to error structure.
4729  *
4730  * @return
4731  *   - 0 on success and non root table.
4732  *   - 1 on success and root table.
4733  *   - a negative errno value otherwise and rte_errno is set.
4734  */
4735 static int
4736 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4737                             const struct rte_flow_attr *attributes,
4738                             bool external __rte_unused,
4739                             struct rte_flow_error *error)
4740 {
4741         struct mlx5_priv *priv = dev->data->dev_private;
4742         uint32_t priority_max = priv->config.flow_prio - 1;
4743         int ret = 0;
4744
4745 #ifndef HAVE_MLX5DV_DR
4746         if (attributes->group)
4747                 return rte_flow_error_set(error, ENOTSUP,
4748                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4749                                           NULL,
4750                                           "groups are not supported");
4751 #else
4752         uint32_t table = 0;
4753
4754         ret = mlx5_flow_group_to_table(attributes, external,
4755                                        attributes->group, !!priv->fdb_def_rule,
4756                                        &table, error);
4757         if (ret)
4758                 return ret;
4759         if (!table)
4760                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4761 #endif
4762         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4763             attributes->priority >= priority_max)
4764                 return rte_flow_error_set(error, ENOTSUP,
4765                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4766                                           NULL,
4767                                           "priority out of range");
4768         if (attributes->transfer) {
4769                 if (!priv->config.dv_esw_en)
4770                         return rte_flow_error_set
4771                                 (error, ENOTSUP,
4772                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4773                                  "E-Switch dr is not supported");
4774                 if (!(priv->representor || priv->master))
4775                         return rte_flow_error_set
4776                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4777                                  NULL, "E-Switch configuration can only be"
4778                                  " done by a master or a representor device");
4779                 if (attributes->egress)
4780                         return rte_flow_error_set
4781                                 (error, ENOTSUP,
4782                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4783                                  "egress is not supported");
4784         }
4785         if (!(attributes->egress ^ attributes->ingress))
4786                 return rte_flow_error_set(error, ENOTSUP,
4787                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4788                                           "must specify exactly one of "
4789                                           "ingress or egress");
4790         return ret;
4791 }
4792
4793 /**
4794  * Internal validation function. For validating both actions and items.
4795  *
4796  * @param[in] dev
4797  *   Pointer to the rte_eth_dev structure.
4798  * @param[in] attr
4799  *   Pointer to the flow attributes.
4800  * @param[in] items
4801  *   Pointer to the list of items.
4802  * @param[in] actions
4803  *   Pointer to the list of actions.
4804  * @param[in] external
4805  *   This flow rule is created by request external to PMD.
4806  * @param[in] hairpin
4807  *   Number of hairpin TX actions, 0 means classic flow.
4808  * @param[out] error
4809  *   Pointer to the error structure.
4810  *
4811  * @return
4812  *   0 on success, a negative errno value otherwise and rte_errno is set.
4813  */
4814 static int
4815 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4816                  const struct rte_flow_item items[],
4817                  const struct rte_flow_action actions[],
4818                  bool external, int hairpin, struct rte_flow_error *error)
4819 {
4820         int ret;
4821         uint64_t action_flags = 0;
4822         uint64_t item_flags = 0;
4823         uint64_t last_item = 0;
4824         uint8_t next_protocol = 0xff;
4825         uint16_t ether_type = 0;
4826         int actions_n = 0;
4827         uint8_t item_ipv6_proto = 0;
4828         const struct rte_flow_item *gre_item = NULL;
4829         const struct rte_flow_action_raw_decap *decap;
4830         const struct rte_flow_action_raw_encap *encap;
4831         const struct rte_flow_action_rss *rss;
4832         const struct rte_flow_item_tcp nic_tcp_mask = {
4833                 .hdr = {
4834                         .tcp_flags = 0xFF,
4835                         .src_port = RTE_BE16(UINT16_MAX),
4836                         .dst_port = RTE_BE16(UINT16_MAX),
4837                 }
4838         };
4839         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4840                 .hdr = {
4841                         .src_addr = RTE_BE32(0xffffffff),
4842                         .dst_addr = RTE_BE32(0xffffffff),
4843                         .type_of_service = 0xff,
4844                         .next_proto_id = 0xff,
4845                         .time_to_live = 0xff,
4846                 },
4847         };
4848         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4849                 .hdr = {
4850                         .src_addr =
4851                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4852                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4853                         .dst_addr =
4854                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4855                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4856                         .vtc_flow = RTE_BE32(0xffffffff),
4857                         .proto = 0xff,
4858                         .hop_limits = 0xff,
4859                 },
4860         };
4861         struct mlx5_priv *priv = dev->data->dev_private;
4862         struct mlx5_dev_config *dev_conf = &priv->config;
4863         uint16_t queue_index = 0xFFFF;
4864         const struct rte_flow_item_vlan *vlan_m = NULL;
4865         int16_t rw_act_num = 0;
4866         uint64_t is_root;
4867
4868         if (items == NULL)
4869                 return -1;
4870         ret = flow_dv_validate_attributes(dev, attr, external, error);
4871         if (ret < 0)
4872                 return ret;
4873         is_root = (uint64_t)ret;
4874         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4875                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4876                 int type = items->type;
4877
4878                 switch (type) {
4879                 case RTE_FLOW_ITEM_TYPE_VOID:
4880                         break;
4881                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4882                         ret = flow_dv_validate_item_port_id
4883                                         (dev, items, attr, item_flags, error);
4884                         if (ret < 0)
4885                                 return ret;
4886                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4887                         break;
4888                 case RTE_FLOW_ITEM_TYPE_ETH:
4889                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4890                                                           error);
4891                         if (ret < 0)
4892                                 return ret;
4893                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4894                                              MLX5_FLOW_LAYER_OUTER_L2;
4895                         if (items->mask != NULL && items->spec != NULL) {
4896                                 ether_type =
4897                                         ((const struct rte_flow_item_eth *)
4898                                          items->spec)->type;
4899                                 ether_type &=
4900                                         ((const struct rte_flow_item_eth *)
4901                                          items->mask)->type;
4902                                 ether_type = rte_be_to_cpu_16(ether_type);
4903                         } else {
4904                                 ether_type = 0;
4905                         }
4906                         break;
4907                 case RTE_FLOW_ITEM_TYPE_VLAN:
4908                         ret = flow_dv_validate_item_vlan(items, item_flags,
4909                                                          dev, error);
4910                         if (ret < 0)
4911                                 return ret;
4912                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4913                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4914                         if (items->mask != NULL && items->spec != NULL) {
4915                                 ether_type =
4916                                         ((const struct rte_flow_item_vlan *)
4917                                          items->spec)->inner_type;
4918                                 ether_type &=
4919                                         ((const struct rte_flow_item_vlan *)
4920                                          items->mask)->inner_type;
4921                                 ether_type = rte_be_to_cpu_16(ether_type);
4922                         } else {
4923                                 ether_type = 0;
4924                         }
4925                         /* Store outer VLAN mask for of_push_vlan action. */
4926                         if (!tunnel)
4927                                 vlan_m = items->mask;
4928                         break;
4929                 case RTE_FLOW_ITEM_TYPE_IPV4:
4930                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4931                                                   &item_flags, &tunnel);
4932                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4933                                                            last_item,
4934                                                            ether_type,
4935                                                            &nic_ipv4_mask,
4936                                                            error);
4937                         if (ret < 0)
4938                                 return ret;
4939                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4940                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4941                         if (items->mask != NULL &&
4942                             ((const struct rte_flow_item_ipv4 *)
4943                              items->mask)->hdr.next_proto_id) {
4944                                 next_protocol =
4945                                         ((const struct rte_flow_item_ipv4 *)
4946                                          (items->spec))->hdr.next_proto_id;
4947                                 next_protocol &=
4948                                         ((const struct rte_flow_item_ipv4 *)
4949                                          (items->mask))->hdr.next_proto_id;
4950                         } else {
4951                                 /* Reset for inner layer. */
4952                                 next_protocol = 0xff;
4953                         }
4954                         break;
4955                 case RTE_FLOW_ITEM_TYPE_IPV6:
4956                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4957                                                   &item_flags, &tunnel);
4958                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4959                                                            last_item,
4960                                                            ether_type,
4961                                                            &nic_ipv6_mask,
4962                                                            error);
4963                         if (ret < 0)
4964                                 return ret;
4965                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4966                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4967                         if (items->mask != NULL &&
4968                             ((const struct rte_flow_item_ipv6 *)
4969                              items->mask)->hdr.proto) {
4970                                 item_ipv6_proto =
4971                                         ((const struct rte_flow_item_ipv6 *)
4972                                          items->spec)->hdr.proto;
4973                                 next_protocol =
4974                                         ((const struct rte_flow_item_ipv6 *)
4975                                          items->spec)->hdr.proto;
4976                                 next_protocol &=
4977                                         ((const struct rte_flow_item_ipv6 *)
4978                                          items->mask)->hdr.proto;
4979                         } else {
4980                                 /* Reset for inner layer. */
4981                                 next_protocol = 0xff;
4982                         }
4983                         break;
4984                 case RTE_FLOW_ITEM_TYPE_TCP:
4985                         ret = mlx5_flow_validate_item_tcp
4986                                                 (items, item_flags,
4987                                                  next_protocol,
4988                                                  &nic_tcp_mask,
4989                                                  error);
4990                         if (ret < 0)
4991                                 return ret;
4992                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4993                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4994                         break;
4995                 case RTE_FLOW_ITEM_TYPE_UDP:
4996                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4997                                                           next_protocol,
4998                                                           error);
4999                         if (ret < 0)
5000                                 return ret;
5001                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5002                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5003                         break;
5004                 case RTE_FLOW_ITEM_TYPE_GRE:
5005                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5006                                                           next_protocol, error);
5007                         if (ret < 0)
5008                                 return ret;
5009                         gre_item = items;
5010                         last_item = MLX5_FLOW_LAYER_GRE;
5011                         break;
5012                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5013                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5014                                                             next_protocol,
5015                                                             error);
5016                         if (ret < 0)
5017                                 return ret;
5018                         last_item = MLX5_FLOW_LAYER_NVGRE;
5019                         break;
5020                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5021                         ret = mlx5_flow_validate_item_gre_key
5022                                 (items, item_flags, gre_item, error);
5023                         if (ret < 0)
5024                                 return ret;
5025                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5026                         break;
5027                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5028                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5029                                                             error);
5030                         if (ret < 0)
5031                                 return ret;
5032                         last_item = MLX5_FLOW_LAYER_VXLAN;
5033                         break;
5034                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5035                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5036                                                                 item_flags, dev,
5037                                                                 error);
5038                         if (ret < 0)
5039                                 return ret;
5040                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5041                         break;
5042                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5043                         ret = mlx5_flow_validate_item_geneve(items,
5044                                                              item_flags, dev,
5045                                                              error);
5046                         if (ret < 0)
5047                                 return ret;
5048                         last_item = MLX5_FLOW_LAYER_GENEVE;
5049                         break;
5050                 case RTE_FLOW_ITEM_TYPE_MPLS:
5051                         ret = mlx5_flow_validate_item_mpls(dev, items,
5052                                                            item_flags,
5053                                                            last_item, error);
5054                         if (ret < 0)
5055                                 return ret;
5056                         last_item = MLX5_FLOW_LAYER_MPLS;
5057                         break;
5058
5059                 case RTE_FLOW_ITEM_TYPE_MARK:
5060                         ret = flow_dv_validate_item_mark(dev, items, attr,
5061                                                          error);
5062                         if (ret < 0)
5063                                 return ret;
5064                         last_item = MLX5_FLOW_ITEM_MARK;
5065                         break;
5066                 case RTE_FLOW_ITEM_TYPE_META:
5067                         ret = flow_dv_validate_item_meta(dev, items, attr,
5068                                                          error);
5069                         if (ret < 0)
5070                                 return ret;
5071                         last_item = MLX5_FLOW_ITEM_METADATA;
5072                         break;
5073                 case RTE_FLOW_ITEM_TYPE_ICMP:
5074                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5075                                                            next_protocol,
5076                                                            error);
5077                         if (ret < 0)
5078                                 return ret;
5079                         last_item = MLX5_FLOW_LAYER_ICMP;
5080                         break;
5081                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5082                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5083                                                             next_protocol,
5084                                                             error);
5085                         if (ret < 0)
5086                                 return ret;
5087                         item_ipv6_proto = IPPROTO_ICMPV6;
5088                         last_item = MLX5_FLOW_LAYER_ICMP6;
5089                         break;
5090                 case RTE_FLOW_ITEM_TYPE_TAG:
5091                         ret = flow_dv_validate_item_tag(dev, items,
5092                                                         attr, error);
5093                         if (ret < 0)
5094                                 return ret;
5095                         last_item = MLX5_FLOW_ITEM_TAG;
5096                         break;
5097                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5098                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5099                         break;
5100                 case RTE_FLOW_ITEM_TYPE_GTP:
5101                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5102                                                         error);
5103                         if (ret < 0)
5104                                 return ret;
5105                         last_item = MLX5_FLOW_LAYER_GTP;
5106                         break;
5107                 default:
5108                         return rte_flow_error_set(error, ENOTSUP,
5109                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5110                                                   NULL, "item not supported");
5111                 }
5112                 item_flags |= last_item;
5113         }
5114         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5115                 int type = actions->type;
5116                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5117                         return rte_flow_error_set(error, ENOTSUP,
5118                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5119                                                   actions, "too many actions");
5120                 switch (type) {
5121                 case RTE_FLOW_ACTION_TYPE_VOID:
5122                         break;
5123                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5124                         ret = flow_dv_validate_action_port_id(dev,
5125                                                               action_flags,
5126                                                               actions,
5127                                                               attr,
5128                                                               error);
5129                         if (ret)
5130                                 return ret;
5131                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5132                         ++actions_n;
5133                         break;
5134                 case RTE_FLOW_ACTION_TYPE_FLAG:
5135                         ret = flow_dv_validate_action_flag(dev, action_flags,
5136                                                            attr, error);
5137                         if (ret < 0)
5138                                 return ret;
5139                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5140                                 /* Count all modify-header actions as one. */
5141                                 if (!(action_flags &
5142                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5143                                         ++actions_n;
5144                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5145                                                 MLX5_FLOW_ACTION_MARK_EXT;
5146                         } else {
5147                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5148                                 ++actions_n;
5149                         }
5150                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5151                         break;
5152                 case RTE_FLOW_ACTION_TYPE_MARK:
5153                         ret = flow_dv_validate_action_mark(dev, actions,
5154                                                            action_flags,
5155                                                            attr, error);
5156                         if (ret < 0)
5157                                 return ret;
5158                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5159                                 /* Count all modify-header actions as one. */
5160                                 if (!(action_flags &
5161                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5162                                         ++actions_n;
5163                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5164                                                 MLX5_FLOW_ACTION_MARK_EXT;
5165                         } else {
5166                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5167                                 ++actions_n;
5168                         }
5169                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5170                         break;
5171                 case RTE_FLOW_ACTION_TYPE_SET_META:
5172                         ret = flow_dv_validate_action_set_meta(dev, actions,
5173                                                                action_flags,
5174                                                                attr, error);
5175                         if (ret < 0)
5176                                 return ret;
5177                         /* Count all modify-header actions as one action. */
5178                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5179                                 ++actions_n;
5180                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5181                         rw_act_num += MLX5_ACT_NUM_SET_META;
5182                         break;
5183                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5184                         ret = flow_dv_validate_action_set_tag(dev, actions,
5185                                                               action_flags,
5186                                                               attr, error);
5187                         if (ret < 0)
5188                                 return ret;
5189                         /* Count all modify-header actions as one action. */
5190                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5191                                 ++actions_n;
5192                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5193                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5194                         break;
5195                 case RTE_FLOW_ACTION_TYPE_DROP:
5196                         ret = mlx5_flow_validate_action_drop(action_flags,
5197                                                              attr, error);
5198                         if (ret < 0)
5199                                 return ret;
5200                         action_flags |= MLX5_FLOW_ACTION_DROP;
5201                         ++actions_n;
5202                         break;
5203                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5204                         ret = mlx5_flow_validate_action_queue(actions,
5205                                                               action_flags, dev,
5206                                                               attr, error);
5207                         if (ret < 0)
5208                                 return ret;
5209                         queue_index = ((const struct rte_flow_action_queue *)
5210                                                         (actions->conf))->index;
5211                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5212                         ++actions_n;
5213                         break;
5214                 case RTE_FLOW_ACTION_TYPE_RSS:
5215                         rss = actions->conf;
5216                         ret = mlx5_flow_validate_action_rss(actions,
5217                                                             action_flags, dev,
5218                                                             attr, item_flags,
5219                                                             error);
5220                         if (ret < 0)
5221                                 return ret;
5222                         if (rss != NULL && rss->queue_num)
5223                                 queue_index = rss->queue[0];
5224                         action_flags |= MLX5_FLOW_ACTION_RSS;
5225                         ++actions_n;
5226                         break;
5227                 case RTE_FLOW_ACTION_TYPE_COUNT:
5228                         ret = flow_dv_validate_action_count(dev, error);
5229                         if (ret < 0)
5230                                 return ret;
5231                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5232                         ++actions_n;
5233                         break;
5234                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5235                         if (flow_dv_validate_action_pop_vlan(dev,
5236                                                              action_flags,
5237                                                              actions,
5238                                                              item_flags, attr,
5239                                                              error))
5240                                 return -rte_errno;
5241                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5242                         ++actions_n;
5243                         break;
5244                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5245                         ret = flow_dv_validate_action_push_vlan(dev,
5246                                                                 action_flags,
5247                                                                 vlan_m,
5248                                                                 actions, attr,
5249                                                                 error);
5250                         if (ret < 0)
5251                                 return ret;
5252                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5253                         ++actions_n;
5254                         break;
5255                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5256                         ret = flow_dv_validate_action_set_vlan_pcp
5257                                                 (action_flags, actions, error);
5258                         if (ret < 0)
5259                                 return ret;
5260                         /* Count PCP with push_vlan command. */
5261                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5262                         break;
5263                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5264                         ret = flow_dv_validate_action_set_vlan_vid
5265                                                 (item_flags, action_flags,
5266                                                  actions, error);
5267                         if (ret < 0)
5268                                 return ret;
5269                         /* Count VID with push_vlan command. */
5270                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5271                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5272                         break;
5273                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5274                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5275                         ret = flow_dv_validate_action_l2_encap(dev,
5276                                                                action_flags,
5277                                                                actions, attr,
5278                                                                error);
5279                         if (ret < 0)
5280                                 return ret;
5281                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5282                         ++actions_n;
5283                         break;
5284                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5285                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5286                         ret = flow_dv_validate_action_decap(dev, action_flags,
5287                                                             attr, error);
5288                         if (ret < 0)
5289                                 return ret;
5290                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5291                         ++actions_n;
5292                         break;
5293                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5294                         ret = flow_dv_validate_action_raw_encap_decap
5295                                 (dev, NULL, actions->conf, attr, &action_flags,
5296                                  &actions_n, error);
5297                         if (ret < 0)
5298                                 return ret;
5299                         break;
5300                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5301                         decap = actions->conf;
5302                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5303                                 ;
5304                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5305                                 encap = NULL;
5306                                 actions--;
5307                         } else {
5308                                 encap = actions->conf;
5309                         }
5310                         ret = flow_dv_validate_action_raw_encap_decap
5311                                            (dev,
5312                                             decap ? decap : &empty_decap, encap,
5313                                             attr, &action_flags, &actions_n,
5314                                             error);
5315                         if (ret < 0)
5316                                 return ret;
5317                         break;
5318                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5319                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5320                         ret = flow_dv_validate_action_modify_mac(action_flags,
5321                                                                  actions,
5322                                                                  item_flags,
5323                                                                  error);
5324                         if (ret < 0)
5325                                 return ret;
5326                         /* Count all modify-header actions as one action. */
5327                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5328                                 ++actions_n;
5329                         action_flags |= actions->type ==
5330                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5331                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5332                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5333                         /*
5334                          * Even if the source and destination MAC addresses have
5335                          * overlap in the header with 4B alignment, the convert
5336                          * function will handle them separately and 4 SW actions
5337                          * will be created. And 2 actions will be added each
5338                          * time no matter how many bytes of address will be set.
5339                          */
5340                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5341                         break;
5342                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5343                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5344                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5345                                                                   actions,
5346                                                                   item_flags,
5347                                                                   error);
5348                         if (ret < 0)
5349                                 return ret;
5350                         /* Count all modify-header actions as one action. */
5351                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5352                                 ++actions_n;
5353                         action_flags |= actions->type ==
5354                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5355                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5356                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5357                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5358                         break;
5359                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5360                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5361                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5362                                                                   actions,
5363                                                                   item_flags,
5364                                                                   error);
5365                         if (ret < 0)
5366                                 return ret;
5367                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5368                                 return rte_flow_error_set(error, ENOTSUP,
5369                                         RTE_FLOW_ERROR_TYPE_ACTION,
5370                                         actions,
5371                                         "Can't change header "
5372                                         "with ICMPv6 proto");
5373                         /* Count all modify-header actions as one action. */
5374                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5375                                 ++actions_n;
5376                         action_flags |= actions->type ==
5377                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5378                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5379                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5380                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5381                         break;
5382                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5383                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5384                         ret = flow_dv_validate_action_modify_tp(action_flags,
5385                                                                 actions,
5386                                                                 item_flags,
5387                                                                 error);
5388                         if (ret < 0)
5389                                 return ret;
5390                         /* Count all modify-header actions as one action. */
5391                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5392                                 ++actions_n;
5393                         action_flags |= actions->type ==
5394                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5395                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5396                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5397                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5398                         break;
5399                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5400                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5401                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5402                                                                  actions,
5403                                                                  item_flags,
5404                                                                  error);
5405                         if (ret < 0)
5406                                 return ret;
5407                         /* Count all modify-header actions as one action. */
5408                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5409                                 ++actions_n;
5410                         action_flags |= actions->type ==
5411                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5412                                                 MLX5_FLOW_ACTION_SET_TTL :
5413                                                 MLX5_FLOW_ACTION_DEC_TTL;
5414                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5415                         break;
5416                 case RTE_FLOW_ACTION_TYPE_JUMP:
5417                         ret = flow_dv_validate_action_jump(actions,
5418                                                            action_flags,
5419                                                            attr, external,
5420                                                            error);
5421                         if (ret)
5422                                 return ret;
5423                         ++actions_n;
5424                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5425                         break;
5426                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5427                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5428                         ret = flow_dv_validate_action_modify_tcp_seq
5429                                                                 (action_flags,
5430                                                                  actions,
5431                                                                  item_flags,
5432                                                                  error);
5433                         if (ret < 0)
5434                                 return ret;
5435                         /* Count all modify-header actions as one action. */
5436                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5437                                 ++actions_n;
5438                         action_flags |= actions->type ==
5439                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5440                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5441                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5442                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5443                         break;
5444                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5445                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5446                         ret = flow_dv_validate_action_modify_tcp_ack
5447                                                                 (action_flags,
5448                                                                  actions,
5449                                                                  item_flags,
5450                                                                  error);
5451                         if (ret < 0)
5452                                 return ret;
5453                         /* Count all modify-header actions as one action. */
5454                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5455                                 ++actions_n;
5456                         action_flags |= actions->type ==
5457                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5458                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5459                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5460                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5461                         break;
5462                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5463                         break;
5464                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5465                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5466                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5467                         break;
5468                 case RTE_FLOW_ACTION_TYPE_METER:
5469                         ret = mlx5_flow_validate_action_meter(dev,
5470                                                               action_flags,
5471                                                               actions, attr,
5472                                                               error);
5473                         if (ret < 0)
5474                                 return ret;
5475                         action_flags |= MLX5_FLOW_ACTION_METER;
5476                         ++actions_n;
5477                         /* Meter action will add one more TAG action. */
5478                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5479                         break;
5480                 case RTE_FLOW_ACTION_TYPE_AGE:
5481                         ret = flow_dv_validate_action_age(action_flags,
5482                                                           actions, dev,
5483                                                           error);
5484                         if (ret < 0)
5485                                 return ret;
5486                         action_flags |= MLX5_FLOW_ACTION_AGE;
5487                         ++actions_n;
5488                         break;
5489                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5490                         ret = flow_dv_validate_action_modify_ipv4_dscp
5491                                                          (action_flags,
5492                                                           actions,
5493                                                           item_flags,
5494                                                           error);
5495                         if (ret < 0)
5496                                 return ret;
5497                         /* Count all modify-header actions as one action. */
5498                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5499                                 ++actions_n;
5500                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5501                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5502                         break;
5503                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5504                         ret = flow_dv_validate_action_modify_ipv6_dscp
5505                                                                 (action_flags,
5506                                                                  actions,
5507                                                                  item_flags,
5508                                                                  error);
5509                         if (ret < 0)
5510                                 return ret;
5511                         /* Count all modify-header actions as one action. */
5512                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5513                                 ++actions_n;
5514                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5515                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5516                         break;
5517                 default:
5518                         return rte_flow_error_set(error, ENOTSUP,
5519                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5520                                                   actions,
5521                                                   "action not supported");
5522                 }
5523         }
5524         /*
5525          * Validate the drop action mutual exclusion with other actions.
5526          * Drop action is mutually-exclusive with any other action, except for
5527          * Count action.
5528          */
5529         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5530             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5531                 return rte_flow_error_set(error, EINVAL,
5532                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5533                                           "Drop action is mutually-exclusive "
5534                                           "with any other action, except for "
5535                                           "Count action");
5536         /* Eswitch has few restrictions on using items and actions */
5537         if (attr->transfer) {
5538                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5539                     action_flags & MLX5_FLOW_ACTION_FLAG)
5540                         return rte_flow_error_set(error, ENOTSUP,
5541                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5542                                                   NULL,
5543                                                   "unsupported action FLAG");
5544                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5545                     action_flags & MLX5_FLOW_ACTION_MARK)
5546                         return rte_flow_error_set(error, ENOTSUP,
5547                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5548                                                   NULL,
5549                                                   "unsupported action MARK");
5550                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5551                         return rte_flow_error_set(error, ENOTSUP,
5552                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5553                                                   NULL,
5554                                                   "unsupported action QUEUE");
5555                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5556                         return rte_flow_error_set(error, ENOTSUP,
5557                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5558                                                   NULL,
5559                                                   "unsupported action RSS");
5560                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5561                         return rte_flow_error_set(error, EINVAL,
5562                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5563                                                   actions,
5564                                                   "no fate action is found");
5565         } else {
5566                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5567                         return rte_flow_error_set(error, EINVAL,
5568                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5569                                                   actions,
5570                                                   "no fate action is found");
5571         }
5572         /* Continue validation for Xcap actions.*/
5573         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5574             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5575                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5576                     MLX5_FLOW_XCAP_ACTIONS)
5577                         return rte_flow_error_set(error, ENOTSUP,
5578                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5579                                                   NULL, "encap and decap "
5580                                                   "combination aren't supported");
5581                 if (!attr->transfer && attr->ingress && (action_flags &
5582                                                         MLX5_FLOW_ACTION_ENCAP))
5583                         return rte_flow_error_set(error, ENOTSUP,
5584                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5585                                                   NULL, "encap is not supported"
5586                                                   " for ingress traffic");
5587         }
5588         /* Hairpin flow will add one more TAG action. */
5589         if (hairpin > 0)
5590                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5591         /* extra metadata enabled: one more TAG action will be add. */
5592         if (dev_conf->dv_flow_en &&
5593             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5594             mlx5_flow_ext_mreg_supported(dev))
5595                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5596         if ((uint32_t)rw_act_num >
5597                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5598                 return rte_flow_error_set(error, ENOTSUP,
5599                                           RTE_FLOW_ERROR_TYPE_ACTION,
5600                                           NULL, "too many header modify"
5601                                           " actions to support");
5602         }
5603         return 0;
5604 }
5605
5606 /**
5607  * Internal preparation function. Allocates the DV flow size,
5608  * this size is constant.
5609  *
5610  * @param[in] dev
5611  *   Pointer to the rte_eth_dev structure.
5612  * @param[in] attr
5613  *   Pointer to the flow attributes.
5614  * @param[in] items
5615  *   Pointer to the list of items.
5616  * @param[in] actions
5617  *   Pointer to the list of actions.
5618  * @param[out] error
5619  *   Pointer to the error structure.
5620  *
5621  * @return
5622  *   Pointer to mlx5_flow object on success,
5623  *   otherwise NULL and rte_errno is set.
5624  */
5625 static struct mlx5_flow *
5626 flow_dv_prepare(struct rte_eth_dev *dev,
5627                 const struct rte_flow_attr *attr __rte_unused,
5628                 const struct rte_flow_item items[] __rte_unused,
5629                 const struct rte_flow_action actions[] __rte_unused,
5630                 struct rte_flow_error *error)
5631 {
5632         uint32_t handle_idx = 0;
5633         struct mlx5_flow *dev_flow;
5634         struct mlx5_flow_handle *dev_handle;
5635         struct mlx5_priv *priv = dev->data->dev_private;
5636
5637         /* In case of corrupting the memory. */
5638         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5639                 rte_flow_error_set(error, ENOSPC,
5640                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5641                                    "not free temporary device flow");
5642                 return NULL;
5643         }
5644         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5645                                    &handle_idx);
5646         if (!dev_handle) {
5647                 rte_flow_error_set(error, ENOMEM,
5648                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5649                                    "not enough memory to create flow handle");
5650                 return NULL;
5651         }
5652         /* No multi-thread supporting. */
5653         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5654         dev_flow->handle = dev_handle;
5655         dev_flow->handle_idx = handle_idx;
5656         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5657         /*
5658          * The matching value needs to be cleared to 0 before using. In the
5659          * past, it will be automatically cleared when using rte_*alloc
5660          * API. The time consumption will be almost the same as before.
5661          */
5662         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5663         dev_flow->ingress = attr->ingress;
5664         dev_flow->dv.transfer = attr->transfer;
5665         return dev_flow;
5666 }
5667
5668 #ifdef RTE_LIBRTE_MLX5_DEBUG
5669 /**
5670  * Sanity check for match mask and value. Similar to check_valid_spec() in
5671  * kernel driver. If unmasked bit is present in value, it returns failure.
5672  *
5673  * @param match_mask
5674  *   pointer to match mask buffer.
5675  * @param match_value
5676  *   pointer to match value buffer.
5677  *
5678  * @return
5679  *   0 if valid, -EINVAL otherwise.
5680  */
5681 static int
5682 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5683 {
5684         uint8_t *m = match_mask;
5685         uint8_t *v = match_value;
5686         unsigned int i;
5687
5688         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5689                 if (v[i] & ~m[i]) {
5690                         DRV_LOG(ERR,
5691                                 "match_value differs from match_criteria"
5692                                 " %p[%u] != %p[%u]",
5693                                 match_value, i, match_mask, i);
5694                         return -EINVAL;
5695                 }
5696         }
5697         return 0;
5698 }
5699 #endif
5700
5701 /**
5702  * Add match of ip_version.
5703  *
5704  * @param[in] group
5705  *   Flow group.
5706  * @param[in] headers_v
5707  *   Values header pointer.
5708  * @param[in] headers_m
5709  *   Masks header pointer.
5710  * @param[in] ip_version
5711  *   The IP version to set.
5712  */
5713 static inline void
5714 flow_dv_set_match_ip_version(uint32_t group,
5715                              void *headers_v,
5716                              void *headers_m,
5717                              uint8_t ip_version)
5718 {
5719         if (group == 0)
5720                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5721         else
5722                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5723                          ip_version);
5724         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5725         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5726         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5727 }
5728
5729 /**
5730  * Add Ethernet item to matcher and to the value.
5731  *
5732  * @param[in, out] matcher
5733  *   Flow matcher.
5734  * @param[in, out] key
5735  *   Flow matcher value.
5736  * @param[in] item
5737  *   Flow pattern to translate.
5738  * @param[in] inner
5739  *   Item is inner pattern.
5740  */
5741 static void
5742 flow_dv_translate_item_eth(void *matcher, void *key,
5743                            const struct rte_flow_item *item, int inner,
5744                            uint32_t group)
5745 {
5746         const struct rte_flow_item_eth *eth_m = item->mask;
5747         const struct rte_flow_item_eth *eth_v = item->spec;
5748         const struct rte_flow_item_eth nic_mask = {
5749                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5750                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5751                 .type = RTE_BE16(0xffff),
5752         };
5753         void *headers_m;
5754         void *headers_v;
5755         char *l24_v;
5756         unsigned int i;
5757
5758         if (!eth_v)
5759                 return;
5760         if (!eth_m)
5761                 eth_m = &nic_mask;
5762         if (inner) {
5763                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5764                                          inner_headers);
5765                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5766         } else {
5767                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5768                                          outer_headers);
5769                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5770         }
5771         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5772                &eth_m->dst, sizeof(eth_m->dst));
5773         /* The value must be in the range of the mask. */
5774         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5775         for (i = 0; i < sizeof(eth_m->dst); ++i)
5776                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5777         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5778                &eth_m->src, sizeof(eth_m->src));
5779         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5780         /* The value must be in the range of the mask. */
5781         for (i = 0; i < sizeof(eth_m->dst); ++i)
5782                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5783         if (eth_v->type) {
5784                 /* When ethertype is present set mask for tagged VLAN. */
5785                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5786                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5787                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5788                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5789                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5790                                  1);
5791                         /* Return here to avoid setting match on ethertype. */
5792                         return;
5793                 }
5794         }
5795         /*
5796          * HW supports match on one Ethertype, the Ethertype following the last
5797          * VLAN tag of the packet (see PRM).
5798          * Set match on ethertype only if ETH header is not followed by VLAN.
5799          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5800          * ethertype, and use ip_version field instead.
5801          */
5802         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5803             eth_m->type == 0xFFFF) {
5804                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5805         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5806                    eth_m->type == 0xFFFF) {
5807                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5808         } else {
5809                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5810                          rte_be_to_cpu_16(eth_m->type));
5811                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5812                                      ethertype);
5813                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5814         }
5815 }
5816
5817 /**
5818  * Add VLAN item to matcher and to the value.
5819  *
5820  * @param[in, out] dev_flow
5821  *   Flow descriptor.
5822  * @param[in, out] matcher
5823  *   Flow matcher.
5824  * @param[in, out] key
5825  *   Flow matcher value.
5826  * @param[in] item
5827  *   Flow pattern to translate.
5828  * @param[in] inner
5829  *   Item is inner pattern.
5830  */
5831 static void
5832 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5833                             void *matcher, void *key,
5834                             const struct rte_flow_item *item,
5835                             int inner, uint32_t group)
5836 {
5837         const struct rte_flow_item_vlan *vlan_m = item->mask;
5838         const struct rte_flow_item_vlan *vlan_v = item->spec;
5839         void *headers_m;
5840         void *headers_v;
5841         uint16_t tci_m;
5842         uint16_t tci_v;
5843
5844         if (inner) {
5845                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5846                                          inner_headers);
5847                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5848         } else {
5849                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5850                                          outer_headers);
5851                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5852                 /*
5853                  * This is workaround, masks are not supported,
5854                  * and pre-validated.
5855                  */
5856                 if (vlan_v)
5857                         dev_flow->handle->vf_vlan.tag =
5858                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5859         }
5860         /*
5861          * When VLAN item exists in flow, mark packet as tagged,
5862          * even if TCI is not specified.
5863          */
5864         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5865         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5866         if (!vlan_v)
5867                 return;
5868         if (!vlan_m)
5869                 vlan_m = &rte_flow_item_vlan_mask;
5870         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5871         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5872         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5873         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5874         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5875         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5876         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5877         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5878         /*
5879          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5880          * ethertype, and use ip_version field instead.
5881          */
5882         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5883             vlan_m->inner_type == 0xFFFF) {
5884                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5885         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5886                    vlan_m->inner_type == 0xFFFF) {
5887                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5888         } else {
5889                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5890                          rte_be_to_cpu_16(vlan_m->inner_type));
5891                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5892                          rte_be_to_cpu_16(vlan_m->inner_type &
5893                                           vlan_v->inner_type));
5894         }
5895 }
5896
5897 /**
5898  * Add IPV4 item to matcher and to the value.
5899  *
5900  * @param[in, out] matcher
5901  *   Flow matcher.
5902  * @param[in, out] key
5903  *   Flow matcher value.
5904  * @param[in] item
5905  *   Flow pattern to translate.
5906  * @param[in] item_flags
5907  *   Bit-fields that holds the items detected until now.
5908  * @param[in] inner
5909  *   Item is inner pattern.
5910  * @param[in] group
5911  *   The group to insert the rule.
5912  */
5913 static void
5914 flow_dv_translate_item_ipv4(void *matcher, void *key,
5915                             const struct rte_flow_item *item,
5916                             const uint64_t item_flags,
5917                             int inner, uint32_t group)
5918 {
5919         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5920         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5921         const struct rte_flow_item_ipv4 nic_mask = {
5922                 .hdr = {
5923                         .src_addr = RTE_BE32(0xffffffff),
5924                         .dst_addr = RTE_BE32(0xffffffff),
5925                         .type_of_service = 0xff,
5926                         .next_proto_id = 0xff,
5927                         .time_to_live = 0xff,
5928                 },
5929         };
5930         void *headers_m;
5931         void *headers_v;
5932         char *l24_m;
5933         char *l24_v;
5934         uint8_t tos;
5935
5936         if (inner) {
5937                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5938                                          inner_headers);
5939                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5940         } else {
5941                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5942                                          outer_headers);
5943                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5944         }
5945         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5946         /*
5947          * On outer header (which must contains L2), or inner header with L2,
5948          * set cvlan_tag mask bit to mark this packet as untagged.
5949          * This should be done even if item->spec is empty.
5950          */
5951         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5952                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5953         if (!ipv4_v)
5954                 return;
5955         if (!ipv4_m)
5956                 ipv4_m = &nic_mask;
5957         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5958                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5959         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5960                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5961         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5962         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5963         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5964                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5965         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5966                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5967         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5968         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5969         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5970         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5971                  ipv4_m->hdr.type_of_service);
5972         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5973         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5974                  ipv4_m->hdr.type_of_service >> 2);
5975         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5976         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5977                  ipv4_m->hdr.next_proto_id);
5978         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5979                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5980         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5981                  ipv4_m->hdr.time_to_live);
5982         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5983                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5984 }
5985
5986 /**
5987  * Add IPV6 item to matcher and to the value.
5988  *
5989  * @param[in, out] matcher
5990  *   Flow matcher.
5991  * @param[in, out] key
5992  *   Flow matcher value.
5993  * @param[in] item
5994  *   Flow pattern to translate.
5995  * @param[in] item_flags
5996  *   Bit-fields that holds the items detected until now.
5997  * @param[in] inner
5998  *   Item is inner pattern.
5999  * @param[in] group
6000  *   The group to insert the rule.
6001  */
6002 static void
6003 flow_dv_translate_item_ipv6(void *matcher, void *key,
6004                             const struct rte_flow_item *item,
6005                             const uint64_t item_flags,
6006                             int inner, uint32_t group)
6007 {
6008         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6009         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6010         const struct rte_flow_item_ipv6 nic_mask = {
6011                 .hdr = {
6012                         .src_addr =
6013                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6014                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6015                         .dst_addr =
6016                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6017                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6018                         .vtc_flow = RTE_BE32(0xffffffff),
6019                         .proto = 0xff,
6020                         .hop_limits = 0xff,
6021                 },
6022         };
6023         void *headers_m;
6024         void *headers_v;
6025         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6026         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6027         char *l24_m;
6028         char *l24_v;
6029         uint32_t vtc_m;
6030         uint32_t vtc_v;
6031         int i;
6032         int size;
6033
6034         if (inner) {
6035                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6036                                          inner_headers);
6037                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6038         } else {
6039                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6040                                          outer_headers);
6041                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6042         }
6043         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6044         /*
6045          * On outer header (which must contains L2), or inner header with L2,
6046          * set cvlan_tag mask bit to mark this packet as untagged.
6047          * This should be done even if item->spec is empty.
6048          */
6049         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6050                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6051         if (!ipv6_v)
6052                 return;
6053         if (!ipv6_m)
6054                 ipv6_m = &nic_mask;
6055         size = sizeof(ipv6_m->hdr.dst_addr);
6056         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6057                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6058         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6059                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6060         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6061         for (i = 0; i < size; ++i)
6062                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6063         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6064                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6065         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6066                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6067         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6068         for (i = 0; i < size; ++i)
6069                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6070         /* TOS. */
6071         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6072         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6073         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6074         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6075         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6076         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6077         /* Label. */
6078         if (inner) {
6079                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6080                          vtc_m);
6081                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6082                          vtc_v);
6083         } else {
6084                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6085                          vtc_m);
6086                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6087                          vtc_v);
6088         }
6089         /* Protocol. */
6090         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6091                  ipv6_m->hdr.proto);
6092         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6093                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6094         /* Hop limit. */
6095         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6096                  ipv6_m->hdr.hop_limits);
6097         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6098                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6099 }
6100
6101 /**
6102  * Add TCP item to matcher and to the value.
6103  *
6104  * @param[in, out] matcher
6105  *   Flow matcher.
6106  * @param[in, out] key
6107  *   Flow matcher value.
6108  * @param[in] item
6109  *   Flow pattern to translate.
6110  * @param[in] inner
6111  *   Item is inner pattern.
6112  */
6113 static void
6114 flow_dv_translate_item_tcp(void *matcher, void *key,
6115                            const struct rte_flow_item *item,
6116                            int inner)
6117 {
6118         const struct rte_flow_item_tcp *tcp_m = item->mask;
6119         const struct rte_flow_item_tcp *tcp_v = item->spec;
6120         void *headers_m;
6121         void *headers_v;
6122
6123         if (inner) {
6124                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6125                                          inner_headers);
6126                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6127         } else {
6128                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6129                                          outer_headers);
6130                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6131         }
6132         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6133         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6134         if (!tcp_v)
6135                 return;
6136         if (!tcp_m)
6137                 tcp_m = &rte_flow_item_tcp_mask;
6138         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6139                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6140         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6141                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6142         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6143                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6144         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6145                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6146         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6147                  tcp_m->hdr.tcp_flags);
6148         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6149                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6150 }
6151
6152 /**
6153  * Add UDP item to matcher and to the value.
6154  *
6155  * @param[in, out] matcher
6156  *   Flow matcher.
6157  * @param[in, out] key
6158  *   Flow matcher value.
6159  * @param[in] item
6160  *   Flow pattern to translate.
6161  * @param[in] inner
6162  *   Item is inner pattern.
6163  */
6164 static void
6165 flow_dv_translate_item_udp(void *matcher, void *key,
6166                            const struct rte_flow_item *item,
6167                            int inner)
6168 {
6169         const struct rte_flow_item_udp *udp_m = item->mask;
6170         const struct rte_flow_item_udp *udp_v = item->spec;
6171         void *headers_m;
6172         void *headers_v;
6173
6174         if (inner) {
6175                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6176                                          inner_headers);
6177                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6178         } else {
6179                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6180                                          outer_headers);
6181                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6182         }
6183         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6184         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6185         if (!udp_v)
6186                 return;
6187         if (!udp_m)
6188                 udp_m = &rte_flow_item_udp_mask;
6189         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6190                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6191         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6192                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6193         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6194                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6195         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6196                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6197 }
6198
6199 /**
6200  * Add GRE optional Key item to matcher and to the value.
6201  *
6202  * @param[in, out] matcher
6203  *   Flow matcher.
6204  * @param[in, out] key
6205  *   Flow matcher value.
6206  * @param[in] item
6207  *   Flow pattern to translate.
6208  * @param[in] inner
6209  *   Item is inner pattern.
6210  */
6211 static void
6212 flow_dv_translate_item_gre_key(void *matcher, void *key,
6213                                    const struct rte_flow_item *item)
6214 {
6215         const rte_be32_t *key_m = item->mask;
6216         const rte_be32_t *key_v = item->spec;
6217         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6218         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6219         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6220
6221         /* GRE K bit must be on and should already be validated */
6222         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6223         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6224         if (!key_v)
6225                 return;
6226         if (!key_m)
6227                 key_m = &gre_key_default_mask;
6228         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6229                  rte_be_to_cpu_32(*key_m) >> 8);
6230         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6231                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6232         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6233                  rte_be_to_cpu_32(*key_m) & 0xFF);
6234         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6235                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6236 }
6237
6238 /**
6239  * Add GRE item to matcher and to the value.
6240  *
6241  * @param[in, out] matcher
6242  *   Flow matcher.
6243  * @param[in, out] key
6244  *   Flow matcher value.
6245  * @param[in] item
6246  *   Flow pattern to translate.
6247  * @param[in] inner
6248  *   Item is inner pattern.
6249  */
6250 static void
6251 flow_dv_translate_item_gre(void *matcher, void *key,
6252                            const struct rte_flow_item *item,
6253                            int inner)
6254 {
6255         const struct rte_flow_item_gre *gre_m = item->mask;
6256         const struct rte_flow_item_gre *gre_v = item->spec;
6257         void *headers_m;
6258         void *headers_v;
6259         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6260         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6261         struct {
6262                 union {
6263                         __extension__
6264                         struct {
6265                                 uint16_t version:3;
6266                                 uint16_t rsvd0:9;
6267                                 uint16_t s_present:1;
6268                                 uint16_t k_present:1;
6269                                 uint16_t rsvd_bit1:1;
6270                                 uint16_t c_present:1;
6271                         };
6272                         uint16_t value;
6273                 };
6274         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6275
6276         if (inner) {
6277                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6278                                          inner_headers);
6279                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6280         } else {
6281                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6282                                          outer_headers);
6283                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6284         }
6285         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6286         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6287         if (!gre_v)
6288                 return;
6289         if (!gre_m)
6290                 gre_m = &rte_flow_item_gre_mask;
6291         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6292                  rte_be_to_cpu_16(gre_m->protocol));
6293         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6294                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6295         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6296         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6297         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6298                  gre_crks_rsvd0_ver_m.c_present);
6299         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6300                  gre_crks_rsvd0_ver_v.c_present &
6301                  gre_crks_rsvd0_ver_m.c_present);
6302         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6303                  gre_crks_rsvd0_ver_m.k_present);
6304         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6305                  gre_crks_rsvd0_ver_v.k_present &
6306                  gre_crks_rsvd0_ver_m.k_present);
6307         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6308                  gre_crks_rsvd0_ver_m.s_present);
6309         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6310                  gre_crks_rsvd0_ver_v.s_present &
6311                  gre_crks_rsvd0_ver_m.s_present);
6312 }
6313
6314 /**
6315  * Add NVGRE item to matcher and to the value.
6316  *
6317  * @param[in, out] matcher
6318  *   Flow matcher.
6319  * @param[in, out] key
6320  *   Flow matcher value.
6321  * @param[in] item
6322  *   Flow pattern to translate.
6323  * @param[in] inner
6324  *   Item is inner pattern.
6325  */
6326 static void
6327 flow_dv_translate_item_nvgre(void *matcher, void *key,
6328                              const struct rte_flow_item *item,
6329                              int inner)
6330 {
6331         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6332         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6333         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6334         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6335         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6336         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6337         char *gre_key_m;
6338         char *gre_key_v;
6339         int size;
6340         int i;
6341
6342         /* For NVGRE, GRE header fields must be set with defined values. */
6343         const struct rte_flow_item_gre gre_spec = {
6344                 .c_rsvd0_ver = RTE_BE16(0x2000),
6345                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6346         };
6347         const struct rte_flow_item_gre gre_mask = {
6348                 .c_rsvd0_ver = RTE_BE16(0xB000),
6349                 .protocol = RTE_BE16(UINT16_MAX),
6350         };
6351         const struct rte_flow_item gre_item = {
6352                 .spec = &gre_spec,
6353                 .mask = &gre_mask,
6354                 .last = NULL,
6355         };
6356         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6357         if (!nvgre_v)
6358                 return;
6359         if (!nvgre_m)
6360                 nvgre_m = &rte_flow_item_nvgre_mask;
6361         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6362         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6363         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6364         memcpy(gre_key_m, tni_flow_id_m, size);
6365         for (i = 0; i < size; ++i)
6366                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6367 }
6368
6369 /**
6370  * Add VXLAN item to matcher and to the value.
6371  *
6372  * @param[in, out] matcher
6373  *   Flow matcher.
6374  * @param[in, out] key
6375  *   Flow matcher value.
6376  * @param[in] item
6377  *   Flow pattern to translate.
6378  * @param[in] inner
6379  *   Item is inner pattern.
6380  */
6381 static void
6382 flow_dv_translate_item_vxlan(void *matcher, void *key,
6383                              const struct rte_flow_item *item,
6384                              int inner)
6385 {
6386         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6387         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6388         void *headers_m;
6389         void *headers_v;
6390         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6391         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6392         char *vni_m;
6393         char *vni_v;
6394         uint16_t dport;
6395         int size;
6396         int i;
6397
6398         if (inner) {
6399                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6400                                          inner_headers);
6401                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6402         } else {
6403                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6404                                          outer_headers);
6405                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6406         }
6407         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6408                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6409         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6410                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6411                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6412         }
6413         if (!vxlan_v)
6414                 return;
6415         if (!vxlan_m)
6416                 vxlan_m = &rte_flow_item_vxlan_mask;
6417         size = sizeof(vxlan_m->vni);
6418         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6419         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6420         memcpy(vni_m, vxlan_m->vni, size);
6421         for (i = 0; i < size; ++i)
6422                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6423 }
6424
6425 /**
6426  * Add VXLAN-GPE item to matcher and to the value.
6427  *
6428  * @param[in, out] matcher
6429  *   Flow matcher.
6430  * @param[in, out] key
6431  *   Flow matcher value.
6432  * @param[in] item
6433  *   Flow pattern to translate.
6434  * @param[in] inner
6435  *   Item is inner pattern.
6436  */
6437
6438 static void
6439 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6440                                  const struct rte_flow_item *item, int inner)
6441 {
6442         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6443         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6444         void *headers_m;
6445         void *headers_v;
6446         void *misc_m =
6447                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6448         void *misc_v =
6449                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6450         char *vni_m;
6451         char *vni_v;
6452         uint16_t dport;
6453         int size;
6454         int i;
6455         uint8_t flags_m = 0xff;
6456         uint8_t flags_v = 0xc;
6457
6458         if (inner) {
6459                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6460                                          inner_headers);
6461                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6462         } else {
6463                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6464                                          outer_headers);
6465                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6466         }
6467         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6468                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6469         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6470                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6471                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6472         }
6473         if (!vxlan_v)
6474                 return;
6475         if (!vxlan_m)
6476                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6477         size = sizeof(vxlan_m->vni);
6478         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6479         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6480         memcpy(vni_m, vxlan_m->vni, size);
6481         for (i = 0; i < size; ++i)
6482                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6483         if (vxlan_m->flags) {
6484                 flags_m = vxlan_m->flags;
6485                 flags_v = vxlan_v->flags;
6486         }
6487         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6488         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6489         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6490                  vxlan_m->protocol);
6491         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6492                  vxlan_v->protocol);
6493 }
6494
6495 /**
6496  * Add Geneve item to matcher and to the value.
6497  *
6498  * @param[in, out] matcher
6499  *   Flow matcher.
6500  * @param[in, out] key
6501  *   Flow matcher value.
6502  * @param[in] item
6503  *   Flow pattern to translate.
6504  * @param[in] inner
6505  *   Item is inner pattern.
6506  */
6507
6508 static void
6509 flow_dv_translate_item_geneve(void *matcher, void *key,
6510                               const struct rte_flow_item *item, int inner)
6511 {
6512         const struct rte_flow_item_geneve *geneve_m = item->mask;
6513         const struct rte_flow_item_geneve *geneve_v = item->spec;
6514         void *headers_m;
6515         void *headers_v;
6516         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6517         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6518         uint16_t dport;
6519         uint16_t gbhdr_m;
6520         uint16_t gbhdr_v;
6521         char *vni_m;
6522         char *vni_v;
6523         size_t size, i;
6524
6525         if (inner) {
6526                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6527                                          inner_headers);
6528                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6529         } else {
6530                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6531                                          outer_headers);
6532                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6533         }
6534         dport = MLX5_UDP_PORT_GENEVE;
6535         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6536                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6537                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6538         }
6539         if (!geneve_v)
6540                 return;
6541         if (!geneve_m)
6542                 geneve_m = &rte_flow_item_geneve_mask;
6543         size = sizeof(geneve_m->vni);
6544         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6545         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6546         memcpy(vni_m, geneve_m->vni, size);
6547         for (i = 0; i < size; ++i)
6548                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6549         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6550                  rte_be_to_cpu_16(geneve_m->protocol));
6551         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6552                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6553         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6554         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6555         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6556                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6557         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6558                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6559         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6560                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6561         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6562                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6563                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6564 }
6565
6566 /**
6567  * Add MPLS item to matcher and to the value.
6568  *
6569  * @param[in, out] matcher
6570  *   Flow matcher.
6571  * @param[in, out] key
6572  *   Flow matcher value.
6573  * @param[in] item
6574  *   Flow pattern to translate.
6575  * @param[in] prev_layer
6576  *   The protocol layer indicated in previous item.
6577  * @param[in] inner
6578  *   Item is inner pattern.
6579  */
6580 static void
6581 flow_dv_translate_item_mpls(void *matcher, void *key,
6582                             const struct rte_flow_item *item,
6583                             uint64_t prev_layer,
6584                             int inner)
6585 {
6586         const uint32_t *in_mpls_m = item->mask;
6587         const uint32_t *in_mpls_v = item->spec;
6588         uint32_t *out_mpls_m = 0;
6589         uint32_t *out_mpls_v = 0;
6590         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6591         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6592         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6593                                      misc_parameters_2);
6594         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6595         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6596         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6597
6598         switch (prev_layer) {
6599         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6600                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6601                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6602                          MLX5_UDP_PORT_MPLS);
6603                 break;
6604         case MLX5_FLOW_LAYER_GRE:
6605                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6606                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6607                          RTE_ETHER_TYPE_MPLS);
6608                 break;
6609         default:
6610                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6611                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6612                          IPPROTO_MPLS);
6613                 break;
6614         }
6615         if (!in_mpls_v)
6616                 return;
6617         if (!in_mpls_m)
6618                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6619         switch (prev_layer) {
6620         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6621                 out_mpls_m =
6622                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6623                                                  outer_first_mpls_over_udp);
6624                 out_mpls_v =
6625                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6626                                                  outer_first_mpls_over_udp);
6627                 break;
6628         case MLX5_FLOW_LAYER_GRE:
6629                 out_mpls_m =
6630                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6631                                                  outer_first_mpls_over_gre);
6632                 out_mpls_v =
6633                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6634                                                  outer_first_mpls_over_gre);
6635                 break;
6636         default:
6637                 /* Inner MPLS not over GRE is not supported. */
6638                 if (!inner) {
6639                         out_mpls_m =
6640                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6641                                                          misc2_m,
6642                                                          outer_first_mpls);
6643                         out_mpls_v =
6644                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6645                                                          misc2_v,
6646                                                          outer_first_mpls);
6647                 }
6648                 break;
6649         }
6650         if (out_mpls_m && out_mpls_v) {
6651                 *out_mpls_m = *in_mpls_m;
6652                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6653         }
6654 }
6655
6656 /**
6657  * Add metadata register item to matcher
6658  *
6659  * @param[in, out] matcher
6660  *   Flow matcher.
6661  * @param[in, out] key
6662  *   Flow matcher value.
6663  * @param[in] reg_type
6664  *   Type of device metadata register
6665  * @param[in] value
6666  *   Register value
6667  * @param[in] mask
6668  *   Register mask
6669  */
6670 static void
6671 flow_dv_match_meta_reg(void *matcher, void *key,
6672                        enum modify_reg reg_type,
6673                        uint32_t data, uint32_t mask)
6674 {
6675         void *misc2_m =
6676                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6677         void *misc2_v =
6678                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6679         uint32_t temp;
6680
6681         data &= mask;
6682         switch (reg_type) {
6683         case REG_A:
6684                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6685                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6686                 break;
6687         case REG_B:
6688                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6689                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6690                 break;
6691         case REG_C_0:
6692                 /*
6693                  * The metadata register C0 field might be divided into
6694                  * source vport index and META item value, we should set
6695                  * this field according to specified mask, not as whole one.
6696                  */
6697                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6698                 temp |= mask;
6699                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6700                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6701                 temp &= ~mask;
6702                 temp |= data;
6703                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6704                 break;
6705         case REG_C_1:
6706                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6707                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6708                 break;
6709         case REG_C_2:
6710                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6711                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6712                 break;
6713         case REG_C_3:
6714                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6715                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6716                 break;
6717         case REG_C_4:
6718                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6719                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6720                 break;
6721         case REG_C_5:
6722                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6723                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6724                 break;
6725         case REG_C_6:
6726                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6727                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6728                 break;
6729         case REG_C_7:
6730                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6731                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6732                 break;
6733         default:
6734                 MLX5_ASSERT(false);
6735                 break;
6736         }
6737 }
6738
6739 /**
6740  * Add MARK item to matcher
6741  *
6742  * @param[in] dev
6743  *   The device to configure through.
6744  * @param[in, out] matcher
6745  *   Flow matcher.
6746  * @param[in, out] key
6747  *   Flow matcher value.
6748  * @param[in] item
6749  *   Flow pattern to translate.
6750  */
6751 static void
6752 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6753                             void *matcher, void *key,
6754                             const struct rte_flow_item *item)
6755 {
6756         struct mlx5_priv *priv = dev->data->dev_private;
6757         const struct rte_flow_item_mark *mark;
6758         uint32_t value;
6759         uint32_t mask;
6760
6761         mark = item->mask ? (const void *)item->mask :
6762                             &rte_flow_item_mark_mask;
6763         mask = mark->id & priv->sh->dv_mark_mask;
6764         mark = (const void *)item->spec;
6765         MLX5_ASSERT(mark);
6766         value = mark->id & priv->sh->dv_mark_mask & mask;
6767         if (mask) {
6768                 enum modify_reg reg;
6769
6770                 /* Get the metadata register index for the mark. */
6771                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6772                 MLX5_ASSERT(reg > 0);
6773                 if (reg == REG_C_0) {
6774                         struct mlx5_priv *priv = dev->data->dev_private;
6775                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6776                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6777
6778                         mask &= msk_c0;
6779                         mask <<= shl_c0;
6780                         value <<= shl_c0;
6781                 }
6782                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6783         }
6784 }
6785
6786 /**
6787  * Add META item to matcher
6788  *
6789  * @param[in] dev
6790  *   The devich to configure through.
6791  * @param[in, out] matcher
6792  *   Flow matcher.
6793  * @param[in, out] key
6794  *   Flow matcher value.
6795  * @param[in] attr
6796  *   Attributes of flow that includes this item.
6797  * @param[in] item
6798  *   Flow pattern to translate.
6799  */
6800 static void
6801 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6802                             void *matcher, void *key,
6803                             const struct rte_flow_attr *attr,
6804                             const struct rte_flow_item *item)
6805 {
6806         const struct rte_flow_item_meta *meta_m;
6807         const struct rte_flow_item_meta *meta_v;
6808
6809         meta_m = (const void *)item->mask;
6810         if (!meta_m)
6811                 meta_m = &rte_flow_item_meta_mask;
6812         meta_v = (const void *)item->spec;
6813         if (meta_v) {
6814                 int reg;
6815                 uint32_t value = meta_v->data;
6816                 uint32_t mask = meta_m->data;
6817
6818                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6819                 if (reg < 0)
6820                         return;
6821                 /*
6822                  * In datapath code there is no endianness
6823                  * coversions for perfromance reasons, all
6824                  * pattern conversions are done in rte_flow.
6825                  */
6826                 value = rte_cpu_to_be_32(value);
6827                 mask = rte_cpu_to_be_32(mask);
6828                 if (reg == REG_C_0) {
6829                         struct mlx5_priv *priv = dev->data->dev_private;
6830                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6831                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6832 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6833                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6834
6835                         value >>= shr_c0;
6836                         mask >>= shr_c0;
6837 #endif
6838                         value <<= shl_c0;
6839                         mask <<= shl_c0;
6840                         MLX5_ASSERT(msk_c0);
6841                         MLX5_ASSERT(!(~msk_c0 & mask));
6842                 }
6843                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6844         }
6845 }
6846
6847 /**
6848  * Add vport metadata Reg C0 item to matcher
6849  *
6850  * @param[in, out] matcher
6851  *   Flow matcher.
6852  * @param[in, out] key
6853  *   Flow matcher value.
6854  * @param[in] reg
6855  *   Flow pattern to translate.
6856  */
6857 static void
6858 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6859                                   uint32_t value, uint32_t mask)
6860 {
6861         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6862 }
6863
6864 /**
6865  * Add tag item to matcher
6866  *
6867  * @param[in] dev
6868  *   The devich to configure through.
6869  * @param[in, out] matcher
6870  *   Flow matcher.
6871  * @param[in, out] key
6872  *   Flow matcher value.
6873  * @param[in] item
6874  *   Flow pattern to translate.
6875  */
6876 static void
6877 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6878                                 void *matcher, void *key,
6879                                 const struct rte_flow_item *item)
6880 {
6881         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6882         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6883         uint32_t mask, value;
6884
6885         MLX5_ASSERT(tag_v);
6886         value = tag_v->data;
6887         mask = tag_m ? tag_m->data : UINT32_MAX;
6888         if (tag_v->id == REG_C_0) {
6889                 struct mlx5_priv *priv = dev->data->dev_private;
6890                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6891                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6892
6893                 mask &= msk_c0;
6894                 mask <<= shl_c0;
6895                 value <<= shl_c0;
6896         }
6897         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6898 }
6899
6900 /**
6901  * Add TAG item to matcher
6902  *
6903  * @param[in] dev
6904  *   The devich to configure through.
6905  * @param[in, out] matcher
6906  *   Flow matcher.
6907  * @param[in, out] key
6908  *   Flow matcher value.
6909  * @param[in] item
6910  *   Flow pattern to translate.
6911  */
6912 static void
6913 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6914                            void *matcher, void *key,
6915                            const struct rte_flow_item *item)
6916 {
6917         const struct rte_flow_item_tag *tag_v = item->spec;
6918         const struct rte_flow_item_tag *tag_m = item->mask;
6919         enum modify_reg reg;
6920
6921         MLX5_ASSERT(tag_v);
6922         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6923         /* Get the metadata register index for the tag. */
6924         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6925         MLX5_ASSERT(reg > 0);
6926         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6927 }
6928
6929 /**
6930  * Add source vport match to the specified matcher.
6931  *
6932  * @param[in, out] matcher
6933  *   Flow matcher.
6934  * @param[in, out] key
6935  *   Flow matcher value.
6936  * @param[in] port
6937  *   Source vport value to match
6938  * @param[in] mask
6939  *   Mask
6940  */
6941 static void
6942 flow_dv_translate_item_source_vport(void *matcher, void *key,
6943                                     int16_t port, uint16_t mask)
6944 {
6945         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6946         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6947
6948         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6949         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6950 }
6951
6952 /**
6953  * Translate port-id item to eswitch match on  port-id.
6954  *
6955  * @param[in] dev
6956  *   The devich to configure through.
6957  * @param[in, out] matcher
6958  *   Flow matcher.
6959  * @param[in, out] key
6960  *   Flow matcher value.
6961  * @param[in] item
6962  *   Flow pattern to translate.
6963  *
6964  * @return
6965  *   0 on success, a negative errno value otherwise.
6966  */
6967 static int
6968 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6969                                void *key, const struct rte_flow_item *item)
6970 {
6971         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6972         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6973         struct mlx5_priv *priv;
6974         uint16_t mask, id;
6975
6976         mask = pid_m ? pid_m->id : 0xffff;
6977         id = pid_v ? pid_v->id : dev->data->port_id;
6978         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6979         if (!priv)
6980                 return -rte_errno;
6981         /* Translate to vport field or to metadata, depending on mode. */
6982         if (priv->vport_meta_mask)
6983                 flow_dv_translate_item_meta_vport(matcher, key,
6984                                                   priv->vport_meta_tag,
6985                                                   priv->vport_meta_mask);
6986         else
6987                 flow_dv_translate_item_source_vport(matcher, key,
6988                                                     priv->vport_id, mask);
6989         return 0;
6990 }
6991
6992 /**
6993  * Add ICMP6 item to matcher and to the value.
6994  *
6995  * @param[in, out] matcher
6996  *   Flow matcher.
6997  * @param[in, out] key
6998  *   Flow matcher value.
6999  * @param[in] item
7000  *   Flow pattern to translate.
7001  * @param[in] inner
7002  *   Item is inner pattern.
7003  */
7004 static void
7005 flow_dv_translate_item_icmp6(void *matcher, void *key,
7006                               const struct rte_flow_item *item,
7007                               int inner)
7008 {
7009         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7010         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7011         void *headers_m;
7012         void *headers_v;
7013         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7014                                      misc_parameters_3);
7015         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7016         if (inner) {
7017                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7018                                          inner_headers);
7019                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7020         } else {
7021                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7022                                          outer_headers);
7023                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7024         }
7025         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7026         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7027         if (!icmp6_v)
7028                 return;
7029         if (!icmp6_m)
7030                 icmp6_m = &rte_flow_item_icmp6_mask;
7031         /*
7032          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7033          * If only the protocol is specified, no need to match the frag.
7034          */
7035         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7036         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7037         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7038         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7039                  icmp6_v->type & icmp6_m->type);
7040         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7041         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7042                  icmp6_v->code & icmp6_m->code);
7043 }
7044
7045 /**
7046  * Add ICMP item to matcher and to the value.
7047  *
7048  * @param[in, out] matcher
7049  *   Flow matcher.
7050  * @param[in, out] key
7051  *   Flow matcher value.
7052  * @param[in] item
7053  *   Flow pattern to translate.
7054  * @param[in] inner
7055  *   Item is inner pattern.
7056  */
7057 static void
7058 flow_dv_translate_item_icmp(void *matcher, void *key,
7059                             const struct rte_flow_item *item,
7060                             int inner)
7061 {
7062         const struct rte_flow_item_icmp *icmp_m = item->mask;
7063         const struct rte_flow_item_icmp *icmp_v = item->spec;
7064         void *headers_m;
7065         void *headers_v;
7066         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7067                                      misc_parameters_3);
7068         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7069         if (inner) {
7070                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7071                                          inner_headers);
7072                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7073         } else {
7074                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7075                                          outer_headers);
7076                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7077         }
7078         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7079         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7080         if (!icmp_v)
7081                 return;
7082         if (!icmp_m)
7083                 icmp_m = &rte_flow_item_icmp_mask;
7084         /*
7085          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7086          * If only the protocol is specified, no need to match the frag.
7087          */
7088         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7089         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7090         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7091                  icmp_m->hdr.icmp_type);
7092         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7093                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7094         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7095                  icmp_m->hdr.icmp_code);
7096         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7097                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7098 }
7099
7100 /**
7101  * Add GTP item to matcher and to the value.
7102  *
7103  * @param[in, out] matcher
7104  *   Flow matcher.
7105  * @param[in, out] key
7106  *   Flow matcher value.
7107  * @param[in] item
7108  *   Flow pattern to translate.
7109  * @param[in] inner
7110  *   Item is inner pattern.
7111  */
7112 static void
7113 flow_dv_translate_item_gtp(void *matcher, void *key,
7114                            const struct rte_flow_item *item, int inner)
7115 {
7116         const struct rte_flow_item_gtp *gtp_m = item->mask;
7117         const struct rte_flow_item_gtp *gtp_v = item->spec;
7118         void *headers_m;
7119         void *headers_v;
7120         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7121                                      misc_parameters_3);
7122         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7123         uint16_t dport = RTE_GTPU_UDP_PORT;
7124
7125         if (inner) {
7126                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7127                                          inner_headers);
7128                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7129         } else {
7130                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7131                                          outer_headers);
7132                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7133         }
7134         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7135                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7136                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7137         }
7138         if (!gtp_v)
7139                 return;
7140         if (!gtp_m)
7141                 gtp_m = &rte_flow_item_gtp_mask;
7142         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7143                  gtp_m->v_pt_rsv_flags);
7144         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7145                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7146         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7147         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7148                  gtp_v->msg_type & gtp_m->msg_type);
7149         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7150                  rte_be_to_cpu_32(gtp_m->teid));
7151         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7152                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7153 }
7154
7155 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7156
7157 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7158         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7159                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7160
7161 /**
7162  * Calculate flow matcher enable bitmap.
7163  *
7164  * @param match_criteria
7165  *   Pointer to flow matcher criteria.
7166  *
7167  * @return
7168  *   Bitmap of enabled fields.
7169  */
7170 static uint8_t
7171 flow_dv_matcher_enable(uint32_t *match_criteria)
7172 {
7173         uint8_t match_criteria_enable;
7174
7175         match_criteria_enable =
7176                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7177                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7178         match_criteria_enable |=
7179                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7180                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7181         match_criteria_enable |=
7182                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7183                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7184         match_criteria_enable |=
7185                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7186                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7187         match_criteria_enable |=
7188                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7189                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7190         return match_criteria_enable;
7191 }
7192
7193
7194 /**
7195  * Get a flow table.
7196  *
7197  * @param[in, out] dev
7198  *   Pointer to rte_eth_dev structure.
7199  * @param[in] table_id
7200  *   Table id to use.
7201  * @param[in] egress
7202  *   Direction of the table.
7203  * @param[in] transfer
7204  *   E-Switch or NIC flow.
7205  * @param[out] error
7206  *   pointer to error structure.
7207  *
7208  * @return
7209  *   Returns tables resource based on the index, NULL in case of failed.
7210  */
7211 static struct mlx5_flow_tbl_resource *
7212 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7213                          uint32_t table_id, uint8_t egress,
7214                          uint8_t transfer,
7215                          struct rte_flow_error *error)
7216 {
7217         struct mlx5_priv *priv = dev->data->dev_private;
7218         struct mlx5_dev_ctx_shared *sh = priv->sh;
7219         struct mlx5_flow_tbl_resource *tbl;
7220         union mlx5_flow_tbl_key table_key = {
7221                 {
7222                         .table_id = table_id,
7223                         .reserved = 0,
7224                         .domain = !!transfer,
7225                         .direction = !!egress,
7226                 }
7227         };
7228         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7229                                                          table_key.v64);
7230         struct mlx5_flow_tbl_data_entry *tbl_data;
7231         uint32_t idx = 0;
7232         int ret;
7233         void *domain;
7234
7235         if (pos) {
7236                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7237                                         entry);
7238                 tbl = &tbl_data->tbl;
7239                 rte_atomic32_inc(&tbl->refcnt);
7240                 return tbl;
7241         }
7242         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7243         if (!tbl_data) {
7244                 rte_flow_error_set(error, ENOMEM,
7245                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7246                                    NULL,
7247                                    "cannot allocate flow table data entry");
7248                 return NULL;
7249         }
7250         tbl_data->idx = idx;
7251         tbl = &tbl_data->tbl;
7252         pos = &tbl_data->entry;
7253         if (transfer)
7254                 domain = sh->fdb_domain;
7255         else if (egress)
7256                 domain = sh->tx_domain;
7257         else
7258                 domain = sh->rx_domain;
7259         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7260         if (!tbl->obj) {
7261                 rte_flow_error_set(error, ENOMEM,
7262                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7263                                    NULL, "cannot create flow table object");
7264                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7265                 return NULL;
7266         }
7267         /*
7268          * No multi-threads now, but still better to initialize the reference
7269          * count before insert it into the hash list.
7270          */
7271         rte_atomic32_init(&tbl->refcnt);
7272         /* Jump action reference count is initialized here. */
7273         rte_atomic32_init(&tbl_data->jump.refcnt);
7274         pos->key = table_key.v64;
7275         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7276         if (ret < 0) {
7277                 rte_flow_error_set(error, -ret,
7278                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7279                                    "cannot insert flow table data entry");
7280                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7281                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7282         }
7283         rte_atomic32_inc(&tbl->refcnt);
7284         return tbl;
7285 }
7286
7287 /**
7288  * Release a flow table.
7289  *
7290  * @param[in] dev
7291  *   Pointer to rte_eth_dev structure.
7292  * @param[in] tbl
7293  *   Table resource to be released.
7294  *
7295  * @return
7296  *   Returns 0 if table was released, else return 1;
7297  */
7298 static int
7299 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7300                              struct mlx5_flow_tbl_resource *tbl)
7301 {
7302         struct mlx5_priv *priv = dev->data->dev_private;
7303         struct mlx5_dev_ctx_shared *sh = priv->sh;
7304         struct mlx5_flow_tbl_data_entry *tbl_data =
7305                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7306
7307         if (!tbl)
7308                 return 0;
7309         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7310                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7311
7312                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7313                 tbl->obj = NULL;
7314                 /* remove the entry from the hash list and free memory. */
7315                 mlx5_hlist_remove(sh->flow_tbls, pos);
7316                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7317                                 tbl_data->idx);
7318                 return 0;
7319         }
7320         return 1;
7321 }
7322
7323 /**
7324  * Register the flow matcher.
7325  *
7326  * @param[in, out] dev
7327  *   Pointer to rte_eth_dev structure.
7328  * @param[in, out] matcher
7329  *   Pointer to flow matcher.
7330  * @param[in, out] key
7331  *   Pointer to flow table key.
7332  * @parm[in, out] dev_flow
7333  *   Pointer to the dev_flow.
7334  * @param[out] error
7335  *   pointer to error structure.
7336  *
7337  * @return
7338  *   0 on success otherwise -errno and errno is set.
7339  */
7340 static int
7341 flow_dv_matcher_register(struct rte_eth_dev *dev,
7342                          struct mlx5_flow_dv_matcher *matcher,
7343                          union mlx5_flow_tbl_key *key,
7344                          struct mlx5_flow *dev_flow,
7345                          struct rte_flow_error *error)
7346 {
7347         struct mlx5_priv *priv = dev->data->dev_private;
7348         struct mlx5_dev_ctx_shared *sh = priv->sh;
7349         struct mlx5_flow_dv_matcher *cache_matcher;
7350         struct mlx5dv_flow_matcher_attr dv_attr = {
7351                 .type = IBV_FLOW_ATTR_NORMAL,
7352                 .match_mask = (void *)&matcher->mask,
7353         };
7354         struct mlx5_flow_tbl_resource *tbl;
7355         struct mlx5_flow_tbl_data_entry *tbl_data;
7356
7357         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7358                                        key->domain, error);
7359         if (!tbl)
7360                 return -rte_errno;      /* No need to refill the error info */
7361         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7362         /* Lookup from cache. */
7363         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7364                 if (matcher->crc == cache_matcher->crc &&
7365                     matcher->priority == cache_matcher->priority &&
7366                     !memcmp((const void *)matcher->mask.buf,
7367                             (const void *)cache_matcher->mask.buf,
7368                             cache_matcher->mask.size)) {
7369                         DRV_LOG(DEBUG,
7370                                 "%s group %u priority %hd use %s "
7371                                 "matcher %p: refcnt %d++",
7372                                 key->domain ? "FDB" : "NIC", key->table_id,
7373                                 cache_matcher->priority,
7374                                 key->direction ? "tx" : "rx",
7375                                 (void *)cache_matcher,
7376                                 rte_atomic32_read(&cache_matcher->refcnt));
7377                         rte_atomic32_inc(&cache_matcher->refcnt);
7378                         dev_flow->handle->dvh.matcher = cache_matcher;
7379                         /* old matcher should not make the table ref++. */
7380                         flow_dv_tbl_resource_release(dev, tbl);
7381                         return 0;
7382                 }
7383         }
7384         /* Register new matcher. */
7385         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7386         if (!cache_matcher) {
7387                 flow_dv_tbl_resource_release(dev, tbl);
7388                 return rte_flow_error_set(error, ENOMEM,
7389                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7390                                           "cannot allocate matcher memory");
7391         }
7392         *cache_matcher = *matcher;
7393         dv_attr.match_criteria_enable =
7394                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7395         dv_attr.priority = matcher->priority;
7396         if (key->direction)
7397                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7398         cache_matcher->matcher_object =
7399                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7400         if (!cache_matcher->matcher_object) {
7401                 rte_free(cache_matcher);
7402 #ifdef HAVE_MLX5DV_DR
7403                 flow_dv_tbl_resource_release(dev, tbl);
7404 #endif
7405                 return rte_flow_error_set(error, ENOMEM,
7406                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7407                                           NULL, "cannot create matcher");
7408         }
7409         /* Save the table information */
7410         cache_matcher->tbl = tbl;
7411         rte_atomic32_init(&cache_matcher->refcnt);
7412         /* only matcher ref++, table ref++ already done above in get API. */
7413         rte_atomic32_inc(&cache_matcher->refcnt);
7414         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7415         dev_flow->handle->dvh.matcher = cache_matcher;
7416         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7417                 key->domain ? "FDB" : "NIC", key->table_id,
7418                 cache_matcher->priority,
7419                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7420                 rte_atomic32_read(&cache_matcher->refcnt));
7421         return 0;
7422 }
7423
7424 /**
7425  * Find existing tag resource or create and register a new one.
7426  *
7427  * @param dev[in, out]
7428  *   Pointer to rte_eth_dev structure.
7429  * @param[in, out] tag_be24
7430  *   Tag value in big endian then R-shift 8.
7431  * @parm[in, out] dev_flow
7432  *   Pointer to the dev_flow.
7433  * @param[out] error
7434  *   pointer to error structure.
7435  *
7436  * @return
7437  *   0 on success otherwise -errno and errno is set.
7438  */
7439 static int
7440 flow_dv_tag_resource_register
7441                         (struct rte_eth_dev *dev,
7442                          uint32_t tag_be24,
7443                          struct mlx5_flow *dev_flow,
7444                          struct rte_flow_error *error)
7445 {
7446         struct mlx5_priv *priv = dev->data->dev_private;
7447         struct mlx5_dev_ctx_shared *sh = priv->sh;
7448         struct mlx5_flow_dv_tag_resource *cache_resource;
7449         struct mlx5_hlist_entry *entry;
7450
7451         /* Lookup a matching resource from cache. */
7452         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7453         if (entry) {
7454                 cache_resource = container_of
7455                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7456                 rte_atomic32_inc(&cache_resource->refcnt);
7457                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7458                 dev_flow->dv.tag_resource = cache_resource;
7459                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7460                         (void *)cache_resource,
7461                         rte_atomic32_read(&cache_resource->refcnt));
7462                 return 0;
7463         }
7464         /* Register new resource. */
7465         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7466                                        &dev_flow->handle->dvh.rix_tag);
7467         if (!cache_resource)
7468                 return rte_flow_error_set(error, ENOMEM,
7469                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7470                                           "cannot allocate resource memory");
7471         cache_resource->entry.key = (uint64_t)tag_be24;
7472         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7473         if (!cache_resource->action) {
7474                 rte_free(cache_resource);
7475                 return rte_flow_error_set(error, ENOMEM,
7476                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7477                                           NULL, "cannot create action");
7478         }
7479         rte_atomic32_init(&cache_resource->refcnt);
7480         rte_atomic32_inc(&cache_resource->refcnt);
7481         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7482                 mlx5_glue->destroy_flow_action(cache_resource->action);
7483                 rte_free(cache_resource);
7484                 return rte_flow_error_set(error, EEXIST,
7485                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7486                                           NULL, "cannot insert tag");
7487         }
7488         dev_flow->dv.tag_resource = cache_resource;
7489         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7490                 (void *)cache_resource,
7491                 rte_atomic32_read(&cache_resource->refcnt));
7492         return 0;
7493 }
7494
7495 /**
7496  * Release the tag.
7497  *
7498  * @param dev
7499  *   Pointer to Ethernet device.
7500  * @param tag_idx
7501  *   Tag index.
7502  *
7503  * @return
7504  *   1 while a reference on it exists, 0 when freed.
7505  */
7506 static int
7507 flow_dv_tag_release(struct rte_eth_dev *dev,
7508                     uint32_t tag_idx)
7509 {
7510         struct mlx5_priv *priv = dev->data->dev_private;
7511         struct mlx5_dev_ctx_shared *sh = priv->sh;
7512         struct mlx5_flow_dv_tag_resource *tag;
7513
7514         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7515         if (!tag)
7516                 return 0;
7517         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7518                 dev->data->port_id, (void *)tag,
7519                 rte_atomic32_read(&tag->refcnt));
7520         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7521                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7522                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7523                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7524                         dev->data->port_id, (void *)tag);
7525                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7526                 return 0;
7527         }
7528         return 1;
7529 }
7530
7531 /**
7532  * Translate port ID action to vport.
7533  *
7534  * @param[in] dev
7535  *   Pointer to rte_eth_dev structure.
7536  * @param[in] action
7537  *   Pointer to the port ID action.
7538  * @param[out] dst_port_id
7539  *   The target port ID.
7540  * @param[out] error
7541  *   Pointer to the error structure.
7542  *
7543  * @return
7544  *   0 on success, a negative errno value otherwise and rte_errno is set.
7545  */
7546 static int
7547 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7548                                  const struct rte_flow_action *action,
7549                                  uint32_t *dst_port_id,
7550                                  struct rte_flow_error *error)
7551 {
7552         uint32_t port;
7553         struct mlx5_priv *priv;
7554         const struct rte_flow_action_port_id *conf =
7555                         (const struct rte_flow_action_port_id *)action->conf;
7556
7557         port = conf->original ? dev->data->port_id : conf->id;
7558         priv = mlx5_port_to_eswitch_info(port, false);
7559         if (!priv)
7560                 return rte_flow_error_set(error, -rte_errno,
7561                                           RTE_FLOW_ERROR_TYPE_ACTION,
7562                                           NULL,
7563                                           "No eswitch info was found for port");
7564 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7565         /*
7566          * This parameter is transferred to
7567          * mlx5dv_dr_action_create_dest_ib_port().
7568          */
7569         *dst_port_id = priv->dev_port;
7570 #else
7571         /*
7572          * Legacy mode, no LAG configurations is supported.
7573          * This parameter is transferred to
7574          * mlx5dv_dr_action_create_dest_vport().
7575          */
7576         *dst_port_id = priv->vport_id;
7577 #endif
7578         return 0;
7579 }
7580
7581 /**
7582  * Create a counter with aging configuration.
7583  *
7584  * @param[in] dev
7585  *   Pointer to rte_eth_dev structure.
7586  * @param[out] count
7587  *   Pointer to the counter action configuration.
7588  * @param[in] age
7589  *   Pointer to the aging action configuration.
7590  *
7591  * @return
7592  *   Index to flow counter on success, 0 otherwise.
7593  */
7594 static uint32_t
7595 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7596                                 struct mlx5_flow *dev_flow,
7597                                 const struct rte_flow_action_count *count,
7598                                 const struct rte_flow_action_age *age)
7599 {
7600         uint32_t counter;
7601         struct mlx5_age_param *age_param;
7602
7603         counter = flow_dv_counter_alloc(dev,
7604                                 count ? count->shared : 0,
7605                                 count ? count->id : 0,
7606                                 dev_flow->dv.group, !!age);
7607         if (!counter || age == NULL)
7608                 return counter;
7609         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7610         /*
7611          * The counter age accuracy may have a bit delay. Have 3/4
7612          * second bias on the timeount in order to let it age in time.
7613          */
7614         age_param->context = age->context ? age->context :
7615                 (void *)(uintptr_t)(dev_flow->flow_idx);
7616         /*
7617          * The counter age accuracy may have a bit delay. Have 3/4
7618          * second bias on the timeount in order to let it age in time.
7619          */
7620         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7621         /* Set expire time in unit of 0.1 sec. */
7622         age_param->port_id = dev->data->port_id;
7623         age_param->expire = age_param->timeout +
7624                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7625         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7626         return counter;
7627 }
7628 /**
7629  * Add Tx queue matcher
7630  *
7631  * @param[in] dev
7632  *   Pointer to the dev struct.
7633  * @param[in, out] matcher
7634  *   Flow matcher.
7635  * @param[in, out] key
7636  *   Flow matcher value.
7637  * @param[in] item
7638  *   Flow pattern to translate.
7639  * @param[in] inner
7640  *   Item is inner pattern.
7641  */
7642 static void
7643 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7644                                 void *matcher, void *key,
7645                                 const struct rte_flow_item *item)
7646 {
7647         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7648         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7649         void *misc_m =
7650                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7651         void *misc_v =
7652                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7653         struct mlx5_txq_ctrl *txq;
7654         uint32_t queue;
7655
7656
7657         queue_m = (const void *)item->mask;
7658         if (!queue_m)
7659                 return;
7660         queue_v = (const void *)item->spec;
7661         if (!queue_v)
7662                 return;
7663         txq = mlx5_txq_get(dev, queue_v->queue);
7664         if (!txq)
7665                 return;
7666         queue = txq->obj->sq->id;
7667         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7668         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7669                  queue & queue_m->queue);
7670         mlx5_txq_release(dev, queue_v->queue);
7671 }
7672
7673 /**
7674  * Set the hash fields according to the @p flow information.
7675  *
7676  * @param[in] dev_flow
7677  *   Pointer to the mlx5_flow.
7678  * @param[in] rss_desc
7679  *   Pointer to the mlx5_flow_rss_desc.
7680  */
7681 static void
7682 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7683                        struct mlx5_flow_rss_desc *rss_desc)
7684 {
7685         uint64_t items = dev_flow->handle->layers;
7686         int rss_inner = 0;
7687         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7688
7689         dev_flow->hash_fields = 0;
7690 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7691         if (rss_desc->level >= 2) {
7692                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7693                 rss_inner = 1;
7694         }
7695 #endif
7696         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7697             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7698                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7699                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7700                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7701                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7702                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7703                         else
7704                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7705                 }
7706         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7707                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7708                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7709                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7710                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7711                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7712                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7713                         else
7714                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7715                 }
7716         }
7717         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7718             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7719                 if (rss_types & ETH_RSS_UDP) {
7720                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7721                                 dev_flow->hash_fields |=
7722                                                 IBV_RX_HASH_SRC_PORT_UDP;
7723                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7724                                 dev_flow->hash_fields |=
7725                                                 IBV_RX_HASH_DST_PORT_UDP;
7726                         else
7727                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7728                 }
7729         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7730                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7731                 if (rss_types & ETH_RSS_TCP) {
7732                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7733                                 dev_flow->hash_fields |=
7734                                                 IBV_RX_HASH_SRC_PORT_TCP;
7735                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7736                                 dev_flow->hash_fields |=
7737                                                 IBV_RX_HASH_DST_PORT_TCP;
7738                         else
7739                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7740                 }
7741         }
7742 }
7743
7744 /**
7745  * Fill the flow with DV spec, lock free
7746  * (mutex should be acquired by caller).
7747  *
7748  * @param[in] dev
7749  *   Pointer to rte_eth_dev structure.
7750  * @param[in, out] dev_flow
7751  *   Pointer to the sub flow.
7752  * @param[in] attr
7753  *   Pointer to the flow attributes.
7754  * @param[in] items
7755  *   Pointer to the list of items.
7756  * @param[in] actions
7757  *   Pointer to the list of actions.
7758  * @param[out] error
7759  *   Pointer to the error structure.
7760  *
7761  * @return
7762  *   0 on success, a negative errno value otherwise and rte_errno is set.
7763  */
7764 static int
7765 __flow_dv_translate(struct rte_eth_dev *dev,
7766                     struct mlx5_flow *dev_flow,
7767                     const struct rte_flow_attr *attr,
7768                     const struct rte_flow_item items[],
7769                     const struct rte_flow_action actions[],
7770                     struct rte_flow_error *error)
7771 {
7772         struct mlx5_priv *priv = dev->data->dev_private;
7773         struct mlx5_dev_config *dev_conf = &priv->config;
7774         struct rte_flow *flow = dev_flow->flow;
7775         struct mlx5_flow_handle *handle = dev_flow->handle;
7776         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7777                                               priv->rss_desc)
7778                                               [!!priv->flow_nested_idx];
7779         uint64_t item_flags = 0;
7780         uint64_t last_item = 0;
7781         uint64_t action_flags = 0;
7782         uint64_t priority = attr->priority;
7783         struct mlx5_flow_dv_matcher matcher = {
7784                 .mask = {
7785                         .size = sizeof(matcher.mask.buf),
7786                 },
7787         };
7788         int actions_n = 0;
7789         bool actions_end = false;
7790         union {
7791                 struct mlx5_flow_dv_modify_hdr_resource res;
7792                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7793                             sizeof(struct mlx5_modification_cmd) *
7794                             (MLX5_MAX_MODIFY_NUM + 1)];
7795         } mhdr_dummy;
7796         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7797         const struct rte_flow_action_count *count = NULL;
7798         const struct rte_flow_action_age *age = NULL;
7799         union flow_dv_attr flow_attr = { .attr = 0 };
7800         uint32_t tag_be;
7801         union mlx5_flow_tbl_key tbl_key;
7802         uint32_t modify_action_position = UINT32_MAX;
7803         void *match_mask = matcher.mask.buf;
7804         void *match_value = dev_flow->dv.value.buf;
7805         uint8_t next_protocol = 0xff;
7806         struct rte_vlan_hdr vlan = { 0 };
7807         uint32_t table;
7808         int ret = 0;
7809
7810         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7811                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7812         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7813                                        !!priv->fdb_def_rule, &table, error);
7814         if (ret)
7815                 return ret;
7816         dev_flow->dv.group = table;
7817         if (attr->transfer)
7818                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7819         if (priority == MLX5_FLOW_PRIO_RSVD)
7820                 priority = dev_conf->flow_prio - 1;
7821         /* number of actions must be set to 0 in case of dirty stack. */
7822         mhdr_res->actions_num = 0;
7823         for (; !actions_end ; actions++) {
7824                 const struct rte_flow_action_queue *queue;
7825                 const struct rte_flow_action_rss *rss;
7826                 const struct rte_flow_action *action = actions;
7827                 const uint8_t *rss_key;
7828                 const struct rte_flow_action_jump *jump_data;
7829                 const struct rte_flow_action_meter *mtr;
7830                 struct mlx5_flow_tbl_resource *tbl;
7831                 uint32_t port_id = 0;
7832                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7833                 int action_type = actions->type;
7834                 const struct rte_flow_action *found_action = NULL;
7835                 struct mlx5_flow_meter *fm = NULL;
7836
7837                 switch (action_type) {
7838                 case RTE_FLOW_ACTION_TYPE_VOID:
7839                         break;
7840                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7841                         if (flow_dv_translate_action_port_id(dev, action,
7842                                                              &port_id, error))
7843                                 return -rte_errno;
7844                         port_id_resource.port_id = port_id;
7845                         MLX5_ASSERT(!handle->rix_port_id_action);
7846                         if (flow_dv_port_id_action_resource_register
7847                             (dev, &port_id_resource, dev_flow, error))
7848                                 return -rte_errno;
7849                         dev_flow->dv.actions[actions_n++] =
7850                                         dev_flow->dv.port_id_action->action;
7851                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7852                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7853                         break;
7854                 case RTE_FLOW_ACTION_TYPE_FLAG:
7855                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7856                         dev_flow->handle->mark = 1;
7857                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7858                                 struct rte_flow_action_mark mark = {
7859                                         .id = MLX5_FLOW_MARK_DEFAULT,
7860                                 };
7861
7862                                 if (flow_dv_convert_action_mark(dev, &mark,
7863                                                                 mhdr_res,
7864                                                                 error))
7865                                         return -rte_errno;
7866                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7867                                 break;
7868                         }
7869                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7870                         /*
7871                          * Only one FLAG or MARK is supported per device flow
7872                          * right now. So the pointer to the tag resource must be
7873                          * zero before the register process.
7874                          */
7875                         MLX5_ASSERT(!handle->dvh.rix_tag);
7876                         if (flow_dv_tag_resource_register(dev, tag_be,
7877                                                           dev_flow, error))
7878                                 return -rte_errno;
7879                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7880                         dev_flow->dv.actions[actions_n++] =
7881                                         dev_flow->dv.tag_resource->action;
7882                         break;
7883                 case RTE_FLOW_ACTION_TYPE_MARK:
7884                         action_flags |= MLX5_FLOW_ACTION_MARK;
7885                         dev_flow->handle->mark = 1;
7886                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7887                                 const struct rte_flow_action_mark *mark =
7888                                         (const struct rte_flow_action_mark *)
7889                                                 actions->conf;
7890
7891                                 if (flow_dv_convert_action_mark(dev, mark,
7892                                                                 mhdr_res,
7893                                                                 error))
7894                                         return -rte_errno;
7895                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7896                                 break;
7897                         }
7898                         /* Fall-through */
7899                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7900                         /* Legacy (non-extensive) MARK action. */
7901                         tag_be = mlx5_flow_mark_set
7902                               (((const struct rte_flow_action_mark *)
7903                                (actions->conf))->id);
7904                         MLX5_ASSERT(!handle->dvh.rix_tag);
7905                         if (flow_dv_tag_resource_register(dev, tag_be,
7906                                                           dev_flow, error))
7907                                 return -rte_errno;
7908                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7909                         dev_flow->dv.actions[actions_n++] =
7910                                         dev_flow->dv.tag_resource->action;
7911                         break;
7912                 case RTE_FLOW_ACTION_TYPE_SET_META:
7913                         if (flow_dv_convert_action_set_meta
7914                                 (dev, mhdr_res, attr,
7915                                  (const struct rte_flow_action_set_meta *)
7916                                   actions->conf, error))
7917                                 return -rte_errno;
7918                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7919                         break;
7920                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7921                         if (flow_dv_convert_action_set_tag
7922                                 (dev, mhdr_res,
7923                                  (const struct rte_flow_action_set_tag *)
7924                                   actions->conf, error))
7925                                 return -rte_errno;
7926                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7927                         break;
7928                 case RTE_FLOW_ACTION_TYPE_DROP:
7929                         action_flags |= MLX5_FLOW_ACTION_DROP;
7930                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7931                         break;
7932                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7933                         queue = actions->conf;
7934                         rss_desc->queue_num = 1;
7935                         rss_desc->queue[0] = queue->index;
7936                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7937                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7938                         break;
7939                 case RTE_FLOW_ACTION_TYPE_RSS:
7940                         rss = actions->conf;
7941                         memcpy(rss_desc->queue, rss->queue,
7942                                rss->queue_num * sizeof(uint16_t));
7943                         rss_desc->queue_num = rss->queue_num;
7944                         /* NULL RSS key indicates default RSS key. */
7945                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7946                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7947                         /*
7948                          * rss->level and rss.types should be set in advance
7949                          * when expanding items for RSS.
7950                          */
7951                         action_flags |= MLX5_FLOW_ACTION_RSS;
7952                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7953                         break;
7954                 case RTE_FLOW_ACTION_TYPE_AGE:
7955                 case RTE_FLOW_ACTION_TYPE_COUNT:
7956                         if (!dev_conf->devx) {
7957                                 return rte_flow_error_set
7958                                               (error, ENOTSUP,
7959                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7960                                                NULL,
7961                                                "count action not supported");
7962                         }
7963                         /* Save information first, will apply later. */
7964                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7965                                 count = action->conf;
7966                         else
7967                                 age = action->conf;
7968                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7969                         break;
7970                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7971                         dev_flow->dv.actions[actions_n++] =
7972                                                 priv->sh->pop_vlan_action;
7973                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7974                         break;
7975                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7976                         if (!(action_flags &
7977                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7978                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7979                         vlan.eth_proto = rte_be_to_cpu_16
7980                              ((((const struct rte_flow_action_of_push_vlan *)
7981                                                    actions->conf)->ethertype));
7982                         found_action = mlx5_flow_find_action
7983                                         (actions + 1,
7984                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7985                         if (found_action)
7986                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7987                         found_action = mlx5_flow_find_action
7988                                         (actions + 1,
7989                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7990                         if (found_action)
7991                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7992                         if (flow_dv_create_action_push_vlan
7993                                             (dev, attr, &vlan, dev_flow, error))
7994                                 return -rte_errno;
7995                         dev_flow->dv.actions[actions_n++] =
7996                                         dev_flow->dv.push_vlan_res->action;
7997                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7998                         break;
7999                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8000                         /* of_vlan_push action handled this action */
8001                         MLX5_ASSERT(action_flags &
8002                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8003                         break;
8004                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8005                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8006                                 break;
8007                         flow_dev_get_vlan_info_from_items(items, &vlan);
8008                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8009                         /* If no VLAN push - this is a modify header action */
8010                         if (flow_dv_convert_action_modify_vlan_vid
8011                                                 (mhdr_res, actions, error))
8012                                 return -rte_errno;
8013                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8014                         break;
8015                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8016                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8017                         if (flow_dv_create_action_l2_encap(dev, actions,
8018                                                            dev_flow,
8019                                                            attr->transfer,
8020                                                            error))
8021                                 return -rte_errno;
8022                         dev_flow->dv.actions[actions_n++] =
8023                                         dev_flow->dv.encap_decap->verbs_action;
8024                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8025                         break;
8026                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8027                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8028                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8029                                                            attr->transfer,
8030                                                            error))
8031                                 return -rte_errno;
8032                         dev_flow->dv.actions[actions_n++] =
8033                                         dev_flow->dv.encap_decap->verbs_action;
8034                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8035                         break;
8036                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8037                         /* Handle encap with preceding decap. */
8038                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8039                                 if (flow_dv_create_action_raw_encap
8040                                         (dev, actions, dev_flow, attr, error))
8041                                         return -rte_errno;
8042                                 dev_flow->dv.actions[actions_n++] =
8043                                         dev_flow->dv.encap_decap->verbs_action;
8044                         } else {
8045                                 /* Handle encap without preceding decap. */
8046                                 if (flow_dv_create_action_l2_encap
8047                                     (dev, actions, dev_flow, attr->transfer,
8048                                      error))
8049                                         return -rte_errno;
8050                                 dev_flow->dv.actions[actions_n++] =
8051                                         dev_flow->dv.encap_decap->verbs_action;
8052                         }
8053                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8054                         break;
8055                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8056                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8057                                 ;
8058                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8059                                 if (flow_dv_create_action_l2_decap
8060                                     (dev, dev_flow, attr->transfer, error))
8061                                         return -rte_errno;
8062                                 dev_flow->dv.actions[actions_n++] =
8063                                         dev_flow->dv.encap_decap->verbs_action;
8064                         }
8065                         /* If decap is followed by encap, handle it at encap. */
8066                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8067                         break;
8068                 case RTE_FLOW_ACTION_TYPE_JUMP:
8069                         jump_data = action->conf;
8070                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8071                                                        jump_data->group,
8072                                                        !!priv->fdb_def_rule,
8073                                                        &table, error);
8074                         if (ret)
8075                                 return ret;
8076                         tbl = flow_dv_tbl_resource_get(dev, table,
8077                                                        attr->egress,
8078                                                        attr->transfer, error);
8079                         if (!tbl)
8080                                 return rte_flow_error_set
8081                                                 (error, errno,
8082                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8083                                                  NULL,
8084                                                  "cannot create jump action.");
8085                         if (flow_dv_jump_tbl_resource_register
8086                             (dev, tbl, dev_flow, error)) {
8087                                 flow_dv_tbl_resource_release(dev, tbl);
8088                                 return rte_flow_error_set
8089                                                 (error, errno,
8090                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8091                                                  NULL,
8092                                                  "cannot create jump action.");
8093                         }
8094                         dev_flow->dv.actions[actions_n++] =
8095                                         dev_flow->dv.jump->action;
8096                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8097                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8098                         break;
8099                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8100                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8101                         if (flow_dv_convert_action_modify_mac
8102                                         (mhdr_res, actions, error))
8103                                 return -rte_errno;
8104                         action_flags |= actions->type ==
8105                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8106                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8107                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8108                         break;
8109                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8110                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8111                         if (flow_dv_convert_action_modify_ipv4
8112                                         (mhdr_res, actions, error))
8113                                 return -rte_errno;
8114                         action_flags |= actions->type ==
8115                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8116                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8117                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8118                         break;
8119                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8120                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8121                         if (flow_dv_convert_action_modify_ipv6
8122                                         (mhdr_res, actions, error))
8123                                 return -rte_errno;
8124                         action_flags |= actions->type ==
8125                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8126                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8127                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8128                         break;
8129                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8130                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8131                         if (flow_dv_convert_action_modify_tp
8132                                         (mhdr_res, actions, items,
8133                                          &flow_attr, dev_flow, !!(action_flags &
8134                                          MLX5_FLOW_ACTION_DECAP), error))
8135                                 return -rte_errno;
8136                         action_flags |= actions->type ==
8137                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8138                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8139                                         MLX5_FLOW_ACTION_SET_TP_DST;
8140                         break;
8141                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8142                         if (flow_dv_convert_action_modify_dec_ttl
8143                                         (mhdr_res, items, &flow_attr, dev_flow,
8144                                          !!(action_flags &
8145                                          MLX5_FLOW_ACTION_DECAP), error))
8146                                 return -rte_errno;
8147                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8148                         break;
8149                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8150                         if (flow_dv_convert_action_modify_ttl
8151                                         (mhdr_res, actions, items, &flow_attr,
8152                                          dev_flow, !!(action_flags &
8153                                          MLX5_FLOW_ACTION_DECAP), error))
8154                                 return -rte_errno;
8155                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8156                         break;
8157                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8158                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8159                         if (flow_dv_convert_action_modify_tcp_seq
8160                                         (mhdr_res, actions, error))
8161                                 return -rte_errno;
8162                         action_flags |= actions->type ==
8163                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8164                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8165                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8166                         break;
8167
8168                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8169                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8170                         if (flow_dv_convert_action_modify_tcp_ack
8171                                         (mhdr_res, actions, error))
8172                                 return -rte_errno;
8173                         action_flags |= actions->type ==
8174                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8175                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8176                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8177                         break;
8178                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8179                         if (flow_dv_convert_action_set_reg
8180                                         (mhdr_res, actions, error))
8181                                 return -rte_errno;
8182                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8183                         break;
8184                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8185                         if (flow_dv_convert_action_copy_mreg
8186                                         (dev, mhdr_res, actions, error))
8187                                 return -rte_errno;
8188                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8189                         break;
8190                 case RTE_FLOW_ACTION_TYPE_METER:
8191                         mtr = actions->conf;
8192                         if (!flow->meter) {
8193                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8194                                                             attr, error);
8195                                 if (!fm)
8196                                         return rte_flow_error_set(error,
8197                                                 rte_errno,
8198                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8199                                                 NULL,
8200                                                 "meter not found "
8201                                                 "or invalid parameters");
8202                                 flow->meter = fm->idx;
8203                         }
8204                         /* Set the meter action. */
8205                         if (!fm) {
8206                                 fm = mlx5_ipool_get(priv->sh->ipool
8207                                                 [MLX5_IPOOL_MTR], flow->meter);
8208                                 if (!fm)
8209                                         return rte_flow_error_set(error,
8210                                                 rte_errno,
8211                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8212                                                 NULL,
8213                                                 "meter not found "
8214                                                 "or invalid parameters");
8215                         }
8216                         dev_flow->dv.actions[actions_n++] =
8217                                 fm->mfts->meter_action;
8218                         action_flags |= MLX5_FLOW_ACTION_METER;
8219                         break;
8220                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8221                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8222                                                               actions, error))
8223                                 return -rte_errno;
8224                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8225                         break;
8226                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8227                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8228                                                               actions, error))
8229                                 return -rte_errno;
8230                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8231                         break;
8232                 case RTE_FLOW_ACTION_TYPE_END:
8233                         actions_end = true;
8234                         if (mhdr_res->actions_num) {
8235                                 /* create modify action if needed. */
8236                                 if (flow_dv_modify_hdr_resource_register
8237                                         (dev, mhdr_res, dev_flow, error))
8238                                         return -rte_errno;
8239                                 dev_flow->dv.actions[modify_action_position] =
8240                                         handle->dvh.modify_hdr->verbs_action;
8241                         }
8242                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8243                                 flow->counter =
8244                                         flow_dv_translate_create_counter(dev,
8245                                                 dev_flow, count, age);
8246
8247                                 if (!flow->counter)
8248                                         return rte_flow_error_set
8249                                                 (error, rte_errno,
8250                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8251                                                 NULL,
8252                                                 "cannot create counter"
8253                                                 " object.");
8254                                 dev_flow->dv.actions[actions_n++] =
8255                                           (flow_dv_counter_get_by_idx(dev,
8256                                           flow->counter, NULL))->action;
8257                         }
8258                         break;
8259                 default:
8260                         break;
8261                 }
8262                 if (mhdr_res->actions_num &&
8263                     modify_action_position == UINT32_MAX)
8264                         modify_action_position = actions_n++;
8265         }
8266         dev_flow->dv.actions_n = actions_n;
8267         dev_flow->act_flags = action_flags;
8268         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8269                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8270                 int item_type = items->type;
8271
8272                 switch (item_type) {
8273                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8274                         flow_dv_translate_item_port_id(dev, match_mask,
8275                                                        match_value, items);
8276                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8277                         break;
8278                 case RTE_FLOW_ITEM_TYPE_ETH:
8279                         flow_dv_translate_item_eth(match_mask, match_value,
8280                                                    items, tunnel,
8281                                                    dev_flow->dv.group);
8282                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8283                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8284                                              MLX5_FLOW_LAYER_OUTER_L2;
8285                         break;
8286                 case RTE_FLOW_ITEM_TYPE_VLAN:
8287                         flow_dv_translate_item_vlan(dev_flow,
8288                                                     match_mask, match_value,
8289                                                     items, tunnel,
8290                                                     dev_flow->dv.group);
8291                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8292                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8293                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8294                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8295                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8296                         break;
8297                 case RTE_FLOW_ITEM_TYPE_IPV4:
8298                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8299                                                   &item_flags, &tunnel);
8300                         flow_dv_translate_item_ipv4(match_mask, match_value,
8301                                                     items, item_flags, tunnel,
8302                                                     dev_flow->dv.group);
8303                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8304                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8305                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8306                         if (items->mask != NULL &&
8307                             ((const struct rte_flow_item_ipv4 *)
8308                              items->mask)->hdr.next_proto_id) {
8309                                 next_protocol =
8310                                         ((const struct rte_flow_item_ipv4 *)
8311                                          (items->spec))->hdr.next_proto_id;
8312                                 next_protocol &=
8313                                         ((const struct rte_flow_item_ipv4 *)
8314                                          (items->mask))->hdr.next_proto_id;
8315                         } else {
8316                                 /* Reset for inner layer. */
8317                                 next_protocol = 0xff;
8318                         }
8319                         break;
8320                 case RTE_FLOW_ITEM_TYPE_IPV6:
8321                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8322                                                   &item_flags, &tunnel);
8323                         flow_dv_translate_item_ipv6(match_mask, match_value,
8324                                                     items, item_flags, tunnel,
8325                                                     dev_flow->dv.group);
8326                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8327                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8328                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8329                         if (items->mask != NULL &&
8330                             ((const struct rte_flow_item_ipv6 *)
8331                              items->mask)->hdr.proto) {
8332                                 next_protocol =
8333                                         ((const struct rte_flow_item_ipv6 *)
8334                                          items->spec)->hdr.proto;
8335                                 next_protocol &=
8336                                         ((const struct rte_flow_item_ipv6 *)
8337                                          items->mask)->hdr.proto;
8338                         } else {
8339                                 /* Reset for inner layer. */
8340                                 next_protocol = 0xff;
8341                         }
8342                         break;
8343                 case RTE_FLOW_ITEM_TYPE_TCP:
8344                         flow_dv_translate_item_tcp(match_mask, match_value,
8345                                                    items, tunnel);
8346                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8347                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8348                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8349                         break;
8350                 case RTE_FLOW_ITEM_TYPE_UDP:
8351                         flow_dv_translate_item_udp(match_mask, match_value,
8352                                                    items, tunnel);
8353                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8354                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8355                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8356                         break;
8357                 case RTE_FLOW_ITEM_TYPE_GRE:
8358                         flow_dv_translate_item_gre(match_mask, match_value,
8359                                                    items, tunnel);
8360                         matcher.priority = rss_desc->level >= 2 ?
8361                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8362                         last_item = MLX5_FLOW_LAYER_GRE;
8363                         break;
8364                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8365                         flow_dv_translate_item_gre_key(match_mask,
8366                                                        match_value, items);
8367                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8368                         break;
8369                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8370                         flow_dv_translate_item_nvgre(match_mask, match_value,
8371                                                      items, tunnel);
8372                         matcher.priority = rss_desc->level >= 2 ?
8373                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8374                         last_item = MLX5_FLOW_LAYER_GRE;
8375                         break;
8376                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8377                         flow_dv_translate_item_vxlan(match_mask, match_value,
8378                                                      items, tunnel);
8379                         matcher.priority = rss_desc->level >= 2 ?
8380                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8381                         last_item = MLX5_FLOW_LAYER_VXLAN;
8382                         break;
8383                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8384                         flow_dv_translate_item_vxlan_gpe(match_mask,
8385                                                          match_value, items,
8386                                                          tunnel);
8387                         matcher.priority = rss_desc->level >= 2 ?
8388                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8389                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8390                         break;
8391                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8392                         flow_dv_translate_item_geneve(match_mask, match_value,
8393                                                       items, tunnel);
8394                         matcher.priority = rss_desc->level >= 2 ?
8395                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8396                         last_item = MLX5_FLOW_LAYER_GENEVE;
8397                         break;
8398                 case RTE_FLOW_ITEM_TYPE_MPLS:
8399                         flow_dv_translate_item_mpls(match_mask, match_value,
8400                                                     items, last_item, tunnel);
8401                         matcher.priority = rss_desc->level >= 2 ?
8402                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8403                         last_item = MLX5_FLOW_LAYER_MPLS;
8404                         break;
8405                 case RTE_FLOW_ITEM_TYPE_MARK:
8406                         flow_dv_translate_item_mark(dev, match_mask,
8407                                                     match_value, items);
8408                         last_item = MLX5_FLOW_ITEM_MARK;
8409                         break;
8410                 case RTE_FLOW_ITEM_TYPE_META:
8411                         flow_dv_translate_item_meta(dev, match_mask,
8412                                                     match_value, attr, items);
8413                         last_item = MLX5_FLOW_ITEM_METADATA;
8414                         break;
8415                 case RTE_FLOW_ITEM_TYPE_ICMP:
8416                         flow_dv_translate_item_icmp(match_mask, match_value,
8417                                                     items, tunnel);
8418                         last_item = MLX5_FLOW_LAYER_ICMP;
8419                         break;
8420                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8421                         flow_dv_translate_item_icmp6(match_mask, match_value,
8422                                                       items, tunnel);
8423                         last_item = MLX5_FLOW_LAYER_ICMP6;
8424                         break;
8425                 case RTE_FLOW_ITEM_TYPE_TAG:
8426                         flow_dv_translate_item_tag(dev, match_mask,
8427                                                    match_value, items);
8428                         last_item = MLX5_FLOW_ITEM_TAG;
8429                         break;
8430                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8431                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8432                                                         match_value, items);
8433                         last_item = MLX5_FLOW_ITEM_TAG;
8434                         break;
8435                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8436                         flow_dv_translate_item_tx_queue(dev, match_mask,
8437                                                         match_value,
8438                                                         items);
8439                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8440                         break;
8441                 case RTE_FLOW_ITEM_TYPE_GTP:
8442                         flow_dv_translate_item_gtp(match_mask, match_value,
8443                                                    items, tunnel);
8444                         matcher.priority = rss_desc->level >= 2 ?
8445                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8446                         last_item = MLX5_FLOW_LAYER_GTP;
8447                         break;
8448                 default:
8449                         break;
8450                 }
8451                 item_flags |= last_item;
8452         }
8453         /*
8454          * When E-Switch mode is enabled, we have two cases where we need to
8455          * set the source port manually.
8456          * The first one, is in case of Nic steering rule, and the second is
8457          * E-Switch rule where no port_id item was found. In both cases
8458          * the source port is set according the current port in use.
8459          */
8460         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8461             (priv->representor || priv->master)) {
8462                 if (flow_dv_translate_item_port_id(dev, match_mask,
8463                                                    match_value, NULL))
8464                         return -rte_errno;
8465         }
8466 #ifdef RTE_LIBRTE_MLX5_DEBUG
8467         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8468                                               dev_flow->dv.value.buf));
8469 #endif
8470         /*
8471          * Layers may be already initialized from prefix flow if this dev_flow
8472          * is the suffix flow.
8473          */
8474         handle->layers |= item_flags;
8475         if (action_flags & MLX5_FLOW_ACTION_RSS)
8476                 flow_dv_hashfields_set(dev_flow, rss_desc);
8477         /* Register matcher. */
8478         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8479                                     matcher.mask.size);
8480         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8481                                                      matcher.priority);
8482         /* reserved field no needs to be set to 0 here. */
8483         tbl_key.domain = attr->transfer;
8484         tbl_key.direction = attr->egress;
8485         tbl_key.table_id = dev_flow->dv.group;
8486         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8487                 return -rte_errno;
8488         return 0;
8489 }
8490
8491 /**
8492  * Apply the flow to the NIC, lock free,
8493  * (mutex should be acquired by caller).
8494  *
8495  * @param[in] dev
8496  *   Pointer to the Ethernet device structure.
8497  * @param[in, out] flow
8498  *   Pointer to flow structure.
8499  * @param[out] error
8500  *   Pointer to error structure.
8501  *
8502  * @return
8503  *   0 on success, a negative errno value otherwise and rte_errno is set.
8504  */
8505 static int
8506 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8507                 struct rte_flow_error *error)
8508 {
8509         struct mlx5_flow_dv_workspace *dv;
8510         struct mlx5_flow_handle *dh;
8511         struct mlx5_flow_handle_dv *dv_h;
8512         struct mlx5_flow *dev_flow;
8513         struct mlx5_priv *priv = dev->data->dev_private;
8514         uint32_t handle_idx;
8515         int n;
8516         int err;
8517         int idx;
8518
8519         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8520                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8521                 dv = &dev_flow->dv;
8522                 dh = dev_flow->handle;
8523                 dv_h = &dh->dvh;
8524                 n = dv->actions_n;
8525                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8526                         if (dv->transfer) {
8527                                 dv->actions[n++] = priv->sh->esw_drop_action;
8528                         } else {
8529                                 struct mlx5_hrxq *drop_hrxq;
8530                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8531                                 if (!drop_hrxq) {
8532                                         rte_flow_error_set
8533                                                 (error, errno,
8534                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8535                                                  NULL,
8536                                                  "cannot get drop hash queue");
8537                                         goto error;
8538                                 }
8539                                 /*
8540                                  * Drop queues will be released by the specify
8541                                  * mlx5_hrxq_drop_release() function. Assign
8542                                  * the special index to hrxq to mark the queue
8543                                  * has been allocated.
8544                                  */
8545                                 dh->rix_hrxq = UINT32_MAX;
8546                                 dv->actions[n++] = drop_hrxq->action;
8547                         }
8548                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8549                         struct mlx5_hrxq *hrxq;
8550                         uint32_t hrxq_idx;
8551                         struct mlx5_flow_rss_desc *rss_desc =
8552                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8553                                 [!!priv->flow_nested_idx];
8554
8555                         MLX5_ASSERT(rss_desc->queue_num);
8556                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8557                                                  MLX5_RSS_HASH_KEY_LEN,
8558                                                  dev_flow->hash_fields,
8559                                                  rss_desc->queue,
8560                                                  rss_desc->queue_num);
8561                         if (!hrxq_idx) {
8562                                 hrxq_idx = mlx5_hrxq_new
8563                                                 (dev, rss_desc->key,
8564                                                 MLX5_RSS_HASH_KEY_LEN,
8565                                                 dev_flow->hash_fields,
8566                                                 rss_desc->queue,
8567                                                 rss_desc->queue_num,
8568                                                 !!(dh->layers &
8569                                                 MLX5_FLOW_LAYER_TUNNEL));
8570                         }
8571                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8572                                               hrxq_idx);
8573                         if (!hrxq) {
8574                                 rte_flow_error_set
8575                                         (error, rte_errno,
8576                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8577                                          "cannot get hash queue");
8578                                 goto error;
8579                         }
8580                         dh->rix_hrxq = hrxq_idx;
8581                         dv->actions[n++] = hrxq->action;
8582                 }
8583                 dh->ib_flow =
8584                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8585                                                   (void *)&dv->value, n,
8586                                                   dv->actions);
8587                 if (!dh->ib_flow) {
8588                         rte_flow_error_set(error, errno,
8589                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8590                                            NULL,
8591                                            "hardware refuses to create flow");
8592                         goto error;
8593                 }
8594                 if (priv->vmwa_context &&
8595                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8596                         /*
8597                          * The rule contains the VLAN pattern.
8598                          * For VF we are going to create VLAN
8599                          * interface to make hypervisor set correct
8600                          * e-Switch vport context.
8601                          */
8602                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8603                 }
8604         }
8605         return 0;
8606 error:
8607         err = rte_errno; /* Save rte_errno before cleanup. */
8608         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8609                        handle_idx, dh, next) {
8610                 /* hrxq is union, don't clear it if the flag is not set. */
8611                 if (dh->rix_hrxq) {
8612                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8613                                 mlx5_hrxq_drop_release(dev);
8614                                 dh->rix_hrxq = 0;
8615                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8616                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8617                                 dh->rix_hrxq = 0;
8618                         }
8619                 }
8620                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8621                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8622         }
8623         rte_errno = err; /* Restore rte_errno. */
8624         return -rte_errno;
8625 }
8626
8627 /**
8628  * Release the flow matcher.
8629  *
8630  * @param dev
8631  *   Pointer to Ethernet device.
8632  * @param handle
8633  *   Pointer to mlx5_flow_handle.
8634  *
8635  * @return
8636  *   1 while a reference on it exists, 0 when freed.
8637  */
8638 static int
8639 flow_dv_matcher_release(struct rte_eth_dev *dev,
8640                         struct mlx5_flow_handle *handle)
8641 {
8642         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8643
8644         MLX5_ASSERT(matcher->matcher_object);
8645         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8646                 dev->data->port_id, (void *)matcher,
8647                 rte_atomic32_read(&matcher->refcnt));
8648         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8649                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8650                            (matcher->matcher_object));
8651                 LIST_REMOVE(matcher, next);
8652                 /* table ref-- in release interface. */
8653                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8654                 rte_free(matcher);
8655                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8656                         dev->data->port_id, (void *)matcher);
8657                 return 0;
8658         }
8659         return 1;
8660 }
8661
8662 /**
8663  * Release an encap/decap resource.
8664  *
8665  * @param dev
8666  *   Pointer to Ethernet device.
8667  * @param handle
8668  *   Pointer to mlx5_flow_handle.
8669  *
8670  * @return
8671  *   1 while a reference on it exists, 0 when freed.
8672  */
8673 static int
8674 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8675                                      struct mlx5_flow_handle *handle)
8676 {
8677         struct mlx5_priv *priv = dev->data->dev_private;
8678         uint32_t idx = handle->dvh.rix_encap_decap;
8679         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8680
8681         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8682                          idx);
8683         if (!cache_resource)
8684                 return 0;
8685         MLX5_ASSERT(cache_resource->verbs_action);
8686         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8687                 (void *)cache_resource,
8688                 rte_atomic32_read(&cache_resource->refcnt));
8689         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8690                 claim_zero(mlx5_glue->destroy_flow_action
8691                                 (cache_resource->verbs_action));
8692                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8693                              &priv->sh->encaps_decaps, idx,
8694                              cache_resource, next);
8695                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8696                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8697                         (void *)cache_resource);
8698                 return 0;
8699         }
8700         return 1;
8701 }
8702
8703 /**
8704  * Release an jump to table action resource.
8705  *
8706  * @param dev
8707  *   Pointer to Ethernet device.
8708  * @param handle
8709  *   Pointer to mlx5_flow_handle.
8710  *
8711  * @return
8712  *   1 while a reference on it exists, 0 when freed.
8713  */
8714 static int
8715 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8716                                   struct mlx5_flow_handle *handle)
8717 {
8718         struct mlx5_priv *priv = dev->data->dev_private;
8719         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8720         struct mlx5_flow_tbl_data_entry *tbl_data;
8721
8722         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8723                              handle->rix_jump);
8724         if (!tbl_data)
8725                 return 0;
8726         cache_resource = &tbl_data->jump;
8727         MLX5_ASSERT(cache_resource->action);
8728         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8729                 (void *)cache_resource,
8730                 rte_atomic32_read(&cache_resource->refcnt));
8731         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8732                 claim_zero(mlx5_glue->destroy_flow_action
8733                                 (cache_resource->action));
8734                 /* jump action memory free is inside the table release. */
8735                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8736                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8737                         (void *)cache_resource);
8738                 return 0;
8739         }
8740         return 1;
8741 }
8742
8743 /**
8744  * Release a modify-header resource.
8745  *
8746  * @param handle
8747  *   Pointer to mlx5_flow_handle.
8748  *
8749  * @return
8750  *   1 while a reference on it exists, 0 when freed.
8751  */
8752 static int
8753 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8754 {
8755         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8756                                                         handle->dvh.modify_hdr;
8757
8758         MLX5_ASSERT(cache_resource->verbs_action);
8759         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8760                 (void *)cache_resource,
8761                 rte_atomic32_read(&cache_resource->refcnt));
8762         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8763                 claim_zero(mlx5_glue->destroy_flow_action
8764                                 (cache_resource->verbs_action));
8765                 LIST_REMOVE(cache_resource, next);
8766                 rte_free(cache_resource);
8767                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8768                         (void *)cache_resource);
8769                 return 0;
8770         }
8771         return 1;
8772 }
8773
8774 /**
8775  * Release port ID action resource.
8776  *
8777  * @param dev
8778  *   Pointer to Ethernet device.
8779  * @param handle
8780  *   Pointer to mlx5_flow_handle.
8781  *
8782  * @return
8783  *   1 while a reference on it exists, 0 when freed.
8784  */
8785 static int
8786 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8787                                         struct mlx5_flow_handle *handle)
8788 {
8789         struct mlx5_priv *priv = dev->data->dev_private;
8790         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8791         uint32_t idx = handle->rix_port_id_action;
8792
8793         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8794                                         idx);
8795         if (!cache_resource)
8796                 return 0;
8797         MLX5_ASSERT(cache_resource->action);
8798         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8799                 (void *)cache_resource,
8800                 rte_atomic32_read(&cache_resource->refcnt));
8801         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8802                 claim_zero(mlx5_glue->destroy_flow_action
8803                                 (cache_resource->action));
8804                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8805                              &priv->sh->port_id_action_list, idx,
8806                              cache_resource, next);
8807                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8808                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8809                         (void *)cache_resource);
8810                 return 0;
8811         }
8812         return 1;
8813 }
8814
8815 /**
8816  * Release push vlan action resource.
8817  *
8818  * @param dev
8819  *   Pointer to Ethernet device.
8820  * @param handle
8821  *   Pointer to mlx5_flow_handle.
8822  *
8823  * @return
8824  *   1 while a reference on it exists, 0 when freed.
8825  */
8826 static int
8827 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8828                                           struct mlx5_flow_handle *handle)
8829 {
8830         struct mlx5_priv *priv = dev->data->dev_private;
8831         uint32_t idx = handle->dvh.rix_push_vlan;
8832         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8833
8834         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8835                                         idx);
8836         if (!cache_resource)
8837                 return 0;
8838         MLX5_ASSERT(cache_resource->action);
8839         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8840                 (void *)cache_resource,
8841                 rte_atomic32_read(&cache_resource->refcnt));
8842         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8843                 claim_zero(mlx5_glue->destroy_flow_action
8844                                 (cache_resource->action));
8845                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8846                              &priv->sh->push_vlan_action_list, idx,
8847                              cache_resource, next);
8848                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8849                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8850                         (void *)cache_resource);
8851                 return 0;
8852         }
8853         return 1;
8854 }
8855
8856 /**
8857  * Release the fate resource.
8858  *
8859  * @param dev
8860  *   Pointer to Ethernet device.
8861  * @param handle
8862  *   Pointer to mlx5_flow_handle.
8863  */
8864 static void
8865 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8866                                struct mlx5_flow_handle *handle)
8867 {
8868         if (!handle->rix_fate)
8869                 return;
8870         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8871                 mlx5_hrxq_drop_release(dev);
8872         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8873                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8874         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8875                 flow_dv_jump_tbl_resource_release(dev, handle);
8876         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8877                 flow_dv_port_id_action_resource_release(dev, handle);
8878         else
8879                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8880         handle->rix_fate = 0;
8881 }
8882
8883 /**
8884  * Remove the flow from the NIC but keeps it in memory.
8885  * Lock free, (mutex should be acquired by caller).
8886  *
8887  * @param[in] dev
8888  *   Pointer to Ethernet device.
8889  * @param[in, out] flow
8890  *   Pointer to flow structure.
8891  */
8892 static void
8893 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8894 {
8895         struct mlx5_flow_handle *dh;
8896         uint32_t handle_idx;
8897         struct mlx5_priv *priv = dev->data->dev_private;
8898
8899         if (!flow)
8900                 return;
8901         handle_idx = flow->dev_handles;
8902         while (handle_idx) {
8903                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8904                                     handle_idx);
8905                 if (!dh)
8906                         return;
8907                 if (dh->ib_flow) {
8908                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8909                         dh->ib_flow = NULL;
8910                 }
8911                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8912                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8913                         flow_dv_fate_resource_release(dev, dh);
8914                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8915                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8916                 handle_idx = dh->next.next;
8917         }
8918 }
8919
8920 /**
8921  * Remove the flow from the NIC and the memory.
8922  * Lock free, (mutex should be acquired by caller).
8923  *
8924  * @param[in] dev
8925  *   Pointer to the Ethernet device structure.
8926  * @param[in, out] flow
8927  *   Pointer to flow structure.
8928  */
8929 static void
8930 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8931 {
8932         struct mlx5_flow_handle *dev_handle;
8933         struct mlx5_priv *priv = dev->data->dev_private;
8934
8935         if (!flow)
8936                 return;
8937         __flow_dv_remove(dev, flow);
8938         if (flow->counter) {
8939                 flow_dv_counter_release(dev, flow->counter);
8940                 flow->counter = 0;
8941         }
8942         if (flow->meter) {
8943                 struct mlx5_flow_meter *fm;
8944
8945                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8946                                     flow->meter);
8947                 if (fm)
8948                         mlx5_flow_meter_detach(fm);
8949                 flow->meter = 0;
8950         }
8951         while (flow->dev_handles) {
8952                 uint32_t tmp_idx = flow->dev_handles;
8953
8954                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8955                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8956                 if (!dev_handle)
8957                         return;
8958                 flow->dev_handles = dev_handle->next.next;
8959                 if (dev_handle->dvh.matcher)
8960                         flow_dv_matcher_release(dev, dev_handle);
8961                 if (dev_handle->dvh.rix_encap_decap)
8962                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8963                 if (dev_handle->dvh.modify_hdr)
8964                         flow_dv_modify_hdr_resource_release(dev_handle);
8965                 if (dev_handle->dvh.rix_push_vlan)
8966                         flow_dv_push_vlan_action_resource_release(dev,
8967                                                                   dev_handle);
8968                 if (dev_handle->dvh.rix_tag)
8969                         flow_dv_tag_release(dev,
8970                                             dev_handle->dvh.rix_tag);
8971                 flow_dv_fate_resource_release(dev, dev_handle);
8972                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8973                            tmp_idx);
8974         }
8975 }
8976
8977 /**
8978  * Query a dv flow  rule for its statistics via devx.
8979  *
8980  * @param[in] dev
8981  *   Pointer to Ethernet device.
8982  * @param[in] flow
8983  *   Pointer to the sub flow.
8984  * @param[out] data
8985  *   data retrieved by the query.
8986  * @param[out] error
8987  *   Perform verbose error reporting if not NULL.
8988  *
8989  * @return
8990  *   0 on success, a negative errno value otherwise and rte_errno is set.
8991  */
8992 static int
8993 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8994                     void *data, struct rte_flow_error *error)
8995 {
8996         struct mlx5_priv *priv = dev->data->dev_private;
8997         struct rte_flow_query_count *qc = data;
8998
8999         if (!priv->config.devx)
9000                 return rte_flow_error_set(error, ENOTSUP,
9001                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9002                                           NULL,
9003                                           "counters are not supported");
9004         if (flow->counter) {
9005                 uint64_t pkts, bytes;
9006                 struct mlx5_flow_counter *cnt;
9007
9008                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9009                                                  NULL);
9010                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9011                                                &bytes);
9012
9013                 if (err)
9014                         return rte_flow_error_set(error, -err,
9015                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9016                                         NULL, "cannot read counters");
9017                 qc->hits_set = 1;
9018                 qc->bytes_set = 1;
9019                 qc->hits = pkts - cnt->hits;
9020                 qc->bytes = bytes - cnt->bytes;
9021                 if (qc->reset) {
9022                         cnt->hits = pkts;
9023                         cnt->bytes = bytes;
9024                 }
9025                 return 0;
9026         }
9027         return rte_flow_error_set(error, EINVAL,
9028                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9029                                   NULL,
9030                                   "counters are not available");
9031 }
9032
9033 /**
9034  * Query a flow.
9035  *
9036  * @see rte_flow_query()
9037  * @see rte_flow_ops
9038  */
9039 static int
9040 flow_dv_query(struct rte_eth_dev *dev,
9041               struct rte_flow *flow __rte_unused,
9042               const struct rte_flow_action *actions __rte_unused,
9043               void *data __rte_unused,
9044               struct rte_flow_error *error __rte_unused)
9045 {
9046         int ret = -EINVAL;
9047
9048         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9049                 switch (actions->type) {
9050                 case RTE_FLOW_ACTION_TYPE_VOID:
9051                         break;
9052                 case RTE_FLOW_ACTION_TYPE_COUNT:
9053                         ret = flow_dv_query_count(dev, flow, data, error);
9054                         break;
9055                 default:
9056                         return rte_flow_error_set(error, ENOTSUP,
9057                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9058                                                   actions,
9059                                                   "action not supported");
9060                 }
9061         }
9062         return ret;
9063 }
9064
9065 /**
9066  * Destroy the meter table set.
9067  * Lock free, (mutex should be acquired by caller).
9068  *
9069  * @param[in] dev
9070  *   Pointer to Ethernet device.
9071  * @param[in] tbl
9072  *   Pointer to the meter table set.
9073  *
9074  * @return
9075  *   Always 0.
9076  */
9077 static int
9078 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9079                         struct mlx5_meter_domains_infos *tbl)
9080 {
9081         struct mlx5_priv *priv = dev->data->dev_private;
9082         struct mlx5_meter_domains_infos *mtd =
9083                                 (struct mlx5_meter_domains_infos *)tbl;
9084
9085         if (!mtd || !priv->config.dv_flow_en)
9086                 return 0;
9087         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9088                 claim_zero(mlx5_glue->dv_destroy_flow
9089                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9090         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9091                 claim_zero(mlx5_glue->dv_destroy_flow
9092                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9093         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9094                 claim_zero(mlx5_glue->dv_destroy_flow
9095                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9096         if (mtd->egress.color_matcher)
9097                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9098                           (mtd->egress.color_matcher));
9099         if (mtd->egress.any_matcher)
9100                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9101                           (mtd->egress.any_matcher));
9102         if (mtd->egress.tbl)
9103                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9104         if (mtd->egress.sfx_tbl)
9105                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9106         if (mtd->ingress.color_matcher)
9107                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9108                           (mtd->ingress.color_matcher));
9109         if (mtd->ingress.any_matcher)
9110                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9111                           (mtd->ingress.any_matcher));
9112         if (mtd->ingress.tbl)
9113                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9114         if (mtd->ingress.sfx_tbl)
9115                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9116         if (mtd->transfer.color_matcher)
9117                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9118                           (mtd->transfer.color_matcher));
9119         if (mtd->transfer.any_matcher)
9120                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9121                           (mtd->transfer.any_matcher));
9122         if (mtd->transfer.tbl)
9123                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9124         if (mtd->transfer.sfx_tbl)
9125                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9126         if (mtd->drop_actn)
9127                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9128         rte_free(mtd);
9129         return 0;
9130 }
9131
9132 /* Number of meter flow actions, count and jump or count and drop. */
9133 #define METER_ACTIONS 2
9134
9135 /**
9136  * Create specify domain meter table and suffix table.
9137  *
9138  * @param[in] dev
9139  *   Pointer to Ethernet device.
9140  * @param[in,out] mtb
9141  *   Pointer to DV meter table set.
9142  * @param[in] egress
9143  *   Table attribute.
9144  * @param[in] transfer
9145  *   Table attribute.
9146  * @param[in] color_reg_c_idx
9147  *   Reg C index for color match.
9148  *
9149  * @return
9150  *   0 on success, -1 otherwise and rte_errno is set.
9151  */
9152 static int
9153 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9154                            struct mlx5_meter_domains_infos *mtb,
9155                            uint8_t egress, uint8_t transfer,
9156                            uint32_t color_reg_c_idx)
9157 {
9158         struct mlx5_priv *priv = dev->data->dev_private;
9159         struct mlx5_dev_ctx_shared *sh = priv->sh;
9160         struct mlx5_flow_dv_match_params mask = {
9161                 .size = sizeof(mask.buf),
9162         };
9163         struct mlx5_flow_dv_match_params value = {
9164                 .size = sizeof(value.buf),
9165         };
9166         struct mlx5dv_flow_matcher_attr dv_attr = {
9167                 .type = IBV_FLOW_ATTR_NORMAL,
9168                 .priority = 0,
9169                 .match_criteria_enable = 0,
9170                 .match_mask = (void *)&mask,
9171         };
9172         void *actions[METER_ACTIONS];
9173         struct mlx5_meter_domain_info *dtb;
9174         struct rte_flow_error error;
9175         int i = 0;
9176
9177         if (transfer)
9178                 dtb = &mtb->transfer;
9179         else if (egress)
9180                 dtb = &mtb->egress;
9181         else
9182                 dtb = &mtb->ingress;
9183         /* Create the meter table with METER level. */
9184         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9185                                             egress, transfer, &error);
9186         if (!dtb->tbl) {
9187                 DRV_LOG(ERR, "Failed to create meter policer table.");
9188                 return -1;
9189         }
9190         /* Create the meter suffix table with SUFFIX level. */
9191         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9192                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9193                                             egress, transfer, &error);
9194         if (!dtb->sfx_tbl) {
9195                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9196                 return -1;
9197         }
9198         /* Create matchers, Any and Color. */
9199         dv_attr.priority = 3;
9200         dv_attr.match_criteria_enable = 0;
9201         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9202                                                              &dv_attr,
9203                                                              dtb->tbl->obj);
9204         if (!dtb->any_matcher) {
9205                 DRV_LOG(ERR, "Failed to create meter"
9206                              " policer default matcher.");
9207                 goto error_exit;
9208         }
9209         dv_attr.priority = 0;
9210         dv_attr.match_criteria_enable =
9211                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9212         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9213                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9214         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9215                                                                &dv_attr,
9216                                                                dtb->tbl->obj);
9217         if (!dtb->color_matcher) {
9218                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9219                 goto error_exit;
9220         }
9221         if (mtb->count_actns[RTE_MTR_DROPPED])
9222                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9223         actions[i++] = mtb->drop_actn;
9224         /* Default rule: lowest priority, match any, actions: drop. */
9225         dtb->policer_rules[RTE_MTR_DROPPED] =
9226                         mlx5_glue->dv_create_flow(dtb->any_matcher,
9227                                                  (void *)&value, i, actions);
9228         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9229                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9230                 goto error_exit;
9231         }
9232         return 0;
9233 error_exit:
9234         return -1;
9235 }
9236
9237 /**
9238  * Create the needed meter and suffix tables.
9239  * Lock free, (mutex should be acquired by caller).
9240  *
9241  * @param[in] dev
9242  *   Pointer to Ethernet device.
9243  * @param[in] fm
9244  *   Pointer to the flow meter.
9245  *
9246  * @return
9247  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9248  */
9249 static struct mlx5_meter_domains_infos *
9250 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9251                        const struct mlx5_flow_meter *fm)
9252 {
9253         struct mlx5_priv *priv = dev->data->dev_private;
9254         struct mlx5_meter_domains_infos *mtb;
9255         int ret;
9256         int i;
9257
9258         if (!priv->mtr_en) {
9259                 rte_errno = ENOTSUP;
9260                 return NULL;
9261         }
9262         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9263         if (!mtb) {
9264                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9265                 return NULL;
9266         }
9267         /* Create meter count actions */
9268         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9269                 struct mlx5_flow_counter *cnt;
9270                 if (!fm->policer_stats.cnt[i])
9271                         continue;
9272                 cnt = flow_dv_counter_get_by_idx(dev,
9273                       fm->policer_stats.cnt[i], NULL);
9274                 mtb->count_actns[i] = cnt->action;
9275         }
9276         /* Create drop action. */
9277         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9278         if (!mtb->drop_actn) {
9279                 DRV_LOG(ERR, "Failed to create drop action.");
9280                 goto error_exit;
9281         }
9282         /* Egress meter table. */
9283         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9284         if (ret) {
9285                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9286                 goto error_exit;
9287         }
9288         /* Ingress meter table. */
9289         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9290         if (ret) {
9291                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9292                 goto error_exit;
9293         }
9294         /* FDB meter table. */
9295         if (priv->config.dv_esw_en) {
9296                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9297                                                  priv->mtr_color_reg);
9298                 if (ret) {
9299                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9300                         goto error_exit;
9301                 }
9302         }
9303         return mtb;
9304 error_exit:
9305         flow_dv_destroy_mtr_tbl(dev, mtb);
9306         return NULL;
9307 }
9308
9309 /**
9310  * Destroy domain policer rule.
9311  *
9312  * @param[in] dt
9313  *   Pointer to domain table.
9314  */
9315 static void
9316 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9317 {
9318         int i;
9319
9320         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9321                 if (dt->policer_rules[i]) {
9322                         claim_zero(mlx5_glue->dv_destroy_flow
9323                                   (dt->policer_rules[i]));
9324                         dt->policer_rules[i] = NULL;
9325                 }
9326         }
9327         if (dt->jump_actn) {
9328                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9329                 dt->jump_actn = NULL;
9330         }
9331 }
9332
9333 /**
9334  * Destroy policer rules.
9335  *
9336  * @param[in] dev
9337  *   Pointer to Ethernet device.
9338  * @param[in] fm
9339  *   Pointer to flow meter structure.
9340  * @param[in] attr
9341  *   Pointer to flow attributes.
9342  *
9343  * @return
9344  *   Always 0.
9345  */
9346 static int
9347 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9348                               const struct mlx5_flow_meter *fm,
9349                               const struct rte_flow_attr *attr)
9350 {
9351         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9352
9353         if (!mtb)
9354                 return 0;
9355         if (attr->egress)
9356                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9357         if (attr->ingress)
9358                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9359         if (attr->transfer)
9360                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9361         return 0;
9362 }
9363
9364 /**
9365  * Create specify domain meter policer rule.
9366  *
9367  * @param[in] fm
9368  *   Pointer to flow meter structure.
9369  * @param[in] mtb
9370  *   Pointer to DV meter table set.
9371  * @param[in] mtr_reg_c
9372  *   Color match REG_C.
9373  *
9374  * @return
9375  *   0 on success, -1 otherwise.
9376  */
9377 static int
9378 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9379                                     struct mlx5_meter_domain_info *dtb,
9380                                     uint8_t mtr_reg_c)
9381 {
9382         struct mlx5_flow_dv_match_params matcher = {
9383                 .size = sizeof(matcher.buf),
9384         };
9385         struct mlx5_flow_dv_match_params value = {
9386                 .size = sizeof(value.buf),
9387         };
9388         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9389         void *actions[METER_ACTIONS];
9390         int i;
9391
9392         /* Create jump action. */
9393         if (!dtb->jump_actn)
9394                 dtb->jump_actn =
9395                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9396                                                         (dtb->sfx_tbl->obj);
9397         if (!dtb->jump_actn) {
9398                 DRV_LOG(ERR, "Failed to create policer jump action.");
9399                 goto error;
9400         }
9401         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9402                 int j = 0;
9403
9404                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9405                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9406                 if (mtb->count_actns[i])
9407                         actions[j++] = mtb->count_actns[i];
9408                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9409                         actions[j++] = mtb->drop_actn;
9410                 else
9411                         actions[j++] = dtb->jump_actn;
9412                 dtb->policer_rules[i] =
9413                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9414                                                  (void *)&value,
9415                                                   j, actions);
9416                 if (!dtb->policer_rules[i]) {
9417                         DRV_LOG(ERR, "Failed to create policer rule.");
9418                         goto error;
9419                 }
9420         }
9421         return 0;
9422 error:
9423         rte_errno = errno;
9424         return -1;
9425 }
9426
9427 /**
9428  * Create policer rules.
9429  *
9430  * @param[in] dev
9431  *   Pointer to Ethernet device.
9432  * @param[in] fm
9433  *   Pointer to flow meter structure.
9434  * @param[in] attr
9435  *   Pointer to flow attributes.
9436  *
9437  * @return
9438  *   0 on success, -1 otherwise.
9439  */
9440 static int
9441 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9442                              struct mlx5_flow_meter *fm,
9443                              const struct rte_flow_attr *attr)
9444 {
9445         struct mlx5_priv *priv = dev->data->dev_private;
9446         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9447         int ret;
9448
9449         if (attr->egress) {
9450                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9451                                                 priv->mtr_color_reg);
9452                 if (ret) {
9453                         DRV_LOG(ERR, "Failed to create egress policer.");
9454                         goto error;
9455                 }
9456         }
9457         if (attr->ingress) {
9458                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9459                                                 priv->mtr_color_reg);
9460                 if (ret) {
9461                         DRV_LOG(ERR, "Failed to create ingress policer.");
9462                         goto error;
9463                 }
9464         }
9465         if (attr->transfer) {
9466                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9467                                                 priv->mtr_color_reg);
9468                 if (ret) {
9469                         DRV_LOG(ERR, "Failed to create transfer policer.");
9470                         goto error;
9471                 }
9472         }
9473         return 0;
9474 error:
9475         flow_dv_destroy_policer_rules(dev, fm, attr);
9476         return -1;
9477 }
9478
9479 /**
9480  * Query a devx counter.
9481  *
9482  * @param[in] dev
9483  *   Pointer to the Ethernet device structure.
9484  * @param[in] cnt
9485  *   Index to the flow counter.
9486  * @param[in] clear
9487  *   Set to clear the counter statistics.
9488  * @param[out] pkts
9489  *   The statistics value of packets.
9490  * @param[out] bytes
9491  *   The statistics value of bytes.
9492  *
9493  * @return
9494  *   0 on success, otherwise return -1.
9495  */
9496 static int
9497 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9498                       uint64_t *pkts, uint64_t *bytes)
9499 {
9500         struct mlx5_priv *priv = dev->data->dev_private;
9501         struct mlx5_flow_counter *cnt;
9502         uint64_t inn_pkts, inn_bytes;
9503         int ret;
9504
9505         if (!priv->config.devx)
9506                 return -1;
9507
9508         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9509         if (ret)
9510                 return -1;
9511         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9512         *pkts = inn_pkts - cnt->hits;
9513         *bytes = inn_bytes - cnt->bytes;
9514         if (clear) {
9515                 cnt->hits = inn_pkts;
9516                 cnt->bytes = inn_bytes;
9517         }
9518         return 0;
9519 }
9520
9521 /**
9522  * Get aged-out flows.
9523  *
9524  * @param[in] dev
9525  *   Pointer to the Ethernet device structure.
9526  * @param[in] context
9527  *   The address of an array of pointers to the aged-out flows contexts.
9528  * @param[in] nb_contexts
9529  *   The length of context array pointers.
9530  * @param[out] error
9531  *   Perform verbose error reporting if not NULL. Initialized in case of
9532  *   error only.
9533  *
9534  * @return
9535  *   how many contexts get in success, otherwise negative errno value.
9536  *   if nb_contexts is 0, return the amount of all aged contexts.
9537  *   if nb_contexts is not 0 , return the amount of aged flows reported
9538  *   in the context array.
9539  * @note: only stub for now
9540  */
9541 static int
9542 flow_get_aged_flows(struct rte_eth_dev *dev,
9543                     void **context,
9544                     uint32_t nb_contexts,
9545                     struct rte_flow_error *error)
9546 {
9547         struct mlx5_priv *priv = dev->data->dev_private;
9548         struct mlx5_age_info *age_info;
9549         struct mlx5_age_param *age_param;
9550         struct mlx5_flow_counter *counter;
9551         int nb_flows = 0;
9552
9553         if (nb_contexts && !context)
9554                 return rte_flow_error_set(error, EINVAL,
9555                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9556                                           NULL,
9557                                           "Should assign at least one flow or"
9558                                           " context to get if nb_contexts != 0");
9559         age_info = GET_PORT_AGE_INFO(priv);
9560         rte_spinlock_lock(&age_info->aged_sl);
9561         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9562                 nb_flows++;
9563                 if (nb_contexts) {
9564                         age_param = MLX5_CNT_TO_AGE(counter);
9565                         context[nb_flows - 1] = age_param->context;
9566                         if (!(--nb_contexts))
9567                                 break;
9568                 }
9569         }
9570         rte_spinlock_unlock(&age_info->aged_sl);
9571         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9572         return nb_flows;
9573 }
9574
9575 /*
9576  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9577  */
9578 static int
9579 flow_dv_translate(struct rte_eth_dev *dev,
9580                   struct mlx5_flow *dev_flow,
9581                   const struct rte_flow_attr *attr,
9582                   const struct rte_flow_item items[],
9583                   const struct rte_flow_action actions[],
9584                   struct rte_flow_error *error)
9585 {
9586         int ret;
9587
9588         flow_dv_shared_lock(dev);
9589         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9590         flow_dv_shared_unlock(dev);
9591         return ret;
9592 }
9593
9594 /*
9595  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9596  */
9597 static int
9598 flow_dv_apply(struct rte_eth_dev *dev,
9599               struct rte_flow *flow,
9600               struct rte_flow_error *error)
9601 {
9602         int ret;
9603
9604         flow_dv_shared_lock(dev);
9605         ret = __flow_dv_apply(dev, flow, error);
9606         flow_dv_shared_unlock(dev);
9607         return ret;
9608 }
9609
9610 /*
9611  * Mutex-protected thunk to lock-free __flow_dv_remove().
9612  */
9613 static void
9614 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9615 {
9616         flow_dv_shared_lock(dev);
9617         __flow_dv_remove(dev, flow);
9618         flow_dv_shared_unlock(dev);
9619 }
9620
9621 /*
9622  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9623  */
9624 static void
9625 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9626 {
9627         flow_dv_shared_lock(dev);
9628         __flow_dv_destroy(dev, flow);
9629         flow_dv_shared_unlock(dev);
9630 }
9631
9632 /*
9633  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9634  */
9635 static uint32_t
9636 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9637 {
9638         uint32_t cnt;
9639
9640         flow_dv_shared_lock(dev);
9641         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9642         flow_dv_shared_unlock(dev);
9643         return cnt;
9644 }
9645
9646 /*
9647  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9648  */
9649 static void
9650 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9651 {
9652         flow_dv_shared_lock(dev);
9653         flow_dv_counter_release(dev, cnt);
9654         flow_dv_shared_unlock(dev);
9655 }
9656
9657 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9658         .validate = flow_dv_validate,
9659         .prepare = flow_dv_prepare,
9660         .translate = flow_dv_translate,
9661         .apply = flow_dv_apply,
9662         .remove = flow_dv_remove,
9663         .destroy = flow_dv_destroy,
9664         .query = flow_dv_query,
9665         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9666         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9667         .create_policer_rules = flow_dv_create_policer_rules,
9668         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9669         .counter_alloc = flow_dv_counter_allocate,
9670         .counter_free = flow_dv_counter_free,
9671         .counter_query = flow_dv_counter_query,
9672         .get_aged_flows = flow_get_aged_flows,
9673 };
9674
9675 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */