drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <rte_ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                       uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84
  85 /**
  86  * Initialize flow attributes structure according to flow items' types.
  87  *
  88  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  89  * mode. For tunnel mode, the items to be modified are the outermost ones.
  90  *
  91  * @param[in] item
  92  *   Pointer to item specification.
  93  * @param[out] attr
  94  *   Pointer to flow attributes structure.
  95  * @param[in] dev_flow
  96  *   Pointer to the sub flow.
  97  * @param[in] tunnel_decap
  98  *   Whether action is after tunnel decapsulation.
  99  */
 100 static void
 101 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 102                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 103 {
 104         uint64_t layers = dev_flow->handle->layers;
 105
 106         /*
 107          * If layers is already initialized, it means this dev_flow is the
 108          * suffix flow, the layers flags is set by the prefix flow. Need to
 109          * use the layer flags from prefix flow as the suffix flow may not
 110          * have the user defined items as the flow is split.
 111          */
 112         if (layers) {
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 114                         attr->ipv4 = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 116                         attr->ipv6 = 1;
 117                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 118                         attr->tcp = 1;
 119                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 120                         attr->udp = 1;
 121                 attr->valid = 1;
 122                 return;
 123         }
 124         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 125                 uint8_t next_protocol = 0xff;
 126                 switch (item->type) {
 127                 case RTE_FLOW_ITEM_TYPE_GRE:
 128                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 129                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 130                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 131                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 132                 case RTE_FLOW_ITEM_TYPE_MPLS:
 133                         if (tunnel_decap)
 134                                 attr->attr = 0;
 135                         break;
 136                 case RTE_FLOW_ITEM_TYPE_IPV4:
 137                         if (!attr->ipv6)
 138                                 attr->ipv4 = 1;
 139                         if (item->mask != NULL &&
 140                             ((const struct rte_flow_item_ipv4 *)
 141                             item->mask)->hdr.next_proto_id)
 142                                 next_protocol =
 143                                     ((const struct rte_flow_item_ipv4 *)
 144                                       (item->spec))->hdr.next_proto_id &
 145                                     ((const struct rte_flow_item_ipv4 *)
 146                                       (item->mask))->hdr.next_proto_id;
 147                         if ((next_protocol == IPPROTO_IPIP ||
 148                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 149                                 attr->attr = 0;
 150                         break;
 151                 case RTE_FLOW_ITEM_TYPE_IPV6:
 152                         if (!attr->ipv4)
 153                                 attr->ipv6 = 1;
 154                         if (item->mask != NULL &&
 155                             ((const struct rte_flow_item_ipv6 *)
 156                             item->mask)->hdr.proto)
 157                                 next_protocol =
 158                                     ((const struct rte_flow_item_ipv6 *)
 159                                       (item->spec))->hdr.proto &
 160                                     ((const struct rte_flow_item_ipv6 *)
 161                                       (item->mask))->hdr.proto;
 162                         if ((next_protocol == IPPROTO_IPIP ||
 163                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 164                                 attr->attr = 0;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_UDP:
 167                         if (!attr->tcp)
 168                                 attr->udp = 1;
 169                         break;
 170                 case RTE_FLOW_ITEM_TYPE_TCP:
 171                         if (!attr->udp)
 172                                 attr->tcp = 1;
 173                         break;
 174                 default:
 175                         break;
 176                 }
 177         }
 178         attr->valid = 1;
 179 }
 180
 181 /**
 182  * Convert rte_mtr_color to mlx5 color.
 183  *
 184  * @param[in] rcol
 185  *   rte_mtr_color.
 186  *
 187  * @return
 188  *   mlx5 color.
 189  */
 190 static int
 191 rte_col_2_mlx5_col(enum rte_color rcol)
 192 {
 193         switch (rcol) {
 194         case RTE_COLOR_GREEN:
 195                 return MLX5_FLOW_COLOR_GREEN;
 196         case RTE_COLOR_YELLOW:
 197                 return MLX5_FLOW_COLOR_YELLOW;
 198         case RTE_COLOR_RED:
 199                 return MLX5_FLOW_COLOR_RED;
 200         default:
 201                 break;
 202         }
 203         return MLX5_FLOW_COLOR_UNDEFINED;
 204 }
 205
 206 struct field_modify_info {
 207         uint32_t size; /* Size of field in protocol header, in bytes. */
 208         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 209         enum mlx5_modification_field id;
 210 };
 211
 212 struct field_modify_info modify_eth[] = {
 213         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 214         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 215         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 216         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 217         {0, 0, 0},
 218 };
 219
 220 struct field_modify_info modify_vlan_out_first_vid[] = {
 221         /* Size in bits !!! */
 222         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_ipv4[] = {
 227         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 228         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 229         {4, 12, MLX5_MODI_OUT_SIPV4},
 230         {4, 16, MLX5_MODI_OUT_DIPV4},
 231         {0, 0, 0},
 232 };
 233
 234 struct field_modify_info modify_ipv6[] = {
 235         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 236         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 237         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 238         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 239         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 240         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 241         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 242         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 243         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 244         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 245         {0, 0, 0},
 246 };
 247
 248 struct field_modify_info modify_udp[] = {
 249         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 250         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_tcp[] = {
 255         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 257         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 258         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 259         {0, 0, 0},
 260 };
 261
 262 static void
 263 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 264                           uint8_t next_protocol, uint64_t *item_flags,
 265                           int *tunnel)
 266 {
 267         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 268                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 269         if (next_protocol == IPPROTO_IPIP) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 271                 *tunnel = 1;
 272         }
 273         if (next_protocol == IPPROTO_IPV6) {
 274                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 275                 *tunnel = 1;
 276         }
 277 }
 278
 279 /**
 280  * Acquire the synchronizing object to protect multithreaded access
 281  * to shared dv context. Lock occurs only if context is actually
 282  * shared, i.e. we have multiport IB device and representors are
 283  * created.
 284  *
 285  * @param[in] dev
 286  *   Pointer to the rte_eth_dev structure.
 287  */
 288 static void
 289 flow_dv_shared_lock(struct rte_eth_dev *dev)
 290 {
 291         struct mlx5_priv *priv = dev->data->dev_private;
 292         struct mlx5_dev_ctx_shared *sh = priv->sh;
 293
 294         if (sh->refcnt > 1) {
 295                 int ret;
 296
 297                 ret = pthread_mutex_lock(&sh->dv_mutex);
 298                 MLX5_ASSERT(!ret);
 299                 (void)ret;
 300         }
 301 }
 302
 303 static void
 304 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 305 {
 306         struct mlx5_priv *priv = dev->data->dev_private;
 307         struct mlx5_dev_ctx_shared *sh = priv->sh;
 308
 309         if (sh->refcnt > 1) {
 310                 int ret;
 311
 312                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 313                 MLX5_ASSERT(!ret);
 314                 (void)ret;
 315         }
 316 }
 317
 318 /* Update VLAN's VID/PCP based on input rte_flow_action.
 319  *
 320  * @param[in] action
 321  *   Pointer to struct rte_flow_action.
 322  * @param[out] vlan
 323  *   Pointer to struct rte_vlan_hdr.
 324  */
 325 static void
 326 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 327                          struct rte_vlan_hdr *vlan)
 328 {
 329         uint16_t vlan_tci;
 330         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 331                 vlan_tci =
 332                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 333                                                action->conf)->vlan_pcp;
 334                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 335                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 336                 vlan->vlan_tci |= vlan_tci;
 337         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 338                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 339                 vlan->vlan_tci |= rte_be_to_cpu_16
 340                     (((const struct rte_flow_action_of_set_vlan_vid *)
 341                                              action->conf)->vlan_vid);
 342         }
 343 }
 344
 345 /**
 346  * Fetch 1, 2, 3 or 4 byte field from the byte array
 347  * and return as unsigned integer in host-endian format.
 348  *
 349  * @param[in] data
 350  *   Pointer to data array.
 351  * @param[in] size
 352  *   Size of field to extract.
 353  *
 354  * @return
 355  *   converted field in host endian format.
 356  */
 357 static inline uint32_t
 358 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 359 {
 360         uint32_t ret;
 361
 362         switch (size) {
 363         case 1:
 364                 ret = *data;
 365                 break;
 366         case 2:
 367                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 368                 break;
 369         case 3:
 370                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 371                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 372                 break;
 373         case 4:
 374                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 375                 break;
 376         default:
 377                 MLX5_ASSERT(false);
 378                 ret = 0;
 379                 break;
 380         }
 381         return ret;
 382 }
 383
 384 /**
 385  * Convert modify-header action to DV specification.
 386  *
 387  * Data length of each action is determined by provided field description
 388  * and the item mask. Data bit offset and width of each action is determined
 389  * by provided item mask.
 390  *
 391  * @param[in] item
 392  *   Pointer to item specification.
 393  * @param[in] field
 394  *   Pointer to field modification information.
 395  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 396  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 397  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 398  * @param[in] dcopy
 399  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 400  *   Negative offset value sets the same offset as source offset.
 401  *   size field is ignored, value is taken from source field.
 402  * @param[in,out] resource
 403  *   Pointer to the modify-header resource.
 404  * @param[in] type
 405  *   Type of modification.
 406  * @param[out] error
 407  *   Pointer to the error structure.
 408  *
 409  * @return
 410  *   0 on success, a negative errno value otherwise and rte_errno is set.
 411  */
 412 static int
 413 flow_dv_convert_modify_action(struct rte_flow_item *item,
 414                               struct field_modify_info *field,
 415                               struct field_modify_info *dcopy,
 416                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 417                               uint32_t type, struct rte_flow_error *error)
 418 {
 419         uint32_t i = resource->actions_num;
 420         struct mlx5_modification_cmd *actions = resource->actions;
 421
 422         /*
 423          * The item and mask are provided in big-endian format.
 424          * The fields should be presented as in big-endian format either.
 425          * Mask must be always present, it defines the actual field width.
 426          */
 427         MLX5_ASSERT(item->mask);
 428         MLX5_ASSERT(field->size);
 429         do {
 430                 unsigned int size_b;
 431                 unsigned int off_b;
 432                 uint32_t mask;
 433                 uint32_t data;
 434
 435                 if (i >= MLX5_MAX_MODIFY_NUM)
 436                         return rte_flow_error_set(error, EINVAL,
 437                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 438                                  "too many items to modify");
 439                 /* Fetch variable byte size mask from the array. */
 440                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 441                                            field->offset, field->size);
 442                 if (!mask) {
 443                         ++field;
 444                         continue;
 445                 }
 446                 /* Deduce actual data width in bits from mask value. */
 447                 off_b = rte_bsf32(mask);
 448                 size_b = sizeof(uint32_t) * CHAR_BIT -
 449                          off_b - __builtin_clz(mask);
 450                 MLX5_ASSERT(size_b);
 451                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 452                 actions[i] = (struct mlx5_modification_cmd) {
 453                         .action_type = type,
 454                         .field = field->id,
 455                         .offset = off_b,
 456                         .length = size_b,
 457                 };
 458                 /* Convert entire record to expected big-endian format. */
 459                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 460                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 461                         MLX5_ASSERT(dcopy);
 462                         actions[i].dst_field = dcopy->id;
 463                         actions[i].dst_offset =
 464                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 465                         /* Convert entire record to big-endian format. */
 466                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 467                 } else {
 468                         MLX5_ASSERT(item->spec);
 469                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 470                                                    field->offset, field->size);
 471                         /* Shift out the trailing masked bits from data. */
 472                         data = (data & mask) >> off_b;
 473                         actions[i].data1 = rte_cpu_to_be_32(data);
 474                 }
 475                 ++i;
 476                 ++field;
 477         } while (field->size);
 478         if (resource->actions_num == i)
 479                 return rte_flow_error_set(error, EINVAL,
 480                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 481                                           "invalid modification flow item");
 482         resource->actions_num = i;
 483         return 0;
 484 }
 485
 486 /**
 487  * Convert modify-header set IPv4 address action to DV specification.
 488  *
 489  * @param[in,out] resource
 490  *   Pointer to the modify-header resource.
 491  * @param[in] action
 492  *   Pointer to action specification.
 493  * @param[out] error
 494  *   Pointer to the error structure.
 495  *
 496  * @return
 497  *   0 on success, a negative errno value otherwise and rte_errno is set.
 498  */
 499 static int
 500 flow_dv_convert_action_modify_ipv4
 501                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 502                          const struct rte_flow_action *action,
 503                          struct rte_flow_error *error)
 504 {
 505         const struct rte_flow_action_set_ipv4 *conf =
 506                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 507         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 508         struct rte_flow_item_ipv4 ipv4;
 509         struct rte_flow_item_ipv4 ipv4_mask;
 510
 511         memset(&ipv4, 0, sizeof(ipv4));
 512         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 513         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 514                 ipv4.hdr.src_addr = conf->ipv4_addr;
 515                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 516         } else {
 517                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 518                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 519         }
 520         item.spec = &ipv4;
 521         item.mask = &ipv4_mask;
 522         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 523                                              MLX5_MODIFICATION_TYPE_SET, error);
 524 }
 525
 526 /**
 527  * Convert modify-header set IPv6 address action to DV specification.
 528  *
 529  * @param[in,out] resource
 530  *   Pointer to the modify-header resource.
 531  * @param[in] action
 532  *   Pointer to action specification.
 533  * @param[out] error
 534  *   Pointer to the error structure.
 535  *
 536  * @return
 537  *   0 on success, a negative errno value otherwise and rte_errno is set.
 538  */
 539 static int
 540 flow_dv_convert_action_modify_ipv6
 541                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 542                          const struct rte_flow_action *action,
 543                          struct rte_flow_error *error)
 544 {
 545         const struct rte_flow_action_set_ipv6 *conf =
 546                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 547         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 548         struct rte_flow_item_ipv6 ipv6;
 549         struct rte_flow_item_ipv6 ipv6_mask;
 550
 551         memset(&ipv6, 0, sizeof(ipv6));
 552         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 553         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 554                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 555                        sizeof(ipv6.hdr.src_addr));
 556                 memcpy(&ipv6_mask.hdr.src_addr,
 557                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 558                        sizeof(ipv6.hdr.src_addr));
 559         } else {
 560                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 561                        sizeof(ipv6.hdr.dst_addr));
 562                 memcpy(&ipv6_mask.hdr.dst_addr,
 563                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 564                        sizeof(ipv6.hdr.dst_addr));
 565         }
 566         item.spec = &ipv6;
 567         item.mask = &ipv6_mask;
 568         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 569                                              MLX5_MODIFICATION_TYPE_SET, error);
 570 }
 571
 572 /**
 573  * Convert modify-header set MAC address action to DV specification.
 574  *
 575  * @param[in,out] resource
 576  *   Pointer to the modify-header resource.
 577  * @param[in] action
 578  *   Pointer to action specification.
 579  * @param[out] error
 580  *   Pointer to the error structure.
 581  *
 582  * @return
 583  *   0 on success, a negative errno value otherwise and rte_errno is set.
 584  */
 585 static int
 586 flow_dv_convert_action_modify_mac
 587                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 588                          const struct rte_flow_action *action,
 589                          struct rte_flow_error *error)
 590 {
 591         const struct rte_flow_action_set_mac *conf =
 592                 (const struct rte_flow_action_set_mac *)(action->conf);
 593         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 594         struct rte_flow_item_eth eth;
 595         struct rte_flow_item_eth eth_mask;
 596
 597         memset(&eth, 0, sizeof(eth));
 598         memset(&eth_mask, 0, sizeof(eth_mask));
 599         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 600                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 601                        sizeof(eth.src.addr_bytes));
 602                 memcpy(&eth_mask.src.addr_bytes,
 603                        &rte_flow_item_eth_mask.src.addr_bytes,
 604                        sizeof(eth_mask.src.addr_bytes));
 605         } else {
 606                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 607                        sizeof(eth.dst.addr_bytes));
 608                 memcpy(&eth_mask.dst.addr_bytes,
 609                        &rte_flow_item_eth_mask.dst.addr_bytes,
 610                        sizeof(eth_mask.dst.addr_bytes));
 611         }
 612         item.spec = &eth;
 613         item.mask = &eth_mask;
 614         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 615                                              MLX5_MODIFICATION_TYPE_SET, error);
 616 }
 617
 618 /**
 619  * Convert modify-header set VLAN VID action to DV specification.
 620  *
 621  * @param[in,out] resource
 622  *   Pointer to the modify-header resource.
 623  * @param[in] action
 624  *   Pointer to action specification.
 625  * @param[out] error
 626  *   Pointer to the error structure.
 627  *
 628  * @return
 629  *   0 on success, a negative errno value otherwise and rte_errno is set.
 630  */
 631 static int
 632 flow_dv_convert_action_modify_vlan_vid
 633                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 634                          const struct rte_flow_action *action,
 635                          struct rte_flow_error *error)
 636 {
 637         const struct rte_flow_action_of_set_vlan_vid *conf =
 638                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 639         int i = resource->actions_num;
 640         struct mlx5_modification_cmd *actions = resource->actions;
 641         struct field_modify_info *field = modify_vlan_out_first_vid;
 642
 643         if (i >= MLX5_MAX_MODIFY_NUM)
 644                 return rte_flow_error_set(error, EINVAL,
 645                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 646                          "too many items to modify");
 647         actions[i] = (struct mlx5_modification_cmd) {
 648                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 649                 .field = field->id,
 650                 .length = field->size,
 651                 .offset = field->offset,
 652         };
 653         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 654         actions[i].data1 = conf->vlan_vid;
 655         actions[i].data1 = actions[i].data1 << 16;
 656         resource->actions_num = ++i;
 657         return 0;
 658 }
 659
 660 /**
 661  * Convert modify-header set TP action to DV specification.
 662  *
 663  * @param[in,out] resource
 664  *   Pointer to the modify-header resource.
 665  * @param[in] action
 666  *   Pointer to action specification.
 667  * @param[in] items
 668  *   Pointer to rte_flow_item objects list.
 669  * @param[in] attr
 670  *   Pointer to flow attributes structure.
 671  * @param[in] dev_flow
 672  *   Pointer to the sub flow.
 673  * @param[in] tunnel_decap
 674  *   Whether action is after tunnel decapsulation.
 675  * @param[out] error
 676  *   Pointer to the error structure.
 677  *
 678  * @return
 679  *   0 on success, a negative errno value otherwise and rte_errno is set.
 680  */
 681 static int
 682 flow_dv_convert_action_modify_tp
 683                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 684                          const struct rte_flow_action *action,
 685                          const struct rte_flow_item *items,
 686                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 687                          bool tunnel_decap, struct rte_flow_error *error)
 688 {
 689         const struct rte_flow_action_set_tp *conf =
 690                 (const struct rte_flow_action_set_tp *)(action->conf);
 691         struct rte_flow_item item;
 692         struct rte_flow_item_udp udp;
 693         struct rte_flow_item_udp udp_mask;
 694         struct rte_flow_item_tcp tcp;
 695         struct rte_flow_item_tcp tcp_mask;
 696         struct field_modify_info *field;
 697
 698         if (!attr->valid)
 699                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 700         if (attr->udp) {
 701                 memset(&udp, 0, sizeof(udp));
 702                 memset(&udp_mask, 0, sizeof(udp_mask));
 703                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 704                         udp.hdr.src_port = conf->port;
 705                         udp_mask.hdr.src_port =
 706                                         rte_flow_item_udp_mask.hdr.src_port;
 707                 } else {
 708                         udp.hdr.dst_port = conf->port;
 709                         udp_mask.hdr.dst_port =
 710                                         rte_flow_item_udp_mask.hdr.dst_port;
 711                 }
 712                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 713                 item.spec = &udp;
 714                 item.mask = &udp_mask;
 715                 field = modify_udp;
 716         } else {
 717                 MLX5_ASSERT(attr->tcp);
 718                 memset(&tcp, 0, sizeof(tcp));
 719                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 720                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 721                         tcp.hdr.src_port = conf->port;
 722                         tcp_mask.hdr.src_port =
 723                                         rte_flow_item_tcp_mask.hdr.src_port;
 724                 } else {
 725                         tcp.hdr.dst_port = conf->port;
 726                         tcp_mask.hdr.dst_port =
 727                                         rte_flow_item_tcp_mask.hdr.dst_port;
 728                 }
 729                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 730                 item.spec = &tcp;
 731                 item.mask = &tcp_mask;
 732                 field = modify_tcp;
 733         }
 734         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 735                                              MLX5_MODIFICATION_TYPE_SET, error);
 736 }
 737
 738 /**
 739  * Convert modify-header set TTL action to DV specification.
 740  *
 741  * @param[in,out] resource
 742  *   Pointer to the modify-header resource.
 743  * @param[in] action
 744  *   Pointer to action specification.
 745  * @param[in] items
 746  *   Pointer to rte_flow_item objects list.
 747  * @param[in] attr
 748  *   Pointer to flow attributes structure.
 749  * @param[in] dev_flow
 750  *   Pointer to the sub flow.
 751  * @param[in] tunnel_decap
 752  *   Whether action is after tunnel decapsulation.
 753  * @param[out] error
 754  *   Pointer to the error structure.
 755  *
 756  * @return
 757  *   0 on success, a negative errno value otherwise and rte_errno is set.
 758  */
 759 static int
 760 flow_dv_convert_action_modify_ttl
 761                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 762                          const struct rte_flow_action *action,
 763                          const struct rte_flow_item *items,
 764                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 765                          bool tunnel_decap, struct rte_flow_error *error)
 766 {
 767         const struct rte_flow_action_set_ttl *conf =
 768                 (const struct rte_flow_action_set_ttl *)(action->conf);
 769         struct rte_flow_item item;
 770         struct rte_flow_item_ipv4 ipv4;
 771         struct rte_flow_item_ipv4 ipv4_mask;
 772         struct rte_flow_item_ipv6 ipv6;
 773         struct rte_flow_item_ipv6 ipv6_mask;
 774         struct field_modify_info *field;
 775
 776         if (!attr->valid)
 777                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 778         if (attr->ipv4) {
 779                 memset(&ipv4, 0, sizeof(ipv4));
 780                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 781                 ipv4.hdr.time_to_live = conf->ttl_value;
 782                 ipv4_mask.hdr.time_to_live = 0xFF;
 783                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 784                 item.spec = &ipv4;
 785                 item.mask = &ipv4_mask;
 786                 field = modify_ipv4;
 787         } else {
 788                 MLX5_ASSERT(attr->ipv6);
 789                 memset(&ipv6, 0, sizeof(ipv6));
 790                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 791                 ipv6.hdr.hop_limits = conf->ttl_value;
 792                 ipv6_mask.hdr.hop_limits = 0xFF;
 793                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 794                 item.spec = &ipv6;
 795                 item.mask = &ipv6_mask;
 796                 field = modify_ipv6;
 797         }
 798         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 799                                              MLX5_MODIFICATION_TYPE_SET, error);
 800 }
 801
 802 /**
 803  * Convert modify-header decrement TTL action to DV specification.
 804  *
 805  * @param[in,out] resource
 806  *   Pointer to the modify-header resource.
 807  * @param[in] action
 808  *   Pointer to action specification.
 809  * @param[in] items
 810  *   Pointer to rte_flow_item objects list.
 811  * @param[in] attr
 812  *   Pointer to flow attributes structure.
 813  * @param[in] dev_flow
 814  *   Pointer to the sub flow.
 815  * @param[in] tunnel_decap
 816  *   Whether action is after tunnel decapsulation.
 817  * @param[out] error
 818  *   Pointer to the error structure.
 819  *
 820  * @return
 821  *   0 on success, a negative errno value otherwise and rte_errno is set.
 822  */
 823 static int
 824 flow_dv_convert_action_modify_dec_ttl
 825                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 826                          const struct rte_flow_item *items,
 827                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 828                          bool tunnel_decap, struct rte_flow_error *error)
 829 {
 830         struct rte_flow_item item;
 831         struct rte_flow_item_ipv4 ipv4;
 832         struct rte_flow_item_ipv4 ipv4_mask;
 833         struct rte_flow_item_ipv6 ipv6;
 834         struct rte_flow_item_ipv6 ipv6_mask;
 835         struct field_modify_info *field;
 836
 837         if (!attr->valid)
 838                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 839         if (attr->ipv4) {
 840                 memset(&ipv4, 0, sizeof(ipv4));
 841                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 842                 ipv4.hdr.time_to_live = 0xFF;
 843                 ipv4_mask.hdr.time_to_live = 0xFF;
 844                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 845                 item.spec = &ipv4;
 846                 item.mask = &ipv4_mask;
 847                 field = modify_ipv4;
 848         } else {
 849                 MLX5_ASSERT(attr->ipv6);
 850                 memset(&ipv6, 0, sizeof(ipv6));
 851                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 852                 ipv6.hdr.hop_limits = 0xFF;
 853                 ipv6_mask.hdr.hop_limits = 0xFF;
 854                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 855                 item.spec = &ipv6;
 856                 item.mask = &ipv6_mask;
 857                 field = modify_ipv6;
 858         }
 859         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 860                                              MLX5_MODIFICATION_TYPE_ADD, error);
 861 }
 862
 863 /**
 864  * Convert modify-header increment/decrement TCP Sequence number
 865  * to DV specification.
 866  *
 867  * @param[in,out] resource
 868  *   Pointer to the modify-header resource.
 869  * @param[in] action
 870  *   Pointer to action specification.
 871  * @param[out] error
 872  *   Pointer to the error structure.
 873  *
 874  * @return
 875  *   0 on success, a negative errno value otherwise and rte_errno is set.
 876  */
 877 static int
 878 flow_dv_convert_action_modify_tcp_seq
 879                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 880                          const struct rte_flow_action *action,
 881                          struct rte_flow_error *error)
 882 {
 883         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 884         uint64_t value = rte_be_to_cpu_32(*conf);
 885         struct rte_flow_item item;
 886         struct rte_flow_item_tcp tcp;
 887         struct rte_flow_item_tcp tcp_mask;
 888
 889         memset(&tcp, 0, sizeof(tcp));
 890         memset(&tcp_mask, 0, sizeof(tcp_mask));
 891         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 892                 /*
 893                  * The HW has no decrement operation, only increment operation.
 894                  * To simulate decrement X from Y using increment operation
 895                  * we need to add UINT32_MAX X times to Y.
 896                  * Each adding of UINT32_MAX decrements Y by 1.
 897                  */
 898                 value *= UINT32_MAX;
 899         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 900         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 901         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 902         item.spec = &tcp;
 903         item.mask = &tcp_mask;
 904         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 905                                              MLX5_MODIFICATION_TYPE_ADD, error);
 906 }
 907
 908 /**
 909  * Convert modify-header increment/decrement TCP Acknowledgment number
 910  * to DV specification.
 911  *
 912  * @param[in,out] resource
 913  *   Pointer to the modify-header resource.
 914  * @param[in] action
 915  *   Pointer to action specification.
 916  * @param[out] error
 917  *   Pointer to the error structure.
 918  *
 919  * @return
 920  *   0 on success, a negative errno value otherwise and rte_errno is set.
 921  */
 922 static int
 923 flow_dv_convert_action_modify_tcp_ack
 924                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 925                          const struct rte_flow_action *action,
 926                          struct rte_flow_error *error)
 927 {
 928         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 929         uint64_t value = rte_be_to_cpu_32(*conf);
 930         struct rte_flow_item item;
 931         struct rte_flow_item_tcp tcp;
 932         struct rte_flow_item_tcp tcp_mask;
 933
 934         memset(&tcp, 0, sizeof(tcp));
 935         memset(&tcp_mask, 0, sizeof(tcp_mask));
 936         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 937                 /*
 938                  * The HW has no decrement operation, only increment operation.
 939                  * To simulate decrement X from Y using increment operation
 940                  * we need to add UINT32_MAX X times to Y.
 941                  * Each adding of UINT32_MAX decrements Y by 1.
 942                  */
 943                 value *= UINT32_MAX;
 944         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 945         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 946         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 947         item.spec = &tcp;
 948         item.mask = &tcp_mask;
 949         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 950                                              MLX5_MODIFICATION_TYPE_ADD, error);
 951 }
 952
 953 static enum mlx5_modification_field reg_to_field[] = {
 954         [REG_NON] = MLX5_MODI_OUT_NONE,
 955         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 956         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 957         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 958         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 959         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 960         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 961         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 962         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 963         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 964         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 965 };
 966
 967 /**
 968  * Convert register set to DV specification.
 969  *
 970  * @param[in,out] resource
 971  *   Pointer to the modify-header resource.
 972  * @param[in] action
 973  *   Pointer to action specification.
 974  * @param[out] error
 975  *   Pointer to the error structure.
 976  *
 977  * @return
 978  *   0 on success, a negative errno value otherwise and rte_errno is set.
 979  */
 980 static int
 981 flow_dv_convert_action_set_reg
 982                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 983                          const struct rte_flow_action *action,
 984                          struct rte_flow_error *error)
 985 {
 986         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 987         struct mlx5_modification_cmd *actions = resource->actions;
 988         uint32_t i = resource->actions_num;
 989
 990         if (i >= MLX5_MAX_MODIFY_NUM)
 991                 return rte_flow_error_set(error, EINVAL,
 992                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 993                                           "too many items to modify");
 994         MLX5_ASSERT(conf->id != REG_NON);
 995         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 996         actions[i] = (struct mlx5_modification_cmd) {
 997                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 998                 .field = reg_to_field[conf->id],
 999         };
1000         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
1001         actions[i].data1 = rte_cpu_to_be_32(conf->data);
1002         ++i;
1003         resource->actions_num = i;
1004         return 0;
1005 }
1006
1007 /**
1008  * Convert SET_TAG action to DV specification.
1009  *
1010  * @param[in] dev
1011  *   Pointer to the rte_eth_dev structure.
1012  * @param[in,out] resource
1013  *   Pointer to the modify-header resource.
1014  * @param[in] conf
1015  *   Pointer to action specification.
1016  * @param[out] error
1017  *   Pointer to the error structure.
1018  *
1019  * @return
1020  *   0 on success, a negative errno value otherwise and rte_errno is set.
1021  */
1022 static int
1023 flow_dv_convert_action_set_tag
1024                         (struct rte_eth_dev *dev,
1025                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1026                          const struct rte_flow_action_set_tag *conf,
1027                          struct rte_flow_error *error)
1028 {
1029         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1030         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1031         struct rte_flow_item item = {
1032                 .spec = &data,
1033                 .mask = &mask,
1034         };
1035         struct field_modify_info reg_c_x[] = {
1036                 [1] = {0, 0, 0},
1037         };
1038         enum mlx5_modification_field reg_type;
1039         int ret;
1040
1041         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1042         if (ret < 0)
1043                 return ret;
1044         MLX5_ASSERT(ret != REG_NON);
1045         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1046         reg_type = reg_to_field[ret];
1047         MLX5_ASSERT(reg_type > 0);
1048         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1049         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1050                                              MLX5_MODIFICATION_TYPE_SET, error);
1051 }
1052
1053 /**
1054  * Convert internal COPY_REG action to DV specification.
1055  *
1056  * @param[in] dev
1057  *   Pointer to the rte_eth_dev structure.
1058  * @param[in,out] res
1059  *   Pointer to the modify-header resource.
1060  * @param[in] action
1061  *   Pointer to action specification.
1062  * @param[out] error
1063  *   Pointer to the error structure.
1064  *
1065  * @return
1066  *   0 on success, a negative errno value otherwise and rte_errno is set.
1067  */
1068 static int
1069 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1070                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1071                                  const struct rte_flow_action *action,
1072                                  struct rte_flow_error *error)
1073 {
1074         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1075         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1076         struct rte_flow_item item = {
1077                 .spec = NULL,
1078                 .mask = &mask,
1079         };
1080         struct field_modify_info reg_src[] = {
1081                 {4, 0, reg_to_field[conf->src]},
1082                 {0, 0, 0},
1083         };
1084         struct field_modify_info reg_dst = {
1085                 .offset = 0,
1086                 .id = reg_to_field[conf->dst],
1087         };
1088         /* Adjust reg_c[0] usage according to reported mask. */
1089         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1090                 struct mlx5_priv *priv = dev->data->dev_private;
1091                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1092
1093                 MLX5_ASSERT(reg_c0);
1094                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1095                 if (conf->dst == REG_C_0) {
1096                         /* Copy to reg_c[0], within mask only. */
1097                         reg_dst.offset = rte_bsf32(reg_c0);
1098                         /*
1099                          * Mask is ignoring the enianness, because
1100                          * there is no conversion in datapath.
1101                          */
1102 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1103                         /* Copy from destination lower bits to reg_c[0]. */
1104                         mask = reg_c0 >> reg_dst.offset;
1105 #else
1106                         /* Copy from destination upper bits to reg_c[0]. */
1107                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1108                                           rte_fls_u32(reg_c0));
1109 #endif
1110                 } else {
1111                         mask = rte_cpu_to_be_32(reg_c0);
1112 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1113                         /* Copy from reg_c[0] to destination lower bits. */
1114                         reg_dst.offset = 0;
1115 #else
1116                         /* Copy from reg_c[0] to destination upper bits. */
1117                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1118                                          (rte_fls_u32(reg_c0) -
1119                                           rte_bsf32(reg_c0));
1120 #endif
1121                 }
1122         }
1123         return flow_dv_convert_modify_action(&item,
1124                                              reg_src, &reg_dst, res,
1125                                              MLX5_MODIFICATION_TYPE_COPY,
1126                                              error);
1127 }
1128
1129 /**
1130  * Convert MARK action to DV specification. This routine is used
1131  * in extensive metadata only and requires metadata register to be
1132  * handled. In legacy mode hardware tag resource is engaged.
1133  *
1134  * @param[in] dev
1135  *   Pointer to the rte_eth_dev structure.
1136  * @param[in] conf
1137  *   Pointer to MARK action specification.
1138  * @param[in,out] resource
1139  *   Pointer to the modify-header resource.
1140  * @param[out] error
1141  *   Pointer to the error structure.
1142  *
1143  * @return
1144  *   0 on success, a negative errno value otherwise and rte_errno is set.
1145  */
1146 static int
1147 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1148                             const struct rte_flow_action_mark *conf,
1149                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1150                             struct rte_flow_error *error)
1151 {
1152         struct mlx5_priv *priv = dev->data->dev_private;
1153         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1154                                            priv->sh->dv_mark_mask);
1155         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1156         struct rte_flow_item item = {
1157                 .spec = &data,
1158                 .mask = &mask,
1159         };
1160         struct field_modify_info reg_c_x[] = {
1161                 [1] = {0, 0, 0},
1162         };
1163         int reg;
1164
1165         if (!mask)
1166                 return rte_flow_error_set(error, EINVAL,
1167                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1168                                           NULL, "zero mark action mask");
1169         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1170         if (reg < 0)
1171                 return reg;
1172         MLX5_ASSERT(reg > 0);
1173         if (reg == REG_C_0) {
1174                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1175                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1176
1177                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1178                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1179                 mask = rte_cpu_to_be_32(mask << shl_c0);
1180         }
1181         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1182         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1183                                              MLX5_MODIFICATION_TYPE_SET, error);
1184 }
1185
1186 /**
1187  * Get metadata register index for specified steering domain.
1188  *
1189  * @param[in] dev
1190  *   Pointer to the rte_eth_dev structure.
1191  * @param[in] attr
1192  *   Attributes of flow to determine steering domain.
1193  * @param[out] error
1194  *   Pointer to the error structure.
1195  *
1196  * @return
1197  *   positive index on success, a negative errno value otherwise
1198  *   and rte_errno is set.
1199  */
1200 static enum modify_reg
1201 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1202                          const struct rte_flow_attr *attr,
1203                          struct rte_flow_error *error)
1204 {
1205         int reg =
1206                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1207                                           MLX5_METADATA_FDB :
1208                                             attr->egress ?
1209                                             MLX5_METADATA_TX :
1210                                             MLX5_METADATA_RX, 0, error);
1211         if (reg < 0)
1212                 return rte_flow_error_set(error,
1213                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1214                                           NULL, "unavailable "
1215                                           "metadata register");
1216         return reg;
1217 }
1218
1219 /**
1220  * Convert SET_META action to DV specification.
1221  *
1222  * @param[in] dev
1223  *   Pointer to the rte_eth_dev structure.
1224  * @param[in,out] resource
1225  *   Pointer to the modify-header resource.
1226  * @param[in] attr
1227  *   Attributes of flow that includes this item.
1228  * @param[in] conf
1229  *   Pointer to action specification.
1230  * @param[out] error
1231  *   Pointer to the error structure.
1232  *
1233  * @return
1234  *   0 on success, a negative errno value otherwise and rte_errno is set.
1235  */
1236 static int
1237 flow_dv_convert_action_set_meta
1238                         (struct rte_eth_dev *dev,
1239                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1240                          const struct rte_flow_attr *attr,
1241                          const struct rte_flow_action_set_meta *conf,
1242                          struct rte_flow_error *error)
1243 {
1244         uint32_t data = conf->data;
1245         uint32_t mask = conf->mask;
1246         struct rte_flow_item item = {
1247                 .spec = &data,
1248                 .mask = &mask,
1249         };
1250         struct field_modify_info reg_c_x[] = {
1251                 [1] = {0, 0, 0},
1252         };
1253         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1254
1255         if (reg < 0)
1256                 return reg;
1257         /*
1258          * In datapath code there is no endianness
1259          * coversions for perfromance reasons, all
1260          * pattern conversions are done in rte_flow.
1261          */
1262         if (reg == REG_C_0) {
1263                 struct mlx5_priv *priv = dev->data->dev_private;
1264                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1265                 uint32_t shl_c0;
1266
1267                 MLX5_ASSERT(msk_c0);
1268 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1269                 shl_c0 = rte_bsf32(msk_c0);
1270 #else
1271                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1272 #endif
1273                 mask <<= shl_c0;
1274                 data <<= shl_c0;
1275                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1276         }
1277         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1278         /* The routine expects parameters in memory as big-endian ones. */
1279         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1280                                              MLX5_MODIFICATION_TYPE_SET, error);
1281 }
1282
1283 /**
1284  * Convert modify-header set IPv4 DSCP action to DV specification.
1285  *
1286  * @param[in,out] resource
1287  *   Pointer to the modify-header resource.
1288  * @param[in] action
1289  *   Pointer to action specification.
1290  * @param[out] error
1291  *   Pointer to the error structure.
1292  *
1293  * @return
1294  *   0 on success, a negative errno value otherwise and rte_errno is set.
1295  */
1296 static int
1297 flow_dv_convert_action_modify_ipv4_dscp
1298                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1299                          const struct rte_flow_action *action,
1300                          struct rte_flow_error *error)
1301 {
1302         const struct rte_flow_action_set_dscp *conf =
1303                 (const struct rte_flow_action_set_dscp *)(action->conf);
1304         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1305         struct rte_flow_item_ipv4 ipv4;
1306         struct rte_flow_item_ipv4 ipv4_mask;
1307
1308         memset(&ipv4, 0, sizeof(ipv4));
1309         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1310         ipv4.hdr.type_of_service = conf->dscp;
1311         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1312         item.spec = &ipv4;
1313         item.mask = &ipv4_mask;
1314         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1315                                              MLX5_MODIFICATION_TYPE_SET, error);
1316 }
1317
1318 /**
1319  * Convert modify-header set IPv6 DSCP action to DV specification.
1320  *
1321  * @param[in,out] resource
1322  *   Pointer to the modify-header resource.
1323  * @param[in] action
1324  *   Pointer to action specification.
1325  * @param[out] error
1326  *   Pointer to the error structure.
1327  *
1328  * @return
1329  *   0 on success, a negative errno value otherwise and rte_errno is set.
1330  */
1331 static int
1332 flow_dv_convert_action_modify_ipv6_dscp
1333                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1334                          const struct rte_flow_action *action,
1335                          struct rte_flow_error *error)
1336 {
1337         const struct rte_flow_action_set_dscp *conf =
1338                 (const struct rte_flow_action_set_dscp *)(action->conf);
1339         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1340         struct rte_flow_item_ipv6 ipv6;
1341         struct rte_flow_item_ipv6 ipv6_mask;
1342
1343         memset(&ipv6, 0, sizeof(ipv6));
1344         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1345         /*
1346          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1347          * rdma-core only accept the DSCP bits byte aligned start from
1348          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1349          * bits in IPv6 case as rdma-core requires byte aligned value.
1350          */
1351         ipv6.hdr.vtc_flow = conf->dscp;
1352         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1353         item.spec = &ipv6;
1354         item.mask = &ipv6_mask;
1355         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1356                                              MLX5_MODIFICATION_TYPE_SET, error);
1357 }
1358
1359 /**
1360  * Validate MARK item.
1361  *
1362  * @param[in] dev
1363  *   Pointer to the rte_eth_dev structure.
1364  * @param[in] item
1365  *   Item specification.
1366  * @param[in] attr
1367  *   Attributes of flow that includes this item.
1368  * @param[out] error
1369  *   Pointer to error structure.
1370  *
1371  * @return
1372  *   0 on success, a negative errno value otherwise and rte_errno is set.
1373  */
1374 static int
1375 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1376                            const struct rte_flow_item *item,
1377                            const struct rte_flow_attr *attr __rte_unused,
1378                            struct rte_flow_error *error)
1379 {
1380         struct mlx5_priv *priv = dev->data->dev_private;
1381         struct mlx5_dev_config *config = &priv->config;
1382         const struct rte_flow_item_mark *spec = item->spec;
1383         const struct rte_flow_item_mark *mask = item->mask;
1384         const struct rte_flow_item_mark nic_mask = {
1385                 .id = priv->sh->dv_mark_mask,
1386         };
1387         int ret;
1388
1389         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1390                 return rte_flow_error_set(error, ENOTSUP,
1391                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1392                                           "extended metadata feature"
1393                                           " isn't enabled");
1394         if (!mlx5_flow_ext_mreg_supported(dev))
1395                 return rte_flow_error_set(error, ENOTSUP,
1396                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1397                                           "extended metadata register"
1398                                           " isn't supported");
1399         if (!nic_mask.id)
1400                 return rte_flow_error_set(error, ENOTSUP,
1401                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1402                                           "extended metadata register"
1403                                           " isn't available");
1404         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1405         if (ret < 0)
1406                 return ret;
1407         if (!spec)
1408                 return rte_flow_error_set(error, EINVAL,
1409                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1410                                           item->spec,
1411                                           "data cannot be empty");
1412         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1413                 return rte_flow_error_set(error, EINVAL,
1414                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1415                                           &spec->id,
1416                                           "mark id exceeds the limit");
1417         if (!mask)
1418                 mask = &nic_mask;
1419         if (!mask->id)
1420                 return rte_flow_error_set(error, EINVAL,
1421                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1422                                         "mask cannot be zero");
1423
1424         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1425                                         (const uint8_t *)&nic_mask,
1426                                         sizeof(struct rte_flow_item_mark),
1427                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1428         if (ret < 0)
1429                 return ret;
1430         return 0;
1431 }
1432
1433 /**
1434  * Validate META item.
1435  *
1436  * @param[in] dev
1437  *   Pointer to the rte_eth_dev structure.
1438  * @param[in] item
1439  *   Item specification.
1440  * @param[in] attr
1441  *   Attributes of flow that includes this item.
1442  * @param[out] error
1443  *   Pointer to error structure.
1444  *
1445  * @return
1446  *   0 on success, a negative errno value otherwise and rte_errno is set.
1447  */
1448 static int
1449 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1450                            const struct rte_flow_item *item,
1451                            const struct rte_flow_attr *attr,
1452                            struct rte_flow_error *error)
1453 {
1454         struct mlx5_priv *priv = dev->data->dev_private;
1455         struct mlx5_dev_config *config = &priv->config;
1456         const struct rte_flow_item_meta *spec = item->spec;
1457         const struct rte_flow_item_meta *mask = item->mask;
1458         struct rte_flow_item_meta nic_mask = {
1459                 .data = UINT32_MAX
1460         };
1461         int reg;
1462         int ret;
1463
1464         if (!spec)
1465                 return rte_flow_error_set(error, EINVAL,
1466                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1467                                           item->spec,
1468                                           "data cannot be empty");
1469         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1470                 if (!mlx5_flow_ext_mreg_supported(dev))
1471                         return rte_flow_error_set(error, ENOTSUP,
1472                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1473                                           "extended metadata register"
1474                                           " isn't supported");
1475                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1476                 if (reg < 0)
1477                         return reg;
1478                 if (reg == REG_B)
1479                         return rte_flow_error_set(error, ENOTSUP,
1480                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1481                                           "match on reg_b "
1482                                           "isn't supported");
1483                 if (reg != REG_A)
1484                         nic_mask.data = priv->sh->dv_meta_mask;
1485         } else if (attr->transfer) {
1486                 return rte_flow_error_set(error, ENOTSUP,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1488                                         "extended metadata feature "
1489                                         "should be enabled when "
1490                                         "meta item is requested "
1491                                         "with e-switch mode ");
1492         }
1493         if (!mask)
1494                 mask = &rte_flow_item_meta_mask;
1495         if (!mask->data)
1496                 return rte_flow_error_set(error, EINVAL,
1497                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1498                                         "mask cannot be zero");
1499
1500         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1501                                         (const uint8_t *)&nic_mask,
1502                                         sizeof(struct rte_flow_item_meta),
1503                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1504         return ret;
1505 }
1506
1507 /**
1508  * Validate TAG item.
1509  *
1510  * @param[in] dev
1511  *   Pointer to the rte_eth_dev structure.
1512  * @param[in] item
1513  *   Item specification.
1514  * @param[in] attr
1515  *   Attributes of flow that includes this item.
1516  * @param[out] error
1517  *   Pointer to error structure.
1518  *
1519  * @return
1520  *   0 on success, a negative errno value otherwise and rte_errno is set.
1521  */
1522 static int
1523 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1524                           const struct rte_flow_item *item,
1525                           const struct rte_flow_attr *attr __rte_unused,
1526                           struct rte_flow_error *error)
1527 {
1528         const struct rte_flow_item_tag *spec = item->spec;
1529         const struct rte_flow_item_tag *mask = item->mask;
1530         const struct rte_flow_item_tag nic_mask = {
1531                 .data = RTE_BE32(UINT32_MAX),
1532                 .index = 0xff,
1533         };
1534         int ret;
1535
1536         if (!mlx5_flow_ext_mreg_supported(dev))
1537                 return rte_flow_error_set(error, ENOTSUP,
1538                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1539                                           "extensive metadata register"
1540                                           " isn't supported");
1541         if (!spec)
1542                 return rte_flow_error_set(error, EINVAL,
1543                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1544                                           item->spec,
1545                                           "data cannot be empty");
1546         if (!mask)
1547                 mask = &rte_flow_item_tag_mask;
1548         if (!mask->data)
1549                 return rte_flow_error_set(error, EINVAL,
1550                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1551                                         "mask cannot be zero");
1552
1553         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1554                                         (const uint8_t *)&nic_mask,
1555                                         sizeof(struct rte_flow_item_tag),
1556                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1557         if (ret < 0)
1558                 return ret;
1559         if (mask->index != 0xff)
1560                 return rte_flow_error_set(error, EINVAL,
1561                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1562                                           "partial mask for tag index"
1563                                           " is not supported");
1564         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1565         if (ret < 0)
1566                 return ret;
1567         MLX5_ASSERT(ret != REG_NON);
1568         return 0;
1569 }
1570
1571 /**
1572  * Validate vport item.
1573  *
1574  * @param[in] dev
1575  *   Pointer to the rte_eth_dev structure.
1576  * @param[in] item
1577  *   Item specification.
1578  * @param[in] attr
1579  *   Attributes of flow that includes this item.
1580  * @param[in] item_flags
1581  *   Bit-fields that holds the items detected until now.
1582  * @param[out] error
1583  *   Pointer to error structure.
1584  *
1585  * @return
1586  *   0 on success, a negative errno value otherwise and rte_errno is set.
1587  */
1588 static int
1589 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1590                               const struct rte_flow_item *item,
1591                               const struct rte_flow_attr *attr,
1592                               uint64_t item_flags,
1593                               struct rte_flow_error *error)
1594 {
1595         const struct rte_flow_item_port_id *spec = item->spec;
1596         const struct rte_flow_item_port_id *mask = item->mask;
1597         const struct rte_flow_item_port_id switch_mask = {
1598                         .id = 0xffffffff,
1599         };
1600         struct mlx5_priv *esw_priv;
1601         struct mlx5_priv *dev_priv;
1602         int ret;
1603
1604         if (!attr->transfer)
1605                 return rte_flow_error_set(error, EINVAL,
1606                                           RTE_FLOW_ERROR_TYPE_ITEM,
1607                                           NULL,
1608                                           "match on port id is valid only"
1609                                           " when transfer flag is enabled");
1610         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1611                 return rte_flow_error_set(error, ENOTSUP,
1612                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1613                                           "multiple source ports are not"
1614                                           " supported");
1615         if (!mask)
1616                 mask = &switch_mask;
1617         if (mask->id != 0xffffffff)
1618                 return rte_flow_error_set(error, ENOTSUP,
1619                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1620                                            mask,
1621                                            "no support for partial mask on"
1622                                            " \"id\" field");
1623         ret = mlx5_flow_item_acceptable
1624                                 (item, (const uint8_t *)mask,
1625                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1626                                  sizeof(struct rte_flow_item_port_id),
1627                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1628         if (ret)
1629                 return ret;
1630         if (!spec)
1631                 return 0;
1632         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1633         if (!esw_priv)
1634                 return rte_flow_error_set(error, rte_errno,
1635                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1636                                           "failed to obtain E-Switch info for"
1637                                           " port");
1638         dev_priv = mlx5_dev_to_eswitch_info(dev);
1639         if (!dev_priv)
1640                 return rte_flow_error_set(error, rte_errno,
1641                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1642                                           NULL,
1643                                           "failed to obtain E-Switch info");
1644         if (esw_priv->domain_id != dev_priv->domain_id)
1645                 return rte_flow_error_set(error, EINVAL,
1646                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1647                                           "cannot match on a port from a"
1648                                           " different E-Switch");
1649         return 0;
1650 }
1651
1652 /**
1653  * Validate VLAN item.
1654  *
1655  * @param[in] item
1656  *   Item specification.
1657  * @param[in] item_flags
1658  *   Bit-fields that holds the items detected until now.
1659  * @param[in] dev
1660  *   Ethernet device flow is being created on.
1661  * @param[out] error
1662  *   Pointer to error structure.
1663  *
1664  * @return
1665  *   0 on success, a negative errno value otherwise and rte_errno is set.
1666  */
1667 static int
1668 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1669                            uint64_t item_flags,
1670                            struct rte_eth_dev *dev,
1671                            struct rte_flow_error *error)
1672 {
1673         const struct rte_flow_item_vlan *mask = item->mask;
1674         const struct rte_flow_item_vlan nic_mask = {
1675                 .tci = RTE_BE16(UINT16_MAX),
1676                 .inner_type = RTE_BE16(UINT16_MAX),
1677                 .has_more_vlan = 1,
1678         };
1679         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1680         int ret;
1681         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1682                                         MLX5_FLOW_LAYER_INNER_L4) :
1683                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1684                                         MLX5_FLOW_LAYER_OUTER_L4);
1685         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1686                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1687
1688         if (item_flags & vlanm)
1689                 return rte_flow_error_set(error, EINVAL,
1690                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1691                                           "multiple VLAN layers not supported");
1692         else if ((item_flags & l34m) != 0)
1693                 return rte_flow_error_set(error, EINVAL,
1694                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1695                                           "VLAN cannot follow L3/L4 layer");
1696         if (!mask)
1697                 mask = &rte_flow_item_vlan_mask;
1698         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1699                                         (const uint8_t *)&nic_mask,
1700                                         sizeof(struct rte_flow_item_vlan),
1701                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1702         if (ret)
1703                 return ret;
1704         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1705                 struct mlx5_priv *priv = dev->data->dev_private;
1706
1707                 if (priv->vmwa_context) {
1708                         /*
1709                          * Non-NULL context means we have a virtual machine
1710                          * and SR-IOV enabled, we have to create VLAN interface
1711                          * to make hypervisor to setup E-Switch vport
1712                          * context correctly. We avoid creating the multiple
1713                          * VLAN interfaces, so we cannot support VLAN tag mask.
1714                          */
1715                         return rte_flow_error_set(error, EINVAL,
1716                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1717                                                   item,
1718                                                   "VLAN tag mask is not"
1719                                                   " supported in virtual"
1720                                                   " environment");
1721                 }
1722         }
1723         return 0;
1724 }
1725
1726 /*
1727  * GTP flags are contained in 1 byte of the format:
1728  * -------------------------------------------
1729  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1730  * |-----------------------------------------|
1731  * | value | Version | PT | Res | E | S | PN |
1732  * -------------------------------------------
1733  *
1734  * Matching is supported only for GTP flags E, S, PN.
1735  */
1736 #define MLX5_GTP_FLAGS_MASK     0x07
1737
1738 /**
1739  * Validate GTP item.
1740  *
1741  * @param[in] dev
1742  *   Pointer to the rte_eth_dev structure.
1743  * @param[in] item
1744  *   Item specification.
1745  * @param[in] item_flags
1746  *   Bit-fields that holds the items detected until now.
1747  * @param[out] error
1748  *   Pointer to error structure.
1749  *
1750  * @return
1751  *   0 on success, a negative errno value otherwise and rte_errno is set.
1752  */
1753 static int
1754 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1755                           const struct rte_flow_item *item,
1756                           uint64_t item_flags,
1757                           struct rte_flow_error *error)
1758 {
1759         struct mlx5_priv *priv = dev->data->dev_private;
1760         const struct rte_flow_item_gtp *spec = item->spec;
1761         const struct rte_flow_item_gtp *mask = item->mask;
1762         const struct rte_flow_item_gtp nic_mask = {
1763                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1764                 .msg_type = 0xff,
1765                 .teid = RTE_BE32(0xffffffff),
1766         };
1767
1768         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1769                 return rte_flow_error_set(error, ENOTSUP,
1770                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1771                                           "GTP support is not enabled");
1772         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "multiple tunnel layers not"
1776                                           " supported");
1777         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1778                 return rte_flow_error_set(error, EINVAL,
1779                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1780                                           "no outer UDP layer found");
1781         if (!mask)
1782                 mask = &rte_flow_item_gtp_mask;
1783         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1784                 return rte_flow_error_set(error, ENOTSUP,
1785                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1786                                           "Match is supported for GTP"
1787                                           " flags only");
1788         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1789                                          (const uint8_t *)&nic_mask,
1790                                          sizeof(struct rte_flow_item_gtp),
1791                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1792 }
1793
1794 /**
1795  * Validate IPV4 item.
1796  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
1797  * add specific validation of fragment_offset field,
1798  *
1799  * @param[in] item
1800  *   Item specification.
1801  * @param[in] item_flags
1802  *   Bit-fields that holds the items detected until now.
1803  * @param[out] error
1804  *   Pointer to error structure.
1805  *
1806  * @return
1807  *   0 on success, a negative errno value otherwise and rte_errno is set.
1808  */
1809 static int
1810 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
1811                            uint64_t item_flags,
1812                            uint64_t last_item,
1813                            uint16_t ether_type,
1814                            struct rte_flow_error *error)
1815 {
1816         int ret;
1817         const struct rte_flow_item_ipv4 *spec = item->spec;
1818         const struct rte_flow_item_ipv4 *last = item->last;
1819         const struct rte_flow_item_ipv4 *mask = item->mask;
1820         rte_be16_t fragment_offset_spec = 0;
1821         rte_be16_t fragment_offset_last = 0;
1822         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
1823                 .hdr = {
1824                         .src_addr = RTE_BE32(0xffffffff),
1825                         .dst_addr = RTE_BE32(0xffffffff),
1826                         .type_of_service = 0xff,
1827                         .fragment_offset = RTE_BE16(0xffff),
1828                         .next_proto_id = 0xff,
1829                         .time_to_live = 0xff,
1830                 },
1831         };
1832
1833         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
1834                                            ether_type, &nic_ipv4_mask,
1835                                            MLX5_ITEM_RANGE_ACCEPTED, error);
1836         if (ret < 0)
1837                 return ret;
1838         if (spec && mask)
1839                 fragment_offset_spec = spec->hdr.fragment_offset &
1840                                        mask->hdr.fragment_offset;
1841         if (!fragment_offset_spec)
1842                 return 0;
1843         /*
1844          * spec and mask are valid, enforce using full mask to make sure the
1845          * complete value is used correctly.
1846          */
1847         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1848                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1849                 return rte_flow_error_set(error, EINVAL,
1850                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1851                                           item, "must use full mask for"
1852                                           " fragment_offset");
1853         /*
1854          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
1855          * indicating this is 1st fragment of fragmented packet.
1856          * This is not yet supported in MLX5, return appropriate error message.
1857          */
1858         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
1859                 return rte_flow_error_set(error, ENOTSUP,
1860                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1861                                           "match on first fragment not "
1862                                           "supported");
1863         if (fragment_offset_spec && !last)
1864                 return rte_flow_error_set(error, ENOTSUP,
1865                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1866                                           "specified value not supported");
1867         /* spec and last are valid, validate the specified range. */
1868         fragment_offset_last = last->hdr.fragment_offset &
1869                                mask->hdr.fragment_offset;
1870         /*
1871          * Match on fragment_offset spec 0x2001 and last 0x3fff
1872          * means MF is 1 and frag-offset is > 0.
1873          * This packet is fragment 2nd and onward, excluding last.
1874          * This is not yet supported in MLX5, return appropriate
1875          * error message.
1876          */
1877         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
1878             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
1879                 return rte_flow_error_set(error, ENOTSUP,
1880                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1881                                           last, "match on following "
1882                                           "fragments not supported");
1883         /*
1884          * Match on fragment_offset spec 0x0001 and last 0x1fff
1885          * means MF is 0 and frag-offset is > 0.
1886          * This packet is last fragment of fragmented packet.
1887          * This is not yet supported in MLX5, return appropriate
1888          * error message.
1889          */
1890         if (fragment_offset_spec == RTE_BE16(1) &&
1891             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
1892                 return rte_flow_error_set(error, ENOTSUP,
1893                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
1894                                           last, "match on last "
1895                                           "fragment not supported");
1896         /*
1897          * Match on fragment_offset spec 0x0001 and last 0x3fff
1898          * means MF and/or frag-offset is not 0.
1899          * This is a fragmented packet.
1900          * Other range values are invalid and rejected.
1901          */
1902         if (!(fragment_offset_spec == RTE_BE16(1) &&
1903               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
1904                 return rte_flow_error_set(error, ENOTSUP,
1905                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
1906                                           "specified range not supported");
1907         return 0;
1908 }
1909
1910 /**
1911  * Validate IPV6 fragment extension item.
1912  *
1913  * @param[in] item
1914  *   Item specification.
1915  * @param[in] item_flags
1916  *   Bit-fields that holds the items detected until now.
1917  * @param[out] error
1918  *   Pointer to error structure.
1919  *
1920  * @return
1921  *   0 on success, a negative errno value otherwise and rte_errno is set.
1922  */
1923 static int
1924 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
1925                                     uint64_t item_flags,
1926                                     struct rte_flow_error *error)
1927 {
1928         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
1929         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
1930         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
1931         rte_be16_t frag_data_spec = 0;
1932         rte_be16_t frag_data_last = 0;
1933         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1934         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
1935                                       MLX5_FLOW_LAYER_OUTER_L4;
1936         int ret = 0;
1937         struct rte_flow_item_ipv6_frag_ext nic_mask = {
1938                 .hdr = {
1939                         .next_header = 0xff,
1940                         .frag_data = RTE_BE16(0xffff),
1941                 },
1942         };
1943
1944         if (item_flags & l4m)
1945                 return rte_flow_error_set(error, EINVAL,
1946                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1947                                           "ipv6 fragment extension item cannot "
1948                                           "follow L4 item.");
1949         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
1950             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
1951                 return rte_flow_error_set(error, EINVAL,
1952                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1953                                           "ipv6 fragment extension item must "
1954                                           "follow ipv6 item");
1955         if (spec && mask)
1956                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
1957         if (!frag_data_spec)
1958                 return 0;
1959         /*
1960          * spec and mask are valid, enforce using full mask to make sure the
1961          * complete value is used correctly.
1962          */
1963         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
1964                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
1965                 return rte_flow_error_set(error, EINVAL,
1966                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1967                                           item, "must use full mask for"
1968                                           " frag_data");
1969         /*
1970          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
1971          * This is 1st fragment of fragmented packet.
1972          */
1973         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
1974                 return rte_flow_error_set(error, ENOTSUP,
1975                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1976                                           "match on first fragment not "
1977                                           "supported");
1978         if (frag_data_spec && !last)
1979                 return rte_flow_error_set(error, EINVAL,
1980                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1981                                           "specified value not supported");
1982         ret = mlx5_flow_item_acceptable
1983                                 (item, (const uint8_t *)mask,
1984                                  (const uint8_t *)&nic_mask,
1985                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
1986                                  MLX5_ITEM_RANGE_ACCEPTED, error);
1987         if (ret)
1988                 return ret;
1989         /* spec and last are valid, validate the specified range. */
1990         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
1991         /*
1992          * Match on frag_data spec 0x0009 and last 0xfff9
1993          * means M is 1 and frag-offset is > 0.
1994          * This packet is fragment 2nd and onward, excluding last.
1995          * This is not yet supported in MLX5, return appropriate
1996          * error message.
1997          */
1998         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
1999                                        RTE_IPV6_EHDR_MF_MASK) &&
2000             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2001                 return rte_flow_error_set(error, ENOTSUP,
2002                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2003                                           last, "match on following "
2004                                           "fragments not supported");
2005         /*
2006          * Match on frag_data spec 0x0008 and last 0xfff8
2007          * means M is 0 and frag-offset is > 0.
2008          * This packet is last fragment of fragmented packet.
2009          * This is not yet supported in MLX5, return appropriate
2010          * error message.
2011          */
2012         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2013             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2014                 return rte_flow_error_set(error, ENOTSUP,
2015                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2016                                           last, "match on last "
2017                                           "fragment not supported");
2018         /* Other range values are invalid and rejected. */
2019         return rte_flow_error_set(error, EINVAL,
2020                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2021                                   "specified range not supported");
2022 }
2023
2024 /**
2025  * Validate the pop VLAN action.
2026  *
2027  * @param[in] dev
2028  *   Pointer to the rte_eth_dev structure.
2029  * @param[in] action_flags
2030  *   Holds the actions detected until now.
2031  * @param[in] action
2032  *   Pointer to the pop vlan action.
2033  * @param[in] item_flags
2034  *   The items found in this flow rule.
2035  * @param[in] attr
2036  *   Pointer to flow attributes.
2037  * @param[out] error
2038  *   Pointer to error structure.
2039  *
2040  * @return
2041  *   0 on success, a negative errno value otherwise and rte_errno is set.
2042  */
2043 static int
2044 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2045                                  uint64_t action_flags,
2046                                  const struct rte_flow_action *action,
2047                                  uint64_t item_flags,
2048                                  const struct rte_flow_attr *attr,
2049                                  struct rte_flow_error *error)
2050 {
2051         const struct mlx5_priv *priv = dev->data->dev_private;
2052
2053         (void)action;
2054         (void)attr;
2055         if (!priv->sh->pop_vlan_action)
2056                 return rte_flow_error_set(error, ENOTSUP,
2057                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2058                                           NULL,
2059                                           "pop vlan action is not supported");
2060         if (attr->egress)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2063                                           NULL,
2064                                           "pop vlan action not supported for "
2065                                           "egress");
2066         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2067                 return rte_flow_error_set(error, ENOTSUP,
2068                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2069                                           "no support for multiple VLAN "
2070                                           "actions");
2071         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2072         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2073             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2074                 return rte_flow_error_set(error, ENOTSUP,
2075                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2076                                           NULL,
2077                                           "cannot pop vlan after decap without "
2078                                           "match on inner vlan in the flow");
2079         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2080         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2081             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2082                 return rte_flow_error_set(error, ENOTSUP,
2083                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2084                                           NULL,
2085                                           "cannot pop vlan without a "
2086                                           "match on (outer) vlan in the flow");
2087         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2088                 return rte_flow_error_set(error, EINVAL,
2089                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2090                                           "wrong action order, port_id should "
2091                                           "be after pop VLAN action");
2092         if (!attr->transfer && priv->representor)
2093                 return rte_flow_error_set(error, ENOTSUP,
2094                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2095                                           "pop vlan action for VF representor "
2096                                           "not supported on NIC table");
2097         return 0;
2098 }
2099
2100 /**
2101  * Get VLAN default info from vlan match info.
2102  *
2103  * @param[in] items
2104  *   the list of item specifications.
2105  * @param[out] vlan
2106  *   pointer VLAN info to fill to.
2107  *
2108  * @return
2109  *   0 on success, a negative errno value otherwise and rte_errno is set.
2110  */
2111 static void
2112 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2113                                   struct rte_vlan_hdr *vlan)
2114 {
2115         const struct rte_flow_item_vlan nic_mask = {
2116                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2117                                 MLX5DV_FLOW_VLAN_VID_MASK),
2118                 .inner_type = RTE_BE16(0xffff),
2119         };
2120
2121         if (items == NULL)
2122                 return;
2123         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2124                 int type = items->type;
2125
2126                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2127                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2128                         break;
2129         }
2130         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2131                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2132                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2133
2134                 /* If VLAN item in pattern doesn't contain data, return here. */
2135                 if (!vlan_v)
2136                         return;
2137                 if (!vlan_m)
2138                         vlan_m = &nic_mask;
2139                 /* Only full match values are accepted */
2140                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2141                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2142                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2143                         vlan->vlan_tci |=
2144                                 rte_be_to_cpu_16(vlan_v->tci &
2145                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2146                 }
2147                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2148                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2149                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2150                         vlan->vlan_tci |=
2151                                 rte_be_to_cpu_16(vlan_v->tci &
2152                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2153                 }
2154                 if (vlan_m->inner_type == nic_mask.inner_type)
2155                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2156                                                            vlan_m->inner_type);
2157         }
2158 }
2159
2160 /**
2161  * Validate the push VLAN action.
2162  *
2163  * @param[in] dev
2164  *   Pointer to the rte_eth_dev structure.
2165  * @param[in] action_flags
2166  *   Holds the actions detected until now.
2167  * @param[in] item_flags
2168  *   The items found in this flow rule.
2169  * @param[in] action
2170  *   Pointer to the action structure.
2171  * @param[in] attr
2172  *   Pointer to flow attributes
2173  * @param[out] error
2174  *   Pointer to error structure.
2175  *
2176  * @return
2177  *   0 on success, a negative errno value otherwise and rte_errno is set.
2178  */
2179 static int
2180 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2181                                   uint64_t action_flags,
2182                                   const struct rte_flow_item_vlan *vlan_m,
2183                                   const struct rte_flow_action *action,
2184                                   const struct rte_flow_attr *attr,
2185                                   struct rte_flow_error *error)
2186 {
2187         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2188         const struct mlx5_priv *priv = dev->data->dev_private;
2189
2190         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2191             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2192                 return rte_flow_error_set(error, EINVAL,
2193                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2194                                           "invalid vlan ethertype");
2195         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2196                 return rte_flow_error_set(error, EINVAL,
2197                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2198                                           "wrong action order, port_id should "
2199                                           "be after push VLAN");
2200         if (!attr->transfer && priv->representor)
2201                 return rte_flow_error_set(error, ENOTSUP,
2202                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2203                                           "push vlan action for VF representor "
2204                                           "not supported on NIC table");
2205         if (vlan_m &&
2206             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2207             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2208                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2209             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2210             !(mlx5_flow_find_action
2211                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2212                 return rte_flow_error_set(error, EINVAL,
2213                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2214                                           "not full match mask on VLAN PCP and "
2215                                           "there is no of_set_vlan_pcp action, "
2216                                           "push VLAN action cannot figure out "
2217                                           "PCP value");
2218         if (vlan_m &&
2219             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2220             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2221                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2222             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2223             !(mlx5_flow_find_action
2224                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2225                 return rte_flow_error_set(error, EINVAL,
2226                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2227                                           "not full match mask on VLAN VID and "
2228                                           "there is no of_set_vlan_vid action, "
2229                                           "push VLAN action cannot figure out "
2230                                           "VID value");
2231         (void)attr;
2232         return 0;
2233 }
2234
2235 /**
2236  * Validate the set VLAN PCP.
2237  *
2238  * @param[in] action_flags
2239  *   Holds the actions detected until now.
2240  * @param[in] actions
2241  *   Pointer to the list of actions remaining in the flow rule.
2242  * @param[out] error
2243  *   Pointer to error structure.
2244  *
2245  * @return
2246  *   0 on success, a negative errno value otherwise and rte_errno is set.
2247  */
2248 static int
2249 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2250                                      const struct rte_flow_action actions[],
2251                                      struct rte_flow_error *error)
2252 {
2253         const struct rte_flow_action *action = actions;
2254         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2255
2256         if (conf->vlan_pcp > 7)
2257                 return rte_flow_error_set(error, EINVAL,
2258                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2259                                           "VLAN PCP value is too big");
2260         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2261                 return rte_flow_error_set(error, ENOTSUP,
2262                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2263                                           "set VLAN PCP action must follow "
2264                                           "the push VLAN action");
2265         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2266                 return rte_flow_error_set(error, ENOTSUP,
2267                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2268                                           "Multiple VLAN PCP modification are "
2269                                           "not supported");
2270         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2271                 return rte_flow_error_set(error, EINVAL,
2272                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2273                                           "wrong action order, port_id should "
2274                                           "be after set VLAN PCP");
2275         return 0;
2276 }
2277
2278 /**
2279  * Validate the set VLAN VID.
2280  *
2281  * @param[in] item_flags
2282  *   Holds the items detected in this rule.
2283  * @param[in] action_flags
2284  *   Holds the actions detected until now.
2285  * @param[in] actions
2286  *   Pointer to the list of actions remaining in the flow rule.
2287  * @param[out] error
2288  *   Pointer to error structure.
2289  *
2290  * @return
2291  *   0 on success, a negative errno value otherwise and rte_errno is set.
2292  */
2293 static int
2294 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2295                                      uint64_t action_flags,
2296                                      const struct rte_flow_action actions[],
2297                                      struct rte_flow_error *error)
2298 {
2299         const struct rte_flow_action *action = actions;
2300         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2301
2302         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2303                 return rte_flow_error_set(error, EINVAL,
2304                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2305                                           "VLAN VID value is too big");
2306         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2307             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2308                 return rte_flow_error_set(error, ENOTSUP,
2309                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2310                                           "set VLAN VID action must follow push"
2311                                           " VLAN action or match on VLAN item");
2312         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2313                 return rte_flow_error_set(error, ENOTSUP,
2314                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2315                                           "Multiple VLAN VID modifications are "
2316                                           "not supported");
2317         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2318                 return rte_flow_error_set(error, EINVAL,
2319                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2320                                           "wrong action order, port_id should "
2321                                           "be after set VLAN VID");
2322         return 0;
2323 }
2324
2325 /*
2326  * Validate the FLAG action.
2327  *
2328  * @param[in] dev
2329  *   Pointer to the rte_eth_dev structure.
2330  * @param[in] action_flags
2331  *   Holds the actions detected until now.
2332  * @param[in] attr
2333  *   Pointer to flow attributes
2334  * @param[out] error
2335  *   Pointer to error structure.
2336  *
2337  * @return
2338  *   0 on success, a negative errno value otherwise and rte_errno is set.
2339  */
2340 static int
2341 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2342                              uint64_t action_flags,
2343                              const struct rte_flow_attr *attr,
2344                              struct rte_flow_error *error)
2345 {
2346         struct mlx5_priv *priv = dev->data->dev_private;
2347         struct mlx5_dev_config *config = &priv->config;
2348         int ret;
2349
2350         /* Fall back if no extended metadata register support. */
2351         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2352                 return mlx5_flow_validate_action_flag(action_flags, attr,
2353                                                       error);
2354         /* Extensive metadata mode requires registers. */
2355         if (!mlx5_flow_ext_mreg_supported(dev))
2356                 return rte_flow_error_set(error, ENOTSUP,
2357                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2358                                           "no metadata registers "
2359                                           "to support flag action");
2360         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2361                 return rte_flow_error_set(error, ENOTSUP,
2362                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2363                                           "extended metadata register"
2364                                           " isn't available");
2365         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2366         if (ret < 0)
2367                 return ret;
2368         MLX5_ASSERT(ret > 0);
2369         if (action_flags & MLX5_FLOW_ACTION_MARK)
2370                 return rte_flow_error_set(error, EINVAL,
2371                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2372                                           "can't mark and flag in same flow");
2373         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2374                 return rte_flow_error_set(error, EINVAL,
2375                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2376                                           "can't have 2 flag"
2377                                           " actions in same flow");
2378         return 0;
2379 }
2380
2381 /**
2382  * Validate MARK action.
2383  *
2384  * @param[in] dev
2385  *   Pointer to the rte_eth_dev structure.
2386  * @param[in] action
2387  *   Pointer to action.
2388  * @param[in] action_flags
2389  *   Holds the actions detected until now.
2390  * @param[in] attr
2391  *   Pointer to flow attributes
2392  * @param[out] error
2393  *   Pointer to error structure.
2394  *
2395  * @return
2396  *   0 on success, a negative errno value otherwise and rte_errno is set.
2397  */
2398 static int
2399 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2400                              const struct rte_flow_action *action,
2401                              uint64_t action_flags,
2402                              const struct rte_flow_attr *attr,
2403                              struct rte_flow_error *error)
2404 {
2405         struct mlx5_priv *priv = dev->data->dev_private;
2406         struct mlx5_dev_config *config = &priv->config;
2407         const struct rte_flow_action_mark *mark = action->conf;
2408         int ret;
2409
2410         /* Fall back if no extended metadata register support. */
2411         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2412                 return mlx5_flow_validate_action_mark(action, action_flags,
2413                                                       attr, error);
2414         /* Extensive metadata mode requires registers. */
2415         if (!mlx5_flow_ext_mreg_supported(dev))
2416                 return rte_flow_error_set(error, ENOTSUP,
2417                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2418                                           "no metadata registers "
2419                                           "to support mark action");
2420         if (!priv->sh->dv_mark_mask)
2421                 return rte_flow_error_set(error, ENOTSUP,
2422                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2423                                           "extended metadata register"
2424                                           " isn't available");
2425         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2426         if (ret < 0)
2427                 return ret;
2428         MLX5_ASSERT(ret > 0);
2429         if (!mark)
2430                 return rte_flow_error_set(error, EINVAL,
2431                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2432                                           "configuration cannot be null");
2433         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2434                 return rte_flow_error_set(error, EINVAL,
2435                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2436                                           &mark->id,
2437                                           "mark id exceeds the limit");
2438         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2439                 return rte_flow_error_set(error, EINVAL,
2440                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2441                                           "can't flag and mark in same flow");
2442         if (action_flags & MLX5_FLOW_ACTION_MARK)
2443                 return rte_flow_error_set(error, EINVAL,
2444                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2445                                           "can't have 2 mark actions in same"
2446                                           " flow");
2447         return 0;
2448 }
2449
2450 /**
2451  * Validate SET_META action.
2452  *
2453  * @param[in] dev
2454  *   Pointer to the rte_eth_dev structure.
2455  * @param[in] action
2456  *   Pointer to the action structure.
2457  * @param[in] action_flags
2458  *   Holds the actions detected until now.
2459  * @param[in] attr
2460  *   Pointer to flow attributes
2461  * @param[out] error
2462  *   Pointer to error structure.
2463  *
2464  * @return
2465  *   0 on success, a negative errno value otherwise and rte_errno is set.
2466  */
2467 static int
2468 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2469                                  const struct rte_flow_action *action,
2470                                  uint64_t action_flags __rte_unused,
2471                                  const struct rte_flow_attr *attr,
2472                                  struct rte_flow_error *error)
2473 {
2474         const struct rte_flow_action_set_meta *conf;
2475         uint32_t nic_mask = UINT32_MAX;
2476         int reg;
2477
2478         if (!mlx5_flow_ext_mreg_supported(dev))
2479                 return rte_flow_error_set(error, ENOTSUP,
2480                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2481                                           "extended metadata register"
2482                                           " isn't supported");
2483         reg = flow_dv_get_metadata_reg(dev, attr, error);
2484         if (reg < 0)
2485                 return reg;
2486         if (reg != REG_A && reg != REG_B) {
2487                 struct mlx5_priv *priv = dev->data->dev_private;
2488
2489                 nic_mask = priv->sh->dv_meta_mask;
2490         }
2491         if (!(action->conf))
2492                 return rte_flow_error_set(error, EINVAL,
2493                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2494                                           "configuration cannot be null");
2495         conf = (const struct rte_flow_action_set_meta *)action->conf;
2496         if (!conf->mask)
2497                 return rte_flow_error_set(error, EINVAL,
2498                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2499                                           "zero mask doesn't have any effect");
2500         if (conf->mask & ~nic_mask)
2501                 return rte_flow_error_set(error, EINVAL,
2502                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2503                                           "meta data must be within reg C0");
2504         return 0;
2505 }
2506
2507 /**
2508  * Validate SET_TAG action.
2509  *
2510  * @param[in] dev
2511  *   Pointer to the rte_eth_dev structure.
2512  * @param[in] action
2513  *   Pointer to the action structure.
2514  * @param[in] action_flags
2515  *   Holds the actions detected until now.
2516  * @param[in] attr
2517  *   Pointer to flow attributes
2518  * @param[out] error
2519  *   Pointer to error structure.
2520  *
2521  * @return
2522  *   0 on success, a negative errno value otherwise and rte_errno is set.
2523  */
2524 static int
2525 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2526                                 const struct rte_flow_action *action,
2527                                 uint64_t action_flags,
2528                                 const struct rte_flow_attr *attr,
2529                                 struct rte_flow_error *error)
2530 {
2531         const struct rte_flow_action_set_tag *conf;
2532         const uint64_t terminal_action_flags =
2533                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2534                 MLX5_FLOW_ACTION_RSS;
2535         int ret;
2536
2537         if (!mlx5_flow_ext_mreg_supported(dev))
2538                 return rte_flow_error_set(error, ENOTSUP,
2539                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2540                                           "extensive metadata register"
2541                                           " isn't supported");
2542         if (!(action->conf))
2543                 return rte_flow_error_set(error, EINVAL,
2544                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2545                                           "configuration cannot be null");
2546         conf = (const struct rte_flow_action_set_tag *)action->conf;
2547         if (!conf->mask)
2548                 return rte_flow_error_set(error, EINVAL,
2549                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2550                                           "zero mask doesn't have any effect");
2551         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2552         if (ret < 0)
2553                 return ret;
2554         if (!attr->transfer && attr->ingress &&
2555             (action_flags & terminal_action_flags))
2556                 return rte_flow_error_set(error, EINVAL,
2557                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2558                                           "set_tag has no effect"
2559                                           " with terminal actions");
2560         return 0;
2561 }
2562
2563 /**
2564  * Validate count action.
2565  *
2566  * @param[in] dev
2567  *   Pointer to rte_eth_dev structure.
2568  * @param[out] error
2569  *   Pointer to error structure.
2570  *
2571  * @return
2572  *   0 on success, a negative errno value otherwise and rte_errno is set.
2573  */
2574 static int
2575 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2576                               struct rte_flow_error *error)
2577 {
2578         struct mlx5_priv *priv = dev->data->dev_private;
2579
2580         if (!priv->config.devx)
2581                 goto notsup_err;
2582 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2583         return 0;
2584 #endif
2585 notsup_err:
2586         return rte_flow_error_set
2587                       (error, ENOTSUP,
2588                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2589                        NULL,
2590                        "count action not supported");
2591 }
2592
2593 /**
2594  * Validate the L2 encap action.
2595  *
2596  * @param[in] dev
2597  *   Pointer to the rte_eth_dev structure.
2598  * @param[in] action_flags
2599  *   Holds the actions detected until now.
2600  * @param[in] action
2601  *   Pointer to the action structure.
2602  * @param[in] attr
2603  *   Pointer to flow attributes.
2604  * @param[out] error
2605  *   Pointer to error structure.
2606  *
2607  * @return
2608  *   0 on success, a negative errno value otherwise and rte_errno is set.
2609  */
2610 static int
2611 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2612                                  uint64_t action_flags,
2613                                  const struct rte_flow_action *action,
2614                                  const struct rte_flow_attr *attr,
2615                                  struct rte_flow_error *error)
2616 {
2617         const struct mlx5_priv *priv = dev->data->dev_private;
2618
2619         if (!(action->conf))
2620                 return rte_flow_error_set(error, EINVAL,
2621                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2622                                           "configuration cannot be null");
2623         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2624                 return rte_flow_error_set(error, EINVAL,
2625                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2626                                           "can only have a single encap action "
2627                                           "in a flow");
2628         if (!attr->transfer && priv->representor)
2629                 return rte_flow_error_set(error, ENOTSUP,
2630                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2631                                           "encap action for VF representor "
2632                                           "not supported on NIC table");
2633         return 0;
2634 }
2635
2636 /**
2637  * Validate a decap action.
2638  *
2639  * @param[in] dev
2640  *   Pointer to the rte_eth_dev structure.
2641  * @param[in] action_flags
2642  *   Holds the actions detected until now.
2643  * @param[in] attr
2644  *   Pointer to flow attributes
2645  * @param[out] error
2646  *   Pointer to error structure.
2647  *
2648  * @return
2649  *   0 on success, a negative errno value otherwise and rte_errno is set.
2650  */
2651 static int
2652 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2653                               uint64_t action_flags,
2654                               const struct rte_flow_attr *attr,
2655                               struct rte_flow_error *error)
2656 {
2657         const struct mlx5_priv *priv = dev->data->dev_private;
2658
2659         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2660             !priv->config.decap_en)
2661                 return rte_flow_error_set(error, ENOTSUP,
2662                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2663                                           "decap is not enabled");
2664         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2665                 return rte_flow_error_set(error, ENOTSUP,
2666                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2667                                           action_flags &
2668                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2669                                           "have a single decap action" : "decap "
2670                                           "after encap is not supported");
2671         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2672                 return rte_flow_error_set(error, EINVAL,
2673                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2674                                           "can't have decap action after"
2675                                           " modify action");
2676         if (attr->egress)
2677                 return rte_flow_error_set(error, ENOTSUP,
2678                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2679                                           NULL,
2680                                           "decap action not supported for "
2681                                           "egress");
2682         if (!attr->transfer && priv->representor)
2683                 return rte_flow_error_set(error, ENOTSUP,
2684                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2685                                           "decap action for VF representor "
2686                                           "not supported on NIC table");
2687         return 0;
2688 }
2689
2690 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2691
2692 /**
2693  * Validate the raw encap and decap actions.
2694  *
2695  * @param[in] dev
2696  *   Pointer to the rte_eth_dev structure.
2697  * @param[in] decap
2698  *   Pointer to the decap action.
2699  * @param[in] encap
2700  *   Pointer to the encap action.
2701  * @param[in] attr
2702  *   Pointer to flow attributes
2703  * @param[in/out] action_flags
2704  *   Holds the actions detected until now.
2705  * @param[out] actions_n
2706  *   pointer to the number of actions counter.
2707  * @param[out] error
2708  *   Pointer to error structure.
2709  *
2710  * @return
2711  *   0 on success, a negative errno value otherwise and rte_errno is set.
2712  */
2713 static int
2714 flow_dv_validate_action_raw_encap_decap
2715         (struct rte_eth_dev *dev,
2716          const struct rte_flow_action_raw_decap *decap,
2717          const struct rte_flow_action_raw_encap *encap,
2718          const struct rte_flow_attr *attr, uint64_t *action_flags,
2719          int *actions_n, struct rte_flow_error *error)
2720 {
2721         const struct mlx5_priv *priv = dev->data->dev_private;
2722         int ret;
2723
2724         if (encap && (!encap->size || !encap->data))
2725                 return rte_flow_error_set(error, EINVAL,
2726                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2727                                           "raw encap data cannot be empty");
2728         if (decap && encap) {
2729                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2730                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2731                         /* L3 encap. */
2732                         decap = NULL;
2733                 else if (encap->size <=
2734                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2735                            decap->size >
2736                            MLX5_ENCAPSULATION_DECISION_SIZE)
2737                         /* L3 decap. */
2738                         encap = NULL;
2739                 else if (encap->size >
2740                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2741                            decap->size >
2742                            MLX5_ENCAPSULATION_DECISION_SIZE)
2743                         /* 2 L2 actions: encap and decap. */
2744                         ;
2745                 else
2746                         return rte_flow_error_set(error,
2747                                 ENOTSUP,
2748                                 RTE_FLOW_ERROR_TYPE_ACTION,
2749                                 NULL, "unsupported too small "
2750                                 "raw decap and too small raw "
2751                                 "encap combination");
2752         }
2753         if (decap) {
2754                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2755                                                     error);
2756                 if (ret < 0)
2757                         return ret;
2758                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2759                 ++(*actions_n);
2760         }
2761         if (encap) {
2762                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2763                         return rte_flow_error_set(error, ENOTSUP,
2764                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2765                                                   NULL,
2766                                                   "small raw encap size");
2767                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2768                         return rte_flow_error_set(error, EINVAL,
2769                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2770                                                   NULL,
2771                                                   "more than one encap action");
2772                 if (!attr->transfer && priv->representor)
2773                         return rte_flow_error_set
2774                                         (error, ENOTSUP,
2775                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2776                                          "encap action for VF representor "
2777                                          "not supported on NIC table");
2778                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2779                 ++(*actions_n);
2780         }
2781         return 0;
2782 }
2783
2784 /**
2785  * Match encap_decap resource.
2786  *
2787  * @param list
2788  *   Pointer to the hash list.
2789  * @param entry
2790  *   Pointer to exist resource entry object.
2791  * @param key
2792  *   Key of the new entry.
2793  * @param ctx_cb
2794  *   Pointer to new encap_decap resource.
2795  *
2796  * @return
2797  *   0 on matching, none-zero otherwise.
2798  */
2799 int
2800 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
2801                              struct mlx5_hlist_entry *entry,
2802                              uint64_t key __rte_unused, void *cb_ctx)
2803 {
2804         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2805         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2806         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2807
2808         cache_resource = container_of(entry,
2809                                       struct mlx5_flow_dv_encap_decap_resource,
2810                                       entry);
2811         if (resource->entry.key == cache_resource->entry.key &&
2812             resource->reformat_type == cache_resource->reformat_type &&
2813             resource->ft_type == cache_resource->ft_type &&
2814             resource->flags == cache_resource->flags &&
2815             resource->size == cache_resource->size &&
2816             !memcmp((const void *)resource->buf,
2817                     (const void *)cache_resource->buf,
2818                     resource->size))
2819                 return 0;
2820         return -1;
2821 }
2822
2823 /**
2824  * Allocate encap_decap resource.
2825  *
2826  * @param list
2827  *   Pointer to the hash list.
2828  * @param entry
2829  *   Pointer to exist resource entry object.
2830  * @param ctx_cb
2831  *   Pointer to new encap_decap resource.
2832  *
2833  * @return
2834  *   0 on matching, none-zero otherwise.
2835  */
2836 struct mlx5_hlist_entry *
2837 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
2838                               uint64_t key __rte_unused,
2839                               void *cb_ctx)
2840 {
2841         struct mlx5_dev_ctx_shared *sh = list->ctx;
2842         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
2843         struct mlx5dv_dr_domain *domain;
2844         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
2845         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2846         uint32_t idx;
2847         int ret;
2848
2849         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2850                 domain = sh->fdb_domain;
2851         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2852                 domain = sh->rx_domain;
2853         else
2854                 domain = sh->tx_domain;
2855         /* Register new encap/decap resource. */
2856         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2857                                        &idx);
2858         if (!cache_resource) {
2859                 rte_flow_error_set(ctx->error, ENOMEM,
2860                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2861                                    "cannot allocate resource memory");
2862                 return NULL;
2863         }
2864         *cache_resource = *resource;
2865         cache_resource->idx = idx;
2866         ret = mlx5_flow_os_create_flow_action_packet_reformat
2867                                         (sh->ctx, domain, cache_resource,
2868                                          &cache_resource->action);
2869         if (ret) {
2870                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
2871                 rte_flow_error_set(ctx->error, ENOMEM,
2872                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2873                                    NULL, "cannot create action");
2874                 return NULL;
2875         }
2876
2877         return &cache_resource->entry;
2878 }
2879
2880 /**
2881  * Find existing encap/decap resource or create and register a new one.
2882  *
2883  * @param[in, out] dev
2884  *   Pointer to rte_eth_dev structure.
2885  * @param[in, out] resource
2886  *   Pointer to encap/decap resource.
2887  * @parm[in, out] dev_flow
2888  *   Pointer to the dev_flow.
2889  * @param[out] error
2890  *   pointer to error structure.
2891  *
2892  * @return
2893  *   0 on success otherwise -errno and errno is set.
2894  */
2895 static int
2896 flow_dv_encap_decap_resource_register
2897                         (struct rte_eth_dev *dev,
2898                          struct mlx5_flow_dv_encap_decap_resource *resource,
2899                          struct mlx5_flow *dev_flow,
2900                          struct rte_flow_error *error)
2901 {
2902         struct mlx5_priv *priv = dev->data->dev_private;
2903         struct mlx5_dev_ctx_shared *sh = priv->sh;
2904         struct mlx5_hlist_entry *entry;
2905         union mlx5_flow_encap_decap_key encap_decap_key = {
2906                 {
2907                         .ft_type = resource->ft_type,
2908                         .refmt_type = resource->reformat_type,
2909                         .buf_size = resource->size,
2910                         .table_level = !!dev_flow->dv.group,
2911                         .cksum = 0,
2912                 }
2913         };
2914         struct mlx5_flow_cb_ctx ctx = {
2915                 .error = error,
2916                 .data = resource,
2917         };
2918
2919         resource->flags = dev_flow->dv.group ? 0 : 1;
2920         encap_decap_key.cksum = __rte_raw_cksum(resource->buf,
2921                                                 resource->size, 0);
2922         resource->entry.key = encap_decap_key.v64;
2923         entry = mlx5_hlist_register(sh->encaps_decaps, resource->entry.key,
2924                                     &ctx);
2925         if (!entry)
2926                 return -rte_errno;
2927         resource = container_of(entry, typeof(*resource), entry);
2928         dev_flow->dv.encap_decap = resource;
2929         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
2930         return 0;
2931 }
2932
2933 /**
2934  * Find existing table jump resource or create and register a new one.
2935  *
2936  * @param[in, out] dev
2937  *   Pointer to rte_eth_dev structure.
2938  * @param[in, out] tbl
2939  *   Pointer to flow table resource.
2940  * @parm[in, out] dev_flow
2941  *   Pointer to the dev_flow.
2942  * @param[out] error
2943  *   pointer to error structure.
2944  *
2945  * @return
2946  *   0 on success otherwise -errno and errno is set.
2947  */
2948 static int
2949 flow_dv_jump_tbl_resource_register
2950                         (struct rte_eth_dev *dev __rte_unused,
2951                          struct mlx5_flow_tbl_resource *tbl,
2952                          struct mlx5_flow *dev_flow,
2953                          struct rte_flow_error *error __rte_unused)
2954 {
2955         struct mlx5_flow_tbl_data_entry *tbl_data =
2956                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2957
2958         MLX5_ASSERT(tbl);
2959         MLX5_ASSERT(tbl_data->jump.action);
2960         dev_flow->handle->rix_jump = tbl_data->idx;
2961         dev_flow->dv.jump = &tbl_data->jump;
2962         return 0;
2963 }
2964
2965 /**
2966  * Find existing table port ID resource or create and register a new one.
2967  *
2968  * @param[in, out] dev
2969  *   Pointer to rte_eth_dev structure.
2970  * @param[in, out] resource
2971  *   Pointer to port ID action resource.
2972  * @parm[in, out] dev_flow
2973  *   Pointer to the dev_flow.
2974  * @param[out] error
2975  *   pointer to error structure.
2976  *
2977  * @return
2978  *   0 on success otherwise -errno and errno is set.
2979  */
2980 static int
2981 flow_dv_port_id_action_resource_register
2982                         (struct rte_eth_dev *dev,
2983                          struct mlx5_flow_dv_port_id_action_resource *resource,
2984                          struct mlx5_flow *dev_flow,
2985                          struct rte_flow_error *error)
2986 {
2987         struct mlx5_priv *priv = dev->data->dev_private;
2988         struct mlx5_dev_ctx_shared *sh = priv->sh;
2989         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2990         uint32_t idx = 0;
2991         int ret;
2992
2993         /* Lookup a matching resource from cache. */
2994         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2995                       idx, cache_resource, next) {
2996                 if (resource->port_id == cache_resource->port_id) {
2997                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2998                                 "refcnt %d++",
2999                                 (void *)cache_resource,
3000                                 __atomic_load_n(&cache_resource->refcnt,
3001                                                 __ATOMIC_RELAXED));
3002                         __atomic_fetch_add(&cache_resource->refcnt, 1,
3003                                            __ATOMIC_RELAXED);
3004                         dev_flow->handle->rix_port_id_action = idx;
3005                         dev_flow->dv.port_id_action = cache_resource;
3006                         return 0;
3007                 }
3008         }
3009         /* Register new port id action resource. */
3010         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
3011                                        &dev_flow->handle->rix_port_id_action);
3012         if (!cache_resource)
3013                 return rte_flow_error_set(error, ENOMEM,
3014                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3015                                           "cannot allocate resource memory");
3016         *cache_resource = *resource;
3017         ret = mlx5_flow_os_create_flow_action_dest_port
3018                                 (priv->sh->fdb_domain, resource->port_id,
3019                                  &cache_resource->action);
3020         if (ret) {
3021                 mlx5_free(cache_resource);
3022                 return rte_flow_error_set(error, ENOMEM,
3023                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3024                                           NULL, "cannot create action");
3025         }
3026         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
3027         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
3028                      dev_flow->handle->rix_port_id_action, cache_resource,
3029                      next);
3030         dev_flow->dv.port_id_action = cache_resource;
3031         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
3032                 (void *)cache_resource,
3033                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
3034         return 0;
3035 }
3036
3037 /**
3038  * Find existing push vlan resource or create and register a new one.
3039  *
3040  * @param [in, out] dev
3041  *   Pointer to rte_eth_dev structure.
3042  * @param[in, out] resource
3043  *   Pointer to port ID action resource.
3044  * @parm[in, out] dev_flow
3045  *   Pointer to the dev_flow.
3046  * @param[out] error
3047  *   pointer to error structure.
3048  *
3049  * @return
3050  *   0 on success otherwise -errno and errno is set.
3051  */
3052 static int
3053 flow_dv_push_vlan_action_resource_register
3054                        (struct rte_eth_dev *dev,
3055                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3056                         struct mlx5_flow *dev_flow,
3057                         struct rte_flow_error *error)
3058 {
3059         struct mlx5_priv *priv = dev->data->dev_private;
3060         struct mlx5_dev_ctx_shared *sh = priv->sh;
3061         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
3062         struct mlx5dv_dr_domain *domain;
3063         uint32_t idx = 0;
3064         int ret;
3065
3066         /* Lookup a matching resource from cache. */
3067         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3068                       sh->push_vlan_action_list, idx, cache_resource, next) {
3069                 if (resource->vlan_tag == cache_resource->vlan_tag &&
3070                     resource->ft_type == cache_resource->ft_type) {
3071                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
3072                                 "refcnt %d++",
3073                                 (void *)cache_resource,
3074                                 __atomic_load_n(&cache_resource->refcnt,
3075                                                 __ATOMIC_RELAXED));
3076                         __atomic_fetch_add(&cache_resource->refcnt, 1,
3077                                            __ATOMIC_RELAXED);
3078                         dev_flow->handle->dvh.rix_push_vlan = idx;
3079                         dev_flow->dv.push_vlan_res = cache_resource;
3080                         return 0;
3081                 }
3082         }
3083         /* Register new push_vlan action resource. */
3084         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3085                                        &dev_flow->handle->dvh.rix_push_vlan);
3086         if (!cache_resource)
3087                 return rte_flow_error_set(error, ENOMEM,
3088                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3089                                           "cannot allocate resource memory");
3090         *cache_resource = *resource;
3091         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3092                 domain = sh->fdb_domain;
3093         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3094                 domain = sh->rx_domain;
3095         else
3096                 domain = sh->tx_domain;
3097         ret = mlx5_flow_os_create_flow_action_push_vlan
3098                                         (domain, resource->vlan_tag,
3099                                          &cache_resource->action);
3100         if (ret) {
3101                 mlx5_free(cache_resource);
3102                 return rte_flow_error_set(error, ENOMEM,
3103                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3104                                           NULL, "cannot create action");
3105         }
3106         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
3107         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
3108                      &sh->push_vlan_action_list,
3109                      dev_flow->handle->dvh.rix_push_vlan,
3110                      cache_resource, next);
3111         dev_flow->dv.push_vlan_res = cache_resource;
3112         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
3113                 (void *)cache_resource,
3114                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
3115         return 0;
3116 }
3117 /**
3118  * Get the size of specific rte_flow_item_type hdr size
3119  *
3120  * @param[in] item_type
3121  *   Tested rte_flow_item_type.
3122  *
3123  * @return
3124  *   sizeof struct item_type, 0 if void or irrelevant.
3125  */
3126 static size_t
3127 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3128 {
3129         size_t retval;
3130
3131         switch (item_type) {
3132         case RTE_FLOW_ITEM_TYPE_ETH:
3133                 retval = sizeof(struct rte_ether_hdr);
3134                 break;
3135         case RTE_FLOW_ITEM_TYPE_VLAN:
3136                 retval = sizeof(struct rte_vlan_hdr);
3137                 break;
3138         case RTE_FLOW_ITEM_TYPE_IPV4:
3139                 retval = sizeof(struct rte_ipv4_hdr);
3140                 break;
3141         case RTE_FLOW_ITEM_TYPE_IPV6:
3142                 retval = sizeof(struct rte_ipv6_hdr);
3143                 break;
3144         case RTE_FLOW_ITEM_TYPE_UDP:
3145                 retval = sizeof(struct rte_udp_hdr);
3146                 break;
3147         case RTE_FLOW_ITEM_TYPE_TCP:
3148                 retval = sizeof(struct rte_tcp_hdr);
3149                 break;
3150         case RTE_FLOW_ITEM_TYPE_VXLAN:
3151         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3152                 retval = sizeof(struct rte_vxlan_hdr);
3153                 break;
3154         case RTE_FLOW_ITEM_TYPE_GRE:
3155         case RTE_FLOW_ITEM_TYPE_NVGRE:
3156                 retval = sizeof(struct rte_gre_hdr);
3157                 break;
3158         case RTE_FLOW_ITEM_TYPE_MPLS:
3159                 retval = sizeof(struct rte_mpls_hdr);
3160                 break;
3161         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3162         default:
3163                 retval = 0;
3164                 break;
3165         }
3166         return retval;
3167 }
3168
3169 #define MLX5_ENCAP_IPV4_VERSION         0x40
3170 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3171 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3172 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3173 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3174 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3175 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3176
3177 /**
3178  * Convert the encap action data from list of rte_flow_item to raw buffer
3179  *
3180  * @param[in] items
3181  *   Pointer to rte_flow_item objects list.
3182  * @param[out] buf
3183  *   Pointer to the output buffer.
3184  * @param[out] size
3185  *   Pointer to the output buffer size.
3186  * @param[out] error
3187  *   Pointer to the error structure.
3188  *
3189  * @return
3190  *   0 on success, a negative errno value otherwise and rte_errno is set.
3191  */
3192 static int
3193 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3194                            size_t *size, struct rte_flow_error *error)
3195 {
3196         struct rte_ether_hdr *eth = NULL;
3197         struct rte_vlan_hdr *vlan = NULL;
3198         struct rte_ipv4_hdr *ipv4 = NULL;
3199         struct rte_ipv6_hdr *ipv6 = NULL;
3200         struct rte_udp_hdr *udp = NULL;
3201         struct rte_vxlan_hdr *vxlan = NULL;
3202         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3203         struct rte_gre_hdr *gre = NULL;
3204         size_t len;
3205         size_t temp_size = 0;
3206
3207         if (!items)
3208                 return rte_flow_error_set(error, EINVAL,
3209                                           RTE_FLOW_ERROR_TYPE_ACTION,
3210                                           NULL, "invalid empty data");
3211         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3212                 len = flow_dv_get_item_hdr_len(items->type);
3213                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3214                         return rte_flow_error_set(error, EINVAL,
3215                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3216                                                   (void *)items->type,
3217                                                   "items total size is too big"
3218                                                   " for encap action");
3219                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3220                 switch (items->type) {
3221                 case RTE_FLOW_ITEM_TYPE_ETH:
3222                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3223                         break;
3224                 case RTE_FLOW_ITEM_TYPE_VLAN:
3225                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3226                         if (!eth)
3227                                 return rte_flow_error_set(error, EINVAL,
3228                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3229                                                 (void *)items->type,
3230                                                 "eth header not found");
3231                         if (!eth->ether_type)
3232                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3233                         break;
3234                 case RTE_FLOW_ITEM_TYPE_IPV4:
3235                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3236                         if (!vlan && !eth)
3237                                 return rte_flow_error_set(error, EINVAL,
3238                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3239                                                 (void *)items->type,
3240                                                 "neither eth nor vlan"
3241                                                 " header found");
3242                         if (vlan && !vlan->eth_proto)
3243                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3244                         else if (eth && !eth->ether_type)
3245                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3246                         if (!ipv4->version_ihl)
3247                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3248                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3249                         if (!ipv4->time_to_live)
3250                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3251                         break;
3252                 case RTE_FLOW_ITEM_TYPE_IPV6:
3253                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3254                         if (!vlan && !eth)
3255                                 return rte_flow_error_set(error, EINVAL,
3256                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3257                                                 (void *)items->type,
3258                                                 "neither eth nor vlan"
3259                                                 " header found");
3260                         if (vlan && !vlan->eth_proto)
3261                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3262                         else if (eth && !eth->ether_type)
3263                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3264                         if (!ipv6->vtc_flow)
3265                                 ipv6->vtc_flow =
3266                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3267                         if (!ipv6->hop_limits)
3268                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3269                         break;
3270                 case RTE_FLOW_ITEM_TYPE_UDP:
3271                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3272                         if (!ipv4 && !ipv6)
3273                                 return rte_flow_error_set(error, EINVAL,
3274                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3275                                                 (void *)items->type,
3276                                                 "ip header not found");
3277                         if (ipv4 && !ipv4->next_proto_id)
3278                                 ipv4->next_proto_id = IPPROTO_UDP;
3279                         else if (ipv6 && !ipv6->proto)
3280                                 ipv6->proto = IPPROTO_UDP;
3281                         break;
3282                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3283                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3284                         if (!udp)
3285                                 return rte_flow_error_set(error, EINVAL,
3286                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3287                                                 (void *)items->type,
3288                                                 "udp header not found");
3289                         if (!udp->dst_port)
3290                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3291                         if (!vxlan->vx_flags)
3292                                 vxlan->vx_flags =
3293                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3294                         break;
3295                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3296                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3297                         if (!udp)
3298                                 return rte_flow_error_set(error, EINVAL,
3299                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3300                                                 (void *)items->type,
3301                                                 "udp header not found");
3302                         if (!vxlan_gpe->proto)
3303                                 return rte_flow_error_set(error, EINVAL,
3304                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3305                                                 (void *)items->type,
3306                                                 "next protocol not found");
3307                         if (!udp->dst_port)
3308                                 udp->dst_port =
3309                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3310                         if (!vxlan_gpe->vx_flags)
3311                                 vxlan_gpe->vx_flags =
3312                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3313                         break;
3314                 case RTE_FLOW_ITEM_TYPE_GRE:
3315                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3316                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3317                         if (!gre->proto)
3318                                 return rte_flow_error_set(error, EINVAL,
3319                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3320                                                 (void *)items->type,
3321                                                 "next protocol not found");
3322                         if (!ipv4 && !ipv6)
3323                                 return rte_flow_error_set(error, EINVAL,
3324                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3325                                                 (void *)items->type,
3326                                                 "ip header not found");
3327                         if (ipv4 && !ipv4->next_proto_id)
3328                                 ipv4->next_proto_id = IPPROTO_GRE;
3329                         else if (ipv6 && !ipv6->proto)
3330                                 ipv6->proto = IPPROTO_GRE;
3331                         break;
3332                 case RTE_FLOW_ITEM_TYPE_VOID:
3333                         break;
3334                 default:
3335                         return rte_flow_error_set(error, EINVAL,
3336                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3337                                                   (void *)items->type,
3338                                                   "unsupported item type");
3339                         break;
3340                 }
3341                 temp_size += len;
3342         }
3343         *size = temp_size;
3344         return 0;
3345 }
3346
3347 static int
3348 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3349 {
3350         struct rte_ether_hdr *eth = NULL;
3351         struct rte_vlan_hdr *vlan = NULL;
3352         struct rte_ipv6_hdr *ipv6 = NULL;
3353         struct rte_udp_hdr *udp = NULL;
3354         char *next_hdr;
3355         uint16_t proto;
3356
3357         eth = (struct rte_ether_hdr *)data;
3358         next_hdr = (char *)(eth + 1);
3359         proto = RTE_BE16(eth->ether_type);
3360
3361         /* VLAN skipping */
3362         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3363                 vlan = (struct rte_vlan_hdr *)next_hdr;
3364                 proto = RTE_BE16(vlan->eth_proto);
3365                 next_hdr += sizeof(struct rte_vlan_hdr);
3366         }
3367
3368         /* HW calculates IPv4 csum. no need to proceed */
3369         if (proto == RTE_ETHER_TYPE_IPV4)
3370                 return 0;
3371
3372         /* non IPv4/IPv6 header. not supported */
3373         if (proto != RTE_ETHER_TYPE_IPV6) {
3374                 return rte_flow_error_set(error, ENOTSUP,
3375                                           RTE_FLOW_ERROR_TYPE_ACTION,
3376                                           NULL, "Cannot offload non IPv4/IPv6");
3377         }
3378
3379         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3380
3381         /* ignore non UDP */
3382         if (ipv6->proto != IPPROTO_UDP)
3383                 return 0;
3384
3385         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3386         udp->dgram_cksum = 0;
3387
3388         return 0;
3389 }
3390
3391 /**
3392  * Convert L2 encap action to DV specification.
3393  *
3394  * @param[in] dev
3395  *   Pointer to rte_eth_dev structure.
3396  * @param[in] action
3397  *   Pointer to action structure.
3398  * @param[in, out] dev_flow
3399  *   Pointer to the mlx5_flow.
3400  * @param[in] transfer
3401  *   Mark if the flow is E-Switch flow.
3402  * @param[out] error
3403  *   Pointer to the error structure.
3404  *
3405  * @return
3406  *   0 on success, a negative errno value otherwise and rte_errno is set.
3407  */
3408 static int
3409 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3410                                const struct rte_flow_action *action,
3411                                struct mlx5_flow *dev_flow,
3412                                uint8_t transfer,
3413                                struct rte_flow_error *error)
3414 {
3415         const struct rte_flow_item *encap_data;
3416         const struct rte_flow_action_raw_encap *raw_encap_data;
3417         struct mlx5_flow_dv_encap_decap_resource res = {
3418                 .reformat_type =
3419                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3420                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3421                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3422         };
3423
3424         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3425                 raw_encap_data =
3426                         (const struct rte_flow_action_raw_encap *)action->conf;
3427                 res.size = raw_encap_data->size;
3428                 memcpy(res.buf, raw_encap_data->data, res.size);
3429         } else {
3430                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3431                         encap_data =
3432                                 ((const struct rte_flow_action_vxlan_encap *)
3433                                                 action->conf)->definition;
3434                 else
3435                         encap_data =
3436                                 ((const struct rte_flow_action_nvgre_encap *)
3437                                                 action->conf)->definition;
3438                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3439                                                &res.size, error))
3440                         return -rte_errno;
3441         }
3442         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3443                 return -rte_errno;
3444         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3445                 return rte_flow_error_set(error, EINVAL,
3446                                           RTE_FLOW_ERROR_TYPE_ACTION,
3447                                           NULL, "can't create L2 encap action");
3448         return 0;
3449 }
3450
3451 /**
3452  * Convert L2 decap action to DV specification.
3453  *
3454  * @param[in] dev
3455  *   Pointer to rte_eth_dev structure.
3456  * @param[in, out] dev_flow
3457  *   Pointer to the mlx5_flow.
3458  * @param[in] transfer
3459  *   Mark if the flow is E-Switch flow.
3460  * @param[out] error
3461  *   Pointer to the error structure.
3462  *
3463  * @return
3464  *   0 on success, a negative errno value otherwise and rte_errno is set.
3465  */
3466 static int
3467 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3468                                struct mlx5_flow *dev_flow,
3469                                uint8_t transfer,
3470                                struct rte_flow_error *error)
3471 {
3472         struct mlx5_flow_dv_encap_decap_resource res = {
3473                 .size = 0,
3474                 .reformat_type =
3475                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3476                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3477                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3478         };
3479
3480         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3481                 return rte_flow_error_set(error, EINVAL,
3482                                           RTE_FLOW_ERROR_TYPE_ACTION,
3483                                           NULL, "can't create L2 decap action");
3484         return 0;
3485 }
3486
3487 /**
3488  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3489  *
3490  * @param[in] dev
3491  *   Pointer to rte_eth_dev structure.
3492  * @param[in] action
3493  *   Pointer to action structure.
3494  * @param[in, out] dev_flow
3495  *   Pointer to the mlx5_flow.
3496  * @param[in] attr
3497  *   Pointer to the flow attributes.
3498  * @param[out] error
3499  *   Pointer to the error structure.
3500  *
3501  * @return
3502  *   0 on success, a negative errno value otherwise and rte_errno is set.
3503  */
3504 static int
3505 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3506                                 const struct rte_flow_action *action,
3507                                 struct mlx5_flow *dev_flow,
3508                                 const struct rte_flow_attr *attr,
3509                                 struct rte_flow_error *error)
3510 {
3511         const struct rte_flow_action_raw_encap *encap_data;
3512         struct mlx5_flow_dv_encap_decap_resource res;
3513
3514         memset(&res, 0, sizeof(res));
3515         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3516         res.size = encap_data->size;
3517         memcpy(res.buf, encap_data->data, res.size);
3518         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3519                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3520                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3521         if (attr->transfer)
3522                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3523         else
3524                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3525                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3526         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3527                 return rte_flow_error_set(error, EINVAL,
3528                                           RTE_FLOW_ERROR_TYPE_ACTION,
3529                                           NULL, "can't create encap action");
3530         return 0;
3531 }
3532
3533 /**
3534  * Create action push VLAN.
3535  *
3536  * @param[in] dev
3537  *   Pointer to rte_eth_dev structure.
3538  * @param[in] attr
3539  *   Pointer to the flow attributes.
3540  * @param[in] vlan
3541  *   Pointer to the vlan to push to the Ethernet header.
3542  * @param[in, out] dev_flow
3543  *   Pointer to the mlx5_flow.
3544  * @param[out] error
3545  *   Pointer to the error structure.
3546  *
3547  * @return
3548  *   0 on success, a negative errno value otherwise and rte_errno is set.
3549  */
3550 static int
3551 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3552                                 const struct rte_flow_attr *attr,
3553                                 const struct rte_vlan_hdr *vlan,
3554                                 struct mlx5_flow *dev_flow,
3555                                 struct rte_flow_error *error)
3556 {
3557         struct mlx5_flow_dv_push_vlan_action_resource res;
3558
3559         memset(&res, 0, sizeof(res));
3560         res.vlan_tag =
3561                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3562                                  vlan->vlan_tci);
3563         if (attr->transfer)
3564                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3565         else
3566                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3567                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3568         return flow_dv_push_vlan_action_resource_register
3569                                             (dev, &res, dev_flow, error);
3570 }
3571
3572 static int fdb_mirror;
3573
3574 /**
3575  * Validate the modify-header actions.
3576  *
3577  * @param[in] action_flags
3578  *   Holds the actions detected until now.
3579  * @param[in] action
3580  *   Pointer to the modify action.
3581  * @param[out] error
3582  *   Pointer to error structure.
3583  *
3584  * @return
3585  *   0 on success, a negative errno value otherwise and rte_errno is set.
3586  */
3587 static int
3588 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3589                                    const struct rte_flow_action *action,
3590                                    struct rte_flow_error *error)
3591 {
3592         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3593                 return rte_flow_error_set(error, EINVAL,
3594                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3595                                           NULL, "action configuration not set");
3596         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3597                 return rte_flow_error_set(error, EINVAL,
3598                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3599                                           "can't have encap action before"
3600                                           " modify action");
3601         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3602                 return rte_flow_error_set(error, EINVAL,
3603                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3604                                           "can't support sample action before"
3605                                           " modify action for E-Switch"
3606                                           " mirroring");
3607         return 0;
3608 }
3609
3610 /**
3611  * Validate the modify-header MAC address actions.
3612  *
3613  * @param[in] action_flags
3614  *   Holds the actions detected until now.
3615  * @param[in] action
3616  *   Pointer to the modify action.
3617  * @param[in] item_flags
3618  *   Holds the items detected.
3619  * @param[out] error
3620  *   Pointer to error structure.
3621  *
3622  * @return
3623  *   0 on success, a negative errno value otherwise and rte_errno is set.
3624  */
3625 static int
3626 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3627                                    const struct rte_flow_action *action,
3628                                    const uint64_t item_flags,
3629                                    struct rte_flow_error *error)
3630 {
3631         int ret = 0;
3632
3633         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3634         if (!ret) {
3635                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3636                         return rte_flow_error_set(error, EINVAL,
3637                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3638                                                   NULL,
3639                                                   "no L2 item in pattern");
3640         }
3641         return ret;
3642 }
3643
3644 /**
3645  * Validate the modify-header IPv4 address actions.
3646  *
3647  * @param[in] action_flags
3648  *   Holds the actions detected until now.
3649  * @param[in] action
3650  *   Pointer to the modify action.
3651  * @param[in] item_flags
3652  *   Holds the items detected.
3653  * @param[out] error
3654  *   Pointer to error structure.
3655  *
3656  * @return
3657  *   0 on success, a negative errno value otherwise and rte_errno is set.
3658  */
3659 static int
3660 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3661                                     const struct rte_flow_action *action,
3662                                     const uint64_t item_flags,
3663                                     struct rte_flow_error *error)
3664 {
3665         int ret = 0;
3666         uint64_t layer;
3667
3668         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3669         if (!ret) {
3670                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3671                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3672                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3673                 if (!(item_flags & layer))
3674                         return rte_flow_error_set(error, EINVAL,
3675                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3676                                                   NULL,
3677                                                   "no ipv4 item in pattern");
3678         }
3679         return ret;
3680 }
3681
3682 /**
3683  * Validate the modify-header IPv6 address actions.
3684  *
3685  * @param[in] action_flags
3686  *   Holds the actions detected until now.
3687  * @param[in] action
3688  *   Pointer to the modify action.
3689  * @param[in] item_flags
3690  *   Holds the items detected.
3691  * @param[out] error
3692  *   Pointer to error structure.
3693  *
3694  * @return
3695  *   0 on success, a negative errno value otherwise and rte_errno is set.
3696  */
3697 static int
3698 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3699                                     const struct rte_flow_action *action,
3700                                     const uint64_t item_flags,
3701                                     struct rte_flow_error *error)
3702 {
3703         int ret = 0;
3704         uint64_t layer;
3705
3706         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3707         if (!ret) {
3708                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3709                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3710                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3711                 if (!(item_flags & layer))
3712                         return rte_flow_error_set(error, EINVAL,
3713                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3714                                                   NULL,
3715                                                   "no ipv6 item in pattern");
3716         }
3717         return ret;
3718 }
3719
3720 /**
3721  * Validate the modify-header TP actions.
3722  *
3723  * @param[in] action_flags
3724  *   Holds the actions detected until now.
3725  * @param[in] action
3726  *   Pointer to the modify action.
3727  * @param[in] item_flags
3728  *   Holds the items detected.
3729  * @param[out] error
3730  *   Pointer to error structure.
3731  *
3732  * @return
3733  *   0 on success, a negative errno value otherwise and rte_errno is set.
3734  */
3735 static int
3736 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3737                                   const struct rte_flow_action *action,
3738                                   const uint64_t item_flags,
3739                                   struct rte_flow_error *error)
3740 {
3741         int ret = 0;
3742         uint64_t layer;
3743
3744         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3745         if (!ret) {
3746                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3747                                  MLX5_FLOW_LAYER_INNER_L4 :
3748                                  MLX5_FLOW_LAYER_OUTER_L4;
3749                 if (!(item_flags & layer))
3750                         return rte_flow_error_set(error, EINVAL,
3751                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3752                                                   NULL, "no transport layer "
3753                                                   "in pattern");
3754         }
3755         return ret;
3756 }
3757
3758 /**
3759  * Validate the modify-header actions of increment/decrement
3760  * TCP Sequence-number.
3761  *
3762  * @param[in] action_flags
3763  *   Holds the actions detected until now.
3764  * @param[in] action
3765  *   Pointer to the modify action.
3766  * @param[in] item_flags
3767  *   Holds the items detected.
3768  * @param[out] error
3769  *   Pointer to error structure.
3770  *
3771  * @return
3772  *   0 on success, a negative errno value otherwise and rte_errno is set.
3773  */
3774 static int
3775 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3776                                        const struct rte_flow_action *action,
3777                                        const uint64_t item_flags,
3778                                        struct rte_flow_error *error)
3779 {
3780         int ret = 0;
3781         uint64_t layer;
3782
3783         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3784         if (!ret) {
3785                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3786                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3787                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3788                 if (!(item_flags & layer))
3789                         return rte_flow_error_set(error, EINVAL,
3790                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3791                                                   NULL, "no TCP item in"
3792                                                   " pattern");
3793                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3794                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3795                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3796                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3797                         return rte_flow_error_set(error, EINVAL,
3798                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3799                                                   NULL,
3800                                                   "cannot decrease and increase"
3801                                                   " TCP sequence number"
3802                                                   " at the same time");
3803         }
3804         return ret;
3805 }
3806
3807 /**
3808  * Validate the modify-header actions of increment/decrement
3809  * TCP Acknowledgment number.
3810  *
3811  * @param[in] action_flags
3812  *   Holds the actions detected until now.
3813  * @param[in] action
3814  *   Pointer to the modify action.
3815  * @param[in] item_flags
3816  *   Holds the items detected.
3817  * @param[out] error
3818  *   Pointer to error structure.
3819  *
3820  * @return
3821  *   0 on success, a negative errno value otherwise and rte_errno is set.
3822  */
3823 static int
3824 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3825                                        const struct rte_flow_action *action,
3826                                        const uint64_t item_flags,
3827                                        struct rte_flow_error *error)
3828 {
3829         int ret = 0;
3830         uint64_t layer;
3831
3832         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3833         if (!ret) {
3834                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3835                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3836                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3837                 if (!(item_flags & layer))
3838                         return rte_flow_error_set(error, EINVAL,
3839                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3840                                                   NULL, "no TCP item in"
3841                                                   " pattern");
3842                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3843                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3844                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3845                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3846                         return rte_flow_error_set(error, EINVAL,
3847                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3848                                                   NULL,
3849                                                   "cannot decrease and increase"
3850                                                   " TCP acknowledgment number"
3851                                                   " at the same time");
3852         }
3853         return ret;
3854 }
3855
3856 /**
3857  * Validate the modify-header TTL actions.
3858  *
3859  * @param[in] action_flags
3860  *   Holds the actions detected until now.
3861  * @param[in] action
3862  *   Pointer to the modify action.
3863  * @param[in] item_flags
3864  *   Holds the items detected.
3865  * @param[out] error
3866  *   Pointer to error structure.
3867  *
3868  * @return
3869  *   0 on success, a negative errno value otherwise and rte_errno is set.
3870  */
3871 static int
3872 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3873                                    const struct rte_flow_action *action,
3874                                    const uint64_t item_flags,
3875                                    struct rte_flow_error *error)
3876 {
3877         int ret = 0;
3878         uint64_t layer;
3879
3880         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3881         if (!ret) {
3882                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3883                                  MLX5_FLOW_LAYER_INNER_L3 :
3884                                  MLX5_FLOW_LAYER_OUTER_L3;
3885                 if (!(item_flags & layer))
3886                         return rte_flow_error_set(error, EINVAL,
3887                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3888                                                   NULL,
3889                                                   "no IP protocol in pattern");
3890         }
3891         return ret;
3892 }
3893
3894 /**
3895  * Validate jump action.
3896  *
3897  * @param[in] action
3898  *   Pointer to the jump action.
3899  * @param[in] action_flags
3900  *   Holds the actions detected until now.
3901  * @param[in] attributes
3902  *   Pointer to flow attributes
3903  * @param[in] external
3904  *   Action belongs to flow rule created by request external to PMD.
3905  * @param[out] error
3906  *   Pointer to error structure.
3907  *
3908  * @return
3909  *   0 on success, a negative errno value otherwise and rte_errno is set.
3910  */
3911 static int
3912 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
3913                              const struct mlx5_flow_tunnel *tunnel,
3914                              const struct rte_flow_action *action,
3915                              uint64_t action_flags,
3916                              const struct rte_flow_attr *attributes,
3917                              bool external, struct rte_flow_error *error)
3918 {
3919         uint32_t target_group, table;
3920         int ret = 0;
3921         struct flow_grp_info grp_info = {
3922                 .external = !!external,
3923                 .transfer = !!attributes->transfer,
3924                 .fdb_def_rule = 1,
3925                 .std_tbl_fix = 0
3926         };
3927         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3928                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3929                 return rte_flow_error_set(error, EINVAL,
3930                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3931                                           "can't have 2 fate actions in"
3932                                           " same flow");
3933         if (action_flags & MLX5_FLOW_ACTION_METER)
3934                 return rte_flow_error_set(error, ENOTSUP,
3935                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3936                                           "jump with meter not support");
3937         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) && fdb_mirror)
3938                 return rte_flow_error_set(error, EINVAL,
3939                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3940                                           "E-Switch mirroring can't support"
3941                                           " Sample action and jump action in"
3942                                           " same flow now");
3943         if (!action->conf)
3944                 return rte_flow_error_set(error, EINVAL,
3945                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3946                                           NULL, "action configuration not set");
3947         target_group =
3948                 ((const struct rte_flow_action_jump *)action->conf)->group;
3949         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
3950                                        grp_info, error);
3951         if (ret)
3952                 return ret;
3953         if (attributes->group == target_group &&
3954             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
3955                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
3956                 return rte_flow_error_set(error, EINVAL,
3957                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3958                                           "target group must be other than"
3959                                           " the current flow group");
3960         return 0;
3961 }
3962
3963 /*
3964  * Validate the port_id action.
3965  *
3966  * @param[in] dev
3967  *   Pointer to rte_eth_dev structure.
3968  * @param[in] action_flags
3969  *   Bit-fields that holds the actions detected until now.
3970  * @param[in] action
3971  *   Port_id RTE action structure.
3972  * @param[in] attr
3973  *   Attributes of flow that includes this action.
3974  * @param[out] error
3975  *   Pointer to error structure.
3976  *
3977  * @return
3978  *   0 on success, a negative errno value otherwise and rte_errno is set.
3979  */
3980 static int
3981 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3982                                 uint64_t action_flags,
3983                                 const struct rte_flow_action *action,
3984                                 const struct rte_flow_attr *attr,
3985                                 struct rte_flow_error *error)
3986 {
3987         const struct rte_flow_action_port_id *port_id;
3988         struct mlx5_priv *act_priv;
3989         struct mlx5_priv *dev_priv;
3990         uint16_t port;
3991
3992         if (!attr->transfer)
3993                 return rte_flow_error_set(error, ENOTSUP,
3994                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3995                                           NULL,
3996                                           "port id action is valid in transfer"
3997                                           " mode only");
3998         if (!action || !action->conf)
3999                 return rte_flow_error_set(error, ENOTSUP,
4000                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4001                                           NULL,
4002                                           "port id action parameters must be"
4003                                           " specified");
4004         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4005                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4006                 return rte_flow_error_set(error, EINVAL,
4007                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4008                                           "can have only one fate actions in"
4009                                           " a flow");
4010         dev_priv = mlx5_dev_to_eswitch_info(dev);
4011         if (!dev_priv)
4012                 return rte_flow_error_set(error, rte_errno,
4013                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4014                                           NULL,
4015                                           "failed to obtain E-Switch info");
4016         port_id = action->conf;
4017         port = port_id->original ? dev->data->port_id : port_id->id;
4018         act_priv = mlx5_port_to_eswitch_info(port, false);
4019         if (!act_priv)
4020                 return rte_flow_error_set
4021                                 (error, rte_errno,
4022                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4023                                  "failed to obtain E-Switch port id for port");
4024         if (act_priv->domain_id != dev_priv->domain_id)
4025                 return rte_flow_error_set
4026                                 (error, EINVAL,
4027                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4028                                  "port does not belong to"
4029                                  " E-Switch being configured");
4030         return 0;
4031 }
4032
4033 /**
4034  * Get the maximum number of modify header actions.
4035  *
4036  * @param dev
4037  *   Pointer to rte_eth_dev structure.
4038  * @param flags
4039  *   Flags bits to check if root level.
4040  *
4041  * @return
4042  *   Max number of modify header actions device can support.
4043  */
4044 static inline unsigned int
4045 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4046                               uint64_t flags)
4047 {
4048         /*
4049          * There's no way to directly query the max capacity from FW.
4050          * The maximal value on root table should be assumed to be supported.
4051          */
4052         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4053                 return MLX5_MAX_MODIFY_NUM;
4054         else
4055                 return MLX5_ROOT_TBL_MODIFY_NUM;
4056 }
4057
4058 /**
4059  * Validate the meter action.
4060  *
4061  * @param[in] dev
4062  *   Pointer to rte_eth_dev structure.
4063  * @param[in] action_flags
4064  *   Bit-fields that holds the actions detected until now.
4065  * @param[in] action
4066  *   Pointer to the meter action.
4067  * @param[in] attr
4068  *   Attributes of flow that includes this action.
4069  * @param[out] error
4070  *   Pointer to error structure.
4071  *
4072  * @return
4073  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4074  */
4075 static int
4076 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4077                                 uint64_t action_flags,
4078                                 const struct rte_flow_action *action,
4079                                 const struct rte_flow_attr *attr,
4080                                 struct rte_flow_error *error)
4081 {
4082         struct mlx5_priv *priv = dev->data->dev_private;
4083         const struct rte_flow_action_meter *am = action->conf;
4084         struct mlx5_flow_meter *fm;
4085
4086         if (!am)
4087                 return rte_flow_error_set(error, EINVAL,
4088                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4089                                           "meter action conf is NULL");
4090
4091         if (action_flags & MLX5_FLOW_ACTION_METER)
4092                 return rte_flow_error_set(error, ENOTSUP,
4093                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4094                                           "meter chaining not support");
4095         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4096                 return rte_flow_error_set(error, ENOTSUP,
4097                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4098                                           "meter with jump not support");
4099         if (!priv->mtr_en)
4100                 return rte_flow_error_set(error, ENOTSUP,
4101                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4102                                           NULL,
4103                                           "meter action not supported");
4104         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4105         if (!fm)
4106                 return rte_flow_error_set(error, EINVAL,
4107                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4108                                           "Meter not found");
4109         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4110               (!fm->ingress && !attr->ingress && attr->egress) ||
4111               (!fm->egress && !attr->egress && attr->ingress))))
4112                 return rte_flow_error_set(error, EINVAL,
4113                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4114                                           "Flow attributes are either invalid "
4115                                           "or have a conflict with current "
4116                                           "meter attributes");
4117         return 0;
4118 }
4119
4120 /**
4121  * Validate the age action.
4122  *
4123  * @param[in] action_flags
4124  *   Holds the actions detected until now.
4125  * @param[in] action
4126  *   Pointer to the age action.
4127  * @param[in] dev
4128  *   Pointer to the Ethernet device structure.
4129  * @param[out] error
4130  *   Pointer to error structure.
4131  *
4132  * @return
4133  *   0 on success, a negative errno value otherwise and rte_errno is set.
4134  */
4135 static int
4136 flow_dv_validate_action_age(uint64_t action_flags,
4137                             const struct rte_flow_action *action,
4138                             struct rte_eth_dev *dev,
4139                             struct rte_flow_error *error)
4140 {
4141         struct mlx5_priv *priv = dev->data->dev_private;
4142         const struct rte_flow_action_age *age = action->conf;
4143
4144         if (!priv->config.devx || priv->sh->cmng.counter_fallback)
4145                 return rte_flow_error_set(error, ENOTSUP,
4146                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4147                                           NULL,
4148                                           "age action not supported");
4149         if (!(action->conf))
4150                 return rte_flow_error_set(error, EINVAL,
4151                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4152                                           "configuration cannot be null");
4153         if (!(age->timeout))
4154                 return rte_flow_error_set(error, EINVAL,
4155                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4156                                           "invalid timeout value 0");
4157         if (action_flags & MLX5_FLOW_ACTION_AGE)
4158                 return rte_flow_error_set(error, EINVAL,
4159                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4160                                           "duplicate age actions set");
4161         return 0;
4162 }
4163
4164 /**
4165  * Validate the modify-header IPv4 DSCP actions.
4166  *
4167  * @param[in] action_flags
4168  *   Holds the actions detected until now.
4169  * @param[in] action
4170  *   Pointer to the modify action.
4171  * @param[in] item_flags
4172  *   Holds the items detected.
4173  * @param[out] error
4174  *   Pointer to error structure.
4175  *
4176  * @return
4177  *   0 on success, a negative errno value otherwise and rte_errno is set.
4178  */
4179 static int
4180 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4181                                          const struct rte_flow_action *action,
4182                                          const uint64_t item_flags,
4183                                          struct rte_flow_error *error)
4184 {
4185         int ret = 0;
4186
4187         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4188         if (!ret) {
4189                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4190                         return rte_flow_error_set(error, EINVAL,
4191                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4192                                                   NULL,
4193                                                   "no ipv4 item in pattern");
4194         }
4195         return ret;
4196 }
4197
4198 /**
4199  * Validate the modify-header IPv6 DSCP actions.
4200  *
4201  * @param[in] action_flags
4202  *   Holds the actions detected until now.
4203  * @param[in] action
4204  *   Pointer to the modify action.
4205  * @param[in] item_flags
4206  *   Holds the items detected.
4207  * @param[out] error
4208  *   Pointer to error structure.
4209  *
4210  * @return
4211  *   0 on success, a negative errno value otherwise and rte_errno is set.
4212  */
4213 static int
4214 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4215                                          const struct rte_flow_action *action,
4216                                          const uint64_t item_flags,
4217                                          struct rte_flow_error *error)
4218 {
4219         int ret = 0;
4220
4221         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4222         if (!ret) {
4223                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4224                         return rte_flow_error_set(error, EINVAL,
4225                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4226                                                   NULL,
4227                                                   "no ipv6 item in pattern");
4228         }
4229         return ret;
4230 }
4231
4232 /**
4233  * Match modify-header resource.
4234  *
4235  * @param list
4236  *   Pointer to the hash list.
4237  * @param entry
4238  *   Pointer to exist resource entry object.
4239  * @param key
4240  *   Key of the new entry.
4241  * @param ctx
4242  *   Pointer to new modify-header resource.
4243  *
4244  * @return
4245  *   0 on matching, non-zero otherwise.
4246  */
4247 int
4248 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
4249                         struct mlx5_hlist_entry *entry,
4250                         uint64_t key __rte_unused, void *cb_ctx)
4251 {
4252         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4253         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4254         struct mlx5_flow_dv_modify_hdr_resource *resource =
4255                         container_of(entry, typeof(*resource), entry);
4256         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4257
4258         key_len += ref->actions_num * sizeof(ref->actions[0]);
4259         return ref->actions_num != resource->actions_num ||
4260                memcmp(&ref->ft_type, &resource->ft_type, key_len);
4261 }
4262
4263 struct mlx5_hlist_entry *
4264 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
4265                          void *cb_ctx)
4266 {
4267         struct mlx5_dev_ctx_shared *sh = list->ctx;
4268         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
4269         struct mlx5dv_dr_domain *ns;
4270         struct mlx5_flow_dv_modify_hdr_resource *entry;
4271         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
4272         int ret;
4273         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
4274         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
4275
4276         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
4277                             SOCKET_ID_ANY);
4278         if (!entry) {
4279                 rte_flow_error_set(ctx->error, ENOMEM,
4280                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4281                                    "cannot allocate resource memory");
4282                 return NULL;
4283         }
4284         rte_memcpy(&entry->ft_type,
4285                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
4286                    key_len + data_len);
4287         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
4288                 ns = sh->fdb_domain;
4289         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4290                 ns = sh->tx_domain;
4291         else
4292                 ns = sh->rx_domain;
4293         ret = mlx5_flow_os_create_flow_action_modify_header
4294                                         (sh->ctx, ns, entry,
4295                                          data_len, &entry->action);
4296         if (ret) {
4297                 mlx5_free(entry);
4298                 rte_flow_error_set(ctx->error, ENOMEM,
4299                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4300                                    NULL, "cannot create modification action");
4301                 return NULL;
4302         }
4303         return &entry->entry;
4304 }
4305
4306 /**
4307  * Validate the sample action.
4308  *
4309  * @param[in] action_flags
4310  *   Holds the actions detected until now.
4311  * @param[in] action
4312  *   Pointer to the sample action.
4313  * @param[in] dev
4314  *   Pointer to the Ethernet device structure.
4315  * @param[in] attr
4316  *   Attributes of flow that includes this action.
4317  * @param[out] error
4318  *   Pointer to error structure.
4319  *
4320  * @return
4321  *   0 on success, a negative errno value otherwise and rte_errno is set.
4322  */
4323 static int
4324 flow_dv_validate_action_sample(uint64_t action_flags,
4325                                const struct rte_flow_action *action,
4326                                struct rte_eth_dev *dev,
4327                                const struct rte_flow_attr *attr,
4328                                struct rte_flow_error *error)
4329 {
4330         struct mlx5_priv *priv = dev->data->dev_private;
4331         struct mlx5_dev_config *dev_conf = &priv->config;
4332         const struct rte_flow_action_sample *sample = action->conf;
4333         const struct rte_flow_action *act;
4334         uint64_t sub_action_flags = 0;
4335         uint16_t queue_index = 0xFFFF;
4336         int actions_n = 0;
4337         int ret;
4338         fdb_mirror = 0;
4339
4340         if (!sample)
4341                 return rte_flow_error_set(error, EINVAL,
4342                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4343                                           "configuration cannot be NULL");
4344         if (sample->ratio == 0)
4345                 return rte_flow_error_set(error, EINVAL,
4346                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4347                                           "ratio value starts from 1");
4348         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
4349                 return rte_flow_error_set(error, ENOTSUP,
4350                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4351                                           NULL,
4352                                           "sample action not supported");
4353         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
4354                 return rte_flow_error_set(error, EINVAL,
4355                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4356                                           "Multiple sample actions not "
4357                                           "supported");
4358         if (action_flags & MLX5_FLOW_ACTION_METER)
4359                 return rte_flow_error_set(error, EINVAL,
4360                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4361                                           "wrong action order, meter should "
4362                                           "be after sample action");
4363         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4364                 return rte_flow_error_set(error, EINVAL,
4365                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4366                                           "wrong action order, jump should "
4367                                           "be after sample action");
4368         act = sample->actions;
4369         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
4370                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4371                         return rte_flow_error_set(error, ENOTSUP,
4372                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4373                                                   act, "too many actions");
4374                 switch (act->type) {
4375                 case RTE_FLOW_ACTION_TYPE_QUEUE:
4376                         ret = mlx5_flow_validate_action_queue(act,
4377                                                               sub_action_flags,
4378                                                               dev,
4379                                                               attr, error);
4380                         if (ret < 0)
4381                                 return ret;
4382                         queue_index = ((const struct rte_flow_action_queue *)
4383                                                         (act->conf))->index;
4384                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
4385                         ++actions_n;
4386                         break;
4387                 case RTE_FLOW_ACTION_TYPE_MARK:
4388                         ret = flow_dv_validate_action_mark(dev, act,
4389                                                            sub_action_flags,
4390                                                            attr, error);
4391                         if (ret < 0)
4392                                 return ret;
4393                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
4394                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
4395                                                 MLX5_FLOW_ACTION_MARK_EXT;
4396                         else
4397                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
4398                         ++actions_n;
4399                         break;
4400                 case RTE_FLOW_ACTION_TYPE_COUNT:
4401                         ret = flow_dv_validate_action_count(dev, error);
4402                         if (ret < 0)
4403                                 return ret;
4404                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
4405                         ++actions_n;
4406                         break;
4407                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4408                         ret = flow_dv_validate_action_port_id(dev,
4409                                                               sub_action_flags,
4410                                                               act,
4411                                                               attr,
4412                                                               error);
4413                         if (ret)
4414                                 return ret;
4415                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4416                         ++actions_n;
4417                         break;
4418                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4419                         ret = flow_dv_validate_action_raw_encap_decap
4420                                 (dev, NULL, act->conf, attr, &sub_action_flags,
4421                                  &actions_n, error);
4422                         if (ret < 0)
4423                                 return ret;
4424                         ++actions_n;
4425                         break;
4426                 default:
4427                         return rte_flow_error_set(error, ENOTSUP,
4428                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4429                                                   NULL,
4430                                                   "Doesn't support optional "
4431                                                   "action");
4432                 }
4433         }
4434         if (attr->ingress && !attr->transfer) {
4435                 if (!(sub_action_flags & MLX5_FLOW_ACTION_QUEUE))
4436                         return rte_flow_error_set(error, EINVAL,
4437                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4438                                                   NULL,
4439                                                   "Ingress must has a dest "
4440                                                   "QUEUE for Sample");
4441         } else if (attr->egress && !attr->transfer) {
4442                 return rte_flow_error_set(error, ENOTSUP,
4443                                           RTE_FLOW_ERROR_TYPE_ACTION,
4444                                           NULL,
4445                                           "Sample Only support Ingress "
4446                                           "or E-Switch");
4447         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
4448                 MLX5_ASSERT(attr->transfer);
4449                 if (sample->ratio > 1)
4450                         return rte_flow_error_set(error, ENOTSUP,
4451                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4452                                                   NULL,
4453                                                   "E-Switch doesn't support "
4454                                                   "any optional action "
4455                                                   "for sampling");
4456                 fdb_mirror = 1;
4457                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
4458                         return rte_flow_error_set(error, ENOTSUP,
4459                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4460                                                   NULL,
4461                                                   "unsupported action QUEUE");
4462                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
4463                         return rte_flow_error_set(error, EINVAL,
4464                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4465                                                   NULL,
4466                                                   "E-Switch must has a dest "
4467                                                   "port for mirroring");
4468         }
4469         /* Continue validation for Xcap actions.*/
4470         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
4471             (queue_index == 0xFFFF ||
4472              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
4473                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
4474                      MLX5_FLOW_XCAP_ACTIONS)
4475                         return rte_flow_error_set(error, ENOTSUP,
4476                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4477                                                   NULL, "encap and decap "
4478                                                   "combination aren't "
4479                                                   "supported");
4480                 if (!attr->transfer && attr->ingress && (sub_action_flags &
4481                                                         MLX5_FLOW_ACTION_ENCAP))
4482                         return rte_flow_error_set(error, ENOTSUP,
4483                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4484                                                   NULL, "encap is not supported"
4485                                                   " for ingress traffic");
4486         }
4487         return 0;
4488 }
4489
4490 /**
4491  * Find existing modify-header resource or create and register a new one.
4492  *
4493  * @param dev[in, out]
4494  *   Pointer to rte_eth_dev structure.
4495  * @param[in, out] resource
4496  *   Pointer to modify-header resource.
4497  * @parm[in, out] dev_flow
4498  *   Pointer to the dev_flow.
4499  * @param[out] error
4500  *   pointer to error structure.
4501  *
4502  * @return
4503  *   0 on success otherwise -errno and errno is set.
4504  */
4505 static int
4506 flow_dv_modify_hdr_resource_register
4507                         (struct rte_eth_dev *dev,
4508                          struct mlx5_flow_dv_modify_hdr_resource *resource,
4509                          struct mlx5_flow *dev_flow,
4510                          struct rte_flow_error *error)
4511 {
4512         struct mlx5_priv *priv = dev->data->dev_private;
4513         struct mlx5_dev_ctx_shared *sh = priv->sh;
4514         uint32_t key_len = sizeof(*resource) -
4515                            offsetof(typeof(*resource), ft_type) +
4516                            resource->actions_num * sizeof(resource->actions[0]);
4517         struct mlx5_hlist_entry *entry;
4518         struct mlx5_flow_cb_ctx ctx = {
4519                 .error = error,
4520                 .data = resource,
4521         };
4522
4523         resource->flags = dev_flow->dv.group ? 0 :
4524                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4525         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
4526                                     resource->flags))
4527                 return rte_flow_error_set(error, EOVERFLOW,
4528                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4529                                           "too many modify header items");
4530         resource->entry.key = __rte_raw_cksum(&resource->ft_type, key_len, 0);
4531         entry = mlx5_hlist_register(sh->modify_cmds, resource->entry.key, &ctx);
4532         if (!entry)
4533                 return -rte_errno;
4534         resource = container_of(entry, typeof(*resource), entry);
4535         dev_flow->handle->dvh.modify_hdr = resource;
4536         return 0;
4537 }
4538
4539 /**
4540  * Get DV flow counter by index.
4541  *
4542  * @param[in] dev
4543  *   Pointer to the Ethernet device structure.
4544  * @param[in] idx
4545  *   mlx5 flow counter index in the container.
4546  * @param[out] ppool
4547  *   mlx5 flow counter pool in the container,
4548  *
4549  * @return
4550  *   Pointer to the counter, NULL otherwise.
4551  */
4552 static struct mlx5_flow_counter *
4553 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4554                            uint32_t idx,
4555                            struct mlx5_flow_counter_pool **ppool)
4556 {
4557         struct mlx5_priv *priv = dev->data->dev_private;
4558         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4559         struct mlx5_flow_counter_pool *pool;
4560
4561         /* Decrease to original index and clear shared bit. */
4562         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
4563         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
4564         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
4565         MLX5_ASSERT(pool);
4566         if (ppool)
4567                 *ppool = pool;
4568         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4569 }
4570
4571 /**
4572  * Check the devx counter belongs to the pool.
4573  *
4574  * @param[in] pool
4575  *   Pointer to the counter pool.
4576  * @param[in] id
4577  *   The counter devx ID.
4578  *
4579  * @return
4580  *   True if counter belongs to the pool, false otherwise.
4581  */
4582 static bool
4583 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4584 {
4585         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4586                    MLX5_COUNTERS_PER_POOL;
4587
4588         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4589                 return true;
4590         return false;
4591 }
4592
4593 /**
4594  * Get a pool by devx counter ID.
4595  *
4596  * @param[in] cmng
4597  *   Pointer to the counter management.
4598  * @param[in] id
4599  *   The counter devx ID.
4600  *
4601  * @return
4602  *   The counter pool pointer if exists, NULL otherwise,
4603  */
4604 static struct mlx5_flow_counter_pool *
4605 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
4606 {
4607         uint32_t i;
4608         struct mlx5_flow_counter_pool *pool = NULL;
4609
4610         rte_spinlock_lock(&cmng->pool_update_sl);
4611         /* Check last used pool. */
4612         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
4613             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
4614                 pool = cmng->pools[cmng->last_pool_idx];
4615                 goto out;
4616         }
4617         /* ID out of range means no suitable pool in the container. */
4618         if (id > cmng->max_id || id < cmng->min_id)
4619                 goto out;
4620         /*
4621          * Find the pool from the end of the container, since mostly counter
4622          * ID is sequence increasing, and the last pool should be the needed
4623          * one.
4624          */
4625         i = cmng->n_valid;
4626         while (i--) {
4627                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
4628
4629                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
4630                         pool = pool_tmp;
4631                         break;
4632                 }
4633         }
4634 out:
4635         rte_spinlock_unlock(&cmng->pool_update_sl);
4636         return pool;
4637 }
4638
4639 /**
4640  * Resize a counter container.
4641  *
4642  * @param[in] dev
4643  *   Pointer to the Ethernet device structure.
4644  *
4645  * @return
4646  *   0 on success, otherwise negative errno value and rte_errno is set.
4647  */
4648 static int
4649 flow_dv_container_resize(struct rte_eth_dev *dev)
4650 {
4651         struct mlx5_priv *priv = dev->data->dev_private;
4652         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4653         void *old_pools = cmng->pools;
4654         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
4655         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4656         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4657
4658         if (!pools) {
4659                 rte_errno = ENOMEM;
4660                 return -ENOMEM;
4661         }
4662         if (old_pools)
4663                 memcpy(pools, old_pools, cmng->n *
4664                                        sizeof(struct mlx5_flow_counter_pool *));
4665         cmng->n = resize;
4666         cmng->pools = pools;
4667         if (old_pools)
4668                 mlx5_free(old_pools);
4669         return 0;
4670 }
4671
4672 /**
4673  * Query a devx flow counter.
4674  *
4675  * @param[in] dev
4676  *   Pointer to the Ethernet device structure.
4677  * @param[in] cnt
4678  *   Index to the flow counter.
4679  * @param[out] pkts
4680  *   The statistics value of packets.
4681  * @param[out] bytes
4682  *   The statistics value of bytes.
4683  *
4684  * @return
4685  *   0 on success, otherwise a negative errno value and rte_errno is set.
4686  */
4687 static inline int
4688 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4689                      uint64_t *bytes)
4690 {
4691         struct mlx5_priv *priv = dev->data->dev_private;
4692         struct mlx5_flow_counter_pool *pool = NULL;
4693         struct mlx5_flow_counter *cnt;
4694         int offset;
4695
4696         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4697         MLX5_ASSERT(pool);
4698         if (priv->sh->cmng.counter_fallback)
4699                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
4700                                         0, pkts, bytes, 0, NULL, NULL, 0);
4701         rte_spinlock_lock(&pool->sl);
4702         if (!pool->raw) {
4703                 *pkts = 0;
4704                 *bytes = 0;
4705         } else {
4706                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4707                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4708                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4709         }
4710         rte_spinlock_unlock(&pool->sl);
4711         return 0;
4712 }
4713
4714 /**
4715  * Create and initialize a new counter pool.
4716  *
4717  * @param[in] dev
4718  *   Pointer to the Ethernet device structure.
4719  * @param[out] dcs
4720  *   The devX counter handle.
4721  * @param[in] age
4722  *   Whether the pool is for counter that was allocated for aging.
4723  * @param[in/out] cont_cur
4724  *   Pointer to the container pointer, it will be update in pool resize.
4725  *
4726  * @return
4727  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4728  */
4729 static struct mlx5_flow_counter_pool *
4730 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4731                     uint32_t age)
4732 {
4733         struct mlx5_priv *priv = dev->data->dev_private;
4734         struct mlx5_flow_counter_pool *pool;
4735         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4736         bool fallback = priv->sh->cmng.counter_fallback;
4737         uint32_t size = sizeof(*pool);
4738
4739         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
4740         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
4741         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4742         if (!pool) {
4743                 rte_errno = ENOMEM;
4744                 return NULL;
4745         }
4746         pool->raw = NULL;
4747         pool->is_aged = !!age;
4748         pool->query_gen = 0;
4749         pool->min_dcs = dcs;
4750         rte_spinlock_init(&pool->sl);
4751         rte_spinlock_init(&pool->csl);
4752         TAILQ_INIT(&pool->counters[0]);
4753         TAILQ_INIT(&pool->counters[1]);
4754         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
4755         rte_spinlock_lock(&cmng->pool_update_sl);
4756         pool->index = cmng->n_valid;
4757         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
4758                 mlx5_free(pool);
4759                 rte_spinlock_unlock(&cmng->pool_update_sl);
4760                 return NULL;
4761         }
4762         cmng->pools[pool->index] = pool;
4763         cmng->n_valid++;
4764         if (unlikely(fallback)) {
4765                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4766
4767                 if (base < cmng->min_id)
4768                         cmng->min_id = base;
4769                 if (base > cmng->max_id)
4770                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4771                 cmng->last_pool_idx = pool->index;
4772         }
4773         rte_spinlock_unlock(&cmng->pool_update_sl);
4774         return pool;
4775 }
4776
4777 /**
4778  * Prepare a new counter and/or a new counter pool.
4779  *
4780  * @param[in] dev
4781  *   Pointer to the Ethernet device structure.
4782  * @param[out] cnt_free
4783  *   Where to put the pointer of a new counter.
4784  * @param[in] age
4785  *   Whether the pool is for counter that was allocated for aging.
4786  *
4787  * @return
4788  *   The counter pool pointer and @p cnt_free is set on success,
4789  *   NULL otherwise and rte_errno is set.
4790  */
4791 static struct mlx5_flow_counter_pool *
4792 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4793                              struct mlx5_flow_counter **cnt_free,
4794                              uint32_t age)
4795 {
4796         struct mlx5_priv *priv = dev->data->dev_private;
4797         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4798         struct mlx5_flow_counter_pool *pool;
4799         struct mlx5_counters tmp_tq;
4800         struct mlx5_devx_obj *dcs = NULL;
4801         struct mlx5_flow_counter *cnt;
4802         enum mlx5_counter_type cnt_type =
4803                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4804         bool fallback = priv->sh->cmng.counter_fallback;
4805         uint32_t i;
4806
4807         if (fallback) {
4808                 /* bulk_bitmap must be 0 for single counter allocation. */
4809                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4810                 if (!dcs)
4811                         return NULL;
4812                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
4813                 if (!pool) {
4814                         pool = flow_dv_pool_create(dev, dcs, age);
4815                         if (!pool) {
4816                                 mlx5_devx_cmd_destroy(dcs);
4817                                 return NULL;
4818                         }
4819                 }
4820                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4821                 cnt = MLX5_POOL_GET_CNT(pool, i);
4822                 cnt->pool = pool;
4823                 cnt->dcs_when_free = dcs;
4824                 *cnt_free = cnt;
4825                 return pool;
4826         }
4827         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4828         if (!dcs) {
4829                 rte_errno = ENODATA;
4830                 return NULL;
4831         }
4832         pool = flow_dv_pool_create(dev, dcs, age);
4833         if (!pool) {
4834                 mlx5_devx_cmd_destroy(dcs);
4835                 return NULL;
4836         }
4837         TAILQ_INIT(&tmp_tq);
4838         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4839                 cnt = MLX5_POOL_GET_CNT(pool, i);
4840                 cnt->pool = pool;
4841                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4842         }
4843         rte_spinlock_lock(&cmng->csl[cnt_type]);
4844         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
4845         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4846         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4847         (*cnt_free)->pool = pool;
4848         return pool;
4849 }
4850
4851 /**
4852  * Allocate a flow counter.
4853  *
4854  * @param[in] dev
4855  *   Pointer to the Ethernet device structure.
4856  * @param[in] age
4857  *   Whether the counter was allocated for aging.
4858  *
4859  * @return
4860  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4861  */
4862 static uint32_t
4863 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
4864 {
4865         struct mlx5_priv *priv = dev->data->dev_private;
4866         struct mlx5_flow_counter_pool *pool = NULL;
4867         struct mlx5_flow_counter *cnt_free = NULL;
4868         bool fallback = priv->sh->cmng.counter_fallback;
4869         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
4870         enum mlx5_counter_type cnt_type =
4871                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
4872         uint32_t cnt_idx;
4873
4874         if (!priv->config.devx) {
4875                 rte_errno = ENOTSUP;
4876                 return 0;
4877         }
4878         /* Get free counters from container. */
4879         rte_spinlock_lock(&cmng->csl[cnt_type]);
4880         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
4881         if (cnt_free)
4882                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
4883         rte_spinlock_unlock(&cmng->csl[cnt_type]);
4884         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
4885                 goto err;
4886         pool = cnt_free->pool;
4887         if (fallback)
4888                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
4889         /* Create a DV counter action only in the first time usage. */
4890         if (!cnt_free->action) {
4891                 uint16_t offset;
4892                 struct mlx5_devx_obj *dcs;
4893                 int ret;
4894
4895                 if (!fallback) {
4896                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4897                         dcs = pool->min_dcs;
4898                 } else {
4899                         offset = 0;
4900                         dcs = cnt_free->dcs_when_free;
4901                 }
4902                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4903                                                             &cnt_free->action);
4904                 if (ret) {
4905                         rte_errno = errno;
4906                         goto err;
4907                 }
4908         }
4909         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4910                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4911         /* Update the counter reset values. */
4912         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4913                                  &cnt_free->bytes))
4914                 goto err;
4915         if (!fallback && !priv->sh->cmng.query_thread_on)
4916                 /* Start the asynchronous batch query by the host thread. */
4917                 mlx5_set_query_alarm(priv->sh);
4918         return cnt_idx;
4919 err:
4920         if (cnt_free) {
4921                 cnt_free->pool = pool;
4922                 if (fallback)
4923                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
4924                 rte_spinlock_lock(&cmng->csl[cnt_type]);
4925                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
4926                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
4927         }
4928         return 0;
4929 }
4930
4931 /**
4932  * Allocate a shared flow counter.
4933  *
4934  * @param[in] ctx
4935  *   Pointer to the shared counter configuration.
4936  * @param[in] data
4937  *   Pointer to save the allocated counter index.
4938  *
4939  * @return
4940  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4941  */
4942
4943 static int32_t
4944 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
4945 {
4946         struct mlx5_shared_counter_conf *conf = ctx;
4947         struct rte_eth_dev *dev = conf->dev;
4948         struct mlx5_flow_counter *cnt;
4949
4950         data->dword = flow_dv_counter_alloc(dev, 0);
4951         data->dword |= MLX5_CNT_SHARED_OFFSET;
4952         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
4953         cnt->shared_info.id = conf->id;
4954         return 0;
4955 }
4956
4957 /**
4958  * Get a shared flow counter.
4959  *
4960  * @param[in] dev
4961  *   Pointer to the Ethernet device structure.
4962  * @param[in] id
4963  *   Counter identifier.
4964  *
4965  * @return
4966  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4967  */
4968 static uint32_t
4969 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
4970 {
4971         struct mlx5_priv *priv = dev->data->dev_private;
4972         struct mlx5_shared_counter_conf conf = {
4973                 .dev = dev,
4974                 .id = id,
4975         };
4976         union mlx5_l3t_data data = {
4977                 .dword = 0,
4978         };
4979
4980         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
4981                                flow_dv_counter_alloc_shared_cb, &conf);
4982         return data.dword;
4983 }
4984
4985 /**
4986  * Get age param from counter index.
4987  *
4988  * @param[in] dev
4989  *   Pointer to the Ethernet device structure.
4990  * @param[in] counter
4991  *   Index to the counter handler.
4992  *
4993  * @return
4994  *   The aging parameter specified for the counter index.
4995  */
4996 static struct mlx5_age_param*
4997 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4998                                 uint32_t counter)
4999 {
5000         struct mlx5_flow_counter *cnt;
5001         struct mlx5_flow_counter_pool *pool = NULL;
5002
5003         flow_dv_counter_get_by_idx(dev, counter, &pool);
5004         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5005         cnt = MLX5_POOL_GET_CNT(pool, counter);
5006         return MLX5_CNT_TO_AGE(cnt);
5007 }
5008
5009 /**
5010  * Remove a flow counter from aged counter list.
5011  *
5012  * @param[in] dev
5013  *   Pointer to the Ethernet device structure.
5014  * @param[in] counter
5015  *   Index to the counter handler.
5016  * @param[in] cnt
5017  *   Pointer to the counter handler.
5018  */
5019 static void
5020 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5021                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5022 {
5023         struct mlx5_age_info *age_info;
5024         struct mlx5_age_param *age_param;
5025         struct mlx5_priv *priv = dev->data->dev_private;
5026         uint16_t expected = AGE_CANDIDATE;
5027
5028         age_info = GET_PORT_AGE_INFO(priv);
5029         age_param = flow_dv_counter_idx_get_age(dev, counter);
5030         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5031                                          AGE_FREE, false, __ATOMIC_RELAXED,
5032                                          __ATOMIC_RELAXED)) {
5033                 /**
5034                  * We need the lock even it is age timeout,
5035                  * since counter may still in process.
5036                  */
5037                 rte_spinlock_lock(&age_info->aged_sl);
5038                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5039                 rte_spinlock_unlock(&age_info->aged_sl);
5040                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5041         }
5042 }
5043
5044 /**
5045  * Release a flow counter.
5046  *
5047  * @param[in] dev
5048  *   Pointer to the Ethernet device structure.
5049  * @param[in] counter
5050  *   Index to the counter handler.
5051  */
5052 static void
5053 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
5054 {
5055         struct mlx5_priv *priv = dev->data->dev_private;
5056         struct mlx5_flow_counter_pool *pool = NULL;
5057         struct mlx5_flow_counter *cnt;
5058         enum mlx5_counter_type cnt_type;
5059
5060         if (!counter)
5061                 return;
5062         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5063         MLX5_ASSERT(pool);
5064         if (IS_SHARED_CNT(counter) &&
5065             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5066                 return;
5067         if (pool->is_aged)
5068                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5069         cnt->pool = pool;
5070         /*
5071          * Put the counter back to list to be updated in none fallback mode.
5072          * Currently, we are using two list alternately, while one is in query,
5073          * add the freed counter to the other list based on the pool query_gen
5074          * value. After query finishes, add counter the list to the global
5075          * container counter list. The list changes while query starts. In
5076          * this case, lock will not be needed as query callback and release
5077          * function both operate with the different list.
5078          *
5079          */
5080         if (!priv->sh->cmng.counter_fallback) {
5081                 rte_spinlock_lock(&pool->csl);
5082                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5083                 rte_spinlock_unlock(&pool->csl);
5084         } else {
5085                 cnt->dcs_when_free = cnt->dcs_when_active;
5086                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5087                                            MLX5_COUNTER_TYPE_ORIGIN;
5088                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5089                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5090                                   cnt, next);
5091                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5092         }
5093 }
5094
5095 /**
5096  * Verify the @p attributes will be correctly understood by the NIC and store
5097  * them in the @p flow if everything is correct.
5098  *
5099  * @param[in] dev
5100  *   Pointer to dev struct.
5101  * @param[in] attributes
5102  *   Pointer to flow attributes
5103  * @param[in] external
5104  *   This flow rule is created by request external to PMD.
5105  * @param[out] error
5106  *   Pointer to error structure.
5107  *
5108  * @return
5109  *   - 0 on success and non root table.
5110  *   - 1 on success and root table.
5111  *   - a negative errno value otherwise and rte_errno is set.
5112  */
5113 static int
5114 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5115                             const struct mlx5_flow_tunnel *tunnel,
5116                             const struct rte_flow_attr *attributes,
5117                             struct flow_grp_info grp_info,
5118                             struct rte_flow_error *error)
5119 {
5120         struct mlx5_priv *priv = dev->data->dev_private;
5121         uint32_t priority_max = priv->config.flow_prio - 1;
5122         int ret = 0;
5123
5124 #ifndef HAVE_MLX5DV_DR
5125         RTE_SET_USED(tunnel);
5126         RTE_SET_USED(grp_info);
5127         if (attributes->group)
5128                 return rte_flow_error_set(error, ENOTSUP,
5129                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5130                                           NULL,
5131                                           "groups are not supported");
5132 #else
5133         uint32_t table = 0;
5134
5135         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5136                                        grp_info, error);
5137         if (ret)
5138                 return ret;
5139         if (!table)
5140                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5141 #endif
5142         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
5143             attributes->priority >= priority_max)
5144                 return rte_flow_error_set(error, ENOTSUP,
5145                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5146                                           NULL,
5147                                           "priority out of range");
5148         if (attributes->transfer) {
5149                 if (!priv->config.dv_esw_en)
5150                         return rte_flow_error_set
5151                                 (error, ENOTSUP,
5152                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5153                                  "E-Switch dr is not supported");
5154                 if (!(priv->representor || priv->master))
5155                         return rte_flow_error_set
5156                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5157                                  NULL, "E-Switch configuration can only be"
5158                                  " done by a master or a representor device");
5159                 if (attributes->egress)
5160                         return rte_flow_error_set
5161                                 (error, ENOTSUP,
5162                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5163                                  "egress is not supported");
5164         }
5165         if (!(attributes->egress ^ attributes->ingress))
5166                 return rte_flow_error_set(error, ENOTSUP,
5167                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5168                                           "must specify exactly one of "
5169                                           "ingress or egress");
5170         return ret;
5171 }
5172
5173 /**
5174  * Internal validation function. For validating both actions and items.
5175  *
5176  * @param[in] dev
5177  *   Pointer to the rte_eth_dev structure.
5178  * @param[in] attr
5179  *   Pointer to the flow attributes.
5180  * @param[in] items
5181  *   Pointer to the list of items.
5182  * @param[in] actions
5183  *   Pointer to the list of actions.
5184  * @param[in] external
5185  *   This flow rule is created by request external to PMD.
5186  * @param[in] hairpin
5187  *   Number of hairpin TX actions, 0 means classic flow.
5188  * @param[out] error
5189  *   Pointer to the error structure.
5190  *
5191  * @return
5192  *   0 on success, a negative errno value otherwise and rte_errno is set.
5193  */
5194 static int
5195 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
5196                  const struct rte_flow_item items[],
5197                  const struct rte_flow_action actions[],
5198                  bool external, int hairpin, struct rte_flow_error *error)
5199 {
5200         int ret;
5201         uint64_t action_flags = 0;
5202         uint64_t item_flags = 0;
5203         uint64_t last_item = 0;
5204         uint8_t next_protocol = 0xff;
5205         uint16_t ether_type = 0;
5206         int actions_n = 0;
5207         uint8_t item_ipv6_proto = 0;
5208         const struct rte_flow_item *gre_item = NULL;
5209         const struct rte_flow_action_raw_decap *decap;
5210         const struct rte_flow_action_raw_encap *encap;
5211         const struct rte_flow_action_rss *rss;
5212         const struct rte_flow_item_tcp nic_tcp_mask = {
5213                 .hdr = {
5214                         .tcp_flags = 0xFF,
5215                         .src_port = RTE_BE16(UINT16_MAX),
5216                         .dst_port = RTE_BE16(UINT16_MAX),
5217                 }
5218         };
5219         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
5220                 .hdr = {
5221                         .src_addr =
5222                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5223                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5224                         .dst_addr =
5225                         "\xff\xff\xff\xff\xff\xff\xff\xff"
5226                         "\xff\xff\xff\xff\xff\xff\xff\xff",
5227                         .vtc_flow = RTE_BE32(0xffffffff),
5228                         .proto = 0xff,
5229                         .hop_limits = 0xff,
5230                 },
5231                 .has_frag_ext = 1,
5232         };
5233         const struct rte_flow_item_ecpri nic_ecpri_mask = {
5234                 .hdr = {
5235                         .common = {
5236                                 .u32 =
5237                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
5238                                         .type = 0xFF,
5239                                         }).u32),
5240                         },
5241                         .dummy[0] = 0xffffffff,
5242                 },
5243         };
5244         struct mlx5_priv *priv = dev->data->dev_private;
5245         struct mlx5_dev_config *dev_conf = &priv->config;
5246         uint16_t queue_index = 0xFFFF;
5247         const struct rte_flow_item_vlan *vlan_m = NULL;
5248         int16_t rw_act_num = 0;
5249         uint64_t is_root;
5250         const struct mlx5_flow_tunnel *tunnel;
5251         struct flow_grp_info grp_info = {
5252                 .external = !!external,
5253                 .transfer = !!attr->transfer,
5254                 .fdb_def_rule = !!priv->fdb_def_rule,
5255         };
5256         const struct rte_eth_hairpin_conf *conf;
5257
5258         if (items == NULL)
5259                 return -1;
5260         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
5261                 tunnel = flow_items_to_tunnel(items);
5262                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
5263                                 MLX5_FLOW_ACTION_DECAP;
5264         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
5265                 tunnel = flow_actions_to_tunnel(actions);
5266                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5267         } else {
5268                 tunnel = NULL;
5269         }
5270         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
5271                                 (dev, tunnel, attr, items, actions);
5272         ret = flow_dv_validate_attributes(dev, tunnel, attr, grp_info, error);
5273         if (ret < 0)
5274                 return ret;
5275         is_root = (uint64_t)ret;
5276         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
5277                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
5278                 int type = items->type;
5279
5280                 if (!mlx5_flow_os_item_supported(type))
5281                         return rte_flow_error_set(error, ENOTSUP,
5282                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5283                                                   NULL, "item not supported");
5284                 switch (type) {
5285                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
5286                         if (items[0].type != (typeof(items[0].type))
5287                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
5288                                 return rte_flow_error_set
5289                                                 (error, EINVAL,
5290                                                 RTE_FLOW_ERROR_TYPE_ITEM,
5291                                                 NULL, "MLX5 private items "
5292                                                 "must be the first");
5293                         break;
5294                 case RTE_FLOW_ITEM_TYPE_VOID:
5295                         break;
5296                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
5297                         ret = flow_dv_validate_item_port_id
5298                                         (dev, items, attr, item_flags, error);
5299                         if (ret < 0)
5300                                 return ret;
5301                         last_item = MLX5_FLOW_ITEM_PORT_ID;
5302                         break;
5303                 case RTE_FLOW_ITEM_TYPE_ETH:
5304                         ret = mlx5_flow_validate_item_eth(items, item_flags,
5305                                                           true, error);
5306                         if (ret < 0)
5307                                 return ret;
5308                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
5309                                              MLX5_FLOW_LAYER_OUTER_L2;
5310                         if (items->mask != NULL && items->spec != NULL) {
5311                                 ether_type =
5312                                         ((const struct rte_flow_item_eth *)
5313                                          items->spec)->type;
5314                                 ether_type &=
5315                                         ((const struct rte_flow_item_eth *)
5316                                          items->mask)->type;
5317                                 ether_type = rte_be_to_cpu_16(ether_type);
5318                         } else {
5319                                 ether_type = 0;
5320                         }
5321                         break;
5322                 case RTE_FLOW_ITEM_TYPE_VLAN:
5323                         ret = flow_dv_validate_item_vlan(items, item_flags,
5324                                                          dev, error);
5325                         if (ret < 0)
5326                                 return ret;
5327                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
5328                                              MLX5_FLOW_LAYER_OUTER_VLAN;
5329                         if (items->mask != NULL && items->spec != NULL) {
5330                                 ether_type =
5331                                         ((const struct rte_flow_item_vlan *)
5332                                          items->spec)->inner_type;
5333                                 ether_type &=
5334                                         ((const struct rte_flow_item_vlan *)
5335                                          items->mask)->inner_type;
5336                                 ether_type = rte_be_to_cpu_16(ether_type);
5337                         } else {
5338                                 ether_type = 0;
5339                         }
5340                         /* Store outer VLAN mask for of_push_vlan action. */
5341                         if (!tunnel)
5342                                 vlan_m = items->mask;
5343                         break;
5344                 case RTE_FLOW_ITEM_TYPE_IPV4:
5345                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5346                                                   &item_flags, &tunnel);
5347                         ret = flow_dv_validate_item_ipv4(items, item_flags,
5348                                                          last_item, ether_type,
5349                                                          error);
5350                         if (ret < 0)
5351                                 return ret;
5352                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5353                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5354                         if (items->mask != NULL &&
5355                             ((const struct rte_flow_item_ipv4 *)
5356                              items->mask)->hdr.next_proto_id) {
5357                                 next_protocol =
5358                                         ((const struct rte_flow_item_ipv4 *)
5359                                          (items->spec))->hdr.next_proto_id;
5360                                 next_protocol &=
5361                                         ((const struct rte_flow_item_ipv4 *)
5362                                          (items->mask))->hdr.next_proto_id;
5363                         } else {
5364                                 /* Reset for inner layer. */
5365                                 next_protocol = 0xff;
5366                         }
5367                         break;
5368                 case RTE_FLOW_ITEM_TYPE_IPV6:
5369                         mlx5_flow_tunnel_ip_check(items, next_protocol,
5370                                                   &item_flags, &tunnel);
5371                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5372                                                            last_item,
5373                                                            ether_type,
5374                                                            &nic_ipv6_mask,
5375                                                            error);
5376                         if (ret < 0)
5377                                 return ret;
5378                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5379                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5380                         if (items->mask != NULL &&
5381                             ((const struct rte_flow_item_ipv6 *)
5382                              items->mask)->hdr.proto) {
5383                                 item_ipv6_proto =
5384                                         ((const struct rte_flow_item_ipv6 *)
5385                                          items->spec)->hdr.proto;
5386                                 next_protocol =
5387                                         ((const struct rte_flow_item_ipv6 *)
5388                                          items->spec)->hdr.proto;
5389                                 next_protocol &=
5390                                         ((const struct rte_flow_item_ipv6 *)
5391                                          items->mask)->hdr.proto;
5392                         } else {
5393                                 /* Reset for inner layer. */
5394                                 next_protocol = 0xff;
5395                         }
5396                         break;
5397                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
5398                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
5399                                                                   item_flags,
5400                                                                   error);
5401                         if (ret < 0)
5402                                 return ret;
5403                         last_item = tunnel ?
5404                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
5405                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
5406                         if (items->mask != NULL &&
5407                             ((const struct rte_flow_item_ipv6_frag_ext *)
5408                              items->mask)->hdr.next_header) {
5409                                 next_protocol =
5410                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5411                                  items->spec)->hdr.next_header;
5412                                 next_protocol &=
5413                                 ((const struct rte_flow_item_ipv6_frag_ext *)
5414                                  items->mask)->hdr.next_header;
5415                         } else {
5416                                 /* Reset for inner layer. */
5417                                 next_protocol = 0xff;
5418                         }
5419                         break;
5420                 case RTE_FLOW_ITEM_TYPE_TCP:
5421                         ret = mlx5_flow_validate_item_tcp
5422                                                 (items, item_flags,
5423                                                  next_protocol,
5424                                                  &nic_tcp_mask,
5425                                                  error);
5426                         if (ret < 0)
5427                                 return ret;
5428                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5429                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5430                         break;
5431                 case RTE_FLOW_ITEM_TYPE_UDP:
5432                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5433                                                           next_protocol,
5434                                                           error);
5435                         if (ret < 0)
5436                                 return ret;
5437                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5438                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5439                         break;
5440                 case RTE_FLOW_ITEM_TYPE_GRE:
5441                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5442                                                           next_protocol, error);
5443                         if (ret < 0)
5444                                 return ret;
5445                         gre_item = items;
5446                         last_item = MLX5_FLOW_LAYER_GRE;
5447                         break;
5448                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5449                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5450                                                             next_protocol,
5451                                                             error);
5452                         if (ret < 0)
5453                                 return ret;
5454                         last_item = MLX5_FLOW_LAYER_NVGRE;
5455                         break;
5456                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5457                         ret = mlx5_flow_validate_item_gre_key
5458                                 (items, item_flags, gre_item, error);
5459                         if (ret < 0)
5460                                 return ret;
5461                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5462                         break;
5463                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5464                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5465                                                             error);
5466                         if (ret < 0)
5467                                 return ret;
5468                         last_item = MLX5_FLOW_LAYER_VXLAN;
5469                         break;
5470                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5471                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5472                                                                 item_flags, dev,
5473                                                                 error);
5474                         if (ret < 0)
5475                                 return ret;
5476                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5477                         break;
5478                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5479                         ret = mlx5_flow_validate_item_geneve(items,
5480                                                              item_flags, dev,
5481                                                              error);
5482                         if (ret < 0)
5483                                 return ret;
5484                         last_item = MLX5_FLOW_LAYER_GENEVE;
5485                         break;
5486                 case RTE_FLOW_ITEM_TYPE_MPLS:
5487                         ret = mlx5_flow_validate_item_mpls(dev, items,
5488                                                            item_flags,
5489                                                            last_item, error);
5490                         if (ret < 0)
5491                                 return ret;
5492                         last_item = MLX5_FLOW_LAYER_MPLS;
5493                         break;
5494
5495                 case RTE_FLOW_ITEM_TYPE_MARK:
5496                         ret = flow_dv_validate_item_mark(dev, items, attr,
5497                                                          error);
5498                         if (ret < 0)
5499                                 return ret;
5500                         last_item = MLX5_FLOW_ITEM_MARK;
5501                         break;
5502                 case RTE_FLOW_ITEM_TYPE_META:
5503                         ret = flow_dv_validate_item_meta(dev, items, attr,
5504                                                          error);
5505                         if (ret < 0)
5506                                 return ret;
5507                         last_item = MLX5_FLOW_ITEM_METADATA;
5508                         break;
5509                 case RTE_FLOW_ITEM_TYPE_ICMP:
5510                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5511                                                            next_protocol,
5512                                                            error);
5513                         if (ret < 0)
5514                                 return ret;
5515                         last_item = MLX5_FLOW_LAYER_ICMP;
5516                         break;
5517                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5518                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5519                                                             next_protocol,
5520                                                             error);
5521                         if (ret < 0)
5522                                 return ret;
5523                         item_ipv6_proto = IPPROTO_ICMPV6;
5524                         last_item = MLX5_FLOW_LAYER_ICMP6;
5525                         break;
5526                 case RTE_FLOW_ITEM_TYPE_TAG:
5527                         ret = flow_dv_validate_item_tag(dev, items,
5528                                                         attr, error);
5529                         if (ret < 0)
5530                                 return ret;
5531                         last_item = MLX5_FLOW_ITEM_TAG;
5532                         break;
5533                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5534                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5535                         break;
5536                 case RTE_FLOW_ITEM_TYPE_GTP:
5537                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5538                                                         error);
5539                         if (ret < 0)
5540                                 return ret;
5541                         last_item = MLX5_FLOW_LAYER_GTP;
5542                         break;
5543                 case RTE_FLOW_ITEM_TYPE_ECPRI:
5544                         /* Capacity will be checked in the translate stage. */
5545                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5546                                                             last_item,
5547                                                             ether_type,
5548                                                             &nic_ecpri_mask,
5549                                                             error);
5550                         if (ret < 0)
5551                                 return ret;
5552                         last_item = MLX5_FLOW_LAYER_ECPRI;
5553                         break;
5554                 default:
5555                         return rte_flow_error_set(error, ENOTSUP,
5556                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5557                                                   NULL, "item not supported");
5558                 }
5559                 item_flags |= last_item;
5560         }
5561         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5562                 int type = actions->type;
5563
5564                 if (!mlx5_flow_os_action_supported(type))
5565                         return rte_flow_error_set(error, ENOTSUP,
5566                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5567                                                   actions,
5568                                                   "action not supported");
5569                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5570                         return rte_flow_error_set(error, ENOTSUP,
5571                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5572                                                   actions, "too many actions");
5573                 switch (type) {
5574                 case RTE_FLOW_ACTION_TYPE_VOID:
5575                         break;
5576                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5577                         ret = flow_dv_validate_action_port_id(dev,
5578                                                               action_flags,
5579                                                               actions,
5580                                                               attr,
5581                                                               error);
5582                         if (ret)
5583                                 return ret;
5584                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5585                         ++actions_n;
5586                         break;
5587                 case RTE_FLOW_ACTION_TYPE_FLAG:
5588                         ret = flow_dv_validate_action_flag(dev, action_flags,
5589                                                            attr, error);
5590                         if (ret < 0)
5591                                 return ret;
5592                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5593                                 /* Count all modify-header actions as one. */
5594                                 if (!(action_flags &
5595                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5596                                         ++actions_n;
5597                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5598                                                 MLX5_FLOW_ACTION_MARK_EXT;
5599                         } else {
5600                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5601                                 ++actions_n;
5602                         }
5603                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5604                         break;
5605                 case RTE_FLOW_ACTION_TYPE_MARK:
5606                         ret = flow_dv_validate_action_mark(dev, actions,
5607                                                            action_flags,
5608                                                            attr, error);
5609                         if (ret < 0)
5610                                 return ret;
5611                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5612                                 /* Count all modify-header actions as one. */
5613                                 if (!(action_flags &
5614                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5615                                         ++actions_n;
5616                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5617                                                 MLX5_FLOW_ACTION_MARK_EXT;
5618                         } else {
5619                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5620                                 ++actions_n;
5621                         }
5622                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5623                         break;
5624                 case RTE_FLOW_ACTION_TYPE_SET_META:
5625                         ret = flow_dv_validate_action_set_meta(dev, actions,
5626                                                                action_flags,
5627                                                                attr, error);
5628                         if (ret < 0)
5629                                 return ret;
5630                         /* Count all modify-header actions as one action. */
5631                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5632                                 ++actions_n;
5633                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5634                         rw_act_num += MLX5_ACT_NUM_SET_META;
5635                         break;
5636                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5637                         ret = flow_dv_validate_action_set_tag(dev, actions,
5638                                                               action_flags,
5639                                                               attr, error);
5640                         if (ret < 0)
5641                                 return ret;
5642                         /* Count all modify-header actions as one action. */
5643                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5644                                 ++actions_n;
5645                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5646                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5647                         break;
5648                 case RTE_FLOW_ACTION_TYPE_DROP:
5649                         ret = mlx5_flow_validate_action_drop(action_flags,
5650                                                              attr, error);
5651                         if (ret < 0)
5652                                 return ret;
5653                         action_flags |= MLX5_FLOW_ACTION_DROP;
5654                         ++actions_n;
5655                         break;
5656                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5657                         ret = mlx5_flow_validate_action_queue(actions,
5658                                                               action_flags, dev,
5659                                                               attr, error);
5660                         if (ret < 0)
5661                                 return ret;
5662                         queue_index = ((const struct rte_flow_action_queue *)
5663                                                         (actions->conf))->index;
5664                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5665                         ++actions_n;
5666                         break;
5667                 case RTE_FLOW_ACTION_TYPE_RSS:
5668                         rss = actions->conf;
5669                         ret = mlx5_flow_validate_action_rss(actions,
5670                                                             action_flags, dev,
5671                                                             attr, item_flags,
5672                                                             error);
5673                         if (ret < 0)
5674                                 return ret;
5675                         if (rss != NULL && rss->queue_num)
5676                                 queue_index = rss->queue[0];
5677                         action_flags |= MLX5_FLOW_ACTION_RSS;
5678                         ++actions_n;
5679                         break;
5680                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5681                         ret =
5682                         mlx5_flow_validate_action_default_miss(action_flags,
5683                                         attr, error);
5684                         if (ret < 0)
5685                                 return ret;
5686                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5687                         ++actions_n;
5688                         break;
5689                 case RTE_FLOW_ACTION_TYPE_COUNT:
5690                         ret = flow_dv_validate_action_count(dev, error);
5691                         if (ret < 0)
5692                                 return ret;
5693                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5694                         ++actions_n;
5695                         break;
5696                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5697                         if (flow_dv_validate_action_pop_vlan(dev,
5698                                                              action_flags,
5699                                                              actions,
5700                                                              item_flags, attr,
5701                                                              error))
5702                                 return -rte_errno;
5703                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5704                         ++actions_n;
5705                         break;
5706                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5707                         ret = flow_dv_validate_action_push_vlan(dev,
5708                                                                 action_flags,
5709                                                                 vlan_m,
5710                                                                 actions, attr,
5711                                                                 error);
5712                         if (ret < 0)
5713                                 return ret;
5714                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5715                         ++actions_n;
5716                         break;
5717                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5718                         ret = flow_dv_validate_action_set_vlan_pcp
5719                                                 (action_flags, actions, error);
5720                         if (ret < 0)
5721                                 return ret;
5722                         /* Count PCP with push_vlan command. */
5723                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5724                         break;
5725                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5726                         ret = flow_dv_validate_action_set_vlan_vid
5727                                                 (item_flags, action_flags,
5728                                                  actions, error);
5729                         if (ret < 0)
5730                                 return ret;
5731                         /* Count VID with push_vlan command. */
5732                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5733                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5734                         break;
5735                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5736                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5737                         ret = flow_dv_validate_action_l2_encap(dev,
5738                                                                action_flags,
5739                                                                actions, attr,
5740                                                                error);
5741                         if (ret < 0)
5742                                 return ret;
5743                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5744                         ++actions_n;
5745                         break;
5746                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5747                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5748                         ret = flow_dv_validate_action_decap(dev, action_flags,
5749                                                             attr, error);
5750                         if (ret < 0)
5751                                 return ret;
5752                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5753                         ++actions_n;
5754                         break;
5755                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5756                         ret = flow_dv_validate_action_raw_encap_decap
5757                                 (dev, NULL, actions->conf, attr, &action_flags,
5758                                  &actions_n, error);
5759                         if (ret < 0)
5760                                 return ret;
5761                         break;
5762                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5763                         decap = actions->conf;
5764                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5765                                 ;
5766                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5767                                 encap = NULL;
5768                                 actions--;
5769                         } else {
5770                                 encap = actions->conf;
5771                         }
5772                         ret = flow_dv_validate_action_raw_encap_decap
5773                                            (dev,
5774                                             decap ? decap : &empty_decap, encap,
5775                                             attr, &action_flags, &actions_n,
5776                                             error);
5777                         if (ret < 0)
5778                                 return ret;
5779                         break;
5780                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5781                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5782                         ret = flow_dv_validate_action_modify_mac(action_flags,
5783                                                                  actions,
5784                                                                  item_flags,
5785                                                                  error);
5786                         if (ret < 0)
5787                                 return ret;
5788                         /* Count all modify-header actions as one action. */
5789                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5790                                 ++actions_n;
5791                         action_flags |= actions->type ==
5792                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5793                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5794                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5795                         /*
5796                          * Even if the source and destination MAC addresses have
5797                          * overlap in the header with 4B alignment, the convert
5798                          * function will handle them separately and 4 SW actions
5799                          * will be created. And 2 actions will be added each
5800                          * time no matter how many bytes of address will be set.
5801                          */
5802                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5803                         break;
5804                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5805                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5806                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5807                                                                   actions,
5808                                                                   item_flags,
5809                                                                   error);
5810                         if (ret < 0)
5811                                 return ret;
5812                         /* Count all modify-header actions as one action. */
5813                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5814                                 ++actions_n;
5815                         action_flags |= actions->type ==
5816                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5817                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5818                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5819                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5820                         break;
5821                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5822                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5823                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5824                                                                   actions,
5825                                                                   item_flags,
5826                                                                   error);
5827                         if (ret < 0)
5828                                 return ret;
5829                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5830                                 return rte_flow_error_set(error, ENOTSUP,
5831                                         RTE_FLOW_ERROR_TYPE_ACTION,
5832                                         actions,
5833                                         "Can't change header "
5834                                         "with ICMPv6 proto");
5835                         /* Count all modify-header actions as one action. */
5836                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5837                                 ++actions_n;
5838                         action_flags |= actions->type ==
5839                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5840                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5841                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5842                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5843                         break;
5844                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5845                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5846                         ret = flow_dv_validate_action_modify_tp(action_flags,
5847                                                                 actions,
5848                                                                 item_flags,
5849                                                                 error);
5850                         if (ret < 0)
5851                                 return ret;
5852                         /* Count all modify-header actions as one action. */
5853                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5854                                 ++actions_n;
5855                         action_flags |= actions->type ==
5856                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5857                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5858                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5859                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5860                         break;
5861                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5862                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5863                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5864                                                                  actions,
5865                                                                  item_flags,
5866                                                                  error);
5867                         if (ret < 0)
5868                                 return ret;
5869                         /* Count all modify-header actions as one action. */
5870                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5871                                 ++actions_n;
5872                         action_flags |= actions->type ==
5873                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5874                                                 MLX5_FLOW_ACTION_SET_TTL :
5875                                                 MLX5_FLOW_ACTION_DEC_TTL;
5876                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5877                         break;
5878                 case RTE_FLOW_ACTION_TYPE_JUMP:
5879                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
5880                                                            action_flags,
5881                                                            attr, external,
5882                                                            error);
5883                         if (ret)
5884                                 return ret;
5885                         ++actions_n;
5886                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5887                         break;
5888                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5889                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5890                         ret = flow_dv_validate_action_modify_tcp_seq
5891                                                                 (action_flags,
5892                                                                  actions,
5893                                                                  item_flags,
5894                                                                  error);
5895                         if (ret < 0)
5896                                 return ret;
5897                         /* Count all modify-header actions as one action. */
5898                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5899                                 ++actions_n;
5900                         action_flags |= actions->type ==
5901                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5902                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5903                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5904                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5905                         break;
5906                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5907                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5908                         ret = flow_dv_validate_action_modify_tcp_ack
5909                                                                 (action_flags,
5910                                                                  actions,
5911                                                                  item_flags,
5912                                                                  error);
5913                         if (ret < 0)
5914                                 return ret;
5915                         /* Count all modify-header actions as one action. */
5916                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5917                                 ++actions_n;
5918                         action_flags |= actions->type ==
5919                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5920                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5921                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5922                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5923                         break;
5924                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5925                         break;
5926                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5927                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5928                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5929                         break;
5930                 case RTE_FLOW_ACTION_TYPE_METER:
5931                         ret = mlx5_flow_validate_action_meter(dev,
5932                                                               action_flags,
5933                                                               actions, attr,
5934                                                               error);
5935                         if (ret < 0)
5936                                 return ret;
5937                         action_flags |= MLX5_FLOW_ACTION_METER;
5938                         ++actions_n;
5939                         /* Meter action will add one more TAG action. */
5940                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5941                         break;
5942                 case RTE_FLOW_ACTION_TYPE_AGE:
5943                         ret = flow_dv_validate_action_age(action_flags,
5944                                                           actions, dev,
5945                                                           error);
5946                         if (ret < 0)
5947                                 return ret;
5948                         action_flags |= MLX5_FLOW_ACTION_AGE;
5949                         ++actions_n;
5950                         break;
5951                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5952                         ret = flow_dv_validate_action_modify_ipv4_dscp
5953                                                          (action_flags,
5954                                                           actions,
5955                                                           item_flags,
5956                                                           error);
5957                         if (ret < 0)
5958                                 return ret;
5959                         /* Count all modify-header actions as one action. */
5960                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5961                                 ++actions_n;
5962                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5963                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5964                         break;
5965                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5966                         ret = flow_dv_validate_action_modify_ipv6_dscp
5967                                                                 (action_flags,
5968                                                                  actions,
5969                                                                  item_flags,
5970                                                                  error);
5971                         if (ret < 0)
5972                                 return ret;
5973                         /* Count all modify-header actions as one action. */
5974                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5975                                 ++actions_n;
5976                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5977                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5978                         break;
5979                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
5980                         ret = flow_dv_validate_action_sample(action_flags,
5981                                                              actions, dev,
5982                                                              attr, error);
5983                         if (ret < 0)
5984                                 return ret;
5985                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
5986                         ++actions_n;
5987                         break;
5988                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
5989                         if (actions[0].type != (typeof(actions[0].type))
5990                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
5991                                 return rte_flow_error_set
5992                                                 (error, EINVAL,
5993                                                 RTE_FLOW_ERROR_TYPE_ACTION,
5994                                                 NULL, "MLX5 private action "
5995                                                 "must be the first");
5996
5997                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
5998                         break;
5999                 default:
6000                         return rte_flow_error_set(error, ENOTSUP,
6001                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6002                                                   actions,
6003                                                   "action not supported");
6004                 }
6005         }
6006         /*
6007          * Validate actions in flow rules
6008          * - Explicit decap action is prohibited by the tunnel offload API.
6009          * - Drop action in tunnel steer rule is prohibited by the API.
6010          * - Application cannot use MARK action because it's value can mask
6011          *   tunnel default miss nitification.
6012          * - JUMP in tunnel match rule has no support in current PMD
6013          *   implementation.
6014          * - TAG & META are reserved for future uses.
6015          */
6016         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6017                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6018                                             MLX5_FLOW_ACTION_MARK     |
6019                                             MLX5_FLOW_ACTION_SET_TAG  |
6020                                             MLX5_FLOW_ACTION_SET_META |
6021                                             MLX5_FLOW_ACTION_DROP;
6022
6023                 if (action_flags & bad_actions_mask)
6024                         return rte_flow_error_set
6025                                         (error, EINVAL,
6026                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6027                                         "Invalid RTE action in tunnel "
6028                                         "set decap rule");
6029                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6030                         return rte_flow_error_set
6031                                         (error, EINVAL,
6032                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6033                                         "tunnel set decap rule must terminate "
6034                                         "with JUMP");
6035                 if (!attr->ingress)
6036                         return rte_flow_error_set
6037                                         (error, EINVAL,
6038                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6039                                         "tunnel flows for ingress traffic only");
6040         }
6041         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6042                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6043                                             MLX5_FLOW_ACTION_MARK    |
6044                                             MLX5_FLOW_ACTION_SET_TAG |
6045                                             MLX5_FLOW_ACTION_SET_META;
6046
6047                 if (action_flags & bad_actions_mask)
6048                         return rte_flow_error_set
6049                                         (error, EINVAL,
6050                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6051                                         "Invalid RTE action in tunnel "
6052                                         "set match rule");
6053         }
6054         /*
6055          * Validate the drop action mutual exclusion with other actions.
6056          * Drop action is mutually-exclusive with any other action, except for
6057          * Count action.
6058          */
6059         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
6060             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
6061                 return rte_flow_error_set(error, EINVAL,
6062                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6063                                           "Drop action is mutually-exclusive "
6064                                           "with any other action, except for "
6065                                           "Count action");
6066         /* Eswitch has few restrictions on using items and actions */
6067         if (attr->transfer) {
6068                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6069                     action_flags & MLX5_FLOW_ACTION_FLAG)
6070                         return rte_flow_error_set(error, ENOTSUP,
6071                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6072                                                   NULL,
6073                                                   "unsupported action FLAG");
6074                 if (!mlx5_flow_ext_mreg_supported(dev) &&
6075                     action_flags & MLX5_FLOW_ACTION_MARK)
6076                         return rte_flow_error_set(error, ENOTSUP,
6077                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6078                                                   NULL,
6079                                                   "unsupported action MARK");
6080                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
6081                         return rte_flow_error_set(error, ENOTSUP,
6082                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6083                                                   NULL,
6084                                                   "unsupported action QUEUE");
6085                 if (action_flags & MLX5_FLOW_ACTION_RSS)
6086                         return rte_flow_error_set(error, ENOTSUP,
6087                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6088                                                   NULL,
6089                                                   "unsupported action RSS");
6090                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
6091                         return rte_flow_error_set(error, EINVAL,
6092                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6093                                                   actions,
6094                                                   "no fate action is found");
6095         } else {
6096                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
6097                         return rte_flow_error_set(error, EINVAL,
6098                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6099                                                   actions,
6100                                                   "no fate action is found");
6101         }
6102         /*
6103          * Continue validation for Xcap and VLAN actions.
6104          * If hairpin is working in explicit TX rule mode, there is no actions
6105          * splitting and the validation of hairpin ingress flow should be the
6106          * same as other standard flows.
6107          */
6108         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
6109                              MLX5_FLOW_VLAN_ACTIONS)) &&
6110             (queue_index == 0xFFFF ||
6111              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
6112              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
6113              conf->tx_explicit != 0))) {
6114                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
6115                     MLX5_FLOW_XCAP_ACTIONS)
6116                         return rte_flow_error_set(error, ENOTSUP,
6117                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6118                                                   NULL, "encap and decap "
6119                                                   "combination aren't supported");
6120                 if (!attr->transfer && attr->ingress) {
6121                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
6122                                 return rte_flow_error_set
6123                                                 (error, ENOTSUP,
6124                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6125                                                  NULL, "encap is not supported"
6126                                                  " for ingress traffic");
6127                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
6128                                 return rte_flow_error_set
6129                                                 (error, ENOTSUP,
6130                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6131                                                  NULL, "push VLAN action not "
6132                                                  "supported for ingress");
6133                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
6134                                         MLX5_FLOW_VLAN_ACTIONS)
6135                                 return rte_flow_error_set
6136                                                 (error, ENOTSUP,
6137                                                  RTE_FLOW_ERROR_TYPE_ACTION,
6138                                                  NULL, "no support for "
6139                                                  "multiple VLAN actions");
6140                 }
6141         }
6142         /*
6143          * Hairpin flow will add one more TAG action in TX implicit mode.
6144          * In TX explicit mode, there will be no hairpin flow ID.
6145          */
6146         if (hairpin > 0)
6147                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6148         /* extra metadata enabled: one more TAG action will be add. */
6149         if (dev_conf->dv_flow_en &&
6150             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
6151             mlx5_flow_ext_mreg_supported(dev))
6152                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
6153         if ((uint32_t)rw_act_num >
6154                         flow_dv_modify_hdr_action_max(dev, is_root)) {
6155                 return rte_flow_error_set(error, ENOTSUP,
6156                                           RTE_FLOW_ERROR_TYPE_ACTION,
6157                                           NULL, "too many header modify"
6158                                           " actions to support");
6159         }
6160         return 0;
6161 }
6162
6163 /**
6164  * Internal preparation function. Allocates the DV flow size,
6165  * this size is constant.
6166  *
6167  * @param[in] dev
6168  *   Pointer to the rte_eth_dev structure.
6169  * @param[in] attr
6170  *   Pointer to the flow attributes.
6171  * @param[in] items
6172  *   Pointer to the list of items.
6173  * @param[in] actions
6174  *   Pointer to the list of actions.
6175  * @param[out] error
6176  *   Pointer to the error structure.
6177  *
6178  * @return
6179  *   Pointer to mlx5_flow object on success,
6180  *   otherwise NULL and rte_errno is set.
6181  */
6182 static struct mlx5_flow *
6183 flow_dv_prepare(struct rte_eth_dev *dev,
6184                 const struct rte_flow_attr *attr __rte_unused,
6185                 const struct rte_flow_item items[] __rte_unused,
6186                 const struct rte_flow_action actions[] __rte_unused,
6187                 struct rte_flow_error *error)
6188 {
6189         uint32_t handle_idx = 0;
6190         struct mlx5_flow *dev_flow;
6191         struct mlx5_flow_handle *dev_handle;
6192         struct mlx5_priv *priv = dev->data->dev_private;
6193         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
6194
6195         MLX5_ASSERT(wks);
6196         /* In case of corrupting the memory. */
6197         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
6198                 rte_flow_error_set(error, ENOSPC,
6199                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6200                                    "not free temporary device flow");
6201                 return NULL;
6202         }
6203         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
6204                                    &handle_idx);
6205         if (!dev_handle) {
6206                 rte_flow_error_set(error, ENOMEM,
6207                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6208                                    "not enough memory to create flow handle");
6209                 return NULL;
6210         }
6211         MLX5_ASSERT(wks->flow_idx + 1 < RTE_DIM(wks->flows));
6212         dev_flow = &wks->flows[wks->flow_idx++];
6213         dev_flow->handle = dev_handle;
6214         dev_flow->handle_idx = handle_idx;
6215         /*
6216          * In some old rdma-core releases, before continuing, a check of the
6217          * length of matching parameter will be done at first. It needs to use
6218          * the length without misc4 param. If the flow has misc4 support, then
6219          * the length needs to be adjusted accordingly. Each param member is
6220          * aligned with a 64B boundary naturally.
6221          */
6222         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
6223                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
6224         /*
6225          * The matching value needs to be cleared to 0 before using. In the
6226          * past, it will be automatically cleared when using rte_*alloc
6227          * API. The time consumption will be almost the same as before.
6228          */
6229         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
6230         dev_flow->ingress = attr->ingress;
6231         dev_flow->dv.transfer = attr->transfer;
6232         return dev_flow;
6233 }
6234
6235 #ifdef RTE_LIBRTE_MLX5_DEBUG
6236 /**
6237  * Sanity check for match mask and value. Similar to check_valid_spec() in
6238  * kernel driver. If unmasked bit is present in value, it returns failure.
6239  *
6240  * @param match_mask
6241  *   pointer to match mask buffer.
6242  * @param match_value
6243  *   pointer to match value buffer.
6244  *
6245  * @return
6246  *   0 if valid, -EINVAL otherwise.
6247  */
6248 static int
6249 flow_dv_check_valid_spec(void *match_mask, void *match_value)
6250 {
6251         uint8_t *m = match_mask;
6252         uint8_t *v = match_value;
6253         unsigned int i;
6254
6255         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
6256                 if (v[i] & ~m[i]) {
6257                         DRV_LOG(ERR,
6258                                 "match_value differs from match_criteria"
6259                                 " %p[%u] != %p[%u]",
6260                                 match_value, i, match_mask, i);
6261                         return -EINVAL;
6262                 }
6263         }
6264         return 0;
6265 }
6266 #endif
6267
6268 /**
6269  * Add match of ip_version.
6270  *
6271  * @param[in] group
6272  *   Flow group.
6273  * @param[in] headers_v
6274  *   Values header pointer.
6275  * @param[in] headers_m
6276  *   Masks header pointer.
6277  * @param[in] ip_version
6278  *   The IP version to set.
6279  */
6280 static inline void
6281 flow_dv_set_match_ip_version(uint32_t group,
6282                              void *headers_v,
6283                              void *headers_m,
6284                              uint8_t ip_version)
6285 {
6286         if (group == 0)
6287                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
6288         else
6289                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
6290                          ip_version);
6291         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
6292         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
6293         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
6294 }
6295
6296 /**
6297  * Add Ethernet item to matcher and to the value.
6298  *
6299  * @param[in, out] matcher
6300  *   Flow matcher.
6301  * @param[in, out] key
6302  *   Flow matcher value.
6303  * @param[in] item
6304  *   Flow pattern to translate.
6305  * @param[in] inner
6306  *   Item is inner pattern.
6307  */
6308 static void
6309 flow_dv_translate_item_eth(void *matcher, void *key,
6310                            const struct rte_flow_item *item, int inner,
6311                            uint32_t group)
6312 {
6313         const struct rte_flow_item_eth *eth_m = item->mask;
6314         const struct rte_flow_item_eth *eth_v = item->spec;
6315         const struct rte_flow_item_eth nic_mask = {
6316                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6317                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
6318                 .type = RTE_BE16(0xffff),
6319                 .has_vlan = 0,
6320         };
6321         void *hdrs_m;
6322         void *hdrs_v;
6323         char *l24_v;
6324         unsigned int i;
6325
6326         if (!eth_v)
6327                 return;
6328         if (!eth_m)
6329                 eth_m = &nic_mask;
6330         if (inner) {
6331                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6332                                          inner_headers);
6333                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6334         } else {
6335                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6336                                          outer_headers);
6337                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6338         }
6339         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
6340                &eth_m->dst, sizeof(eth_m->dst));
6341         /* The value must be in the range of the mask. */
6342         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
6343         for (i = 0; i < sizeof(eth_m->dst); ++i)
6344                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
6345         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
6346                &eth_m->src, sizeof(eth_m->src));
6347         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
6348         /* The value must be in the range of the mask. */
6349         for (i = 0; i < sizeof(eth_m->dst); ++i)
6350                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
6351         /*
6352          * HW supports match on one Ethertype, the Ethertype following the last
6353          * VLAN tag of the packet (see PRM).
6354          * Set match on ethertype only if ETH header is not followed by VLAN.
6355          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6356          * ethertype, and use ip_version field instead.
6357          * eCPRI over Ether layer will use type value 0xAEFE.
6358          */
6359         if (eth_m->type == 0xFFFF) {
6360                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
6361                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6362                 switch (eth_v->type) {
6363                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6364                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6365                         return;
6366                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
6367                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6368                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6369                         return;
6370                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6371                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6372                         return;
6373                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6374                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6375                         return;
6376                 default:
6377                         break;
6378                 }
6379         }
6380         if (eth_m->has_vlan) {
6381                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6382                 if (eth_v->has_vlan) {
6383                         /*
6384                          * Here, when also has_more_vlan field in VLAN item is
6385                          * not set, only single-tagged packets will be matched.
6386                          */
6387                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6388                         return;
6389                 }
6390         }
6391         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6392                  rte_be_to_cpu_16(eth_m->type));
6393         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
6394         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
6395 }
6396
6397 /**
6398  * Add VLAN item to matcher and to the value.
6399  *
6400  * @param[in, out] dev_flow
6401  *   Flow descriptor.
6402  * @param[in, out] matcher
6403  *   Flow matcher.
6404  * @param[in, out] key
6405  *   Flow matcher value.
6406  * @param[in] item
6407  *   Flow pattern to translate.
6408  * @param[in] inner
6409  *   Item is inner pattern.
6410  */
6411 static void
6412 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
6413                             void *matcher, void *key,
6414                             const struct rte_flow_item *item,
6415                             int inner, uint32_t group)
6416 {
6417         const struct rte_flow_item_vlan *vlan_m = item->mask;
6418         const struct rte_flow_item_vlan *vlan_v = item->spec;
6419         void *hdrs_m;
6420         void *hdrs_v;
6421         uint16_t tci_m;
6422         uint16_t tci_v;
6423
6424         if (inner) {
6425                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6426                                          inner_headers);
6427                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6428         } else {
6429                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
6430                                          outer_headers);
6431                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6432                 /*
6433                  * This is workaround, masks are not supported,
6434                  * and pre-validated.
6435                  */
6436                 if (vlan_v)
6437                         dev_flow->handle->vf_vlan.tag =
6438                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
6439         }
6440         /*
6441          * When VLAN item exists in flow, mark packet as tagged,
6442          * even if TCI is not specified.
6443          */
6444         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
6445                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
6446                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
6447         }
6448         if (!vlan_v)
6449                 return;
6450         if (!vlan_m)
6451                 vlan_m = &rte_flow_item_vlan_mask;
6452         tci_m = rte_be_to_cpu_16(vlan_m->tci);
6453         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6454         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
6455         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
6456         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
6457         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
6458         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
6459         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
6460         /*
6461          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6462          * ethertype, and use ip_version field instead.
6463          */
6464         if (vlan_m->inner_type == 0xFFFF) {
6465                 switch (vlan_v->inner_type) {
6466                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
6467                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6468                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6469                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6470                         return;
6471                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
6472                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
6473                         return;
6474                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
6475                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
6476                         return;
6477                 default:
6478                         break;
6479                 }
6480         }
6481         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
6482                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
6483                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
6484                 /* Only one vlan_tag bit can be set. */
6485                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
6486                 return;
6487         }
6488         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
6489                  rte_be_to_cpu_16(vlan_m->inner_type));
6490         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
6491                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
6492 }
6493
6494 /**
6495  * Add IPV4 item to matcher and to the value.
6496  *
6497  * @param[in, out] matcher
6498  *   Flow matcher.
6499  * @param[in, out] key
6500  *   Flow matcher value.
6501  * @param[in] item
6502  *   Flow pattern to translate.
6503  * @param[in] inner
6504  *   Item is inner pattern.
6505  * @param[in] group
6506  *   The group to insert the rule.
6507  */
6508 static void
6509 flow_dv_translate_item_ipv4(void *matcher, void *key,
6510                             const struct rte_flow_item *item,
6511                             int inner, uint32_t group)
6512 {
6513         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6514         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6515         const struct rte_flow_item_ipv4 nic_mask = {
6516                 .hdr = {
6517                         .src_addr = RTE_BE32(0xffffffff),
6518                         .dst_addr = RTE_BE32(0xffffffff),
6519                         .type_of_service = 0xff,
6520                         .next_proto_id = 0xff,
6521                         .time_to_live = 0xff,
6522                 },
6523         };
6524         void *headers_m;
6525         void *headers_v;
6526         char *l24_m;
6527         char *l24_v;
6528         uint8_t tos;
6529
6530         if (inner) {
6531                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6532                                          inner_headers);
6533                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6534         } else {
6535                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6536                                          outer_headers);
6537                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6538         }
6539         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6540         if (!ipv4_v)
6541                 return;
6542         if (!ipv4_m)
6543                 ipv4_m = &nic_mask;
6544         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6545                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6546         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6547                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6548         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6549         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6550         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6551                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6552         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6553                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
6554         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6555         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6556         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6557         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6558                  ipv4_m->hdr.type_of_service);
6559         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6560         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6561                  ipv4_m->hdr.type_of_service >> 2);
6562         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6563         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6564                  ipv4_m->hdr.next_proto_id);
6565         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6566                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6567         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6568                  ipv4_m->hdr.time_to_live);
6569         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6570                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6571         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6572                  !!(ipv4_m->hdr.fragment_offset));
6573         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6574                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
6575 }
6576
6577 /**
6578  * Add IPV6 item to matcher and to the value.
6579  *
6580  * @param[in, out] matcher
6581  *   Flow matcher.
6582  * @param[in, out] key
6583  *   Flow matcher value.
6584  * @param[in] item
6585  *   Flow pattern to translate.
6586  * @param[in] inner
6587  *   Item is inner pattern.
6588  * @param[in] group
6589  *   The group to insert the rule.
6590  */
6591 static void
6592 flow_dv_translate_item_ipv6(void *matcher, void *key,
6593                             const struct rte_flow_item *item,
6594                             int inner, uint32_t group)
6595 {
6596         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6597         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6598         const struct rte_flow_item_ipv6 nic_mask = {
6599                 .hdr = {
6600                         .src_addr =
6601                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6602                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6603                         .dst_addr =
6604                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6605                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6606                         .vtc_flow = RTE_BE32(0xffffffff),
6607                         .proto = 0xff,
6608                         .hop_limits = 0xff,
6609                 },
6610         };
6611         void *headers_m;
6612         void *headers_v;
6613         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6614         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6615         char *l24_m;
6616         char *l24_v;
6617         uint32_t vtc_m;
6618         uint32_t vtc_v;
6619         int i;
6620         int size;
6621
6622         if (inner) {
6623                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6624                                          inner_headers);
6625                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6626         } else {
6627                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6628                                          outer_headers);
6629                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6630         }
6631         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6632         if (!ipv6_v)
6633                 return;
6634         if (!ipv6_m)
6635                 ipv6_m = &nic_mask;
6636         size = sizeof(ipv6_m->hdr.dst_addr);
6637         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6638                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6639         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6640                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6641         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6642         for (i = 0; i < size; ++i)
6643                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6644         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6645                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6646         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6647                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6648         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6649         for (i = 0; i < size; ++i)
6650                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6651         /* TOS. */
6652         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6653         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6654         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6655         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6656         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6657         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6658         /* Label. */
6659         if (inner) {
6660                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6661                          vtc_m);
6662                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6663                          vtc_v);
6664         } else {
6665                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6666                          vtc_m);
6667                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6668                          vtc_v);
6669         }
6670         /* Protocol. */
6671         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6672                  ipv6_m->hdr.proto);
6673         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6674                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6675         /* Hop limit. */
6676         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6677                  ipv6_m->hdr.hop_limits);
6678         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6679                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6680         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
6681                  !!(ipv6_m->has_frag_ext));
6682         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
6683                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
6684 }
6685
6686 /**
6687  * Add IPV6 fragment extension item to matcher and to the value.
6688  *
6689  * @param[in, out] matcher
6690  *   Flow matcher.
6691  * @param[in, out] key
6692  *   Flow matcher value.
6693  * @param[in] item
6694  *   Flow pattern to translate.
6695  * @param[in] inner
6696  *   Item is inner pattern.
6697  */
6698 static void
6699 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
6700                                      const struct rte_flow_item *item,
6701                                      int inner)
6702 {
6703         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
6704         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
6705         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
6706                 .hdr = {
6707                         .next_header = 0xff,
6708                         .frag_data = RTE_BE16(0xffff),
6709                 },
6710         };
6711         void *headers_m;
6712         void *headers_v;
6713
6714         if (inner) {
6715                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6716                                          inner_headers);
6717                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6718         } else {
6719                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6720                                          outer_headers);
6721                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6722         }
6723         /* IPv6 fragment extension item exists, so packet is IP fragment. */
6724         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6725         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
6726         if (!ipv6_frag_ext_v)
6727                 return;
6728         if (!ipv6_frag_ext_m)
6729                 ipv6_frag_ext_m = &nic_mask;
6730         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6731                  ipv6_frag_ext_m->hdr.next_header);
6732         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6733                  ipv6_frag_ext_v->hdr.next_header &
6734                  ipv6_frag_ext_m->hdr.next_header);
6735 }
6736
6737 /**
6738  * Add TCP item to matcher and to the value.
6739  *
6740  * @param[in, out] matcher
6741  *   Flow matcher.
6742  * @param[in, out] key
6743  *   Flow matcher value.
6744  * @param[in] item
6745  *   Flow pattern to translate.
6746  * @param[in] inner
6747  *   Item is inner pattern.
6748  */
6749 static void
6750 flow_dv_translate_item_tcp(void *matcher, void *key,
6751                            const struct rte_flow_item *item,
6752                            int inner)
6753 {
6754         const struct rte_flow_item_tcp *tcp_m = item->mask;
6755         const struct rte_flow_item_tcp *tcp_v = item->spec;
6756         void *headers_m;
6757         void *headers_v;
6758
6759         if (inner) {
6760                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6761                                          inner_headers);
6762                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6763         } else {
6764                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6765                                          outer_headers);
6766                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6767         }
6768         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6769         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6770         if (!tcp_v)
6771                 return;
6772         if (!tcp_m)
6773                 tcp_m = &rte_flow_item_tcp_mask;
6774         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6775                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6776         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6777                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6778         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6779                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6780         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6781                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6782         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6783                  tcp_m->hdr.tcp_flags);
6784         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6785                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6786 }
6787
6788 /**
6789  * Add UDP item to matcher and to the value.
6790  *
6791  * @param[in, out] matcher
6792  *   Flow matcher.
6793  * @param[in, out] key
6794  *   Flow matcher value.
6795  * @param[in] item
6796  *   Flow pattern to translate.
6797  * @param[in] inner
6798  *   Item is inner pattern.
6799  */
6800 static void
6801 flow_dv_translate_item_udp(void *matcher, void *key,
6802                            const struct rte_flow_item *item,
6803                            int inner)
6804 {
6805         const struct rte_flow_item_udp *udp_m = item->mask;
6806         const struct rte_flow_item_udp *udp_v = item->spec;
6807         void *headers_m;
6808         void *headers_v;
6809
6810         if (inner) {
6811                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6812                                          inner_headers);
6813                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6814         } else {
6815                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6816                                          outer_headers);
6817                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6818         }
6819         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6820         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6821         if (!udp_v)
6822                 return;
6823         if (!udp_m)
6824                 udp_m = &rte_flow_item_udp_mask;
6825         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6826                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6827         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6828                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6829         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6830                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6831         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6832                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6833 }
6834
6835 /**
6836  * Add GRE optional Key item to matcher and to the value.
6837  *
6838  * @param[in, out] matcher
6839  *   Flow matcher.
6840  * @param[in, out] key
6841  *   Flow matcher value.
6842  * @param[in] item
6843  *   Flow pattern to translate.
6844  * @param[in] inner
6845  *   Item is inner pattern.
6846  */
6847 static void
6848 flow_dv_translate_item_gre_key(void *matcher, void *key,
6849                                    const struct rte_flow_item *item)
6850 {
6851         const rte_be32_t *key_m = item->mask;
6852         const rte_be32_t *key_v = item->spec;
6853         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6854         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6855         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6856
6857         /* GRE K bit must be on and should already be validated */
6858         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6859         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6860         if (!key_v)
6861                 return;
6862         if (!key_m)
6863                 key_m = &gre_key_default_mask;
6864         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6865                  rte_be_to_cpu_32(*key_m) >> 8);
6866         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6867                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6868         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6869                  rte_be_to_cpu_32(*key_m) & 0xFF);
6870         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6871                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6872 }
6873
6874 /**
6875  * Add GRE item to matcher and to the value.
6876  *
6877  * @param[in, out] matcher
6878  *   Flow matcher.
6879  * @param[in, out] key
6880  *   Flow matcher value.
6881  * @param[in] item
6882  *   Flow pattern to translate.
6883  * @param[in] inner
6884  *   Item is inner pattern.
6885  */
6886 static void
6887 flow_dv_translate_item_gre(void *matcher, void *key,
6888                            const struct rte_flow_item *item,
6889                            int inner)
6890 {
6891         const struct rte_flow_item_gre *gre_m = item->mask;
6892         const struct rte_flow_item_gre *gre_v = item->spec;
6893         void *headers_m;
6894         void *headers_v;
6895         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6896         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6897         struct {
6898                 union {
6899                         __extension__
6900                         struct {
6901                                 uint16_t version:3;
6902                                 uint16_t rsvd0:9;
6903                                 uint16_t s_present:1;
6904                                 uint16_t k_present:1;
6905                                 uint16_t rsvd_bit1:1;
6906                                 uint16_t c_present:1;
6907                         };
6908                         uint16_t value;
6909                 };
6910         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6911
6912         if (inner) {
6913                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6914                                          inner_headers);
6915                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6916         } else {
6917                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6918                                          outer_headers);
6919                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6920         }
6921         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6922         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6923         if (!gre_v)
6924                 return;
6925         if (!gre_m)
6926                 gre_m = &rte_flow_item_gre_mask;
6927         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6928                  rte_be_to_cpu_16(gre_m->protocol));
6929         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6930                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6931         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6932         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6933         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6934                  gre_crks_rsvd0_ver_m.c_present);
6935         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6936                  gre_crks_rsvd0_ver_v.c_present &
6937                  gre_crks_rsvd0_ver_m.c_present);
6938         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6939                  gre_crks_rsvd0_ver_m.k_present);
6940         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6941                  gre_crks_rsvd0_ver_v.k_present &
6942                  gre_crks_rsvd0_ver_m.k_present);
6943         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6944                  gre_crks_rsvd0_ver_m.s_present);
6945         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6946                  gre_crks_rsvd0_ver_v.s_present &
6947                  gre_crks_rsvd0_ver_m.s_present);
6948 }
6949
6950 /**
6951  * Add NVGRE item to matcher and to the value.
6952  *
6953  * @param[in, out] matcher
6954  *   Flow matcher.
6955  * @param[in, out] key
6956  *   Flow matcher value.
6957  * @param[in] item
6958  *   Flow pattern to translate.
6959  * @param[in] inner
6960  *   Item is inner pattern.
6961  */
6962 static void
6963 flow_dv_translate_item_nvgre(void *matcher, void *key,
6964                              const struct rte_flow_item *item,
6965                              int inner)
6966 {
6967         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6968         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6969         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6970         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6971         const char *tni_flow_id_m;
6972         const char *tni_flow_id_v;
6973         char *gre_key_m;
6974         char *gre_key_v;
6975         int size;
6976         int i;
6977
6978         /* For NVGRE, GRE header fields must be set with defined values. */
6979         const struct rte_flow_item_gre gre_spec = {
6980                 .c_rsvd0_ver = RTE_BE16(0x2000),
6981                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6982         };
6983         const struct rte_flow_item_gre gre_mask = {
6984                 .c_rsvd0_ver = RTE_BE16(0xB000),
6985                 .protocol = RTE_BE16(UINT16_MAX),
6986         };
6987         const struct rte_flow_item gre_item = {
6988                 .spec = &gre_spec,
6989                 .mask = &gre_mask,
6990                 .last = NULL,
6991         };
6992         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6993         if (!nvgre_v)
6994                 return;
6995         if (!nvgre_m)
6996                 nvgre_m = &rte_flow_item_nvgre_mask;
6997         tni_flow_id_m = (const char *)nvgre_m->tni;
6998         tni_flow_id_v = (const char *)nvgre_v->tni;
6999         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7000         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7001         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7002         memcpy(gre_key_m, tni_flow_id_m, size);
7003         for (i = 0; i < size; ++i)
7004                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7005 }
7006
7007 /**
7008  * Add VXLAN item to matcher and to the value.
7009  *
7010  * @param[in, out] matcher
7011  *   Flow matcher.
7012  * @param[in, out] key
7013  *   Flow matcher value.
7014  * @param[in] item
7015  *   Flow pattern to translate.
7016  * @param[in] inner
7017  *   Item is inner pattern.
7018  */
7019 static void
7020 flow_dv_translate_item_vxlan(void *matcher, void *key,
7021                              const struct rte_flow_item *item,
7022                              int inner)
7023 {
7024         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7025         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7026         void *headers_m;
7027         void *headers_v;
7028         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7029         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7030         char *vni_m;
7031         char *vni_v;
7032         uint16_t dport;
7033         int size;
7034         int i;
7035
7036         if (inner) {
7037                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7038                                          inner_headers);
7039                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7040         } else {
7041                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7042                                          outer_headers);
7043                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7044         }
7045         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7046                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7047         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7048                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7049                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7050         }
7051         if (!vxlan_v)
7052                 return;
7053         if (!vxlan_m)
7054                 vxlan_m = &rte_flow_item_vxlan_mask;
7055         size = sizeof(vxlan_m->vni);
7056         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
7057         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
7058         memcpy(vni_m, vxlan_m->vni, size);
7059         for (i = 0; i < size; ++i)
7060                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7061 }
7062
7063 /**
7064  * Add VXLAN-GPE item to matcher and to the value.
7065  *
7066  * @param[in, out] matcher
7067  *   Flow matcher.
7068  * @param[in, out] key
7069  *   Flow matcher value.
7070  * @param[in] item
7071  *   Flow pattern to translate.
7072  * @param[in] inner
7073  *   Item is inner pattern.
7074  */
7075
7076 static void
7077 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
7078                                  const struct rte_flow_item *item, int inner)
7079 {
7080         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
7081         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
7082         void *headers_m;
7083         void *headers_v;
7084         void *misc_m =
7085                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
7086         void *misc_v =
7087                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7088         char *vni_m;
7089         char *vni_v;
7090         uint16_t dport;
7091         int size;
7092         int i;
7093         uint8_t flags_m = 0xff;
7094         uint8_t flags_v = 0xc;
7095
7096         if (inner) {
7097                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7098                                          inner_headers);
7099                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7100         } else {
7101                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7102                                          outer_headers);
7103                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7104         }
7105         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7106                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7107         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7108                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7109                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7110         }
7111         if (!vxlan_v)
7112                 return;
7113         if (!vxlan_m)
7114                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
7115         size = sizeof(vxlan_m->vni);
7116         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
7117         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
7118         memcpy(vni_m, vxlan_m->vni, size);
7119         for (i = 0; i < size; ++i)
7120                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
7121         if (vxlan_m->flags) {
7122                 flags_m = vxlan_m->flags;
7123                 flags_v = vxlan_v->flags;
7124         }
7125         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
7126         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
7127         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
7128                  vxlan_m->protocol);
7129         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
7130                  vxlan_v->protocol);
7131 }
7132
7133 /**
7134  * Add Geneve item to matcher and to the value.
7135  *
7136  * @param[in, out] matcher
7137  *   Flow matcher.
7138  * @param[in, out] key
7139  *   Flow matcher value.
7140  * @param[in] item
7141  *   Flow pattern to translate.
7142  * @param[in] inner
7143  *   Item is inner pattern.
7144  */
7145
7146 static void
7147 flow_dv_translate_item_geneve(void *matcher, void *key,
7148                               const struct rte_flow_item *item, int inner)
7149 {
7150         const struct rte_flow_item_geneve *geneve_m = item->mask;
7151         const struct rte_flow_item_geneve *geneve_v = item->spec;
7152         void *headers_m;
7153         void *headers_v;
7154         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7155         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7156         uint16_t dport;
7157         uint16_t gbhdr_m;
7158         uint16_t gbhdr_v;
7159         char *vni_m;
7160         char *vni_v;
7161         size_t size, i;
7162
7163         if (inner) {
7164                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7165                                          inner_headers);
7166                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7167         } else {
7168                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7169                                          outer_headers);
7170                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7171         }
7172         dport = MLX5_UDP_PORT_GENEVE;
7173         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7174                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7175                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7176         }
7177         if (!geneve_v)
7178                 return;
7179         if (!geneve_m)
7180                 geneve_m = &rte_flow_item_geneve_mask;
7181         size = sizeof(geneve_m->vni);
7182         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
7183         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
7184         memcpy(vni_m, geneve_m->vni, size);
7185         for (i = 0; i < size; ++i)
7186                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
7187         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
7188                  rte_be_to_cpu_16(geneve_m->protocol));
7189         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
7190                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
7191         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
7192         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
7193         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
7194                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7195         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
7196                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
7197         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
7198                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7199         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
7200                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
7201                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
7202 }
7203
7204 /**
7205  * Add MPLS item to matcher and to the value.
7206  *
7207  * @param[in, out] matcher
7208  *   Flow matcher.
7209  * @param[in, out] key
7210  *   Flow matcher value.
7211  * @param[in] item
7212  *   Flow pattern to translate.
7213  * @param[in] prev_layer
7214  *   The protocol layer indicated in previous item.
7215  * @param[in] inner
7216  *   Item is inner pattern.
7217  */
7218 static void
7219 flow_dv_translate_item_mpls(void *matcher, void *key,
7220                             const struct rte_flow_item *item,
7221                             uint64_t prev_layer,
7222                             int inner)
7223 {
7224         const uint32_t *in_mpls_m = item->mask;
7225         const uint32_t *in_mpls_v = item->spec;
7226         uint32_t *out_mpls_m = 0;
7227         uint32_t *out_mpls_v = 0;
7228         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7229         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7230         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
7231                                      misc_parameters_2);
7232         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7233         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
7234         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7235
7236         switch (prev_layer) {
7237         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7238                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
7239                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7240                          MLX5_UDP_PORT_MPLS);
7241                 break;
7242         case MLX5_FLOW_LAYER_GRE:
7243                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
7244                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7245                          RTE_ETHER_TYPE_MPLS);
7246                 break;
7247         default:
7248                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7249                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7250                          IPPROTO_MPLS);
7251                 break;
7252         }
7253         if (!in_mpls_v)
7254                 return;
7255         if (!in_mpls_m)
7256                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
7257         switch (prev_layer) {
7258         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
7259                 out_mpls_m =
7260                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7261                                                  outer_first_mpls_over_udp);
7262                 out_mpls_v =
7263                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7264                                                  outer_first_mpls_over_udp);
7265                 break;
7266         case MLX5_FLOW_LAYER_GRE:
7267                 out_mpls_m =
7268                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
7269                                                  outer_first_mpls_over_gre);
7270                 out_mpls_v =
7271                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
7272                                                  outer_first_mpls_over_gre);
7273                 break;
7274         default:
7275                 /* Inner MPLS not over GRE is not supported. */
7276                 if (!inner) {
7277                         out_mpls_m =
7278                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7279                                                          misc2_m,
7280                                                          outer_first_mpls);
7281                         out_mpls_v =
7282                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
7283                                                          misc2_v,
7284                                                          outer_first_mpls);
7285                 }
7286                 break;
7287         }
7288         if (out_mpls_m && out_mpls_v) {
7289                 *out_mpls_m = *in_mpls_m;
7290                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
7291         }
7292 }
7293
7294 /**
7295  * Add metadata register item to matcher
7296  *
7297  * @param[in, out] matcher
7298  *   Flow matcher.
7299  * @param[in, out] key
7300  *   Flow matcher value.
7301  * @param[in] reg_type
7302  *   Type of device metadata register
7303  * @param[in] value
7304  *   Register value
7305  * @param[in] mask
7306  *   Register mask
7307  */
7308 static void
7309 flow_dv_match_meta_reg(void *matcher, void *key,
7310                        enum modify_reg reg_type,
7311                        uint32_t data, uint32_t mask)
7312 {
7313         void *misc2_m =
7314                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
7315         void *misc2_v =
7316                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
7317         uint32_t temp;
7318
7319         data &= mask;
7320         switch (reg_type) {
7321         case REG_A:
7322                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
7323                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
7324                 break;
7325         case REG_B:
7326                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
7327                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
7328                 break;
7329         case REG_C_0:
7330                 /*
7331                  * The metadata register C0 field might be divided into
7332                  * source vport index and META item value, we should set
7333                  * this field according to specified mask, not as whole one.
7334                  */
7335                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
7336                 temp |= mask;
7337                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
7338                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
7339                 temp &= ~mask;
7340                 temp |= data;
7341                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
7342                 break;
7343         case REG_C_1:
7344                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
7345                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
7346                 break;
7347         case REG_C_2:
7348                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
7349                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
7350                 break;
7351         case REG_C_3:
7352                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
7353                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
7354                 break;
7355         case REG_C_4:
7356                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
7357                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
7358                 break;
7359         case REG_C_5:
7360                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
7361                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
7362                 break;
7363         case REG_C_6:
7364                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
7365                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
7366                 break;
7367         case REG_C_7:
7368                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
7369                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
7370                 break;
7371         default:
7372                 MLX5_ASSERT(false);
7373                 break;
7374         }
7375 }
7376
7377 /**
7378  * Add MARK item to matcher
7379  *
7380  * @param[in] dev
7381  *   The device to configure through.
7382  * @param[in, out] matcher
7383  *   Flow matcher.
7384  * @param[in, out] key
7385  *   Flow matcher value.
7386  * @param[in] item
7387  *   Flow pattern to translate.
7388  */
7389 static void
7390 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
7391                             void *matcher, void *key,
7392                             const struct rte_flow_item *item)
7393 {
7394         struct mlx5_priv *priv = dev->data->dev_private;
7395         const struct rte_flow_item_mark *mark;
7396         uint32_t value;
7397         uint32_t mask;
7398
7399         mark = item->mask ? (const void *)item->mask :
7400                             &rte_flow_item_mark_mask;
7401         mask = mark->id & priv->sh->dv_mark_mask;
7402         mark = (const void *)item->spec;
7403         MLX5_ASSERT(mark);
7404         value = mark->id & priv->sh->dv_mark_mask & mask;
7405         if (mask) {
7406                 enum modify_reg reg;
7407
7408                 /* Get the metadata register index for the mark. */
7409                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
7410                 MLX5_ASSERT(reg > 0);
7411                 if (reg == REG_C_0) {
7412                         struct mlx5_priv *priv = dev->data->dev_private;
7413                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7414                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7415
7416                         mask &= msk_c0;
7417                         mask <<= shl_c0;
7418                         value <<= shl_c0;
7419                 }
7420                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7421         }
7422 }
7423
7424 /**
7425  * Add META item to matcher
7426  *
7427  * @param[in] dev
7428  *   The devich to configure through.
7429  * @param[in, out] matcher
7430  *   Flow matcher.
7431  * @param[in, out] key
7432  *   Flow matcher value.
7433  * @param[in] attr
7434  *   Attributes of flow that includes this item.
7435  * @param[in] item
7436  *   Flow pattern to translate.
7437  */
7438 static void
7439 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
7440                             void *matcher, void *key,
7441                             const struct rte_flow_attr *attr,
7442                             const struct rte_flow_item *item)
7443 {
7444         const struct rte_flow_item_meta *meta_m;
7445         const struct rte_flow_item_meta *meta_v;
7446
7447         meta_m = (const void *)item->mask;
7448         if (!meta_m)
7449                 meta_m = &rte_flow_item_meta_mask;
7450         meta_v = (const void *)item->spec;
7451         if (meta_v) {
7452                 int reg;
7453                 uint32_t value = meta_v->data;
7454                 uint32_t mask = meta_m->data;
7455
7456                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
7457                 if (reg < 0)
7458                         return;
7459                 /*
7460                  * In datapath code there is no endianness
7461                  * coversions for perfromance reasons, all
7462                  * pattern conversions are done in rte_flow.
7463                  */
7464                 value = rte_cpu_to_be_32(value);
7465                 mask = rte_cpu_to_be_32(mask);
7466                 if (reg == REG_C_0) {
7467                         struct mlx5_priv *priv = dev->data->dev_private;
7468                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7469                         uint32_t shl_c0 = rte_bsf32(msk_c0);
7470 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
7471                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
7472
7473                         value >>= shr_c0;
7474                         mask >>= shr_c0;
7475 #endif
7476                         value <<= shl_c0;
7477                         mask <<= shl_c0;
7478                         MLX5_ASSERT(msk_c0);
7479                         MLX5_ASSERT(!(~msk_c0 & mask));
7480                 }
7481                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
7482         }
7483 }
7484
7485 /**
7486  * Add vport metadata Reg C0 item to matcher
7487  *
7488  * @param[in, out] matcher
7489  *   Flow matcher.
7490  * @param[in, out] key
7491  *   Flow matcher value.
7492  * @param[in] reg
7493  *   Flow pattern to translate.
7494  */
7495 static void
7496 flow_dv_translate_item_meta_vport(void *matcher, void *key,
7497                                   uint32_t value, uint32_t mask)
7498 {
7499         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
7500 }
7501
7502 /**
7503  * Add tag item to matcher
7504  *
7505  * @param[in] dev
7506  *   The devich to configure through.
7507  * @param[in, out] matcher
7508  *   Flow matcher.
7509  * @param[in, out] key
7510  *   Flow matcher value.
7511  * @param[in] item
7512  *   Flow pattern to translate.
7513  */
7514 static void
7515 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7516                                 void *matcher, void *key,
7517                                 const struct rte_flow_item *item)
7518 {
7519         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7520         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7521         uint32_t mask, value;
7522
7523         MLX5_ASSERT(tag_v);
7524         value = tag_v->data;
7525         mask = tag_m ? tag_m->data : UINT32_MAX;
7526         if (tag_v->id == REG_C_0) {
7527                 struct mlx5_priv *priv = dev->data->dev_private;
7528                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7529                 uint32_t shl_c0 = rte_bsf32(msk_c0);
7530
7531                 mask &= msk_c0;
7532                 mask <<= shl_c0;
7533                 value <<= shl_c0;
7534         }
7535         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7536 }
7537
7538 /**
7539  * Add TAG item to matcher
7540  *
7541  * @param[in] dev
7542  *   The devich to configure through.
7543  * @param[in, out] matcher
7544  *   Flow matcher.
7545  * @param[in, out] key
7546  *   Flow matcher value.
7547  * @param[in] item
7548  *   Flow pattern to translate.
7549  */
7550 static void
7551 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7552                            void *matcher, void *key,
7553                            const struct rte_flow_item *item)
7554 {
7555         const struct rte_flow_item_tag *tag_v = item->spec;
7556         const struct rte_flow_item_tag *tag_m = item->mask;
7557         enum modify_reg reg;
7558
7559         MLX5_ASSERT(tag_v);
7560         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7561         /* Get the metadata register index for the tag. */
7562         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7563         MLX5_ASSERT(reg > 0);
7564         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7565 }
7566
7567 /**
7568  * Add source vport match to the specified matcher.
7569  *
7570  * @param[in, out] matcher
7571  *   Flow matcher.
7572  * @param[in, out] key
7573  *   Flow matcher value.
7574  * @param[in] port
7575  *   Source vport value to match
7576  * @param[in] mask
7577  *   Mask
7578  */
7579 static void
7580 flow_dv_translate_item_source_vport(void *matcher, void *key,
7581                                     int16_t port, uint16_t mask)
7582 {
7583         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7584         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7585
7586         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7587         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7588 }
7589
7590 /**
7591  * Translate port-id item to eswitch match on  port-id.
7592  *
7593  * @param[in] dev
7594  *   The devich to configure through.
7595  * @param[in, out] matcher
7596  *   Flow matcher.
7597  * @param[in, out] key
7598  *   Flow matcher value.
7599  * @param[in] item
7600  *   Flow pattern to translate.
7601  *
7602  * @return
7603  *   0 on success, a negative errno value otherwise.
7604  */
7605 static int
7606 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7607                                void *key, const struct rte_flow_item *item)
7608 {
7609         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7610         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7611         struct mlx5_priv *priv;
7612         uint16_t mask, id;
7613
7614         mask = pid_m ? pid_m->id : 0xffff;
7615         id = pid_v ? pid_v->id : dev->data->port_id;
7616         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7617         if (!priv)
7618                 return -rte_errno;
7619         /* Translate to vport field or to metadata, depending on mode. */
7620         if (priv->vport_meta_mask)
7621                 flow_dv_translate_item_meta_vport(matcher, key,
7622                                                   priv->vport_meta_tag,
7623                                                   priv->vport_meta_mask);
7624         else
7625                 flow_dv_translate_item_source_vport(matcher, key,
7626                                                     priv->vport_id, mask);
7627         return 0;
7628 }
7629
7630 /**
7631  * Add ICMP6 item to matcher and to the value.
7632  *
7633  * @param[in, out] matcher
7634  *   Flow matcher.
7635  * @param[in, out] key
7636  *   Flow matcher value.
7637  * @param[in] item
7638  *   Flow pattern to translate.
7639  * @param[in] inner
7640  *   Item is inner pattern.
7641  */
7642 static void
7643 flow_dv_translate_item_icmp6(void *matcher, void *key,
7644                               const struct rte_flow_item *item,
7645                               int inner)
7646 {
7647         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7648         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7649         void *headers_m;
7650         void *headers_v;
7651         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7652                                      misc_parameters_3);
7653         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7654         if (inner) {
7655                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7656                                          inner_headers);
7657                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7658         } else {
7659                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7660                                          outer_headers);
7661                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7662         }
7663         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7664         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7665         if (!icmp6_v)
7666                 return;
7667         if (!icmp6_m)
7668                 icmp6_m = &rte_flow_item_icmp6_mask;
7669         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7670         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7671                  icmp6_v->type & icmp6_m->type);
7672         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7673         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7674                  icmp6_v->code & icmp6_m->code);
7675 }
7676
7677 /**
7678  * Add ICMP item to matcher and to the value.
7679  *
7680  * @param[in, out] matcher
7681  *   Flow matcher.
7682  * @param[in, out] key
7683  *   Flow matcher value.
7684  * @param[in] item
7685  *   Flow pattern to translate.
7686  * @param[in] inner
7687  *   Item is inner pattern.
7688  */
7689 static void
7690 flow_dv_translate_item_icmp(void *matcher, void *key,
7691                             const struct rte_flow_item *item,
7692                             int inner)
7693 {
7694         const struct rte_flow_item_icmp *icmp_m = item->mask;
7695         const struct rte_flow_item_icmp *icmp_v = item->spec;
7696         uint32_t icmp_header_data_m = 0;
7697         uint32_t icmp_header_data_v = 0;
7698         void *headers_m;
7699         void *headers_v;
7700         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7701                                      misc_parameters_3);
7702         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7703         if (inner) {
7704                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7705                                          inner_headers);
7706                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7707         } else {
7708                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7709                                          outer_headers);
7710                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7711         }
7712         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7713         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7714         if (!icmp_v)
7715                 return;
7716         if (!icmp_m)
7717                 icmp_m = &rte_flow_item_icmp_mask;
7718         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7719                  icmp_m->hdr.icmp_type);
7720         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7721                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7722         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7723                  icmp_m->hdr.icmp_code);
7724         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7725                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7726         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
7727         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
7728         if (icmp_header_data_m) {
7729                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
7730                 icmp_header_data_v |=
7731                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
7732                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
7733                          icmp_header_data_m);
7734                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
7735                          icmp_header_data_v & icmp_header_data_m);
7736         }
7737 }
7738
7739 /**
7740  * Add GTP item to matcher and to the value.
7741  *
7742  * @param[in, out] matcher
7743  *   Flow matcher.
7744  * @param[in, out] key
7745  *   Flow matcher value.
7746  * @param[in] item
7747  *   Flow pattern to translate.
7748  * @param[in] inner
7749  *   Item is inner pattern.
7750  */
7751 static void
7752 flow_dv_translate_item_gtp(void *matcher, void *key,
7753                            const struct rte_flow_item *item, int inner)
7754 {
7755         const struct rte_flow_item_gtp *gtp_m = item->mask;
7756         const struct rte_flow_item_gtp *gtp_v = item->spec;
7757         void *headers_m;
7758         void *headers_v;
7759         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7760                                      misc_parameters_3);
7761         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7762         uint16_t dport = RTE_GTPU_UDP_PORT;
7763
7764         if (inner) {
7765                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7766                                          inner_headers);
7767                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7768         } else {
7769                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7770                                          outer_headers);
7771                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7772         }
7773         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7774                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7775                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7776         }
7777         if (!gtp_v)
7778                 return;
7779         if (!gtp_m)
7780                 gtp_m = &rte_flow_item_gtp_mask;
7781         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7782                  gtp_m->v_pt_rsv_flags);
7783         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7784                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7785         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7786         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7787                  gtp_v->msg_type & gtp_m->msg_type);
7788         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7789                  rte_be_to_cpu_32(gtp_m->teid));
7790         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7791                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7792 }
7793
7794 /**
7795  * Add eCPRI item to matcher and to the value.
7796  *
7797  * @param[in] dev
7798  *   The devich to configure through.
7799  * @param[in, out] matcher
7800  *   Flow matcher.
7801  * @param[in, out] key
7802  *   Flow matcher value.
7803  * @param[in] item
7804  *   Flow pattern to translate.
7805  * @param[in] samples
7806  *   Sample IDs to be used in the matching.
7807  */
7808 static void
7809 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7810                              void *key, const struct rte_flow_item *item)
7811 {
7812         struct mlx5_priv *priv = dev->data->dev_private;
7813         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7814         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7815         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7816                                      misc_parameters_4);
7817         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7818         uint32_t *samples;
7819         void *dw_m;
7820         void *dw_v;
7821
7822         if (!ecpri_v)
7823                 return;
7824         if (!ecpri_m)
7825                 ecpri_m = &rte_flow_item_ecpri_mask;
7826         /*
7827          * Maximal four DW samples are supported in a single matching now.
7828          * Two are used now for a eCPRI matching:
7829          * 1. Type: one byte, mask should be 0x00ff0000 in network order
7830          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7831          *    if any.
7832          */
7833         if (!ecpri_m->hdr.common.u32)
7834                 return;
7835         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7836         /* Need to take the whole DW as the mask to fill the entry. */
7837         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7838                             prog_sample_field_value_0);
7839         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7840                             prog_sample_field_value_0);
7841         /* Already big endian (network order) in the header. */
7842         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7843         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7844         /* Sample#0, used for matching type, offset 0. */
7845         MLX5_SET(fte_match_set_misc4, misc4_m,
7846                  prog_sample_field_id_0, samples[0]);
7847         /* It makes no sense to set the sample ID in the mask field. */
7848         MLX5_SET(fte_match_set_misc4, misc4_v,
7849                  prog_sample_field_id_0, samples[0]);
7850         /*
7851          * Checking if message body part needs to be matched.
7852          * Some wildcard rules only matching type field should be supported.
7853          */
7854         if (ecpri_m->hdr.dummy[0]) {
7855                 switch (ecpri_v->hdr.common.type) {
7856                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7857                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7858                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7859                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7860                                             prog_sample_field_value_1);
7861                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7862                                             prog_sample_field_value_1);
7863                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7864                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7865                         /* Sample#1, to match message body, offset 4. */
7866                         MLX5_SET(fte_match_set_misc4, misc4_m,
7867                                  prog_sample_field_id_1, samples[1]);
7868                         MLX5_SET(fte_match_set_misc4, misc4_v,
7869                                  prog_sample_field_id_1, samples[1]);
7870                         break;
7871                 default:
7872                         /* Others, do not match any sample ID. */
7873                         break;
7874                 }
7875         }
7876 }
7877
7878 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7879
7880 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7881         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7882                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7883
7884 /**
7885  * Calculate flow matcher enable bitmap.
7886  *
7887  * @param match_criteria
7888  *   Pointer to flow matcher criteria.
7889  *
7890  * @return
7891  *   Bitmap of enabled fields.
7892  */
7893 static uint8_t
7894 flow_dv_matcher_enable(uint32_t *match_criteria)
7895 {
7896         uint8_t match_criteria_enable;
7897
7898         match_criteria_enable =
7899                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7900                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7901         match_criteria_enable |=
7902                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7903                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7904         match_criteria_enable |=
7905                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7906                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7907         match_criteria_enable |=
7908                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7909                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7910         match_criteria_enable |=
7911                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7912                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7913         match_criteria_enable |=
7914                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7915                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7916         return match_criteria_enable;
7917 }
7918
7919 struct mlx5_hlist_entry *
7920 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
7921 {
7922         struct mlx5_dev_ctx_shared *sh = list->ctx;
7923         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
7924         struct rte_eth_dev *dev = ctx->dev;
7925         struct mlx5_flow_tbl_data_entry *tbl_data;
7926         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
7927         struct rte_flow_error *error = ctx->error;
7928         union mlx5_flow_tbl_key key = { .v64 = key64 };
7929         struct mlx5_flow_tbl_resource *tbl;
7930         void *domain;
7931         uint32_t idx = 0;
7932         int ret;
7933
7934         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7935         if (!tbl_data) {
7936                 rte_flow_error_set(error, ENOMEM,
7937                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7938                                    NULL,
7939                                    "cannot allocate flow table data entry");
7940                 return NULL;
7941         }
7942         tbl_data->idx = idx;
7943         tbl_data->tunnel = tt_prm->tunnel;
7944         tbl_data->group_id = tt_prm->group_id;
7945         tbl_data->external = tt_prm->external;
7946         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
7947         tbl = &tbl_data->tbl;
7948         if (key.dummy)
7949                 return &tbl_data->entry;
7950         if (key.domain)
7951                 domain = sh->fdb_domain;
7952         else if (key.direction)
7953                 domain = sh->tx_domain;
7954         else
7955                 domain = sh->rx_domain;
7956         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
7957         if (ret) {
7958                 rte_flow_error_set(error, ENOMEM,
7959                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7960                                    NULL, "cannot create flow table object");
7961                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7962                 return NULL;
7963         }
7964         if (key.table_id) {
7965                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
7966                                         (tbl->obj, &tbl_data->jump.action);
7967                 if (ret) {
7968                         rte_flow_error_set(error, ENOMEM,
7969                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7970                                            NULL,
7971                                            "cannot create flow jump action");
7972                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7973                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7974                         return NULL;
7975                 }
7976         }
7977         return &tbl_data->entry;
7978 }
7979
7980 /**
7981  * Get a flow table.
7982  *
7983  * @param[in, out] dev
7984  *   Pointer to rte_eth_dev structure.
7985  * @param[in] table_id
7986  *   Table id to use.
7987  * @param[in] egress
7988  *   Direction of the table.
7989  * @param[in] transfer
7990  *   E-Switch or NIC flow.
7991  * @param[in] dummy
7992  *   Dummy entry for dv API.
7993  * @param[out] error
7994  *   pointer to error structure.
7995  *
7996  * @return
7997  *   Returns tables resource based on the index, NULL in case of failed.
7998  */
7999 struct mlx5_flow_tbl_resource *
8000 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
8001                          uint32_t table_id, uint8_t egress,
8002                          uint8_t transfer,
8003                          bool external,
8004                          const struct mlx5_flow_tunnel *tunnel,
8005                          uint32_t group_id, uint8_t dummy,
8006                          struct rte_flow_error *error)
8007 {
8008         struct mlx5_priv *priv = dev->data->dev_private;
8009         union mlx5_flow_tbl_key table_key = {
8010                 {
8011                         .table_id = table_id,
8012                         .dummy = dummy,
8013                         .domain = !!transfer,
8014                         .direction = !!egress,
8015                 }
8016         };
8017         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
8018                 .tunnel = tunnel,
8019                 .group_id = group_id,
8020                 .external = external,
8021         };
8022         struct mlx5_flow_cb_ctx ctx = {
8023                 .dev = dev,
8024                 .error = error,
8025                 .data = &tt_prm,
8026         };
8027         struct mlx5_hlist_entry *entry;
8028         struct mlx5_flow_tbl_data_entry *tbl_data;
8029
8030         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
8031         if (!entry) {
8032                 rte_flow_error_set(error, ENOMEM,
8033                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8034                                    "cannot get table");
8035                 return NULL;
8036         }
8037         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8038         return &tbl_data->tbl;
8039 }
8040
8041 void
8042 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
8043                       struct mlx5_hlist_entry *entry)
8044 {
8045         struct mlx5_dev_ctx_shared *sh = list->ctx;
8046         struct mlx5_flow_tbl_data_entry *tbl_data =
8047                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
8048
8049         MLX5_ASSERT(entry && sh);
8050         if (tbl_data->jump.action)
8051                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
8052         if (tbl_data->tbl.obj)
8053                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
8054         if (tbl_data->tunnel_offload && tbl_data->external) {
8055                 struct mlx5_hlist_entry *he;
8056                 struct mlx5_hlist *tunnel_grp_hash;
8057                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
8058                 union tunnel_tbl_key tunnel_key = {
8059                         .tunnel_id = tbl_data->tunnel ?
8060                                         tbl_data->tunnel->tunnel_id : 0,
8061                         .group = tbl_data->group_id
8062                 };
8063                 union mlx5_flow_tbl_key table_key = {
8064                         .v64 = entry->key
8065                 };
8066                 uint32_t table_id = table_key.table_id;
8067
8068                 tunnel_grp_hash = tbl_data->tunnel ?
8069                                         tbl_data->tunnel->groups :
8070                                         thub->groups;
8071                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
8072                 if (he) {
8073                         struct tunnel_tbl_entry *tte;
8074                         tte = container_of(he, typeof(*tte), hash);
8075                         MLX5_ASSERT(tte->flow_table == table_id);
8076                         mlx5_hlist_remove(tunnel_grp_hash, he);
8077                         mlx5_free(tte);
8078                 }
8079                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID],
8080                                 tunnel_flow_tbl_to_id(table_id));
8081                 DRV_LOG(DEBUG,
8082                         "Table_id %#x tunnel %u group %u released.",
8083                         table_id,
8084                         tbl_data->tunnel ?
8085                         tbl_data->tunnel->tunnel_id : 0,
8086                         tbl_data->group_id);
8087         }
8088         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
8089 }
8090
8091 /**
8092  * Release a flow table.
8093  *
8094  * @param[in] dev
8095  *   Pointer to rte_eth_dev structure.
8096  * @param[in] tbl
8097  *   Table resource to be released.
8098  *
8099  * @return
8100  *   Returns 0 if table was released, else return 1;
8101  */
8102 static int
8103 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
8104                              struct mlx5_flow_tbl_resource *tbl)
8105 {
8106         struct mlx5_priv *priv = dev->data->dev_private;
8107         struct mlx5_dev_ctx_shared *sh = priv->sh;
8108         struct mlx5_flow_tbl_data_entry *tbl_data =
8109                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8110
8111         if (!tbl)
8112                 return 0;
8113         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
8114 }
8115
8116 /**
8117  * Register the flow matcher.
8118  *
8119  * @param[in, out] dev
8120  *   Pointer to rte_eth_dev structure.
8121  * @param[in, out] matcher
8122  *   Pointer to flow matcher.
8123  * @param[in, out] key
8124  *   Pointer to flow table key.
8125  * @parm[in, out] dev_flow
8126  *   Pointer to the dev_flow.
8127  * @param[out] error
8128  *   pointer to error structure.
8129  *
8130  * @return
8131  *   0 on success otherwise -errno and errno is set.
8132  */
8133 static int
8134 flow_dv_matcher_register(struct rte_eth_dev *dev,
8135                          struct mlx5_flow_dv_matcher *matcher,
8136                          union mlx5_flow_tbl_key *key,
8137                          struct mlx5_flow *dev_flow,
8138                          struct rte_flow_error *error)
8139 {
8140         struct mlx5_priv *priv = dev->data->dev_private;
8141         struct mlx5_dev_ctx_shared *sh = priv->sh;
8142         struct mlx5_flow_dv_matcher *cache_matcher;
8143         struct mlx5dv_flow_matcher_attr dv_attr = {
8144                 .type = IBV_FLOW_ATTR_NORMAL,
8145                 .match_mask = (void *)&matcher->mask,
8146         };
8147         struct mlx5_flow_tbl_resource *tbl;
8148         struct mlx5_flow_tbl_data_entry *tbl_data;
8149         int ret;
8150
8151         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
8152                                        key->domain, false, NULL, 0, 0, error);
8153         if (!tbl)
8154                 return -rte_errno;      /* No need to refill the error info */
8155         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
8156         /* Lookup from cache. */
8157         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
8158                 if (matcher->crc == cache_matcher->crc &&
8159                     matcher->priority == cache_matcher->priority &&
8160                     !memcmp((const void *)matcher->mask.buf,
8161                             (const void *)cache_matcher->mask.buf,
8162                             cache_matcher->mask.size)) {
8163                         DRV_LOG(DEBUG,
8164                                 "%s group %u priority %hd use %s "
8165                                 "matcher %p: refcnt %d++",
8166                                 key->domain ? "FDB" : "NIC", key->table_id,
8167                                 cache_matcher->priority,
8168                                 key->direction ? "tx" : "rx",
8169                                 (void *)cache_matcher,
8170                                 __atomic_load_n(&cache_matcher->refcnt,
8171                                                 __ATOMIC_RELAXED));
8172                         __atomic_fetch_add(&cache_matcher->refcnt, 1,
8173                                            __ATOMIC_RELAXED);
8174                         dev_flow->handle->dvh.matcher = cache_matcher;
8175                         /* old matcher should not make the table ref++. */
8176                         flow_dv_tbl_resource_release(dev, tbl);
8177                         return 0;
8178                 }
8179         }
8180         /* Register new matcher. */
8181         cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
8182                                     SOCKET_ID_ANY);
8183         if (!cache_matcher) {
8184                 flow_dv_tbl_resource_release(dev, tbl);
8185                 return rte_flow_error_set(error, ENOMEM,
8186                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8187                                           "cannot allocate matcher memory");
8188         }
8189         *cache_matcher = *matcher;
8190         dv_attr.match_criteria_enable =
8191                 flow_dv_matcher_enable(cache_matcher->mask.buf);
8192         dv_attr.priority = matcher->priority;
8193         if (key->direction)
8194                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
8195         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
8196                                                &cache_matcher->matcher_object);
8197         if (ret) {
8198                 mlx5_free(cache_matcher);
8199 #ifdef HAVE_MLX5DV_DR
8200                 flow_dv_tbl_resource_release(dev, tbl);
8201 #endif
8202                 return rte_flow_error_set(error, ENOMEM,
8203                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8204                                           NULL, "cannot create matcher");
8205         }
8206         /* Save the table information */
8207         cache_matcher->tbl = tbl;
8208         /* only matcher ref++, table ref++ already done above in get API. */
8209         __atomic_store_n(&cache_matcher->refcnt, 1, __ATOMIC_RELAXED);
8210         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
8211         dev_flow->handle->dvh.matcher = cache_matcher;
8212         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
8213                 key->domain ? "FDB" : "NIC", key->table_id,
8214                 cache_matcher->priority,
8215                 key->direction ? "tx" : "rx", (void *)cache_matcher,
8216                 __atomic_load_n(&cache_matcher->refcnt, __ATOMIC_RELAXED));
8217         return 0;
8218 }
8219
8220 struct mlx5_hlist_entry *
8221 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
8222 {
8223         struct mlx5_dev_ctx_shared *sh = list->ctx;
8224         struct rte_flow_error *error = ctx;
8225         struct mlx5_flow_dv_tag_resource *entry;
8226         uint32_t idx = 0;
8227         int ret;
8228
8229         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
8230         if (!entry) {
8231                 rte_flow_error_set(error, ENOMEM,
8232                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8233                                    "cannot allocate resource memory");
8234                 return NULL;
8235         }
8236         entry->idx = idx;
8237         ret = mlx5_flow_os_create_flow_action_tag(key,
8238                                                   &entry->action);
8239         if (ret) {
8240                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
8241                 rte_flow_error_set(error, ENOMEM,
8242                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8243                                    NULL, "cannot create action");
8244                 return NULL;
8245         }
8246         return &entry->entry;
8247 }
8248
8249 /**
8250  * Find existing tag resource or create and register a new one.
8251  *
8252  * @param dev[in, out]
8253  *   Pointer to rte_eth_dev structure.
8254  * @param[in, out] tag_be24
8255  *   Tag value in big endian then R-shift 8.
8256  * @parm[in, out] dev_flow
8257  *   Pointer to the dev_flow.
8258  * @param[out] error
8259  *   pointer to error structure.
8260  *
8261  * @return
8262  *   0 on success otherwise -errno and errno is set.
8263  */
8264 static int
8265 flow_dv_tag_resource_register
8266                         (struct rte_eth_dev *dev,
8267                          uint32_t tag_be24,
8268                          struct mlx5_flow *dev_flow,
8269                          struct rte_flow_error *error)
8270 {
8271         struct mlx5_priv *priv = dev->data->dev_private;
8272         struct mlx5_flow_dv_tag_resource *cache_resource;
8273         struct mlx5_hlist_entry *entry;
8274
8275         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
8276         if (entry) {
8277                 cache_resource = container_of
8278                         (entry, struct mlx5_flow_dv_tag_resource, entry);
8279                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
8280                 dev_flow->dv.tag_resource = cache_resource;
8281                 return 0;
8282         }
8283         return -rte_errno;
8284 }
8285
8286 void
8287 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
8288                       struct mlx5_hlist_entry *entry)
8289 {
8290         struct mlx5_dev_ctx_shared *sh = list->ctx;
8291         struct mlx5_flow_dv_tag_resource *tag =
8292                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
8293
8294         MLX5_ASSERT(tag && sh && tag->action);
8295         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
8296         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
8297         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
8298 }
8299
8300 /**
8301  * Release the tag.
8302  *
8303  * @param dev
8304  *   Pointer to Ethernet device.
8305  * @param tag_idx
8306  *   Tag index.
8307  *
8308  * @return
8309  *   1 while a reference on it exists, 0 when freed.
8310  */
8311 static int
8312 flow_dv_tag_release(struct rte_eth_dev *dev,
8313                     uint32_t tag_idx)
8314 {
8315         struct mlx5_priv *priv = dev->data->dev_private;
8316         struct mlx5_flow_dv_tag_resource *tag;
8317
8318         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
8319         if (!tag)
8320                 return 0;
8321         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
8322                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
8323         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
8324 }
8325
8326 /**
8327  * Translate port ID action to vport.
8328  *
8329  * @param[in] dev
8330  *   Pointer to rte_eth_dev structure.
8331  * @param[in] action
8332  *   Pointer to the port ID action.
8333  * @param[out] dst_port_id
8334  *   The target port ID.
8335  * @param[out] error
8336  *   Pointer to the error structure.
8337  *
8338  * @return
8339  *   0 on success, a negative errno value otherwise and rte_errno is set.
8340  */
8341 static int
8342 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
8343                                  const struct rte_flow_action *action,
8344                                  uint32_t *dst_port_id,
8345                                  struct rte_flow_error *error)
8346 {
8347         uint32_t port;
8348         struct mlx5_priv *priv;
8349         const struct rte_flow_action_port_id *conf =
8350                         (const struct rte_flow_action_port_id *)action->conf;
8351
8352         port = conf->original ? dev->data->port_id : conf->id;
8353         priv = mlx5_port_to_eswitch_info(port, false);
8354         if (!priv)
8355                 return rte_flow_error_set(error, -rte_errno,
8356                                           RTE_FLOW_ERROR_TYPE_ACTION,
8357                                           NULL,
8358                                           "No eswitch info was found for port");
8359 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
8360         /*
8361          * This parameter is transferred to
8362          * mlx5dv_dr_action_create_dest_ib_port().
8363          */
8364         *dst_port_id = priv->dev_port;
8365 #else
8366         /*
8367          * Legacy mode, no LAG configurations is supported.
8368          * This parameter is transferred to
8369          * mlx5dv_dr_action_create_dest_vport().
8370          */
8371         *dst_port_id = priv->vport_id;
8372 #endif
8373         return 0;
8374 }
8375
8376 /**
8377  * Create a counter with aging configuration.
8378  *
8379  * @param[in] dev
8380  *   Pointer to rte_eth_dev structure.
8381  * @param[out] count
8382  *   Pointer to the counter action configuration.
8383  * @param[in] age
8384  *   Pointer to the aging action configuration.
8385  *
8386  * @return
8387  *   Index to flow counter on success, 0 otherwise.
8388  */
8389 static uint32_t
8390 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
8391                                 struct mlx5_flow *dev_flow,
8392                                 const struct rte_flow_action_count *count,
8393                                 const struct rte_flow_action_age *age)
8394 {
8395         uint32_t counter;
8396         struct mlx5_age_param *age_param;
8397
8398         if (count && count->shared)
8399                 counter = flow_dv_counter_get_shared(dev, count->id);
8400         else
8401                 counter = flow_dv_counter_alloc(dev, !!age);
8402         if (!counter || age == NULL)
8403                 return counter;
8404         age_param  = flow_dv_counter_idx_get_age(dev, counter);
8405         age_param->context = age->context ? age->context :
8406                 (void *)(uintptr_t)(dev_flow->flow_idx);
8407         age_param->timeout = age->timeout;
8408         age_param->port_id = dev->data->port_id;
8409         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
8410         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
8411         return counter;
8412 }
8413 /**
8414  * Add Tx queue matcher
8415  *
8416  * @param[in] dev
8417  *   Pointer to the dev struct.
8418  * @param[in, out] matcher
8419  *   Flow matcher.
8420  * @param[in, out] key
8421  *   Flow matcher value.
8422  * @param[in] item
8423  *   Flow pattern to translate.
8424  * @param[in] inner
8425  *   Item is inner pattern.
8426  */
8427 static void
8428 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
8429                                 void *matcher, void *key,
8430                                 const struct rte_flow_item *item)
8431 {
8432         const struct mlx5_rte_flow_item_tx_queue *queue_m;
8433         const struct mlx5_rte_flow_item_tx_queue *queue_v;
8434         void *misc_m =
8435                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8436         void *misc_v =
8437                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8438         struct mlx5_txq_ctrl *txq;
8439         uint32_t queue;
8440
8441
8442         queue_m = (const void *)item->mask;
8443         if (!queue_m)
8444                 return;
8445         queue_v = (const void *)item->spec;
8446         if (!queue_v)
8447                 return;
8448         txq = mlx5_txq_get(dev, queue_v->queue);
8449         if (!txq)
8450                 return;
8451         queue = txq->obj->sq->id;
8452         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
8453         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
8454                  queue & queue_m->queue);
8455         mlx5_txq_release(dev, queue_v->queue);
8456 }
8457
8458 /**
8459  * Set the hash fields according to the @p flow information.
8460  *
8461  * @param[in] dev_flow
8462  *   Pointer to the mlx5_flow.
8463  * @param[in] rss_desc
8464  *   Pointer to the mlx5_flow_rss_desc.
8465  */
8466 static void
8467 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
8468                        struct mlx5_flow_rss_desc *rss_desc)
8469 {
8470         uint64_t items = dev_flow->handle->layers;
8471         int rss_inner = 0;
8472         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
8473
8474         dev_flow->hash_fields = 0;
8475 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
8476         if (rss_desc->level >= 2) {
8477                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
8478                 rss_inner = 1;
8479         }
8480 #endif
8481         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
8482             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
8483                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
8484                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8485                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
8486                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8487                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
8488                         else
8489                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
8490                 }
8491         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
8492                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
8493                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
8494                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
8495                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
8496                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
8497                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
8498                         else
8499                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
8500                 }
8501         }
8502         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
8503             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
8504                 if (rss_types & ETH_RSS_UDP) {
8505                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8506                                 dev_flow->hash_fields |=
8507                                                 IBV_RX_HASH_SRC_PORT_UDP;
8508                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8509                                 dev_flow->hash_fields |=
8510                                                 IBV_RX_HASH_DST_PORT_UDP;
8511                         else
8512                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
8513                 }
8514         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
8515                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
8516                 if (rss_types & ETH_RSS_TCP) {
8517                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
8518                                 dev_flow->hash_fields |=
8519                                                 IBV_RX_HASH_SRC_PORT_TCP;
8520                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
8521                                 dev_flow->hash_fields |=
8522                                                 IBV_RX_HASH_DST_PORT_TCP;
8523                         else
8524                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
8525                 }
8526         }
8527 }
8528
8529 /**
8530  * Prepare an Rx Hash queue.
8531  *
8532  * @param dev
8533  *   Pointer to Ethernet device.
8534  * @param[in] dev_flow
8535  *   Pointer to the mlx5_flow.
8536  * @param[in] rss_desc
8537  *   Pointer to the mlx5_flow_rss_desc.
8538  * @param[out] hrxq_idx
8539  *   Hash Rx queue index.
8540  *
8541  * @return
8542  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
8543  */
8544 static struct mlx5_hrxq *
8545 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
8546                      struct mlx5_flow *dev_flow,
8547                      struct mlx5_flow_rss_desc *rss_desc,
8548                      uint32_t *hrxq_idx)
8549 {
8550         struct mlx5_priv *priv = dev->data->dev_private;
8551         struct mlx5_flow_handle *dh = dev_flow->handle;
8552         struct mlx5_hrxq *hrxq;
8553
8554         MLX5_ASSERT(rss_desc->queue_num);
8555         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
8556         rss_desc->hash_fields = dev_flow->hash_fields;
8557         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
8558         rss_desc->standalone = false;
8559         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
8560         if (!*hrxq_idx)
8561                 return NULL;
8562         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8563                               *hrxq_idx);
8564         return hrxq;
8565 }
8566
8567 /**
8568  * Find existing sample resource or create and register a new one.
8569  *
8570  * @param[in, out] dev
8571  *   Pointer to rte_eth_dev structure.
8572  * @param[in] attr
8573  *   Attributes of flow that includes this item.
8574  * @param[in] resource
8575  *   Pointer to sample resource.
8576  * @parm[in, out] dev_flow
8577  *   Pointer to the dev_flow.
8578  * @param[in, out] sample_dv_actions
8579  *   Pointer to sample actions list.
8580  * @param[out] error
8581  *   pointer to error structure.
8582  *
8583  * @return
8584  *   0 on success otherwise -errno and errno is set.
8585  */
8586 static int
8587 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
8588                          const struct rte_flow_attr *attr,
8589                          struct mlx5_flow_dv_sample_resource *resource,
8590                          struct mlx5_flow *dev_flow,
8591                          void **sample_dv_actions,
8592                          struct rte_flow_error *error)
8593 {
8594         struct mlx5_flow_dv_sample_resource *cache_resource;
8595         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
8596         struct mlx5_priv *priv = dev->data->dev_private;
8597         struct mlx5_dev_ctx_shared *sh = priv->sh;
8598         struct mlx5_flow_tbl_resource *tbl;
8599         uint32_t idx = 0;
8600         const uint32_t next_ft_step = 1;
8601         uint32_t next_ft_id = resource->ft_id + next_ft_step;
8602
8603         /* Lookup a matching resource from cache. */
8604         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_SAMPLE], sh->sample_action_list,
8605                       idx, cache_resource, next) {
8606                 if (resource->ratio == cache_resource->ratio &&
8607                     resource->ft_type == cache_resource->ft_type &&
8608                     resource->ft_id == cache_resource->ft_id &&
8609                     resource->set_action == cache_resource->set_action &&
8610                     !memcmp((void *)&resource->sample_act,
8611                             (void *)&cache_resource->sample_act,
8612                             sizeof(struct mlx5_flow_sub_actions_list))) {
8613                         DRV_LOG(DEBUG, "sample resource %p: refcnt %d++",
8614                                 (void *)cache_resource,
8615                                 __atomic_load_n(&cache_resource->refcnt,
8616                                                 __ATOMIC_RELAXED));
8617                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8618                                            __ATOMIC_RELAXED);
8619                         dev_flow->handle->dvh.rix_sample = idx;
8620                         dev_flow->dv.sample_res = cache_resource;
8621                         return 0;
8622                 }
8623         }
8624         /* Register new sample resource. */
8625         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE],
8626                                        &dev_flow->handle->dvh.rix_sample);
8627         if (!cache_resource)
8628                 return rte_flow_error_set(error, ENOMEM,
8629                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8630                                           NULL,
8631                                           "cannot allocate resource memory");
8632         *cache_resource = *resource;
8633         /* Create normal path table level */
8634         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
8635                                         attr->egress, attr->transfer,
8636                                         dev_flow->external, NULL, 0, 0, error);
8637         if (!tbl) {
8638                 rte_flow_error_set(error, ENOMEM,
8639                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8640                                           NULL,
8641                                           "fail to create normal path table "
8642                                           "for sample");
8643                 goto error;
8644         }
8645         cache_resource->normal_path_tbl = tbl;
8646         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8647                 cache_resource->default_miss =
8648                                 mlx5_glue->dr_create_flow_action_default_miss();
8649                 if (!cache_resource->default_miss) {
8650                         rte_flow_error_set(error, ENOMEM,
8651                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8652                                                 NULL,
8653                                                 "cannot create default miss "
8654                                                 "action");
8655                         goto error;
8656                 }
8657                 sample_dv_actions[resource->sample_act.actions_num++] =
8658                                                 cache_resource->default_miss;
8659         }
8660         /* Create a DR sample action */
8661         sampler_attr.sample_ratio = cache_resource->ratio;
8662         sampler_attr.default_next_table = tbl->obj;
8663         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
8664         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
8665                                                         &sample_dv_actions[0];
8666         sampler_attr.action = cache_resource->set_action;
8667         cache_resource->verbs_action =
8668                 mlx5_glue->dr_create_flow_action_sampler(&sampler_attr);
8669         if (!cache_resource->verbs_action) {
8670                 rte_flow_error_set(error, ENOMEM,
8671                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8672                                         NULL, "cannot create sample action");
8673                 goto error;
8674         }
8675         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8676         ILIST_INSERT(sh->ipool[MLX5_IPOOL_SAMPLE], &sh->sample_action_list,
8677                      dev_flow->handle->dvh.rix_sample, cache_resource,
8678                      next);
8679         dev_flow->dv.sample_res = cache_resource;
8680         DRV_LOG(DEBUG, "new sample resource %p: refcnt %d++",
8681                 (void *)cache_resource,
8682                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8683         return 0;
8684 error:
8685         if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
8686                 if (cache_resource->default_miss)
8687                         claim_zero(mlx5_glue->destroy_flow_action
8688                                 (cache_resource->default_miss));
8689         } else {
8690                 if (cache_resource->sample_idx.rix_hrxq &&
8691                     !mlx5_hrxq_release(dev,
8692                                 cache_resource->sample_idx.rix_hrxq))
8693                         cache_resource->sample_idx.rix_hrxq = 0;
8694                 if (cache_resource->sample_idx.rix_tag &&
8695                     !flow_dv_tag_release(dev,
8696                                 cache_resource->sample_idx.rix_tag))
8697                         cache_resource->sample_idx.rix_tag = 0;
8698                 if (cache_resource->sample_idx.cnt) {
8699                         flow_dv_counter_release(dev,
8700                                 cache_resource->sample_idx.cnt);
8701                         cache_resource->sample_idx.cnt = 0;
8702                 }
8703         }
8704         if (cache_resource->normal_path_tbl)
8705                 flow_dv_tbl_resource_release(dev,
8706                                 cache_resource->normal_path_tbl);
8707         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE],
8708                                 dev_flow->handle->dvh.rix_sample);
8709         dev_flow->handle->dvh.rix_sample = 0;
8710         return -rte_errno;
8711 }
8712
8713 /**
8714  * Find existing destination array resource or create and register a new one.
8715  *
8716  * @param[in, out] dev
8717  *   Pointer to rte_eth_dev structure.
8718  * @param[in] attr
8719  *   Attributes of flow that includes this item.
8720  * @param[in] resource
8721  *   Pointer to destination array resource.
8722  * @parm[in, out] dev_flow
8723  *   Pointer to the dev_flow.
8724  * @param[out] error
8725  *   pointer to error structure.
8726  *
8727  * @return
8728  *   0 on success otherwise -errno and errno is set.
8729  */
8730 static int
8731 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
8732                          const struct rte_flow_attr *attr,
8733                          struct mlx5_flow_dv_dest_array_resource *resource,
8734                          struct mlx5_flow *dev_flow,
8735                          struct rte_flow_error *error)
8736 {
8737         struct mlx5_flow_dv_dest_array_resource *cache_resource;
8738         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
8739         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
8740         struct mlx5_priv *priv = dev->data->dev_private;
8741         struct mlx5_dev_ctx_shared *sh = priv->sh;
8742         struct mlx5_flow_sub_actions_list *sample_act;
8743         struct mlx5dv_dr_domain *domain;
8744         uint32_t idx = 0;
8745
8746         /* Lookup a matching resource from cache. */
8747         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8748                       sh->dest_array_list,
8749                       idx, cache_resource, next) {
8750                 if (resource->num_of_dest == cache_resource->num_of_dest &&
8751                     resource->ft_type == cache_resource->ft_type &&
8752                     !memcmp((void *)cache_resource->sample_act,
8753                             (void *)resource->sample_act,
8754                            (resource->num_of_dest *
8755                            sizeof(struct mlx5_flow_sub_actions_list)))) {
8756                         DRV_LOG(DEBUG, "dest array resource %p: refcnt %d++",
8757                                 (void *)cache_resource,
8758                                 __atomic_load_n(&cache_resource->refcnt,
8759                                                 __ATOMIC_RELAXED));
8760                         __atomic_fetch_add(&cache_resource->refcnt, 1,
8761                                            __ATOMIC_RELAXED);
8762                         dev_flow->handle->dvh.rix_dest_array = idx;
8763                         dev_flow->dv.dest_array_res = cache_resource;
8764                         return 0;
8765                 }
8766         }
8767         /* Register new destination array resource. */
8768         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8769                                        &dev_flow->handle->dvh.rix_dest_array);
8770         if (!cache_resource)
8771                 return rte_flow_error_set(error, ENOMEM,
8772                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8773                                           NULL,
8774                                           "cannot allocate resource memory");
8775         *cache_resource = *resource;
8776         if (attr->transfer)
8777                 domain = sh->fdb_domain;
8778         else if (attr->ingress)
8779                 domain = sh->rx_domain;
8780         else
8781                 domain = sh->tx_domain;
8782         for (idx = 0; idx < resource->num_of_dest; idx++) {
8783                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
8784                                  mlx5_malloc(MLX5_MEM_ZERO,
8785                                  sizeof(struct mlx5dv_dr_action_dest_attr),
8786                                  0, SOCKET_ID_ANY);
8787                 if (!dest_attr[idx]) {
8788                         rte_flow_error_set(error, ENOMEM,
8789                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8790                                            NULL,
8791                                            "cannot allocate resource memory");
8792                         goto error;
8793                 }
8794                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
8795                 sample_act = &resource->sample_act[idx];
8796                 if (sample_act->action_flags == MLX5_FLOW_ACTION_QUEUE) {
8797                         dest_attr[idx]->dest = sample_act->dr_queue_action;
8798                 } else if (sample_act->action_flags ==
8799                           (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP)) {
8800                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
8801                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
8802                         dest_attr[idx]->dest_reformat->reformat =
8803                                         sample_act->dr_encap_action;
8804                         dest_attr[idx]->dest_reformat->dest =
8805                                         sample_act->dr_port_id_action;
8806                 } else if (sample_act->action_flags ==
8807                            MLX5_FLOW_ACTION_PORT_ID) {
8808                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
8809                 }
8810         }
8811         /* create a dest array actioin */
8812         cache_resource->action = mlx5_glue->dr_create_flow_action_dest_array
8813                                                 (domain,
8814                                                  cache_resource->num_of_dest,
8815                                                  dest_attr);
8816         if (!cache_resource->action) {
8817                 rte_flow_error_set(error, ENOMEM,
8818                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8819                                    NULL,
8820                                    "cannot create destination array action");
8821                 goto error;
8822         }
8823         __atomic_store_n(&cache_resource->refcnt, 1, __ATOMIC_RELAXED);
8824         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8825                      &sh->dest_array_list,
8826                      dev_flow->handle->dvh.rix_dest_array, cache_resource,
8827                      next);
8828         dev_flow->dv.dest_array_res = cache_resource;
8829         DRV_LOG(DEBUG, "new destination array resource %p: refcnt %d++",
8830                 (void *)cache_resource,
8831                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
8832         for (idx = 0; idx < resource->num_of_dest; idx++)
8833                 mlx5_free(dest_attr[idx]);
8834         return 0;
8835 error:
8836         for (idx = 0; idx < resource->num_of_dest; idx++) {
8837                 struct mlx5_flow_sub_actions_idx *act_res =
8838                                         &cache_resource->sample_idx[idx];
8839                 if (act_res->rix_hrxq &&
8840                     !mlx5_hrxq_release(dev,
8841                                 act_res->rix_hrxq))
8842                         act_res->rix_hrxq = 0;
8843                 if (act_res->rix_encap_decap &&
8844                         !flow_dv_encap_decap_resource_release(dev,
8845                                 act_res->rix_encap_decap))
8846                         act_res->rix_encap_decap = 0;
8847                 if (act_res->rix_port_id_action &&
8848                         !flow_dv_port_id_action_resource_release(dev,
8849                                 act_res->rix_port_id_action))
8850                         act_res->rix_port_id_action = 0;
8851                 if (dest_attr[idx])
8852                         mlx5_free(dest_attr[idx]);
8853         }
8854
8855         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
8856                                 dev_flow->handle->dvh.rix_dest_array);
8857         dev_flow->handle->dvh.rix_dest_array = 0;
8858         return -rte_errno;
8859 }
8860
8861 /**
8862  * Convert Sample action to DV specification.
8863  *
8864  * @param[in] dev
8865  *   Pointer to rte_eth_dev structure.
8866  * @param[in] action
8867  *   Pointer to action structure.
8868  * @param[in, out] dev_flow
8869  *   Pointer to the mlx5_flow.
8870  * @param[in] attr
8871  *   Pointer to the flow attributes.
8872  * @param[in, out] num_of_dest
8873  *   Pointer to the num of destination.
8874  * @param[in, out] sample_actions
8875  *   Pointer to sample actions list.
8876  * @param[in, out] res
8877  *   Pointer to sample resource.
8878  * @param[out] error
8879  *   Pointer to the error structure.
8880  *
8881  * @return
8882  *   0 on success, a negative errno value otherwise and rte_errno is set.
8883  */
8884 static int
8885 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
8886                                 const struct rte_flow_action *action,
8887                                 struct mlx5_flow *dev_flow,
8888                                 const struct rte_flow_attr *attr,
8889                                 uint32_t *num_of_dest,
8890                                 void **sample_actions,
8891                                 struct mlx5_flow_dv_sample_resource *res,
8892                                 struct rte_flow_error *error)
8893 {
8894         struct mlx5_priv *priv = dev->data->dev_private;
8895         const struct rte_flow_action_sample *sample_action;
8896         const struct rte_flow_action *sub_actions;
8897         const struct rte_flow_action_queue *queue;
8898         struct mlx5_flow_sub_actions_list *sample_act;
8899         struct mlx5_flow_sub_actions_idx *sample_idx;
8900         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
8901         struct mlx5_flow_rss_desc *rss_desc;
8902         uint64_t action_flags = 0;
8903
8904         MLX5_ASSERT(wks);
8905         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
8906         sample_act = &res->sample_act;
8907         sample_idx = &res->sample_idx;
8908         sample_action = (const struct rte_flow_action_sample *)action->conf;
8909         res->ratio = sample_action->ratio;
8910         sub_actions = sample_action->actions;
8911         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
8912                 int type = sub_actions->type;
8913                 uint32_t pre_rix = 0;
8914                 void *pre_r;
8915                 switch (type) {
8916                 case RTE_FLOW_ACTION_TYPE_QUEUE:
8917                 {
8918                         struct mlx5_hrxq *hrxq;
8919                         uint32_t hrxq_idx;
8920
8921                         queue = sub_actions->conf;
8922                         rss_desc->queue_num = 1;
8923                         rss_desc->queue[0] = queue->index;
8924                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
8925                                                     rss_desc, &hrxq_idx);
8926                         if (!hrxq)
8927                                 return rte_flow_error_set
8928                                         (error, rte_errno,
8929                                          RTE_FLOW_ERROR_TYPE_ACTION,
8930                                          NULL,
8931                                          "cannot create fate queue");
8932                         sample_act->dr_queue_action = hrxq->action;
8933                         sample_idx->rix_hrxq = hrxq_idx;
8934                         sample_actions[sample_act->actions_num++] =
8935                                                 hrxq->action;
8936                         (*num_of_dest)++;
8937                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
8938                         if (action_flags & MLX5_FLOW_ACTION_MARK)
8939                                 dev_flow->handle->rix_hrxq = hrxq_idx;
8940                         dev_flow->handle->fate_action =
8941                                         MLX5_FLOW_FATE_QUEUE;
8942                         break;
8943                 }
8944                 case RTE_FLOW_ACTION_TYPE_MARK:
8945                 {
8946                         uint32_t tag_be = mlx5_flow_mark_set
8947                                 (((const struct rte_flow_action_mark *)
8948                                 (sub_actions->conf))->id);
8949
8950                         dev_flow->handle->mark = 1;
8951                         pre_rix = dev_flow->handle->dvh.rix_tag;
8952                         /* Save the mark resource before sample */
8953                         pre_r = dev_flow->dv.tag_resource;
8954                         if (flow_dv_tag_resource_register(dev, tag_be,
8955                                                   dev_flow, error))
8956                                 return -rte_errno;
8957                         MLX5_ASSERT(dev_flow->dv.tag_resource);
8958                         sample_act->dr_tag_action =
8959                                 dev_flow->dv.tag_resource->action;
8960                         sample_idx->rix_tag =
8961                                 dev_flow->handle->dvh.rix_tag;
8962                         sample_actions[sample_act->actions_num++] =
8963                                                 sample_act->dr_tag_action;
8964                         /* Recover the mark resource after sample */
8965                         dev_flow->dv.tag_resource = pre_r;
8966                         dev_flow->handle->dvh.rix_tag = pre_rix;
8967                         action_flags |= MLX5_FLOW_ACTION_MARK;
8968                         break;
8969                 }
8970                 case RTE_FLOW_ACTION_TYPE_COUNT:
8971                 {
8972                         uint32_t counter;
8973
8974                         counter = flow_dv_translate_create_counter(dev,
8975                                         dev_flow, sub_actions->conf, 0);
8976                         if (!counter)
8977                                 return rte_flow_error_set
8978                                                 (error, rte_errno,
8979                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8980                                                  NULL,
8981                                                  "cannot create counter"
8982                                                  " object.");
8983                         sample_idx->cnt = counter;
8984                         sample_act->dr_cnt_action =
8985                                   (flow_dv_counter_get_by_idx(dev,
8986                                   counter, NULL))->action;
8987                         sample_actions[sample_act->actions_num++] =
8988                                                 sample_act->dr_cnt_action;
8989                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8990                         break;
8991                 }
8992                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8993                 {
8994                         struct mlx5_flow_dv_port_id_action_resource
8995                                         port_id_resource;
8996                         uint32_t port_id = 0;
8997
8998                         memset(&port_id_resource, 0, sizeof(port_id_resource));
8999                         /* Save the port id resource before sample */
9000                         pre_rix = dev_flow->handle->rix_port_id_action;
9001                         pre_r = dev_flow->dv.port_id_action;
9002                         if (flow_dv_translate_action_port_id(dev, sub_actions,
9003                                                              &port_id, error))
9004                                 return -rte_errno;
9005                         port_id_resource.port_id = port_id;
9006                         if (flow_dv_port_id_action_resource_register
9007                             (dev, &port_id_resource, dev_flow, error))
9008                                 return -rte_errno;
9009                         sample_act->dr_port_id_action =
9010                                 dev_flow->dv.port_id_action->action;
9011                         sample_idx->rix_port_id_action =
9012                                 dev_flow->handle->rix_port_id_action;
9013                         sample_actions[sample_act->actions_num++] =
9014                                                 sample_act->dr_port_id_action;
9015                         /* Recover the port id resource after sample */
9016                         dev_flow->dv.port_id_action = pre_r;
9017                         dev_flow->handle->rix_port_id_action = pre_rix;
9018                         (*num_of_dest)++;
9019                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9020                         break;
9021                 }
9022                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9023                         /* Save the encap resource before sample */
9024                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
9025                         pre_r = dev_flow->dv.encap_decap;
9026                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
9027                                                            dev_flow,
9028                                                            attr->transfer,
9029                                                            error))
9030                                 return -rte_errno;
9031                         sample_act->dr_encap_action =
9032                                 dev_flow->dv.encap_decap->action;
9033                         sample_idx->rix_encap_decap =
9034                                 dev_flow->handle->dvh.rix_encap_decap;
9035                         sample_actions[sample_act->actions_num++] =
9036                                                 sample_act->dr_encap_action;
9037                         /* Recover the encap resource after sample */
9038                         dev_flow->dv.encap_decap = pre_r;
9039                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
9040                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9041                         break;
9042                 default:
9043                         return rte_flow_error_set(error, EINVAL,
9044                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9045                                 NULL,
9046                                 "Not support for sampler action");
9047                 }
9048         }
9049         sample_act->action_flags = action_flags;
9050         res->ft_id = dev_flow->dv.group;
9051         if (attr->transfer) {
9052                 union {
9053                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
9054                         uint64_t set_action;
9055                 } action_ctx = { .set_action = 0 };
9056
9057                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9058                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
9059                          MLX5_MODIFICATION_TYPE_SET);
9060                 MLX5_SET(set_action_in, action_ctx.action_in, field,
9061                          MLX5_MODI_META_REG_C_0);
9062                 MLX5_SET(set_action_in, action_ctx.action_in, data,
9063                          priv->vport_meta_tag);
9064                 res->set_action = action_ctx.set_action;
9065         } else if (attr->ingress) {
9066                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9067         }
9068         return 0;
9069 }
9070
9071 /**
9072  * Convert Sample action to DV specification.
9073  *
9074  * @param[in] dev
9075  *   Pointer to rte_eth_dev structure.
9076  * @param[in, out] dev_flow
9077  *   Pointer to the mlx5_flow.
9078  * @param[in] attr
9079  *   Pointer to the flow attributes.
9080  * @param[in] num_of_dest
9081  *   The num of destination.
9082  * @param[in, out] res
9083  *   Pointer to sample resource.
9084  * @param[in, out] mdest_res
9085  *   Pointer to destination array resource.
9086  * @param[in] sample_actions
9087  *   Pointer to sample path actions list.
9088  * @param[in] action_flags
9089  *   Holds the actions detected until now.
9090  * @param[out] error
9091  *   Pointer to the error structure.
9092  *
9093  * @return
9094  *   0 on success, a negative errno value otherwise and rte_errno is set.
9095  */
9096 static int
9097 flow_dv_create_action_sample(struct rte_eth_dev *dev,
9098                              struct mlx5_flow *dev_flow,
9099                              const struct rte_flow_attr *attr,
9100                              uint32_t num_of_dest,
9101                              struct mlx5_flow_dv_sample_resource *res,
9102                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
9103                              void **sample_actions,
9104                              uint64_t action_flags,
9105                              struct rte_flow_error *error)
9106 {
9107         /* update normal path action resource into last index of array */
9108         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
9109         struct mlx5_flow_sub_actions_list *sample_act =
9110                                         &mdest_res->sample_act[dest_index];
9111         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9112         struct mlx5_flow_rss_desc *rss_desc;
9113         uint32_t normal_idx = 0;
9114         struct mlx5_hrxq *hrxq;
9115         uint32_t hrxq_idx;
9116
9117         MLX5_ASSERT(wks);
9118         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
9119         if (num_of_dest > 1) {
9120                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
9121                         /* Handle QP action for mirroring */
9122                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
9123                                                     rss_desc, &hrxq_idx);
9124                         if (!hrxq)
9125                                 return rte_flow_error_set
9126                                      (error, rte_errno,
9127                                       RTE_FLOW_ERROR_TYPE_ACTION,
9128                                       NULL,
9129                                       "cannot create rx queue");
9130                         normal_idx++;
9131                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
9132                         sample_act->dr_queue_action = hrxq->action;
9133                         if (action_flags & MLX5_FLOW_ACTION_MARK)
9134                                 dev_flow->handle->rix_hrxq = hrxq_idx;
9135                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9136                 }
9137                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
9138                         normal_idx++;
9139                         mdest_res->sample_idx[dest_index].rix_encap_decap =
9140                                 dev_flow->handle->dvh.rix_encap_decap;
9141                         sample_act->dr_encap_action =
9142                                 dev_flow->dv.encap_decap->action;
9143                 }
9144                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
9145                         normal_idx++;
9146                         mdest_res->sample_idx[dest_index].rix_port_id_action =
9147                                 dev_flow->handle->rix_port_id_action;
9148                         sample_act->dr_port_id_action =
9149                                 dev_flow->dv.port_id_action->action;
9150                 }
9151                 sample_act->actions_num = normal_idx;
9152                 /* update sample action resource into first index of array */
9153                 mdest_res->ft_type = res->ft_type;
9154                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
9155                                 sizeof(struct mlx5_flow_sub_actions_idx));
9156                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
9157                                 sizeof(struct mlx5_flow_sub_actions_list));
9158                 mdest_res->num_of_dest = num_of_dest;
9159                 if (flow_dv_dest_array_resource_register(dev, attr, mdest_res,
9160                                                          dev_flow, error))
9161                         return rte_flow_error_set(error, EINVAL,
9162                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9163                                                   NULL, "can't create sample "
9164                                                   "action");
9165         } else {
9166                 if (flow_dv_sample_resource_register(dev, attr, res, dev_flow,
9167                                                      sample_actions, error))
9168                         return rte_flow_error_set(error, EINVAL,
9169                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9170                                                   NULL,
9171                                                   "can't create sample action");
9172         }
9173         return 0;
9174 }
9175
9176 /**
9177  * Fill the flow with DV spec, lock free
9178  * (mutex should be acquired by caller).
9179  *
9180  * @param[in] dev
9181  *   Pointer to rte_eth_dev structure.
9182  * @param[in, out] dev_flow
9183  *   Pointer to the sub flow.
9184  * @param[in] attr
9185  *   Pointer to the flow attributes.
9186  * @param[in] items
9187  *   Pointer to the list of items.
9188  * @param[in] actions
9189  *   Pointer to the list of actions.
9190  * @param[out] error
9191  *   Pointer to the error structure.
9192  *
9193  * @return
9194  *   0 on success, a negative errno value otherwise and rte_errno is set.
9195  */
9196 static int
9197 __flow_dv_translate(struct rte_eth_dev *dev,
9198                     struct mlx5_flow *dev_flow,
9199                     const struct rte_flow_attr *attr,
9200                     const struct rte_flow_item items[],
9201                     const struct rte_flow_action actions[],
9202                     struct rte_flow_error *error)
9203 {
9204         struct mlx5_priv *priv = dev->data->dev_private;
9205         struct mlx5_dev_config *dev_conf = &priv->config;
9206         struct rte_flow *flow = dev_flow->flow;
9207         struct mlx5_flow_handle *handle = dev_flow->handle;
9208         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
9209         struct mlx5_flow_rss_desc *rss_desc;
9210         uint64_t item_flags = 0;
9211         uint64_t last_item = 0;
9212         uint64_t action_flags = 0;
9213         uint64_t priority = attr->priority;
9214         struct mlx5_flow_dv_matcher matcher = {
9215                 .mask = {
9216                         .size = sizeof(matcher.mask.buf) -
9217                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
9218                 },
9219         };
9220         int actions_n = 0;
9221         bool actions_end = false;
9222         union {
9223                 struct mlx5_flow_dv_modify_hdr_resource res;
9224                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
9225                             sizeof(struct mlx5_modification_cmd) *
9226                             (MLX5_MAX_MODIFY_NUM + 1)];
9227         } mhdr_dummy;
9228         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
9229         const struct rte_flow_action_count *count = NULL;
9230         const struct rte_flow_action_age *age = NULL;
9231         union flow_dv_attr flow_attr = { .attr = 0 };
9232         uint32_t tag_be;
9233         union mlx5_flow_tbl_key tbl_key;
9234         uint32_t modify_action_position = UINT32_MAX;
9235         void *match_mask = matcher.mask.buf;
9236         void *match_value = dev_flow->dv.value.buf;
9237         uint8_t next_protocol = 0xff;
9238         struct rte_vlan_hdr vlan = { 0 };
9239         struct mlx5_flow_dv_dest_array_resource mdest_res;
9240         struct mlx5_flow_dv_sample_resource sample_res;
9241         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9242         struct mlx5_flow_sub_actions_list *sample_act;
9243         uint32_t sample_act_pos = UINT32_MAX;
9244         uint32_t num_of_dest = 0;
9245         int tmp_actions_n = 0;
9246         uint32_t table;
9247         int ret = 0;
9248         const struct mlx5_flow_tunnel *tunnel;
9249         struct flow_grp_info grp_info = {
9250                 .external = !!dev_flow->external,
9251                 .transfer = !!attr->transfer,
9252                 .fdb_def_rule = !!priv->fdb_def_rule,
9253         };
9254
9255         MLX5_ASSERT(wks);
9256         rss_desc = &wks->rss_desc[!!wks->flow_nested_idx];
9257         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
9258         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
9259         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9260                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9261         /* update normal path action resource into last index of array */
9262         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
9263         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
9264                  flow_items_to_tunnel(items) :
9265                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
9266                  flow_actions_to_tunnel(actions) :
9267                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
9268         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
9269                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
9270         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
9271                                 (dev, tunnel, attr, items, actions);
9272         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
9273                                        grp_info, error);
9274         if (ret)
9275                 return ret;
9276         dev_flow->dv.group = table;
9277         if (attr->transfer)
9278                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
9279         if (priority == MLX5_FLOW_PRIO_RSVD)
9280                 priority = dev_conf->flow_prio - 1;
9281         /* number of actions must be set to 0 in case of dirty stack. */
9282         mhdr_res->actions_num = 0;
9283         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
9284                 /*
9285                  * do not add decap action if match rule drops packet
9286                  * HW rejects rules with decap & drop
9287                  */
9288                 bool add_decap = true;
9289                 const struct rte_flow_action *ptr = actions;
9290                 struct mlx5_flow_tbl_resource *tbl;
9291
9292                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
9293                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
9294                                 add_decap = false;
9295                                 break;
9296                         }
9297                 }
9298                 if (add_decap) {
9299                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9300                                                            attr->transfer,
9301                                                            error))
9302                                 return -rte_errno;
9303                         dev_flow->dv.actions[actions_n++] =
9304                                         dev_flow->dv.encap_decap->action;
9305                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9306                 }
9307                 /*
9308                  * bind table_id with <group, table> for tunnel match rule.
9309                  * Tunnel set rule establishes that bind in JUMP action handler.
9310                  * Required for scenario when application creates tunnel match
9311                  * rule before tunnel set rule.
9312                  */
9313                 tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9314                                                attr->transfer,
9315                                                !!dev_flow->external, tunnel,
9316                                                attr->group, 0, error);
9317                 if (!tbl)
9318                         return rte_flow_error_set
9319                                (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
9320                                actions, "cannot register tunnel group");
9321         }
9322         for (; !actions_end ; actions++) {
9323                 const struct rte_flow_action_queue *queue;
9324                 const struct rte_flow_action_rss *rss;
9325                 const struct rte_flow_action *action = actions;
9326                 const uint8_t *rss_key;
9327                 const struct rte_flow_action_meter *mtr;
9328                 struct mlx5_flow_tbl_resource *tbl;
9329                 uint32_t port_id = 0;
9330                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
9331                 int action_type = actions->type;
9332                 const struct rte_flow_action *found_action = NULL;
9333                 struct mlx5_flow_meter *fm = NULL;
9334                 uint32_t jump_group = 0;
9335
9336                 if (!mlx5_flow_os_action_supported(action_type))
9337                         return rte_flow_error_set(error, ENOTSUP,
9338                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9339                                                   actions,
9340                                                   "action not supported");
9341                 switch (action_type) {
9342                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
9343                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
9344                         break;
9345                 case RTE_FLOW_ACTION_TYPE_VOID:
9346                         break;
9347                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
9348                         if (flow_dv_translate_action_port_id(dev, action,
9349                                                              &port_id, error))
9350                                 return -rte_errno;
9351                         port_id_resource.port_id = port_id;
9352                         MLX5_ASSERT(!handle->rix_port_id_action);
9353                         if (flow_dv_port_id_action_resource_register
9354                             (dev, &port_id_resource, dev_flow, error))
9355                                 return -rte_errno;
9356                         dev_flow->dv.actions[actions_n++] =
9357                                         dev_flow->dv.port_id_action->action;
9358                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9359                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
9360                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
9361                         num_of_dest++;
9362                         break;
9363                 case RTE_FLOW_ACTION_TYPE_FLAG:
9364                         action_flags |= MLX5_FLOW_ACTION_FLAG;
9365                         dev_flow->handle->mark = 1;
9366                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9367                                 struct rte_flow_action_mark mark = {
9368                                         .id = MLX5_FLOW_MARK_DEFAULT,
9369                                 };
9370
9371                                 if (flow_dv_convert_action_mark(dev, &mark,
9372                                                                 mhdr_res,
9373                                                                 error))
9374                                         return -rte_errno;
9375                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9376                                 break;
9377                         }
9378                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
9379                         /*
9380                          * Only one FLAG or MARK is supported per device flow
9381                          * right now. So the pointer to the tag resource must be
9382                          * zero before the register process.
9383                          */
9384                         MLX5_ASSERT(!handle->dvh.rix_tag);
9385                         if (flow_dv_tag_resource_register(dev, tag_be,
9386                                                           dev_flow, error))
9387                                 return -rte_errno;
9388                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9389                         dev_flow->dv.actions[actions_n++] =
9390                                         dev_flow->dv.tag_resource->action;
9391                         break;
9392                 case RTE_FLOW_ACTION_TYPE_MARK:
9393                         action_flags |= MLX5_FLOW_ACTION_MARK;
9394                         dev_flow->handle->mark = 1;
9395                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
9396                                 const struct rte_flow_action_mark *mark =
9397                                         (const struct rte_flow_action_mark *)
9398                                                 actions->conf;
9399
9400                                 if (flow_dv_convert_action_mark(dev, mark,
9401                                                                 mhdr_res,
9402                                                                 error))
9403                                         return -rte_errno;
9404                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
9405                                 break;
9406                         }
9407                         /* Fall-through */
9408                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
9409                         /* Legacy (non-extensive) MARK action. */
9410                         tag_be = mlx5_flow_mark_set
9411                               (((const struct rte_flow_action_mark *)
9412                                (actions->conf))->id);
9413                         MLX5_ASSERT(!handle->dvh.rix_tag);
9414                         if (flow_dv_tag_resource_register(dev, tag_be,
9415                                                           dev_flow, error))
9416                                 return -rte_errno;
9417                         MLX5_ASSERT(dev_flow->dv.tag_resource);
9418                         dev_flow->dv.actions[actions_n++] =
9419                                         dev_flow->dv.tag_resource->action;
9420                         break;
9421                 case RTE_FLOW_ACTION_TYPE_SET_META:
9422                         if (flow_dv_convert_action_set_meta
9423                                 (dev, mhdr_res, attr,
9424                                  (const struct rte_flow_action_set_meta *)
9425                                   actions->conf, error))
9426                                 return -rte_errno;
9427                         action_flags |= MLX5_FLOW_ACTION_SET_META;
9428                         break;
9429                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
9430                         if (flow_dv_convert_action_set_tag
9431                                 (dev, mhdr_res,
9432                                  (const struct rte_flow_action_set_tag *)
9433                                   actions->conf, error))
9434                                 return -rte_errno;
9435                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9436                         break;
9437                 case RTE_FLOW_ACTION_TYPE_DROP:
9438                         action_flags |= MLX5_FLOW_ACTION_DROP;
9439                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
9440                         break;
9441                 case RTE_FLOW_ACTION_TYPE_QUEUE:
9442                         queue = actions->conf;
9443                         rss_desc->queue_num = 1;
9444                         rss_desc->queue[0] = queue->index;
9445                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
9446                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9447                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
9448                         num_of_dest++;
9449                         break;
9450                 case RTE_FLOW_ACTION_TYPE_RSS:
9451                         rss = actions->conf;
9452                         memcpy(rss_desc->queue, rss->queue,
9453                                rss->queue_num * sizeof(uint16_t));
9454                         rss_desc->queue_num = rss->queue_num;
9455                         /* NULL RSS key indicates default RSS key. */
9456                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
9457                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
9458                         /*
9459                          * rss->level and rss.types should be set in advance
9460                          * when expanding items for RSS.
9461                          */
9462                         action_flags |= MLX5_FLOW_ACTION_RSS;
9463                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
9464                         break;
9465                 case RTE_FLOW_ACTION_TYPE_AGE:
9466                 case RTE_FLOW_ACTION_TYPE_COUNT:
9467                         if (!dev_conf->devx) {
9468                                 return rte_flow_error_set
9469                                               (error, ENOTSUP,
9470                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9471                                                NULL,
9472                                                "count action not supported");
9473                         }
9474                         /* Save information first, will apply later. */
9475                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
9476                                 count = action->conf;
9477                         else
9478                                 age = action->conf;
9479                         action_flags |= MLX5_FLOW_ACTION_COUNT;
9480                         break;
9481                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
9482                         dev_flow->dv.actions[actions_n++] =
9483                                                 priv->sh->pop_vlan_action;
9484                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
9485                         break;
9486                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
9487                         if (!(action_flags &
9488                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
9489                                 flow_dev_get_vlan_info_from_items(items, &vlan);
9490                         vlan.eth_proto = rte_be_to_cpu_16
9491                              ((((const struct rte_flow_action_of_push_vlan *)
9492                                                    actions->conf)->ethertype));
9493                         found_action = mlx5_flow_find_action
9494                                         (actions + 1,
9495                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
9496                         if (found_action)
9497                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9498                         found_action = mlx5_flow_find_action
9499                                         (actions + 1,
9500                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
9501                         if (found_action)
9502                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
9503                         if (flow_dv_create_action_push_vlan
9504                                             (dev, attr, &vlan, dev_flow, error))
9505                                 return -rte_errno;
9506                         dev_flow->dv.actions[actions_n++] =
9507                                         dev_flow->dv.push_vlan_res->action;
9508                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
9509                         break;
9510                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
9511                         /* of_vlan_push action handled this action */
9512                         MLX5_ASSERT(action_flags &
9513                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
9514                         break;
9515                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
9516                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
9517                                 break;
9518                         flow_dev_get_vlan_info_from_items(items, &vlan);
9519                         mlx5_update_vlan_vid_pcp(actions, &vlan);
9520                         /* If no VLAN push - this is a modify header action */
9521                         if (flow_dv_convert_action_modify_vlan_vid
9522                                                 (mhdr_res, actions, error))
9523                                 return -rte_errno;
9524                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
9525                         break;
9526                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
9527                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
9528                         if (flow_dv_create_action_l2_encap(dev, actions,
9529                                                            dev_flow,
9530                                                            attr->transfer,
9531                                                            error))
9532                                 return -rte_errno;
9533                         dev_flow->dv.actions[actions_n++] =
9534                                         dev_flow->dv.encap_decap->action;
9535                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9536                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9537                                 sample_act->action_flags |=
9538                                                         MLX5_FLOW_ACTION_ENCAP;
9539                         break;
9540                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
9541                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
9542                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
9543                                                            attr->transfer,
9544                                                            error))
9545                                 return -rte_errno;
9546                         dev_flow->dv.actions[actions_n++] =
9547                                         dev_flow->dv.encap_decap->action;
9548                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9549                         break;
9550                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
9551                         /* Handle encap with preceding decap. */
9552                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
9553                                 if (flow_dv_create_action_raw_encap
9554                                         (dev, actions, dev_flow, attr, error))
9555                                         return -rte_errno;
9556                                 dev_flow->dv.actions[actions_n++] =
9557                                         dev_flow->dv.encap_decap->action;
9558                         } else {
9559                                 /* Handle encap without preceding decap. */
9560                                 if (flow_dv_create_action_l2_encap
9561                                     (dev, actions, dev_flow, attr->transfer,
9562                                      error))
9563                                         return -rte_errno;
9564                                 dev_flow->dv.actions[actions_n++] =
9565                                         dev_flow->dv.encap_decap->action;
9566                         }
9567                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
9568                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
9569                                 sample_act->action_flags |=
9570                                                         MLX5_FLOW_ACTION_ENCAP;
9571                         break;
9572                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
9573                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
9574                                 ;
9575                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
9576                                 if (flow_dv_create_action_l2_decap
9577                                     (dev, dev_flow, attr->transfer, error))
9578                                         return -rte_errno;
9579                                 dev_flow->dv.actions[actions_n++] =
9580                                         dev_flow->dv.encap_decap->action;
9581                         }
9582                         /* If decap is followed by encap, handle it at encap. */
9583                         action_flags |= MLX5_FLOW_ACTION_DECAP;
9584                         break;
9585                 case RTE_FLOW_ACTION_TYPE_JUMP:
9586                         jump_group = ((const struct rte_flow_action_jump *)
9587                                                         action->conf)->group;
9588                         grp_info.std_tbl_fix = 0;
9589                         ret = mlx5_flow_group_to_table(dev, tunnel,
9590                                                        jump_group,
9591                                                        &table,
9592                                                        grp_info, error);
9593                         if (ret)
9594                                 return ret;
9595                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
9596                                                        attr->transfer,
9597                                                        !!dev_flow->external,
9598                                                        tunnel, jump_group, 0,
9599                                                        error);
9600                         if (!tbl)
9601                                 return rte_flow_error_set
9602                                                 (error, errno,
9603                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9604                                                  NULL,
9605                                                  "cannot create jump action.");
9606                         if (flow_dv_jump_tbl_resource_register
9607                             (dev, tbl, dev_flow, error)) {
9608                                 flow_dv_tbl_resource_release(dev, tbl);
9609                                 return rte_flow_error_set
9610                                                 (error, errno,
9611                                                  RTE_FLOW_ERROR_TYPE_ACTION,
9612                                                  NULL,
9613                                                  "cannot create jump action.");
9614                         }
9615                         dev_flow->dv.actions[actions_n++] =
9616                                         dev_flow->dv.jump->action;
9617                         action_flags |= MLX5_FLOW_ACTION_JUMP;
9618                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
9619                         break;
9620                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
9621                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
9622                         if (flow_dv_convert_action_modify_mac
9623                                         (mhdr_res, actions, error))
9624                                 return -rte_errno;
9625                         action_flags |= actions->type ==
9626                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
9627                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
9628                                         MLX5_FLOW_ACTION_SET_MAC_DST;
9629                         break;
9630                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
9631                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
9632                         if (flow_dv_convert_action_modify_ipv4
9633                                         (mhdr_res, actions, error))
9634                                 return -rte_errno;
9635                         action_flags |= actions->type ==
9636                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
9637                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
9638                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
9639                         break;
9640                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
9641                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
9642                         if (flow_dv_convert_action_modify_ipv6
9643                                         (mhdr_res, actions, error))
9644                                 return -rte_errno;
9645                         action_flags |= actions->type ==
9646                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
9647                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
9648                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
9649                         break;
9650                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
9651                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
9652                         if (flow_dv_convert_action_modify_tp
9653                                         (mhdr_res, actions, items,
9654                                          &flow_attr, dev_flow, !!(action_flags &
9655                                          MLX5_FLOW_ACTION_DECAP), error))
9656                                 return -rte_errno;
9657                         action_flags |= actions->type ==
9658                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
9659                                         MLX5_FLOW_ACTION_SET_TP_SRC :
9660                                         MLX5_FLOW_ACTION_SET_TP_DST;
9661                         break;
9662                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
9663                         if (flow_dv_convert_action_modify_dec_ttl
9664                                         (mhdr_res, items, &flow_attr, dev_flow,
9665                                          !!(action_flags &
9666                                          MLX5_FLOW_ACTION_DECAP), error))
9667                                 return -rte_errno;
9668                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
9669                         break;
9670                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
9671                         if (flow_dv_convert_action_modify_ttl
9672                                         (mhdr_res, actions, items, &flow_attr,
9673                                          dev_flow, !!(action_flags &
9674                                          MLX5_FLOW_ACTION_DECAP), error))
9675                                 return -rte_errno;
9676                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
9677                         break;
9678                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
9679                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
9680                         if (flow_dv_convert_action_modify_tcp_seq
9681                                         (mhdr_res, actions, error))
9682                                 return -rte_errno;
9683                         action_flags |= actions->type ==
9684                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
9685                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
9686                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
9687                         break;
9688
9689                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
9690                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
9691                         if (flow_dv_convert_action_modify_tcp_ack
9692                                         (mhdr_res, actions, error))
9693                                 return -rte_errno;
9694                         action_flags |= actions->type ==
9695                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
9696                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
9697                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
9698                         break;
9699                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
9700                         if (flow_dv_convert_action_set_reg
9701                                         (mhdr_res, actions, error))
9702                                 return -rte_errno;
9703                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9704                         break;
9705                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
9706                         if (flow_dv_convert_action_copy_mreg
9707                                         (dev, mhdr_res, actions, error))
9708                                 return -rte_errno;
9709                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
9710                         break;
9711                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
9712                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
9713                         dev_flow->handle->fate_action =
9714                                         MLX5_FLOW_FATE_DEFAULT_MISS;
9715                         break;
9716                 case RTE_FLOW_ACTION_TYPE_METER:
9717                         mtr = actions->conf;
9718                         if (!flow->meter) {
9719                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
9720                                                             attr, error);
9721                                 if (!fm)
9722                                         return rte_flow_error_set(error,
9723                                                 rte_errno,
9724                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9725                                                 NULL,
9726                                                 "meter not found "
9727                                                 "or invalid parameters");
9728                                 flow->meter = fm->idx;
9729                         }
9730                         /* Set the meter action. */
9731                         if (!fm) {
9732                                 fm = mlx5_ipool_get(priv->sh->ipool
9733                                                 [MLX5_IPOOL_MTR], flow->meter);
9734                                 if (!fm)
9735                                         return rte_flow_error_set(error,
9736                                                 rte_errno,
9737                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9738                                                 NULL,
9739                                                 "meter not found "
9740                                                 "or invalid parameters");
9741                         }
9742                         dev_flow->dv.actions[actions_n++] =
9743                                 fm->mfts->meter_action;
9744                         action_flags |= MLX5_FLOW_ACTION_METER;
9745                         break;
9746                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
9747                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
9748                                                               actions, error))
9749                                 return -rte_errno;
9750                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
9751                         break;
9752                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
9753                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
9754                                                               actions, error))
9755                                 return -rte_errno;
9756                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
9757                         break;
9758                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
9759                         sample_act_pos = actions_n;
9760                         ret = flow_dv_translate_action_sample(dev,
9761                                                               actions,
9762                                                               dev_flow, attr,
9763                                                               &num_of_dest,
9764                                                               sample_actions,
9765                                                               &sample_res,
9766                                                               error);
9767                         if (ret < 0)
9768                                 return ret;
9769                         actions_n++;
9770                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
9771                         /* put encap action into group if work with port id */
9772                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
9773                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
9774                                 sample_act->action_flags |=
9775                                                         MLX5_FLOW_ACTION_ENCAP;
9776                         break;
9777                 case RTE_FLOW_ACTION_TYPE_END:
9778                         actions_end = true;
9779                         if (mhdr_res->actions_num) {
9780                                 /* create modify action if needed. */
9781                                 if (flow_dv_modify_hdr_resource_register
9782                                         (dev, mhdr_res, dev_flow, error))
9783                                         return -rte_errno;
9784                                 dev_flow->dv.actions[modify_action_position] =
9785                                         handle->dvh.modify_hdr->action;
9786                         }
9787                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
9788                                 flow->counter =
9789                                         flow_dv_translate_create_counter(dev,
9790                                                 dev_flow, count, age);
9791
9792                                 if (!flow->counter)
9793                                         return rte_flow_error_set
9794                                                 (error, rte_errno,
9795                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9796                                                 NULL,
9797                                                 "cannot create counter"
9798                                                 " object.");
9799                                 dev_flow->dv.actions[actions_n] =
9800                                           (flow_dv_counter_get_by_idx(dev,
9801                                           flow->counter, NULL))->action;
9802                                 actions_n++;
9803                         }
9804                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
9805                                 ret = flow_dv_create_action_sample(dev,
9806                                                           dev_flow, attr,
9807                                                           num_of_dest,
9808                                                           &sample_res,
9809                                                           &mdest_res,
9810                                                           sample_actions,
9811                                                           action_flags,
9812                                                           error);
9813                                 if (ret < 0)
9814                                         return rte_flow_error_set
9815                                                 (error, rte_errno,
9816                                                 RTE_FLOW_ERROR_TYPE_ACTION,
9817                                                 NULL,
9818                                                 "cannot create sample action");
9819                                 if (num_of_dest > 1) {
9820                                         dev_flow->dv.actions[sample_act_pos] =
9821                                         dev_flow->dv.dest_array_res->action;
9822                                 } else {
9823                                         dev_flow->dv.actions[sample_act_pos] =
9824                                         dev_flow->dv.sample_res->verbs_action;
9825                                 }
9826                         }
9827                         break;
9828                 default:
9829                         break;
9830                 }
9831                 if (mhdr_res->actions_num &&
9832                     modify_action_position == UINT32_MAX)
9833                         modify_action_position = actions_n++;
9834         }
9835         /*
9836          * For multiple destination (sample action with ratio=1), the encap
9837          * action and port id action will be combined into group action.
9838          * So need remove the original these actions in the flow and only
9839          * use the sample action instead of.
9840          */
9841         if (num_of_dest > 1 && sample_act->dr_port_id_action) {
9842                 int i;
9843                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
9844
9845                 for (i = 0; i < actions_n; i++) {
9846                         if ((sample_act->dr_encap_action &&
9847                                 sample_act->dr_encap_action ==
9848                                 dev_flow->dv.actions[i]) ||
9849                                 (sample_act->dr_port_id_action &&
9850                                 sample_act->dr_port_id_action ==
9851                                 dev_flow->dv.actions[i]))
9852                                 continue;
9853                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
9854                 }
9855                 memcpy((void *)dev_flow->dv.actions,
9856                                 (void *)temp_actions,
9857                                 tmp_actions_n * sizeof(void *));
9858                 actions_n = tmp_actions_n;
9859         }
9860         dev_flow->dv.actions_n = actions_n;
9861         dev_flow->act_flags = action_flags;
9862         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
9863                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
9864                 int item_type = items->type;
9865
9866                 if (!mlx5_flow_os_item_supported(item_type))
9867                         return rte_flow_error_set(error, ENOTSUP,
9868                                                   RTE_FLOW_ERROR_TYPE_ITEM,
9869                                                   NULL, "item not supported");
9870                 switch (item_type) {
9871                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
9872                         flow_dv_translate_item_port_id(dev, match_mask,
9873                                                        match_value, items);
9874                         last_item = MLX5_FLOW_ITEM_PORT_ID;
9875                         break;
9876                 case RTE_FLOW_ITEM_TYPE_ETH:
9877                         flow_dv_translate_item_eth(match_mask, match_value,
9878                                                    items, tunnel,
9879                                                    dev_flow->dv.group);
9880                         matcher.priority = action_flags &
9881                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
9882                                         !dev_flow->external ?
9883                                         MLX5_PRIORITY_MAP_L3 :
9884                                         MLX5_PRIORITY_MAP_L2;
9885                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
9886                                              MLX5_FLOW_LAYER_OUTER_L2;
9887                         break;
9888                 case RTE_FLOW_ITEM_TYPE_VLAN:
9889                         flow_dv_translate_item_vlan(dev_flow,
9890                                                     match_mask, match_value,
9891                                                     items, tunnel,
9892                                                     dev_flow->dv.group);
9893                         matcher.priority = MLX5_PRIORITY_MAP_L2;
9894                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
9895                                               MLX5_FLOW_LAYER_INNER_VLAN) :
9896                                              (MLX5_FLOW_LAYER_OUTER_L2 |
9897                                               MLX5_FLOW_LAYER_OUTER_VLAN);
9898                         break;
9899                 case RTE_FLOW_ITEM_TYPE_IPV4:
9900                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9901                                                   &item_flags, &tunnel);
9902                         flow_dv_translate_item_ipv4(match_mask, match_value,
9903                                                     items, tunnel,
9904                                                     dev_flow->dv.group);
9905                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9906                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
9907                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
9908                         if (items->mask != NULL &&
9909                             ((const struct rte_flow_item_ipv4 *)
9910                              items->mask)->hdr.next_proto_id) {
9911                                 next_protocol =
9912                                         ((const struct rte_flow_item_ipv4 *)
9913                                          (items->spec))->hdr.next_proto_id;
9914                                 next_protocol &=
9915                                         ((const struct rte_flow_item_ipv4 *)
9916                                          (items->mask))->hdr.next_proto_id;
9917                         } else {
9918                                 /* Reset for inner layer. */
9919                                 next_protocol = 0xff;
9920                         }
9921                         break;
9922                 case RTE_FLOW_ITEM_TYPE_IPV6:
9923                         mlx5_flow_tunnel_ip_check(items, next_protocol,
9924                                                   &item_flags, &tunnel);
9925                         flow_dv_translate_item_ipv6(match_mask, match_value,
9926                                                     items, tunnel,
9927                                                     dev_flow->dv.group);
9928                         matcher.priority = MLX5_PRIORITY_MAP_L3;
9929                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
9930                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
9931                         if (items->mask != NULL &&
9932                             ((const struct rte_flow_item_ipv6 *)
9933                              items->mask)->hdr.proto) {
9934                                 next_protocol =
9935                                         ((const struct rte_flow_item_ipv6 *)
9936                                          items->spec)->hdr.proto;
9937                                 next_protocol &=
9938                                         ((const struct rte_flow_item_ipv6 *)
9939                                          items->mask)->hdr.proto;
9940                         } else {
9941                                 /* Reset for inner layer. */
9942                                 next_protocol = 0xff;
9943                         }
9944                         break;
9945                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
9946                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
9947                                                              match_value,
9948                                                              items, tunnel);
9949                         last_item = tunnel ?
9950                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
9951                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
9952                         if (items->mask != NULL &&
9953                             ((const struct rte_flow_item_ipv6_frag_ext *)
9954                              items->mask)->hdr.next_header) {
9955                                 next_protocol =
9956                                 ((const struct rte_flow_item_ipv6_frag_ext *)
9957                                  items->spec)->hdr.next_header;
9958                                 next_protocol &=
9959                                 ((const struct rte_flow_item_ipv6_frag_ext *)
9960                                  items->mask)->hdr.next_header;
9961                         } else {
9962                                 /* Reset for inner layer. */
9963                                 next_protocol = 0xff;
9964                         }
9965                         break;
9966                 case RTE_FLOW_ITEM_TYPE_TCP:
9967                         flow_dv_translate_item_tcp(match_mask, match_value,
9968                                                    items, tunnel);
9969                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9970                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
9971                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
9972                         break;
9973                 case RTE_FLOW_ITEM_TYPE_UDP:
9974                         flow_dv_translate_item_udp(match_mask, match_value,
9975                                                    items, tunnel);
9976                         matcher.priority = MLX5_PRIORITY_MAP_L4;
9977                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
9978                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
9979                         break;
9980                 case RTE_FLOW_ITEM_TYPE_GRE:
9981                         flow_dv_translate_item_gre(match_mask, match_value,
9982                                                    items, tunnel);
9983                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9984                         last_item = MLX5_FLOW_LAYER_GRE;
9985                         break;
9986                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
9987                         flow_dv_translate_item_gre_key(match_mask,
9988                                                        match_value, items);
9989                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
9990                         break;
9991                 case RTE_FLOW_ITEM_TYPE_NVGRE:
9992                         flow_dv_translate_item_nvgre(match_mask, match_value,
9993                                                      items, tunnel);
9994                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
9995                         last_item = MLX5_FLOW_LAYER_GRE;
9996                         break;
9997                 case RTE_FLOW_ITEM_TYPE_VXLAN:
9998                         flow_dv_translate_item_vxlan(match_mask, match_value,
9999                                                      items, tunnel);
10000                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10001                         last_item = MLX5_FLOW_LAYER_VXLAN;
10002                         break;
10003                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
10004                         flow_dv_translate_item_vxlan_gpe(match_mask,
10005                                                          match_value, items,
10006                                                          tunnel);
10007                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10008                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
10009                         break;
10010                 case RTE_FLOW_ITEM_TYPE_GENEVE:
10011                         flow_dv_translate_item_geneve(match_mask, match_value,
10012                                                       items, tunnel);
10013                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10014                         last_item = MLX5_FLOW_LAYER_GENEVE;
10015                         break;
10016                 case RTE_FLOW_ITEM_TYPE_MPLS:
10017                         flow_dv_translate_item_mpls(match_mask, match_value,
10018                                                     items, last_item, tunnel);
10019                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10020                         last_item = MLX5_FLOW_LAYER_MPLS;
10021                         break;
10022                 case RTE_FLOW_ITEM_TYPE_MARK:
10023                         flow_dv_translate_item_mark(dev, match_mask,
10024                                                     match_value, items);
10025                         last_item = MLX5_FLOW_ITEM_MARK;
10026                         break;
10027                 case RTE_FLOW_ITEM_TYPE_META:
10028                         flow_dv_translate_item_meta(dev, match_mask,
10029                                                     match_value, attr, items);
10030                         last_item = MLX5_FLOW_ITEM_METADATA;
10031                         break;
10032                 case RTE_FLOW_ITEM_TYPE_ICMP:
10033                         flow_dv_translate_item_icmp(match_mask, match_value,
10034                                                     items, tunnel);
10035                         last_item = MLX5_FLOW_LAYER_ICMP;
10036                         break;
10037                 case RTE_FLOW_ITEM_TYPE_ICMP6:
10038                         flow_dv_translate_item_icmp6(match_mask, match_value,
10039                                                       items, tunnel);
10040                         last_item = MLX5_FLOW_LAYER_ICMP6;
10041                         break;
10042                 case RTE_FLOW_ITEM_TYPE_TAG:
10043                         flow_dv_translate_item_tag(dev, match_mask,
10044                                                    match_value, items);
10045                         last_item = MLX5_FLOW_ITEM_TAG;
10046                         break;
10047                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
10048                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
10049                                                         match_value, items);
10050                         last_item = MLX5_FLOW_ITEM_TAG;
10051                         break;
10052                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
10053                         flow_dv_translate_item_tx_queue(dev, match_mask,
10054                                                         match_value,
10055                                                         items);
10056                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
10057                         break;
10058                 case RTE_FLOW_ITEM_TYPE_GTP:
10059                         flow_dv_translate_item_gtp(match_mask, match_value,
10060                                                    items, tunnel);
10061                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
10062                         last_item = MLX5_FLOW_LAYER_GTP;
10063                         break;
10064                 case RTE_FLOW_ITEM_TYPE_ECPRI:
10065                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
10066                                 /* Create it only the first time to be used. */
10067                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
10068                                 if (ret)
10069                                         return rte_flow_error_set
10070                                                 (error, -ret,
10071                                                 RTE_FLOW_ERROR_TYPE_ITEM,
10072                                                 NULL,
10073                                                 "cannot create eCPRI parser");
10074                         }
10075                         /* Adjust the length matcher and device flow value. */
10076                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
10077                         dev_flow->dv.value.size =
10078                                         MLX5_ST_SZ_BYTES(fte_match_param);
10079                         flow_dv_translate_item_ecpri(dev, match_mask,
10080                                                      match_value, items);
10081                         /* No other protocol should follow eCPRI layer. */
10082                         last_item = MLX5_FLOW_LAYER_ECPRI;
10083                         break;
10084                 default:
10085                         break;
10086                 }
10087                 item_flags |= last_item;
10088         }
10089         /*
10090          * When E-Switch mode is enabled, we have two cases where we need to
10091          * set the source port manually.
10092          * The first one, is in case of Nic steering rule, and the second is
10093          * E-Switch rule where no port_id item was found. In both cases
10094          * the source port is set according the current port in use.
10095          */
10096         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
10097             (priv->representor || priv->master)) {
10098                 if (flow_dv_translate_item_port_id(dev, match_mask,
10099                                                    match_value, NULL))
10100                         return -rte_errno;
10101         }
10102 #ifdef RTE_LIBRTE_MLX5_DEBUG
10103         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
10104                                               dev_flow->dv.value.buf));
10105 #endif
10106         /*
10107          * Layers may be already initialized from prefix flow if this dev_flow
10108          * is the suffix flow.
10109          */
10110         handle->layers |= item_flags;
10111         if (action_flags & MLX5_FLOW_ACTION_RSS)
10112                 flow_dv_hashfields_set(dev_flow, rss_desc);
10113         /* Register matcher. */
10114         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
10115                                     matcher.mask.size);
10116         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
10117                                                      matcher.priority);
10118         /* reserved field no needs to be set to 0 here. */
10119         tbl_key.domain = attr->transfer;
10120         tbl_key.direction = attr->egress;
10121         tbl_key.table_id = dev_flow->dv.group;
10122         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
10123                 return -rte_errno;
10124         return 0;
10125 }
10126
10127 /**
10128  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10129  * and tunnel.
10130  *
10131  * @param[in, out] action
10132  *   Shred RSS action holding hash RX queue objects.
10133  * @param[in] hash_fields
10134  *   Defines combination of packet fields to participate in RX hash.
10135  * @param[in] tunnel
10136  *   Tunnel type
10137  * @param[in] hrxq_idx
10138  *   Hash RX queue index to set.
10139  *
10140  * @return
10141  *   0 on success, otherwise negative errno value.
10142  */
10143 static int
10144 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
10145                               const uint64_t hash_fields,
10146                               const int tunnel,
10147                               uint32_t hrxq_idx)
10148 {
10149         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10150
10151         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10152         case MLX5_RSS_HASH_IPV4:
10153                 hrxqs[0] = hrxq_idx;
10154                 return 0;
10155         case MLX5_RSS_HASH_IPV4_TCP:
10156                 hrxqs[1] = hrxq_idx;
10157                 return 0;
10158         case MLX5_RSS_HASH_IPV4_UDP:
10159                 hrxqs[2] = hrxq_idx;
10160                 return 0;
10161         case MLX5_RSS_HASH_IPV6:
10162                 hrxqs[3] = hrxq_idx;
10163                 return 0;
10164         case MLX5_RSS_HASH_IPV6_TCP:
10165                 hrxqs[4] = hrxq_idx;
10166                 return 0;
10167         case MLX5_RSS_HASH_IPV6_UDP:
10168                 hrxqs[5] = hrxq_idx;
10169                 return 0;
10170         case MLX5_RSS_HASH_NONE:
10171                 hrxqs[6] = hrxq_idx;
10172                 return 0;
10173         default:
10174                 return -1;
10175         }
10176 }
10177
10178 /**
10179  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
10180  * and tunnel.
10181  *
10182  * @param[in] action
10183  *   Shred RSS action holding hash RX queue objects.
10184  * @param[in] hash_fields
10185  *   Defines combination of packet fields to participate in RX hash.
10186  * @param[in] tunnel
10187  *   Tunnel type
10188  *
10189  * @return
10190  *   Valid hash RX queue index, otherwise 0.
10191  */
10192 static uint32_t
10193 __flow_dv_action_rss_hrxq_lookup(const struct mlx5_shared_action_rss *action,
10194                                  const uint64_t hash_fields,
10195                                  const int tunnel)
10196 {
10197         const uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
10198
10199         switch (hash_fields & ~IBV_RX_HASH_INNER) {
10200         case MLX5_RSS_HASH_IPV4:
10201                 return hrxqs[0];
10202         case MLX5_RSS_HASH_IPV4_TCP:
10203                 return hrxqs[1];
10204         case MLX5_RSS_HASH_IPV4_UDP:
10205                 return hrxqs[2];
10206         case MLX5_RSS_HASH_IPV6:
10207                 return hrxqs[3];
10208         case MLX5_RSS_HASH_IPV6_TCP:
10209                 return hrxqs[4];
10210         case MLX5_RSS_HASH_IPV6_UDP:
10211                 return hrxqs[5];
10212         case MLX5_RSS_HASH_NONE:
10213                 return hrxqs[6];
10214         default:
10215                 return 0;
10216         }
10217 }
10218
10219 /**
10220  * Retrieves hash RX queue suitable for the *flow*.
10221  * If shared action configured for *flow* suitable hash RX queue will be
10222  * retrieved from attached shared action.
10223  *
10224  * @param[in] flow
10225  *   Shred RSS action holding hash RX queue objects.
10226  * @param[in] dev_flow
10227  *   Pointer to the sub flow.
10228  * @param[out] hrxq
10229  *   Pointer to retrieved hash RX queue object.
10230  *
10231  * @return
10232  *   Valid hash RX queue index, otherwise 0 and rte_errno is set.
10233  */
10234 static uint32_t
10235 __flow_dv_rss_get_hrxq(struct rte_eth_dev *dev, struct rte_flow *flow,
10236                            struct mlx5_flow *dev_flow,
10237                            struct mlx5_hrxq **hrxq)
10238 {
10239         struct mlx5_priv *priv = dev->data->dev_private;
10240         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10241         uint32_t hrxq_idx;
10242
10243         if (flow->shared_rss) {
10244                 hrxq_idx = __flow_dv_action_rss_hrxq_lookup
10245                                 (flow->shared_rss, dev_flow->hash_fields,
10246                                  !!(dev_flow->handle->layers &
10247                                     MLX5_FLOW_LAYER_TUNNEL));
10248                 if (hrxq_idx) {
10249                         *hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
10250                                                hrxq_idx);
10251                         __atomic_fetch_add(&(*hrxq)->refcnt, 1,
10252                                            __ATOMIC_RELAXED);
10253                 }
10254         } else {
10255                 struct mlx5_flow_rss_desc *rss_desc =
10256                                 &wks->rss_desc[!!wks->flow_nested_idx];
10257
10258                 *hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
10259                                              &hrxq_idx);
10260         }
10261         return hrxq_idx;
10262 }
10263
10264 /**
10265  * Apply the flow to the NIC, lock free,
10266  * (mutex should be acquired by caller).
10267  *
10268  * @param[in] dev
10269  *   Pointer to the Ethernet device structure.
10270  * @param[in, out] flow
10271  *   Pointer to flow structure.
10272  * @param[out] error
10273  *   Pointer to error structure.
10274  *
10275  * @return
10276  *   0 on success, a negative errno value otherwise and rte_errno is set.
10277  */
10278 static int
10279 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
10280                 struct rte_flow_error *error)
10281 {
10282         struct mlx5_flow_dv_workspace *dv;
10283         struct mlx5_flow_handle *dh;
10284         struct mlx5_flow_handle_dv *dv_h;
10285         struct mlx5_flow *dev_flow;
10286         struct mlx5_priv *priv = dev->data->dev_private;
10287         uint32_t handle_idx;
10288         int n;
10289         int err;
10290         int idx;
10291         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10292
10293         MLX5_ASSERT(wks);
10294         for (idx = wks->flow_idx - 1; idx >= wks->flow_nested_idx; idx--) {
10295                 dev_flow = &wks->flows[idx];
10296                 dv = &dev_flow->dv;
10297                 dh = dev_flow->handle;
10298                 dv_h = &dh->dvh;
10299                 n = dv->actions_n;
10300                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
10301                         if (dv->transfer) {
10302                                 dv->actions[n++] = priv->sh->esw_drop_action;
10303                         } else {
10304                                 MLX5_ASSERT(priv->drop_queue.hrxq);
10305                                 dv->actions[n++] =
10306                                                 priv->drop_queue.hrxq->action;
10307                         }
10308                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
10309                            !dv_h->rix_sample && !dv_h->rix_dest_array) {
10310                         struct mlx5_hrxq *hrxq = NULL;
10311                         uint32_t hrxq_idx = __flow_dv_rss_get_hrxq
10312                                                 (dev, flow, dev_flow, &hrxq);
10313                         if (!hrxq) {
10314                                 rte_flow_error_set
10315                                         (error, rte_errno,
10316                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10317                                          "cannot get hash queue");
10318                                 goto error;
10319                         }
10320                         dh->rix_hrxq = hrxq_idx;
10321                         dv->actions[n++] = hrxq->action;
10322                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
10323                         if (!priv->sh->default_miss_action) {
10324                                 rte_flow_error_set
10325                                         (error, rte_errno,
10326                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10327                                          "default miss action not be created.");
10328                                 goto error;
10329                         }
10330                         dv->actions[n++] = priv->sh->default_miss_action;
10331                 }
10332                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
10333                                                (void *)&dv->value, n,
10334                                                dv->actions, &dh->drv_flow);
10335                 if (err) {
10336                         rte_flow_error_set(error, errno,
10337                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10338                                            NULL,
10339                                            "hardware refuses to create flow");
10340                         goto error;
10341                 }
10342                 if (priv->vmwa_context &&
10343                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
10344                         /*
10345                          * The rule contains the VLAN pattern.
10346                          * For VF we are going to create VLAN
10347                          * interface to make hypervisor set correct
10348                          * e-Switch vport context.
10349                          */
10350                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
10351                 }
10352         }
10353         return 0;
10354 error:
10355         err = rte_errno; /* Save rte_errno before cleanup. */
10356         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
10357                        handle_idx, dh, next) {
10358                 /* hrxq is union, don't clear it if the flag is not set. */
10359                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
10360                         mlx5_hrxq_release(dev, dh->rix_hrxq);
10361                         dh->rix_hrxq = 0;
10362                 }
10363                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10364                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10365         }
10366         rte_errno = err; /* Restore rte_errno. */
10367         return -rte_errno;
10368 }
10369
10370 /**
10371  * Release the flow matcher.
10372  *
10373  * @param dev
10374  *   Pointer to Ethernet device.
10375  * @param handle
10376  *   Pointer to mlx5_flow_handle.
10377  *
10378  * @return
10379  *   1 while a reference on it exists, 0 when freed.
10380  */
10381 static int
10382 flow_dv_matcher_release(struct rte_eth_dev *dev,
10383                         struct mlx5_flow_handle *handle)
10384 {
10385         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
10386
10387         MLX5_ASSERT(matcher->matcher_object);
10388         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
10389                 dev->data->port_id, (void *)matcher,
10390                 __atomic_load_n(&matcher->refcnt, __ATOMIC_RELAXED));
10391         if (__atomic_sub_fetch(&matcher->refcnt, 1, __ATOMIC_RELAXED) == 0) {
10392                 claim_zero(mlx5_flow_os_destroy_flow_matcher
10393                            (matcher->matcher_object));
10394                 LIST_REMOVE(matcher, next);
10395                 /* table ref-- in release interface. */
10396                 flow_dv_tbl_resource_release(dev, matcher->tbl);
10397                 mlx5_free(matcher);
10398                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
10399                         dev->data->port_id, (void *)matcher);
10400                 return 0;
10401         }
10402         return 1;
10403 }
10404
10405 /**
10406  * Release encap_decap resource.
10407  *
10408  * @param list
10409  *   Pointer to the hash list.
10410  * @param entry
10411  *   Pointer to exist resource entry object.
10412  */
10413 void
10414 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
10415                               struct mlx5_hlist_entry *entry)
10416 {
10417         struct mlx5_dev_ctx_shared *sh = list->ctx;
10418         struct mlx5_flow_dv_encap_decap_resource *res =
10419                 container_of(entry, typeof(*res), entry);
10420
10421         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10422         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
10423 }
10424
10425 /**
10426  * Release an encap/decap resource.
10427  *
10428  * @param dev
10429  *   Pointer to Ethernet device.
10430  * @param encap_decap_idx
10431  *   Index of encap decap resource.
10432  *
10433  * @return
10434  *   1 while a reference on it exists, 0 when freed.
10435  */
10436 static int
10437 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
10438                                      uint32_t encap_decap_idx)
10439 {
10440         struct mlx5_priv *priv = dev->data->dev_private;
10441         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
10442
10443         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
10444                                         encap_decap_idx);
10445         if (!cache_resource)
10446                 return 0;
10447         MLX5_ASSERT(cache_resource->action);
10448         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
10449                                      &cache_resource->entry);
10450 }
10451
10452 /**
10453  * Release an jump to table action resource.
10454  *
10455  * @param dev
10456  *   Pointer to Ethernet device.
10457  * @param handle
10458  *   Pointer to mlx5_flow_handle.
10459  *
10460  * @return
10461  *   1 while a reference on it exists, 0 when freed.
10462  */
10463 static int
10464 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
10465                                   struct mlx5_flow_handle *handle)
10466 {
10467         struct mlx5_priv *priv = dev->data->dev_private;
10468         struct mlx5_flow_tbl_data_entry *tbl_data;
10469
10470         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
10471                              handle->rix_jump);
10472         if (!tbl_data)
10473                 return 0;
10474         return flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
10475 }
10476
10477 void
10478 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
10479                          struct mlx5_hlist_entry *entry)
10480 {
10481         struct mlx5_flow_dv_modify_hdr_resource *res =
10482                 container_of(entry, typeof(*res), entry);
10483
10484         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
10485         mlx5_free(entry);
10486 }
10487
10488 /**
10489  * Release a modify-header resource.
10490  *
10491  * @param dev
10492  *   Pointer to Ethernet device.
10493  * @param handle
10494  *   Pointer to mlx5_flow_handle.
10495  *
10496  * @return
10497  *   1 while a reference on it exists, 0 when freed.
10498  */
10499 static int
10500 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
10501                                     struct mlx5_flow_handle *handle)
10502 {
10503         struct mlx5_priv *priv = dev->data->dev_private;
10504         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
10505
10506         MLX5_ASSERT(entry->action);
10507         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
10508 }
10509
10510 /**
10511  * Release port ID action resource.
10512  *
10513  * @param dev
10514  *   Pointer to Ethernet device.
10515  * @param handle
10516  *   Pointer to mlx5_flow_handle.
10517  *
10518  * @return
10519  *   1 while a reference on it exists, 0 when freed.
10520  */
10521 static int
10522 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
10523                                         uint32_t port_id)
10524 {
10525         struct mlx5_priv *priv = dev->data->dev_private;
10526         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
10527         uint32_t idx = port_id;
10528
10529         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10530                                         idx);
10531         if (!cache_resource)
10532                 return 0;
10533         MLX5_ASSERT(cache_resource->action);
10534         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
10535                 (void *)cache_resource,
10536                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10537         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10538                                __ATOMIC_RELAXED) == 0) {
10539                 claim_zero(mlx5_flow_os_destroy_flow_action
10540                                                 (cache_resource->action));
10541                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
10542                              &priv->sh->port_id_action_list, idx,
10543                              cache_resource, next);
10544                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
10545                 DRV_LOG(DEBUG, "port id action resource %p: removed",
10546                         (void *)cache_resource);
10547                 return 0;
10548         }
10549         return 1;
10550 }
10551
10552 /**
10553  * Release push vlan action resource.
10554  *
10555  * @param dev
10556  *   Pointer to Ethernet device.
10557  * @param handle
10558  *   Pointer to mlx5_flow_handle.
10559  *
10560  * @return
10561  *   1 while a reference on it exists, 0 when freed.
10562  */
10563 static int
10564 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
10565                                           struct mlx5_flow_handle *handle)
10566 {
10567         struct mlx5_priv *priv = dev->data->dev_private;
10568         uint32_t idx = handle->dvh.rix_push_vlan;
10569         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
10570
10571         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10572                                         idx);
10573         if (!cache_resource)
10574                 return 0;
10575         MLX5_ASSERT(cache_resource->action);
10576         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
10577                 (void *)cache_resource,
10578                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10579         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10580                                __ATOMIC_RELAXED) == 0) {
10581                 claim_zero(mlx5_flow_os_destroy_flow_action
10582                                                 (cache_resource->action));
10583                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
10584                              &priv->sh->push_vlan_action_list, idx,
10585                              cache_resource, next);
10586                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
10587                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
10588                         (void *)cache_resource);
10589                 return 0;
10590         }
10591         return 1;
10592 }
10593
10594 /**
10595  * Release the fate resource.
10596  *
10597  * @param dev
10598  *   Pointer to Ethernet device.
10599  * @param handle
10600  *   Pointer to mlx5_flow_handle.
10601  */
10602 static void
10603 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
10604                                struct mlx5_flow_handle *handle)
10605 {
10606         if (!handle->rix_fate)
10607                 return;
10608         switch (handle->fate_action) {
10609         case MLX5_FLOW_FATE_QUEUE:
10610                 mlx5_hrxq_release(dev, handle->rix_hrxq);
10611                 break;
10612         case MLX5_FLOW_FATE_JUMP:
10613                 flow_dv_jump_tbl_resource_release(dev, handle);
10614                 break;
10615         case MLX5_FLOW_FATE_PORT_ID:
10616                 flow_dv_port_id_action_resource_release(dev,
10617                                 handle->rix_port_id_action);
10618                 break;
10619         default:
10620                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
10621                 break;
10622         }
10623         handle->rix_fate = 0;
10624 }
10625
10626 /**
10627  * Release an sample resource.
10628  *
10629  * @param dev
10630  *   Pointer to Ethernet device.
10631  * @param handle
10632  *   Pointer to mlx5_flow_handle.
10633  *
10634  * @return
10635  *   1 while a reference on it exists, 0 when freed.
10636  */
10637 static int
10638 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
10639                                      struct mlx5_flow_handle *handle)
10640 {
10641         struct mlx5_priv *priv = dev->data->dev_private;
10642         uint32_t idx = handle->dvh.rix_sample;
10643         struct mlx5_flow_dv_sample_resource *cache_resource;
10644
10645         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10646                          idx);
10647         if (!cache_resource)
10648                 return 0;
10649         MLX5_ASSERT(cache_resource->verbs_action);
10650         DRV_LOG(DEBUG, "sample resource %p: refcnt %d--",
10651                 (void *)cache_resource,
10652                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10653         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10654                                __ATOMIC_RELAXED) == 0) {
10655                 if (cache_resource->verbs_action)
10656                         claim_zero(mlx5_glue->destroy_flow_action
10657                                         (cache_resource->verbs_action));
10658                 if (cache_resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
10659                         if (cache_resource->default_miss)
10660                                 claim_zero(mlx5_glue->destroy_flow_action
10661                                   (cache_resource->default_miss));
10662                 }
10663                 if (cache_resource->normal_path_tbl)
10664                         flow_dv_tbl_resource_release(dev,
10665                                 cache_resource->normal_path_tbl);
10666         }
10667         if (cache_resource->sample_idx.rix_hrxq &&
10668                 !mlx5_hrxq_release(dev,
10669                         cache_resource->sample_idx.rix_hrxq))
10670                 cache_resource->sample_idx.rix_hrxq = 0;
10671         if (cache_resource->sample_idx.rix_tag &&
10672                 !flow_dv_tag_release(dev,
10673                         cache_resource->sample_idx.rix_tag))
10674                 cache_resource->sample_idx.rix_tag = 0;
10675         if (cache_resource->sample_idx.cnt) {
10676                 flow_dv_counter_release(dev,
10677                         cache_resource->sample_idx.cnt);
10678                 cache_resource->sample_idx.cnt = 0;
10679         }
10680         if (!__atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED)) {
10681                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
10682                              &priv->sh->sample_action_list, idx,
10683                              cache_resource, next);
10684                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE], idx);
10685                 DRV_LOG(DEBUG, "sample resource %p: removed",
10686                         (void *)cache_resource);
10687                 return 0;
10688         }
10689         return 1;
10690 }
10691
10692 /**
10693  * Release an destination array resource.
10694  *
10695  * @param dev
10696  *   Pointer to Ethernet device.
10697  * @param handle
10698  *   Pointer to mlx5_flow_handle.
10699  *
10700  * @return
10701  *   1 while a reference on it exists, 0 when freed.
10702  */
10703 static int
10704 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
10705                                      struct mlx5_flow_handle *handle)
10706 {
10707         struct mlx5_priv *priv = dev->data->dev_private;
10708         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10709         struct mlx5_flow_sub_actions_idx *mdest_act_res;
10710         uint32_t idx = handle->dvh.rix_dest_array;
10711         uint32_t i = 0;
10712
10713         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10714                          idx);
10715         if (!cache_resource)
10716                 return 0;
10717         MLX5_ASSERT(cache_resource->action);
10718         DRV_LOG(DEBUG, "destination array resource %p: refcnt %d--",
10719                 (void *)cache_resource,
10720                 __atomic_load_n(&cache_resource->refcnt, __ATOMIC_RELAXED));
10721         if (__atomic_sub_fetch(&cache_resource->refcnt, 1,
10722                                __ATOMIC_RELAXED) == 0) {
10723                 if (cache_resource->action)
10724                         claim_zero(mlx5_glue->destroy_flow_action
10725                                                 (cache_resource->action));
10726                 for (; i < cache_resource->num_of_dest; i++) {
10727                         mdest_act_res = &cache_resource->sample_idx[i];
10728                         if (mdest_act_res->rix_hrxq) {
10729                                 mlx5_hrxq_release(dev,
10730                                         mdest_act_res->rix_hrxq);
10731                                 mdest_act_res->rix_hrxq = 0;
10732                         }
10733                         if (mdest_act_res->rix_encap_decap) {
10734                                 flow_dv_encap_decap_resource_release(dev,
10735                                         mdest_act_res->rix_encap_decap);
10736                                 mdest_act_res->rix_encap_decap = 0;
10737                         }
10738                         if (mdest_act_res->rix_port_id_action) {
10739                                 flow_dv_port_id_action_resource_release(dev,
10740                                         mdest_act_res->rix_port_id_action);
10741                                 mdest_act_res->rix_port_id_action = 0;
10742                         }
10743                         if (mdest_act_res->rix_tag) {
10744                                 flow_dv_tag_release(dev,
10745                                         mdest_act_res->rix_tag);
10746                                 mdest_act_res->rix_tag = 0;
10747                         }
10748                 }
10749                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10750                              &priv->sh->dest_array_list, idx,
10751                              cache_resource, next);
10752                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY], idx);
10753                 DRV_LOG(DEBUG, "destination array resource %p: removed",
10754                         (void *)cache_resource);
10755                 return 0;
10756         }
10757         return 1;
10758 }
10759
10760 /**
10761  * Remove the flow from the NIC but keeps it in memory.
10762  * Lock free, (mutex should be acquired by caller).
10763  *
10764  * @param[in] dev
10765  *   Pointer to Ethernet device.
10766  * @param[in, out] flow
10767  *   Pointer to flow structure.
10768  */
10769 static void
10770 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
10771 {
10772         struct mlx5_flow_handle *dh;
10773         uint32_t handle_idx;
10774         struct mlx5_priv *priv = dev->data->dev_private;
10775
10776         if (!flow)
10777                 return;
10778         handle_idx = flow->dev_handles;
10779         while (handle_idx) {
10780                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10781                                     handle_idx);
10782                 if (!dh)
10783                         return;
10784                 if (dh->drv_flow) {
10785                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
10786                         dh->drv_flow = NULL;
10787                 }
10788                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
10789                         flow_dv_fate_resource_release(dev, dh);
10790                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
10791                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
10792                 handle_idx = dh->next.next;
10793         }
10794 }
10795
10796 /**
10797  * Remove the flow from the NIC and the memory.
10798  * Lock free, (mutex should be acquired by caller).
10799  *
10800  * @param[in] dev
10801  *   Pointer to the Ethernet device structure.
10802  * @param[in, out] flow
10803  *   Pointer to flow structure.
10804  */
10805 static void
10806 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
10807 {
10808         struct rte_flow_shared_action *shared;
10809         struct mlx5_flow_handle *dev_handle;
10810         struct mlx5_priv *priv = dev->data->dev_private;
10811
10812         if (!flow)
10813                 return;
10814         __flow_dv_remove(dev, flow);
10815         shared = mlx5_flow_get_shared_rss(flow);
10816         if (shared)
10817                 __atomic_sub_fetch(&shared->refcnt, 1, __ATOMIC_RELAXED);
10818         if (flow->counter) {
10819                 flow_dv_counter_release(dev, flow->counter);
10820                 flow->counter = 0;
10821         }
10822         if (flow->meter) {
10823                 struct mlx5_flow_meter *fm;
10824
10825                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
10826                                     flow->meter);
10827                 if (fm)
10828                         mlx5_flow_meter_detach(fm);
10829                 flow->meter = 0;
10830         }
10831         while (flow->dev_handles) {
10832                 uint32_t tmp_idx = flow->dev_handles;
10833
10834                 dev_handle = mlx5_ipool_get(priv->sh->ipool
10835                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
10836                 if (!dev_handle)
10837                         return;
10838                 flow->dev_handles = dev_handle->next.next;
10839                 if (dev_handle->dvh.matcher)
10840                         flow_dv_matcher_release(dev, dev_handle);
10841                 if (dev_handle->dvh.rix_sample)
10842                         flow_dv_sample_resource_release(dev, dev_handle);
10843                 if (dev_handle->dvh.rix_dest_array)
10844                         flow_dv_dest_array_resource_release(dev, dev_handle);
10845                 if (dev_handle->dvh.rix_encap_decap)
10846                         flow_dv_encap_decap_resource_release(dev,
10847                                 dev_handle->dvh.rix_encap_decap);
10848                 if (dev_handle->dvh.modify_hdr)
10849                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
10850                 if (dev_handle->dvh.rix_push_vlan)
10851                         flow_dv_push_vlan_action_resource_release(dev,
10852                                                                   dev_handle);
10853                 if (dev_handle->dvh.rix_tag)
10854                         flow_dv_tag_release(dev,
10855                                             dev_handle->dvh.rix_tag);
10856                 flow_dv_fate_resource_release(dev, dev_handle);
10857                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
10858                            tmp_idx);
10859         }
10860 }
10861
10862 /**
10863  * Release array of hash RX queue objects.
10864  * Helper function.
10865  *
10866  * @param[in] dev
10867  *   Pointer to the Ethernet device structure.
10868  * @param[in, out] hrxqs
10869  *   Array of hash RX queue objects.
10870  *
10871  * @return
10872  *   Total number of references to hash RX queue objects in *hrxqs* array
10873  *   after this operation.
10874  */
10875 static int
10876 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
10877                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
10878 {
10879         size_t i;
10880         int remaining = 0;
10881
10882         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
10883                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
10884
10885                 if (!ret)
10886                         (*hrxqs)[i] = 0;
10887                 remaining += ret;
10888         }
10889         return remaining;
10890 }
10891
10892 /**
10893  * Release all hash RX queue objects representing shared RSS action.
10894  *
10895  * @param[in] dev
10896  *   Pointer to the Ethernet device structure.
10897  * @param[in, out] action
10898  *   Shared RSS action to remove hash RX queue objects from.
10899  *
10900  * @return
10901  *   Total number of references to hash RX queue objects stored in *action*
10902  *   after this operation.
10903  *   Expected to be 0 if no external references held.
10904  */
10905 static int
10906 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
10907                                  struct mlx5_shared_action_rss *action)
10908 {
10909         return __flow_dv_hrxqs_release(dev, &action->hrxq) +
10910                 __flow_dv_hrxqs_release(dev, &action->hrxq_tunnel);
10911 }
10912
10913 /**
10914  * Setup shared RSS action.
10915  * Prepare set of hash RX queue objects sufficient to handle all valid
10916  * hash_fields combinations (see enum ibv_rx_hash_fields).
10917  *
10918  * @param[in] dev
10919  *   Pointer to the Ethernet device structure.
10920  * @param[in, out] action
10921  *   Partially initialized shared RSS action.
10922  * @param[out] error
10923  *   Perform verbose error reporting if not NULL. Initialized in case of
10924  *   error only.
10925  *
10926  * @return
10927  *   0 on success, otherwise negative errno value.
10928  */
10929 static int
10930 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
10931                         struct mlx5_shared_action_rss *action,
10932                         struct rte_flow_error *error)
10933 {
10934         struct mlx5_flow_rss_desc rss_desc = { 0 };
10935         size_t i;
10936         int err;
10937
10938         memcpy(rss_desc.key, action->origin.key, MLX5_RSS_HASH_KEY_LEN);
10939         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
10940         rss_desc.const_q = action->origin.queue;
10941         rss_desc.queue_num = action->origin.queue_num;
10942         rss_desc.standalone = true;
10943         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
10944                 uint32_t hrxq_idx;
10945                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
10946                 int tunnel;
10947
10948                 for (tunnel = 0; tunnel < 2; tunnel++) {
10949                         rss_desc.tunnel = tunnel;
10950                         rss_desc.hash_fields = hash_fields;
10951                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
10952                         if (!hrxq_idx) {
10953                                 rte_flow_error_set
10954                                         (error, rte_errno,
10955                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
10956                                          "cannot get hash queue");
10957                                 goto error_hrxq_new;
10958                         }
10959                         err = __flow_dv_action_rss_hrxq_set
10960                                 (action, hash_fields, tunnel, hrxq_idx);
10961                         MLX5_ASSERT(!err);
10962                 }
10963         }
10964         return 0;
10965 error_hrxq_new:
10966         err = rte_errno;
10967         __flow_dv_action_rss_hrxqs_release(dev, action);
10968         rte_errno = err;
10969         return -rte_errno;
10970 }
10971
10972 /**
10973  * Create shared RSS action.
10974  *
10975  * @param[in] dev
10976  *   Pointer to the Ethernet device structure.
10977  * @param[in] conf
10978  *   Shared action configuration.
10979  * @param[in] rss
10980  *   RSS action specification used to create shared action.
10981  * @param[out] error
10982  *   Perform verbose error reporting if not NULL. Initialized in case of
10983  *   error only.
10984  *
10985  * @return
10986  *   A valid shared action handle in case of success, NULL otherwise and
10987  *   rte_errno is set.
10988  */
10989 static struct rte_flow_shared_action *
10990 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
10991                             const struct rte_flow_shared_action_conf *conf,
10992                             const struct rte_flow_action_rss *rss,
10993                             struct rte_flow_error *error)
10994 {
10995         struct rte_flow_shared_action *shared_action = NULL;
10996         void *queue = NULL;
10997         struct mlx5_shared_action_rss *shared_rss;
10998         struct rte_flow_action_rss *origin;
10999         const uint8_t *rss_key;
11000         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
11001
11002         RTE_SET_USED(conf);
11003         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11004                             0, SOCKET_ID_ANY);
11005         shared_action = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*shared_action), 0,
11006                                     SOCKET_ID_ANY);
11007         if (!shared_action || !queue) {
11008                 rte_flow_error_set(error, ENOMEM,
11009                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
11010                                    "cannot allocate resource memory");
11011                 goto error_rss_init;
11012         }
11013         shared_rss = &shared_action->rss;
11014         shared_rss->queue = queue;
11015         origin = &shared_rss->origin;
11016         origin->func = rss->func;
11017         origin->level = rss->level;
11018         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
11019         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
11020         /* NULL RSS key indicates default RSS key. */
11021         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11022         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11023         origin->key = &shared_rss->key[0];
11024         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
11025         memcpy(shared_rss->queue, rss->queue, queue_size);
11026         origin->queue = shared_rss->queue;
11027         origin->queue_num = rss->queue_num;
11028         if (__flow_dv_action_rss_setup(dev, shared_rss, error))
11029                 goto error_rss_init;
11030         shared_action->type = MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS;
11031         return shared_action;
11032 error_rss_init:
11033         mlx5_free(shared_action);
11034         mlx5_free(queue);
11035         return NULL;
11036 }
11037
11038 /**
11039  * Destroy the shared RSS action.
11040  * Release related hash RX queue objects.
11041  *
11042  * @param[in] dev
11043  *   Pointer to the Ethernet device structure.
11044  * @param[in] shared_rss
11045  *   The shared RSS action object to be removed.
11046  * @param[out] error
11047  *   Perform verbose error reporting if not NULL. Initialized in case of
11048  *   error only.
11049  *
11050  * @return
11051  *   0 on success, otherwise negative errno value.
11052  */
11053 static int
11054 __flow_dv_action_rss_release(struct rte_eth_dev *dev,
11055                          struct mlx5_shared_action_rss *shared_rss,
11056                          struct rte_flow_error *error)
11057 {
11058         struct rte_flow_shared_action *shared_action = NULL;
11059         uint32_t old_refcnt = 1;
11060         int remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
11061
11062         if (remaining) {
11063                 return rte_flow_error_set(error, ETOOMANYREFS,
11064                                           RTE_FLOW_ERROR_TYPE_ACTION,
11065                                           NULL,
11066                                           "shared rss hrxq has references");
11067         }
11068         shared_action = container_of(shared_rss,
11069                                      struct rte_flow_shared_action, rss);
11070         if (!__atomic_compare_exchange_n(&shared_action->refcnt, &old_refcnt,
11071                                          0, 0,
11072                                          __ATOMIC_ACQUIRE, __ATOMIC_RELAXED)) {
11073                 return rte_flow_error_set(error, ETOOMANYREFS,
11074                                           RTE_FLOW_ERROR_TYPE_ACTION,
11075                                           NULL,
11076                                           "shared rss has references");
11077         }
11078         rte_free(shared_rss->queue);
11079         return 0;
11080 }
11081
11082 /**
11083  * Create shared action, lock free,
11084  * (mutex should be acquired by caller).
11085  * Dispatcher for action type specific call.
11086  *
11087  * @param[in] dev
11088  *   Pointer to the Ethernet device structure.
11089  * @param[in] conf
11090  *   Shared action configuration.
11091  * @param[in] action
11092  *   Action specification used to create shared action.
11093  * @param[out] error
11094  *   Perform verbose error reporting if not NULL. Initialized in case of
11095  *   error only.
11096  *
11097  * @return
11098  *   A valid shared action handle in case of success, NULL otherwise and
11099  *   rte_errno is set.
11100  */
11101 static struct rte_flow_shared_action *
11102 __flow_dv_action_create(struct rte_eth_dev *dev,
11103                         const struct rte_flow_shared_action_conf *conf,
11104                         const struct rte_flow_action *action,
11105                         struct rte_flow_error *error)
11106 {
11107         struct rte_flow_shared_action *shared_action = NULL;
11108         struct mlx5_priv *priv = dev->data->dev_private;
11109
11110         switch (action->type) {
11111         case RTE_FLOW_ACTION_TYPE_RSS:
11112                 shared_action = __flow_dv_action_rss_create(dev, conf,
11113                                                             action->conf,
11114                                                             error);
11115                 break;
11116         default:
11117                 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
11118                                    NULL, "action type not supported");
11119                 break;
11120         }
11121         if (shared_action) {
11122                 __atomic_add_fetch(&shared_action->refcnt, 1,
11123                                    __ATOMIC_RELAXED);
11124                 LIST_INSERT_HEAD(&priv->shared_actions, shared_action, next);
11125         }
11126         return shared_action;
11127 }
11128
11129 /**
11130  * Destroy the shared action.
11131  * Release action related resources on the NIC and the memory.
11132  * Lock free, (mutex should be acquired by caller).
11133  * Dispatcher for action type specific call.
11134  *
11135  * @param[in] dev
11136  *   Pointer to the Ethernet device structure.
11137  * @param[in] action
11138  *   The shared action object to be removed.
11139  * @param[out] error
11140  *   Perform verbose error reporting if not NULL. Initialized in case of
11141  *   error only.
11142  *
11143  * @return
11144  *   0 on success, otherwise negative errno value.
11145  */
11146 static int
11147 __flow_dv_action_destroy(struct rte_eth_dev *dev,
11148                          struct rte_flow_shared_action *action,
11149                          struct rte_flow_error *error)
11150 {
11151         int ret;
11152
11153         switch (action->type) {
11154         case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11155                 ret = __flow_dv_action_rss_release(dev, &action->rss, error);
11156                 break;
11157         default:
11158                 return rte_flow_error_set(error, ENOTSUP,
11159                                           RTE_FLOW_ERROR_TYPE_ACTION,
11160                                           NULL,
11161                                           "action type not supported");
11162         }
11163         if (ret)
11164                 return ret;
11165         LIST_REMOVE(action, next);
11166         rte_free(action);
11167         return 0;
11168 }
11169
11170 /**
11171  * Updates in place shared RSS action configuration.
11172  *
11173  * @param[in] dev
11174  *   Pointer to the Ethernet device structure.
11175  * @param[in] shared_rss
11176  *   The shared RSS action object to be updated.
11177  * @param[in] action_conf
11178  *   RSS action specification used to modify *shared_rss*.
11179  * @param[out] error
11180  *   Perform verbose error reporting if not NULL. Initialized in case of
11181  *   error only.
11182  *
11183  * @return
11184  *   0 on success, otherwise negative errno value.
11185  * @note: currently only support update of RSS queues.
11186  */
11187 static int
11188 __flow_dv_action_rss_update(struct rte_eth_dev *dev,
11189                             struct mlx5_shared_action_rss *shared_rss,
11190                             const struct rte_flow_action_rss *action_conf,
11191                             struct rte_flow_error *error)
11192 {
11193         size_t i;
11194         int ret;
11195         void *queue = NULL;
11196         const uint8_t *rss_key;
11197         uint32_t rss_key_len;
11198         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
11199
11200         queue = mlx5_malloc(MLX5_MEM_ZERO,
11201                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
11202                             0, SOCKET_ID_ANY);
11203         if (!queue)
11204                 return rte_flow_error_set(error, ENOMEM,
11205                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11206                                           NULL,
11207                                           "cannot allocate resource memory");
11208         if (action_conf->key) {
11209                 rss_key = action_conf->key;
11210                 rss_key_len = action_conf->key_len;
11211         } else {
11212                 rss_key = rss_hash_default_key;
11213                 rss_key_len = MLX5_RSS_HASH_KEY_LEN;
11214         }
11215         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
11216                 uint32_t hrxq_idx;
11217                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
11218                 int tunnel;
11219
11220                 for (tunnel = 0; tunnel < 2; tunnel++) {
11221                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup
11222                                         (shared_rss, hash_fields, tunnel);
11223                         MLX5_ASSERT(hrxq_idx);
11224                         ret = mlx5_hrxq_modify
11225                                 (dev, hrxq_idx,
11226                                  rss_key, rss_key_len,
11227                                  hash_fields,
11228                                  action_conf->queue, action_conf->queue_num);
11229                         if (ret) {
11230                                 mlx5_free(queue);
11231                                 return rte_flow_error_set
11232                                         (error, rte_errno,
11233                                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
11234                                          "cannot update hash queue");
11235                         }
11236                 }
11237         }
11238         mlx5_free(shared_rss->queue);
11239         shared_rss->queue = queue;
11240         memcpy(shared_rss->queue, action_conf->queue, queue_size);
11241         shared_rss->origin.queue = shared_rss->queue;
11242         shared_rss->origin.queue_num = action_conf->queue_num;
11243         return 0;
11244 }
11245
11246 /**
11247  * Updates in place shared action configuration, lock free,
11248  * (mutex should be acquired by caller).
11249  *
11250  * @param[in] dev
11251  *   Pointer to the Ethernet device structure.
11252  * @param[in] action
11253  *   The shared action object to be updated.
11254  * @param[in] action_conf
11255  *   Action specification used to modify *action*.
11256  *   *action_conf* should be of type correlating with type of the *action*,
11257  *   otherwise considered as invalid.
11258  * @param[out] error
11259  *   Perform verbose error reporting if not NULL. Initialized in case of
11260  *   error only.
11261  *
11262  * @return
11263  *   0 on success, otherwise negative errno value.
11264  */
11265 static int
11266 __flow_dv_action_update(struct rte_eth_dev *dev,
11267                         struct rte_flow_shared_action *action,
11268                         const void *action_conf,
11269                         struct rte_flow_error *error)
11270 {
11271         switch (action->type) {
11272         case MLX5_RTE_FLOW_ACTION_TYPE_SHARED_RSS:
11273                 return __flow_dv_action_rss_update(dev, &action->rss,
11274                                                    action_conf, error);
11275         default:
11276                 return rte_flow_error_set(error, ENOTSUP,
11277                                           RTE_FLOW_ERROR_TYPE_ACTION,
11278                                           NULL,
11279                                           "action type not supported");
11280         }
11281 }
11282 /**
11283  * Query a dv flow  rule for its statistics via devx.
11284  *
11285  * @param[in] dev
11286  *   Pointer to Ethernet device.
11287  * @param[in] flow
11288  *   Pointer to the sub flow.
11289  * @param[out] data
11290  *   data retrieved by the query.
11291  * @param[out] error
11292  *   Perform verbose error reporting if not NULL.
11293  *
11294  * @return
11295  *   0 on success, a negative errno value otherwise and rte_errno is set.
11296  */
11297 static int
11298 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
11299                     void *data, struct rte_flow_error *error)
11300 {
11301         struct mlx5_priv *priv = dev->data->dev_private;
11302         struct rte_flow_query_count *qc = data;
11303
11304         if (!priv->config.devx)
11305                 return rte_flow_error_set(error, ENOTSUP,
11306                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11307                                           NULL,
11308                                           "counters are not supported");
11309         if (flow->counter) {
11310                 uint64_t pkts, bytes;
11311                 struct mlx5_flow_counter *cnt;
11312
11313                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
11314                                                  NULL);
11315                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
11316                                                &bytes);
11317
11318                 if (err)
11319                         return rte_flow_error_set(error, -err,
11320                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11321                                         NULL, "cannot read counters");
11322                 qc->hits_set = 1;
11323                 qc->bytes_set = 1;
11324                 qc->hits = pkts - cnt->hits;
11325                 qc->bytes = bytes - cnt->bytes;
11326                 if (qc->reset) {
11327                         cnt->hits = pkts;
11328                         cnt->bytes = bytes;
11329                 }
11330                 return 0;
11331         }
11332         return rte_flow_error_set(error, EINVAL,
11333                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11334                                   NULL,
11335                                   "counters are not available");
11336 }
11337
11338 /**
11339  * Query a flow rule AGE action for aging information.
11340  *
11341  * @param[in] dev
11342  *   Pointer to Ethernet device.
11343  * @param[in] flow
11344  *   Pointer to the sub flow.
11345  * @param[out] data
11346  *   data retrieved by the query.
11347  * @param[out] error
11348  *   Perform verbose error reporting if not NULL.
11349  *
11350  * @return
11351  *   0 on success, a negative errno value otherwise and rte_errno is set.
11352  */
11353 static int
11354 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
11355                   void *data, struct rte_flow_error *error)
11356 {
11357         struct rte_flow_query_age *resp = data;
11358
11359         if (flow->counter) {
11360                 struct mlx5_age_param *age_param =
11361                                 flow_dv_counter_idx_get_age(dev, flow->counter);
11362
11363                 if (!age_param || !age_param->timeout)
11364                         return rte_flow_error_set
11365                                         (error, EINVAL,
11366                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11367                                          NULL, "cannot read age data");
11368                 resp->aged = __atomic_load_n(&age_param->state,
11369                                              __ATOMIC_RELAXED) ==
11370                                                         AGE_TMOUT ? 1 : 0;
11371                 resp->sec_since_last_hit_valid = !resp->aged;
11372                 if (resp->sec_since_last_hit_valid)
11373                         resp->sec_since_last_hit =
11374                                 __atomic_load_n(&age_param->sec_since_last_hit,
11375                                                 __ATOMIC_RELAXED);
11376                 return 0;
11377         }
11378         return rte_flow_error_set(error, EINVAL,
11379                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11380                                   NULL,
11381                                   "age data not available");
11382 }
11383
11384 /**
11385  * Query a flow.
11386  *
11387  * @see rte_flow_query()
11388  * @see rte_flow_ops
11389  */
11390 static int
11391 flow_dv_query(struct rte_eth_dev *dev,
11392               struct rte_flow *flow __rte_unused,
11393               const struct rte_flow_action *actions __rte_unused,
11394               void *data __rte_unused,
11395               struct rte_flow_error *error __rte_unused)
11396 {
11397         int ret = -EINVAL;
11398
11399         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
11400                 switch (actions->type) {
11401                 case RTE_FLOW_ACTION_TYPE_VOID:
11402                         break;
11403                 case RTE_FLOW_ACTION_TYPE_COUNT:
11404                         ret = flow_dv_query_count(dev, flow, data, error);
11405                         break;
11406                 case RTE_FLOW_ACTION_TYPE_AGE:
11407                         ret = flow_dv_query_age(dev, flow, data, error);
11408                         break;
11409                 default:
11410                         return rte_flow_error_set(error, ENOTSUP,
11411                                                   RTE_FLOW_ERROR_TYPE_ACTION,
11412                                                   actions,
11413                                                   "action not supported");
11414                 }
11415         }
11416         return ret;
11417 }
11418
11419 /**
11420  * Destroy the meter table set.
11421  * Lock free, (mutex should be acquired by caller).
11422  *
11423  * @param[in] dev
11424  *   Pointer to Ethernet device.
11425  * @param[in] tbl
11426  *   Pointer to the meter table set.
11427  *
11428  * @return
11429  *   Always 0.
11430  */
11431 static int
11432 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
11433                         struct mlx5_meter_domains_infos *tbl)
11434 {
11435         struct mlx5_priv *priv = dev->data->dev_private;
11436         struct mlx5_meter_domains_infos *mtd =
11437                                 (struct mlx5_meter_domains_infos *)tbl;
11438
11439         if (!mtd || !priv->config.dv_flow_en)
11440                 return 0;
11441         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
11442                 claim_zero(mlx5_flow_os_destroy_flow
11443                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
11444         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
11445                 claim_zero(mlx5_flow_os_destroy_flow
11446                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
11447         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
11448                 claim_zero(mlx5_flow_os_destroy_flow
11449                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
11450         if (mtd->egress.color_matcher)
11451                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11452                            (mtd->egress.color_matcher));
11453         if (mtd->egress.any_matcher)
11454                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11455                            (mtd->egress.any_matcher));
11456         if (mtd->egress.tbl)
11457                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
11458         if (mtd->egress.sfx_tbl)
11459                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
11460         if (mtd->ingress.color_matcher)
11461                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11462                            (mtd->ingress.color_matcher));
11463         if (mtd->ingress.any_matcher)
11464                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11465                            (mtd->ingress.any_matcher));
11466         if (mtd->ingress.tbl)
11467                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
11468         if (mtd->ingress.sfx_tbl)
11469                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
11470         if (mtd->transfer.color_matcher)
11471                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11472                            (mtd->transfer.color_matcher));
11473         if (mtd->transfer.any_matcher)
11474                 claim_zero(mlx5_flow_os_destroy_flow_matcher
11475                            (mtd->transfer.any_matcher));
11476         if (mtd->transfer.tbl)
11477                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
11478         if (mtd->transfer.sfx_tbl)
11479                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
11480         if (mtd->drop_actn)
11481                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
11482         mlx5_free(mtd);
11483         return 0;
11484 }
11485
11486 /* Number of meter flow actions, count and jump or count and drop. */
11487 #define METER_ACTIONS 2
11488
11489 /**
11490  * Create specify domain meter table and suffix table.
11491  *
11492  * @param[in] dev
11493  *   Pointer to Ethernet device.
11494  * @param[in,out] mtb
11495  *   Pointer to DV meter table set.
11496  * @param[in] egress
11497  *   Table attribute.
11498  * @param[in] transfer
11499  *   Table attribute.
11500  * @param[in] color_reg_c_idx
11501  *   Reg C index for color match.
11502  *
11503  * @return
11504  *   0 on success, -1 otherwise and rte_errno is set.
11505  */
11506 static int
11507 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
11508                            struct mlx5_meter_domains_infos *mtb,
11509                            uint8_t egress, uint8_t transfer,
11510                            uint32_t color_reg_c_idx)
11511 {
11512         struct mlx5_priv *priv = dev->data->dev_private;
11513         struct mlx5_dev_ctx_shared *sh = priv->sh;
11514         struct mlx5_flow_dv_match_params mask = {
11515                 .size = sizeof(mask.buf),
11516         };
11517         struct mlx5_flow_dv_match_params value = {
11518                 .size = sizeof(value.buf),
11519         };
11520         struct mlx5dv_flow_matcher_attr dv_attr = {
11521                 .type = IBV_FLOW_ATTR_NORMAL,
11522                 .priority = 0,
11523                 .match_criteria_enable = 0,
11524                 .match_mask = (void *)&mask,
11525         };
11526         void *actions[METER_ACTIONS];
11527         struct mlx5_meter_domain_info *dtb;
11528         struct rte_flow_error error;
11529         int i = 0;
11530         int ret;
11531
11532         if (transfer)
11533                 dtb = &mtb->transfer;
11534         else if (egress)
11535                 dtb = &mtb->egress;
11536         else
11537                 dtb = &mtb->ingress;
11538         /* Create the meter table with METER level. */
11539         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
11540                                             egress, transfer, false, NULL, 0,
11541                                             0, &error);
11542         if (!dtb->tbl) {
11543                 DRV_LOG(ERR, "Failed to create meter policer table.");
11544                 return -1;
11545         }
11546         /* Create the meter suffix table with SUFFIX level. */
11547         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
11548                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
11549                                             egress, transfer, false, NULL, 0,
11550                                             0, &error);
11551         if (!dtb->sfx_tbl) {
11552                 DRV_LOG(ERR, "Failed to create meter suffix table.");
11553                 return -1;
11554         }
11555         /* Create matchers, Any and Color. */
11556         dv_attr.priority = 3;
11557         dv_attr.match_criteria_enable = 0;
11558         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11559                                                &dtb->any_matcher);
11560         if (ret) {
11561                 DRV_LOG(ERR, "Failed to create meter"
11562                              " policer default matcher.");
11563                 goto error_exit;
11564         }
11565         dv_attr.priority = 0;
11566         dv_attr.match_criteria_enable =
11567                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
11568         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
11569                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
11570         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
11571                                                &dtb->color_matcher);
11572         if (ret) {
11573                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
11574                 goto error_exit;
11575         }
11576         if (mtb->count_actns[RTE_MTR_DROPPED])
11577                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
11578         actions[i++] = mtb->drop_actn;
11579         /* Default rule: lowest priority, match any, actions: drop. */
11580         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
11581                                        actions,
11582                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
11583         if (ret) {
11584                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
11585                 goto error_exit;
11586         }
11587         return 0;
11588 error_exit:
11589         return -1;
11590 }
11591
11592 /**
11593  * Create the needed meter and suffix tables.
11594  * Lock free, (mutex should be acquired by caller).
11595  *
11596  * @param[in] dev
11597  *   Pointer to Ethernet device.
11598  * @param[in] fm
11599  *   Pointer to the flow meter.
11600  *
11601  * @return
11602  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
11603  */
11604 static struct mlx5_meter_domains_infos *
11605 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
11606                        const struct mlx5_flow_meter *fm)
11607 {
11608         struct mlx5_priv *priv = dev->data->dev_private;
11609         struct mlx5_meter_domains_infos *mtb;
11610         int ret;
11611         int i;
11612
11613         if (!priv->mtr_en) {
11614                 rte_errno = ENOTSUP;
11615                 return NULL;
11616         }
11617         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
11618         if (!mtb) {
11619                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
11620                 return NULL;
11621         }
11622         /* Create meter count actions */
11623         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
11624                 struct mlx5_flow_counter *cnt;
11625                 if (!fm->policer_stats.cnt[i])
11626                         continue;
11627                 cnt = flow_dv_counter_get_by_idx(dev,
11628                       fm->policer_stats.cnt[i], NULL);
11629                 mtb->count_actns[i] = cnt->action;
11630         }
11631         /* Create drop action. */
11632         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
11633         if (ret) {
11634                 DRV_LOG(ERR, "Failed to create drop action.");
11635                 goto error_exit;
11636         }
11637         /* Egress meter table. */
11638         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
11639         if (ret) {
11640                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
11641                 goto error_exit;
11642         }
11643         /* Ingress meter table. */
11644         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
11645         if (ret) {
11646                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
11647                 goto error_exit;
11648         }
11649         /* FDB meter table. */
11650         if (priv->config.dv_esw_en) {
11651                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
11652                                                  priv->mtr_color_reg);
11653                 if (ret) {
11654                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
11655                         goto error_exit;
11656                 }
11657         }
11658         return mtb;
11659 error_exit:
11660         flow_dv_destroy_mtr_tbl(dev, mtb);
11661         return NULL;
11662 }
11663
11664 /**
11665  * Destroy domain policer rule.
11666  *
11667  * @param[in] dt
11668  *   Pointer to domain table.
11669  */
11670 static void
11671 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
11672 {
11673         int i;
11674
11675         for (i = 0; i < RTE_MTR_DROPPED; i++) {
11676                 if (dt->policer_rules[i]) {
11677                         claim_zero(mlx5_flow_os_destroy_flow
11678                                    (dt->policer_rules[i]));
11679                         dt->policer_rules[i] = NULL;
11680                 }
11681         }
11682         if (dt->jump_actn) {
11683                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
11684                 dt->jump_actn = NULL;
11685         }
11686 }
11687
11688 /**
11689  * Destroy policer rules.
11690  *
11691  * @param[in] dev
11692  *   Pointer to Ethernet device.
11693  * @param[in] fm
11694  *   Pointer to flow meter structure.
11695  * @param[in] attr
11696  *   Pointer to flow attributes.
11697  *
11698  * @return
11699  *   Always 0.
11700  */
11701 static int
11702 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
11703                               const struct mlx5_flow_meter *fm,
11704                               const struct rte_flow_attr *attr)
11705 {
11706         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
11707
11708         if (!mtb)
11709                 return 0;
11710         if (attr->egress)
11711                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
11712         if (attr->ingress)
11713                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
11714         if (attr->transfer)
11715                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
11716         return 0;
11717 }
11718
11719 /**
11720  * Create specify domain meter policer rule.
11721  *
11722  * @param[in] fm
11723  *   Pointer to flow meter structure.
11724  * @param[in] mtb
11725  *   Pointer to DV meter table set.
11726  * @param[in] mtr_reg_c
11727  *   Color match REG_C.
11728  *
11729  * @return
11730  *   0 on success, -1 otherwise.
11731  */
11732 static int
11733 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
11734                                     struct mlx5_meter_domain_info *dtb,
11735                                     uint8_t mtr_reg_c)
11736 {
11737         struct mlx5_flow_dv_match_params matcher = {
11738                 .size = sizeof(matcher.buf),
11739         };
11740         struct mlx5_flow_dv_match_params value = {
11741                 .size = sizeof(value.buf),
11742         };
11743         struct mlx5_meter_domains_infos *mtb = fm->mfts;
11744         void *actions[METER_ACTIONS];
11745         int i;
11746         int ret = 0;
11747
11748         /* Create jump action. */
11749         if (!dtb->jump_actn)
11750                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11751                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
11752         if (ret) {
11753                 DRV_LOG(ERR, "Failed to create policer jump action.");
11754                 goto error;
11755         }
11756         for (i = 0; i < RTE_MTR_DROPPED; i++) {
11757                 int j = 0;
11758
11759                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
11760                                        rte_col_2_mlx5_col(i), UINT8_MAX);
11761                 if (mtb->count_actns[i])
11762                         actions[j++] = mtb->count_actns[i];
11763                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
11764                         actions[j++] = mtb->drop_actn;
11765                 else
11766                         actions[j++] = dtb->jump_actn;
11767                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
11768                                                (void *)&value, j, actions,
11769                                                &dtb->policer_rules[i]);
11770                 if (ret) {
11771                         DRV_LOG(ERR, "Failed to create policer rule.");
11772                         goto error;
11773                 }
11774         }
11775         return 0;
11776 error:
11777         rte_errno = errno;
11778         return -1;
11779 }
11780
11781 /**
11782  * Create policer rules.
11783  *
11784  * @param[in] dev
11785  *   Pointer to Ethernet device.
11786  * @param[in] fm
11787  *   Pointer to flow meter structure.
11788  * @param[in] attr
11789  *   Pointer to flow attributes.
11790  *
11791  * @return
11792  *   0 on success, -1 otherwise.
11793  */
11794 static int
11795 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
11796                              struct mlx5_flow_meter *fm,
11797                              const struct rte_flow_attr *attr)
11798 {
11799         struct mlx5_priv *priv = dev->data->dev_private;
11800         struct mlx5_meter_domains_infos *mtb = fm->mfts;
11801         int ret;
11802
11803         if (attr->egress) {
11804                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
11805                                                 priv->mtr_color_reg);
11806                 if (ret) {
11807                         DRV_LOG(ERR, "Failed to create egress policer.");
11808                         goto error;
11809                 }
11810         }
11811         if (attr->ingress) {
11812                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
11813                                                 priv->mtr_color_reg);
11814                 if (ret) {
11815                         DRV_LOG(ERR, "Failed to create ingress policer.");
11816                         goto error;
11817                 }
11818         }
11819         if (attr->transfer) {
11820                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
11821                                                 priv->mtr_color_reg);
11822                 if (ret) {
11823                         DRV_LOG(ERR, "Failed to create transfer policer.");
11824                         goto error;
11825                 }
11826         }
11827         return 0;
11828 error:
11829         flow_dv_destroy_policer_rules(dev, fm, attr);
11830         return -1;
11831 }
11832
11833 /**
11834  * Validate the batch counter support in root table.
11835  *
11836  * Create a simple flow with invalid counter and drop action on root table to
11837  * validate if batch counter with offset on root table is supported or not.
11838  *
11839  * @param[in] dev
11840  *   Pointer to rte_eth_dev structure.
11841  *
11842  * @return
11843  *   0 on success, a negative errno value otherwise and rte_errno is set.
11844  */
11845 int
11846 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
11847 {
11848         struct mlx5_priv *priv = dev->data->dev_private;
11849         struct mlx5_dev_ctx_shared *sh = priv->sh;
11850         struct mlx5_flow_dv_match_params mask = {
11851                 .size = sizeof(mask.buf),
11852         };
11853         struct mlx5_flow_dv_match_params value = {
11854                 .size = sizeof(value.buf),
11855         };
11856         struct mlx5dv_flow_matcher_attr dv_attr = {
11857                 .type = IBV_FLOW_ATTR_NORMAL,
11858                 .priority = 0,
11859                 .match_criteria_enable = 0,
11860                 .match_mask = (void *)&mask,
11861         };
11862         void *actions[2] = { 0 };
11863         struct mlx5_flow_tbl_resource *tbl = NULL, *dest_tbl = NULL;
11864         struct mlx5_devx_obj *dcs = NULL;
11865         void *matcher = NULL;
11866         void *flow = NULL;
11867         int i, ret = -1;
11868
11869         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
11870         if (!tbl)
11871                 goto err;
11872         dest_tbl = flow_dv_tbl_resource_get(dev, 1, 0, 0, false,
11873                                             NULL, 0, 0, NULL);
11874         if (!dest_tbl)
11875                 goto err;
11876         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
11877         if (!dcs)
11878                 goto err;
11879         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
11880                                                     &actions[0]);
11881         if (ret)
11882                 goto err;
11883         ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
11884                                 (dest_tbl->obj, &actions[1]);
11885         if (ret)
11886                 goto err;
11887         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
11888         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
11889                                                &matcher);
11890         if (ret)
11891                 goto err;
11892         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
11893                                        actions, &flow);
11894 err:
11895         /*
11896          * If batch counter with offset is not supported, the driver will not
11897          * validate the invalid offset value, flow create should success.
11898          * In this case, it means batch counter is not supported in root table.
11899          *
11900          * Otherwise, if flow create is failed, counter offset is supported.
11901          */
11902         if (flow) {
11903                 DRV_LOG(INFO, "Batch counter is not supported in root "
11904                               "table. Switch to fallback mode.");
11905                 rte_errno = ENOTSUP;
11906                 ret = -rte_errno;
11907                 claim_zero(mlx5_flow_os_destroy_flow(flow));
11908         } else {
11909                 /* Check matcher to make sure validate fail at flow create. */
11910                 if (!matcher || (matcher && errno != EINVAL))
11911                         DRV_LOG(ERR, "Unexpected error in counter offset "
11912                                      "support detection");
11913                 ret = 0;
11914         }
11915         for (i = 0; i < 2; i++) {
11916                 if (actions[i])
11917                         claim_zero(mlx5_flow_os_destroy_flow_action
11918                                    (actions[i]));
11919         }
11920         if (matcher)
11921                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
11922         if (tbl)
11923                 flow_dv_tbl_resource_release(dev, tbl);
11924         if (dest_tbl)
11925                 flow_dv_tbl_resource_release(dev, dest_tbl);
11926         if (dcs)
11927                 claim_zero(mlx5_devx_cmd_destroy(dcs));
11928         return ret;
11929 }
11930
11931 /**
11932  * Query a devx counter.
11933  *
11934  * @param[in] dev
11935  *   Pointer to the Ethernet device structure.
11936  * @param[in] cnt
11937  *   Index to the flow counter.
11938  * @param[in] clear
11939  *   Set to clear the counter statistics.
11940  * @param[out] pkts
11941  *   The statistics value of packets.
11942  * @param[out] bytes
11943  *   The statistics value of bytes.
11944  *
11945  * @return
11946  *   0 on success, otherwise return -1.
11947  */
11948 static int
11949 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
11950                       uint64_t *pkts, uint64_t *bytes)
11951 {
11952         struct mlx5_priv *priv = dev->data->dev_private;
11953         struct mlx5_flow_counter *cnt;
11954         uint64_t inn_pkts, inn_bytes;
11955         int ret;
11956
11957         if (!priv->config.devx)
11958                 return -1;
11959
11960         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
11961         if (ret)
11962                 return -1;
11963         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
11964         *pkts = inn_pkts - cnt->hits;
11965         *bytes = inn_bytes - cnt->bytes;
11966         if (clear) {
11967                 cnt->hits = inn_pkts;
11968                 cnt->bytes = inn_bytes;
11969         }
11970         return 0;
11971 }
11972
11973 /**
11974  * Get aged-out flows.
11975  *
11976  * @param[in] dev
11977  *   Pointer to the Ethernet device structure.
11978  * @param[in] context
11979  *   The address of an array of pointers to the aged-out flows contexts.
11980  * @param[in] nb_contexts
11981  *   The length of context array pointers.
11982  * @param[out] error
11983  *   Perform verbose error reporting if not NULL. Initialized in case of
11984  *   error only.
11985  *
11986  * @return
11987  *   how many contexts get in success, otherwise negative errno value.
11988  *   if nb_contexts is 0, return the amount of all aged contexts.
11989  *   if nb_contexts is not 0 , return the amount of aged flows reported
11990  *   in the context array.
11991  * @note: only stub for now
11992  */
11993 static int
11994 flow_get_aged_flows(struct rte_eth_dev *dev,
11995                     void **context,
11996                     uint32_t nb_contexts,
11997                     struct rte_flow_error *error)
11998 {
11999         struct mlx5_priv *priv = dev->data->dev_private;
12000         struct mlx5_age_info *age_info;
12001         struct mlx5_age_param *age_param;
12002         struct mlx5_flow_counter *counter;
12003         int nb_flows = 0;
12004
12005         if (nb_contexts && !context)
12006                 return rte_flow_error_set(error, EINVAL,
12007                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12008                                           NULL,
12009                                           "Should assign at least one flow or"
12010                                           " context to get if nb_contexts != 0");
12011         age_info = GET_PORT_AGE_INFO(priv);
12012         rte_spinlock_lock(&age_info->aged_sl);
12013         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
12014                 nb_flows++;
12015                 if (nb_contexts) {
12016                         age_param = MLX5_CNT_TO_AGE(counter);
12017                         context[nb_flows - 1] = age_param->context;
12018                         if (!(--nb_contexts))
12019                                 break;
12020                 }
12021         }
12022         rte_spinlock_unlock(&age_info->aged_sl);
12023         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
12024         return nb_flows;
12025 }
12026
12027 /*
12028  * Mutex-protected thunk to lock-free  __flow_dv_translate().
12029  */
12030 static int
12031 flow_dv_translate(struct rte_eth_dev *dev,
12032                   struct mlx5_flow *dev_flow,
12033                   const struct rte_flow_attr *attr,
12034                   const struct rte_flow_item items[],
12035                   const struct rte_flow_action actions[],
12036                   struct rte_flow_error *error)
12037 {
12038         int ret;
12039
12040         flow_dv_shared_lock(dev);
12041         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
12042         flow_dv_shared_unlock(dev);
12043         return ret;
12044 }
12045
12046 /*
12047  * Mutex-protected thunk to lock-free  __flow_dv_apply().
12048  */
12049 static int
12050 flow_dv_apply(struct rte_eth_dev *dev,
12051               struct rte_flow *flow,
12052               struct rte_flow_error *error)
12053 {
12054         int ret;
12055
12056         flow_dv_shared_lock(dev);
12057         ret = __flow_dv_apply(dev, flow, error);
12058         flow_dv_shared_unlock(dev);
12059         return ret;
12060 }
12061
12062 /*
12063  * Mutex-protected thunk to lock-free __flow_dv_remove().
12064  */
12065 static void
12066 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12067 {
12068         flow_dv_shared_lock(dev);
12069         __flow_dv_remove(dev, flow);
12070         flow_dv_shared_unlock(dev);
12071 }
12072
12073 /*
12074  * Mutex-protected thunk to lock-free __flow_dv_destroy().
12075  */
12076 static void
12077 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12078 {
12079         flow_dv_shared_lock(dev);
12080         __flow_dv_destroy(dev, flow);
12081         flow_dv_shared_unlock(dev);
12082 }
12083
12084 /*
12085  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
12086  */
12087 static uint32_t
12088 flow_dv_counter_allocate(struct rte_eth_dev *dev)
12089 {
12090         uint32_t cnt;
12091
12092         flow_dv_shared_lock(dev);
12093         cnt = flow_dv_counter_alloc(dev, 0);
12094         flow_dv_shared_unlock(dev);
12095         return cnt;
12096 }
12097
12098 /*
12099  * Mutex-protected thunk to lock-free flow_dv_counter_release().
12100  */
12101 static void
12102 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
12103 {
12104         flow_dv_shared_lock(dev);
12105         flow_dv_counter_release(dev, cnt);
12106         flow_dv_shared_unlock(dev);
12107 }
12108
12109 /**
12110  * Validate shared action.
12111  * Dispatcher for action type specific validation.
12112  *
12113  * @param[in] dev
12114  *   Pointer to the Ethernet device structure.
12115  * @param[in] conf
12116  *   Shared action configuration.
12117  * @param[in] action
12118  *   The shared action object to validate.
12119  * @param[out] error
12120  *   Perform verbose error reporting if not NULL. Initialized in case of
12121  *   error only.
12122  *
12123  * @return
12124  *   0 on success, otherwise negative errno value.
12125  */
12126 static int
12127 flow_dv_action_validate(struct rte_eth_dev *dev,
12128                         const struct rte_flow_shared_action_conf *conf,
12129                         const struct rte_flow_action *action,
12130                         struct rte_flow_error *error)
12131 {
12132         RTE_SET_USED(conf);
12133         switch (action->type) {
12134         case RTE_FLOW_ACTION_TYPE_RSS:
12135                 return mlx5_validate_action_rss(dev, action, error);
12136         default:
12137                 return rte_flow_error_set(error, ENOTSUP,
12138                                           RTE_FLOW_ERROR_TYPE_ACTION,
12139                                           NULL,
12140                                           "action type not supported");
12141         }
12142 }
12143
12144 /*
12145  * Mutex-protected thunk to lock-free  __flow_dv_action_create().
12146  */
12147 static struct rte_flow_shared_action *
12148 flow_dv_action_create(struct rte_eth_dev *dev,
12149                       const struct rte_flow_shared_action_conf *conf,
12150                       const struct rte_flow_action *action,
12151                       struct rte_flow_error *error)
12152 {
12153         struct rte_flow_shared_action *shared_action = NULL;
12154
12155         flow_dv_shared_lock(dev);
12156         shared_action = __flow_dv_action_create(dev, conf, action, error);
12157         flow_dv_shared_unlock(dev);
12158         return shared_action;
12159 }
12160
12161 /*
12162  * Mutex-protected thunk to lock-free  __flow_dv_action_destroy().
12163  */
12164 static int
12165 flow_dv_action_destroy(struct rte_eth_dev *dev,
12166                        struct rte_flow_shared_action *action,
12167                        struct rte_flow_error *error)
12168 {
12169         int ret;
12170
12171         flow_dv_shared_lock(dev);
12172         ret = __flow_dv_action_destroy(dev, action, error);
12173         flow_dv_shared_unlock(dev);
12174         return ret;
12175 }
12176
12177 /*
12178  * Mutex-protected thunk to lock-free  __flow_dv_action_update().
12179  */
12180 static int
12181 flow_dv_action_update(struct rte_eth_dev *dev,
12182                       struct rte_flow_shared_action *action,
12183                       const void *action_conf,
12184                       struct rte_flow_error *error)
12185 {
12186         int ret;
12187
12188         flow_dv_shared_lock(dev);
12189         ret = __flow_dv_action_update(dev, action, action_conf,
12190                                       error);
12191         flow_dv_shared_unlock(dev);
12192         return ret;
12193 }
12194
12195 static int
12196 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
12197 {
12198         struct mlx5_priv *priv = dev->data->dev_private;
12199         int ret = 0;
12200
12201         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
12202                 ret = mlx5_glue->dr_sync_domain(priv->sh->rx_domain,
12203                                                 flags);
12204                 if (ret != 0)
12205                         return ret;
12206         }
12207         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
12208                 ret = mlx5_glue->dr_sync_domain(priv->sh->tx_domain, flags);
12209                 if (ret != 0)
12210                         return ret;
12211         }
12212         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
12213                 ret = mlx5_glue->dr_sync_domain(priv->sh->fdb_domain, flags);
12214                 if (ret != 0)
12215                         return ret;
12216         }
12217         return 0;
12218 }
12219
12220 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
12221         .validate = flow_dv_validate,
12222         .prepare = flow_dv_prepare,
12223         .translate = flow_dv_translate,
12224         .apply = flow_dv_apply,
12225         .remove = flow_dv_remove,
12226         .destroy = flow_dv_destroy,
12227         .query = flow_dv_query,
12228         .create_mtr_tbls = flow_dv_create_mtr_tbl,
12229         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
12230         .create_policer_rules = flow_dv_create_policer_rules,
12231         .destroy_policer_rules = flow_dv_destroy_policer_rules,
12232         .counter_alloc = flow_dv_counter_allocate,
12233         .counter_free = flow_dv_counter_free,
12234         .counter_query = flow_dv_counter_query,
12235         .get_aged_flows = flow_get_aged_flows,
12236         .action_validate = flow_dv_action_validate,
12237         .action_create = flow_dv_action_create,
12238         .action_destroy = flow_dv_action_destroy,
12239         .action_update = flow_dv_action_update,
12240         .sync_domain = flow_dv_sync_domain,
12241 };
12242
12243 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
12244