1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
43 #ifndef HAVE_MLX5DV_DR_ESWITCH
44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
49 #ifndef HAVE_MLX5DV_DR
50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
53 /* VLAN header definitions */
54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
74 struct mlx5_flow_tbl_resource *tbl);
77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
80 * Initialize flow attributes structure according to flow items' types.
82 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
83 * mode. For tunnel mode, the items to be modified are the outermost ones.
86 * Pointer to item specification.
88 * Pointer to flow attributes structure.
90 * Pointer to the sub flow.
91 * @param[in] tunnel_decap
92 * Whether action is after tunnel decapsulation.
95 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
96 struct mlx5_flow *dev_flow, bool tunnel_decap)
98 uint64_t layers = dev_flow->handle->layers;
101 * If layers is already initialized, it means this dev_flow is the
102 * suffix flow, the layers flags is set by the prefix flow. Need to
103 * use the layer flags from prefix flow as the suffix flow may not
104 * have the user defined items as the flow is split.
107 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
109 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
111 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
113 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
118 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
119 uint8_t next_protocol = 0xff;
120 switch (item->type) {
121 case RTE_FLOW_ITEM_TYPE_GRE:
122 case RTE_FLOW_ITEM_TYPE_NVGRE:
123 case RTE_FLOW_ITEM_TYPE_VXLAN:
124 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
125 case RTE_FLOW_ITEM_TYPE_GENEVE:
126 case RTE_FLOW_ITEM_TYPE_MPLS:
130 case RTE_FLOW_ITEM_TYPE_IPV4:
133 if (item->mask != NULL &&
134 ((const struct rte_flow_item_ipv4 *)
135 item->mask)->hdr.next_proto_id)
137 ((const struct rte_flow_item_ipv4 *)
138 (item->spec))->hdr.next_proto_id &
139 ((const struct rte_flow_item_ipv4 *)
140 (item->mask))->hdr.next_proto_id;
141 if ((next_protocol == IPPROTO_IPIP ||
142 next_protocol == IPPROTO_IPV6) && tunnel_decap)
145 case RTE_FLOW_ITEM_TYPE_IPV6:
148 if (item->mask != NULL &&
149 ((const struct rte_flow_item_ipv6 *)
150 item->mask)->hdr.proto)
152 ((const struct rte_flow_item_ipv6 *)
153 (item->spec))->hdr.proto &
154 ((const struct rte_flow_item_ipv6 *)
155 (item->mask))->hdr.proto;
156 if ((next_protocol == IPPROTO_IPIP ||
157 next_protocol == IPPROTO_IPV6) && tunnel_decap)
160 case RTE_FLOW_ITEM_TYPE_UDP:
164 case RTE_FLOW_ITEM_TYPE_TCP:
176 * Convert rte_mtr_color to mlx5 color.
185 rte_col_2_mlx5_col(enum rte_color rcol)
188 case RTE_COLOR_GREEN:
189 return MLX5_FLOW_COLOR_GREEN;
190 case RTE_COLOR_YELLOW:
191 return MLX5_FLOW_COLOR_YELLOW;
193 return MLX5_FLOW_COLOR_RED;
197 return MLX5_FLOW_COLOR_UNDEFINED;
200 struct field_modify_info {
201 uint32_t size; /* Size of field in protocol header, in bytes. */
202 uint32_t offset; /* Offset of field in protocol header, in bytes. */
203 enum mlx5_modification_field id;
206 struct field_modify_info modify_eth[] = {
207 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
208 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
209 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
210 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
214 struct field_modify_info modify_vlan_out_first_vid[] = {
215 /* Size in bits !!! */
216 {12, 0, MLX5_MODI_OUT_FIRST_VID},
220 struct field_modify_info modify_ipv4[] = {
221 {1, 1, MLX5_MODI_OUT_IP_DSCP},
222 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
223 {4, 12, MLX5_MODI_OUT_SIPV4},
224 {4, 16, MLX5_MODI_OUT_DIPV4},
228 struct field_modify_info modify_ipv6[] = {
229 {1, 0, MLX5_MODI_OUT_IP_DSCP},
230 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
231 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
232 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
233 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
234 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
235 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
236 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
237 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
238 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
242 struct field_modify_info modify_udp[] = {
243 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
244 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
248 struct field_modify_info modify_tcp[] = {
249 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
250 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
251 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
252 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
257 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
258 uint8_t next_protocol, uint64_t *item_flags,
261 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
262 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
263 if (next_protocol == IPPROTO_IPIP) {
264 *item_flags |= MLX5_FLOW_LAYER_IPIP;
267 if (next_protocol == IPPROTO_IPV6) {
268 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
274 * Acquire the synchronizing object to protect multithreaded access
275 * to shared dv context. Lock occurs only if context is actually
276 * shared, i.e. we have multiport IB device and representors are
280 * Pointer to the rte_eth_dev structure.
283 flow_dv_shared_lock(struct rte_eth_dev *dev)
285 struct mlx5_priv *priv = dev->data->dev_private;
286 struct mlx5_dev_ctx_shared *sh = priv->sh;
288 if (sh->dv_refcnt > 1) {
291 ret = pthread_mutex_lock(&sh->dv_mutex);
298 flow_dv_shared_unlock(struct rte_eth_dev *dev)
300 struct mlx5_priv *priv = dev->data->dev_private;
301 struct mlx5_dev_ctx_shared *sh = priv->sh;
303 if (sh->dv_refcnt > 1) {
306 ret = pthread_mutex_unlock(&sh->dv_mutex);
312 /* Update VLAN's VID/PCP based on input rte_flow_action.
315 * Pointer to struct rte_flow_action.
317 * Pointer to struct rte_vlan_hdr.
320 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
321 struct rte_vlan_hdr *vlan)
324 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
326 ((const struct rte_flow_action_of_set_vlan_pcp *)
327 action->conf)->vlan_pcp;
328 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
329 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
330 vlan->vlan_tci |= vlan_tci;
331 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
332 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
333 vlan->vlan_tci |= rte_be_to_cpu_16
334 (((const struct rte_flow_action_of_set_vlan_vid *)
335 action->conf)->vlan_vid);
340 * Fetch 1, 2, 3 or 4 byte field from the byte array
341 * and return as unsigned integer in host-endian format.
344 * Pointer to data array.
346 * Size of field to extract.
349 * converted field in host endian format.
351 static inline uint32_t
352 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
361 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
364 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
365 ret = (ret << 8) | *(data + sizeof(uint16_t));
368 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
379 * Convert modify-header action to DV specification.
381 * Data length of each action is determined by provided field description
382 * and the item mask. Data bit offset and width of each action is determined
383 * by provided item mask.
386 * Pointer to item specification.
388 * Pointer to field modification information.
389 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
390 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
391 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
393 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
394 * Negative offset value sets the same offset as source offset.
395 * size field is ignored, value is taken from source field.
396 * @param[in,out] resource
397 * Pointer to the modify-header resource.
399 * Type of modification.
401 * Pointer to the error structure.
404 * 0 on success, a negative errno value otherwise and rte_errno is set.
407 flow_dv_convert_modify_action(struct rte_flow_item *item,
408 struct field_modify_info *field,
409 struct field_modify_info *dcopy,
410 struct mlx5_flow_dv_modify_hdr_resource *resource,
411 uint32_t type, struct rte_flow_error *error)
413 uint32_t i = resource->actions_num;
414 struct mlx5_modification_cmd *actions = resource->actions;
417 * The item and mask are provided in big-endian format.
418 * The fields should be presented as in big-endian format either.
419 * Mask must be always present, it defines the actual field width.
421 MLX5_ASSERT(item->mask);
422 MLX5_ASSERT(field->size);
429 if (i >= MLX5_MAX_MODIFY_NUM)
430 return rte_flow_error_set(error, EINVAL,
431 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
432 "too many items to modify");
433 /* Fetch variable byte size mask from the array. */
434 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
435 field->offset, field->size);
440 /* Deduce actual data width in bits from mask value. */
441 off_b = rte_bsf32(mask);
442 size_b = sizeof(uint32_t) * CHAR_BIT -
443 off_b - __builtin_clz(mask);
445 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
446 actions[i] = (struct mlx5_modification_cmd) {
452 /* Convert entire record to expected big-endian format. */
453 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
454 if (type == MLX5_MODIFICATION_TYPE_COPY) {
456 actions[i].dst_field = dcopy->id;
457 actions[i].dst_offset =
458 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
459 /* Convert entire record to big-endian format. */
460 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
462 MLX5_ASSERT(item->spec);
463 data = flow_dv_fetch_field((const uint8_t *)item->spec +
464 field->offset, field->size);
465 /* Shift out the trailing masked bits from data. */
466 data = (data & mask) >> off_b;
467 actions[i].data1 = rte_cpu_to_be_32(data);
471 } while (field->size);
472 if (resource->actions_num == i)
473 return rte_flow_error_set(error, EINVAL,
474 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
475 "invalid modification flow item");
476 resource->actions_num = i;
481 * Convert modify-header set IPv4 address action to DV specification.
483 * @param[in,out] resource
484 * Pointer to the modify-header resource.
486 * Pointer to action specification.
488 * Pointer to the error structure.
491 * 0 on success, a negative errno value otherwise and rte_errno is set.
494 flow_dv_convert_action_modify_ipv4
495 (struct mlx5_flow_dv_modify_hdr_resource *resource,
496 const struct rte_flow_action *action,
497 struct rte_flow_error *error)
499 const struct rte_flow_action_set_ipv4 *conf =
500 (const struct rte_flow_action_set_ipv4 *)(action->conf);
501 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
502 struct rte_flow_item_ipv4 ipv4;
503 struct rte_flow_item_ipv4 ipv4_mask;
505 memset(&ipv4, 0, sizeof(ipv4));
506 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
507 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
508 ipv4.hdr.src_addr = conf->ipv4_addr;
509 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
511 ipv4.hdr.dst_addr = conf->ipv4_addr;
512 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
515 item.mask = &ipv4_mask;
516 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
517 MLX5_MODIFICATION_TYPE_SET, error);
521 * Convert modify-header set IPv6 address action to DV specification.
523 * @param[in,out] resource
524 * Pointer to the modify-header resource.
526 * Pointer to action specification.
528 * Pointer to the error structure.
531 * 0 on success, a negative errno value otherwise and rte_errno is set.
534 flow_dv_convert_action_modify_ipv6
535 (struct mlx5_flow_dv_modify_hdr_resource *resource,
536 const struct rte_flow_action *action,
537 struct rte_flow_error *error)
539 const struct rte_flow_action_set_ipv6 *conf =
540 (const struct rte_flow_action_set_ipv6 *)(action->conf);
541 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
542 struct rte_flow_item_ipv6 ipv6;
543 struct rte_flow_item_ipv6 ipv6_mask;
545 memset(&ipv6, 0, sizeof(ipv6));
546 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
547 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
548 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
549 sizeof(ipv6.hdr.src_addr));
550 memcpy(&ipv6_mask.hdr.src_addr,
551 &rte_flow_item_ipv6_mask.hdr.src_addr,
552 sizeof(ipv6.hdr.src_addr));
554 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
555 sizeof(ipv6.hdr.dst_addr));
556 memcpy(&ipv6_mask.hdr.dst_addr,
557 &rte_flow_item_ipv6_mask.hdr.dst_addr,
558 sizeof(ipv6.hdr.dst_addr));
561 item.mask = &ipv6_mask;
562 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
563 MLX5_MODIFICATION_TYPE_SET, error);
567 * Convert modify-header set MAC address action to DV specification.
569 * @param[in,out] resource
570 * Pointer to the modify-header resource.
572 * Pointer to action specification.
574 * Pointer to the error structure.
577 * 0 on success, a negative errno value otherwise and rte_errno is set.
580 flow_dv_convert_action_modify_mac
581 (struct mlx5_flow_dv_modify_hdr_resource *resource,
582 const struct rte_flow_action *action,
583 struct rte_flow_error *error)
585 const struct rte_flow_action_set_mac *conf =
586 (const struct rte_flow_action_set_mac *)(action->conf);
587 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
588 struct rte_flow_item_eth eth;
589 struct rte_flow_item_eth eth_mask;
591 memset(ð, 0, sizeof(eth));
592 memset(ð_mask, 0, sizeof(eth_mask));
593 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
594 memcpy(ð.src.addr_bytes, &conf->mac_addr,
595 sizeof(eth.src.addr_bytes));
596 memcpy(ð_mask.src.addr_bytes,
597 &rte_flow_item_eth_mask.src.addr_bytes,
598 sizeof(eth_mask.src.addr_bytes));
600 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
601 sizeof(eth.dst.addr_bytes));
602 memcpy(ð_mask.dst.addr_bytes,
603 &rte_flow_item_eth_mask.dst.addr_bytes,
604 sizeof(eth_mask.dst.addr_bytes));
607 item.mask = ð_mask;
608 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
609 MLX5_MODIFICATION_TYPE_SET, error);
613 * Convert modify-header set VLAN VID action to DV specification.
615 * @param[in,out] resource
616 * Pointer to the modify-header resource.
618 * Pointer to action specification.
620 * Pointer to the error structure.
623 * 0 on success, a negative errno value otherwise and rte_errno is set.
626 flow_dv_convert_action_modify_vlan_vid
627 (struct mlx5_flow_dv_modify_hdr_resource *resource,
628 const struct rte_flow_action *action,
629 struct rte_flow_error *error)
631 const struct rte_flow_action_of_set_vlan_vid *conf =
632 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
633 int i = resource->actions_num;
634 struct mlx5_modification_cmd *actions = resource->actions;
635 struct field_modify_info *field = modify_vlan_out_first_vid;
637 if (i >= MLX5_MAX_MODIFY_NUM)
638 return rte_flow_error_set(error, EINVAL,
639 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
640 "too many items to modify");
641 actions[i] = (struct mlx5_modification_cmd) {
642 .action_type = MLX5_MODIFICATION_TYPE_SET,
644 .length = field->size,
645 .offset = field->offset,
647 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
648 actions[i].data1 = conf->vlan_vid;
649 actions[i].data1 = actions[i].data1 << 16;
650 resource->actions_num = ++i;
655 * Convert modify-header set TP action to DV specification.
657 * @param[in,out] resource
658 * Pointer to the modify-header resource.
660 * Pointer to action specification.
662 * Pointer to rte_flow_item objects list.
664 * Pointer to flow attributes structure.
665 * @param[in] dev_flow
666 * Pointer to the sub flow.
667 * @param[in] tunnel_decap
668 * Whether action is after tunnel decapsulation.
670 * Pointer to the error structure.
673 * 0 on success, a negative errno value otherwise and rte_errno is set.
676 flow_dv_convert_action_modify_tp
677 (struct mlx5_flow_dv_modify_hdr_resource *resource,
678 const struct rte_flow_action *action,
679 const struct rte_flow_item *items,
680 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
681 bool tunnel_decap, struct rte_flow_error *error)
683 const struct rte_flow_action_set_tp *conf =
684 (const struct rte_flow_action_set_tp *)(action->conf);
685 struct rte_flow_item item;
686 struct rte_flow_item_udp udp;
687 struct rte_flow_item_udp udp_mask;
688 struct rte_flow_item_tcp tcp;
689 struct rte_flow_item_tcp tcp_mask;
690 struct field_modify_info *field;
693 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
695 memset(&udp, 0, sizeof(udp));
696 memset(&udp_mask, 0, sizeof(udp_mask));
697 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
698 udp.hdr.src_port = conf->port;
699 udp_mask.hdr.src_port =
700 rte_flow_item_udp_mask.hdr.src_port;
702 udp.hdr.dst_port = conf->port;
703 udp_mask.hdr.dst_port =
704 rte_flow_item_udp_mask.hdr.dst_port;
706 item.type = RTE_FLOW_ITEM_TYPE_UDP;
708 item.mask = &udp_mask;
711 MLX5_ASSERT(attr->tcp);
712 memset(&tcp, 0, sizeof(tcp));
713 memset(&tcp_mask, 0, sizeof(tcp_mask));
714 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
715 tcp.hdr.src_port = conf->port;
716 tcp_mask.hdr.src_port =
717 rte_flow_item_tcp_mask.hdr.src_port;
719 tcp.hdr.dst_port = conf->port;
720 tcp_mask.hdr.dst_port =
721 rte_flow_item_tcp_mask.hdr.dst_port;
723 item.type = RTE_FLOW_ITEM_TYPE_TCP;
725 item.mask = &tcp_mask;
728 return flow_dv_convert_modify_action(&item, field, NULL, resource,
729 MLX5_MODIFICATION_TYPE_SET, error);
733 * Convert modify-header set TTL action to DV specification.
735 * @param[in,out] resource
736 * Pointer to the modify-header resource.
738 * Pointer to action specification.
740 * Pointer to rte_flow_item objects list.
742 * Pointer to flow attributes structure.
743 * @param[in] dev_flow
744 * Pointer to the sub flow.
745 * @param[in] tunnel_decap
746 * Whether action is after tunnel decapsulation.
748 * Pointer to the error structure.
751 * 0 on success, a negative errno value otherwise and rte_errno is set.
754 flow_dv_convert_action_modify_ttl
755 (struct mlx5_flow_dv_modify_hdr_resource *resource,
756 const struct rte_flow_action *action,
757 const struct rte_flow_item *items,
758 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
759 bool tunnel_decap, struct rte_flow_error *error)
761 const struct rte_flow_action_set_ttl *conf =
762 (const struct rte_flow_action_set_ttl *)(action->conf);
763 struct rte_flow_item item;
764 struct rte_flow_item_ipv4 ipv4;
765 struct rte_flow_item_ipv4 ipv4_mask;
766 struct rte_flow_item_ipv6 ipv6;
767 struct rte_flow_item_ipv6 ipv6_mask;
768 struct field_modify_info *field;
771 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
773 memset(&ipv4, 0, sizeof(ipv4));
774 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
775 ipv4.hdr.time_to_live = conf->ttl_value;
776 ipv4_mask.hdr.time_to_live = 0xFF;
777 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
779 item.mask = &ipv4_mask;
782 MLX5_ASSERT(attr->ipv6);
783 memset(&ipv6, 0, sizeof(ipv6));
784 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
785 ipv6.hdr.hop_limits = conf->ttl_value;
786 ipv6_mask.hdr.hop_limits = 0xFF;
787 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
789 item.mask = &ipv6_mask;
792 return flow_dv_convert_modify_action(&item, field, NULL, resource,
793 MLX5_MODIFICATION_TYPE_SET, error);
797 * Convert modify-header decrement TTL action to DV specification.
799 * @param[in,out] resource
800 * Pointer to the modify-header resource.
802 * Pointer to action specification.
804 * Pointer to rte_flow_item objects list.
806 * Pointer to flow attributes structure.
807 * @param[in] dev_flow
808 * Pointer to the sub flow.
809 * @param[in] tunnel_decap
810 * Whether action is after tunnel decapsulation.
812 * Pointer to the error structure.
815 * 0 on success, a negative errno value otherwise and rte_errno is set.
818 flow_dv_convert_action_modify_dec_ttl
819 (struct mlx5_flow_dv_modify_hdr_resource *resource,
820 const struct rte_flow_item *items,
821 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
822 bool tunnel_decap, struct rte_flow_error *error)
824 struct rte_flow_item item;
825 struct rte_flow_item_ipv4 ipv4;
826 struct rte_flow_item_ipv4 ipv4_mask;
827 struct rte_flow_item_ipv6 ipv6;
828 struct rte_flow_item_ipv6 ipv6_mask;
829 struct field_modify_info *field;
832 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
834 memset(&ipv4, 0, sizeof(ipv4));
835 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
836 ipv4.hdr.time_to_live = 0xFF;
837 ipv4_mask.hdr.time_to_live = 0xFF;
838 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
840 item.mask = &ipv4_mask;
843 MLX5_ASSERT(attr->ipv6);
844 memset(&ipv6, 0, sizeof(ipv6));
845 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
846 ipv6.hdr.hop_limits = 0xFF;
847 ipv6_mask.hdr.hop_limits = 0xFF;
848 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
850 item.mask = &ipv6_mask;
853 return flow_dv_convert_modify_action(&item, field, NULL, resource,
854 MLX5_MODIFICATION_TYPE_ADD, error);
858 * Convert modify-header increment/decrement TCP Sequence number
859 * to DV specification.
861 * @param[in,out] resource
862 * Pointer to the modify-header resource.
864 * Pointer to action specification.
866 * Pointer to the error structure.
869 * 0 on success, a negative errno value otherwise and rte_errno is set.
872 flow_dv_convert_action_modify_tcp_seq
873 (struct mlx5_flow_dv_modify_hdr_resource *resource,
874 const struct rte_flow_action *action,
875 struct rte_flow_error *error)
877 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
878 uint64_t value = rte_be_to_cpu_32(*conf);
879 struct rte_flow_item item;
880 struct rte_flow_item_tcp tcp;
881 struct rte_flow_item_tcp tcp_mask;
883 memset(&tcp, 0, sizeof(tcp));
884 memset(&tcp_mask, 0, sizeof(tcp_mask));
885 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
887 * The HW has no decrement operation, only increment operation.
888 * To simulate decrement X from Y using increment operation
889 * we need to add UINT32_MAX X times to Y.
890 * Each adding of UINT32_MAX decrements Y by 1.
893 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
894 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
895 item.type = RTE_FLOW_ITEM_TYPE_TCP;
897 item.mask = &tcp_mask;
898 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
899 MLX5_MODIFICATION_TYPE_ADD, error);
903 * Convert modify-header increment/decrement TCP Acknowledgment number
904 * to DV specification.
906 * @param[in,out] resource
907 * Pointer to the modify-header resource.
909 * Pointer to action specification.
911 * Pointer to the error structure.
914 * 0 on success, a negative errno value otherwise and rte_errno is set.
917 flow_dv_convert_action_modify_tcp_ack
918 (struct mlx5_flow_dv_modify_hdr_resource *resource,
919 const struct rte_flow_action *action,
920 struct rte_flow_error *error)
922 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
923 uint64_t value = rte_be_to_cpu_32(*conf);
924 struct rte_flow_item item;
925 struct rte_flow_item_tcp tcp;
926 struct rte_flow_item_tcp tcp_mask;
928 memset(&tcp, 0, sizeof(tcp));
929 memset(&tcp_mask, 0, sizeof(tcp_mask));
930 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
932 * The HW has no decrement operation, only increment operation.
933 * To simulate decrement X from Y using increment operation
934 * we need to add UINT32_MAX X times to Y.
935 * Each adding of UINT32_MAX decrements Y by 1.
938 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
939 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
940 item.type = RTE_FLOW_ITEM_TYPE_TCP;
942 item.mask = &tcp_mask;
943 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
944 MLX5_MODIFICATION_TYPE_ADD, error);
947 static enum mlx5_modification_field reg_to_field[] = {
948 [REG_NONE] = MLX5_MODI_OUT_NONE,
949 [REG_A] = MLX5_MODI_META_DATA_REG_A,
950 [REG_B] = MLX5_MODI_META_DATA_REG_B,
951 [REG_C_0] = MLX5_MODI_META_REG_C_0,
952 [REG_C_1] = MLX5_MODI_META_REG_C_1,
953 [REG_C_2] = MLX5_MODI_META_REG_C_2,
954 [REG_C_3] = MLX5_MODI_META_REG_C_3,
955 [REG_C_4] = MLX5_MODI_META_REG_C_4,
956 [REG_C_5] = MLX5_MODI_META_REG_C_5,
957 [REG_C_6] = MLX5_MODI_META_REG_C_6,
958 [REG_C_7] = MLX5_MODI_META_REG_C_7,
962 * Convert register set to DV specification.
964 * @param[in,out] resource
965 * Pointer to the modify-header resource.
967 * Pointer to action specification.
969 * Pointer to the error structure.
972 * 0 on success, a negative errno value otherwise and rte_errno is set.
975 flow_dv_convert_action_set_reg
976 (struct mlx5_flow_dv_modify_hdr_resource *resource,
977 const struct rte_flow_action *action,
978 struct rte_flow_error *error)
980 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
981 struct mlx5_modification_cmd *actions = resource->actions;
982 uint32_t i = resource->actions_num;
984 if (i >= MLX5_MAX_MODIFY_NUM)
985 return rte_flow_error_set(error, EINVAL,
986 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
987 "too many items to modify");
988 MLX5_ASSERT(conf->id != REG_NONE);
989 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
990 actions[i] = (struct mlx5_modification_cmd) {
991 .action_type = MLX5_MODIFICATION_TYPE_SET,
992 .field = reg_to_field[conf->id],
994 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
995 actions[i].data1 = rte_cpu_to_be_32(conf->data);
997 resource->actions_num = i;
1002 * Convert SET_TAG action to DV specification.
1005 * Pointer to the rte_eth_dev structure.
1006 * @param[in,out] resource
1007 * Pointer to the modify-header resource.
1009 * Pointer to action specification.
1011 * Pointer to the error structure.
1014 * 0 on success, a negative errno value otherwise and rte_errno is set.
1017 flow_dv_convert_action_set_tag
1018 (struct rte_eth_dev *dev,
1019 struct mlx5_flow_dv_modify_hdr_resource *resource,
1020 const struct rte_flow_action_set_tag *conf,
1021 struct rte_flow_error *error)
1023 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1024 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1025 struct rte_flow_item item = {
1029 struct field_modify_info reg_c_x[] = {
1032 enum mlx5_modification_field reg_type;
1035 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038 MLX5_ASSERT(ret != REG_NONE);
1039 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1040 reg_type = reg_to_field[ret];
1041 MLX5_ASSERT(reg_type > 0);
1042 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1043 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1044 MLX5_MODIFICATION_TYPE_SET, error);
1048 * Convert internal COPY_REG action to DV specification.
1051 * Pointer to the rte_eth_dev structure.
1052 * @param[in,out] res
1053 * Pointer to the modify-header resource.
1055 * Pointer to action specification.
1057 * Pointer to the error structure.
1060 * 0 on success, a negative errno value otherwise and rte_errno is set.
1063 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1064 struct mlx5_flow_dv_modify_hdr_resource *res,
1065 const struct rte_flow_action *action,
1066 struct rte_flow_error *error)
1068 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1069 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1070 struct rte_flow_item item = {
1074 struct field_modify_info reg_src[] = {
1075 {4, 0, reg_to_field[conf->src]},
1078 struct field_modify_info reg_dst = {
1080 .id = reg_to_field[conf->dst],
1082 /* Adjust reg_c[0] usage according to reported mask. */
1083 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1084 struct mlx5_priv *priv = dev->data->dev_private;
1085 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1087 MLX5_ASSERT(reg_c0);
1088 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1089 if (conf->dst == REG_C_0) {
1090 /* Copy to reg_c[0], within mask only. */
1091 reg_dst.offset = rte_bsf32(reg_c0);
1093 * Mask is ignoring the enianness, because
1094 * there is no conversion in datapath.
1096 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1097 /* Copy from destination lower bits to reg_c[0]. */
1098 mask = reg_c0 >> reg_dst.offset;
1100 /* Copy from destination upper bits to reg_c[0]. */
1101 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1102 rte_fls_u32(reg_c0));
1105 mask = rte_cpu_to_be_32(reg_c0);
1106 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1107 /* Copy from reg_c[0] to destination lower bits. */
1110 /* Copy from reg_c[0] to destination upper bits. */
1111 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1112 (rte_fls_u32(reg_c0) -
1117 return flow_dv_convert_modify_action(&item,
1118 reg_src, ®_dst, res,
1119 MLX5_MODIFICATION_TYPE_COPY,
1124 * Convert MARK action to DV specification. This routine is used
1125 * in extensive metadata only and requires metadata register to be
1126 * handled. In legacy mode hardware tag resource is engaged.
1129 * Pointer to the rte_eth_dev structure.
1131 * Pointer to MARK action specification.
1132 * @param[in,out] resource
1133 * Pointer to the modify-header resource.
1135 * Pointer to the error structure.
1138 * 0 on success, a negative errno value otherwise and rte_errno is set.
1141 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1142 const struct rte_flow_action_mark *conf,
1143 struct mlx5_flow_dv_modify_hdr_resource *resource,
1144 struct rte_flow_error *error)
1146 struct mlx5_priv *priv = dev->data->dev_private;
1147 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1148 priv->sh->dv_mark_mask);
1149 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1150 struct rte_flow_item item = {
1154 struct field_modify_info reg_c_x[] = {
1155 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1161 return rte_flow_error_set(error, EINVAL,
1162 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1163 NULL, "zero mark action mask");
1164 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167 MLX5_ASSERT(reg > 0);
1168 if (reg == REG_C_0) {
1169 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1170 uint32_t shl_c0 = rte_bsf32(msk_c0);
1172 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1173 mask = rte_cpu_to_be_32(mask) & msk_c0;
1174 mask = rte_cpu_to_be_32(mask << shl_c0);
1176 reg_c_x[0].id = reg_to_field[reg];
1177 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1178 MLX5_MODIFICATION_TYPE_SET, error);
1182 * Get metadata register index for specified steering domain.
1185 * Pointer to the rte_eth_dev structure.
1187 * Attributes of flow to determine steering domain.
1189 * Pointer to the error structure.
1192 * positive index on success, a negative errno value otherwise
1193 * and rte_errno is set.
1195 static enum modify_reg
1196 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1197 const struct rte_flow_attr *attr,
1198 struct rte_flow_error *error)
1201 mlx5_flow_get_reg_id(dev, attr->transfer ?
1205 MLX5_METADATA_RX, 0, error);
1207 return rte_flow_error_set(error,
1208 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1209 NULL, "unavailable "
1210 "metadata register");
1215 * Convert SET_META action to DV specification.
1218 * Pointer to the rte_eth_dev structure.
1219 * @param[in,out] resource
1220 * Pointer to the modify-header resource.
1222 * Attributes of flow that includes this item.
1224 * Pointer to action specification.
1226 * Pointer to the error structure.
1229 * 0 on success, a negative errno value otherwise and rte_errno is set.
1232 flow_dv_convert_action_set_meta
1233 (struct rte_eth_dev *dev,
1234 struct mlx5_flow_dv_modify_hdr_resource *resource,
1235 const struct rte_flow_attr *attr,
1236 const struct rte_flow_action_set_meta *conf,
1237 struct rte_flow_error *error)
1239 uint32_t data = conf->data;
1240 uint32_t mask = conf->mask;
1241 struct rte_flow_item item = {
1245 struct field_modify_info reg_c_x[] = {
1248 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1253 * In datapath code there is no endianness
1254 * coversions for perfromance reasons, all
1255 * pattern conversions are done in rte_flow.
1257 if (reg == REG_C_0) {
1258 struct mlx5_priv *priv = dev->data->dev_private;
1259 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262 MLX5_ASSERT(msk_c0);
1263 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1264 shl_c0 = rte_bsf32(msk_c0);
1266 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1270 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1272 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1273 /* The routine expects parameters in memory as big-endian ones. */
1274 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1275 MLX5_MODIFICATION_TYPE_SET, error);
1279 * Convert modify-header set IPv4 DSCP action to DV specification.
1281 * @param[in,out] resource
1282 * Pointer to the modify-header resource.
1284 * Pointer to action specification.
1286 * Pointer to the error structure.
1289 * 0 on success, a negative errno value otherwise and rte_errno is set.
1292 flow_dv_convert_action_modify_ipv4_dscp
1293 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1294 const struct rte_flow_action *action,
1295 struct rte_flow_error *error)
1297 const struct rte_flow_action_set_dscp *conf =
1298 (const struct rte_flow_action_set_dscp *)(action->conf);
1299 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1300 struct rte_flow_item_ipv4 ipv4;
1301 struct rte_flow_item_ipv4 ipv4_mask;
1303 memset(&ipv4, 0, sizeof(ipv4));
1304 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1305 ipv4.hdr.type_of_service = conf->dscp;
1306 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1308 item.mask = &ipv4_mask;
1309 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1310 MLX5_MODIFICATION_TYPE_SET, error);
1314 * Convert modify-header set IPv6 DSCP action to DV specification.
1316 * @param[in,out] resource
1317 * Pointer to the modify-header resource.
1319 * Pointer to action specification.
1321 * Pointer to the error structure.
1324 * 0 on success, a negative errno value otherwise and rte_errno is set.
1327 flow_dv_convert_action_modify_ipv6_dscp
1328 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1329 const struct rte_flow_action *action,
1330 struct rte_flow_error *error)
1332 const struct rte_flow_action_set_dscp *conf =
1333 (const struct rte_flow_action_set_dscp *)(action->conf);
1334 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1335 struct rte_flow_item_ipv6 ipv6;
1336 struct rte_flow_item_ipv6 ipv6_mask;
1338 memset(&ipv6, 0, sizeof(ipv6));
1339 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1341 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1342 * rdma-core only accept the DSCP bits byte aligned start from
1343 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1344 * bits in IPv6 case as rdma-core requires byte aligned value.
1346 ipv6.hdr.vtc_flow = conf->dscp;
1347 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1349 item.mask = &ipv6_mask;
1350 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1351 MLX5_MODIFICATION_TYPE_SET, error);
1355 * Validate MARK item.
1358 * Pointer to the rte_eth_dev structure.
1360 * Item specification.
1362 * Attributes of flow that includes this item.
1364 * Pointer to error structure.
1367 * 0 on success, a negative errno value otherwise and rte_errno is set.
1370 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1371 const struct rte_flow_item *item,
1372 const struct rte_flow_attr *attr __rte_unused,
1373 struct rte_flow_error *error)
1375 struct mlx5_priv *priv = dev->data->dev_private;
1376 struct mlx5_dev_config *config = &priv->config;
1377 const struct rte_flow_item_mark *spec = item->spec;
1378 const struct rte_flow_item_mark *mask = item->mask;
1379 const struct rte_flow_item_mark nic_mask = {
1380 .id = priv->sh->dv_mark_mask,
1384 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1385 return rte_flow_error_set(error, ENOTSUP,
1386 RTE_FLOW_ERROR_TYPE_ITEM, item,
1387 "extended metadata feature"
1389 if (!mlx5_flow_ext_mreg_supported(dev))
1390 return rte_flow_error_set(error, ENOTSUP,
1391 RTE_FLOW_ERROR_TYPE_ITEM, item,
1392 "extended metadata register"
1393 " isn't supported");
1395 return rte_flow_error_set(error, ENOTSUP,
1396 RTE_FLOW_ERROR_TYPE_ITEM, item,
1397 "extended metadata register"
1398 " isn't available");
1399 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1403 return rte_flow_error_set(error, EINVAL,
1404 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1406 "data cannot be empty");
1407 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1408 return rte_flow_error_set(error, EINVAL,
1409 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1411 "mark id exceeds the limit");
1415 return rte_flow_error_set(error, EINVAL,
1416 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1417 "mask cannot be zero");
1419 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1420 (const uint8_t *)&nic_mask,
1421 sizeof(struct rte_flow_item_mark),
1429 * Validate META item.
1432 * Pointer to the rte_eth_dev structure.
1434 * Item specification.
1436 * Attributes of flow that includes this item.
1438 * Pointer to error structure.
1441 * 0 on success, a negative errno value otherwise and rte_errno is set.
1444 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1445 const struct rte_flow_item *item,
1446 const struct rte_flow_attr *attr,
1447 struct rte_flow_error *error)
1449 struct mlx5_priv *priv = dev->data->dev_private;
1450 struct mlx5_dev_config *config = &priv->config;
1451 const struct rte_flow_item_meta *spec = item->spec;
1452 const struct rte_flow_item_meta *mask = item->mask;
1453 struct rte_flow_item_meta nic_mask = {
1460 return rte_flow_error_set(error, EINVAL,
1461 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1463 "data cannot be empty");
1464 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1465 if (!mlx5_flow_ext_mreg_supported(dev))
1466 return rte_flow_error_set(error, ENOTSUP,
1467 RTE_FLOW_ERROR_TYPE_ITEM, item,
1468 "extended metadata register"
1469 " isn't supported");
1470 reg = flow_dv_get_metadata_reg(dev, attr, error);
1474 return rte_flow_error_set(error, ENOTSUP,
1475 RTE_FLOW_ERROR_TYPE_ITEM, item,
1479 nic_mask.data = priv->sh->dv_meta_mask;
1480 } else if (attr->transfer) {
1481 return rte_flow_error_set(error, ENOTSUP,
1482 RTE_FLOW_ERROR_TYPE_ITEM, item,
1483 "extended metadata feature "
1484 "should be enabled when "
1485 "meta item is requested "
1486 "with e-switch mode ");
1489 mask = &rte_flow_item_meta_mask;
1491 return rte_flow_error_set(error, EINVAL,
1492 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1493 "mask cannot be zero");
1495 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1496 (const uint8_t *)&nic_mask,
1497 sizeof(struct rte_flow_item_meta),
1503 * Validate TAG item.
1506 * Pointer to the rte_eth_dev structure.
1508 * Item specification.
1510 * Attributes of flow that includes this item.
1512 * Pointer to error structure.
1515 * 0 on success, a negative errno value otherwise and rte_errno is set.
1518 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1519 const struct rte_flow_item *item,
1520 const struct rte_flow_attr *attr __rte_unused,
1521 struct rte_flow_error *error)
1523 const struct rte_flow_item_tag *spec = item->spec;
1524 const struct rte_flow_item_tag *mask = item->mask;
1525 const struct rte_flow_item_tag nic_mask = {
1526 .data = RTE_BE32(UINT32_MAX),
1531 if (!mlx5_flow_ext_mreg_supported(dev))
1532 return rte_flow_error_set(error, ENOTSUP,
1533 RTE_FLOW_ERROR_TYPE_ITEM, item,
1534 "extensive metadata register"
1535 " isn't supported");
1537 return rte_flow_error_set(error, EINVAL,
1538 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1540 "data cannot be empty");
1542 mask = &rte_flow_item_tag_mask;
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1546 "mask cannot be zero");
1548 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1549 (const uint8_t *)&nic_mask,
1550 sizeof(struct rte_flow_item_tag),
1554 if (mask->index != 0xff)
1555 return rte_flow_error_set(error, EINVAL,
1556 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1557 "partial mask for tag index"
1558 " is not supported");
1559 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1562 MLX5_ASSERT(ret != REG_NONE);
1567 * Validate vport item.
1570 * Pointer to the rte_eth_dev structure.
1572 * Item specification.
1574 * Attributes of flow that includes this item.
1575 * @param[in] item_flags
1576 * Bit-fields that holds the items detected until now.
1578 * Pointer to error structure.
1581 * 0 on success, a negative errno value otherwise and rte_errno is set.
1584 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1585 const struct rte_flow_item *item,
1586 const struct rte_flow_attr *attr,
1587 uint64_t item_flags,
1588 struct rte_flow_error *error)
1590 const struct rte_flow_item_port_id *spec = item->spec;
1591 const struct rte_flow_item_port_id *mask = item->mask;
1592 const struct rte_flow_item_port_id switch_mask = {
1595 struct mlx5_priv *esw_priv;
1596 struct mlx5_priv *dev_priv;
1599 if (!attr->transfer)
1600 return rte_flow_error_set(error, EINVAL,
1601 RTE_FLOW_ERROR_TYPE_ITEM,
1603 "match on port id is valid only"
1604 " when transfer flag is enabled");
1605 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1606 return rte_flow_error_set(error, ENOTSUP,
1607 RTE_FLOW_ERROR_TYPE_ITEM, item,
1608 "multiple source ports are not"
1611 mask = &switch_mask;
1612 if (mask->id != 0xffffffff)
1613 return rte_flow_error_set(error, ENOTSUP,
1614 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1616 "no support for partial mask on"
1618 ret = mlx5_flow_item_acceptable
1619 (item, (const uint8_t *)mask,
1620 (const uint8_t *)&rte_flow_item_port_id_mask,
1621 sizeof(struct rte_flow_item_port_id),
1627 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1629 return rte_flow_error_set(error, rte_errno,
1630 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1631 "failed to obtain E-Switch info for"
1633 dev_priv = mlx5_dev_to_eswitch_info(dev);
1635 return rte_flow_error_set(error, rte_errno,
1636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1638 "failed to obtain E-Switch info");
1639 if (esw_priv->domain_id != dev_priv->domain_id)
1640 return rte_flow_error_set(error, EINVAL,
1641 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1642 "cannot match on a port from a"
1643 " different E-Switch");
1648 * Validate VLAN item.
1651 * Item specification.
1652 * @param[in] item_flags
1653 * Bit-fields that holds the items detected until now.
1655 * Ethernet device flow is being created on.
1657 * Pointer to error structure.
1660 * 0 on success, a negative errno value otherwise and rte_errno is set.
1663 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1664 uint64_t item_flags,
1665 struct rte_eth_dev *dev,
1666 struct rte_flow_error *error)
1668 const struct rte_flow_item_vlan *mask = item->mask;
1669 const struct rte_flow_item_vlan nic_mask = {
1670 .tci = RTE_BE16(UINT16_MAX),
1671 .inner_type = RTE_BE16(UINT16_MAX),
1673 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1675 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1676 MLX5_FLOW_LAYER_INNER_L4) :
1677 (MLX5_FLOW_LAYER_OUTER_L3 |
1678 MLX5_FLOW_LAYER_OUTER_L4);
1679 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1680 MLX5_FLOW_LAYER_OUTER_VLAN;
1682 if (item_flags & vlanm)
1683 return rte_flow_error_set(error, EINVAL,
1684 RTE_FLOW_ERROR_TYPE_ITEM, item,
1685 "multiple VLAN layers not supported");
1686 else if ((item_flags & l34m) != 0)
1687 return rte_flow_error_set(error, EINVAL,
1688 RTE_FLOW_ERROR_TYPE_ITEM, item,
1689 "VLAN cannot follow L3/L4 layer");
1691 mask = &rte_flow_item_vlan_mask;
1692 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1693 (const uint8_t *)&nic_mask,
1694 sizeof(struct rte_flow_item_vlan),
1698 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1699 struct mlx5_priv *priv = dev->data->dev_private;
1701 if (priv->vmwa_context) {
1703 * Non-NULL context means we have a virtual machine
1704 * and SR-IOV enabled, we have to create VLAN interface
1705 * to make hypervisor to setup E-Switch vport
1706 * context correctly. We avoid creating the multiple
1707 * VLAN interfaces, so we cannot support VLAN tag mask.
1709 return rte_flow_error_set(error, EINVAL,
1710 RTE_FLOW_ERROR_TYPE_ITEM,
1712 "VLAN tag mask is not"
1713 " supported in virtual"
1721 * GTP flags are contained in 1 byte of the format:
1722 * -------------------------------------------
1723 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1724 * |-----------------------------------------|
1725 * | value | Version | PT | Res | E | S | PN |
1726 * -------------------------------------------
1728 * Matching is supported only for GTP flags E, S, PN.
1730 #define MLX5_GTP_FLAGS_MASK 0x07
1733 * Validate GTP item.
1736 * Pointer to the rte_eth_dev structure.
1738 * Item specification.
1739 * @param[in] item_flags
1740 * Bit-fields that holds the items detected until now.
1742 * Pointer to error structure.
1745 * 0 on success, a negative errno value otherwise and rte_errno is set.
1748 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1749 const struct rte_flow_item *item,
1750 uint64_t item_flags,
1751 struct rte_flow_error *error)
1753 struct mlx5_priv *priv = dev->data->dev_private;
1754 const struct rte_flow_item_gtp *spec = item->spec;
1755 const struct rte_flow_item_gtp *mask = item->mask;
1756 const struct rte_flow_item_gtp nic_mask = {
1757 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1759 .teid = RTE_BE32(0xffffffff),
1762 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1763 return rte_flow_error_set(error, ENOTSUP,
1764 RTE_FLOW_ERROR_TYPE_ITEM, item,
1765 "GTP support is not enabled");
1766 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1767 return rte_flow_error_set(error, ENOTSUP,
1768 RTE_FLOW_ERROR_TYPE_ITEM, item,
1769 "multiple tunnel layers not"
1771 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1772 return rte_flow_error_set(error, EINVAL,
1773 RTE_FLOW_ERROR_TYPE_ITEM, item,
1774 "no outer UDP layer found");
1776 mask = &rte_flow_item_gtp_mask;
1777 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1778 return rte_flow_error_set(error, ENOTSUP,
1779 RTE_FLOW_ERROR_TYPE_ITEM, item,
1780 "Match is supported for GTP"
1782 return mlx5_flow_item_acceptable
1783 (item, (const uint8_t *)mask,
1784 (const uint8_t *)&nic_mask,
1785 sizeof(struct rte_flow_item_gtp),
1790 * Validate the pop VLAN action.
1793 * Pointer to the rte_eth_dev structure.
1794 * @param[in] action_flags
1795 * Holds the actions detected until now.
1797 * Pointer to the pop vlan action.
1798 * @param[in] item_flags
1799 * The items found in this flow rule.
1801 * Pointer to flow attributes.
1803 * Pointer to error structure.
1806 * 0 on success, a negative errno value otherwise and rte_errno is set.
1809 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1810 uint64_t action_flags,
1811 const struct rte_flow_action *action,
1812 uint64_t item_flags,
1813 const struct rte_flow_attr *attr,
1814 struct rte_flow_error *error)
1816 const struct mlx5_priv *priv = dev->data->dev_private;
1820 if (!priv->sh->pop_vlan_action)
1821 return rte_flow_error_set(error, ENOTSUP,
1822 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1824 "pop vlan action is not supported");
1826 return rte_flow_error_set(error, ENOTSUP,
1827 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1829 "pop vlan action not supported for "
1831 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1832 return rte_flow_error_set(error, ENOTSUP,
1833 RTE_FLOW_ERROR_TYPE_ACTION, action,
1834 "no support for multiple VLAN "
1836 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
1837 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
1838 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
1839 return rte_flow_error_set(error, ENOTSUP,
1840 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1842 "cannot pop vlan after decap without "
1843 "match on inner vlan in the flow");
1844 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
1845 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
1846 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1850 "cannot pop vlan without a "
1851 "match on (outer) vlan in the flow");
1852 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1853 return rte_flow_error_set(error, EINVAL,
1854 RTE_FLOW_ERROR_TYPE_ACTION, action,
1855 "wrong action order, port_id should "
1856 "be after pop VLAN action");
1857 if (!attr->transfer && priv->representor)
1858 return rte_flow_error_set(error, ENOTSUP,
1859 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1860 "pop vlan action for VF representor "
1861 "not supported on NIC table");
1866 * Get VLAN default info from vlan match info.
1869 * the list of item specifications.
1871 * pointer VLAN info to fill to.
1874 * 0 on success, a negative errno value otherwise and rte_errno is set.
1877 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1878 struct rte_vlan_hdr *vlan)
1880 const struct rte_flow_item_vlan nic_mask = {
1881 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1882 MLX5DV_FLOW_VLAN_VID_MASK),
1883 .inner_type = RTE_BE16(0xffff),
1888 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1889 int type = items->type;
1891 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1892 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1895 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1896 const struct rte_flow_item_vlan *vlan_m = items->mask;
1897 const struct rte_flow_item_vlan *vlan_v = items->spec;
1899 /* If VLAN item in pattern doesn't contain data, return here. */
1904 /* Only full match values are accepted */
1905 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1906 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1907 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1909 rte_be_to_cpu_16(vlan_v->tci &
1910 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1912 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1913 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1914 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1916 rte_be_to_cpu_16(vlan_v->tci &
1917 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1919 if (vlan_m->inner_type == nic_mask.inner_type)
1920 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1921 vlan_m->inner_type);
1926 * Validate the push VLAN action.
1929 * Pointer to the rte_eth_dev structure.
1930 * @param[in] action_flags
1931 * Holds the actions detected until now.
1932 * @param[in] item_flags
1933 * The items found in this flow rule.
1935 * Pointer to the action structure.
1937 * Pointer to flow attributes
1939 * Pointer to error structure.
1942 * 0 on success, a negative errno value otherwise and rte_errno is set.
1945 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1946 uint64_t action_flags,
1947 const struct rte_flow_item_vlan *vlan_m,
1948 const struct rte_flow_action *action,
1949 const struct rte_flow_attr *attr,
1950 struct rte_flow_error *error)
1952 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1953 const struct mlx5_priv *priv = dev->data->dev_private;
1955 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1956 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1957 return rte_flow_error_set(error, EINVAL,
1958 RTE_FLOW_ERROR_TYPE_ACTION, action,
1959 "invalid vlan ethertype");
1960 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1961 return rte_flow_error_set(error, EINVAL,
1962 RTE_FLOW_ERROR_TYPE_ACTION, action,
1963 "wrong action order, port_id should "
1964 "be after push VLAN");
1965 if (!attr->transfer && priv->representor)
1966 return rte_flow_error_set(error, ENOTSUP,
1967 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1968 "push vlan action for VF representor "
1969 "not supported on NIC table");
1971 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1972 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1973 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1974 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1975 !(mlx5_flow_find_action
1976 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1977 return rte_flow_error_set(error, EINVAL,
1978 RTE_FLOW_ERROR_TYPE_ACTION, action,
1979 "not full match mask on VLAN PCP and "
1980 "there is no of_set_vlan_pcp action, "
1981 "push VLAN action cannot figure out "
1984 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1985 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1986 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1987 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1988 !(mlx5_flow_find_action
1989 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1990 return rte_flow_error_set(error, EINVAL,
1991 RTE_FLOW_ERROR_TYPE_ACTION, action,
1992 "not full match mask on VLAN VID and "
1993 "there is no of_set_vlan_vid action, "
1994 "push VLAN action cannot figure out "
2001 * Validate the set VLAN PCP.
2003 * @param[in] action_flags
2004 * Holds the actions detected until now.
2005 * @param[in] actions
2006 * Pointer to the list of actions remaining in the flow rule.
2008 * Pointer to error structure.
2011 * 0 on success, a negative errno value otherwise and rte_errno is set.
2014 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2015 const struct rte_flow_action actions[],
2016 struct rte_flow_error *error)
2018 const struct rte_flow_action *action = actions;
2019 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2021 if (conf->vlan_pcp > 7)
2022 return rte_flow_error_set(error, EINVAL,
2023 RTE_FLOW_ERROR_TYPE_ACTION, action,
2024 "VLAN PCP value is too big");
2025 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ACTION, action,
2028 "set VLAN PCP action must follow "
2029 "the push VLAN action");
2030 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2031 return rte_flow_error_set(error, ENOTSUP,
2032 RTE_FLOW_ERROR_TYPE_ACTION, action,
2033 "Multiple VLAN PCP modification are "
2035 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2036 return rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ACTION, action,
2038 "wrong action order, port_id should "
2039 "be after set VLAN PCP");
2044 * Validate the set VLAN VID.
2046 * @param[in] item_flags
2047 * Holds the items detected in this rule.
2048 * @param[in] action_flags
2049 * Holds the actions detected until now.
2050 * @param[in] actions
2051 * Pointer to the list of actions remaining in the flow rule.
2053 * Pointer to error structure.
2056 * 0 on success, a negative errno value otherwise and rte_errno is set.
2059 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2060 uint64_t action_flags,
2061 const struct rte_flow_action actions[],
2062 struct rte_flow_error *error)
2064 const struct rte_flow_action *action = actions;
2065 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2067 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2068 return rte_flow_error_set(error, EINVAL,
2069 RTE_FLOW_ERROR_TYPE_ACTION, action,
2070 "VLAN VID value is too big");
2071 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2072 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2073 return rte_flow_error_set(error, ENOTSUP,
2074 RTE_FLOW_ERROR_TYPE_ACTION, action,
2075 "set VLAN VID action must follow push"
2076 " VLAN action or match on VLAN item");
2077 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2078 return rte_flow_error_set(error, ENOTSUP,
2079 RTE_FLOW_ERROR_TYPE_ACTION, action,
2080 "Multiple VLAN VID modifications are "
2082 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2083 return rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ACTION, action,
2085 "wrong action order, port_id should "
2086 "be after set VLAN VID");
2091 * Validate the FLAG action.
2094 * Pointer to the rte_eth_dev structure.
2095 * @param[in] action_flags
2096 * Holds the actions detected until now.
2098 * Pointer to flow attributes
2100 * Pointer to error structure.
2103 * 0 on success, a negative errno value otherwise and rte_errno is set.
2106 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2107 uint64_t action_flags,
2108 const struct rte_flow_attr *attr,
2109 struct rte_flow_error *error)
2111 struct mlx5_priv *priv = dev->data->dev_private;
2112 struct mlx5_dev_config *config = &priv->config;
2115 /* Fall back if no extended metadata register support. */
2116 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2117 return mlx5_flow_validate_action_flag(action_flags, attr,
2119 /* Extensive metadata mode requires registers. */
2120 if (!mlx5_flow_ext_mreg_supported(dev))
2121 return rte_flow_error_set(error, ENOTSUP,
2122 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2123 "no metadata registers "
2124 "to support flag action");
2125 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2126 return rte_flow_error_set(error, ENOTSUP,
2127 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2128 "extended metadata register"
2129 " isn't available");
2130 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2133 MLX5_ASSERT(ret > 0);
2134 if (action_flags & MLX5_FLOW_ACTION_MARK)
2135 return rte_flow_error_set(error, EINVAL,
2136 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137 "can't mark and flag in same flow");
2138 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2139 return rte_flow_error_set(error, EINVAL,
2140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2142 " actions in same flow");
2147 * Validate MARK action.
2150 * Pointer to the rte_eth_dev structure.
2152 * Pointer to action.
2153 * @param[in] action_flags
2154 * Holds the actions detected until now.
2156 * Pointer to flow attributes
2158 * Pointer to error structure.
2161 * 0 on success, a negative errno value otherwise and rte_errno is set.
2164 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2165 const struct rte_flow_action *action,
2166 uint64_t action_flags,
2167 const struct rte_flow_attr *attr,
2168 struct rte_flow_error *error)
2170 struct mlx5_priv *priv = dev->data->dev_private;
2171 struct mlx5_dev_config *config = &priv->config;
2172 const struct rte_flow_action_mark *mark = action->conf;
2175 /* Fall back if no extended metadata register support. */
2176 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2177 return mlx5_flow_validate_action_mark(action, action_flags,
2179 /* Extensive metadata mode requires registers. */
2180 if (!mlx5_flow_ext_mreg_supported(dev))
2181 return rte_flow_error_set(error, ENOTSUP,
2182 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2183 "no metadata registers "
2184 "to support mark action");
2185 if (!priv->sh->dv_mark_mask)
2186 return rte_flow_error_set(error, ENOTSUP,
2187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 "extended metadata register"
2189 " isn't available");
2190 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2193 MLX5_ASSERT(ret > 0);
2195 return rte_flow_error_set(error, EINVAL,
2196 RTE_FLOW_ERROR_TYPE_ACTION, action,
2197 "configuration cannot be null");
2198 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2199 return rte_flow_error_set(error, EINVAL,
2200 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2202 "mark id exceeds the limit");
2203 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2204 return rte_flow_error_set(error, EINVAL,
2205 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206 "can't flag and mark in same flow");
2207 if (action_flags & MLX5_FLOW_ACTION_MARK)
2208 return rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2210 "can't have 2 mark actions in same"
2216 * Validate SET_META action.
2219 * Pointer to the rte_eth_dev structure.
2221 * Pointer to the action structure.
2222 * @param[in] action_flags
2223 * Holds the actions detected until now.
2225 * Pointer to flow attributes
2227 * Pointer to error structure.
2230 * 0 on success, a negative errno value otherwise and rte_errno is set.
2233 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2234 const struct rte_flow_action *action,
2235 uint64_t action_flags __rte_unused,
2236 const struct rte_flow_attr *attr,
2237 struct rte_flow_error *error)
2239 const struct rte_flow_action_set_meta *conf;
2240 uint32_t nic_mask = UINT32_MAX;
2243 if (!mlx5_flow_ext_mreg_supported(dev))
2244 return rte_flow_error_set(error, ENOTSUP,
2245 RTE_FLOW_ERROR_TYPE_ACTION, action,
2246 "extended metadata register"
2247 " isn't supported");
2248 reg = flow_dv_get_metadata_reg(dev, attr, error);
2251 if (reg != REG_A && reg != REG_B) {
2252 struct mlx5_priv *priv = dev->data->dev_private;
2254 nic_mask = priv->sh->dv_meta_mask;
2256 if (!(action->conf))
2257 return rte_flow_error_set(error, EINVAL,
2258 RTE_FLOW_ERROR_TYPE_ACTION, action,
2259 "configuration cannot be null");
2260 conf = (const struct rte_flow_action_set_meta *)action->conf;
2262 return rte_flow_error_set(error, EINVAL,
2263 RTE_FLOW_ERROR_TYPE_ACTION, action,
2264 "zero mask doesn't have any effect");
2265 if (conf->mask & ~nic_mask)
2266 return rte_flow_error_set(error, EINVAL,
2267 RTE_FLOW_ERROR_TYPE_ACTION, action,
2268 "meta data must be within reg C0");
2273 * Validate SET_TAG action.
2276 * Pointer to the rte_eth_dev structure.
2278 * Pointer to the action structure.
2279 * @param[in] action_flags
2280 * Holds the actions detected until now.
2282 * Pointer to flow attributes
2284 * Pointer to error structure.
2287 * 0 on success, a negative errno value otherwise and rte_errno is set.
2290 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2291 const struct rte_flow_action *action,
2292 uint64_t action_flags,
2293 const struct rte_flow_attr *attr,
2294 struct rte_flow_error *error)
2296 const struct rte_flow_action_set_tag *conf;
2297 const uint64_t terminal_action_flags =
2298 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2299 MLX5_FLOW_ACTION_RSS;
2302 if (!mlx5_flow_ext_mreg_supported(dev))
2303 return rte_flow_error_set(error, ENOTSUP,
2304 RTE_FLOW_ERROR_TYPE_ACTION, action,
2305 "extensive metadata register"
2306 " isn't supported");
2307 if (!(action->conf))
2308 return rte_flow_error_set(error, EINVAL,
2309 RTE_FLOW_ERROR_TYPE_ACTION, action,
2310 "configuration cannot be null");
2311 conf = (const struct rte_flow_action_set_tag *)action->conf;
2313 return rte_flow_error_set(error, EINVAL,
2314 RTE_FLOW_ERROR_TYPE_ACTION, action,
2315 "zero mask doesn't have any effect");
2316 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2319 if (!attr->transfer && attr->ingress &&
2320 (action_flags & terminal_action_flags))
2321 return rte_flow_error_set(error, EINVAL,
2322 RTE_FLOW_ERROR_TYPE_ACTION, action,
2323 "set_tag has no effect"
2324 " with terminal actions");
2329 * Validate count action.
2332 * Pointer to rte_eth_dev structure.
2334 * Pointer to error structure.
2337 * 0 on success, a negative errno value otherwise and rte_errno is set.
2340 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2341 struct rte_flow_error *error)
2343 struct mlx5_priv *priv = dev->data->dev_private;
2345 if (!priv->config.devx)
2347 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2351 return rte_flow_error_set
2353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2355 "count action not supported");
2359 * Validate the L2 encap action.
2362 * Pointer to the rte_eth_dev structure.
2363 * @param[in] action_flags
2364 * Holds the actions detected until now.
2366 * Pointer to the action structure.
2368 * Pointer to flow attributes.
2370 * Pointer to error structure.
2373 * 0 on success, a negative errno value otherwise and rte_errno is set.
2376 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2377 uint64_t action_flags,
2378 const struct rte_flow_action *action,
2379 const struct rte_flow_attr *attr,
2380 struct rte_flow_error *error)
2382 const struct mlx5_priv *priv = dev->data->dev_private;
2384 if (!(action->conf))
2385 return rte_flow_error_set(error, EINVAL,
2386 RTE_FLOW_ERROR_TYPE_ACTION, action,
2387 "configuration cannot be null");
2388 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2389 return rte_flow_error_set(error, EINVAL,
2390 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391 "can only have a single encap action "
2393 if (!attr->transfer && priv->representor)
2394 return rte_flow_error_set(error, ENOTSUP,
2395 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2396 "encap action for VF representor "
2397 "not supported on NIC table");
2402 * Validate a decap action.
2405 * Pointer to the rte_eth_dev structure.
2406 * @param[in] action_flags
2407 * Holds the actions detected until now.
2409 * Pointer to flow attributes
2411 * Pointer to error structure.
2414 * 0 on success, a negative errno value otherwise and rte_errno is set.
2417 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2418 uint64_t action_flags,
2419 const struct rte_flow_attr *attr,
2420 struct rte_flow_error *error)
2422 const struct mlx5_priv *priv = dev->data->dev_private;
2424 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2425 !priv->config.decap_en)
2426 return rte_flow_error_set(error, ENOTSUP,
2427 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2428 "decap is not enabled");
2429 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2430 return rte_flow_error_set(error, ENOTSUP,
2431 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2433 MLX5_FLOW_ACTION_DECAP ? "can only "
2434 "have a single decap action" : "decap "
2435 "after encap is not supported");
2436 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2437 return rte_flow_error_set(error, EINVAL,
2438 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2439 "can't have decap action after"
2442 return rte_flow_error_set(error, ENOTSUP,
2443 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2445 "decap action not supported for "
2447 if (!attr->transfer && priv->representor)
2448 return rte_flow_error_set(error, ENOTSUP,
2449 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2450 "decap action for VF representor "
2451 "not supported on NIC table");
2455 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2458 * Validate the raw encap and decap actions.
2461 * Pointer to the rte_eth_dev structure.
2463 * Pointer to the decap action.
2465 * Pointer to the encap action.
2467 * Pointer to flow attributes
2468 * @param[in/out] action_flags
2469 * Holds the actions detected until now.
2470 * @param[out] actions_n
2471 * pointer to the number of actions counter.
2473 * Pointer to error structure.
2476 * 0 on success, a negative errno value otherwise and rte_errno is set.
2479 flow_dv_validate_action_raw_encap_decap
2480 (struct rte_eth_dev *dev,
2481 const struct rte_flow_action_raw_decap *decap,
2482 const struct rte_flow_action_raw_encap *encap,
2483 const struct rte_flow_attr *attr, uint64_t *action_flags,
2484 int *actions_n, struct rte_flow_error *error)
2486 const struct mlx5_priv *priv = dev->data->dev_private;
2489 if (encap && (!encap->size || !encap->data))
2490 return rte_flow_error_set(error, EINVAL,
2491 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2492 "raw encap data cannot be empty");
2493 if (decap && encap) {
2494 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2495 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2498 else if (encap->size <=
2499 MLX5_ENCAPSULATION_DECISION_SIZE &&
2501 MLX5_ENCAPSULATION_DECISION_SIZE)
2504 else if (encap->size >
2505 MLX5_ENCAPSULATION_DECISION_SIZE &&
2507 MLX5_ENCAPSULATION_DECISION_SIZE)
2508 /* 2 L2 actions: encap and decap. */
2511 return rte_flow_error_set(error,
2513 RTE_FLOW_ERROR_TYPE_ACTION,
2514 NULL, "unsupported too small "
2515 "raw decap and too small raw "
2516 "encap combination");
2519 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2523 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2527 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2528 return rte_flow_error_set(error, ENOTSUP,
2529 RTE_FLOW_ERROR_TYPE_ACTION,
2531 "small raw encap size");
2532 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2533 return rte_flow_error_set(error, EINVAL,
2534 RTE_FLOW_ERROR_TYPE_ACTION,
2536 "more than one encap action");
2537 if (!attr->transfer && priv->representor)
2538 return rte_flow_error_set
2540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2541 "encap action for VF representor "
2542 "not supported on NIC table");
2543 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2550 * Find existing encap/decap resource or create and register a new one.
2552 * @param[in, out] dev
2553 * Pointer to rte_eth_dev structure.
2554 * @param[in, out] resource
2555 * Pointer to encap/decap resource.
2556 * @parm[in, out] dev_flow
2557 * Pointer to the dev_flow.
2559 * pointer to error structure.
2562 * 0 on success otherwise -errno and errno is set.
2565 flow_dv_encap_decap_resource_register
2566 (struct rte_eth_dev *dev,
2567 struct mlx5_flow_dv_encap_decap_resource *resource,
2568 struct mlx5_flow *dev_flow,
2569 struct rte_flow_error *error)
2571 struct mlx5_priv *priv = dev->data->dev_private;
2572 struct mlx5_dev_ctx_shared *sh = priv->sh;
2573 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2574 struct mlx5dv_dr_domain *domain;
2578 resource->flags = dev_flow->dv.group ? 0 : 1;
2579 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2580 domain = sh->fdb_domain;
2581 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2582 domain = sh->rx_domain;
2584 domain = sh->tx_domain;
2585 /* Lookup a matching resource from cache. */
2586 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2587 cache_resource, next) {
2588 if (resource->reformat_type == cache_resource->reformat_type &&
2589 resource->ft_type == cache_resource->ft_type &&
2590 resource->flags == cache_resource->flags &&
2591 resource->size == cache_resource->size &&
2592 !memcmp((const void *)resource->buf,
2593 (const void *)cache_resource->buf,
2595 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2596 (void *)cache_resource,
2597 rte_atomic32_read(&cache_resource->refcnt));
2598 rte_atomic32_inc(&cache_resource->refcnt);
2599 dev_flow->handle->dvh.rix_encap_decap = idx;
2600 dev_flow->dv.encap_decap = cache_resource;
2604 /* Register new encap/decap resource. */
2605 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2606 &dev_flow->handle->dvh.rix_encap_decap);
2607 if (!cache_resource)
2608 return rte_flow_error_set(error, ENOMEM,
2609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2610 "cannot allocate resource memory");
2611 *cache_resource = *resource;
2612 ret = mlx5_flow_os_create_flow_action_packet_reformat
2613 (sh->ctx, domain, cache_resource,
2614 &cache_resource->action);
2616 mlx5_free(cache_resource);
2617 return rte_flow_error_set(error, ENOMEM,
2618 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2619 NULL, "cannot create action");
2621 rte_atomic32_init(&cache_resource->refcnt);
2622 rte_atomic32_inc(&cache_resource->refcnt);
2623 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2624 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2626 dev_flow->dv.encap_decap = cache_resource;
2627 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2628 (void *)cache_resource,
2629 rte_atomic32_read(&cache_resource->refcnt));
2634 * Find existing table jump resource or create and register a new one.
2636 * @param[in, out] dev
2637 * Pointer to rte_eth_dev structure.
2638 * @param[in, out] tbl
2639 * Pointer to flow table resource.
2640 * @parm[in, out] dev_flow
2641 * Pointer to the dev_flow.
2643 * pointer to error structure.
2646 * 0 on success otherwise -errno and errno is set.
2649 flow_dv_jump_tbl_resource_register
2650 (struct rte_eth_dev *dev __rte_unused,
2651 struct mlx5_flow_tbl_resource *tbl,
2652 struct mlx5_flow *dev_flow,
2653 struct rte_flow_error *error)
2655 struct mlx5_flow_tbl_data_entry *tbl_data =
2656 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2660 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2662 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2663 (tbl->obj, &tbl_data->jump.action);
2665 return rte_flow_error_set(error, ENOMEM,
2666 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2667 NULL, "cannot create jump action");
2668 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2669 (void *)&tbl_data->jump, cnt);
2671 /* old jump should not make the table ref++. */
2672 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2673 MLX5_ASSERT(tbl_data->jump.action);
2674 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2675 (void *)&tbl_data->jump, cnt);
2677 rte_atomic32_inc(&tbl_data->jump.refcnt);
2678 dev_flow->handle->rix_jump = tbl_data->idx;
2679 dev_flow->dv.jump = &tbl_data->jump;
2684 * Find existing default miss resource or create and register a new one.
2686 * @param[in, out] dev
2687 * Pointer to rte_eth_dev structure.
2689 * pointer to error structure.
2692 * 0 on success otherwise -errno and errno is set.
2695 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2696 struct rte_flow_error *error)
2698 struct mlx5_priv *priv = dev->data->dev_private;
2699 struct mlx5_dev_ctx_shared *sh = priv->sh;
2700 struct mlx5_flow_default_miss_resource *cache_resource =
2702 int cnt = rte_atomic32_read(&cache_resource->refcnt);
2705 MLX5_ASSERT(cache_resource->action);
2706 cache_resource->action =
2707 mlx5_glue->dr_create_flow_action_default_miss();
2708 if (!cache_resource->action)
2709 return rte_flow_error_set(error, ENOMEM,
2710 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2711 "cannot create default miss action");
2712 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2713 (void *)cache_resource->action, cnt);
2715 rte_atomic32_inc(&cache_resource->refcnt);
2720 * Find existing table port ID resource or create and register a new one.
2722 * @param[in, out] dev
2723 * Pointer to rte_eth_dev structure.
2724 * @param[in, out] resource
2725 * Pointer to port ID action resource.
2726 * @parm[in, out] dev_flow
2727 * Pointer to the dev_flow.
2729 * pointer to error structure.
2732 * 0 on success otherwise -errno and errno is set.
2735 flow_dv_port_id_action_resource_register
2736 (struct rte_eth_dev *dev,
2737 struct mlx5_flow_dv_port_id_action_resource *resource,
2738 struct mlx5_flow *dev_flow,
2739 struct rte_flow_error *error)
2741 struct mlx5_priv *priv = dev->data->dev_private;
2742 struct mlx5_dev_ctx_shared *sh = priv->sh;
2743 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2747 /* Lookup a matching resource from cache. */
2748 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2749 idx, cache_resource, next) {
2750 if (resource->port_id == cache_resource->port_id) {
2751 DRV_LOG(DEBUG, "port id action resource resource %p: "
2753 (void *)cache_resource,
2754 rte_atomic32_read(&cache_resource->refcnt));
2755 rte_atomic32_inc(&cache_resource->refcnt);
2756 dev_flow->handle->rix_port_id_action = idx;
2757 dev_flow->dv.port_id_action = cache_resource;
2761 /* Register new port id action resource. */
2762 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2763 &dev_flow->handle->rix_port_id_action);
2764 if (!cache_resource)
2765 return rte_flow_error_set(error, ENOMEM,
2766 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2767 "cannot allocate resource memory");
2768 *cache_resource = *resource;
2769 ret = mlx5_flow_os_create_flow_action_dest_port
2770 (priv->sh->fdb_domain, resource->port_id,
2771 &cache_resource->action);
2773 mlx5_free(cache_resource);
2774 return rte_flow_error_set(error, ENOMEM,
2775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2776 NULL, "cannot create action");
2778 rte_atomic32_init(&cache_resource->refcnt);
2779 rte_atomic32_inc(&cache_resource->refcnt);
2780 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2781 dev_flow->handle->rix_port_id_action, cache_resource,
2783 dev_flow->dv.port_id_action = cache_resource;
2784 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2785 (void *)cache_resource,
2786 rte_atomic32_read(&cache_resource->refcnt));
2791 * Find existing push vlan resource or create and register a new one.
2793 * @param [in, out] dev
2794 * Pointer to rte_eth_dev structure.
2795 * @param[in, out] resource
2796 * Pointer to port ID action resource.
2797 * @parm[in, out] dev_flow
2798 * Pointer to the dev_flow.
2800 * pointer to error structure.
2803 * 0 on success otherwise -errno and errno is set.
2806 flow_dv_push_vlan_action_resource_register
2807 (struct rte_eth_dev *dev,
2808 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2809 struct mlx5_flow *dev_flow,
2810 struct rte_flow_error *error)
2812 struct mlx5_priv *priv = dev->data->dev_private;
2813 struct mlx5_dev_ctx_shared *sh = priv->sh;
2814 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2815 struct mlx5dv_dr_domain *domain;
2819 /* Lookup a matching resource from cache. */
2820 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821 sh->push_vlan_action_list, idx, cache_resource, next) {
2822 if (resource->vlan_tag == cache_resource->vlan_tag &&
2823 resource->ft_type == cache_resource->ft_type) {
2824 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2826 (void *)cache_resource,
2827 rte_atomic32_read(&cache_resource->refcnt));
2828 rte_atomic32_inc(&cache_resource->refcnt);
2829 dev_flow->handle->dvh.rix_push_vlan = idx;
2830 dev_flow->dv.push_vlan_res = cache_resource;
2834 /* Register new push_vlan action resource. */
2835 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2836 &dev_flow->handle->dvh.rix_push_vlan);
2837 if (!cache_resource)
2838 return rte_flow_error_set(error, ENOMEM,
2839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2840 "cannot allocate resource memory");
2841 *cache_resource = *resource;
2842 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2843 domain = sh->fdb_domain;
2844 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2845 domain = sh->rx_domain;
2847 domain = sh->tx_domain;
2848 ret = mlx5_flow_os_create_flow_action_push_vlan
2849 (domain, resource->vlan_tag,
2850 &cache_resource->action);
2852 mlx5_free(cache_resource);
2853 return rte_flow_error_set(error, ENOMEM,
2854 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2855 NULL, "cannot create action");
2857 rte_atomic32_init(&cache_resource->refcnt);
2858 rte_atomic32_inc(&cache_resource->refcnt);
2859 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2860 &sh->push_vlan_action_list,
2861 dev_flow->handle->dvh.rix_push_vlan,
2862 cache_resource, next);
2863 dev_flow->dv.push_vlan_res = cache_resource;
2864 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2865 (void *)cache_resource,
2866 rte_atomic32_read(&cache_resource->refcnt));
2870 * Get the size of specific rte_flow_item_type hdr size
2872 * @param[in] item_type
2873 * Tested rte_flow_item_type.
2876 * sizeof struct item_type, 0 if void or irrelevant.
2879 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
2883 switch (item_type) {
2884 case RTE_FLOW_ITEM_TYPE_ETH:
2885 retval = sizeof(struct rte_ether_hdr);
2887 case RTE_FLOW_ITEM_TYPE_VLAN:
2888 retval = sizeof(struct rte_vlan_hdr);
2890 case RTE_FLOW_ITEM_TYPE_IPV4:
2891 retval = sizeof(struct rte_ipv4_hdr);
2893 case RTE_FLOW_ITEM_TYPE_IPV6:
2894 retval = sizeof(struct rte_ipv6_hdr);
2896 case RTE_FLOW_ITEM_TYPE_UDP:
2897 retval = sizeof(struct rte_udp_hdr);
2899 case RTE_FLOW_ITEM_TYPE_TCP:
2900 retval = sizeof(struct rte_tcp_hdr);
2902 case RTE_FLOW_ITEM_TYPE_VXLAN:
2903 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2904 retval = sizeof(struct rte_vxlan_hdr);
2906 case RTE_FLOW_ITEM_TYPE_GRE:
2907 case RTE_FLOW_ITEM_TYPE_NVGRE:
2908 retval = sizeof(struct rte_gre_hdr);
2910 case RTE_FLOW_ITEM_TYPE_MPLS:
2911 retval = sizeof(struct rte_mpls_hdr);
2913 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2921 #define MLX5_ENCAP_IPV4_VERSION 0x40
2922 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2923 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2924 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2925 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2926 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2927 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2930 * Convert the encap action data from list of rte_flow_item to raw buffer
2933 * Pointer to rte_flow_item objects list.
2935 * Pointer to the output buffer.
2937 * Pointer to the output buffer size.
2939 * Pointer to the error structure.
2942 * 0 on success, a negative errno value otherwise and rte_errno is set.
2945 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2946 size_t *size, struct rte_flow_error *error)
2948 struct rte_ether_hdr *eth = NULL;
2949 struct rte_vlan_hdr *vlan = NULL;
2950 struct rte_ipv4_hdr *ipv4 = NULL;
2951 struct rte_ipv6_hdr *ipv6 = NULL;
2952 struct rte_udp_hdr *udp = NULL;
2953 struct rte_vxlan_hdr *vxlan = NULL;
2954 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2955 struct rte_gre_hdr *gre = NULL;
2957 size_t temp_size = 0;
2960 return rte_flow_error_set(error, EINVAL,
2961 RTE_FLOW_ERROR_TYPE_ACTION,
2962 NULL, "invalid empty data");
2963 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2964 len = flow_dv_get_item_hdr_len(items->type);
2965 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION,
2968 (void *)items->type,
2969 "items total size is too big"
2970 " for encap action");
2971 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2972 switch (items->type) {
2973 case RTE_FLOW_ITEM_TYPE_ETH:
2974 eth = (struct rte_ether_hdr *)&buf[temp_size];
2976 case RTE_FLOW_ITEM_TYPE_VLAN:
2977 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2979 return rte_flow_error_set(error, EINVAL,
2980 RTE_FLOW_ERROR_TYPE_ACTION,
2981 (void *)items->type,
2982 "eth header not found");
2983 if (!eth->ether_type)
2984 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2986 case RTE_FLOW_ITEM_TYPE_IPV4:
2987 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2989 return rte_flow_error_set(error, EINVAL,
2990 RTE_FLOW_ERROR_TYPE_ACTION,
2991 (void *)items->type,
2992 "neither eth nor vlan"
2994 if (vlan && !vlan->eth_proto)
2995 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2996 else if (eth && !eth->ether_type)
2997 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2998 if (!ipv4->version_ihl)
2999 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3000 MLX5_ENCAP_IPV4_IHL_MIN;
3001 if (!ipv4->time_to_live)
3002 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3004 case RTE_FLOW_ITEM_TYPE_IPV6:
3005 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3007 return rte_flow_error_set(error, EINVAL,
3008 RTE_FLOW_ERROR_TYPE_ACTION,
3009 (void *)items->type,
3010 "neither eth nor vlan"
3012 if (vlan && !vlan->eth_proto)
3013 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3014 else if (eth && !eth->ether_type)
3015 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3016 if (!ipv6->vtc_flow)
3018 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3019 if (!ipv6->hop_limits)
3020 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3022 case RTE_FLOW_ITEM_TYPE_UDP:
3023 udp = (struct rte_udp_hdr *)&buf[temp_size];
3025 return rte_flow_error_set(error, EINVAL,
3026 RTE_FLOW_ERROR_TYPE_ACTION,
3027 (void *)items->type,
3028 "ip header not found");
3029 if (ipv4 && !ipv4->next_proto_id)
3030 ipv4->next_proto_id = IPPROTO_UDP;
3031 else if (ipv6 && !ipv6->proto)
3032 ipv6->proto = IPPROTO_UDP;
3034 case RTE_FLOW_ITEM_TYPE_VXLAN:
3035 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3037 return rte_flow_error_set(error, EINVAL,
3038 RTE_FLOW_ERROR_TYPE_ACTION,
3039 (void *)items->type,
3040 "udp header not found");
3042 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3043 if (!vxlan->vx_flags)
3045 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3047 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3048 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3050 return rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION,
3052 (void *)items->type,
3053 "udp header not found");
3054 if (!vxlan_gpe->proto)
3055 return rte_flow_error_set(error, EINVAL,
3056 RTE_FLOW_ERROR_TYPE_ACTION,
3057 (void *)items->type,
3058 "next protocol not found");
3061 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3062 if (!vxlan_gpe->vx_flags)
3063 vxlan_gpe->vx_flags =
3064 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3066 case RTE_FLOW_ITEM_TYPE_GRE:
3067 case RTE_FLOW_ITEM_TYPE_NVGRE:
3068 gre = (struct rte_gre_hdr *)&buf[temp_size];
3070 return rte_flow_error_set(error, EINVAL,
3071 RTE_FLOW_ERROR_TYPE_ACTION,
3072 (void *)items->type,
3073 "next protocol not found");
3075 return rte_flow_error_set(error, EINVAL,
3076 RTE_FLOW_ERROR_TYPE_ACTION,
3077 (void *)items->type,
3078 "ip header not found");
3079 if (ipv4 && !ipv4->next_proto_id)
3080 ipv4->next_proto_id = IPPROTO_GRE;
3081 else if (ipv6 && !ipv6->proto)
3082 ipv6->proto = IPPROTO_GRE;
3084 case RTE_FLOW_ITEM_TYPE_VOID:
3087 return rte_flow_error_set(error, EINVAL,
3088 RTE_FLOW_ERROR_TYPE_ACTION,
3089 (void *)items->type,
3090 "unsupported item type");
3100 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3102 struct rte_ether_hdr *eth = NULL;
3103 struct rte_vlan_hdr *vlan = NULL;
3104 struct rte_ipv6_hdr *ipv6 = NULL;
3105 struct rte_udp_hdr *udp = NULL;
3109 eth = (struct rte_ether_hdr *)data;
3110 next_hdr = (char *)(eth + 1);
3111 proto = RTE_BE16(eth->ether_type);
3114 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3115 vlan = (struct rte_vlan_hdr *)next_hdr;
3116 proto = RTE_BE16(vlan->eth_proto);
3117 next_hdr += sizeof(struct rte_vlan_hdr);
3120 /* HW calculates IPv4 csum. no need to proceed */
3121 if (proto == RTE_ETHER_TYPE_IPV4)
3124 /* non IPv4/IPv6 header. not supported */
3125 if (proto != RTE_ETHER_TYPE_IPV6) {
3126 return rte_flow_error_set(error, ENOTSUP,
3127 RTE_FLOW_ERROR_TYPE_ACTION,
3128 NULL, "Cannot offload non IPv4/IPv6");
3131 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3133 /* ignore non UDP */
3134 if (ipv6->proto != IPPROTO_UDP)
3137 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3138 udp->dgram_cksum = 0;
3144 * Convert L2 encap action to DV specification.
3147 * Pointer to rte_eth_dev structure.
3149 * Pointer to action structure.
3150 * @param[in, out] dev_flow
3151 * Pointer to the mlx5_flow.
3152 * @param[in] transfer
3153 * Mark if the flow is E-Switch flow.
3155 * Pointer to the error structure.
3158 * 0 on success, a negative errno value otherwise and rte_errno is set.
3161 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3162 const struct rte_flow_action *action,
3163 struct mlx5_flow *dev_flow,
3165 struct rte_flow_error *error)
3167 const struct rte_flow_item *encap_data;
3168 const struct rte_flow_action_raw_encap *raw_encap_data;
3169 struct mlx5_flow_dv_encap_decap_resource res = {
3171 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3172 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3173 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3176 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3178 (const struct rte_flow_action_raw_encap *)action->conf;
3179 res.size = raw_encap_data->size;
3180 memcpy(res.buf, raw_encap_data->data, res.size);
3182 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3184 ((const struct rte_flow_action_vxlan_encap *)
3185 action->conf)->definition;
3188 ((const struct rte_flow_action_nvgre_encap *)
3189 action->conf)->definition;
3190 if (flow_dv_convert_encap_data(encap_data, res.buf,
3194 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3196 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3197 return rte_flow_error_set(error, EINVAL,
3198 RTE_FLOW_ERROR_TYPE_ACTION,
3199 NULL, "can't create L2 encap action");
3204 * Convert L2 decap action to DV specification.
3207 * Pointer to rte_eth_dev structure.
3208 * @param[in, out] dev_flow
3209 * Pointer to the mlx5_flow.
3210 * @param[in] transfer
3211 * Mark if the flow is E-Switch flow.
3213 * Pointer to the error structure.
3216 * 0 on success, a negative errno value otherwise and rte_errno is set.
3219 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3220 struct mlx5_flow *dev_flow,
3222 struct rte_flow_error *error)
3224 struct mlx5_flow_dv_encap_decap_resource res = {
3227 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3228 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3229 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3232 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3233 return rte_flow_error_set(error, EINVAL,
3234 RTE_FLOW_ERROR_TYPE_ACTION,
3235 NULL, "can't create L2 decap action");
3240 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3243 * Pointer to rte_eth_dev structure.
3245 * Pointer to action structure.
3246 * @param[in, out] dev_flow
3247 * Pointer to the mlx5_flow.
3249 * Pointer to the flow attributes.
3251 * Pointer to the error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3258 const struct rte_flow_action *action,
3259 struct mlx5_flow *dev_flow,
3260 const struct rte_flow_attr *attr,
3261 struct rte_flow_error *error)
3263 const struct rte_flow_action_raw_encap *encap_data;
3264 struct mlx5_flow_dv_encap_decap_resource res;
3266 memset(&res, 0, sizeof(res));
3267 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3268 res.size = encap_data->size;
3269 memcpy(res.buf, encap_data->data, res.size);
3270 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3271 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3272 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3274 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3276 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3277 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3278 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION,
3281 NULL, "can't create encap action");
3286 * Create action push VLAN.
3289 * Pointer to rte_eth_dev structure.
3291 * Pointer to the flow attributes.
3293 * Pointer to the vlan to push to the Ethernet header.
3294 * @param[in, out] dev_flow
3295 * Pointer to the mlx5_flow.
3297 * Pointer to the error structure.
3300 * 0 on success, a negative errno value otherwise and rte_errno is set.
3303 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3304 const struct rte_flow_attr *attr,
3305 const struct rte_vlan_hdr *vlan,
3306 struct mlx5_flow *dev_flow,
3307 struct rte_flow_error *error)
3309 struct mlx5_flow_dv_push_vlan_action_resource res;
3311 memset(&res, 0, sizeof(res));
3313 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3316 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3318 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3319 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3320 return flow_dv_push_vlan_action_resource_register
3321 (dev, &res, dev_flow, error);
3325 * Validate the modify-header actions.
3327 * @param[in] action_flags
3328 * Holds the actions detected until now.
3330 * Pointer to the modify action.
3332 * Pointer to error structure.
3335 * 0 on success, a negative errno value otherwise and rte_errno is set.
3338 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3339 const struct rte_flow_action *action,
3340 struct rte_flow_error *error)
3342 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3343 return rte_flow_error_set(error, EINVAL,
3344 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3345 NULL, "action configuration not set");
3346 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3347 return rte_flow_error_set(error, EINVAL,
3348 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3349 "can't have encap action before"
3355 * Validate the modify-header MAC address actions.
3357 * @param[in] action_flags
3358 * Holds the actions detected until now.
3360 * Pointer to the modify action.
3361 * @param[in] item_flags
3362 * Holds the items detected.
3364 * Pointer to error structure.
3367 * 0 on success, a negative errno value otherwise and rte_errno is set.
3370 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3371 const struct rte_flow_action *action,
3372 const uint64_t item_flags,
3373 struct rte_flow_error *error)
3377 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3379 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3380 return rte_flow_error_set(error, EINVAL,
3381 RTE_FLOW_ERROR_TYPE_ACTION,
3383 "no L2 item in pattern");
3389 * Validate the modify-header IPv4 address actions.
3391 * @param[in] action_flags
3392 * Holds the actions detected until now.
3394 * Pointer to the modify action.
3395 * @param[in] item_flags
3396 * Holds the items detected.
3398 * Pointer to error structure.
3401 * 0 on success, a negative errno value otherwise and rte_errno is set.
3404 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3405 const struct rte_flow_action *action,
3406 const uint64_t item_flags,
3407 struct rte_flow_error *error)
3412 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3414 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3416 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3417 if (!(item_flags & layer))
3418 return rte_flow_error_set(error, EINVAL,
3419 RTE_FLOW_ERROR_TYPE_ACTION,
3421 "no ipv4 item in pattern");
3427 * Validate the modify-header IPv6 address actions.
3429 * @param[in] action_flags
3430 * Holds the actions detected until now.
3432 * Pointer to the modify action.
3433 * @param[in] item_flags
3434 * Holds the items detected.
3436 * Pointer to error structure.
3439 * 0 on success, a negative errno value otherwise and rte_errno is set.
3442 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3443 const struct rte_flow_action *action,
3444 const uint64_t item_flags,
3445 struct rte_flow_error *error)
3450 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3452 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3454 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3455 if (!(item_flags & layer))
3456 return rte_flow_error_set(error, EINVAL,
3457 RTE_FLOW_ERROR_TYPE_ACTION,
3459 "no ipv6 item in pattern");
3465 * Validate the modify-header TP actions.
3467 * @param[in] action_flags
3468 * Holds the actions detected until now.
3470 * Pointer to the modify action.
3471 * @param[in] item_flags
3472 * Holds the items detected.
3474 * Pointer to error structure.
3477 * 0 on success, a negative errno value otherwise and rte_errno is set.
3480 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3481 const struct rte_flow_action *action,
3482 const uint64_t item_flags,
3483 struct rte_flow_error *error)
3488 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3490 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3491 MLX5_FLOW_LAYER_INNER_L4 :
3492 MLX5_FLOW_LAYER_OUTER_L4;
3493 if (!(item_flags & layer))
3494 return rte_flow_error_set(error, EINVAL,
3495 RTE_FLOW_ERROR_TYPE_ACTION,
3496 NULL, "no transport layer "
3503 * Validate the modify-header actions of increment/decrement
3504 * TCP Sequence-number.
3506 * @param[in] action_flags
3507 * Holds the actions detected until now.
3509 * Pointer to the modify action.
3510 * @param[in] item_flags
3511 * Holds the items detected.
3513 * Pointer to error structure.
3516 * 0 on success, a negative errno value otherwise and rte_errno is set.
3519 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3520 const struct rte_flow_action *action,
3521 const uint64_t item_flags,
3522 struct rte_flow_error *error)
3527 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3529 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3530 MLX5_FLOW_LAYER_INNER_L4_TCP :
3531 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3532 if (!(item_flags & layer))
3533 return rte_flow_error_set(error, EINVAL,
3534 RTE_FLOW_ERROR_TYPE_ACTION,
3535 NULL, "no TCP item in"
3537 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3538 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3539 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3540 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3541 return rte_flow_error_set(error, EINVAL,
3542 RTE_FLOW_ERROR_TYPE_ACTION,
3544 "cannot decrease and increase"
3545 " TCP sequence number"
3546 " at the same time");
3552 * Validate the modify-header actions of increment/decrement
3553 * TCP Acknowledgment number.
3555 * @param[in] action_flags
3556 * Holds the actions detected until now.
3558 * Pointer to the modify action.
3559 * @param[in] item_flags
3560 * Holds the items detected.
3562 * Pointer to error structure.
3565 * 0 on success, a negative errno value otherwise and rte_errno is set.
3568 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3569 const struct rte_flow_action *action,
3570 const uint64_t item_flags,
3571 struct rte_flow_error *error)
3576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3578 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3579 MLX5_FLOW_LAYER_INNER_L4_TCP :
3580 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3581 if (!(item_flags & layer))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_ACTION,
3584 NULL, "no TCP item in"
3586 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3587 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3588 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3589 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3590 return rte_flow_error_set(error, EINVAL,
3591 RTE_FLOW_ERROR_TYPE_ACTION,
3593 "cannot decrease and increase"
3594 " TCP acknowledgment number"
3595 " at the same time");
3601 * Validate the modify-header TTL actions.
3603 * @param[in] action_flags
3604 * Holds the actions detected until now.
3606 * Pointer to the modify action.
3607 * @param[in] item_flags
3608 * Holds the items detected.
3610 * Pointer to error structure.
3613 * 0 on success, a negative errno value otherwise and rte_errno is set.
3616 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3617 const struct rte_flow_action *action,
3618 const uint64_t item_flags,
3619 struct rte_flow_error *error)
3624 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3626 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3627 MLX5_FLOW_LAYER_INNER_L3 :
3628 MLX5_FLOW_LAYER_OUTER_L3;
3629 if (!(item_flags & layer))
3630 return rte_flow_error_set(error, EINVAL,
3631 RTE_FLOW_ERROR_TYPE_ACTION,
3633 "no IP protocol in pattern");
3639 * Validate jump action.
3642 * Pointer to the jump action.
3643 * @param[in] action_flags
3644 * Holds the actions detected until now.
3645 * @param[in] attributes
3646 * Pointer to flow attributes
3647 * @param[in] external
3648 * Action belongs to flow rule created by request external to PMD.
3650 * Pointer to error structure.
3653 * 0 on success, a negative errno value otherwise and rte_errno is set.
3656 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3657 uint64_t action_flags,
3658 const struct rte_flow_attr *attributes,
3659 bool external, struct rte_flow_error *error)
3661 uint32_t target_group, table;
3664 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3665 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3666 return rte_flow_error_set(error, EINVAL,
3667 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3668 "can't have 2 fate actions in"
3670 if (action_flags & MLX5_FLOW_ACTION_METER)
3671 return rte_flow_error_set(error, ENOTSUP,
3672 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3673 "jump with meter not support");
3675 return rte_flow_error_set(error, EINVAL,
3676 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3677 NULL, "action configuration not set");
3679 ((const struct rte_flow_action_jump *)action->conf)->group;
3680 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3681 true, &table, error);
3684 if (attributes->group == target_group)
3685 return rte_flow_error_set(error, EINVAL,
3686 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3687 "target group must be other than"
3688 " the current flow group");
3693 * Validate the port_id action.
3696 * Pointer to rte_eth_dev structure.
3697 * @param[in] action_flags
3698 * Bit-fields that holds the actions detected until now.
3700 * Port_id RTE action structure.
3702 * Attributes of flow that includes this action.
3704 * Pointer to error structure.
3707 * 0 on success, a negative errno value otherwise and rte_errno is set.
3710 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3711 uint64_t action_flags,
3712 const struct rte_flow_action *action,
3713 const struct rte_flow_attr *attr,
3714 struct rte_flow_error *error)
3716 const struct rte_flow_action_port_id *port_id;
3717 struct mlx5_priv *act_priv;
3718 struct mlx5_priv *dev_priv;
3721 if (!attr->transfer)
3722 return rte_flow_error_set(error, ENOTSUP,
3723 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3725 "port id action is valid in transfer"
3727 if (!action || !action->conf)
3728 return rte_flow_error_set(error, ENOTSUP,
3729 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3731 "port id action parameters must be"
3733 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3734 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3735 return rte_flow_error_set(error, EINVAL,
3736 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3737 "can have only one fate actions in"
3739 dev_priv = mlx5_dev_to_eswitch_info(dev);
3741 return rte_flow_error_set(error, rte_errno,
3742 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3744 "failed to obtain E-Switch info");
3745 port_id = action->conf;
3746 port = port_id->original ? dev->data->port_id : port_id->id;
3747 act_priv = mlx5_port_to_eswitch_info(port, false);
3749 return rte_flow_error_set
3751 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3752 "failed to obtain E-Switch port id for port");
3753 if (act_priv->domain_id != dev_priv->domain_id)
3754 return rte_flow_error_set
3756 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3757 "port does not belong to"
3758 " E-Switch being configured");
3763 * Get the maximum number of modify header actions.
3766 * Pointer to rte_eth_dev structure.
3768 * Flags bits to check if root level.
3771 * Max number of modify header actions device can support.
3773 static inline unsigned int
3774 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3778 * There's no way to directly query the max capacity from FW.
3779 * The maximal value on root table should be assumed to be supported.
3781 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3782 return MLX5_MAX_MODIFY_NUM;
3784 return MLX5_ROOT_TBL_MODIFY_NUM;
3788 * Validate the meter action.
3791 * Pointer to rte_eth_dev structure.
3792 * @param[in] action_flags
3793 * Bit-fields that holds the actions detected until now.
3795 * Pointer to the meter action.
3797 * Attributes of flow that includes this action.
3799 * Pointer to error structure.
3802 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3805 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3806 uint64_t action_flags,
3807 const struct rte_flow_action *action,
3808 const struct rte_flow_attr *attr,
3809 struct rte_flow_error *error)
3811 struct mlx5_priv *priv = dev->data->dev_private;
3812 const struct rte_flow_action_meter *am = action->conf;
3813 struct mlx5_flow_meter *fm;
3816 return rte_flow_error_set(error, EINVAL,
3817 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3818 "meter action conf is NULL");
3820 if (action_flags & MLX5_FLOW_ACTION_METER)
3821 return rte_flow_error_set(error, ENOTSUP,
3822 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3823 "meter chaining not support");
3824 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3825 return rte_flow_error_set(error, ENOTSUP,
3826 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3827 "meter with jump not support");
3829 return rte_flow_error_set(error, ENOTSUP,
3830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3832 "meter action not supported");
3833 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3835 return rte_flow_error_set(error, EINVAL,
3836 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3838 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3839 (!fm->ingress && !attr->ingress && attr->egress) ||
3840 (!fm->egress && !attr->egress && attr->ingress))))
3841 return rte_flow_error_set(error, EINVAL,
3842 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3843 "Flow attributes are either invalid "
3844 "or have a conflict with current "
3845 "meter attributes");
3850 * Validate the age action.
3852 * @param[in] action_flags
3853 * Holds the actions detected until now.
3855 * Pointer to the age action.
3857 * Pointer to the Ethernet device structure.
3859 * Pointer to error structure.
3862 * 0 on success, a negative errno value otherwise and rte_errno is set.
3865 flow_dv_validate_action_age(uint64_t action_flags,
3866 const struct rte_flow_action *action,
3867 struct rte_eth_dev *dev,
3868 struct rte_flow_error *error)
3870 struct mlx5_priv *priv = dev->data->dev_private;
3871 const struct rte_flow_action_age *age = action->conf;
3873 if (!priv->config.devx || priv->counter_fallback)
3874 return rte_flow_error_set(error, ENOTSUP,
3875 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3877 "age action not supported");
3878 if (!(action->conf))
3879 return rte_flow_error_set(error, EINVAL,
3880 RTE_FLOW_ERROR_TYPE_ACTION, action,
3881 "configuration cannot be null");
3882 if (age->timeout >= UINT16_MAX / 2 / 10)
3883 return rte_flow_error_set(error, ENOTSUP,
3884 RTE_FLOW_ERROR_TYPE_ACTION, action,
3885 "Max age time: 3275 seconds");
3886 if (action_flags & MLX5_FLOW_ACTION_AGE)
3887 return rte_flow_error_set(error, EINVAL,
3888 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3889 "Duplicate age ctions set");
3894 * Validate the modify-header IPv4 DSCP actions.
3896 * @param[in] action_flags
3897 * Holds the actions detected until now.
3899 * Pointer to the modify action.
3900 * @param[in] item_flags
3901 * Holds the items detected.
3903 * Pointer to error structure.
3906 * 0 on success, a negative errno value otherwise and rte_errno is set.
3909 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3910 const struct rte_flow_action *action,
3911 const uint64_t item_flags,
3912 struct rte_flow_error *error)
3916 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3918 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3919 return rte_flow_error_set(error, EINVAL,
3920 RTE_FLOW_ERROR_TYPE_ACTION,
3922 "no ipv4 item in pattern");
3928 * Validate the modify-header IPv6 DSCP actions.
3930 * @param[in] action_flags
3931 * Holds the actions detected until now.
3933 * Pointer to the modify action.
3934 * @param[in] item_flags
3935 * Holds the items detected.
3937 * Pointer to error structure.
3940 * 0 on success, a negative errno value otherwise and rte_errno is set.
3943 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3944 const struct rte_flow_action *action,
3945 const uint64_t item_flags,
3946 struct rte_flow_error *error)
3950 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3952 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3953 return rte_flow_error_set(error, EINVAL,
3954 RTE_FLOW_ERROR_TYPE_ACTION,
3956 "no ipv6 item in pattern");
3962 * Find existing modify-header resource or create and register a new one.
3964 * @param dev[in, out]
3965 * Pointer to rte_eth_dev structure.
3966 * @param[in, out] resource
3967 * Pointer to modify-header resource.
3968 * @parm[in, out] dev_flow
3969 * Pointer to the dev_flow.
3971 * pointer to error structure.
3974 * 0 on success otherwise -errno and errno is set.
3977 flow_dv_modify_hdr_resource_register
3978 (struct rte_eth_dev *dev,
3979 struct mlx5_flow_dv_modify_hdr_resource *resource,
3980 struct mlx5_flow *dev_flow,
3981 struct rte_flow_error *error)
3983 struct mlx5_priv *priv = dev->data->dev_private;
3984 struct mlx5_dev_ctx_shared *sh = priv->sh;
3985 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3986 struct mlx5dv_dr_domain *ns;
3987 uint32_t actions_len;
3990 resource->flags = dev_flow->dv.group ? 0 :
3991 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3992 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3994 return rte_flow_error_set(error, EOVERFLOW,
3995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3996 "too many modify header items");
3997 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3998 ns = sh->fdb_domain;
3999 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4003 /* Lookup a matching resource from cache. */
4004 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4005 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
4006 if (resource->ft_type == cache_resource->ft_type &&
4007 resource->actions_num == cache_resource->actions_num &&
4008 resource->flags == cache_resource->flags &&
4009 !memcmp((const void *)resource->actions,
4010 (const void *)cache_resource->actions,
4012 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4013 (void *)cache_resource,
4014 rte_atomic32_read(&cache_resource->refcnt));
4015 rte_atomic32_inc(&cache_resource->refcnt);
4016 dev_flow->handle->dvh.modify_hdr = cache_resource;
4020 /* Register new modify-header resource. */
4021 cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4022 sizeof(*cache_resource) + actions_len, 0,
4024 if (!cache_resource)
4025 return rte_flow_error_set(error, ENOMEM,
4026 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4027 "cannot allocate resource memory");
4028 *cache_resource = *resource;
4029 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4030 ret = mlx5_flow_os_create_flow_action_modify_header
4031 (sh->ctx, ns, cache_resource,
4032 actions_len, &cache_resource->action);
4034 mlx5_free(cache_resource);
4035 return rte_flow_error_set(error, ENOMEM,
4036 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4037 NULL, "cannot create action");
4039 rte_atomic32_init(&cache_resource->refcnt);
4040 rte_atomic32_inc(&cache_resource->refcnt);
4041 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4042 dev_flow->handle->dvh.modify_hdr = cache_resource;
4043 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4044 (void *)cache_resource,
4045 rte_atomic32_read(&cache_resource->refcnt));
4050 * Get DV flow counter by index.
4053 * Pointer to the Ethernet device structure.
4055 * mlx5 flow counter index in the container.
4057 * mlx5 flow counter pool in the container,
4060 * Pointer to the counter, NULL otherwise.
4062 static struct mlx5_flow_counter *
4063 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4065 struct mlx5_flow_counter_pool **ppool)
4067 struct mlx5_priv *priv = dev->data->dev_private;
4068 struct mlx5_pools_container *cont;
4069 struct mlx5_flow_counter_pool *pool;
4070 uint32_t batch = 0, age = 0;
4073 age = MLX_CNT_IS_AGE(idx);
4074 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4075 if (idx >= MLX5_CNT_BATCH_OFFSET) {
4076 idx -= MLX5_CNT_BATCH_OFFSET;
4079 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4080 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4081 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4085 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4089 * Check the devx counter belongs to the pool.
4092 * Pointer to the counter pool.
4094 * The counter devx ID.
4097 * True if counter belongs to the pool, false otherwise.
4100 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4102 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4103 MLX5_COUNTERS_PER_POOL;
4105 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4111 * Get a pool by devx counter ID.
4114 * Pointer to the counter container.
4116 * The counter devx ID.
4119 * The counter pool pointer if exists, NULL otherwise,
4121 static struct mlx5_flow_counter_pool *
4122 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4126 /* Check last used pool. */
4127 if (cont->last_pool_idx != POOL_IDX_INVALID &&
4128 flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4129 return cont->pools[cont->last_pool_idx];
4130 /* ID out of range means no suitable pool in the container. */
4131 if (id > cont->max_id || id < cont->min_id)
4134 * Find the pool from the end of the container, since mostly counter
4135 * ID is sequence increasing, and the last pool should be the needed
4138 i = rte_atomic16_read(&cont->n_valid);
4140 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4142 if (flow_dv_is_counter_in_pool(pool, id))
4149 * Allocate a new memory for the counter values wrapped by all the needed
4153 * Pointer to the Ethernet device structure.
4155 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4158 * The new memory management pointer on success, otherwise NULL and rte_errno
4161 static struct mlx5_counter_stats_mem_mng *
4162 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4164 struct mlx5_priv *priv = dev->data->dev_private;
4165 struct mlx5_dev_ctx_shared *sh = priv->sh;
4166 struct mlx5_devx_mkey_attr mkey_attr;
4167 struct mlx5_counter_stats_mem_mng *mem_mng;
4168 volatile struct flow_counter_stats *raw_data;
4169 int size = (sizeof(struct flow_counter_stats) *
4170 MLX5_COUNTERS_PER_POOL +
4171 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4172 sizeof(struct mlx5_counter_stats_mem_mng);
4173 size_t pgsize = rte_mem_page_size();
4174 if (pgsize == (size_t)-1) {
4175 DRV_LOG(ERR, "Failed to get mem page size");
4179 uint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,
4187 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4188 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4189 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4190 IBV_ACCESS_LOCAL_WRITE);
4191 if (!mem_mng->umem) {
4196 mkey_attr.addr = (uintptr_t)mem;
4197 mkey_attr.size = size;
4198 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4199 mkey_attr.pd = sh->pdn;
4200 mkey_attr.log_entity_size = 0;
4201 mkey_attr.pg_access = 0;
4202 mkey_attr.klm_array = NULL;
4203 mkey_attr.klm_num = 0;
4204 if (priv->config.hca_attr.relaxed_ordering_write &&
4205 priv->config.hca_attr.relaxed_ordering_read &&
4206 !haswell_broadwell_cpu)
4207 mkey_attr.relaxed_ordering = 1;
4208 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4210 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4215 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4216 raw_data = (volatile struct flow_counter_stats *)mem;
4217 for (i = 0; i < raws_n; ++i) {
4218 mem_mng->raws[i].mem_mng = mem_mng;
4219 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4221 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4226 * Resize a counter container.
4229 * Pointer to the Ethernet device structure.
4231 * Whether the pool is for counter that was allocated by batch command.
4233 * Whether the pool is for Aging counter.
4236 * 0 on success, otherwise negative errno value and rte_errno is set.
4239 flow_dv_container_resize(struct rte_eth_dev *dev,
4240 uint32_t batch, uint32_t age)
4242 struct mlx5_priv *priv = dev->data->dev_private;
4243 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4245 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4246 void *old_pools = cont->pools;
4247 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4248 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4249 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4256 memcpy(pools, old_pools, cont->n *
4257 sizeof(struct mlx5_flow_counter_pool *));
4259 * Fallback mode query the counter directly, no background query
4260 * resources are needed.
4262 if (!priv->counter_fallback) {
4265 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4266 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4271 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4272 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4274 MLX5_CNT_CONTAINER_RESIZE +
4277 rte_spinlock_lock(&cont->resize_sl);
4279 cont->mem_mng = mem_mng;
4280 cont->pools = pools;
4281 rte_spinlock_unlock(&cont->resize_sl);
4283 mlx5_free(old_pools);
4288 * Query a devx flow counter.
4291 * Pointer to the Ethernet device structure.
4293 * Index to the flow counter.
4295 * The statistics value of packets.
4297 * The statistics value of bytes.
4300 * 0 on success, otherwise a negative errno value and rte_errno is set.
4303 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4306 struct mlx5_priv *priv = dev->data->dev_private;
4307 struct mlx5_flow_counter_pool *pool = NULL;
4308 struct mlx5_flow_counter *cnt;
4309 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4312 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4314 if (counter < MLX5_CNT_BATCH_OFFSET) {
4315 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4316 if (priv->counter_fallback)
4317 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4318 0, pkts, bytes, 0, NULL, NULL, 0);
4321 rte_spinlock_lock(&pool->sl);
4323 * The single counters allocation may allocate smaller ID than the
4324 * current allocated in parallel to the host reading.
4325 * In this case the new counter values must be reported as 0.
4327 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4331 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4332 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4333 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4335 rte_spinlock_unlock(&pool->sl);
4340 * Create and initialize a new counter pool.
4343 * Pointer to the Ethernet device structure.
4345 * The devX counter handle.
4347 * Whether the pool is for counter that was allocated by batch command.
4349 * Whether the pool is for counter that was allocated for aging.
4350 * @param[in/out] cont_cur
4351 * Pointer to the container pointer, it will be update in pool resize.
4354 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4356 static struct mlx5_flow_counter_pool *
4357 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4358 uint32_t batch, uint32_t age)
4360 struct mlx5_priv *priv = dev->data->dev_private;
4361 struct mlx5_flow_counter_pool *pool;
4362 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4364 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4365 uint32_t size = sizeof(*pool);
4367 if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4369 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4370 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4371 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4372 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4377 pool->min_dcs = dcs;
4378 if (!priv->counter_fallback)
4379 pool->raw = cont->mem_mng->raws + n_valid %
4380 MLX5_CNT_CONTAINER_RESIZE;
4381 pool->raw_hw = NULL;
4383 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4384 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4385 pool->query_gen = 0;
4386 rte_spinlock_init(&pool->sl);
4387 TAILQ_INIT(&pool->counters[0]);
4388 TAILQ_INIT(&pool->counters[1]);
4389 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4390 pool->index = n_valid;
4391 cont->pools[n_valid] = pool;
4393 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4395 if (base < cont->min_id)
4396 cont->min_id = base;
4397 if (base > cont->max_id)
4398 cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4399 cont->last_pool_idx = pool->index;
4401 /* Pool initialization must be updated before host thread access. */
4403 rte_atomic16_add(&cont->n_valid, 1);
4408 * Prepare a new counter and/or a new counter pool.
4411 * Pointer to the Ethernet device structure.
4412 * @param[out] cnt_free
4413 * Where to put the pointer of a new counter.
4415 * Whether the pool is for counter that was allocated by batch command.
4417 * Whether the pool is for counter that was allocated for aging.
4420 * The counter pool pointer and @p cnt_free is set on success,
4421 * NULL otherwise and rte_errno is set.
4423 static struct mlx5_flow_counter_pool *
4424 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4425 struct mlx5_flow_counter **cnt_free,
4426 uint32_t batch, uint32_t age)
4428 struct mlx5_priv *priv = dev->data->dev_private;
4429 struct mlx5_pools_container *cont;
4430 struct mlx5_flow_counter_pool *pool;
4431 struct mlx5_counters tmp_tq;
4432 struct mlx5_devx_obj *dcs = NULL;
4433 struct mlx5_flow_counter *cnt;
4437 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4441 /* bulk_bitmap must be 0 for single counter allocation. */
4442 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4445 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4446 /* Check if counter belongs to exist pool ID range. */
4448 pool = flow_dv_find_pool_by_id
4450 (priv->sh, batch, (age ^ 0x1)), dcs->id);
4452 * Pool eixsts, counter will be added to the other
4453 * container, need to reallocate it later.
4458 pool = flow_dv_pool_create(dev, dcs, batch,
4461 mlx5_devx_cmd_destroy(dcs);
4466 if (dcs->id < pool->min_dcs->id)
4467 rte_atomic64_set(&pool->a64_dcs,
4468 (int64_t)(uintptr_t)dcs);
4469 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4470 cnt = MLX5_POOL_GET_CNT(pool, i);
4472 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4474 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen],
4481 /* bulk_bitmap is in 128 counters units. */
4482 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4483 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4485 rte_errno = ENODATA;
4488 pool = flow_dv_pool_create(dev, dcs, batch, age);
4490 mlx5_devx_cmd_destroy(dcs);
4493 TAILQ_INIT(&tmp_tq);
4494 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4495 cnt = MLX5_POOL_GET_CNT(pool, i);
4497 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4499 rte_spinlock_lock(&cont->csl);
4500 TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4501 rte_spinlock_unlock(&cont->csl);
4502 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4503 (*cnt_free)->pool = pool;
4508 * Search for existed shared counter.
4511 * Pointer to the Ethernet device structure.
4513 * The shared counter ID to search.
4515 * mlx5 flow counter pool in the container,
4518 * NULL if not existed, otherwise pointer to the shared extend counter.
4520 static struct mlx5_flow_counter_ext *
4521 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4522 struct mlx5_flow_counter_pool **ppool)
4524 struct mlx5_priv *priv = dev->data->dev_private;
4525 union mlx5_l3t_data data;
4528 if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4530 cnt_idx = data.dword;
4532 * Shared counters don't have age info. The counter extend is after
4533 * the counter datat structure.
4535 return (struct mlx5_flow_counter_ext *)
4536 ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4540 * Allocate a flow counter.
4543 * Pointer to the Ethernet device structure.
4545 * Indicate if this counter is shared with other flows.
4547 * Counter identifier.
4549 * Counter flow group.
4551 * Whether the counter was allocated for aging.
4554 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4557 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4558 uint16_t group, uint32_t age)
4560 struct mlx5_priv *priv = dev->data->dev_private;
4561 struct mlx5_flow_counter_pool *pool = NULL;
4562 struct mlx5_flow_counter *cnt_free = NULL;
4563 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4565 * Currently group 0 flow counter cannot be assigned to a flow if it is
4566 * not the first one in the batch counter allocation, so it is better
4567 * to allocate counters one by one for these flows in a separate
4569 * A counter can be shared between different groups so need to take
4570 * shared counters from the single container.
4572 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4573 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4577 if (!priv->config.devx) {
4578 rte_errno = ENOTSUP;
4582 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4584 if (cnt_ext->ref_cnt + 1 == 0) {
4589 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4590 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4595 /* Get free counters from container. */
4596 rte_spinlock_lock(&cont->csl);
4597 cnt_free = TAILQ_FIRST(&cont->counters);
4599 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4600 rte_spinlock_unlock(&cont->csl);
4601 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4604 pool = cnt_free->pool;
4606 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4607 /* Create a DV counter action only in the first time usage. */
4608 if (!cnt_free->action) {
4610 struct mlx5_devx_obj *dcs;
4614 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4615 dcs = pool->min_dcs;
4620 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4627 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4628 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4629 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4630 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4631 /* Update the counter reset values. */
4632 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4636 cnt_ext->shared = shared;
4637 cnt_ext->ref_cnt = 1;
4640 union mlx5_l3t_data data;
4642 data.dword = cnt_idx;
4643 if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4647 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4648 /* Start the asynchronous batch query by the host thread. */
4649 mlx5_set_query_alarm(priv->sh);
4653 cnt_free->pool = pool;
4654 rte_spinlock_lock(&cont->csl);
4655 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4656 rte_spinlock_unlock(&cont->csl);
4662 * Get age param from counter index.
4665 * Pointer to the Ethernet device structure.
4666 * @param[in] counter
4667 * Index to the counter handler.
4670 * The aging parameter specified for the counter index.
4672 static struct mlx5_age_param*
4673 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4676 struct mlx5_flow_counter *cnt;
4677 struct mlx5_flow_counter_pool *pool = NULL;
4679 flow_dv_counter_get_by_idx(dev, counter, &pool);
4680 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4681 cnt = MLX5_POOL_GET_CNT(pool, counter);
4682 return MLX5_CNT_TO_AGE(cnt);
4686 * Remove a flow counter from aged counter list.
4689 * Pointer to the Ethernet device structure.
4690 * @param[in] counter
4691 * Index to the counter handler.
4693 * Pointer to the counter handler.
4696 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4697 uint32_t counter, struct mlx5_flow_counter *cnt)
4699 struct mlx5_age_info *age_info;
4700 struct mlx5_age_param *age_param;
4701 struct mlx5_priv *priv = dev->data->dev_private;
4703 age_info = GET_PORT_AGE_INFO(priv);
4704 age_param = flow_dv_counter_idx_get_age(dev, counter);
4705 if (rte_atomic16_cmpset((volatile uint16_t *)
4707 AGE_CANDIDATE, AGE_FREE)
4710 * We need the lock even it is age timeout,
4711 * since counter may still in process.
4713 rte_spinlock_lock(&age_info->aged_sl);
4714 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4715 rte_spinlock_unlock(&age_info->aged_sl);
4717 rte_atomic16_set(&age_param->state, AGE_FREE);
4720 * Release a flow counter.
4723 * Pointer to the Ethernet device structure.
4724 * @param[in] counter
4725 * Index to the counter handler.
4728 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4730 struct mlx5_priv *priv = dev->data->dev_private;
4731 struct mlx5_flow_counter_pool *pool = NULL;
4732 struct mlx5_flow_counter *cnt;
4733 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4737 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4739 if (counter < MLX5_CNT_BATCH_OFFSET) {
4740 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4742 if (--cnt_ext->ref_cnt)
4744 if (cnt_ext->shared)
4745 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4749 if (IS_AGE_POOL(pool))
4750 flow_dv_counter_remove_from_age(dev, counter, cnt);
4753 * Put the counter back to list to be updated in none fallback mode.
4754 * Currently, we are using two list alternately, while one is in query,
4755 * add the freed counter to the other list based on the pool query_gen
4756 * value. After query finishes, add counter the list to the global
4757 * container counter list. The list changes while query starts. In
4758 * this case, lock will not be needed as query callback and release
4759 * function both operate with the different list.
4762 if (!priv->counter_fallback)
4763 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4765 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4766 (priv->sh, 0, 0))->counters),
4771 * Verify the @p attributes will be correctly understood by the NIC and store
4772 * them in the @p flow if everything is correct.
4775 * Pointer to dev struct.
4776 * @param[in] attributes
4777 * Pointer to flow attributes
4778 * @param[in] external
4779 * This flow rule is created by request external to PMD.
4781 * Pointer to error structure.
4784 * - 0 on success and non root table.
4785 * - 1 on success and root table.
4786 * - a negative errno value otherwise and rte_errno is set.
4789 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4790 const struct rte_flow_attr *attributes,
4791 bool external __rte_unused,
4792 struct rte_flow_error *error)
4794 struct mlx5_priv *priv = dev->data->dev_private;
4795 uint32_t priority_max = priv->config.flow_prio - 1;
4798 #ifndef HAVE_MLX5DV_DR
4799 if (attributes->group)
4800 return rte_flow_error_set(error, ENOTSUP,
4801 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4803 "groups are not supported");
4807 ret = mlx5_flow_group_to_table(attributes, external,
4808 attributes->group, !!priv->fdb_def_rule,
4813 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4815 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4816 attributes->priority >= priority_max)
4817 return rte_flow_error_set(error, ENOTSUP,
4818 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4820 "priority out of range");
4821 if (attributes->transfer) {
4822 if (!priv->config.dv_esw_en)
4823 return rte_flow_error_set
4825 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4826 "E-Switch dr is not supported");
4827 if (!(priv->representor || priv->master))
4828 return rte_flow_error_set
4829 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4830 NULL, "E-Switch configuration can only be"
4831 " done by a master or a representor device");
4832 if (attributes->egress)
4833 return rte_flow_error_set
4835 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4836 "egress is not supported");
4838 if (!(attributes->egress ^ attributes->ingress))
4839 return rte_flow_error_set(error, ENOTSUP,
4840 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4841 "must specify exactly one of "
4842 "ingress or egress");
4847 * Internal validation function. For validating both actions and items.
4850 * Pointer to the rte_eth_dev structure.
4852 * Pointer to the flow attributes.
4854 * Pointer to the list of items.
4855 * @param[in] actions
4856 * Pointer to the list of actions.
4857 * @param[in] external
4858 * This flow rule is created by request external to PMD.
4859 * @param[in] hairpin
4860 * Number of hairpin TX actions, 0 means classic flow.
4862 * Pointer to the error structure.
4865 * 0 on success, a negative errno value otherwise and rte_errno is set.
4868 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4869 const struct rte_flow_item items[],
4870 const struct rte_flow_action actions[],
4871 bool external, int hairpin, struct rte_flow_error *error)
4874 uint64_t action_flags = 0;
4875 uint64_t item_flags = 0;
4876 uint64_t last_item = 0;
4877 uint8_t next_protocol = 0xff;
4878 uint16_t ether_type = 0;
4880 uint8_t item_ipv6_proto = 0;
4881 const struct rte_flow_item *gre_item = NULL;
4882 const struct rte_flow_action_raw_decap *decap;
4883 const struct rte_flow_action_raw_encap *encap;
4884 const struct rte_flow_action_rss *rss;
4885 const struct rte_flow_item_tcp nic_tcp_mask = {
4888 .src_port = RTE_BE16(UINT16_MAX),
4889 .dst_port = RTE_BE16(UINT16_MAX),
4892 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4894 .src_addr = RTE_BE32(0xffffffff),
4895 .dst_addr = RTE_BE32(0xffffffff),
4896 .type_of_service = 0xff,
4897 .next_proto_id = 0xff,
4898 .time_to_live = 0xff,
4901 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4904 "\xff\xff\xff\xff\xff\xff\xff\xff"
4905 "\xff\xff\xff\xff\xff\xff\xff\xff",
4907 "\xff\xff\xff\xff\xff\xff\xff\xff"
4908 "\xff\xff\xff\xff\xff\xff\xff\xff",
4909 .vtc_flow = RTE_BE32(0xffffffff),
4914 const struct rte_flow_item_ecpri nic_ecpri_mask = {
4918 RTE_BE32(((const struct rte_ecpri_common_hdr) {
4922 .dummy[0] = 0xffffffff,
4925 struct mlx5_priv *priv = dev->data->dev_private;
4926 struct mlx5_dev_config *dev_conf = &priv->config;
4927 uint16_t queue_index = 0xFFFF;
4928 const struct rte_flow_item_vlan *vlan_m = NULL;
4929 int16_t rw_act_num = 0;
4934 ret = flow_dv_validate_attributes(dev, attr, external, error);
4937 is_root = (uint64_t)ret;
4938 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4939 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4940 int type = items->type;
4942 if (!mlx5_flow_os_item_supported(type))
4943 return rte_flow_error_set(error, ENOTSUP,
4944 RTE_FLOW_ERROR_TYPE_ITEM,
4945 NULL, "item not supported");
4947 case RTE_FLOW_ITEM_TYPE_VOID:
4949 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4950 ret = flow_dv_validate_item_port_id
4951 (dev, items, attr, item_flags, error);
4954 last_item = MLX5_FLOW_ITEM_PORT_ID;
4956 case RTE_FLOW_ITEM_TYPE_ETH:
4957 ret = mlx5_flow_validate_item_eth(items, item_flags,
4961 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4962 MLX5_FLOW_LAYER_OUTER_L2;
4963 if (items->mask != NULL && items->spec != NULL) {
4965 ((const struct rte_flow_item_eth *)
4968 ((const struct rte_flow_item_eth *)
4970 ether_type = rte_be_to_cpu_16(ether_type);
4975 case RTE_FLOW_ITEM_TYPE_VLAN:
4976 ret = flow_dv_validate_item_vlan(items, item_flags,
4980 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4981 MLX5_FLOW_LAYER_OUTER_VLAN;
4982 if (items->mask != NULL && items->spec != NULL) {
4984 ((const struct rte_flow_item_vlan *)
4985 items->spec)->inner_type;
4987 ((const struct rte_flow_item_vlan *)
4988 items->mask)->inner_type;
4989 ether_type = rte_be_to_cpu_16(ether_type);
4993 /* Store outer VLAN mask for of_push_vlan action. */
4995 vlan_m = items->mask;
4997 case RTE_FLOW_ITEM_TYPE_IPV4:
4998 mlx5_flow_tunnel_ip_check(items, next_protocol,
4999 &item_flags, &tunnel);
5000 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5007 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5008 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5009 if (items->mask != NULL &&
5010 ((const struct rte_flow_item_ipv4 *)
5011 items->mask)->hdr.next_proto_id) {
5013 ((const struct rte_flow_item_ipv4 *)
5014 (items->spec))->hdr.next_proto_id;
5016 ((const struct rte_flow_item_ipv4 *)
5017 (items->mask))->hdr.next_proto_id;
5019 /* Reset for inner layer. */
5020 next_protocol = 0xff;
5023 case RTE_FLOW_ITEM_TYPE_IPV6:
5024 mlx5_flow_tunnel_ip_check(items, next_protocol,
5025 &item_flags, &tunnel);
5026 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5033 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5034 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5035 if (items->mask != NULL &&
5036 ((const struct rte_flow_item_ipv6 *)
5037 items->mask)->hdr.proto) {
5039 ((const struct rte_flow_item_ipv6 *)
5040 items->spec)->hdr.proto;
5042 ((const struct rte_flow_item_ipv6 *)
5043 items->spec)->hdr.proto;
5045 ((const struct rte_flow_item_ipv6 *)
5046 items->mask)->hdr.proto;
5048 /* Reset for inner layer. */
5049 next_protocol = 0xff;
5052 case RTE_FLOW_ITEM_TYPE_TCP:
5053 ret = mlx5_flow_validate_item_tcp
5060 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5061 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5063 case RTE_FLOW_ITEM_TYPE_UDP:
5064 ret = mlx5_flow_validate_item_udp(items, item_flags,
5069 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5070 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5072 case RTE_FLOW_ITEM_TYPE_GRE:
5073 ret = mlx5_flow_validate_item_gre(items, item_flags,
5074 next_protocol, error);
5078 last_item = MLX5_FLOW_LAYER_GRE;
5080 case RTE_FLOW_ITEM_TYPE_NVGRE:
5081 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5086 last_item = MLX5_FLOW_LAYER_NVGRE;
5088 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5089 ret = mlx5_flow_validate_item_gre_key
5090 (items, item_flags, gre_item, error);
5093 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5095 case RTE_FLOW_ITEM_TYPE_VXLAN:
5096 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5100 last_item = MLX5_FLOW_LAYER_VXLAN;
5102 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5103 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5108 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5110 case RTE_FLOW_ITEM_TYPE_GENEVE:
5111 ret = mlx5_flow_validate_item_geneve(items,
5116 last_item = MLX5_FLOW_LAYER_GENEVE;
5118 case RTE_FLOW_ITEM_TYPE_MPLS:
5119 ret = mlx5_flow_validate_item_mpls(dev, items,
5124 last_item = MLX5_FLOW_LAYER_MPLS;
5127 case RTE_FLOW_ITEM_TYPE_MARK:
5128 ret = flow_dv_validate_item_mark(dev, items, attr,
5132 last_item = MLX5_FLOW_ITEM_MARK;
5134 case RTE_FLOW_ITEM_TYPE_META:
5135 ret = flow_dv_validate_item_meta(dev, items, attr,
5139 last_item = MLX5_FLOW_ITEM_METADATA;
5141 case RTE_FLOW_ITEM_TYPE_ICMP:
5142 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5147 last_item = MLX5_FLOW_LAYER_ICMP;
5149 case RTE_FLOW_ITEM_TYPE_ICMP6:
5150 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5155 item_ipv6_proto = IPPROTO_ICMPV6;
5156 last_item = MLX5_FLOW_LAYER_ICMP6;
5158 case RTE_FLOW_ITEM_TYPE_TAG:
5159 ret = flow_dv_validate_item_tag(dev, items,
5163 last_item = MLX5_FLOW_ITEM_TAG;
5165 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5166 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5168 case RTE_FLOW_ITEM_TYPE_GTP:
5169 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5173 last_item = MLX5_FLOW_LAYER_GTP;
5175 case RTE_FLOW_ITEM_TYPE_ECPRI:
5176 /* Capacity will be checked in the translate stage. */
5177 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5184 last_item = MLX5_FLOW_LAYER_ECPRI;
5187 return rte_flow_error_set(error, ENOTSUP,
5188 RTE_FLOW_ERROR_TYPE_ITEM,
5189 NULL, "item not supported");
5191 item_flags |= last_item;
5193 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5194 int type = actions->type;
5196 if (!mlx5_flow_os_action_supported(type))
5197 return rte_flow_error_set(error, ENOTSUP,
5198 RTE_FLOW_ERROR_TYPE_ACTION,
5200 "action not supported");
5201 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5202 return rte_flow_error_set(error, ENOTSUP,
5203 RTE_FLOW_ERROR_TYPE_ACTION,
5204 actions, "too many actions");
5206 case RTE_FLOW_ACTION_TYPE_VOID:
5208 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5209 ret = flow_dv_validate_action_port_id(dev,
5216 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5219 case RTE_FLOW_ACTION_TYPE_FLAG:
5220 ret = flow_dv_validate_action_flag(dev, action_flags,
5224 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5225 /* Count all modify-header actions as one. */
5226 if (!(action_flags &
5227 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5229 action_flags |= MLX5_FLOW_ACTION_FLAG |
5230 MLX5_FLOW_ACTION_MARK_EXT;
5232 action_flags |= MLX5_FLOW_ACTION_FLAG;
5235 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5237 case RTE_FLOW_ACTION_TYPE_MARK:
5238 ret = flow_dv_validate_action_mark(dev, actions,
5243 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5244 /* Count all modify-header actions as one. */
5245 if (!(action_flags &
5246 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5248 action_flags |= MLX5_FLOW_ACTION_MARK |
5249 MLX5_FLOW_ACTION_MARK_EXT;
5251 action_flags |= MLX5_FLOW_ACTION_MARK;
5254 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5256 case RTE_FLOW_ACTION_TYPE_SET_META:
5257 ret = flow_dv_validate_action_set_meta(dev, actions,
5262 /* Count all modify-header actions as one action. */
5263 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5265 action_flags |= MLX5_FLOW_ACTION_SET_META;
5266 rw_act_num += MLX5_ACT_NUM_SET_META;
5268 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5269 ret = flow_dv_validate_action_set_tag(dev, actions,
5274 /* Count all modify-header actions as one action. */
5275 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5277 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5278 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5280 case RTE_FLOW_ACTION_TYPE_DROP:
5281 ret = mlx5_flow_validate_action_drop(action_flags,
5285 action_flags |= MLX5_FLOW_ACTION_DROP;
5288 case RTE_FLOW_ACTION_TYPE_QUEUE:
5289 ret = mlx5_flow_validate_action_queue(actions,
5294 queue_index = ((const struct rte_flow_action_queue *)
5295 (actions->conf))->index;
5296 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5299 case RTE_FLOW_ACTION_TYPE_RSS:
5300 rss = actions->conf;
5301 ret = mlx5_flow_validate_action_rss(actions,
5307 if (rss != NULL && rss->queue_num)
5308 queue_index = rss->queue[0];
5309 action_flags |= MLX5_FLOW_ACTION_RSS;
5312 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5314 mlx5_flow_validate_action_default_miss(action_flags,
5318 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5321 case RTE_FLOW_ACTION_TYPE_COUNT:
5322 ret = flow_dv_validate_action_count(dev, error);
5325 action_flags |= MLX5_FLOW_ACTION_COUNT;
5328 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5329 if (flow_dv_validate_action_pop_vlan(dev,
5335 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5338 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5339 ret = flow_dv_validate_action_push_vlan(dev,
5346 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5349 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5350 ret = flow_dv_validate_action_set_vlan_pcp
5351 (action_flags, actions, error);
5354 /* Count PCP with push_vlan command. */
5355 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5357 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5358 ret = flow_dv_validate_action_set_vlan_vid
5359 (item_flags, action_flags,
5363 /* Count VID with push_vlan command. */
5364 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5365 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5367 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5368 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5369 ret = flow_dv_validate_action_l2_encap(dev,
5375 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5378 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5379 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5380 ret = flow_dv_validate_action_decap(dev, action_flags,
5384 action_flags |= MLX5_FLOW_ACTION_DECAP;
5387 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5388 ret = flow_dv_validate_action_raw_encap_decap
5389 (dev, NULL, actions->conf, attr, &action_flags,
5394 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5395 decap = actions->conf;
5396 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5398 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5402 encap = actions->conf;
5404 ret = flow_dv_validate_action_raw_encap_decap
5406 decap ? decap : &empty_decap, encap,
5407 attr, &action_flags, &actions_n,
5412 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5413 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5414 ret = flow_dv_validate_action_modify_mac(action_flags,
5420 /* Count all modify-header actions as one action. */
5421 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5423 action_flags |= actions->type ==
5424 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5425 MLX5_FLOW_ACTION_SET_MAC_SRC :
5426 MLX5_FLOW_ACTION_SET_MAC_DST;
5428 * Even if the source and destination MAC addresses have
5429 * overlap in the header with 4B alignment, the convert
5430 * function will handle them separately and 4 SW actions
5431 * will be created. And 2 actions will be added each
5432 * time no matter how many bytes of address will be set.
5434 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5436 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5437 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5438 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5444 /* Count all modify-header actions as one action. */
5445 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5447 action_flags |= actions->type ==
5448 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5449 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5450 MLX5_FLOW_ACTION_SET_IPV4_DST;
5451 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5453 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5454 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5455 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5461 if (item_ipv6_proto == IPPROTO_ICMPV6)
5462 return rte_flow_error_set(error, ENOTSUP,
5463 RTE_FLOW_ERROR_TYPE_ACTION,
5465 "Can't change header "
5466 "with ICMPv6 proto");
5467 /* Count all modify-header actions as one action. */
5468 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5470 action_flags |= actions->type ==
5471 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5472 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5473 MLX5_FLOW_ACTION_SET_IPV6_DST;
5474 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5476 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5477 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5478 ret = flow_dv_validate_action_modify_tp(action_flags,
5484 /* Count all modify-header actions as one action. */
5485 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5487 action_flags |= actions->type ==
5488 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5489 MLX5_FLOW_ACTION_SET_TP_SRC :
5490 MLX5_FLOW_ACTION_SET_TP_DST;
5491 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5493 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5494 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5495 ret = flow_dv_validate_action_modify_ttl(action_flags,
5501 /* Count all modify-header actions as one action. */
5502 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5504 action_flags |= actions->type ==
5505 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5506 MLX5_FLOW_ACTION_SET_TTL :
5507 MLX5_FLOW_ACTION_DEC_TTL;
5508 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5510 case RTE_FLOW_ACTION_TYPE_JUMP:
5511 ret = flow_dv_validate_action_jump(actions,
5518 action_flags |= MLX5_FLOW_ACTION_JUMP;
5520 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5521 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5522 ret = flow_dv_validate_action_modify_tcp_seq
5529 /* Count all modify-header actions as one action. */
5530 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5532 action_flags |= actions->type ==
5533 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5534 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5535 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5536 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5538 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5539 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5540 ret = flow_dv_validate_action_modify_tcp_ack
5547 /* Count all modify-header actions as one action. */
5548 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5550 action_flags |= actions->type ==
5551 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5552 MLX5_FLOW_ACTION_INC_TCP_ACK :
5553 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5554 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5556 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5558 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5559 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5560 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5562 case RTE_FLOW_ACTION_TYPE_METER:
5563 ret = mlx5_flow_validate_action_meter(dev,
5569 action_flags |= MLX5_FLOW_ACTION_METER;
5571 /* Meter action will add one more TAG action. */
5572 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5574 case RTE_FLOW_ACTION_TYPE_AGE:
5575 ret = flow_dv_validate_action_age(action_flags,
5580 action_flags |= MLX5_FLOW_ACTION_AGE;
5583 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5584 ret = flow_dv_validate_action_modify_ipv4_dscp
5591 /* Count all modify-header actions as one action. */
5592 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5594 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5595 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5597 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5598 ret = flow_dv_validate_action_modify_ipv6_dscp
5605 /* Count all modify-header actions as one action. */
5606 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5608 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5609 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5612 return rte_flow_error_set(error, ENOTSUP,
5613 RTE_FLOW_ERROR_TYPE_ACTION,
5615 "action not supported");
5619 * Validate the drop action mutual exclusion with other actions.
5620 * Drop action is mutually-exclusive with any other action, except for
5623 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5624 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5625 return rte_flow_error_set(error, EINVAL,
5626 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5627 "Drop action is mutually-exclusive "
5628 "with any other action, except for "
5630 /* Eswitch has few restrictions on using items and actions */
5631 if (attr->transfer) {
5632 if (!mlx5_flow_ext_mreg_supported(dev) &&
5633 action_flags & MLX5_FLOW_ACTION_FLAG)
5634 return rte_flow_error_set(error, ENOTSUP,
5635 RTE_FLOW_ERROR_TYPE_ACTION,
5637 "unsupported action FLAG");
5638 if (!mlx5_flow_ext_mreg_supported(dev) &&
5639 action_flags & MLX5_FLOW_ACTION_MARK)
5640 return rte_flow_error_set(error, ENOTSUP,
5641 RTE_FLOW_ERROR_TYPE_ACTION,
5643 "unsupported action MARK");
5644 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5645 return rte_flow_error_set(error, ENOTSUP,
5646 RTE_FLOW_ERROR_TYPE_ACTION,
5648 "unsupported action QUEUE");
5649 if (action_flags & MLX5_FLOW_ACTION_RSS)
5650 return rte_flow_error_set(error, ENOTSUP,
5651 RTE_FLOW_ERROR_TYPE_ACTION,
5653 "unsupported action RSS");
5654 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5655 return rte_flow_error_set(error, EINVAL,
5656 RTE_FLOW_ERROR_TYPE_ACTION,
5658 "no fate action is found");
5660 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5661 return rte_flow_error_set(error, EINVAL,
5662 RTE_FLOW_ERROR_TYPE_ACTION,
5664 "no fate action is found");
5666 /* Continue validation for Xcap and VLAN actions.*/
5667 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
5668 MLX5_FLOW_VLAN_ACTIONS)) &&
5669 (queue_index == 0xFFFF ||
5670 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5671 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5672 MLX5_FLOW_XCAP_ACTIONS)
5673 return rte_flow_error_set(error, ENOTSUP,
5674 RTE_FLOW_ERROR_TYPE_ACTION,
5675 NULL, "encap and decap "
5676 "combination aren't supported");
5677 if (!attr->transfer && attr->ingress) {
5678 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
5679 return rte_flow_error_set
5681 RTE_FLOW_ERROR_TYPE_ACTION,
5682 NULL, "encap is not supported"
5683 " for ingress traffic");
5684 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5685 return rte_flow_error_set
5687 RTE_FLOW_ERROR_TYPE_ACTION,
5688 NULL, "push VLAN action not "
5689 "supported for ingress");
5690 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
5691 MLX5_FLOW_VLAN_ACTIONS)
5692 return rte_flow_error_set
5694 RTE_FLOW_ERROR_TYPE_ACTION,
5695 NULL, "no support for "
5696 "multiple VLAN actions");
5699 /* Hairpin flow will add one more TAG action. */
5701 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5702 /* extra metadata enabled: one more TAG action will be add. */
5703 if (dev_conf->dv_flow_en &&
5704 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5705 mlx5_flow_ext_mreg_supported(dev))
5706 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5707 if ((uint32_t)rw_act_num >
5708 flow_dv_modify_hdr_action_max(dev, is_root)) {
5709 return rte_flow_error_set(error, ENOTSUP,
5710 RTE_FLOW_ERROR_TYPE_ACTION,
5711 NULL, "too many header modify"
5712 " actions to support");
5718 * Internal preparation function. Allocates the DV flow size,
5719 * this size is constant.
5722 * Pointer to the rte_eth_dev structure.
5724 * Pointer to the flow attributes.
5726 * Pointer to the list of items.
5727 * @param[in] actions
5728 * Pointer to the list of actions.
5730 * Pointer to the error structure.
5733 * Pointer to mlx5_flow object on success,
5734 * otherwise NULL and rte_errno is set.
5736 static struct mlx5_flow *
5737 flow_dv_prepare(struct rte_eth_dev *dev,
5738 const struct rte_flow_attr *attr __rte_unused,
5739 const struct rte_flow_item items[] __rte_unused,
5740 const struct rte_flow_action actions[] __rte_unused,
5741 struct rte_flow_error *error)
5743 uint32_t handle_idx = 0;
5744 struct mlx5_flow *dev_flow;
5745 struct mlx5_flow_handle *dev_handle;
5746 struct mlx5_priv *priv = dev->data->dev_private;
5748 /* In case of corrupting the memory. */
5749 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5750 rte_flow_error_set(error, ENOSPC,
5751 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5752 "not free temporary device flow");
5755 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5758 rte_flow_error_set(error, ENOMEM,
5759 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5760 "not enough memory to create flow handle");
5763 /* No multi-thread supporting. */
5764 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5765 dev_flow->handle = dev_handle;
5766 dev_flow->handle_idx = handle_idx;
5768 * In some old rdma-core releases, before continuing, a check of the
5769 * length of matching parameter will be done at first. It needs to use
5770 * the length without misc4 param. If the flow has misc4 support, then
5771 * the length needs to be adjusted accordingly. Each param member is
5772 * aligned with a 64B boundary naturally.
5774 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
5775 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
5777 * The matching value needs to be cleared to 0 before using. In the
5778 * past, it will be automatically cleared when using rte_*alloc
5779 * API. The time consumption will be almost the same as before.
5781 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5782 dev_flow->ingress = attr->ingress;
5783 dev_flow->dv.transfer = attr->transfer;
5787 #ifdef RTE_LIBRTE_MLX5_DEBUG
5789 * Sanity check for match mask and value. Similar to check_valid_spec() in
5790 * kernel driver. If unmasked bit is present in value, it returns failure.
5793 * pointer to match mask buffer.
5794 * @param match_value
5795 * pointer to match value buffer.
5798 * 0 if valid, -EINVAL otherwise.
5801 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5803 uint8_t *m = match_mask;
5804 uint8_t *v = match_value;
5807 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5810 "match_value differs from match_criteria"
5811 " %p[%u] != %p[%u]",
5812 match_value, i, match_mask, i);
5821 * Add match of ip_version.
5825 * @param[in] headers_v
5826 * Values header pointer.
5827 * @param[in] headers_m
5828 * Masks header pointer.
5829 * @param[in] ip_version
5830 * The IP version to set.
5833 flow_dv_set_match_ip_version(uint32_t group,
5839 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5841 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5843 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5844 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5845 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5849 * Add Ethernet item to matcher and to the value.
5851 * @param[in, out] matcher
5853 * @param[in, out] key
5854 * Flow matcher value.
5856 * Flow pattern to translate.
5858 * Item is inner pattern.
5861 flow_dv_translate_item_eth(void *matcher, void *key,
5862 const struct rte_flow_item *item, int inner,
5865 const struct rte_flow_item_eth *eth_m = item->mask;
5866 const struct rte_flow_item_eth *eth_v = item->spec;
5867 const struct rte_flow_item_eth nic_mask = {
5868 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5869 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5870 .type = RTE_BE16(0xffff),
5882 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5884 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5886 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5888 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5890 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5891 ð_m->dst, sizeof(eth_m->dst));
5892 /* The value must be in the range of the mask. */
5893 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5894 for (i = 0; i < sizeof(eth_m->dst); ++i)
5895 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5896 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5897 ð_m->src, sizeof(eth_m->src));
5898 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5899 /* The value must be in the range of the mask. */
5900 for (i = 0; i < sizeof(eth_m->dst); ++i)
5901 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5903 /* When ethertype is present set mask for tagged VLAN. */
5904 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5905 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5906 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5907 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5908 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5910 /* Return here to avoid setting match on ethertype. */
5915 * HW supports match on one Ethertype, the Ethertype following the last
5916 * VLAN tag of the packet (see PRM).
5917 * Set match on ethertype only if ETH header is not followed by VLAN.
5918 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5919 * ethertype, and use ip_version field instead.
5920 * eCPRI over Ether layer will use type value 0xAEFE.
5922 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5923 eth_m->type == 0xFFFF) {
5924 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5925 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5926 eth_m->type == 0xFFFF) {
5927 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5929 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5930 rte_be_to_cpu_16(eth_m->type));
5931 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5933 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5938 * Add VLAN item to matcher and to the value.
5940 * @param[in, out] dev_flow
5942 * @param[in, out] matcher
5944 * @param[in, out] key
5945 * Flow matcher value.
5947 * Flow pattern to translate.
5949 * Item is inner pattern.
5952 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5953 void *matcher, void *key,
5954 const struct rte_flow_item *item,
5955 int inner, uint32_t group)
5957 const struct rte_flow_item_vlan *vlan_m = item->mask;
5958 const struct rte_flow_item_vlan *vlan_v = item->spec;
5965 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5967 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5969 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5971 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5973 * This is workaround, masks are not supported,
5974 * and pre-validated.
5977 dev_flow->handle->vf_vlan.tag =
5978 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5981 * When VLAN item exists in flow, mark packet as tagged,
5982 * even if TCI is not specified.
5984 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5985 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5989 vlan_m = &rte_flow_item_vlan_mask;
5990 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5991 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5992 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5993 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5994 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5995 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5996 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5997 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5999 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6000 * ethertype, and use ip_version field instead.
6002 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6003 vlan_m->inner_type == 0xFFFF) {
6004 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6005 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6006 vlan_m->inner_type == 0xFFFF) {
6007 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6009 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6010 rte_be_to_cpu_16(vlan_m->inner_type));
6011 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6012 rte_be_to_cpu_16(vlan_m->inner_type &
6013 vlan_v->inner_type));
6018 * Add IPV4 item to matcher and to the value.
6020 * @param[in, out] matcher
6022 * @param[in, out] key
6023 * Flow matcher value.
6025 * Flow pattern to translate.
6026 * @param[in] item_flags
6027 * Bit-fields that holds the items detected until now.
6029 * Item is inner pattern.
6031 * The group to insert the rule.
6034 flow_dv_translate_item_ipv4(void *matcher, void *key,
6035 const struct rte_flow_item *item,
6036 const uint64_t item_flags,
6037 int inner, uint32_t group)
6039 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6040 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6041 const struct rte_flow_item_ipv4 nic_mask = {
6043 .src_addr = RTE_BE32(0xffffffff),
6044 .dst_addr = RTE_BE32(0xffffffff),
6045 .type_of_service = 0xff,
6046 .next_proto_id = 0xff,
6047 .time_to_live = 0xff,
6057 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6059 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6061 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6063 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6065 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6067 * On outer header (which must contains L2), or inner header with L2,
6068 * set cvlan_tag mask bit to mark this packet as untagged.
6069 * This should be done even if item->spec is empty.
6071 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6072 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6077 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6078 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6079 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6080 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6081 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6082 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6083 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6084 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6085 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6086 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6087 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6088 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6089 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6090 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6091 ipv4_m->hdr.type_of_service);
6092 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6093 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6094 ipv4_m->hdr.type_of_service >> 2);
6095 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6096 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6097 ipv4_m->hdr.next_proto_id);
6098 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6099 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6100 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6101 ipv4_m->hdr.time_to_live);
6102 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6103 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6107 * Add IPV6 item to matcher and to the value.
6109 * @param[in, out] matcher
6111 * @param[in, out] key
6112 * Flow matcher value.
6114 * Flow pattern to translate.
6115 * @param[in] item_flags
6116 * Bit-fields that holds the items detected until now.
6118 * Item is inner pattern.
6120 * The group to insert the rule.
6123 flow_dv_translate_item_ipv6(void *matcher, void *key,
6124 const struct rte_flow_item *item,
6125 const uint64_t item_flags,
6126 int inner, uint32_t group)
6128 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6129 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6130 const struct rte_flow_item_ipv6 nic_mask = {
6133 "\xff\xff\xff\xff\xff\xff\xff\xff"
6134 "\xff\xff\xff\xff\xff\xff\xff\xff",
6136 "\xff\xff\xff\xff\xff\xff\xff\xff"
6137 "\xff\xff\xff\xff\xff\xff\xff\xff",
6138 .vtc_flow = RTE_BE32(0xffffffff),
6145 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6146 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6155 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6157 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6159 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6161 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6163 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6165 * On outer header (which must contains L2), or inner header with L2,
6166 * set cvlan_tag mask bit to mark this packet as untagged.
6167 * This should be done even if item->spec is empty.
6169 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6170 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6175 size = sizeof(ipv6_m->hdr.dst_addr);
6176 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6177 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6178 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6179 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6180 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6181 for (i = 0; i < size; ++i)
6182 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6183 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6184 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6185 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6186 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6187 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6188 for (i = 0; i < size; ++i)
6189 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6191 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6192 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6193 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6194 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6195 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6196 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6199 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6201 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6204 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6206 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6210 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6212 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6213 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6215 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6216 ipv6_m->hdr.hop_limits);
6217 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6218 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6222 * Add TCP item to matcher and to the value.
6224 * @param[in, out] matcher
6226 * @param[in, out] key
6227 * Flow matcher value.
6229 * Flow pattern to translate.
6231 * Item is inner pattern.
6234 flow_dv_translate_item_tcp(void *matcher, void *key,
6235 const struct rte_flow_item *item,
6238 const struct rte_flow_item_tcp *tcp_m = item->mask;
6239 const struct rte_flow_item_tcp *tcp_v = item->spec;
6244 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6246 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6248 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6250 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6252 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6253 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6257 tcp_m = &rte_flow_item_tcp_mask;
6258 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6259 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6260 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6261 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6262 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6263 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6264 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6265 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6266 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6267 tcp_m->hdr.tcp_flags);
6268 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6269 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6273 * Add UDP item to matcher and to the value.
6275 * @param[in, out] matcher
6277 * @param[in, out] key
6278 * Flow matcher value.
6280 * Flow pattern to translate.
6282 * Item is inner pattern.
6285 flow_dv_translate_item_udp(void *matcher, void *key,
6286 const struct rte_flow_item *item,
6289 const struct rte_flow_item_udp *udp_m = item->mask;
6290 const struct rte_flow_item_udp *udp_v = item->spec;
6295 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6297 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6299 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6301 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6303 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6304 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6308 udp_m = &rte_flow_item_udp_mask;
6309 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6310 rte_be_to_cpu_16(udp_m->hdr.src_port));
6311 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6312 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6313 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6314 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6315 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6316 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6320 * Add GRE optional Key item to matcher and to the value.
6322 * @param[in, out] matcher
6324 * @param[in, out] key
6325 * Flow matcher value.
6327 * Flow pattern to translate.
6329 * Item is inner pattern.
6332 flow_dv_translate_item_gre_key(void *matcher, void *key,
6333 const struct rte_flow_item *item)
6335 const rte_be32_t *key_m = item->mask;
6336 const rte_be32_t *key_v = item->spec;
6337 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6338 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6339 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6341 /* GRE K bit must be on and should already be validated */
6342 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6343 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6347 key_m = &gre_key_default_mask;
6348 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6349 rte_be_to_cpu_32(*key_m) >> 8);
6350 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6351 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6352 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6353 rte_be_to_cpu_32(*key_m) & 0xFF);
6354 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6355 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6359 * Add GRE item to matcher and to the value.
6361 * @param[in, out] matcher
6363 * @param[in, out] key
6364 * Flow matcher value.
6366 * Flow pattern to translate.
6368 * Item is inner pattern.
6371 flow_dv_translate_item_gre(void *matcher, void *key,
6372 const struct rte_flow_item *item,
6375 const struct rte_flow_item_gre *gre_m = item->mask;
6376 const struct rte_flow_item_gre *gre_v = item->spec;
6379 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6380 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6387 uint16_t s_present:1;
6388 uint16_t k_present:1;
6389 uint16_t rsvd_bit1:1;
6390 uint16_t c_present:1;
6394 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6397 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6399 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6401 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6403 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6405 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6406 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6410 gre_m = &rte_flow_item_gre_mask;
6411 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6412 rte_be_to_cpu_16(gre_m->protocol));
6413 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6414 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6415 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6416 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6417 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6418 gre_crks_rsvd0_ver_m.c_present);
6419 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6420 gre_crks_rsvd0_ver_v.c_present &
6421 gre_crks_rsvd0_ver_m.c_present);
6422 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6423 gre_crks_rsvd0_ver_m.k_present);
6424 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6425 gre_crks_rsvd0_ver_v.k_present &
6426 gre_crks_rsvd0_ver_m.k_present);
6427 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6428 gre_crks_rsvd0_ver_m.s_present);
6429 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6430 gre_crks_rsvd0_ver_v.s_present &
6431 gre_crks_rsvd0_ver_m.s_present);
6435 * Add NVGRE item to matcher and to the value.
6437 * @param[in, out] matcher
6439 * @param[in, out] key
6440 * Flow matcher value.
6442 * Flow pattern to translate.
6444 * Item is inner pattern.
6447 flow_dv_translate_item_nvgre(void *matcher, void *key,
6448 const struct rte_flow_item *item,
6451 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6452 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6453 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6454 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6455 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6456 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6462 /* For NVGRE, GRE header fields must be set with defined values. */
6463 const struct rte_flow_item_gre gre_spec = {
6464 .c_rsvd0_ver = RTE_BE16(0x2000),
6465 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6467 const struct rte_flow_item_gre gre_mask = {
6468 .c_rsvd0_ver = RTE_BE16(0xB000),
6469 .protocol = RTE_BE16(UINT16_MAX),
6471 const struct rte_flow_item gre_item = {
6476 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6480 nvgre_m = &rte_flow_item_nvgre_mask;
6481 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6482 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6483 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6484 memcpy(gre_key_m, tni_flow_id_m, size);
6485 for (i = 0; i < size; ++i)
6486 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6490 * Add VXLAN item to matcher and to the value.
6492 * @param[in, out] matcher
6494 * @param[in, out] key
6495 * Flow matcher value.
6497 * Flow pattern to translate.
6499 * Item is inner pattern.
6502 flow_dv_translate_item_vxlan(void *matcher, void *key,
6503 const struct rte_flow_item *item,
6506 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6507 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6510 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6511 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6519 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6521 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6523 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6525 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6527 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6528 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6529 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6530 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6531 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6536 vxlan_m = &rte_flow_item_vxlan_mask;
6537 size = sizeof(vxlan_m->vni);
6538 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6539 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6540 memcpy(vni_m, vxlan_m->vni, size);
6541 for (i = 0; i < size; ++i)
6542 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6546 * Add VXLAN-GPE item to matcher and to the value.
6548 * @param[in, out] matcher
6550 * @param[in, out] key
6551 * Flow matcher value.
6553 * Flow pattern to translate.
6555 * Item is inner pattern.
6559 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6560 const struct rte_flow_item *item, int inner)
6562 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6563 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6567 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6569 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6575 uint8_t flags_m = 0xff;
6576 uint8_t flags_v = 0xc;
6579 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6581 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6583 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6585 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6587 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6588 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6589 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6590 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6591 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6596 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6597 size = sizeof(vxlan_m->vni);
6598 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6599 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6600 memcpy(vni_m, vxlan_m->vni, size);
6601 for (i = 0; i < size; ++i)
6602 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6603 if (vxlan_m->flags) {
6604 flags_m = vxlan_m->flags;
6605 flags_v = vxlan_v->flags;
6607 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6608 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6609 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6611 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6616 * Add Geneve item to matcher and to the value.
6618 * @param[in, out] matcher
6620 * @param[in, out] key
6621 * Flow matcher value.
6623 * Flow pattern to translate.
6625 * Item is inner pattern.
6629 flow_dv_translate_item_geneve(void *matcher, void *key,
6630 const struct rte_flow_item *item, int inner)
6632 const struct rte_flow_item_geneve *geneve_m = item->mask;
6633 const struct rte_flow_item_geneve *geneve_v = item->spec;
6636 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6637 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6646 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6648 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6650 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6652 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6654 dport = MLX5_UDP_PORT_GENEVE;
6655 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6656 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6657 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6662 geneve_m = &rte_flow_item_geneve_mask;
6663 size = sizeof(geneve_m->vni);
6664 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6665 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6666 memcpy(vni_m, geneve_m->vni, size);
6667 for (i = 0; i < size; ++i)
6668 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6669 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6670 rte_be_to_cpu_16(geneve_m->protocol));
6671 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6672 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6673 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6674 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6675 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6676 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6677 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6678 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6679 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6680 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6681 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6682 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6683 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6687 * Add MPLS item to matcher and to the value.
6689 * @param[in, out] matcher
6691 * @param[in, out] key
6692 * Flow matcher value.
6694 * Flow pattern to translate.
6695 * @param[in] prev_layer
6696 * The protocol layer indicated in previous item.
6698 * Item is inner pattern.
6701 flow_dv_translate_item_mpls(void *matcher, void *key,
6702 const struct rte_flow_item *item,
6703 uint64_t prev_layer,
6706 const uint32_t *in_mpls_m = item->mask;
6707 const uint32_t *in_mpls_v = item->spec;
6708 uint32_t *out_mpls_m = 0;
6709 uint32_t *out_mpls_v = 0;
6710 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6711 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6712 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6714 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6715 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6716 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6718 switch (prev_layer) {
6719 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6720 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6721 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6722 MLX5_UDP_PORT_MPLS);
6724 case MLX5_FLOW_LAYER_GRE:
6725 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6726 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6727 RTE_ETHER_TYPE_MPLS);
6730 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6731 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6738 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6739 switch (prev_layer) {
6740 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6742 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6743 outer_first_mpls_over_udp);
6745 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6746 outer_first_mpls_over_udp);
6748 case MLX5_FLOW_LAYER_GRE:
6750 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6751 outer_first_mpls_over_gre);
6753 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6754 outer_first_mpls_over_gre);
6757 /* Inner MPLS not over GRE is not supported. */
6760 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6764 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6770 if (out_mpls_m && out_mpls_v) {
6771 *out_mpls_m = *in_mpls_m;
6772 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6777 * Add metadata register item to matcher
6779 * @param[in, out] matcher
6781 * @param[in, out] key
6782 * Flow matcher value.
6783 * @param[in] reg_type
6784 * Type of device metadata register
6791 flow_dv_match_meta_reg(void *matcher, void *key,
6792 enum modify_reg reg_type,
6793 uint32_t data, uint32_t mask)
6796 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6798 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6804 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6805 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6808 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6809 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6813 * The metadata register C0 field might be divided into
6814 * source vport index and META item value, we should set
6815 * this field according to specified mask, not as whole one.
6817 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6819 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6820 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6823 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6826 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6827 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6830 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6831 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6834 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6835 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6838 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6839 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6842 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6843 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6846 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6847 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6850 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6851 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6860 * Add MARK item to matcher
6863 * The device to configure through.
6864 * @param[in, out] matcher
6866 * @param[in, out] key
6867 * Flow matcher value.
6869 * Flow pattern to translate.
6872 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6873 void *matcher, void *key,
6874 const struct rte_flow_item *item)
6876 struct mlx5_priv *priv = dev->data->dev_private;
6877 const struct rte_flow_item_mark *mark;
6881 mark = item->mask ? (const void *)item->mask :
6882 &rte_flow_item_mark_mask;
6883 mask = mark->id & priv->sh->dv_mark_mask;
6884 mark = (const void *)item->spec;
6886 value = mark->id & priv->sh->dv_mark_mask & mask;
6888 enum modify_reg reg;
6890 /* Get the metadata register index for the mark. */
6891 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6892 MLX5_ASSERT(reg > 0);
6893 if (reg == REG_C_0) {
6894 struct mlx5_priv *priv = dev->data->dev_private;
6895 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6896 uint32_t shl_c0 = rte_bsf32(msk_c0);
6902 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6907 * Add META item to matcher
6910 * The devich to configure through.
6911 * @param[in, out] matcher
6913 * @param[in, out] key
6914 * Flow matcher value.
6916 * Attributes of flow that includes this item.
6918 * Flow pattern to translate.
6921 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6922 void *matcher, void *key,
6923 const struct rte_flow_attr *attr,
6924 const struct rte_flow_item *item)
6926 const struct rte_flow_item_meta *meta_m;
6927 const struct rte_flow_item_meta *meta_v;
6929 meta_m = (const void *)item->mask;
6931 meta_m = &rte_flow_item_meta_mask;
6932 meta_v = (const void *)item->spec;
6935 uint32_t value = meta_v->data;
6936 uint32_t mask = meta_m->data;
6938 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6942 * In datapath code there is no endianness
6943 * coversions for perfromance reasons, all
6944 * pattern conversions are done in rte_flow.
6946 value = rte_cpu_to_be_32(value);
6947 mask = rte_cpu_to_be_32(mask);
6948 if (reg == REG_C_0) {
6949 struct mlx5_priv *priv = dev->data->dev_private;
6950 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6951 uint32_t shl_c0 = rte_bsf32(msk_c0);
6952 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6953 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6960 MLX5_ASSERT(msk_c0);
6961 MLX5_ASSERT(!(~msk_c0 & mask));
6963 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6968 * Add vport metadata Reg C0 item to matcher
6970 * @param[in, out] matcher
6972 * @param[in, out] key
6973 * Flow matcher value.
6975 * Flow pattern to translate.
6978 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6979 uint32_t value, uint32_t mask)
6981 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6985 * Add tag item to matcher
6988 * The devich to configure through.
6989 * @param[in, out] matcher
6991 * @param[in, out] key
6992 * Flow matcher value.
6994 * Flow pattern to translate.
6997 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6998 void *matcher, void *key,
6999 const struct rte_flow_item *item)
7001 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7002 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7003 uint32_t mask, value;
7006 value = tag_v->data;
7007 mask = tag_m ? tag_m->data : UINT32_MAX;
7008 if (tag_v->id == REG_C_0) {
7009 struct mlx5_priv *priv = dev->data->dev_private;
7010 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7011 uint32_t shl_c0 = rte_bsf32(msk_c0);
7017 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7021 * Add TAG item to matcher
7024 * The devich to configure through.
7025 * @param[in, out] matcher
7027 * @param[in, out] key
7028 * Flow matcher value.
7030 * Flow pattern to translate.
7033 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7034 void *matcher, void *key,
7035 const struct rte_flow_item *item)
7037 const struct rte_flow_item_tag *tag_v = item->spec;
7038 const struct rte_flow_item_tag *tag_m = item->mask;
7039 enum modify_reg reg;
7042 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7043 /* Get the metadata register index for the tag. */
7044 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7045 MLX5_ASSERT(reg > 0);
7046 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7050 * Add source vport match to the specified matcher.
7052 * @param[in, out] matcher
7054 * @param[in, out] key
7055 * Flow matcher value.
7057 * Source vport value to match
7062 flow_dv_translate_item_source_vport(void *matcher, void *key,
7063 int16_t port, uint16_t mask)
7065 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7066 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7068 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7069 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7073 * Translate port-id item to eswitch match on port-id.
7076 * The devich to configure through.
7077 * @param[in, out] matcher
7079 * @param[in, out] key
7080 * Flow matcher value.
7082 * Flow pattern to translate.
7085 * 0 on success, a negative errno value otherwise.
7088 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7089 void *key, const struct rte_flow_item *item)
7091 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7092 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7093 struct mlx5_priv *priv;
7096 mask = pid_m ? pid_m->id : 0xffff;
7097 id = pid_v ? pid_v->id : dev->data->port_id;
7098 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7101 /* Translate to vport field or to metadata, depending on mode. */
7102 if (priv->vport_meta_mask)
7103 flow_dv_translate_item_meta_vport(matcher, key,
7104 priv->vport_meta_tag,
7105 priv->vport_meta_mask);
7107 flow_dv_translate_item_source_vport(matcher, key,
7108 priv->vport_id, mask);
7113 * Add ICMP6 item to matcher and to the value.
7115 * @param[in, out] matcher
7117 * @param[in, out] key
7118 * Flow matcher value.
7120 * Flow pattern to translate.
7122 * Item is inner pattern.
7125 flow_dv_translate_item_icmp6(void *matcher, void *key,
7126 const struct rte_flow_item *item,
7129 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7130 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7133 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7135 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7137 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7139 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7141 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7143 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7145 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7146 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7150 icmp6_m = &rte_flow_item_icmp6_mask;
7152 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7153 * If only the protocol is specified, no need to match the frag.
7155 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7156 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7157 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7158 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7159 icmp6_v->type & icmp6_m->type);
7160 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7161 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7162 icmp6_v->code & icmp6_m->code);
7166 * Add ICMP item to matcher and to the value.
7168 * @param[in, out] matcher
7170 * @param[in, out] key
7171 * Flow matcher value.
7173 * Flow pattern to translate.
7175 * Item is inner pattern.
7178 flow_dv_translate_item_icmp(void *matcher, void *key,
7179 const struct rte_flow_item *item,
7182 const struct rte_flow_item_icmp *icmp_m = item->mask;
7183 const struct rte_flow_item_icmp *icmp_v = item->spec;
7186 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7188 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7190 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7192 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7194 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7196 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7198 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7199 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7203 icmp_m = &rte_flow_item_icmp_mask;
7205 * Force flow only to match the non-fragmented IPv4 ICMP packets.
7206 * If only the protocol is specified, no need to match the frag.
7208 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7209 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7210 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7211 icmp_m->hdr.icmp_type);
7212 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7213 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7214 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7215 icmp_m->hdr.icmp_code);
7216 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7217 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7221 * Add GTP item to matcher and to the value.
7223 * @param[in, out] matcher
7225 * @param[in, out] key
7226 * Flow matcher value.
7228 * Flow pattern to translate.
7230 * Item is inner pattern.
7233 flow_dv_translate_item_gtp(void *matcher, void *key,
7234 const struct rte_flow_item *item, int inner)
7236 const struct rte_flow_item_gtp *gtp_m = item->mask;
7237 const struct rte_flow_item_gtp *gtp_v = item->spec;
7240 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7242 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7243 uint16_t dport = RTE_GTPU_UDP_PORT;
7246 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7248 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7250 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7252 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7254 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7255 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7256 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7261 gtp_m = &rte_flow_item_gtp_mask;
7262 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7263 gtp_m->v_pt_rsv_flags);
7264 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7265 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7266 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7267 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7268 gtp_v->msg_type & gtp_m->msg_type);
7269 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7270 rte_be_to_cpu_32(gtp_m->teid));
7271 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7272 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7276 * Add eCPRI item to matcher and to the value.
7279 * The devich to configure through.
7280 * @param[in, out] matcher
7282 * @param[in, out] key
7283 * Flow matcher value.
7285 * Flow pattern to translate.
7286 * @param[in] samples
7287 * Sample IDs to be used in the matching.
7290 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7291 void *key, const struct rte_flow_item *item)
7293 struct mlx5_priv *priv = dev->data->dev_private;
7294 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7295 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7296 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7298 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7306 ecpri_m = &rte_flow_item_ecpri_mask;
7308 * Maximal four DW samples are supported in a single matching now.
7309 * Two are used now for a eCPRI matching:
7310 * 1. Type: one byte, mask should be 0x00ff0000 in network order
7311 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7314 if (!ecpri_m->hdr.common.u32)
7316 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7317 /* Need to take the whole DW as the mask to fill the entry. */
7318 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7319 prog_sample_field_value_0);
7320 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7321 prog_sample_field_value_0);
7322 /* Already big endian (network order) in the header. */
7323 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7324 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7325 /* Sample#0, used for matching type, offset 0. */
7326 MLX5_SET(fte_match_set_misc4, misc4_m,
7327 prog_sample_field_id_0, samples[0]);
7328 /* It makes no sense to set the sample ID in the mask field. */
7329 MLX5_SET(fte_match_set_misc4, misc4_v,
7330 prog_sample_field_id_0, samples[0]);
7332 * Checking if message body part needs to be matched.
7333 * Some wildcard rules only matching type field should be supported.
7335 if (ecpri_m->hdr.dummy[0]) {
7336 switch (ecpri_v->hdr.common.type) {
7337 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7338 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7339 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7340 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7341 prog_sample_field_value_1);
7342 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7343 prog_sample_field_value_1);
7344 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7345 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7346 /* Sample#1, to match message body, offset 4. */
7347 MLX5_SET(fte_match_set_misc4, misc4_m,
7348 prog_sample_field_id_1, samples[1]);
7349 MLX5_SET(fte_match_set_misc4, misc4_v,
7350 prog_sample_field_id_1, samples[1]);
7353 /* Others, do not match any sample ID. */
7359 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7361 #define HEADER_IS_ZERO(match_criteria, headers) \
7362 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7363 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7366 * Calculate flow matcher enable bitmap.
7368 * @param match_criteria
7369 * Pointer to flow matcher criteria.
7372 * Bitmap of enabled fields.
7375 flow_dv_matcher_enable(uint32_t *match_criteria)
7377 uint8_t match_criteria_enable;
7379 match_criteria_enable =
7380 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7381 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7382 match_criteria_enable |=
7383 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7384 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7385 match_criteria_enable |=
7386 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7387 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7388 match_criteria_enable |=
7389 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7390 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7391 match_criteria_enable |=
7392 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7393 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7394 match_criteria_enable |=
7395 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7396 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7397 return match_criteria_enable;
7404 * @param[in, out] dev
7405 * Pointer to rte_eth_dev structure.
7406 * @param[in] table_id
7409 * Direction of the table.
7410 * @param[in] transfer
7411 * E-Switch or NIC flow.
7413 * pointer to error structure.
7416 * Returns tables resource based on the index, NULL in case of failed.
7418 static struct mlx5_flow_tbl_resource *
7419 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7420 uint32_t table_id, uint8_t egress,
7422 struct rte_flow_error *error)
7424 struct mlx5_priv *priv = dev->data->dev_private;
7425 struct mlx5_dev_ctx_shared *sh = priv->sh;
7426 struct mlx5_flow_tbl_resource *tbl;
7427 union mlx5_flow_tbl_key table_key = {
7429 .table_id = table_id,
7431 .domain = !!transfer,
7432 .direction = !!egress,
7435 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7437 struct mlx5_flow_tbl_data_entry *tbl_data;
7443 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7445 tbl = &tbl_data->tbl;
7446 rte_atomic32_inc(&tbl->refcnt);
7449 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7451 rte_flow_error_set(error, ENOMEM,
7452 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7454 "cannot allocate flow table data entry");
7457 tbl_data->idx = idx;
7458 tbl = &tbl_data->tbl;
7459 pos = &tbl_data->entry;
7461 domain = sh->fdb_domain;
7463 domain = sh->tx_domain;
7465 domain = sh->rx_domain;
7466 ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7468 rte_flow_error_set(error, ENOMEM,
7469 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7470 NULL, "cannot create flow table object");
7471 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7475 * No multi-threads now, but still better to initialize the reference
7476 * count before insert it into the hash list.
7478 rte_atomic32_init(&tbl->refcnt);
7479 /* Jump action reference count is initialized here. */
7480 rte_atomic32_init(&tbl_data->jump.refcnt);
7481 pos->key = table_key.v64;
7482 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7484 rte_flow_error_set(error, -ret,
7485 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7486 "cannot insert flow table data entry");
7487 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7488 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7490 rte_atomic32_inc(&tbl->refcnt);
7495 * Release a flow table.
7498 * Pointer to rte_eth_dev structure.
7500 * Table resource to be released.
7503 * Returns 0 if table was released, else return 1;
7506 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7507 struct mlx5_flow_tbl_resource *tbl)
7509 struct mlx5_priv *priv = dev->data->dev_private;
7510 struct mlx5_dev_ctx_shared *sh = priv->sh;
7511 struct mlx5_flow_tbl_data_entry *tbl_data =
7512 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7516 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7517 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7519 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7521 /* remove the entry from the hash list and free memory. */
7522 mlx5_hlist_remove(sh->flow_tbls, pos);
7523 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7531 * Register the flow matcher.
7533 * @param[in, out] dev
7534 * Pointer to rte_eth_dev structure.
7535 * @param[in, out] matcher
7536 * Pointer to flow matcher.
7537 * @param[in, out] key
7538 * Pointer to flow table key.
7539 * @parm[in, out] dev_flow
7540 * Pointer to the dev_flow.
7542 * pointer to error structure.
7545 * 0 on success otherwise -errno and errno is set.
7548 flow_dv_matcher_register(struct rte_eth_dev *dev,
7549 struct mlx5_flow_dv_matcher *matcher,
7550 union mlx5_flow_tbl_key *key,
7551 struct mlx5_flow *dev_flow,
7552 struct rte_flow_error *error)
7554 struct mlx5_priv *priv = dev->data->dev_private;
7555 struct mlx5_dev_ctx_shared *sh = priv->sh;
7556 struct mlx5_flow_dv_matcher *cache_matcher;
7557 struct mlx5dv_flow_matcher_attr dv_attr = {
7558 .type = IBV_FLOW_ATTR_NORMAL,
7559 .match_mask = (void *)&matcher->mask,
7561 struct mlx5_flow_tbl_resource *tbl;
7562 struct mlx5_flow_tbl_data_entry *tbl_data;
7565 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7566 key->domain, error);
7568 return -rte_errno; /* No need to refill the error info */
7569 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7570 /* Lookup from cache. */
7571 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7572 if (matcher->crc == cache_matcher->crc &&
7573 matcher->priority == cache_matcher->priority &&
7574 !memcmp((const void *)matcher->mask.buf,
7575 (const void *)cache_matcher->mask.buf,
7576 cache_matcher->mask.size)) {
7578 "%s group %u priority %hd use %s "
7579 "matcher %p: refcnt %d++",
7580 key->domain ? "FDB" : "NIC", key->table_id,
7581 cache_matcher->priority,
7582 key->direction ? "tx" : "rx",
7583 (void *)cache_matcher,
7584 rte_atomic32_read(&cache_matcher->refcnt));
7585 rte_atomic32_inc(&cache_matcher->refcnt);
7586 dev_flow->handle->dvh.matcher = cache_matcher;
7587 /* old matcher should not make the table ref++. */
7588 flow_dv_tbl_resource_release(dev, tbl);
7592 /* Register new matcher. */
7593 cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
7595 if (!cache_matcher) {
7596 flow_dv_tbl_resource_release(dev, tbl);
7597 return rte_flow_error_set(error, ENOMEM,
7598 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7599 "cannot allocate matcher memory");
7601 *cache_matcher = *matcher;
7602 dv_attr.match_criteria_enable =
7603 flow_dv_matcher_enable(cache_matcher->mask.buf);
7604 dv_attr.priority = matcher->priority;
7606 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7607 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7608 &cache_matcher->matcher_object);
7610 mlx5_free(cache_matcher);
7611 #ifdef HAVE_MLX5DV_DR
7612 flow_dv_tbl_resource_release(dev, tbl);
7614 return rte_flow_error_set(error, ENOMEM,
7615 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7616 NULL, "cannot create matcher");
7618 /* Save the table information */
7619 cache_matcher->tbl = tbl;
7620 rte_atomic32_init(&cache_matcher->refcnt);
7621 /* only matcher ref++, table ref++ already done above in get API. */
7622 rte_atomic32_inc(&cache_matcher->refcnt);
7623 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7624 dev_flow->handle->dvh.matcher = cache_matcher;
7625 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7626 key->domain ? "FDB" : "NIC", key->table_id,
7627 cache_matcher->priority,
7628 key->direction ? "tx" : "rx", (void *)cache_matcher,
7629 rte_atomic32_read(&cache_matcher->refcnt));
7634 * Find existing tag resource or create and register a new one.
7636 * @param dev[in, out]
7637 * Pointer to rte_eth_dev structure.
7638 * @param[in, out] tag_be24
7639 * Tag value in big endian then R-shift 8.
7640 * @parm[in, out] dev_flow
7641 * Pointer to the dev_flow.
7643 * pointer to error structure.
7646 * 0 on success otherwise -errno and errno is set.
7649 flow_dv_tag_resource_register
7650 (struct rte_eth_dev *dev,
7652 struct mlx5_flow *dev_flow,
7653 struct rte_flow_error *error)
7655 struct mlx5_priv *priv = dev->data->dev_private;
7656 struct mlx5_dev_ctx_shared *sh = priv->sh;
7657 struct mlx5_flow_dv_tag_resource *cache_resource;
7658 struct mlx5_hlist_entry *entry;
7661 /* Lookup a matching resource from cache. */
7662 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7664 cache_resource = container_of
7665 (entry, struct mlx5_flow_dv_tag_resource, entry);
7666 rte_atomic32_inc(&cache_resource->refcnt);
7667 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7668 dev_flow->dv.tag_resource = cache_resource;
7669 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7670 (void *)cache_resource,
7671 rte_atomic32_read(&cache_resource->refcnt));
7674 /* Register new resource. */
7675 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7676 &dev_flow->handle->dvh.rix_tag);
7677 if (!cache_resource)
7678 return rte_flow_error_set(error, ENOMEM,
7679 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7680 "cannot allocate resource memory");
7681 cache_resource->entry.key = (uint64_t)tag_be24;
7682 ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
7683 &cache_resource->action);
7685 mlx5_free(cache_resource);
7686 return rte_flow_error_set(error, ENOMEM,
7687 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7688 NULL, "cannot create action");
7690 rte_atomic32_init(&cache_resource->refcnt);
7691 rte_atomic32_inc(&cache_resource->refcnt);
7692 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7693 mlx5_flow_os_destroy_flow_action(cache_resource->action);
7694 mlx5_free(cache_resource);
7695 return rte_flow_error_set(error, EEXIST,
7696 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7697 NULL, "cannot insert tag");
7699 dev_flow->dv.tag_resource = cache_resource;
7700 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7701 (void *)cache_resource,
7702 rte_atomic32_read(&cache_resource->refcnt));
7710 * Pointer to Ethernet device.
7715 * 1 while a reference on it exists, 0 when freed.
7718 flow_dv_tag_release(struct rte_eth_dev *dev,
7721 struct mlx5_priv *priv = dev->data->dev_private;
7722 struct mlx5_dev_ctx_shared *sh = priv->sh;
7723 struct mlx5_flow_dv_tag_resource *tag;
7725 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7728 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7729 dev->data->port_id, (void *)tag,
7730 rte_atomic32_read(&tag->refcnt));
7731 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7732 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
7733 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7734 DRV_LOG(DEBUG, "port %u tag %p: removed",
7735 dev->data->port_id, (void *)tag);
7736 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7743 * Translate port ID action to vport.
7746 * Pointer to rte_eth_dev structure.
7748 * Pointer to the port ID action.
7749 * @param[out] dst_port_id
7750 * The target port ID.
7752 * Pointer to the error structure.
7755 * 0 on success, a negative errno value otherwise and rte_errno is set.
7758 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7759 const struct rte_flow_action *action,
7760 uint32_t *dst_port_id,
7761 struct rte_flow_error *error)
7764 struct mlx5_priv *priv;
7765 const struct rte_flow_action_port_id *conf =
7766 (const struct rte_flow_action_port_id *)action->conf;
7768 port = conf->original ? dev->data->port_id : conf->id;
7769 priv = mlx5_port_to_eswitch_info(port, false);
7771 return rte_flow_error_set(error, -rte_errno,
7772 RTE_FLOW_ERROR_TYPE_ACTION,
7774 "No eswitch info was found for port");
7775 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7777 * This parameter is transferred to
7778 * mlx5dv_dr_action_create_dest_ib_port().
7780 *dst_port_id = priv->dev_port;
7783 * Legacy mode, no LAG configurations is supported.
7784 * This parameter is transferred to
7785 * mlx5dv_dr_action_create_dest_vport().
7787 *dst_port_id = priv->vport_id;
7793 * Create a counter with aging configuration.
7796 * Pointer to rte_eth_dev structure.
7798 * Pointer to the counter action configuration.
7800 * Pointer to the aging action configuration.
7803 * Index to flow counter on success, 0 otherwise.
7806 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7807 struct mlx5_flow *dev_flow,
7808 const struct rte_flow_action_count *count,
7809 const struct rte_flow_action_age *age)
7812 struct mlx5_age_param *age_param;
7814 counter = flow_dv_counter_alloc(dev,
7815 count ? count->shared : 0,
7816 count ? count->id : 0,
7817 dev_flow->dv.group, !!age);
7818 if (!counter || age == NULL)
7820 age_param = flow_dv_counter_idx_get_age(dev, counter);
7822 * The counter age accuracy may have a bit delay. Have 3/4
7823 * second bias on the timeount in order to let it age in time.
7825 age_param->context = age->context ? age->context :
7826 (void *)(uintptr_t)(dev_flow->flow_idx);
7828 * The counter age accuracy may have a bit delay. Have 3/4
7829 * second bias on the timeount in order to let it age in time.
7831 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7832 /* Set expire time in unit of 0.1 sec. */
7833 age_param->port_id = dev->data->port_id;
7834 age_param->expire = age_param->timeout +
7835 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7836 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7840 * Add Tx queue matcher
7843 * Pointer to the dev struct.
7844 * @param[in, out] matcher
7846 * @param[in, out] key
7847 * Flow matcher value.
7849 * Flow pattern to translate.
7851 * Item is inner pattern.
7854 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7855 void *matcher, void *key,
7856 const struct rte_flow_item *item)
7858 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7859 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7861 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7863 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7864 struct mlx5_txq_ctrl *txq;
7868 queue_m = (const void *)item->mask;
7871 queue_v = (const void *)item->spec;
7874 txq = mlx5_txq_get(dev, queue_v->queue);
7877 queue = txq->obj->sq->id;
7878 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7879 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7880 queue & queue_m->queue);
7881 mlx5_txq_release(dev, queue_v->queue);
7885 * Set the hash fields according to the @p flow information.
7887 * @param[in] dev_flow
7888 * Pointer to the mlx5_flow.
7889 * @param[in] rss_desc
7890 * Pointer to the mlx5_flow_rss_desc.
7893 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7894 struct mlx5_flow_rss_desc *rss_desc)
7896 uint64_t items = dev_flow->handle->layers;
7898 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7900 dev_flow->hash_fields = 0;
7901 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7902 if (rss_desc->level >= 2) {
7903 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7907 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7908 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7909 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7910 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7911 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7912 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7913 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7915 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7917 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7918 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7919 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7920 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7921 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7922 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7923 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7925 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7928 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7929 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7930 if (rss_types & ETH_RSS_UDP) {
7931 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7932 dev_flow->hash_fields |=
7933 IBV_RX_HASH_SRC_PORT_UDP;
7934 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7935 dev_flow->hash_fields |=
7936 IBV_RX_HASH_DST_PORT_UDP;
7938 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7940 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7941 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7942 if (rss_types & ETH_RSS_TCP) {
7943 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7944 dev_flow->hash_fields |=
7945 IBV_RX_HASH_SRC_PORT_TCP;
7946 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7947 dev_flow->hash_fields |=
7948 IBV_RX_HASH_DST_PORT_TCP;
7950 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7956 * Fill the flow with DV spec, lock free
7957 * (mutex should be acquired by caller).
7960 * Pointer to rte_eth_dev structure.
7961 * @param[in, out] dev_flow
7962 * Pointer to the sub flow.
7964 * Pointer to the flow attributes.
7966 * Pointer to the list of items.
7967 * @param[in] actions
7968 * Pointer to the list of actions.
7970 * Pointer to the error structure.
7973 * 0 on success, a negative errno value otherwise and rte_errno is set.
7976 __flow_dv_translate(struct rte_eth_dev *dev,
7977 struct mlx5_flow *dev_flow,
7978 const struct rte_flow_attr *attr,
7979 const struct rte_flow_item items[],
7980 const struct rte_flow_action actions[],
7981 struct rte_flow_error *error)
7983 struct mlx5_priv *priv = dev->data->dev_private;
7984 struct mlx5_dev_config *dev_conf = &priv->config;
7985 struct rte_flow *flow = dev_flow->flow;
7986 struct mlx5_flow_handle *handle = dev_flow->handle;
7987 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7989 [!!priv->flow_nested_idx];
7990 uint64_t item_flags = 0;
7991 uint64_t last_item = 0;
7992 uint64_t action_flags = 0;
7993 uint64_t priority = attr->priority;
7994 struct mlx5_flow_dv_matcher matcher = {
7996 .size = sizeof(matcher.mask.buf) -
7997 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
8001 bool actions_end = false;
8003 struct mlx5_flow_dv_modify_hdr_resource res;
8004 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
8005 sizeof(struct mlx5_modification_cmd) *
8006 (MLX5_MAX_MODIFY_NUM + 1)];
8008 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
8009 const struct rte_flow_action_count *count = NULL;
8010 const struct rte_flow_action_age *age = NULL;
8011 union flow_dv_attr flow_attr = { .attr = 0 };
8013 union mlx5_flow_tbl_key tbl_key;
8014 uint32_t modify_action_position = UINT32_MAX;
8015 void *match_mask = matcher.mask.buf;
8016 void *match_value = dev_flow->dv.value.buf;
8017 uint8_t next_protocol = 0xff;
8018 struct rte_vlan_hdr vlan = { 0 };
8022 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
8023 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8024 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
8025 !!priv->fdb_def_rule, &table, error);
8028 dev_flow->dv.group = table;
8030 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8031 if (priority == MLX5_FLOW_PRIO_RSVD)
8032 priority = dev_conf->flow_prio - 1;
8033 /* number of actions must be set to 0 in case of dirty stack. */
8034 mhdr_res->actions_num = 0;
8035 for (; !actions_end ; actions++) {
8036 const struct rte_flow_action_queue *queue;
8037 const struct rte_flow_action_rss *rss;
8038 const struct rte_flow_action *action = actions;
8039 const uint8_t *rss_key;
8040 const struct rte_flow_action_jump *jump_data;
8041 const struct rte_flow_action_meter *mtr;
8042 struct mlx5_flow_tbl_resource *tbl;
8043 uint32_t port_id = 0;
8044 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
8045 int action_type = actions->type;
8046 const struct rte_flow_action *found_action = NULL;
8047 struct mlx5_flow_meter *fm = NULL;
8049 if (!mlx5_flow_os_action_supported(action_type))
8050 return rte_flow_error_set(error, ENOTSUP,
8051 RTE_FLOW_ERROR_TYPE_ACTION,
8053 "action not supported");
8054 switch (action_type) {
8055 case RTE_FLOW_ACTION_TYPE_VOID:
8057 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8058 if (flow_dv_translate_action_port_id(dev, action,
8061 port_id_resource.port_id = port_id;
8062 MLX5_ASSERT(!handle->rix_port_id_action);
8063 if (flow_dv_port_id_action_resource_register
8064 (dev, &port_id_resource, dev_flow, error))
8066 dev_flow->dv.actions[actions_n++] =
8067 dev_flow->dv.port_id_action->action;
8068 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
8069 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
8071 case RTE_FLOW_ACTION_TYPE_FLAG:
8072 action_flags |= MLX5_FLOW_ACTION_FLAG;
8073 dev_flow->handle->mark = 1;
8074 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8075 struct rte_flow_action_mark mark = {
8076 .id = MLX5_FLOW_MARK_DEFAULT,
8079 if (flow_dv_convert_action_mark(dev, &mark,
8083 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8086 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
8088 * Only one FLAG or MARK is supported per device flow
8089 * right now. So the pointer to the tag resource must be
8090 * zero before the register process.
8092 MLX5_ASSERT(!handle->dvh.rix_tag);
8093 if (flow_dv_tag_resource_register(dev, tag_be,
8096 MLX5_ASSERT(dev_flow->dv.tag_resource);
8097 dev_flow->dv.actions[actions_n++] =
8098 dev_flow->dv.tag_resource->action;
8100 case RTE_FLOW_ACTION_TYPE_MARK:
8101 action_flags |= MLX5_FLOW_ACTION_MARK;
8102 dev_flow->handle->mark = 1;
8103 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8104 const struct rte_flow_action_mark *mark =
8105 (const struct rte_flow_action_mark *)
8108 if (flow_dv_convert_action_mark(dev, mark,
8112 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8116 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
8117 /* Legacy (non-extensive) MARK action. */
8118 tag_be = mlx5_flow_mark_set
8119 (((const struct rte_flow_action_mark *)
8120 (actions->conf))->id);
8121 MLX5_ASSERT(!handle->dvh.rix_tag);
8122 if (flow_dv_tag_resource_register(dev, tag_be,
8125 MLX5_ASSERT(dev_flow->dv.tag_resource);
8126 dev_flow->dv.actions[actions_n++] =
8127 dev_flow->dv.tag_resource->action;
8129 case RTE_FLOW_ACTION_TYPE_SET_META:
8130 if (flow_dv_convert_action_set_meta
8131 (dev, mhdr_res, attr,
8132 (const struct rte_flow_action_set_meta *)
8133 actions->conf, error))
8135 action_flags |= MLX5_FLOW_ACTION_SET_META;
8137 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8138 if (flow_dv_convert_action_set_tag
8140 (const struct rte_flow_action_set_tag *)
8141 actions->conf, error))
8143 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8145 case RTE_FLOW_ACTION_TYPE_DROP:
8146 action_flags |= MLX5_FLOW_ACTION_DROP;
8147 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8149 case RTE_FLOW_ACTION_TYPE_QUEUE:
8150 queue = actions->conf;
8151 rss_desc->queue_num = 1;
8152 rss_desc->queue[0] = queue->index;
8153 action_flags |= MLX5_FLOW_ACTION_QUEUE;
8154 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8156 case RTE_FLOW_ACTION_TYPE_RSS:
8157 rss = actions->conf;
8158 memcpy(rss_desc->queue, rss->queue,
8159 rss->queue_num * sizeof(uint16_t));
8160 rss_desc->queue_num = rss->queue_num;
8161 /* NULL RSS key indicates default RSS key. */
8162 rss_key = !rss->key ? rss_hash_default_key : rss->key;
8163 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8165 * rss->level and rss.types should be set in advance
8166 * when expanding items for RSS.
8168 action_flags |= MLX5_FLOW_ACTION_RSS;
8169 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8171 case RTE_FLOW_ACTION_TYPE_AGE:
8172 case RTE_FLOW_ACTION_TYPE_COUNT:
8173 if (!dev_conf->devx) {
8174 return rte_flow_error_set
8176 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8178 "count action not supported");
8180 /* Save information first, will apply later. */
8181 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8182 count = action->conf;
8185 action_flags |= MLX5_FLOW_ACTION_COUNT;
8187 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8188 dev_flow->dv.actions[actions_n++] =
8189 priv->sh->pop_vlan_action;
8190 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8192 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8193 if (!(action_flags &
8194 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8195 flow_dev_get_vlan_info_from_items(items, &vlan);
8196 vlan.eth_proto = rte_be_to_cpu_16
8197 ((((const struct rte_flow_action_of_push_vlan *)
8198 actions->conf)->ethertype));
8199 found_action = mlx5_flow_find_action
8201 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8203 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8204 found_action = mlx5_flow_find_action
8206 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8208 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8209 if (flow_dv_create_action_push_vlan
8210 (dev, attr, &vlan, dev_flow, error))
8212 dev_flow->dv.actions[actions_n++] =
8213 dev_flow->dv.push_vlan_res->action;
8214 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8216 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8217 /* of_vlan_push action handled this action */
8218 MLX5_ASSERT(action_flags &
8219 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8221 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8222 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8224 flow_dev_get_vlan_info_from_items(items, &vlan);
8225 mlx5_update_vlan_vid_pcp(actions, &vlan);
8226 /* If no VLAN push - this is a modify header action */
8227 if (flow_dv_convert_action_modify_vlan_vid
8228 (mhdr_res, actions, error))
8230 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8232 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8233 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8234 if (flow_dv_create_action_l2_encap(dev, actions,
8239 dev_flow->dv.actions[actions_n++] =
8240 dev_flow->dv.encap_decap->action;
8241 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8243 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8244 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8245 if (flow_dv_create_action_l2_decap(dev, dev_flow,
8249 dev_flow->dv.actions[actions_n++] =
8250 dev_flow->dv.encap_decap->action;
8251 action_flags |= MLX5_FLOW_ACTION_DECAP;
8253 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8254 /* Handle encap with preceding decap. */
8255 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8256 if (flow_dv_create_action_raw_encap
8257 (dev, actions, dev_flow, attr, error))
8259 dev_flow->dv.actions[actions_n++] =
8260 dev_flow->dv.encap_decap->action;
8262 /* Handle encap without preceding decap. */
8263 if (flow_dv_create_action_l2_encap
8264 (dev, actions, dev_flow, attr->transfer,
8267 dev_flow->dv.actions[actions_n++] =
8268 dev_flow->dv.encap_decap->action;
8270 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8272 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8273 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8275 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8276 if (flow_dv_create_action_l2_decap
8277 (dev, dev_flow, attr->transfer, error))
8279 dev_flow->dv.actions[actions_n++] =
8280 dev_flow->dv.encap_decap->action;
8282 /* If decap is followed by encap, handle it at encap. */
8283 action_flags |= MLX5_FLOW_ACTION_DECAP;
8285 case RTE_FLOW_ACTION_TYPE_JUMP:
8286 jump_data = action->conf;
8287 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8289 !!priv->fdb_def_rule,
8293 tbl = flow_dv_tbl_resource_get(dev, table,
8295 attr->transfer, error);
8297 return rte_flow_error_set
8299 RTE_FLOW_ERROR_TYPE_ACTION,
8301 "cannot create jump action.");
8302 if (flow_dv_jump_tbl_resource_register
8303 (dev, tbl, dev_flow, error)) {
8304 flow_dv_tbl_resource_release(dev, tbl);
8305 return rte_flow_error_set
8307 RTE_FLOW_ERROR_TYPE_ACTION,
8309 "cannot create jump action.");
8311 dev_flow->dv.actions[actions_n++] =
8312 dev_flow->dv.jump->action;
8313 action_flags |= MLX5_FLOW_ACTION_JUMP;
8314 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8316 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8317 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8318 if (flow_dv_convert_action_modify_mac
8319 (mhdr_res, actions, error))
8321 action_flags |= actions->type ==
8322 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8323 MLX5_FLOW_ACTION_SET_MAC_SRC :
8324 MLX5_FLOW_ACTION_SET_MAC_DST;
8326 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8327 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8328 if (flow_dv_convert_action_modify_ipv4
8329 (mhdr_res, actions, error))
8331 action_flags |= actions->type ==
8332 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8333 MLX5_FLOW_ACTION_SET_IPV4_SRC :
8334 MLX5_FLOW_ACTION_SET_IPV4_DST;
8336 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8337 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8338 if (flow_dv_convert_action_modify_ipv6
8339 (mhdr_res, actions, error))
8341 action_flags |= actions->type ==
8342 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8343 MLX5_FLOW_ACTION_SET_IPV6_SRC :
8344 MLX5_FLOW_ACTION_SET_IPV6_DST;
8346 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8347 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8348 if (flow_dv_convert_action_modify_tp
8349 (mhdr_res, actions, items,
8350 &flow_attr, dev_flow, !!(action_flags &
8351 MLX5_FLOW_ACTION_DECAP), error))
8353 action_flags |= actions->type ==
8354 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8355 MLX5_FLOW_ACTION_SET_TP_SRC :
8356 MLX5_FLOW_ACTION_SET_TP_DST;
8358 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8359 if (flow_dv_convert_action_modify_dec_ttl
8360 (mhdr_res, items, &flow_attr, dev_flow,
8362 MLX5_FLOW_ACTION_DECAP), error))
8364 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8366 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8367 if (flow_dv_convert_action_modify_ttl
8368 (mhdr_res, actions, items, &flow_attr,
8369 dev_flow, !!(action_flags &
8370 MLX5_FLOW_ACTION_DECAP), error))
8372 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8374 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8375 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8376 if (flow_dv_convert_action_modify_tcp_seq
8377 (mhdr_res, actions, error))
8379 action_flags |= actions->type ==
8380 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8381 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8382 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8385 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8386 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8387 if (flow_dv_convert_action_modify_tcp_ack
8388 (mhdr_res, actions, error))
8390 action_flags |= actions->type ==
8391 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8392 MLX5_FLOW_ACTION_INC_TCP_ACK :
8393 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8395 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8396 if (flow_dv_convert_action_set_reg
8397 (mhdr_res, actions, error))
8399 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8401 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8402 if (flow_dv_convert_action_copy_mreg
8403 (dev, mhdr_res, actions, error))
8405 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8407 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8408 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8409 dev_flow->handle->fate_action =
8410 MLX5_FLOW_FATE_DEFAULT_MISS;
8412 case RTE_FLOW_ACTION_TYPE_METER:
8413 mtr = actions->conf;
8415 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8418 return rte_flow_error_set(error,
8420 RTE_FLOW_ERROR_TYPE_ACTION,
8423 "or invalid parameters");
8424 flow->meter = fm->idx;
8426 /* Set the meter action. */
8428 fm = mlx5_ipool_get(priv->sh->ipool
8429 [MLX5_IPOOL_MTR], flow->meter);
8431 return rte_flow_error_set(error,
8433 RTE_FLOW_ERROR_TYPE_ACTION,
8436 "or invalid parameters");
8438 dev_flow->dv.actions[actions_n++] =
8439 fm->mfts->meter_action;
8440 action_flags |= MLX5_FLOW_ACTION_METER;
8442 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8443 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8446 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8448 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8449 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8452 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8454 case RTE_FLOW_ACTION_TYPE_END:
8456 if (mhdr_res->actions_num) {
8457 /* create modify action if needed. */
8458 if (flow_dv_modify_hdr_resource_register
8459 (dev, mhdr_res, dev_flow, error))
8461 dev_flow->dv.actions[modify_action_position] =
8462 handle->dvh.modify_hdr->action;
8464 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8466 flow_dv_translate_create_counter(dev,
8467 dev_flow, count, age);
8470 return rte_flow_error_set
8472 RTE_FLOW_ERROR_TYPE_ACTION,
8474 "cannot create counter"
8476 dev_flow->dv.actions[actions_n++] =
8477 (flow_dv_counter_get_by_idx(dev,
8478 flow->counter, NULL))->action;
8484 if (mhdr_res->actions_num &&
8485 modify_action_position == UINT32_MAX)
8486 modify_action_position = actions_n++;
8488 dev_flow->dv.actions_n = actions_n;
8489 dev_flow->act_flags = action_flags;
8490 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8491 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8492 int item_type = items->type;
8494 if (!mlx5_flow_os_item_supported(item_type))
8495 return rte_flow_error_set(error, ENOTSUP,
8496 RTE_FLOW_ERROR_TYPE_ITEM,
8497 NULL, "item not supported");
8498 switch (item_type) {
8499 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8500 flow_dv_translate_item_port_id(dev, match_mask,
8501 match_value, items);
8502 last_item = MLX5_FLOW_ITEM_PORT_ID;
8504 case RTE_FLOW_ITEM_TYPE_ETH:
8505 flow_dv_translate_item_eth(match_mask, match_value,
8507 dev_flow->dv.group);
8508 matcher.priority = action_flags &
8509 MLX5_FLOW_ACTION_DEFAULT_MISS &&
8510 !dev_flow->external ?
8511 MLX5_PRIORITY_MAP_L3 :
8512 MLX5_PRIORITY_MAP_L2;
8513 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8514 MLX5_FLOW_LAYER_OUTER_L2;
8516 case RTE_FLOW_ITEM_TYPE_VLAN:
8517 flow_dv_translate_item_vlan(dev_flow,
8518 match_mask, match_value,
8520 dev_flow->dv.group);
8521 matcher.priority = MLX5_PRIORITY_MAP_L2;
8522 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8523 MLX5_FLOW_LAYER_INNER_VLAN) :
8524 (MLX5_FLOW_LAYER_OUTER_L2 |
8525 MLX5_FLOW_LAYER_OUTER_VLAN);
8527 case RTE_FLOW_ITEM_TYPE_IPV4:
8528 mlx5_flow_tunnel_ip_check(items, next_protocol,
8529 &item_flags, &tunnel);
8530 flow_dv_translate_item_ipv4(match_mask, match_value,
8531 items, item_flags, tunnel,
8532 dev_flow->dv.group);
8533 matcher.priority = MLX5_PRIORITY_MAP_L3;
8534 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8535 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8536 if (items->mask != NULL &&
8537 ((const struct rte_flow_item_ipv4 *)
8538 items->mask)->hdr.next_proto_id) {
8540 ((const struct rte_flow_item_ipv4 *)
8541 (items->spec))->hdr.next_proto_id;
8543 ((const struct rte_flow_item_ipv4 *)
8544 (items->mask))->hdr.next_proto_id;
8546 /* Reset for inner layer. */
8547 next_protocol = 0xff;
8550 case RTE_FLOW_ITEM_TYPE_IPV6:
8551 mlx5_flow_tunnel_ip_check(items, next_protocol,
8552 &item_flags, &tunnel);
8553 flow_dv_translate_item_ipv6(match_mask, match_value,
8554 items, item_flags, tunnel,
8555 dev_flow->dv.group);
8556 matcher.priority = MLX5_PRIORITY_MAP_L3;
8557 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8558 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8559 if (items->mask != NULL &&
8560 ((const struct rte_flow_item_ipv6 *)
8561 items->mask)->hdr.proto) {
8563 ((const struct rte_flow_item_ipv6 *)
8564 items->spec)->hdr.proto;
8566 ((const struct rte_flow_item_ipv6 *)
8567 items->mask)->hdr.proto;
8569 /* Reset for inner layer. */
8570 next_protocol = 0xff;
8573 case RTE_FLOW_ITEM_TYPE_TCP:
8574 flow_dv_translate_item_tcp(match_mask, match_value,
8576 matcher.priority = MLX5_PRIORITY_MAP_L4;
8577 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8578 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8580 case RTE_FLOW_ITEM_TYPE_UDP:
8581 flow_dv_translate_item_udp(match_mask, match_value,
8583 matcher.priority = MLX5_PRIORITY_MAP_L4;
8584 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8585 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8587 case RTE_FLOW_ITEM_TYPE_GRE:
8588 flow_dv_translate_item_gre(match_mask, match_value,
8590 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8591 last_item = MLX5_FLOW_LAYER_GRE;
8593 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8594 flow_dv_translate_item_gre_key(match_mask,
8595 match_value, items);
8596 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8598 case RTE_FLOW_ITEM_TYPE_NVGRE:
8599 flow_dv_translate_item_nvgre(match_mask, match_value,
8601 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8602 last_item = MLX5_FLOW_LAYER_GRE;
8604 case RTE_FLOW_ITEM_TYPE_VXLAN:
8605 flow_dv_translate_item_vxlan(match_mask, match_value,
8607 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8608 last_item = MLX5_FLOW_LAYER_VXLAN;
8610 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8611 flow_dv_translate_item_vxlan_gpe(match_mask,
8614 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8615 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8617 case RTE_FLOW_ITEM_TYPE_GENEVE:
8618 flow_dv_translate_item_geneve(match_mask, match_value,
8620 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8621 last_item = MLX5_FLOW_LAYER_GENEVE;
8623 case RTE_FLOW_ITEM_TYPE_MPLS:
8624 flow_dv_translate_item_mpls(match_mask, match_value,
8625 items, last_item, tunnel);
8626 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8627 last_item = MLX5_FLOW_LAYER_MPLS;
8629 case RTE_FLOW_ITEM_TYPE_MARK:
8630 flow_dv_translate_item_mark(dev, match_mask,
8631 match_value, items);
8632 last_item = MLX5_FLOW_ITEM_MARK;
8634 case RTE_FLOW_ITEM_TYPE_META:
8635 flow_dv_translate_item_meta(dev, match_mask,
8636 match_value, attr, items);
8637 last_item = MLX5_FLOW_ITEM_METADATA;
8639 case RTE_FLOW_ITEM_TYPE_ICMP:
8640 flow_dv_translate_item_icmp(match_mask, match_value,
8642 last_item = MLX5_FLOW_LAYER_ICMP;
8644 case RTE_FLOW_ITEM_TYPE_ICMP6:
8645 flow_dv_translate_item_icmp6(match_mask, match_value,
8647 last_item = MLX5_FLOW_LAYER_ICMP6;
8649 case RTE_FLOW_ITEM_TYPE_TAG:
8650 flow_dv_translate_item_tag(dev, match_mask,
8651 match_value, items);
8652 last_item = MLX5_FLOW_ITEM_TAG;
8654 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8655 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8656 match_value, items);
8657 last_item = MLX5_FLOW_ITEM_TAG;
8659 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8660 flow_dv_translate_item_tx_queue(dev, match_mask,
8663 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8665 case RTE_FLOW_ITEM_TYPE_GTP:
8666 flow_dv_translate_item_gtp(match_mask, match_value,
8668 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8669 last_item = MLX5_FLOW_LAYER_GTP;
8671 case RTE_FLOW_ITEM_TYPE_ECPRI:
8672 if (!mlx5_flex_parser_ecpri_exist(dev)) {
8673 /* Create it only the first time to be used. */
8674 ret = mlx5_flex_parser_ecpri_alloc(dev);
8676 return rte_flow_error_set
8678 RTE_FLOW_ERROR_TYPE_ITEM,
8680 "cannot create eCPRI parser");
8682 /* Adjust the length matcher and device flow value. */
8683 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
8684 dev_flow->dv.value.size =
8685 MLX5_ST_SZ_BYTES(fte_match_param);
8686 flow_dv_translate_item_ecpri(dev, match_mask,
8687 match_value, items);
8688 /* No other protocol should follow eCPRI layer. */
8689 last_item = MLX5_FLOW_LAYER_ECPRI;
8694 item_flags |= last_item;
8697 * When E-Switch mode is enabled, we have two cases where we need to
8698 * set the source port manually.
8699 * The first one, is in case of Nic steering rule, and the second is
8700 * E-Switch rule where no port_id item was found. In both cases
8701 * the source port is set according the current port in use.
8703 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8704 (priv->representor || priv->master)) {
8705 if (flow_dv_translate_item_port_id(dev, match_mask,
8709 #ifdef RTE_LIBRTE_MLX5_DEBUG
8710 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8711 dev_flow->dv.value.buf));
8714 * Layers may be already initialized from prefix flow if this dev_flow
8715 * is the suffix flow.
8717 handle->layers |= item_flags;
8718 if (action_flags & MLX5_FLOW_ACTION_RSS)
8719 flow_dv_hashfields_set(dev_flow, rss_desc);
8720 /* Register matcher. */
8721 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8723 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8725 /* reserved field no needs to be set to 0 here. */
8726 tbl_key.domain = attr->transfer;
8727 tbl_key.direction = attr->egress;
8728 tbl_key.table_id = dev_flow->dv.group;
8729 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8735 * Apply the flow to the NIC, lock free,
8736 * (mutex should be acquired by caller).
8739 * Pointer to the Ethernet device structure.
8740 * @param[in, out] flow
8741 * Pointer to flow structure.
8743 * Pointer to error structure.
8746 * 0 on success, a negative errno value otherwise and rte_errno is set.
8749 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8750 struct rte_flow_error *error)
8752 struct mlx5_flow_dv_workspace *dv;
8753 struct mlx5_flow_handle *dh;
8754 struct mlx5_flow_handle_dv *dv_h;
8755 struct mlx5_flow *dev_flow;
8756 struct mlx5_priv *priv = dev->data->dev_private;
8757 uint32_t handle_idx;
8762 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8763 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8765 dh = dev_flow->handle;
8768 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8770 dv->actions[n++] = priv->sh->esw_drop_action;
8772 struct mlx5_hrxq *drop_hrxq;
8773 drop_hrxq = mlx5_hrxq_drop_new(dev);
8777 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8779 "cannot get drop hash queue");
8783 * Drop queues will be released by the specify
8784 * mlx5_hrxq_drop_release() function. Assign
8785 * the special index to hrxq to mark the queue
8786 * has been allocated.
8788 dh->rix_hrxq = UINT32_MAX;
8789 dv->actions[n++] = drop_hrxq->action;
8791 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8792 struct mlx5_hrxq *hrxq;
8794 struct mlx5_flow_rss_desc *rss_desc =
8795 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8796 [!!priv->flow_nested_idx];
8798 MLX5_ASSERT(rss_desc->queue_num);
8799 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8800 MLX5_RSS_HASH_KEY_LEN,
8801 dev_flow->hash_fields,
8803 rss_desc->queue_num);
8805 hrxq_idx = mlx5_hrxq_new
8806 (dev, rss_desc->key,
8807 MLX5_RSS_HASH_KEY_LEN,
8808 dev_flow->hash_fields,
8810 rss_desc->queue_num,
8812 MLX5_FLOW_LAYER_TUNNEL));
8814 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8819 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8820 "cannot get hash queue");
8823 dh->rix_hrxq = hrxq_idx;
8824 dv->actions[n++] = hrxq->action;
8825 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
8826 if (flow_dv_default_miss_resource_register
8830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8831 "cannot create default miss resource");
8832 goto error_default_miss;
8834 dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;
8835 dv->actions[n++] = priv->sh->default_miss.action;
8837 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
8838 (void *)&dv->value, n,
8839 dv->actions, &dh->drv_flow);
8841 rte_flow_error_set(error, errno,
8842 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8844 "hardware refuses to create flow");
8847 if (priv->vmwa_context &&
8848 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8850 * The rule contains the VLAN pattern.
8851 * For VF we are going to create VLAN
8852 * interface to make hypervisor set correct
8853 * e-Switch vport context.
8855 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8860 if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
8861 flow_dv_default_miss_resource_release(dev);
8863 err = rte_errno; /* Save rte_errno before cleanup. */
8864 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8865 handle_idx, dh, next) {
8866 /* hrxq is union, don't clear it if the flag is not set. */
8868 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8869 mlx5_hrxq_drop_release(dev);
8871 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8872 mlx5_hrxq_release(dev, dh->rix_hrxq);
8876 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8877 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8879 rte_errno = err; /* Restore rte_errno. */
8884 * Release the flow matcher.
8887 * Pointer to Ethernet device.
8889 * Pointer to mlx5_flow_handle.
8892 * 1 while a reference on it exists, 0 when freed.
8895 flow_dv_matcher_release(struct rte_eth_dev *dev,
8896 struct mlx5_flow_handle *handle)
8898 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8900 MLX5_ASSERT(matcher->matcher_object);
8901 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8902 dev->data->port_id, (void *)matcher,
8903 rte_atomic32_read(&matcher->refcnt));
8904 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8905 claim_zero(mlx5_flow_os_destroy_flow_matcher
8906 (matcher->matcher_object));
8907 LIST_REMOVE(matcher, next);
8908 /* table ref-- in release interface. */
8909 flow_dv_tbl_resource_release(dev, matcher->tbl);
8911 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8912 dev->data->port_id, (void *)matcher);
8919 * Release an encap/decap resource.
8922 * Pointer to Ethernet device.
8924 * Pointer to mlx5_flow_handle.
8927 * 1 while a reference on it exists, 0 when freed.
8930 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8931 struct mlx5_flow_handle *handle)
8933 struct mlx5_priv *priv = dev->data->dev_private;
8934 uint32_t idx = handle->dvh.rix_encap_decap;
8935 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8937 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8939 if (!cache_resource)
8941 MLX5_ASSERT(cache_resource->action);
8942 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8943 (void *)cache_resource,
8944 rte_atomic32_read(&cache_resource->refcnt));
8945 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8946 claim_zero(mlx5_flow_os_destroy_flow_action
8947 (cache_resource->action));
8948 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8949 &priv->sh->encaps_decaps, idx,
8950 cache_resource, next);
8951 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8952 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8953 (void *)cache_resource);
8960 * Release an jump to table action resource.
8963 * Pointer to Ethernet device.
8965 * Pointer to mlx5_flow_handle.
8968 * 1 while a reference on it exists, 0 when freed.
8971 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8972 struct mlx5_flow_handle *handle)
8974 struct mlx5_priv *priv = dev->data->dev_private;
8975 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8976 struct mlx5_flow_tbl_data_entry *tbl_data;
8978 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8982 cache_resource = &tbl_data->jump;
8983 MLX5_ASSERT(cache_resource->action);
8984 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8985 (void *)cache_resource,
8986 rte_atomic32_read(&cache_resource->refcnt));
8987 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8988 claim_zero(mlx5_flow_os_destroy_flow_action
8989 (cache_resource->action));
8990 /* jump action memory free is inside the table release. */
8991 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8992 DRV_LOG(DEBUG, "jump table resource %p: removed",
8993 (void *)cache_resource);
9000 * Release a default miss resource.
9003 * Pointer to Ethernet device.
9005 * 1 while a reference on it exists, 0 when freed.
9008 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
9010 struct mlx5_priv *priv = dev->data->dev_private;
9011 struct mlx5_dev_ctx_shared *sh = priv->sh;
9012 struct mlx5_flow_default_miss_resource *cache_resource =
9015 MLX5_ASSERT(cache_resource->action);
9016 DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
9017 (void *)cache_resource->action,
9018 rte_atomic32_read(&cache_resource->refcnt));
9019 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9020 claim_zero(mlx5_glue->destroy_flow_action
9021 (cache_resource->action));
9022 DRV_LOG(DEBUG, "default miss resource %p: removed",
9023 (void *)cache_resource->action);
9030 * Release a modify-header resource.
9033 * Pointer to mlx5_flow_handle.
9036 * 1 while a reference on it exists, 0 when freed.
9039 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
9041 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
9042 handle->dvh.modify_hdr;
9044 MLX5_ASSERT(cache_resource->action);
9045 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
9046 (void *)cache_resource,
9047 rte_atomic32_read(&cache_resource->refcnt));
9048 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9049 claim_zero(mlx5_flow_os_destroy_flow_action
9050 (cache_resource->action));
9051 LIST_REMOVE(cache_resource, next);
9052 mlx5_free(cache_resource);
9053 DRV_LOG(DEBUG, "modify-header resource %p: removed",
9054 (void *)cache_resource);
9061 * Release port ID action resource.
9064 * Pointer to Ethernet device.
9066 * Pointer to mlx5_flow_handle.
9069 * 1 while a reference on it exists, 0 when freed.
9072 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
9073 struct mlx5_flow_handle *handle)
9075 struct mlx5_priv *priv = dev->data->dev_private;
9076 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
9077 uint32_t idx = handle->rix_port_id_action;
9079 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9081 if (!cache_resource)
9083 MLX5_ASSERT(cache_resource->action);
9084 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
9085 (void *)cache_resource,
9086 rte_atomic32_read(&cache_resource->refcnt));
9087 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9088 claim_zero(mlx5_flow_os_destroy_flow_action
9089 (cache_resource->action));
9090 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9091 &priv->sh->port_id_action_list, idx,
9092 cache_resource, next);
9093 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
9094 DRV_LOG(DEBUG, "port id action resource %p: removed",
9095 (void *)cache_resource);
9102 * Release push vlan action resource.
9105 * Pointer to Ethernet device.
9107 * Pointer to mlx5_flow_handle.
9110 * 1 while a reference on it exists, 0 when freed.
9113 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
9114 struct mlx5_flow_handle *handle)
9116 struct mlx5_priv *priv = dev->data->dev_private;
9117 uint32_t idx = handle->dvh.rix_push_vlan;
9118 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
9120 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9122 if (!cache_resource)
9124 MLX5_ASSERT(cache_resource->action);
9125 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
9126 (void *)cache_resource,
9127 rte_atomic32_read(&cache_resource->refcnt));
9128 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9129 claim_zero(mlx5_flow_os_destroy_flow_action
9130 (cache_resource->action));
9131 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9132 &priv->sh->push_vlan_action_list, idx,
9133 cache_resource, next);
9134 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
9135 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
9136 (void *)cache_resource);
9143 * Release the fate resource.
9146 * Pointer to Ethernet device.
9148 * Pointer to mlx5_flow_handle.
9151 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9152 struct mlx5_flow_handle *handle)
9154 if (!handle->rix_fate)
9156 switch (handle->fate_action) {
9157 case MLX5_FLOW_FATE_DROP:
9158 mlx5_hrxq_drop_release(dev);
9160 case MLX5_FLOW_FATE_QUEUE:
9161 mlx5_hrxq_release(dev, handle->rix_hrxq);
9163 case MLX5_FLOW_FATE_JUMP:
9164 flow_dv_jump_tbl_resource_release(dev, handle);
9166 case MLX5_FLOW_FATE_PORT_ID:
9167 flow_dv_port_id_action_resource_release(dev, handle);
9169 case MLX5_FLOW_FATE_DEFAULT_MISS:
9170 flow_dv_default_miss_resource_release(dev);
9173 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9176 handle->rix_fate = 0;
9180 * Remove the flow from the NIC but keeps it in memory.
9181 * Lock free, (mutex should be acquired by caller).
9184 * Pointer to Ethernet device.
9185 * @param[in, out] flow
9186 * Pointer to flow structure.
9189 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9191 struct mlx5_flow_handle *dh;
9192 uint32_t handle_idx;
9193 struct mlx5_priv *priv = dev->data->dev_private;
9197 handle_idx = flow->dev_handles;
9198 while (handle_idx) {
9199 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9204 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
9205 dh->drv_flow = NULL;
9207 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9208 dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9209 dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9210 flow_dv_fate_resource_release(dev, dh);
9211 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9212 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9213 handle_idx = dh->next.next;
9218 * Remove the flow from the NIC and the memory.
9219 * Lock free, (mutex should be acquired by caller).
9222 * Pointer to the Ethernet device structure.
9223 * @param[in, out] flow
9224 * Pointer to flow structure.
9227 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9229 struct mlx5_flow_handle *dev_handle;
9230 struct mlx5_priv *priv = dev->data->dev_private;
9234 __flow_dv_remove(dev, flow);
9235 if (flow->counter) {
9236 flow_dv_counter_release(dev, flow->counter);
9240 struct mlx5_flow_meter *fm;
9242 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9245 mlx5_flow_meter_detach(fm);
9248 while (flow->dev_handles) {
9249 uint32_t tmp_idx = flow->dev_handles;
9251 dev_handle = mlx5_ipool_get(priv->sh->ipool
9252 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9255 flow->dev_handles = dev_handle->next.next;
9256 if (dev_handle->dvh.matcher)
9257 flow_dv_matcher_release(dev, dev_handle);
9258 if (dev_handle->dvh.rix_encap_decap)
9259 flow_dv_encap_decap_resource_release(dev, dev_handle);
9260 if (dev_handle->dvh.modify_hdr)
9261 flow_dv_modify_hdr_resource_release(dev_handle);
9262 if (dev_handle->dvh.rix_push_vlan)
9263 flow_dv_push_vlan_action_resource_release(dev,
9265 if (dev_handle->dvh.rix_tag)
9266 flow_dv_tag_release(dev,
9267 dev_handle->dvh.rix_tag);
9268 flow_dv_fate_resource_release(dev, dev_handle);
9269 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9275 * Query a dv flow rule for its statistics via devx.
9278 * Pointer to Ethernet device.
9280 * Pointer to the sub flow.
9282 * data retrieved by the query.
9284 * Perform verbose error reporting if not NULL.
9287 * 0 on success, a negative errno value otherwise and rte_errno is set.
9290 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9291 void *data, struct rte_flow_error *error)
9293 struct mlx5_priv *priv = dev->data->dev_private;
9294 struct rte_flow_query_count *qc = data;
9296 if (!priv->config.devx)
9297 return rte_flow_error_set(error, ENOTSUP,
9298 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9300 "counters are not supported");
9301 if (flow->counter) {
9302 uint64_t pkts, bytes;
9303 struct mlx5_flow_counter *cnt;
9305 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9307 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9311 return rte_flow_error_set(error, -err,
9312 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9313 NULL, "cannot read counters");
9316 qc->hits = pkts - cnt->hits;
9317 qc->bytes = bytes - cnt->bytes;
9324 return rte_flow_error_set(error, EINVAL,
9325 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9327 "counters are not available");
9333 * @see rte_flow_query()
9337 flow_dv_query(struct rte_eth_dev *dev,
9338 struct rte_flow *flow __rte_unused,
9339 const struct rte_flow_action *actions __rte_unused,
9340 void *data __rte_unused,
9341 struct rte_flow_error *error __rte_unused)
9345 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9346 switch (actions->type) {
9347 case RTE_FLOW_ACTION_TYPE_VOID:
9349 case RTE_FLOW_ACTION_TYPE_COUNT:
9350 ret = flow_dv_query_count(dev, flow, data, error);
9353 return rte_flow_error_set(error, ENOTSUP,
9354 RTE_FLOW_ERROR_TYPE_ACTION,
9356 "action not supported");
9363 * Destroy the meter table set.
9364 * Lock free, (mutex should be acquired by caller).
9367 * Pointer to Ethernet device.
9369 * Pointer to the meter table set.
9375 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9376 struct mlx5_meter_domains_infos *tbl)
9378 struct mlx5_priv *priv = dev->data->dev_private;
9379 struct mlx5_meter_domains_infos *mtd =
9380 (struct mlx5_meter_domains_infos *)tbl;
9382 if (!mtd || !priv->config.dv_flow_en)
9384 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9385 claim_zero(mlx5_flow_os_destroy_flow
9386 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9387 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9388 claim_zero(mlx5_flow_os_destroy_flow
9389 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9390 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9391 claim_zero(mlx5_flow_os_destroy_flow
9392 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9393 if (mtd->egress.color_matcher)
9394 claim_zero(mlx5_flow_os_destroy_flow_matcher
9395 (mtd->egress.color_matcher));
9396 if (mtd->egress.any_matcher)
9397 claim_zero(mlx5_flow_os_destroy_flow_matcher
9398 (mtd->egress.any_matcher));
9399 if (mtd->egress.tbl)
9400 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9401 if (mtd->egress.sfx_tbl)
9402 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9403 if (mtd->ingress.color_matcher)
9404 claim_zero(mlx5_flow_os_destroy_flow_matcher
9405 (mtd->ingress.color_matcher));
9406 if (mtd->ingress.any_matcher)
9407 claim_zero(mlx5_flow_os_destroy_flow_matcher
9408 (mtd->ingress.any_matcher));
9409 if (mtd->ingress.tbl)
9410 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9411 if (mtd->ingress.sfx_tbl)
9412 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9413 if (mtd->transfer.color_matcher)
9414 claim_zero(mlx5_flow_os_destroy_flow_matcher
9415 (mtd->transfer.color_matcher));
9416 if (mtd->transfer.any_matcher)
9417 claim_zero(mlx5_flow_os_destroy_flow_matcher
9418 (mtd->transfer.any_matcher));
9419 if (mtd->transfer.tbl)
9420 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9421 if (mtd->transfer.sfx_tbl)
9422 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9424 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
9429 /* Number of meter flow actions, count and jump or count and drop. */
9430 #define METER_ACTIONS 2
9433 * Create specify domain meter table and suffix table.
9436 * Pointer to Ethernet device.
9437 * @param[in,out] mtb
9438 * Pointer to DV meter table set.
9441 * @param[in] transfer
9443 * @param[in] color_reg_c_idx
9444 * Reg C index for color match.
9447 * 0 on success, -1 otherwise and rte_errno is set.
9450 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9451 struct mlx5_meter_domains_infos *mtb,
9452 uint8_t egress, uint8_t transfer,
9453 uint32_t color_reg_c_idx)
9455 struct mlx5_priv *priv = dev->data->dev_private;
9456 struct mlx5_dev_ctx_shared *sh = priv->sh;
9457 struct mlx5_flow_dv_match_params mask = {
9458 .size = sizeof(mask.buf),
9460 struct mlx5_flow_dv_match_params value = {
9461 .size = sizeof(value.buf),
9463 struct mlx5dv_flow_matcher_attr dv_attr = {
9464 .type = IBV_FLOW_ATTR_NORMAL,
9466 .match_criteria_enable = 0,
9467 .match_mask = (void *)&mask,
9469 void *actions[METER_ACTIONS];
9470 struct mlx5_meter_domain_info *dtb;
9471 struct rte_flow_error error;
9476 dtb = &mtb->transfer;
9480 dtb = &mtb->ingress;
9481 /* Create the meter table with METER level. */
9482 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9483 egress, transfer, &error);
9485 DRV_LOG(ERR, "Failed to create meter policer table.");
9488 /* Create the meter suffix table with SUFFIX level. */
9489 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9490 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9491 egress, transfer, &error);
9492 if (!dtb->sfx_tbl) {
9493 DRV_LOG(ERR, "Failed to create meter suffix table.");
9496 /* Create matchers, Any and Color. */
9497 dv_attr.priority = 3;
9498 dv_attr.match_criteria_enable = 0;
9499 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9502 DRV_LOG(ERR, "Failed to create meter"
9503 " policer default matcher.");
9506 dv_attr.priority = 0;
9507 dv_attr.match_criteria_enable =
9508 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9509 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9510 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9511 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9512 &dtb->color_matcher);
9514 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9517 if (mtb->count_actns[RTE_MTR_DROPPED])
9518 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9519 actions[i++] = mtb->drop_actn;
9520 /* Default rule: lowest priority, match any, actions: drop. */
9521 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
9523 &dtb->policer_rules[RTE_MTR_DROPPED]);
9525 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9534 * Create the needed meter and suffix tables.
9535 * Lock free, (mutex should be acquired by caller).
9538 * Pointer to Ethernet device.
9540 * Pointer to the flow meter.
9543 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9545 static struct mlx5_meter_domains_infos *
9546 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9547 const struct mlx5_flow_meter *fm)
9549 struct mlx5_priv *priv = dev->data->dev_private;
9550 struct mlx5_meter_domains_infos *mtb;
9554 if (!priv->mtr_en) {
9555 rte_errno = ENOTSUP;
9558 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
9560 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9563 /* Create meter count actions */
9564 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9565 struct mlx5_flow_counter *cnt;
9566 if (!fm->policer_stats.cnt[i])
9568 cnt = flow_dv_counter_get_by_idx(dev,
9569 fm->policer_stats.cnt[i], NULL);
9570 mtb->count_actns[i] = cnt->action;
9572 /* Create drop action. */
9573 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
9575 DRV_LOG(ERR, "Failed to create drop action.");
9578 /* Egress meter table. */
9579 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9581 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9584 /* Ingress meter table. */
9585 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9587 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9590 /* FDB meter table. */
9591 if (priv->config.dv_esw_en) {
9592 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9593 priv->mtr_color_reg);
9595 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9601 flow_dv_destroy_mtr_tbl(dev, mtb);
9606 * Destroy domain policer rule.
9609 * Pointer to domain table.
9612 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9616 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9617 if (dt->policer_rules[i]) {
9618 claim_zero(mlx5_flow_os_destroy_flow
9619 (dt->policer_rules[i]));
9620 dt->policer_rules[i] = NULL;
9623 if (dt->jump_actn) {
9624 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
9625 dt->jump_actn = NULL;
9630 * Destroy policer rules.
9633 * Pointer to Ethernet device.
9635 * Pointer to flow meter structure.
9637 * Pointer to flow attributes.
9643 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9644 const struct mlx5_flow_meter *fm,
9645 const struct rte_flow_attr *attr)
9647 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9652 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9654 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9656 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9661 * Create specify domain meter policer rule.
9664 * Pointer to flow meter structure.
9666 * Pointer to DV meter table set.
9667 * @param[in] mtr_reg_c
9668 * Color match REG_C.
9671 * 0 on success, -1 otherwise.
9674 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9675 struct mlx5_meter_domain_info *dtb,
9678 struct mlx5_flow_dv_match_params matcher = {
9679 .size = sizeof(matcher.buf),
9681 struct mlx5_flow_dv_match_params value = {
9682 .size = sizeof(value.buf),
9684 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9685 void *actions[METER_ACTIONS];
9689 /* Create jump action. */
9690 if (!dtb->jump_actn)
9691 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9692 (dtb->sfx_tbl->obj, &dtb->jump_actn);
9694 DRV_LOG(ERR, "Failed to create policer jump action.");
9697 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9700 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9701 rte_col_2_mlx5_col(i), UINT8_MAX);
9702 if (mtb->count_actns[i])
9703 actions[j++] = mtb->count_actns[i];
9704 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9705 actions[j++] = mtb->drop_actn;
9707 actions[j++] = dtb->jump_actn;
9708 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
9709 (void *)&value, j, actions,
9710 &dtb->policer_rules[i]);
9712 DRV_LOG(ERR, "Failed to create policer rule.");
9723 * Create policer rules.
9726 * Pointer to Ethernet device.
9728 * Pointer to flow meter structure.
9730 * Pointer to flow attributes.
9733 * 0 on success, -1 otherwise.
9736 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9737 struct mlx5_flow_meter *fm,
9738 const struct rte_flow_attr *attr)
9740 struct mlx5_priv *priv = dev->data->dev_private;
9741 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9745 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9746 priv->mtr_color_reg);
9748 DRV_LOG(ERR, "Failed to create egress policer.");
9752 if (attr->ingress) {
9753 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9754 priv->mtr_color_reg);
9756 DRV_LOG(ERR, "Failed to create ingress policer.");
9760 if (attr->transfer) {
9761 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9762 priv->mtr_color_reg);
9764 DRV_LOG(ERR, "Failed to create transfer policer.");
9770 flow_dv_destroy_policer_rules(dev, fm, attr);
9775 * Query a devx counter.
9778 * Pointer to the Ethernet device structure.
9780 * Index to the flow counter.
9782 * Set to clear the counter statistics.
9784 * The statistics value of packets.
9786 * The statistics value of bytes.
9789 * 0 on success, otherwise return -1.
9792 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9793 uint64_t *pkts, uint64_t *bytes)
9795 struct mlx5_priv *priv = dev->data->dev_private;
9796 struct mlx5_flow_counter *cnt;
9797 uint64_t inn_pkts, inn_bytes;
9800 if (!priv->config.devx)
9803 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9806 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9807 *pkts = inn_pkts - cnt->hits;
9808 *bytes = inn_bytes - cnt->bytes;
9810 cnt->hits = inn_pkts;
9811 cnt->bytes = inn_bytes;
9817 * Get aged-out flows.
9820 * Pointer to the Ethernet device structure.
9821 * @param[in] context
9822 * The address of an array of pointers to the aged-out flows contexts.
9823 * @param[in] nb_contexts
9824 * The length of context array pointers.
9826 * Perform verbose error reporting if not NULL. Initialized in case of
9830 * how many contexts get in success, otherwise negative errno value.
9831 * if nb_contexts is 0, return the amount of all aged contexts.
9832 * if nb_contexts is not 0 , return the amount of aged flows reported
9833 * in the context array.
9834 * @note: only stub for now
9837 flow_get_aged_flows(struct rte_eth_dev *dev,
9839 uint32_t nb_contexts,
9840 struct rte_flow_error *error)
9842 struct mlx5_priv *priv = dev->data->dev_private;
9843 struct mlx5_age_info *age_info;
9844 struct mlx5_age_param *age_param;
9845 struct mlx5_flow_counter *counter;
9848 if (nb_contexts && !context)
9849 return rte_flow_error_set(error, EINVAL,
9850 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9852 "Should assign at least one flow or"
9853 " context to get if nb_contexts != 0");
9854 age_info = GET_PORT_AGE_INFO(priv);
9855 rte_spinlock_lock(&age_info->aged_sl);
9856 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9859 age_param = MLX5_CNT_TO_AGE(counter);
9860 context[nb_flows - 1] = age_param->context;
9861 if (!(--nb_contexts))
9865 rte_spinlock_unlock(&age_info->aged_sl);
9866 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9871 * Mutex-protected thunk to lock-free __flow_dv_translate().
9874 flow_dv_translate(struct rte_eth_dev *dev,
9875 struct mlx5_flow *dev_flow,
9876 const struct rte_flow_attr *attr,
9877 const struct rte_flow_item items[],
9878 const struct rte_flow_action actions[],
9879 struct rte_flow_error *error)
9883 flow_dv_shared_lock(dev);
9884 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9885 flow_dv_shared_unlock(dev);
9890 * Mutex-protected thunk to lock-free __flow_dv_apply().
9893 flow_dv_apply(struct rte_eth_dev *dev,
9894 struct rte_flow *flow,
9895 struct rte_flow_error *error)
9899 flow_dv_shared_lock(dev);
9900 ret = __flow_dv_apply(dev, flow, error);
9901 flow_dv_shared_unlock(dev);
9906 * Mutex-protected thunk to lock-free __flow_dv_remove().
9909 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9911 flow_dv_shared_lock(dev);
9912 __flow_dv_remove(dev, flow);
9913 flow_dv_shared_unlock(dev);
9917 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9920 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9922 flow_dv_shared_lock(dev);
9923 __flow_dv_destroy(dev, flow);
9924 flow_dv_shared_unlock(dev);
9928 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9931 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9935 flow_dv_shared_lock(dev);
9936 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9937 flow_dv_shared_unlock(dev);
9942 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9945 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9947 flow_dv_shared_lock(dev);
9948 flow_dv_counter_release(dev, cnt);
9949 flow_dv_shared_unlock(dev);
9952 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9953 .validate = flow_dv_validate,
9954 .prepare = flow_dv_prepare,
9955 .translate = flow_dv_translate,
9956 .apply = flow_dv_apply,
9957 .remove = flow_dv_remove,
9958 .destroy = flow_dv_destroy,
9959 .query = flow_dv_query,
9960 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9961 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9962 .create_policer_rules = flow_dv_create_policer_rules,
9963 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9964 .counter_alloc = flow_dv_counter_allocate,
9965 .counter_free = flow_dv_counter_free,
9966 .counter_query = flow_dv_counter_query,
9967 .get_aged_flows = flow_get_aged_flows,
9970 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */