drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_cycles.h>
  28 #include <rte_ip.h>
  29 #include <rte_gre.h>
  30 #include <rte_vxlan.h>
  31 #include <rte_gtp.h>
  32
  33 #include <mlx5_glue.h>
  34 #include <mlx5_devx_cmds.h>
  35 #include <mlx5_prm.h>
  36
  37 #include "mlx5_defs.h"
  38 #include "mlx5.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_rxtx.h"
  41
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43
  44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  46 #endif
  47
  48 #ifndef HAVE_MLX5DV_DR_ESWITCH
  49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  51 #endif
  52 #endif
  53
  54 #ifndef HAVE_MLX5DV_DR
  55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  56 #endif
  57
  58 /* VLAN header definitions */
  59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  64
  65 union flow_dv_attr {
  66         struct {
  67                 uint32_t valid:1;
  68                 uint32_t ipv4:1;
  69                 uint32_t ipv6:1;
  70                 uint32_t tcp:1;
  71                 uint32_t udp:1;
  72                 uint32_t reserved:27;
  73         };
  74         uint32_t attr;
  75 };
  76
  77 static int
  78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  79                              struct mlx5_flow_tbl_resource *tbl);
  80
  81 /**
  82  * Initialize flow attributes structure according to flow items' types.
  83  *
  84  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  85  * mode. For tunnel mode, the items to be modified are the outermost ones.
  86  *
  87  * @param[in] item
  88  *   Pointer to item specification.
  89  * @param[out] attr
  90  *   Pointer to flow attributes structure.
  91  * @param[in] dev_flow
  92  *   Pointer to the sub flow.
  93  * @param[in] tunnel_decap
  94  *   Whether action is after tunnel decapsulation.
  95  */
  96 static void
  97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  98                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  99 {
 100         uint64_t layers = dev_flow->handle->layers;
 101
 102         /*
 103          * If layers is already initialized, it means this dev_flow is the
 104          * suffix flow, the layers flags is set by the prefix flow. Need to
 105          * use the layer flags from prefix flow as the suffix flow may not
 106          * have the user defined items as the flow is split.
 107          */
 108         if (layers) {
 109                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 110                         attr->ipv4 = 1;
 111                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 112                         attr->ipv6 = 1;
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 114                         attr->tcp = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 116                         attr->udp = 1;
 117                 attr->valid = 1;
 118                 return;
 119         }
 120         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 121                 uint8_t next_protocol = 0xff;
 122                 switch (item->type) {
 123                 case RTE_FLOW_ITEM_TYPE_GRE:
 124                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 126                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 127                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 128                 case RTE_FLOW_ITEM_TYPE_MPLS:
 129                         if (tunnel_decap)
 130                                 attr->attr = 0;
 131                         break;
 132                 case RTE_FLOW_ITEM_TYPE_IPV4:
 133                         if (!attr->ipv6)
 134                                 attr->ipv4 = 1;
 135                         if (item->mask != NULL &&
 136                             ((const struct rte_flow_item_ipv4 *)
 137                             item->mask)->hdr.next_proto_id)
 138                                 next_protocol =
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->spec))->hdr.next_proto_id &
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->mask))->hdr.next_proto_id;
 143                         if ((next_protocol == IPPROTO_IPIP ||
 144                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 145                                 attr->attr = 0;
 146                         break;
 147                 case RTE_FLOW_ITEM_TYPE_IPV6:
 148                         if (!attr->ipv4)
 149                                 attr->ipv6 = 1;
 150                         if (item->mask != NULL &&
 151                             ((const struct rte_flow_item_ipv6 *)
 152                             item->mask)->hdr.proto)
 153                                 next_protocol =
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->spec))->hdr.proto &
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->mask))->hdr.proto;
 158                         if ((next_protocol == IPPROTO_IPIP ||
 159                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 160                                 attr->attr = 0;
 161                         break;
 162                 case RTE_FLOW_ITEM_TYPE_UDP:
 163                         if (!attr->tcp)
 164                                 attr->udp = 1;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_TCP:
 167                         if (!attr->udp)
 168                                 attr->tcp = 1;
 169                         break;
 170                 default:
 171                         break;
 172                 }
 173         }
 174         attr->valid = 1;
 175 }
 176
 177 /**
 178  * Convert rte_mtr_color to mlx5 color.
 179  *
 180  * @param[in] rcol
 181  *   rte_mtr_color.
 182  *
 183  * @return
 184  *   mlx5 color.
 185  */
 186 static int
 187 rte_col_2_mlx5_col(enum rte_color rcol)
 188 {
 189         switch (rcol) {
 190         case RTE_COLOR_GREEN:
 191                 return MLX5_FLOW_COLOR_GREEN;
 192         case RTE_COLOR_YELLOW:
 193                 return MLX5_FLOW_COLOR_YELLOW;
 194         case RTE_COLOR_RED:
 195                 return MLX5_FLOW_COLOR_RED;
 196         default:
 197                 break;
 198         }
 199         return MLX5_FLOW_COLOR_UNDEFINED;
 200 }
 201
 202 struct field_modify_info {
 203         uint32_t size; /* Size of field in protocol header, in bytes. */
 204         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 205         enum mlx5_modification_field id;
 206 };
 207
 208 struct field_modify_info modify_eth[] = {
 209         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 210         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 211         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 212         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_vlan_out_first_vid[] = {
 217         /* Size in bits !!! */
 218         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_ipv4[] = {
 223         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 224         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 225         {4, 12, MLX5_MODI_OUT_SIPV4},
 226         {4, 16, MLX5_MODI_OUT_DIPV4},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_ipv6[] = {
 231         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 232         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 233         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 234         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 235         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 236         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 237         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 238         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 239         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 240         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 241         {0, 0, 0},
 242 };
 243
 244 struct field_modify_info modify_udp[] = {
 245         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 246         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_tcp[] = {
 251         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 253         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 254         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 255         {0, 0, 0},
 256 };
 257
 258 static void
 259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 260                           uint8_t next_protocol, uint64_t *item_flags,
 261                           int *tunnel)
 262 {
 263         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 264                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 265         if (next_protocol == IPPROTO_IPIP) {
 266                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 267                 *tunnel = 1;
 268         }
 269         if (next_protocol == IPPROTO_IPV6) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 271                 *tunnel = 1;
 272         }
 273 }
 274
 275 /**
 276  * Acquire the synchronizing object to protect multithreaded access
 277  * to shared dv context. Lock occurs only if context is actually
 278  * shared, i.e. we have multiport IB device and representors are
 279  * created.
 280  *
 281  * @param[in] dev
 282  *   Pointer to the rte_eth_dev structure.
 283  */
 284 static void
 285 flow_dv_shared_lock(struct rte_eth_dev *dev)
 286 {
 287         struct mlx5_priv *priv = dev->data->dev_private;
 288         struct mlx5_ibv_shared *sh = priv->sh;
 289
 290         if (sh->dv_refcnt > 1) {
 291                 int ret;
 292
 293                 ret = pthread_mutex_lock(&sh->dv_mutex);
 294                 MLX5_ASSERT(!ret);
 295                 (void)ret;
 296         }
 297 }
 298
 299 static void
 300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 301 {
 302         struct mlx5_priv *priv = dev->data->dev_private;
 303         struct mlx5_ibv_shared *sh = priv->sh;
 304
 305         if (sh->dv_refcnt > 1) {
 306                 int ret;
 307
 308                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 309                 MLX5_ASSERT(!ret);
 310                 (void)ret;
 311         }
 312 }
 313
 314 /* Update VLAN's VID/PCP based on input rte_flow_action.
 315  *
 316  * @param[in] action
 317  *   Pointer to struct rte_flow_action.
 318  * @param[out] vlan
 319  *   Pointer to struct rte_vlan_hdr.
 320  */
 321 static void
 322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 323                          struct rte_vlan_hdr *vlan)
 324 {
 325         uint16_t vlan_tci;
 326         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 327                 vlan_tci =
 328                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 329                                                action->conf)->vlan_pcp;
 330                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 331                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 332                 vlan->vlan_tci |= vlan_tci;
 333         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 334                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 335                 vlan->vlan_tci |= rte_be_to_cpu_16
 336                     (((const struct rte_flow_action_of_set_vlan_vid *)
 337                                              action->conf)->vlan_vid);
 338         }
 339 }
 340
 341 /**
 342  * Fetch 1, 2, 3 or 4 byte field from the byte array
 343  * and return as unsigned integer in host-endian format.
 344  *
 345  * @param[in] data
 346  *   Pointer to data array.
 347  * @param[in] size
 348  *   Size of field to extract.
 349  *
 350  * @return
 351  *   converted field in host endian format.
 352  */
 353 static inline uint32_t
 354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 355 {
 356         uint32_t ret;
 357
 358         switch (size) {
 359         case 1:
 360                 ret = *data;
 361                 break;
 362         case 2:
 363                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 364                 break;
 365         case 3:
 366                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 367                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 368                 break;
 369         case 4:
 370                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 371                 break;
 372         default:
 373                 MLX5_ASSERT(false);
 374                 ret = 0;
 375                 break;
 376         }
 377         return ret;
 378 }
 379
 380 /**
 381  * Convert modify-header action to DV specification.
 382  *
 383  * Data length of each action is determined by provided field description
 384  * and the item mask. Data bit offset and width of each action is determined
 385  * by provided item mask.
 386  *
 387  * @param[in] item
 388  *   Pointer to item specification.
 389  * @param[in] field
 390  *   Pointer to field modification information.
 391  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 393  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 394  * @param[in] dcopy
 395  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 396  *   Negative offset value sets the same offset as source offset.
 397  *   size field is ignored, value is taken from source field.
 398  * @param[in,out] resource
 399  *   Pointer to the modify-header resource.
 400  * @param[in] type
 401  *   Type of modification.
 402  * @param[out] error
 403  *   Pointer to the error structure.
 404  *
 405  * @return
 406  *   0 on success, a negative errno value otherwise and rte_errno is set.
 407  */
 408 static int
 409 flow_dv_convert_modify_action(struct rte_flow_item *item,
 410                               struct field_modify_info *field,
 411                               struct field_modify_info *dcopy,
 412                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 413                               uint32_t type, struct rte_flow_error *error)
 414 {
 415         uint32_t i = resource->actions_num;
 416         struct mlx5_modification_cmd *actions = resource->actions;
 417
 418         /*
 419          * The item and mask are provided in big-endian format.
 420          * The fields should be presented as in big-endian format either.
 421          * Mask must be always present, it defines the actual field width.
 422          */
 423         MLX5_ASSERT(item->mask);
 424         MLX5_ASSERT(field->size);
 425         do {
 426                 unsigned int size_b;
 427                 unsigned int off_b;
 428                 uint32_t mask;
 429                 uint32_t data;
 430
 431                 if (i >= MLX5_MAX_MODIFY_NUM)
 432                         return rte_flow_error_set(error, EINVAL,
 433                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 434                                  "too many items to modify");
 435                 /* Fetch variable byte size mask from the array. */
 436                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 437                                            field->offset, field->size);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /*
1643  * GTP flags are contained in 1 byte of the format:
1644  * -------------------------------------------
1645  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1646  * |-----------------------------------------|
1647  * | value | Version | PT | Res | E | S | PN |
1648  * -------------------------------------------
1649  *
1650  * Matching is supported only for GTP flags E, S, PN.
1651  */
1652 #define MLX5_GTP_FLAGS_MASK     0x07
1653
1654 /**
1655  * Validate VLAN item.
1656  *
1657  * @param[in] item
1658  *   Item specification.
1659  * @param[in] item_flags
1660  *   Bit-fields that holds the items detected until now.
1661  * @param[in] dev
1662  *   Ethernet device flow is being created on.
1663  * @param[out] error
1664  *   Pointer to error structure.
1665  *
1666  * @return
1667  *   0 on success, a negative errno value otherwise and rte_errno is set.
1668  */
1669 static int
1670 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1671                            uint64_t item_flags,
1672                            struct rte_eth_dev *dev,
1673                            struct rte_flow_error *error)
1674 {
1675         const struct rte_flow_item_vlan *mask = item->mask;
1676         const struct rte_flow_item_vlan nic_mask = {
1677                 .tci = RTE_BE16(UINT16_MAX),
1678                 .inner_type = RTE_BE16(UINT16_MAX),
1679         };
1680         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1681         int ret;
1682         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1683                                         MLX5_FLOW_LAYER_INNER_L4) :
1684                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1685                                         MLX5_FLOW_LAYER_OUTER_L4);
1686         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1687                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1688
1689         if (item_flags & vlanm)
1690                 return rte_flow_error_set(error, EINVAL,
1691                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1692                                           "multiple VLAN layers not supported");
1693         else if ((item_flags & l34m) != 0)
1694                 return rte_flow_error_set(error, EINVAL,
1695                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1696                                           "VLAN cannot follow L3/L4 layer");
1697         if (!mask)
1698                 mask = &rte_flow_item_vlan_mask;
1699         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1700                                         (const uint8_t *)&nic_mask,
1701                                         sizeof(struct rte_flow_item_vlan),
1702                                         error);
1703         if (ret)
1704                 return ret;
1705         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1706                 struct mlx5_priv *priv = dev->data->dev_private;
1707
1708                 if (priv->vmwa_context) {
1709                         /*
1710                          * Non-NULL context means we have a virtual machine
1711                          * and SR-IOV enabled, we have to create VLAN interface
1712                          * to make hypervisor to setup E-Switch vport
1713                          * context correctly. We avoid creating the multiple
1714                          * VLAN interfaces, so we cannot support VLAN tag mask.
1715                          */
1716                         return rte_flow_error_set(error, EINVAL,
1717                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1718                                                   item,
1719                                                   "VLAN tag mask is not"
1720                                                   " supported in virtual"
1721                                                   " environment");
1722                 }
1723         }
1724         return 0;
1725 }
1726
1727 /**
1728  * Validate GTP item.
1729  *
1730  * @param[in] dev
1731  *   Pointer to the rte_eth_dev structure.
1732  * @param[in] item
1733  *   Item specification.
1734  * @param[in] item_flags
1735  *   Bit-fields that holds the items detected until now.
1736  * @param[out] error
1737  *   Pointer to error structure.
1738  *
1739  * @return
1740  *   0 on success, a negative errno value otherwise and rte_errno is set.
1741  */
1742 static int
1743 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1744                           const struct rte_flow_item *item,
1745                           uint64_t item_flags,
1746                           struct rte_flow_error *error)
1747 {
1748         struct mlx5_priv *priv = dev->data->dev_private;
1749         const struct rte_flow_item_gtp *spec = item->spec;
1750         const struct rte_flow_item_gtp *mask = item->mask;
1751         const struct rte_flow_item_gtp nic_mask = {
1752                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1753                 .msg_type = 0xff,
1754                 .teid = RTE_BE32(0xffffffff),
1755         };
1756
1757         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1758                 return rte_flow_error_set(error, ENOTSUP,
1759                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1760                                           "GTP support is not enabled");
1761         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1762                 return rte_flow_error_set(error, ENOTSUP,
1763                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1764                                           "multiple tunnel layers not"
1765                                           " supported");
1766         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1767                 return rte_flow_error_set(error, EINVAL,
1768                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1769                                           "no outer UDP layer found");
1770         if (!mask)
1771                 mask = &rte_flow_item_gtp_mask;
1772         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "Match is supported for GTP"
1776                                           " flags only");
1777         return mlx5_flow_item_acceptable
1778                 (item, (const uint8_t *)mask,
1779                  (const uint8_t *)&nic_mask,
1780                  sizeof(struct rte_flow_item_gtp),
1781                  error);
1782 }
1783
1784 /**
1785  * Validate the pop VLAN action.
1786  *
1787  * @param[in] dev
1788  *   Pointer to the rte_eth_dev structure.
1789  * @param[in] action_flags
1790  *   Holds the actions detected until now.
1791  * @param[in] action
1792  *   Pointer to the pop vlan action.
1793  * @param[in] item_flags
1794  *   The items found in this flow rule.
1795  * @param[in] attr
1796  *   Pointer to flow attributes.
1797  * @param[out] error
1798  *   Pointer to error structure.
1799  *
1800  * @return
1801  *   0 on success, a negative errno value otherwise and rte_errno is set.
1802  */
1803 static int
1804 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1805                                  uint64_t action_flags,
1806                                  const struct rte_flow_action *action,
1807                                  uint64_t item_flags,
1808                                  const struct rte_flow_attr *attr,
1809                                  struct rte_flow_error *error)
1810 {
1811         const struct mlx5_priv *priv = dev->data->dev_private;
1812
1813         (void)action;
1814         (void)attr;
1815         if (!priv->sh->pop_vlan_action)
1816                 return rte_flow_error_set(error, ENOTSUP,
1817                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1818                                           NULL,
1819                                           "pop vlan action is not supported");
1820         if (attr->egress)
1821                 return rte_flow_error_set(error, ENOTSUP,
1822                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1823                                           NULL,
1824                                           "pop vlan action not supported for "
1825                                           "egress");
1826         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1829                                           "no support for multiple VLAN "
1830                                           "actions");
1831         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1834                                           NULL,
1835                                           "cannot pop vlan without a "
1836                                           "match on (outer) vlan in the flow");
1837         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1838                 return rte_flow_error_set(error, EINVAL,
1839                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1840                                           "wrong action order, port_id should "
1841                                           "be after pop VLAN action");
1842         if (!attr->transfer && priv->representor)
1843                 return rte_flow_error_set(error, ENOTSUP,
1844                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1845                                           "pop vlan action for VF representor "
1846                                           "not supported on NIC table");
1847         return 0;
1848 }
1849
1850 /**
1851  * Get VLAN default info from vlan match info.
1852  *
1853  * @param[in] items
1854  *   the list of item specifications.
1855  * @param[out] vlan
1856  *   pointer VLAN info to fill to.
1857  *
1858  * @return
1859  *   0 on success, a negative errno value otherwise and rte_errno is set.
1860  */
1861 static void
1862 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1863                                   struct rte_vlan_hdr *vlan)
1864 {
1865         const struct rte_flow_item_vlan nic_mask = {
1866                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1867                                 MLX5DV_FLOW_VLAN_VID_MASK),
1868                 .inner_type = RTE_BE16(0xffff),
1869         };
1870
1871         if (items == NULL)
1872                 return;
1873         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1874                 int type = items->type;
1875
1876                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1877                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1878                         break;
1879         }
1880         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1881                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1882                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1883
1884                 if (!vlan_m)
1885                         vlan_m = &nic_mask;
1886                 /* Only full match values are accepted */
1887                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1888                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1889                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1890                         vlan->vlan_tci |=
1891                                 rte_be_to_cpu_16(vlan_v->tci &
1892                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1893                 }
1894                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1895                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1896                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1897                         vlan->vlan_tci |=
1898                                 rte_be_to_cpu_16(vlan_v->tci &
1899                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1900                 }
1901                 if (vlan_m->inner_type == nic_mask.inner_type)
1902                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1903                                                            vlan_m->inner_type);
1904         }
1905 }
1906
1907 /**
1908  * Validate the push VLAN action.
1909  *
1910  * @param[in] dev
1911  *   Pointer to the rte_eth_dev structure.
1912  * @param[in] action_flags
1913  *   Holds the actions detected until now.
1914  * @param[in] item_flags
1915  *   The items found in this flow rule.
1916  * @param[in] action
1917  *   Pointer to the action structure.
1918  * @param[in] attr
1919  *   Pointer to flow attributes
1920  * @param[out] error
1921  *   Pointer to error structure.
1922  *
1923  * @return
1924  *   0 on success, a negative errno value otherwise and rte_errno is set.
1925  */
1926 static int
1927 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1928                                   uint64_t action_flags,
1929                                   const struct rte_flow_item_vlan *vlan_m,
1930                                   const struct rte_flow_action *action,
1931                                   const struct rte_flow_attr *attr,
1932                                   struct rte_flow_error *error)
1933 {
1934         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1935         const struct mlx5_priv *priv = dev->data->dev_private;
1936
1937         if (!attr->transfer && attr->ingress)
1938                 return rte_flow_error_set(error, ENOTSUP,
1939                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1940                                           NULL,
1941                                           "push VLAN action not supported for "
1942                                           "ingress");
1943         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1944             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1945                 return rte_flow_error_set(error, EINVAL,
1946                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1947                                           "invalid vlan ethertype");
1948         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1949                 return rte_flow_error_set(error, ENOTSUP,
1950                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1951                                           "no support for multiple VLAN "
1952                                           "actions");
1953         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1954                 return rte_flow_error_set(error, EINVAL,
1955                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1956                                           "wrong action order, port_id should "
1957                                           "be after push VLAN");
1958         if (!attr->transfer && priv->representor)
1959                 return rte_flow_error_set(error, ENOTSUP,
1960                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1961                                           "push vlan action for VF representor "
1962                                           "not supported on NIC table");
1963         if (vlan_m &&
1964             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1965             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1966                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1967             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1968             !(mlx5_flow_find_action
1969                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1970                 return rte_flow_error_set(error, EINVAL,
1971                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1972                                           "not full match mask on VLAN PCP and "
1973                                           "there is no of_set_vlan_pcp action, "
1974                                           "push VLAN action cannot figure out "
1975                                           "PCP value");
1976         if (vlan_m &&
1977             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1978             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1979                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1980             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1981             !(mlx5_flow_find_action
1982                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1983                 return rte_flow_error_set(error, EINVAL,
1984                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1985                                           "not full match mask on VLAN VID and "
1986                                           "there is no of_set_vlan_vid action, "
1987                                           "push VLAN action cannot figure out "
1988                                           "VID value");
1989         (void)attr;
1990         return 0;
1991 }
1992
1993 /**
1994  * Validate the set VLAN PCP.
1995  *
1996  * @param[in] action_flags
1997  *   Holds the actions detected until now.
1998  * @param[in] actions
1999  *   Pointer to the list of actions remaining in the flow rule.
2000  * @param[out] error
2001  *   Pointer to error structure.
2002  *
2003  * @return
2004  *   0 on success, a negative errno value otherwise and rte_errno is set.
2005  */
2006 static int
2007 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2008                                      const struct rte_flow_action actions[],
2009                                      struct rte_flow_error *error)
2010 {
2011         const struct rte_flow_action *action = actions;
2012         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2013
2014         if (conf->vlan_pcp > 7)
2015                 return rte_flow_error_set(error, EINVAL,
2016                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2017                                           "VLAN PCP value is too big");
2018         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2019                 return rte_flow_error_set(error, ENOTSUP,
2020                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2021                                           "set VLAN PCP action must follow "
2022                                           "the push VLAN action");
2023         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2024                 return rte_flow_error_set(error, ENOTSUP,
2025                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2026                                           "Multiple VLAN PCP modification are "
2027                                           "not supported");
2028         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2029                 return rte_flow_error_set(error, EINVAL,
2030                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2031                                           "wrong action order, port_id should "
2032                                           "be after set VLAN PCP");
2033         return 0;
2034 }
2035
2036 /**
2037  * Validate the set VLAN VID.
2038  *
2039  * @param[in] item_flags
2040  *   Holds the items detected in this rule.
2041  * @param[in] action_flags
2042  *   Holds the actions detected until now.
2043  * @param[in] actions
2044  *   Pointer to the list of actions remaining in the flow rule.
2045  * @param[out] error
2046  *   Pointer to error structure.
2047  *
2048  * @return
2049  *   0 on success, a negative errno value otherwise and rte_errno is set.
2050  */
2051 static int
2052 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2053                                      uint64_t action_flags,
2054                                      const struct rte_flow_action actions[],
2055                                      struct rte_flow_error *error)
2056 {
2057         const struct rte_flow_action *action = actions;
2058         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2059
2060         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2061                 return rte_flow_error_set(error, EINVAL,
2062                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2063                                           "VLAN VID value is too big");
2064         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2065             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2066                 return rte_flow_error_set(error, ENOTSUP,
2067                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2068                                           "set VLAN VID action must follow push"
2069                                           " VLAN action or match on VLAN item");
2070         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2071                 return rte_flow_error_set(error, ENOTSUP,
2072                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2073                                           "Multiple VLAN VID modifications are "
2074                                           "not supported");
2075         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2076                 return rte_flow_error_set(error, EINVAL,
2077                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2078                                           "wrong action order, port_id should "
2079                                           "be after set VLAN VID");
2080         return 0;
2081 }
2082
2083 /*
2084  * Validate the FLAG action.
2085  *
2086  * @param[in] dev
2087  *   Pointer to the rte_eth_dev structure.
2088  * @param[in] action_flags
2089  *   Holds the actions detected until now.
2090  * @param[in] attr
2091  *   Pointer to flow attributes
2092  * @param[out] error
2093  *   Pointer to error structure.
2094  *
2095  * @return
2096  *   0 on success, a negative errno value otherwise and rte_errno is set.
2097  */
2098 static int
2099 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2100                              uint64_t action_flags,
2101                              const struct rte_flow_attr *attr,
2102                              struct rte_flow_error *error)
2103 {
2104         struct mlx5_priv *priv = dev->data->dev_private;
2105         struct mlx5_dev_config *config = &priv->config;
2106         int ret;
2107
2108         /* Fall back if no extended metadata register support. */
2109         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2110                 return mlx5_flow_validate_action_flag(action_flags, attr,
2111                                                       error);
2112         /* Extensive metadata mode requires registers. */
2113         if (!mlx5_flow_ext_mreg_supported(dev))
2114                 return rte_flow_error_set(error, ENOTSUP,
2115                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2116                                           "no metadata registers "
2117                                           "to support flag action");
2118         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2119                 return rte_flow_error_set(error, ENOTSUP,
2120                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2121                                           "extended metadata register"
2122                                           " isn't available");
2123         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2124         if (ret < 0)
2125                 return ret;
2126         MLX5_ASSERT(ret > 0);
2127         if (action_flags & MLX5_FLOW_ACTION_MARK)
2128                 return rte_flow_error_set(error, EINVAL,
2129                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2130                                           "can't mark and flag in same flow");
2131         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2132                 return rte_flow_error_set(error, EINVAL,
2133                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2134                                           "can't have 2 flag"
2135                                           " actions in same flow");
2136         return 0;
2137 }
2138
2139 /**
2140  * Validate MARK action.
2141  *
2142  * @param[in] dev
2143  *   Pointer to the rte_eth_dev structure.
2144  * @param[in] action
2145  *   Pointer to action.
2146  * @param[in] action_flags
2147  *   Holds the actions detected until now.
2148  * @param[in] attr
2149  *   Pointer to flow attributes
2150  * @param[out] error
2151  *   Pointer to error structure.
2152  *
2153  * @return
2154  *   0 on success, a negative errno value otherwise and rte_errno is set.
2155  */
2156 static int
2157 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2158                              const struct rte_flow_action *action,
2159                              uint64_t action_flags,
2160                              const struct rte_flow_attr *attr,
2161                              struct rte_flow_error *error)
2162 {
2163         struct mlx5_priv *priv = dev->data->dev_private;
2164         struct mlx5_dev_config *config = &priv->config;
2165         const struct rte_flow_action_mark *mark = action->conf;
2166         int ret;
2167
2168         /* Fall back if no extended metadata register support. */
2169         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2170                 return mlx5_flow_validate_action_mark(action, action_flags,
2171                                                       attr, error);
2172         /* Extensive metadata mode requires registers. */
2173         if (!mlx5_flow_ext_mreg_supported(dev))
2174                 return rte_flow_error_set(error, ENOTSUP,
2175                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2176                                           "no metadata registers "
2177                                           "to support mark action");
2178         if (!priv->sh->dv_mark_mask)
2179                 return rte_flow_error_set(error, ENOTSUP,
2180                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2181                                           "extended metadata register"
2182                                           " isn't available");
2183         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2184         if (ret < 0)
2185                 return ret;
2186         MLX5_ASSERT(ret > 0);
2187         if (!mark)
2188                 return rte_flow_error_set(error, EINVAL,
2189                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2190                                           "configuration cannot be null");
2191         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2192                 return rte_flow_error_set(error, EINVAL,
2193                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2194                                           &mark->id,
2195                                           "mark id exceeds the limit");
2196         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2197                 return rte_flow_error_set(error, EINVAL,
2198                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2199                                           "can't flag and mark in same flow");
2200         if (action_flags & MLX5_FLOW_ACTION_MARK)
2201                 return rte_flow_error_set(error, EINVAL,
2202                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2203                                           "can't have 2 mark actions in same"
2204                                           " flow");
2205         return 0;
2206 }
2207
2208 /**
2209  * Validate SET_META action.
2210  *
2211  * @param[in] dev
2212  *   Pointer to the rte_eth_dev structure.
2213  * @param[in] action
2214  *   Pointer to the action structure.
2215  * @param[in] action_flags
2216  *   Holds the actions detected until now.
2217  * @param[in] attr
2218  *   Pointer to flow attributes
2219  * @param[out] error
2220  *   Pointer to error structure.
2221  *
2222  * @return
2223  *   0 on success, a negative errno value otherwise and rte_errno is set.
2224  */
2225 static int
2226 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2227                                  const struct rte_flow_action *action,
2228                                  uint64_t action_flags __rte_unused,
2229                                  const struct rte_flow_attr *attr,
2230                                  struct rte_flow_error *error)
2231 {
2232         const struct rte_flow_action_set_meta *conf;
2233         uint32_t nic_mask = UINT32_MAX;
2234         int reg;
2235
2236         if (!mlx5_flow_ext_mreg_supported(dev))
2237                 return rte_flow_error_set(error, ENOTSUP,
2238                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2239                                           "extended metadata register"
2240                                           " isn't supported");
2241         reg = flow_dv_get_metadata_reg(dev, attr, error);
2242         if (reg < 0)
2243                 return reg;
2244         if (reg != REG_A && reg != REG_B) {
2245                 struct mlx5_priv *priv = dev->data->dev_private;
2246
2247                 nic_mask = priv->sh->dv_meta_mask;
2248         }
2249         if (!(action->conf))
2250                 return rte_flow_error_set(error, EINVAL,
2251                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2252                                           "configuration cannot be null");
2253         conf = (const struct rte_flow_action_set_meta *)action->conf;
2254         if (!conf->mask)
2255                 return rte_flow_error_set(error, EINVAL,
2256                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2257                                           "zero mask doesn't have any effect");
2258         if (conf->mask & ~nic_mask)
2259                 return rte_flow_error_set(error, EINVAL,
2260                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2261                                           "meta data must be within reg C0");
2262         return 0;
2263 }
2264
2265 /**
2266  * Validate SET_TAG action.
2267  *
2268  * @param[in] dev
2269  *   Pointer to the rte_eth_dev structure.
2270  * @param[in] action
2271  *   Pointer to the action structure.
2272  * @param[in] action_flags
2273  *   Holds the actions detected until now.
2274  * @param[in] attr
2275  *   Pointer to flow attributes
2276  * @param[out] error
2277  *   Pointer to error structure.
2278  *
2279  * @return
2280  *   0 on success, a negative errno value otherwise and rte_errno is set.
2281  */
2282 static int
2283 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2284                                 const struct rte_flow_action *action,
2285                                 uint64_t action_flags,
2286                                 const struct rte_flow_attr *attr,
2287                                 struct rte_flow_error *error)
2288 {
2289         const struct rte_flow_action_set_tag *conf;
2290         const uint64_t terminal_action_flags =
2291                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2292                 MLX5_FLOW_ACTION_RSS;
2293         int ret;
2294
2295         if (!mlx5_flow_ext_mreg_supported(dev))
2296                 return rte_flow_error_set(error, ENOTSUP,
2297                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2298                                           "extensive metadata register"
2299                                           " isn't supported");
2300         if (!(action->conf))
2301                 return rte_flow_error_set(error, EINVAL,
2302                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2303                                           "configuration cannot be null");
2304         conf = (const struct rte_flow_action_set_tag *)action->conf;
2305         if (!conf->mask)
2306                 return rte_flow_error_set(error, EINVAL,
2307                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2308                                           "zero mask doesn't have any effect");
2309         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2310         if (ret < 0)
2311                 return ret;
2312         if (!attr->transfer && attr->ingress &&
2313             (action_flags & terminal_action_flags))
2314                 return rte_flow_error_set(error, EINVAL,
2315                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2316                                           "set_tag has no effect"
2317                                           " with terminal actions");
2318         return 0;
2319 }
2320
2321 /**
2322  * Validate count action.
2323  *
2324  * @param[in] dev
2325  *   Pointer to rte_eth_dev structure.
2326  * @param[out] error
2327  *   Pointer to error structure.
2328  *
2329  * @return
2330  *   0 on success, a negative errno value otherwise and rte_errno is set.
2331  */
2332 static int
2333 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2334                               struct rte_flow_error *error)
2335 {
2336         struct mlx5_priv *priv = dev->data->dev_private;
2337
2338         if (!priv->config.devx)
2339                 goto notsup_err;
2340 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2341         return 0;
2342 #endif
2343 notsup_err:
2344         return rte_flow_error_set
2345                       (error, ENOTSUP,
2346                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2347                        NULL,
2348                        "count action not supported");
2349 }
2350
2351 /**
2352  * Validate the L2 encap action.
2353  *
2354  * @param[in] dev
2355  *   Pointer to the rte_eth_dev structure.
2356  * @param[in] action_flags
2357  *   Holds the actions detected until now.
2358  * @param[in] action
2359  *   Pointer to the action structure.
2360  * @param[in] attr
2361  *   Pointer to flow attributes.
2362  * @param[out] error
2363  *   Pointer to error structure.
2364  *
2365  * @return
2366  *   0 on success, a negative errno value otherwise and rte_errno is set.
2367  */
2368 static int
2369 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2370                                  uint64_t action_flags,
2371                                  const struct rte_flow_action *action,
2372                                  const struct rte_flow_attr *attr,
2373                                  struct rte_flow_error *error)
2374 {
2375         const struct mlx5_priv *priv = dev->data->dev_private;
2376
2377         if (!(action->conf))
2378                 return rte_flow_error_set(error, EINVAL,
2379                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2380                                           "configuration cannot be null");
2381         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2382                 return rte_flow_error_set(error, EINVAL,
2383                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2384                                           "can only have a single encap action "
2385                                           "in a flow");
2386         if (!attr->transfer && priv->representor)
2387                 return rte_flow_error_set(error, ENOTSUP,
2388                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2389                                           "encap action for VF representor "
2390                                           "not supported on NIC table");
2391         return 0;
2392 }
2393
2394 /**
2395  * Validate a decap action.
2396  *
2397  * @param[in] dev
2398  *   Pointer to the rte_eth_dev structure.
2399  * @param[in] action_flags
2400  *   Holds the actions detected until now.
2401  * @param[in] attr
2402  *   Pointer to flow attributes
2403  * @param[out] error
2404  *   Pointer to error structure.
2405  *
2406  * @return
2407  *   0 on success, a negative errno value otherwise and rte_errno is set.
2408  */
2409 static int
2410 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2411                               uint64_t action_flags,
2412                               const struct rte_flow_attr *attr,
2413                               struct rte_flow_error *error)
2414 {
2415         const struct mlx5_priv *priv = dev->data->dev_private;
2416
2417         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2418                 return rte_flow_error_set(error, ENOTSUP,
2419                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2420                                           action_flags &
2421                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2422                                           "have a single decap action" : "decap "
2423                                           "after encap is not supported");
2424         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2425                 return rte_flow_error_set(error, EINVAL,
2426                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2427                                           "can't have decap action after"
2428                                           " modify action");
2429         if (attr->egress)
2430                 return rte_flow_error_set(error, ENOTSUP,
2431                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2432                                           NULL,
2433                                           "decap action not supported for "
2434                                           "egress");
2435         if (!attr->transfer && priv->representor)
2436                 return rte_flow_error_set(error, ENOTSUP,
2437                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2438                                           "decap action for VF representor "
2439                                           "not supported on NIC table");
2440         return 0;
2441 }
2442
2443 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2444
2445 /**
2446  * Validate the raw encap and decap actions.
2447  *
2448  * @param[in] dev
2449  *   Pointer to the rte_eth_dev structure.
2450  * @param[in] decap
2451  *   Pointer to the decap action.
2452  * @param[in] encap
2453  *   Pointer to the encap action.
2454  * @param[in] attr
2455  *   Pointer to flow attributes
2456  * @param[in/out] action_flags
2457  *   Holds the actions detected until now.
2458  * @param[out] actions_n
2459  *   pointer to the number of actions counter.
2460  * @param[out] error
2461  *   Pointer to error structure.
2462  *
2463  * @return
2464  *   0 on success, a negative errno value otherwise and rte_errno is set.
2465  */
2466 static int
2467 flow_dv_validate_action_raw_encap_decap
2468         (struct rte_eth_dev *dev,
2469          const struct rte_flow_action_raw_decap *decap,
2470          const struct rte_flow_action_raw_encap *encap,
2471          const struct rte_flow_attr *attr, uint64_t *action_flags,
2472          int *actions_n, struct rte_flow_error *error)
2473 {
2474         const struct mlx5_priv *priv = dev->data->dev_private;
2475         int ret;
2476
2477         if (encap && (!encap->size || !encap->data))
2478                 return rte_flow_error_set(error, EINVAL,
2479                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2480                                           "raw encap data cannot be empty");
2481         if (decap && encap) {
2482                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2483                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2484                         /* L3 encap. */
2485                         decap = NULL;
2486                 else if (encap->size <=
2487                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2488                            decap->size >
2489                            MLX5_ENCAPSULATION_DECISION_SIZE)
2490                         /* L3 decap. */
2491                         encap = NULL;
2492                 else if (encap->size >
2493                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2494                            decap->size >
2495                            MLX5_ENCAPSULATION_DECISION_SIZE)
2496                         /* 2 L2 actions: encap and decap. */
2497                         ;
2498                 else
2499                         return rte_flow_error_set(error,
2500                                 ENOTSUP,
2501                                 RTE_FLOW_ERROR_TYPE_ACTION,
2502                                 NULL, "unsupported too small "
2503                                 "raw decap and too small raw "
2504                                 "encap combination");
2505         }
2506         if (decap) {
2507                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2508                                                     error);
2509                 if (ret < 0)
2510                         return ret;
2511                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2512                 ++(*actions_n);
2513         }
2514         if (encap) {
2515                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2516                         return rte_flow_error_set(error, ENOTSUP,
2517                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2518                                                   NULL,
2519                                                   "small raw encap size");
2520                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2521                         return rte_flow_error_set(error, EINVAL,
2522                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2523                                                   NULL,
2524                                                   "more than one encap action");
2525                 if (!attr->transfer && priv->representor)
2526                         return rte_flow_error_set
2527                                         (error, ENOTSUP,
2528                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2529                                          "encap action for VF representor "
2530                                          "not supported on NIC table");
2531                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2532                 ++(*actions_n);
2533         }
2534         return 0;
2535 }
2536
2537 /**
2538  * Find existing encap/decap resource or create and register a new one.
2539  *
2540  * @param[in, out] dev
2541  *   Pointer to rte_eth_dev structure.
2542  * @param[in, out] resource
2543  *   Pointer to encap/decap resource.
2544  * @parm[in, out] dev_flow
2545  *   Pointer to the dev_flow.
2546  * @param[out] error
2547  *   pointer to error structure.
2548  *
2549  * @return
2550  *   0 on success otherwise -errno and errno is set.
2551  */
2552 static int
2553 flow_dv_encap_decap_resource_register
2554                         (struct rte_eth_dev *dev,
2555                          struct mlx5_flow_dv_encap_decap_resource *resource,
2556                          struct mlx5_flow *dev_flow,
2557                          struct rte_flow_error *error)
2558 {
2559         struct mlx5_priv *priv = dev->data->dev_private;
2560         struct mlx5_ibv_shared *sh = priv->sh;
2561         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2562         struct mlx5dv_dr_domain *domain;
2563         uint32_t idx = 0;
2564
2565         resource->flags = dev_flow->dv.group ? 0 : 1;
2566         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2567                 domain = sh->fdb_domain;
2568         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2569                 domain = sh->rx_domain;
2570         else
2571                 domain = sh->tx_domain;
2572         /* Lookup a matching resource from cache. */
2573         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2574                       cache_resource, next) {
2575                 if (resource->reformat_type == cache_resource->reformat_type &&
2576                     resource->ft_type == cache_resource->ft_type &&
2577                     resource->flags == cache_resource->flags &&
2578                     resource->size == cache_resource->size &&
2579                     !memcmp((const void *)resource->buf,
2580                             (const void *)cache_resource->buf,
2581                             resource->size)) {
2582                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2583                                 (void *)cache_resource,
2584                                 rte_atomic32_read(&cache_resource->refcnt));
2585                         rte_atomic32_inc(&cache_resource->refcnt);
2586                         dev_flow->handle->dvh.rix_encap_decap = idx;
2587                         dev_flow->dv.encap_decap = cache_resource;
2588                         return 0;
2589                 }
2590         }
2591         /* Register new encap/decap resource. */
2592         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2593                                        &dev_flow->handle->dvh.rix_encap_decap);
2594         if (!cache_resource)
2595                 return rte_flow_error_set(error, ENOMEM,
2596                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2597                                           "cannot allocate resource memory");
2598         *cache_resource = *resource;
2599         cache_resource->verbs_action =
2600                 mlx5_glue->dv_create_flow_action_packet_reformat
2601                         (sh->ctx, cache_resource->reformat_type,
2602                          cache_resource->ft_type, domain, cache_resource->flags,
2603                          cache_resource->size,
2604                          (cache_resource->size ? cache_resource->buf : NULL));
2605         if (!cache_resource->verbs_action) {
2606                 rte_free(cache_resource);
2607                 return rte_flow_error_set(error, ENOMEM,
2608                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2609                                           NULL, "cannot create action");
2610         }
2611         rte_atomic32_init(&cache_resource->refcnt);
2612         rte_atomic32_inc(&cache_resource->refcnt);
2613         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2614                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2615                      next);
2616         dev_flow->dv.encap_decap = cache_resource;
2617         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2618                 (void *)cache_resource,
2619                 rte_atomic32_read(&cache_resource->refcnt));
2620         return 0;
2621 }
2622
2623 /**
2624  * Find existing table jump resource or create and register a new one.
2625  *
2626  * @param[in, out] dev
2627  *   Pointer to rte_eth_dev structure.
2628  * @param[in, out] tbl
2629  *   Pointer to flow table resource.
2630  * @parm[in, out] dev_flow
2631  *   Pointer to the dev_flow.
2632  * @param[out] error
2633  *   pointer to error structure.
2634  *
2635  * @return
2636  *   0 on success otherwise -errno and errno is set.
2637  */
2638 static int
2639 flow_dv_jump_tbl_resource_register
2640                         (struct rte_eth_dev *dev __rte_unused,
2641                          struct mlx5_flow_tbl_resource *tbl,
2642                          struct mlx5_flow *dev_flow,
2643                          struct rte_flow_error *error)
2644 {
2645         struct mlx5_flow_tbl_data_entry *tbl_data =
2646                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2647         int cnt;
2648
2649         MLX5_ASSERT(tbl);
2650         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2651         if (!cnt) {
2652                 tbl_data->jump.action =
2653                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2654                         (tbl->obj);
2655                 if (!tbl_data->jump.action)
2656                         return rte_flow_error_set(error, ENOMEM,
2657                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2658                                         NULL, "cannot create jump action");
2659                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2660                         (void *)&tbl_data->jump, cnt);
2661         } else {
2662                 /* old jump should not make the table ref++. */
2663                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2664                 MLX5_ASSERT(tbl_data->jump.action);
2665                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2666                         (void *)&tbl_data->jump, cnt);
2667         }
2668         rte_atomic32_inc(&tbl_data->jump.refcnt);
2669         dev_flow->handle->rix_jump = tbl_data->idx;
2670         dev_flow->dv.jump = &tbl_data->jump;
2671         return 0;
2672 }
2673
2674 /**
2675  * Find existing table port ID resource or create and register a new one.
2676  *
2677  * @param[in, out] dev
2678  *   Pointer to rte_eth_dev structure.
2679  * @param[in, out] resource
2680  *   Pointer to port ID action resource.
2681  * @parm[in, out] dev_flow
2682  *   Pointer to the dev_flow.
2683  * @param[out] error
2684  *   pointer to error structure.
2685  *
2686  * @return
2687  *   0 on success otherwise -errno and errno is set.
2688  */
2689 static int
2690 flow_dv_port_id_action_resource_register
2691                         (struct rte_eth_dev *dev,
2692                          struct mlx5_flow_dv_port_id_action_resource *resource,
2693                          struct mlx5_flow *dev_flow,
2694                          struct rte_flow_error *error)
2695 {
2696         struct mlx5_priv *priv = dev->data->dev_private;
2697         struct mlx5_ibv_shared *sh = priv->sh;
2698         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2699         uint32_t idx = 0;
2700
2701         /* Lookup a matching resource from cache. */
2702         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2703                       idx, cache_resource, next) {
2704                 if (resource->port_id == cache_resource->port_id) {
2705                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2706                                 "refcnt %d++",
2707                                 (void *)cache_resource,
2708                                 rte_atomic32_read(&cache_resource->refcnt));
2709                         rte_atomic32_inc(&cache_resource->refcnt);
2710                         dev_flow->handle->rix_port_id_action = idx;
2711                         dev_flow->dv.port_id_action = cache_resource;
2712                         return 0;
2713                 }
2714         }
2715         /* Register new port id action resource. */
2716         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2717                                        &dev_flow->handle->rix_port_id_action);
2718         if (!cache_resource)
2719                 return rte_flow_error_set(error, ENOMEM,
2720                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2721                                           "cannot allocate resource memory");
2722         *cache_resource = *resource;
2723         /*
2724          * Depending on rdma_core version the glue routine calls
2725          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2726          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2727          */
2728         cache_resource->action =
2729                 mlx5_glue->dr_create_flow_action_dest_port
2730                         (priv->sh->fdb_domain, resource->port_id);
2731         if (!cache_resource->action) {
2732                 rte_free(cache_resource);
2733                 return rte_flow_error_set(error, ENOMEM,
2734                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2735                                           NULL, "cannot create action");
2736         }
2737         rte_atomic32_init(&cache_resource->refcnt);
2738         rte_atomic32_inc(&cache_resource->refcnt);
2739         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2740                      dev_flow->handle->rix_port_id_action, cache_resource,
2741                      next);
2742         dev_flow->dv.port_id_action = cache_resource;
2743         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2744                 (void *)cache_resource,
2745                 rte_atomic32_read(&cache_resource->refcnt));
2746         return 0;
2747 }
2748
2749 /**
2750  * Find existing push vlan resource or create and register a new one.
2751  *
2752  * @param [in, out] dev
2753  *   Pointer to rte_eth_dev structure.
2754  * @param[in, out] resource
2755  *   Pointer to port ID action resource.
2756  * @parm[in, out] dev_flow
2757  *   Pointer to the dev_flow.
2758  * @param[out] error
2759  *   pointer to error structure.
2760  *
2761  * @return
2762  *   0 on success otherwise -errno and errno is set.
2763  */
2764 static int
2765 flow_dv_push_vlan_action_resource_register
2766                        (struct rte_eth_dev *dev,
2767                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2768                         struct mlx5_flow *dev_flow,
2769                         struct rte_flow_error *error)
2770 {
2771         struct mlx5_priv *priv = dev->data->dev_private;
2772         struct mlx5_ibv_shared *sh = priv->sh;
2773         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2774         struct mlx5dv_dr_domain *domain;
2775         uint32_t idx = 0;
2776
2777         /* Lookup a matching resource from cache. */
2778         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2779                       sh->push_vlan_action_list, idx, cache_resource, next) {
2780                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2781                     resource->ft_type == cache_resource->ft_type) {
2782                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2783                                 "refcnt %d++",
2784                                 (void *)cache_resource,
2785                                 rte_atomic32_read(&cache_resource->refcnt));
2786                         rte_atomic32_inc(&cache_resource->refcnt);
2787                         dev_flow->handle->dvh.rix_push_vlan = idx;
2788                         dev_flow->dv.push_vlan_res = cache_resource;
2789                         return 0;
2790                 }
2791         }
2792         /* Register new push_vlan action resource. */
2793         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2794                                        &dev_flow->handle->dvh.rix_push_vlan);
2795         if (!cache_resource)
2796                 return rte_flow_error_set(error, ENOMEM,
2797                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2798                                           "cannot allocate resource memory");
2799         *cache_resource = *resource;
2800         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2801                 domain = sh->fdb_domain;
2802         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2803                 domain = sh->rx_domain;
2804         else
2805                 domain = sh->tx_domain;
2806         cache_resource->action =
2807                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2808                                                            resource->vlan_tag);
2809         if (!cache_resource->action) {
2810                 rte_free(cache_resource);
2811                 return rte_flow_error_set(error, ENOMEM,
2812                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2813                                           NULL, "cannot create action");
2814         }
2815         rte_atomic32_init(&cache_resource->refcnt);
2816         rte_atomic32_inc(&cache_resource->refcnt);
2817         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2818                      &sh->push_vlan_action_list,
2819                      dev_flow->handle->dvh.rix_push_vlan,
2820                      cache_resource, next);
2821         dev_flow->dv.push_vlan_res = cache_resource;
2822         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2823                 (void *)cache_resource,
2824                 rte_atomic32_read(&cache_resource->refcnt));
2825         return 0;
2826 }
2827 /**
2828  * Get the size of specific rte_flow_item_type
2829  *
2830  * @param[in] item_type
2831  *   Tested rte_flow_item_type.
2832  *
2833  * @return
2834  *   sizeof struct item_type, 0 if void or irrelevant.
2835  */
2836 static size_t
2837 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2838 {
2839         size_t retval;
2840
2841         switch (item_type) {
2842         case RTE_FLOW_ITEM_TYPE_ETH:
2843                 retval = sizeof(struct rte_flow_item_eth);
2844                 break;
2845         case RTE_FLOW_ITEM_TYPE_VLAN:
2846                 retval = sizeof(struct rte_flow_item_vlan);
2847                 break;
2848         case RTE_FLOW_ITEM_TYPE_IPV4:
2849                 retval = sizeof(struct rte_flow_item_ipv4);
2850                 break;
2851         case RTE_FLOW_ITEM_TYPE_IPV6:
2852                 retval = sizeof(struct rte_flow_item_ipv6);
2853                 break;
2854         case RTE_FLOW_ITEM_TYPE_UDP:
2855                 retval = sizeof(struct rte_flow_item_udp);
2856                 break;
2857         case RTE_FLOW_ITEM_TYPE_TCP:
2858                 retval = sizeof(struct rte_flow_item_tcp);
2859                 break;
2860         case RTE_FLOW_ITEM_TYPE_VXLAN:
2861                 retval = sizeof(struct rte_flow_item_vxlan);
2862                 break;
2863         case RTE_FLOW_ITEM_TYPE_GRE:
2864                 retval = sizeof(struct rte_flow_item_gre);
2865                 break;
2866         case RTE_FLOW_ITEM_TYPE_NVGRE:
2867                 retval = sizeof(struct rte_flow_item_nvgre);
2868                 break;
2869         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2870                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2871                 break;
2872         case RTE_FLOW_ITEM_TYPE_MPLS:
2873                 retval = sizeof(struct rte_flow_item_mpls);
2874                 break;
2875         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2876         default:
2877                 retval = 0;
2878                 break;
2879         }
2880         return retval;
2881 }
2882
2883 #define MLX5_ENCAP_IPV4_VERSION         0x40
2884 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2885 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2886 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2887 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2888 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2889 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2890
2891 /**
2892  * Convert the encap action data from list of rte_flow_item to raw buffer
2893  *
2894  * @param[in] items
2895  *   Pointer to rte_flow_item objects list.
2896  * @param[out] buf
2897  *   Pointer to the output buffer.
2898  * @param[out] size
2899  *   Pointer to the output buffer size.
2900  * @param[out] error
2901  *   Pointer to the error structure.
2902  *
2903  * @return
2904  *   0 on success, a negative errno value otherwise and rte_errno is set.
2905  */
2906 static int
2907 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2908                            size_t *size, struct rte_flow_error *error)
2909 {
2910         struct rte_ether_hdr *eth = NULL;
2911         struct rte_vlan_hdr *vlan = NULL;
2912         struct rte_ipv4_hdr *ipv4 = NULL;
2913         struct rte_ipv6_hdr *ipv6 = NULL;
2914         struct rte_udp_hdr *udp = NULL;
2915         struct rte_vxlan_hdr *vxlan = NULL;
2916         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2917         struct rte_gre_hdr *gre = NULL;
2918         size_t len;
2919         size_t temp_size = 0;
2920
2921         if (!items)
2922                 return rte_flow_error_set(error, EINVAL,
2923                                           RTE_FLOW_ERROR_TYPE_ACTION,
2924                                           NULL, "invalid empty data");
2925         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2926                 len = flow_dv_get_item_len(items->type);
2927                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2928                         return rte_flow_error_set(error, EINVAL,
2929                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2930                                                   (void *)items->type,
2931                                                   "items total size is too big"
2932                                                   " for encap action");
2933                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2934                 switch (items->type) {
2935                 case RTE_FLOW_ITEM_TYPE_ETH:
2936                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2937                         break;
2938                 case RTE_FLOW_ITEM_TYPE_VLAN:
2939                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2940                         if (!eth)
2941                                 return rte_flow_error_set(error, EINVAL,
2942                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2943                                                 (void *)items->type,
2944                                                 "eth header not found");
2945                         if (!eth->ether_type)
2946                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2947                         break;
2948                 case RTE_FLOW_ITEM_TYPE_IPV4:
2949                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2950                         if (!vlan && !eth)
2951                                 return rte_flow_error_set(error, EINVAL,
2952                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2953                                                 (void *)items->type,
2954                                                 "neither eth nor vlan"
2955                                                 " header found");
2956                         if (vlan && !vlan->eth_proto)
2957                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2958                         else if (eth && !eth->ether_type)
2959                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2960                         if (!ipv4->version_ihl)
2961                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2962                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2963                         if (!ipv4->time_to_live)
2964                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2965                         break;
2966                 case RTE_FLOW_ITEM_TYPE_IPV6:
2967                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2968                         if (!vlan && !eth)
2969                                 return rte_flow_error_set(error, EINVAL,
2970                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2971                                                 (void *)items->type,
2972                                                 "neither eth nor vlan"
2973                                                 " header found");
2974                         if (vlan && !vlan->eth_proto)
2975                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2976                         else if (eth && !eth->ether_type)
2977                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2978                         if (!ipv6->vtc_flow)
2979                                 ipv6->vtc_flow =
2980                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2981                         if (!ipv6->hop_limits)
2982                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2983                         break;
2984                 case RTE_FLOW_ITEM_TYPE_UDP:
2985                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2986                         if (!ipv4 && !ipv6)
2987                                 return rte_flow_error_set(error, EINVAL,
2988                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2989                                                 (void *)items->type,
2990                                                 "ip header not found");
2991                         if (ipv4 && !ipv4->next_proto_id)
2992                                 ipv4->next_proto_id = IPPROTO_UDP;
2993                         else if (ipv6 && !ipv6->proto)
2994                                 ipv6->proto = IPPROTO_UDP;
2995                         break;
2996                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2997                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2998                         if (!udp)
2999                                 return rte_flow_error_set(error, EINVAL,
3000                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3001                                                 (void *)items->type,
3002                                                 "udp header not found");
3003                         if (!udp->dst_port)
3004                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3005                         if (!vxlan->vx_flags)
3006                                 vxlan->vx_flags =
3007                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3008                         break;
3009                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3010                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3011                         if (!udp)
3012                                 return rte_flow_error_set(error, EINVAL,
3013                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3014                                                 (void *)items->type,
3015                                                 "udp header not found");
3016                         if (!vxlan_gpe->proto)
3017                                 return rte_flow_error_set(error, EINVAL,
3018                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3019                                                 (void *)items->type,
3020                                                 "next protocol not found");
3021                         if (!udp->dst_port)
3022                                 udp->dst_port =
3023                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3024                         if (!vxlan_gpe->vx_flags)
3025                                 vxlan_gpe->vx_flags =
3026                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3027                         break;
3028                 case RTE_FLOW_ITEM_TYPE_GRE:
3029                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3030                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3031                         if (!gre->proto)
3032                                 return rte_flow_error_set(error, EINVAL,
3033                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3034                                                 (void *)items->type,
3035                                                 "next protocol not found");
3036                         if (!ipv4 && !ipv6)
3037                                 return rte_flow_error_set(error, EINVAL,
3038                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3039                                                 (void *)items->type,
3040                                                 "ip header not found");
3041                         if (ipv4 && !ipv4->next_proto_id)
3042                                 ipv4->next_proto_id = IPPROTO_GRE;
3043                         else if (ipv6 && !ipv6->proto)
3044                                 ipv6->proto = IPPROTO_GRE;
3045                         break;
3046                 case RTE_FLOW_ITEM_TYPE_VOID:
3047                         break;
3048                 default:
3049                         return rte_flow_error_set(error, EINVAL,
3050                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3051                                                   (void *)items->type,
3052                                                   "unsupported item type");
3053                         break;
3054                 }
3055                 temp_size += len;
3056         }
3057         *size = temp_size;
3058         return 0;
3059 }
3060
3061 static int
3062 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3063 {
3064         struct rte_ether_hdr *eth = NULL;
3065         struct rte_vlan_hdr *vlan = NULL;
3066         struct rte_ipv6_hdr *ipv6 = NULL;
3067         struct rte_udp_hdr *udp = NULL;
3068         char *next_hdr;
3069         uint16_t proto;
3070
3071         eth = (struct rte_ether_hdr *)data;
3072         next_hdr = (char *)(eth + 1);
3073         proto = RTE_BE16(eth->ether_type);
3074
3075         /* VLAN skipping */
3076         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3077                 vlan = (struct rte_vlan_hdr *)next_hdr;
3078                 proto = RTE_BE16(vlan->eth_proto);
3079                 next_hdr += sizeof(struct rte_vlan_hdr);
3080         }
3081
3082         /* HW calculates IPv4 csum. no need to proceed */
3083         if (proto == RTE_ETHER_TYPE_IPV4)
3084                 return 0;
3085
3086         /* non IPv4/IPv6 header. not supported */
3087         if (proto != RTE_ETHER_TYPE_IPV6) {
3088                 return rte_flow_error_set(error, ENOTSUP,
3089                                           RTE_FLOW_ERROR_TYPE_ACTION,
3090                                           NULL, "Cannot offload non IPv4/IPv6");
3091         }
3092
3093         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3094
3095         /* ignore non UDP */
3096         if (ipv6->proto != IPPROTO_UDP)
3097                 return 0;
3098
3099         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3100         udp->dgram_cksum = 0;
3101
3102         return 0;
3103 }
3104
3105 /**
3106  * Convert L2 encap action to DV specification.
3107  *
3108  * @param[in] dev
3109  *   Pointer to rte_eth_dev structure.
3110  * @param[in] action
3111  *   Pointer to action structure.
3112  * @param[in, out] dev_flow
3113  *   Pointer to the mlx5_flow.
3114  * @param[in] transfer
3115  *   Mark if the flow is E-Switch flow.
3116  * @param[out] error
3117  *   Pointer to the error structure.
3118  *
3119  * @return
3120  *   0 on success, a negative errno value otherwise and rte_errno is set.
3121  */
3122 static int
3123 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3124                                const struct rte_flow_action *action,
3125                                struct mlx5_flow *dev_flow,
3126                                uint8_t transfer,
3127                                struct rte_flow_error *error)
3128 {
3129         const struct rte_flow_item *encap_data;
3130         const struct rte_flow_action_raw_encap *raw_encap_data;
3131         struct mlx5_flow_dv_encap_decap_resource res = {
3132                 .reformat_type =
3133                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3134                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3135                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3136         };
3137
3138         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3139                 raw_encap_data =
3140                         (const struct rte_flow_action_raw_encap *)action->conf;
3141                 res.size = raw_encap_data->size;
3142                 memcpy(res.buf, raw_encap_data->data, res.size);
3143         } else {
3144                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3145                         encap_data =
3146                                 ((const struct rte_flow_action_vxlan_encap *)
3147                                                 action->conf)->definition;
3148                 else
3149                         encap_data =
3150                                 ((const struct rte_flow_action_nvgre_encap *)
3151                                                 action->conf)->definition;
3152                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3153                                                &res.size, error))
3154                         return -rte_errno;
3155         }
3156         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3157                 return -rte_errno;
3158         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3159                 return rte_flow_error_set(error, EINVAL,
3160                                           RTE_FLOW_ERROR_TYPE_ACTION,
3161                                           NULL, "can't create L2 encap action");
3162         return 0;
3163 }
3164
3165 /**
3166  * Convert L2 decap action to DV specification.
3167  *
3168  * @param[in] dev
3169  *   Pointer to rte_eth_dev structure.
3170  * @param[in, out] dev_flow
3171  *   Pointer to the mlx5_flow.
3172  * @param[in] transfer
3173  *   Mark if the flow is E-Switch flow.
3174  * @param[out] error
3175  *   Pointer to the error structure.
3176  *
3177  * @return
3178  *   0 on success, a negative errno value otherwise and rte_errno is set.
3179  */
3180 static int
3181 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3182                                struct mlx5_flow *dev_flow,
3183                                uint8_t transfer,
3184                                struct rte_flow_error *error)
3185 {
3186         struct mlx5_flow_dv_encap_decap_resource res = {
3187                 .size = 0,
3188                 .reformat_type =
3189                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3190                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3191                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3192         };
3193
3194         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3195                 return rte_flow_error_set(error, EINVAL,
3196                                           RTE_FLOW_ERROR_TYPE_ACTION,
3197                                           NULL, "can't create L2 decap action");
3198         return 0;
3199 }
3200
3201 /**
3202  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3203  *
3204  * @param[in] dev
3205  *   Pointer to rte_eth_dev structure.
3206  * @param[in] action
3207  *   Pointer to action structure.
3208  * @param[in, out] dev_flow
3209  *   Pointer to the mlx5_flow.
3210  * @param[in] attr
3211  *   Pointer to the flow attributes.
3212  * @param[out] error
3213  *   Pointer to the error structure.
3214  *
3215  * @return
3216  *   0 on success, a negative errno value otherwise and rte_errno is set.
3217  */
3218 static int
3219 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3220                                 const struct rte_flow_action *action,
3221                                 struct mlx5_flow *dev_flow,
3222                                 const struct rte_flow_attr *attr,
3223                                 struct rte_flow_error *error)
3224 {
3225         const struct rte_flow_action_raw_encap *encap_data;
3226         struct mlx5_flow_dv_encap_decap_resource res;
3227
3228         memset(&res, 0, sizeof(res));
3229         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3230         res.size = encap_data->size;
3231         memcpy(res.buf, encap_data->data, res.size);
3232         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3233                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3234                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3235         if (attr->transfer)
3236                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3237         else
3238                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3239                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3240         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3241                 return rte_flow_error_set(error, EINVAL,
3242                                           RTE_FLOW_ERROR_TYPE_ACTION,
3243                                           NULL, "can't create encap action");
3244         return 0;
3245 }
3246
3247 /**
3248  * Create action push VLAN.
3249  *
3250  * @param[in] dev
3251  *   Pointer to rte_eth_dev structure.
3252  * @param[in] attr
3253  *   Pointer to the flow attributes.
3254  * @param[in] vlan
3255  *   Pointer to the vlan to push to the Ethernet header.
3256  * @param[in, out] dev_flow
3257  *   Pointer to the mlx5_flow.
3258  * @param[out] error
3259  *   Pointer to the error structure.
3260  *
3261  * @return
3262  *   0 on success, a negative errno value otherwise and rte_errno is set.
3263  */
3264 static int
3265 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3266                                 const struct rte_flow_attr *attr,
3267                                 const struct rte_vlan_hdr *vlan,
3268                                 struct mlx5_flow *dev_flow,
3269                                 struct rte_flow_error *error)
3270 {
3271         struct mlx5_flow_dv_push_vlan_action_resource res;
3272
3273         memset(&res, 0, sizeof(res));
3274         res.vlan_tag =
3275                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3276                                  vlan->vlan_tci);
3277         if (attr->transfer)
3278                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3279         else
3280                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3281                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3282         return flow_dv_push_vlan_action_resource_register
3283                                             (dev, &res, dev_flow, error);
3284 }
3285
3286 /**
3287  * Validate the modify-header actions.
3288  *
3289  * @param[in] action_flags
3290  *   Holds the actions detected until now.
3291  * @param[in] action
3292  *   Pointer to the modify action.
3293  * @param[out] error
3294  *   Pointer to error structure.
3295  *
3296  * @return
3297  *   0 on success, a negative errno value otherwise and rte_errno is set.
3298  */
3299 static int
3300 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3301                                    const struct rte_flow_action *action,
3302                                    struct rte_flow_error *error)
3303 {
3304         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3305                 return rte_flow_error_set(error, EINVAL,
3306                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3307                                           NULL, "action configuration not set");
3308         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3309                 return rte_flow_error_set(error, EINVAL,
3310                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3311                                           "can't have encap action before"
3312                                           " modify action");
3313         return 0;
3314 }
3315
3316 /**
3317  * Validate the modify-header MAC address actions.
3318  *
3319  * @param[in] action_flags
3320  *   Holds the actions detected until now.
3321  * @param[in] action
3322  *   Pointer to the modify action.
3323  * @param[in] item_flags
3324  *   Holds the items detected.
3325  * @param[out] error
3326  *   Pointer to error structure.
3327  *
3328  * @return
3329  *   0 on success, a negative errno value otherwise and rte_errno is set.
3330  */
3331 static int
3332 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3333                                    const struct rte_flow_action *action,
3334                                    const uint64_t item_flags,
3335                                    struct rte_flow_error *error)
3336 {
3337         int ret = 0;
3338
3339         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3340         if (!ret) {
3341                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3342                         return rte_flow_error_set(error, EINVAL,
3343                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3344                                                   NULL,
3345                                                   "no L2 item in pattern");
3346         }
3347         return ret;
3348 }
3349
3350 /**
3351  * Validate the modify-header IPv4 address actions.
3352  *
3353  * @param[in] action_flags
3354  *   Holds the actions detected until now.
3355  * @param[in] action
3356  *   Pointer to the modify action.
3357  * @param[in] item_flags
3358  *   Holds the items detected.
3359  * @param[out] error
3360  *   Pointer to error structure.
3361  *
3362  * @return
3363  *   0 on success, a negative errno value otherwise and rte_errno is set.
3364  */
3365 static int
3366 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3367                                     const struct rte_flow_action *action,
3368                                     const uint64_t item_flags,
3369                                     struct rte_flow_error *error)
3370 {
3371         int ret = 0;
3372         uint64_t layer;
3373
3374         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3375         if (!ret) {
3376                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3377                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3378                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3379                 if (!(item_flags & layer))
3380                         return rte_flow_error_set(error, EINVAL,
3381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3382                                                   NULL,
3383                                                   "no ipv4 item in pattern");
3384         }
3385         return ret;
3386 }
3387
3388 /**
3389  * Validate the modify-header IPv6 address actions.
3390  *
3391  * @param[in] action_flags
3392  *   Holds the actions detected until now.
3393  * @param[in] action
3394  *   Pointer to the modify action.
3395  * @param[in] item_flags
3396  *   Holds the items detected.
3397  * @param[out] error
3398  *   Pointer to error structure.
3399  *
3400  * @return
3401  *   0 on success, a negative errno value otherwise and rte_errno is set.
3402  */
3403 static int
3404 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3405                                     const struct rte_flow_action *action,
3406                                     const uint64_t item_flags,
3407                                     struct rte_flow_error *error)
3408 {
3409         int ret = 0;
3410         uint64_t layer;
3411
3412         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3413         if (!ret) {
3414                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3416                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3417                 if (!(item_flags & layer))
3418                         return rte_flow_error_set(error, EINVAL,
3419                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3420                                                   NULL,
3421                                                   "no ipv6 item in pattern");
3422         }
3423         return ret;
3424 }
3425
3426 /**
3427  * Validate the modify-header TP actions.
3428  *
3429  * @param[in] action_flags
3430  *   Holds the actions detected until now.
3431  * @param[in] action
3432  *   Pointer to the modify action.
3433  * @param[in] item_flags
3434  *   Holds the items detected.
3435  * @param[out] error
3436  *   Pointer to error structure.
3437  *
3438  * @return
3439  *   0 on success, a negative errno value otherwise and rte_errno is set.
3440  */
3441 static int
3442 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3443                                   const struct rte_flow_action *action,
3444                                   const uint64_t item_flags,
3445                                   struct rte_flow_error *error)
3446 {
3447         int ret = 0;
3448         uint64_t layer;
3449
3450         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3451         if (!ret) {
3452                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453                                  MLX5_FLOW_LAYER_INNER_L4 :
3454                                  MLX5_FLOW_LAYER_OUTER_L4;
3455                 if (!(item_flags & layer))
3456                         return rte_flow_error_set(error, EINVAL,
3457                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3458                                                   NULL, "no transport layer "
3459                                                   "in pattern");
3460         }
3461         return ret;
3462 }
3463
3464 /**
3465  * Validate the modify-header actions of increment/decrement
3466  * TCP Sequence-number.
3467  *
3468  * @param[in] action_flags
3469  *   Holds the actions detected until now.
3470  * @param[in] action
3471  *   Pointer to the modify action.
3472  * @param[in] item_flags
3473  *   Holds the items detected.
3474  * @param[out] error
3475  *   Pointer to error structure.
3476  *
3477  * @return
3478  *   0 on success, a negative errno value otherwise and rte_errno is set.
3479  */
3480 static int
3481 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3482                                        const struct rte_flow_action *action,
3483                                        const uint64_t item_flags,
3484                                        struct rte_flow_error *error)
3485 {
3486         int ret = 0;
3487         uint64_t layer;
3488
3489         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3490         if (!ret) {
3491                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3492                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3493                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3494                 if (!(item_flags & layer))
3495                         return rte_flow_error_set(error, EINVAL,
3496                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3497                                                   NULL, "no TCP item in"
3498                                                   " pattern");
3499                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3500                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3501                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3502                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3503                         return rte_flow_error_set(error, EINVAL,
3504                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3505                                                   NULL,
3506                                                   "cannot decrease and increase"
3507                                                   " TCP sequence number"
3508                                                   " at the same time");
3509         }
3510         return ret;
3511 }
3512
3513 /**
3514  * Validate the modify-header actions of increment/decrement
3515  * TCP Acknowledgment number.
3516  *
3517  * @param[in] action_flags
3518  *   Holds the actions detected until now.
3519  * @param[in] action
3520  *   Pointer to the modify action.
3521  * @param[in] item_flags
3522  *   Holds the items detected.
3523  * @param[out] error
3524  *   Pointer to error structure.
3525  *
3526  * @return
3527  *   0 on success, a negative errno value otherwise and rte_errno is set.
3528  */
3529 static int
3530 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3531                                        const struct rte_flow_action *action,
3532                                        const uint64_t item_flags,
3533                                        struct rte_flow_error *error)
3534 {
3535         int ret = 0;
3536         uint64_t layer;
3537
3538         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3539         if (!ret) {
3540                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3541                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3542                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3543                 if (!(item_flags & layer))
3544                         return rte_flow_error_set(error, EINVAL,
3545                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3546                                                   NULL, "no TCP item in"
3547                                                   " pattern");
3548                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3549                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3550                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3551                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3552                         return rte_flow_error_set(error, EINVAL,
3553                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3554                                                   NULL,
3555                                                   "cannot decrease and increase"
3556                                                   " TCP acknowledgment number"
3557                                                   " at the same time");
3558         }
3559         return ret;
3560 }
3561
3562 /**
3563  * Validate the modify-header TTL actions.
3564  *
3565  * @param[in] action_flags
3566  *   Holds the actions detected until now.
3567  * @param[in] action
3568  *   Pointer to the modify action.
3569  * @param[in] item_flags
3570  *   Holds the items detected.
3571  * @param[out] error
3572  *   Pointer to error structure.
3573  *
3574  * @return
3575  *   0 on success, a negative errno value otherwise and rte_errno is set.
3576  */
3577 static int
3578 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3579                                    const struct rte_flow_action *action,
3580                                    const uint64_t item_flags,
3581                                    struct rte_flow_error *error)
3582 {
3583         int ret = 0;
3584         uint64_t layer;
3585
3586         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3587         if (!ret) {
3588                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3589                                  MLX5_FLOW_LAYER_INNER_L3 :
3590                                  MLX5_FLOW_LAYER_OUTER_L3;
3591                 if (!(item_flags & layer))
3592                         return rte_flow_error_set(error, EINVAL,
3593                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3594                                                   NULL,
3595                                                   "no IP protocol in pattern");
3596         }
3597         return ret;
3598 }
3599
3600 /**
3601  * Validate jump action.
3602  *
3603  * @param[in] action
3604  *   Pointer to the jump action.
3605  * @param[in] action_flags
3606  *   Holds the actions detected until now.
3607  * @param[in] attributes
3608  *   Pointer to flow attributes
3609  * @param[in] external
3610  *   Action belongs to flow rule created by request external to PMD.
3611  * @param[out] error
3612  *   Pointer to error structure.
3613  *
3614  * @return
3615  *   0 on success, a negative errno value otherwise and rte_errno is set.
3616  */
3617 static int
3618 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3619                              uint64_t action_flags,
3620                              const struct rte_flow_attr *attributes,
3621                              bool external, struct rte_flow_error *error)
3622 {
3623         uint32_t target_group, table;
3624         int ret = 0;
3625
3626         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3627                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3628                 return rte_flow_error_set(error, EINVAL,
3629                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3630                                           "can't have 2 fate actions in"
3631                                           " same flow");
3632         if (action_flags & MLX5_FLOW_ACTION_METER)
3633                 return rte_flow_error_set(error, ENOTSUP,
3634                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3635                                           "jump with meter not support");
3636         if (!action->conf)
3637                 return rte_flow_error_set(error, EINVAL,
3638                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3639                                           NULL, "action configuration not set");
3640         target_group =
3641                 ((const struct rte_flow_action_jump *)action->conf)->group;
3642         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3643                                        true, &table, error);
3644         if (ret)
3645                 return ret;
3646         if (attributes->group == target_group)
3647                 return rte_flow_error_set(error, EINVAL,
3648                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3649                                           "target group must be other than"
3650                                           " the current flow group");
3651         return 0;
3652 }
3653
3654 /*
3655  * Validate the port_id action.
3656  *
3657  * @param[in] dev
3658  *   Pointer to rte_eth_dev structure.
3659  * @param[in] action_flags
3660  *   Bit-fields that holds the actions detected until now.
3661  * @param[in] action
3662  *   Port_id RTE action structure.
3663  * @param[in] attr
3664  *   Attributes of flow that includes this action.
3665  * @param[out] error
3666  *   Pointer to error structure.
3667  *
3668  * @return
3669  *   0 on success, a negative errno value otherwise and rte_errno is set.
3670  */
3671 static int
3672 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3673                                 uint64_t action_flags,
3674                                 const struct rte_flow_action *action,
3675                                 const struct rte_flow_attr *attr,
3676                                 struct rte_flow_error *error)
3677 {
3678         const struct rte_flow_action_port_id *port_id;
3679         struct mlx5_priv *act_priv;
3680         struct mlx5_priv *dev_priv;
3681         uint16_t port;
3682
3683         if (!attr->transfer)
3684                 return rte_flow_error_set(error, ENOTSUP,
3685                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3686                                           NULL,
3687                                           "port id action is valid in transfer"
3688                                           " mode only");
3689         if (!action || !action->conf)
3690                 return rte_flow_error_set(error, ENOTSUP,
3691                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3692                                           NULL,
3693                                           "port id action parameters must be"
3694                                           " specified");
3695         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3696                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3697                 return rte_flow_error_set(error, EINVAL,
3698                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3699                                           "can have only one fate actions in"
3700                                           " a flow");
3701         dev_priv = mlx5_dev_to_eswitch_info(dev);
3702         if (!dev_priv)
3703                 return rte_flow_error_set(error, rte_errno,
3704                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3705                                           NULL,
3706                                           "failed to obtain E-Switch info");
3707         port_id = action->conf;
3708         port = port_id->original ? dev->data->port_id : port_id->id;
3709         act_priv = mlx5_port_to_eswitch_info(port, false);
3710         if (!act_priv)
3711                 return rte_flow_error_set
3712                                 (error, rte_errno,
3713                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3714                                  "failed to obtain E-Switch port id for port");
3715         if (act_priv->domain_id != dev_priv->domain_id)
3716                 return rte_flow_error_set
3717                                 (error, EINVAL,
3718                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3719                                  "port does not belong to"
3720                                  " E-Switch being configured");
3721         return 0;
3722 }
3723
3724 /**
3725  * Get the maximum number of modify header actions.
3726  *
3727  * @param dev
3728  *   Pointer to rte_eth_dev structure.
3729  * @param flags
3730  *   Flags bits to check if root level.
3731  *
3732  * @return
3733  *   Max number of modify header actions device can support.
3734  */
3735 static inline unsigned int
3736 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3737                               uint64_t flags)
3738 {
3739         /*
3740          * There's no way to directly query the max capacity from FW.
3741          * The maximal value on root table should be assumed to be supported.
3742          */
3743         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3744                 return MLX5_MAX_MODIFY_NUM;
3745         else
3746                 return MLX5_ROOT_TBL_MODIFY_NUM;
3747 }
3748
3749 /**
3750  * Validate the meter action.
3751  *
3752  * @param[in] dev
3753  *   Pointer to rte_eth_dev structure.
3754  * @param[in] action_flags
3755  *   Bit-fields that holds the actions detected until now.
3756  * @param[in] action
3757  *   Pointer to the meter action.
3758  * @param[in] attr
3759  *   Attributes of flow that includes this action.
3760  * @param[out] error
3761  *   Pointer to error structure.
3762  *
3763  * @return
3764  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3765  */
3766 static int
3767 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3768                                 uint64_t action_flags,
3769                                 const struct rte_flow_action *action,
3770                                 const struct rte_flow_attr *attr,
3771                                 struct rte_flow_error *error)
3772 {
3773         struct mlx5_priv *priv = dev->data->dev_private;
3774         const struct rte_flow_action_meter *am = action->conf;
3775         struct mlx5_flow_meter *fm;
3776
3777         if (!am)
3778                 return rte_flow_error_set(error, EINVAL,
3779                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3780                                           "meter action conf is NULL");
3781
3782         if (action_flags & MLX5_FLOW_ACTION_METER)
3783                 return rte_flow_error_set(error, ENOTSUP,
3784                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3785                                           "meter chaining not support");
3786         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3787                 return rte_flow_error_set(error, ENOTSUP,
3788                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3789                                           "meter with jump not support");
3790         if (!priv->mtr_en)
3791                 return rte_flow_error_set(error, ENOTSUP,
3792                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3793                                           NULL,
3794                                           "meter action not supported");
3795         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3796         if (!fm)
3797                 return rte_flow_error_set(error, EINVAL,
3798                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3799                                           "Meter not found");
3800         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3801               (!fm->ingress && !attr->ingress && attr->egress) ||
3802               (!fm->egress && !attr->egress && attr->ingress))))
3803                 return rte_flow_error_set(error, EINVAL,
3804                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3805                                           "Flow attributes are either invalid "
3806                                           "or have a conflict with current "
3807                                           "meter attributes");
3808         return 0;
3809 }
3810
3811 /**
3812  * Validate the age action.
3813  *
3814  * @param[in] action_flags
3815  *   Holds the actions detected until now.
3816  * @param[in] action
3817  *   Pointer to the age action.
3818  * @param[in] dev
3819  *   Pointer to the Ethernet device structure.
3820  * @param[out] error
3821  *   Pointer to error structure.
3822  *
3823  * @return
3824  *   0 on success, a negative errno value otherwise and rte_errno is set.
3825  */
3826 static int
3827 flow_dv_validate_action_age(uint64_t action_flags,
3828                             const struct rte_flow_action *action,
3829                             struct rte_eth_dev *dev,
3830                             struct rte_flow_error *error)
3831 {
3832         struct mlx5_priv *priv = dev->data->dev_private;
3833         const struct rte_flow_action_age *age = action->conf;
3834
3835         if (!priv->config.devx || priv->counter_fallback)
3836                 return rte_flow_error_set(error, ENOTSUP,
3837                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3838                                           NULL,
3839                                           "age action not supported");
3840         if (!(action->conf))
3841                 return rte_flow_error_set(error, EINVAL,
3842                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3843                                           "configuration cannot be null");
3844         if (age->timeout >= UINT16_MAX / 2 / 10)
3845                 return rte_flow_error_set(error, ENOTSUP,
3846                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3847                                           "Max age time: 3275 seconds");
3848         if (action_flags & MLX5_FLOW_ACTION_AGE)
3849                 return rte_flow_error_set(error, EINVAL,
3850                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3851                                           "Duplicate age ctions set");
3852         return 0;
3853 }
3854
3855 /**
3856  * Validate the modify-header IPv4 DSCP actions.
3857  *
3858  * @param[in] action_flags
3859  *   Holds the actions detected until now.
3860  * @param[in] action
3861  *   Pointer to the modify action.
3862  * @param[in] item_flags
3863  *   Holds the items detected.
3864  * @param[out] error
3865  *   Pointer to error structure.
3866  *
3867  * @return
3868  *   0 on success, a negative errno value otherwise and rte_errno is set.
3869  */
3870 static int
3871 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3872                                          const struct rte_flow_action *action,
3873                                          const uint64_t item_flags,
3874                                          struct rte_flow_error *error)
3875 {
3876         int ret = 0;
3877
3878         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3879         if (!ret) {
3880                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3881                         return rte_flow_error_set(error, EINVAL,
3882                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3883                                                   NULL,
3884                                                   "no ipv4 item in pattern");
3885         }
3886         return ret;
3887 }
3888
3889 /**
3890  * Validate the modify-header IPv6 DSCP actions.
3891  *
3892  * @param[in] action_flags
3893  *   Holds the actions detected until now.
3894  * @param[in] action
3895  *   Pointer to the modify action.
3896  * @param[in] item_flags
3897  *   Holds the items detected.
3898  * @param[out] error
3899  *   Pointer to error structure.
3900  *
3901  * @return
3902  *   0 on success, a negative errno value otherwise and rte_errno is set.
3903  */
3904 static int
3905 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3906                                          const struct rte_flow_action *action,
3907                                          const uint64_t item_flags,
3908                                          struct rte_flow_error *error)
3909 {
3910         int ret = 0;
3911
3912         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3913         if (!ret) {
3914                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3915                         return rte_flow_error_set(error, EINVAL,
3916                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3917                                                   NULL,
3918                                                   "no ipv6 item in pattern");
3919         }
3920         return ret;
3921 }
3922
3923 /**
3924  * Find existing modify-header resource or create and register a new one.
3925  *
3926  * @param dev[in, out]
3927  *   Pointer to rte_eth_dev structure.
3928  * @param[in, out] resource
3929  *   Pointer to modify-header resource.
3930  * @parm[in, out] dev_flow
3931  *   Pointer to the dev_flow.
3932  * @param[out] error
3933  *   pointer to error structure.
3934  *
3935  * @return
3936  *   0 on success otherwise -errno and errno is set.
3937  */
3938 static int
3939 flow_dv_modify_hdr_resource_register
3940                         (struct rte_eth_dev *dev,
3941                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3942                          struct mlx5_flow *dev_flow,
3943                          struct rte_flow_error *error)
3944 {
3945         struct mlx5_priv *priv = dev->data->dev_private;
3946         struct mlx5_ibv_shared *sh = priv->sh;
3947         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3948         struct mlx5dv_dr_domain *ns;
3949         uint32_t actions_len;
3950
3951         resource->flags = dev_flow->dv.group ? 0 :
3952                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3953         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3954                                     resource->flags))
3955                 return rte_flow_error_set(error, EOVERFLOW,
3956                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3957                                           "too many modify header items");
3958         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3959                 ns = sh->fdb_domain;
3960         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3961                 ns = sh->tx_domain;
3962         else
3963                 ns = sh->rx_domain;
3964         /* Lookup a matching resource from cache. */
3965         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3966         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3967                 if (resource->ft_type == cache_resource->ft_type &&
3968                     resource->actions_num == cache_resource->actions_num &&
3969                     resource->flags == cache_resource->flags &&
3970                     !memcmp((const void *)resource->actions,
3971                             (const void *)cache_resource->actions,
3972                             actions_len)) {
3973                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3974                                 (void *)cache_resource,
3975                                 rte_atomic32_read(&cache_resource->refcnt));
3976                         rte_atomic32_inc(&cache_resource->refcnt);
3977                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3978                         return 0;
3979                 }
3980         }
3981         /* Register new modify-header resource. */
3982         cache_resource = rte_calloc(__func__, 1,
3983                                     sizeof(*cache_resource) + actions_len, 0);
3984         if (!cache_resource)
3985                 return rte_flow_error_set(error, ENOMEM,
3986                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3987                                           "cannot allocate resource memory");
3988         *cache_resource = *resource;
3989         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3990         cache_resource->verbs_action =
3991                 mlx5_glue->dv_create_flow_action_modify_header
3992                                         (sh->ctx, cache_resource->ft_type, ns,
3993                                          cache_resource->flags, actions_len,
3994                                          (uint64_t *)cache_resource->actions);
3995         if (!cache_resource->verbs_action) {
3996                 rte_free(cache_resource);
3997                 return rte_flow_error_set(error, ENOMEM,
3998                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3999                                           NULL, "cannot create action");
4000         }
4001         rte_atomic32_init(&cache_resource->refcnt);
4002         rte_atomic32_inc(&cache_resource->refcnt);
4003         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4004         dev_flow->handle->dvh.modify_hdr = cache_resource;
4005         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4006                 (void *)cache_resource,
4007                 rte_atomic32_read(&cache_resource->refcnt));
4008         return 0;
4009 }
4010
4011 /**
4012  * Get DV flow counter by index.
4013  *
4014  * @param[in] dev
4015  *   Pointer to the Ethernet device structure.
4016  * @param[in] idx
4017  *   mlx5 flow counter index in the container.
4018  * @param[out] ppool
4019  *   mlx5 flow counter pool in the container,
4020  *
4021  * @return
4022  *   Pointer to the counter, NULL otherwise.
4023  */
4024 static struct mlx5_flow_counter *
4025 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4026                            uint32_t idx,
4027                            struct mlx5_flow_counter_pool **ppool)
4028 {
4029         struct mlx5_priv *priv = dev->data->dev_private;
4030         struct mlx5_pools_container *cont;
4031         struct mlx5_flow_counter_pool *pool;
4032         uint32_t batch = 0, age = 0;
4033
4034         idx--;
4035         age = MLX_CNT_IS_AGE(idx);
4036         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4037         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4038                 idx -= MLX5_CNT_BATCH_OFFSET;
4039                 batch = 1;
4040         }
4041         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4042         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4043         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4044         MLX5_ASSERT(pool);
4045         if (ppool)
4046                 *ppool = pool;
4047         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4048 }
4049
4050 /**
4051  * Get a pool by devx counter ID.
4052  *
4053  * @param[in] cont
4054  *   Pointer to the counter container.
4055  * @param[in] id
4056  *   The counter devx ID.
4057  *
4058  * @return
4059  *   The counter pool pointer if exists, NULL otherwise,
4060  */
4061 static struct mlx5_flow_counter_pool *
4062 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4063 {
4064         uint32_t i;
4065         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4066
4067         for (i = 0; i < n_valid; i++) {
4068                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4069                 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4070                            MLX5_COUNTERS_PER_POOL;
4071
4072                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
4073                         /*
4074                          * Move the pool to the head, as counter allocate
4075                          * always gets the first pool in the container.
4076                          */
4077                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
4078                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4079                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4080                         }
4081                         return pool;
4082                 }
4083         }
4084         return NULL;
4085 }
4086
4087 /**
4088  * Allocate a new memory for the counter values wrapped by all the needed
4089  * management.
4090  *
4091  * @param[in] dev
4092  *   Pointer to the Ethernet device structure.
4093  * @param[in] raws_n
4094  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4095  *
4096  * @return
4097  *   The new memory management pointer on success, otherwise NULL and rte_errno
4098  *   is set.
4099  */
4100 static struct mlx5_counter_stats_mem_mng *
4101 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4102 {
4103         struct mlx5_priv *priv = dev->data->dev_private;
4104         struct mlx5_ibv_shared *sh = priv->sh;
4105         struct mlx5_devx_mkey_attr mkey_attr;
4106         struct mlx5_counter_stats_mem_mng *mem_mng;
4107         volatile struct flow_counter_stats *raw_data;
4108         int size = (sizeof(struct flow_counter_stats) *
4109                         MLX5_COUNTERS_PER_POOL +
4110                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4111                         sizeof(struct mlx5_counter_stats_mem_mng);
4112         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4113         int i;
4114
4115         if (!mem) {
4116                 rte_errno = ENOMEM;
4117                 return NULL;
4118         }
4119         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4120         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4121         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4122                                                  IBV_ACCESS_LOCAL_WRITE);
4123         if (!mem_mng->umem) {
4124                 rte_errno = errno;
4125                 rte_free(mem);
4126                 return NULL;
4127         }
4128         mkey_attr.addr = (uintptr_t)mem;
4129         mkey_attr.size = size;
4130         mkey_attr.umem_id = mem_mng->umem->umem_id;
4131         mkey_attr.pd = sh->pdn;
4132         mkey_attr.log_entity_size = 0;
4133         mkey_attr.pg_access = 0;
4134         mkey_attr.klm_array = NULL;
4135         mkey_attr.klm_num = 0;
4136         if (priv->config.hca_attr.relaxed_ordering_write &&
4137                 priv->config.hca_attr.relaxed_ordering_read  &&
4138                 !haswell_broadwell_cpu)
4139                 mkey_attr.relaxed_ordering = 1;
4140         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4141         if (!mem_mng->dm) {
4142                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4143                 rte_errno = errno;
4144                 rte_free(mem);
4145                 return NULL;
4146         }
4147         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4148         raw_data = (volatile struct flow_counter_stats *)mem;
4149         for (i = 0; i < raws_n; ++i) {
4150                 mem_mng->raws[i].mem_mng = mem_mng;
4151                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4152         }
4153         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4154         return mem_mng;
4155 }
4156
4157 /**
4158  * Resize a counter container.
4159  *
4160  * @param[in] dev
4161  *   Pointer to the Ethernet device structure.
4162  * @param[in] batch
4163  *   Whether the pool is for counter that was allocated by batch command.
4164  * @param[in] age
4165  *   Whether the pool is for Aging counter.
4166  *
4167  * @return
4168  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4169  */
4170 static struct mlx5_pools_container *
4171 flow_dv_container_resize(struct rte_eth_dev *dev,
4172                                 uint32_t batch, uint32_t age)
4173 {
4174         struct mlx5_priv *priv = dev->data->dev_private;
4175         struct mlx5_pools_container *cont =
4176                         MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4177         struct mlx5_pools_container *new_cont =
4178                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0, age);
4179         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4180         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4181         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4182         int i;
4183
4184         /* Fallback mode has no background thread. Skip the check. */
4185         if (!priv->counter_fallback &&
4186             cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1, age)) {
4187                 /* The last resize still hasn't detected by the host thread. */
4188                 rte_errno = EAGAIN;
4189                 return NULL;
4190         }
4191         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4192         if (!new_cont->pools) {
4193                 rte_errno = ENOMEM;
4194                 return NULL;
4195         }
4196         if (cont->n)
4197                 memcpy(new_cont->pools, cont->pools, cont->n *
4198                        sizeof(struct mlx5_flow_counter_pool *));
4199         /*
4200          * Fallback mode query the counter directly, no background query
4201          * resources are needed.
4202          */
4203         if (!priv->counter_fallback) {
4204                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4205                         MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4206                 if (!mem_mng) {
4207                         rte_free(new_cont->pools);
4208                         return NULL;
4209                 }
4210                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4211                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4212                                          mem_mng->raws +
4213                                          MLX5_CNT_CONTAINER_RESIZE +
4214                                          i, next);
4215         } else {
4216                 /*
4217                  * Release the old container pools directly as no background
4218                  * thread helps that.
4219                  */
4220                 rte_free(cont->pools);
4221         }
4222         new_cont->n = resize;
4223         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4224         TAILQ_INIT(&new_cont->pool_list);
4225         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4226         new_cont->init_mem_mng = mem_mng;
4227         rte_cio_wmb();
4228          /* Flip the master container. */
4229         priv->sh->cmng.mhi[batch][age] ^= (uint8_t)1;
4230         return new_cont;
4231 }
4232
4233 /**
4234  * Query a devx flow counter.
4235  *
4236  * @param[in] dev
4237  *   Pointer to the Ethernet device structure.
4238  * @param[in] cnt
4239  *   Index to the flow counter.
4240  * @param[out] pkts
4241  *   The statistics value of packets.
4242  * @param[out] bytes
4243  *   The statistics value of bytes.
4244  *
4245  * @return
4246  *   0 on success, otherwise a negative errno value and rte_errno is set.
4247  */
4248 static inline int
4249 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4250                      uint64_t *bytes)
4251 {
4252         struct mlx5_priv *priv = dev->data->dev_private;
4253         struct mlx5_flow_counter_pool *pool = NULL;
4254         struct mlx5_flow_counter *cnt;
4255         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4256         int offset;
4257
4258         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4259         MLX5_ASSERT(pool);
4260         if (counter < MLX5_CNT_BATCH_OFFSET) {
4261                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4262                 if (priv->counter_fallback)
4263                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4264                                         0, pkts, bytes, 0, NULL, NULL, 0);
4265         }
4266
4267         rte_spinlock_lock(&pool->sl);
4268         /*
4269          * The single counters allocation may allocate smaller ID than the
4270          * current allocated in parallel to the host reading.
4271          * In this case the new counter values must be reported as 0.
4272          */
4273         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4274                 *pkts = 0;
4275                 *bytes = 0;
4276         } else {
4277                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4278                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4279                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4280         }
4281         rte_spinlock_unlock(&pool->sl);
4282         return 0;
4283 }
4284
4285 /**
4286  * Create and initialize a new counter pool.
4287  *
4288  * @param[in] dev
4289  *   Pointer to the Ethernet device structure.
4290  * @param[out] dcs
4291  *   The devX counter handle.
4292  * @param[in] batch
4293  *   Whether the pool is for counter that was allocated by batch command.
4294  * @param[in] age
4295  *   Whether the pool is for counter that was allocated for aging.
4296  * @param[in/out] cont_cur
4297  *   Pointer to the container pointer, it will be update in pool resize.
4298  *
4299  * @return
4300  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4301  */
4302 static struct mlx5_pools_container *
4303 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4304                     uint32_t batch, uint32_t age)
4305 {
4306         struct mlx5_priv *priv = dev->data->dev_private;
4307         struct mlx5_flow_counter_pool *pool;
4308         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4309                                                                0, age);
4310         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4311         uint32_t size = sizeof(*pool);
4312
4313         if (cont->n == n_valid) {
4314                 cont = flow_dv_container_resize(dev, batch, age);
4315                 if (!cont)
4316                         return NULL;
4317         }
4318         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4319         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4320         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4321         pool = rte_calloc(__func__, 1, size, 0);
4322         if (!pool) {
4323                 rte_errno = ENOMEM;
4324                 return NULL;
4325         }
4326         pool->min_dcs = dcs;
4327         if (!priv->counter_fallback)
4328                 pool->raw = cont->init_mem_mng->raws + n_valid %
4329                                                      MLX5_CNT_CONTAINER_RESIZE;
4330         pool->raw_hw = NULL;
4331         pool->type = 0;
4332         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4333         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4334         rte_spinlock_init(&pool->sl);
4335         /*
4336          * The generation of the new allocated counters in this pool is 0, 2 in
4337          * the pool generation makes all the counters valid for allocation.
4338          * The start and end query generation protect the counters be released
4339          * between the query and update gap period will not be reallocated
4340          * without the last query finished and stats updated to the memory.
4341          */
4342         rte_atomic64_set(&pool->start_query_gen, 0x2);
4343         /*
4344          * There's no background query thread for fallback mode, set the
4345          * end_query_gen to the maximum value since no need to wait for
4346          * statistics update.
4347          */
4348         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4349                          INT64_MAX : 0x2);
4350         TAILQ_INIT(&pool->counters);
4351         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4352         pool->index = n_valid;
4353         cont->pools[n_valid] = pool;
4354         /* Pool initialization must be updated before host thread access. */
4355         rte_cio_wmb();
4356         rte_atomic16_add(&cont->n_valid, 1);
4357         return cont;
4358 }
4359
4360 /**
4361  * Update the minimum dcs-id for aged or no-aged counter pool.
4362  *
4363  * @param[in] dev
4364  *   Pointer to the Ethernet device structure.
4365  * @param[in] pool
4366  *   Current counter pool.
4367  * @param[in] batch
4368  *   Whether the pool is for counter that was allocated by batch command.
4369  * @param[in] age
4370  *   Whether the counter is for aging.
4371  */
4372 static void
4373 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4374                         struct mlx5_flow_counter_pool *pool,
4375                         uint32_t batch, uint32_t age)
4376 {
4377         struct mlx5_priv *priv = dev->data->dev_private;
4378         struct mlx5_flow_counter_pool *other;
4379         struct mlx5_pools_container *cont;
4380
4381         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, (age ^ 0x1));
4382         other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4383         if (!other)
4384                 return;
4385         if (pool->min_dcs->id < other->min_dcs->id) {
4386                 rte_atomic64_set(&other->a64_dcs,
4387                         rte_atomic64_read(&pool->a64_dcs));
4388         } else {
4389                 rte_atomic64_set(&pool->a64_dcs,
4390                         rte_atomic64_read(&other->a64_dcs));
4391         }
4392 }
4393 /**
4394  * Prepare a new counter and/or a new counter pool.
4395  *
4396  * @param[in] dev
4397  *   Pointer to the Ethernet device structure.
4398  * @param[out] cnt_free
4399  *   Where to put the pointer of a new counter.
4400  * @param[in] batch
4401  *   Whether the pool is for counter that was allocated by batch command.
4402  * @param[in] age
4403  *   Whether the pool is for counter that was allocated for aging.
4404  *
4405  * @return
4406  *   The counter container pointer and @p cnt_free is set on success,
4407  *   NULL otherwise and rte_errno is set.
4408  */
4409 static struct mlx5_pools_container *
4410 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4411                              struct mlx5_flow_counter **cnt_free,
4412                              uint32_t batch, uint32_t age)
4413 {
4414         struct mlx5_priv *priv = dev->data->dev_private;
4415         struct mlx5_pools_container *cont;
4416         struct mlx5_flow_counter_pool *pool;
4417         struct mlx5_devx_obj *dcs = NULL;
4418         struct mlx5_flow_counter *cnt;
4419         uint32_t i;
4420
4421         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0, age);
4422         if (!batch) {
4423                 /* bulk_bitmap must be 0 for single counter allocation. */
4424                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4425                 if (!dcs)
4426                         return NULL;
4427                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4428                 if (!pool) {
4429                         cont = flow_dv_pool_create(dev, dcs, batch, age);
4430                         if (!cont) {
4431                                 mlx5_devx_cmd_destroy(dcs);
4432                                 return NULL;
4433                         }
4434                         pool = TAILQ_FIRST(&cont->pool_list);
4435                 } else if (dcs->id < pool->min_dcs->id) {
4436                         rte_atomic64_set(&pool->a64_dcs,
4437                                          (int64_t)(uintptr_t)dcs);
4438                 }
4439                 flow_dv_counter_update_min_dcs(dev,
4440                                                 pool, batch, age);
4441                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4442                 cnt = MLX5_POOL_GET_CNT(pool, i);
4443                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4444                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4445                 *cnt_free = cnt;
4446                 return cont;
4447         }
4448         /* bulk_bitmap is in 128 counters units. */
4449         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4450                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4451         if (!dcs) {
4452                 rte_errno = ENODATA;
4453                 return NULL;
4454         }
4455         cont = flow_dv_pool_create(dev, dcs, batch, age);
4456         if (!cont) {
4457                 mlx5_devx_cmd_destroy(dcs);
4458                 return NULL;
4459         }
4460         pool = TAILQ_FIRST(&cont->pool_list);
4461         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4462                 cnt = MLX5_POOL_GET_CNT(pool, i);
4463                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4464         }
4465         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4466         return cont;
4467 }
4468
4469 /**
4470  * Search for existed shared counter.
4471  *
4472  * @param[in] cont
4473  *   Pointer to the relevant counter pool container.
4474  * @param[in] id
4475  *   The shared counter ID to search.
4476  * @param[out] ppool
4477  *   mlx5 flow counter pool in the container,
4478  *
4479  * @return
4480  *   NULL if not existed, otherwise pointer to the shared extend counter.
4481  */
4482 static struct mlx5_flow_counter_ext *
4483 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4484                               struct mlx5_flow_counter_pool **ppool)
4485 {
4486         static struct mlx5_flow_counter_ext *cnt;
4487         struct mlx5_flow_counter_pool *pool;
4488         uint32_t i;
4489         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4490
4491         for (i = 0; i < n_valid; i++) {
4492                 pool = cont->pools[i];
4493                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4494                         cnt = MLX5_GET_POOL_CNT_EXT(pool, i);
4495                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4496                                 if (ppool)
4497                                         *ppool = cont->pools[i];
4498                                 return cnt;
4499                         }
4500                 }
4501         }
4502         return NULL;
4503 }
4504
4505 /**
4506  * Allocate a flow counter.
4507  *
4508  * @param[in] dev
4509  *   Pointer to the Ethernet device structure.
4510  * @param[in] shared
4511  *   Indicate if this counter is shared with other flows.
4512  * @param[in] id
4513  *   Counter identifier.
4514  * @param[in] group
4515  *   Counter flow group.
4516  * @param[in] age
4517  *   Whether the counter was allocated for aging.
4518  *
4519  * @return
4520  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4521  */
4522 static uint32_t
4523 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4524                       uint16_t group, uint32_t age)
4525 {
4526         struct mlx5_priv *priv = dev->data->dev_private;
4527         struct mlx5_flow_counter_pool *pool = NULL;
4528         struct mlx5_flow_counter *cnt_free = NULL;
4529         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4530         /*
4531          * Currently group 0 flow counter cannot be assigned to a flow if it is
4532          * not the first one in the batch counter allocation, so it is better
4533          * to allocate counters one by one for these flows in a separate
4534          * container.
4535          * A counter can be shared between different groups so need to take
4536          * shared counters from the single container.
4537          */
4538         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4539         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4540                                                                0, age);
4541         uint32_t cnt_idx;
4542
4543         if (!priv->config.devx) {
4544                 rte_errno = ENOTSUP;
4545                 return 0;
4546         }
4547         if (shared) {
4548                 cnt_ext = flow_dv_counter_shared_search(cont, id, &pool);
4549                 if (cnt_ext) {
4550                         if (cnt_ext->ref_cnt + 1 == 0) {
4551                                 rte_errno = E2BIG;
4552                                 return 0;
4553                         }
4554                         cnt_ext->ref_cnt++;
4555                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4556                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4557                                   + 1;
4558                         return cnt_idx;
4559                 }
4560         }
4561         /* Pools which has a free counters are in the start. */
4562         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4563                 /*
4564                  * The free counter reset values must be updated between the
4565                  * counter release to the counter allocation, so, at least one
4566                  * query must be done in this time. ensure it by saving the
4567                  * query generation in the release time.
4568                  * The free list is sorted according to the generation - so if
4569                  * the first one is not updated, all the others are not
4570                  * updated too.
4571                  */
4572                 cnt_free = TAILQ_FIRST(&pool->counters);
4573                 if (cnt_free && cnt_free->query_gen <
4574                     rte_atomic64_read(&pool->end_query_gen))
4575                         break;
4576                 cnt_free = NULL;
4577         }
4578         if (!cnt_free) {
4579                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4580                 if (!cont)
4581                         return 0;
4582                 pool = TAILQ_FIRST(&cont->pool_list);
4583         }
4584         if (!batch)
4585                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4586         /* Create a DV counter action only in the first time usage. */
4587         if (!cnt_free->action) {
4588                 uint16_t offset;
4589                 struct mlx5_devx_obj *dcs;
4590
4591                 if (batch) {
4592                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4593                         dcs = pool->min_dcs;
4594                 } else {
4595                         offset = 0;
4596                         dcs = cnt_ext->dcs;
4597                 }
4598                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4599                                         (dcs->obj, offset);
4600                 if (!cnt_free->action) {
4601                         rte_errno = errno;
4602                         return 0;
4603                 }
4604         }
4605         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4606                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4607         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4608         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4609         /* Update the counter reset values. */
4610         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4611                                  &cnt_free->bytes))
4612                 return 0;
4613         if (cnt_ext) {
4614                 cnt_ext->shared = shared;
4615                 cnt_ext->ref_cnt = 1;
4616                 cnt_ext->id = id;
4617         }
4618         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4619                 /* Start the asynchronous batch query by the host thread. */
4620                 mlx5_set_query_alarm(priv->sh);
4621         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4622         if (TAILQ_EMPTY(&pool->counters)) {
4623                 /* Move the pool to the end of the container pool list. */
4624                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4625                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4626         }
4627         return cnt_idx;
4628 }
4629
4630 /**
4631  * Get age param from counter index.
4632  *
4633  * @param[in] dev
4634  *   Pointer to the Ethernet device structure.
4635  * @param[in] counter
4636  *   Index to the counter handler.
4637  *
4638  * @return
4639  *   The aging parameter specified for the counter index.
4640  */
4641 static struct mlx5_age_param*
4642 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4643                                 uint32_t counter)
4644 {
4645         struct mlx5_flow_counter *cnt;
4646         struct mlx5_flow_counter_pool *pool = NULL;
4647
4648         flow_dv_counter_get_by_idx(dev, counter, &pool);
4649         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4650         cnt = MLX5_POOL_GET_CNT(pool, counter);
4651         return MLX5_CNT_TO_AGE(cnt);
4652 }
4653
4654 /**
4655  * Remove a flow counter from aged counter list.
4656  *
4657  * @param[in] dev
4658  *   Pointer to the Ethernet device structure.
4659  * @param[in] counter
4660  *   Index to the counter handler.
4661  * @param[in] cnt
4662  *   Pointer to the counter handler.
4663  */
4664 static void
4665 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4666                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4667 {
4668         struct mlx5_age_info *age_info;
4669         struct mlx5_age_param *age_param;
4670         struct mlx5_priv *priv = dev->data->dev_private;
4671
4672         age_info = GET_PORT_AGE_INFO(priv);
4673         age_param = flow_dv_counter_idx_get_age(dev, counter);
4674         if (rte_atomic16_cmpset((volatile uint16_t *)
4675                         &age_param->state,
4676                         AGE_CANDIDATE, AGE_FREE)
4677                         != AGE_CANDIDATE) {
4678                 /**
4679                  * We need the lock even it is age timeout,
4680                  * since counter may still in process.
4681                  */
4682                 rte_spinlock_lock(&age_info->aged_sl);
4683                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4684                 rte_spinlock_unlock(&age_info->aged_sl);
4685         }
4686         rte_atomic16_set(&age_param->state, AGE_FREE);
4687 }
4688 /**
4689  * Release a flow counter.
4690  *
4691  * @param[in] dev
4692  *   Pointer to the Ethernet device structure.
4693  * @param[in] counter
4694  *   Index to the counter handler.
4695  */
4696 static void
4697 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4698 {
4699         struct mlx5_flow_counter_pool *pool = NULL;
4700         struct mlx5_flow_counter *cnt;
4701         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4702
4703         if (!counter)
4704                 return;
4705         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4706         MLX5_ASSERT(pool);
4707         if (counter < MLX5_CNT_BATCH_OFFSET) {
4708                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4709                 if (cnt_ext && --cnt_ext->ref_cnt)
4710                         return;
4711         }
4712         if (IS_AGE_POOL(pool))
4713                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4714         /* Put the counter in the end - the last updated one. */
4715         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4716         /*
4717          * Counters released between query trigger and handler need
4718          * to wait the next round of query. Since the packets arrive
4719          * in the gap period will not be taken into account to the
4720          * old counter.
4721          */
4722         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4723 }
4724
4725 /**
4726  * Verify the @p attributes will be correctly understood by the NIC and store
4727  * them in the @p flow if everything is correct.
4728  *
4729  * @param[in] dev
4730  *   Pointer to dev struct.
4731  * @param[in] attributes
4732  *   Pointer to flow attributes
4733  * @param[in] external
4734  *   This flow rule is created by request external to PMD.
4735  * @param[out] error
4736  *   Pointer to error structure.
4737  *
4738  * @return
4739  *   - 0 on success and non root table.
4740  *   - 1 on success and root table.
4741  *   - a negative errno value otherwise and rte_errno is set.
4742  */
4743 static int
4744 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4745                             const struct rte_flow_attr *attributes,
4746                             bool external __rte_unused,
4747                             struct rte_flow_error *error)
4748 {
4749         struct mlx5_priv *priv = dev->data->dev_private;
4750         uint32_t priority_max = priv->config.flow_prio - 1;
4751         int ret = 0;
4752
4753 #ifndef HAVE_MLX5DV_DR
4754         if (attributes->group)
4755                 return rte_flow_error_set(error, ENOTSUP,
4756                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4757                                           NULL,
4758                                           "groups are not supported");
4759 #else
4760         uint32_t table = 0;
4761
4762         ret = mlx5_flow_group_to_table(attributes, external,
4763                                        attributes->group, !!priv->fdb_def_rule,
4764                                        &table, error);
4765         if (ret)
4766                 return ret;
4767         if (!table)
4768                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4769 #endif
4770         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4771             attributes->priority >= priority_max)
4772                 return rte_flow_error_set(error, ENOTSUP,
4773                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4774                                           NULL,
4775                                           "priority out of range");
4776         if (attributes->transfer) {
4777                 if (!priv->config.dv_esw_en)
4778                         return rte_flow_error_set
4779                                 (error, ENOTSUP,
4780                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4781                                  "E-Switch dr is not supported");
4782                 if (!(priv->representor || priv->master))
4783                         return rte_flow_error_set
4784                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4785                                  NULL, "E-Switch configuration can only be"
4786                                  " done by a master or a representor device");
4787                 if (attributes->egress)
4788                         return rte_flow_error_set
4789                                 (error, ENOTSUP,
4790                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4791                                  "egress is not supported");
4792         }
4793         if (!(attributes->egress ^ attributes->ingress))
4794                 return rte_flow_error_set(error, ENOTSUP,
4795                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4796                                           "must specify exactly one of "
4797                                           "ingress or egress");
4798         return ret;
4799 }
4800
4801 /**
4802  * Internal validation function. For validating both actions and items.
4803  *
4804  * @param[in] dev
4805  *   Pointer to the rte_eth_dev structure.
4806  * @param[in] attr
4807  *   Pointer to the flow attributes.
4808  * @param[in] items
4809  *   Pointer to the list of items.
4810  * @param[in] actions
4811  *   Pointer to the list of actions.
4812  * @param[in] external
4813  *   This flow rule is created by request external to PMD.
4814  * @param[in] hairpin
4815  *   Number of hairpin TX actions, 0 means classic flow.
4816  * @param[out] error
4817  *   Pointer to the error structure.
4818  *
4819  * @return
4820  *   0 on success, a negative errno value otherwise and rte_errno is set.
4821  */
4822 static int
4823 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4824                  const struct rte_flow_item items[],
4825                  const struct rte_flow_action actions[],
4826                  bool external, int hairpin, struct rte_flow_error *error)
4827 {
4828         int ret;
4829         uint64_t action_flags = 0;
4830         uint64_t item_flags = 0;
4831         uint64_t last_item = 0;
4832         uint8_t next_protocol = 0xff;
4833         uint16_t ether_type = 0;
4834         int actions_n = 0;
4835         uint8_t item_ipv6_proto = 0;
4836         const struct rte_flow_item *gre_item = NULL;
4837         const struct rte_flow_action_raw_decap *decap;
4838         const struct rte_flow_action_raw_encap *encap;
4839         const struct rte_flow_action_rss *rss;
4840         const struct rte_flow_item_tcp nic_tcp_mask = {
4841                 .hdr = {
4842                         .tcp_flags = 0xFF,
4843                         .src_port = RTE_BE16(UINT16_MAX),
4844                         .dst_port = RTE_BE16(UINT16_MAX),
4845                 }
4846         };
4847         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4848                 .hdr = {
4849                         .src_addr = RTE_BE32(0xffffffff),
4850                         .dst_addr = RTE_BE32(0xffffffff),
4851                         .type_of_service = 0xff,
4852                         .next_proto_id = 0xff,
4853                         .time_to_live = 0xff,
4854                 },
4855         };
4856         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4857                 .hdr = {
4858                         .src_addr =
4859                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4860                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4861                         .dst_addr =
4862                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4863                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4864                         .vtc_flow = RTE_BE32(0xffffffff),
4865                         .proto = 0xff,
4866                         .hop_limits = 0xff,
4867                 },
4868         };
4869         struct mlx5_priv *priv = dev->data->dev_private;
4870         struct mlx5_dev_config *dev_conf = &priv->config;
4871         uint16_t queue_index = 0xFFFF;
4872         const struct rte_flow_item_vlan *vlan_m = NULL;
4873         int16_t rw_act_num = 0;
4874         uint64_t is_root;
4875
4876         if (items == NULL)
4877                 return -1;
4878         ret = flow_dv_validate_attributes(dev, attr, external, error);
4879         if (ret < 0)
4880                 return ret;
4881         is_root = (uint64_t)ret;
4882         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4883                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4884                 int type = items->type;
4885
4886                 switch (type) {
4887                 case RTE_FLOW_ITEM_TYPE_VOID:
4888                         break;
4889                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4890                         ret = flow_dv_validate_item_port_id
4891                                         (dev, items, attr, item_flags, error);
4892                         if (ret < 0)
4893                                 return ret;
4894                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4895                         break;
4896                 case RTE_FLOW_ITEM_TYPE_ETH:
4897                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4898                                                           error);
4899                         if (ret < 0)
4900                                 return ret;
4901                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4902                                              MLX5_FLOW_LAYER_OUTER_L2;
4903                         if (items->mask != NULL && items->spec != NULL) {
4904                                 ether_type =
4905                                         ((const struct rte_flow_item_eth *)
4906                                          items->spec)->type;
4907                                 ether_type &=
4908                                         ((const struct rte_flow_item_eth *)
4909                                          items->mask)->type;
4910                                 ether_type = rte_be_to_cpu_16(ether_type);
4911                         } else {
4912                                 ether_type = 0;
4913                         }
4914                         break;
4915                 case RTE_FLOW_ITEM_TYPE_VLAN:
4916                         ret = flow_dv_validate_item_vlan(items, item_flags,
4917                                                          dev, error);
4918                         if (ret < 0)
4919                                 return ret;
4920                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4921                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4922                         if (items->mask != NULL && items->spec != NULL) {
4923                                 ether_type =
4924                                         ((const struct rte_flow_item_vlan *)
4925                                          items->spec)->inner_type;
4926                                 ether_type &=
4927                                         ((const struct rte_flow_item_vlan *)
4928                                          items->mask)->inner_type;
4929                                 ether_type = rte_be_to_cpu_16(ether_type);
4930                         } else {
4931                                 ether_type = 0;
4932                         }
4933                         /* Store outer VLAN mask for of_push_vlan action. */
4934                         if (!tunnel)
4935                                 vlan_m = items->mask;
4936                         break;
4937                 case RTE_FLOW_ITEM_TYPE_IPV4:
4938                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4939                                                   &item_flags, &tunnel);
4940                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4941                                                            last_item,
4942                                                            ether_type,
4943                                                            &nic_ipv4_mask,
4944                                                            error);
4945                         if (ret < 0)
4946                                 return ret;
4947                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4948                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4949                         if (items->mask != NULL &&
4950                             ((const struct rte_flow_item_ipv4 *)
4951                              items->mask)->hdr.next_proto_id) {
4952                                 next_protocol =
4953                                         ((const struct rte_flow_item_ipv4 *)
4954                                          (items->spec))->hdr.next_proto_id;
4955                                 next_protocol &=
4956                                         ((const struct rte_flow_item_ipv4 *)
4957                                          (items->mask))->hdr.next_proto_id;
4958                         } else {
4959                                 /* Reset for inner layer. */
4960                                 next_protocol = 0xff;
4961                         }
4962                         break;
4963                 case RTE_FLOW_ITEM_TYPE_IPV6:
4964                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4965                                                   &item_flags, &tunnel);
4966                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4967                                                            last_item,
4968                                                            ether_type,
4969                                                            &nic_ipv6_mask,
4970                                                            error);
4971                         if (ret < 0)
4972                                 return ret;
4973                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4974                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4975                         if (items->mask != NULL &&
4976                             ((const struct rte_flow_item_ipv6 *)
4977                              items->mask)->hdr.proto) {
4978                                 item_ipv6_proto =
4979                                         ((const struct rte_flow_item_ipv6 *)
4980                                          items->spec)->hdr.proto;
4981                                 next_protocol =
4982                                         ((const struct rte_flow_item_ipv6 *)
4983                                          items->spec)->hdr.proto;
4984                                 next_protocol &=
4985                                         ((const struct rte_flow_item_ipv6 *)
4986                                          items->mask)->hdr.proto;
4987                         } else {
4988                                 /* Reset for inner layer. */
4989                                 next_protocol = 0xff;
4990                         }
4991                         break;
4992                 case RTE_FLOW_ITEM_TYPE_TCP:
4993                         ret = mlx5_flow_validate_item_tcp
4994                                                 (items, item_flags,
4995                                                  next_protocol,
4996                                                  &nic_tcp_mask,
4997                                                  error);
4998                         if (ret < 0)
4999                                 return ret;
5000                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5001                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5002                         break;
5003                 case RTE_FLOW_ITEM_TYPE_UDP:
5004                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5005                                                           next_protocol,
5006                                                           error);
5007                         if (ret < 0)
5008                                 return ret;
5009                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5010                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5011                         break;
5012                 case RTE_FLOW_ITEM_TYPE_GRE:
5013                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5014                                                           next_protocol, error);
5015                         if (ret < 0)
5016                                 return ret;
5017                         gre_item = items;
5018                         last_item = MLX5_FLOW_LAYER_GRE;
5019                         break;
5020                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5021                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5022                                                             next_protocol,
5023                                                             error);
5024                         if (ret < 0)
5025                                 return ret;
5026                         last_item = MLX5_FLOW_LAYER_NVGRE;
5027                         break;
5028                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5029                         ret = mlx5_flow_validate_item_gre_key
5030                                 (items, item_flags, gre_item, error);
5031                         if (ret < 0)
5032                                 return ret;
5033                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5034                         break;
5035                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5036                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5037                                                             error);
5038                         if (ret < 0)
5039                                 return ret;
5040                         last_item = MLX5_FLOW_LAYER_VXLAN;
5041                         break;
5042                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5043                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5044                                                                 item_flags, dev,
5045                                                                 error);
5046                         if (ret < 0)
5047                                 return ret;
5048                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5049                         break;
5050                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5051                         ret = mlx5_flow_validate_item_geneve(items,
5052                                                              item_flags, dev,
5053                                                              error);
5054                         if (ret < 0)
5055                                 return ret;
5056                         last_item = MLX5_FLOW_LAYER_GENEVE;
5057                         break;
5058                 case RTE_FLOW_ITEM_TYPE_MPLS:
5059                         ret = mlx5_flow_validate_item_mpls(dev, items,
5060                                                            item_flags,
5061                                                            last_item, error);
5062                         if (ret < 0)
5063                                 return ret;
5064                         last_item = MLX5_FLOW_LAYER_MPLS;
5065                         break;
5066
5067                 case RTE_FLOW_ITEM_TYPE_MARK:
5068                         ret = flow_dv_validate_item_mark(dev, items, attr,
5069                                                          error);
5070                         if (ret < 0)
5071                                 return ret;
5072                         last_item = MLX5_FLOW_ITEM_MARK;
5073                         break;
5074                 case RTE_FLOW_ITEM_TYPE_META:
5075                         ret = flow_dv_validate_item_meta(dev, items, attr,
5076                                                          error);
5077                         if (ret < 0)
5078                                 return ret;
5079                         last_item = MLX5_FLOW_ITEM_METADATA;
5080                         break;
5081                 case RTE_FLOW_ITEM_TYPE_ICMP:
5082                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5083                                                            next_protocol,
5084                                                            error);
5085                         if (ret < 0)
5086                                 return ret;
5087                         last_item = MLX5_FLOW_LAYER_ICMP;
5088                         break;
5089                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5090                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5091                                                             next_protocol,
5092                                                             error);
5093                         if (ret < 0)
5094                                 return ret;
5095                         item_ipv6_proto = IPPROTO_ICMPV6;
5096                         last_item = MLX5_FLOW_LAYER_ICMP6;
5097                         break;
5098                 case RTE_FLOW_ITEM_TYPE_TAG:
5099                         ret = flow_dv_validate_item_tag(dev, items,
5100                                                         attr, error);
5101                         if (ret < 0)
5102                                 return ret;
5103                         last_item = MLX5_FLOW_ITEM_TAG;
5104                         break;
5105                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5106                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5107                         break;
5108                 case RTE_FLOW_ITEM_TYPE_GTP:
5109                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5110                                                         error);
5111                         if (ret < 0)
5112                                 return ret;
5113                         last_item = MLX5_FLOW_LAYER_GTP;
5114                         break;
5115                 default:
5116                         return rte_flow_error_set(error, ENOTSUP,
5117                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5118                                                   NULL, "item not supported");
5119                 }
5120                 item_flags |= last_item;
5121         }
5122         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5123                 int type = actions->type;
5124                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5125                         return rte_flow_error_set(error, ENOTSUP,
5126                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5127                                                   actions, "too many actions");
5128                 switch (type) {
5129                 case RTE_FLOW_ACTION_TYPE_VOID:
5130                         break;
5131                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5132                         ret = flow_dv_validate_action_port_id(dev,
5133                                                               action_flags,
5134                                                               actions,
5135                                                               attr,
5136                                                               error);
5137                         if (ret)
5138                                 return ret;
5139                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5140                         ++actions_n;
5141                         break;
5142                 case RTE_FLOW_ACTION_TYPE_FLAG:
5143                         ret = flow_dv_validate_action_flag(dev, action_flags,
5144                                                            attr, error);
5145                         if (ret < 0)
5146                                 return ret;
5147                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5148                                 /* Count all modify-header actions as one. */
5149                                 if (!(action_flags &
5150                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5151                                         ++actions_n;
5152                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5153                                                 MLX5_FLOW_ACTION_MARK_EXT;
5154                         } else {
5155                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5156                                 ++actions_n;
5157                         }
5158                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5159                         break;
5160                 case RTE_FLOW_ACTION_TYPE_MARK:
5161                         ret = flow_dv_validate_action_mark(dev, actions,
5162                                                            action_flags,
5163                                                            attr, error);
5164                         if (ret < 0)
5165                                 return ret;
5166                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5167                                 /* Count all modify-header actions as one. */
5168                                 if (!(action_flags &
5169                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5170                                         ++actions_n;
5171                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5172                                                 MLX5_FLOW_ACTION_MARK_EXT;
5173                         } else {
5174                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5175                                 ++actions_n;
5176                         }
5177                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5178                         break;
5179                 case RTE_FLOW_ACTION_TYPE_SET_META:
5180                         ret = flow_dv_validate_action_set_meta(dev, actions,
5181                                                                action_flags,
5182                                                                attr, error);
5183                         if (ret < 0)
5184                                 return ret;
5185                         /* Count all modify-header actions as one action. */
5186                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5187                                 ++actions_n;
5188                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5189                         rw_act_num += MLX5_ACT_NUM_SET_META;
5190                         break;
5191                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5192                         ret = flow_dv_validate_action_set_tag(dev, actions,
5193                                                               action_flags,
5194                                                               attr, error);
5195                         if (ret < 0)
5196                                 return ret;
5197                         /* Count all modify-header actions as one action. */
5198                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5199                                 ++actions_n;
5200                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5201                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5202                         break;
5203                 case RTE_FLOW_ACTION_TYPE_DROP:
5204                         ret = mlx5_flow_validate_action_drop(action_flags,
5205                                                              attr, error);
5206                         if (ret < 0)
5207                                 return ret;
5208                         action_flags |= MLX5_FLOW_ACTION_DROP;
5209                         ++actions_n;
5210                         break;
5211                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5212                         ret = mlx5_flow_validate_action_queue(actions,
5213                                                               action_flags, dev,
5214                                                               attr, error);
5215                         if (ret < 0)
5216                                 return ret;
5217                         queue_index = ((const struct rte_flow_action_queue *)
5218                                                         (actions->conf))->index;
5219                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5220                         ++actions_n;
5221                         break;
5222                 case RTE_FLOW_ACTION_TYPE_RSS:
5223                         rss = actions->conf;
5224                         ret = mlx5_flow_validate_action_rss(actions,
5225                                                             action_flags, dev,
5226                                                             attr, item_flags,
5227                                                             error);
5228                         if (ret < 0)
5229                                 return ret;
5230                         if (rss != NULL && rss->queue_num)
5231                                 queue_index = rss->queue[0];
5232                         action_flags |= MLX5_FLOW_ACTION_RSS;
5233                         ++actions_n;
5234                         break;
5235                 case RTE_FLOW_ACTION_TYPE_COUNT:
5236                         ret = flow_dv_validate_action_count(dev, error);
5237                         if (ret < 0)
5238                                 return ret;
5239                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5240                         ++actions_n;
5241                         break;
5242                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5243                         if (flow_dv_validate_action_pop_vlan(dev,
5244                                                              action_flags,
5245                                                              actions,
5246                                                              item_flags, attr,
5247                                                              error))
5248                                 return -rte_errno;
5249                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5250                         ++actions_n;
5251                         break;
5252                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5253                         ret = flow_dv_validate_action_push_vlan(dev,
5254                                                                 action_flags,
5255                                                                 vlan_m,
5256                                                                 actions, attr,
5257                                                                 error);
5258                         if (ret < 0)
5259                                 return ret;
5260                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5261                         ++actions_n;
5262                         break;
5263                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5264                         ret = flow_dv_validate_action_set_vlan_pcp
5265                                                 (action_flags, actions, error);
5266                         if (ret < 0)
5267                                 return ret;
5268                         /* Count PCP with push_vlan command. */
5269                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5270                         break;
5271                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5272                         ret = flow_dv_validate_action_set_vlan_vid
5273                                                 (item_flags, action_flags,
5274                                                  actions, error);
5275                         if (ret < 0)
5276                                 return ret;
5277                         /* Count VID with push_vlan command. */
5278                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5279                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5280                         break;
5281                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5282                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5283                         ret = flow_dv_validate_action_l2_encap(dev,
5284                                                                action_flags,
5285                                                                actions, attr,
5286                                                                error);
5287                         if (ret < 0)
5288                                 return ret;
5289                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5290                         ++actions_n;
5291                         break;
5292                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5293                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5294                         ret = flow_dv_validate_action_decap(dev, action_flags,
5295                                                             attr, error);
5296                         if (ret < 0)
5297                                 return ret;
5298                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5299                         ++actions_n;
5300                         break;
5301                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5302                         ret = flow_dv_validate_action_raw_encap_decap
5303                                 (dev, NULL, actions->conf, attr, &action_flags,
5304                                  &actions_n, error);
5305                         if (ret < 0)
5306                                 return ret;
5307                         break;
5308                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5309                         decap = actions->conf;
5310                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5311                                 ;
5312                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5313                                 encap = NULL;
5314                                 actions--;
5315                         } else {
5316                                 encap = actions->conf;
5317                         }
5318                         ret = flow_dv_validate_action_raw_encap_decap
5319                                            (dev,
5320                                             decap ? decap : &empty_decap, encap,
5321                                             attr, &action_flags, &actions_n,
5322                                             error);
5323                         if (ret < 0)
5324                                 return ret;
5325                         break;
5326                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5327                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5328                         ret = flow_dv_validate_action_modify_mac(action_flags,
5329                                                                  actions,
5330                                                                  item_flags,
5331                                                                  error);
5332                         if (ret < 0)
5333                                 return ret;
5334                         /* Count all modify-header actions as one action. */
5335                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5336                                 ++actions_n;
5337                         action_flags |= actions->type ==
5338                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5339                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5340                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5341                         /*
5342                          * Even if the source and destination MAC addresses have
5343                          * overlap in the header with 4B alignment, the convert
5344                          * function will handle them separately and 4 SW actions
5345                          * will be created. And 2 actions will be added each
5346                          * time no matter how many bytes of address will be set.
5347                          */
5348                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5349                         break;
5350                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5351                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5352                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5353                                                                   actions,
5354                                                                   item_flags,
5355                                                                   error);
5356                         if (ret < 0)
5357                                 return ret;
5358                         /* Count all modify-header actions as one action. */
5359                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5360                                 ++actions_n;
5361                         action_flags |= actions->type ==
5362                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5363                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5364                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5365                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5366                         break;
5367                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5368                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5369                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5370                                                                   actions,
5371                                                                   item_flags,
5372                                                                   error);
5373                         if (ret < 0)
5374                                 return ret;
5375                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5376                                 return rte_flow_error_set(error, ENOTSUP,
5377                                         RTE_FLOW_ERROR_TYPE_ACTION,
5378                                         actions,
5379                                         "Can't change header "
5380                                         "with ICMPv6 proto");
5381                         /* Count all modify-header actions as one action. */
5382                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5383                                 ++actions_n;
5384                         action_flags |= actions->type ==
5385                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5386                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5387                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5388                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5389                         break;
5390                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5391                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5392                         ret = flow_dv_validate_action_modify_tp(action_flags,
5393                                                                 actions,
5394                                                                 item_flags,
5395                                                                 error);
5396                         if (ret < 0)
5397                                 return ret;
5398                         /* Count all modify-header actions as one action. */
5399                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5400                                 ++actions_n;
5401                         action_flags |= actions->type ==
5402                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5403                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5404                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5405                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5406                         break;
5407                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5408                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5409                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5410                                                                  actions,
5411                                                                  item_flags,
5412                                                                  error);
5413                         if (ret < 0)
5414                                 return ret;
5415                         /* Count all modify-header actions as one action. */
5416                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5417                                 ++actions_n;
5418                         action_flags |= actions->type ==
5419                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5420                                                 MLX5_FLOW_ACTION_SET_TTL :
5421                                                 MLX5_FLOW_ACTION_DEC_TTL;
5422                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5423                         break;
5424                 case RTE_FLOW_ACTION_TYPE_JUMP:
5425                         ret = flow_dv_validate_action_jump(actions,
5426                                                            action_flags,
5427                                                            attr, external,
5428                                                            error);
5429                         if (ret)
5430                                 return ret;
5431                         ++actions_n;
5432                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5433                         break;
5434                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5435                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5436                         ret = flow_dv_validate_action_modify_tcp_seq
5437                                                                 (action_flags,
5438                                                                  actions,
5439                                                                  item_flags,
5440                                                                  error);
5441                         if (ret < 0)
5442                                 return ret;
5443                         /* Count all modify-header actions as one action. */
5444                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5445                                 ++actions_n;
5446                         action_flags |= actions->type ==
5447                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5448                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5449                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5450                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5451                         break;
5452                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5453                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5454                         ret = flow_dv_validate_action_modify_tcp_ack
5455                                                                 (action_flags,
5456                                                                  actions,
5457                                                                  item_flags,
5458                                                                  error);
5459                         if (ret < 0)
5460                                 return ret;
5461                         /* Count all modify-header actions as one action. */
5462                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5463                                 ++actions_n;
5464                         action_flags |= actions->type ==
5465                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5466                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5467                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5468                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5469                         break;
5470                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5471                         break;
5472                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5473                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5474                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5475                         break;
5476                 case RTE_FLOW_ACTION_TYPE_METER:
5477                         ret = mlx5_flow_validate_action_meter(dev,
5478                                                               action_flags,
5479                                                               actions, attr,
5480                                                               error);
5481                         if (ret < 0)
5482                                 return ret;
5483                         action_flags |= MLX5_FLOW_ACTION_METER;
5484                         ++actions_n;
5485                         /* Meter action will add one more TAG action. */
5486                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5487                         break;
5488                 case RTE_FLOW_ACTION_TYPE_AGE:
5489                         ret = flow_dv_validate_action_age(action_flags,
5490                                                           actions, dev,
5491                                                           error);
5492                         if (ret < 0)
5493                                 return ret;
5494                         action_flags |= MLX5_FLOW_ACTION_AGE;
5495                         ++actions_n;
5496                         break;
5497                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5498                         ret = flow_dv_validate_action_modify_ipv4_dscp
5499                                                          (action_flags,
5500                                                           actions,
5501                                                           item_flags,
5502                                                           error);
5503                         if (ret < 0)
5504                                 return ret;
5505                         /* Count all modify-header actions as one action. */
5506                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5507                                 ++actions_n;
5508                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5509                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5510                         break;
5511                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5512                         ret = flow_dv_validate_action_modify_ipv6_dscp
5513                                                                 (action_flags,
5514                                                                  actions,
5515                                                                  item_flags,
5516                                                                  error);
5517                         if (ret < 0)
5518                                 return ret;
5519                         /* Count all modify-header actions as one action. */
5520                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5521                                 ++actions_n;
5522                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5523                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5524                         break;
5525                 default:
5526                         return rte_flow_error_set(error, ENOTSUP,
5527                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5528                                                   actions,
5529                                                   "action not supported");
5530                 }
5531         }
5532         /*
5533          * Validate the drop action mutual exclusion with other actions.
5534          * Drop action is mutually-exclusive with any other action, except for
5535          * Count action.
5536          */
5537         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5538             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5539                 return rte_flow_error_set(error, EINVAL,
5540                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5541                                           "Drop action is mutually-exclusive "
5542                                           "with any other action, except for "
5543                                           "Count action");
5544         /* Eswitch has few restrictions on using items and actions */
5545         if (attr->transfer) {
5546                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5547                     action_flags & MLX5_FLOW_ACTION_FLAG)
5548                         return rte_flow_error_set(error, ENOTSUP,
5549                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5550                                                   NULL,
5551                                                   "unsupported action FLAG");
5552                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5553                     action_flags & MLX5_FLOW_ACTION_MARK)
5554                         return rte_flow_error_set(error, ENOTSUP,
5555                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5556                                                   NULL,
5557                                                   "unsupported action MARK");
5558                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5559                         return rte_flow_error_set(error, ENOTSUP,
5560                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5561                                                   NULL,
5562                                                   "unsupported action QUEUE");
5563                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5564                         return rte_flow_error_set(error, ENOTSUP,
5565                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5566                                                   NULL,
5567                                                   "unsupported action RSS");
5568                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5569                         return rte_flow_error_set(error, EINVAL,
5570                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5571                                                   actions,
5572                                                   "no fate action is found");
5573         } else {
5574                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5575                         return rte_flow_error_set(error, EINVAL,
5576                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5577                                                   actions,
5578                                                   "no fate action is found");
5579         }
5580         /* Continue validation for Xcap actions.*/
5581         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5582             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5583                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5584                     MLX5_FLOW_XCAP_ACTIONS)
5585                         return rte_flow_error_set(error, ENOTSUP,
5586                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5587                                                   NULL, "encap and decap "
5588                                                   "combination aren't supported");
5589                 if (!attr->transfer && attr->ingress && (action_flags &
5590                                                         MLX5_FLOW_ACTION_ENCAP))
5591                         return rte_flow_error_set(error, ENOTSUP,
5592                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5593                                                   NULL, "encap is not supported"
5594                                                   " for ingress traffic");
5595         }
5596         /* Hairpin flow will add one more TAG action. */
5597         if (hairpin > 0)
5598                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5599         /* extra metadata enabled: one more TAG action will be add. */
5600         if (dev_conf->dv_flow_en &&
5601             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5602             mlx5_flow_ext_mreg_supported(dev))
5603                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5604         if ((uint32_t)rw_act_num >
5605                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5606                 return rte_flow_error_set(error, ENOTSUP,
5607                                           RTE_FLOW_ERROR_TYPE_ACTION,
5608                                           NULL, "too many header modify"
5609                                           " actions to support");
5610         }
5611         return 0;
5612 }
5613
5614 /**
5615  * Internal preparation function. Allocates the DV flow size,
5616  * this size is constant.
5617  *
5618  * @param[in] dev
5619  *   Pointer to the rte_eth_dev structure.
5620  * @param[in] attr
5621  *   Pointer to the flow attributes.
5622  * @param[in] items
5623  *   Pointer to the list of items.
5624  * @param[in] actions
5625  *   Pointer to the list of actions.
5626  * @param[out] error
5627  *   Pointer to the error structure.
5628  *
5629  * @return
5630  *   Pointer to mlx5_flow object on success,
5631  *   otherwise NULL and rte_errno is set.
5632  */
5633 static struct mlx5_flow *
5634 flow_dv_prepare(struct rte_eth_dev *dev,
5635                 const struct rte_flow_attr *attr __rte_unused,
5636                 const struct rte_flow_item items[] __rte_unused,
5637                 const struct rte_flow_action actions[] __rte_unused,
5638                 struct rte_flow_error *error)
5639 {
5640         uint32_t handle_idx = 0;
5641         struct mlx5_flow *dev_flow;
5642         struct mlx5_flow_handle *dev_handle;
5643         struct mlx5_priv *priv = dev->data->dev_private;
5644
5645         /* In case of corrupting the memory. */
5646         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5647                 rte_flow_error_set(error, ENOSPC,
5648                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5649                                    "not free temporary device flow");
5650                 return NULL;
5651         }
5652         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5653                                    &handle_idx);
5654         if (!dev_handle) {
5655                 rte_flow_error_set(error, ENOMEM,
5656                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5657                                    "not enough memory to create flow handle");
5658                 return NULL;
5659         }
5660         /* No multi-thread supporting. */
5661         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5662         dev_flow->handle = dev_handle;
5663         dev_flow->handle_idx = handle_idx;
5664         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5665         /*
5666          * The matching value needs to be cleared to 0 before using. In the
5667          * past, it will be automatically cleared when using rte_*alloc
5668          * API. The time consumption will be almost the same as before.
5669          */
5670         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5671         dev_flow->ingress = attr->ingress;
5672         dev_flow->dv.transfer = attr->transfer;
5673         return dev_flow;
5674 }
5675
5676 #ifdef RTE_LIBRTE_MLX5_DEBUG
5677 /**
5678  * Sanity check for match mask and value. Similar to check_valid_spec() in
5679  * kernel driver. If unmasked bit is present in value, it returns failure.
5680  *
5681  * @param match_mask
5682  *   pointer to match mask buffer.
5683  * @param match_value
5684  *   pointer to match value buffer.
5685  *
5686  * @return
5687  *   0 if valid, -EINVAL otherwise.
5688  */
5689 static int
5690 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5691 {
5692         uint8_t *m = match_mask;
5693         uint8_t *v = match_value;
5694         unsigned int i;
5695
5696         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5697                 if (v[i] & ~m[i]) {
5698                         DRV_LOG(ERR,
5699                                 "match_value differs from match_criteria"
5700                                 " %p[%u] != %p[%u]",
5701                                 match_value, i, match_mask, i);
5702                         return -EINVAL;
5703                 }
5704         }
5705         return 0;
5706 }
5707 #endif
5708
5709 /**
5710  * Add match of ip_version.
5711  *
5712  * @param[in] group
5713  *   Flow group.
5714  * @param[in] headers_v
5715  *   Values header pointer.
5716  * @param[in] headers_m
5717  *   Masks header pointer.
5718  * @param[in] ip_version
5719  *   The IP version to set.
5720  */
5721 static inline void
5722 flow_dv_set_match_ip_version(uint32_t group,
5723                              void *headers_v,
5724                              void *headers_m,
5725                              uint8_t ip_version)
5726 {
5727         if (group == 0)
5728                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5729         else
5730                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5731                          ip_version);
5732         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5733         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5734         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5735 }
5736
5737 /**
5738  * Add Ethernet item to matcher and to the value.
5739  *
5740  * @param[in, out] matcher
5741  *   Flow matcher.
5742  * @param[in, out] key
5743  *   Flow matcher value.
5744  * @param[in] item
5745  *   Flow pattern to translate.
5746  * @param[in] inner
5747  *   Item is inner pattern.
5748  */
5749 static void
5750 flow_dv_translate_item_eth(void *matcher, void *key,
5751                            const struct rte_flow_item *item, int inner,
5752                            uint32_t group)
5753 {
5754         const struct rte_flow_item_eth *eth_m = item->mask;
5755         const struct rte_flow_item_eth *eth_v = item->spec;
5756         const struct rte_flow_item_eth nic_mask = {
5757                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5758                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5759                 .type = RTE_BE16(0xffff),
5760         };
5761         void *headers_m;
5762         void *headers_v;
5763         char *l24_v;
5764         unsigned int i;
5765
5766         if (!eth_v)
5767                 return;
5768         if (!eth_m)
5769                 eth_m = &nic_mask;
5770         if (inner) {
5771                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5772                                          inner_headers);
5773                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5774         } else {
5775                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5776                                          outer_headers);
5777                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5778         }
5779         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5780                &eth_m->dst, sizeof(eth_m->dst));
5781         /* The value must be in the range of the mask. */
5782         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5783         for (i = 0; i < sizeof(eth_m->dst); ++i)
5784                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5785         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5786                &eth_m->src, sizeof(eth_m->src));
5787         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5788         /* The value must be in the range of the mask. */
5789         for (i = 0; i < sizeof(eth_m->dst); ++i)
5790                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5791         if (eth_v->type) {
5792                 /* When ethertype is present set mask for tagged VLAN. */
5793                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5794                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5795                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5796                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5797                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5798                                  1);
5799                         /* Return here to avoid setting match on ethertype. */
5800                         return;
5801                 }
5802         }
5803         /*
5804          * HW supports match on one Ethertype, the Ethertype following the last
5805          * VLAN tag of the packet (see PRM).
5806          * Set match on ethertype only if ETH header is not followed by VLAN.
5807          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5808          * ethertype, and use ip_version field instead.
5809          */
5810         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5811             eth_m->type == 0xFFFF) {
5812                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5813         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5814                    eth_m->type == 0xFFFF) {
5815                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5816         } else {
5817                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5818                          rte_be_to_cpu_16(eth_m->type));
5819                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5820                                      ethertype);
5821                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5822         }
5823 }
5824
5825 /**
5826  * Add VLAN item to matcher and to the value.
5827  *
5828  * @param[in, out] dev_flow
5829  *   Flow descriptor.
5830  * @param[in, out] matcher
5831  *   Flow matcher.
5832  * @param[in, out] key
5833  *   Flow matcher value.
5834  * @param[in] item
5835  *   Flow pattern to translate.
5836  * @param[in] inner
5837  *   Item is inner pattern.
5838  */
5839 static void
5840 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5841                             void *matcher, void *key,
5842                             const struct rte_flow_item *item,
5843                             int inner, uint32_t group)
5844 {
5845         const struct rte_flow_item_vlan *vlan_m = item->mask;
5846         const struct rte_flow_item_vlan *vlan_v = item->spec;
5847         void *headers_m;
5848         void *headers_v;
5849         uint16_t tci_m;
5850         uint16_t tci_v;
5851
5852         if (inner) {
5853                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5854                                          inner_headers);
5855                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5856         } else {
5857                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5858                                          outer_headers);
5859                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5860                 /*
5861                  * This is workaround, masks are not supported,
5862                  * and pre-validated.
5863                  */
5864                 if (vlan_v)
5865                         dev_flow->handle->vf_vlan.tag =
5866                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5867         }
5868         /*
5869          * When VLAN item exists in flow, mark packet as tagged,
5870          * even if TCI is not specified.
5871          */
5872         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5873         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5874         if (!vlan_v)
5875                 return;
5876         if (!vlan_m)
5877                 vlan_m = &rte_flow_item_vlan_mask;
5878         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5879         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5880         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5881         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5882         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5883         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5884         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5885         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5886         /*
5887          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5888          * ethertype, and use ip_version field instead.
5889          */
5890         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5891             vlan_m->inner_type == 0xFFFF) {
5892                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5893         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5894                    vlan_m->inner_type == 0xFFFF) {
5895                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5896         } else {
5897                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5898                          rte_be_to_cpu_16(vlan_m->inner_type));
5899                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5900                          rte_be_to_cpu_16(vlan_m->inner_type &
5901                                           vlan_v->inner_type));
5902         }
5903 }
5904
5905 /**
5906  * Add IPV4 item to matcher and to the value.
5907  *
5908  * @param[in, out] matcher
5909  *   Flow matcher.
5910  * @param[in, out] key
5911  *   Flow matcher value.
5912  * @param[in] item
5913  *   Flow pattern to translate.
5914  * @param[in] item_flags
5915  *   Bit-fields that holds the items detected until now.
5916  * @param[in] inner
5917  *   Item is inner pattern.
5918  * @param[in] group
5919  *   The group to insert the rule.
5920  */
5921 static void
5922 flow_dv_translate_item_ipv4(void *matcher, void *key,
5923                             const struct rte_flow_item *item,
5924                             const uint64_t item_flags,
5925                             int inner, uint32_t group)
5926 {
5927         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5928         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5929         const struct rte_flow_item_ipv4 nic_mask = {
5930                 .hdr = {
5931                         .src_addr = RTE_BE32(0xffffffff),
5932                         .dst_addr = RTE_BE32(0xffffffff),
5933                         .type_of_service = 0xff,
5934                         .next_proto_id = 0xff,
5935                         .time_to_live = 0xff,
5936                 },
5937         };
5938         void *headers_m;
5939         void *headers_v;
5940         char *l24_m;
5941         char *l24_v;
5942         uint8_t tos;
5943
5944         if (inner) {
5945                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5946                                          inner_headers);
5947                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5948         } else {
5949                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5950                                          outer_headers);
5951                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5952         }
5953         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5954         /*
5955          * On outer header (which must contains L2), or inner header with L2,
5956          * set cvlan_tag mask bit to mark this packet as untagged.
5957          * This should be done even if item->spec is empty.
5958          */
5959         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5960                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5961         if (!ipv4_v)
5962                 return;
5963         if (!ipv4_m)
5964                 ipv4_m = &nic_mask;
5965         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5966                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5967         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5968                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5969         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5970         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5971         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5972                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5973         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5974                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5975         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5976         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5977         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5978         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5979                  ipv4_m->hdr.type_of_service);
5980         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5981         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5982                  ipv4_m->hdr.type_of_service >> 2);
5983         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5984         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5985                  ipv4_m->hdr.next_proto_id);
5986         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5987                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5988         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5989                  ipv4_m->hdr.time_to_live);
5990         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5991                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5992 }
5993
5994 /**
5995  * Add IPV6 item to matcher and to the value.
5996  *
5997  * @param[in, out] matcher
5998  *   Flow matcher.
5999  * @param[in, out] key
6000  *   Flow matcher value.
6001  * @param[in] item
6002  *   Flow pattern to translate.
6003  * @param[in] item_flags
6004  *   Bit-fields that holds the items detected until now.
6005  * @param[in] inner
6006  *   Item is inner pattern.
6007  * @param[in] group
6008  *   The group to insert the rule.
6009  */
6010 static void
6011 flow_dv_translate_item_ipv6(void *matcher, void *key,
6012                             const struct rte_flow_item *item,
6013                             const uint64_t item_flags,
6014                             int inner, uint32_t group)
6015 {
6016         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6017         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6018         const struct rte_flow_item_ipv6 nic_mask = {
6019                 .hdr = {
6020                         .src_addr =
6021                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6022                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6023                         .dst_addr =
6024                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6025                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6026                         .vtc_flow = RTE_BE32(0xffffffff),
6027                         .proto = 0xff,
6028                         .hop_limits = 0xff,
6029                 },
6030         };
6031         void *headers_m;
6032         void *headers_v;
6033         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6034         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6035         char *l24_m;
6036         char *l24_v;
6037         uint32_t vtc_m;
6038         uint32_t vtc_v;
6039         int i;
6040         int size;
6041
6042         if (inner) {
6043                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6044                                          inner_headers);
6045                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6046         } else {
6047                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6048                                          outer_headers);
6049                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6050         }
6051         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6052         /*
6053          * On outer header (which must contains L2), or inner header with L2,
6054          * set cvlan_tag mask bit to mark this packet as untagged.
6055          * This should be done even if item->spec is empty.
6056          */
6057         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6058                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6059         if (!ipv6_v)
6060                 return;
6061         if (!ipv6_m)
6062                 ipv6_m = &nic_mask;
6063         size = sizeof(ipv6_m->hdr.dst_addr);
6064         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6065                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6066         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6067                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6068         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6069         for (i = 0; i < size; ++i)
6070                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6071         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6072                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6073         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6074                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6075         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6076         for (i = 0; i < size; ++i)
6077                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6078         /* TOS. */
6079         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6080         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6081         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6082         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6083         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6084         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6085         /* Label. */
6086         if (inner) {
6087                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6088                          vtc_m);
6089                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6090                          vtc_v);
6091         } else {
6092                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6093                          vtc_m);
6094                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6095                          vtc_v);
6096         }
6097         /* Protocol. */
6098         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6099                  ipv6_m->hdr.proto);
6100         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6101                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6102         /* Hop limit. */
6103         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6104                  ipv6_m->hdr.hop_limits);
6105         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6106                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6107 }
6108
6109 /**
6110  * Add TCP item to matcher and to the value.
6111  *
6112  * @param[in, out] matcher
6113  *   Flow matcher.
6114  * @param[in, out] key
6115  *   Flow matcher value.
6116  * @param[in] item
6117  *   Flow pattern to translate.
6118  * @param[in] inner
6119  *   Item is inner pattern.
6120  */
6121 static void
6122 flow_dv_translate_item_tcp(void *matcher, void *key,
6123                            const struct rte_flow_item *item,
6124                            int inner)
6125 {
6126         const struct rte_flow_item_tcp *tcp_m = item->mask;
6127         const struct rte_flow_item_tcp *tcp_v = item->spec;
6128         void *headers_m;
6129         void *headers_v;
6130
6131         if (inner) {
6132                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6133                                          inner_headers);
6134                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6135         } else {
6136                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6137                                          outer_headers);
6138                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6139         }
6140         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6141         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6142         if (!tcp_v)
6143                 return;
6144         if (!tcp_m)
6145                 tcp_m = &rte_flow_item_tcp_mask;
6146         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6147                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6148         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6149                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6150         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6151                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6152         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6153                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6154         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6155                  tcp_m->hdr.tcp_flags);
6156         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6157                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6158 }
6159
6160 /**
6161  * Add UDP item to matcher and to the value.
6162  *
6163  * @param[in, out] matcher
6164  *   Flow matcher.
6165  * @param[in, out] key
6166  *   Flow matcher value.
6167  * @param[in] item
6168  *   Flow pattern to translate.
6169  * @param[in] inner
6170  *   Item is inner pattern.
6171  */
6172 static void
6173 flow_dv_translate_item_udp(void *matcher, void *key,
6174                            const struct rte_flow_item *item,
6175                            int inner)
6176 {
6177         const struct rte_flow_item_udp *udp_m = item->mask;
6178         const struct rte_flow_item_udp *udp_v = item->spec;
6179         void *headers_m;
6180         void *headers_v;
6181
6182         if (inner) {
6183                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6184                                          inner_headers);
6185                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6186         } else {
6187                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6188                                          outer_headers);
6189                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6190         }
6191         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6192         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6193         if (!udp_v)
6194                 return;
6195         if (!udp_m)
6196                 udp_m = &rte_flow_item_udp_mask;
6197         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6198                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6199         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6200                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6201         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6202                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6203         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6204                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6205 }
6206
6207 /**
6208  * Add GRE optional Key item to matcher and to the value.
6209  *
6210  * @param[in, out] matcher
6211  *   Flow matcher.
6212  * @param[in, out] key
6213  *   Flow matcher value.
6214  * @param[in] item
6215  *   Flow pattern to translate.
6216  * @param[in] inner
6217  *   Item is inner pattern.
6218  */
6219 static void
6220 flow_dv_translate_item_gre_key(void *matcher, void *key,
6221                                    const struct rte_flow_item *item)
6222 {
6223         const rte_be32_t *key_m = item->mask;
6224         const rte_be32_t *key_v = item->spec;
6225         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6226         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6227         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6228
6229         /* GRE K bit must be on and should already be validated */
6230         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6231         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6232         if (!key_v)
6233                 return;
6234         if (!key_m)
6235                 key_m = &gre_key_default_mask;
6236         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6237                  rte_be_to_cpu_32(*key_m) >> 8);
6238         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6239                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6240         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6241                  rte_be_to_cpu_32(*key_m) & 0xFF);
6242         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6243                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6244 }
6245
6246 /**
6247  * Add GRE item to matcher and to the value.
6248  *
6249  * @param[in, out] matcher
6250  *   Flow matcher.
6251  * @param[in, out] key
6252  *   Flow matcher value.
6253  * @param[in] item
6254  *   Flow pattern to translate.
6255  * @param[in] inner
6256  *   Item is inner pattern.
6257  */
6258 static void
6259 flow_dv_translate_item_gre(void *matcher, void *key,
6260                            const struct rte_flow_item *item,
6261                            int inner)
6262 {
6263         const struct rte_flow_item_gre *gre_m = item->mask;
6264         const struct rte_flow_item_gre *gre_v = item->spec;
6265         void *headers_m;
6266         void *headers_v;
6267         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6268         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6269         struct {
6270                 union {
6271                         __extension__
6272                         struct {
6273                                 uint16_t version:3;
6274                                 uint16_t rsvd0:9;
6275                                 uint16_t s_present:1;
6276                                 uint16_t k_present:1;
6277                                 uint16_t rsvd_bit1:1;
6278                                 uint16_t c_present:1;
6279                         };
6280                         uint16_t value;
6281                 };
6282         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6283
6284         if (inner) {
6285                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6286                                          inner_headers);
6287                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6288         } else {
6289                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6290                                          outer_headers);
6291                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6292         }
6293         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6294         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6295         if (!gre_v)
6296                 return;
6297         if (!gre_m)
6298                 gre_m = &rte_flow_item_gre_mask;
6299         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6300                  rte_be_to_cpu_16(gre_m->protocol));
6301         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6302                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6303         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6304         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6305         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6306                  gre_crks_rsvd0_ver_m.c_present);
6307         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6308                  gre_crks_rsvd0_ver_v.c_present &
6309                  gre_crks_rsvd0_ver_m.c_present);
6310         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6311                  gre_crks_rsvd0_ver_m.k_present);
6312         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6313                  gre_crks_rsvd0_ver_v.k_present &
6314                  gre_crks_rsvd0_ver_m.k_present);
6315         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6316                  gre_crks_rsvd0_ver_m.s_present);
6317         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6318                  gre_crks_rsvd0_ver_v.s_present &
6319                  gre_crks_rsvd0_ver_m.s_present);
6320 }
6321
6322 /**
6323  * Add NVGRE item to matcher and to the value.
6324  *
6325  * @param[in, out] matcher
6326  *   Flow matcher.
6327  * @param[in, out] key
6328  *   Flow matcher value.
6329  * @param[in] item
6330  *   Flow pattern to translate.
6331  * @param[in] inner
6332  *   Item is inner pattern.
6333  */
6334 static void
6335 flow_dv_translate_item_nvgre(void *matcher, void *key,
6336                              const struct rte_flow_item *item,
6337                              int inner)
6338 {
6339         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6340         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6341         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6342         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6343         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6344         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6345         char *gre_key_m;
6346         char *gre_key_v;
6347         int size;
6348         int i;
6349
6350         /* For NVGRE, GRE header fields must be set with defined values. */
6351         const struct rte_flow_item_gre gre_spec = {
6352                 .c_rsvd0_ver = RTE_BE16(0x2000),
6353                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6354         };
6355         const struct rte_flow_item_gre gre_mask = {
6356                 .c_rsvd0_ver = RTE_BE16(0xB000),
6357                 .protocol = RTE_BE16(UINT16_MAX),
6358         };
6359         const struct rte_flow_item gre_item = {
6360                 .spec = &gre_spec,
6361                 .mask = &gre_mask,
6362                 .last = NULL,
6363         };
6364         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6365         if (!nvgre_v)
6366                 return;
6367         if (!nvgre_m)
6368                 nvgre_m = &rte_flow_item_nvgre_mask;
6369         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6370         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6371         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6372         memcpy(gre_key_m, tni_flow_id_m, size);
6373         for (i = 0; i < size; ++i)
6374                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6375 }
6376
6377 /**
6378  * Add VXLAN item to matcher and to the value.
6379  *
6380  * @param[in, out] matcher
6381  *   Flow matcher.
6382  * @param[in, out] key
6383  *   Flow matcher value.
6384  * @param[in] item
6385  *   Flow pattern to translate.
6386  * @param[in] inner
6387  *   Item is inner pattern.
6388  */
6389 static void
6390 flow_dv_translate_item_vxlan(void *matcher, void *key,
6391                              const struct rte_flow_item *item,
6392                              int inner)
6393 {
6394         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6395         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6396         void *headers_m;
6397         void *headers_v;
6398         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6399         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6400         char *vni_m;
6401         char *vni_v;
6402         uint16_t dport;
6403         int size;
6404         int i;
6405
6406         if (inner) {
6407                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6408                                          inner_headers);
6409                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6410         } else {
6411                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6412                                          outer_headers);
6413                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6414         }
6415         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6416                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6417         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6418                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6419                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6420         }
6421         if (!vxlan_v)
6422                 return;
6423         if (!vxlan_m)
6424                 vxlan_m = &rte_flow_item_vxlan_mask;
6425         size = sizeof(vxlan_m->vni);
6426         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6427         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6428         memcpy(vni_m, vxlan_m->vni, size);
6429         for (i = 0; i < size; ++i)
6430                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6431 }
6432
6433 /**
6434  * Add VXLAN-GPE item to matcher and to the value.
6435  *
6436  * @param[in, out] matcher
6437  *   Flow matcher.
6438  * @param[in, out] key
6439  *   Flow matcher value.
6440  * @param[in] item
6441  *   Flow pattern to translate.
6442  * @param[in] inner
6443  *   Item is inner pattern.
6444  */
6445
6446 static void
6447 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6448                                  const struct rte_flow_item *item, int inner)
6449 {
6450         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6451         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6452         void *headers_m;
6453         void *headers_v;
6454         void *misc_m =
6455                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6456         void *misc_v =
6457                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6458         char *vni_m;
6459         char *vni_v;
6460         uint16_t dport;
6461         int size;
6462         int i;
6463         uint8_t flags_m = 0xff;
6464         uint8_t flags_v = 0xc;
6465
6466         if (inner) {
6467                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6468                                          inner_headers);
6469                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6470         } else {
6471                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6472                                          outer_headers);
6473                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6474         }
6475         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6476                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6477         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6478                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6479                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6480         }
6481         if (!vxlan_v)
6482                 return;
6483         if (!vxlan_m)
6484                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6485         size = sizeof(vxlan_m->vni);
6486         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6487         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6488         memcpy(vni_m, vxlan_m->vni, size);
6489         for (i = 0; i < size; ++i)
6490                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6491         if (vxlan_m->flags) {
6492                 flags_m = vxlan_m->flags;
6493                 flags_v = vxlan_v->flags;
6494         }
6495         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6496         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6497         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6498                  vxlan_m->protocol);
6499         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6500                  vxlan_v->protocol);
6501 }
6502
6503 /**
6504  * Add Geneve item to matcher and to the value.
6505  *
6506  * @param[in, out] matcher
6507  *   Flow matcher.
6508  * @param[in, out] key
6509  *   Flow matcher value.
6510  * @param[in] item
6511  *   Flow pattern to translate.
6512  * @param[in] inner
6513  *   Item is inner pattern.
6514  */
6515
6516 static void
6517 flow_dv_translate_item_geneve(void *matcher, void *key,
6518                               const struct rte_flow_item *item, int inner)
6519 {
6520         const struct rte_flow_item_geneve *geneve_m = item->mask;
6521         const struct rte_flow_item_geneve *geneve_v = item->spec;
6522         void *headers_m;
6523         void *headers_v;
6524         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6525         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6526         uint16_t dport;
6527         uint16_t gbhdr_m;
6528         uint16_t gbhdr_v;
6529         char *vni_m;
6530         char *vni_v;
6531         size_t size, i;
6532
6533         if (inner) {
6534                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6535                                          inner_headers);
6536                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6537         } else {
6538                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6539                                          outer_headers);
6540                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6541         }
6542         dport = MLX5_UDP_PORT_GENEVE;
6543         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6544                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6545                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6546         }
6547         if (!geneve_v)
6548                 return;
6549         if (!geneve_m)
6550                 geneve_m = &rte_flow_item_geneve_mask;
6551         size = sizeof(geneve_m->vni);
6552         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6553         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6554         memcpy(vni_m, geneve_m->vni, size);
6555         for (i = 0; i < size; ++i)
6556                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6557         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6558                  rte_be_to_cpu_16(geneve_m->protocol));
6559         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6560                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6561         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6562         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6563         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6564                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6565         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6566                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6567         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6568                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6569         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6570                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6571                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6572 }
6573
6574 /**
6575  * Add MPLS item to matcher and to the value.
6576  *
6577  * @param[in, out] matcher
6578  *   Flow matcher.
6579  * @param[in, out] key
6580  *   Flow matcher value.
6581  * @param[in] item
6582  *   Flow pattern to translate.
6583  * @param[in] prev_layer
6584  *   The protocol layer indicated in previous item.
6585  * @param[in] inner
6586  *   Item is inner pattern.
6587  */
6588 static void
6589 flow_dv_translate_item_mpls(void *matcher, void *key,
6590                             const struct rte_flow_item *item,
6591                             uint64_t prev_layer,
6592                             int inner)
6593 {
6594         const uint32_t *in_mpls_m = item->mask;
6595         const uint32_t *in_mpls_v = item->spec;
6596         uint32_t *out_mpls_m = 0;
6597         uint32_t *out_mpls_v = 0;
6598         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6599         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6600         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6601                                      misc_parameters_2);
6602         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6603         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6604         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6605
6606         switch (prev_layer) {
6607         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6608                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6609                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6610                          MLX5_UDP_PORT_MPLS);
6611                 break;
6612         case MLX5_FLOW_LAYER_GRE:
6613                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6614                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6615                          RTE_ETHER_TYPE_MPLS);
6616                 break;
6617         default:
6618                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6619                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6620                          IPPROTO_MPLS);
6621                 break;
6622         }
6623         if (!in_mpls_v)
6624                 return;
6625         if (!in_mpls_m)
6626                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6627         switch (prev_layer) {
6628         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6629                 out_mpls_m =
6630                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6631                                                  outer_first_mpls_over_udp);
6632                 out_mpls_v =
6633                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6634                                                  outer_first_mpls_over_udp);
6635                 break;
6636         case MLX5_FLOW_LAYER_GRE:
6637                 out_mpls_m =
6638                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6639                                                  outer_first_mpls_over_gre);
6640                 out_mpls_v =
6641                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6642                                                  outer_first_mpls_over_gre);
6643                 break;
6644         default:
6645                 /* Inner MPLS not over GRE is not supported. */
6646                 if (!inner) {
6647                         out_mpls_m =
6648                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6649                                                          misc2_m,
6650                                                          outer_first_mpls);
6651                         out_mpls_v =
6652                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6653                                                          misc2_v,
6654                                                          outer_first_mpls);
6655                 }
6656                 break;
6657         }
6658         if (out_mpls_m && out_mpls_v) {
6659                 *out_mpls_m = *in_mpls_m;
6660                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6661         }
6662 }
6663
6664 /**
6665  * Add metadata register item to matcher
6666  *
6667  * @param[in, out] matcher
6668  *   Flow matcher.
6669  * @param[in, out] key
6670  *   Flow matcher value.
6671  * @param[in] reg_type
6672  *   Type of device metadata register
6673  * @param[in] value
6674  *   Register value
6675  * @param[in] mask
6676  *   Register mask
6677  */
6678 static void
6679 flow_dv_match_meta_reg(void *matcher, void *key,
6680                        enum modify_reg reg_type,
6681                        uint32_t data, uint32_t mask)
6682 {
6683         void *misc2_m =
6684                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6685         void *misc2_v =
6686                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6687         uint32_t temp;
6688
6689         data &= mask;
6690         switch (reg_type) {
6691         case REG_A:
6692                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6693                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6694                 break;
6695         case REG_B:
6696                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6697                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6698                 break;
6699         case REG_C_0:
6700                 /*
6701                  * The metadata register C0 field might be divided into
6702                  * source vport index and META item value, we should set
6703                  * this field according to specified mask, not as whole one.
6704                  */
6705                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6706                 temp |= mask;
6707                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6708                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6709                 temp &= ~mask;
6710                 temp |= data;
6711                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6712                 break;
6713         case REG_C_1:
6714                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6715                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6716                 break;
6717         case REG_C_2:
6718                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6719                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6720                 break;
6721         case REG_C_3:
6722                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6723                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6724                 break;
6725         case REG_C_4:
6726                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6727                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6728                 break;
6729         case REG_C_5:
6730                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6731                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6732                 break;
6733         case REG_C_6:
6734                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6735                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6736                 break;
6737         case REG_C_7:
6738                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6739                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6740                 break;
6741         default:
6742                 MLX5_ASSERT(false);
6743                 break;
6744         }
6745 }
6746
6747 /**
6748  * Add MARK item to matcher
6749  *
6750  * @param[in] dev
6751  *   The device to configure through.
6752  * @param[in, out] matcher
6753  *   Flow matcher.
6754  * @param[in, out] key
6755  *   Flow matcher value.
6756  * @param[in] item
6757  *   Flow pattern to translate.
6758  */
6759 static void
6760 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6761                             void *matcher, void *key,
6762                             const struct rte_flow_item *item)
6763 {
6764         struct mlx5_priv *priv = dev->data->dev_private;
6765         const struct rte_flow_item_mark *mark;
6766         uint32_t value;
6767         uint32_t mask;
6768
6769         mark = item->mask ? (const void *)item->mask :
6770                             &rte_flow_item_mark_mask;
6771         mask = mark->id & priv->sh->dv_mark_mask;
6772         mark = (const void *)item->spec;
6773         MLX5_ASSERT(mark);
6774         value = mark->id & priv->sh->dv_mark_mask & mask;
6775         if (mask) {
6776                 enum modify_reg reg;
6777
6778                 /* Get the metadata register index for the mark. */
6779                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6780                 MLX5_ASSERT(reg > 0);
6781                 if (reg == REG_C_0) {
6782                         struct mlx5_priv *priv = dev->data->dev_private;
6783                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6784                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6785
6786                         mask &= msk_c0;
6787                         mask <<= shl_c0;
6788                         value <<= shl_c0;
6789                 }
6790                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6791         }
6792 }
6793
6794 /**
6795  * Add META item to matcher
6796  *
6797  * @param[in] dev
6798  *   The devich to configure through.
6799  * @param[in, out] matcher
6800  *   Flow matcher.
6801  * @param[in, out] key
6802  *   Flow matcher value.
6803  * @param[in] attr
6804  *   Attributes of flow that includes this item.
6805  * @param[in] item
6806  *   Flow pattern to translate.
6807  */
6808 static void
6809 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6810                             void *matcher, void *key,
6811                             const struct rte_flow_attr *attr,
6812                             const struct rte_flow_item *item)
6813 {
6814         const struct rte_flow_item_meta *meta_m;
6815         const struct rte_flow_item_meta *meta_v;
6816
6817         meta_m = (const void *)item->mask;
6818         if (!meta_m)
6819                 meta_m = &rte_flow_item_meta_mask;
6820         meta_v = (const void *)item->spec;
6821         if (meta_v) {
6822                 int reg;
6823                 uint32_t value = meta_v->data;
6824                 uint32_t mask = meta_m->data;
6825
6826                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6827                 if (reg < 0)
6828                         return;
6829                 /*
6830                  * In datapath code there is no endianness
6831                  * coversions for perfromance reasons, all
6832                  * pattern conversions are done in rte_flow.
6833                  */
6834                 value = rte_cpu_to_be_32(value);
6835                 mask = rte_cpu_to_be_32(mask);
6836                 if (reg == REG_C_0) {
6837                         struct mlx5_priv *priv = dev->data->dev_private;
6838                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6839                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6840 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6841                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6842
6843                         value >>= shr_c0;
6844                         mask >>= shr_c0;
6845 #endif
6846                         value <<= shl_c0;
6847                         mask <<= shl_c0;
6848                         MLX5_ASSERT(msk_c0);
6849                         MLX5_ASSERT(!(~msk_c0 & mask));
6850                 }
6851                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6852         }
6853 }
6854
6855 /**
6856  * Add vport metadata Reg C0 item to matcher
6857  *
6858  * @param[in, out] matcher
6859  *   Flow matcher.
6860  * @param[in, out] key
6861  *   Flow matcher value.
6862  * @param[in] reg
6863  *   Flow pattern to translate.
6864  */
6865 static void
6866 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6867                                   uint32_t value, uint32_t mask)
6868 {
6869         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6870 }
6871
6872 /**
6873  * Add tag item to matcher
6874  *
6875  * @param[in] dev
6876  *   The devich to configure through.
6877  * @param[in, out] matcher
6878  *   Flow matcher.
6879  * @param[in, out] key
6880  *   Flow matcher value.
6881  * @param[in] item
6882  *   Flow pattern to translate.
6883  */
6884 static void
6885 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6886                                 void *matcher, void *key,
6887                                 const struct rte_flow_item *item)
6888 {
6889         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6890         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6891         uint32_t mask, value;
6892
6893         MLX5_ASSERT(tag_v);
6894         value = tag_v->data;
6895         mask = tag_m ? tag_m->data : UINT32_MAX;
6896         if (tag_v->id == REG_C_0) {
6897                 struct mlx5_priv *priv = dev->data->dev_private;
6898                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6899                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6900
6901                 mask &= msk_c0;
6902                 mask <<= shl_c0;
6903                 value <<= shl_c0;
6904         }
6905         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6906 }
6907
6908 /**
6909  * Add TAG item to matcher
6910  *
6911  * @param[in] dev
6912  *   The devich to configure through.
6913  * @param[in, out] matcher
6914  *   Flow matcher.
6915  * @param[in, out] key
6916  *   Flow matcher value.
6917  * @param[in] item
6918  *   Flow pattern to translate.
6919  */
6920 static void
6921 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6922                            void *matcher, void *key,
6923                            const struct rte_flow_item *item)
6924 {
6925         const struct rte_flow_item_tag *tag_v = item->spec;
6926         const struct rte_flow_item_tag *tag_m = item->mask;
6927         enum modify_reg reg;
6928
6929         MLX5_ASSERT(tag_v);
6930         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6931         /* Get the metadata register index for the tag. */
6932         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6933         MLX5_ASSERT(reg > 0);
6934         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6935 }
6936
6937 /**
6938  * Add source vport match to the specified matcher.
6939  *
6940  * @param[in, out] matcher
6941  *   Flow matcher.
6942  * @param[in, out] key
6943  *   Flow matcher value.
6944  * @param[in] port
6945  *   Source vport value to match
6946  * @param[in] mask
6947  *   Mask
6948  */
6949 static void
6950 flow_dv_translate_item_source_vport(void *matcher, void *key,
6951                                     int16_t port, uint16_t mask)
6952 {
6953         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6954         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6955
6956         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6957         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6958 }
6959
6960 /**
6961  * Translate port-id item to eswitch match on  port-id.
6962  *
6963  * @param[in] dev
6964  *   The devich to configure through.
6965  * @param[in, out] matcher
6966  *   Flow matcher.
6967  * @param[in, out] key
6968  *   Flow matcher value.
6969  * @param[in] item
6970  *   Flow pattern to translate.
6971  *
6972  * @return
6973  *   0 on success, a negative errno value otherwise.
6974  */
6975 static int
6976 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6977                                void *key, const struct rte_flow_item *item)
6978 {
6979         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6980         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6981         struct mlx5_priv *priv;
6982         uint16_t mask, id;
6983
6984         mask = pid_m ? pid_m->id : 0xffff;
6985         id = pid_v ? pid_v->id : dev->data->port_id;
6986         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6987         if (!priv)
6988                 return -rte_errno;
6989         /* Translate to vport field or to metadata, depending on mode. */
6990         if (priv->vport_meta_mask)
6991                 flow_dv_translate_item_meta_vport(matcher, key,
6992                                                   priv->vport_meta_tag,
6993                                                   priv->vport_meta_mask);
6994         else
6995                 flow_dv_translate_item_source_vport(matcher, key,
6996                                                     priv->vport_id, mask);
6997         return 0;
6998 }
6999
7000 /**
7001  * Add ICMP6 item to matcher and to the value.
7002  *
7003  * @param[in, out] matcher
7004  *   Flow matcher.
7005  * @param[in, out] key
7006  *   Flow matcher value.
7007  * @param[in] item
7008  *   Flow pattern to translate.
7009  * @param[in] inner
7010  *   Item is inner pattern.
7011  */
7012 static void
7013 flow_dv_translate_item_icmp6(void *matcher, void *key,
7014                               const struct rte_flow_item *item,
7015                               int inner)
7016 {
7017         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7018         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7019         void *headers_m;
7020         void *headers_v;
7021         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7022                                      misc_parameters_3);
7023         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7024         if (inner) {
7025                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7026                                          inner_headers);
7027                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7028         } else {
7029                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7030                                          outer_headers);
7031                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7032         }
7033         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7034         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7035         if (!icmp6_v)
7036                 return;
7037         if (!icmp6_m)
7038                 icmp6_m = &rte_flow_item_icmp6_mask;
7039         /*
7040          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7041          * If only the protocol is specified, no need to match the frag.
7042          */
7043         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7044         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7045         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7046         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7047                  icmp6_v->type & icmp6_m->type);
7048         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7049         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7050                  icmp6_v->code & icmp6_m->code);
7051 }
7052
7053 /**
7054  * Add ICMP item to matcher and to the value.
7055  *
7056  * @param[in, out] matcher
7057  *   Flow matcher.
7058  * @param[in, out] key
7059  *   Flow matcher value.
7060  * @param[in] item
7061  *   Flow pattern to translate.
7062  * @param[in] inner
7063  *   Item is inner pattern.
7064  */
7065 static void
7066 flow_dv_translate_item_icmp(void *matcher, void *key,
7067                             const struct rte_flow_item *item,
7068                             int inner)
7069 {
7070         const struct rte_flow_item_icmp *icmp_m = item->mask;
7071         const struct rte_flow_item_icmp *icmp_v = item->spec;
7072         void *headers_m;
7073         void *headers_v;
7074         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7075                                      misc_parameters_3);
7076         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7077         if (inner) {
7078                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7079                                          inner_headers);
7080                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7081         } else {
7082                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7083                                          outer_headers);
7084                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7085         }
7086         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7087         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7088         if (!icmp_v)
7089                 return;
7090         if (!icmp_m)
7091                 icmp_m = &rte_flow_item_icmp_mask;
7092         /*
7093          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7094          * If only the protocol is specified, no need to match the frag.
7095          */
7096         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7097         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7098         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7099                  icmp_m->hdr.icmp_type);
7100         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7101                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7102         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7103                  icmp_m->hdr.icmp_code);
7104         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7105                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7106 }
7107
7108 /**
7109  * Add GTP item to matcher and to the value.
7110  *
7111  * @param[in, out] matcher
7112  *   Flow matcher.
7113  * @param[in, out] key
7114  *   Flow matcher value.
7115  * @param[in] item
7116  *   Flow pattern to translate.
7117  * @param[in] inner
7118  *   Item is inner pattern.
7119  */
7120 static void
7121 flow_dv_translate_item_gtp(void *matcher, void *key,
7122                            const struct rte_flow_item *item, int inner)
7123 {
7124         const struct rte_flow_item_gtp *gtp_m = item->mask;
7125         const struct rte_flow_item_gtp *gtp_v = item->spec;
7126         void *headers_m;
7127         void *headers_v;
7128         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7129                                      misc_parameters_3);
7130         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7131         uint16_t dport = RTE_GTPU_UDP_PORT;
7132
7133         if (inner) {
7134                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7135                                          inner_headers);
7136                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7137         } else {
7138                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7139                                          outer_headers);
7140                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7141         }
7142         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7143                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7144                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7145         }
7146         if (!gtp_v)
7147                 return;
7148         if (!gtp_m)
7149                 gtp_m = &rte_flow_item_gtp_mask;
7150         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7151                  gtp_m->v_pt_rsv_flags);
7152         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7153                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7154         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7155         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7156                  gtp_v->msg_type & gtp_m->msg_type);
7157         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7158                  rte_be_to_cpu_32(gtp_m->teid));
7159         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7160                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7161 }
7162
7163 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7164
7165 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7166         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7167                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7168
7169 /**
7170  * Calculate flow matcher enable bitmap.
7171  *
7172  * @param match_criteria
7173  *   Pointer to flow matcher criteria.
7174  *
7175  * @return
7176  *   Bitmap of enabled fields.
7177  */
7178 static uint8_t
7179 flow_dv_matcher_enable(uint32_t *match_criteria)
7180 {
7181         uint8_t match_criteria_enable;
7182
7183         match_criteria_enable =
7184                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7185                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7186         match_criteria_enable |=
7187                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7188                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7189         match_criteria_enable |=
7190                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7191                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7192         match_criteria_enable |=
7193                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7194                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7195         match_criteria_enable |=
7196                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7197                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7198         return match_criteria_enable;
7199 }
7200
7201
7202 /**
7203  * Get a flow table.
7204  *
7205  * @param[in, out] dev
7206  *   Pointer to rte_eth_dev structure.
7207  * @param[in] table_id
7208  *   Table id to use.
7209  * @param[in] egress
7210  *   Direction of the table.
7211  * @param[in] transfer
7212  *   E-Switch or NIC flow.
7213  * @param[out] error
7214  *   pointer to error structure.
7215  *
7216  * @return
7217  *   Returns tables resource based on the index, NULL in case of failed.
7218  */
7219 static struct mlx5_flow_tbl_resource *
7220 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7221                          uint32_t table_id, uint8_t egress,
7222                          uint8_t transfer,
7223                          struct rte_flow_error *error)
7224 {
7225         struct mlx5_priv *priv = dev->data->dev_private;
7226         struct mlx5_ibv_shared *sh = priv->sh;
7227         struct mlx5_flow_tbl_resource *tbl;
7228         union mlx5_flow_tbl_key table_key = {
7229                 {
7230                         .table_id = table_id,
7231                         .reserved = 0,
7232                         .domain = !!transfer,
7233                         .direction = !!egress,
7234                 }
7235         };
7236         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7237                                                          table_key.v64);
7238         struct mlx5_flow_tbl_data_entry *tbl_data;
7239         uint32_t idx = 0;
7240         int ret;
7241         void *domain;
7242
7243         if (pos) {
7244                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7245                                         entry);
7246                 tbl = &tbl_data->tbl;
7247                 rte_atomic32_inc(&tbl->refcnt);
7248                 return tbl;
7249         }
7250         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7251         if (!tbl_data) {
7252                 rte_flow_error_set(error, ENOMEM,
7253                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7254                                    NULL,
7255                                    "cannot allocate flow table data entry");
7256                 return NULL;
7257         }
7258         tbl_data->idx = idx;
7259         tbl = &tbl_data->tbl;
7260         pos = &tbl_data->entry;
7261         if (transfer)
7262                 domain = sh->fdb_domain;
7263         else if (egress)
7264                 domain = sh->tx_domain;
7265         else
7266                 domain = sh->rx_domain;
7267         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7268         if (!tbl->obj) {
7269                 rte_flow_error_set(error, ENOMEM,
7270                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7271                                    NULL, "cannot create flow table object");
7272                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7273                 return NULL;
7274         }
7275         /*
7276          * No multi-threads now, but still better to initialize the reference
7277          * count before insert it into the hash list.
7278          */
7279         rte_atomic32_init(&tbl->refcnt);
7280         /* Jump action reference count is initialized here. */
7281         rte_atomic32_init(&tbl_data->jump.refcnt);
7282         pos->key = table_key.v64;
7283         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7284         if (ret < 0) {
7285                 rte_flow_error_set(error, -ret,
7286                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7287                                    "cannot insert flow table data entry");
7288                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7289                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7290         }
7291         rte_atomic32_inc(&tbl->refcnt);
7292         return tbl;
7293 }
7294
7295 /**
7296  * Release a flow table.
7297  *
7298  * @param[in] dev
7299  *   Pointer to rte_eth_dev structure.
7300  * @param[in] tbl
7301  *   Table resource to be released.
7302  *
7303  * @return
7304  *   Returns 0 if table was released, else return 1;
7305  */
7306 static int
7307 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7308                              struct mlx5_flow_tbl_resource *tbl)
7309 {
7310         struct mlx5_priv *priv = dev->data->dev_private;
7311         struct mlx5_ibv_shared *sh = priv->sh;
7312         struct mlx5_flow_tbl_data_entry *tbl_data =
7313                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7314
7315         if (!tbl)
7316                 return 0;
7317         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7318                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7319
7320                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7321                 tbl->obj = NULL;
7322                 /* remove the entry from the hash list and free memory. */
7323                 mlx5_hlist_remove(sh->flow_tbls, pos);
7324                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7325                                 tbl_data->idx);
7326                 return 0;
7327         }
7328         return 1;
7329 }
7330
7331 /**
7332  * Register the flow matcher.
7333  *
7334  * @param[in, out] dev
7335  *   Pointer to rte_eth_dev structure.
7336  * @param[in, out] matcher
7337  *   Pointer to flow matcher.
7338  * @param[in, out] key
7339  *   Pointer to flow table key.
7340  * @parm[in, out] dev_flow
7341  *   Pointer to the dev_flow.
7342  * @param[out] error
7343  *   pointer to error structure.
7344  *
7345  * @return
7346  *   0 on success otherwise -errno and errno is set.
7347  */
7348 static int
7349 flow_dv_matcher_register(struct rte_eth_dev *dev,
7350                          struct mlx5_flow_dv_matcher *matcher,
7351                          union mlx5_flow_tbl_key *key,
7352                          struct mlx5_flow *dev_flow,
7353                          struct rte_flow_error *error)
7354 {
7355         struct mlx5_priv *priv = dev->data->dev_private;
7356         struct mlx5_ibv_shared *sh = priv->sh;
7357         struct mlx5_flow_dv_matcher *cache_matcher;
7358         struct mlx5dv_flow_matcher_attr dv_attr = {
7359                 .type = IBV_FLOW_ATTR_NORMAL,
7360                 .match_mask = (void *)&matcher->mask,
7361         };
7362         struct mlx5_flow_tbl_resource *tbl;
7363         struct mlx5_flow_tbl_data_entry *tbl_data;
7364
7365         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7366                                        key->domain, error);
7367         if (!tbl)
7368                 return -rte_errno;      /* No need to refill the error info */
7369         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7370         /* Lookup from cache. */
7371         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7372                 if (matcher->crc == cache_matcher->crc &&
7373                     matcher->priority == cache_matcher->priority &&
7374                     !memcmp((const void *)matcher->mask.buf,
7375                             (const void *)cache_matcher->mask.buf,
7376                             cache_matcher->mask.size)) {
7377                         DRV_LOG(DEBUG,
7378                                 "%s group %u priority %hd use %s "
7379                                 "matcher %p: refcnt %d++",
7380                                 key->domain ? "FDB" : "NIC", key->table_id,
7381                                 cache_matcher->priority,
7382                                 key->direction ? "tx" : "rx",
7383                                 (void *)cache_matcher,
7384                                 rte_atomic32_read(&cache_matcher->refcnt));
7385                         rte_atomic32_inc(&cache_matcher->refcnt);
7386                         dev_flow->handle->dvh.matcher = cache_matcher;
7387                         /* old matcher should not make the table ref++. */
7388                         flow_dv_tbl_resource_release(dev, tbl);
7389                         return 0;
7390                 }
7391         }
7392         /* Register new matcher. */
7393         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7394         if (!cache_matcher) {
7395                 flow_dv_tbl_resource_release(dev, tbl);
7396                 return rte_flow_error_set(error, ENOMEM,
7397                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7398                                           "cannot allocate matcher memory");
7399         }
7400         *cache_matcher = *matcher;
7401         dv_attr.match_criteria_enable =
7402                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7403         dv_attr.priority = matcher->priority;
7404         if (key->direction)
7405                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7406         cache_matcher->matcher_object =
7407                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7408         if (!cache_matcher->matcher_object) {
7409                 rte_free(cache_matcher);
7410 #ifdef HAVE_MLX5DV_DR
7411                 flow_dv_tbl_resource_release(dev, tbl);
7412 #endif
7413                 return rte_flow_error_set(error, ENOMEM,
7414                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7415                                           NULL, "cannot create matcher");
7416         }
7417         /* Save the table information */
7418         cache_matcher->tbl = tbl;
7419         rte_atomic32_init(&cache_matcher->refcnt);
7420         /* only matcher ref++, table ref++ already done above in get API. */
7421         rte_atomic32_inc(&cache_matcher->refcnt);
7422         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7423         dev_flow->handle->dvh.matcher = cache_matcher;
7424         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7425                 key->domain ? "FDB" : "NIC", key->table_id,
7426                 cache_matcher->priority,
7427                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7428                 rte_atomic32_read(&cache_matcher->refcnt));
7429         return 0;
7430 }
7431
7432 /**
7433  * Find existing tag resource or create and register a new one.
7434  *
7435  * @param dev[in, out]
7436  *   Pointer to rte_eth_dev structure.
7437  * @param[in, out] tag_be24
7438  *   Tag value in big endian then R-shift 8.
7439  * @parm[in, out] dev_flow
7440  *   Pointer to the dev_flow.
7441  * @param[out] error
7442  *   pointer to error structure.
7443  *
7444  * @return
7445  *   0 on success otherwise -errno and errno is set.
7446  */
7447 static int
7448 flow_dv_tag_resource_register
7449                         (struct rte_eth_dev *dev,
7450                          uint32_t tag_be24,
7451                          struct mlx5_flow *dev_flow,
7452                          struct rte_flow_error *error)
7453 {
7454         struct mlx5_priv *priv = dev->data->dev_private;
7455         struct mlx5_ibv_shared *sh = priv->sh;
7456         struct mlx5_flow_dv_tag_resource *cache_resource;
7457         struct mlx5_hlist_entry *entry;
7458
7459         /* Lookup a matching resource from cache. */
7460         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7461         if (entry) {
7462                 cache_resource = container_of
7463                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7464                 rte_atomic32_inc(&cache_resource->refcnt);
7465                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7466                 dev_flow->dv.tag_resource = cache_resource;
7467                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7468                         (void *)cache_resource,
7469                         rte_atomic32_read(&cache_resource->refcnt));
7470                 return 0;
7471         }
7472         /* Register new resource. */
7473         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7474                                        &dev_flow->handle->dvh.rix_tag);
7475         if (!cache_resource)
7476                 return rte_flow_error_set(error, ENOMEM,
7477                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7478                                           "cannot allocate resource memory");
7479         cache_resource->entry.key = (uint64_t)tag_be24;
7480         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7481         if (!cache_resource->action) {
7482                 rte_free(cache_resource);
7483                 return rte_flow_error_set(error, ENOMEM,
7484                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7485                                           NULL, "cannot create action");
7486         }
7487         rte_atomic32_init(&cache_resource->refcnt);
7488         rte_atomic32_inc(&cache_resource->refcnt);
7489         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7490                 mlx5_glue->destroy_flow_action(cache_resource->action);
7491                 rte_free(cache_resource);
7492                 return rte_flow_error_set(error, EEXIST,
7493                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7494                                           NULL, "cannot insert tag");
7495         }
7496         dev_flow->dv.tag_resource = cache_resource;
7497         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7498                 (void *)cache_resource,
7499                 rte_atomic32_read(&cache_resource->refcnt));
7500         return 0;
7501 }
7502
7503 /**
7504  * Release the tag.
7505  *
7506  * @param dev
7507  *   Pointer to Ethernet device.
7508  * @param tag_idx
7509  *   Tag index.
7510  *
7511  * @return
7512  *   1 while a reference on it exists, 0 when freed.
7513  */
7514 static int
7515 flow_dv_tag_release(struct rte_eth_dev *dev,
7516                     uint32_t tag_idx)
7517 {
7518         struct mlx5_priv *priv = dev->data->dev_private;
7519         struct mlx5_ibv_shared *sh = priv->sh;
7520         struct mlx5_flow_dv_tag_resource *tag;
7521
7522         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7523         if (!tag)
7524                 return 0;
7525         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7526                 dev->data->port_id, (void *)tag,
7527                 rte_atomic32_read(&tag->refcnt));
7528         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7529                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7530                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7531                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7532                         dev->data->port_id, (void *)tag);
7533                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7534                 return 0;
7535         }
7536         return 1;
7537 }
7538
7539 /**
7540  * Translate port ID action to vport.
7541  *
7542  * @param[in] dev
7543  *   Pointer to rte_eth_dev structure.
7544  * @param[in] action
7545  *   Pointer to the port ID action.
7546  * @param[out] dst_port_id
7547  *   The target port ID.
7548  * @param[out] error
7549  *   Pointer to the error structure.
7550  *
7551  * @return
7552  *   0 on success, a negative errno value otherwise and rte_errno is set.
7553  */
7554 static int
7555 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7556                                  const struct rte_flow_action *action,
7557                                  uint32_t *dst_port_id,
7558                                  struct rte_flow_error *error)
7559 {
7560         uint32_t port;
7561         struct mlx5_priv *priv;
7562         const struct rte_flow_action_port_id *conf =
7563                         (const struct rte_flow_action_port_id *)action->conf;
7564
7565         port = conf->original ? dev->data->port_id : conf->id;
7566         priv = mlx5_port_to_eswitch_info(port, false);
7567         if (!priv)
7568                 return rte_flow_error_set(error, -rte_errno,
7569                                           RTE_FLOW_ERROR_TYPE_ACTION,
7570                                           NULL,
7571                                           "No eswitch info was found for port");
7572 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7573         /*
7574          * This parameter is transferred to
7575          * mlx5dv_dr_action_create_dest_ib_port().
7576          */
7577         *dst_port_id = priv->ibv_port;
7578 #else
7579         /*
7580          * Legacy mode, no LAG configurations is supported.
7581          * This parameter is transferred to
7582          * mlx5dv_dr_action_create_dest_vport().
7583          */
7584         *dst_port_id = priv->vport_id;
7585 #endif
7586         return 0;
7587 }
7588
7589 /**
7590  * Create a counter with aging configuration.
7591  *
7592  * @param[in] dev
7593  *   Pointer to rte_eth_dev structure.
7594  * @param[out] count
7595  *   Pointer to the counter action configuration.
7596  * @param[in] age
7597  *   Pointer to the aging action configuration.
7598  *
7599  * @return
7600  *   Index to flow counter on success, 0 otherwise.
7601  */
7602 static uint32_t
7603 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7604                                 struct mlx5_flow *dev_flow,
7605                                 const struct rte_flow_action_count *count,
7606                                 const struct rte_flow_action_age *age)
7607 {
7608         uint32_t counter;
7609         struct mlx5_age_param *age_param;
7610
7611         counter = flow_dv_counter_alloc(dev,
7612                                 count ? count->shared : 0,
7613                                 count ? count->id : 0,
7614                                 dev_flow->dv.group, !!age);
7615         if (!counter || age == NULL)
7616                 return counter;
7617         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7618         /*
7619          * The counter age accuracy may have a bit delay. Have 3/4
7620          * second bias on the timeount in order to let it age in time.
7621          */
7622         age_param->context = age->context ? age->context :
7623                 (void *)(uintptr_t)(dev_flow->flow_idx);
7624         /*
7625          * The counter age accuracy may have a bit delay. Have 3/4
7626          * second bias on the timeount in order to let it age in time.
7627          */
7628         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7629         /* Set expire time in unit of 0.1 sec. */
7630         age_param->port_id = dev->data->port_id;
7631         age_param->expire = age_param->timeout +
7632                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7633         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7634         return counter;
7635 }
7636 /**
7637  * Add Tx queue matcher
7638  *
7639  * @param[in] dev
7640  *   Pointer to the dev struct.
7641  * @param[in, out] matcher
7642  *   Flow matcher.
7643  * @param[in, out] key
7644  *   Flow matcher value.
7645  * @param[in] item
7646  *   Flow pattern to translate.
7647  * @param[in] inner
7648  *   Item is inner pattern.
7649  */
7650 static void
7651 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7652                                 void *matcher, void *key,
7653                                 const struct rte_flow_item *item)
7654 {
7655         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7656         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7657         void *misc_m =
7658                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7659         void *misc_v =
7660                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7661         struct mlx5_txq_ctrl *txq;
7662         uint32_t queue;
7663
7664
7665         queue_m = (const void *)item->mask;
7666         if (!queue_m)
7667                 return;
7668         queue_v = (const void *)item->spec;
7669         if (!queue_v)
7670                 return;
7671         txq = mlx5_txq_get(dev, queue_v->queue);
7672         if (!txq)
7673                 return;
7674         queue = txq->obj->sq->id;
7675         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7676         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7677                  queue & queue_m->queue);
7678         mlx5_txq_release(dev, queue_v->queue);
7679 }
7680
7681 /**
7682  * Set the hash fields according to the @p flow information.
7683  *
7684  * @param[in] dev_flow
7685  *   Pointer to the mlx5_flow.
7686  * @param[in] rss_desc
7687  *   Pointer to the mlx5_flow_rss_desc.
7688  */
7689 static void
7690 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7691                        struct mlx5_flow_rss_desc *rss_desc)
7692 {
7693         uint64_t items = dev_flow->handle->layers;
7694         int rss_inner = 0;
7695         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7696
7697         dev_flow->hash_fields = 0;
7698 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7699         if (rss_desc->level >= 2) {
7700                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7701                 rss_inner = 1;
7702         }
7703 #endif
7704         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7705             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7706                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7707                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7708                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7709                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7710                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7711                         else
7712                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7713                 }
7714         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7715                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7716                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7717                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7718                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7719                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7720                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7721                         else
7722                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7723                 }
7724         }
7725         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7726             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7727                 if (rss_types & ETH_RSS_UDP) {
7728                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7729                                 dev_flow->hash_fields |=
7730                                                 IBV_RX_HASH_SRC_PORT_UDP;
7731                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7732                                 dev_flow->hash_fields |=
7733                                                 IBV_RX_HASH_DST_PORT_UDP;
7734                         else
7735                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7736                 }
7737         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7738                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7739                 if (rss_types & ETH_RSS_TCP) {
7740                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7741                                 dev_flow->hash_fields |=
7742                                                 IBV_RX_HASH_SRC_PORT_TCP;
7743                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7744                                 dev_flow->hash_fields |=
7745                                                 IBV_RX_HASH_DST_PORT_TCP;
7746                         else
7747                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7748                 }
7749         }
7750 }
7751
7752 /**
7753  * Fill the flow with DV spec, lock free
7754  * (mutex should be acquired by caller).
7755  *
7756  * @param[in] dev
7757  *   Pointer to rte_eth_dev structure.
7758  * @param[in, out] dev_flow
7759  *   Pointer to the sub flow.
7760  * @param[in] attr
7761  *   Pointer to the flow attributes.
7762  * @param[in] items
7763  *   Pointer to the list of items.
7764  * @param[in] actions
7765  *   Pointer to the list of actions.
7766  * @param[out] error
7767  *   Pointer to the error structure.
7768  *
7769  * @return
7770  *   0 on success, a negative errno value otherwise and rte_errno is set.
7771  */
7772 static int
7773 __flow_dv_translate(struct rte_eth_dev *dev,
7774                     struct mlx5_flow *dev_flow,
7775                     const struct rte_flow_attr *attr,
7776                     const struct rte_flow_item items[],
7777                     const struct rte_flow_action actions[],
7778                     struct rte_flow_error *error)
7779 {
7780         struct mlx5_priv *priv = dev->data->dev_private;
7781         struct mlx5_dev_config *dev_conf = &priv->config;
7782         struct rte_flow *flow = dev_flow->flow;
7783         struct mlx5_flow_handle *handle = dev_flow->handle;
7784         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7785                                               priv->rss_desc)
7786                                               [!!priv->flow_nested_idx];
7787         uint64_t item_flags = 0;
7788         uint64_t last_item = 0;
7789         uint64_t action_flags = 0;
7790         uint64_t priority = attr->priority;
7791         struct mlx5_flow_dv_matcher matcher = {
7792                 .mask = {
7793                         .size = sizeof(matcher.mask.buf),
7794                 },
7795         };
7796         int actions_n = 0;
7797         bool actions_end = false;
7798         union {
7799                 struct mlx5_flow_dv_modify_hdr_resource res;
7800                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7801                             sizeof(struct mlx5_modification_cmd) *
7802                             (MLX5_MAX_MODIFY_NUM + 1)];
7803         } mhdr_dummy;
7804         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7805         const struct rte_flow_action_count *count = NULL;
7806         const struct rte_flow_action_age *age = NULL;
7807         union flow_dv_attr flow_attr = { .attr = 0 };
7808         uint32_t tag_be;
7809         union mlx5_flow_tbl_key tbl_key;
7810         uint32_t modify_action_position = UINT32_MAX;
7811         void *match_mask = matcher.mask.buf;
7812         void *match_value = dev_flow->dv.value.buf;
7813         uint8_t next_protocol = 0xff;
7814         struct rte_vlan_hdr vlan = { 0 };
7815         uint32_t table;
7816         int ret = 0;
7817
7818         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7819                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7820         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7821                                        !!priv->fdb_def_rule, &table, error);
7822         if (ret)
7823                 return ret;
7824         dev_flow->dv.group = table;
7825         if (attr->transfer)
7826                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7827         if (priority == MLX5_FLOW_PRIO_RSVD)
7828                 priority = dev_conf->flow_prio - 1;
7829         /* number of actions must be set to 0 in case of dirty stack. */
7830         mhdr_res->actions_num = 0;
7831         for (; !actions_end ; actions++) {
7832                 const struct rte_flow_action_queue *queue;
7833                 const struct rte_flow_action_rss *rss;
7834                 const struct rte_flow_action *action = actions;
7835                 const uint8_t *rss_key;
7836                 const struct rte_flow_action_jump *jump_data;
7837                 const struct rte_flow_action_meter *mtr;
7838                 struct mlx5_flow_tbl_resource *tbl;
7839                 uint32_t port_id = 0;
7840                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7841                 int action_type = actions->type;
7842                 const struct rte_flow_action *found_action = NULL;
7843                 struct mlx5_flow_meter *fm = NULL;
7844
7845                 switch (action_type) {
7846                 case RTE_FLOW_ACTION_TYPE_VOID:
7847                         break;
7848                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7849                         if (flow_dv_translate_action_port_id(dev, action,
7850                                                              &port_id, error))
7851                                 return -rte_errno;
7852                         memset(&port_id_resource, 0, sizeof(port_id_resource));
7853                         port_id_resource.port_id = port_id;
7854                         if (flow_dv_port_id_action_resource_register
7855                             (dev, &port_id_resource, dev_flow, error))
7856                                 return -rte_errno;
7857                         MLX5_ASSERT(!handle->rix_port_id_action);
7858                         dev_flow->dv.actions[actions_n++] =
7859                                         dev_flow->dv.port_id_action->action;
7860                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7861                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7862                         break;
7863                 case RTE_FLOW_ACTION_TYPE_FLAG:
7864                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7865                         dev_flow->handle->mark = 1;
7866                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7867                                 struct rte_flow_action_mark mark = {
7868                                         .id = MLX5_FLOW_MARK_DEFAULT,
7869                                 };
7870
7871                                 if (flow_dv_convert_action_mark(dev, &mark,
7872                                                                 mhdr_res,
7873                                                                 error))
7874                                         return -rte_errno;
7875                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7876                                 break;
7877                         }
7878                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7879                         /*
7880                          * Only one FLAG or MARK is supported per device flow
7881                          * right now. So the pointer to the tag resource must be
7882                          * zero before the register process.
7883                          */
7884                         MLX5_ASSERT(!handle->dvh.rix_tag);
7885                         if (flow_dv_tag_resource_register(dev, tag_be,
7886                                                           dev_flow, error))
7887                                 return -rte_errno;
7888                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7889                         dev_flow->dv.actions[actions_n++] =
7890                                         dev_flow->dv.tag_resource->action;
7891                         break;
7892                 case RTE_FLOW_ACTION_TYPE_MARK:
7893                         action_flags |= MLX5_FLOW_ACTION_MARK;
7894                         dev_flow->handle->mark = 1;
7895                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7896                                 const struct rte_flow_action_mark *mark =
7897                                         (const struct rte_flow_action_mark *)
7898                                                 actions->conf;
7899
7900                                 if (flow_dv_convert_action_mark(dev, mark,
7901                                                                 mhdr_res,
7902                                                                 error))
7903                                         return -rte_errno;
7904                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7905                                 break;
7906                         }
7907                         /* Fall-through */
7908                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7909                         /* Legacy (non-extensive) MARK action. */
7910                         tag_be = mlx5_flow_mark_set
7911                               (((const struct rte_flow_action_mark *)
7912                                (actions->conf))->id);
7913                         MLX5_ASSERT(!handle->dvh.rix_tag);
7914                         if (flow_dv_tag_resource_register(dev, tag_be,
7915                                                           dev_flow, error))
7916                                 return -rte_errno;
7917                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7918                         dev_flow->dv.actions[actions_n++] =
7919                                         dev_flow->dv.tag_resource->action;
7920                         break;
7921                 case RTE_FLOW_ACTION_TYPE_SET_META:
7922                         if (flow_dv_convert_action_set_meta
7923                                 (dev, mhdr_res, attr,
7924                                  (const struct rte_flow_action_set_meta *)
7925                                   actions->conf, error))
7926                                 return -rte_errno;
7927                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7928                         break;
7929                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7930                         if (flow_dv_convert_action_set_tag
7931                                 (dev, mhdr_res,
7932                                  (const struct rte_flow_action_set_tag *)
7933                                   actions->conf, error))
7934                                 return -rte_errno;
7935                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7936                         break;
7937                 case RTE_FLOW_ACTION_TYPE_DROP:
7938                         action_flags |= MLX5_FLOW_ACTION_DROP;
7939                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7940                         break;
7941                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7942                         queue = actions->conf;
7943                         rss_desc->queue_num = 1;
7944                         rss_desc->queue[0] = queue->index;
7945                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7946                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7947                         break;
7948                 case RTE_FLOW_ACTION_TYPE_RSS:
7949                         rss = actions->conf;
7950                         memcpy(rss_desc->queue, rss->queue,
7951                                rss->queue_num * sizeof(uint16_t));
7952                         rss_desc->queue_num = rss->queue_num;
7953                         /* NULL RSS key indicates default RSS key. */
7954                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7955                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7956                         /*
7957                          * rss->level and rss.types should be set in advance
7958                          * when expanding items for RSS.
7959                          */
7960                         action_flags |= MLX5_FLOW_ACTION_RSS;
7961                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7962                         break;
7963                 case RTE_FLOW_ACTION_TYPE_AGE:
7964                 case RTE_FLOW_ACTION_TYPE_COUNT:
7965                         if (!dev_conf->devx) {
7966                                 return rte_flow_error_set
7967                                               (error, ENOTSUP,
7968                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7969                                                NULL,
7970                                                "count action not supported");
7971                         }
7972                         /* Save information first, will apply later. */
7973                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7974                                 count = action->conf;
7975                         else
7976                                 age = action->conf;
7977                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7978                         break;
7979                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7980                         dev_flow->dv.actions[actions_n++] =
7981                                                 priv->sh->pop_vlan_action;
7982                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7983                         break;
7984                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7985                         if (!(action_flags &
7986                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
7987                                 flow_dev_get_vlan_info_from_items(items, &vlan);
7988                         vlan.eth_proto = rte_be_to_cpu_16
7989                              ((((const struct rte_flow_action_of_push_vlan *)
7990                                                    actions->conf)->ethertype));
7991                         found_action = mlx5_flow_find_action
7992                                         (actions + 1,
7993                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7994                         if (found_action)
7995                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7996                         found_action = mlx5_flow_find_action
7997                                         (actions + 1,
7998                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7999                         if (found_action)
8000                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8001                         if (flow_dv_create_action_push_vlan
8002                                             (dev, attr, &vlan, dev_flow, error))
8003                                 return -rte_errno;
8004                         dev_flow->dv.actions[actions_n++] =
8005                                         dev_flow->dv.push_vlan_res->action;
8006                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8007                         break;
8008                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8009                         /* of_vlan_push action handled this action */
8010                         MLX5_ASSERT(action_flags &
8011                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8012                         break;
8013                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8014                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8015                                 break;
8016                         flow_dev_get_vlan_info_from_items(items, &vlan);
8017                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8018                         /* If no VLAN push - this is a modify header action */
8019                         if (flow_dv_convert_action_modify_vlan_vid
8020                                                 (mhdr_res, actions, error))
8021                                 return -rte_errno;
8022                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8023                         break;
8024                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8025                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8026                         if (flow_dv_create_action_l2_encap(dev, actions,
8027                                                            dev_flow,
8028                                                            attr->transfer,
8029                                                            error))
8030                                 return -rte_errno;
8031                         dev_flow->dv.actions[actions_n++] =
8032                                         dev_flow->dv.encap_decap->verbs_action;
8033                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8034                         break;
8035                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8036                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8037                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8038                                                            attr->transfer,
8039                                                            error))
8040                                 return -rte_errno;
8041                         dev_flow->dv.actions[actions_n++] =
8042                                         dev_flow->dv.encap_decap->verbs_action;
8043                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8044                         break;
8045                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8046                         /* Handle encap with preceding decap. */
8047                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8048                                 if (flow_dv_create_action_raw_encap
8049                                         (dev, actions, dev_flow, attr, error))
8050                                         return -rte_errno;
8051                                 dev_flow->dv.actions[actions_n++] =
8052                                         dev_flow->dv.encap_decap->verbs_action;
8053                         } else {
8054                                 /* Handle encap without preceding decap. */
8055                                 if (flow_dv_create_action_l2_encap
8056                                     (dev, actions, dev_flow, attr->transfer,
8057                                      error))
8058                                         return -rte_errno;
8059                                 dev_flow->dv.actions[actions_n++] =
8060                                         dev_flow->dv.encap_decap->verbs_action;
8061                         }
8062                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8063                         break;
8064                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8065                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8066                                 ;
8067                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8068                                 if (flow_dv_create_action_l2_decap
8069                                     (dev, dev_flow, attr->transfer, error))
8070                                         return -rte_errno;
8071                                 dev_flow->dv.actions[actions_n++] =
8072                                         dev_flow->dv.encap_decap->verbs_action;
8073                         }
8074                         /* If decap is followed by encap, handle it at encap. */
8075                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8076                         break;
8077                 case RTE_FLOW_ACTION_TYPE_JUMP:
8078                         jump_data = action->conf;
8079                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8080                                                        jump_data->group,
8081                                                        !!priv->fdb_def_rule,
8082                                                        &table, error);
8083                         if (ret)
8084                                 return ret;
8085                         tbl = flow_dv_tbl_resource_get(dev, table,
8086                                                        attr->egress,
8087                                                        attr->transfer, error);
8088                         if (!tbl)
8089                                 return rte_flow_error_set
8090                                                 (error, errno,
8091                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8092                                                  NULL,
8093                                                  "cannot create jump action.");
8094                         if (flow_dv_jump_tbl_resource_register
8095                             (dev, tbl, dev_flow, error)) {
8096                                 flow_dv_tbl_resource_release(dev, tbl);
8097                                 return rte_flow_error_set
8098                                                 (error, errno,
8099                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8100                                                  NULL,
8101                                                  "cannot create jump action.");
8102                         }
8103                         dev_flow->dv.actions[actions_n++] =
8104                                         dev_flow->dv.jump->action;
8105                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8106                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8107                         break;
8108                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8109                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8110                         if (flow_dv_convert_action_modify_mac
8111                                         (mhdr_res, actions, error))
8112                                 return -rte_errno;
8113                         action_flags |= actions->type ==
8114                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8115                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8116                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8117                         break;
8118                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8119                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8120                         if (flow_dv_convert_action_modify_ipv4
8121                                         (mhdr_res, actions, error))
8122                                 return -rte_errno;
8123                         action_flags |= actions->type ==
8124                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8125                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8126                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8127                         break;
8128                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8129                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8130                         if (flow_dv_convert_action_modify_ipv6
8131                                         (mhdr_res, actions, error))
8132                                 return -rte_errno;
8133                         action_flags |= actions->type ==
8134                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8135                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8136                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8137                         break;
8138                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8139                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8140                         if (flow_dv_convert_action_modify_tp
8141                                         (mhdr_res, actions, items,
8142                                          &flow_attr, dev_flow, !!(action_flags &
8143                                          MLX5_FLOW_ACTION_DECAP), error))
8144                                 return -rte_errno;
8145                         action_flags |= actions->type ==
8146                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8147                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8148                                         MLX5_FLOW_ACTION_SET_TP_DST;
8149                         break;
8150                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8151                         if (flow_dv_convert_action_modify_dec_ttl
8152                                         (mhdr_res, items, &flow_attr, dev_flow,
8153                                          !!(action_flags &
8154                                          MLX5_FLOW_ACTION_DECAP), error))
8155                                 return -rte_errno;
8156                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8157                         break;
8158                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8159                         if (flow_dv_convert_action_modify_ttl
8160                                         (mhdr_res, actions, items, &flow_attr,
8161                                          dev_flow, !!(action_flags &
8162                                          MLX5_FLOW_ACTION_DECAP), error))
8163                                 return -rte_errno;
8164                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8165                         break;
8166                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8167                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8168                         if (flow_dv_convert_action_modify_tcp_seq
8169                                         (mhdr_res, actions, error))
8170                                 return -rte_errno;
8171                         action_flags |= actions->type ==
8172                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8173                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8174                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8175                         break;
8176
8177                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8178                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8179                         if (flow_dv_convert_action_modify_tcp_ack
8180                                         (mhdr_res, actions, error))
8181                                 return -rte_errno;
8182                         action_flags |= actions->type ==
8183                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8184                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8185                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8186                         break;
8187                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8188                         if (flow_dv_convert_action_set_reg
8189                                         (mhdr_res, actions, error))
8190                                 return -rte_errno;
8191                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8192                         break;
8193                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8194                         if (flow_dv_convert_action_copy_mreg
8195                                         (dev, mhdr_res, actions, error))
8196                                 return -rte_errno;
8197                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8198                         break;
8199                 case RTE_FLOW_ACTION_TYPE_METER:
8200                         mtr = actions->conf;
8201                         if (!flow->meter) {
8202                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8203                                                             attr, error);
8204                                 if (!fm)
8205                                         return rte_flow_error_set(error,
8206                                                 rte_errno,
8207                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8208                                                 NULL,
8209                                                 "meter not found "
8210                                                 "or invalid parameters");
8211                                 flow->meter = fm->idx;
8212                         }
8213                         /* Set the meter action. */
8214                         if (!fm) {
8215                                 fm = mlx5_ipool_get(priv->sh->ipool
8216                                                 [MLX5_IPOOL_MTR], flow->meter);
8217                                 if (!fm)
8218                                         return rte_flow_error_set(error,
8219                                                 rte_errno,
8220                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8221                                                 NULL,
8222                                                 "meter not found "
8223                                                 "or invalid parameters");
8224                         }
8225                         dev_flow->dv.actions[actions_n++] =
8226                                 fm->mfts->meter_action;
8227                         action_flags |= MLX5_FLOW_ACTION_METER;
8228                         break;
8229                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8230                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8231                                                               actions, error))
8232                                 return -rte_errno;
8233                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8234                         break;
8235                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8236                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8237                                                               actions, error))
8238                                 return -rte_errno;
8239                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8240                         break;
8241                 case RTE_FLOW_ACTION_TYPE_END:
8242                         actions_end = true;
8243                         if (mhdr_res->actions_num) {
8244                                 /* create modify action if needed. */
8245                                 if (flow_dv_modify_hdr_resource_register
8246                                         (dev, mhdr_res, dev_flow, error))
8247                                         return -rte_errno;
8248                                 dev_flow->dv.actions[modify_action_position] =
8249                                         handle->dvh.modify_hdr->verbs_action;
8250                         }
8251                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8252                                 flow->counter =
8253                                         flow_dv_translate_create_counter(dev,
8254                                                 dev_flow, count, age);
8255
8256                                 if (!flow->counter)
8257                                         return rte_flow_error_set
8258                                                 (error, rte_errno,
8259                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8260                                                 NULL,
8261                                                 "cannot create counter"
8262                                                 " object.");
8263                                 dev_flow->dv.actions[actions_n++] =
8264                                           (flow_dv_counter_get_by_idx(dev,
8265                                           flow->counter, NULL))->action;
8266                         }
8267                         break;
8268                 default:
8269                         break;
8270                 }
8271                 if (mhdr_res->actions_num &&
8272                     modify_action_position == UINT32_MAX)
8273                         modify_action_position = actions_n++;
8274         }
8275         dev_flow->dv.actions_n = actions_n;
8276         dev_flow->act_flags = action_flags;
8277         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8278                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8279                 int item_type = items->type;
8280
8281                 switch (item_type) {
8282                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8283                         flow_dv_translate_item_port_id(dev, match_mask,
8284                                                        match_value, items);
8285                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8286                         break;
8287                 case RTE_FLOW_ITEM_TYPE_ETH:
8288                         flow_dv_translate_item_eth(match_mask, match_value,
8289                                                    items, tunnel,
8290                                                    dev_flow->dv.group);
8291                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8292                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8293                                              MLX5_FLOW_LAYER_OUTER_L2;
8294                         break;
8295                 case RTE_FLOW_ITEM_TYPE_VLAN:
8296                         flow_dv_translate_item_vlan(dev_flow,
8297                                                     match_mask, match_value,
8298                                                     items, tunnel,
8299                                                     dev_flow->dv.group);
8300                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8301                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8302                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8303                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8304                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8305                         break;
8306                 case RTE_FLOW_ITEM_TYPE_IPV4:
8307                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8308                                                   &item_flags, &tunnel);
8309                         flow_dv_translate_item_ipv4(match_mask, match_value,
8310                                                     items, item_flags, tunnel,
8311                                                     dev_flow->dv.group);
8312                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8313                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8314                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8315                         if (items->mask != NULL &&
8316                             ((const struct rte_flow_item_ipv4 *)
8317                              items->mask)->hdr.next_proto_id) {
8318                                 next_protocol =
8319                                         ((const struct rte_flow_item_ipv4 *)
8320                                          (items->spec))->hdr.next_proto_id;
8321                                 next_protocol &=
8322                                         ((const struct rte_flow_item_ipv4 *)
8323                                          (items->mask))->hdr.next_proto_id;
8324                         } else {
8325                                 /* Reset for inner layer. */
8326                                 next_protocol = 0xff;
8327                         }
8328                         break;
8329                 case RTE_FLOW_ITEM_TYPE_IPV6:
8330                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8331                                                   &item_flags, &tunnel);
8332                         flow_dv_translate_item_ipv6(match_mask, match_value,
8333                                                     items, item_flags, tunnel,
8334                                                     dev_flow->dv.group);
8335                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8336                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8337                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8338                         if (items->mask != NULL &&
8339                             ((const struct rte_flow_item_ipv6 *)
8340                              items->mask)->hdr.proto) {
8341                                 next_protocol =
8342                                         ((const struct rte_flow_item_ipv6 *)
8343                                          items->spec)->hdr.proto;
8344                                 next_protocol &=
8345                                         ((const struct rte_flow_item_ipv6 *)
8346                                          items->mask)->hdr.proto;
8347                         } else {
8348                                 /* Reset for inner layer. */
8349                                 next_protocol = 0xff;
8350                         }
8351                         break;
8352                 case RTE_FLOW_ITEM_TYPE_TCP:
8353                         flow_dv_translate_item_tcp(match_mask, match_value,
8354                                                    items, tunnel);
8355                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8356                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8357                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8358                         break;
8359                 case RTE_FLOW_ITEM_TYPE_UDP:
8360                         flow_dv_translate_item_udp(match_mask, match_value,
8361                                                    items, tunnel);
8362                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8363                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8364                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8365                         break;
8366                 case RTE_FLOW_ITEM_TYPE_GRE:
8367                         flow_dv_translate_item_gre(match_mask, match_value,
8368                                                    items, tunnel);
8369                         matcher.priority = rss_desc->level >= 2 ?
8370                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8371                         last_item = MLX5_FLOW_LAYER_GRE;
8372                         break;
8373                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8374                         flow_dv_translate_item_gre_key(match_mask,
8375                                                        match_value, items);
8376                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8377                         break;
8378                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8379                         flow_dv_translate_item_nvgre(match_mask, match_value,
8380                                                      items, tunnel);
8381                         matcher.priority = rss_desc->level >= 2 ?
8382                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8383                         last_item = MLX5_FLOW_LAYER_GRE;
8384                         break;
8385                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8386                         flow_dv_translate_item_vxlan(match_mask, match_value,
8387                                                      items, tunnel);
8388                         matcher.priority = rss_desc->level >= 2 ?
8389                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8390                         last_item = MLX5_FLOW_LAYER_VXLAN;
8391                         break;
8392                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8393                         flow_dv_translate_item_vxlan_gpe(match_mask,
8394                                                          match_value, items,
8395                                                          tunnel);
8396                         matcher.priority = rss_desc->level >= 2 ?
8397                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8398                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8399                         break;
8400                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8401                         flow_dv_translate_item_geneve(match_mask, match_value,
8402                                                       items, tunnel);
8403                         matcher.priority = rss_desc->level >= 2 ?
8404                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8405                         last_item = MLX5_FLOW_LAYER_GENEVE;
8406                         break;
8407                 case RTE_FLOW_ITEM_TYPE_MPLS:
8408                         flow_dv_translate_item_mpls(match_mask, match_value,
8409                                                     items, last_item, tunnel);
8410                         matcher.priority = rss_desc->level >= 2 ?
8411                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8412                         last_item = MLX5_FLOW_LAYER_MPLS;
8413                         break;
8414                 case RTE_FLOW_ITEM_TYPE_MARK:
8415                         flow_dv_translate_item_mark(dev, match_mask,
8416                                                     match_value, items);
8417                         last_item = MLX5_FLOW_ITEM_MARK;
8418                         break;
8419                 case RTE_FLOW_ITEM_TYPE_META:
8420                         flow_dv_translate_item_meta(dev, match_mask,
8421                                                     match_value, attr, items);
8422                         last_item = MLX5_FLOW_ITEM_METADATA;
8423                         break;
8424                 case RTE_FLOW_ITEM_TYPE_ICMP:
8425                         flow_dv_translate_item_icmp(match_mask, match_value,
8426                                                     items, tunnel);
8427                         last_item = MLX5_FLOW_LAYER_ICMP;
8428                         break;
8429                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8430                         flow_dv_translate_item_icmp6(match_mask, match_value,
8431                                                       items, tunnel);
8432                         last_item = MLX5_FLOW_LAYER_ICMP6;
8433                         break;
8434                 case RTE_FLOW_ITEM_TYPE_TAG:
8435                         flow_dv_translate_item_tag(dev, match_mask,
8436                                                    match_value, items);
8437                         last_item = MLX5_FLOW_ITEM_TAG;
8438                         break;
8439                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8440                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8441                                                         match_value, items);
8442                         last_item = MLX5_FLOW_ITEM_TAG;
8443                         break;
8444                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8445                         flow_dv_translate_item_tx_queue(dev, match_mask,
8446                                                         match_value,
8447                                                         items);
8448                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8449                         break;
8450                 case RTE_FLOW_ITEM_TYPE_GTP:
8451                         flow_dv_translate_item_gtp(match_mask, match_value,
8452                                                    items, tunnel);
8453                         matcher.priority = rss_desc->level >= 2 ?
8454                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8455                         last_item = MLX5_FLOW_LAYER_GTP;
8456                         break;
8457                 default:
8458                         break;
8459                 }
8460                 item_flags |= last_item;
8461         }
8462         /*
8463          * When E-Switch mode is enabled, we have two cases where we need to
8464          * set the source port manually.
8465          * The first one, is in case of Nic steering rule, and the second is
8466          * E-Switch rule where no port_id item was found. In both cases
8467          * the source port is set according the current port in use.
8468          */
8469         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8470             (priv->representor || priv->master)) {
8471                 if (flow_dv_translate_item_port_id(dev, match_mask,
8472                                                    match_value, NULL))
8473                         return -rte_errno;
8474         }
8475 #ifdef RTE_LIBRTE_MLX5_DEBUG
8476         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8477                                               dev_flow->dv.value.buf));
8478 #endif
8479         /*
8480          * Layers may be already initialized from prefix flow if this dev_flow
8481          * is the suffix flow.
8482          */
8483         handle->layers |= item_flags;
8484         if (action_flags & MLX5_FLOW_ACTION_RSS)
8485                 flow_dv_hashfields_set(dev_flow, rss_desc);
8486         /* Register matcher. */
8487         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8488                                     matcher.mask.size);
8489         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8490                                                      matcher.priority);
8491         /* reserved field no needs to be set to 0 here. */
8492         tbl_key.domain = attr->transfer;
8493         tbl_key.direction = attr->egress;
8494         tbl_key.table_id = dev_flow->dv.group;
8495         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8496                 return -rte_errno;
8497         return 0;
8498 }
8499
8500 /**
8501  * Apply the flow to the NIC, lock free,
8502  * (mutex should be acquired by caller).
8503  *
8504  * @param[in] dev
8505  *   Pointer to the Ethernet device structure.
8506  * @param[in, out] flow
8507  *   Pointer to flow structure.
8508  * @param[out] error
8509  *   Pointer to error structure.
8510  *
8511  * @return
8512  *   0 on success, a negative errno value otherwise and rte_errno is set.
8513  */
8514 static int
8515 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8516                 struct rte_flow_error *error)
8517 {
8518         struct mlx5_flow_dv_workspace *dv;
8519         struct mlx5_flow_handle *dh;
8520         struct mlx5_flow_handle_dv *dv_h;
8521         struct mlx5_flow *dev_flow;
8522         struct mlx5_priv *priv = dev->data->dev_private;
8523         uint32_t handle_idx;
8524         int n;
8525         int err;
8526         int idx;
8527
8528         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8529                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8530                 dv = &dev_flow->dv;
8531                 dh = dev_flow->handle;
8532                 dv_h = &dh->dvh;
8533                 n = dv->actions_n;
8534                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8535                         if (dv->transfer) {
8536                                 dv->actions[n++] = priv->sh->esw_drop_action;
8537                         } else {
8538                                 struct mlx5_hrxq *drop_hrxq;
8539                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8540                                 if (!drop_hrxq) {
8541                                         rte_flow_error_set
8542                                                 (error, errno,
8543                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8544                                                  NULL,
8545                                                  "cannot get drop hash queue");
8546                                         goto error;
8547                                 }
8548                                 /*
8549                                  * Drop queues will be released by the specify
8550                                  * mlx5_hrxq_drop_release() function. Assign
8551                                  * the special index to hrxq to mark the queue
8552                                  * has been allocated.
8553                                  */
8554                                 dh->rix_hrxq = UINT32_MAX;
8555                                 dv->actions[n++] = drop_hrxq->action;
8556                         }
8557                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8558                         struct mlx5_hrxq *hrxq;
8559                         uint32_t hrxq_idx;
8560                         struct mlx5_flow_rss_desc *rss_desc =
8561                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8562                                 [!!priv->flow_nested_idx];
8563
8564                         MLX5_ASSERT(rss_desc->queue_num);
8565                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8566                                                  MLX5_RSS_HASH_KEY_LEN,
8567                                                  dev_flow->hash_fields,
8568                                                  rss_desc->queue,
8569                                                  rss_desc->queue_num);
8570                         if (!hrxq_idx) {
8571                                 hrxq_idx = mlx5_hrxq_new
8572                                                 (dev, rss_desc->key,
8573                                                 MLX5_RSS_HASH_KEY_LEN,
8574                                                 dev_flow->hash_fields,
8575                                                 rss_desc->queue,
8576                                                 rss_desc->queue_num,
8577                                                 !!(dh->layers &
8578                                                 MLX5_FLOW_LAYER_TUNNEL));
8579                         }
8580                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8581                                               hrxq_idx);
8582                         if (!hrxq) {
8583                                 rte_flow_error_set
8584                                         (error, rte_errno,
8585                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8586                                          "cannot get hash queue");
8587                                 goto error;
8588                         }
8589                         dh->rix_hrxq = hrxq_idx;
8590                         dv->actions[n++] = hrxq->action;
8591                 }
8592                 dh->ib_flow =
8593                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8594                                                   (void *)&dv->value, n,
8595                                                   dv->actions);
8596                 if (!dh->ib_flow) {
8597                         rte_flow_error_set(error, errno,
8598                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8599                                            NULL,
8600                                            "hardware refuses to create flow");
8601                         goto error;
8602                 }
8603                 if (priv->vmwa_context &&
8604                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8605                         /*
8606                          * The rule contains the VLAN pattern.
8607                          * For VF we are going to create VLAN
8608                          * interface to make hypervisor set correct
8609                          * e-Switch vport context.
8610                          */
8611                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8612                 }
8613         }
8614         return 0;
8615 error:
8616         err = rte_errno; /* Save rte_errno before cleanup. */
8617         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8618                        handle_idx, dh, next) {
8619                 /* hrxq is union, don't clear it if the flag is not set. */
8620                 if (dh->rix_hrxq) {
8621                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8622                                 mlx5_hrxq_drop_release(dev);
8623                                 dh->rix_hrxq = 0;
8624                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8625                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8626                                 dh->rix_hrxq = 0;
8627                         }
8628                 }
8629                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8630                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8631         }
8632         rte_errno = err; /* Restore rte_errno. */
8633         return -rte_errno;
8634 }
8635
8636 /**
8637  * Release the flow matcher.
8638  *
8639  * @param dev
8640  *   Pointer to Ethernet device.
8641  * @param handle
8642  *   Pointer to mlx5_flow_handle.
8643  *
8644  * @return
8645  *   1 while a reference on it exists, 0 when freed.
8646  */
8647 static int
8648 flow_dv_matcher_release(struct rte_eth_dev *dev,
8649                         struct mlx5_flow_handle *handle)
8650 {
8651         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8652
8653         MLX5_ASSERT(matcher->matcher_object);
8654         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8655                 dev->data->port_id, (void *)matcher,
8656                 rte_atomic32_read(&matcher->refcnt));
8657         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8658                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8659                            (matcher->matcher_object));
8660                 LIST_REMOVE(matcher, next);
8661                 /* table ref-- in release interface. */
8662                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8663                 rte_free(matcher);
8664                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8665                         dev->data->port_id, (void *)matcher);
8666                 return 0;
8667         }
8668         return 1;
8669 }
8670
8671 /**
8672  * Release an encap/decap resource.
8673  *
8674  * @param dev
8675  *   Pointer to Ethernet device.
8676  * @param handle
8677  *   Pointer to mlx5_flow_handle.
8678  *
8679  * @return
8680  *   1 while a reference on it exists, 0 when freed.
8681  */
8682 static int
8683 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8684                                      struct mlx5_flow_handle *handle)
8685 {
8686         struct mlx5_priv *priv = dev->data->dev_private;
8687         uint32_t idx = handle->dvh.rix_encap_decap;
8688         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8689
8690         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8691                          idx);
8692         if (!cache_resource)
8693                 return 0;
8694         MLX5_ASSERT(cache_resource->verbs_action);
8695         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8696                 (void *)cache_resource,
8697                 rte_atomic32_read(&cache_resource->refcnt));
8698         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8699                 claim_zero(mlx5_glue->destroy_flow_action
8700                                 (cache_resource->verbs_action));
8701                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8702                              &priv->sh->encaps_decaps, idx,
8703                              cache_resource, next);
8704                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8705                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8706                         (void *)cache_resource);
8707                 return 0;
8708         }
8709         return 1;
8710 }
8711
8712 /**
8713  * Release an jump to table action resource.
8714  *
8715  * @param dev
8716  *   Pointer to Ethernet device.
8717  * @param handle
8718  *   Pointer to mlx5_flow_handle.
8719  *
8720  * @return
8721  *   1 while a reference on it exists, 0 when freed.
8722  */
8723 static int
8724 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8725                                   struct mlx5_flow_handle *handle)
8726 {
8727         struct mlx5_priv *priv = dev->data->dev_private;
8728         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8729         struct mlx5_flow_tbl_data_entry *tbl_data;
8730
8731         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8732                              handle->rix_jump);
8733         if (!tbl_data)
8734                 return 0;
8735         cache_resource = &tbl_data->jump;
8736         MLX5_ASSERT(cache_resource->action);
8737         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8738                 (void *)cache_resource,
8739                 rte_atomic32_read(&cache_resource->refcnt));
8740         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8741                 claim_zero(mlx5_glue->destroy_flow_action
8742                                 (cache_resource->action));
8743                 /* jump action memory free is inside the table release. */
8744                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8745                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8746                         (void *)cache_resource);
8747                 return 0;
8748         }
8749         return 1;
8750 }
8751
8752 /**
8753  * Release a modify-header resource.
8754  *
8755  * @param handle
8756  *   Pointer to mlx5_flow_handle.
8757  *
8758  * @return
8759  *   1 while a reference on it exists, 0 when freed.
8760  */
8761 static int
8762 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8763 {
8764         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8765                                                         handle->dvh.modify_hdr;
8766
8767         MLX5_ASSERT(cache_resource->verbs_action);
8768         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8769                 (void *)cache_resource,
8770                 rte_atomic32_read(&cache_resource->refcnt));
8771         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8772                 claim_zero(mlx5_glue->destroy_flow_action
8773                                 (cache_resource->verbs_action));
8774                 LIST_REMOVE(cache_resource, next);
8775                 rte_free(cache_resource);
8776                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8777                         (void *)cache_resource);
8778                 return 0;
8779         }
8780         return 1;
8781 }
8782
8783 /**
8784  * Release port ID action resource.
8785  *
8786  * @param dev
8787  *   Pointer to Ethernet device.
8788  * @param handle
8789  *   Pointer to mlx5_flow_handle.
8790  *
8791  * @return
8792  *   1 while a reference on it exists, 0 when freed.
8793  */
8794 static int
8795 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8796                                         struct mlx5_flow_handle *handle)
8797 {
8798         struct mlx5_priv *priv = dev->data->dev_private;
8799         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8800         uint32_t idx = handle->rix_port_id_action;
8801
8802         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8803                                         idx);
8804         if (!cache_resource)
8805                 return 0;
8806         MLX5_ASSERT(cache_resource->action);
8807         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8808                 (void *)cache_resource,
8809                 rte_atomic32_read(&cache_resource->refcnt));
8810         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8811                 claim_zero(mlx5_glue->destroy_flow_action
8812                                 (cache_resource->action));
8813                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8814                              &priv->sh->port_id_action_list, idx,
8815                              cache_resource, next);
8816                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8817                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8818                         (void *)cache_resource);
8819                 return 0;
8820         }
8821         return 1;
8822 }
8823
8824 /**
8825  * Release push vlan action resource.
8826  *
8827  * @param dev
8828  *   Pointer to Ethernet device.
8829  * @param handle
8830  *   Pointer to mlx5_flow_handle.
8831  *
8832  * @return
8833  *   1 while a reference on it exists, 0 when freed.
8834  */
8835 static int
8836 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8837                                           struct mlx5_flow_handle *handle)
8838 {
8839         struct mlx5_priv *priv = dev->data->dev_private;
8840         uint32_t idx = handle->dvh.rix_push_vlan;
8841         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8842
8843         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8844                                         idx);
8845         if (!cache_resource)
8846                 return 0;
8847         MLX5_ASSERT(cache_resource->action);
8848         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8849                 (void *)cache_resource,
8850                 rte_atomic32_read(&cache_resource->refcnt));
8851         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8852                 claim_zero(mlx5_glue->destroy_flow_action
8853                                 (cache_resource->action));
8854                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8855                              &priv->sh->push_vlan_action_list, idx,
8856                              cache_resource, next);
8857                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8858                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8859                         (void *)cache_resource);
8860                 return 0;
8861         }
8862         return 1;
8863 }
8864
8865 /**
8866  * Release the fate resource.
8867  *
8868  * @param dev
8869  *   Pointer to Ethernet device.
8870  * @param handle
8871  *   Pointer to mlx5_flow_handle.
8872  */
8873 static void
8874 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8875                                struct mlx5_flow_handle *handle)
8876 {
8877         if (!handle->rix_fate)
8878                 return;
8879         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8880                 mlx5_hrxq_drop_release(dev);
8881         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8882                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8883         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8884                 flow_dv_jump_tbl_resource_release(dev, handle);
8885         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8886                 flow_dv_port_id_action_resource_release(dev, handle);
8887         else
8888                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8889         handle->rix_fate = 0;
8890 }
8891
8892 /**
8893  * Remove the flow from the NIC but keeps it in memory.
8894  * Lock free, (mutex should be acquired by caller).
8895  *
8896  * @param[in] dev
8897  *   Pointer to Ethernet device.
8898  * @param[in, out] flow
8899  *   Pointer to flow structure.
8900  */
8901 static void
8902 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8903 {
8904         struct mlx5_flow_handle *dh;
8905         uint32_t handle_idx;
8906         struct mlx5_priv *priv = dev->data->dev_private;
8907
8908         if (!flow)
8909                 return;
8910         handle_idx = flow->dev_handles;
8911         while (handle_idx) {
8912                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8913                                     handle_idx);
8914                 if (!dh)
8915                         return;
8916                 if (dh->ib_flow) {
8917                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8918                         dh->ib_flow = NULL;
8919                 }
8920                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8921                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8922                         flow_dv_fate_resource_release(dev, dh);
8923                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8924                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8925                 handle_idx = dh->next.next;
8926         }
8927 }
8928
8929 /**
8930  * Remove the flow from the NIC and the memory.
8931  * Lock free, (mutex should be acquired by caller).
8932  *
8933  * @param[in] dev
8934  *   Pointer to the Ethernet device structure.
8935  * @param[in, out] flow
8936  *   Pointer to flow structure.
8937  */
8938 static void
8939 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8940 {
8941         struct mlx5_flow_handle *dev_handle;
8942         struct mlx5_priv *priv = dev->data->dev_private;
8943
8944         if (!flow)
8945                 return;
8946         __flow_dv_remove(dev, flow);
8947         if (flow->counter) {
8948                 flow_dv_counter_release(dev, flow->counter);
8949                 flow->counter = 0;
8950         }
8951         if (flow->meter) {
8952                 struct mlx5_flow_meter *fm;
8953
8954                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8955                                     flow->meter);
8956                 if (fm)
8957                         mlx5_flow_meter_detach(fm);
8958                 flow->meter = 0;
8959         }
8960         while (flow->dev_handles) {
8961                 uint32_t tmp_idx = flow->dev_handles;
8962
8963                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8964                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8965                 if (!dev_handle)
8966                         return;
8967                 flow->dev_handles = dev_handle->next.next;
8968                 if (dev_handle->dvh.matcher)
8969                         flow_dv_matcher_release(dev, dev_handle);
8970                 if (dev_handle->dvh.rix_encap_decap)
8971                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8972                 if (dev_handle->dvh.modify_hdr)
8973                         flow_dv_modify_hdr_resource_release(dev_handle);
8974                 if (dev_handle->dvh.rix_push_vlan)
8975                         flow_dv_push_vlan_action_resource_release(dev,
8976                                                                   dev_handle);
8977                 if (dev_handle->dvh.rix_tag)
8978                         flow_dv_tag_release(dev,
8979                                             dev_handle->dvh.rix_tag);
8980                 flow_dv_fate_resource_release(dev, dev_handle);
8981                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8982                            tmp_idx);
8983         }
8984 }
8985
8986 /**
8987  * Query a dv flow  rule for its statistics via devx.
8988  *
8989  * @param[in] dev
8990  *   Pointer to Ethernet device.
8991  * @param[in] flow
8992  *   Pointer to the sub flow.
8993  * @param[out] data
8994  *   data retrieved by the query.
8995  * @param[out] error
8996  *   Perform verbose error reporting if not NULL.
8997  *
8998  * @return
8999  *   0 on success, a negative errno value otherwise and rte_errno is set.
9000  */
9001 static int
9002 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9003                     void *data, struct rte_flow_error *error)
9004 {
9005         struct mlx5_priv *priv = dev->data->dev_private;
9006         struct rte_flow_query_count *qc = data;
9007
9008         if (!priv->config.devx)
9009                 return rte_flow_error_set(error, ENOTSUP,
9010                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9011                                           NULL,
9012                                           "counters are not supported");
9013         if (flow->counter) {
9014                 uint64_t pkts, bytes;
9015                 struct mlx5_flow_counter *cnt;
9016
9017                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9018                                                  NULL);
9019                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9020                                                &bytes);
9021
9022                 if (err)
9023                         return rte_flow_error_set(error, -err,
9024                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9025                                         NULL, "cannot read counters");
9026                 qc->hits_set = 1;
9027                 qc->bytes_set = 1;
9028                 qc->hits = pkts - cnt->hits;
9029                 qc->bytes = bytes - cnt->bytes;
9030                 if (qc->reset) {
9031                         cnt->hits = pkts;
9032                         cnt->bytes = bytes;
9033                 }
9034                 return 0;
9035         }
9036         return rte_flow_error_set(error, EINVAL,
9037                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9038                                   NULL,
9039                                   "counters are not available");
9040 }
9041
9042 /**
9043  * Query a flow.
9044  *
9045  * @see rte_flow_query()
9046  * @see rte_flow_ops
9047  */
9048 static int
9049 flow_dv_query(struct rte_eth_dev *dev,
9050               struct rte_flow *flow __rte_unused,
9051               const struct rte_flow_action *actions __rte_unused,
9052               void *data __rte_unused,
9053               struct rte_flow_error *error __rte_unused)
9054 {
9055         int ret = -EINVAL;
9056
9057         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9058                 switch (actions->type) {
9059                 case RTE_FLOW_ACTION_TYPE_VOID:
9060                         break;
9061                 case RTE_FLOW_ACTION_TYPE_COUNT:
9062                         ret = flow_dv_query_count(dev, flow, data, error);
9063                         break;
9064                 default:
9065                         return rte_flow_error_set(error, ENOTSUP,
9066                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9067                                                   actions,
9068                                                   "action not supported");
9069                 }
9070         }
9071         return ret;
9072 }
9073
9074 /**
9075  * Destroy the meter table set.
9076  * Lock free, (mutex should be acquired by caller).
9077  *
9078  * @param[in] dev
9079  *   Pointer to Ethernet device.
9080  * @param[in] tbl
9081  *   Pointer to the meter table set.
9082  *
9083  * @return
9084  *   Always 0.
9085  */
9086 static int
9087 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9088                         struct mlx5_meter_domains_infos *tbl)
9089 {
9090         struct mlx5_priv *priv = dev->data->dev_private;
9091         struct mlx5_meter_domains_infos *mtd =
9092                                 (struct mlx5_meter_domains_infos *)tbl;
9093
9094         if (!mtd || !priv->config.dv_flow_en)
9095                 return 0;
9096         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9097                 claim_zero(mlx5_glue->dv_destroy_flow
9098                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9099         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9100                 claim_zero(mlx5_glue->dv_destroy_flow
9101                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9102         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9103                 claim_zero(mlx5_glue->dv_destroy_flow
9104                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9105         if (mtd->egress.color_matcher)
9106                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9107                           (mtd->egress.color_matcher));
9108         if (mtd->egress.any_matcher)
9109                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9110                           (mtd->egress.any_matcher));
9111         if (mtd->egress.tbl)
9112                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9113         if (mtd->egress.sfx_tbl)
9114                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9115         if (mtd->ingress.color_matcher)
9116                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9117                           (mtd->ingress.color_matcher));
9118         if (mtd->ingress.any_matcher)
9119                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9120                           (mtd->ingress.any_matcher));
9121         if (mtd->ingress.tbl)
9122                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9123         if (mtd->ingress.sfx_tbl)
9124                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9125         if (mtd->transfer.color_matcher)
9126                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9127                           (mtd->transfer.color_matcher));
9128         if (mtd->transfer.any_matcher)
9129                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9130                           (mtd->transfer.any_matcher));
9131         if (mtd->transfer.tbl)
9132                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9133         if (mtd->transfer.sfx_tbl)
9134                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9135         if (mtd->drop_actn)
9136                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9137         rte_free(mtd);
9138         return 0;
9139 }
9140
9141 /* Number of meter flow actions, count and jump or count and drop. */
9142 #define METER_ACTIONS 2
9143
9144 /**
9145  * Create specify domain meter table and suffix table.
9146  *
9147  * @param[in] dev
9148  *   Pointer to Ethernet device.
9149  * @param[in,out] mtb
9150  *   Pointer to DV meter table set.
9151  * @param[in] egress
9152  *   Table attribute.
9153  * @param[in] transfer
9154  *   Table attribute.
9155  * @param[in] color_reg_c_idx
9156  *   Reg C index for color match.
9157  *
9158  * @return
9159  *   0 on success, -1 otherwise and rte_errno is set.
9160  */
9161 static int
9162 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9163                            struct mlx5_meter_domains_infos *mtb,
9164                            uint8_t egress, uint8_t transfer,
9165                            uint32_t color_reg_c_idx)
9166 {
9167         struct mlx5_priv *priv = dev->data->dev_private;
9168         struct mlx5_ibv_shared *sh = priv->sh;
9169         struct mlx5_flow_dv_match_params mask = {
9170                 .size = sizeof(mask.buf),
9171         };
9172         struct mlx5_flow_dv_match_params value = {
9173                 .size = sizeof(value.buf),
9174         };
9175         struct mlx5dv_flow_matcher_attr dv_attr = {
9176                 .type = IBV_FLOW_ATTR_NORMAL,
9177                 .priority = 0,
9178                 .match_criteria_enable = 0,
9179                 .match_mask = (void *)&mask,
9180         };
9181         void *actions[METER_ACTIONS];
9182         struct mlx5_meter_domain_info *dtb;
9183         struct rte_flow_error error;
9184         int i = 0;
9185
9186         if (transfer)
9187                 dtb = &mtb->transfer;
9188         else if (egress)
9189                 dtb = &mtb->egress;
9190         else
9191                 dtb = &mtb->ingress;
9192         /* Create the meter table with METER level. */
9193         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9194                                             egress, transfer, &error);
9195         if (!dtb->tbl) {
9196                 DRV_LOG(ERR, "Failed to create meter policer table.");
9197                 return -1;
9198         }
9199         /* Create the meter suffix table with SUFFIX level. */
9200         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9201                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9202                                             egress, transfer, &error);
9203         if (!dtb->sfx_tbl) {
9204                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9205                 return -1;
9206         }
9207         /* Create matchers, Any and Color. */
9208         dv_attr.priority = 3;
9209         dv_attr.match_criteria_enable = 0;
9210         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9211                                                              &dv_attr,
9212                                                              dtb->tbl->obj);
9213         if (!dtb->any_matcher) {
9214                 DRV_LOG(ERR, "Failed to create meter"
9215                              " policer default matcher.");
9216                 goto error_exit;
9217         }
9218         dv_attr.priority = 0;
9219         dv_attr.match_criteria_enable =
9220                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9221         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9222                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9223         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9224                                                                &dv_attr,
9225                                                                dtb->tbl->obj);
9226         if (!dtb->color_matcher) {
9227                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9228                 goto error_exit;
9229         }
9230         if (mtb->count_actns[RTE_MTR_DROPPED])
9231                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9232         actions[i++] = mtb->drop_actn;
9233         /* Default rule: lowest priority, match any, actions: drop. */
9234         dtb->policer_rules[RTE_MTR_DROPPED] =
9235                         mlx5_glue->dv_create_flow(dtb->any_matcher,
9236                                                  (void *)&value, i, actions);
9237         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9238                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9239                 goto error_exit;
9240         }
9241         return 0;
9242 error_exit:
9243         return -1;
9244 }
9245
9246 /**
9247  * Create the needed meter and suffix tables.
9248  * Lock free, (mutex should be acquired by caller).
9249  *
9250  * @param[in] dev
9251  *   Pointer to Ethernet device.
9252  * @param[in] fm
9253  *   Pointer to the flow meter.
9254  *
9255  * @return
9256  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9257  */
9258 static struct mlx5_meter_domains_infos *
9259 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9260                        const struct mlx5_flow_meter *fm)
9261 {
9262         struct mlx5_priv *priv = dev->data->dev_private;
9263         struct mlx5_meter_domains_infos *mtb;
9264         int ret;
9265         int i;
9266
9267         if (!priv->mtr_en) {
9268                 rte_errno = ENOTSUP;
9269                 return NULL;
9270         }
9271         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9272         if (!mtb) {
9273                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9274                 return NULL;
9275         }
9276         /* Create meter count actions */
9277         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9278                 struct mlx5_flow_counter *cnt;
9279                 if (!fm->policer_stats.cnt[i])
9280                         continue;
9281                 cnt = flow_dv_counter_get_by_idx(dev,
9282                       fm->policer_stats.cnt[i], NULL);
9283                 mtb->count_actns[i] = cnt->action;
9284         }
9285         /* Create drop action. */
9286         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9287         if (!mtb->drop_actn) {
9288                 DRV_LOG(ERR, "Failed to create drop action.");
9289                 goto error_exit;
9290         }
9291         /* Egress meter table. */
9292         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9293         if (ret) {
9294                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9295                 goto error_exit;
9296         }
9297         /* Ingress meter table. */
9298         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9299         if (ret) {
9300                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9301                 goto error_exit;
9302         }
9303         /* FDB meter table. */
9304         if (priv->config.dv_esw_en) {
9305                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9306                                                  priv->mtr_color_reg);
9307                 if (ret) {
9308                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9309                         goto error_exit;
9310                 }
9311         }
9312         return mtb;
9313 error_exit:
9314         flow_dv_destroy_mtr_tbl(dev, mtb);
9315         return NULL;
9316 }
9317
9318 /**
9319  * Destroy domain policer rule.
9320  *
9321  * @param[in] dt
9322  *   Pointer to domain table.
9323  */
9324 static void
9325 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9326 {
9327         int i;
9328
9329         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9330                 if (dt->policer_rules[i]) {
9331                         claim_zero(mlx5_glue->dv_destroy_flow
9332                                   (dt->policer_rules[i]));
9333                         dt->policer_rules[i] = NULL;
9334                 }
9335         }
9336         if (dt->jump_actn) {
9337                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9338                 dt->jump_actn = NULL;
9339         }
9340 }
9341
9342 /**
9343  * Destroy policer rules.
9344  *
9345  * @param[in] dev
9346  *   Pointer to Ethernet device.
9347  * @param[in] fm
9348  *   Pointer to flow meter structure.
9349  * @param[in] attr
9350  *   Pointer to flow attributes.
9351  *
9352  * @return
9353  *   Always 0.
9354  */
9355 static int
9356 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9357                               const struct mlx5_flow_meter *fm,
9358                               const struct rte_flow_attr *attr)
9359 {
9360         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9361
9362         if (!mtb)
9363                 return 0;
9364         if (attr->egress)
9365                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9366         if (attr->ingress)
9367                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9368         if (attr->transfer)
9369                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9370         return 0;
9371 }
9372
9373 /**
9374  * Create specify domain meter policer rule.
9375  *
9376  * @param[in] fm
9377  *   Pointer to flow meter structure.
9378  * @param[in] mtb
9379  *   Pointer to DV meter table set.
9380  * @param[in] mtr_reg_c
9381  *   Color match REG_C.
9382  *
9383  * @return
9384  *   0 on success, -1 otherwise.
9385  */
9386 static int
9387 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9388                                     struct mlx5_meter_domain_info *dtb,
9389                                     uint8_t mtr_reg_c)
9390 {
9391         struct mlx5_flow_dv_match_params matcher = {
9392                 .size = sizeof(matcher.buf),
9393         };
9394         struct mlx5_flow_dv_match_params value = {
9395                 .size = sizeof(value.buf),
9396         };
9397         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9398         void *actions[METER_ACTIONS];
9399         int i;
9400
9401         /* Create jump action. */
9402         if (!dtb->jump_actn)
9403                 dtb->jump_actn =
9404                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9405                                                         (dtb->sfx_tbl->obj);
9406         if (!dtb->jump_actn) {
9407                 DRV_LOG(ERR, "Failed to create policer jump action.");
9408                 goto error;
9409         }
9410         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9411                 int j = 0;
9412
9413                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9414                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9415                 if (mtb->count_actns[i])
9416                         actions[j++] = mtb->count_actns[i];
9417                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9418                         actions[j++] = mtb->drop_actn;
9419                 else
9420                         actions[j++] = dtb->jump_actn;
9421                 dtb->policer_rules[i] =
9422                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9423                                                  (void *)&value,
9424                                                   j, actions);
9425                 if (!dtb->policer_rules[i]) {
9426                         DRV_LOG(ERR, "Failed to create policer rule.");
9427                         goto error;
9428                 }
9429         }
9430         return 0;
9431 error:
9432         rte_errno = errno;
9433         return -1;
9434 }
9435
9436 /**
9437  * Create policer rules.
9438  *
9439  * @param[in] dev
9440  *   Pointer to Ethernet device.
9441  * @param[in] fm
9442  *   Pointer to flow meter structure.
9443  * @param[in] attr
9444  *   Pointer to flow attributes.
9445  *
9446  * @return
9447  *   0 on success, -1 otherwise.
9448  */
9449 static int
9450 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9451                              struct mlx5_flow_meter *fm,
9452                              const struct rte_flow_attr *attr)
9453 {
9454         struct mlx5_priv *priv = dev->data->dev_private;
9455         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9456         int ret;
9457
9458         if (attr->egress) {
9459                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9460                                                 priv->mtr_color_reg);
9461                 if (ret) {
9462                         DRV_LOG(ERR, "Failed to create egress policer.");
9463                         goto error;
9464                 }
9465         }
9466         if (attr->ingress) {
9467                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9468                                                 priv->mtr_color_reg);
9469                 if (ret) {
9470                         DRV_LOG(ERR, "Failed to create ingress policer.");
9471                         goto error;
9472                 }
9473         }
9474         if (attr->transfer) {
9475                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9476                                                 priv->mtr_color_reg);
9477                 if (ret) {
9478                         DRV_LOG(ERR, "Failed to create transfer policer.");
9479                         goto error;
9480                 }
9481         }
9482         return 0;
9483 error:
9484         flow_dv_destroy_policer_rules(dev, fm, attr);
9485         return -1;
9486 }
9487
9488 /**
9489  * Query a devx counter.
9490  *
9491  * @param[in] dev
9492  *   Pointer to the Ethernet device structure.
9493  * @param[in] cnt
9494  *   Index to the flow counter.
9495  * @param[in] clear
9496  *   Set to clear the counter statistics.
9497  * @param[out] pkts
9498  *   The statistics value of packets.
9499  * @param[out] bytes
9500  *   The statistics value of bytes.
9501  *
9502  * @return
9503  *   0 on success, otherwise return -1.
9504  */
9505 static int
9506 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9507                       uint64_t *pkts, uint64_t *bytes)
9508 {
9509         struct mlx5_priv *priv = dev->data->dev_private;
9510         struct mlx5_flow_counter *cnt;
9511         uint64_t inn_pkts, inn_bytes;
9512         int ret;
9513
9514         if (!priv->config.devx)
9515                 return -1;
9516
9517         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9518         if (ret)
9519                 return -1;
9520         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9521         *pkts = inn_pkts - cnt->hits;
9522         *bytes = inn_bytes - cnt->bytes;
9523         if (clear) {
9524                 cnt->hits = inn_pkts;
9525                 cnt->bytes = inn_bytes;
9526         }
9527         return 0;
9528 }
9529
9530 /**
9531  * Get aged-out flows.
9532  *
9533  * @param[in] dev
9534  *   Pointer to the Ethernet device structure.
9535  * @param[in] context
9536  *   The address of an array of pointers to the aged-out flows contexts.
9537  * @param[in] nb_contexts
9538  *   The length of context array pointers.
9539  * @param[out] error
9540  *   Perform verbose error reporting if not NULL. Initialized in case of
9541  *   error only.
9542  *
9543  * @return
9544  *   how many contexts get in success, otherwise negative errno value.
9545  *   if nb_contexts is 0, return the amount of all aged contexts.
9546  *   if nb_contexts is not 0 , return the amount of aged flows reported
9547  *   in the context array.
9548  * @note: only stub for now
9549  */
9550 static int
9551 flow_get_aged_flows(struct rte_eth_dev *dev,
9552                     void **context,
9553                     uint32_t nb_contexts,
9554                     struct rte_flow_error *error)
9555 {
9556         struct mlx5_priv *priv = dev->data->dev_private;
9557         struct mlx5_age_info *age_info;
9558         struct mlx5_age_param *age_param;
9559         struct mlx5_flow_counter *counter;
9560         int nb_flows = 0;
9561
9562         if (nb_contexts && !context)
9563                 return rte_flow_error_set(error, EINVAL,
9564                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9565                                           NULL,
9566                                           "Should assign at least one flow or"
9567                                           " context to get if nb_contexts != 0");
9568         age_info = GET_PORT_AGE_INFO(priv);
9569         rte_spinlock_lock(&age_info->aged_sl);
9570         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9571                 nb_flows++;
9572                 if (nb_contexts) {
9573                         age_param = MLX5_CNT_TO_AGE(counter);
9574                         context[nb_flows - 1] = age_param->context;
9575                         if (!(--nb_contexts))
9576                                 break;
9577                 }
9578         }
9579         rte_spinlock_unlock(&age_info->aged_sl);
9580         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9581         return nb_flows;
9582 }
9583
9584 /*
9585  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9586  */
9587 static int
9588 flow_dv_translate(struct rte_eth_dev *dev,
9589                   struct mlx5_flow *dev_flow,
9590                   const struct rte_flow_attr *attr,
9591                   const struct rte_flow_item items[],
9592                   const struct rte_flow_action actions[],
9593                   struct rte_flow_error *error)
9594 {
9595         int ret;
9596
9597         flow_dv_shared_lock(dev);
9598         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9599         flow_dv_shared_unlock(dev);
9600         return ret;
9601 }
9602
9603 /*
9604  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9605  */
9606 static int
9607 flow_dv_apply(struct rte_eth_dev *dev,
9608               struct rte_flow *flow,
9609               struct rte_flow_error *error)
9610 {
9611         int ret;
9612
9613         flow_dv_shared_lock(dev);
9614         ret = __flow_dv_apply(dev, flow, error);
9615         flow_dv_shared_unlock(dev);
9616         return ret;
9617 }
9618
9619 /*
9620  * Mutex-protected thunk to lock-free __flow_dv_remove().
9621  */
9622 static void
9623 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9624 {
9625         flow_dv_shared_lock(dev);
9626         __flow_dv_remove(dev, flow);
9627         flow_dv_shared_unlock(dev);
9628 }
9629
9630 /*
9631  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9632  */
9633 static void
9634 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9635 {
9636         flow_dv_shared_lock(dev);
9637         __flow_dv_destroy(dev, flow);
9638         flow_dv_shared_unlock(dev);
9639 }
9640
9641 /*
9642  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9643  */
9644 static uint32_t
9645 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9646 {
9647         uint32_t cnt;
9648
9649         flow_dv_shared_lock(dev);
9650         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9651         flow_dv_shared_unlock(dev);
9652         return cnt;
9653 }
9654
9655 /*
9656  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9657  */
9658 static void
9659 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9660 {
9661         flow_dv_shared_lock(dev);
9662         flow_dv_counter_release(dev, cnt);
9663         flow_dv_shared_unlock(dev);
9664 }
9665
9666 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9667         .validate = flow_dv_validate,
9668         .prepare = flow_dv_prepare,
9669         .translate = flow_dv_translate,
9670         .apply = flow_dv_apply,
9671         .remove = flow_dv_remove,
9672         .destroy = flow_dv_destroy,
9673         .query = flow_dv_query,
9674         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9675         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9676         .create_policer_rules = flow_dv_create_policer_rules,
9677         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9678         .counter_alloc = flow_dv_counter_allocate,
9679         .counter_free = flow_dv_counter_free,
9680         .counter_query = flow_dv_counter_query,
9681         .get_aged_flows = flow_get_aged_flows,
9682 };
9683
9684 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */