drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29 #include <rte_vxlan.h>
  30 #include <rte_gtp.h>
  31
  32 #include <mlx5_glue.h>
  33 #include <mlx5_devx_cmds.h>
  34 #include <mlx5_prm.h>
  35
  36 #include "mlx5_defs.h"
  37 #include "mlx5.h"
  38 #include "mlx5_flow.h"
  39 #include "mlx5_rxtx.h"
  40
  41 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  42
  43 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  44 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  45 #endif
  46
  47 #ifndef HAVE_MLX5DV_DR_ESWITCH
  48 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  49 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  50 #endif
  51 #endif
  52
  53 #ifndef HAVE_MLX5DV_DR
  54 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  55 #endif
  56
  57 /* VLAN header definitions */
  58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  63
  64 union flow_dv_attr {
  65         struct {
  66                 uint32_t valid:1;
  67                 uint32_t ipv4:1;
  68                 uint32_t ipv6:1;
  69                 uint32_t tcp:1;
  70                 uint32_t udp:1;
  71                 uint32_t reserved:27;
  72         };
  73         uint32_t attr;
  74 };
  75
  76 static struct mlx5_flow_counter_pool *
  77 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, bool fallback,
  78                         int id);
  79 static struct mlx5_pools_container *
  80 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
  81                     uint32_t batch);
  82
  83 /**
  84  * Initialize flow attributes structure according to flow items' types.
  85  *
  86  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  87  * mode. For tunnel mode, the items to be modified are the outermost ones.
  88  *
  89  * @param[in] item
  90  *   Pointer to item specification.
  91  * @param[out] attr
  92  *   Pointer to flow attributes structure.
  93  * @param[in] dev_flow
  94  *   Pointer to the sub flow.
  95  * @param[in] tunnel_decap
  96  *   Whether action is after tunnel decapsulation.
  97  */
  98 static void
  99 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 100                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 101 {
 102         uint64_t layers = dev_flow->handle->layers;
 103
 104         /*
 105          * If layers is already initialized, it means this dev_flow is the
 106          * suffix flow, the layers flags is set by the prefix flow. Need to
 107          * use the layer flags from prefix flow as the suffix flow may not
 108          * have the user defined items as the flow is split.
 109          */
 110         if (layers) {
 111                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 112                         attr->ipv4 = 1;
 113                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 114                         attr->ipv6 = 1;
 115                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 116                         attr->tcp = 1;
 117                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 118                         attr->udp = 1;
 119                 attr->valid = 1;
 120                 return;
 121         }
 122         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 123                 uint8_t next_protocol = 0xff;
 124                 switch (item->type) {
 125                 case RTE_FLOW_ITEM_TYPE_GRE:
 126                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 127                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 128                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 129                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 130                 case RTE_FLOW_ITEM_TYPE_MPLS:
 131                         if (tunnel_decap)
 132                                 attr->attr = 0;
 133                         break;
 134                 case RTE_FLOW_ITEM_TYPE_IPV4:
 135                         if (!attr->ipv6)
 136                                 attr->ipv4 = 1;
 137                         if (item->mask != NULL &&
 138                             ((const struct rte_flow_item_ipv4 *)
 139                             item->mask)->hdr.next_proto_id)
 140                                 next_protocol =
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->spec))->hdr.next_proto_id &
 143                                     ((const struct rte_flow_item_ipv4 *)
 144                                       (item->mask))->hdr.next_proto_id;
 145                         if ((next_protocol == IPPROTO_IPIP ||
 146                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 147                                 attr->attr = 0;
 148                         break;
 149                 case RTE_FLOW_ITEM_TYPE_IPV6:
 150                         if (!attr->ipv4)
 151                                 attr->ipv6 = 1;
 152                         if (item->mask != NULL &&
 153                             ((const struct rte_flow_item_ipv6 *)
 154                             item->mask)->hdr.proto)
 155                                 next_protocol =
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->spec))->hdr.proto &
 158                                     ((const struct rte_flow_item_ipv6 *)
 159                                       (item->mask))->hdr.proto;
 160                         if ((next_protocol == IPPROTO_IPIP ||
 161                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 162                                 attr->attr = 0;
 163                         break;
 164                 case RTE_FLOW_ITEM_TYPE_UDP:
 165                         if (!attr->tcp)
 166                                 attr->udp = 1;
 167                         break;
 168                 case RTE_FLOW_ITEM_TYPE_TCP:
 169                         if (!attr->udp)
 170                                 attr->tcp = 1;
 171                         break;
 172                 default:
 173                         break;
 174                 }
 175         }
 176         attr->valid = 1;
 177 }
 178
 179 /**
 180  * Convert rte_mtr_color to mlx5 color.
 181  *
 182  * @param[in] rcol
 183  *   rte_mtr_color.
 184  *
 185  * @return
 186  *   mlx5 color.
 187  */
 188 static int
 189 rte_col_2_mlx5_col(enum rte_color rcol)
 190 {
 191         switch (rcol) {
 192         case RTE_COLOR_GREEN:
 193                 return MLX5_FLOW_COLOR_GREEN;
 194         case RTE_COLOR_YELLOW:
 195                 return MLX5_FLOW_COLOR_YELLOW;
 196         case RTE_COLOR_RED:
 197                 return MLX5_FLOW_COLOR_RED;
 198         default:
 199                 break;
 200         }
 201         return MLX5_FLOW_COLOR_UNDEFINED;
 202 }
 203
 204 struct field_modify_info {
 205         uint32_t size; /* Size of field in protocol header, in bytes. */
 206         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 207         enum mlx5_modification_field id;
 208 };
 209
 210 struct field_modify_info modify_eth[] = {
 211         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 212         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 213         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 214         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 215         {0, 0, 0},
 216 };
 217
 218 struct field_modify_info modify_vlan_out_first_vid[] = {
 219         /* Size in bits !!! */
 220         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 221         {0, 0, 0},
 222 };
 223
 224 struct field_modify_info modify_ipv4[] = {
 225         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 226         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 227         {4, 12, MLX5_MODI_OUT_SIPV4},
 228         {4, 16, MLX5_MODI_OUT_DIPV4},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv6[] = {
 233         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 235         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 236         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 237         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 238         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 239         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 240         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 241         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 242         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 243         {0, 0, 0},
 244 };
 245
 246 struct field_modify_info modify_udp[] = {
 247         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 248         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 249         {0, 0, 0},
 250 };
 251
 252 struct field_modify_info modify_tcp[] = {
 253         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 254         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 255         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 256         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 257         {0, 0, 0},
 258 };
 259
 260 static void
 261 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 262                           uint8_t next_protocol, uint64_t *item_flags,
 263                           int *tunnel)
 264 {
 265         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 266                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 267         if (next_protocol == IPPROTO_IPIP) {
 268                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 269                 *tunnel = 1;
 270         }
 271         if (next_protocol == IPPROTO_IPV6) {
 272                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 273                 *tunnel = 1;
 274         }
 275 }
 276
 277 /**
 278  * Acquire the synchronizing object to protect multithreaded access
 279  * to shared dv context. Lock occurs only if context is actually
 280  * shared, i.e. we have multiport IB device and representors are
 281  * created.
 282  *
 283  * @param[in] dev
 284  *   Pointer to the rte_eth_dev structure.
 285  */
 286 static void
 287 flow_dv_shared_lock(struct rte_eth_dev *dev)
 288 {
 289         struct mlx5_priv *priv = dev->data->dev_private;
 290         struct mlx5_ibv_shared *sh = priv->sh;
 291
 292         if (sh->dv_refcnt > 1) {
 293                 int ret;
 294
 295                 ret = pthread_mutex_lock(&sh->dv_mutex);
 296                 MLX5_ASSERT(!ret);
 297                 (void)ret;
 298         }
 299 }
 300
 301 static void
 302 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 303 {
 304         struct mlx5_priv *priv = dev->data->dev_private;
 305         struct mlx5_ibv_shared *sh = priv->sh;
 306
 307         if (sh->dv_refcnt > 1) {
 308                 int ret;
 309
 310                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 311                 MLX5_ASSERT(!ret);
 312                 (void)ret;
 313         }
 314 }
 315
 316 /* Update VLAN's VID/PCP based on input rte_flow_action.
 317  *
 318  * @param[in] action
 319  *   Pointer to struct rte_flow_action.
 320  * @param[out] vlan
 321  *   Pointer to struct rte_vlan_hdr.
 322  */
 323 static void
 324 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 325                          struct rte_vlan_hdr *vlan)
 326 {
 327         uint16_t vlan_tci;
 328         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 329                 vlan_tci =
 330                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 331                                                action->conf)->vlan_pcp;
 332                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 333                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 334                 vlan->vlan_tci |= vlan_tci;
 335         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 336                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 337                 vlan->vlan_tci |= rte_be_to_cpu_16
 338                     (((const struct rte_flow_action_of_set_vlan_vid *)
 339                                              action->conf)->vlan_vid);
 340         }
 341 }
 342
 343 /**
 344  * Fetch 1, 2, 3 or 4 byte field from the byte array
 345  * and return as unsigned integer in host-endian format.
 346  *
 347  * @param[in] data
 348  *   Pointer to data array.
 349  * @param[in] size
 350  *   Size of field to extract.
 351  *
 352  * @return
 353  *   converted field in host endian format.
 354  */
 355 static inline uint32_t
 356 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 357 {
 358         uint32_t ret;
 359
 360         switch (size) {
 361         case 1:
 362                 ret = *data;
 363                 break;
 364         case 2:
 365                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 366                 break;
 367         case 3:
 368                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 369                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 370                 break;
 371         case 4:
 372                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 373                 break;
 374         default:
 375                 MLX5_ASSERT(false);
 376                 ret = 0;
 377                 break;
 378         }
 379         return ret;
 380 }
 381
 382 /**
 383  * Convert modify-header action to DV specification.
 384  *
 385  * Data length of each action is determined by provided field description
 386  * and the item mask. Data bit offset and width of each action is determined
 387  * by provided item mask.
 388  *
 389  * @param[in] item
 390  *   Pointer to item specification.
 391  * @param[in] field
 392  *   Pointer to field modification information.
 393  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 394  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 395  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 396  * @param[in] dcopy
 397  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 398  *   Negative offset value sets the same offset as source offset.
 399  *   size field is ignored, value is taken from source field.
 400  * @param[in,out] resource
 401  *   Pointer to the modify-header resource.
 402  * @param[in] type
 403  *   Type of modification.
 404  * @param[out] error
 405  *   Pointer to the error structure.
 406  *
 407  * @return
 408  *   0 on success, a negative errno value otherwise and rte_errno is set.
 409  */
 410 static int
 411 flow_dv_convert_modify_action(struct rte_flow_item *item,
 412                               struct field_modify_info *field,
 413                               struct field_modify_info *dcopy,
 414                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 415                               uint32_t type, struct rte_flow_error *error)
 416 {
 417         uint32_t i = resource->actions_num;
 418         struct mlx5_modification_cmd *actions = resource->actions;
 419
 420         /*
 421          * The item and mask are provided in big-endian format.
 422          * The fields should be presented as in big-endian format either.
 423          * Mask must be always present, it defines the actual field width.
 424          */
 425         MLX5_ASSERT(item->mask);
 426         MLX5_ASSERT(field->size);
 427         do {
 428                 unsigned int size_b;
 429                 unsigned int off_b;
 430                 uint32_t mask;
 431                 uint32_t data;
 432
 433                 if (i >= MLX5_MAX_MODIFY_NUM)
 434                         return rte_flow_error_set(error, EINVAL,
 435                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 436                                  "too many items to modify");
 437                 /* Fetch variable byte size mask from the array. */
 438                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 439                                            field->offset, field->size);
 440                 if (!mask) {
 441                         ++field;
 442                         continue;
 443                 }
 444                 /* Deduce actual data width in bits from mask value. */
 445                 off_b = rte_bsf32(mask);
 446                 size_b = sizeof(uint32_t) * CHAR_BIT -
 447                          off_b - __builtin_clz(mask);
 448                 MLX5_ASSERT(size_b);
 449                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 450                 actions[i] = (struct mlx5_modification_cmd) {
 451                         .action_type = type,
 452                         .field = field->id,
 453                         .offset = off_b,
 454                         .length = size_b,
 455                 };
 456                 /* Convert entire record to expected big-endian format. */
 457                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 458                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 459                         MLX5_ASSERT(dcopy);
 460                         actions[i].dst_field = dcopy->id;
 461                         actions[i].dst_offset =
 462                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 463                         /* Convert entire record to big-endian format. */
 464                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 465                 } else {
 466                         MLX5_ASSERT(item->spec);
 467                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 468                                                    field->offset, field->size);
 469                         /* Shift out the trailing masked bits from data. */
 470                         data = (data & mask) >> off_b;
 471                         actions[i].data1 = rte_cpu_to_be_32(data);
 472                 }
 473                 ++i;
 474                 ++field;
 475         } while (field->size);
 476         if (resource->actions_num == i)
 477                 return rte_flow_error_set(error, EINVAL,
 478                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 479                                           "invalid modification flow item");
 480         resource->actions_num = i;
 481         return 0;
 482 }
 483
 484 /**
 485  * Convert modify-header set IPv4 address action to DV specification.
 486  *
 487  * @param[in,out] resource
 488  *   Pointer to the modify-header resource.
 489  * @param[in] action
 490  *   Pointer to action specification.
 491  * @param[out] error
 492  *   Pointer to the error structure.
 493  *
 494  * @return
 495  *   0 on success, a negative errno value otherwise and rte_errno is set.
 496  */
 497 static int
 498 flow_dv_convert_action_modify_ipv4
 499                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 500                          const struct rte_flow_action *action,
 501                          struct rte_flow_error *error)
 502 {
 503         const struct rte_flow_action_set_ipv4 *conf =
 504                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 505         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 506         struct rte_flow_item_ipv4 ipv4;
 507         struct rte_flow_item_ipv4 ipv4_mask;
 508
 509         memset(&ipv4, 0, sizeof(ipv4));
 510         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 511         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 512                 ipv4.hdr.src_addr = conf->ipv4_addr;
 513                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 514         } else {
 515                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 516                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 517         }
 518         item.spec = &ipv4;
 519         item.mask = &ipv4_mask;
 520         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 521                                              MLX5_MODIFICATION_TYPE_SET, error);
 522 }
 523
 524 /**
 525  * Convert modify-header set IPv6 address action to DV specification.
 526  *
 527  * @param[in,out] resource
 528  *   Pointer to the modify-header resource.
 529  * @param[in] action
 530  *   Pointer to action specification.
 531  * @param[out] error
 532  *   Pointer to the error structure.
 533  *
 534  * @return
 535  *   0 on success, a negative errno value otherwise and rte_errno is set.
 536  */
 537 static int
 538 flow_dv_convert_action_modify_ipv6
 539                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 540                          const struct rte_flow_action *action,
 541                          struct rte_flow_error *error)
 542 {
 543         const struct rte_flow_action_set_ipv6 *conf =
 544                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 545         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 546         struct rte_flow_item_ipv6 ipv6;
 547         struct rte_flow_item_ipv6 ipv6_mask;
 548
 549         memset(&ipv6, 0, sizeof(ipv6));
 550         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 551         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 552                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 553                        sizeof(ipv6.hdr.src_addr));
 554                 memcpy(&ipv6_mask.hdr.src_addr,
 555                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 556                        sizeof(ipv6.hdr.src_addr));
 557         } else {
 558                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 559                        sizeof(ipv6.hdr.dst_addr));
 560                 memcpy(&ipv6_mask.hdr.dst_addr,
 561                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 562                        sizeof(ipv6.hdr.dst_addr));
 563         }
 564         item.spec = &ipv6;
 565         item.mask = &ipv6_mask;
 566         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 567                                              MLX5_MODIFICATION_TYPE_SET, error);
 568 }
 569
 570 /**
 571  * Convert modify-header set MAC address action to DV specification.
 572  *
 573  * @param[in,out] resource
 574  *   Pointer to the modify-header resource.
 575  * @param[in] action
 576  *   Pointer to action specification.
 577  * @param[out] error
 578  *   Pointer to the error structure.
 579  *
 580  * @return
 581  *   0 on success, a negative errno value otherwise and rte_errno is set.
 582  */
 583 static int
 584 flow_dv_convert_action_modify_mac
 585                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 586                          const struct rte_flow_action *action,
 587                          struct rte_flow_error *error)
 588 {
 589         const struct rte_flow_action_set_mac *conf =
 590                 (const struct rte_flow_action_set_mac *)(action->conf);
 591         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 592         struct rte_flow_item_eth eth;
 593         struct rte_flow_item_eth eth_mask;
 594
 595         memset(&eth, 0, sizeof(eth));
 596         memset(&eth_mask, 0, sizeof(eth_mask));
 597         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 598                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 599                        sizeof(eth.src.addr_bytes));
 600                 memcpy(&eth_mask.src.addr_bytes,
 601                        &rte_flow_item_eth_mask.src.addr_bytes,
 602                        sizeof(eth_mask.src.addr_bytes));
 603         } else {
 604                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 605                        sizeof(eth.dst.addr_bytes));
 606                 memcpy(&eth_mask.dst.addr_bytes,
 607                        &rte_flow_item_eth_mask.dst.addr_bytes,
 608                        sizeof(eth_mask.dst.addr_bytes));
 609         }
 610         item.spec = &eth;
 611         item.mask = &eth_mask;
 612         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 613                                              MLX5_MODIFICATION_TYPE_SET, error);
 614 }
 615
 616 /**
 617  * Convert modify-header set VLAN VID action to DV specification.
 618  *
 619  * @param[in,out] resource
 620  *   Pointer to the modify-header resource.
 621  * @param[in] action
 622  *   Pointer to action specification.
 623  * @param[out] error
 624  *   Pointer to the error structure.
 625  *
 626  * @return
 627  *   0 on success, a negative errno value otherwise and rte_errno is set.
 628  */
 629 static int
 630 flow_dv_convert_action_modify_vlan_vid
 631                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 632                          const struct rte_flow_action *action,
 633                          struct rte_flow_error *error)
 634 {
 635         const struct rte_flow_action_of_set_vlan_vid *conf =
 636                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 637         int i = resource->actions_num;
 638         struct mlx5_modification_cmd *actions = resource->actions;
 639         struct field_modify_info *field = modify_vlan_out_first_vid;
 640
 641         if (i >= MLX5_MAX_MODIFY_NUM)
 642                 return rte_flow_error_set(error, EINVAL,
 643                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 644                          "too many items to modify");
 645         actions[i] = (struct mlx5_modification_cmd) {
 646                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 647                 .field = field->id,
 648                 .length = field->size,
 649                 .offset = field->offset,
 650         };
 651         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 652         actions[i].data1 = conf->vlan_vid;
 653         actions[i].data1 = actions[i].data1 << 16;
 654         resource->actions_num = ++i;
 655         return 0;
 656 }
 657
 658 /**
 659  * Convert modify-header set TP action to DV specification.
 660  *
 661  * @param[in,out] resource
 662  *   Pointer to the modify-header resource.
 663  * @param[in] action
 664  *   Pointer to action specification.
 665  * @param[in] items
 666  *   Pointer to rte_flow_item objects list.
 667  * @param[in] attr
 668  *   Pointer to flow attributes structure.
 669  * @param[in] dev_flow
 670  *   Pointer to the sub flow.
 671  * @param[in] tunnel_decap
 672  *   Whether action is after tunnel decapsulation.
 673  * @param[out] error
 674  *   Pointer to the error structure.
 675  *
 676  * @return
 677  *   0 on success, a negative errno value otherwise and rte_errno is set.
 678  */
 679 static int
 680 flow_dv_convert_action_modify_tp
 681                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 682                          const struct rte_flow_action *action,
 683                          const struct rte_flow_item *items,
 684                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 685                          bool tunnel_decap, struct rte_flow_error *error)
 686 {
 687         const struct rte_flow_action_set_tp *conf =
 688                 (const struct rte_flow_action_set_tp *)(action->conf);
 689         struct rte_flow_item item;
 690         struct rte_flow_item_udp udp;
 691         struct rte_flow_item_udp udp_mask;
 692         struct rte_flow_item_tcp tcp;
 693         struct rte_flow_item_tcp tcp_mask;
 694         struct field_modify_info *field;
 695
 696         if (!attr->valid)
 697                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 698         if (attr->udp) {
 699                 memset(&udp, 0, sizeof(udp));
 700                 memset(&udp_mask, 0, sizeof(udp_mask));
 701                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 702                         udp.hdr.src_port = conf->port;
 703                         udp_mask.hdr.src_port =
 704                                         rte_flow_item_udp_mask.hdr.src_port;
 705                 } else {
 706                         udp.hdr.dst_port = conf->port;
 707                         udp_mask.hdr.dst_port =
 708                                         rte_flow_item_udp_mask.hdr.dst_port;
 709                 }
 710                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 711                 item.spec = &udp;
 712                 item.mask = &udp_mask;
 713                 field = modify_udp;
 714         } else {
 715                 MLX5_ASSERT(attr->tcp);
 716                 memset(&tcp, 0, sizeof(tcp));
 717                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 718                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 719                         tcp.hdr.src_port = conf->port;
 720                         tcp_mask.hdr.src_port =
 721                                         rte_flow_item_tcp_mask.hdr.src_port;
 722                 } else {
 723                         tcp.hdr.dst_port = conf->port;
 724                         tcp_mask.hdr.dst_port =
 725                                         rte_flow_item_tcp_mask.hdr.dst_port;
 726                 }
 727                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 728                 item.spec = &tcp;
 729                 item.mask = &tcp_mask;
 730                 field = modify_tcp;
 731         }
 732         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 733                                              MLX5_MODIFICATION_TYPE_SET, error);
 734 }
 735
 736 /**
 737  * Convert modify-header set TTL action to DV specification.
 738  *
 739  * @param[in,out] resource
 740  *   Pointer to the modify-header resource.
 741  * @param[in] action
 742  *   Pointer to action specification.
 743  * @param[in] items
 744  *   Pointer to rte_flow_item objects list.
 745  * @param[in] attr
 746  *   Pointer to flow attributes structure.
 747  * @param[in] dev_flow
 748  *   Pointer to the sub flow.
 749  * @param[in] tunnel_decap
 750  *   Whether action is after tunnel decapsulation.
 751  * @param[out] error
 752  *   Pointer to the error structure.
 753  *
 754  * @return
 755  *   0 on success, a negative errno value otherwise and rte_errno is set.
 756  */
 757 static int
 758 flow_dv_convert_action_modify_ttl
 759                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 760                          const struct rte_flow_action *action,
 761                          const struct rte_flow_item *items,
 762                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 763                          bool tunnel_decap, struct rte_flow_error *error)
 764 {
 765         const struct rte_flow_action_set_ttl *conf =
 766                 (const struct rte_flow_action_set_ttl *)(action->conf);
 767         struct rte_flow_item item;
 768         struct rte_flow_item_ipv4 ipv4;
 769         struct rte_flow_item_ipv4 ipv4_mask;
 770         struct rte_flow_item_ipv6 ipv6;
 771         struct rte_flow_item_ipv6 ipv6_mask;
 772         struct field_modify_info *field;
 773
 774         if (!attr->valid)
 775                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 776         if (attr->ipv4) {
 777                 memset(&ipv4, 0, sizeof(ipv4));
 778                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 779                 ipv4.hdr.time_to_live = conf->ttl_value;
 780                 ipv4_mask.hdr.time_to_live = 0xFF;
 781                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 782                 item.spec = &ipv4;
 783                 item.mask = &ipv4_mask;
 784                 field = modify_ipv4;
 785         } else {
 786                 MLX5_ASSERT(attr->ipv6);
 787                 memset(&ipv6, 0, sizeof(ipv6));
 788                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 789                 ipv6.hdr.hop_limits = conf->ttl_value;
 790                 ipv6_mask.hdr.hop_limits = 0xFF;
 791                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 792                 item.spec = &ipv6;
 793                 item.mask = &ipv6_mask;
 794                 field = modify_ipv6;
 795         }
 796         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 797                                              MLX5_MODIFICATION_TYPE_SET, error);
 798 }
 799
 800 /**
 801  * Convert modify-header decrement TTL action to DV specification.
 802  *
 803  * @param[in,out] resource
 804  *   Pointer to the modify-header resource.
 805  * @param[in] action
 806  *   Pointer to action specification.
 807  * @param[in] items
 808  *   Pointer to rte_flow_item objects list.
 809  * @param[in] attr
 810  *   Pointer to flow attributes structure.
 811  * @param[in] dev_flow
 812  *   Pointer to the sub flow.
 813  * @param[in] tunnel_decap
 814  *   Whether action is after tunnel decapsulation.
 815  * @param[out] error
 816  *   Pointer to the error structure.
 817  *
 818  * @return
 819  *   0 on success, a negative errno value otherwise and rte_errno is set.
 820  */
 821 static int
 822 flow_dv_convert_action_modify_dec_ttl
 823                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 824                          const struct rte_flow_item *items,
 825                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 826                          bool tunnel_decap, struct rte_flow_error *error)
 827 {
 828         struct rte_flow_item item;
 829         struct rte_flow_item_ipv4 ipv4;
 830         struct rte_flow_item_ipv4 ipv4_mask;
 831         struct rte_flow_item_ipv6 ipv6;
 832         struct rte_flow_item_ipv6 ipv6_mask;
 833         struct field_modify_info *field;
 834
 835         if (!attr->valid)
 836                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 837         if (attr->ipv4) {
 838                 memset(&ipv4, 0, sizeof(ipv4));
 839                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 840                 ipv4.hdr.time_to_live = 0xFF;
 841                 ipv4_mask.hdr.time_to_live = 0xFF;
 842                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 843                 item.spec = &ipv4;
 844                 item.mask = &ipv4_mask;
 845                 field = modify_ipv4;
 846         } else {
 847                 MLX5_ASSERT(attr->ipv6);
 848                 memset(&ipv6, 0, sizeof(ipv6));
 849                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 850                 ipv6.hdr.hop_limits = 0xFF;
 851                 ipv6_mask.hdr.hop_limits = 0xFF;
 852                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 853                 item.spec = &ipv6;
 854                 item.mask = &ipv6_mask;
 855                 field = modify_ipv6;
 856         }
 857         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 858                                              MLX5_MODIFICATION_TYPE_ADD, error);
 859 }
 860
 861 /**
 862  * Convert modify-header increment/decrement TCP Sequence number
 863  * to DV specification.
 864  *
 865  * @param[in,out] resource
 866  *   Pointer to the modify-header resource.
 867  * @param[in] action
 868  *   Pointer to action specification.
 869  * @param[out] error
 870  *   Pointer to the error structure.
 871  *
 872  * @return
 873  *   0 on success, a negative errno value otherwise and rte_errno is set.
 874  */
 875 static int
 876 flow_dv_convert_action_modify_tcp_seq
 877                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 878                          const struct rte_flow_action *action,
 879                          struct rte_flow_error *error)
 880 {
 881         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 882         uint64_t value = rte_be_to_cpu_32(*conf);
 883         struct rte_flow_item item;
 884         struct rte_flow_item_tcp tcp;
 885         struct rte_flow_item_tcp tcp_mask;
 886
 887         memset(&tcp, 0, sizeof(tcp));
 888         memset(&tcp_mask, 0, sizeof(tcp_mask));
 889         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 890                 /*
 891                  * The HW has no decrement operation, only increment operation.
 892                  * To simulate decrement X from Y using increment operation
 893                  * we need to add UINT32_MAX X times to Y.
 894                  * Each adding of UINT32_MAX decrements Y by 1.
 895                  */
 896                 value *= UINT32_MAX;
 897         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 898         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 899         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 900         item.spec = &tcp;
 901         item.mask = &tcp_mask;
 902         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 903                                              MLX5_MODIFICATION_TYPE_ADD, error);
 904 }
 905
 906 /**
 907  * Convert modify-header increment/decrement TCP Acknowledgment number
 908  * to DV specification.
 909  *
 910  * @param[in,out] resource
 911  *   Pointer to the modify-header resource.
 912  * @param[in] action
 913  *   Pointer to action specification.
 914  * @param[out] error
 915  *   Pointer to the error structure.
 916  *
 917  * @return
 918  *   0 on success, a negative errno value otherwise and rte_errno is set.
 919  */
 920 static int
 921 flow_dv_convert_action_modify_tcp_ack
 922                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 923                          const struct rte_flow_action *action,
 924                          struct rte_flow_error *error)
 925 {
 926         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 927         uint64_t value = rte_be_to_cpu_32(*conf);
 928         struct rte_flow_item item;
 929         struct rte_flow_item_tcp tcp;
 930         struct rte_flow_item_tcp tcp_mask;
 931
 932         memset(&tcp, 0, sizeof(tcp));
 933         memset(&tcp_mask, 0, sizeof(tcp_mask));
 934         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 935                 /*
 936                  * The HW has no decrement operation, only increment operation.
 937                  * To simulate decrement X from Y using increment operation
 938                  * we need to add UINT32_MAX X times to Y.
 939                  * Each adding of UINT32_MAX decrements Y by 1.
 940                  */
 941                 value *= UINT32_MAX;
 942         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 943         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 944         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 945         item.spec = &tcp;
 946         item.mask = &tcp_mask;
 947         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 948                                              MLX5_MODIFICATION_TYPE_ADD, error);
 949 }
 950
 951 static enum mlx5_modification_field reg_to_field[] = {
 952         [REG_NONE] = MLX5_MODI_OUT_NONE,
 953         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 954         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 955         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 956         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 957         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 958         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 959         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 960         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 961         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 962         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 963 };
 964
 965 /**
 966  * Convert register set to DV specification.
 967  *
 968  * @param[in,out] resource
 969  *   Pointer to the modify-header resource.
 970  * @param[in] action
 971  *   Pointer to action specification.
 972  * @param[out] error
 973  *   Pointer to the error structure.
 974  *
 975  * @return
 976  *   0 on success, a negative errno value otherwise and rte_errno is set.
 977  */
 978 static int
 979 flow_dv_convert_action_set_reg
 980                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 981                          const struct rte_flow_action *action,
 982                          struct rte_flow_error *error)
 983 {
 984         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 985         struct mlx5_modification_cmd *actions = resource->actions;
 986         uint32_t i = resource->actions_num;
 987
 988         if (i >= MLX5_MAX_MODIFY_NUM)
 989                 return rte_flow_error_set(error, EINVAL,
 990                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 991                                           "too many items to modify");
 992         MLX5_ASSERT(conf->id != REG_NONE);
 993         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 994         actions[i] = (struct mlx5_modification_cmd) {
 995                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 996                 .field = reg_to_field[conf->id],
 997         };
 998         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 999         actions[i].data1 = rte_cpu_to_be_32(conf->data);
1000         ++i;
1001         resource->actions_num = i;
1002         return 0;
1003 }
1004
1005 /**
1006  * Convert SET_TAG action to DV specification.
1007  *
1008  * @param[in] dev
1009  *   Pointer to the rte_eth_dev structure.
1010  * @param[in,out] resource
1011  *   Pointer to the modify-header resource.
1012  * @param[in] conf
1013  *   Pointer to action specification.
1014  * @param[out] error
1015  *   Pointer to the error structure.
1016  *
1017  * @return
1018  *   0 on success, a negative errno value otherwise and rte_errno is set.
1019  */
1020 static int
1021 flow_dv_convert_action_set_tag
1022                         (struct rte_eth_dev *dev,
1023                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1024                          const struct rte_flow_action_set_tag *conf,
1025                          struct rte_flow_error *error)
1026 {
1027         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1028         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1029         struct rte_flow_item item = {
1030                 .spec = &data,
1031                 .mask = &mask,
1032         };
1033         struct field_modify_info reg_c_x[] = {
1034                 [1] = {0, 0, 0},
1035         };
1036         enum mlx5_modification_field reg_type;
1037         int ret;
1038
1039         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1040         if (ret < 0)
1041                 return ret;
1042         MLX5_ASSERT(ret != REG_NONE);
1043         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1044         reg_type = reg_to_field[ret];
1045         MLX5_ASSERT(reg_type > 0);
1046         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1047         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1048                                              MLX5_MODIFICATION_TYPE_SET, error);
1049 }
1050
1051 /**
1052  * Convert internal COPY_REG action to DV specification.
1053  *
1054  * @param[in] dev
1055  *   Pointer to the rte_eth_dev structure.
1056  * @param[in,out] res
1057  *   Pointer to the modify-header resource.
1058  * @param[in] action
1059  *   Pointer to action specification.
1060  * @param[out] error
1061  *   Pointer to the error structure.
1062  *
1063  * @return
1064  *   0 on success, a negative errno value otherwise and rte_errno is set.
1065  */
1066 static int
1067 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1068                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1069                                  const struct rte_flow_action *action,
1070                                  struct rte_flow_error *error)
1071 {
1072         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1073         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1074         struct rte_flow_item item = {
1075                 .spec = NULL,
1076                 .mask = &mask,
1077         };
1078         struct field_modify_info reg_src[] = {
1079                 {4, 0, reg_to_field[conf->src]},
1080                 {0, 0, 0},
1081         };
1082         struct field_modify_info reg_dst = {
1083                 .offset = 0,
1084                 .id = reg_to_field[conf->dst],
1085         };
1086         /* Adjust reg_c[0] usage according to reported mask. */
1087         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1088                 struct mlx5_priv *priv = dev->data->dev_private;
1089                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1090
1091                 MLX5_ASSERT(reg_c0);
1092                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1093                 if (conf->dst == REG_C_0) {
1094                         /* Copy to reg_c[0], within mask only. */
1095                         reg_dst.offset = rte_bsf32(reg_c0);
1096                         /*
1097                          * Mask is ignoring the enianness, because
1098                          * there is no conversion in datapath.
1099                          */
1100 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1101                         /* Copy from destination lower bits to reg_c[0]. */
1102                         mask = reg_c0 >> reg_dst.offset;
1103 #else
1104                         /* Copy from destination upper bits to reg_c[0]. */
1105                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1106                                           rte_fls_u32(reg_c0));
1107 #endif
1108                 } else {
1109                         mask = rte_cpu_to_be_32(reg_c0);
1110 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1111                         /* Copy from reg_c[0] to destination lower bits. */
1112                         reg_dst.offset = 0;
1113 #else
1114                         /* Copy from reg_c[0] to destination upper bits. */
1115                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1116                                          (rte_fls_u32(reg_c0) -
1117                                           rte_bsf32(reg_c0));
1118 #endif
1119                 }
1120         }
1121         return flow_dv_convert_modify_action(&item,
1122                                              reg_src, &reg_dst, res,
1123                                              MLX5_MODIFICATION_TYPE_COPY,
1124                                              error);
1125 }
1126
1127 /**
1128  * Convert MARK action to DV specification. This routine is used
1129  * in extensive metadata only and requires metadata register to be
1130  * handled. In legacy mode hardware tag resource is engaged.
1131  *
1132  * @param[in] dev
1133  *   Pointer to the rte_eth_dev structure.
1134  * @param[in] conf
1135  *   Pointer to MARK action specification.
1136  * @param[in,out] resource
1137  *   Pointer to the modify-header resource.
1138  * @param[out] error
1139  *   Pointer to the error structure.
1140  *
1141  * @return
1142  *   0 on success, a negative errno value otherwise and rte_errno is set.
1143  */
1144 static int
1145 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1146                             const struct rte_flow_action_mark *conf,
1147                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1148                             struct rte_flow_error *error)
1149 {
1150         struct mlx5_priv *priv = dev->data->dev_private;
1151         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1152                                            priv->sh->dv_mark_mask);
1153         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1154         struct rte_flow_item item = {
1155                 .spec = &data,
1156                 .mask = &mask,
1157         };
1158         struct field_modify_info reg_c_x[] = {
1159                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1160                 {0, 0, 0},
1161         };
1162         int reg;
1163
1164         if (!mask)
1165                 return rte_flow_error_set(error, EINVAL,
1166                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1167                                           NULL, "zero mark action mask");
1168         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1169         if (reg < 0)
1170                 return reg;
1171         MLX5_ASSERT(reg > 0);
1172         if (reg == REG_C_0) {
1173                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1174                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1175
1176                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1177                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1178                 mask = rte_cpu_to_be_32(mask << shl_c0);
1179         }
1180         reg_c_x[0].id = reg_to_field[reg];
1181         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1182                                              MLX5_MODIFICATION_TYPE_SET, error);
1183 }
1184
1185 /**
1186  * Get metadata register index for specified steering domain.
1187  *
1188  * @param[in] dev
1189  *   Pointer to the rte_eth_dev structure.
1190  * @param[in] attr
1191  *   Attributes of flow to determine steering domain.
1192  * @param[out] error
1193  *   Pointer to the error structure.
1194  *
1195  * @return
1196  *   positive index on success, a negative errno value otherwise
1197  *   and rte_errno is set.
1198  */
1199 static enum modify_reg
1200 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1201                          const struct rte_flow_attr *attr,
1202                          struct rte_flow_error *error)
1203 {
1204         int reg =
1205                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1206                                           MLX5_METADATA_FDB :
1207                                             attr->egress ?
1208                                             MLX5_METADATA_TX :
1209                                             MLX5_METADATA_RX, 0, error);
1210         if (reg < 0)
1211                 return rte_flow_error_set(error,
1212                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1213                                           NULL, "unavailable "
1214                                           "metadata register");
1215         return reg;
1216 }
1217
1218 /**
1219  * Convert SET_META action to DV specification.
1220  *
1221  * @param[in] dev
1222  *   Pointer to the rte_eth_dev structure.
1223  * @param[in,out] resource
1224  *   Pointer to the modify-header resource.
1225  * @param[in] attr
1226  *   Attributes of flow that includes this item.
1227  * @param[in] conf
1228  *   Pointer to action specification.
1229  * @param[out] error
1230  *   Pointer to the error structure.
1231  *
1232  * @return
1233  *   0 on success, a negative errno value otherwise and rte_errno is set.
1234  */
1235 static int
1236 flow_dv_convert_action_set_meta
1237                         (struct rte_eth_dev *dev,
1238                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1239                          const struct rte_flow_attr *attr,
1240                          const struct rte_flow_action_set_meta *conf,
1241                          struct rte_flow_error *error)
1242 {
1243         uint32_t data = conf->data;
1244         uint32_t mask = conf->mask;
1245         struct rte_flow_item item = {
1246                 .spec = &data,
1247                 .mask = &mask,
1248         };
1249         struct field_modify_info reg_c_x[] = {
1250                 [1] = {0, 0, 0},
1251         };
1252         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1253
1254         if (reg < 0)
1255                 return reg;
1256         /*
1257          * In datapath code there is no endianness
1258          * coversions for perfromance reasons, all
1259          * pattern conversions are done in rte_flow.
1260          */
1261         if (reg == REG_C_0) {
1262                 struct mlx5_priv *priv = dev->data->dev_private;
1263                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1264                 uint32_t shl_c0;
1265
1266                 MLX5_ASSERT(msk_c0);
1267 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1268                 shl_c0 = rte_bsf32(msk_c0);
1269 #else
1270                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1271 #endif
1272                 mask <<= shl_c0;
1273                 data <<= shl_c0;
1274                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1275         }
1276         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1277         /* The routine expects parameters in memory as big-endian ones. */
1278         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1279                                              MLX5_MODIFICATION_TYPE_SET, error);
1280 }
1281
1282 /**
1283  * Convert modify-header set IPv4 DSCP action to DV specification.
1284  *
1285  * @param[in,out] resource
1286  *   Pointer to the modify-header resource.
1287  * @param[in] action
1288  *   Pointer to action specification.
1289  * @param[out] error
1290  *   Pointer to the error structure.
1291  *
1292  * @return
1293  *   0 on success, a negative errno value otherwise and rte_errno is set.
1294  */
1295 static int
1296 flow_dv_convert_action_modify_ipv4_dscp
1297                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1298                          const struct rte_flow_action *action,
1299                          struct rte_flow_error *error)
1300 {
1301         const struct rte_flow_action_set_dscp *conf =
1302                 (const struct rte_flow_action_set_dscp *)(action->conf);
1303         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1304         struct rte_flow_item_ipv4 ipv4;
1305         struct rte_flow_item_ipv4 ipv4_mask;
1306
1307         memset(&ipv4, 0, sizeof(ipv4));
1308         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1309         ipv4.hdr.type_of_service = conf->dscp;
1310         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1311         item.spec = &ipv4;
1312         item.mask = &ipv4_mask;
1313         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1314                                              MLX5_MODIFICATION_TYPE_SET, error);
1315 }
1316
1317 /**
1318  * Convert modify-header set IPv6 DSCP action to DV specification.
1319  *
1320  * @param[in,out] resource
1321  *   Pointer to the modify-header resource.
1322  * @param[in] action
1323  *   Pointer to action specification.
1324  * @param[out] error
1325  *   Pointer to the error structure.
1326  *
1327  * @return
1328  *   0 on success, a negative errno value otherwise and rte_errno is set.
1329  */
1330 static int
1331 flow_dv_convert_action_modify_ipv6_dscp
1332                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1333                          const struct rte_flow_action *action,
1334                          struct rte_flow_error *error)
1335 {
1336         const struct rte_flow_action_set_dscp *conf =
1337                 (const struct rte_flow_action_set_dscp *)(action->conf);
1338         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1339         struct rte_flow_item_ipv6 ipv6;
1340         struct rte_flow_item_ipv6 ipv6_mask;
1341
1342         memset(&ipv6, 0, sizeof(ipv6));
1343         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1344         /*
1345          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1346          * rdma-core only accept the DSCP bits byte aligned start from
1347          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1348          * bits in IPv6 case as rdma-core requires byte aligned value.
1349          */
1350         ipv6.hdr.vtc_flow = conf->dscp;
1351         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1352         item.spec = &ipv6;
1353         item.mask = &ipv6_mask;
1354         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1355                                              MLX5_MODIFICATION_TYPE_SET, error);
1356 }
1357
1358 /**
1359  * Validate MARK item.
1360  *
1361  * @param[in] dev
1362  *   Pointer to the rte_eth_dev structure.
1363  * @param[in] item
1364  *   Item specification.
1365  * @param[in] attr
1366  *   Attributes of flow that includes this item.
1367  * @param[out] error
1368  *   Pointer to error structure.
1369  *
1370  * @return
1371  *   0 on success, a negative errno value otherwise and rte_errno is set.
1372  */
1373 static int
1374 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1375                            const struct rte_flow_item *item,
1376                            const struct rte_flow_attr *attr __rte_unused,
1377                            struct rte_flow_error *error)
1378 {
1379         struct mlx5_priv *priv = dev->data->dev_private;
1380         struct mlx5_dev_config *config = &priv->config;
1381         const struct rte_flow_item_mark *spec = item->spec;
1382         const struct rte_flow_item_mark *mask = item->mask;
1383         const struct rte_flow_item_mark nic_mask = {
1384                 .id = priv->sh->dv_mark_mask,
1385         };
1386         int ret;
1387
1388         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1389                 return rte_flow_error_set(error, ENOTSUP,
1390                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1391                                           "extended metadata feature"
1392                                           " isn't enabled");
1393         if (!mlx5_flow_ext_mreg_supported(dev))
1394                 return rte_flow_error_set(error, ENOTSUP,
1395                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1396                                           "extended metadata register"
1397                                           " isn't supported");
1398         if (!nic_mask.id)
1399                 return rte_flow_error_set(error, ENOTSUP,
1400                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1401                                           "extended metadata register"
1402                                           " isn't available");
1403         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1404         if (ret < 0)
1405                 return ret;
1406         if (!spec)
1407                 return rte_flow_error_set(error, EINVAL,
1408                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1409                                           item->spec,
1410                                           "data cannot be empty");
1411         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1412                 return rte_flow_error_set(error, EINVAL,
1413                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1414                                           &spec->id,
1415                                           "mark id exceeds the limit");
1416         if (!mask)
1417                 mask = &nic_mask;
1418         if (!mask->id)
1419                 return rte_flow_error_set(error, EINVAL,
1420                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1421                                         "mask cannot be zero");
1422
1423         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1424                                         (const uint8_t *)&nic_mask,
1425                                         sizeof(struct rte_flow_item_mark),
1426                                         error);
1427         if (ret < 0)
1428                 return ret;
1429         return 0;
1430 }
1431
1432 /**
1433  * Validate META item.
1434  *
1435  * @param[in] dev
1436  *   Pointer to the rte_eth_dev structure.
1437  * @param[in] item
1438  *   Item specification.
1439  * @param[in] attr
1440  *   Attributes of flow that includes this item.
1441  * @param[out] error
1442  *   Pointer to error structure.
1443  *
1444  * @return
1445  *   0 on success, a negative errno value otherwise and rte_errno is set.
1446  */
1447 static int
1448 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1449                            const struct rte_flow_item *item,
1450                            const struct rte_flow_attr *attr,
1451                            struct rte_flow_error *error)
1452 {
1453         struct mlx5_priv *priv = dev->data->dev_private;
1454         struct mlx5_dev_config *config = &priv->config;
1455         const struct rte_flow_item_meta *spec = item->spec;
1456         const struct rte_flow_item_meta *mask = item->mask;
1457         struct rte_flow_item_meta nic_mask = {
1458                 .data = UINT32_MAX
1459         };
1460         int reg;
1461         int ret;
1462
1463         if (!spec)
1464                 return rte_flow_error_set(error, EINVAL,
1465                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1466                                           item->spec,
1467                                           "data cannot be empty");
1468         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1469                 if (!mlx5_flow_ext_mreg_supported(dev))
1470                         return rte_flow_error_set(error, ENOTSUP,
1471                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1472                                           "extended metadata register"
1473                                           " isn't supported");
1474                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1475                 if (reg < 0)
1476                         return reg;
1477                 if (reg == REG_B)
1478                         return rte_flow_error_set(error, ENOTSUP,
1479                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1480                                           "match on reg_b "
1481                                           "isn't supported");
1482                 if (reg != REG_A)
1483                         nic_mask.data = priv->sh->dv_meta_mask;
1484         }
1485         if (!mask)
1486                 mask = &rte_flow_item_meta_mask;
1487         if (!mask->data)
1488                 return rte_flow_error_set(error, EINVAL,
1489                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1490                                         "mask cannot be zero");
1491
1492         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1493                                         (const uint8_t *)&nic_mask,
1494                                         sizeof(struct rte_flow_item_meta),
1495                                         error);
1496         return ret;
1497 }
1498
1499 /**
1500  * Validate TAG item.
1501  *
1502  * @param[in] dev
1503  *   Pointer to the rte_eth_dev structure.
1504  * @param[in] item
1505  *   Item specification.
1506  * @param[in] attr
1507  *   Attributes of flow that includes this item.
1508  * @param[out] error
1509  *   Pointer to error structure.
1510  *
1511  * @return
1512  *   0 on success, a negative errno value otherwise and rte_errno is set.
1513  */
1514 static int
1515 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1516                           const struct rte_flow_item *item,
1517                           const struct rte_flow_attr *attr __rte_unused,
1518                           struct rte_flow_error *error)
1519 {
1520         const struct rte_flow_item_tag *spec = item->spec;
1521         const struct rte_flow_item_tag *mask = item->mask;
1522         const struct rte_flow_item_tag nic_mask = {
1523                 .data = RTE_BE32(UINT32_MAX),
1524                 .index = 0xff,
1525         };
1526         int ret;
1527
1528         if (!mlx5_flow_ext_mreg_supported(dev))
1529                 return rte_flow_error_set(error, ENOTSUP,
1530                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1531                                           "extensive metadata register"
1532                                           " isn't supported");
1533         if (!spec)
1534                 return rte_flow_error_set(error, EINVAL,
1535                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1536                                           item->spec,
1537                                           "data cannot be empty");
1538         if (!mask)
1539                 mask = &rte_flow_item_tag_mask;
1540         if (!mask->data)
1541                 return rte_flow_error_set(error, EINVAL,
1542                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1543                                         "mask cannot be zero");
1544
1545         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1546                                         (const uint8_t *)&nic_mask,
1547                                         sizeof(struct rte_flow_item_tag),
1548                                         error);
1549         if (ret < 0)
1550                 return ret;
1551         if (mask->index != 0xff)
1552                 return rte_flow_error_set(error, EINVAL,
1553                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1554                                           "partial mask for tag index"
1555                                           " is not supported");
1556         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1557         if (ret < 0)
1558                 return ret;
1559         MLX5_ASSERT(ret != REG_NONE);
1560         return 0;
1561 }
1562
1563 /**
1564  * Validate vport item.
1565  *
1566  * @param[in] dev
1567  *   Pointer to the rte_eth_dev structure.
1568  * @param[in] item
1569  *   Item specification.
1570  * @param[in] attr
1571  *   Attributes of flow that includes this item.
1572  * @param[in] item_flags
1573  *   Bit-fields that holds the items detected until now.
1574  * @param[out] error
1575  *   Pointer to error structure.
1576  *
1577  * @return
1578  *   0 on success, a negative errno value otherwise and rte_errno is set.
1579  */
1580 static int
1581 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1582                               const struct rte_flow_item *item,
1583                               const struct rte_flow_attr *attr,
1584                               uint64_t item_flags,
1585                               struct rte_flow_error *error)
1586 {
1587         const struct rte_flow_item_port_id *spec = item->spec;
1588         const struct rte_flow_item_port_id *mask = item->mask;
1589         const struct rte_flow_item_port_id switch_mask = {
1590                         .id = 0xffffffff,
1591         };
1592         struct mlx5_priv *esw_priv;
1593         struct mlx5_priv *dev_priv;
1594         int ret;
1595
1596         if (!attr->transfer)
1597                 return rte_flow_error_set(error, EINVAL,
1598                                           RTE_FLOW_ERROR_TYPE_ITEM,
1599                                           NULL,
1600                                           "match on port id is valid only"
1601                                           " when transfer flag is enabled");
1602         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1603                 return rte_flow_error_set(error, ENOTSUP,
1604                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1605                                           "multiple source ports are not"
1606                                           " supported");
1607         if (!mask)
1608                 mask = &switch_mask;
1609         if (mask->id != 0xffffffff)
1610                 return rte_flow_error_set(error, ENOTSUP,
1611                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1612                                            mask,
1613                                            "no support for partial mask on"
1614                                            " \"id\" field");
1615         ret = mlx5_flow_item_acceptable
1616                                 (item, (const uint8_t *)mask,
1617                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1618                                  sizeof(struct rte_flow_item_port_id),
1619                                  error);
1620         if (ret)
1621                 return ret;
1622         if (!spec)
1623                 return 0;
1624         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1625         if (!esw_priv)
1626                 return rte_flow_error_set(error, rte_errno,
1627                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1628                                           "failed to obtain E-Switch info for"
1629                                           " port");
1630         dev_priv = mlx5_dev_to_eswitch_info(dev);
1631         if (!dev_priv)
1632                 return rte_flow_error_set(error, rte_errno,
1633                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1634                                           NULL,
1635                                           "failed to obtain E-Switch info");
1636         if (esw_priv->domain_id != dev_priv->domain_id)
1637                 return rte_flow_error_set(error, EINVAL,
1638                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1639                                           "cannot match on a port from a"
1640                                           " different E-Switch");
1641         return 0;
1642 }
1643
1644 /**
1645  * Validate GTP item.
1646  *
1647  * @param[in] dev
1648  *   Pointer to the rte_eth_dev structure.
1649  * @param[in] item
1650  *   Item specification.
1651  * @param[in] item_flags
1652  *   Bit-fields that holds the items detected until now.
1653  * @param[out] error
1654  *   Pointer to error structure.
1655  *
1656  * @return
1657  *   0 on success, a negative errno value otherwise and rte_errno is set.
1658  */
1659 static int
1660 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1661                           const struct rte_flow_item *item,
1662                           uint64_t item_flags,
1663                           struct rte_flow_error *error)
1664 {
1665         struct mlx5_priv *priv = dev->data->dev_private;
1666         const struct rte_flow_item_gtp *mask = item->mask;
1667         const struct rte_flow_item_gtp nic_mask = {
1668                 .msg_type = 0xff,
1669                 .teid = RTE_BE32(0xffffffff),
1670         };
1671
1672         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1673                 return rte_flow_error_set(error, ENOTSUP,
1674                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1675                                           "GTP support is not enabled");
1676         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1677                 return rte_flow_error_set(error, ENOTSUP,
1678                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1679                                           "multiple tunnel layers not"
1680                                           " supported");
1681         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1682                 return rte_flow_error_set(error, EINVAL,
1683                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1684                                           "no outer UDP layer found");
1685         if (!mask)
1686                 mask = &rte_flow_item_gtp_mask;
1687         return mlx5_flow_item_acceptable
1688                 (item, (const uint8_t *)mask,
1689                  (const uint8_t *)&nic_mask,
1690                  sizeof(struct rte_flow_item_gtp),
1691                  error);
1692 }
1693
1694 /**
1695  * Validate the pop VLAN action.
1696  *
1697  * @param[in] dev
1698  *   Pointer to the rte_eth_dev structure.
1699  * @param[in] action_flags
1700  *   Holds the actions detected until now.
1701  * @param[in] action
1702  *   Pointer to the pop vlan action.
1703  * @param[in] item_flags
1704  *   The items found in this flow rule.
1705  * @param[in] attr
1706  *   Pointer to flow attributes.
1707  * @param[out] error
1708  *   Pointer to error structure.
1709  *
1710  * @return
1711  *   0 on success, a negative errno value otherwise and rte_errno is set.
1712  */
1713 static int
1714 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1715                                  uint64_t action_flags,
1716                                  const struct rte_flow_action *action,
1717                                  uint64_t item_flags,
1718                                  const struct rte_flow_attr *attr,
1719                                  struct rte_flow_error *error)
1720 {
1721         const struct mlx5_priv *priv = dev->data->dev_private;
1722
1723         (void)action;
1724         (void)attr;
1725         if (!priv->sh->pop_vlan_action)
1726                 return rte_flow_error_set(error, ENOTSUP,
1727                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1728                                           NULL,
1729                                           "pop vlan action is not supported");
1730         if (attr->egress)
1731                 return rte_flow_error_set(error, ENOTSUP,
1732                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1733                                           NULL,
1734                                           "pop vlan action not supported for "
1735                                           "egress");
1736         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1737                 return rte_flow_error_set(error, ENOTSUP,
1738                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1739                                           "no support for multiple VLAN "
1740                                           "actions");
1741         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1742                 return rte_flow_error_set(error, ENOTSUP,
1743                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1744                                           NULL,
1745                                           "cannot pop vlan without a "
1746                                           "match on (outer) vlan in the flow");
1747         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1748                 return rte_flow_error_set(error, EINVAL,
1749                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1750                                           "wrong action order, port_id should "
1751                                           "be after pop VLAN action");
1752         if (!attr->transfer && priv->representor)
1753                 return rte_flow_error_set(error, ENOTSUP,
1754                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1755                                           "pop vlan action for VF representor "
1756                                           "not supported on NIC table");
1757         return 0;
1758 }
1759
1760 /**
1761  * Get VLAN default info from vlan match info.
1762  *
1763  * @param[in] items
1764  *   the list of item specifications.
1765  * @param[out] vlan
1766  *   pointer VLAN info to fill to.
1767  *
1768  * @return
1769  *   0 on success, a negative errno value otherwise and rte_errno is set.
1770  */
1771 static void
1772 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1773                                   struct rte_vlan_hdr *vlan)
1774 {
1775         const struct rte_flow_item_vlan nic_mask = {
1776                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1777                                 MLX5DV_FLOW_VLAN_VID_MASK),
1778                 .inner_type = RTE_BE16(0xffff),
1779         };
1780
1781         if (items == NULL)
1782                 return;
1783         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1784                 int type = items->type;
1785
1786                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1787                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1788                         break;
1789         }
1790         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1791                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1792                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1793
1794                 if (!vlan_m)
1795                         vlan_m = &nic_mask;
1796                 /* Only full match values are accepted */
1797                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1798                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1799                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1800                         vlan->vlan_tci |=
1801                                 rte_be_to_cpu_16(vlan_v->tci &
1802                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1803                 }
1804                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1805                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1806                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1807                         vlan->vlan_tci |=
1808                                 rte_be_to_cpu_16(vlan_v->tci &
1809                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1810                 }
1811                 if (vlan_m->inner_type == nic_mask.inner_type)
1812                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1813                                                            vlan_m->inner_type);
1814         }
1815 }
1816
1817 /**
1818  * Validate the push VLAN action.
1819  *
1820  * @param[in] dev
1821  *   Pointer to the rte_eth_dev structure.
1822  * @param[in] action_flags
1823  *   Holds the actions detected until now.
1824  * @param[in] item_flags
1825  *   The items found in this flow rule.
1826  * @param[in] action
1827  *   Pointer to the action structure.
1828  * @param[in] attr
1829  *   Pointer to flow attributes
1830  * @param[out] error
1831  *   Pointer to error structure.
1832  *
1833  * @return
1834  *   0 on success, a negative errno value otherwise and rte_errno is set.
1835  */
1836 static int
1837 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1838                                   uint64_t action_flags,
1839                                   uint64_t item_flags __rte_unused,
1840                                   const struct rte_flow_action *action,
1841                                   const struct rte_flow_attr *attr,
1842                                   struct rte_flow_error *error)
1843 {
1844         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1845         const struct mlx5_priv *priv = dev->data->dev_private;
1846
1847         if (!attr->transfer && attr->ingress)
1848                 return rte_flow_error_set(error, ENOTSUP,
1849                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1850                                           NULL,
1851                                           "push VLAN action not supported for "
1852                                           "ingress");
1853         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1854             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1855                 return rte_flow_error_set(error, EINVAL,
1856                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1857                                           "invalid vlan ethertype");
1858         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1859                 return rte_flow_error_set(error, ENOTSUP,
1860                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1861                                           "no support for multiple VLAN "
1862                                           "actions");
1863         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1864                 return rte_flow_error_set(error, EINVAL,
1865                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1866                                           "wrong action order, port_id should "
1867                                           "be after push VLAN");
1868         if (!attr->transfer && priv->representor)
1869                 return rte_flow_error_set(error, ENOTSUP,
1870                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1871                                           "push vlan action for VF representor "
1872                                           "not supported on NIC table");
1873         (void)attr;
1874         return 0;
1875 }
1876
1877 /**
1878  * Validate the set VLAN PCP.
1879  *
1880  * @param[in] action_flags
1881  *   Holds the actions detected until now.
1882  * @param[in] actions
1883  *   Pointer to the list of actions remaining in the flow rule.
1884  * @param[out] error
1885  *   Pointer to error structure.
1886  *
1887  * @return
1888  *   0 on success, a negative errno value otherwise and rte_errno is set.
1889  */
1890 static int
1891 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1892                                      const struct rte_flow_action actions[],
1893                                      struct rte_flow_error *error)
1894 {
1895         const struct rte_flow_action *action = actions;
1896         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1897
1898         if (conf->vlan_pcp > 7)
1899                 return rte_flow_error_set(error, EINVAL,
1900                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1901                                           "VLAN PCP value is too big");
1902         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1903                 return rte_flow_error_set(error, ENOTSUP,
1904                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1905                                           "set VLAN PCP action must follow "
1906                                           "the push VLAN action");
1907         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1908                 return rte_flow_error_set(error, ENOTSUP,
1909                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1910                                           "Multiple VLAN PCP modification are "
1911                                           "not supported");
1912         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1913                 return rte_flow_error_set(error, EINVAL,
1914                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1915                                           "wrong action order, port_id should "
1916                                           "be after set VLAN PCP");
1917         return 0;
1918 }
1919
1920 /**
1921  * Validate the set VLAN VID.
1922  *
1923  * @param[in] item_flags
1924  *   Holds the items detected in this rule.
1925  * @param[in] action_flags
1926  *   Holds the actions detected until now.
1927  * @param[in] actions
1928  *   Pointer to the list of actions remaining in the flow rule.
1929  * @param[out] error
1930  *   Pointer to error structure.
1931  *
1932  * @return
1933  *   0 on success, a negative errno value otherwise and rte_errno is set.
1934  */
1935 static int
1936 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1937                                      uint64_t action_flags,
1938                                      const struct rte_flow_action actions[],
1939                                      struct rte_flow_error *error)
1940 {
1941         const struct rte_flow_action *action = actions;
1942         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1943
1944         if (conf->vlan_vid > RTE_BE16(0xFFE))
1945                 return rte_flow_error_set(error, EINVAL,
1946                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1947                                           "VLAN VID value is too big");
1948         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1949             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1950                 return rte_flow_error_set(error, ENOTSUP,
1951                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1952                                           "set VLAN VID action must follow push"
1953                                           " VLAN action or match on VLAN item");
1954         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1955                 return rte_flow_error_set(error, ENOTSUP,
1956                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1957                                           "Multiple VLAN VID modifications are "
1958                                           "not supported");
1959         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1960                 return rte_flow_error_set(error, EINVAL,
1961                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1962                                           "wrong action order, port_id should "
1963                                           "be after set VLAN VID");
1964         return 0;
1965 }
1966
1967 /*
1968  * Validate the FLAG action.
1969  *
1970  * @param[in] dev
1971  *   Pointer to the rte_eth_dev structure.
1972  * @param[in] action_flags
1973  *   Holds the actions detected until now.
1974  * @param[in] attr
1975  *   Pointer to flow attributes
1976  * @param[out] error
1977  *   Pointer to error structure.
1978  *
1979  * @return
1980  *   0 on success, a negative errno value otherwise and rte_errno is set.
1981  */
1982 static int
1983 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1984                              uint64_t action_flags,
1985                              const struct rte_flow_attr *attr,
1986                              struct rte_flow_error *error)
1987 {
1988         struct mlx5_priv *priv = dev->data->dev_private;
1989         struct mlx5_dev_config *config = &priv->config;
1990         int ret;
1991
1992         /* Fall back if no extended metadata register support. */
1993         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1994                 return mlx5_flow_validate_action_flag(action_flags, attr,
1995                                                       error);
1996         /* Extensive metadata mode requires registers. */
1997         if (!mlx5_flow_ext_mreg_supported(dev))
1998                 return rte_flow_error_set(error, ENOTSUP,
1999                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2000                                           "no metadata registers "
2001                                           "to support flag action");
2002         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2003                 return rte_flow_error_set(error, ENOTSUP,
2004                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2005                                           "extended metadata register"
2006                                           " isn't available");
2007         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2008         if (ret < 0)
2009                 return ret;
2010         MLX5_ASSERT(ret > 0);
2011         if (action_flags & MLX5_FLOW_ACTION_MARK)
2012                 return rte_flow_error_set(error, EINVAL,
2013                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2014                                           "can't mark and flag in same flow");
2015         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2016                 return rte_flow_error_set(error, EINVAL,
2017                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2018                                           "can't have 2 flag"
2019                                           " actions in same flow");
2020         return 0;
2021 }
2022
2023 /**
2024  * Validate MARK action.
2025  *
2026  * @param[in] dev
2027  *   Pointer to the rte_eth_dev structure.
2028  * @param[in] action
2029  *   Pointer to action.
2030  * @param[in] action_flags
2031  *   Holds the actions detected until now.
2032  * @param[in] attr
2033  *   Pointer to flow attributes
2034  * @param[out] error
2035  *   Pointer to error structure.
2036  *
2037  * @return
2038  *   0 on success, a negative errno value otherwise and rte_errno is set.
2039  */
2040 static int
2041 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2042                              const struct rte_flow_action *action,
2043                              uint64_t action_flags,
2044                              const struct rte_flow_attr *attr,
2045                              struct rte_flow_error *error)
2046 {
2047         struct mlx5_priv *priv = dev->data->dev_private;
2048         struct mlx5_dev_config *config = &priv->config;
2049         const struct rte_flow_action_mark *mark = action->conf;
2050         int ret;
2051
2052         /* Fall back if no extended metadata register support. */
2053         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2054                 return mlx5_flow_validate_action_mark(action, action_flags,
2055                                                       attr, error);
2056         /* Extensive metadata mode requires registers. */
2057         if (!mlx5_flow_ext_mreg_supported(dev))
2058                 return rte_flow_error_set(error, ENOTSUP,
2059                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2060                                           "no metadata registers "
2061                                           "to support mark action");
2062         if (!priv->sh->dv_mark_mask)
2063                 return rte_flow_error_set(error, ENOTSUP,
2064                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2065                                           "extended metadata register"
2066                                           " isn't available");
2067         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2068         if (ret < 0)
2069                 return ret;
2070         MLX5_ASSERT(ret > 0);
2071         if (!mark)
2072                 return rte_flow_error_set(error, EINVAL,
2073                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2074                                           "configuration cannot be null");
2075         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2076                 return rte_flow_error_set(error, EINVAL,
2077                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2078                                           &mark->id,
2079                                           "mark id exceeds the limit");
2080         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2081                 return rte_flow_error_set(error, EINVAL,
2082                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2083                                           "can't flag and mark in same flow");
2084         if (action_flags & MLX5_FLOW_ACTION_MARK)
2085                 return rte_flow_error_set(error, EINVAL,
2086                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2087                                           "can't have 2 mark actions in same"
2088                                           " flow");
2089         return 0;
2090 }
2091
2092 /**
2093  * Validate SET_META action.
2094  *
2095  * @param[in] dev
2096  *   Pointer to the rte_eth_dev structure.
2097  * @param[in] action
2098  *   Pointer to the action structure.
2099  * @param[in] action_flags
2100  *   Holds the actions detected until now.
2101  * @param[in] attr
2102  *   Pointer to flow attributes
2103  * @param[out] error
2104  *   Pointer to error structure.
2105  *
2106  * @return
2107  *   0 on success, a negative errno value otherwise and rte_errno is set.
2108  */
2109 static int
2110 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2111                                  const struct rte_flow_action *action,
2112                                  uint64_t action_flags __rte_unused,
2113                                  const struct rte_flow_attr *attr,
2114                                  struct rte_flow_error *error)
2115 {
2116         const struct rte_flow_action_set_meta *conf;
2117         uint32_t nic_mask = UINT32_MAX;
2118         int reg;
2119
2120         if (!mlx5_flow_ext_mreg_supported(dev))
2121                 return rte_flow_error_set(error, ENOTSUP,
2122                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2123                                           "extended metadata register"
2124                                           " isn't supported");
2125         reg = flow_dv_get_metadata_reg(dev, attr, error);
2126         if (reg < 0)
2127                 return reg;
2128         if (reg != REG_A && reg != REG_B) {
2129                 struct mlx5_priv *priv = dev->data->dev_private;
2130
2131                 nic_mask = priv->sh->dv_meta_mask;
2132         }
2133         if (!(action->conf))
2134                 return rte_flow_error_set(error, EINVAL,
2135                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2136                                           "configuration cannot be null");
2137         conf = (const struct rte_flow_action_set_meta *)action->conf;
2138         if (!conf->mask)
2139                 return rte_flow_error_set(error, EINVAL,
2140                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2141                                           "zero mask doesn't have any effect");
2142         if (conf->mask & ~nic_mask)
2143                 return rte_flow_error_set(error, EINVAL,
2144                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2145                                           "meta data must be within reg C0");
2146         return 0;
2147 }
2148
2149 /**
2150  * Validate SET_TAG action.
2151  *
2152  * @param[in] dev
2153  *   Pointer to the rte_eth_dev structure.
2154  * @param[in] action
2155  *   Pointer to the action structure.
2156  * @param[in] action_flags
2157  *   Holds the actions detected until now.
2158  * @param[in] attr
2159  *   Pointer to flow attributes
2160  * @param[out] error
2161  *   Pointer to error structure.
2162  *
2163  * @return
2164  *   0 on success, a negative errno value otherwise and rte_errno is set.
2165  */
2166 static int
2167 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2168                                 const struct rte_flow_action *action,
2169                                 uint64_t action_flags,
2170                                 const struct rte_flow_attr *attr,
2171                                 struct rte_flow_error *error)
2172 {
2173         const struct rte_flow_action_set_tag *conf;
2174         const uint64_t terminal_action_flags =
2175                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2176                 MLX5_FLOW_ACTION_RSS;
2177         int ret;
2178
2179         if (!mlx5_flow_ext_mreg_supported(dev))
2180                 return rte_flow_error_set(error, ENOTSUP,
2181                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2182                                           "extensive metadata register"
2183                                           " isn't supported");
2184         if (!(action->conf))
2185                 return rte_flow_error_set(error, EINVAL,
2186                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2187                                           "configuration cannot be null");
2188         conf = (const struct rte_flow_action_set_tag *)action->conf;
2189         if (!conf->mask)
2190                 return rte_flow_error_set(error, EINVAL,
2191                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2192                                           "zero mask doesn't have any effect");
2193         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2194         if (ret < 0)
2195                 return ret;
2196         if (!attr->transfer && attr->ingress &&
2197             (action_flags & terminal_action_flags))
2198                 return rte_flow_error_set(error, EINVAL,
2199                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2200                                           "set_tag has no effect"
2201                                           " with terminal actions");
2202         return 0;
2203 }
2204
2205 /**
2206  * Validate count action.
2207  *
2208  * @param[in] dev
2209  *   Pointer to rte_eth_dev structure.
2210  * @param[out] error
2211  *   Pointer to error structure.
2212  *
2213  * @return
2214  *   0 on success, a negative errno value otherwise and rte_errno is set.
2215  */
2216 static int
2217 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2218                               struct rte_flow_error *error)
2219 {
2220         struct mlx5_priv *priv = dev->data->dev_private;
2221
2222         if (!priv->config.devx)
2223                 goto notsup_err;
2224 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2225         return 0;
2226 #endif
2227 notsup_err:
2228         return rte_flow_error_set
2229                       (error, ENOTSUP,
2230                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2231                        NULL,
2232                        "count action not supported");
2233 }
2234
2235 /**
2236  * Validate the L2 encap action.
2237  *
2238  * @param[in] dev
2239  *   Pointer to the rte_eth_dev structure.
2240  * @param[in] action_flags
2241  *   Holds the actions detected until now.
2242  * @param[in] action
2243  *   Pointer to the action structure.
2244  * @param[in] attr
2245  *   Pointer to flow attributes.
2246  * @param[out] error
2247  *   Pointer to error structure.
2248  *
2249  * @return
2250  *   0 on success, a negative errno value otherwise and rte_errno is set.
2251  */
2252 static int
2253 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2254                                  uint64_t action_flags,
2255                                  const struct rte_flow_action *action,
2256                                  const struct rte_flow_attr *attr,
2257                                  struct rte_flow_error *error)
2258 {
2259         const struct mlx5_priv *priv = dev->data->dev_private;
2260
2261         if (!(action->conf))
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "configuration cannot be null");
2265         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2266                 return rte_flow_error_set(error, EINVAL,
2267                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2268                                           "can only have a single encap action "
2269                                           "in a flow");
2270         if (!attr->transfer && priv->representor)
2271                 return rte_flow_error_set(error, ENOTSUP,
2272                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2273                                           "encap action for VF representor "
2274                                           "not supported on NIC table");
2275         return 0;
2276 }
2277
2278 /**
2279  * Validate a decap action.
2280  *
2281  * @param[in] dev
2282  *   Pointer to the rte_eth_dev structure.
2283  * @param[in] action_flags
2284  *   Holds the actions detected until now.
2285  * @param[in] attr
2286  *   Pointer to flow attributes
2287  * @param[out] error
2288  *   Pointer to error structure.
2289  *
2290  * @return
2291  *   0 on success, a negative errno value otherwise and rte_errno is set.
2292  */
2293 static int
2294 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2295                               uint64_t action_flags,
2296                               const struct rte_flow_attr *attr,
2297                               struct rte_flow_error *error)
2298 {
2299         const struct mlx5_priv *priv = dev->data->dev_private;
2300
2301         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2302                 return rte_flow_error_set(error, ENOTSUP,
2303                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2304                                           action_flags &
2305                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2306                                           "have a single decap action" : "decap "
2307                                           "after encap is not supported");
2308         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2311                                           "can't have decap action after"
2312                                           " modify action");
2313         if (attr->egress)
2314                 return rte_flow_error_set(error, ENOTSUP,
2315                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2316                                           NULL,
2317                                           "decap action not supported for "
2318                                           "egress");
2319         if (!attr->transfer && priv->representor)
2320                 return rte_flow_error_set(error, ENOTSUP,
2321                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2322                                           "decap action for VF representor "
2323                                           "not supported on NIC table");
2324         return 0;
2325 }
2326
2327 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2328
2329 /**
2330  * Validate the raw encap and decap actions.
2331  *
2332  * @param[in] dev
2333  *   Pointer to the rte_eth_dev structure.
2334  * @param[in] decap
2335  *   Pointer to the decap action.
2336  * @param[in] encap
2337  *   Pointer to the encap action.
2338  * @param[in] attr
2339  *   Pointer to flow attributes
2340  * @param[in/out] action_flags
2341  *   Holds the actions detected until now.
2342  * @param[out] actions_n
2343  *   pointer to the number of actions counter.
2344  * @param[out] error
2345  *   Pointer to error structure.
2346  *
2347  * @return
2348  *   0 on success, a negative errno value otherwise and rte_errno is set.
2349  */
2350 static int
2351 flow_dv_validate_action_raw_encap_decap
2352         (struct rte_eth_dev *dev,
2353          const struct rte_flow_action_raw_decap *decap,
2354          const struct rte_flow_action_raw_encap *encap,
2355          const struct rte_flow_attr *attr, uint64_t *action_flags,
2356          int *actions_n, struct rte_flow_error *error)
2357 {
2358         const struct mlx5_priv *priv = dev->data->dev_private;
2359         int ret;
2360
2361         if (encap && (!encap->size || !encap->data))
2362                 return rte_flow_error_set(error, EINVAL,
2363                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2364                                           "raw encap data cannot be empty");
2365         if (decap && encap) {
2366                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2367                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2368                         /* L3 encap. */
2369                         decap = NULL;
2370                 else if (encap->size <=
2371                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2372                            decap->size >
2373                            MLX5_ENCAPSULATION_DECISION_SIZE)
2374                         /* L3 decap. */
2375                         encap = NULL;
2376                 else if (encap->size >
2377                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2378                            decap->size >
2379                            MLX5_ENCAPSULATION_DECISION_SIZE)
2380                         /* 2 L2 actions: encap and decap. */
2381                         ;
2382                 else
2383                         return rte_flow_error_set(error,
2384                                 ENOTSUP,
2385                                 RTE_FLOW_ERROR_TYPE_ACTION,
2386                                 NULL, "unsupported too small "
2387                                 "raw decap and too small raw "
2388                                 "encap combination");
2389         }
2390         if (decap) {
2391                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2392                                                     error);
2393                 if (ret < 0)
2394                         return ret;
2395                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2396                 ++(*actions_n);
2397         }
2398         if (encap) {
2399                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2400                         return rte_flow_error_set(error, ENOTSUP,
2401                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2402                                                   NULL,
2403                                                   "small raw encap size");
2404                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2405                         return rte_flow_error_set(error, EINVAL,
2406                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2407                                                   NULL,
2408                                                   "more than one encap action");
2409                 if (!attr->transfer && priv->representor)
2410                         return rte_flow_error_set
2411                                         (error, ENOTSUP,
2412                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2413                                          "encap action for VF representor "
2414                                          "not supported on NIC table");
2415                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2416                 ++(*actions_n);
2417         }
2418         return 0;
2419 }
2420
2421 /**
2422  * Find existing encap/decap resource or create and register a new one.
2423  *
2424  * @param[in, out] dev
2425  *   Pointer to rte_eth_dev structure.
2426  * @param[in, out] resource
2427  *   Pointer to encap/decap resource.
2428  * @parm[in, out] dev_flow
2429  *   Pointer to the dev_flow.
2430  * @param[out] error
2431  *   pointer to error structure.
2432  *
2433  * @return
2434  *   0 on success otherwise -errno and errno is set.
2435  */
2436 static int
2437 flow_dv_encap_decap_resource_register
2438                         (struct rte_eth_dev *dev,
2439                          struct mlx5_flow_dv_encap_decap_resource *resource,
2440                          struct mlx5_flow *dev_flow,
2441                          struct rte_flow_error *error)
2442 {
2443         struct mlx5_priv *priv = dev->data->dev_private;
2444         struct mlx5_ibv_shared *sh = priv->sh;
2445         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2446         struct mlx5dv_dr_domain *domain;
2447
2448         resource->flags = dev_flow->dv.group ? 0 : 1;
2449         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2450                 domain = sh->fdb_domain;
2451         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2452                 domain = sh->rx_domain;
2453         else
2454                 domain = sh->tx_domain;
2455         /* Lookup a matching resource from cache. */
2456         LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2457                 if (resource->reformat_type == cache_resource->reformat_type &&
2458                     resource->ft_type == cache_resource->ft_type &&
2459                     resource->flags == cache_resource->flags &&
2460                     resource->size == cache_resource->size &&
2461                     !memcmp((const void *)resource->buf,
2462                             (const void *)cache_resource->buf,
2463                             resource->size)) {
2464                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2465                                 (void *)cache_resource,
2466                                 rte_atomic32_read(&cache_resource->refcnt));
2467                         rte_atomic32_inc(&cache_resource->refcnt);
2468                         dev_flow->handle->dvh.encap_decap = cache_resource;
2469                         return 0;
2470                 }
2471         }
2472         /* Register new encap/decap resource. */
2473         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2474         if (!cache_resource)
2475                 return rte_flow_error_set(error, ENOMEM,
2476                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2477                                           "cannot allocate resource memory");
2478         *cache_resource = *resource;
2479         cache_resource->verbs_action =
2480                 mlx5_glue->dv_create_flow_action_packet_reformat
2481                         (sh->ctx, cache_resource->reformat_type,
2482                          cache_resource->ft_type, domain, cache_resource->flags,
2483                          cache_resource->size,
2484                          (cache_resource->size ? cache_resource->buf : NULL));
2485         if (!cache_resource->verbs_action) {
2486                 rte_free(cache_resource);
2487                 return rte_flow_error_set(error, ENOMEM,
2488                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2489                                           NULL, "cannot create action");
2490         }
2491         rte_atomic32_init(&cache_resource->refcnt);
2492         rte_atomic32_inc(&cache_resource->refcnt);
2493         LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2494         dev_flow->handle->dvh.encap_decap = cache_resource;
2495         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2496                 (void *)cache_resource,
2497                 rte_atomic32_read(&cache_resource->refcnt));
2498         return 0;
2499 }
2500
2501 /**
2502  * Find existing table jump resource or create and register a new one.
2503  *
2504  * @param[in, out] dev
2505  *   Pointer to rte_eth_dev structure.
2506  * @param[in, out] tbl
2507  *   Pointer to flow table resource.
2508  * @parm[in, out] dev_flow
2509  *   Pointer to the dev_flow.
2510  * @param[out] error
2511  *   pointer to error structure.
2512  *
2513  * @return
2514  *   0 on success otherwise -errno and errno is set.
2515  */
2516 static int
2517 flow_dv_jump_tbl_resource_register
2518                         (struct rte_eth_dev *dev __rte_unused,
2519                          struct mlx5_flow_tbl_resource *tbl,
2520                          struct mlx5_flow *dev_flow,
2521                          struct rte_flow_error *error)
2522 {
2523         struct mlx5_flow_tbl_data_entry *tbl_data =
2524                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2525         int cnt;
2526
2527         MLX5_ASSERT(tbl);
2528         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2529         if (!cnt) {
2530                 tbl_data->jump.action =
2531                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2532                         (tbl->obj);
2533                 if (!tbl_data->jump.action)
2534                         return rte_flow_error_set(error, ENOMEM,
2535                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2536                                         NULL, "cannot create jump action");
2537                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2538                         (void *)&tbl_data->jump, cnt);
2539         } else {
2540                 MLX5_ASSERT(tbl_data->jump.action);
2541                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2542                         (void *)&tbl_data->jump, cnt);
2543         }
2544         rte_atomic32_inc(&tbl_data->jump.refcnt);
2545         dev_flow->handle->dvh.jump = &tbl_data->jump;
2546         return 0;
2547 }
2548
2549 /**
2550  * Find existing table port ID resource or create and register a new one.
2551  *
2552  * @param[in, out] dev
2553  *   Pointer to rte_eth_dev structure.
2554  * @param[in, out] resource
2555  *   Pointer to port ID action resource.
2556  * @parm[in, out] dev_flow
2557  *   Pointer to the dev_flow.
2558  * @param[out] error
2559  *   pointer to error structure.
2560  *
2561  * @return
2562  *   0 on success otherwise -errno and errno is set.
2563  */
2564 static int
2565 flow_dv_port_id_action_resource_register
2566                         (struct rte_eth_dev *dev,
2567                          struct mlx5_flow_dv_port_id_action_resource *resource,
2568                          struct mlx5_flow *dev_flow,
2569                          struct rte_flow_error *error)
2570 {
2571         struct mlx5_priv *priv = dev->data->dev_private;
2572         struct mlx5_ibv_shared *sh = priv->sh;
2573         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2574
2575         /* Lookup a matching resource from cache. */
2576         LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2577                 if (resource->port_id == cache_resource->port_id) {
2578                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2579                                 "refcnt %d++",
2580                                 (void *)cache_resource,
2581                                 rte_atomic32_read(&cache_resource->refcnt));
2582                         rte_atomic32_inc(&cache_resource->refcnt);
2583                         dev_flow->handle->dvh.port_id_action = cache_resource;
2584                         return 0;
2585                 }
2586         }
2587         /* Register new port id action resource. */
2588         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2589         if (!cache_resource)
2590                 return rte_flow_error_set(error, ENOMEM,
2591                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2592                                           "cannot allocate resource memory");
2593         *cache_resource = *resource;
2594         /*
2595          * Depending on rdma_core version the glue routine calls
2596          * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2597          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2598          */
2599         cache_resource->action =
2600                 mlx5_glue->dr_create_flow_action_dest_port
2601                         (priv->sh->fdb_domain, resource->port_id);
2602         if (!cache_resource->action) {
2603                 rte_free(cache_resource);
2604                 return rte_flow_error_set(error, ENOMEM,
2605                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2606                                           NULL, "cannot create action");
2607         }
2608         rte_atomic32_init(&cache_resource->refcnt);
2609         rte_atomic32_inc(&cache_resource->refcnt);
2610         LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2611         dev_flow->handle->dvh.port_id_action = cache_resource;
2612         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2613                 (void *)cache_resource,
2614                 rte_atomic32_read(&cache_resource->refcnt));
2615         return 0;
2616 }
2617
2618 /**
2619  * Find existing push vlan resource or create and register a new one.
2620  *
2621  * @param [in, out] dev
2622  *   Pointer to rte_eth_dev structure.
2623  * @param[in, out] resource
2624  *   Pointer to port ID action resource.
2625  * @parm[in, out] dev_flow
2626  *   Pointer to the dev_flow.
2627  * @param[out] error
2628  *   pointer to error structure.
2629  *
2630  * @return
2631  *   0 on success otherwise -errno and errno is set.
2632  */
2633 static int
2634 flow_dv_push_vlan_action_resource_register
2635                        (struct rte_eth_dev *dev,
2636                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2637                         struct mlx5_flow *dev_flow,
2638                         struct rte_flow_error *error)
2639 {
2640         struct mlx5_priv *priv = dev->data->dev_private;
2641         struct mlx5_ibv_shared *sh = priv->sh;
2642         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2643         struct mlx5dv_dr_domain *domain;
2644
2645         /* Lookup a matching resource from cache. */
2646         LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2647                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2648                     resource->ft_type == cache_resource->ft_type) {
2649                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2650                                 "refcnt %d++",
2651                                 (void *)cache_resource,
2652                                 rte_atomic32_read(&cache_resource->refcnt));
2653                         rte_atomic32_inc(&cache_resource->refcnt);
2654                         dev_flow->handle->dvh.push_vlan_res = cache_resource;
2655                         return 0;
2656                 }
2657         }
2658         /* Register new push_vlan action resource. */
2659         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2660         if (!cache_resource)
2661                 return rte_flow_error_set(error, ENOMEM,
2662                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2663                                           "cannot allocate resource memory");
2664         *cache_resource = *resource;
2665         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2666                 domain = sh->fdb_domain;
2667         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2668                 domain = sh->rx_domain;
2669         else
2670                 domain = sh->tx_domain;
2671         cache_resource->action =
2672                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2673                                                            resource->vlan_tag);
2674         if (!cache_resource->action) {
2675                 rte_free(cache_resource);
2676                 return rte_flow_error_set(error, ENOMEM,
2677                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2678                                           NULL, "cannot create action");
2679         }
2680         rte_atomic32_init(&cache_resource->refcnt);
2681         rte_atomic32_inc(&cache_resource->refcnt);
2682         LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2683         dev_flow->handle->dvh.push_vlan_res = cache_resource;
2684         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2685                 (void *)cache_resource,
2686                 rte_atomic32_read(&cache_resource->refcnt));
2687         return 0;
2688 }
2689 /**
2690  * Get the size of specific rte_flow_item_type
2691  *
2692  * @param[in] item_type
2693  *   Tested rte_flow_item_type.
2694  *
2695  * @return
2696  *   sizeof struct item_type, 0 if void or irrelevant.
2697  */
2698 static size_t
2699 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2700 {
2701         size_t retval;
2702
2703         switch (item_type) {
2704         case RTE_FLOW_ITEM_TYPE_ETH:
2705                 retval = sizeof(struct rte_flow_item_eth);
2706                 break;
2707         case RTE_FLOW_ITEM_TYPE_VLAN:
2708                 retval = sizeof(struct rte_flow_item_vlan);
2709                 break;
2710         case RTE_FLOW_ITEM_TYPE_IPV4:
2711                 retval = sizeof(struct rte_flow_item_ipv4);
2712                 break;
2713         case RTE_FLOW_ITEM_TYPE_IPV6:
2714                 retval = sizeof(struct rte_flow_item_ipv6);
2715                 break;
2716         case RTE_FLOW_ITEM_TYPE_UDP:
2717                 retval = sizeof(struct rte_flow_item_udp);
2718                 break;
2719         case RTE_FLOW_ITEM_TYPE_TCP:
2720                 retval = sizeof(struct rte_flow_item_tcp);
2721                 break;
2722         case RTE_FLOW_ITEM_TYPE_VXLAN:
2723                 retval = sizeof(struct rte_flow_item_vxlan);
2724                 break;
2725         case RTE_FLOW_ITEM_TYPE_GRE:
2726                 retval = sizeof(struct rte_flow_item_gre);
2727                 break;
2728         case RTE_FLOW_ITEM_TYPE_NVGRE:
2729                 retval = sizeof(struct rte_flow_item_nvgre);
2730                 break;
2731         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2732                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2733                 break;
2734         case RTE_FLOW_ITEM_TYPE_MPLS:
2735                 retval = sizeof(struct rte_flow_item_mpls);
2736                 break;
2737         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2738         default:
2739                 retval = 0;
2740                 break;
2741         }
2742         return retval;
2743 }
2744
2745 #define MLX5_ENCAP_IPV4_VERSION         0x40
2746 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2747 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2748 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2749 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2750 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2751 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2752
2753 /**
2754  * Convert the encap action data from list of rte_flow_item to raw buffer
2755  *
2756  * @param[in] items
2757  *   Pointer to rte_flow_item objects list.
2758  * @param[out] buf
2759  *   Pointer to the output buffer.
2760  * @param[out] size
2761  *   Pointer to the output buffer size.
2762  * @param[out] error
2763  *   Pointer to the error structure.
2764  *
2765  * @return
2766  *   0 on success, a negative errno value otherwise and rte_errno is set.
2767  */
2768 static int
2769 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2770                            size_t *size, struct rte_flow_error *error)
2771 {
2772         struct rte_ether_hdr *eth = NULL;
2773         struct rte_vlan_hdr *vlan = NULL;
2774         struct rte_ipv4_hdr *ipv4 = NULL;
2775         struct rte_ipv6_hdr *ipv6 = NULL;
2776         struct rte_udp_hdr *udp = NULL;
2777         struct rte_vxlan_hdr *vxlan = NULL;
2778         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2779         struct rte_gre_hdr *gre = NULL;
2780         size_t len;
2781         size_t temp_size = 0;
2782
2783         if (!items)
2784                 return rte_flow_error_set(error, EINVAL,
2785                                           RTE_FLOW_ERROR_TYPE_ACTION,
2786                                           NULL, "invalid empty data");
2787         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2788                 len = flow_dv_get_item_len(items->type);
2789                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2790                         return rte_flow_error_set(error, EINVAL,
2791                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2792                                                   (void *)items->type,
2793                                                   "items total size is too big"
2794                                                   " for encap action");
2795                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2796                 switch (items->type) {
2797                 case RTE_FLOW_ITEM_TYPE_ETH:
2798                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2799                         break;
2800                 case RTE_FLOW_ITEM_TYPE_VLAN:
2801                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2802                         if (!eth)
2803                                 return rte_flow_error_set(error, EINVAL,
2804                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2805                                                 (void *)items->type,
2806                                                 "eth header not found");
2807                         if (!eth->ether_type)
2808                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2809                         break;
2810                 case RTE_FLOW_ITEM_TYPE_IPV4:
2811                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2812                         if (!vlan && !eth)
2813                                 return rte_flow_error_set(error, EINVAL,
2814                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2815                                                 (void *)items->type,
2816                                                 "neither eth nor vlan"
2817                                                 " header found");
2818                         if (vlan && !vlan->eth_proto)
2819                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2820                         else if (eth && !eth->ether_type)
2821                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2822                         if (!ipv4->version_ihl)
2823                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2824                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2825                         if (!ipv4->time_to_live)
2826                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2827                         break;
2828                 case RTE_FLOW_ITEM_TYPE_IPV6:
2829                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2830                         if (!vlan && !eth)
2831                                 return rte_flow_error_set(error, EINVAL,
2832                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2833                                                 (void *)items->type,
2834                                                 "neither eth nor vlan"
2835                                                 " header found");
2836                         if (vlan && !vlan->eth_proto)
2837                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2838                         else if (eth && !eth->ether_type)
2839                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2840                         if (!ipv6->vtc_flow)
2841                                 ipv6->vtc_flow =
2842                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2843                         if (!ipv6->hop_limits)
2844                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2845                         break;
2846                 case RTE_FLOW_ITEM_TYPE_UDP:
2847                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2848                         if (!ipv4 && !ipv6)
2849                                 return rte_flow_error_set(error, EINVAL,
2850                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2851                                                 (void *)items->type,
2852                                                 "ip header not found");
2853                         if (ipv4 && !ipv4->next_proto_id)
2854                                 ipv4->next_proto_id = IPPROTO_UDP;
2855                         else if (ipv6 && !ipv6->proto)
2856                                 ipv6->proto = IPPROTO_UDP;
2857                         break;
2858                 case RTE_FLOW_ITEM_TYPE_VXLAN:
2859                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2860                         if (!udp)
2861                                 return rte_flow_error_set(error, EINVAL,
2862                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2863                                                 (void *)items->type,
2864                                                 "udp header not found");
2865                         if (!udp->dst_port)
2866                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2867                         if (!vxlan->vx_flags)
2868                                 vxlan->vx_flags =
2869                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2870                         break;
2871                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2872                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2873                         if (!udp)
2874                                 return rte_flow_error_set(error, EINVAL,
2875                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2876                                                 (void *)items->type,
2877                                                 "udp header not found");
2878                         if (!vxlan_gpe->proto)
2879                                 return rte_flow_error_set(error, EINVAL,
2880                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2881                                                 (void *)items->type,
2882                                                 "next protocol not found");
2883                         if (!udp->dst_port)
2884                                 udp->dst_port =
2885                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2886                         if (!vxlan_gpe->vx_flags)
2887                                 vxlan_gpe->vx_flags =
2888                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2889                         break;
2890                 case RTE_FLOW_ITEM_TYPE_GRE:
2891                 case RTE_FLOW_ITEM_TYPE_NVGRE:
2892                         gre = (struct rte_gre_hdr *)&buf[temp_size];
2893                         if (!gre->proto)
2894                                 return rte_flow_error_set(error, EINVAL,
2895                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2896                                                 (void *)items->type,
2897                                                 "next protocol not found");
2898                         if (!ipv4 && !ipv6)
2899                                 return rte_flow_error_set(error, EINVAL,
2900                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2901                                                 (void *)items->type,
2902                                                 "ip header not found");
2903                         if (ipv4 && !ipv4->next_proto_id)
2904                                 ipv4->next_proto_id = IPPROTO_GRE;
2905                         else if (ipv6 && !ipv6->proto)
2906                                 ipv6->proto = IPPROTO_GRE;
2907                         break;
2908                 case RTE_FLOW_ITEM_TYPE_VOID:
2909                         break;
2910                 default:
2911                         return rte_flow_error_set(error, EINVAL,
2912                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2913                                                   (void *)items->type,
2914                                                   "unsupported item type");
2915                         break;
2916                 }
2917                 temp_size += len;
2918         }
2919         *size = temp_size;
2920         return 0;
2921 }
2922
2923 static int
2924 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2925 {
2926         struct rte_ether_hdr *eth = NULL;
2927         struct rte_vlan_hdr *vlan = NULL;
2928         struct rte_ipv6_hdr *ipv6 = NULL;
2929         struct rte_udp_hdr *udp = NULL;
2930         char *next_hdr;
2931         uint16_t proto;
2932
2933         eth = (struct rte_ether_hdr *)data;
2934         next_hdr = (char *)(eth + 1);
2935         proto = RTE_BE16(eth->ether_type);
2936
2937         /* VLAN skipping */
2938         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2939                 vlan = (struct rte_vlan_hdr *)next_hdr;
2940                 proto = RTE_BE16(vlan->eth_proto);
2941                 next_hdr += sizeof(struct rte_vlan_hdr);
2942         }
2943
2944         /* HW calculates IPv4 csum. no need to proceed */
2945         if (proto == RTE_ETHER_TYPE_IPV4)
2946                 return 0;
2947
2948         /* non IPv4/IPv6 header. not supported */
2949         if (proto != RTE_ETHER_TYPE_IPV6) {
2950                 return rte_flow_error_set(error, ENOTSUP,
2951                                           RTE_FLOW_ERROR_TYPE_ACTION,
2952                                           NULL, "Cannot offload non IPv4/IPv6");
2953         }
2954
2955         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2956
2957         /* ignore non UDP */
2958         if (ipv6->proto != IPPROTO_UDP)
2959                 return 0;
2960
2961         udp = (struct rte_udp_hdr *)(ipv6 + 1);
2962         udp->dgram_cksum = 0;
2963
2964         return 0;
2965 }
2966
2967 /**
2968  * Convert L2 encap action to DV specification.
2969  *
2970  * @param[in] dev
2971  *   Pointer to rte_eth_dev structure.
2972  * @param[in] action
2973  *   Pointer to action structure.
2974  * @param[in, out] dev_flow
2975  *   Pointer to the mlx5_flow.
2976  * @param[in] transfer
2977  *   Mark if the flow is E-Switch flow.
2978  * @param[out] error
2979  *   Pointer to the error structure.
2980  *
2981  * @return
2982  *   0 on success, a negative errno value otherwise and rte_errno is set.
2983  */
2984 static int
2985 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2986                                const struct rte_flow_action *action,
2987                                struct mlx5_flow *dev_flow,
2988                                uint8_t transfer,
2989                                struct rte_flow_error *error)
2990 {
2991         const struct rte_flow_item *encap_data;
2992         const struct rte_flow_action_raw_encap *raw_encap_data;
2993         struct mlx5_flow_dv_encap_decap_resource res = {
2994                 .reformat_type =
2995                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2996                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2997                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2998         };
2999
3000         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3001                 raw_encap_data =
3002                         (const struct rte_flow_action_raw_encap *)action->conf;
3003                 res.size = raw_encap_data->size;
3004                 memcpy(res.buf, raw_encap_data->data, res.size);
3005         } else {
3006                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3007                         encap_data =
3008                                 ((const struct rte_flow_action_vxlan_encap *)
3009                                                 action->conf)->definition;
3010                 else
3011                         encap_data =
3012                                 ((const struct rte_flow_action_nvgre_encap *)
3013                                                 action->conf)->definition;
3014                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3015                                                &res.size, error))
3016                         return -rte_errno;
3017         }
3018         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3019                 return -rte_errno;
3020         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3021                 return rte_flow_error_set(error, EINVAL,
3022                                           RTE_FLOW_ERROR_TYPE_ACTION,
3023                                           NULL, "can't create L2 encap action");
3024         return 0;
3025 }
3026
3027 /**
3028  * Convert L2 decap action to DV specification.
3029  *
3030  * @param[in] dev
3031  *   Pointer to rte_eth_dev structure.
3032  * @param[in, out] dev_flow
3033  *   Pointer to the mlx5_flow.
3034  * @param[in] transfer
3035  *   Mark if the flow is E-Switch flow.
3036  * @param[out] error
3037  *   Pointer to the error structure.
3038  *
3039  * @return
3040  *   0 on success, a negative errno value otherwise and rte_errno is set.
3041  */
3042 static int
3043 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3044                                struct mlx5_flow *dev_flow,
3045                                uint8_t transfer,
3046                                struct rte_flow_error *error)
3047 {
3048         struct mlx5_flow_dv_encap_decap_resource res = {
3049                 .size = 0,
3050                 .reformat_type =
3051                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3052                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3053                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3054         };
3055
3056         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3057                 return rte_flow_error_set(error, EINVAL,
3058                                           RTE_FLOW_ERROR_TYPE_ACTION,
3059                                           NULL, "can't create L2 decap action");
3060         return 0;
3061 }
3062
3063 /**
3064  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3065  *
3066  * @param[in] dev
3067  *   Pointer to rte_eth_dev structure.
3068  * @param[in] action
3069  *   Pointer to action structure.
3070  * @param[in, out] dev_flow
3071  *   Pointer to the mlx5_flow.
3072  * @param[in] attr
3073  *   Pointer to the flow attributes.
3074  * @param[out] error
3075  *   Pointer to the error structure.
3076  *
3077  * @return
3078  *   0 on success, a negative errno value otherwise and rte_errno is set.
3079  */
3080 static int
3081 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3082                                 const struct rte_flow_action *action,
3083                                 struct mlx5_flow *dev_flow,
3084                                 const struct rte_flow_attr *attr,
3085                                 struct rte_flow_error *error)
3086 {
3087         const struct rte_flow_action_raw_encap *encap_data;
3088         struct mlx5_flow_dv_encap_decap_resource res;
3089
3090         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3091         res.size = encap_data->size;
3092         memcpy(res.buf, encap_data->data, res.size);
3093         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3094                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3095                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3096         if (attr->transfer)
3097                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3098         else
3099                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3100                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3101         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3102                 return rte_flow_error_set(error, EINVAL,
3103                                           RTE_FLOW_ERROR_TYPE_ACTION,
3104                                           NULL, "can't create encap action");
3105         return 0;
3106 }
3107
3108 /**
3109  * Create action push VLAN.
3110  *
3111  * @param[in] dev
3112  *   Pointer to rte_eth_dev structure.
3113  * @param[in] attr
3114  *   Pointer to the flow attributes.
3115  * @param[in] vlan
3116  *   Pointer to the vlan to push to the Ethernet header.
3117  * @param[in, out] dev_flow
3118  *   Pointer to the mlx5_flow.
3119  * @param[out] error
3120  *   Pointer to the error structure.
3121  *
3122  * @return
3123  *   0 on success, a negative errno value otherwise and rte_errno is set.
3124  */
3125 static int
3126 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3127                                 const struct rte_flow_attr *attr,
3128                                 const struct rte_vlan_hdr *vlan,
3129                                 struct mlx5_flow *dev_flow,
3130                                 struct rte_flow_error *error)
3131 {
3132         struct mlx5_flow_dv_push_vlan_action_resource res;
3133
3134         res.vlan_tag =
3135                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3136                                  vlan->vlan_tci);
3137         if (attr->transfer)
3138                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3139         else
3140                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3141                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3142         return flow_dv_push_vlan_action_resource_register
3143                                             (dev, &res, dev_flow, error);
3144 }
3145
3146 /**
3147  * Validate the modify-header actions.
3148  *
3149  * @param[in] action_flags
3150  *   Holds the actions detected until now.
3151  * @param[in] action
3152  *   Pointer to the modify action.
3153  * @param[out] error
3154  *   Pointer to error structure.
3155  *
3156  * @return
3157  *   0 on success, a negative errno value otherwise and rte_errno is set.
3158  */
3159 static int
3160 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3161                                    const struct rte_flow_action *action,
3162                                    struct rte_flow_error *error)
3163 {
3164         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3165                 return rte_flow_error_set(error, EINVAL,
3166                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3167                                           NULL, "action configuration not set");
3168         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3169                 return rte_flow_error_set(error, EINVAL,
3170                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3171                                           "can't have encap action before"
3172                                           " modify action");
3173         return 0;
3174 }
3175
3176 /**
3177  * Validate the modify-header MAC address actions.
3178  *
3179  * @param[in] action_flags
3180  *   Holds the actions detected until now.
3181  * @param[in] action
3182  *   Pointer to the modify action.
3183  * @param[in] item_flags
3184  *   Holds the items detected.
3185  * @param[out] error
3186  *   Pointer to error structure.
3187  *
3188  * @return
3189  *   0 on success, a negative errno value otherwise and rte_errno is set.
3190  */
3191 static int
3192 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3193                                    const struct rte_flow_action *action,
3194                                    const uint64_t item_flags,
3195                                    struct rte_flow_error *error)
3196 {
3197         int ret = 0;
3198
3199         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3200         if (!ret) {
3201                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3202                         return rte_flow_error_set(error, EINVAL,
3203                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3204                                                   NULL,
3205                                                   "no L2 item in pattern");
3206         }
3207         return ret;
3208 }
3209
3210 /**
3211  * Validate the modify-header IPv4 address actions.
3212  *
3213  * @param[in] action_flags
3214  *   Holds the actions detected until now.
3215  * @param[in] action
3216  *   Pointer to the modify action.
3217  * @param[in] item_flags
3218  *   Holds the items detected.
3219  * @param[out] error
3220  *   Pointer to error structure.
3221  *
3222  * @return
3223  *   0 on success, a negative errno value otherwise and rte_errno is set.
3224  */
3225 static int
3226 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3227                                     const struct rte_flow_action *action,
3228                                     const uint64_t item_flags,
3229                                     struct rte_flow_error *error)
3230 {
3231         int ret = 0;
3232         uint64_t layer;
3233
3234         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3235         if (!ret) {
3236                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3237                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3238                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3239                 if (!(item_flags & layer))
3240                         return rte_flow_error_set(error, EINVAL,
3241                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3242                                                   NULL,
3243                                                   "no ipv4 item in pattern");
3244         }
3245         return ret;
3246 }
3247
3248 /**
3249  * Validate the modify-header IPv6 address actions.
3250  *
3251  * @param[in] action_flags
3252  *   Holds the actions detected until now.
3253  * @param[in] action
3254  *   Pointer to the modify action.
3255  * @param[in] item_flags
3256  *   Holds the items detected.
3257  * @param[out] error
3258  *   Pointer to error structure.
3259  *
3260  * @return
3261  *   0 on success, a negative errno value otherwise and rte_errno is set.
3262  */
3263 static int
3264 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3265                                     const struct rte_flow_action *action,
3266                                     const uint64_t item_flags,
3267                                     struct rte_flow_error *error)
3268 {
3269         int ret = 0;
3270         uint64_t layer;
3271
3272         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3273         if (!ret) {
3274                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3275                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3276                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3277                 if (!(item_flags & layer))
3278                         return rte_flow_error_set(error, EINVAL,
3279                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3280                                                   NULL,
3281                                                   "no ipv6 item in pattern");
3282         }
3283         return ret;
3284 }
3285
3286 /**
3287  * Validate the modify-header TP actions.
3288  *
3289  * @param[in] action_flags
3290  *   Holds the actions detected until now.
3291  * @param[in] action
3292  *   Pointer to the modify action.
3293  * @param[in] item_flags
3294  *   Holds the items detected.
3295  * @param[out] error
3296  *   Pointer to error structure.
3297  *
3298  * @return
3299  *   0 on success, a negative errno value otherwise and rte_errno is set.
3300  */
3301 static int
3302 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3303                                   const struct rte_flow_action *action,
3304                                   const uint64_t item_flags,
3305                                   struct rte_flow_error *error)
3306 {
3307         int ret = 0;
3308         uint64_t layer;
3309
3310         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3311         if (!ret) {
3312                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3313                                  MLX5_FLOW_LAYER_INNER_L4 :
3314                                  MLX5_FLOW_LAYER_OUTER_L4;
3315                 if (!(item_flags & layer))
3316                         return rte_flow_error_set(error, EINVAL,
3317                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3318                                                   NULL, "no transport layer "
3319                                                   "in pattern");
3320         }
3321         return ret;
3322 }
3323
3324 /**
3325  * Validate the modify-header actions of increment/decrement
3326  * TCP Sequence-number.
3327  *
3328  * @param[in] action_flags
3329  *   Holds the actions detected until now.
3330  * @param[in] action
3331  *   Pointer to the modify action.
3332  * @param[in] item_flags
3333  *   Holds the items detected.
3334  * @param[out] error
3335  *   Pointer to error structure.
3336  *
3337  * @return
3338  *   0 on success, a negative errno value otherwise and rte_errno is set.
3339  */
3340 static int
3341 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3342                                        const struct rte_flow_action *action,
3343                                        const uint64_t item_flags,
3344                                        struct rte_flow_error *error)
3345 {
3346         int ret = 0;
3347         uint64_t layer;
3348
3349         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3350         if (!ret) {
3351                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3352                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3353                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3354                 if (!(item_flags & layer))
3355                         return rte_flow_error_set(error, EINVAL,
3356                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3357                                                   NULL, "no TCP item in"
3358                                                   " pattern");
3359                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3360                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3361                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3362                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3363                         return rte_flow_error_set(error, EINVAL,
3364                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3365                                                   NULL,
3366                                                   "cannot decrease and increase"
3367                                                   " TCP sequence number"
3368                                                   " at the same time");
3369         }
3370         return ret;
3371 }
3372
3373 /**
3374  * Validate the modify-header actions of increment/decrement
3375  * TCP Acknowledgment number.
3376  *
3377  * @param[in] action_flags
3378  *   Holds the actions detected until now.
3379  * @param[in] action
3380  *   Pointer to the modify action.
3381  * @param[in] item_flags
3382  *   Holds the items detected.
3383  * @param[out] error
3384  *   Pointer to error structure.
3385  *
3386  * @return
3387  *   0 on success, a negative errno value otherwise and rte_errno is set.
3388  */
3389 static int
3390 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3391                                        const struct rte_flow_action *action,
3392                                        const uint64_t item_flags,
3393                                        struct rte_flow_error *error)
3394 {
3395         int ret = 0;
3396         uint64_t layer;
3397
3398         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3399         if (!ret) {
3400                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3401                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3402                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3403                 if (!(item_flags & layer))
3404                         return rte_flow_error_set(error, EINVAL,
3405                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3406                                                   NULL, "no TCP item in"
3407                                                   " pattern");
3408                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3409                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3410                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3411                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3412                         return rte_flow_error_set(error, EINVAL,
3413                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3414                                                   NULL,
3415                                                   "cannot decrease and increase"
3416                                                   " TCP acknowledgment number"
3417                                                   " at the same time");
3418         }
3419         return ret;
3420 }
3421
3422 /**
3423  * Validate the modify-header TTL actions.
3424  *
3425  * @param[in] action_flags
3426  *   Holds the actions detected until now.
3427  * @param[in] action
3428  *   Pointer to the modify action.
3429  * @param[in] item_flags
3430  *   Holds the items detected.
3431  * @param[out] error
3432  *   Pointer to error structure.
3433  *
3434  * @return
3435  *   0 on success, a negative errno value otherwise and rte_errno is set.
3436  */
3437 static int
3438 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3439                                    const struct rte_flow_action *action,
3440                                    const uint64_t item_flags,
3441                                    struct rte_flow_error *error)
3442 {
3443         int ret = 0;
3444         uint64_t layer;
3445
3446         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3447         if (!ret) {
3448                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3449                                  MLX5_FLOW_LAYER_INNER_L3 :
3450                                  MLX5_FLOW_LAYER_OUTER_L3;
3451                 if (!(item_flags & layer))
3452                         return rte_flow_error_set(error, EINVAL,
3453                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3454                                                   NULL,
3455                                                   "no IP protocol in pattern");
3456         }
3457         return ret;
3458 }
3459
3460 /**
3461  * Validate jump action.
3462  *
3463  * @param[in] action
3464  *   Pointer to the jump action.
3465  * @param[in] action_flags
3466  *   Holds the actions detected until now.
3467  * @param[in] attributes
3468  *   Pointer to flow attributes
3469  * @param[in] external
3470  *   Action belongs to flow rule created by request external to PMD.
3471  * @param[out] error
3472  *   Pointer to error structure.
3473  *
3474  * @return
3475  *   0 on success, a negative errno value otherwise and rte_errno is set.
3476  */
3477 static int
3478 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3479                              uint64_t action_flags,
3480                              const struct rte_flow_attr *attributes,
3481                              bool external, struct rte_flow_error *error)
3482 {
3483         uint32_t target_group, table;
3484         int ret = 0;
3485
3486         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3487                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3488                 return rte_flow_error_set(error, EINVAL,
3489                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3490                                           "can't have 2 fate actions in"
3491                                           " same flow");
3492         if (action_flags & MLX5_FLOW_ACTION_METER)
3493                 return rte_flow_error_set(error, ENOTSUP,
3494                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3495                                           "jump with meter not support");
3496         if (!action->conf)
3497                 return rte_flow_error_set(error, EINVAL,
3498                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3499                                           NULL, "action configuration not set");
3500         target_group =
3501                 ((const struct rte_flow_action_jump *)action->conf)->group;
3502         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3503                                        true, &table, error);
3504         if (ret)
3505                 return ret;
3506         if (attributes->group == target_group)
3507                 return rte_flow_error_set(error, EINVAL,
3508                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3509                                           "target group must be other than"
3510                                           " the current flow group");
3511         return 0;
3512 }
3513
3514 /*
3515  * Validate the port_id action.
3516  *
3517  * @param[in] dev
3518  *   Pointer to rte_eth_dev structure.
3519  * @param[in] action_flags
3520  *   Bit-fields that holds the actions detected until now.
3521  * @param[in] action
3522  *   Port_id RTE action structure.
3523  * @param[in] attr
3524  *   Attributes of flow that includes this action.
3525  * @param[out] error
3526  *   Pointer to error structure.
3527  *
3528  * @return
3529  *   0 on success, a negative errno value otherwise and rte_errno is set.
3530  */
3531 static int
3532 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3533                                 uint64_t action_flags,
3534                                 const struct rte_flow_action *action,
3535                                 const struct rte_flow_attr *attr,
3536                                 struct rte_flow_error *error)
3537 {
3538         const struct rte_flow_action_port_id *port_id;
3539         struct mlx5_priv *act_priv;
3540         struct mlx5_priv *dev_priv;
3541         uint16_t port;
3542
3543         if (!attr->transfer)
3544                 return rte_flow_error_set(error, ENOTSUP,
3545                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3546                                           NULL,
3547                                           "port id action is valid in transfer"
3548                                           " mode only");
3549         if (!action || !action->conf)
3550                 return rte_flow_error_set(error, ENOTSUP,
3551                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3552                                           NULL,
3553                                           "port id action parameters must be"
3554                                           " specified");
3555         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3556                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3557                 return rte_flow_error_set(error, EINVAL,
3558                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3559                                           "can have only one fate actions in"
3560                                           " a flow");
3561         dev_priv = mlx5_dev_to_eswitch_info(dev);
3562         if (!dev_priv)
3563                 return rte_flow_error_set(error, rte_errno,
3564                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3565                                           NULL,
3566                                           "failed to obtain E-Switch info");
3567         port_id = action->conf;
3568         port = port_id->original ? dev->data->port_id : port_id->id;
3569         act_priv = mlx5_port_to_eswitch_info(port, false);
3570         if (!act_priv)
3571                 return rte_flow_error_set
3572                                 (error, rte_errno,
3573                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3574                                  "failed to obtain E-Switch port id for port");
3575         if (act_priv->domain_id != dev_priv->domain_id)
3576                 return rte_flow_error_set
3577                                 (error, EINVAL,
3578                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3579                                  "port does not belong to"
3580                                  " E-Switch being configured");
3581         return 0;
3582 }
3583
3584 /**
3585  * Get the maximum number of modify header actions.
3586  *
3587  * @param dev
3588  *   Pointer to rte_eth_dev structure.
3589  * @param flags
3590  *   Flags bits to check if root level.
3591  *
3592  * @return
3593  *   Max number of modify header actions device can support.
3594  */
3595 static unsigned int
3596 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3597 {
3598         /*
3599          * There's no way to directly query the max cap. Although it has to be
3600          * acquried by iterative trial, it is a safe assumption that more
3601          * actions are supported by FW if extensive metadata register is
3602          * supported. (Only in the root table)
3603          */
3604         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3605                 return MLX5_MAX_MODIFY_NUM;
3606         else
3607                 return mlx5_flow_ext_mreg_supported(dev) ?
3608                                         MLX5_ROOT_TBL_MODIFY_NUM :
3609                                         MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3610 }
3611
3612 /**
3613  * Validate the meter action.
3614  *
3615  * @param[in] dev
3616  *   Pointer to rte_eth_dev structure.
3617  * @param[in] action_flags
3618  *   Bit-fields that holds the actions detected until now.
3619  * @param[in] action
3620  *   Pointer to the meter action.
3621  * @param[in] attr
3622  *   Attributes of flow that includes this action.
3623  * @param[out] error
3624  *   Pointer to error structure.
3625  *
3626  * @return
3627  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3628  */
3629 static int
3630 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3631                                 uint64_t action_flags,
3632                                 const struct rte_flow_action *action,
3633                                 const struct rte_flow_attr *attr,
3634                                 struct rte_flow_error *error)
3635 {
3636         struct mlx5_priv *priv = dev->data->dev_private;
3637         const struct rte_flow_action_meter *am = action->conf;
3638         struct mlx5_flow_meter *fm;
3639
3640         if (!am)
3641                 return rte_flow_error_set(error, EINVAL,
3642                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3643                                           "meter action conf is NULL");
3644
3645         if (action_flags & MLX5_FLOW_ACTION_METER)
3646                 return rte_flow_error_set(error, ENOTSUP,
3647                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3648                                           "meter chaining not support");
3649         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3650                 return rte_flow_error_set(error, ENOTSUP,
3651                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3652                                           "meter with jump not support");
3653         if (!priv->mtr_en)
3654                 return rte_flow_error_set(error, ENOTSUP,
3655                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3656                                           NULL,
3657                                           "meter action not supported");
3658         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3659         if (!fm)
3660                 return rte_flow_error_set(error, EINVAL,
3661                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3662                                           "Meter not found");
3663         if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3664               (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3665               (!fm->attr.egress && !attr->egress && attr->ingress))))
3666                 return rte_flow_error_set(error, EINVAL,
3667                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3668                                           "Flow attributes are either invalid "
3669                                           "or have a conflict with current "
3670                                           "meter attributes");
3671         return 0;
3672 }
3673
3674 /**
3675  * Validate the modify-header IPv4 DSCP actions.
3676  *
3677  * @param[in] action_flags
3678  *   Holds the actions detected until now.
3679  * @param[in] action
3680  *   Pointer to the modify action.
3681  * @param[in] item_flags
3682  *   Holds the items detected.
3683  * @param[out] error
3684  *   Pointer to error structure.
3685  *
3686  * @return
3687  *   0 on success, a negative errno value otherwise and rte_errno is set.
3688  */
3689 static int
3690 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3691                                          const struct rte_flow_action *action,
3692                                          const uint64_t item_flags,
3693                                          struct rte_flow_error *error)
3694 {
3695         int ret = 0;
3696
3697         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3698         if (!ret) {
3699                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3700                         return rte_flow_error_set(error, EINVAL,
3701                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3702                                                   NULL,
3703                                                   "no ipv4 item in pattern");
3704         }
3705         return ret;
3706 }
3707
3708 /**
3709  * Validate the modify-header IPv6 DSCP actions.
3710  *
3711  * @param[in] action_flags
3712  *   Holds the actions detected until now.
3713  * @param[in] action
3714  *   Pointer to the modify action.
3715  * @param[in] item_flags
3716  *   Holds the items detected.
3717  * @param[out] error
3718  *   Pointer to error structure.
3719  *
3720  * @return
3721  *   0 on success, a negative errno value otherwise and rte_errno is set.
3722  */
3723 static int
3724 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3725                                          const struct rte_flow_action *action,
3726                                          const uint64_t item_flags,
3727                                          struct rte_flow_error *error)
3728 {
3729         int ret = 0;
3730
3731         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3732         if (!ret) {
3733                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3734                         return rte_flow_error_set(error, EINVAL,
3735                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3736                                                   NULL,
3737                                                   "no ipv6 item in pattern");
3738         }
3739         return ret;
3740 }
3741
3742 /**
3743  * Find existing modify-header resource or create and register a new one.
3744  *
3745  * @param dev[in, out]
3746  *   Pointer to rte_eth_dev structure.
3747  * @param[in, out] resource
3748  *   Pointer to modify-header resource.
3749  * @parm[in, out] dev_flow
3750  *   Pointer to the dev_flow.
3751  * @param[out] error
3752  *   pointer to error structure.
3753  *
3754  * @return
3755  *   0 on success otherwise -errno and errno is set.
3756  */
3757 static int
3758 flow_dv_modify_hdr_resource_register
3759                         (struct rte_eth_dev *dev,
3760                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3761                          struct mlx5_flow *dev_flow,
3762                          struct rte_flow_error *error)
3763 {
3764         struct mlx5_priv *priv = dev->data->dev_private;
3765         struct mlx5_ibv_shared *sh = priv->sh;
3766         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3767         struct mlx5dv_dr_domain *ns;
3768         uint32_t actions_len;
3769
3770         resource->flags = dev_flow->dv.group ? 0 :
3771                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3772         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3773                                     resource->flags))
3774                 return rte_flow_error_set(error, EOVERFLOW,
3775                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3776                                           "too many modify header items");
3777         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3778                 ns = sh->fdb_domain;
3779         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3780                 ns = sh->tx_domain;
3781         else
3782                 ns = sh->rx_domain;
3783         /* Lookup a matching resource from cache. */
3784         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3785         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3786                 if (resource->ft_type == cache_resource->ft_type &&
3787                     resource->actions_num == cache_resource->actions_num &&
3788                     resource->flags == cache_resource->flags &&
3789                     !memcmp((const void *)resource->actions,
3790                             (const void *)cache_resource->actions,
3791                             actions_len)) {
3792                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3793                                 (void *)cache_resource,
3794                                 rte_atomic32_read(&cache_resource->refcnt));
3795                         rte_atomic32_inc(&cache_resource->refcnt);
3796                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3797                         return 0;
3798                 }
3799         }
3800         /* Register new modify-header resource. */
3801         cache_resource = rte_calloc(__func__, 1,
3802                                     sizeof(*cache_resource) + actions_len, 0);
3803         if (!cache_resource)
3804                 return rte_flow_error_set(error, ENOMEM,
3805                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3806                                           "cannot allocate resource memory");
3807         *cache_resource = *resource;
3808         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3809         cache_resource->verbs_action =
3810                 mlx5_glue->dv_create_flow_action_modify_header
3811                                         (sh->ctx, cache_resource->ft_type, ns,
3812                                          cache_resource->flags, actions_len,
3813                                          (uint64_t *)cache_resource->actions);
3814         if (!cache_resource->verbs_action) {
3815                 rte_free(cache_resource);
3816                 return rte_flow_error_set(error, ENOMEM,
3817                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3818                                           NULL, "cannot create action");
3819         }
3820         rte_atomic32_init(&cache_resource->refcnt);
3821         rte_atomic32_inc(&cache_resource->refcnt);
3822         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3823         dev_flow->handle->dvh.modify_hdr = cache_resource;
3824         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3825                 (void *)cache_resource,
3826                 rte_atomic32_read(&cache_resource->refcnt));
3827         return 0;
3828 }
3829
3830 /**
3831  * Get or create a flow counter.
3832  *
3833  * @param[in] dev
3834  *   Pointer to the Ethernet device structure.
3835  * @param[in] shared
3836  *   Indicate if this counter is shared with other flows.
3837  * @param[in] id
3838  *   Counter identifier.
3839  *
3840  * @return
3841  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
3842  */
3843 static uint32_t
3844 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3845                                uint32_t id)
3846 {
3847         struct mlx5_priv *priv = dev->data->dev_private;
3848         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, 0, 0);
3849         struct mlx5_flow_counter_pool *pool;
3850         struct mlx5_flow_counter *cnt = NULL;
3851         struct mlx5_devx_obj *dcs = NULL;
3852         uint32_t offset;
3853
3854         if (!priv->config.devx) {
3855                 rte_errno = ENOTSUP;
3856                 return 0;
3857         }
3858         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3859         if (!dcs)
3860                 return 0;
3861         pool = flow_dv_find_pool_by_id(cont, true, dcs->id);
3862         if (!pool) {
3863                 cont = flow_dv_pool_create(dev, dcs, 0);
3864                 if (!cont) {
3865                         mlx5_devx_cmd_destroy(dcs);
3866                         rte_errno = ENOMEM;
3867                         return 0;
3868                 }
3869                 pool = TAILQ_FIRST(&cont->pool_list);
3870         }
3871         offset = dcs->id % MLX5_COUNTERS_PER_POOL;
3872         cnt = &pool->counters_raw[offset];
3873         struct mlx5_flow_counter tmpl = {
3874                 .shared = shared,
3875                 .ref_cnt = 1,
3876                 .id = id,
3877                 .dcs = dcs,
3878         };
3879         tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3880         if (!tmpl.action) {
3881                 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3882                 rte_errno = errno;
3883                 return 0;
3884         }
3885         *cnt = tmpl;
3886         return MLX5_MAKE_CNT_IDX(pool->index, offset);
3887 }
3888
3889 /**
3890  * Release a flow counter.
3891  *
3892  * @param[in] dev
3893  *   Pointer to the Ethernet device structure.
3894  * @param[in] counter
3895  *   Pointer to the counter handler.
3896  */
3897 static void
3898 flow_dv_counter_release_fallback(struct rte_eth_dev *dev __rte_unused,
3899                                  struct mlx5_flow_counter *counter)
3900 {
3901         if (!counter)
3902                 return;
3903         if (--counter->ref_cnt == 0) {
3904                 claim_zero(mlx5_glue->destroy_flow_action(counter->action));
3905                 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3906                 counter->action = NULL;
3907                 counter->dcs = NULL;
3908         }
3909 }
3910
3911 /**
3912  * Query a devx flow counter.
3913  *
3914  * @param[in] dev
3915  *   Pointer to the Ethernet device structure.
3916  * @param[in] cnt
3917  *   Pointer to the flow counter.
3918  * @param[out] pkts
3919  *   The statistics value of packets.
3920  * @param[out] bytes
3921  *   The statistics value of bytes.
3922  *
3923  * @return
3924  *   0 on success, otherwise a negative errno value and rte_errno is set.
3925  */
3926 static inline int
3927 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3928                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
3929                      uint64_t *bytes)
3930 {
3931         return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3932                                                 0, NULL, NULL, 0);
3933 }
3934
3935 /**
3936  * Get a pool by a counter.
3937  *
3938  * @param[in] cnt
3939  *   Pointer to the counter.
3940  *
3941  * @return
3942  *   The counter pool.
3943  */
3944 static struct mlx5_flow_counter_pool *
3945 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3946 {
3947         if (!cnt->batch) {
3948                 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3949                 return (struct mlx5_flow_counter_pool *)cnt - 1;
3950         }
3951         return cnt->pool;
3952 }
3953
3954 /**
3955  * Get DV flow counter by index.
3956  *
3957  * @param[in] dev
3958  *   Pointer to the Ethernet device structure.
3959  * @param[in] idx
3960  *   mlx5 flow counter index in the container.
3961  * @param[out] ppool
3962  *   mlx5 flow counter pool in the container,
3963  *
3964  * @return
3965  *   Pointer to the counter, NULL otherwise.
3966  */
3967 static struct mlx5_flow_counter *
3968 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
3969                            uint32_t idx,
3970                            struct mlx5_flow_counter_pool **ppool)
3971 {
3972         struct mlx5_priv *priv = dev->data->dev_private;
3973         struct mlx5_pools_container *cont;
3974         struct mlx5_flow_counter_pool *pool;
3975         uint32_t batch = 0;
3976
3977         idx--;
3978         if (idx >= MLX5_CNT_BATCH_OFFSET) {
3979                 idx -= MLX5_CNT_BATCH_OFFSET;
3980                 batch = 1;
3981         }
3982         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3983         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
3984         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
3985         MLX5_ASSERT(pool);
3986         if (ppool)
3987                 *ppool = pool;
3988         return &pool->counters_raw[idx % MLX5_COUNTERS_PER_POOL];
3989 }
3990
3991 /**
3992  * Get a pool by devx counter ID.
3993  *
3994  * @param[in] cont
3995  *   Pointer to the counter container.
3996  * @param[in] fallback
3997  *   Fallback mode.
3998  * @param[in] id
3999  *   The counter devx ID.
4000  *
4001  * @return
4002  *   The counter pool pointer if exists, NULL otherwise,
4003  */
4004 static struct mlx5_flow_counter_pool *
4005 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, bool fallback,
4006                         int id)
4007 {
4008         uint32_t i;
4009         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4010
4011         for (i = 0; i < n_valid; i++) {
4012                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4013                 int base = ((fallback ? pool->dcs_id : pool->min_dcs->id) /
4014                            MLX5_COUNTERS_PER_POOL) * MLX5_COUNTERS_PER_POOL;
4015
4016                 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL) {
4017                         /*
4018                          * Move the pool to the head, as counter allocate
4019                          * always gets the first pool in the container.
4020                          */
4021                         if (pool != TAILQ_FIRST(&cont->pool_list)) {
4022                                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4023                                 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4024                         }
4025                         return pool;
4026                 }
4027         }
4028         return NULL;
4029 }
4030
4031 /**
4032  * Allocate a new memory for the counter values wrapped by all the needed
4033  * management.
4034  *
4035  * @param[in] dev
4036  *   Pointer to the Ethernet device structure.
4037  * @param[in] raws_n
4038  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4039  *
4040  * @return
4041  *   The new memory management pointer on success, otherwise NULL and rte_errno
4042  *   is set.
4043  */
4044 static struct mlx5_counter_stats_mem_mng *
4045 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4046 {
4047         struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
4048                                         (dev->data->dev_private))->sh;
4049         struct mlx5_devx_mkey_attr mkey_attr;
4050         struct mlx5_counter_stats_mem_mng *mem_mng;
4051         volatile struct flow_counter_stats *raw_data;
4052         int size = (sizeof(struct flow_counter_stats) *
4053                         MLX5_COUNTERS_PER_POOL +
4054                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4055                         sizeof(struct mlx5_counter_stats_mem_mng);
4056         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4057         int i;
4058
4059         if (!mem) {
4060                 rte_errno = ENOMEM;
4061                 return NULL;
4062         }
4063         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4064         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4065         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4066                                                  IBV_ACCESS_LOCAL_WRITE);
4067         if (!mem_mng->umem) {
4068                 rte_errno = errno;
4069                 rte_free(mem);
4070                 return NULL;
4071         }
4072         mkey_attr.addr = (uintptr_t)mem;
4073         mkey_attr.size = size;
4074         mkey_attr.umem_id = mem_mng->umem->umem_id;
4075         mkey_attr.pd = sh->pdn;
4076         mkey_attr.log_entity_size = 0;
4077         mkey_attr.pg_access = 0;
4078         mkey_attr.klm_array = NULL;
4079         mkey_attr.klm_num = 0;
4080         mkey_attr.relaxed_ordering = 1;
4081         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4082         if (!mem_mng->dm) {
4083                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4084                 rte_errno = errno;
4085                 rte_free(mem);
4086                 return NULL;
4087         }
4088         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4089         raw_data = (volatile struct flow_counter_stats *)mem;
4090         for (i = 0; i < raws_n; ++i) {
4091                 mem_mng->raws[i].mem_mng = mem_mng;
4092                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4093         }
4094         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4095         return mem_mng;
4096 }
4097
4098 /**
4099  * Resize a counter container.
4100  *
4101  * @param[in] dev
4102  *   Pointer to the Ethernet device structure.
4103  * @param[in] batch
4104  *   Whether the pool is for counter that was allocated by batch command.
4105  *
4106  * @return
4107  *   The new container pointer on success, otherwise NULL and rte_errno is set.
4108  */
4109 static struct mlx5_pools_container *
4110 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
4111 {
4112         struct mlx5_priv *priv = dev->data->dev_private;
4113         struct mlx5_pools_container *cont =
4114                         MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4115         struct mlx5_pools_container *new_cont =
4116                         MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
4117         struct mlx5_counter_stats_mem_mng *mem_mng;
4118         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4119         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4120         int i;
4121
4122         if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
4123                 /* The last resize still hasn't detected by the host thread. */
4124                 rte_errno = EAGAIN;
4125                 return NULL;
4126         }
4127         new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
4128         if (!new_cont->pools) {
4129                 rte_errno = ENOMEM;
4130                 return NULL;
4131         }
4132         if (cont->n)
4133                 memcpy(new_cont->pools, cont->pools, cont->n *
4134                        sizeof(struct mlx5_flow_counter_pool *));
4135         mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4136                 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4137         if (!mem_mng) {
4138                 rte_free(new_cont->pools);
4139                 return NULL;
4140         }
4141         for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4142                 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4143                                  mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
4144                                  i, next);
4145         new_cont->n = resize;
4146         rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
4147         TAILQ_INIT(&new_cont->pool_list);
4148         TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
4149         new_cont->init_mem_mng = mem_mng;
4150         rte_cio_wmb();
4151          /* Flip the master container. */
4152         priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
4153         return new_cont;
4154 }
4155
4156 /**
4157  * Query a devx flow counter.
4158  *
4159  * @param[in] dev
4160  *   Pointer to the Ethernet device structure.
4161  * @param[in] cnt
4162  *   Pointer to the flow counter.
4163  * @param[out] pkts
4164  *   The statistics value of packets.
4165  * @param[out] bytes
4166  *   The statistics value of bytes.
4167  *
4168  * @return
4169  *   0 on success, otherwise a negative errno value and rte_errno is set.
4170  */
4171 static inline int
4172 _flow_dv_query_count(struct rte_eth_dev *dev,
4173                      struct mlx5_flow_counter *cnt, uint64_t *pkts,
4174                      uint64_t *bytes)
4175 {
4176         struct mlx5_priv *priv = dev->data->dev_private;
4177         struct mlx5_flow_counter_pool *pool =
4178                         flow_dv_counter_pool_get(cnt);
4179         int offset = cnt - &pool->counters_raw[0];
4180
4181         if (priv->counter_fallback)
4182                 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
4183
4184         rte_spinlock_lock(&pool->sl);
4185         /*
4186          * The single counters allocation may allocate smaller ID than the
4187          * current allocated in parallel to the host reading.
4188          * In this case the new counter values must be reported as 0.
4189          */
4190         if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
4191                 *pkts = 0;
4192                 *bytes = 0;
4193         } else {
4194                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4195                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4196         }
4197         rte_spinlock_unlock(&pool->sl);
4198         return 0;
4199 }
4200
4201 /**
4202  * Create and initialize a new counter pool.
4203  *
4204  * @param[in] dev
4205  *   Pointer to the Ethernet device structure.
4206  * @param[out] dcs
4207  *   The devX counter handle.
4208  * @param[in] batch
4209  *   Whether the pool is for counter that was allocated by batch command.
4210  * @param[in/out] cont_cur
4211  *   Pointer to the container pointer, it will be update in pool resize.
4212  *
4213  * @return
4214  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4215  */
4216 static struct mlx5_pools_container *
4217 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4218                     uint32_t batch)
4219 {
4220         struct mlx5_priv *priv = dev->data->dev_private;
4221         struct mlx5_flow_counter_pool *pool;
4222         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4223                                                                0);
4224         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4225         uint32_t size;
4226
4227         if (cont->n == n_valid) {
4228                 cont = flow_dv_container_resize(dev, batch);
4229                 if (!cont)
4230                         return NULL;
4231         }
4232         size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4233                         sizeof(struct mlx5_flow_counter);
4234         pool = rte_calloc(__func__, 1, size, 0);
4235         if (!pool) {
4236                 rte_errno = ENOMEM;
4237                 return NULL;
4238         }
4239         if (priv->counter_fallback)
4240                 pool->dcs_id = dcs->id;
4241         else
4242                 pool->min_dcs = dcs;
4243         pool->raw = cont->init_mem_mng->raws + n_valid %
4244                                                      MLX5_CNT_CONTAINER_RESIZE;
4245         pool->raw_hw = NULL;
4246         rte_spinlock_init(&pool->sl);
4247         /*
4248          * The generation of the new allocated counters in this pool is 0, 2 in
4249          * the pool generation makes all the counters valid for allocation.
4250          * The start and end query generation protect the counters be released
4251          * between the query and update gap period will not be reallocated
4252          * without the last query finished and stats updated to the memory.
4253          */
4254         rte_atomic64_set(&pool->start_query_gen, 0x2);
4255         rte_atomic64_set(&pool->end_query_gen, 0x2);
4256         TAILQ_INIT(&pool->counters);
4257         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4258         pool->index = n_valid;
4259         cont->pools[n_valid] = pool;
4260         /* Pool initialization must be updated before host thread access. */
4261         rte_cio_wmb();
4262         rte_atomic16_add(&cont->n_valid, 1);
4263         return cont;
4264 }
4265
4266 /**
4267  * Prepare a new counter and/or a new counter pool.
4268  *
4269  * @param[in] dev
4270  *   Pointer to the Ethernet device structure.
4271  * @param[out] cnt_free
4272  *   Where to put the pointer of a new counter.
4273  * @param[in] batch
4274  *   Whether the pool is for counter that was allocated by batch command.
4275  *
4276  * @return
4277  *   The counter container pointer and @p cnt_free is set on success,
4278  *   NULL otherwise and rte_errno is set.
4279  */
4280 static struct mlx5_pools_container *
4281 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4282                              struct mlx5_flow_counter **cnt_free,
4283                              uint32_t batch)
4284 {
4285         struct mlx5_priv *priv = dev->data->dev_private;
4286         struct mlx5_pools_container *cont;
4287         struct mlx5_flow_counter_pool *pool;
4288         struct mlx5_devx_obj *dcs = NULL;
4289         struct mlx5_flow_counter *cnt;
4290         uint32_t i;
4291
4292         cont = MLX5_CNT_CONTAINER(priv->sh, batch, 0);
4293         if (!batch) {
4294                 /* bulk_bitmap must be 0 for single counter allocation. */
4295                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4296                 if (!dcs)
4297                         return NULL;
4298                 pool = flow_dv_find_pool_by_id(cont, false, dcs->id);
4299                 if (!pool) {
4300                         cont = flow_dv_pool_create(dev, dcs, batch);
4301                         if (!cont) {
4302                                 mlx5_devx_cmd_destroy(dcs);
4303                                 return NULL;
4304                         }
4305                         pool = TAILQ_FIRST(&cont->pool_list);
4306                 } else if (dcs->id < pool->min_dcs->id) {
4307                         rte_atomic64_set(&pool->a64_dcs,
4308                                          (int64_t)(uintptr_t)dcs);
4309                 }
4310                 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4311                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4312                 cnt->dcs = dcs;
4313                 *cnt_free = cnt;
4314                 return cont;
4315         }
4316         /* bulk_bitmap is in 128 counters units. */
4317         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4318                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4319         if (!dcs) {
4320                 rte_errno = ENODATA;
4321                 return NULL;
4322         }
4323         cont = flow_dv_pool_create(dev, dcs, batch);
4324         if (!cont) {
4325                 mlx5_devx_cmd_destroy(dcs);
4326                 return NULL;
4327         }
4328         pool = TAILQ_FIRST(&cont->pool_list);
4329         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4330                 cnt = &pool->counters_raw[i];
4331                 cnt->pool = pool;
4332                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4333         }
4334         *cnt_free = &pool->counters_raw[0];
4335         return cont;
4336 }
4337
4338 /**
4339  * Search for existed shared counter.
4340  *
4341  * @param[in] cont
4342  *   Pointer to the relevant counter pool container.
4343  * @param[in] id
4344  *   The shared counter ID to search.
4345  * @param[out] ppool
4346  *   mlx5 flow counter pool in the container,
4347  *
4348  * @return
4349  *   NULL if not existed, otherwise pointer to the shared counter.
4350  */
4351 static struct mlx5_flow_counter *
4352 flow_dv_counter_shared_search(struct mlx5_pools_container *cont, uint32_t id,
4353                               struct mlx5_flow_counter_pool **ppool)
4354 {
4355         static struct mlx5_flow_counter *cnt;
4356         struct mlx5_flow_counter_pool *pool;
4357         uint32_t i;
4358         uint32_t n_valid = rte_atomic16_read(&cont->n_valid);
4359
4360         for (i = 0; i < n_valid; i++) {
4361                 pool = cont->pools[i];
4362                 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4363                         cnt = &pool->counters_raw[i];
4364                         if (cnt->ref_cnt && cnt->shared && cnt->id == id) {
4365                                 if (ppool)
4366                                         *ppool = pool;
4367                                 return cnt;
4368                         }
4369                 }
4370         }
4371         return NULL;
4372 }
4373
4374 /**
4375  * Allocate a flow counter.
4376  *
4377  * @param[in] dev
4378  *   Pointer to the Ethernet device structure.
4379  * @param[in] shared
4380  *   Indicate if this counter is shared with other flows.
4381  * @param[in] id
4382  *   Counter identifier.
4383  * @param[in] group
4384  *   Counter flow group.
4385  *
4386  * @return
4387  *   pointer to flow counter on success, NULL otherwise and rte_errno is set.
4388  */
4389 static struct mlx5_flow_counter *
4390 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4391                       uint16_t group)
4392 {
4393         struct mlx5_priv *priv = dev->data->dev_private;
4394         struct mlx5_flow_counter_pool *pool = NULL;
4395         struct mlx5_flow_counter *cnt_free = NULL;
4396         /*
4397          * Currently group 0 flow counter cannot be assigned to a flow if it is
4398          * not the first one in the batch counter allocation, so it is better
4399          * to allocate counters one by one for these flows in a separate
4400          * container.
4401          * A counter can be shared between different groups so need to take
4402          * shared counters from the single container.
4403          */
4404         uint32_t batch = (group && !shared) ? 1 : 0;
4405         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4406                                                                0);
4407         uint32_t cnt_idx;
4408
4409         if (!priv->config.devx) {
4410                 rte_errno = ENOTSUP;
4411                 return NULL;
4412         }
4413         if (shared) {
4414                 cnt_free = flow_dv_counter_shared_search(cont, id, &pool);
4415                 if (cnt_free) {
4416                         if (cnt_free->ref_cnt + 1 == 0) {
4417                                 rte_errno = E2BIG;
4418                                 return NULL;
4419                         }
4420                         cnt_free->ref_cnt++;
4421                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4422                                   (cnt_free - pool->counters_raw) + 1;
4423                         return (struct mlx5_flow_counter *)(uintptr_t)cnt_idx;
4424                 }
4425         }
4426         if (priv->counter_fallback)
4427                 return (struct mlx5_flow_counter *)(uintptr_t)
4428                        flow_dv_counter_alloc_fallback(dev, shared, id);
4429         /* Pools which has a free counters are in the start. */
4430         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4431                 /*
4432                  * The free counter reset values must be updated between the
4433                  * counter release to the counter allocation, so, at least one
4434                  * query must be done in this time. ensure it by saving the
4435                  * query generation in the release time.
4436                  * The free list is sorted according to the generation - so if
4437                  * the first one is not updated, all the others are not
4438                  * updated too.
4439                  */
4440                 cnt_free = TAILQ_FIRST(&pool->counters);
4441                 if (cnt_free && cnt_free->query_gen <
4442                     rte_atomic64_read(&pool->end_query_gen))
4443                         break;
4444                 cnt_free = NULL;
4445         }
4446         if (!cnt_free) {
4447                 cont = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4448                 if (!cont)
4449                         return NULL;
4450                 pool = TAILQ_FIRST(&cont->pool_list);
4451         }
4452         cnt_free->batch = batch;
4453         /* Create a DV counter action only in the first time usage. */
4454         if (!cnt_free->action) {
4455                 uint16_t offset;
4456                 struct mlx5_devx_obj *dcs;
4457
4458                 if (batch) {
4459                         offset = cnt_free - &pool->counters_raw[0];
4460                         dcs = pool->min_dcs;
4461                 } else {
4462                         offset = 0;
4463                         dcs = cnt_free->dcs;
4464                 }
4465                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4466                                         (dcs->obj, offset);
4467                 if (!cnt_free->action) {
4468                         rte_errno = errno;
4469                         return NULL;
4470                 }
4471         }
4472         /* Update the counter reset values. */
4473         if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4474                                  &cnt_free->bytes))
4475                 return NULL;
4476         cnt_free->shared = shared;
4477         cnt_free->ref_cnt = 1;
4478         cnt_free->id = id;
4479         if (!priv->sh->cmng.query_thread_on)
4480                 /* Start the asynchronous batch query by the host thread. */
4481                 mlx5_set_query_alarm(priv->sh);
4482         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4483         if (TAILQ_EMPTY(&pool->counters)) {
4484                 /* Move the pool to the end of the container pool list. */
4485                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4486                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4487         }
4488         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4489                                     (cnt_free - pool->counters_raw));
4490         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4491         return (struct mlx5_flow_counter *)(uintptr_t)cnt_idx;
4492 }
4493
4494 /**
4495  * Release a flow counter.
4496  *
4497  * @param[in] dev
4498  *   Pointer to the Ethernet device structure.
4499  * @param[in] counter
4500  *   Pointer to the counter handler.
4501  */
4502 static void
4503 flow_dv_counter_release(struct rte_eth_dev *dev,
4504                         struct mlx5_flow_counter *counter)
4505 {
4506         struct mlx5_priv *priv = dev->data->dev_private;
4507         struct mlx5_flow_counter_pool *pool;
4508         struct mlx5_flow_counter *cnt;
4509
4510         if (!counter)
4511                 return;
4512         cnt = flow_dv_counter_get_by_idx(dev, (uintptr_t)counter, &pool);
4513         if (priv->counter_fallback) {
4514                 flow_dv_counter_release_fallback(dev, cnt);
4515                 return;
4516         }
4517         if (--cnt->ref_cnt == 0) {
4518                 /* Put the counter in the end - the last updated one. */
4519                 TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4520                 /*
4521                  * Counters released between query trigger and handler need
4522                  * to wait the next round of query. Since the packets arrive
4523                  * in the gap period will not be taken into account to the
4524                  * old counter.
4525                  */
4526                 cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4527         }
4528 }
4529
4530 /**
4531  * Verify the @p attributes will be correctly understood by the NIC and store
4532  * them in the @p flow if everything is correct.
4533  *
4534  * @param[in] dev
4535  *   Pointer to dev struct.
4536  * @param[in] attributes
4537  *   Pointer to flow attributes
4538  * @param[in] external
4539  *   This flow rule is created by request external to PMD.
4540  * @param[out] error
4541  *   Pointer to error structure.
4542  *
4543  * @return
4544  *   0 on success, a negative errno value otherwise and rte_errno is set.
4545  */
4546 static int
4547 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4548                             const struct rte_flow_attr *attributes,
4549                             bool external __rte_unused,
4550                             struct rte_flow_error *error)
4551 {
4552         struct mlx5_priv *priv = dev->data->dev_private;
4553         uint32_t priority_max = priv->config.flow_prio - 1;
4554
4555 #ifndef HAVE_MLX5DV_DR
4556         if (attributes->group)
4557                 return rte_flow_error_set(error, ENOTSUP,
4558                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4559                                           NULL,
4560                                           "groups are not supported");
4561 #else
4562         uint32_t table;
4563         int ret;
4564
4565         ret = mlx5_flow_group_to_table(attributes, external,
4566                                        attributes->group, !!priv->fdb_def_rule,
4567                                        &table, error);
4568         if (ret)
4569                 return ret;
4570 #endif
4571         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4572             attributes->priority >= priority_max)
4573                 return rte_flow_error_set(error, ENOTSUP,
4574                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4575                                           NULL,
4576                                           "priority out of range");
4577         if (attributes->transfer) {
4578                 if (!priv->config.dv_esw_en)
4579                         return rte_flow_error_set
4580                                 (error, ENOTSUP,
4581                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4582                                  "E-Switch dr is not supported");
4583                 if (!(priv->representor || priv->master))
4584                         return rte_flow_error_set
4585                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4586                                  NULL, "E-Switch configuration can only be"
4587                                  " done by a master or a representor device");
4588                 if (attributes->egress)
4589                         return rte_flow_error_set
4590                                 (error, ENOTSUP,
4591                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4592                                  "egress is not supported");
4593         }
4594         if (!(attributes->egress ^ attributes->ingress))
4595                 return rte_flow_error_set(error, ENOTSUP,
4596                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4597                                           "must specify exactly one of "
4598                                           "ingress or egress");
4599         return 0;
4600 }
4601
4602 /**
4603  * Internal validation function. For validating both actions and items.
4604  *
4605  * @param[in] dev
4606  *   Pointer to the rte_eth_dev structure.
4607  * @param[in] attr
4608  *   Pointer to the flow attributes.
4609  * @param[in] items
4610  *   Pointer to the list of items.
4611  * @param[in] actions
4612  *   Pointer to the list of actions.
4613  * @param[in] external
4614  *   This flow rule is created by request external to PMD.
4615  * @param[out] error
4616  *   Pointer to the error structure.
4617  *
4618  * @return
4619  *   0 on success, a negative errno value otherwise and rte_errno is set.
4620  */
4621 static int
4622 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4623                  const struct rte_flow_item items[],
4624                  const struct rte_flow_action actions[],
4625                  bool external, struct rte_flow_error *error)
4626 {
4627         int ret;
4628         uint64_t action_flags = 0;
4629         uint64_t item_flags = 0;
4630         uint64_t last_item = 0;
4631         uint8_t next_protocol = 0xff;
4632         uint16_t ether_type = 0;
4633         int actions_n = 0;
4634         uint8_t item_ipv6_proto = 0;
4635         const struct rte_flow_item *gre_item = NULL;
4636         const struct rte_flow_action_raw_decap *decap;
4637         const struct rte_flow_action_raw_encap *encap;
4638         const struct rte_flow_action_rss *rss;
4639         const struct rte_flow_item_tcp nic_tcp_mask = {
4640                 .hdr = {
4641                         .tcp_flags = 0xFF,
4642                         .src_port = RTE_BE16(UINT16_MAX),
4643                         .dst_port = RTE_BE16(UINT16_MAX),
4644                 }
4645         };
4646         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4647                 .hdr = {
4648                         .src_addr = RTE_BE32(0xffffffff),
4649                         .dst_addr = RTE_BE32(0xffffffff),
4650                         .type_of_service = 0xff,
4651                         .next_proto_id = 0xff,
4652                         .time_to_live = 0xff,
4653                 },
4654         };
4655         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4656                 .hdr = {
4657                         .src_addr =
4658                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4659                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4660                         .dst_addr =
4661                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4662                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4663                         .vtc_flow = RTE_BE32(0xffffffff),
4664                         .proto = 0xff,
4665                         .hop_limits = 0xff,
4666                 },
4667         };
4668         struct mlx5_priv *priv = dev->data->dev_private;
4669         struct mlx5_dev_config *dev_conf = &priv->config;
4670         uint16_t queue_index = 0xFFFF;
4671
4672         if (items == NULL)
4673                 return -1;
4674         ret = flow_dv_validate_attributes(dev, attr, external, error);
4675         if (ret < 0)
4676                 return ret;
4677         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4678                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4679                 int type = items->type;
4680
4681                 switch (type) {
4682                 case RTE_FLOW_ITEM_TYPE_VOID:
4683                         break;
4684                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4685                         ret = flow_dv_validate_item_port_id
4686                                         (dev, items, attr, item_flags, error);
4687                         if (ret < 0)
4688                                 return ret;
4689                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4690                         break;
4691                 case RTE_FLOW_ITEM_TYPE_ETH:
4692                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4693                                                           error);
4694                         if (ret < 0)
4695                                 return ret;
4696                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4697                                              MLX5_FLOW_LAYER_OUTER_L2;
4698                         if (items->mask != NULL && items->spec != NULL) {
4699                                 ether_type =
4700                                         ((const struct rte_flow_item_eth *)
4701                                          items->spec)->type;
4702                                 ether_type &=
4703                                         ((const struct rte_flow_item_eth *)
4704                                          items->mask)->type;
4705                                 ether_type = rte_be_to_cpu_16(ether_type);
4706                         } else {
4707                                 ether_type = 0;
4708                         }
4709                         break;
4710                 case RTE_FLOW_ITEM_TYPE_VLAN:
4711                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
4712                                                            dev, error);
4713                         if (ret < 0)
4714                                 return ret;
4715                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4716                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4717                         if (items->mask != NULL && items->spec != NULL) {
4718                                 ether_type =
4719                                         ((const struct rte_flow_item_vlan *)
4720                                          items->spec)->inner_type;
4721                                 ether_type &=
4722                                         ((const struct rte_flow_item_vlan *)
4723                                          items->mask)->inner_type;
4724                                 ether_type = rte_be_to_cpu_16(ether_type);
4725                         } else {
4726                                 ether_type = 0;
4727                         }
4728                         break;
4729                 case RTE_FLOW_ITEM_TYPE_IPV4:
4730                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4731                                                   &item_flags, &tunnel);
4732                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4733                                                            last_item,
4734                                                            ether_type,
4735                                                            &nic_ipv4_mask,
4736                                                            error);
4737                         if (ret < 0)
4738                                 return ret;
4739                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4740                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4741                         if (items->mask != NULL &&
4742                             ((const struct rte_flow_item_ipv4 *)
4743                              items->mask)->hdr.next_proto_id) {
4744                                 next_protocol =
4745                                         ((const struct rte_flow_item_ipv4 *)
4746                                          (items->spec))->hdr.next_proto_id;
4747                                 next_protocol &=
4748                                         ((const struct rte_flow_item_ipv4 *)
4749                                          (items->mask))->hdr.next_proto_id;
4750                         } else {
4751                                 /* Reset for inner layer. */
4752                                 next_protocol = 0xff;
4753                         }
4754                         break;
4755                 case RTE_FLOW_ITEM_TYPE_IPV6:
4756                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4757                                                   &item_flags, &tunnel);
4758                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4759                                                            last_item,
4760                                                            ether_type,
4761                                                            &nic_ipv6_mask,
4762                                                            error);
4763                         if (ret < 0)
4764                                 return ret;
4765                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4766                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4767                         if (items->mask != NULL &&
4768                             ((const struct rte_flow_item_ipv6 *)
4769                              items->mask)->hdr.proto) {
4770                                 item_ipv6_proto =
4771                                         ((const struct rte_flow_item_ipv6 *)
4772                                          items->spec)->hdr.proto;
4773                                 next_protocol =
4774                                         ((const struct rte_flow_item_ipv6 *)
4775                                          items->spec)->hdr.proto;
4776                                 next_protocol &=
4777                                         ((const struct rte_flow_item_ipv6 *)
4778                                          items->mask)->hdr.proto;
4779                         } else {
4780                                 /* Reset for inner layer. */
4781                                 next_protocol = 0xff;
4782                         }
4783                         break;
4784                 case RTE_FLOW_ITEM_TYPE_TCP:
4785                         ret = mlx5_flow_validate_item_tcp
4786                                                 (items, item_flags,
4787                                                  next_protocol,
4788                                                  &nic_tcp_mask,
4789                                                  error);
4790                         if (ret < 0)
4791                                 return ret;
4792                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4793                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
4794                         break;
4795                 case RTE_FLOW_ITEM_TYPE_UDP:
4796                         ret = mlx5_flow_validate_item_udp(items, item_flags,
4797                                                           next_protocol,
4798                                                           error);
4799                         if (ret < 0)
4800                                 return ret;
4801                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4802                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
4803                         break;
4804                 case RTE_FLOW_ITEM_TYPE_GRE:
4805                         ret = mlx5_flow_validate_item_gre(items, item_flags,
4806                                                           next_protocol, error);
4807                         if (ret < 0)
4808                                 return ret;
4809                         gre_item = items;
4810                         last_item = MLX5_FLOW_LAYER_GRE;
4811                         break;
4812                 case RTE_FLOW_ITEM_TYPE_NVGRE:
4813                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4814                                                             next_protocol,
4815                                                             error);
4816                         if (ret < 0)
4817                                 return ret;
4818                         last_item = MLX5_FLOW_LAYER_NVGRE;
4819                         break;
4820                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4821                         ret = mlx5_flow_validate_item_gre_key
4822                                 (items, item_flags, gre_item, error);
4823                         if (ret < 0)
4824                                 return ret;
4825                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
4826                         break;
4827                 case RTE_FLOW_ITEM_TYPE_VXLAN:
4828                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4829                                                             error);
4830                         if (ret < 0)
4831                                 return ret;
4832                         last_item = MLX5_FLOW_LAYER_VXLAN;
4833                         break;
4834                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4835                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
4836                                                                 item_flags, dev,
4837                                                                 error);
4838                         if (ret < 0)
4839                                 return ret;
4840                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4841                         break;
4842                 case RTE_FLOW_ITEM_TYPE_GENEVE:
4843                         ret = mlx5_flow_validate_item_geneve(items,
4844                                                              item_flags, dev,
4845                                                              error);
4846                         if (ret < 0)
4847                                 return ret;
4848                         last_item = MLX5_FLOW_LAYER_GENEVE;
4849                         break;
4850                 case RTE_FLOW_ITEM_TYPE_MPLS:
4851                         ret = mlx5_flow_validate_item_mpls(dev, items,
4852                                                            item_flags,
4853                                                            last_item, error);
4854                         if (ret < 0)
4855                                 return ret;
4856                         last_item = MLX5_FLOW_LAYER_MPLS;
4857                         break;
4858
4859                 case RTE_FLOW_ITEM_TYPE_MARK:
4860                         ret = flow_dv_validate_item_mark(dev, items, attr,
4861                                                          error);
4862                         if (ret < 0)
4863                                 return ret;
4864                         last_item = MLX5_FLOW_ITEM_MARK;
4865                         break;
4866                 case RTE_FLOW_ITEM_TYPE_META:
4867                         ret = flow_dv_validate_item_meta(dev, items, attr,
4868                                                          error);
4869                         if (ret < 0)
4870                                 return ret;
4871                         last_item = MLX5_FLOW_ITEM_METADATA;
4872                         break;
4873                 case RTE_FLOW_ITEM_TYPE_ICMP:
4874                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
4875                                                            next_protocol,
4876                                                            error);
4877                         if (ret < 0)
4878                                 return ret;
4879                         last_item = MLX5_FLOW_LAYER_ICMP;
4880                         break;
4881                 case RTE_FLOW_ITEM_TYPE_ICMP6:
4882                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4883                                                             next_protocol,
4884                                                             error);
4885                         if (ret < 0)
4886                                 return ret;
4887                         item_ipv6_proto = IPPROTO_ICMPV6;
4888                         last_item = MLX5_FLOW_LAYER_ICMP6;
4889                         break;
4890                 case RTE_FLOW_ITEM_TYPE_TAG:
4891                         ret = flow_dv_validate_item_tag(dev, items,
4892                                                         attr, error);
4893                         if (ret < 0)
4894                                 return ret;
4895                         last_item = MLX5_FLOW_ITEM_TAG;
4896                         break;
4897                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4898                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4899                         break;
4900                 case RTE_FLOW_ITEM_TYPE_GTP:
4901                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4902                                                         error);
4903                         if (ret < 0)
4904                                 return ret;
4905                         last_item = MLX5_FLOW_LAYER_GTP;
4906                         break;
4907                 default:
4908                         return rte_flow_error_set(error, ENOTSUP,
4909                                                   RTE_FLOW_ERROR_TYPE_ITEM,
4910                                                   NULL, "item not supported");
4911                 }
4912                 item_flags |= last_item;
4913         }
4914         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4915                 int type = actions->type;
4916                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4917                         return rte_flow_error_set(error, ENOTSUP,
4918                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4919                                                   actions, "too many actions");
4920                 switch (type) {
4921                 case RTE_FLOW_ACTION_TYPE_VOID:
4922                         break;
4923                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4924                         ret = flow_dv_validate_action_port_id(dev,
4925                                                               action_flags,
4926                                                               actions,
4927                                                               attr,
4928                                                               error);
4929                         if (ret)
4930                                 return ret;
4931                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4932                         ++actions_n;
4933                         break;
4934                 case RTE_FLOW_ACTION_TYPE_FLAG:
4935                         ret = flow_dv_validate_action_flag(dev, action_flags,
4936                                                            attr, error);
4937                         if (ret < 0)
4938                                 return ret;
4939                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4940                                 /* Count all modify-header actions as one. */
4941                                 if (!(action_flags &
4942                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4943                                         ++actions_n;
4944                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
4945                                                 MLX5_FLOW_ACTION_MARK_EXT;
4946                         } else {
4947                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
4948                                 ++actions_n;
4949                         }
4950                         break;
4951                 case RTE_FLOW_ACTION_TYPE_MARK:
4952                         ret = flow_dv_validate_action_mark(dev, actions,
4953                                                            action_flags,
4954                                                            attr, error);
4955                         if (ret < 0)
4956                                 return ret;
4957                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4958                                 /* Count all modify-header actions as one. */
4959                                 if (!(action_flags &
4960                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
4961                                         ++actions_n;
4962                                 action_flags |= MLX5_FLOW_ACTION_MARK |
4963                                                 MLX5_FLOW_ACTION_MARK_EXT;
4964                         } else {
4965                                 action_flags |= MLX5_FLOW_ACTION_MARK;
4966                                 ++actions_n;
4967                         }
4968                         break;
4969                 case RTE_FLOW_ACTION_TYPE_SET_META:
4970                         ret = flow_dv_validate_action_set_meta(dev, actions,
4971                                                                action_flags,
4972                                                                attr, error);
4973                         if (ret < 0)
4974                                 return ret;
4975                         /* Count all modify-header actions as one action. */
4976                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4977                                 ++actions_n;
4978                         action_flags |= MLX5_FLOW_ACTION_SET_META;
4979                         break;
4980                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4981                         ret = flow_dv_validate_action_set_tag(dev, actions,
4982                                                               action_flags,
4983                                                               attr, error);
4984                         if (ret < 0)
4985                                 return ret;
4986                         /* Count all modify-header actions as one action. */
4987                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4988                                 ++actions_n;
4989                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4990                         break;
4991                 case RTE_FLOW_ACTION_TYPE_DROP:
4992                         ret = mlx5_flow_validate_action_drop(action_flags,
4993                                                              attr, error);
4994                         if (ret < 0)
4995                                 return ret;
4996                         action_flags |= MLX5_FLOW_ACTION_DROP;
4997                         ++actions_n;
4998                         break;
4999                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5000                         ret = mlx5_flow_validate_action_queue(actions,
5001                                                               action_flags, dev,
5002                                                               attr, error);
5003                         if (ret < 0)
5004                                 return ret;
5005                         queue_index = ((const struct rte_flow_action_queue *)
5006                                                         (actions->conf))->index;
5007                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5008                         ++actions_n;
5009                         break;
5010                 case RTE_FLOW_ACTION_TYPE_RSS:
5011                         rss = actions->conf;
5012                         ret = mlx5_flow_validate_action_rss(actions,
5013                                                             action_flags, dev,
5014                                                             attr, item_flags,
5015                                                             error);
5016                         if (ret < 0)
5017                                 return ret;
5018                         if (rss != NULL && rss->queue_num)
5019                                 queue_index = rss->queue[0];
5020                         action_flags |= MLX5_FLOW_ACTION_RSS;
5021                         ++actions_n;
5022                         break;
5023                 case RTE_FLOW_ACTION_TYPE_COUNT:
5024                         ret = flow_dv_validate_action_count(dev, error);
5025                         if (ret < 0)
5026                                 return ret;
5027                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5028                         ++actions_n;
5029                         break;
5030                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5031                         if (flow_dv_validate_action_pop_vlan(dev,
5032                                                              action_flags,
5033                                                              actions,
5034                                                              item_flags, attr,
5035                                                              error))
5036                                 return -rte_errno;
5037                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5038                         ++actions_n;
5039                         break;
5040                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5041                         ret = flow_dv_validate_action_push_vlan(dev,
5042                                                                 action_flags,
5043                                                                 item_flags,
5044                                                                 actions, attr,
5045                                                                 error);
5046                         if (ret < 0)
5047                                 return ret;
5048                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5049                         ++actions_n;
5050                         break;
5051                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5052                         ret = flow_dv_validate_action_set_vlan_pcp
5053                                                 (action_flags, actions, error);
5054                         if (ret < 0)
5055                                 return ret;
5056                         /* Count PCP with push_vlan command. */
5057                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5058                         break;
5059                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5060                         ret = flow_dv_validate_action_set_vlan_vid
5061                                                 (item_flags, action_flags,
5062                                                  actions, error);
5063                         if (ret < 0)
5064                                 return ret;
5065                         /* Count VID with push_vlan command. */
5066                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5067                         break;
5068                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5069                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5070                         ret = flow_dv_validate_action_l2_encap(dev,
5071                                                                action_flags,
5072                                                                actions, attr,
5073                                                                error);
5074                         if (ret < 0)
5075                                 return ret;
5076                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5077                         ++actions_n;
5078                         break;
5079                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5080                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5081                         ret = flow_dv_validate_action_decap(dev, action_flags,
5082                                                             attr, error);
5083                         if (ret < 0)
5084                                 return ret;
5085                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5086                         ++actions_n;
5087                         break;
5088                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5089                         ret = flow_dv_validate_action_raw_encap_decap
5090                                 (dev, NULL, actions->conf, attr, &action_flags,
5091                                  &actions_n, error);
5092                         if (ret < 0)
5093                                 return ret;
5094                         break;
5095                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5096                         decap = actions->conf;
5097                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5098                                 ;
5099                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5100                                 encap = NULL;
5101                                 actions--;
5102                         } else {
5103                                 encap = actions->conf;
5104                         }
5105                         ret = flow_dv_validate_action_raw_encap_decap
5106                                            (dev,
5107                                             decap ? decap : &empty_decap, encap,
5108                                             attr, &action_flags, &actions_n,
5109                                             error);
5110                         if (ret < 0)
5111                                 return ret;
5112                         break;
5113                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5114                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5115                         ret = flow_dv_validate_action_modify_mac(action_flags,
5116                                                                  actions,
5117                                                                  item_flags,
5118                                                                  error);
5119                         if (ret < 0)
5120                                 return ret;
5121                         /* Count all modify-header actions as one action. */
5122                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5123                                 ++actions_n;
5124                         action_flags |= actions->type ==
5125                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5126                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5127                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5128                         break;
5129
5130                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5131                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5132                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5133                                                                   actions,
5134                                                                   item_flags,
5135                                                                   error);
5136                         if (ret < 0)
5137                                 return ret;
5138                         /* Count all modify-header actions as one action. */
5139                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5140                                 ++actions_n;
5141                         action_flags |= actions->type ==
5142                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5143                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5144                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5145                         break;
5146                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5147                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5148                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5149                                                                   actions,
5150                                                                   item_flags,
5151                                                                   error);
5152                         if (ret < 0)
5153                                 return ret;
5154                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5155                                 return rte_flow_error_set(error, ENOTSUP,
5156                                         RTE_FLOW_ERROR_TYPE_ACTION,
5157                                         actions,
5158                                         "Can't change header "
5159                                         "with ICMPv6 proto");
5160                         /* Count all modify-header actions as one action. */
5161                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5162                                 ++actions_n;
5163                         action_flags |= actions->type ==
5164                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5165                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5166                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5167                         break;
5168                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5169                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5170                         ret = flow_dv_validate_action_modify_tp(action_flags,
5171                                                                 actions,
5172                                                                 item_flags,
5173                                                                 error);
5174                         if (ret < 0)
5175                                 return ret;
5176                         /* Count all modify-header actions as one action. */
5177                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5178                                 ++actions_n;
5179                         action_flags |= actions->type ==
5180                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5181                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5182                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5183                         break;
5184                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5185                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5186                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5187                                                                  actions,
5188                                                                  item_flags,
5189                                                                  error);
5190                         if (ret < 0)
5191                                 return ret;
5192                         /* Count all modify-header actions as one action. */
5193                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5194                                 ++actions_n;
5195                         action_flags |= actions->type ==
5196                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5197                                                 MLX5_FLOW_ACTION_SET_TTL :
5198                                                 MLX5_FLOW_ACTION_DEC_TTL;
5199                         break;
5200                 case RTE_FLOW_ACTION_TYPE_JUMP:
5201                         ret = flow_dv_validate_action_jump(actions,
5202                                                            action_flags,
5203                                                            attr, external,
5204                                                            error);
5205                         if (ret)
5206                                 return ret;
5207                         ++actions_n;
5208                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5209                         break;
5210                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5211                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5212                         ret = flow_dv_validate_action_modify_tcp_seq
5213                                                                 (action_flags,
5214                                                                  actions,
5215                                                                  item_flags,
5216                                                                  error);
5217                         if (ret < 0)
5218                                 return ret;
5219                         /* Count all modify-header actions as one action. */
5220                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5221                                 ++actions_n;
5222                         action_flags |= actions->type ==
5223                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5224                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5225                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5226                         break;
5227                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5228                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5229                         ret = flow_dv_validate_action_modify_tcp_ack
5230                                                                 (action_flags,
5231                                                                  actions,
5232                                                                  item_flags,
5233                                                                  error);
5234                         if (ret < 0)
5235                                 return ret;
5236                         /* Count all modify-header actions as one action. */
5237                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5238                                 ++actions_n;
5239                         action_flags |= actions->type ==
5240                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5241                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5242                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5243                         break;
5244                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5245                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5246                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5247                         break;
5248                 case RTE_FLOW_ACTION_TYPE_METER:
5249                         ret = mlx5_flow_validate_action_meter(dev,
5250                                                               action_flags,
5251                                                               actions, attr,
5252                                                               error);
5253                         if (ret < 0)
5254                                 return ret;
5255                         action_flags |= MLX5_FLOW_ACTION_METER;
5256                         ++actions_n;
5257                         break;
5258                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5259                         ret = flow_dv_validate_action_modify_ipv4_dscp
5260                                                          (action_flags,
5261                                                           actions,
5262                                                           item_flags,
5263                                                           error);
5264                         if (ret < 0)
5265                                 return ret;
5266                         /* Count all modify-header actions as one action. */
5267                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5268                                 ++actions_n;
5269                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5270                         break;
5271                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5272                         ret = flow_dv_validate_action_modify_ipv6_dscp
5273                                                                 (action_flags,
5274                                                                  actions,
5275                                                                  item_flags,
5276                                                                  error);
5277                         if (ret < 0)
5278                                 return ret;
5279                         /* Count all modify-header actions as one action. */
5280                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5281                                 ++actions_n;
5282                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5283                         break;
5284                 default:
5285                         return rte_flow_error_set(error, ENOTSUP,
5286                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5287                                                   actions,
5288                                                   "action not supported");
5289                 }
5290         }
5291         /*
5292          * Validate the drop action mutual exclusion with other actions.
5293          * Drop action is mutually-exclusive with any other action, except for
5294          * Count action.
5295          */
5296         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5297             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5298                 return rte_flow_error_set(error, EINVAL,
5299                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5300                                           "Drop action is mutually-exclusive "
5301                                           "with any other action, except for "
5302                                           "Count action");
5303         /* Eswitch has few restrictions on using items and actions */
5304         if (attr->transfer) {
5305                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5306                     action_flags & MLX5_FLOW_ACTION_FLAG)
5307                         return rte_flow_error_set(error, ENOTSUP,
5308                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5309                                                   NULL,
5310                                                   "unsupported action FLAG");
5311                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5312                     action_flags & MLX5_FLOW_ACTION_MARK)
5313                         return rte_flow_error_set(error, ENOTSUP,
5314                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5315                                                   NULL,
5316                                                   "unsupported action MARK");
5317                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5318                         return rte_flow_error_set(error, ENOTSUP,
5319                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5320                                                   NULL,
5321                                                   "unsupported action QUEUE");
5322                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5323                         return rte_flow_error_set(error, ENOTSUP,
5324                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5325                                                   NULL,
5326                                                   "unsupported action RSS");
5327                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5328                         return rte_flow_error_set(error, EINVAL,
5329                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5330                                                   actions,
5331                                                   "no fate action is found");
5332         } else {
5333                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5334                         return rte_flow_error_set(error, EINVAL,
5335                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5336                                                   actions,
5337                                                   "no fate action is found");
5338         }
5339         /* Continue validation for Xcap actions.*/
5340         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5341             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5342                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5343                     MLX5_FLOW_XCAP_ACTIONS)
5344                         return rte_flow_error_set(error, ENOTSUP,
5345                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5346                                                   NULL, "encap and decap "
5347                                                   "combination aren't supported");
5348                 if (!attr->transfer && attr->ingress && (action_flags &
5349                                                         MLX5_FLOW_ACTION_ENCAP))
5350                         return rte_flow_error_set(error, ENOTSUP,
5351                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5352                                                   NULL, "encap is not supported"
5353                                                   " for ingress traffic");
5354         }
5355         return 0;
5356 }
5357
5358 /**
5359  * Internal preparation function. Allocates the DV flow size,
5360  * this size is constant.
5361  *
5362  * @param[in] dev
5363  *   Pointer to the rte_eth_dev structure.
5364  * @param[in] attr
5365  *   Pointer to the flow attributes.
5366  * @param[in] items
5367  *   Pointer to the list of items.
5368  * @param[in] actions
5369  *   Pointer to the list of actions.
5370  * @param[out] error
5371  *   Pointer to the error structure.
5372  *
5373  * @return
5374  *   Pointer to mlx5_flow object on success,
5375  *   otherwise NULL and rte_errno is set.
5376  */
5377 static struct mlx5_flow *
5378 flow_dv_prepare(struct rte_eth_dev *dev,
5379                 const struct rte_flow_attr *attr __rte_unused,
5380                 const struct rte_flow_item items[] __rte_unused,
5381                 const struct rte_flow_action actions[] __rte_unused,
5382                 struct rte_flow_error *error)
5383 {
5384         size_t size = sizeof(struct mlx5_flow_handle);
5385         struct mlx5_flow *dev_flow;
5386         struct mlx5_flow_handle *dev_handle;
5387         struct mlx5_priv *priv = dev->data->dev_private;
5388
5389         /* In case of corrupting the memory. */
5390         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5391                 rte_flow_error_set(error, ENOSPC,
5392                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5393                                    "not free temporary device flow");
5394                 return NULL;
5395         }
5396         dev_handle = rte_calloc(__func__, 1, size, 0);
5397         if (!dev_handle) {
5398                 rte_flow_error_set(error, ENOMEM,
5399                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5400                                    "not enough memory to create flow handle");
5401                 return NULL;
5402         }
5403         /* No multi-thread supporting. */
5404         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5405         dev_flow->handle = dev_handle;
5406         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5407         /*
5408          * The matching value needs to be cleared to 0 before using. In the
5409          * past, it will be automatically cleared when using rte_*alloc
5410          * API. The time consumption will be almost the same as before.
5411          */
5412         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5413         dev_flow->ingress = attr->ingress;
5414         dev_flow->dv.transfer = attr->transfer;
5415         return dev_flow;
5416 }
5417
5418 #ifdef RTE_LIBRTE_MLX5_DEBUG
5419 /**
5420  * Sanity check for match mask and value. Similar to check_valid_spec() in
5421  * kernel driver. If unmasked bit is present in value, it returns failure.
5422  *
5423  * @param match_mask
5424  *   pointer to match mask buffer.
5425  * @param match_value
5426  *   pointer to match value buffer.
5427  *
5428  * @return
5429  *   0 if valid, -EINVAL otherwise.
5430  */
5431 static int
5432 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5433 {
5434         uint8_t *m = match_mask;
5435         uint8_t *v = match_value;
5436         unsigned int i;
5437
5438         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5439                 if (v[i] & ~m[i]) {
5440                         DRV_LOG(ERR,
5441                                 "match_value differs from match_criteria"
5442                                 " %p[%u] != %p[%u]",
5443                                 match_value, i, match_mask, i);
5444                         return -EINVAL;
5445                 }
5446         }
5447         return 0;
5448 }
5449 #endif
5450
5451 /**
5452  * Add Ethernet item to matcher and to the value.
5453  *
5454  * @param[in, out] matcher
5455  *   Flow matcher.
5456  * @param[in, out] key
5457  *   Flow matcher value.
5458  * @param[in] item
5459  *   Flow pattern to translate.
5460  * @param[in] inner
5461  *   Item is inner pattern.
5462  */
5463 static void
5464 flow_dv_translate_item_eth(void *matcher, void *key,
5465                            const struct rte_flow_item *item, int inner)
5466 {
5467         const struct rte_flow_item_eth *eth_m = item->mask;
5468         const struct rte_flow_item_eth *eth_v = item->spec;
5469         const struct rte_flow_item_eth nic_mask = {
5470                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5471                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5472                 .type = RTE_BE16(0xffff),
5473         };
5474         void *headers_m;
5475         void *headers_v;
5476         char *l24_v;
5477         unsigned int i;
5478
5479         if (!eth_v)
5480                 return;
5481         if (!eth_m)
5482                 eth_m = &nic_mask;
5483         if (inner) {
5484                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5485                                          inner_headers);
5486                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5487         } else {
5488                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5489                                          outer_headers);
5490                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5491         }
5492         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5493                &eth_m->dst, sizeof(eth_m->dst));
5494         /* The value must be in the range of the mask. */
5495         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5496         for (i = 0; i < sizeof(eth_m->dst); ++i)
5497                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5498         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5499                &eth_m->src, sizeof(eth_m->src));
5500         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5501         /* The value must be in the range of the mask. */
5502         for (i = 0; i < sizeof(eth_m->dst); ++i)
5503                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5504         if (eth_v->type) {
5505                 /* When ethertype is present set mask for tagged VLAN. */
5506                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5507                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5508                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5509                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5510                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5511                                  1);
5512                         /* Return here to avoid setting match on ethertype. */
5513                         return;
5514                 }
5515         }
5516         /*
5517          * HW supports match on one Ethertype, the Ethertype following the last
5518          * VLAN tag of the packet (see PRM).
5519          * Set match on ethertype only if ETH header is not followed by VLAN.
5520          */
5521         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5522                  rte_be_to_cpu_16(eth_m->type));
5523         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5524         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5525 }
5526
5527 /**
5528  * Add VLAN item to matcher and to the value.
5529  *
5530  * @param[in, out] dev_flow
5531  *   Flow descriptor.
5532  * @param[in, out] matcher
5533  *   Flow matcher.
5534  * @param[in, out] key
5535  *   Flow matcher value.
5536  * @param[in] item
5537  *   Flow pattern to translate.
5538  * @param[in] inner
5539  *   Item is inner pattern.
5540  */
5541 static void
5542 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5543                             void *matcher, void *key,
5544                             const struct rte_flow_item *item,
5545                             int inner)
5546 {
5547         const struct rte_flow_item_vlan *vlan_m = item->mask;
5548         const struct rte_flow_item_vlan *vlan_v = item->spec;
5549         void *headers_m;
5550         void *headers_v;
5551         uint16_t tci_m;
5552         uint16_t tci_v;
5553
5554         if (!vlan_v)
5555                 return;
5556         if (!vlan_m)
5557                 vlan_m = &rte_flow_item_vlan_mask;
5558         if (inner) {
5559                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5560                                          inner_headers);
5561                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5562         } else {
5563                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5564                                          outer_headers);
5565                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5566                 /*
5567                  * This is workaround, masks are not supported,
5568                  * and pre-validated.
5569                  */
5570                 dev_flow->handle->vf_vlan.tag =
5571                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5572         }
5573         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5574         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5575         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5576         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5577         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5578         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5579         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5580         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5581         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5582         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5583         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5584                  rte_be_to_cpu_16(vlan_m->inner_type));
5585         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5586                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5587 }
5588
5589 /**
5590  * Add IPV4 item to matcher and to the value.
5591  *
5592  * @param[in, out] matcher
5593  *   Flow matcher.
5594  * @param[in, out] key
5595  *   Flow matcher value.
5596  * @param[in] item
5597  *   Flow pattern to translate.
5598  * @param[in] item_flags
5599  *   Bit-fields that holds the items detected until now.
5600  * @param[in] inner
5601  *   Item is inner pattern.
5602  * @param[in] group
5603  *   The group to insert the rule.
5604  */
5605 static void
5606 flow_dv_translate_item_ipv4(void *matcher, void *key,
5607                             const struct rte_flow_item *item,
5608                             const uint64_t item_flags,
5609                             int inner, uint32_t group)
5610 {
5611         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5612         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5613         const struct rte_flow_item_ipv4 nic_mask = {
5614                 .hdr = {
5615                         .src_addr = RTE_BE32(0xffffffff),
5616                         .dst_addr = RTE_BE32(0xffffffff),
5617                         .type_of_service = 0xff,
5618                         .next_proto_id = 0xff,
5619                         .time_to_live = 0xff,
5620                 },
5621         };
5622         void *headers_m;
5623         void *headers_v;
5624         char *l24_m;
5625         char *l24_v;
5626         uint8_t tos;
5627
5628         if (inner) {
5629                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5630                                          inner_headers);
5631                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5632         } else {
5633                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5634                                          outer_headers);
5635                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5636         }
5637         if (group == 0)
5638                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5639         else
5640                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5641         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5642         /*
5643          * On outer header (which must contains L2), or inner header with L2,
5644          * set cvlan_tag mask bit to mark this packet as untagged.
5645          * This should be done even if item->spec is empty.
5646          */
5647         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5648                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5649         if (!ipv4_v)
5650                 return;
5651         if (!ipv4_m)
5652                 ipv4_m = &nic_mask;
5653         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5654                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5655         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5656                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5657         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5658         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5659         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5660                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5661         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5662                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5663         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5664         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5665         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5666         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5667                  ipv4_m->hdr.type_of_service);
5668         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5669         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5670                  ipv4_m->hdr.type_of_service >> 2);
5671         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5672         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5673                  ipv4_m->hdr.next_proto_id);
5674         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5675                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5676         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5677                  ipv4_m->hdr.time_to_live);
5678         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5679                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
5680 }
5681
5682 /**
5683  * Add IPV6 item to matcher and to the value.
5684  *
5685  * @param[in, out] matcher
5686  *   Flow matcher.
5687  * @param[in, out] key
5688  *   Flow matcher value.
5689  * @param[in] item
5690  *   Flow pattern to translate.
5691  * @param[in] item_flags
5692  *   Bit-fields that holds the items detected until now.
5693  * @param[in] inner
5694  *   Item is inner pattern.
5695  * @param[in] group
5696  *   The group to insert the rule.
5697  */
5698 static void
5699 flow_dv_translate_item_ipv6(void *matcher, void *key,
5700                             const struct rte_flow_item *item,
5701                             const uint64_t item_flags,
5702                             int inner, uint32_t group)
5703 {
5704         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5705         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5706         const struct rte_flow_item_ipv6 nic_mask = {
5707                 .hdr = {
5708                         .src_addr =
5709                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5710                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5711                         .dst_addr =
5712                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
5713                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
5714                         .vtc_flow = RTE_BE32(0xffffffff),
5715                         .proto = 0xff,
5716                         .hop_limits = 0xff,
5717                 },
5718         };
5719         void *headers_m;
5720         void *headers_v;
5721         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5722         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5723         char *l24_m;
5724         char *l24_v;
5725         uint32_t vtc_m;
5726         uint32_t vtc_v;
5727         int i;
5728         int size;
5729
5730         if (inner) {
5731                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5732                                          inner_headers);
5733                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5734         } else {
5735                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5736                                          outer_headers);
5737                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5738         }
5739         if (group == 0)
5740                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5741         else
5742                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5743         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5744         /*
5745          * On outer header (which must contains L2), or inner header with L2,
5746          * set cvlan_tag mask bit to mark this packet as untagged.
5747          * This should be done even if item->spec is empty.
5748          */
5749         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5750                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5751         if (!ipv6_v)
5752                 return;
5753         if (!ipv6_m)
5754                 ipv6_m = &nic_mask;
5755         size = sizeof(ipv6_m->hdr.dst_addr);
5756         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5757                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5758         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5759                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5760         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5761         for (i = 0; i < size; ++i)
5762                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5763         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5764                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5765         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5766                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
5767         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5768         for (i = 0; i < size; ++i)
5769                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5770         /* TOS. */
5771         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5772         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5773         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5774         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5775         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5776         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5777         /* Label. */
5778         if (inner) {
5779                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5780                          vtc_m);
5781                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5782                          vtc_v);
5783         } else {
5784                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5785                          vtc_m);
5786                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5787                          vtc_v);
5788         }
5789         /* Protocol. */
5790         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5791                  ipv6_m->hdr.proto);
5792         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5793                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5794         /* Hop limit. */
5795         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
5796                  ipv6_m->hdr.hop_limits);
5797         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
5798                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
5799 }
5800
5801 /**
5802  * Add TCP item to matcher and to the value.
5803  *
5804  * @param[in, out] matcher
5805  *   Flow matcher.
5806  * @param[in, out] key
5807  *   Flow matcher value.
5808  * @param[in] item
5809  *   Flow pattern to translate.
5810  * @param[in] inner
5811  *   Item is inner pattern.
5812  */
5813 static void
5814 flow_dv_translate_item_tcp(void *matcher, void *key,
5815                            const struct rte_flow_item *item,
5816                            int inner)
5817 {
5818         const struct rte_flow_item_tcp *tcp_m = item->mask;
5819         const struct rte_flow_item_tcp *tcp_v = item->spec;
5820         void *headers_m;
5821         void *headers_v;
5822
5823         if (inner) {
5824                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5825                                          inner_headers);
5826                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5827         } else {
5828                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5829                                          outer_headers);
5830                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5831         }
5832         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5833         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5834         if (!tcp_v)
5835                 return;
5836         if (!tcp_m)
5837                 tcp_m = &rte_flow_item_tcp_mask;
5838         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5839                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
5840         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5841                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5842         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5843                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5844         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5845                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5846         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5847                  tcp_m->hdr.tcp_flags);
5848         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5849                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5850 }
5851
5852 /**
5853  * Add UDP item to matcher and to the value.
5854  *
5855  * @param[in, out] matcher
5856  *   Flow matcher.
5857  * @param[in, out] key
5858  *   Flow matcher value.
5859  * @param[in] item
5860  *   Flow pattern to translate.
5861  * @param[in] inner
5862  *   Item is inner pattern.
5863  */
5864 static void
5865 flow_dv_translate_item_udp(void *matcher, void *key,
5866                            const struct rte_flow_item *item,
5867                            int inner)
5868 {
5869         const struct rte_flow_item_udp *udp_m = item->mask;
5870         const struct rte_flow_item_udp *udp_v = item->spec;
5871         void *headers_m;
5872         void *headers_v;
5873
5874         if (inner) {
5875                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5876                                          inner_headers);
5877                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5878         } else {
5879                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5880                                          outer_headers);
5881                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5882         }
5883         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5884         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5885         if (!udp_v)
5886                 return;
5887         if (!udp_m)
5888                 udp_m = &rte_flow_item_udp_mask;
5889         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5890                  rte_be_to_cpu_16(udp_m->hdr.src_port));
5891         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5892                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5893         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5894                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
5895         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5896                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5897 }
5898
5899 /**
5900  * Add GRE optional Key item to matcher and to the value.
5901  *
5902  * @param[in, out] matcher
5903  *   Flow matcher.
5904  * @param[in, out] key
5905  *   Flow matcher value.
5906  * @param[in] item
5907  *   Flow pattern to translate.
5908  * @param[in] inner
5909  *   Item is inner pattern.
5910  */
5911 static void
5912 flow_dv_translate_item_gre_key(void *matcher, void *key,
5913                                    const struct rte_flow_item *item)
5914 {
5915         const rte_be32_t *key_m = item->mask;
5916         const rte_be32_t *key_v = item->spec;
5917         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5918         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5919         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5920
5921         /* GRE K bit must be on and should already be validated */
5922         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5923         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5924         if (!key_v)
5925                 return;
5926         if (!key_m)
5927                 key_m = &gre_key_default_mask;
5928         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5929                  rte_be_to_cpu_32(*key_m) >> 8);
5930         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5931                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5932         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5933                  rte_be_to_cpu_32(*key_m) & 0xFF);
5934         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5935                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5936 }
5937
5938 /**
5939  * Add GRE item to matcher and to the value.
5940  *
5941  * @param[in, out] matcher
5942  *   Flow matcher.
5943  * @param[in, out] key
5944  *   Flow matcher value.
5945  * @param[in] item
5946  *   Flow pattern to translate.
5947  * @param[in] inner
5948  *   Item is inner pattern.
5949  */
5950 static void
5951 flow_dv_translate_item_gre(void *matcher, void *key,
5952                            const struct rte_flow_item *item,
5953                            int inner)
5954 {
5955         const struct rte_flow_item_gre *gre_m = item->mask;
5956         const struct rte_flow_item_gre *gre_v = item->spec;
5957         void *headers_m;
5958         void *headers_v;
5959         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5960         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5961         struct {
5962                 union {
5963                         __extension__
5964                         struct {
5965                                 uint16_t version:3;
5966                                 uint16_t rsvd0:9;
5967                                 uint16_t s_present:1;
5968                                 uint16_t k_present:1;
5969                                 uint16_t rsvd_bit1:1;
5970                                 uint16_t c_present:1;
5971                         };
5972                         uint16_t value;
5973                 };
5974         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5975
5976         if (inner) {
5977                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5978                                          inner_headers);
5979                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5980         } else {
5981                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5982                                          outer_headers);
5983                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5984         }
5985         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5986         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5987         if (!gre_v)
5988                 return;
5989         if (!gre_m)
5990                 gre_m = &rte_flow_item_gre_mask;
5991         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5992                  rte_be_to_cpu_16(gre_m->protocol));
5993         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5994                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5995         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5996         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5997         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5998                  gre_crks_rsvd0_ver_m.c_present);
5999         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6000                  gre_crks_rsvd0_ver_v.c_present &
6001                  gre_crks_rsvd0_ver_m.c_present);
6002         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6003                  gre_crks_rsvd0_ver_m.k_present);
6004         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6005                  gre_crks_rsvd0_ver_v.k_present &
6006                  gre_crks_rsvd0_ver_m.k_present);
6007         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6008                  gre_crks_rsvd0_ver_m.s_present);
6009         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6010                  gre_crks_rsvd0_ver_v.s_present &
6011                  gre_crks_rsvd0_ver_m.s_present);
6012 }
6013
6014 /**
6015  * Add NVGRE item to matcher and to the value.
6016  *
6017  * @param[in, out] matcher
6018  *   Flow matcher.
6019  * @param[in, out] key
6020  *   Flow matcher value.
6021  * @param[in] item
6022  *   Flow pattern to translate.
6023  * @param[in] inner
6024  *   Item is inner pattern.
6025  */
6026 static void
6027 flow_dv_translate_item_nvgre(void *matcher, void *key,
6028                              const struct rte_flow_item *item,
6029                              int inner)
6030 {
6031         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6032         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6033         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6034         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6035         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6036         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6037         char *gre_key_m;
6038         char *gre_key_v;
6039         int size;
6040         int i;
6041
6042         /* For NVGRE, GRE header fields must be set with defined values. */
6043         const struct rte_flow_item_gre gre_spec = {
6044                 .c_rsvd0_ver = RTE_BE16(0x2000),
6045                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6046         };
6047         const struct rte_flow_item_gre gre_mask = {
6048                 .c_rsvd0_ver = RTE_BE16(0xB000),
6049                 .protocol = RTE_BE16(UINT16_MAX),
6050         };
6051         const struct rte_flow_item gre_item = {
6052                 .spec = &gre_spec,
6053                 .mask = &gre_mask,
6054                 .last = NULL,
6055         };
6056         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6057         if (!nvgre_v)
6058                 return;
6059         if (!nvgre_m)
6060                 nvgre_m = &rte_flow_item_nvgre_mask;
6061         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6062         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6063         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6064         memcpy(gre_key_m, tni_flow_id_m, size);
6065         for (i = 0; i < size; ++i)
6066                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6067 }
6068
6069 /**
6070  * Add VXLAN item to matcher and to the value.
6071  *
6072  * @param[in, out] matcher
6073  *   Flow matcher.
6074  * @param[in, out] key
6075  *   Flow matcher value.
6076  * @param[in] item
6077  *   Flow pattern to translate.
6078  * @param[in] inner
6079  *   Item is inner pattern.
6080  */
6081 static void
6082 flow_dv_translate_item_vxlan(void *matcher, void *key,
6083                              const struct rte_flow_item *item,
6084                              int inner)
6085 {
6086         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6087         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6088         void *headers_m;
6089         void *headers_v;
6090         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6091         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6092         char *vni_m;
6093         char *vni_v;
6094         uint16_t dport;
6095         int size;
6096         int i;
6097
6098         if (inner) {
6099                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6100                                          inner_headers);
6101                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6102         } else {
6103                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6104                                          outer_headers);
6105                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6106         }
6107         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6108                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6109         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6110                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6111                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6112         }
6113         if (!vxlan_v)
6114                 return;
6115         if (!vxlan_m)
6116                 vxlan_m = &rte_flow_item_vxlan_mask;
6117         size = sizeof(vxlan_m->vni);
6118         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6119         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6120         memcpy(vni_m, vxlan_m->vni, size);
6121         for (i = 0; i < size; ++i)
6122                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6123 }
6124
6125 /**
6126  * Add VXLAN-GPE item to matcher and to the value.
6127  *
6128  * @param[in, out] matcher
6129  *   Flow matcher.
6130  * @param[in, out] key
6131  *   Flow matcher value.
6132  * @param[in] item
6133  *   Flow pattern to translate.
6134  * @param[in] inner
6135  *   Item is inner pattern.
6136  */
6137
6138 static void
6139 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6140                                  const struct rte_flow_item *item, int inner)
6141 {
6142         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6143         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6144         void *headers_m;
6145         void *headers_v;
6146         void *misc_m =
6147                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6148         void *misc_v =
6149                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6150         char *vni_m;
6151         char *vni_v;
6152         uint16_t dport;
6153         int size;
6154         int i;
6155         uint8_t flags_m = 0xff;
6156         uint8_t flags_v = 0xc;
6157
6158         if (inner) {
6159                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6160                                          inner_headers);
6161                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6162         } else {
6163                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6164                                          outer_headers);
6165                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6166         }
6167         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6168                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6169         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6170                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6171                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6172         }
6173         if (!vxlan_v)
6174                 return;
6175         if (!vxlan_m)
6176                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6177         size = sizeof(vxlan_m->vni);
6178         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6179         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6180         memcpy(vni_m, vxlan_m->vni, size);
6181         for (i = 0; i < size; ++i)
6182                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6183         if (vxlan_m->flags) {
6184                 flags_m = vxlan_m->flags;
6185                 flags_v = vxlan_v->flags;
6186         }
6187         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6188         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6189         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6190                  vxlan_m->protocol);
6191         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6192                  vxlan_v->protocol);
6193 }
6194
6195 /**
6196  * Add Geneve item to matcher and to the value.
6197  *
6198  * @param[in, out] matcher
6199  *   Flow matcher.
6200  * @param[in, out] key
6201  *   Flow matcher value.
6202  * @param[in] item
6203  *   Flow pattern to translate.
6204  * @param[in] inner
6205  *   Item is inner pattern.
6206  */
6207
6208 static void
6209 flow_dv_translate_item_geneve(void *matcher, void *key,
6210                               const struct rte_flow_item *item, int inner)
6211 {
6212         const struct rte_flow_item_geneve *geneve_m = item->mask;
6213         const struct rte_flow_item_geneve *geneve_v = item->spec;
6214         void *headers_m;
6215         void *headers_v;
6216         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6217         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6218         uint16_t dport;
6219         uint16_t gbhdr_m;
6220         uint16_t gbhdr_v;
6221         char *vni_m;
6222         char *vni_v;
6223         size_t size, i;
6224
6225         if (inner) {
6226                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6227                                          inner_headers);
6228                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6229         } else {
6230                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6231                                          outer_headers);
6232                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6233         }
6234         dport = MLX5_UDP_PORT_GENEVE;
6235         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6236                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6237                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6238         }
6239         if (!geneve_v)
6240                 return;
6241         if (!geneve_m)
6242                 geneve_m = &rte_flow_item_geneve_mask;
6243         size = sizeof(geneve_m->vni);
6244         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6245         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6246         memcpy(vni_m, geneve_m->vni, size);
6247         for (i = 0; i < size; ++i)
6248                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6249         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6250                  rte_be_to_cpu_16(geneve_m->protocol));
6251         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6252                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6253         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6254         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6255         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6256                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6257         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6258                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6259         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6260                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6261         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6262                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6263                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6264 }
6265
6266 /**
6267  * Add MPLS item to matcher and to the value.
6268  *
6269  * @param[in, out] matcher
6270  *   Flow matcher.
6271  * @param[in, out] key
6272  *   Flow matcher value.
6273  * @param[in] item
6274  *   Flow pattern to translate.
6275  * @param[in] prev_layer
6276  *   The protocol layer indicated in previous item.
6277  * @param[in] inner
6278  *   Item is inner pattern.
6279  */
6280 static void
6281 flow_dv_translate_item_mpls(void *matcher, void *key,
6282                             const struct rte_flow_item *item,
6283                             uint64_t prev_layer,
6284                             int inner)
6285 {
6286         const uint32_t *in_mpls_m = item->mask;
6287         const uint32_t *in_mpls_v = item->spec;
6288         uint32_t *out_mpls_m = 0;
6289         uint32_t *out_mpls_v = 0;
6290         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6291         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6292         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6293                                      misc_parameters_2);
6294         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6295         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6296         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6297
6298         switch (prev_layer) {
6299         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6300                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6301                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6302                          MLX5_UDP_PORT_MPLS);
6303                 break;
6304         case MLX5_FLOW_LAYER_GRE:
6305                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6306                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6307                          RTE_ETHER_TYPE_MPLS);
6308                 break;
6309         default:
6310                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6311                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6312                          IPPROTO_MPLS);
6313                 break;
6314         }
6315         if (!in_mpls_v)
6316                 return;
6317         if (!in_mpls_m)
6318                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6319         switch (prev_layer) {
6320         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6321                 out_mpls_m =
6322                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6323                                                  outer_first_mpls_over_udp);
6324                 out_mpls_v =
6325                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6326                                                  outer_first_mpls_over_udp);
6327                 break;
6328         case MLX5_FLOW_LAYER_GRE:
6329                 out_mpls_m =
6330                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6331                                                  outer_first_mpls_over_gre);
6332                 out_mpls_v =
6333                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6334                                                  outer_first_mpls_over_gre);
6335                 break;
6336         default:
6337                 /* Inner MPLS not over GRE is not supported. */
6338                 if (!inner) {
6339                         out_mpls_m =
6340                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6341                                                          misc2_m,
6342                                                          outer_first_mpls);
6343                         out_mpls_v =
6344                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6345                                                          misc2_v,
6346                                                          outer_first_mpls);
6347                 }
6348                 break;
6349         }
6350         if (out_mpls_m && out_mpls_v) {
6351                 *out_mpls_m = *in_mpls_m;
6352                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6353         }
6354 }
6355
6356 /**
6357  * Add metadata register item to matcher
6358  *
6359  * @param[in, out] matcher
6360  *   Flow matcher.
6361  * @param[in, out] key
6362  *   Flow matcher value.
6363  * @param[in] reg_type
6364  *   Type of device metadata register
6365  * @param[in] value
6366  *   Register value
6367  * @param[in] mask
6368  *   Register mask
6369  */
6370 static void
6371 flow_dv_match_meta_reg(void *matcher, void *key,
6372                        enum modify_reg reg_type,
6373                        uint32_t data, uint32_t mask)
6374 {
6375         void *misc2_m =
6376                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6377         void *misc2_v =
6378                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6379         uint32_t temp;
6380
6381         data &= mask;
6382         switch (reg_type) {
6383         case REG_A:
6384                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6385                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6386                 break;
6387         case REG_B:
6388                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6389                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6390                 break;
6391         case REG_C_0:
6392                 /*
6393                  * The metadata register C0 field might be divided into
6394                  * source vport index and META item value, we should set
6395                  * this field according to specified mask, not as whole one.
6396                  */
6397                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6398                 temp |= mask;
6399                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6400                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6401                 temp &= ~mask;
6402                 temp |= data;
6403                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6404                 break;
6405         case REG_C_1:
6406                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6407                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6408                 break;
6409         case REG_C_2:
6410                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6411                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6412                 break;
6413         case REG_C_3:
6414                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6415                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6416                 break;
6417         case REG_C_4:
6418                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6419                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6420                 break;
6421         case REG_C_5:
6422                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6423                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6424                 break;
6425         case REG_C_6:
6426                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6427                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6428                 break;
6429         case REG_C_7:
6430                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6431                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6432                 break;
6433         default:
6434                 MLX5_ASSERT(false);
6435                 break;
6436         }
6437 }
6438
6439 /**
6440  * Add MARK item to matcher
6441  *
6442  * @param[in] dev
6443  *   The device to configure through.
6444  * @param[in, out] matcher
6445  *   Flow matcher.
6446  * @param[in, out] key
6447  *   Flow matcher value.
6448  * @param[in] item
6449  *   Flow pattern to translate.
6450  */
6451 static void
6452 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6453                             void *matcher, void *key,
6454                             const struct rte_flow_item *item)
6455 {
6456         struct mlx5_priv *priv = dev->data->dev_private;
6457         const struct rte_flow_item_mark *mark;
6458         uint32_t value;
6459         uint32_t mask;
6460
6461         mark = item->mask ? (const void *)item->mask :
6462                             &rte_flow_item_mark_mask;
6463         mask = mark->id & priv->sh->dv_mark_mask;
6464         mark = (const void *)item->spec;
6465         MLX5_ASSERT(mark);
6466         value = mark->id & priv->sh->dv_mark_mask & mask;
6467         if (mask) {
6468                 enum modify_reg reg;
6469
6470                 /* Get the metadata register index for the mark. */
6471                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6472                 MLX5_ASSERT(reg > 0);
6473                 if (reg == REG_C_0) {
6474                         struct mlx5_priv *priv = dev->data->dev_private;
6475                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6476                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6477
6478                         mask &= msk_c0;
6479                         mask <<= shl_c0;
6480                         value <<= shl_c0;
6481                 }
6482                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6483         }
6484 }
6485
6486 /**
6487  * Add META item to matcher
6488  *
6489  * @param[in] dev
6490  *   The devich to configure through.
6491  * @param[in, out] matcher
6492  *   Flow matcher.
6493  * @param[in, out] key
6494  *   Flow matcher value.
6495  * @param[in] attr
6496  *   Attributes of flow that includes this item.
6497  * @param[in] item
6498  *   Flow pattern to translate.
6499  */
6500 static void
6501 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6502                             void *matcher, void *key,
6503                             const struct rte_flow_attr *attr,
6504                             const struct rte_flow_item *item)
6505 {
6506         const struct rte_flow_item_meta *meta_m;
6507         const struct rte_flow_item_meta *meta_v;
6508
6509         meta_m = (const void *)item->mask;
6510         if (!meta_m)
6511                 meta_m = &rte_flow_item_meta_mask;
6512         meta_v = (const void *)item->spec;
6513         if (meta_v) {
6514                 int reg;
6515                 uint32_t value = meta_v->data;
6516                 uint32_t mask = meta_m->data;
6517
6518                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6519                 if (reg < 0)
6520                         return;
6521                 /*
6522                  * In datapath code there is no endianness
6523                  * coversions for perfromance reasons, all
6524                  * pattern conversions are done in rte_flow.
6525                  */
6526                 value = rte_cpu_to_be_32(value);
6527                 mask = rte_cpu_to_be_32(mask);
6528                 if (reg == REG_C_0) {
6529                         struct mlx5_priv *priv = dev->data->dev_private;
6530                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6531                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6532 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6533                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6534
6535                         value >>= shr_c0;
6536                         mask >>= shr_c0;
6537 #endif
6538                         value <<= shl_c0;
6539                         mask <<= shl_c0;
6540                         MLX5_ASSERT(msk_c0);
6541                         MLX5_ASSERT(!(~msk_c0 & mask));
6542                 }
6543                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6544         }
6545 }
6546
6547 /**
6548  * Add vport metadata Reg C0 item to matcher
6549  *
6550  * @param[in, out] matcher
6551  *   Flow matcher.
6552  * @param[in, out] key
6553  *   Flow matcher value.
6554  * @param[in] reg
6555  *   Flow pattern to translate.
6556  */
6557 static void
6558 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6559                                   uint32_t value, uint32_t mask)
6560 {
6561         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6562 }
6563
6564 /**
6565  * Add tag item to matcher
6566  *
6567  * @param[in] dev
6568  *   The devich to configure through.
6569  * @param[in, out] matcher
6570  *   Flow matcher.
6571  * @param[in, out] key
6572  *   Flow matcher value.
6573  * @param[in] item
6574  *   Flow pattern to translate.
6575  */
6576 static void
6577 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6578                                 void *matcher, void *key,
6579                                 const struct rte_flow_item *item)
6580 {
6581         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6582         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6583         uint32_t mask, value;
6584
6585         MLX5_ASSERT(tag_v);
6586         value = tag_v->data;
6587         mask = tag_m ? tag_m->data : UINT32_MAX;
6588         if (tag_v->id == REG_C_0) {
6589                 struct mlx5_priv *priv = dev->data->dev_private;
6590                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6591                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6592
6593                 mask &= msk_c0;
6594                 mask <<= shl_c0;
6595                 value <<= shl_c0;
6596         }
6597         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6598 }
6599
6600 /**
6601  * Add TAG item to matcher
6602  *
6603  * @param[in] dev
6604  *   The devich to configure through.
6605  * @param[in, out] matcher
6606  *   Flow matcher.
6607  * @param[in, out] key
6608  *   Flow matcher value.
6609  * @param[in] item
6610  *   Flow pattern to translate.
6611  */
6612 static void
6613 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6614                            void *matcher, void *key,
6615                            const struct rte_flow_item *item)
6616 {
6617         const struct rte_flow_item_tag *tag_v = item->spec;
6618         const struct rte_flow_item_tag *tag_m = item->mask;
6619         enum modify_reg reg;
6620
6621         MLX5_ASSERT(tag_v);
6622         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6623         /* Get the metadata register index for the tag. */
6624         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6625         MLX5_ASSERT(reg > 0);
6626         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6627 }
6628
6629 /**
6630  * Add source vport match to the specified matcher.
6631  *
6632  * @param[in, out] matcher
6633  *   Flow matcher.
6634  * @param[in, out] key
6635  *   Flow matcher value.
6636  * @param[in] port
6637  *   Source vport value to match
6638  * @param[in] mask
6639  *   Mask
6640  */
6641 static void
6642 flow_dv_translate_item_source_vport(void *matcher, void *key,
6643                                     int16_t port, uint16_t mask)
6644 {
6645         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6646         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6647
6648         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6649         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6650 }
6651
6652 /**
6653  * Translate port-id item to eswitch match on  port-id.
6654  *
6655  * @param[in] dev
6656  *   The devich to configure through.
6657  * @param[in, out] matcher
6658  *   Flow matcher.
6659  * @param[in, out] key
6660  *   Flow matcher value.
6661  * @param[in] item
6662  *   Flow pattern to translate.
6663  *
6664  * @return
6665  *   0 on success, a negative errno value otherwise.
6666  */
6667 static int
6668 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6669                                void *key, const struct rte_flow_item *item)
6670 {
6671         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6672         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6673         struct mlx5_priv *priv;
6674         uint16_t mask, id;
6675
6676         mask = pid_m ? pid_m->id : 0xffff;
6677         id = pid_v ? pid_v->id : dev->data->port_id;
6678         priv = mlx5_port_to_eswitch_info(id, item == NULL);
6679         if (!priv)
6680                 return -rte_errno;
6681         /* Translate to vport field or to metadata, depending on mode. */
6682         if (priv->vport_meta_mask)
6683                 flow_dv_translate_item_meta_vport(matcher, key,
6684                                                   priv->vport_meta_tag,
6685                                                   priv->vport_meta_mask);
6686         else
6687                 flow_dv_translate_item_source_vport(matcher, key,
6688                                                     priv->vport_id, mask);
6689         return 0;
6690 }
6691
6692 /**
6693  * Add ICMP6 item to matcher and to the value.
6694  *
6695  * @param[in, out] matcher
6696  *   Flow matcher.
6697  * @param[in, out] key
6698  *   Flow matcher value.
6699  * @param[in] item
6700  *   Flow pattern to translate.
6701  * @param[in] inner
6702  *   Item is inner pattern.
6703  */
6704 static void
6705 flow_dv_translate_item_icmp6(void *matcher, void *key,
6706                               const struct rte_flow_item *item,
6707                               int inner)
6708 {
6709         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6710         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6711         void *headers_m;
6712         void *headers_v;
6713         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6714                                      misc_parameters_3);
6715         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6716         if (inner) {
6717                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6718                                          inner_headers);
6719                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6720         } else {
6721                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6722                                          outer_headers);
6723                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6724         }
6725         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6726         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6727         if (!icmp6_v)
6728                 return;
6729         if (!icmp6_m)
6730                 icmp6_m = &rte_flow_item_icmp6_mask;
6731         /*
6732          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
6733          * If only the protocol is specified, no need to match the frag.
6734          */
6735         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6736         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6737         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6738         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6739                  icmp6_v->type & icmp6_m->type);
6740         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6741         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6742                  icmp6_v->code & icmp6_m->code);
6743 }
6744
6745 /**
6746  * Add ICMP item to matcher and to the value.
6747  *
6748  * @param[in, out] matcher
6749  *   Flow matcher.
6750  * @param[in, out] key
6751  *   Flow matcher value.
6752  * @param[in] item
6753  *   Flow pattern to translate.
6754  * @param[in] inner
6755  *   Item is inner pattern.
6756  */
6757 static void
6758 flow_dv_translate_item_icmp(void *matcher, void *key,
6759                             const struct rte_flow_item *item,
6760                             int inner)
6761 {
6762         const struct rte_flow_item_icmp *icmp_m = item->mask;
6763         const struct rte_flow_item_icmp *icmp_v = item->spec;
6764         void *headers_m;
6765         void *headers_v;
6766         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6767                                      misc_parameters_3);
6768         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6769         if (inner) {
6770                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6771                                          inner_headers);
6772                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6773         } else {
6774                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6775                                          outer_headers);
6776                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6777         }
6778         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6779         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6780         if (!icmp_v)
6781                 return;
6782         if (!icmp_m)
6783                 icmp_m = &rte_flow_item_icmp_mask;
6784         /*
6785          * Force flow only to match the non-fragmented IPv4 ICMP packets.
6786          * If only the protocol is specified, no need to match the frag.
6787          */
6788         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
6789         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
6790         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6791                  icmp_m->hdr.icmp_type);
6792         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6793                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6794         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6795                  icmp_m->hdr.icmp_code);
6796         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6797                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6798 }
6799
6800 /**
6801  * Add GTP item to matcher and to the value.
6802  *
6803  * @param[in, out] matcher
6804  *   Flow matcher.
6805  * @param[in, out] key
6806  *   Flow matcher value.
6807  * @param[in] item
6808  *   Flow pattern to translate.
6809  * @param[in] inner
6810  *   Item is inner pattern.
6811  */
6812 static void
6813 flow_dv_translate_item_gtp(void *matcher, void *key,
6814                            const struct rte_flow_item *item, int inner)
6815 {
6816         const struct rte_flow_item_gtp *gtp_m = item->mask;
6817         const struct rte_flow_item_gtp *gtp_v = item->spec;
6818         void *headers_m;
6819         void *headers_v;
6820         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6821                                      misc_parameters_3);
6822         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6823         uint16_t dport = RTE_GTPU_UDP_PORT;
6824
6825         if (inner) {
6826                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6827                                          inner_headers);
6828                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6829         } else {
6830                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6831                                          outer_headers);
6832                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6833         }
6834         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6835                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6836                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6837         }
6838         if (!gtp_v)
6839                 return;
6840         if (!gtp_m)
6841                 gtp_m = &rte_flow_item_gtp_mask;
6842         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6843         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6844                  gtp_v->msg_type & gtp_m->msg_type);
6845         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6846                  rte_be_to_cpu_32(gtp_m->teid));
6847         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6848                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6849 }
6850
6851 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6852
6853 #define HEADER_IS_ZERO(match_criteria, headers)                              \
6854         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
6855                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6856
6857 /**
6858  * Calculate flow matcher enable bitmap.
6859  *
6860  * @param match_criteria
6861  *   Pointer to flow matcher criteria.
6862  *
6863  * @return
6864  *   Bitmap of enabled fields.
6865  */
6866 static uint8_t
6867 flow_dv_matcher_enable(uint32_t *match_criteria)
6868 {
6869         uint8_t match_criteria_enable;
6870
6871         match_criteria_enable =
6872                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6873                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6874         match_criteria_enable |=
6875                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6876                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6877         match_criteria_enable |=
6878                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6879                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6880         match_criteria_enable |=
6881                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6882                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6883         match_criteria_enable |=
6884                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6885                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6886         return match_criteria_enable;
6887 }
6888
6889
6890 /**
6891  * Get a flow table.
6892  *
6893  * @param[in, out] dev
6894  *   Pointer to rte_eth_dev structure.
6895  * @param[in] table_id
6896  *   Table id to use.
6897  * @param[in] egress
6898  *   Direction of the table.
6899  * @param[in] transfer
6900  *   E-Switch or NIC flow.
6901  * @param[out] error
6902  *   pointer to error structure.
6903  *
6904  * @return
6905  *   Returns tables resource based on the index, NULL in case of failed.
6906  */
6907 static struct mlx5_flow_tbl_resource *
6908 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6909                          uint32_t table_id, uint8_t egress,
6910                          uint8_t transfer,
6911                          struct rte_flow_error *error)
6912 {
6913         struct mlx5_priv *priv = dev->data->dev_private;
6914         struct mlx5_ibv_shared *sh = priv->sh;
6915         struct mlx5_flow_tbl_resource *tbl;
6916         union mlx5_flow_tbl_key table_key = {
6917                 {
6918                         .table_id = table_id,
6919                         .reserved = 0,
6920                         .domain = !!transfer,
6921                         .direction = !!egress,
6922                 }
6923         };
6924         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6925                                                          table_key.v64);
6926         struct mlx5_flow_tbl_data_entry *tbl_data;
6927         int ret;
6928         void *domain;
6929
6930         if (pos) {
6931                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6932                                         entry);
6933                 tbl = &tbl_data->tbl;
6934                 rte_atomic32_inc(&tbl->refcnt);
6935                 return tbl;
6936         }
6937         tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6938         if (!tbl_data) {
6939                 rte_flow_error_set(error, ENOMEM,
6940                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6941                                    NULL,
6942                                    "cannot allocate flow table data entry");
6943                 return NULL;
6944         }
6945         tbl = &tbl_data->tbl;
6946         pos = &tbl_data->entry;
6947         if (transfer)
6948                 domain = sh->fdb_domain;
6949         else if (egress)
6950                 domain = sh->tx_domain;
6951         else
6952                 domain = sh->rx_domain;
6953         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6954         if (!tbl->obj) {
6955                 rte_flow_error_set(error, ENOMEM,
6956                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6957                                    NULL, "cannot create flow table object");
6958                 rte_free(tbl_data);
6959                 return NULL;
6960         }
6961         /*
6962          * No multi-threads now, but still better to initialize the reference
6963          * count before insert it into the hash list.
6964          */
6965         rte_atomic32_init(&tbl->refcnt);
6966         /* Jump action reference count is initialized here. */
6967         rte_atomic32_init(&tbl_data->jump.refcnt);
6968         pos->key = table_key.v64;
6969         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6970         if (ret < 0) {
6971                 rte_flow_error_set(error, -ret,
6972                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6973                                    "cannot insert flow table data entry");
6974                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6975                 rte_free(tbl_data);
6976         }
6977         rte_atomic32_inc(&tbl->refcnt);
6978         return tbl;
6979 }
6980
6981 /**
6982  * Release a flow table.
6983  *
6984  * @param[in] dev
6985  *   Pointer to rte_eth_dev structure.
6986  * @param[in] tbl
6987  *   Table resource to be released.
6988  *
6989  * @return
6990  *   Returns 0 if table was released, else return 1;
6991  */
6992 static int
6993 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6994                              struct mlx5_flow_tbl_resource *tbl)
6995 {
6996         struct mlx5_priv *priv = dev->data->dev_private;
6997         struct mlx5_ibv_shared *sh = priv->sh;
6998         struct mlx5_flow_tbl_data_entry *tbl_data =
6999                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7000
7001         if (!tbl)
7002                 return 0;
7003         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7004                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7005
7006                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7007                 tbl->obj = NULL;
7008                 /* remove the entry from the hash list and free memory. */
7009                 mlx5_hlist_remove(sh->flow_tbls, pos);
7010                 rte_free(tbl_data);
7011                 return 0;
7012         }
7013         return 1;
7014 }
7015
7016 /**
7017  * Register the flow matcher.
7018  *
7019  * @param[in, out] dev
7020  *   Pointer to rte_eth_dev structure.
7021  * @param[in, out] matcher
7022  *   Pointer to flow matcher.
7023  * @param[in, out] key
7024  *   Pointer to flow table key.
7025  * @parm[in, out] dev_flow
7026  *   Pointer to the dev_flow.
7027  * @param[out] error
7028  *   pointer to error structure.
7029  *
7030  * @return
7031  *   0 on success otherwise -errno and errno is set.
7032  */
7033 static int
7034 flow_dv_matcher_register(struct rte_eth_dev *dev,
7035                          struct mlx5_flow_dv_matcher *matcher,
7036                          union mlx5_flow_tbl_key *key,
7037                          struct mlx5_flow *dev_flow,
7038                          struct rte_flow_error *error)
7039 {
7040         struct mlx5_priv *priv = dev->data->dev_private;
7041         struct mlx5_ibv_shared *sh = priv->sh;
7042         struct mlx5_flow_dv_matcher *cache_matcher;
7043         struct mlx5dv_flow_matcher_attr dv_attr = {
7044                 .type = IBV_FLOW_ATTR_NORMAL,
7045                 .match_mask = (void *)&matcher->mask,
7046         };
7047         struct mlx5_flow_tbl_resource *tbl;
7048         struct mlx5_flow_tbl_data_entry *tbl_data;
7049
7050         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7051                                        key->domain, error);
7052         if (!tbl)
7053                 return -rte_errno;      /* No need to refill the error info */
7054         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7055         /* Lookup from cache. */
7056         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7057                 if (matcher->crc == cache_matcher->crc &&
7058                     matcher->priority == cache_matcher->priority &&
7059                     !memcmp((const void *)matcher->mask.buf,
7060                             (const void *)cache_matcher->mask.buf,
7061                             cache_matcher->mask.size)) {
7062                         DRV_LOG(DEBUG,
7063                                 "%s group %u priority %hd use %s "
7064                                 "matcher %p: refcnt %d++",
7065                                 key->domain ? "FDB" : "NIC", key->table_id,
7066                                 cache_matcher->priority,
7067                                 key->direction ? "tx" : "rx",
7068                                 (void *)cache_matcher,
7069                                 rte_atomic32_read(&cache_matcher->refcnt));
7070                         rte_atomic32_inc(&cache_matcher->refcnt);
7071                         dev_flow->handle->dvh.matcher = cache_matcher;
7072                         /* old matcher should not make the table ref++. */
7073                         flow_dv_tbl_resource_release(dev, tbl);
7074                         return 0;
7075                 }
7076         }
7077         /* Register new matcher. */
7078         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7079         if (!cache_matcher) {
7080                 flow_dv_tbl_resource_release(dev, tbl);
7081                 return rte_flow_error_set(error, ENOMEM,
7082                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7083                                           "cannot allocate matcher memory");
7084         }
7085         *cache_matcher = *matcher;
7086         dv_attr.match_criteria_enable =
7087                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7088         dv_attr.priority = matcher->priority;
7089         if (key->direction)
7090                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7091         cache_matcher->matcher_object =
7092                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7093         if (!cache_matcher->matcher_object) {
7094                 rte_free(cache_matcher);
7095 #ifdef HAVE_MLX5DV_DR
7096                 flow_dv_tbl_resource_release(dev, tbl);
7097 #endif
7098                 return rte_flow_error_set(error, ENOMEM,
7099                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7100                                           NULL, "cannot create matcher");
7101         }
7102         /* Save the table information */
7103         cache_matcher->tbl = tbl;
7104         rte_atomic32_init(&cache_matcher->refcnt);
7105         /* only matcher ref++, table ref++ already done above in get API. */
7106         rte_atomic32_inc(&cache_matcher->refcnt);
7107         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7108         dev_flow->handle->dvh.matcher = cache_matcher;
7109         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7110                 key->domain ? "FDB" : "NIC", key->table_id,
7111                 cache_matcher->priority,
7112                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7113                 rte_atomic32_read(&cache_matcher->refcnt));
7114         return 0;
7115 }
7116
7117 /**
7118  * Find existing tag resource or create and register a new one.
7119  *
7120  * @param dev[in, out]
7121  *   Pointer to rte_eth_dev structure.
7122  * @param[in, out] tag_be24
7123  *   Tag value in big endian then R-shift 8.
7124  * @parm[in, out] dev_flow
7125  *   Pointer to the dev_flow.
7126  * @param[out] error
7127  *   pointer to error structure.
7128  *
7129  * @return
7130  *   0 on success otherwise -errno and errno is set.
7131  */
7132 static int
7133 flow_dv_tag_resource_register
7134                         (struct rte_eth_dev *dev,
7135                          uint32_t tag_be24,
7136                          struct mlx5_flow *dev_flow,
7137                          struct rte_flow_error *error)
7138 {
7139         struct mlx5_priv *priv = dev->data->dev_private;
7140         struct mlx5_ibv_shared *sh = priv->sh;
7141         struct mlx5_flow_dv_tag_resource *cache_resource;
7142         struct mlx5_hlist_entry *entry;
7143
7144         /* Lookup a matching resource from cache. */
7145         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7146         if (entry) {
7147                 cache_resource = container_of
7148                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7149                 rte_atomic32_inc(&cache_resource->refcnt);
7150                 dev_flow->handle->dvh.tag_resource = cache_resource;
7151                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7152                         (void *)cache_resource,
7153                         rte_atomic32_read(&cache_resource->refcnt));
7154                 return 0;
7155         }
7156         /* Register new resource. */
7157         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
7158         if (!cache_resource)
7159                 return rte_flow_error_set(error, ENOMEM,
7160                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7161                                           "cannot allocate resource memory");
7162         cache_resource->entry.key = (uint64_t)tag_be24;
7163         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7164         if (!cache_resource->action) {
7165                 rte_free(cache_resource);
7166                 return rte_flow_error_set(error, ENOMEM,
7167                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7168                                           NULL, "cannot create action");
7169         }
7170         rte_atomic32_init(&cache_resource->refcnt);
7171         rte_atomic32_inc(&cache_resource->refcnt);
7172         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7173                 mlx5_glue->destroy_flow_action(cache_resource->action);
7174                 rte_free(cache_resource);
7175                 return rte_flow_error_set(error, EEXIST,
7176                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7177                                           NULL, "cannot insert tag");
7178         }
7179         dev_flow->handle->dvh.tag_resource = cache_resource;
7180         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7181                 (void *)cache_resource,
7182                 rte_atomic32_read(&cache_resource->refcnt));
7183         return 0;
7184 }
7185
7186 /**
7187  * Release the tag.
7188  *
7189  * @param dev
7190  *   Pointer to Ethernet device.
7191  * @param flow
7192  *   Pointer to mlx5_flow.
7193  *
7194  * @return
7195  *   1 while a reference on it exists, 0 when freed.
7196  */
7197 static int
7198 flow_dv_tag_release(struct rte_eth_dev *dev,
7199                     struct mlx5_flow_dv_tag_resource *tag)
7200 {
7201         struct mlx5_priv *priv = dev->data->dev_private;
7202         struct mlx5_ibv_shared *sh = priv->sh;
7203
7204         MLX5_ASSERT(tag);
7205         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7206                 dev->data->port_id, (void *)tag,
7207                 rte_atomic32_read(&tag->refcnt));
7208         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7209                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7210                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7211                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7212                         dev->data->port_id, (void *)tag);
7213                 rte_free(tag);
7214                 return 0;
7215         }
7216         return 1;
7217 }
7218
7219 /**
7220  * Translate port ID action to vport.
7221  *
7222  * @param[in] dev
7223  *   Pointer to rte_eth_dev structure.
7224  * @param[in] action
7225  *   Pointer to the port ID action.
7226  * @param[out] dst_port_id
7227  *   The target port ID.
7228  * @param[out] error
7229  *   Pointer to the error structure.
7230  *
7231  * @return
7232  *   0 on success, a negative errno value otherwise and rte_errno is set.
7233  */
7234 static int
7235 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7236                                  const struct rte_flow_action *action,
7237                                  uint32_t *dst_port_id,
7238                                  struct rte_flow_error *error)
7239 {
7240         uint32_t port;
7241         struct mlx5_priv *priv;
7242         const struct rte_flow_action_port_id *conf =
7243                         (const struct rte_flow_action_port_id *)action->conf;
7244
7245         port = conf->original ? dev->data->port_id : conf->id;
7246         priv = mlx5_port_to_eswitch_info(port, false);
7247         if (!priv)
7248                 return rte_flow_error_set(error, -rte_errno,
7249                                           RTE_FLOW_ERROR_TYPE_ACTION,
7250                                           NULL,
7251                                           "No eswitch info was found for port");
7252 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7253         /*
7254          * This parameter is transferred to
7255          * mlx5dv_dr_action_create_dest_ib_port().
7256          */
7257         *dst_port_id = priv->ibv_port;
7258 #else
7259         /*
7260          * Legacy mode, no LAG configurations is supported.
7261          * This parameter is transferred to
7262          * mlx5dv_dr_action_create_dest_vport().
7263          */
7264         *dst_port_id = priv->vport_id;
7265 #endif
7266         return 0;
7267 }
7268
7269 /**
7270  * Add Tx queue matcher
7271  *
7272  * @param[in] dev
7273  *   Pointer to the dev struct.
7274  * @param[in, out] matcher
7275  *   Flow matcher.
7276  * @param[in, out] key
7277  *   Flow matcher value.
7278  * @param[in] item
7279  *   Flow pattern to translate.
7280  * @param[in] inner
7281  *   Item is inner pattern.
7282  */
7283 static void
7284 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7285                                 void *matcher, void *key,
7286                                 const struct rte_flow_item *item)
7287 {
7288         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7289         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7290         void *misc_m =
7291                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7292         void *misc_v =
7293                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7294         struct mlx5_txq_ctrl *txq;
7295         uint32_t queue;
7296
7297
7298         queue_m = (const void *)item->mask;
7299         if (!queue_m)
7300                 return;
7301         queue_v = (const void *)item->spec;
7302         if (!queue_v)
7303                 return;
7304         txq = mlx5_txq_get(dev, queue_v->queue);
7305         if (!txq)
7306                 return;
7307         queue = txq->obj->sq->id;
7308         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7309         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7310                  queue & queue_m->queue);
7311         mlx5_txq_release(dev, queue_v->queue);
7312 }
7313
7314 /**
7315  * Set the hash fields according to the @p flow information.
7316  *
7317  * @param[in] dev_flow
7318  *   Pointer to the mlx5_flow.
7319  */
7320 static void
7321 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
7322 {
7323         struct rte_flow *flow = dev_flow->flow;
7324         uint64_t items = dev_flow->handle->layers;
7325         int rss_inner = 0;
7326         uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
7327
7328         dev_flow->hash_fields = 0;
7329 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7330         if (flow->rss.level >= 2) {
7331                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7332                 rss_inner = 1;
7333         }
7334 #endif
7335         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7336             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7337                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7338                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7339                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7340                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7341                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7342                         else
7343                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7344                 }
7345         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7346                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7347                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7348                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7349                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7350                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7351                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7352                         else
7353                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7354                 }
7355         }
7356         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7357             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7358                 if (rss_types & ETH_RSS_UDP) {
7359                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7360                                 dev_flow->hash_fields |=
7361                                                 IBV_RX_HASH_SRC_PORT_UDP;
7362                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7363                                 dev_flow->hash_fields |=
7364                                                 IBV_RX_HASH_DST_PORT_UDP;
7365                         else
7366                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7367                 }
7368         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7369                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7370                 if (rss_types & ETH_RSS_TCP) {
7371                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7372                                 dev_flow->hash_fields |=
7373                                                 IBV_RX_HASH_SRC_PORT_TCP;
7374                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7375                                 dev_flow->hash_fields |=
7376                                                 IBV_RX_HASH_DST_PORT_TCP;
7377                         else
7378                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7379                 }
7380         }
7381 }
7382
7383 /**
7384  * Fill the flow with DV spec, lock free
7385  * (mutex should be acquired by caller).
7386  *
7387  * @param[in] dev
7388  *   Pointer to rte_eth_dev structure.
7389  * @param[in, out] dev_flow
7390  *   Pointer to the sub flow.
7391  * @param[in] attr
7392  *   Pointer to the flow attributes.
7393  * @param[in] items
7394  *   Pointer to the list of items.
7395  * @param[in] actions
7396  *   Pointer to the list of actions.
7397  * @param[out] error
7398  *   Pointer to the error structure.
7399  *
7400  * @return
7401  *   0 on success, a negative errno value otherwise and rte_errno is set.
7402  */
7403 static int
7404 __flow_dv_translate(struct rte_eth_dev *dev,
7405                     struct mlx5_flow *dev_flow,
7406                     const struct rte_flow_attr *attr,
7407                     const struct rte_flow_item items[],
7408                     const struct rte_flow_action actions[],
7409                     struct rte_flow_error *error)
7410 {
7411         struct mlx5_priv *priv = dev->data->dev_private;
7412         struct mlx5_dev_config *dev_conf = &priv->config;
7413         struct rte_flow *flow = dev_flow->flow;
7414         struct mlx5_flow_handle *handle = dev_flow->handle;
7415         uint64_t item_flags = 0;
7416         uint64_t last_item = 0;
7417         uint64_t action_flags = 0;
7418         uint64_t priority = attr->priority;
7419         struct mlx5_flow_dv_matcher matcher = {
7420                 .mask = {
7421                         .size = sizeof(matcher.mask.buf),
7422                 },
7423         };
7424         int actions_n = 0;
7425         bool actions_end = false;
7426         union {
7427                 struct mlx5_flow_dv_modify_hdr_resource res;
7428                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7429                             sizeof(struct mlx5_modification_cmd) *
7430                             (MLX5_MAX_MODIFY_NUM + 1)];
7431         } mhdr_dummy;
7432         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7433         union flow_dv_attr flow_attr = { .attr = 0 };
7434         uint32_t tag_be;
7435         union mlx5_flow_tbl_key tbl_key;
7436         uint32_t modify_action_position = UINT32_MAX;
7437         void *match_mask = matcher.mask.buf;
7438         void *match_value = dev_flow->dv.value.buf;
7439         uint8_t next_protocol = 0xff;
7440         struct rte_vlan_hdr vlan = { 0 };
7441         uint32_t table;
7442         int ret = 0;
7443
7444         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7445                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7446         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7447                                        !!priv->fdb_def_rule, &table, error);
7448         if (ret)
7449                 return ret;
7450         dev_flow->dv.group = table;
7451         if (attr->transfer)
7452                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7453         if (priority == MLX5_FLOW_PRIO_RSVD)
7454                 priority = dev_conf->flow_prio - 1;
7455         /* number of actions must be set to 0 in case of dirty stack. */
7456         mhdr_res->actions_num = 0;
7457         for (; !actions_end ; actions++) {
7458                 const struct rte_flow_action_queue *queue;
7459                 const struct rte_flow_action_rss *rss;
7460                 const struct rte_flow_action *action = actions;
7461                 const struct rte_flow_action_count *count = action->conf;
7462                 const uint8_t *rss_key;
7463                 const struct rte_flow_action_jump *jump_data;
7464                 const struct rte_flow_action_meter *mtr;
7465                 struct mlx5_flow_tbl_resource *tbl;
7466                 uint32_t port_id = 0;
7467                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7468                 int action_type = actions->type;
7469                 const struct rte_flow_action *found_action = NULL;
7470
7471                 switch (action_type) {
7472                 case RTE_FLOW_ACTION_TYPE_VOID:
7473                         break;
7474                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7475                         if (flow_dv_translate_action_port_id(dev, action,
7476                                                              &port_id, error))
7477                                 return -rte_errno;
7478                         port_id_resource.port_id = port_id;
7479                         if (flow_dv_port_id_action_resource_register
7480                             (dev, &port_id_resource, dev_flow, error))
7481                                 return -rte_errno;
7482                         dev_flow->dv.actions[actions_n++] =
7483                                         handle->dvh.port_id_action->action;
7484                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7485                         break;
7486                 case RTE_FLOW_ACTION_TYPE_FLAG:
7487                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7488                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7489                                 struct rte_flow_action_mark mark = {
7490                                         .id = MLX5_FLOW_MARK_DEFAULT,
7491                                 };
7492
7493                                 if (flow_dv_convert_action_mark(dev, &mark,
7494                                                                 mhdr_res,
7495                                                                 error))
7496                                         return -rte_errno;
7497                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7498                                 break;
7499                         }
7500                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7501                         /*
7502                          * Only one FLAG or MARK is supported per device flow
7503                          * right now. So the pointer to the tag resource must be
7504                          * zero before the register process.
7505                          */
7506                         MLX5_ASSERT(!handle->dvh.tag_resource);
7507                         if (flow_dv_tag_resource_register(dev, tag_be,
7508                                                           dev_flow, error))
7509                                 return -rte_errno;
7510                         dev_flow->dv.actions[actions_n++] =
7511                                         handle->dvh.tag_resource->action;
7512                         break;
7513                 case RTE_FLOW_ACTION_TYPE_MARK:
7514                         action_flags |= MLX5_FLOW_ACTION_MARK;
7515                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7516                                 const struct rte_flow_action_mark *mark =
7517                                         (const struct rte_flow_action_mark *)
7518                                                 actions->conf;
7519
7520                                 if (flow_dv_convert_action_mark(dev, mark,
7521                                                                 mhdr_res,
7522                                                                 error))
7523                                         return -rte_errno;
7524                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7525                                 break;
7526                         }
7527                         /* Fall-through */
7528                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7529                         /* Legacy (non-extensive) MARK action. */
7530                         tag_be = mlx5_flow_mark_set
7531                               (((const struct rte_flow_action_mark *)
7532                                (actions->conf))->id);
7533                         MLX5_ASSERT(!handle->dvh.tag_resource);
7534                         if (flow_dv_tag_resource_register(dev, tag_be,
7535                                                           dev_flow, error))
7536                                 return -rte_errno;
7537                         dev_flow->dv.actions[actions_n++] =
7538                                         handle->dvh.tag_resource->action;
7539                         break;
7540                 case RTE_FLOW_ACTION_TYPE_SET_META:
7541                         if (flow_dv_convert_action_set_meta
7542                                 (dev, mhdr_res, attr,
7543                                  (const struct rte_flow_action_set_meta *)
7544                                   actions->conf, error))
7545                                 return -rte_errno;
7546                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7547                         break;
7548                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7549                         if (flow_dv_convert_action_set_tag
7550                                 (dev, mhdr_res,
7551                                  (const struct rte_flow_action_set_tag *)
7552                                   actions->conf, error))
7553                                 return -rte_errno;
7554                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7555                         break;
7556                 case RTE_FLOW_ACTION_TYPE_DROP:
7557                         action_flags |= MLX5_FLOW_ACTION_DROP;
7558                         break;
7559                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7560                         MLX5_ASSERT(flow->rss.queue);
7561                         queue = actions->conf;
7562                         flow->rss.queue_num = 1;
7563                         (*flow->rss.queue)[0] = queue->index;
7564                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7565                         break;
7566                 case RTE_FLOW_ACTION_TYPE_RSS:
7567                         MLX5_ASSERT(flow->rss.queue);
7568                         rss = actions->conf;
7569                         if (flow->rss.queue)
7570                                 memcpy((*flow->rss.queue), rss->queue,
7571                                        rss->queue_num * sizeof(uint16_t));
7572                         flow->rss.queue_num = rss->queue_num;
7573                         /* NULL RSS key indicates default RSS key. */
7574                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7575                         memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7576                         /*
7577                          * rss->level and rss.types should be set in advance
7578                          * when expanding items for RSS.
7579                          */
7580                         action_flags |= MLX5_FLOW_ACTION_RSS;
7581                         break;
7582                 case RTE_FLOW_ACTION_TYPE_COUNT:
7583                         if (!dev_conf->devx) {
7584                                 rte_errno = ENOTSUP;
7585                                 goto cnt_err;
7586                         }
7587                         flow->counter = flow_dv_counter_alloc(dev,
7588                                                         count->shared,
7589                                                         count->id,
7590                                                         dev_flow->dv.group);
7591                         if (flow->counter == NULL)
7592                                 goto cnt_err;
7593                         dev_flow->dv.actions[actions_n++] =
7594                                   (flow_dv_counter_get_by_idx(dev,
7595                                   (uintptr_t)flow->counter, NULL))->action;
7596                         action_flags |= MLX5_FLOW_ACTION_COUNT;
7597                         break;
7598 cnt_err:
7599                         if (rte_errno == ENOTSUP)
7600                                 return rte_flow_error_set
7601                                               (error, ENOTSUP,
7602                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7603                                                NULL,
7604                                                "count action not supported");
7605                         else
7606                                 return rte_flow_error_set
7607                                                 (error, rte_errno,
7608                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7609                                                  action,
7610                                                  "cannot create counter"
7611                                                   " object.");
7612                         break;
7613                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7614                         dev_flow->dv.actions[actions_n++] =
7615                                                 priv->sh->pop_vlan_action;
7616                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7617                         break;
7618                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7619                         flow_dev_get_vlan_info_from_items(items, &vlan);
7620                         vlan.eth_proto = rte_be_to_cpu_16
7621                              ((((const struct rte_flow_action_of_push_vlan *)
7622                                                    actions->conf)->ethertype));
7623                         found_action = mlx5_flow_find_action
7624                                         (actions + 1,
7625                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7626                         if (found_action)
7627                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7628                         found_action = mlx5_flow_find_action
7629                                         (actions + 1,
7630                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7631                         if (found_action)
7632                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7633                         if (flow_dv_create_action_push_vlan
7634                                             (dev, attr, &vlan, dev_flow, error))
7635                                 return -rte_errno;
7636                         dev_flow->dv.actions[actions_n++] =
7637                                         handle->dvh.push_vlan_res->action;
7638                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7639                         break;
7640                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7641                         /* of_vlan_push action handled this action */
7642                         MLX5_ASSERT(action_flags &
7643                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7644                         break;
7645                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7646                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7647                                 break;
7648                         flow_dev_get_vlan_info_from_items(items, &vlan);
7649                         mlx5_update_vlan_vid_pcp(actions, &vlan);
7650                         /* If no VLAN push - this is a modify header action */
7651                         if (flow_dv_convert_action_modify_vlan_vid
7652                                                 (mhdr_res, actions, error))
7653                                 return -rte_errno;
7654                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7655                         break;
7656                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7657                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7658                         if (flow_dv_create_action_l2_encap(dev, actions,
7659                                                            dev_flow,
7660                                                            attr->transfer,
7661                                                            error))
7662                                 return -rte_errno;
7663                         dev_flow->dv.actions[actions_n++] =
7664                                         handle->dvh.encap_decap->verbs_action;
7665                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7666                         break;
7667                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7668                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7669                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
7670                                                            attr->transfer,
7671                                                            error))
7672                                 return -rte_errno;
7673                         dev_flow->dv.actions[actions_n++] =
7674                                         handle->dvh.encap_decap->verbs_action;
7675                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7676                         break;
7677                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7678                         /* Handle encap with preceding decap. */
7679                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
7680                                 if (flow_dv_create_action_raw_encap
7681                                         (dev, actions, dev_flow, attr, error))
7682                                         return -rte_errno;
7683                                 dev_flow->dv.actions[actions_n++] =
7684                                         handle->dvh.encap_decap->verbs_action;
7685                         } else {
7686                                 /* Handle encap without preceding decap. */
7687                                 if (flow_dv_create_action_l2_encap
7688                                     (dev, actions, dev_flow, attr->transfer,
7689                                      error))
7690                                         return -rte_errno;
7691                                 dev_flow->dv.actions[actions_n++] =
7692                                         handle->dvh.encap_decap->verbs_action;
7693                         }
7694                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
7695                         break;
7696                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7697                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
7698                                 ;
7699                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7700                                 if (flow_dv_create_action_l2_decap
7701                                     (dev, dev_flow, attr->transfer, error))
7702                                         return -rte_errno;
7703                                 dev_flow->dv.actions[actions_n++] =
7704                                         handle->dvh.encap_decap->verbs_action;
7705                         }
7706                         /* If decap is followed by encap, handle it at encap. */
7707                         action_flags |= MLX5_FLOW_ACTION_DECAP;
7708                         break;
7709                 case RTE_FLOW_ACTION_TYPE_JUMP:
7710                         jump_data = action->conf;
7711                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7712                                                        jump_data->group,
7713                                                        !!priv->fdb_def_rule,
7714                                                        &table, error);
7715                         if (ret)
7716                                 return ret;
7717                         tbl = flow_dv_tbl_resource_get(dev, table,
7718                                                        attr->egress,
7719                                                        attr->transfer, error);
7720                         if (!tbl)
7721                                 return rte_flow_error_set
7722                                                 (error, errno,
7723                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7724                                                  NULL,
7725                                                  "cannot create jump action.");
7726                         if (flow_dv_jump_tbl_resource_register
7727                             (dev, tbl, dev_flow, error)) {
7728                                 flow_dv_tbl_resource_release(dev, tbl);
7729                                 return rte_flow_error_set
7730                                                 (error, errno,
7731                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7732                                                  NULL,
7733                                                  "cannot create jump action.");
7734                         }
7735                         dev_flow->dv.actions[actions_n++] =
7736                                         handle->dvh.jump->action;
7737                         action_flags |= MLX5_FLOW_ACTION_JUMP;
7738                         break;
7739                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7740                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7741                         if (flow_dv_convert_action_modify_mac
7742                                         (mhdr_res, actions, error))
7743                                 return -rte_errno;
7744                         action_flags |= actions->type ==
7745                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7746                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
7747                                         MLX5_FLOW_ACTION_SET_MAC_DST;
7748                         break;
7749                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7750                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7751                         if (flow_dv_convert_action_modify_ipv4
7752                                         (mhdr_res, actions, error))
7753                                 return -rte_errno;
7754                         action_flags |= actions->type ==
7755                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7756                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
7757                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
7758                         break;
7759                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7760                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7761                         if (flow_dv_convert_action_modify_ipv6
7762                                         (mhdr_res, actions, error))
7763                                 return -rte_errno;
7764                         action_flags |= actions->type ==
7765                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7766                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
7767                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
7768                         break;
7769                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7770                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7771                         if (flow_dv_convert_action_modify_tp
7772                                         (mhdr_res, actions, items,
7773                                          &flow_attr, dev_flow, !!(action_flags &
7774                                          MLX5_FLOW_ACTION_DECAP), error))
7775                                 return -rte_errno;
7776                         action_flags |= actions->type ==
7777                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7778                                         MLX5_FLOW_ACTION_SET_TP_SRC :
7779                                         MLX5_FLOW_ACTION_SET_TP_DST;
7780                         break;
7781                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7782                         if (flow_dv_convert_action_modify_dec_ttl
7783                                         (mhdr_res, items, &flow_attr, dev_flow,
7784                                          !!(action_flags &
7785                                          MLX5_FLOW_ACTION_DECAP), error))
7786                                 return -rte_errno;
7787                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7788                         break;
7789                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7790                         if (flow_dv_convert_action_modify_ttl
7791                                         (mhdr_res, actions, items, &flow_attr,
7792                                          dev_flow, !!(action_flags &
7793                                          MLX5_FLOW_ACTION_DECAP), error))
7794                                 return -rte_errno;
7795                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7796                         break;
7797                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7798                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7799                         if (flow_dv_convert_action_modify_tcp_seq
7800                                         (mhdr_res, actions, error))
7801                                 return -rte_errno;
7802                         action_flags |= actions->type ==
7803                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7804                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
7805                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7806                         break;
7807
7808                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7809                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7810                         if (flow_dv_convert_action_modify_tcp_ack
7811                                         (mhdr_res, actions, error))
7812                                 return -rte_errno;
7813                         action_flags |= actions->type ==
7814                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7815                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
7816                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
7817                         break;
7818                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7819                         if (flow_dv_convert_action_set_reg
7820                                         (mhdr_res, actions, error))
7821                                 return -rte_errno;
7822                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7823                         break;
7824                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7825                         if (flow_dv_convert_action_copy_mreg
7826                                         (dev, mhdr_res, actions, error))
7827                                 return -rte_errno;
7828                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7829                         break;
7830                 case RTE_FLOW_ACTION_TYPE_METER:
7831                         mtr = actions->conf;
7832                         if (!flow->meter) {
7833                                 flow->meter = mlx5_flow_meter_attach(priv,
7834                                                         mtr->mtr_id, attr,
7835                                                         error);
7836                                 if (!flow->meter)
7837                                         return rte_flow_error_set(error,
7838                                                 rte_errno,
7839                                                 RTE_FLOW_ERROR_TYPE_ACTION,
7840                                                 NULL,
7841                                                 "meter not found "
7842                                                 "or invalid parameters");
7843                         }
7844                         /* Set the meter action. */
7845                         dev_flow->dv.actions[actions_n++] =
7846                                 flow->meter->mfts->meter_action;
7847                         action_flags |= MLX5_FLOW_ACTION_METER;
7848                         break;
7849                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7850                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7851                                                               actions, error))
7852                                 return -rte_errno;
7853                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7854                         break;
7855                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7856                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7857                                                               actions, error))
7858                                 return -rte_errno;
7859                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7860                         break;
7861                 case RTE_FLOW_ACTION_TYPE_END:
7862                         actions_end = true;
7863                         if (mhdr_res->actions_num) {
7864                                 /* create modify action if needed. */
7865                                 if (flow_dv_modify_hdr_resource_register
7866                                         (dev, mhdr_res, dev_flow, error))
7867                                         return -rte_errno;
7868                                 dev_flow->dv.actions[modify_action_position] =
7869                                         handle->dvh.modify_hdr->verbs_action;
7870                         }
7871                         break;
7872                 default:
7873                         break;
7874                 }
7875                 if (mhdr_res->actions_num &&
7876                     modify_action_position == UINT32_MAX)
7877                         modify_action_position = actions_n++;
7878         }
7879         dev_flow->dv.actions_n = actions_n;
7880         handle->act_flags = action_flags;
7881         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7882                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7883                 int item_type = items->type;
7884
7885                 switch (item_type) {
7886                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7887                         flow_dv_translate_item_port_id(dev, match_mask,
7888                                                        match_value, items);
7889                         last_item = MLX5_FLOW_ITEM_PORT_ID;
7890                         break;
7891                 case RTE_FLOW_ITEM_TYPE_ETH:
7892                         flow_dv_translate_item_eth(match_mask, match_value,
7893                                                    items, tunnel);
7894                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7895                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7896                                              MLX5_FLOW_LAYER_OUTER_L2;
7897                         break;
7898                 case RTE_FLOW_ITEM_TYPE_VLAN:
7899                         flow_dv_translate_item_vlan(dev_flow,
7900                                                     match_mask, match_value,
7901                                                     items, tunnel);
7902                         matcher.priority = MLX5_PRIORITY_MAP_L2;
7903                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7904                                               MLX5_FLOW_LAYER_INNER_VLAN) :
7905                                              (MLX5_FLOW_LAYER_OUTER_L2 |
7906                                               MLX5_FLOW_LAYER_OUTER_VLAN);
7907                         break;
7908                 case RTE_FLOW_ITEM_TYPE_IPV4:
7909                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7910                                                   &item_flags, &tunnel);
7911                         flow_dv_translate_item_ipv4(match_mask, match_value,
7912                                                     items, item_flags, tunnel,
7913                                                     dev_flow->dv.group);
7914                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7915                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7916                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7917                         if (items->mask != NULL &&
7918                             ((const struct rte_flow_item_ipv4 *)
7919                              items->mask)->hdr.next_proto_id) {
7920                                 next_protocol =
7921                                         ((const struct rte_flow_item_ipv4 *)
7922                                          (items->spec))->hdr.next_proto_id;
7923                                 next_protocol &=
7924                                         ((const struct rte_flow_item_ipv4 *)
7925                                          (items->mask))->hdr.next_proto_id;
7926                         } else {
7927                                 /* Reset for inner layer. */
7928                                 next_protocol = 0xff;
7929                         }
7930                         break;
7931                 case RTE_FLOW_ITEM_TYPE_IPV6:
7932                         mlx5_flow_tunnel_ip_check(items, next_protocol,
7933                                                   &item_flags, &tunnel);
7934                         flow_dv_translate_item_ipv6(match_mask, match_value,
7935                                                     items, item_flags, tunnel,
7936                                                     dev_flow->dv.group);
7937                         matcher.priority = MLX5_PRIORITY_MAP_L3;
7938                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7939                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7940                         if (items->mask != NULL &&
7941                             ((const struct rte_flow_item_ipv6 *)
7942                              items->mask)->hdr.proto) {
7943                                 next_protocol =
7944                                         ((const struct rte_flow_item_ipv6 *)
7945                                          items->spec)->hdr.proto;
7946                                 next_protocol &=
7947                                         ((const struct rte_flow_item_ipv6 *)
7948                                          items->mask)->hdr.proto;
7949                         } else {
7950                                 /* Reset for inner layer. */
7951                                 next_protocol = 0xff;
7952                         }
7953                         break;
7954                 case RTE_FLOW_ITEM_TYPE_TCP:
7955                         flow_dv_translate_item_tcp(match_mask, match_value,
7956                                                    items, tunnel);
7957                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7958                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7959                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
7960                         break;
7961                 case RTE_FLOW_ITEM_TYPE_UDP:
7962                         flow_dv_translate_item_udp(match_mask, match_value,
7963                                                    items, tunnel);
7964                         matcher.priority = MLX5_PRIORITY_MAP_L4;
7965                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7966                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
7967                         break;
7968                 case RTE_FLOW_ITEM_TYPE_GRE:
7969                         flow_dv_translate_item_gre(match_mask, match_value,
7970                                                    items, tunnel);
7971                         matcher.priority = flow->rss.level >= 2 ?
7972                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7973                         last_item = MLX5_FLOW_LAYER_GRE;
7974                         break;
7975                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7976                         flow_dv_translate_item_gre_key(match_mask,
7977                                                        match_value, items);
7978                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
7979                         break;
7980                 case RTE_FLOW_ITEM_TYPE_NVGRE:
7981                         flow_dv_translate_item_nvgre(match_mask, match_value,
7982                                                      items, tunnel);
7983                         matcher.priority = flow->rss.level >= 2 ?
7984                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7985                         last_item = MLX5_FLOW_LAYER_GRE;
7986                         break;
7987                 case RTE_FLOW_ITEM_TYPE_VXLAN:
7988                         flow_dv_translate_item_vxlan(match_mask, match_value,
7989                                                      items, tunnel);
7990                         matcher.priority = flow->rss.level >= 2 ?
7991                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
7992                         last_item = MLX5_FLOW_LAYER_VXLAN;
7993                         break;
7994                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7995                         flow_dv_translate_item_vxlan_gpe(match_mask,
7996                                                          match_value, items,
7997                                                          tunnel);
7998                         matcher.priority = flow->rss.level >= 2 ?
7999                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8000                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8001                         break;
8002                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8003                         flow_dv_translate_item_geneve(match_mask, match_value,
8004                                                       items, tunnel);
8005                         matcher.priority = flow->rss.level >= 2 ?
8006                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8007                         last_item = MLX5_FLOW_LAYER_GENEVE;
8008                         break;
8009                 case RTE_FLOW_ITEM_TYPE_MPLS:
8010                         flow_dv_translate_item_mpls(match_mask, match_value,
8011                                                     items, last_item, tunnel);
8012                         matcher.priority = flow->rss.level >= 2 ?
8013                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8014                         last_item = MLX5_FLOW_LAYER_MPLS;
8015                         break;
8016                 case RTE_FLOW_ITEM_TYPE_MARK:
8017                         flow_dv_translate_item_mark(dev, match_mask,
8018                                                     match_value, items);
8019                         last_item = MLX5_FLOW_ITEM_MARK;
8020                         break;
8021                 case RTE_FLOW_ITEM_TYPE_META:
8022                         flow_dv_translate_item_meta(dev, match_mask,
8023                                                     match_value, attr, items);
8024                         last_item = MLX5_FLOW_ITEM_METADATA;
8025                         break;
8026                 case RTE_FLOW_ITEM_TYPE_ICMP:
8027                         flow_dv_translate_item_icmp(match_mask, match_value,
8028                                                     items, tunnel);
8029                         last_item = MLX5_FLOW_LAYER_ICMP;
8030                         break;
8031                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8032                         flow_dv_translate_item_icmp6(match_mask, match_value,
8033                                                       items, tunnel);
8034                         last_item = MLX5_FLOW_LAYER_ICMP6;
8035                         break;
8036                 case RTE_FLOW_ITEM_TYPE_TAG:
8037                         flow_dv_translate_item_tag(dev, match_mask,
8038                                                    match_value, items);
8039                         last_item = MLX5_FLOW_ITEM_TAG;
8040                         break;
8041                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8042                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8043                                                         match_value, items);
8044                         last_item = MLX5_FLOW_ITEM_TAG;
8045                         break;
8046                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8047                         flow_dv_translate_item_tx_queue(dev, match_mask,
8048                                                         match_value,
8049                                                         items);
8050                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8051                         break;
8052                 case RTE_FLOW_ITEM_TYPE_GTP:
8053                         flow_dv_translate_item_gtp(match_mask, match_value,
8054                                                    items, tunnel);
8055                         matcher.priority = flow->rss.level >= 2 ?
8056                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8057                         last_item = MLX5_FLOW_LAYER_GTP;
8058                         break;
8059                 default:
8060                         break;
8061                 }
8062                 item_flags |= last_item;
8063         }
8064         /*
8065          * When E-Switch mode is enabled, we have two cases where we need to
8066          * set the source port manually.
8067          * The first one, is in case of Nic steering rule, and the second is
8068          * E-Switch rule where no port_id item was found. In both cases
8069          * the source port is set according the current port in use.
8070          */
8071         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8072             (priv->representor || priv->master)) {
8073                 if (flow_dv_translate_item_port_id(dev, match_mask,
8074                                                    match_value, NULL))
8075                         return -rte_errno;
8076         }
8077 #ifdef RTE_LIBRTE_MLX5_DEBUG
8078         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8079                                               dev_flow->dv.value.buf));
8080 #endif
8081         /*
8082          * Layers may be already initialized from prefix flow if this dev_flow
8083          * is the suffix flow.
8084          */
8085         handle->layers |= item_flags;
8086         if (action_flags & MLX5_FLOW_ACTION_RSS)
8087                 flow_dv_hashfields_set(dev_flow);
8088         /* Register matcher. */
8089         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8090                                     matcher.mask.size);
8091         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8092                                                      matcher.priority);
8093         /* reserved field no needs to be set to 0 here. */
8094         tbl_key.domain = attr->transfer;
8095         tbl_key.direction = attr->egress;
8096         tbl_key.table_id = dev_flow->dv.group;
8097         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8098                 return -rte_errno;
8099         return 0;
8100 }
8101
8102 /**
8103  * Apply the flow to the NIC, lock free,
8104  * (mutex should be acquired by caller).
8105  *
8106  * @param[in] dev
8107  *   Pointer to the Ethernet device structure.
8108  * @param[in, out] flow
8109  *   Pointer to flow structure.
8110  * @param[out] error
8111  *   Pointer to error structure.
8112  *
8113  * @return
8114  *   0 on success, a negative errno value otherwise and rte_errno is set.
8115  */
8116 static int
8117 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8118                 struct rte_flow_error *error)
8119 {
8120         struct mlx5_flow_dv_workspace *dv;
8121         struct mlx5_flow_handle *dh;
8122         struct mlx5_flow_handle_dv *dv_h;
8123         struct mlx5_flow *dev_flow;
8124         struct mlx5_priv *priv = dev->data->dev_private;
8125         int n;
8126         int err;
8127         int idx;
8128
8129         for (idx = priv->flow_idx - 1; idx >= 0; idx--) {
8130                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8131                 dv = &dev_flow->dv;
8132                 dh = dev_flow->handle;
8133                 dv_h = &dh->dvh;
8134                 n = dv->actions_n;
8135                 if (dh->act_flags & MLX5_FLOW_ACTION_DROP) {
8136                         if (dv->transfer) {
8137                                 dv->actions[n++] = priv->sh->esw_drop_action;
8138                         } else {
8139                                 dh->hrxq = mlx5_hrxq_drop_new(dev);
8140                                 if (!dh->hrxq) {
8141                                         rte_flow_error_set
8142                                                 (error, errno,
8143                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8144                                                  NULL,
8145                                                  "cannot get drop hash queue");
8146                                         goto error;
8147                                 }
8148                                 dv->actions[n++] = dh->hrxq->action;
8149                         }
8150                 } else if (dh->act_flags &
8151                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
8152                         struct mlx5_hrxq *hrxq;
8153
8154                         MLX5_ASSERT(flow->rss.queue);
8155                         hrxq = mlx5_hrxq_get(dev, flow->rss.key,
8156                                              MLX5_RSS_HASH_KEY_LEN,
8157                                              dev_flow->hash_fields,
8158                                              (*flow->rss.queue),
8159                                              flow->rss.queue_num);
8160                         if (!hrxq) {
8161                                 hrxq = mlx5_hrxq_new
8162                                         (dev, flow->rss.key,
8163                                          MLX5_RSS_HASH_KEY_LEN,
8164                                          dev_flow->hash_fields,
8165                                          (*flow->rss.queue),
8166                                          flow->rss.queue_num,
8167                                          !!(dh->layers &
8168                                             MLX5_FLOW_LAYER_TUNNEL));
8169                         }
8170                         if (!hrxq) {
8171                                 rte_flow_error_set
8172                                         (error, rte_errno,
8173                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8174                                          "cannot get hash queue");
8175                                 goto error;
8176                         }
8177                         dh->hrxq = hrxq;
8178                         dv->actions[n++] = dh->hrxq->action;
8179                 }
8180                 dh->ib_flow =
8181                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8182                                                   (void *)&dv->value, n,
8183                                                   dv->actions);
8184                 if (!dh->ib_flow) {
8185                         rte_flow_error_set(error, errno,
8186                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8187                                            NULL,
8188                                            "hardware refuses to create flow");
8189                         goto error;
8190                 }
8191                 if (priv->vmwa_context &&
8192                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8193                         /*
8194                          * The rule contains the VLAN pattern.
8195                          * For VF we are going to create VLAN
8196                          * interface to make hypervisor set correct
8197                          * e-Switch vport context.
8198                          */
8199                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8200                 }
8201         }
8202         return 0;
8203 error:
8204         err = rte_errno; /* Save rte_errno before cleanup. */
8205         LIST_FOREACH(dh, &flow->dev_handles, next) {
8206                 if (dh->hrxq) {
8207                         if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8208                                 mlx5_hrxq_drop_release(dev);
8209                         else
8210                                 mlx5_hrxq_release(dev, dh->hrxq);
8211                         dh->hrxq = NULL;
8212                 }
8213                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8214                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8215         }
8216         rte_errno = err; /* Restore rte_errno. */
8217         return -rte_errno;
8218 }
8219
8220 /**
8221  * Release the flow matcher.
8222  *
8223  * @param dev
8224  *   Pointer to Ethernet device.
8225  * @param handle
8226  *   Pointer to mlx5_flow_handle.
8227  *
8228  * @return
8229  *   1 while a reference on it exists, 0 when freed.
8230  */
8231 static int
8232 flow_dv_matcher_release(struct rte_eth_dev *dev,
8233                         struct mlx5_flow_handle *handle)
8234 {
8235         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8236
8237         MLX5_ASSERT(matcher->matcher_object);
8238         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8239                 dev->data->port_id, (void *)matcher,
8240                 rte_atomic32_read(&matcher->refcnt));
8241         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8242                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8243                            (matcher->matcher_object));
8244                 LIST_REMOVE(matcher, next);
8245                 /* table ref-- in release interface. */
8246                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8247                 rte_free(matcher);
8248                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8249                         dev->data->port_id, (void *)matcher);
8250                 return 0;
8251         }
8252         return 1;
8253 }
8254
8255 /**
8256  * Release an encap/decap resource.
8257  *
8258  * @param handle
8259  *   Pointer to mlx5_flow_handle.
8260  *
8261  * @return
8262  *   1 while a reference on it exists, 0 when freed.
8263  */
8264 static int
8265 flow_dv_encap_decap_resource_release(struct mlx5_flow_handle *handle)
8266 {
8267         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
8268                                                 handle->dvh.encap_decap;
8269
8270         MLX5_ASSERT(cache_resource->verbs_action);
8271         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8272                 (void *)cache_resource,
8273                 rte_atomic32_read(&cache_resource->refcnt));
8274         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8275                 claim_zero(mlx5_glue->destroy_flow_action
8276                                 (cache_resource->verbs_action));
8277                 LIST_REMOVE(cache_resource, next);
8278                 rte_free(cache_resource);
8279                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8280                         (void *)cache_resource);
8281                 return 0;
8282         }
8283         return 1;
8284 }
8285
8286 /**
8287  * Release an jump to table action resource.
8288  *
8289  * @param dev
8290  *   Pointer to Ethernet device.
8291  * @param handle
8292  *   Pointer to mlx5_flow_handle.
8293  *
8294  * @return
8295  *   1 while a reference on it exists, 0 when freed.
8296  */
8297 static int
8298 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8299                                   struct mlx5_flow_handle *handle)
8300 {
8301         struct mlx5_flow_dv_jump_tbl_resource *cache_resource =
8302                                                         handle->dvh.jump;
8303         struct mlx5_flow_tbl_data_entry *tbl_data =
8304                         container_of(cache_resource,
8305                                      struct mlx5_flow_tbl_data_entry, jump);
8306
8307         MLX5_ASSERT(cache_resource->action);
8308         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8309                 (void *)cache_resource,
8310                 rte_atomic32_read(&cache_resource->refcnt));
8311         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8312                 claim_zero(mlx5_glue->destroy_flow_action
8313                                 (cache_resource->action));
8314                 /* jump action memory free is inside the table release. */
8315                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8316                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8317                         (void *)cache_resource);
8318                 return 0;
8319         }
8320         return 1;
8321 }
8322
8323 /**
8324  * Release a modify-header resource.
8325  *
8326  * @param handle
8327  *   Pointer to mlx5_flow_handle.
8328  *
8329  * @return
8330  *   1 while a reference on it exists, 0 when freed.
8331  */
8332 static int
8333 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8334 {
8335         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8336                                                         handle->dvh.modify_hdr;
8337
8338         MLX5_ASSERT(cache_resource->verbs_action);
8339         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8340                 (void *)cache_resource,
8341                 rte_atomic32_read(&cache_resource->refcnt));
8342         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8343                 claim_zero(mlx5_glue->destroy_flow_action
8344                                 (cache_resource->verbs_action));
8345                 LIST_REMOVE(cache_resource, next);
8346                 rte_free(cache_resource);
8347                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8348                         (void *)cache_resource);
8349                 return 0;
8350         }
8351         return 1;
8352 }
8353
8354 /**
8355  * Release port ID action resource.
8356  *
8357  * @param handle
8358  *   Pointer to mlx5_flow_handle.
8359  *
8360  * @return
8361  *   1 while a reference on it exists, 0 when freed.
8362  */
8363 static int
8364 flow_dv_port_id_action_resource_release(struct mlx5_flow_handle *handle)
8365 {
8366         struct mlx5_flow_dv_port_id_action_resource *cache_resource =
8367                                                 handle->dvh.port_id_action;
8368
8369         MLX5_ASSERT(cache_resource->action);
8370         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8371                 (void *)cache_resource,
8372                 rte_atomic32_read(&cache_resource->refcnt));
8373         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8374                 claim_zero(mlx5_glue->destroy_flow_action
8375                                 (cache_resource->action));
8376                 LIST_REMOVE(cache_resource, next);
8377                 rte_free(cache_resource);
8378                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8379                         (void *)cache_resource);
8380                 return 0;
8381         }
8382         return 1;
8383 }
8384
8385 /**
8386  * Release push vlan action resource.
8387  *
8388  * @param handle
8389  *   Pointer to mlx5_flow_handle.
8390  *
8391  * @return
8392  *   1 while a reference on it exists, 0 when freed.
8393  */
8394 static int
8395 flow_dv_push_vlan_action_resource_release(struct mlx5_flow_handle *handle)
8396 {
8397         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
8398                                                 handle->dvh.push_vlan_res;
8399
8400         MLX5_ASSERT(cache_resource->action);
8401         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8402                 (void *)cache_resource,
8403                 rte_atomic32_read(&cache_resource->refcnt));
8404         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8405                 claim_zero(mlx5_glue->destroy_flow_action
8406                                 (cache_resource->action));
8407                 LIST_REMOVE(cache_resource, next);
8408                 rte_free(cache_resource);
8409                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8410                         (void *)cache_resource);
8411                 return 0;
8412         }
8413         return 1;
8414 }
8415
8416 /**
8417  * Remove the flow from the NIC but keeps it in memory.
8418  * Lock free, (mutex should be acquired by caller).
8419  *
8420  * @param[in] dev
8421  *   Pointer to Ethernet device.
8422  * @param[in, out] flow
8423  *   Pointer to flow structure.
8424  */
8425 static void
8426 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8427 {
8428         struct mlx5_flow_handle *dh;
8429
8430         if (!flow)
8431                 return;
8432         LIST_FOREACH(dh, &flow->dev_handles, next) {
8433                 if (dh->ib_flow) {
8434                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8435                         dh->ib_flow = NULL;
8436                 }
8437                 if (dh->hrxq) {
8438                         if (dh->act_flags & MLX5_FLOW_ACTION_DROP)
8439                                 mlx5_hrxq_drop_release(dev);
8440                         else
8441                                 mlx5_hrxq_release(dev, dh->hrxq);
8442                         dh->hrxq = NULL;
8443                 }
8444                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8445                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8446         }
8447 }
8448
8449 /**
8450  * Remove the flow from the NIC and the memory.
8451  * Lock free, (mutex should be acquired by caller).
8452  *
8453  * @param[in] dev
8454  *   Pointer to the Ethernet device structure.
8455  * @param[in, out] flow
8456  *   Pointer to flow structure.
8457  */
8458 static void
8459 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8460 {
8461         struct mlx5_flow_handle *dev_handle;
8462
8463         if (!flow)
8464                 return;
8465         __flow_dv_remove(dev, flow);
8466         if (flow->counter) {
8467                 flow_dv_counter_release(dev, flow->counter);
8468                 flow->counter = NULL;
8469         }
8470         if (flow->meter) {
8471                 mlx5_flow_meter_detach(flow->meter);
8472                 flow->meter = NULL;
8473         }
8474         while (!LIST_EMPTY(&flow->dev_handles)) {
8475                 dev_handle = LIST_FIRST(&flow->dev_handles);
8476                 LIST_REMOVE(dev_handle, next);
8477                 if (dev_handle->dvh.matcher)
8478                         flow_dv_matcher_release(dev, dev_handle);
8479                 if (dev_handle->dvh.encap_decap)
8480                         flow_dv_encap_decap_resource_release(dev_handle);
8481                 if (dev_handle->dvh.modify_hdr)
8482                         flow_dv_modify_hdr_resource_release(dev_handle);
8483                 if (dev_handle->dvh.jump)
8484                         flow_dv_jump_tbl_resource_release(dev, dev_handle);
8485                 if (dev_handle->dvh.port_id_action)
8486                         flow_dv_port_id_action_resource_release(dev_handle);
8487                 if (dev_handle->dvh.push_vlan_res)
8488                         flow_dv_push_vlan_action_resource_release(dev_handle);
8489                 if (dev_handle->dvh.tag_resource)
8490                         flow_dv_tag_release(dev,
8491                                             dev_handle->dvh.tag_resource);
8492                 rte_free(dev_handle);
8493         }
8494 }
8495
8496 /**
8497  * Query a dv flow  rule for its statistics via devx.
8498  *
8499  * @param[in] dev
8500  *   Pointer to Ethernet device.
8501  * @param[in] flow
8502  *   Pointer to the sub flow.
8503  * @param[out] data
8504  *   data retrieved by the query.
8505  * @param[out] error
8506  *   Perform verbose error reporting if not NULL.
8507  *
8508  * @return
8509  *   0 on success, a negative errno value otherwise and rte_errno is set.
8510  */
8511 static int
8512 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8513                     void *data, struct rte_flow_error *error)
8514 {
8515         struct mlx5_priv *priv = dev->data->dev_private;
8516         struct rte_flow_query_count *qc = data;
8517
8518         if (!priv->config.devx)
8519                 return rte_flow_error_set(error, ENOTSUP,
8520                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8521                                           NULL,
8522                                           "counters are not supported");
8523         if (flow->counter) {
8524                 uint64_t pkts, bytes;
8525                 struct mlx5_flow_counter *cnt;
8526
8527                 cnt = flow_dv_counter_get_by_idx(dev, (uintptr_t)flow->counter,
8528                                                  NULL);
8529                 int err = _flow_dv_query_count(dev, cnt, &pkts,
8530                                                &bytes);
8531
8532                 if (err)
8533                         return rte_flow_error_set(error, -err,
8534                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8535                                         NULL, "cannot read counters");
8536                 qc->hits_set = 1;
8537                 qc->bytes_set = 1;
8538                 qc->hits = pkts - cnt->hits;
8539                 qc->bytes = bytes - cnt->bytes;
8540                 if (qc->reset) {
8541                         cnt->hits = pkts;
8542                         cnt->bytes = bytes;
8543                 }
8544                 return 0;
8545         }
8546         return rte_flow_error_set(error, EINVAL,
8547                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8548                                   NULL,
8549                                   "counters are not available");
8550 }
8551
8552 /**
8553  * Query a flow.
8554  *
8555  * @see rte_flow_query()
8556  * @see rte_flow_ops
8557  */
8558 static int
8559 flow_dv_query(struct rte_eth_dev *dev,
8560               struct rte_flow *flow __rte_unused,
8561               const struct rte_flow_action *actions __rte_unused,
8562               void *data __rte_unused,
8563               struct rte_flow_error *error __rte_unused)
8564 {
8565         int ret = -EINVAL;
8566
8567         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8568                 switch (actions->type) {
8569                 case RTE_FLOW_ACTION_TYPE_VOID:
8570                         break;
8571                 case RTE_FLOW_ACTION_TYPE_COUNT:
8572                         ret = flow_dv_query_count(dev, flow, data, error);
8573                         break;
8574                 default:
8575                         return rte_flow_error_set(error, ENOTSUP,
8576                                                   RTE_FLOW_ERROR_TYPE_ACTION,
8577                                                   actions,
8578                                                   "action not supported");
8579                 }
8580         }
8581         return ret;
8582 }
8583
8584 /**
8585  * Destroy the meter table set.
8586  * Lock free, (mutex should be acquired by caller).
8587  *
8588  * @param[in] dev
8589  *   Pointer to Ethernet device.
8590  * @param[in] tbl
8591  *   Pointer to the meter table set.
8592  *
8593  * @return
8594  *   Always 0.
8595  */
8596 static int
8597 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8598                         struct mlx5_meter_domains_infos *tbl)
8599 {
8600         struct mlx5_priv *priv = dev->data->dev_private;
8601         struct mlx5_meter_domains_infos *mtd =
8602                                 (struct mlx5_meter_domains_infos *)tbl;
8603
8604         if (!mtd || !priv->config.dv_flow_en)
8605                 return 0;
8606         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8607                 claim_zero(mlx5_glue->dv_destroy_flow
8608                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8609         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8610                 claim_zero(mlx5_glue->dv_destroy_flow
8611                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8612         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8613                 claim_zero(mlx5_glue->dv_destroy_flow
8614                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8615         if (mtd->egress.color_matcher)
8616                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8617                           (mtd->egress.color_matcher));
8618         if (mtd->egress.any_matcher)
8619                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8620                           (mtd->egress.any_matcher));
8621         if (mtd->egress.tbl)
8622                 claim_zero(flow_dv_tbl_resource_release(dev,
8623                                                         mtd->egress.tbl));
8624         if (mtd->ingress.color_matcher)
8625                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8626                           (mtd->ingress.color_matcher));
8627         if (mtd->ingress.any_matcher)
8628                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8629                           (mtd->ingress.any_matcher));
8630         if (mtd->ingress.tbl)
8631                 claim_zero(flow_dv_tbl_resource_release(dev,
8632                                                         mtd->ingress.tbl));
8633         if (mtd->transfer.color_matcher)
8634                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8635                           (mtd->transfer.color_matcher));
8636         if (mtd->transfer.any_matcher)
8637                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8638                           (mtd->transfer.any_matcher));
8639         if (mtd->transfer.tbl)
8640                 claim_zero(flow_dv_tbl_resource_release(dev,
8641                                                         mtd->transfer.tbl));
8642         if (mtd->drop_actn)
8643                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8644         rte_free(mtd);
8645         return 0;
8646 }
8647
8648 /* Number of meter flow actions, count and jump or count and drop. */
8649 #define METER_ACTIONS 2
8650
8651 /**
8652  * Create specify domain meter table and suffix table.
8653  *
8654  * @param[in] dev
8655  *   Pointer to Ethernet device.
8656  * @param[in,out] mtb
8657  *   Pointer to DV meter table set.
8658  * @param[in] egress
8659  *   Table attribute.
8660  * @param[in] transfer
8661  *   Table attribute.
8662  * @param[in] color_reg_c_idx
8663  *   Reg C index for color match.
8664  *
8665  * @return
8666  *   0 on success, -1 otherwise and rte_errno is set.
8667  */
8668 static int
8669 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8670                            struct mlx5_meter_domains_infos *mtb,
8671                            uint8_t egress, uint8_t transfer,
8672                            uint32_t color_reg_c_idx)
8673 {
8674         struct mlx5_priv *priv = dev->data->dev_private;
8675         struct mlx5_ibv_shared *sh = priv->sh;
8676         struct mlx5_flow_dv_match_params mask = {
8677                 .size = sizeof(mask.buf),
8678         };
8679         struct mlx5_flow_dv_match_params value = {
8680                 .size = sizeof(value.buf),
8681         };
8682         struct mlx5dv_flow_matcher_attr dv_attr = {
8683                 .type = IBV_FLOW_ATTR_NORMAL,
8684                 .priority = 0,
8685                 .match_criteria_enable = 0,
8686                 .match_mask = (void *)&mask,
8687         };
8688         void *actions[METER_ACTIONS];
8689         struct mlx5_flow_tbl_resource **sfx_tbl;
8690         struct mlx5_meter_domain_info *dtb;
8691         struct rte_flow_error error;
8692         int i = 0;
8693
8694         if (transfer) {
8695                 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8696                 dtb = &mtb->transfer;
8697         } else if (egress) {
8698                 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8699                 dtb = &mtb->egress;
8700         } else {
8701                 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8702                 dtb = &mtb->ingress;
8703         }
8704         /* If the suffix table in missing, create it. */
8705         if (!(*sfx_tbl)) {
8706                 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8707                                                 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8708                                                 egress, transfer, &error);
8709                 if (!(*sfx_tbl)) {
8710                         DRV_LOG(ERR, "Failed to create meter suffix table.");
8711                         return -1;
8712                 }
8713         }
8714         /* Create the meter table with METER level. */
8715         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8716                                             egress, transfer, &error);
8717         if (!dtb->tbl) {
8718                 DRV_LOG(ERR, "Failed to create meter policer table.");
8719                 return -1;
8720         }
8721         /* Create matchers, Any and Color. */
8722         dv_attr.priority = 3;
8723         dv_attr.match_criteria_enable = 0;
8724         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8725                                                              &dv_attr,
8726                                                              dtb->tbl->obj);
8727         if (!dtb->any_matcher) {
8728                 DRV_LOG(ERR, "Failed to create meter"
8729                              " policer default matcher.");
8730                 goto error_exit;
8731         }
8732         dv_attr.priority = 0;
8733         dv_attr.match_criteria_enable =
8734                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8735         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8736                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8737         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8738                                                                &dv_attr,
8739                                                                dtb->tbl->obj);
8740         if (!dtb->color_matcher) {
8741                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8742                 goto error_exit;
8743         }
8744         if (mtb->count_actns[RTE_MTR_DROPPED])
8745                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8746         actions[i++] = mtb->drop_actn;
8747         /* Default rule: lowest priority, match any, actions: drop. */
8748         dtb->policer_rules[RTE_MTR_DROPPED] =
8749                         mlx5_glue->dv_create_flow(dtb->any_matcher,
8750                                                  (void *)&value, i, actions);
8751         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8752                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8753                 goto error_exit;
8754         }
8755         return 0;
8756 error_exit:
8757         return -1;
8758 }
8759
8760 /**
8761  * Create the needed meter and suffix tables.
8762  * Lock free, (mutex should be acquired by caller).
8763  *
8764  * @param[in] dev
8765  *   Pointer to Ethernet device.
8766  * @param[in] fm
8767  *   Pointer to the flow meter.
8768  *
8769  * @return
8770  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
8771  */
8772 static struct mlx5_meter_domains_infos *
8773 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8774                        const struct mlx5_flow_meter *fm)
8775 {
8776         struct mlx5_priv *priv = dev->data->dev_private;
8777         struct mlx5_meter_domains_infos *mtb;
8778         int ret;
8779         int i;
8780
8781         if (!priv->mtr_en) {
8782                 rte_errno = ENOTSUP;
8783                 return NULL;
8784         }
8785         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8786         if (!mtb) {
8787                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8788                 return NULL;
8789         }
8790         /* Create meter count actions */
8791         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8792                 struct mlx5_flow_counter *cnt;
8793                 if (!fm->policer_stats.cnt[i])
8794                         continue;
8795                 cnt = flow_dv_counter_get_by_idx(dev,
8796                       (uintptr_t)fm->policer_stats.cnt[i], NULL);
8797                 mtb->count_actns[i] = cnt->action;
8798         }
8799         /* Create drop action. */
8800         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8801         if (!mtb->drop_actn) {
8802                 DRV_LOG(ERR, "Failed to create drop action.");
8803                 goto error_exit;
8804         }
8805         /* Egress meter table. */
8806         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8807         if (ret) {
8808                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8809                 goto error_exit;
8810         }
8811         /* Ingress meter table. */
8812         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8813         if (ret) {
8814                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8815                 goto error_exit;
8816         }
8817         /* FDB meter table. */
8818         if (priv->config.dv_esw_en) {
8819                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8820                                                  priv->mtr_color_reg);
8821                 if (ret) {
8822                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8823                         goto error_exit;
8824                 }
8825         }
8826         return mtb;
8827 error_exit:
8828         flow_dv_destroy_mtr_tbl(dev, mtb);
8829         return NULL;
8830 }
8831
8832 /**
8833  * Destroy domain policer rule.
8834  *
8835  * @param[in] dt
8836  *   Pointer to domain table.
8837  */
8838 static void
8839 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8840 {
8841         int i;
8842
8843         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8844                 if (dt->policer_rules[i]) {
8845                         claim_zero(mlx5_glue->dv_destroy_flow
8846                                   (dt->policer_rules[i]));
8847                         dt->policer_rules[i] = NULL;
8848                 }
8849         }
8850         if (dt->jump_actn) {
8851                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8852                 dt->jump_actn = NULL;
8853         }
8854 }
8855
8856 /**
8857  * Destroy policer rules.
8858  *
8859  * @param[in] dev
8860  *   Pointer to Ethernet device.
8861  * @param[in] fm
8862  *   Pointer to flow meter structure.
8863  * @param[in] attr
8864  *   Pointer to flow attributes.
8865  *
8866  * @return
8867  *   Always 0.
8868  */
8869 static int
8870 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8871                               const struct mlx5_flow_meter *fm,
8872                               const struct rte_flow_attr *attr)
8873 {
8874         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8875
8876         if (!mtb)
8877                 return 0;
8878         if (attr->egress)
8879                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8880         if (attr->ingress)
8881                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8882         if (attr->transfer)
8883                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8884         return 0;
8885 }
8886
8887 /**
8888  * Create specify domain meter policer rule.
8889  *
8890  * @param[in] fm
8891  *   Pointer to flow meter structure.
8892  * @param[in] mtb
8893  *   Pointer to DV meter table set.
8894  * @param[in] sfx_tb
8895  *   Pointer to suffix table.
8896  * @param[in] mtr_reg_c
8897  *   Color match REG_C.
8898  *
8899  * @return
8900  *   0 on success, -1 otherwise.
8901  */
8902 static int
8903 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8904                                     struct mlx5_meter_domain_info *dtb,
8905                                     struct mlx5_flow_tbl_resource *sfx_tb,
8906                                     uint8_t mtr_reg_c)
8907 {
8908         struct mlx5_flow_dv_match_params matcher = {
8909                 .size = sizeof(matcher.buf),
8910         };
8911         struct mlx5_flow_dv_match_params value = {
8912                 .size = sizeof(value.buf),
8913         };
8914         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8915         void *actions[METER_ACTIONS];
8916         int i;
8917
8918         /* Create jump action. */
8919         if (!sfx_tb)
8920                 return -1;
8921         if (!dtb->jump_actn)
8922                 dtb->jump_actn =
8923                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
8924                                                         (sfx_tb->obj);
8925         if (!dtb->jump_actn) {
8926                 DRV_LOG(ERR, "Failed to create policer jump action.");
8927                 goto error;
8928         }
8929         for (i = 0; i < RTE_MTR_DROPPED; i++) {
8930                 int j = 0;
8931
8932                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8933                                        rte_col_2_mlx5_col(i), UINT8_MAX);
8934                 if (mtb->count_actns[i])
8935                         actions[j++] = mtb->count_actns[i];
8936                 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8937                         actions[j++] = mtb->drop_actn;
8938                 else
8939                         actions[j++] = dtb->jump_actn;
8940                 dtb->policer_rules[i] =
8941                         mlx5_glue->dv_create_flow(dtb->color_matcher,
8942                                                  (void *)&value,
8943                                                   j, actions);
8944                 if (!dtb->policer_rules[i]) {
8945                         DRV_LOG(ERR, "Failed to create policer rule.");
8946                         goto error;
8947                 }
8948         }
8949         return 0;
8950 error:
8951         rte_errno = errno;
8952         return -1;
8953 }
8954
8955 /**
8956  * Create policer rules.
8957  *
8958  * @param[in] dev
8959  *   Pointer to Ethernet device.
8960  * @param[in] fm
8961  *   Pointer to flow meter structure.
8962  * @param[in] attr
8963  *   Pointer to flow attributes.
8964  *
8965  * @return
8966  *   0 on success, -1 otherwise.
8967  */
8968 static int
8969 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8970                              struct mlx5_flow_meter *fm,
8971                              const struct rte_flow_attr *attr)
8972 {
8973         struct mlx5_priv *priv = dev->data->dev_private;
8974         struct mlx5_meter_domains_infos *mtb = fm->mfts;
8975         int ret;
8976
8977         if (attr->egress) {
8978                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8979                                                 priv->sh->tx_mtr_sfx_tbl,
8980                                                 priv->mtr_color_reg);
8981                 if (ret) {
8982                         DRV_LOG(ERR, "Failed to create egress policer.");
8983                         goto error;
8984                 }
8985         }
8986         if (attr->ingress) {
8987                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8988                                                 priv->sh->rx_mtr_sfx_tbl,
8989                                                 priv->mtr_color_reg);
8990                 if (ret) {
8991                         DRV_LOG(ERR, "Failed to create ingress policer.");
8992                         goto error;
8993                 }
8994         }
8995         if (attr->transfer) {
8996                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8997                                                 priv->sh->fdb_mtr_sfx_tbl,
8998                                                 priv->mtr_color_reg);
8999                 if (ret) {
9000                         DRV_LOG(ERR, "Failed to create transfer policer.");
9001                         goto error;
9002                 }
9003         }
9004         return 0;
9005 error:
9006         flow_dv_destroy_policer_rules(dev, fm, attr);
9007         return -1;
9008 }
9009
9010 /**
9011  * Query a devx counter.
9012  *
9013  * @param[in] dev
9014  *   Pointer to the Ethernet device structure.
9015  * @param[in] cnt
9016  *   Pointer to the flow counter.
9017  * @param[in] clear
9018  *   Set to clear the counter statistics.
9019  * @param[out] pkts
9020  *   The statistics value of packets.
9021  * @param[out] bytes
9022  *   The statistics value of bytes.
9023  *
9024  * @return
9025  *   0 on success, otherwise return -1.
9026  */
9027 static int
9028 flow_dv_counter_query(struct rte_eth_dev *dev,
9029                       struct mlx5_flow_counter *counter, bool clear,
9030                       uint64_t *pkts, uint64_t *bytes)
9031 {
9032         struct mlx5_priv *priv = dev->data->dev_private;
9033         struct mlx5_flow_counter *cnt;
9034         uint64_t inn_pkts, inn_bytes;
9035         int ret;
9036
9037         if (!priv->config.devx)
9038                 return -1;
9039
9040         cnt = flow_dv_counter_get_by_idx(dev, (uintptr_t)counter, NULL);
9041         ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
9042         if (ret)
9043                 return -1;
9044         *pkts = inn_pkts - cnt->hits;
9045         *bytes = inn_bytes - cnt->bytes;
9046         if (clear) {
9047                 cnt->hits = inn_pkts;
9048                 cnt->bytes = inn_bytes;
9049         }
9050         return 0;
9051 }
9052
9053 /*
9054  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9055  */
9056 static int
9057 flow_dv_translate(struct rte_eth_dev *dev,
9058                   struct mlx5_flow *dev_flow,
9059                   const struct rte_flow_attr *attr,
9060                   const struct rte_flow_item items[],
9061                   const struct rte_flow_action actions[],
9062                   struct rte_flow_error *error)
9063 {
9064         int ret;
9065
9066         flow_dv_shared_lock(dev);
9067         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9068         flow_dv_shared_unlock(dev);
9069         return ret;
9070 }
9071
9072 /*
9073  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9074  */
9075 static int
9076 flow_dv_apply(struct rte_eth_dev *dev,
9077               struct rte_flow *flow,
9078               struct rte_flow_error *error)
9079 {
9080         int ret;
9081
9082         flow_dv_shared_lock(dev);
9083         ret = __flow_dv_apply(dev, flow, error);
9084         flow_dv_shared_unlock(dev);
9085         return ret;
9086 }
9087
9088 /*
9089  * Mutex-protected thunk to lock-free __flow_dv_remove().
9090  */
9091 static void
9092 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9093 {
9094         flow_dv_shared_lock(dev);
9095         __flow_dv_remove(dev, flow);
9096         flow_dv_shared_unlock(dev);
9097 }
9098
9099 /*
9100  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9101  */
9102 static void
9103 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9104 {
9105         flow_dv_shared_lock(dev);
9106         __flow_dv_destroy(dev, flow);
9107         flow_dv_shared_unlock(dev);
9108 }
9109
9110 /*
9111  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9112  */
9113 static struct mlx5_flow_counter *
9114 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9115 {
9116         struct mlx5_flow_counter *cnt;
9117
9118         flow_dv_shared_lock(dev);
9119         cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
9120         flow_dv_shared_unlock(dev);
9121         return cnt;
9122 }
9123
9124 /*
9125  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9126  */
9127 static void
9128 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
9129 {
9130         flow_dv_shared_lock(dev);
9131         flow_dv_counter_release(dev, cnt);
9132         flow_dv_shared_unlock(dev);
9133 }
9134
9135 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9136         .validate = flow_dv_validate,
9137         .prepare = flow_dv_prepare,
9138         .translate = flow_dv_translate,
9139         .apply = flow_dv_apply,
9140         .remove = flow_dv_remove,
9141         .destroy = flow_dv_destroy,
9142         .query = flow_dv_query,
9143         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9144         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9145         .create_policer_rules = flow_dv_create_policer_rules,
9146         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9147         .counter_alloc = flow_dv_counter_allocate,
9148         .counter_free = flow_dv_counter_free,
9149         .counter_query = flow_dv_counter_query,
9150 };
9151
9152 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */