drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #ifdef PEDANTIC
  18 #pragma GCC diagnostic error "-Wpedantic"
  19 #endif
  20
  21 #include <rte_common.h>
  22 #include <rte_ether.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_cycles.h>
  28 #include <rte_ip.h>
  29 #include <rte_gre.h>
  30 #include <rte_vxlan.h>
  31 #include <rte_gtp.h>
  32
  33 #include <mlx5_glue.h>
  34 #include <mlx5_devx_cmds.h>
  35 #include <mlx5_prm.h>
  36
  37 #include "mlx5_defs.h"
  38 #include "mlx5.h"
  39 #include "mlx5_flow.h"
  40 #include "mlx5_rxtx.h"
  41
  42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  43
  44 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  45 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  46 #endif
  47
  48 #ifndef HAVE_MLX5DV_DR_ESWITCH
  49 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  50 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  51 #endif
  52 #endif
  53
  54 #ifndef HAVE_MLX5DV_DR
  55 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  56 #endif
  57
  58 /* VLAN header definitions */
  59 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  60 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  61 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  62 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  63 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  64
  65 union flow_dv_attr {
  66         struct {
  67                 uint32_t valid:1;
  68                 uint32_t ipv4:1;
  69                 uint32_t ipv6:1;
  70                 uint32_t tcp:1;
  71                 uint32_t udp:1;
  72                 uint32_t reserved:27;
  73         };
  74         uint32_t attr;
  75 };
  76
  77 static int
  78 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
  79                              struct mlx5_flow_tbl_resource *tbl);
  80
  81 /**
  82  * Initialize flow attributes structure according to flow items' types.
  83  *
  84  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  85  * mode. For tunnel mode, the items to be modified are the outermost ones.
  86  *
  87  * @param[in] item
  88  *   Pointer to item specification.
  89  * @param[out] attr
  90  *   Pointer to flow attributes structure.
  91  * @param[in] dev_flow
  92  *   Pointer to the sub flow.
  93  * @param[in] tunnel_decap
  94  *   Whether action is after tunnel decapsulation.
  95  */
  96 static void
  97 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
  98                   struct mlx5_flow *dev_flow, bool tunnel_decap)
  99 {
 100         uint64_t layers = dev_flow->handle->layers;
 101
 102         /*
 103          * If layers is already initialized, it means this dev_flow is the
 104          * suffix flow, the layers flags is set by the prefix flow. Need to
 105          * use the layer flags from prefix flow as the suffix flow may not
 106          * have the user defined items as the flow is split.
 107          */
 108         if (layers) {
 109                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 110                         attr->ipv4 = 1;
 111                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 112                         attr->ipv6 = 1;
 113                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 114                         attr->tcp = 1;
 115                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 116                         attr->udp = 1;
 117                 attr->valid = 1;
 118                 return;
 119         }
 120         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 121                 uint8_t next_protocol = 0xff;
 122                 switch (item->type) {
 123                 case RTE_FLOW_ITEM_TYPE_GRE:
 124                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 125                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 126                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 127                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 128                 case RTE_FLOW_ITEM_TYPE_MPLS:
 129                         if (tunnel_decap)
 130                                 attr->attr = 0;
 131                         break;
 132                 case RTE_FLOW_ITEM_TYPE_IPV4:
 133                         if (!attr->ipv6)
 134                                 attr->ipv4 = 1;
 135                         if (item->mask != NULL &&
 136                             ((const struct rte_flow_item_ipv4 *)
 137                             item->mask)->hdr.next_proto_id)
 138                                 next_protocol =
 139                                     ((const struct rte_flow_item_ipv4 *)
 140                                       (item->spec))->hdr.next_proto_id &
 141                                     ((const struct rte_flow_item_ipv4 *)
 142                                       (item->mask))->hdr.next_proto_id;
 143                         if ((next_protocol == IPPROTO_IPIP ||
 144                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 145                                 attr->attr = 0;
 146                         break;
 147                 case RTE_FLOW_ITEM_TYPE_IPV6:
 148                         if (!attr->ipv4)
 149                                 attr->ipv6 = 1;
 150                         if (item->mask != NULL &&
 151                             ((const struct rte_flow_item_ipv6 *)
 152                             item->mask)->hdr.proto)
 153                                 next_protocol =
 154                                     ((const struct rte_flow_item_ipv6 *)
 155                                       (item->spec))->hdr.proto &
 156                                     ((const struct rte_flow_item_ipv6 *)
 157                                       (item->mask))->hdr.proto;
 158                         if ((next_protocol == IPPROTO_IPIP ||
 159                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 160                                 attr->attr = 0;
 161                         break;
 162                 case RTE_FLOW_ITEM_TYPE_UDP:
 163                         if (!attr->tcp)
 164                                 attr->udp = 1;
 165                         break;
 166                 case RTE_FLOW_ITEM_TYPE_TCP:
 167                         if (!attr->udp)
 168                                 attr->tcp = 1;
 169                         break;
 170                 default:
 171                         break;
 172                 }
 173         }
 174         attr->valid = 1;
 175 }
 176
 177 /**
 178  * Convert rte_mtr_color to mlx5 color.
 179  *
 180  * @param[in] rcol
 181  *   rte_mtr_color.
 182  *
 183  * @return
 184  *   mlx5 color.
 185  */
 186 static int
 187 rte_col_2_mlx5_col(enum rte_color rcol)
 188 {
 189         switch (rcol) {
 190         case RTE_COLOR_GREEN:
 191                 return MLX5_FLOW_COLOR_GREEN;
 192         case RTE_COLOR_YELLOW:
 193                 return MLX5_FLOW_COLOR_YELLOW;
 194         case RTE_COLOR_RED:
 195                 return MLX5_FLOW_COLOR_RED;
 196         default:
 197                 break;
 198         }
 199         return MLX5_FLOW_COLOR_UNDEFINED;
 200 }
 201
 202 struct field_modify_info {
 203         uint32_t size; /* Size of field in protocol header, in bytes. */
 204         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 205         enum mlx5_modification_field id;
 206 };
 207
 208 struct field_modify_info modify_eth[] = {
 209         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 210         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 211         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 212         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 213         {0, 0, 0},
 214 };
 215
 216 struct field_modify_info modify_vlan_out_first_vid[] = {
 217         /* Size in bits !!! */
 218         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 219         {0, 0, 0},
 220 };
 221
 222 struct field_modify_info modify_ipv4[] = {
 223         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 224         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 225         {4, 12, MLX5_MODI_OUT_SIPV4},
 226         {4, 16, MLX5_MODI_OUT_DIPV4},
 227         {0, 0, 0},
 228 };
 229
 230 struct field_modify_info modify_ipv6[] = {
 231         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 232         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 233         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 234         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 235         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 236         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 237         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 238         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 239         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 240         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 241         {0, 0, 0},
 242 };
 243
 244 struct field_modify_info modify_udp[] = {
 245         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 246         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 247         {0, 0, 0},
 248 };
 249
 250 struct field_modify_info modify_tcp[] = {
 251         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 252         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 253         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 254         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 255         {0, 0, 0},
 256 };
 257
 258 static void
 259 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 260                           uint8_t next_protocol, uint64_t *item_flags,
 261                           int *tunnel)
 262 {
 263         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 264                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 265         if (next_protocol == IPPROTO_IPIP) {
 266                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 267                 *tunnel = 1;
 268         }
 269         if (next_protocol == IPPROTO_IPV6) {
 270                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 271                 *tunnel = 1;
 272         }
 273 }
 274
 275 /**
 276  * Acquire the synchronizing object to protect multithreaded access
 277  * to shared dv context. Lock occurs only if context is actually
 278  * shared, i.e. we have multiport IB device and representors are
 279  * created.
 280  *
 281  * @param[in] dev
 282  *   Pointer to the rte_eth_dev structure.
 283  */
 284 static void
 285 flow_dv_shared_lock(struct rte_eth_dev *dev)
 286 {
 287         struct mlx5_priv *priv = dev->data->dev_private;
 288         struct mlx5_dev_ctx_shared *sh = priv->sh;
 289
 290         if (sh->dv_refcnt > 1) {
 291                 int ret;
 292
 293                 ret = pthread_mutex_lock(&sh->dv_mutex);
 294                 MLX5_ASSERT(!ret);
 295                 (void)ret;
 296         }
 297 }
 298
 299 static void
 300 flow_dv_shared_unlock(struct rte_eth_dev *dev)
 301 {
 302         struct mlx5_priv *priv = dev->data->dev_private;
 303         struct mlx5_dev_ctx_shared *sh = priv->sh;
 304
 305         if (sh->dv_refcnt > 1) {
 306                 int ret;
 307
 308                 ret = pthread_mutex_unlock(&sh->dv_mutex);
 309                 MLX5_ASSERT(!ret);
 310                 (void)ret;
 311         }
 312 }
 313
 314 /* Update VLAN's VID/PCP based on input rte_flow_action.
 315  *
 316  * @param[in] action
 317  *   Pointer to struct rte_flow_action.
 318  * @param[out] vlan
 319  *   Pointer to struct rte_vlan_hdr.
 320  */
 321 static void
 322 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 323                          struct rte_vlan_hdr *vlan)
 324 {
 325         uint16_t vlan_tci;
 326         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 327                 vlan_tci =
 328                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 329                                                action->conf)->vlan_pcp;
 330                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 331                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 332                 vlan->vlan_tci |= vlan_tci;
 333         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 334                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 335                 vlan->vlan_tci |= rte_be_to_cpu_16
 336                     (((const struct rte_flow_action_of_set_vlan_vid *)
 337                                              action->conf)->vlan_vid);
 338         }
 339 }
 340
 341 /**
 342  * Fetch 1, 2, 3 or 4 byte field from the byte array
 343  * and return as unsigned integer in host-endian format.
 344  *
 345  * @param[in] data
 346  *   Pointer to data array.
 347  * @param[in] size
 348  *   Size of field to extract.
 349  *
 350  * @return
 351  *   converted field in host endian format.
 352  */
 353 static inline uint32_t
 354 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 355 {
 356         uint32_t ret;
 357
 358         switch (size) {
 359         case 1:
 360                 ret = *data;
 361                 break;
 362         case 2:
 363                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 364                 break;
 365         case 3:
 366                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 367                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 368                 break;
 369         case 4:
 370                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 371                 break;
 372         default:
 373                 MLX5_ASSERT(false);
 374                 ret = 0;
 375                 break;
 376         }
 377         return ret;
 378 }
 379
 380 /**
 381  * Convert modify-header action to DV specification.
 382  *
 383  * Data length of each action is determined by provided field description
 384  * and the item mask. Data bit offset and width of each action is determined
 385  * by provided item mask.
 386  *
 387  * @param[in] item
 388  *   Pointer to item specification.
 389  * @param[in] field
 390  *   Pointer to field modification information.
 391  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 392  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 393  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 394  * @param[in] dcopy
 395  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 396  *   Negative offset value sets the same offset as source offset.
 397  *   size field is ignored, value is taken from source field.
 398  * @param[in,out] resource
 399  *   Pointer to the modify-header resource.
 400  * @param[in] type
 401  *   Type of modification.
 402  * @param[out] error
 403  *   Pointer to the error structure.
 404  *
 405  * @return
 406  *   0 on success, a negative errno value otherwise and rte_errno is set.
 407  */
 408 static int
 409 flow_dv_convert_modify_action(struct rte_flow_item *item,
 410                               struct field_modify_info *field,
 411                               struct field_modify_info *dcopy,
 412                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 413                               uint32_t type, struct rte_flow_error *error)
 414 {
 415         uint32_t i = resource->actions_num;
 416         struct mlx5_modification_cmd *actions = resource->actions;
 417
 418         /*
 419          * The item and mask are provided in big-endian format.
 420          * The fields should be presented as in big-endian format either.
 421          * Mask must be always present, it defines the actual field width.
 422          */
 423         MLX5_ASSERT(item->mask);
 424         MLX5_ASSERT(field->size);
 425         do {
 426                 unsigned int size_b;
 427                 unsigned int off_b;
 428                 uint32_t mask;
 429                 uint32_t data;
 430
 431                 if (i >= MLX5_MAX_MODIFY_NUM)
 432                         return rte_flow_error_set(error, EINVAL,
 433                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 434                                  "too many items to modify");
 435                 /* Fetch variable byte size mask from the array. */
 436                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 437                                            field->offset, field->size);
 438                 if (!mask) {
 439                         ++field;
 440                         continue;
 441                 }
 442                 /* Deduce actual data width in bits from mask value. */
 443                 off_b = rte_bsf32(mask);
 444                 size_b = sizeof(uint32_t) * CHAR_BIT -
 445                          off_b - __builtin_clz(mask);
 446                 MLX5_ASSERT(size_b);
 447                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 448                 actions[i] = (struct mlx5_modification_cmd) {
 449                         .action_type = type,
 450                         .field = field->id,
 451                         .offset = off_b,
 452                         .length = size_b,
 453                 };
 454                 /* Convert entire record to expected big-endian format. */
 455                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 456                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 457                         MLX5_ASSERT(dcopy);
 458                         actions[i].dst_field = dcopy->id;
 459                         actions[i].dst_offset =
 460                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 461                         /* Convert entire record to big-endian format. */
 462                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 463                 } else {
 464                         MLX5_ASSERT(item->spec);
 465                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 466                                                    field->offset, field->size);
 467                         /* Shift out the trailing masked bits from data. */
 468                         data = (data & mask) >> off_b;
 469                         actions[i].data1 = rte_cpu_to_be_32(data);
 470                 }
 471                 ++i;
 472                 ++field;
 473         } while (field->size);
 474         if (resource->actions_num == i)
 475                 return rte_flow_error_set(error, EINVAL,
 476                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 477                                           "invalid modification flow item");
 478         resource->actions_num = i;
 479         return 0;
 480 }
 481
 482 /**
 483  * Convert modify-header set IPv4 address action to DV specification.
 484  *
 485  * @param[in,out] resource
 486  *   Pointer to the modify-header resource.
 487  * @param[in] action
 488  *   Pointer to action specification.
 489  * @param[out] error
 490  *   Pointer to the error structure.
 491  *
 492  * @return
 493  *   0 on success, a negative errno value otherwise and rte_errno is set.
 494  */
 495 static int
 496 flow_dv_convert_action_modify_ipv4
 497                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 498                          const struct rte_flow_action *action,
 499                          struct rte_flow_error *error)
 500 {
 501         const struct rte_flow_action_set_ipv4 *conf =
 502                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 503         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 504         struct rte_flow_item_ipv4 ipv4;
 505         struct rte_flow_item_ipv4 ipv4_mask;
 506
 507         memset(&ipv4, 0, sizeof(ipv4));
 508         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 509         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 510                 ipv4.hdr.src_addr = conf->ipv4_addr;
 511                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 512         } else {
 513                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 514                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 515         }
 516         item.spec = &ipv4;
 517         item.mask = &ipv4_mask;
 518         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 519                                              MLX5_MODIFICATION_TYPE_SET, error);
 520 }
 521
 522 /**
 523  * Convert modify-header set IPv6 address action to DV specification.
 524  *
 525  * @param[in,out] resource
 526  *   Pointer to the modify-header resource.
 527  * @param[in] action
 528  *   Pointer to action specification.
 529  * @param[out] error
 530  *   Pointer to the error structure.
 531  *
 532  * @return
 533  *   0 on success, a negative errno value otherwise and rte_errno is set.
 534  */
 535 static int
 536 flow_dv_convert_action_modify_ipv6
 537                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 538                          const struct rte_flow_action *action,
 539                          struct rte_flow_error *error)
 540 {
 541         const struct rte_flow_action_set_ipv6 *conf =
 542                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 543         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 544         struct rte_flow_item_ipv6 ipv6;
 545         struct rte_flow_item_ipv6 ipv6_mask;
 546
 547         memset(&ipv6, 0, sizeof(ipv6));
 548         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 549         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 550                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 551                        sizeof(ipv6.hdr.src_addr));
 552                 memcpy(&ipv6_mask.hdr.src_addr,
 553                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 554                        sizeof(ipv6.hdr.src_addr));
 555         } else {
 556                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 557                        sizeof(ipv6.hdr.dst_addr));
 558                 memcpy(&ipv6_mask.hdr.dst_addr,
 559                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 560                        sizeof(ipv6.hdr.dst_addr));
 561         }
 562         item.spec = &ipv6;
 563         item.mask = &ipv6_mask;
 564         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 565                                              MLX5_MODIFICATION_TYPE_SET, error);
 566 }
 567
 568 /**
 569  * Convert modify-header set MAC address action to DV specification.
 570  *
 571  * @param[in,out] resource
 572  *   Pointer to the modify-header resource.
 573  * @param[in] action
 574  *   Pointer to action specification.
 575  * @param[out] error
 576  *   Pointer to the error structure.
 577  *
 578  * @return
 579  *   0 on success, a negative errno value otherwise and rte_errno is set.
 580  */
 581 static int
 582 flow_dv_convert_action_modify_mac
 583                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 584                          const struct rte_flow_action *action,
 585                          struct rte_flow_error *error)
 586 {
 587         const struct rte_flow_action_set_mac *conf =
 588                 (const struct rte_flow_action_set_mac *)(action->conf);
 589         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 590         struct rte_flow_item_eth eth;
 591         struct rte_flow_item_eth eth_mask;
 592
 593         memset(&eth, 0, sizeof(eth));
 594         memset(&eth_mask, 0, sizeof(eth_mask));
 595         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 596                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 597                        sizeof(eth.src.addr_bytes));
 598                 memcpy(&eth_mask.src.addr_bytes,
 599                        &rte_flow_item_eth_mask.src.addr_bytes,
 600                        sizeof(eth_mask.src.addr_bytes));
 601         } else {
 602                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 603                        sizeof(eth.dst.addr_bytes));
 604                 memcpy(&eth_mask.dst.addr_bytes,
 605                        &rte_flow_item_eth_mask.dst.addr_bytes,
 606                        sizeof(eth_mask.dst.addr_bytes));
 607         }
 608         item.spec = &eth;
 609         item.mask = &eth_mask;
 610         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 611                                              MLX5_MODIFICATION_TYPE_SET, error);
 612 }
 613
 614 /**
 615  * Convert modify-header set VLAN VID action to DV specification.
 616  *
 617  * @param[in,out] resource
 618  *   Pointer to the modify-header resource.
 619  * @param[in] action
 620  *   Pointer to action specification.
 621  * @param[out] error
 622  *   Pointer to the error structure.
 623  *
 624  * @return
 625  *   0 on success, a negative errno value otherwise and rte_errno is set.
 626  */
 627 static int
 628 flow_dv_convert_action_modify_vlan_vid
 629                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 630                          const struct rte_flow_action *action,
 631                          struct rte_flow_error *error)
 632 {
 633         const struct rte_flow_action_of_set_vlan_vid *conf =
 634                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 635         int i = resource->actions_num;
 636         struct mlx5_modification_cmd *actions = resource->actions;
 637         struct field_modify_info *field = modify_vlan_out_first_vid;
 638
 639         if (i >= MLX5_MAX_MODIFY_NUM)
 640                 return rte_flow_error_set(error, EINVAL,
 641                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 642                          "too many items to modify");
 643         actions[i] = (struct mlx5_modification_cmd) {
 644                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 645                 .field = field->id,
 646                 .length = field->size,
 647                 .offset = field->offset,
 648         };
 649         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 650         actions[i].data1 = conf->vlan_vid;
 651         actions[i].data1 = actions[i].data1 << 16;
 652         resource->actions_num = ++i;
 653         return 0;
 654 }
 655
 656 /**
 657  * Convert modify-header set TP action to DV specification.
 658  *
 659  * @param[in,out] resource
 660  *   Pointer to the modify-header resource.
 661  * @param[in] action
 662  *   Pointer to action specification.
 663  * @param[in] items
 664  *   Pointer to rte_flow_item objects list.
 665  * @param[in] attr
 666  *   Pointer to flow attributes structure.
 667  * @param[in] dev_flow
 668  *   Pointer to the sub flow.
 669  * @param[in] tunnel_decap
 670  *   Whether action is after tunnel decapsulation.
 671  * @param[out] error
 672  *   Pointer to the error structure.
 673  *
 674  * @return
 675  *   0 on success, a negative errno value otherwise and rte_errno is set.
 676  */
 677 static int
 678 flow_dv_convert_action_modify_tp
 679                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 680                          const struct rte_flow_action *action,
 681                          const struct rte_flow_item *items,
 682                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 683                          bool tunnel_decap, struct rte_flow_error *error)
 684 {
 685         const struct rte_flow_action_set_tp *conf =
 686                 (const struct rte_flow_action_set_tp *)(action->conf);
 687         struct rte_flow_item item;
 688         struct rte_flow_item_udp udp;
 689         struct rte_flow_item_udp udp_mask;
 690         struct rte_flow_item_tcp tcp;
 691         struct rte_flow_item_tcp tcp_mask;
 692         struct field_modify_info *field;
 693
 694         if (!attr->valid)
 695                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 696         if (attr->udp) {
 697                 memset(&udp, 0, sizeof(udp));
 698                 memset(&udp_mask, 0, sizeof(udp_mask));
 699                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 700                         udp.hdr.src_port = conf->port;
 701                         udp_mask.hdr.src_port =
 702                                         rte_flow_item_udp_mask.hdr.src_port;
 703                 } else {
 704                         udp.hdr.dst_port = conf->port;
 705                         udp_mask.hdr.dst_port =
 706                                         rte_flow_item_udp_mask.hdr.dst_port;
 707                 }
 708                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 709                 item.spec = &udp;
 710                 item.mask = &udp_mask;
 711                 field = modify_udp;
 712         } else {
 713                 MLX5_ASSERT(attr->tcp);
 714                 memset(&tcp, 0, sizeof(tcp));
 715                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 716                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 717                         tcp.hdr.src_port = conf->port;
 718                         tcp_mask.hdr.src_port =
 719                                         rte_flow_item_tcp_mask.hdr.src_port;
 720                 } else {
 721                         tcp.hdr.dst_port = conf->port;
 722                         tcp_mask.hdr.dst_port =
 723                                         rte_flow_item_tcp_mask.hdr.dst_port;
 724                 }
 725                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 726                 item.spec = &tcp;
 727                 item.mask = &tcp_mask;
 728                 field = modify_tcp;
 729         }
 730         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 731                                              MLX5_MODIFICATION_TYPE_SET, error);
 732 }
 733
 734 /**
 735  * Convert modify-header set TTL action to DV specification.
 736  *
 737  * @param[in,out] resource
 738  *   Pointer to the modify-header resource.
 739  * @param[in] action
 740  *   Pointer to action specification.
 741  * @param[in] items
 742  *   Pointer to rte_flow_item objects list.
 743  * @param[in] attr
 744  *   Pointer to flow attributes structure.
 745  * @param[in] dev_flow
 746  *   Pointer to the sub flow.
 747  * @param[in] tunnel_decap
 748  *   Whether action is after tunnel decapsulation.
 749  * @param[out] error
 750  *   Pointer to the error structure.
 751  *
 752  * @return
 753  *   0 on success, a negative errno value otherwise and rte_errno is set.
 754  */
 755 static int
 756 flow_dv_convert_action_modify_ttl
 757                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 758                          const struct rte_flow_action *action,
 759                          const struct rte_flow_item *items,
 760                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 761                          bool tunnel_decap, struct rte_flow_error *error)
 762 {
 763         const struct rte_flow_action_set_ttl *conf =
 764                 (const struct rte_flow_action_set_ttl *)(action->conf);
 765         struct rte_flow_item item;
 766         struct rte_flow_item_ipv4 ipv4;
 767         struct rte_flow_item_ipv4 ipv4_mask;
 768         struct rte_flow_item_ipv6 ipv6;
 769         struct rte_flow_item_ipv6 ipv6_mask;
 770         struct field_modify_info *field;
 771
 772         if (!attr->valid)
 773                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 774         if (attr->ipv4) {
 775                 memset(&ipv4, 0, sizeof(ipv4));
 776                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 777                 ipv4.hdr.time_to_live = conf->ttl_value;
 778                 ipv4_mask.hdr.time_to_live = 0xFF;
 779                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 780                 item.spec = &ipv4;
 781                 item.mask = &ipv4_mask;
 782                 field = modify_ipv4;
 783         } else {
 784                 MLX5_ASSERT(attr->ipv6);
 785                 memset(&ipv6, 0, sizeof(ipv6));
 786                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 787                 ipv6.hdr.hop_limits = conf->ttl_value;
 788                 ipv6_mask.hdr.hop_limits = 0xFF;
 789                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 790                 item.spec = &ipv6;
 791                 item.mask = &ipv6_mask;
 792                 field = modify_ipv6;
 793         }
 794         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 795                                              MLX5_MODIFICATION_TYPE_SET, error);
 796 }
 797
 798 /**
 799  * Convert modify-header decrement TTL action to DV specification.
 800  *
 801  * @param[in,out] resource
 802  *   Pointer to the modify-header resource.
 803  * @param[in] action
 804  *   Pointer to action specification.
 805  * @param[in] items
 806  *   Pointer to rte_flow_item objects list.
 807  * @param[in] attr
 808  *   Pointer to flow attributes structure.
 809  * @param[in] dev_flow
 810  *   Pointer to the sub flow.
 811  * @param[in] tunnel_decap
 812  *   Whether action is after tunnel decapsulation.
 813  * @param[out] error
 814  *   Pointer to the error structure.
 815  *
 816  * @return
 817  *   0 on success, a negative errno value otherwise and rte_errno is set.
 818  */
 819 static int
 820 flow_dv_convert_action_modify_dec_ttl
 821                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 822                          const struct rte_flow_item *items,
 823                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 824                          bool tunnel_decap, struct rte_flow_error *error)
 825 {
 826         struct rte_flow_item item;
 827         struct rte_flow_item_ipv4 ipv4;
 828         struct rte_flow_item_ipv4 ipv4_mask;
 829         struct rte_flow_item_ipv6 ipv6;
 830         struct rte_flow_item_ipv6 ipv6_mask;
 831         struct field_modify_info *field;
 832
 833         if (!attr->valid)
 834                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 835         if (attr->ipv4) {
 836                 memset(&ipv4, 0, sizeof(ipv4));
 837                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 838                 ipv4.hdr.time_to_live = 0xFF;
 839                 ipv4_mask.hdr.time_to_live = 0xFF;
 840                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 841                 item.spec = &ipv4;
 842                 item.mask = &ipv4_mask;
 843                 field = modify_ipv4;
 844         } else {
 845                 MLX5_ASSERT(attr->ipv6);
 846                 memset(&ipv6, 0, sizeof(ipv6));
 847                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 848                 ipv6.hdr.hop_limits = 0xFF;
 849                 ipv6_mask.hdr.hop_limits = 0xFF;
 850                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 851                 item.spec = &ipv6;
 852                 item.mask = &ipv6_mask;
 853                 field = modify_ipv6;
 854         }
 855         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 856                                              MLX5_MODIFICATION_TYPE_ADD, error);
 857 }
 858
 859 /**
 860  * Convert modify-header increment/decrement TCP Sequence number
 861  * to DV specification.
 862  *
 863  * @param[in,out] resource
 864  *   Pointer to the modify-header resource.
 865  * @param[in] action
 866  *   Pointer to action specification.
 867  * @param[out] error
 868  *   Pointer to the error structure.
 869  *
 870  * @return
 871  *   0 on success, a negative errno value otherwise and rte_errno is set.
 872  */
 873 static int
 874 flow_dv_convert_action_modify_tcp_seq
 875                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 876                          const struct rte_flow_action *action,
 877                          struct rte_flow_error *error)
 878 {
 879         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 880         uint64_t value = rte_be_to_cpu_32(*conf);
 881         struct rte_flow_item item;
 882         struct rte_flow_item_tcp tcp;
 883         struct rte_flow_item_tcp tcp_mask;
 884
 885         memset(&tcp, 0, sizeof(tcp));
 886         memset(&tcp_mask, 0, sizeof(tcp_mask));
 887         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 888                 /*
 889                  * The HW has no decrement operation, only increment operation.
 890                  * To simulate decrement X from Y using increment operation
 891                  * we need to add UINT32_MAX X times to Y.
 892                  * Each adding of UINT32_MAX decrements Y by 1.
 893                  */
 894                 value *= UINT32_MAX;
 895         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 896         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 897         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 898         item.spec = &tcp;
 899         item.mask = &tcp_mask;
 900         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 901                                              MLX5_MODIFICATION_TYPE_ADD, error);
 902 }
 903
 904 /**
 905  * Convert modify-header increment/decrement TCP Acknowledgment number
 906  * to DV specification.
 907  *
 908  * @param[in,out] resource
 909  *   Pointer to the modify-header resource.
 910  * @param[in] action
 911  *   Pointer to action specification.
 912  * @param[out] error
 913  *   Pointer to the error structure.
 914  *
 915  * @return
 916  *   0 on success, a negative errno value otherwise and rte_errno is set.
 917  */
 918 static int
 919 flow_dv_convert_action_modify_tcp_ack
 920                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 921                          const struct rte_flow_action *action,
 922                          struct rte_flow_error *error)
 923 {
 924         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 925         uint64_t value = rte_be_to_cpu_32(*conf);
 926         struct rte_flow_item item;
 927         struct rte_flow_item_tcp tcp;
 928         struct rte_flow_item_tcp tcp_mask;
 929
 930         memset(&tcp, 0, sizeof(tcp));
 931         memset(&tcp_mask, 0, sizeof(tcp_mask));
 932         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 933                 /*
 934                  * The HW has no decrement operation, only increment operation.
 935                  * To simulate decrement X from Y using increment operation
 936                  * we need to add UINT32_MAX X times to Y.
 937                  * Each adding of UINT32_MAX decrements Y by 1.
 938                  */
 939                 value *= UINT32_MAX;
 940         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 941         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 942         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 943         item.spec = &tcp;
 944         item.mask = &tcp_mask;
 945         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 946                                              MLX5_MODIFICATION_TYPE_ADD, error);
 947 }
 948
 949 static enum mlx5_modification_field reg_to_field[] = {
 950         [REG_NONE] = MLX5_MODI_OUT_NONE,
 951         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 952         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 953         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 954         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 955         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 956         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 957         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 958         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 959         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 960         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 961 };
 962
 963 /**
 964  * Convert register set to DV specification.
 965  *
 966  * @param[in,out] resource
 967  *   Pointer to the modify-header resource.
 968  * @param[in] action
 969  *   Pointer to action specification.
 970  * @param[out] error
 971  *   Pointer to the error structure.
 972  *
 973  * @return
 974  *   0 on success, a negative errno value otherwise and rte_errno is set.
 975  */
 976 static int
 977 flow_dv_convert_action_set_reg
 978                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 979                          const struct rte_flow_action *action,
 980                          struct rte_flow_error *error)
 981 {
 982         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 983         struct mlx5_modification_cmd *actions = resource->actions;
 984         uint32_t i = resource->actions_num;
 985
 986         if (i >= MLX5_MAX_MODIFY_NUM)
 987                 return rte_flow_error_set(error, EINVAL,
 988                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 989                                           "too many items to modify");
 990         MLX5_ASSERT(conf->id != REG_NONE);
 991         MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
 992         actions[i] = (struct mlx5_modification_cmd) {
 993                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 994                 .field = reg_to_field[conf->id],
 995         };
 996         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 997         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 998         ++i;
 999         resource->actions_num = i;
1000         return 0;
1001 }
1002
1003 /**
1004  * Convert SET_TAG action to DV specification.
1005  *
1006  * @param[in] dev
1007  *   Pointer to the rte_eth_dev structure.
1008  * @param[in,out] resource
1009  *   Pointer to the modify-header resource.
1010  * @param[in] conf
1011  *   Pointer to action specification.
1012  * @param[out] error
1013  *   Pointer to the error structure.
1014  *
1015  * @return
1016  *   0 on success, a negative errno value otherwise and rte_errno is set.
1017  */
1018 static int
1019 flow_dv_convert_action_set_tag
1020                         (struct rte_eth_dev *dev,
1021                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1022                          const struct rte_flow_action_set_tag *conf,
1023                          struct rte_flow_error *error)
1024 {
1025         rte_be32_t data = rte_cpu_to_be_32(conf->data);
1026         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1027         struct rte_flow_item item = {
1028                 .spec = &data,
1029                 .mask = &mask,
1030         };
1031         struct field_modify_info reg_c_x[] = {
1032                 [1] = {0, 0, 0},
1033         };
1034         enum mlx5_modification_field reg_type;
1035         int ret;
1036
1037         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038         if (ret < 0)
1039                 return ret;
1040         MLX5_ASSERT(ret != REG_NONE);
1041         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1042         reg_type = reg_to_field[ret];
1043         MLX5_ASSERT(reg_type > 0);
1044         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1045         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1046                                              MLX5_MODIFICATION_TYPE_SET, error);
1047 }
1048
1049 /**
1050  * Convert internal COPY_REG action to DV specification.
1051  *
1052  * @param[in] dev
1053  *   Pointer to the rte_eth_dev structure.
1054  * @param[in,out] res
1055  *   Pointer to the modify-header resource.
1056  * @param[in] action
1057  *   Pointer to action specification.
1058  * @param[out] error
1059  *   Pointer to the error structure.
1060  *
1061  * @return
1062  *   0 on success, a negative errno value otherwise and rte_errno is set.
1063  */
1064 static int
1065 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1066                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1067                                  const struct rte_flow_action *action,
1068                                  struct rte_flow_error *error)
1069 {
1070         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1071         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1072         struct rte_flow_item item = {
1073                 .spec = NULL,
1074                 .mask = &mask,
1075         };
1076         struct field_modify_info reg_src[] = {
1077                 {4, 0, reg_to_field[conf->src]},
1078                 {0, 0, 0},
1079         };
1080         struct field_modify_info reg_dst = {
1081                 .offset = 0,
1082                 .id = reg_to_field[conf->dst],
1083         };
1084         /* Adjust reg_c[0] usage according to reported mask. */
1085         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1086                 struct mlx5_priv *priv = dev->data->dev_private;
1087                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1088
1089                 MLX5_ASSERT(reg_c0);
1090                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1091                 if (conf->dst == REG_C_0) {
1092                         /* Copy to reg_c[0], within mask only. */
1093                         reg_dst.offset = rte_bsf32(reg_c0);
1094                         /*
1095                          * Mask is ignoring the enianness, because
1096                          * there is no conversion in datapath.
1097                          */
1098 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1099                         /* Copy from destination lower bits to reg_c[0]. */
1100                         mask = reg_c0 >> reg_dst.offset;
1101 #else
1102                         /* Copy from destination upper bits to reg_c[0]. */
1103                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1104                                           rte_fls_u32(reg_c0));
1105 #endif
1106                 } else {
1107                         mask = rte_cpu_to_be_32(reg_c0);
1108 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1109                         /* Copy from reg_c[0] to destination lower bits. */
1110                         reg_dst.offset = 0;
1111 #else
1112                         /* Copy from reg_c[0] to destination upper bits. */
1113                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1114                                          (rte_fls_u32(reg_c0) -
1115                                           rte_bsf32(reg_c0));
1116 #endif
1117                 }
1118         }
1119         return flow_dv_convert_modify_action(&item,
1120                                              reg_src, &reg_dst, res,
1121                                              MLX5_MODIFICATION_TYPE_COPY,
1122                                              error);
1123 }
1124
1125 /**
1126  * Convert MARK action to DV specification. This routine is used
1127  * in extensive metadata only and requires metadata register to be
1128  * handled. In legacy mode hardware tag resource is engaged.
1129  *
1130  * @param[in] dev
1131  *   Pointer to the rte_eth_dev structure.
1132  * @param[in] conf
1133  *   Pointer to MARK action specification.
1134  * @param[in,out] resource
1135  *   Pointer to the modify-header resource.
1136  * @param[out] error
1137  *   Pointer to the error structure.
1138  *
1139  * @return
1140  *   0 on success, a negative errno value otherwise and rte_errno is set.
1141  */
1142 static int
1143 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1144                             const struct rte_flow_action_mark *conf,
1145                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1146                             struct rte_flow_error *error)
1147 {
1148         struct mlx5_priv *priv = dev->data->dev_private;
1149         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1150                                            priv->sh->dv_mark_mask);
1151         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1152         struct rte_flow_item item = {
1153                 .spec = &data,
1154                 .mask = &mask,
1155         };
1156         struct field_modify_info reg_c_x[] = {
1157                 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1158                 {0, 0, 0},
1159         };
1160         int reg;
1161
1162         if (!mask)
1163                 return rte_flow_error_set(error, EINVAL,
1164                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1165                                           NULL, "zero mark action mask");
1166         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167         if (reg < 0)
1168                 return reg;
1169         MLX5_ASSERT(reg > 0);
1170         if (reg == REG_C_0) {
1171                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1172                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1173
1174                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1175                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1176                 mask = rte_cpu_to_be_32(mask << shl_c0);
1177         }
1178         reg_c_x[0].id = reg_to_field[reg];
1179         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1180                                              MLX5_MODIFICATION_TYPE_SET, error);
1181 }
1182
1183 /**
1184  * Get metadata register index for specified steering domain.
1185  *
1186  * @param[in] dev
1187  *   Pointer to the rte_eth_dev structure.
1188  * @param[in] attr
1189  *   Attributes of flow to determine steering domain.
1190  * @param[out] error
1191  *   Pointer to the error structure.
1192  *
1193  * @return
1194  *   positive index on success, a negative errno value otherwise
1195  *   and rte_errno is set.
1196  */
1197 static enum modify_reg
1198 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1199                          const struct rte_flow_attr *attr,
1200                          struct rte_flow_error *error)
1201 {
1202         int reg =
1203                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1204                                           MLX5_METADATA_FDB :
1205                                             attr->egress ?
1206                                             MLX5_METADATA_TX :
1207                                             MLX5_METADATA_RX, 0, error);
1208         if (reg < 0)
1209                 return rte_flow_error_set(error,
1210                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1211                                           NULL, "unavailable "
1212                                           "metadata register");
1213         return reg;
1214 }
1215
1216 /**
1217  * Convert SET_META action to DV specification.
1218  *
1219  * @param[in] dev
1220  *   Pointer to the rte_eth_dev structure.
1221  * @param[in,out] resource
1222  *   Pointer to the modify-header resource.
1223  * @param[in] attr
1224  *   Attributes of flow that includes this item.
1225  * @param[in] conf
1226  *   Pointer to action specification.
1227  * @param[out] error
1228  *   Pointer to the error structure.
1229  *
1230  * @return
1231  *   0 on success, a negative errno value otherwise and rte_errno is set.
1232  */
1233 static int
1234 flow_dv_convert_action_set_meta
1235                         (struct rte_eth_dev *dev,
1236                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1237                          const struct rte_flow_attr *attr,
1238                          const struct rte_flow_action_set_meta *conf,
1239                          struct rte_flow_error *error)
1240 {
1241         uint32_t data = conf->data;
1242         uint32_t mask = conf->mask;
1243         struct rte_flow_item item = {
1244                 .spec = &data,
1245                 .mask = &mask,
1246         };
1247         struct field_modify_info reg_c_x[] = {
1248                 [1] = {0, 0, 0},
1249         };
1250         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1251
1252         if (reg < 0)
1253                 return reg;
1254         /*
1255          * In datapath code there is no endianness
1256          * coversions for perfromance reasons, all
1257          * pattern conversions are done in rte_flow.
1258          */
1259         if (reg == REG_C_0) {
1260                 struct mlx5_priv *priv = dev->data->dev_private;
1261                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262                 uint32_t shl_c0;
1263
1264                 MLX5_ASSERT(msk_c0);
1265 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1266                 shl_c0 = rte_bsf32(msk_c0);
1267 #else
1268                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1269 #endif
1270                 mask <<= shl_c0;
1271                 data <<= shl_c0;
1272                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1273         }
1274         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1275         /* The routine expects parameters in memory as big-endian ones. */
1276         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1277                                              MLX5_MODIFICATION_TYPE_SET, error);
1278 }
1279
1280 /**
1281  * Convert modify-header set IPv4 DSCP action to DV specification.
1282  *
1283  * @param[in,out] resource
1284  *   Pointer to the modify-header resource.
1285  * @param[in] action
1286  *   Pointer to action specification.
1287  * @param[out] error
1288  *   Pointer to the error structure.
1289  *
1290  * @return
1291  *   0 on success, a negative errno value otherwise and rte_errno is set.
1292  */
1293 static int
1294 flow_dv_convert_action_modify_ipv4_dscp
1295                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1296                          const struct rte_flow_action *action,
1297                          struct rte_flow_error *error)
1298 {
1299         const struct rte_flow_action_set_dscp *conf =
1300                 (const struct rte_flow_action_set_dscp *)(action->conf);
1301         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1302         struct rte_flow_item_ipv4 ipv4;
1303         struct rte_flow_item_ipv4 ipv4_mask;
1304
1305         memset(&ipv4, 0, sizeof(ipv4));
1306         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1307         ipv4.hdr.type_of_service = conf->dscp;
1308         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1309         item.spec = &ipv4;
1310         item.mask = &ipv4_mask;
1311         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1312                                              MLX5_MODIFICATION_TYPE_SET, error);
1313 }
1314
1315 /**
1316  * Convert modify-header set IPv6 DSCP action to DV specification.
1317  *
1318  * @param[in,out] resource
1319  *   Pointer to the modify-header resource.
1320  * @param[in] action
1321  *   Pointer to action specification.
1322  * @param[out] error
1323  *   Pointer to the error structure.
1324  *
1325  * @return
1326  *   0 on success, a negative errno value otherwise and rte_errno is set.
1327  */
1328 static int
1329 flow_dv_convert_action_modify_ipv6_dscp
1330                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1331                          const struct rte_flow_action *action,
1332                          struct rte_flow_error *error)
1333 {
1334         const struct rte_flow_action_set_dscp *conf =
1335                 (const struct rte_flow_action_set_dscp *)(action->conf);
1336         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1337         struct rte_flow_item_ipv6 ipv6;
1338         struct rte_flow_item_ipv6 ipv6_mask;
1339
1340         memset(&ipv6, 0, sizeof(ipv6));
1341         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1342         /*
1343          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1344          * rdma-core only accept the DSCP bits byte aligned start from
1345          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1346          * bits in IPv6 case as rdma-core requires byte aligned value.
1347          */
1348         ipv6.hdr.vtc_flow = conf->dscp;
1349         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1350         item.spec = &ipv6;
1351         item.mask = &ipv6_mask;
1352         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1353                                              MLX5_MODIFICATION_TYPE_SET, error);
1354 }
1355
1356 /**
1357  * Validate MARK item.
1358  *
1359  * @param[in] dev
1360  *   Pointer to the rte_eth_dev structure.
1361  * @param[in] item
1362  *   Item specification.
1363  * @param[in] attr
1364  *   Attributes of flow that includes this item.
1365  * @param[out] error
1366  *   Pointer to error structure.
1367  *
1368  * @return
1369  *   0 on success, a negative errno value otherwise and rte_errno is set.
1370  */
1371 static int
1372 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1373                            const struct rte_flow_item *item,
1374                            const struct rte_flow_attr *attr __rte_unused,
1375                            struct rte_flow_error *error)
1376 {
1377         struct mlx5_priv *priv = dev->data->dev_private;
1378         struct mlx5_dev_config *config = &priv->config;
1379         const struct rte_flow_item_mark *spec = item->spec;
1380         const struct rte_flow_item_mark *mask = item->mask;
1381         const struct rte_flow_item_mark nic_mask = {
1382                 .id = priv->sh->dv_mark_mask,
1383         };
1384         int ret;
1385
1386         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1387                 return rte_flow_error_set(error, ENOTSUP,
1388                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1389                                           "extended metadata feature"
1390                                           " isn't enabled");
1391         if (!mlx5_flow_ext_mreg_supported(dev))
1392                 return rte_flow_error_set(error, ENOTSUP,
1393                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1394                                           "extended metadata register"
1395                                           " isn't supported");
1396         if (!nic_mask.id)
1397                 return rte_flow_error_set(error, ENOTSUP,
1398                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1399                                           "extended metadata register"
1400                                           " isn't available");
1401         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1402         if (ret < 0)
1403                 return ret;
1404         if (!spec)
1405                 return rte_flow_error_set(error, EINVAL,
1406                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1407                                           item->spec,
1408                                           "data cannot be empty");
1409         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1410                 return rte_flow_error_set(error, EINVAL,
1411                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1412                                           &spec->id,
1413                                           "mark id exceeds the limit");
1414         if (!mask)
1415                 mask = &nic_mask;
1416         if (!mask->id)
1417                 return rte_flow_error_set(error, EINVAL,
1418                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1419                                         "mask cannot be zero");
1420
1421         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1422                                         (const uint8_t *)&nic_mask,
1423                                         sizeof(struct rte_flow_item_mark),
1424                                         error);
1425         if (ret < 0)
1426                 return ret;
1427         return 0;
1428 }
1429
1430 /**
1431  * Validate META item.
1432  *
1433  * @param[in] dev
1434  *   Pointer to the rte_eth_dev structure.
1435  * @param[in] item
1436  *   Item specification.
1437  * @param[in] attr
1438  *   Attributes of flow that includes this item.
1439  * @param[out] error
1440  *   Pointer to error structure.
1441  *
1442  * @return
1443  *   0 on success, a negative errno value otherwise and rte_errno is set.
1444  */
1445 static int
1446 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1447                            const struct rte_flow_item *item,
1448                            const struct rte_flow_attr *attr,
1449                            struct rte_flow_error *error)
1450 {
1451         struct mlx5_priv *priv = dev->data->dev_private;
1452         struct mlx5_dev_config *config = &priv->config;
1453         const struct rte_flow_item_meta *spec = item->spec;
1454         const struct rte_flow_item_meta *mask = item->mask;
1455         struct rte_flow_item_meta nic_mask = {
1456                 .data = UINT32_MAX
1457         };
1458         int reg;
1459         int ret;
1460
1461         if (!spec)
1462                 return rte_flow_error_set(error, EINVAL,
1463                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1464                                           item->spec,
1465                                           "data cannot be empty");
1466         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1467                 if (!mlx5_flow_ext_mreg_supported(dev))
1468                         return rte_flow_error_set(error, ENOTSUP,
1469                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1470                                           "extended metadata register"
1471                                           " isn't supported");
1472                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1473                 if (reg < 0)
1474                         return reg;
1475                 if (reg == REG_B)
1476                         return rte_flow_error_set(error, ENOTSUP,
1477                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1478                                           "match on reg_b "
1479                                           "isn't supported");
1480                 if (reg != REG_A)
1481                         nic_mask.data = priv->sh->dv_meta_mask;
1482         }
1483         if (!mask)
1484                 mask = &rte_flow_item_meta_mask;
1485         if (!mask->data)
1486                 return rte_flow_error_set(error, EINVAL,
1487                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1488                                         "mask cannot be zero");
1489
1490         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1491                                         (const uint8_t *)&nic_mask,
1492                                         sizeof(struct rte_flow_item_meta),
1493                                         error);
1494         return ret;
1495 }
1496
1497 /**
1498  * Validate TAG item.
1499  *
1500  * @param[in] dev
1501  *   Pointer to the rte_eth_dev structure.
1502  * @param[in] item
1503  *   Item specification.
1504  * @param[in] attr
1505  *   Attributes of flow that includes this item.
1506  * @param[out] error
1507  *   Pointer to error structure.
1508  *
1509  * @return
1510  *   0 on success, a negative errno value otherwise and rte_errno is set.
1511  */
1512 static int
1513 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1514                           const struct rte_flow_item *item,
1515                           const struct rte_flow_attr *attr __rte_unused,
1516                           struct rte_flow_error *error)
1517 {
1518         const struct rte_flow_item_tag *spec = item->spec;
1519         const struct rte_flow_item_tag *mask = item->mask;
1520         const struct rte_flow_item_tag nic_mask = {
1521                 .data = RTE_BE32(UINT32_MAX),
1522                 .index = 0xff,
1523         };
1524         int ret;
1525
1526         if (!mlx5_flow_ext_mreg_supported(dev))
1527                 return rte_flow_error_set(error, ENOTSUP,
1528                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1529                                           "extensive metadata register"
1530                                           " isn't supported");
1531         if (!spec)
1532                 return rte_flow_error_set(error, EINVAL,
1533                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1534                                           item->spec,
1535                                           "data cannot be empty");
1536         if (!mask)
1537                 mask = &rte_flow_item_tag_mask;
1538         if (!mask->data)
1539                 return rte_flow_error_set(error, EINVAL,
1540                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1541                                         "mask cannot be zero");
1542
1543         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1544                                         (const uint8_t *)&nic_mask,
1545                                         sizeof(struct rte_flow_item_tag),
1546                                         error);
1547         if (ret < 0)
1548                 return ret;
1549         if (mask->index != 0xff)
1550                 return rte_flow_error_set(error, EINVAL,
1551                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1552                                           "partial mask for tag index"
1553                                           " is not supported");
1554         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1555         if (ret < 0)
1556                 return ret;
1557         MLX5_ASSERT(ret != REG_NONE);
1558         return 0;
1559 }
1560
1561 /**
1562  * Validate vport item.
1563  *
1564  * @param[in] dev
1565  *   Pointer to the rte_eth_dev structure.
1566  * @param[in] item
1567  *   Item specification.
1568  * @param[in] attr
1569  *   Attributes of flow that includes this item.
1570  * @param[in] item_flags
1571  *   Bit-fields that holds the items detected until now.
1572  * @param[out] error
1573  *   Pointer to error structure.
1574  *
1575  * @return
1576  *   0 on success, a negative errno value otherwise and rte_errno is set.
1577  */
1578 static int
1579 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1580                               const struct rte_flow_item *item,
1581                               const struct rte_flow_attr *attr,
1582                               uint64_t item_flags,
1583                               struct rte_flow_error *error)
1584 {
1585         const struct rte_flow_item_port_id *spec = item->spec;
1586         const struct rte_flow_item_port_id *mask = item->mask;
1587         const struct rte_flow_item_port_id switch_mask = {
1588                         .id = 0xffffffff,
1589         };
1590         struct mlx5_priv *esw_priv;
1591         struct mlx5_priv *dev_priv;
1592         int ret;
1593
1594         if (!attr->transfer)
1595                 return rte_flow_error_set(error, EINVAL,
1596                                           RTE_FLOW_ERROR_TYPE_ITEM,
1597                                           NULL,
1598                                           "match on port id is valid only"
1599                                           " when transfer flag is enabled");
1600         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1601                 return rte_flow_error_set(error, ENOTSUP,
1602                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1603                                           "multiple source ports are not"
1604                                           " supported");
1605         if (!mask)
1606                 mask = &switch_mask;
1607         if (mask->id != 0xffffffff)
1608                 return rte_flow_error_set(error, ENOTSUP,
1609                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1610                                            mask,
1611                                            "no support for partial mask on"
1612                                            " \"id\" field");
1613         ret = mlx5_flow_item_acceptable
1614                                 (item, (const uint8_t *)mask,
1615                                  (const uint8_t *)&rte_flow_item_port_id_mask,
1616                                  sizeof(struct rte_flow_item_port_id),
1617                                  error);
1618         if (ret)
1619                 return ret;
1620         if (!spec)
1621                 return 0;
1622         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1623         if (!esw_priv)
1624                 return rte_flow_error_set(error, rte_errno,
1625                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1626                                           "failed to obtain E-Switch info for"
1627                                           " port");
1628         dev_priv = mlx5_dev_to_eswitch_info(dev);
1629         if (!dev_priv)
1630                 return rte_flow_error_set(error, rte_errno,
1631                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1632                                           NULL,
1633                                           "failed to obtain E-Switch info");
1634         if (esw_priv->domain_id != dev_priv->domain_id)
1635                 return rte_flow_error_set(error, EINVAL,
1636                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1637                                           "cannot match on a port from a"
1638                                           " different E-Switch");
1639         return 0;
1640 }
1641
1642 /**
1643  * Validate VLAN item.
1644  *
1645  * @param[in] item
1646  *   Item specification.
1647  * @param[in] item_flags
1648  *   Bit-fields that holds the items detected until now.
1649  * @param[in] dev
1650  *   Ethernet device flow is being created on.
1651  * @param[out] error
1652  *   Pointer to error structure.
1653  *
1654  * @return
1655  *   0 on success, a negative errno value otherwise and rte_errno is set.
1656  */
1657 static int
1658 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1659                            uint64_t item_flags,
1660                            struct rte_eth_dev *dev,
1661                            struct rte_flow_error *error)
1662 {
1663         const struct rte_flow_item_vlan *mask = item->mask;
1664         const struct rte_flow_item_vlan nic_mask = {
1665                 .tci = RTE_BE16(UINT16_MAX),
1666                 .inner_type = RTE_BE16(UINT16_MAX),
1667         };
1668         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1669         int ret;
1670         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1671                                         MLX5_FLOW_LAYER_INNER_L4) :
1672                                        (MLX5_FLOW_LAYER_OUTER_L3 |
1673                                         MLX5_FLOW_LAYER_OUTER_L4);
1674         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1675                                         MLX5_FLOW_LAYER_OUTER_VLAN;
1676
1677         if (item_flags & vlanm)
1678                 return rte_flow_error_set(error, EINVAL,
1679                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1680                                           "multiple VLAN layers not supported");
1681         else if ((item_flags & l34m) != 0)
1682                 return rte_flow_error_set(error, EINVAL,
1683                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1684                                           "VLAN cannot follow L3/L4 layer");
1685         if (!mask)
1686                 mask = &rte_flow_item_vlan_mask;
1687         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1688                                         (const uint8_t *)&nic_mask,
1689                                         sizeof(struct rte_flow_item_vlan),
1690                                         error);
1691         if (ret)
1692                 return ret;
1693         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1694                 struct mlx5_priv *priv = dev->data->dev_private;
1695
1696                 if (priv->vmwa_context) {
1697                         /*
1698                          * Non-NULL context means we have a virtual machine
1699                          * and SR-IOV enabled, we have to create VLAN interface
1700                          * to make hypervisor to setup E-Switch vport
1701                          * context correctly. We avoid creating the multiple
1702                          * VLAN interfaces, so we cannot support VLAN tag mask.
1703                          */
1704                         return rte_flow_error_set(error, EINVAL,
1705                                                   RTE_FLOW_ERROR_TYPE_ITEM,
1706                                                   item,
1707                                                   "VLAN tag mask is not"
1708                                                   " supported in virtual"
1709                                                   " environment");
1710                 }
1711         }
1712         return 0;
1713 }
1714
1715 /*
1716  * GTP flags are contained in 1 byte of the format:
1717  * -------------------------------------------
1718  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
1719  * |-----------------------------------------|
1720  * | value | Version | PT | Res | E | S | PN |
1721  * -------------------------------------------
1722  *
1723  * Matching is supported only for GTP flags E, S, PN.
1724  */
1725 #define MLX5_GTP_FLAGS_MASK     0x07
1726
1727 /**
1728  * Validate GTP item.
1729  *
1730  * @param[in] dev
1731  *   Pointer to the rte_eth_dev structure.
1732  * @param[in] item
1733  *   Item specification.
1734  * @param[in] item_flags
1735  *   Bit-fields that holds the items detected until now.
1736  * @param[out] error
1737  *   Pointer to error structure.
1738  *
1739  * @return
1740  *   0 on success, a negative errno value otherwise and rte_errno is set.
1741  */
1742 static int
1743 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1744                           const struct rte_flow_item *item,
1745                           uint64_t item_flags,
1746                           struct rte_flow_error *error)
1747 {
1748         struct mlx5_priv *priv = dev->data->dev_private;
1749         const struct rte_flow_item_gtp *spec = item->spec;
1750         const struct rte_flow_item_gtp *mask = item->mask;
1751         const struct rte_flow_item_gtp nic_mask = {
1752                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1753                 .msg_type = 0xff,
1754                 .teid = RTE_BE32(0xffffffff),
1755         };
1756
1757         if (!priv->config.hca_attr.tunnel_stateless_gtp)
1758                 return rte_flow_error_set(error, ENOTSUP,
1759                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1760                                           "GTP support is not enabled");
1761         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1762                 return rte_flow_error_set(error, ENOTSUP,
1763                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1764                                           "multiple tunnel layers not"
1765                                           " supported");
1766         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1767                 return rte_flow_error_set(error, EINVAL,
1768                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1769                                           "no outer UDP layer found");
1770         if (!mask)
1771                 mask = &rte_flow_item_gtp_mask;
1772         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1773                 return rte_flow_error_set(error, ENOTSUP,
1774                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1775                                           "Match is supported for GTP"
1776                                           " flags only");
1777         return mlx5_flow_item_acceptable
1778                 (item, (const uint8_t *)mask,
1779                  (const uint8_t *)&nic_mask,
1780                  sizeof(struct rte_flow_item_gtp),
1781                  error);
1782 }
1783
1784 /**
1785  * Validate the pop VLAN action.
1786  *
1787  * @param[in] dev
1788  *   Pointer to the rte_eth_dev structure.
1789  * @param[in] action_flags
1790  *   Holds the actions detected until now.
1791  * @param[in] action
1792  *   Pointer to the pop vlan action.
1793  * @param[in] item_flags
1794  *   The items found in this flow rule.
1795  * @param[in] attr
1796  *   Pointer to flow attributes.
1797  * @param[out] error
1798  *   Pointer to error structure.
1799  *
1800  * @return
1801  *   0 on success, a negative errno value otherwise and rte_errno is set.
1802  */
1803 static int
1804 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1805                                  uint64_t action_flags,
1806                                  const struct rte_flow_action *action,
1807                                  uint64_t item_flags,
1808                                  const struct rte_flow_attr *attr,
1809                                  struct rte_flow_error *error)
1810 {
1811         const struct mlx5_priv *priv = dev->data->dev_private;
1812
1813         (void)action;
1814         (void)attr;
1815         if (!priv->sh->pop_vlan_action)
1816                 return rte_flow_error_set(error, ENOTSUP,
1817                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1818                                           NULL,
1819                                           "pop vlan action is not supported");
1820         if (attr->egress)
1821                 return rte_flow_error_set(error, ENOTSUP,
1822                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1823                                           NULL,
1824                                           "pop vlan action not supported for "
1825                                           "egress");
1826         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1827                 return rte_flow_error_set(error, ENOTSUP,
1828                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1829                                           "no support for multiple VLAN "
1830                                           "actions");
1831         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1832                 return rte_flow_error_set(error, ENOTSUP,
1833                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1834                                           NULL,
1835                                           "cannot pop vlan without a "
1836                                           "match on (outer) vlan in the flow");
1837         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1838                 return rte_flow_error_set(error, EINVAL,
1839                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1840                                           "wrong action order, port_id should "
1841                                           "be after pop VLAN action");
1842         if (!attr->transfer && priv->representor)
1843                 return rte_flow_error_set(error, ENOTSUP,
1844                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1845                                           "pop vlan action for VF representor "
1846                                           "not supported on NIC table");
1847         return 0;
1848 }
1849
1850 /**
1851  * Get VLAN default info from vlan match info.
1852  *
1853  * @param[in] items
1854  *   the list of item specifications.
1855  * @param[out] vlan
1856  *   pointer VLAN info to fill to.
1857  *
1858  * @return
1859  *   0 on success, a negative errno value otherwise and rte_errno is set.
1860  */
1861 static void
1862 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1863                                   struct rte_vlan_hdr *vlan)
1864 {
1865         const struct rte_flow_item_vlan nic_mask = {
1866                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1867                                 MLX5DV_FLOW_VLAN_VID_MASK),
1868                 .inner_type = RTE_BE16(0xffff),
1869         };
1870
1871         if (items == NULL)
1872                 return;
1873         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1874                 int type = items->type;
1875
1876                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1877                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1878                         break;
1879         }
1880         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1881                 const struct rte_flow_item_vlan *vlan_m = items->mask;
1882                 const struct rte_flow_item_vlan *vlan_v = items->spec;
1883
1884                 /* If VLAN item in pattern doesn't contain data, return here. */
1885                 if (!vlan_v)
1886                         return;
1887                 if (!vlan_m)
1888                         vlan_m = &nic_mask;
1889                 /* Only full match values are accepted */
1890                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1891                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1892                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1893                         vlan->vlan_tci |=
1894                                 rte_be_to_cpu_16(vlan_v->tci &
1895                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1896                 }
1897                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1898                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1899                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1900                         vlan->vlan_tci |=
1901                                 rte_be_to_cpu_16(vlan_v->tci &
1902                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
1903                 }
1904                 if (vlan_m->inner_type == nic_mask.inner_type)
1905                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1906                                                            vlan_m->inner_type);
1907         }
1908 }
1909
1910 /**
1911  * Validate the push VLAN action.
1912  *
1913  * @param[in] dev
1914  *   Pointer to the rte_eth_dev structure.
1915  * @param[in] action_flags
1916  *   Holds the actions detected until now.
1917  * @param[in] item_flags
1918  *   The items found in this flow rule.
1919  * @param[in] action
1920  *   Pointer to the action structure.
1921  * @param[in] attr
1922  *   Pointer to flow attributes
1923  * @param[out] error
1924  *   Pointer to error structure.
1925  *
1926  * @return
1927  *   0 on success, a negative errno value otherwise and rte_errno is set.
1928  */
1929 static int
1930 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1931                                   uint64_t action_flags,
1932                                   const struct rte_flow_item_vlan *vlan_m,
1933                                   const struct rte_flow_action *action,
1934                                   const struct rte_flow_attr *attr,
1935                                   struct rte_flow_error *error)
1936 {
1937         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1938         const struct mlx5_priv *priv = dev->data->dev_private;
1939
1940         if (!attr->transfer && attr->ingress)
1941                 return rte_flow_error_set(error, ENOTSUP,
1942                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1943                                           NULL,
1944                                           "push VLAN action not supported for "
1945                                           "ingress");
1946         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1947             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1948                 return rte_flow_error_set(error, EINVAL,
1949                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1950                                           "invalid vlan ethertype");
1951         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1952                 return rte_flow_error_set(error, ENOTSUP,
1953                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1954                                           "no support for multiple VLAN "
1955                                           "actions");
1956         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1957                 return rte_flow_error_set(error, EINVAL,
1958                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1959                                           "wrong action order, port_id should "
1960                                           "be after push VLAN");
1961         if (!attr->transfer && priv->representor)
1962                 return rte_flow_error_set(error, ENOTSUP,
1963                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1964                                           "push vlan action for VF representor "
1965                                           "not supported on NIC table");
1966         if (vlan_m &&
1967             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1968             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1969                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1970             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1971             !(mlx5_flow_find_action
1972                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1973                 return rte_flow_error_set(error, EINVAL,
1974                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1975                                           "not full match mask on VLAN PCP and "
1976                                           "there is no of_set_vlan_pcp action, "
1977                                           "push VLAN action cannot figure out "
1978                                           "PCP value");
1979         if (vlan_m &&
1980             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1981             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1982                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1983             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1984             !(mlx5_flow_find_action
1985                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1986                 return rte_flow_error_set(error, EINVAL,
1987                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
1988                                           "not full match mask on VLAN VID and "
1989                                           "there is no of_set_vlan_vid action, "
1990                                           "push VLAN action cannot figure out "
1991                                           "VID value");
1992         (void)attr;
1993         return 0;
1994 }
1995
1996 /**
1997  * Validate the set VLAN PCP.
1998  *
1999  * @param[in] action_flags
2000  *   Holds the actions detected until now.
2001  * @param[in] actions
2002  *   Pointer to the list of actions remaining in the flow rule.
2003  * @param[out] error
2004  *   Pointer to error structure.
2005  *
2006  * @return
2007  *   0 on success, a negative errno value otherwise and rte_errno is set.
2008  */
2009 static int
2010 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2011                                      const struct rte_flow_action actions[],
2012                                      struct rte_flow_error *error)
2013 {
2014         const struct rte_flow_action *action = actions;
2015         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2016
2017         if (conf->vlan_pcp > 7)
2018                 return rte_flow_error_set(error, EINVAL,
2019                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2020                                           "VLAN PCP value is too big");
2021         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2022                 return rte_flow_error_set(error, ENOTSUP,
2023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2024                                           "set VLAN PCP action must follow "
2025                                           "the push VLAN action");
2026         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2027                 return rte_flow_error_set(error, ENOTSUP,
2028                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2029                                           "Multiple VLAN PCP modification are "
2030                                           "not supported");
2031         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2032                 return rte_flow_error_set(error, EINVAL,
2033                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2034                                           "wrong action order, port_id should "
2035                                           "be after set VLAN PCP");
2036         return 0;
2037 }
2038
2039 /**
2040  * Validate the set VLAN VID.
2041  *
2042  * @param[in] item_flags
2043  *   Holds the items detected in this rule.
2044  * @param[in] action_flags
2045  *   Holds the actions detected until now.
2046  * @param[in] actions
2047  *   Pointer to the list of actions remaining in the flow rule.
2048  * @param[out] error
2049  *   Pointer to error structure.
2050  *
2051  * @return
2052  *   0 on success, a negative errno value otherwise and rte_errno is set.
2053  */
2054 static int
2055 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2056                                      uint64_t action_flags,
2057                                      const struct rte_flow_action actions[],
2058                                      struct rte_flow_error *error)
2059 {
2060         const struct rte_flow_action *action = actions;
2061         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2062
2063         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2064                 return rte_flow_error_set(error, EINVAL,
2065                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2066                                           "VLAN VID value is too big");
2067         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2068             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2069                 return rte_flow_error_set(error, ENOTSUP,
2070                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2071                                           "set VLAN VID action must follow push"
2072                                           " VLAN action or match on VLAN item");
2073         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2074                 return rte_flow_error_set(error, ENOTSUP,
2075                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2076                                           "Multiple VLAN VID modifications are "
2077                                           "not supported");
2078         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2079                 return rte_flow_error_set(error, EINVAL,
2080                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2081                                           "wrong action order, port_id should "
2082                                           "be after set VLAN VID");
2083         return 0;
2084 }
2085
2086 /*
2087  * Validate the FLAG action.
2088  *
2089  * @param[in] dev
2090  *   Pointer to the rte_eth_dev structure.
2091  * @param[in] action_flags
2092  *   Holds the actions detected until now.
2093  * @param[in] attr
2094  *   Pointer to flow attributes
2095  * @param[out] error
2096  *   Pointer to error structure.
2097  *
2098  * @return
2099  *   0 on success, a negative errno value otherwise and rte_errno is set.
2100  */
2101 static int
2102 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2103                              uint64_t action_flags,
2104                              const struct rte_flow_attr *attr,
2105                              struct rte_flow_error *error)
2106 {
2107         struct mlx5_priv *priv = dev->data->dev_private;
2108         struct mlx5_dev_config *config = &priv->config;
2109         int ret;
2110
2111         /* Fall back if no extended metadata register support. */
2112         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2113                 return mlx5_flow_validate_action_flag(action_flags, attr,
2114                                                       error);
2115         /* Extensive metadata mode requires registers. */
2116         if (!mlx5_flow_ext_mreg_supported(dev))
2117                 return rte_flow_error_set(error, ENOTSUP,
2118                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2119                                           "no metadata registers "
2120                                           "to support flag action");
2121         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2122                 return rte_flow_error_set(error, ENOTSUP,
2123                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2124                                           "extended metadata register"
2125                                           " isn't available");
2126         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2127         if (ret < 0)
2128                 return ret;
2129         MLX5_ASSERT(ret > 0);
2130         if (action_flags & MLX5_FLOW_ACTION_MARK)
2131                 return rte_flow_error_set(error, EINVAL,
2132                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2133                                           "can't mark and flag in same flow");
2134         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2135                 return rte_flow_error_set(error, EINVAL,
2136                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137                                           "can't have 2 flag"
2138                                           " actions in same flow");
2139         return 0;
2140 }
2141
2142 /**
2143  * Validate MARK action.
2144  *
2145  * @param[in] dev
2146  *   Pointer to the rte_eth_dev structure.
2147  * @param[in] action
2148  *   Pointer to action.
2149  * @param[in] action_flags
2150  *   Holds the actions detected until now.
2151  * @param[in] attr
2152  *   Pointer to flow attributes
2153  * @param[out] error
2154  *   Pointer to error structure.
2155  *
2156  * @return
2157  *   0 on success, a negative errno value otherwise and rte_errno is set.
2158  */
2159 static int
2160 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2161                              const struct rte_flow_action *action,
2162                              uint64_t action_flags,
2163                              const struct rte_flow_attr *attr,
2164                              struct rte_flow_error *error)
2165 {
2166         struct mlx5_priv *priv = dev->data->dev_private;
2167         struct mlx5_dev_config *config = &priv->config;
2168         const struct rte_flow_action_mark *mark = action->conf;
2169         int ret;
2170
2171         /* Fall back if no extended metadata register support. */
2172         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2173                 return mlx5_flow_validate_action_mark(action, action_flags,
2174                                                       attr, error);
2175         /* Extensive metadata mode requires registers. */
2176         if (!mlx5_flow_ext_mreg_supported(dev))
2177                 return rte_flow_error_set(error, ENOTSUP,
2178                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2179                                           "no metadata registers "
2180                                           "to support mark action");
2181         if (!priv->sh->dv_mark_mask)
2182                 return rte_flow_error_set(error, ENOTSUP,
2183                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2184                                           "extended metadata register"
2185                                           " isn't available");
2186         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2187         if (ret < 0)
2188                 return ret;
2189         MLX5_ASSERT(ret > 0);
2190         if (!mark)
2191                 return rte_flow_error_set(error, EINVAL,
2192                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2193                                           "configuration cannot be null");
2194         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2195                 return rte_flow_error_set(error, EINVAL,
2196                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2197                                           &mark->id,
2198                                           "mark id exceeds the limit");
2199         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2200                 return rte_flow_error_set(error, EINVAL,
2201                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2202                                           "can't flag and mark in same flow");
2203         if (action_flags & MLX5_FLOW_ACTION_MARK)
2204                 return rte_flow_error_set(error, EINVAL,
2205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206                                           "can't have 2 mark actions in same"
2207                                           " flow");
2208         return 0;
2209 }
2210
2211 /**
2212  * Validate SET_META action.
2213  *
2214  * @param[in] dev
2215  *   Pointer to the rte_eth_dev structure.
2216  * @param[in] action
2217  *   Pointer to the action structure.
2218  * @param[in] action_flags
2219  *   Holds the actions detected until now.
2220  * @param[in] attr
2221  *   Pointer to flow attributes
2222  * @param[out] error
2223  *   Pointer to error structure.
2224  *
2225  * @return
2226  *   0 on success, a negative errno value otherwise and rte_errno is set.
2227  */
2228 static int
2229 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2230                                  const struct rte_flow_action *action,
2231                                  uint64_t action_flags __rte_unused,
2232                                  const struct rte_flow_attr *attr,
2233                                  struct rte_flow_error *error)
2234 {
2235         const struct rte_flow_action_set_meta *conf;
2236         uint32_t nic_mask = UINT32_MAX;
2237         int reg;
2238
2239         if (!mlx5_flow_ext_mreg_supported(dev))
2240                 return rte_flow_error_set(error, ENOTSUP,
2241                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2242                                           "extended metadata register"
2243                                           " isn't supported");
2244         reg = flow_dv_get_metadata_reg(dev, attr, error);
2245         if (reg < 0)
2246                 return reg;
2247         if (reg != REG_A && reg != REG_B) {
2248                 struct mlx5_priv *priv = dev->data->dev_private;
2249
2250                 nic_mask = priv->sh->dv_meta_mask;
2251         }
2252         if (!(action->conf))
2253                 return rte_flow_error_set(error, EINVAL,
2254                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2255                                           "configuration cannot be null");
2256         conf = (const struct rte_flow_action_set_meta *)action->conf;
2257         if (!conf->mask)
2258                 return rte_flow_error_set(error, EINVAL,
2259                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2260                                           "zero mask doesn't have any effect");
2261         if (conf->mask & ~nic_mask)
2262                 return rte_flow_error_set(error, EINVAL,
2263                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2264                                           "meta data must be within reg C0");
2265         return 0;
2266 }
2267
2268 /**
2269  * Validate SET_TAG action.
2270  *
2271  * @param[in] dev
2272  *   Pointer to the rte_eth_dev structure.
2273  * @param[in] action
2274  *   Pointer to the action structure.
2275  * @param[in] action_flags
2276  *   Holds the actions detected until now.
2277  * @param[in] attr
2278  *   Pointer to flow attributes
2279  * @param[out] error
2280  *   Pointer to error structure.
2281  *
2282  * @return
2283  *   0 on success, a negative errno value otherwise and rte_errno is set.
2284  */
2285 static int
2286 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2287                                 const struct rte_flow_action *action,
2288                                 uint64_t action_flags,
2289                                 const struct rte_flow_attr *attr,
2290                                 struct rte_flow_error *error)
2291 {
2292         const struct rte_flow_action_set_tag *conf;
2293         const uint64_t terminal_action_flags =
2294                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2295                 MLX5_FLOW_ACTION_RSS;
2296         int ret;
2297
2298         if (!mlx5_flow_ext_mreg_supported(dev))
2299                 return rte_flow_error_set(error, ENOTSUP,
2300                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2301                                           "extensive metadata register"
2302                                           " isn't supported");
2303         if (!(action->conf))
2304                 return rte_flow_error_set(error, EINVAL,
2305                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2306                                           "configuration cannot be null");
2307         conf = (const struct rte_flow_action_set_tag *)action->conf;
2308         if (!conf->mask)
2309                 return rte_flow_error_set(error, EINVAL,
2310                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2311                                           "zero mask doesn't have any effect");
2312         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2313         if (ret < 0)
2314                 return ret;
2315         if (!attr->transfer && attr->ingress &&
2316             (action_flags & terminal_action_flags))
2317                 return rte_flow_error_set(error, EINVAL,
2318                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2319                                           "set_tag has no effect"
2320                                           " with terminal actions");
2321         return 0;
2322 }
2323
2324 /**
2325  * Validate count action.
2326  *
2327  * @param[in] dev
2328  *   Pointer to rte_eth_dev structure.
2329  * @param[out] error
2330  *   Pointer to error structure.
2331  *
2332  * @return
2333  *   0 on success, a negative errno value otherwise and rte_errno is set.
2334  */
2335 static int
2336 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2337                               struct rte_flow_error *error)
2338 {
2339         struct mlx5_priv *priv = dev->data->dev_private;
2340
2341         if (!priv->config.devx)
2342                 goto notsup_err;
2343 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2344         return 0;
2345 #endif
2346 notsup_err:
2347         return rte_flow_error_set
2348                       (error, ENOTSUP,
2349                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2350                        NULL,
2351                        "count action not supported");
2352 }
2353
2354 /**
2355  * Validate the L2 encap action.
2356  *
2357  * @param[in] dev
2358  *   Pointer to the rte_eth_dev structure.
2359  * @param[in] action_flags
2360  *   Holds the actions detected until now.
2361  * @param[in] action
2362  *   Pointer to the action structure.
2363  * @param[in] attr
2364  *   Pointer to flow attributes.
2365  * @param[out] error
2366  *   Pointer to error structure.
2367  *
2368  * @return
2369  *   0 on success, a negative errno value otherwise and rte_errno is set.
2370  */
2371 static int
2372 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2373                                  uint64_t action_flags,
2374                                  const struct rte_flow_action *action,
2375                                  const struct rte_flow_attr *attr,
2376                                  struct rte_flow_error *error)
2377 {
2378         const struct mlx5_priv *priv = dev->data->dev_private;
2379
2380         if (!(action->conf))
2381                 return rte_flow_error_set(error, EINVAL,
2382                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2383                                           "configuration cannot be null");
2384         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2385                 return rte_flow_error_set(error, EINVAL,
2386                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2387                                           "can only have a single encap action "
2388                                           "in a flow");
2389         if (!attr->transfer && priv->representor)
2390                 return rte_flow_error_set(error, ENOTSUP,
2391                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2392                                           "encap action for VF representor "
2393                                           "not supported on NIC table");
2394         return 0;
2395 }
2396
2397 /**
2398  * Validate a decap action.
2399  *
2400  * @param[in] dev
2401  *   Pointer to the rte_eth_dev structure.
2402  * @param[in] action_flags
2403  *   Holds the actions detected until now.
2404  * @param[in] attr
2405  *   Pointer to flow attributes
2406  * @param[out] error
2407  *   Pointer to error structure.
2408  *
2409  * @return
2410  *   0 on success, a negative errno value otherwise and rte_errno is set.
2411  */
2412 static int
2413 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2414                               uint64_t action_flags,
2415                               const struct rte_flow_attr *attr,
2416                               struct rte_flow_error *error)
2417 {
2418         const struct mlx5_priv *priv = dev->data->dev_private;
2419
2420         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2421                 return rte_flow_error_set(error, ENOTSUP,
2422                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2423                                           action_flags &
2424                                           MLX5_FLOW_ACTION_DECAP ? "can only "
2425                                           "have a single decap action" : "decap "
2426                                           "after encap is not supported");
2427         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2428                 return rte_flow_error_set(error, EINVAL,
2429                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2430                                           "can't have decap action after"
2431                                           " modify action");
2432         if (attr->egress)
2433                 return rte_flow_error_set(error, ENOTSUP,
2434                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2435                                           NULL,
2436                                           "decap action not supported for "
2437                                           "egress");
2438         if (!attr->transfer && priv->representor)
2439                 return rte_flow_error_set(error, ENOTSUP,
2440                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2441                                           "decap action for VF representor "
2442                                           "not supported on NIC table");
2443         return 0;
2444 }
2445
2446 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2447
2448 /**
2449  * Validate the raw encap and decap actions.
2450  *
2451  * @param[in] dev
2452  *   Pointer to the rte_eth_dev structure.
2453  * @param[in] decap
2454  *   Pointer to the decap action.
2455  * @param[in] encap
2456  *   Pointer to the encap action.
2457  * @param[in] attr
2458  *   Pointer to flow attributes
2459  * @param[in/out] action_flags
2460  *   Holds the actions detected until now.
2461  * @param[out] actions_n
2462  *   pointer to the number of actions counter.
2463  * @param[out] error
2464  *   Pointer to error structure.
2465  *
2466  * @return
2467  *   0 on success, a negative errno value otherwise and rte_errno is set.
2468  */
2469 static int
2470 flow_dv_validate_action_raw_encap_decap
2471         (struct rte_eth_dev *dev,
2472          const struct rte_flow_action_raw_decap *decap,
2473          const struct rte_flow_action_raw_encap *encap,
2474          const struct rte_flow_attr *attr, uint64_t *action_flags,
2475          int *actions_n, struct rte_flow_error *error)
2476 {
2477         const struct mlx5_priv *priv = dev->data->dev_private;
2478         int ret;
2479
2480         if (encap && (!encap->size || !encap->data))
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2483                                           "raw encap data cannot be empty");
2484         if (decap && encap) {
2485                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2486                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2487                         /* L3 encap. */
2488                         decap = NULL;
2489                 else if (encap->size <=
2490                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2491                            decap->size >
2492                            MLX5_ENCAPSULATION_DECISION_SIZE)
2493                         /* L3 decap. */
2494                         encap = NULL;
2495                 else if (encap->size >
2496                            MLX5_ENCAPSULATION_DECISION_SIZE &&
2497                            decap->size >
2498                            MLX5_ENCAPSULATION_DECISION_SIZE)
2499                         /* 2 L2 actions: encap and decap. */
2500                         ;
2501                 else
2502                         return rte_flow_error_set(error,
2503                                 ENOTSUP,
2504                                 RTE_FLOW_ERROR_TYPE_ACTION,
2505                                 NULL, "unsupported too small "
2506                                 "raw decap and too small raw "
2507                                 "encap combination");
2508         }
2509         if (decap) {
2510                 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2511                                                     error);
2512                 if (ret < 0)
2513                         return ret;
2514                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2515                 ++(*actions_n);
2516         }
2517         if (encap) {
2518                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2519                         return rte_flow_error_set(error, ENOTSUP,
2520                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2521                                                   NULL,
2522                                                   "small raw encap size");
2523                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2524                         return rte_flow_error_set(error, EINVAL,
2525                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2526                                                   NULL,
2527                                                   "more than one encap action");
2528                 if (!attr->transfer && priv->representor)
2529                         return rte_flow_error_set
2530                                         (error, ENOTSUP,
2531                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2532                                          "encap action for VF representor "
2533                                          "not supported on NIC table");
2534                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2535                 ++(*actions_n);
2536         }
2537         return 0;
2538 }
2539
2540 /**
2541  * Find existing encap/decap resource or create and register a new one.
2542  *
2543  * @param[in, out] dev
2544  *   Pointer to rte_eth_dev structure.
2545  * @param[in, out] resource
2546  *   Pointer to encap/decap resource.
2547  * @parm[in, out] dev_flow
2548  *   Pointer to the dev_flow.
2549  * @param[out] error
2550  *   pointer to error structure.
2551  *
2552  * @return
2553  *   0 on success otherwise -errno and errno is set.
2554  */
2555 static int
2556 flow_dv_encap_decap_resource_register
2557                         (struct rte_eth_dev *dev,
2558                          struct mlx5_flow_dv_encap_decap_resource *resource,
2559                          struct mlx5_flow *dev_flow,
2560                          struct rte_flow_error *error)
2561 {
2562         struct mlx5_priv *priv = dev->data->dev_private;
2563         struct mlx5_dev_ctx_shared *sh = priv->sh;
2564         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2565         struct mlx5dv_dr_domain *domain;
2566         uint32_t idx = 0;
2567
2568         resource->flags = dev_flow->dv.group ? 0 : 1;
2569         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2570                 domain = sh->fdb_domain;
2571         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2572                 domain = sh->rx_domain;
2573         else
2574                 domain = sh->tx_domain;
2575         /* Lookup a matching resource from cache. */
2576         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2577                       cache_resource, next) {
2578                 if (resource->reformat_type == cache_resource->reformat_type &&
2579                     resource->ft_type == cache_resource->ft_type &&
2580                     resource->flags == cache_resource->flags &&
2581                     resource->size == cache_resource->size &&
2582                     !memcmp((const void *)resource->buf,
2583                             (const void *)cache_resource->buf,
2584                             resource->size)) {
2585                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2586                                 (void *)cache_resource,
2587                                 rte_atomic32_read(&cache_resource->refcnt));
2588                         rte_atomic32_inc(&cache_resource->refcnt);
2589                         dev_flow->handle->dvh.rix_encap_decap = idx;
2590                         dev_flow->dv.encap_decap = cache_resource;
2591                         return 0;
2592                 }
2593         }
2594         /* Register new encap/decap resource. */
2595         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2596                                        &dev_flow->handle->dvh.rix_encap_decap);
2597         if (!cache_resource)
2598                 return rte_flow_error_set(error, ENOMEM,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2600                                           "cannot allocate resource memory");
2601         *cache_resource = *resource;
2602         cache_resource->verbs_action =
2603                 mlx5_glue->dv_create_flow_action_packet_reformat
2604                         (sh->ctx, cache_resource->reformat_type,
2605                          cache_resource->ft_type, domain, cache_resource->flags,
2606                          cache_resource->size,
2607                          (cache_resource->size ? cache_resource->buf : NULL));
2608         if (!cache_resource->verbs_action) {
2609                 rte_free(cache_resource);
2610                 return rte_flow_error_set(error, ENOMEM,
2611                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2612                                           NULL, "cannot create action");
2613         }
2614         rte_atomic32_init(&cache_resource->refcnt);
2615         rte_atomic32_inc(&cache_resource->refcnt);
2616         ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2617                      dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2618                      next);
2619         dev_flow->dv.encap_decap = cache_resource;
2620         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2621                 (void *)cache_resource,
2622                 rte_atomic32_read(&cache_resource->refcnt));
2623         return 0;
2624 }
2625
2626 /**
2627  * Find existing table jump resource or create and register a new one.
2628  *
2629  * @param[in, out] dev
2630  *   Pointer to rte_eth_dev structure.
2631  * @param[in, out] tbl
2632  *   Pointer to flow table resource.
2633  * @parm[in, out] dev_flow
2634  *   Pointer to the dev_flow.
2635  * @param[out] error
2636  *   pointer to error structure.
2637  *
2638  * @return
2639  *   0 on success otherwise -errno and errno is set.
2640  */
2641 static int
2642 flow_dv_jump_tbl_resource_register
2643                         (struct rte_eth_dev *dev __rte_unused,
2644                          struct mlx5_flow_tbl_resource *tbl,
2645                          struct mlx5_flow *dev_flow,
2646                          struct rte_flow_error *error)
2647 {
2648         struct mlx5_flow_tbl_data_entry *tbl_data =
2649                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2650         int cnt;
2651
2652         MLX5_ASSERT(tbl);
2653         cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2654         if (!cnt) {
2655                 tbl_data->jump.action =
2656                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
2657                         (tbl->obj);
2658                 if (!tbl_data->jump.action)
2659                         return rte_flow_error_set(error, ENOMEM,
2660                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2661                                         NULL, "cannot create jump action");
2662                 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2663                         (void *)&tbl_data->jump, cnt);
2664         } else {
2665                 /* old jump should not make the table ref++. */
2666                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2667                 MLX5_ASSERT(tbl_data->jump.action);
2668                 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2669                         (void *)&tbl_data->jump, cnt);
2670         }
2671         rte_atomic32_inc(&tbl_data->jump.refcnt);
2672         dev_flow->handle->rix_jump = tbl_data->idx;
2673         dev_flow->dv.jump = &tbl_data->jump;
2674         return 0;
2675 }
2676
2677 /**
2678  * Find existing table port ID resource or create and register a new one.
2679  *
2680  * @param[in, out] dev
2681  *   Pointer to rte_eth_dev structure.
2682  * @param[in, out] resource
2683  *   Pointer to port ID action resource.
2684  * @parm[in, out] dev_flow
2685  *   Pointer to the dev_flow.
2686  * @param[out] error
2687  *   pointer to error structure.
2688  *
2689  * @return
2690  *   0 on success otherwise -errno and errno is set.
2691  */
2692 static int
2693 flow_dv_port_id_action_resource_register
2694                         (struct rte_eth_dev *dev,
2695                          struct mlx5_flow_dv_port_id_action_resource *resource,
2696                          struct mlx5_flow *dev_flow,
2697                          struct rte_flow_error *error)
2698 {
2699         struct mlx5_priv *priv = dev->data->dev_private;
2700         struct mlx5_dev_ctx_shared *sh = priv->sh;
2701         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2702         uint32_t idx = 0;
2703
2704         /* Lookup a matching resource from cache. */
2705         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2706                       idx, cache_resource, next) {
2707                 if (resource->port_id == cache_resource->port_id) {
2708                         DRV_LOG(DEBUG, "port id action resource resource %p: "
2709                                 "refcnt %d++",
2710                                 (void *)cache_resource,
2711                                 rte_atomic32_read(&cache_resource->refcnt));
2712                         rte_atomic32_inc(&cache_resource->refcnt);
2713                         dev_flow->handle->rix_port_id_action = idx;
2714                         dev_flow->dv.port_id_action = cache_resource;
2715                         return 0;
2716                 }
2717         }
2718         /* Register new port id action resource. */
2719         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2720                                        &dev_flow->handle->rix_port_id_action);
2721         if (!cache_resource)
2722                 return rte_flow_error_set(error, ENOMEM,
2723                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2724                                           "cannot allocate resource memory");
2725         *cache_resource = *resource;
2726         /*
2727          * Depending on rdma_core version the glue routine calls
2728          * either mlx5dv_dr_action_create_dest_ib_port(domain, dev_port)
2729          * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2730          */
2731         cache_resource->action =
2732                 mlx5_glue->dr_create_flow_action_dest_port
2733                         (priv->sh->fdb_domain, resource->port_id);
2734         if (!cache_resource->action) {
2735                 rte_free(cache_resource);
2736                 return rte_flow_error_set(error, ENOMEM,
2737                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2738                                           NULL, "cannot create action");
2739         }
2740         rte_atomic32_init(&cache_resource->refcnt);
2741         rte_atomic32_inc(&cache_resource->refcnt);
2742         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2743                      dev_flow->handle->rix_port_id_action, cache_resource,
2744                      next);
2745         dev_flow->dv.port_id_action = cache_resource;
2746         DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2747                 (void *)cache_resource,
2748                 rte_atomic32_read(&cache_resource->refcnt));
2749         return 0;
2750 }
2751
2752 /**
2753  * Find existing push vlan resource or create and register a new one.
2754  *
2755  * @param [in, out] dev
2756  *   Pointer to rte_eth_dev structure.
2757  * @param[in, out] resource
2758  *   Pointer to port ID action resource.
2759  * @parm[in, out] dev_flow
2760  *   Pointer to the dev_flow.
2761  * @param[out] error
2762  *   pointer to error structure.
2763  *
2764  * @return
2765  *   0 on success otherwise -errno and errno is set.
2766  */
2767 static int
2768 flow_dv_push_vlan_action_resource_register
2769                        (struct rte_eth_dev *dev,
2770                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
2771                         struct mlx5_flow *dev_flow,
2772                         struct rte_flow_error *error)
2773 {
2774         struct mlx5_priv *priv = dev->data->dev_private;
2775         struct mlx5_dev_ctx_shared *sh = priv->sh;
2776         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2777         struct mlx5dv_dr_domain *domain;
2778         uint32_t idx = 0;
2779
2780         /* Lookup a matching resource from cache. */
2781         ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2782                       sh->push_vlan_action_list, idx, cache_resource, next) {
2783                 if (resource->vlan_tag == cache_resource->vlan_tag &&
2784                     resource->ft_type == cache_resource->ft_type) {
2785                         DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2786                                 "refcnt %d++",
2787                                 (void *)cache_resource,
2788                                 rte_atomic32_read(&cache_resource->refcnt));
2789                         rte_atomic32_inc(&cache_resource->refcnt);
2790                         dev_flow->handle->dvh.rix_push_vlan = idx;
2791                         dev_flow->dv.push_vlan_res = cache_resource;
2792                         return 0;
2793                 }
2794         }
2795         /* Register new push_vlan action resource. */
2796         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2797                                        &dev_flow->handle->dvh.rix_push_vlan);
2798         if (!cache_resource)
2799                 return rte_flow_error_set(error, ENOMEM,
2800                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2801                                           "cannot allocate resource memory");
2802         *cache_resource = *resource;
2803         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2804                 domain = sh->fdb_domain;
2805         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2806                 domain = sh->rx_domain;
2807         else
2808                 domain = sh->tx_domain;
2809         cache_resource->action =
2810                 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2811                                                            resource->vlan_tag);
2812         if (!cache_resource->action) {
2813                 rte_free(cache_resource);
2814                 return rte_flow_error_set(error, ENOMEM,
2815                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2816                                           NULL, "cannot create action");
2817         }
2818         rte_atomic32_init(&cache_resource->refcnt);
2819         rte_atomic32_inc(&cache_resource->refcnt);
2820         ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821                      &sh->push_vlan_action_list,
2822                      dev_flow->handle->dvh.rix_push_vlan,
2823                      cache_resource, next);
2824         dev_flow->dv.push_vlan_res = cache_resource;
2825         DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2826                 (void *)cache_resource,
2827                 rte_atomic32_read(&cache_resource->refcnt));
2828         return 0;
2829 }
2830 /**
2831  * Get the size of specific rte_flow_item_type
2832  *
2833  * @param[in] item_type
2834  *   Tested rte_flow_item_type.
2835  *
2836  * @return
2837  *   sizeof struct item_type, 0 if void or irrelevant.
2838  */
2839 static size_t
2840 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2841 {
2842         size_t retval;
2843
2844         switch (item_type) {
2845         case RTE_FLOW_ITEM_TYPE_ETH:
2846                 retval = sizeof(struct rte_flow_item_eth);
2847                 break;
2848         case RTE_FLOW_ITEM_TYPE_VLAN:
2849                 retval = sizeof(struct rte_flow_item_vlan);
2850                 break;
2851         case RTE_FLOW_ITEM_TYPE_IPV4:
2852                 retval = sizeof(struct rte_flow_item_ipv4);
2853                 break;
2854         case RTE_FLOW_ITEM_TYPE_IPV6:
2855                 retval = sizeof(struct rte_flow_item_ipv6);
2856                 break;
2857         case RTE_FLOW_ITEM_TYPE_UDP:
2858                 retval = sizeof(struct rte_flow_item_udp);
2859                 break;
2860         case RTE_FLOW_ITEM_TYPE_TCP:
2861                 retval = sizeof(struct rte_flow_item_tcp);
2862                 break;
2863         case RTE_FLOW_ITEM_TYPE_VXLAN:
2864                 retval = sizeof(struct rte_flow_item_vxlan);
2865                 break;
2866         case RTE_FLOW_ITEM_TYPE_GRE:
2867                 retval = sizeof(struct rte_flow_item_gre);
2868                 break;
2869         case RTE_FLOW_ITEM_TYPE_NVGRE:
2870                 retval = sizeof(struct rte_flow_item_nvgre);
2871                 break;
2872         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2873                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2874                 break;
2875         case RTE_FLOW_ITEM_TYPE_MPLS:
2876                 retval = sizeof(struct rte_flow_item_mpls);
2877                 break;
2878         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2879         default:
2880                 retval = 0;
2881                 break;
2882         }
2883         return retval;
2884 }
2885
2886 #define MLX5_ENCAP_IPV4_VERSION         0x40
2887 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
2888 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
2889 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
2890 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
2891 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
2892 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
2893
2894 /**
2895  * Convert the encap action data from list of rte_flow_item to raw buffer
2896  *
2897  * @param[in] items
2898  *   Pointer to rte_flow_item objects list.
2899  * @param[out] buf
2900  *   Pointer to the output buffer.
2901  * @param[out] size
2902  *   Pointer to the output buffer size.
2903  * @param[out] error
2904  *   Pointer to the error structure.
2905  *
2906  * @return
2907  *   0 on success, a negative errno value otherwise and rte_errno is set.
2908  */
2909 static int
2910 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2911                            size_t *size, struct rte_flow_error *error)
2912 {
2913         struct rte_ether_hdr *eth = NULL;
2914         struct rte_vlan_hdr *vlan = NULL;
2915         struct rte_ipv4_hdr *ipv4 = NULL;
2916         struct rte_ipv6_hdr *ipv6 = NULL;
2917         struct rte_udp_hdr *udp = NULL;
2918         struct rte_vxlan_hdr *vxlan = NULL;
2919         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2920         struct rte_gre_hdr *gre = NULL;
2921         size_t len;
2922         size_t temp_size = 0;
2923
2924         if (!items)
2925                 return rte_flow_error_set(error, EINVAL,
2926                                           RTE_FLOW_ERROR_TYPE_ACTION,
2927                                           NULL, "invalid empty data");
2928         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2929                 len = flow_dv_get_item_len(items->type);
2930                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2931                         return rte_flow_error_set(error, EINVAL,
2932                                                   RTE_FLOW_ERROR_TYPE_ACTION,
2933                                                   (void *)items->type,
2934                                                   "items total size is too big"
2935                                                   " for encap action");
2936                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2937                 switch (items->type) {
2938                 case RTE_FLOW_ITEM_TYPE_ETH:
2939                         eth = (struct rte_ether_hdr *)&buf[temp_size];
2940                         break;
2941                 case RTE_FLOW_ITEM_TYPE_VLAN:
2942                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2943                         if (!eth)
2944                                 return rte_flow_error_set(error, EINVAL,
2945                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2946                                                 (void *)items->type,
2947                                                 "eth header not found");
2948                         if (!eth->ether_type)
2949                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2950                         break;
2951                 case RTE_FLOW_ITEM_TYPE_IPV4:
2952                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2953                         if (!vlan && !eth)
2954                                 return rte_flow_error_set(error, EINVAL,
2955                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2956                                                 (void *)items->type,
2957                                                 "neither eth nor vlan"
2958                                                 " header found");
2959                         if (vlan && !vlan->eth_proto)
2960                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2961                         else if (eth && !eth->ether_type)
2962                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2963                         if (!ipv4->version_ihl)
2964                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2965                                                     MLX5_ENCAP_IPV4_IHL_MIN;
2966                         if (!ipv4->time_to_live)
2967                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2968                         break;
2969                 case RTE_FLOW_ITEM_TYPE_IPV6:
2970                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2971                         if (!vlan && !eth)
2972                                 return rte_flow_error_set(error, EINVAL,
2973                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2974                                                 (void *)items->type,
2975                                                 "neither eth nor vlan"
2976                                                 " header found");
2977                         if (vlan && !vlan->eth_proto)
2978                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2979                         else if (eth && !eth->ether_type)
2980                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2981                         if (!ipv6->vtc_flow)
2982                                 ipv6->vtc_flow =
2983                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2984                         if (!ipv6->hop_limits)
2985                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2986                         break;
2987                 case RTE_FLOW_ITEM_TYPE_UDP:
2988                         udp = (struct rte_udp_hdr *)&buf[temp_size];
2989                         if (!ipv4 && !ipv6)
2990                                 return rte_flow_error_set(error, EINVAL,
2991                                                 RTE_FLOW_ERROR_TYPE_ACTION,
2992                                                 (void *)items->type,
2993                                                 "ip header not found");
2994                         if (ipv4 && !ipv4->next_proto_id)
2995                                 ipv4->next_proto_id = IPPROTO_UDP;
2996                         else if (ipv6 && !ipv6->proto)
2997                                 ipv6->proto = IPPROTO_UDP;
2998                         break;
2999                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3000                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3001                         if (!udp)
3002                                 return rte_flow_error_set(error, EINVAL,
3003                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3004                                                 (void *)items->type,
3005                                                 "udp header not found");
3006                         if (!udp->dst_port)
3007                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3008                         if (!vxlan->vx_flags)
3009                                 vxlan->vx_flags =
3010                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3011                         break;
3012                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3013                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3014                         if (!udp)
3015                                 return rte_flow_error_set(error, EINVAL,
3016                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3017                                                 (void *)items->type,
3018                                                 "udp header not found");
3019                         if (!vxlan_gpe->proto)
3020                                 return rte_flow_error_set(error, EINVAL,
3021                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3022                                                 (void *)items->type,
3023                                                 "next protocol not found");
3024                         if (!udp->dst_port)
3025                                 udp->dst_port =
3026                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3027                         if (!vxlan_gpe->vx_flags)
3028                                 vxlan_gpe->vx_flags =
3029                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3030                         break;
3031                 case RTE_FLOW_ITEM_TYPE_GRE:
3032                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3033                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3034                         if (!gre->proto)
3035                                 return rte_flow_error_set(error, EINVAL,
3036                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3037                                                 (void *)items->type,
3038                                                 "next protocol not found");
3039                         if (!ipv4 && !ipv6)
3040                                 return rte_flow_error_set(error, EINVAL,
3041                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3042                                                 (void *)items->type,
3043                                                 "ip header not found");
3044                         if (ipv4 && !ipv4->next_proto_id)
3045                                 ipv4->next_proto_id = IPPROTO_GRE;
3046                         else if (ipv6 && !ipv6->proto)
3047                                 ipv6->proto = IPPROTO_GRE;
3048                         break;
3049                 case RTE_FLOW_ITEM_TYPE_VOID:
3050                         break;
3051                 default:
3052                         return rte_flow_error_set(error, EINVAL,
3053                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3054                                                   (void *)items->type,
3055                                                   "unsupported item type");
3056                         break;
3057                 }
3058                 temp_size += len;
3059         }
3060         *size = temp_size;
3061         return 0;
3062 }
3063
3064 static int
3065 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3066 {
3067         struct rte_ether_hdr *eth = NULL;
3068         struct rte_vlan_hdr *vlan = NULL;
3069         struct rte_ipv6_hdr *ipv6 = NULL;
3070         struct rte_udp_hdr *udp = NULL;
3071         char *next_hdr;
3072         uint16_t proto;
3073
3074         eth = (struct rte_ether_hdr *)data;
3075         next_hdr = (char *)(eth + 1);
3076         proto = RTE_BE16(eth->ether_type);
3077
3078         /* VLAN skipping */
3079         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3080                 vlan = (struct rte_vlan_hdr *)next_hdr;
3081                 proto = RTE_BE16(vlan->eth_proto);
3082                 next_hdr += sizeof(struct rte_vlan_hdr);
3083         }
3084
3085         /* HW calculates IPv4 csum. no need to proceed */
3086         if (proto == RTE_ETHER_TYPE_IPV4)
3087                 return 0;
3088
3089         /* non IPv4/IPv6 header. not supported */
3090         if (proto != RTE_ETHER_TYPE_IPV6) {
3091                 return rte_flow_error_set(error, ENOTSUP,
3092                                           RTE_FLOW_ERROR_TYPE_ACTION,
3093                                           NULL, "Cannot offload non IPv4/IPv6");
3094         }
3095
3096         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3097
3098         /* ignore non UDP */
3099         if (ipv6->proto != IPPROTO_UDP)
3100                 return 0;
3101
3102         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3103         udp->dgram_cksum = 0;
3104
3105         return 0;
3106 }
3107
3108 /**
3109  * Convert L2 encap action to DV specification.
3110  *
3111  * @param[in] dev
3112  *   Pointer to rte_eth_dev structure.
3113  * @param[in] action
3114  *   Pointer to action structure.
3115  * @param[in, out] dev_flow
3116  *   Pointer to the mlx5_flow.
3117  * @param[in] transfer
3118  *   Mark if the flow is E-Switch flow.
3119  * @param[out] error
3120  *   Pointer to the error structure.
3121  *
3122  * @return
3123  *   0 on success, a negative errno value otherwise and rte_errno is set.
3124  */
3125 static int
3126 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3127                                const struct rte_flow_action *action,
3128                                struct mlx5_flow *dev_flow,
3129                                uint8_t transfer,
3130                                struct rte_flow_error *error)
3131 {
3132         const struct rte_flow_item *encap_data;
3133         const struct rte_flow_action_raw_encap *raw_encap_data;
3134         struct mlx5_flow_dv_encap_decap_resource res = {
3135                 .reformat_type =
3136                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3137                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3138                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3139         };
3140
3141         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3142                 raw_encap_data =
3143                         (const struct rte_flow_action_raw_encap *)action->conf;
3144                 res.size = raw_encap_data->size;
3145                 memcpy(res.buf, raw_encap_data->data, res.size);
3146         } else {
3147                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3148                         encap_data =
3149                                 ((const struct rte_flow_action_vxlan_encap *)
3150                                                 action->conf)->definition;
3151                 else
3152                         encap_data =
3153                                 ((const struct rte_flow_action_nvgre_encap *)
3154                                                 action->conf)->definition;
3155                 if (flow_dv_convert_encap_data(encap_data, res.buf,
3156                                                &res.size, error))
3157                         return -rte_errno;
3158         }
3159         if (flow_dv_zero_encap_udp_csum(res.buf, error))
3160                 return -rte_errno;
3161         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3162                 return rte_flow_error_set(error, EINVAL,
3163                                           RTE_FLOW_ERROR_TYPE_ACTION,
3164                                           NULL, "can't create L2 encap action");
3165         return 0;
3166 }
3167
3168 /**
3169  * Convert L2 decap action to DV specification.
3170  *
3171  * @param[in] dev
3172  *   Pointer to rte_eth_dev structure.
3173  * @param[in, out] dev_flow
3174  *   Pointer to the mlx5_flow.
3175  * @param[in] transfer
3176  *   Mark if the flow is E-Switch flow.
3177  * @param[out] error
3178  *   Pointer to the error structure.
3179  *
3180  * @return
3181  *   0 on success, a negative errno value otherwise and rte_errno is set.
3182  */
3183 static int
3184 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3185                                struct mlx5_flow *dev_flow,
3186                                uint8_t transfer,
3187                                struct rte_flow_error *error)
3188 {
3189         struct mlx5_flow_dv_encap_decap_resource res = {
3190                 .size = 0,
3191                 .reformat_type =
3192                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3193                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3194                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3195         };
3196
3197         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3198                 return rte_flow_error_set(error, EINVAL,
3199                                           RTE_FLOW_ERROR_TYPE_ACTION,
3200                                           NULL, "can't create L2 decap action");
3201         return 0;
3202 }
3203
3204 /**
3205  * Convert raw decap/encap (L3 tunnel) action to DV specification.
3206  *
3207  * @param[in] dev
3208  *   Pointer to rte_eth_dev structure.
3209  * @param[in] action
3210  *   Pointer to action structure.
3211  * @param[in, out] dev_flow
3212  *   Pointer to the mlx5_flow.
3213  * @param[in] attr
3214  *   Pointer to the flow attributes.
3215  * @param[out] error
3216  *   Pointer to the error structure.
3217  *
3218  * @return
3219  *   0 on success, a negative errno value otherwise and rte_errno is set.
3220  */
3221 static int
3222 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3223                                 const struct rte_flow_action *action,
3224                                 struct mlx5_flow *dev_flow,
3225                                 const struct rte_flow_attr *attr,
3226                                 struct rte_flow_error *error)
3227 {
3228         const struct rte_flow_action_raw_encap *encap_data;
3229         struct mlx5_flow_dv_encap_decap_resource res;
3230
3231         memset(&res, 0, sizeof(res));
3232         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3233         res.size = encap_data->size;
3234         memcpy(res.buf, encap_data->data, res.size);
3235         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3236                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3237                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3238         if (attr->transfer)
3239                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3240         else
3241                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3242                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3243         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3244                 return rte_flow_error_set(error, EINVAL,
3245                                           RTE_FLOW_ERROR_TYPE_ACTION,
3246                                           NULL, "can't create encap action");
3247         return 0;
3248 }
3249
3250 /**
3251  * Create action push VLAN.
3252  *
3253  * @param[in] dev
3254  *   Pointer to rte_eth_dev structure.
3255  * @param[in] attr
3256  *   Pointer to the flow attributes.
3257  * @param[in] vlan
3258  *   Pointer to the vlan to push to the Ethernet header.
3259  * @param[in, out] dev_flow
3260  *   Pointer to the mlx5_flow.
3261  * @param[out] error
3262  *   Pointer to the error structure.
3263  *
3264  * @return
3265  *   0 on success, a negative errno value otherwise and rte_errno is set.
3266  */
3267 static int
3268 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3269                                 const struct rte_flow_attr *attr,
3270                                 const struct rte_vlan_hdr *vlan,
3271                                 struct mlx5_flow *dev_flow,
3272                                 struct rte_flow_error *error)
3273 {
3274         struct mlx5_flow_dv_push_vlan_action_resource res;
3275
3276         memset(&res, 0, sizeof(res));
3277         res.vlan_tag =
3278                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3279                                  vlan->vlan_tci);
3280         if (attr->transfer)
3281                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3282         else
3283                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3284                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3285         return flow_dv_push_vlan_action_resource_register
3286                                             (dev, &res, dev_flow, error);
3287 }
3288
3289 /**
3290  * Validate the modify-header actions.
3291  *
3292  * @param[in] action_flags
3293  *   Holds the actions detected until now.
3294  * @param[in] action
3295  *   Pointer to the modify action.
3296  * @param[out] error
3297  *   Pointer to error structure.
3298  *
3299  * @return
3300  *   0 on success, a negative errno value otherwise and rte_errno is set.
3301  */
3302 static int
3303 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3304                                    const struct rte_flow_action *action,
3305                                    struct rte_flow_error *error)
3306 {
3307         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3308                 return rte_flow_error_set(error, EINVAL,
3309                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3310                                           NULL, "action configuration not set");
3311         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3312                 return rte_flow_error_set(error, EINVAL,
3313                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3314                                           "can't have encap action before"
3315                                           " modify action");
3316         return 0;
3317 }
3318
3319 /**
3320  * Validate the modify-header MAC address actions.
3321  *
3322  * @param[in] action_flags
3323  *   Holds the actions detected until now.
3324  * @param[in] action
3325  *   Pointer to the modify action.
3326  * @param[in] item_flags
3327  *   Holds the items detected.
3328  * @param[out] error
3329  *   Pointer to error structure.
3330  *
3331  * @return
3332  *   0 on success, a negative errno value otherwise and rte_errno is set.
3333  */
3334 static int
3335 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3336                                    const struct rte_flow_action *action,
3337                                    const uint64_t item_flags,
3338                                    struct rte_flow_error *error)
3339 {
3340         int ret = 0;
3341
3342         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3343         if (!ret) {
3344                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3345                         return rte_flow_error_set(error, EINVAL,
3346                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3347                                                   NULL,
3348                                                   "no L2 item in pattern");
3349         }
3350         return ret;
3351 }
3352
3353 /**
3354  * Validate the modify-header IPv4 address actions.
3355  *
3356  * @param[in] action_flags
3357  *   Holds the actions detected until now.
3358  * @param[in] action
3359  *   Pointer to the modify action.
3360  * @param[in] item_flags
3361  *   Holds the items detected.
3362  * @param[out] error
3363  *   Pointer to error structure.
3364  *
3365  * @return
3366  *   0 on success, a negative errno value otherwise and rte_errno is set.
3367  */
3368 static int
3369 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3370                                     const struct rte_flow_action *action,
3371                                     const uint64_t item_flags,
3372                                     struct rte_flow_error *error)
3373 {
3374         int ret = 0;
3375         uint64_t layer;
3376
3377         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3378         if (!ret) {
3379                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3380                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3381                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3382                 if (!(item_flags & layer))
3383                         return rte_flow_error_set(error, EINVAL,
3384                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3385                                                   NULL,
3386                                                   "no ipv4 item in pattern");
3387         }
3388         return ret;
3389 }
3390
3391 /**
3392  * Validate the modify-header IPv6 address actions.
3393  *
3394  * @param[in] action_flags
3395  *   Holds the actions detected until now.
3396  * @param[in] action
3397  *   Pointer to the modify action.
3398  * @param[in] item_flags
3399  *   Holds the items detected.
3400  * @param[out] error
3401  *   Pointer to error structure.
3402  *
3403  * @return
3404  *   0 on success, a negative errno value otherwise and rte_errno is set.
3405  */
3406 static int
3407 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3408                                     const struct rte_flow_action *action,
3409                                     const uint64_t item_flags,
3410                                     struct rte_flow_error *error)
3411 {
3412         int ret = 0;
3413         uint64_t layer;
3414
3415         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3416         if (!ret) {
3417                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3418                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3419                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3420                 if (!(item_flags & layer))
3421                         return rte_flow_error_set(error, EINVAL,
3422                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3423                                                   NULL,
3424                                                   "no ipv6 item in pattern");
3425         }
3426         return ret;
3427 }
3428
3429 /**
3430  * Validate the modify-header TP actions.
3431  *
3432  * @param[in] action_flags
3433  *   Holds the actions detected until now.
3434  * @param[in] action
3435  *   Pointer to the modify action.
3436  * @param[in] item_flags
3437  *   Holds the items detected.
3438  * @param[out] error
3439  *   Pointer to error structure.
3440  *
3441  * @return
3442  *   0 on success, a negative errno value otherwise and rte_errno is set.
3443  */
3444 static int
3445 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3446                                   const struct rte_flow_action *action,
3447                                   const uint64_t item_flags,
3448                                   struct rte_flow_error *error)
3449 {
3450         int ret = 0;
3451         uint64_t layer;
3452
3453         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3454         if (!ret) {
3455                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3456                                  MLX5_FLOW_LAYER_INNER_L4 :
3457                                  MLX5_FLOW_LAYER_OUTER_L4;
3458                 if (!(item_flags & layer))
3459                         return rte_flow_error_set(error, EINVAL,
3460                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3461                                                   NULL, "no transport layer "
3462                                                   "in pattern");
3463         }
3464         return ret;
3465 }
3466
3467 /**
3468  * Validate the modify-header actions of increment/decrement
3469  * TCP Sequence-number.
3470  *
3471  * @param[in] action_flags
3472  *   Holds the actions detected until now.
3473  * @param[in] action
3474  *   Pointer to the modify action.
3475  * @param[in] item_flags
3476  *   Holds the items detected.
3477  * @param[out] error
3478  *   Pointer to error structure.
3479  *
3480  * @return
3481  *   0 on success, a negative errno value otherwise and rte_errno is set.
3482  */
3483 static int
3484 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3485                                        const struct rte_flow_action *action,
3486                                        const uint64_t item_flags,
3487                                        struct rte_flow_error *error)
3488 {
3489         int ret = 0;
3490         uint64_t layer;
3491
3492         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3493         if (!ret) {
3494                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3495                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3496                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3497                 if (!(item_flags & layer))
3498                         return rte_flow_error_set(error, EINVAL,
3499                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3500                                                   NULL, "no TCP item in"
3501                                                   " pattern");
3502                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3503                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3504                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3505                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3506                         return rte_flow_error_set(error, EINVAL,
3507                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3508                                                   NULL,
3509                                                   "cannot decrease and increase"
3510                                                   " TCP sequence number"
3511                                                   " at the same time");
3512         }
3513         return ret;
3514 }
3515
3516 /**
3517  * Validate the modify-header actions of increment/decrement
3518  * TCP Acknowledgment number.
3519  *
3520  * @param[in] action_flags
3521  *   Holds the actions detected until now.
3522  * @param[in] action
3523  *   Pointer to the modify action.
3524  * @param[in] item_flags
3525  *   Holds the items detected.
3526  * @param[out] error
3527  *   Pointer to error structure.
3528  *
3529  * @return
3530  *   0 on success, a negative errno value otherwise and rte_errno is set.
3531  */
3532 static int
3533 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3534                                        const struct rte_flow_action *action,
3535                                        const uint64_t item_flags,
3536                                        struct rte_flow_error *error)
3537 {
3538         int ret = 0;
3539         uint64_t layer;
3540
3541         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3542         if (!ret) {
3543                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3544                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
3545                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
3546                 if (!(item_flags & layer))
3547                         return rte_flow_error_set(error, EINVAL,
3548                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3549                                                   NULL, "no TCP item in"
3550                                                   " pattern");
3551                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3552                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3553                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3554                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3555                         return rte_flow_error_set(error, EINVAL,
3556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3557                                                   NULL,
3558                                                   "cannot decrease and increase"
3559                                                   " TCP acknowledgment number"
3560                                                   " at the same time");
3561         }
3562         return ret;
3563 }
3564
3565 /**
3566  * Validate the modify-header TTL actions.
3567  *
3568  * @param[in] action_flags
3569  *   Holds the actions detected until now.
3570  * @param[in] action
3571  *   Pointer to the modify action.
3572  * @param[in] item_flags
3573  *   Holds the items detected.
3574  * @param[out] error
3575  *   Pointer to error structure.
3576  *
3577  * @return
3578  *   0 on success, a negative errno value otherwise and rte_errno is set.
3579  */
3580 static int
3581 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3582                                    const struct rte_flow_action *action,
3583                                    const uint64_t item_flags,
3584                                    struct rte_flow_error *error)
3585 {
3586         int ret = 0;
3587         uint64_t layer;
3588
3589         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3590         if (!ret) {
3591                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3592                                  MLX5_FLOW_LAYER_INNER_L3 :
3593                                  MLX5_FLOW_LAYER_OUTER_L3;
3594                 if (!(item_flags & layer))
3595                         return rte_flow_error_set(error, EINVAL,
3596                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3597                                                   NULL,
3598                                                   "no IP protocol in pattern");
3599         }
3600         return ret;
3601 }
3602
3603 /**
3604  * Validate jump action.
3605  *
3606  * @param[in] action
3607  *   Pointer to the jump action.
3608  * @param[in] action_flags
3609  *   Holds the actions detected until now.
3610  * @param[in] attributes
3611  *   Pointer to flow attributes
3612  * @param[in] external
3613  *   Action belongs to flow rule created by request external to PMD.
3614  * @param[out] error
3615  *   Pointer to error structure.
3616  *
3617  * @return
3618  *   0 on success, a negative errno value otherwise and rte_errno is set.
3619  */
3620 static int
3621 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3622                              uint64_t action_flags,
3623                              const struct rte_flow_attr *attributes,
3624                              bool external, struct rte_flow_error *error)
3625 {
3626         uint32_t target_group, table;
3627         int ret = 0;
3628
3629         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3630                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3631                 return rte_flow_error_set(error, EINVAL,
3632                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3633                                           "can't have 2 fate actions in"
3634                                           " same flow");
3635         if (action_flags & MLX5_FLOW_ACTION_METER)
3636                 return rte_flow_error_set(error, ENOTSUP,
3637                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3638                                           "jump with meter not support");
3639         if (!action->conf)
3640                 return rte_flow_error_set(error, EINVAL,
3641                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3642                                           NULL, "action configuration not set");
3643         target_group =
3644                 ((const struct rte_flow_action_jump *)action->conf)->group;
3645         ret = mlx5_flow_group_to_table(attributes, external, target_group,
3646                                        true, &table, error);
3647         if (ret)
3648                 return ret;
3649         if (attributes->group == target_group)
3650                 return rte_flow_error_set(error, EINVAL,
3651                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3652                                           "target group must be other than"
3653                                           " the current flow group");
3654         return 0;
3655 }
3656
3657 /*
3658  * Validate the port_id action.
3659  *
3660  * @param[in] dev
3661  *   Pointer to rte_eth_dev structure.
3662  * @param[in] action_flags
3663  *   Bit-fields that holds the actions detected until now.
3664  * @param[in] action
3665  *   Port_id RTE action structure.
3666  * @param[in] attr
3667  *   Attributes of flow that includes this action.
3668  * @param[out] error
3669  *   Pointer to error structure.
3670  *
3671  * @return
3672  *   0 on success, a negative errno value otherwise and rte_errno is set.
3673  */
3674 static int
3675 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3676                                 uint64_t action_flags,
3677                                 const struct rte_flow_action *action,
3678                                 const struct rte_flow_attr *attr,
3679                                 struct rte_flow_error *error)
3680 {
3681         const struct rte_flow_action_port_id *port_id;
3682         struct mlx5_priv *act_priv;
3683         struct mlx5_priv *dev_priv;
3684         uint16_t port;
3685
3686         if (!attr->transfer)
3687                 return rte_flow_error_set(error, ENOTSUP,
3688                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3689                                           NULL,
3690                                           "port id action is valid in transfer"
3691                                           " mode only");
3692         if (!action || !action->conf)
3693                 return rte_flow_error_set(error, ENOTSUP,
3694                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3695                                           NULL,
3696                                           "port id action parameters must be"
3697                                           " specified");
3698         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3699                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3700                 return rte_flow_error_set(error, EINVAL,
3701                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3702                                           "can have only one fate actions in"
3703                                           " a flow");
3704         dev_priv = mlx5_dev_to_eswitch_info(dev);
3705         if (!dev_priv)
3706                 return rte_flow_error_set(error, rte_errno,
3707                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3708                                           NULL,
3709                                           "failed to obtain E-Switch info");
3710         port_id = action->conf;
3711         port = port_id->original ? dev->data->port_id : port_id->id;
3712         act_priv = mlx5_port_to_eswitch_info(port, false);
3713         if (!act_priv)
3714                 return rte_flow_error_set
3715                                 (error, rte_errno,
3716                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3717                                  "failed to obtain E-Switch port id for port");
3718         if (act_priv->domain_id != dev_priv->domain_id)
3719                 return rte_flow_error_set
3720                                 (error, EINVAL,
3721                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3722                                  "port does not belong to"
3723                                  " E-Switch being configured");
3724         return 0;
3725 }
3726
3727 /**
3728  * Get the maximum number of modify header actions.
3729  *
3730  * @param dev
3731  *   Pointer to rte_eth_dev structure.
3732  * @param flags
3733  *   Flags bits to check if root level.
3734  *
3735  * @return
3736  *   Max number of modify header actions device can support.
3737  */
3738 static inline unsigned int
3739 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3740                               uint64_t flags)
3741 {
3742         /*
3743          * There's no way to directly query the max capacity from FW.
3744          * The maximal value on root table should be assumed to be supported.
3745          */
3746         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3747                 return MLX5_MAX_MODIFY_NUM;
3748         else
3749                 return MLX5_ROOT_TBL_MODIFY_NUM;
3750 }
3751
3752 /**
3753  * Validate the meter action.
3754  *
3755  * @param[in] dev
3756  *   Pointer to rte_eth_dev structure.
3757  * @param[in] action_flags
3758  *   Bit-fields that holds the actions detected until now.
3759  * @param[in] action
3760  *   Pointer to the meter action.
3761  * @param[in] attr
3762  *   Attributes of flow that includes this action.
3763  * @param[out] error
3764  *   Pointer to error structure.
3765  *
3766  * @return
3767  *   0 on success, a negative errno value otherwise and rte_ernno is set.
3768  */
3769 static int
3770 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3771                                 uint64_t action_flags,
3772                                 const struct rte_flow_action *action,
3773                                 const struct rte_flow_attr *attr,
3774                                 struct rte_flow_error *error)
3775 {
3776         struct mlx5_priv *priv = dev->data->dev_private;
3777         const struct rte_flow_action_meter *am = action->conf;
3778         struct mlx5_flow_meter *fm;
3779
3780         if (!am)
3781                 return rte_flow_error_set(error, EINVAL,
3782                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3783                                           "meter action conf is NULL");
3784
3785         if (action_flags & MLX5_FLOW_ACTION_METER)
3786                 return rte_flow_error_set(error, ENOTSUP,
3787                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3788                                           "meter chaining not support");
3789         if (action_flags & MLX5_FLOW_ACTION_JUMP)
3790                 return rte_flow_error_set(error, ENOTSUP,
3791                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3792                                           "meter with jump not support");
3793         if (!priv->mtr_en)
3794                 return rte_flow_error_set(error, ENOTSUP,
3795                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3796                                           NULL,
3797                                           "meter action not supported");
3798         fm = mlx5_flow_meter_find(priv, am->mtr_id);
3799         if (!fm)
3800                 return rte_flow_error_set(error, EINVAL,
3801                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3802                                           "Meter not found");
3803         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3804               (!fm->ingress && !attr->ingress && attr->egress) ||
3805               (!fm->egress && !attr->egress && attr->ingress))))
3806                 return rte_flow_error_set(error, EINVAL,
3807                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3808                                           "Flow attributes are either invalid "
3809                                           "or have a conflict with current "
3810                                           "meter attributes");
3811         return 0;
3812 }
3813
3814 /**
3815  * Validate the age action.
3816  *
3817  * @param[in] action_flags
3818  *   Holds the actions detected until now.
3819  * @param[in] action
3820  *   Pointer to the age action.
3821  * @param[in] dev
3822  *   Pointer to the Ethernet device structure.
3823  * @param[out] error
3824  *   Pointer to error structure.
3825  *
3826  * @return
3827  *   0 on success, a negative errno value otherwise and rte_errno is set.
3828  */
3829 static int
3830 flow_dv_validate_action_age(uint64_t action_flags,
3831                             const struct rte_flow_action *action,
3832                             struct rte_eth_dev *dev,
3833                             struct rte_flow_error *error)
3834 {
3835         struct mlx5_priv *priv = dev->data->dev_private;
3836         const struct rte_flow_action_age *age = action->conf;
3837
3838         if (!priv->config.devx || priv->counter_fallback)
3839                 return rte_flow_error_set(error, ENOTSUP,
3840                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3841                                           NULL,
3842                                           "age action not supported");
3843         if (!(action->conf))
3844                 return rte_flow_error_set(error, EINVAL,
3845                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3846                                           "configuration cannot be null");
3847         if (age->timeout >= UINT16_MAX / 2 / 10)
3848                 return rte_flow_error_set(error, ENOTSUP,
3849                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3850                                           "Max age time: 3275 seconds");
3851         if (action_flags & MLX5_FLOW_ACTION_AGE)
3852                 return rte_flow_error_set(error, EINVAL,
3853                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3854                                           "Duplicate age ctions set");
3855         return 0;
3856 }
3857
3858 /**
3859  * Validate the modify-header IPv4 DSCP actions.
3860  *
3861  * @param[in] action_flags
3862  *   Holds the actions detected until now.
3863  * @param[in] action
3864  *   Pointer to the modify action.
3865  * @param[in] item_flags
3866  *   Holds the items detected.
3867  * @param[out] error
3868  *   Pointer to error structure.
3869  *
3870  * @return
3871  *   0 on success, a negative errno value otherwise and rte_errno is set.
3872  */
3873 static int
3874 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3875                                          const struct rte_flow_action *action,
3876                                          const uint64_t item_flags,
3877                                          struct rte_flow_error *error)
3878 {
3879         int ret = 0;
3880
3881         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3882         if (!ret) {
3883                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3884                         return rte_flow_error_set(error, EINVAL,
3885                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                   NULL,
3887                                                   "no ipv4 item in pattern");
3888         }
3889         return ret;
3890 }
3891
3892 /**
3893  * Validate the modify-header IPv6 DSCP actions.
3894  *
3895  * @param[in] action_flags
3896  *   Holds the actions detected until now.
3897  * @param[in] action
3898  *   Pointer to the modify action.
3899  * @param[in] item_flags
3900  *   Holds the items detected.
3901  * @param[out] error
3902  *   Pointer to error structure.
3903  *
3904  * @return
3905  *   0 on success, a negative errno value otherwise and rte_errno is set.
3906  */
3907 static int
3908 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3909                                          const struct rte_flow_action *action,
3910                                          const uint64_t item_flags,
3911                                          struct rte_flow_error *error)
3912 {
3913         int ret = 0;
3914
3915         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3916         if (!ret) {
3917                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3918                         return rte_flow_error_set(error, EINVAL,
3919                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3920                                                   NULL,
3921                                                   "no ipv6 item in pattern");
3922         }
3923         return ret;
3924 }
3925
3926 /**
3927  * Find existing modify-header resource or create and register a new one.
3928  *
3929  * @param dev[in, out]
3930  *   Pointer to rte_eth_dev structure.
3931  * @param[in, out] resource
3932  *   Pointer to modify-header resource.
3933  * @parm[in, out] dev_flow
3934  *   Pointer to the dev_flow.
3935  * @param[out] error
3936  *   pointer to error structure.
3937  *
3938  * @return
3939  *   0 on success otherwise -errno and errno is set.
3940  */
3941 static int
3942 flow_dv_modify_hdr_resource_register
3943                         (struct rte_eth_dev *dev,
3944                          struct mlx5_flow_dv_modify_hdr_resource *resource,
3945                          struct mlx5_flow *dev_flow,
3946                          struct rte_flow_error *error)
3947 {
3948         struct mlx5_priv *priv = dev->data->dev_private;
3949         struct mlx5_dev_ctx_shared *sh = priv->sh;
3950         struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3951         struct mlx5dv_dr_domain *ns;
3952         uint32_t actions_len;
3953
3954         resource->flags = dev_flow->dv.group ? 0 :
3955                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3956         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3957                                     resource->flags))
3958                 return rte_flow_error_set(error, EOVERFLOW,
3959                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3960                                           "too many modify header items");
3961         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3962                 ns = sh->fdb_domain;
3963         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3964                 ns = sh->tx_domain;
3965         else
3966                 ns = sh->rx_domain;
3967         /* Lookup a matching resource from cache. */
3968         actions_len = resource->actions_num * sizeof(resource->actions[0]);
3969         LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3970                 if (resource->ft_type == cache_resource->ft_type &&
3971                     resource->actions_num == cache_resource->actions_num &&
3972                     resource->flags == cache_resource->flags &&
3973                     !memcmp((const void *)resource->actions,
3974                             (const void *)cache_resource->actions,
3975                             actions_len)) {
3976                         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3977                                 (void *)cache_resource,
3978                                 rte_atomic32_read(&cache_resource->refcnt));
3979                         rte_atomic32_inc(&cache_resource->refcnt);
3980                         dev_flow->handle->dvh.modify_hdr = cache_resource;
3981                         return 0;
3982                 }
3983         }
3984         /* Register new modify-header resource. */
3985         cache_resource = rte_calloc(__func__, 1,
3986                                     sizeof(*cache_resource) + actions_len, 0);
3987         if (!cache_resource)
3988                 return rte_flow_error_set(error, ENOMEM,
3989                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3990                                           "cannot allocate resource memory");
3991         *cache_resource = *resource;
3992         rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3993         cache_resource->verbs_action =
3994                 mlx5_glue->dv_create_flow_action_modify_header
3995                                         (sh->ctx, cache_resource->ft_type, ns,
3996                                          cache_resource->flags, actions_len,
3997                                          (uint64_t *)cache_resource->actions);
3998         if (!cache_resource->verbs_action) {
3999                 rte_free(cache_resource);
4000                 return rte_flow_error_set(error, ENOMEM,
4001                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4002                                           NULL, "cannot create action");
4003         }
4004         rte_atomic32_init(&cache_resource->refcnt);
4005         rte_atomic32_inc(&cache_resource->refcnt);
4006         LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4007         dev_flow->handle->dvh.modify_hdr = cache_resource;
4008         DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4009                 (void *)cache_resource,
4010                 rte_atomic32_read(&cache_resource->refcnt));
4011         return 0;
4012 }
4013
4014 /**
4015  * Get DV flow counter by index.
4016  *
4017  * @param[in] dev
4018  *   Pointer to the Ethernet device structure.
4019  * @param[in] idx
4020  *   mlx5 flow counter index in the container.
4021  * @param[out] ppool
4022  *   mlx5 flow counter pool in the container,
4023  *
4024  * @return
4025  *   Pointer to the counter, NULL otherwise.
4026  */
4027 static struct mlx5_flow_counter *
4028 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4029                            uint32_t idx,
4030                            struct mlx5_flow_counter_pool **ppool)
4031 {
4032         struct mlx5_priv *priv = dev->data->dev_private;
4033         struct mlx5_pools_container *cont;
4034         struct mlx5_flow_counter_pool *pool;
4035         uint32_t batch = 0, age = 0;
4036
4037         idx--;
4038         age = MLX_CNT_IS_AGE(idx);
4039         idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4040         if (idx >= MLX5_CNT_BATCH_OFFSET) {
4041                 idx -= MLX5_CNT_BATCH_OFFSET;
4042                 batch = 1;
4043         }
4044         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4045         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4046         pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4047         MLX5_ASSERT(pool);
4048         if (ppool)
4049                 *ppool = pool;
4050         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4051 }
4052
4053 /**
4054  * Check the devx counter belongs to the pool.
4055  *
4056  * @param[in] pool
4057  *   Pointer to the counter pool.
4058  * @param[in] id
4059  *   The counter devx ID.
4060  *
4061  * @return
4062  *   True if counter belongs to the pool, false otherwise.
4063  */
4064 static bool
4065 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4066 {
4067         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4068                    MLX5_COUNTERS_PER_POOL;
4069
4070         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4071                 return true;
4072         return false;
4073 }
4074
4075 /**
4076  * Get a pool by devx counter ID.
4077  *
4078  * @param[in] cont
4079  *   Pointer to the counter container.
4080  * @param[in] id
4081  *   The counter devx ID.
4082  *
4083  * @return
4084  *   The counter pool pointer if exists, NULL otherwise,
4085  */
4086 static struct mlx5_flow_counter_pool *
4087 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4088 {
4089         uint32_t i;
4090
4091         /* Check last used pool. */
4092         if (cont->last_pool_idx != POOL_IDX_INVALID &&
4093             flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4094                 return cont->pools[cont->last_pool_idx];
4095         /* ID out of range means no suitable pool in the container. */
4096         if (id > cont->max_id || id < cont->min_id)
4097                 return NULL;
4098         /*
4099          * Find the pool from the end of the container, since mostly counter
4100          * ID is sequence increasing, and the last pool should be the needed
4101          * one.
4102          */
4103         i = rte_atomic16_read(&cont->n_valid);
4104         while (i--) {
4105                 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4106
4107                 if (flow_dv_is_counter_in_pool(pool, id))
4108                         return pool;
4109         }
4110         return NULL;
4111 }
4112
4113 /**
4114  * Allocate a new memory for the counter values wrapped by all the needed
4115  * management.
4116  *
4117  * @param[in] dev
4118  *   Pointer to the Ethernet device structure.
4119  * @param[in] raws_n
4120  *   The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4121  *
4122  * @return
4123  *   The new memory management pointer on success, otherwise NULL and rte_errno
4124  *   is set.
4125  */
4126 static struct mlx5_counter_stats_mem_mng *
4127 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4128 {
4129         struct mlx5_priv *priv = dev->data->dev_private;
4130         struct mlx5_dev_ctx_shared *sh = priv->sh;
4131         struct mlx5_devx_mkey_attr mkey_attr;
4132         struct mlx5_counter_stats_mem_mng *mem_mng;
4133         volatile struct flow_counter_stats *raw_data;
4134         int size = (sizeof(struct flow_counter_stats) *
4135                         MLX5_COUNTERS_PER_POOL +
4136                         sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4137                         sizeof(struct mlx5_counter_stats_mem_mng);
4138         uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
4139         int i;
4140
4141         if (!mem) {
4142                 rte_errno = ENOMEM;
4143                 return NULL;
4144         }
4145         mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4146         size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4147         mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4148                                                  IBV_ACCESS_LOCAL_WRITE);
4149         if (!mem_mng->umem) {
4150                 rte_errno = errno;
4151                 rte_free(mem);
4152                 return NULL;
4153         }
4154         mkey_attr.addr = (uintptr_t)mem;
4155         mkey_attr.size = size;
4156         mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4157         mkey_attr.pd = sh->pdn;
4158         mkey_attr.log_entity_size = 0;
4159         mkey_attr.pg_access = 0;
4160         mkey_attr.klm_array = NULL;
4161         mkey_attr.klm_num = 0;
4162         if (priv->config.hca_attr.relaxed_ordering_write &&
4163                 priv->config.hca_attr.relaxed_ordering_read  &&
4164                 !haswell_broadwell_cpu)
4165                 mkey_attr.relaxed_ordering = 1;
4166         mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4167         if (!mem_mng->dm) {
4168                 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4169                 rte_errno = errno;
4170                 rte_free(mem);
4171                 return NULL;
4172         }
4173         mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4174         raw_data = (volatile struct flow_counter_stats *)mem;
4175         for (i = 0; i < raws_n; ++i) {
4176                 mem_mng->raws[i].mem_mng = mem_mng;
4177                 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4178         }
4179         LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4180         return mem_mng;
4181 }
4182
4183 /**
4184  * Resize a counter container.
4185  *
4186  * @param[in] dev
4187  *   Pointer to the Ethernet device structure.
4188  * @param[in] batch
4189  *   Whether the pool is for counter that was allocated by batch command.
4190  * @param[in] age
4191  *   Whether the pool is for Aging counter.
4192  *
4193  * @return
4194  *   0 on success, otherwise negative errno value and rte_errno is set.
4195  */
4196 static int
4197 flow_dv_container_resize(struct rte_eth_dev *dev,
4198                                 uint32_t batch, uint32_t age)
4199 {
4200         struct mlx5_priv *priv = dev->data->dev_private;
4201         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4202                                                                age);
4203         struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4204         void *old_pools = cont->pools;
4205         uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4206         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4207         void *pools = rte_calloc(__func__, 1, mem_size, 0);
4208
4209         if (!pools) {
4210                 rte_errno = ENOMEM;
4211                 return -ENOMEM;
4212         }
4213         if (old_pools)
4214                 memcpy(pools, old_pools, cont->n *
4215                                        sizeof(struct mlx5_flow_counter_pool *));
4216         /*
4217          * Fallback mode query the counter directly, no background query
4218          * resources are needed.
4219          */
4220         if (!priv->counter_fallback) {
4221                 int i;
4222
4223                 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4224                           MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4225                 if (!mem_mng) {
4226                         rte_free(pools);
4227                         return -ENOMEM;
4228                 }
4229                 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4230                         LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4231                                          mem_mng->raws +
4232                                          MLX5_CNT_CONTAINER_RESIZE +
4233                                          i, next);
4234         }
4235         rte_spinlock_lock(&cont->resize_sl);
4236         cont->n = resize;
4237         cont->mem_mng = mem_mng;
4238         cont->pools = pools;
4239         rte_spinlock_unlock(&cont->resize_sl);
4240         if (old_pools)
4241                 rte_free(old_pools);
4242         return 0;
4243 }
4244
4245 /**
4246  * Query a devx flow counter.
4247  *
4248  * @param[in] dev
4249  *   Pointer to the Ethernet device structure.
4250  * @param[in] cnt
4251  *   Index to the flow counter.
4252  * @param[out] pkts
4253  *   The statistics value of packets.
4254  * @param[out] bytes
4255  *   The statistics value of bytes.
4256  *
4257  * @return
4258  *   0 on success, otherwise a negative errno value and rte_errno is set.
4259  */
4260 static inline int
4261 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4262                      uint64_t *bytes)
4263 {
4264         struct mlx5_priv *priv = dev->data->dev_private;
4265         struct mlx5_flow_counter_pool *pool = NULL;
4266         struct mlx5_flow_counter *cnt;
4267         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4268         int offset;
4269
4270         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4271         MLX5_ASSERT(pool);
4272         if (counter < MLX5_CNT_BATCH_OFFSET) {
4273                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4274                 if (priv->counter_fallback)
4275                         return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4276                                         0, pkts, bytes, 0, NULL, NULL, 0);
4277         }
4278
4279         rte_spinlock_lock(&pool->sl);
4280         /*
4281          * The single counters allocation may allocate smaller ID than the
4282          * current allocated in parallel to the host reading.
4283          * In this case the new counter values must be reported as 0.
4284          */
4285         if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4286                 *pkts = 0;
4287                 *bytes = 0;
4288         } else {
4289                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4290                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4291                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4292         }
4293         rte_spinlock_unlock(&pool->sl);
4294         return 0;
4295 }
4296
4297 /**
4298  * Create and initialize a new counter pool.
4299  *
4300  * @param[in] dev
4301  *   Pointer to the Ethernet device structure.
4302  * @param[out] dcs
4303  *   The devX counter handle.
4304  * @param[in] batch
4305  *   Whether the pool is for counter that was allocated by batch command.
4306  * @param[in] age
4307  *   Whether the pool is for counter that was allocated for aging.
4308  * @param[in/out] cont_cur
4309  *   Pointer to the container pointer, it will be update in pool resize.
4310  *
4311  * @return
4312  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
4313  */
4314 static struct mlx5_flow_counter_pool *
4315 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4316                     uint32_t batch, uint32_t age)
4317 {
4318         struct mlx5_priv *priv = dev->data->dev_private;
4319         struct mlx5_flow_counter_pool *pool;
4320         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4321                                                                age);
4322         int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4323         uint32_t size = sizeof(*pool);
4324
4325         if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4326                 return NULL;
4327         size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4328         size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4329         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4330         pool = rte_calloc(__func__, 1, size, 0);
4331         if (!pool) {
4332                 rte_errno = ENOMEM;
4333                 return NULL;
4334         }
4335         pool->min_dcs = dcs;
4336         if (!priv->counter_fallback)
4337                 pool->raw = cont->mem_mng->raws + n_valid %
4338                                                       MLX5_CNT_CONTAINER_RESIZE;
4339         pool->raw_hw = NULL;
4340         pool->type = 0;
4341         pool->type |= (batch ? 0 :  CNT_POOL_TYPE_EXT);
4342         pool->type |= (!age ? 0 :  CNT_POOL_TYPE_AGE);
4343         rte_spinlock_init(&pool->sl);
4344         /*
4345          * The generation of the new allocated counters in this pool is 0, 2 in
4346          * the pool generation makes all the counters valid for allocation.
4347          * The start and end query generation protect the counters be released
4348          * between the query and update gap period will not be reallocated
4349          * without the last query finished and stats updated to the memory.
4350          */
4351         rte_atomic64_set(&pool->start_query_gen, 0x2);
4352         /*
4353          * There's no background query thread for fallback mode, set the
4354          * end_query_gen to the maximum value since no need to wait for
4355          * statistics update.
4356          */
4357         rte_atomic64_set(&pool->end_query_gen, priv->counter_fallback ?
4358                          INT64_MAX : 0x2);
4359         TAILQ_INIT(&pool->counters);
4360         TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4361         pool->index = n_valid;
4362         cont->pools[n_valid] = pool;
4363         if (!batch) {
4364                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4365
4366                 if (base < cont->min_id)
4367                         cont->min_id = base;
4368                 if (base > cont->max_id)
4369                         cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4370                 cont->last_pool_idx = pool->index;
4371         }
4372         /* Pool initialization must be updated before host thread access. */
4373         rte_cio_wmb();
4374         rte_atomic16_add(&cont->n_valid, 1);
4375         return pool;
4376 }
4377
4378 /**
4379  * Update the minimum dcs-id for aged or no-aged counter pool.
4380  *
4381  * @param[in] dev
4382  *   Pointer to the Ethernet device structure.
4383  * @param[in] pool
4384  *   Current counter pool.
4385  * @param[in] batch
4386  *   Whether the pool is for counter that was allocated by batch command.
4387  * @param[in] age
4388  *   Whether the counter is for aging.
4389  */
4390 static void
4391 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4392                         struct mlx5_flow_counter_pool *pool,
4393                         uint32_t batch, uint32_t age)
4394 {
4395         struct mlx5_priv *priv = dev->data->dev_private;
4396         struct mlx5_flow_counter_pool *other;
4397         struct mlx5_pools_container *cont;
4398
4399         cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4400         other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4401         if (!other)
4402                 return;
4403         if (pool->min_dcs->id < other->min_dcs->id) {
4404                 rte_atomic64_set(&other->a64_dcs,
4405                         rte_atomic64_read(&pool->a64_dcs));
4406         } else {
4407                 rte_atomic64_set(&pool->a64_dcs,
4408                         rte_atomic64_read(&other->a64_dcs));
4409         }
4410 }
4411 /**
4412  * Prepare a new counter and/or a new counter pool.
4413  *
4414  * @param[in] dev
4415  *   Pointer to the Ethernet device structure.
4416  * @param[out] cnt_free
4417  *   Where to put the pointer of a new counter.
4418  * @param[in] batch
4419  *   Whether the pool is for counter that was allocated by batch command.
4420  * @param[in] age
4421  *   Whether the pool is for counter that was allocated for aging.
4422  *
4423  * @return
4424  *   The counter pool pointer and @p cnt_free is set on success,
4425  *   NULL otherwise and rte_errno is set.
4426  */
4427 static struct mlx5_flow_counter_pool *
4428 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4429                              struct mlx5_flow_counter **cnt_free,
4430                              uint32_t batch, uint32_t age)
4431 {
4432         struct mlx5_priv *priv = dev->data->dev_private;
4433         struct mlx5_pools_container *cont;
4434         struct mlx5_flow_counter_pool *pool;
4435         struct mlx5_devx_obj *dcs = NULL;
4436         struct mlx5_flow_counter *cnt;
4437         uint32_t i;
4438
4439         cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4440         if (!batch) {
4441                 /* bulk_bitmap must be 0 for single counter allocation. */
4442                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4443                 if (!dcs)
4444                         return NULL;
4445                 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4446                 if (!pool) {
4447                         pool = flow_dv_pool_create(dev, dcs, batch, age);
4448                         if (!pool) {
4449                                 mlx5_devx_cmd_destroy(dcs);
4450                                 return NULL;
4451                         }
4452                 } else if (dcs->id < pool->min_dcs->id) {
4453                         rte_atomic64_set(&pool->a64_dcs,
4454                                          (int64_t)(uintptr_t)dcs);
4455                 }
4456                 flow_dv_counter_update_min_dcs(dev,
4457                                                 pool, batch, age);
4458                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4459                 cnt = MLX5_POOL_GET_CNT(pool, i);
4460                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4461                 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4462                 *cnt_free = cnt;
4463                 return pool;
4464         }
4465         /* bulk_bitmap is in 128 counters units. */
4466         if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4467                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4468         if (!dcs) {
4469                 rte_errno = ENODATA;
4470                 return NULL;
4471         }
4472         pool = flow_dv_pool_create(dev, dcs, batch, age);
4473         if (!pool) {
4474                 mlx5_devx_cmd_destroy(dcs);
4475                 return NULL;
4476         }
4477         for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4478                 cnt = MLX5_POOL_GET_CNT(pool, i);
4479                 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4480         }
4481         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4482         return pool;
4483 }
4484
4485 /**
4486  * Search for existed shared counter.
4487  *
4488  * @param[in] dev
4489  *   Pointer to the Ethernet device structure.
4490  * @param[in] id
4491  *   The shared counter ID to search.
4492  * @param[out] ppool
4493  *   mlx5 flow counter pool in the container,
4494  *
4495  * @return
4496  *   NULL if not existed, otherwise pointer to the shared extend counter.
4497  */
4498 static struct mlx5_flow_counter_ext *
4499 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4500                               struct mlx5_flow_counter_pool **ppool)
4501 {
4502         struct mlx5_priv *priv = dev->data->dev_private;
4503         union mlx5_l3t_data data;
4504         uint32_t cnt_idx;
4505
4506         if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4507                 return NULL;
4508         cnt_idx = data.dword;
4509         /*
4510          * Shared counters don't have age info. The counter extend is after
4511          * the counter datat structure.
4512          */
4513         return (struct mlx5_flow_counter_ext *)
4514                ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4515 }
4516
4517 /**
4518  * Allocate a flow counter.
4519  *
4520  * @param[in] dev
4521  *   Pointer to the Ethernet device structure.
4522  * @param[in] shared
4523  *   Indicate if this counter is shared with other flows.
4524  * @param[in] id
4525  *   Counter identifier.
4526  * @param[in] group
4527  *   Counter flow group.
4528  * @param[in] age
4529  *   Whether the counter was allocated for aging.
4530  *
4531  * @return
4532  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
4533  */
4534 static uint32_t
4535 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4536                       uint16_t group, uint32_t age)
4537 {
4538         struct mlx5_priv *priv = dev->data->dev_private;
4539         struct mlx5_flow_counter_pool *pool = NULL;
4540         struct mlx5_flow_counter *cnt_free = NULL;
4541         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4542         /*
4543          * Currently group 0 flow counter cannot be assigned to a flow if it is
4544          * not the first one in the batch counter allocation, so it is better
4545          * to allocate counters one by one for these flows in a separate
4546          * container.
4547          * A counter can be shared between different groups so need to take
4548          * shared counters from the single container.
4549          */
4550         uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4551         struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4552                                                                age);
4553         uint32_t cnt_idx;
4554
4555         if (!priv->config.devx) {
4556                 rte_errno = ENOTSUP;
4557                 return 0;
4558         }
4559         if (shared) {
4560                 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4561                 if (cnt_ext) {
4562                         if (cnt_ext->ref_cnt + 1 == 0) {
4563                                 rte_errno = E2BIG;
4564                                 return 0;
4565                         }
4566                         cnt_ext->ref_cnt++;
4567                         cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4568                                   (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4569                                   + 1;
4570                         return cnt_idx;
4571                 }
4572         }
4573         /* Pools which has a free counters are in the start. */
4574         TAILQ_FOREACH(pool, &cont->pool_list, next) {
4575                 /*
4576                  * The free counter reset values must be updated between the
4577                  * counter release to the counter allocation, so, at least one
4578                  * query must be done in this time. ensure it by saving the
4579                  * query generation in the release time.
4580                  * The free list is sorted according to the generation - so if
4581                  * the first one is not updated, all the others are not
4582                  * updated too.
4583                  */
4584                 cnt_free = TAILQ_FIRST(&pool->counters);
4585                 if (cnt_free && cnt_free->query_gen <
4586                     rte_atomic64_read(&pool->end_query_gen))
4587                         break;
4588                 cnt_free = NULL;
4589         }
4590         if (!cnt_free) {
4591                 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch, age);
4592                 if (!pool)
4593                         return 0;
4594         }
4595         if (!batch)
4596                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4597         /* Create a DV counter action only in the first time usage. */
4598         if (!cnt_free->action) {
4599                 uint16_t offset;
4600                 struct mlx5_devx_obj *dcs;
4601
4602                 if (batch) {
4603                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4604                         dcs = pool->min_dcs;
4605                 } else {
4606                         offset = 0;
4607                         dcs = cnt_ext->dcs;
4608                 }
4609                 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4610                                         (dcs->obj, offset);
4611                 if (!cnt_free->action) {
4612                         rte_errno = errno;
4613                         return 0;
4614                 }
4615         }
4616         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4617                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4618         cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4619         cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4620         /* Update the counter reset values. */
4621         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4622                                  &cnt_free->bytes))
4623                 return 0;
4624         if (cnt_ext) {
4625                 cnt_ext->shared = shared;
4626                 cnt_ext->ref_cnt = 1;
4627                 cnt_ext->id = id;
4628                 if (shared) {
4629                         union mlx5_l3t_data data;
4630
4631                         data.dword = cnt_idx;
4632                         if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4633                                 return 0;
4634                 }
4635         }
4636         if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4637                 /* Start the asynchronous batch query by the host thread. */
4638                 mlx5_set_query_alarm(priv->sh);
4639         TAILQ_REMOVE(&pool->counters, cnt_free, next);
4640         if (TAILQ_EMPTY(&pool->counters)) {
4641                 /* Move the pool to the end of the container pool list. */
4642                 TAILQ_REMOVE(&cont->pool_list, pool, next);
4643                 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4644         }
4645         return cnt_idx;
4646 }
4647
4648 /**
4649  * Get age param from counter index.
4650  *
4651  * @param[in] dev
4652  *   Pointer to the Ethernet device structure.
4653  * @param[in] counter
4654  *   Index to the counter handler.
4655  *
4656  * @return
4657  *   The aging parameter specified for the counter index.
4658  */
4659 static struct mlx5_age_param*
4660 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4661                                 uint32_t counter)
4662 {
4663         struct mlx5_flow_counter *cnt;
4664         struct mlx5_flow_counter_pool *pool = NULL;
4665
4666         flow_dv_counter_get_by_idx(dev, counter, &pool);
4667         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4668         cnt = MLX5_POOL_GET_CNT(pool, counter);
4669         return MLX5_CNT_TO_AGE(cnt);
4670 }
4671
4672 /**
4673  * Remove a flow counter from aged counter list.
4674  *
4675  * @param[in] dev
4676  *   Pointer to the Ethernet device structure.
4677  * @param[in] counter
4678  *   Index to the counter handler.
4679  * @param[in] cnt
4680  *   Pointer to the counter handler.
4681  */
4682 static void
4683 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4684                                 uint32_t counter, struct mlx5_flow_counter *cnt)
4685 {
4686         struct mlx5_age_info *age_info;
4687         struct mlx5_age_param *age_param;
4688         struct mlx5_priv *priv = dev->data->dev_private;
4689
4690         age_info = GET_PORT_AGE_INFO(priv);
4691         age_param = flow_dv_counter_idx_get_age(dev, counter);
4692         if (rte_atomic16_cmpset((volatile uint16_t *)
4693                         &age_param->state,
4694                         AGE_CANDIDATE, AGE_FREE)
4695                         != AGE_CANDIDATE) {
4696                 /**
4697                  * We need the lock even it is age timeout,
4698                  * since counter may still in process.
4699                  */
4700                 rte_spinlock_lock(&age_info->aged_sl);
4701                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4702                 rte_spinlock_unlock(&age_info->aged_sl);
4703         }
4704         rte_atomic16_set(&age_param->state, AGE_FREE);
4705 }
4706 /**
4707  * Release a flow counter.
4708  *
4709  * @param[in] dev
4710  *   Pointer to the Ethernet device structure.
4711  * @param[in] counter
4712  *   Index to the counter handler.
4713  */
4714 static void
4715 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4716 {
4717         struct mlx5_priv *priv = dev->data->dev_private;
4718         struct mlx5_flow_counter_pool *pool = NULL;
4719         struct mlx5_flow_counter *cnt;
4720         struct mlx5_flow_counter_ext *cnt_ext = NULL;
4721
4722         if (!counter)
4723                 return;
4724         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4725         MLX5_ASSERT(pool);
4726         if (counter < MLX5_CNT_BATCH_OFFSET) {
4727                 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4728                 if (cnt_ext) {
4729                         if (--cnt_ext->ref_cnt)
4730                                 return;
4731                         if (cnt_ext->shared)
4732                                 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4733                                                      cnt_ext->id);
4734                 }
4735         }
4736         if (IS_AGE_POOL(pool))
4737                 flow_dv_counter_remove_from_age(dev, counter, cnt);
4738         /* Put the counter in the end - the last updated one. */
4739         TAILQ_INSERT_TAIL(&pool->counters, cnt, next);
4740         /*
4741          * Counters released between query trigger and handler need
4742          * to wait the next round of query. Since the packets arrive
4743          * in the gap period will not be taken into account to the
4744          * old counter.
4745          */
4746         cnt->query_gen = rte_atomic64_read(&pool->start_query_gen);
4747 }
4748
4749 /**
4750  * Verify the @p attributes will be correctly understood by the NIC and store
4751  * them in the @p flow if everything is correct.
4752  *
4753  * @param[in] dev
4754  *   Pointer to dev struct.
4755  * @param[in] attributes
4756  *   Pointer to flow attributes
4757  * @param[in] external
4758  *   This flow rule is created by request external to PMD.
4759  * @param[out] error
4760  *   Pointer to error structure.
4761  *
4762  * @return
4763  *   - 0 on success and non root table.
4764  *   - 1 on success and root table.
4765  *   - a negative errno value otherwise and rte_errno is set.
4766  */
4767 static int
4768 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4769                             const struct rte_flow_attr *attributes,
4770                             bool external __rte_unused,
4771                             struct rte_flow_error *error)
4772 {
4773         struct mlx5_priv *priv = dev->data->dev_private;
4774         uint32_t priority_max = priv->config.flow_prio - 1;
4775         int ret = 0;
4776
4777 #ifndef HAVE_MLX5DV_DR
4778         if (attributes->group)
4779                 return rte_flow_error_set(error, ENOTSUP,
4780                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4781                                           NULL,
4782                                           "groups are not supported");
4783 #else
4784         uint32_t table = 0;
4785
4786         ret = mlx5_flow_group_to_table(attributes, external,
4787                                        attributes->group, !!priv->fdb_def_rule,
4788                                        &table, error);
4789         if (ret)
4790                 return ret;
4791         if (!table)
4792                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4793 #endif
4794         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4795             attributes->priority >= priority_max)
4796                 return rte_flow_error_set(error, ENOTSUP,
4797                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4798                                           NULL,
4799                                           "priority out of range");
4800         if (attributes->transfer) {
4801                 if (!priv->config.dv_esw_en)
4802                         return rte_flow_error_set
4803                                 (error, ENOTSUP,
4804                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4805                                  "E-Switch dr is not supported");
4806                 if (!(priv->representor || priv->master))
4807                         return rte_flow_error_set
4808                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4809                                  NULL, "E-Switch configuration can only be"
4810                                  " done by a master or a representor device");
4811                 if (attributes->egress)
4812                         return rte_flow_error_set
4813                                 (error, ENOTSUP,
4814                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4815                                  "egress is not supported");
4816         }
4817         if (!(attributes->egress ^ attributes->ingress))
4818                 return rte_flow_error_set(error, ENOTSUP,
4819                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4820                                           "must specify exactly one of "
4821                                           "ingress or egress");
4822         return ret;
4823 }
4824
4825 /**
4826  * Internal validation function. For validating both actions and items.
4827  *
4828  * @param[in] dev
4829  *   Pointer to the rte_eth_dev structure.
4830  * @param[in] attr
4831  *   Pointer to the flow attributes.
4832  * @param[in] items
4833  *   Pointer to the list of items.
4834  * @param[in] actions
4835  *   Pointer to the list of actions.
4836  * @param[in] external
4837  *   This flow rule is created by request external to PMD.
4838  * @param[in] hairpin
4839  *   Number of hairpin TX actions, 0 means classic flow.
4840  * @param[out] error
4841  *   Pointer to the error structure.
4842  *
4843  * @return
4844  *   0 on success, a negative errno value otherwise and rte_errno is set.
4845  */
4846 static int
4847 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4848                  const struct rte_flow_item items[],
4849                  const struct rte_flow_action actions[],
4850                  bool external, int hairpin, struct rte_flow_error *error)
4851 {
4852         int ret;
4853         uint64_t action_flags = 0;
4854         uint64_t item_flags = 0;
4855         uint64_t last_item = 0;
4856         uint8_t next_protocol = 0xff;
4857         uint16_t ether_type = 0;
4858         int actions_n = 0;
4859         uint8_t item_ipv6_proto = 0;
4860         const struct rte_flow_item *gre_item = NULL;
4861         const struct rte_flow_action_raw_decap *decap;
4862         const struct rte_flow_action_raw_encap *encap;
4863         const struct rte_flow_action_rss *rss;
4864         const struct rte_flow_item_tcp nic_tcp_mask = {
4865                 .hdr = {
4866                         .tcp_flags = 0xFF,
4867                         .src_port = RTE_BE16(UINT16_MAX),
4868                         .dst_port = RTE_BE16(UINT16_MAX),
4869                 }
4870         };
4871         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4872                 .hdr = {
4873                         .src_addr = RTE_BE32(0xffffffff),
4874                         .dst_addr = RTE_BE32(0xffffffff),
4875                         .type_of_service = 0xff,
4876                         .next_proto_id = 0xff,
4877                         .time_to_live = 0xff,
4878                 },
4879         };
4880         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4881                 .hdr = {
4882                         .src_addr =
4883                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4884                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4885                         .dst_addr =
4886                         "\xff\xff\xff\xff\xff\xff\xff\xff"
4887                         "\xff\xff\xff\xff\xff\xff\xff\xff",
4888                         .vtc_flow = RTE_BE32(0xffffffff),
4889                         .proto = 0xff,
4890                         .hop_limits = 0xff,
4891                 },
4892         };
4893         struct mlx5_priv *priv = dev->data->dev_private;
4894         struct mlx5_dev_config *dev_conf = &priv->config;
4895         uint16_t queue_index = 0xFFFF;
4896         const struct rte_flow_item_vlan *vlan_m = NULL;
4897         int16_t rw_act_num = 0;
4898         uint64_t is_root;
4899
4900         if (items == NULL)
4901                 return -1;
4902         ret = flow_dv_validate_attributes(dev, attr, external, error);
4903         if (ret < 0)
4904                 return ret;
4905         is_root = (uint64_t)ret;
4906         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4907                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4908                 int type = items->type;
4909
4910                 switch (type) {
4911                 case RTE_FLOW_ITEM_TYPE_VOID:
4912                         break;
4913                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4914                         ret = flow_dv_validate_item_port_id
4915                                         (dev, items, attr, item_flags, error);
4916                         if (ret < 0)
4917                                 return ret;
4918                         last_item = MLX5_FLOW_ITEM_PORT_ID;
4919                         break;
4920                 case RTE_FLOW_ITEM_TYPE_ETH:
4921                         ret = mlx5_flow_validate_item_eth(items, item_flags,
4922                                                           error);
4923                         if (ret < 0)
4924                                 return ret;
4925                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4926                                              MLX5_FLOW_LAYER_OUTER_L2;
4927                         if (items->mask != NULL && items->spec != NULL) {
4928                                 ether_type =
4929                                         ((const struct rte_flow_item_eth *)
4930                                          items->spec)->type;
4931                                 ether_type &=
4932                                         ((const struct rte_flow_item_eth *)
4933                                          items->mask)->type;
4934                                 ether_type = rte_be_to_cpu_16(ether_type);
4935                         } else {
4936                                 ether_type = 0;
4937                         }
4938                         break;
4939                 case RTE_FLOW_ITEM_TYPE_VLAN:
4940                         ret = flow_dv_validate_item_vlan(items, item_flags,
4941                                                          dev, error);
4942                         if (ret < 0)
4943                                 return ret;
4944                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4945                                              MLX5_FLOW_LAYER_OUTER_VLAN;
4946                         if (items->mask != NULL && items->spec != NULL) {
4947                                 ether_type =
4948                                         ((const struct rte_flow_item_vlan *)
4949                                          items->spec)->inner_type;
4950                                 ether_type &=
4951                                         ((const struct rte_flow_item_vlan *)
4952                                          items->mask)->inner_type;
4953                                 ether_type = rte_be_to_cpu_16(ether_type);
4954                         } else {
4955                                 ether_type = 0;
4956                         }
4957                         /* Store outer VLAN mask for of_push_vlan action. */
4958                         if (!tunnel)
4959                                 vlan_m = items->mask;
4960                         break;
4961                 case RTE_FLOW_ITEM_TYPE_IPV4:
4962                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4963                                                   &item_flags, &tunnel);
4964                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4965                                                            last_item,
4966                                                            ether_type,
4967                                                            &nic_ipv4_mask,
4968                                                            error);
4969                         if (ret < 0)
4970                                 return ret;
4971                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4972                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4973                         if (items->mask != NULL &&
4974                             ((const struct rte_flow_item_ipv4 *)
4975                              items->mask)->hdr.next_proto_id) {
4976                                 next_protocol =
4977                                         ((const struct rte_flow_item_ipv4 *)
4978                                          (items->spec))->hdr.next_proto_id;
4979                                 next_protocol &=
4980                                         ((const struct rte_flow_item_ipv4 *)
4981                                          (items->mask))->hdr.next_proto_id;
4982                         } else {
4983                                 /* Reset for inner layer. */
4984                                 next_protocol = 0xff;
4985                         }
4986                         break;
4987                 case RTE_FLOW_ITEM_TYPE_IPV6:
4988                         mlx5_flow_tunnel_ip_check(items, next_protocol,
4989                                                   &item_flags, &tunnel);
4990                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4991                                                            last_item,
4992                                                            ether_type,
4993                                                            &nic_ipv6_mask,
4994                                                            error);
4995                         if (ret < 0)
4996                                 return ret;
4997                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4998                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4999                         if (items->mask != NULL &&
5000                             ((const struct rte_flow_item_ipv6 *)
5001                              items->mask)->hdr.proto) {
5002                                 item_ipv6_proto =
5003                                         ((const struct rte_flow_item_ipv6 *)
5004                                          items->spec)->hdr.proto;
5005                                 next_protocol =
5006                                         ((const struct rte_flow_item_ipv6 *)
5007                                          items->spec)->hdr.proto;
5008                                 next_protocol &=
5009                                         ((const struct rte_flow_item_ipv6 *)
5010                                          items->mask)->hdr.proto;
5011                         } else {
5012                                 /* Reset for inner layer. */
5013                                 next_protocol = 0xff;
5014                         }
5015                         break;
5016                 case RTE_FLOW_ITEM_TYPE_TCP:
5017                         ret = mlx5_flow_validate_item_tcp
5018                                                 (items, item_flags,
5019                                                  next_protocol,
5020                                                  &nic_tcp_mask,
5021                                                  error);
5022                         if (ret < 0)
5023                                 return ret;
5024                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5025                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
5026                         break;
5027                 case RTE_FLOW_ITEM_TYPE_UDP:
5028                         ret = mlx5_flow_validate_item_udp(items, item_flags,
5029                                                           next_protocol,
5030                                                           error);
5031                         if (ret < 0)
5032                                 return ret;
5033                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5034                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
5035                         break;
5036                 case RTE_FLOW_ITEM_TYPE_GRE:
5037                         ret = mlx5_flow_validate_item_gre(items, item_flags,
5038                                                           next_protocol, error);
5039                         if (ret < 0)
5040                                 return ret;
5041                         gre_item = items;
5042                         last_item = MLX5_FLOW_LAYER_GRE;
5043                         break;
5044                 case RTE_FLOW_ITEM_TYPE_NVGRE:
5045                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5046                                                             next_protocol,
5047                                                             error);
5048                         if (ret < 0)
5049                                 return ret;
5050                         last_item = MLX5_FLOW_LAYER_NVGRE;
5051                         break;
5052                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5053                         ret = mlx5_flow_validate_item_gre_key
5054                                 (items, item_flags, gre_item, error);
5055                         if (ret < 0)
5056                                 return ret;
5057                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
5058                         break;
5059                 case RTE_FLOW_ITEM_TYPE_VXLAN:
5060                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5061                                                             error);
5062                         if (ret < 0)
5063                                 return ret;
5064                         last_item = MLX5_FLOW_LAYER_VXLAN;
5065                         break;
5066                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5067                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
5068                                                                 item_flags, dev,
5069                                                                 error);
5070                         if (ret < 0)
5071                                 return ret;
5072                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5073                         break;
5074                 case RTE_FLOW_ITEM_TYPE_GENEVE:
5075                         ret = mlx5_flow_validate_item_geneve(items,
5076                                                              item_flags, dev,
5077                                                              error);
5078                         if (ret < 0)
5079                                 return ret;
5080                         last_item = MLX5_FLOW_LAYER_GENEVE;
5081                         break;
5082                 case RTE_FLOW_ITEM_TYPE_MPLS:
5083                         ret = mlx5_flow_validate_item_mpls(dev, items,
5084                                                            item_flags,
5085                                                            last_item, error);
5086                         if (ret < 0)
5087                                 return ret;
5088                         last_item = MLX5_FLOW_LAYER_MPLS;
5089                         break;
5090
5091                 case RTE_FLOW_ITEM_TYPE_MARK:
5092                         ret = flow_dv_validate_item_mark(dev, items, attr,
5093                                                          error);
5094                         if (ret < 0)
5095                                 return ret;
5096                         last_item = MLX5_FLOW_ITEM_MARK;
5097                         break;
5098                 case RTE_FLOW_ITEM_TYPE_META:
5099                         ret = flow_dv_validate_item_meta(dev, items, attr,
5100                                                          error);
5101                         if (ret < 0)
5102                                 return ret;
5103                         last_item = MLX5_FLOW_ITEM_METADATA;
5104                         break;
5105                 case RTE_FLOW_ITEM_TYPE_ICMP:
5106                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
5107                                                            next_protocol,
5108                                                            error);
5109                         if (ret < 0)
5110                                 return ret;
5111                         last_item = MLX5_FLOW_LAYER_ICMP;
5112                         break;
5113                 case RTE_FLOW_ITEM_TYPE_ICMP6:
5114                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5115                                                             next_protocol,
5116                                                             error);
5117                         if (ret < 0)
5118                                 return ret;
5119                         item_ipv6_proto = IPPROTO_ICMPV6;
5120                         last_item = MLX5_FLOW_LAYER_ICMP6;
5121                         break;
5122                 case RTE_FLOW_ITEM_TYPE_TAG:
5123                         ret = flow_dv_validate_item_tag(dev, items,
5124                                                         attr, error);
5125                         if (ret < 0)
5126                                 return ret;
5127                         last_item = MLX5_FLOW_ITEM_TAG;
5128                         break;
5129                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5130                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5131                         break;
5132                 case RTE_FLOW_ITEM_TYPE_GTP:
5133                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5134                                                         error);
5135                         if (ret < 0)
5136                                 return ret;
5137                         last_item = MLX5_FLOW_LAYER_GTP;
5138                         break;
5139                 default:
5140                         return rte_flow_error_set(error, ENOTSUP,
5141                                                   RTE_FLOW_ERROR_TYPE_ITEM,
5142                                                   NULL, "item not supported");
5143                 }
5144                 item_flags |= last_item;
5145         }
5146         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5147                 int type = actions->type;
5148                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5149                         return rte_flow_error_set(error, ENOTSUP,
5150                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5151                                                   actions, "too many actions");
5152                 switch (type) {
5153                 case RTE_FLOW_ACTION_TYPE_VOID:
5154                         break;
5155                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5156                         ret = flow_dv_validate_action_port_id(dev,
5157                                                               action_flags,
5158                                                               actions,
5159                                                               attr,
5160                                                               error);
5161                         if (ret)
5162                                 return ret;
5163                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5164                         ++actions_n;
5165                         break;
5166                 case RTE_FLOW_ACTION_TYPE_FLAG:
5167                         ret = flow_dv_validate_action_flag(dev, action_flags,
5168                                                            attr, error);
5169                         if (ret < 0)
5170                                 return ret;
5171                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5172                                 /* Count all modify-header actions as one. */
5173                                 if (!(action_flags &
5174                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5175                                         ++actions_n;
5176                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
5177                                                 MLX5_FLOW_ACTION_MARK_EXT;
5178                         } else {
5179                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
5180                                 ++actions_n;
5181                         }
5182                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5183                         break;
5184                 case RTE_FLOW_ACTION_TYPE_MARK:
5185                         ret = flow_dv_validate_action_mark(dev, actions,
5186                                                            action_flags,
5187                                                            attr, error);
5188                         if (ret < 0)
5189                                 return ret;
5190                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5191                                 /* Count all modify-header actions as one. */
5192                                 if (!(action_flags &
5193                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
5194                                         ++actions_n;
5195                                 action_flags |= MLX5_FLOW_ACTION_MARK |
5196                                                 MLX5_FLOW_ACTION_MARK_EXT;
5197                         } else {
5198                                 action_flags |= MLX5_FLOW_ACTION_MARK;
5199                                 ++actions_n;
5200                         }
5201                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
5202                         break;
5203                 case RTE_FLOW_ACTION_TYPE_SET_META:
5204                         ret = flow_dv_validate_action_set_meta(dev, actions,
5205                                                                action_flags,
5206                                                                attr, error);
5207                         if (ret < 0)
5208                                 return ret;
5209                         /* Count all modify-header actions as one action. */
5210                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5211                                 ++actions_n;
5212                         action_flags |= MLX5_FLOW_ACTION_SET_META;
5213                         rw_act_num += MLX5_ACT_NUM_SET_META;
5214                         break;
5215                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5216                         ret = flow_dv_validate_action_set_tag(dev, actions,
5217                                                               action_flags,
5218                                                               attr, error);
5219                         if (ret < 0)
5220                                 return ret;
5221                         /* Count all modify-header actions as one action. */
5222                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5223                                 ++actions_n;
5224                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5225                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5226                         break;
5227                 case RTE_FLOW_ACTION_TYPE_DROP:
5228                         ret = mlx5_flow_validate_action_drop(action_flags,
5229                                                              attr, error);
5230                         if (ret < 0)
5231                                 return ret;
5232                         action_flags |= MLX5_FLOW_ACTION_DROP;
5233                         ++actions_n;
5234                         break;
5235                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5236                         ret = mlx5_flow_validate_action_queue(actions,
5237                                                               action_flags, dev,
5238                                                               attr, error);
5239                         if (ret < 0)
5240                                 return ret;
5241                         queue_index = ((const struct rte_flow_action_queue *)
5242                                                         (actions->conf))->index;
5243                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
5244                         ++actions_n;
5245                         break;
5246                 case RTE_FLOW_ACTION_TYPE_RSS:
5247                         rss = actions->conf;
5248                         ret = mlx5_flow_validate_action_rss(actions,
5249                                                             action_flags, dev,
5250                                                             attr, item_flags,
5251                                                             error);
5252                         if (ret < 0)
5253                                 return ret;
5254                         if (rss != NULL && rss->queue_num)
5255                                 queue_index = rss->queue[0];
5256                         action_flags |= MLX5_FLOW_ACTION_RSS;
5257                         ++actions_n;
5258                         break;
5259                 case RTE_FLOW_ACTION_TYPE_COUNT:
5260                         ret = flow_dv_validate_action_count(dev, error);
5261                         if (ret < 0)
5262                                 return ret;
5263                         action_flags |= MLX5_FLOW_ACTION_COUNT;
5264                         ++actions_n;
5265                         break;
5266                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5267                         if (flow_dv_validate_action_pop_vlan(dev,
5268                                                              action_flags,
5269                                                              actions,
5270                                                              item_flags, attr,
5271                                                              error))
5272                                 return -rte_errno;
5273                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5274                         ++actions_n;
5275                         break;
5276                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5277                         ret = flow_dv_validate_action_push_vlan(dev,
5278                                                                 action_flags,
5279                                                                 vlan_m,
5280                                                                 actions, attr,
5281                                                                 error);
5282                         if (ret < 0)
5283                                 return ret;
5284                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5285                         ++actions_n;
5286                         break;
5287                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5288                         ret = flow_dv_validate_action_set_vlan_pcp
5289                                                 (action_flags, actions, error);
5290                         if (ret < 0)
5291                                 return ret;
5292                         /* Count PCP with push_vlan command. */
5293                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5294                         break;
5295                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5296                         ret = flow_dv_validate_action_set_vlan_vid
5297                                                 (item_flags, action_flags,
5298                                                  actions, error);
5299                         if (ret < 0)
5300                                 return ret;
5301                         /* Count VID with push_vlan command. */
5302                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5303                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
5304                         break;
5305                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5306                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5307                         ret = flow_dv_validate_action_l2_encap(dev,
5308                                                                action_flags,
5309                                                                actions, attr,
5310                                                                error);
5311                         if (ret < 0)
5312                                 return ret;
5313                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
5314                         ++actions_n;
5315                         break;
5316                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5317                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5318                         ret = flow_dv_validate_action_decap(dev, action_flags,
5319                                                             attr, error);
5320                         if (ret < 0)
5321                                 return ret;
5322                         action_flags |= MLX5_FLOW_ACTION_DECAP;
5323                         ++actions_n;
5324                         break;
5325                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5326                         ret = flow_dv_validate_action_raw_encap_decap
5327                                 (dev, NULL, actions->conf, attr, &action_flags,
5328                                  &actions_n, error);
5329                         if (ret < 0)
5330                                 return ret;
5331                         break;
5332                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5333                         decap = actions->conf;
5334                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5335                                 ;
5336                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5337                                 encap = NULL;
5338                                 actions--;
5339                         } else {
5340                                 encap = actions->conf;
5341                         }
5342                         ret = flow_dv_validate_action_raw_encap_decap
5343                                            (dev,
5344                                             decap ? decap : &empty_decap, encap,
5345                                             attr, &action_flags, &actions_n,
5346                                             error);
5347                         if (ret < 0)
5348                                 return ret;
5349                         break;
5350                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5351                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5352                         ret = flow_dv_validate_action_modify_mac(action_flags,
5353                                                                  actions,
5354                                                                  item_flags,
5355                                                                  error);
5356                         if (ret < 0)
5357                                 return ret;
5358                         /* Count all modify-header actions as one action. */
5359                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5360                                 ++actions_n;
5361                         action_flags |= actions->type ==
5362                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5363                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
5364                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
5365                         /*
5366                          * Even if the source and destination MAC addresses have
5367                          * overlap in the header with 4B alignment, the convert
5368                          * function will handle them separately and 4 SW actions
5369                          * will be created. And 2 actions will be added each
5370                          * time no matter how many bytes of address will be set.
5371                          */
5372                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5373                         break;
5374                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5375                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5376                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
5377                                                                   actions,
5378                                                                   item_flags,
5379                                                                   error);
5380                         if (ret < 0)
5381                                 return ret;
5382                         /* Count all modify-header actions as one action. */
5383                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5384                                 ++actions_n;
5385                         action_flags |= actions->type ==
5386                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5387                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5388                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
5389                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5390                         break;
5391                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5392                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5393                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
5394                                                                   actions,
5395                                                                   item_flags,
5396                                                                   error);
5397                         if (ret < 0)
5398                                 return ret;
5399                         if (item_ipv6_proto == IPPROTO_ICMPV6)
5400                                 return rte_flow_error_set(error, ENOTSUP,
5401                                         RTE_FLOW_ERROR_TYPE_ACTION,
5402                                         actions,
5403                                         "Can't change header "
5404                                         "with ICMPv6 proto");
5405                         /* Count all modify-header actions as one action. */
5406                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5407                                 ++actions_n;
5408                         action_flags |= actions->type ==
5409                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5410                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5411                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
5412                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5413                         break;
5414                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5415                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5416                         ret = flow_dv_validate_action_modify_tp(action_flags,
5417                                                                 actions,
5418                                                                 item_flags,
5419                                                                 error);
5420                         if (ret < 0)
5421                                 return ret;
5422                         /* Count all modify-header actions as one action. */
5423                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5424                                 ++actions_n;
5425                         action_flags |= actions->type ==
5426                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5427                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
5428                                                 MLX5_FLOW_ACTION_SET_TP_DST;
5429                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5430                         break;
5431                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5432                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5433                         ret = flow_dv_validate_action_modify_ttl(action_flags,
5434                                                                  actions,
5435                                                                  item_flags,
5436                                                                  error);
5437                         if (ret < 0)
5438                                 return ret;
5439                         /* Count all modify-header actions as one action. */
5440                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5441                                 ++actions_n;
5442                         action_flags |= actions->type ==
5443                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
5444                                                 MLX5_FLOW_ACTION_SET_TTL :
5445                                                 MLX5_FLOW_ACTION_DEC_TTL;
5446                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5447                         break;
5448                 case RTE_FLOW_ACTION_TYPE_JUMP:
5449                         ret = flow_dv_validate_action_jump(actions,
5450                                                            action_flags,
5451                                                            attr, external,
5452                                                            error);
5453                         if (ret)
5454                                 return ret;
5455                         ++actions_n;
5456                         action_flags |= MLX5_FLOW_ACTION_JUMP;
5457                         break;
5458                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5459                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5460                         ret = flow_dv_validate_action_modify_tcp_seq
5461                                                                 (action_flags,
5462                                                                  actions,
5463                                                                  item_flags,
5464                                                                  error);
5465                         if (ret < 0)
5466                                 return ret;
5467                         /* Count all modify-header actions as one action. */
5468                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5469                                 ++actions_n;
5470                         action_flags |= actions->type ==
5471                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5472                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5473                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5474                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5475                         break;
5476                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5477                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5478                         ret = flow_dv_validate_action_modify_tcp_ack
5479                                                                 (action_flags,
5480                                                                  actions,
5481                                                                  item_flags,
5482                                                                  error);
5483                         if (ret < 0)
5484                                 return ret;
5485                         /* Count all modify-header actions as one action. */
5486                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5487                                 ++actions_n;
5488                         action_flags |= actions->type ==
5489                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5490                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
5491                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5492                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5493                         break;
5494                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5495                         break;
5496                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5497                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5498                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5499                         break;
5500                 case RTE_FLOW_ACTION_TYPE_METER:
5501                         ret = mlx5_flow_validate_action_meter(dev,
5502                                                               action_flags,
5503                                                               actions, attr,
5504                                                               error);
5505                         if (ret < 0)
5506                                 return ret;
5507                         action_flags |= MLX5_FLOW_ACTION_METER;
5508                         ++actions_n;
5509                         /* Meter action will add one more TAG action. */
5510                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
5511                         break;
5512                 case RTE_FLOW_ACTION_TYPE_AGE:
5513                         ret = flow_dv_validate_action_age(action_flags,
5514                                                           actions, dev,
5515                                                           error);
5516                         if (ret < 0)
5517                                 return ret;
5518                         action_flags |= MLX5_FLOW_ACTION_AGE;
5519                         ++actions_n;
5520                         break;
5521                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5522                         ret = flow_dv_validate_action_modify_ipv4_dscp
5523                                                          (action_flags,
5524                                                           actions,
5525                                                           item_flags,
5526                                                           error);
5527                         if (ret < 0)
5528                                 return ret;
5529                         /* Count all modify-header actions as one action. */
5530                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5531                                 ++actions_n;
5532                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5533                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5534                         break;
5535                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5536                         ret = flow_dv_validate_action_modify_ipv6_dscp
5537                                                                 (action_flags,
5538                                                                  actions,
5539                                                                  item_flags,
5540                                                                  error);
5541                         if (ret < 0)
5542                                 return ret;
5543                         /* Count all modify-header actions as one action. */
5544                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5545                                 ++actions_n;
5546                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5547                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5548                         break;
5549                 default:
5550                         return rte_flow_error_set(error, ENOTSUP,
5551                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5552                                                   actions,
5553                                                   "action not supported");
5554                 }
5555         }
5556         /*
5557          * Validate the drop action mutual exclusion with other actions.
5558          * Drop action is mutually-exclusive with any other action, except for
5559          * Count action.
5560          */
5561         if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5562             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5563                 return rte_flow_error_set(error, EINVAL,
5564                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5565                                           "Drop action is mutually-exclusive "
5566                                           "with any other action, except for "
5567                                           "Count action");
5568         /* Eswitch has few restrictions on using items and actions */
5569         if (attr->transfer) {
5570                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5571                     action_flags & MLX5_FLOW_ACTION_FLAG)
5572                         return rte_flow_error_set(error, ENOTSUP,
5573                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5574                                                   NULL,
5575                                                   "unsupported action FLAG");
5576                 if (!mlx5_flow_ext_mreg_supported(dev) &&
5577                     action_flags & MLX5_FLOW_ACTION_MARK)
5578                         return rte_flow_error_set(error, ENOTSUP,
5579                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5580                                                   NULL,
5581                                                   "unsupported action MARK");
5582                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5583                         return rte_flow_error_set(error, ENOTSUP,
5584                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5585                                                   NULL,
5586                                                   "unsupported action QUEUE");
5587                 if (action_flags & MLX5_FLOW_ACTION_RSS)
5588                         return rte_flow_error_set(error, ENOTSUP,
5589                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5590                                                   NULL,
5591                                                   "unsupported action RSS");
5592                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5593                         return rte_flow_error_set(error, EINVAL,
5594                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5595                                                   actions,
5596                                                   "no fate action is found");
5597         } else {
5598                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5599                         return rte_flow_error_set(error, EINVAL,
5600                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5601                                                   actions,
5602                                                   "no fate action is found");
5603         }
5604         /* Continue validation for Xcap actions.*/
5605         if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) && (queue_index == 0xFFFF ||
5606             mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5607                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5608                     MLX5_FLOW_XCAP_ACTIONS)
5609                         return rte_flow_error_set(error, ENOTSUP,
5610                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5611                                                   NULL, "encap and decap "
5612                                                   "combination aren't supported");
5613                 if (!attr->transfer && attr->ingress && (action_flags &
5614                                                         MLX5_FLOW_ACTION_ENCAP))
5615                         return rte_flow_error_set(error, ENOTSUP,
5616                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5617                                                   NULL, "encap is not supported"
5618                                                   " for ingress traffic");
5619         }
5620         /* Hairpin flow will add one more TAG action. */
5621         if (hairpin > 0)
5622                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5623         /* extra metadata enabled: one more TAG action will be add. */
5624         if (dev_conf->dv_flow_en &&
5625             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5626             mlx5_flow_ext_mreg_supported(dev))
5627                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5628         if ((uint32_t)rw_act_num >
5629                         flow_dv_modify_hdr_action_max(dev, is_root)) {
5630                 return rte_flow_error_set(error, ENOTSUP,
5631                                           RTE_FLOW_ERROR_TYPE_ACTION,
5632                                           NULL, "too many header modify"
5633                                           " actions to support");
5634         }
5635         return 0;
5636 }
5637
5638 /**
5639  * Internal preparation function. Allocates the DV flow size,
5640  * this size is constant.
5641  *
5642  * @param[in] dev
5643  *   Pointer to the rte_eth_dev structure.
5644  * @param[in] attr
5645  *   Pointer to the flow attributes.
5646  * @param[in] items
5647  *   Pointer to the list of items.
5648  * @param[in] actions
5649  *   Pointer to the list of actions.
5650  * @param[out] error
5651  *   Pointer to the error structure.
5652  *
5653  * @return
5654  *   Pointer to mlx5_flow object on success,
5655  *   otherwise NULL and rte_errno is set.
5656  */
5657 static struct mlx5_flow *
5658 flow_dv_prepare(struct rte_eth_dev *dev,
5659                 const struct rte_flow_attr *attr __rte_unused,
5660                 const struct rte_flow_item items[] __rte_unused,
5661                 const struct rte_flow_action actions[] __rte_unused,
5662                 struct rte_flow_error *error)
5663 {
5664         uint32_t handle_idx = 0;
5665         struct mlx5_flow *dev_flow;
5666         struct mlx5_flow_handle *dev_handle;
5667         struct mlx5_priv *priv = dev->data->dev_private;
5668
5669         /* In case of corrupting the memory. */
5670         if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5671                 rte_flow_error_set(error, ENOSPC,
5672                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5673                                    "not free temporary device flow");
5674                 return NULL;
5675         }
5676         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5677                                    &handle_idx);
5678         if (!dev_handle) {
5679                 rte_flow_error_set(error, ENOMEM,
5680                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5681                                    "not enough memory to create flow handle");
5682                 return NULL;
5683         }
5684         /* No multi-thread supporting. */
5685         dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5686         dev_flow->handle = dev_handle;
5687         dev_flow->handle_idx = handle_idx;
5688         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5689         /*
5690          * The matching value needs to be cleared to 0 before using. In the
5691          * past, it will be automatically cleared when using rte_*alloc
5692          * API. The time consumption will be almost the same as before.
5693          */
5694         memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5695         dev_flow->ingress = attr->ingress;
5696         dev_flow->dv.transfer = attr->transfer;
5697         return dev_flow;
5698 }
5699
5700 #ifdef RTE_LIBRTE_MLX5_DEBUG
5701 /**
5702  * Sanity check for match mask and value. Similar to check_valid_spec() in
5703  * kernel driver. If unmasked bit is present in value, it returns failure.
5704  *
5705  * @param match_mask
5706  *   pointer to match mask buffer.
5707  * @param match_value
5708  *   pointer to match value buffer.
5709  *
5710  * @return
5711  *   0 if valid, -EINVAL otherwise.
5712  */
5713 static int
5714 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5715 {
5716         uint8_t *m = match_mask;
5717         uint8_t *v = match_value;
5718         unsigned int i;
5719
5720         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5721                 if (v[i] & ~m[i]) {
5722                         DRV_LOG(ERR,
5723                                 "match_value differs from match_criteria"
5724                                 " %p[%u] != %p[%u]",
5725                                 match_value, i, match_mask, i);
5726                         return -EINVAL;
5727                 }
5728         }
5729         return 0;
5730 }
5731 #endif
5732
5733 /**
5734  * Add match of ip_version.
5735  *
5736  * @param[in] group
5737  *   Flow group.
5738  * @param[in] headers_v
5739  *   Values header pointer.
5740  * @param[in] headers_m
5741  *   Masks header pointer.
5742  * @param[in] ip_version
5743  *   The IP version to set.
5744  */
5745 static inline void
5746 flow_dv_set_match_ip_version(uint32_t group,
5747                              void *headers_v,
5748                              void *headers_m,
5749                              uint8_t ip_version)
5750 {
5751         if (group == 0)
5752                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5753         else
5754                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5755                          ip_version);
5756         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5757         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5758         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5759 }
5760
5761 /**
5762  * Add Ethernet item to matcher and to the value.
5763  *
5764  * @param[in, out] matcher
5765  *   Flow matcher.
5766  * @param[in, out] key
5767  *   Flow matcher value.
5768  * @param[in] item
5769  *   Flow pattern to translate.
5770  * @param[in] inner
5771  *   Item is inner pattern.
5772  */
5773 static void
5774 flow_dv_translate_item_eth(void *matcher, void *key,
5775                            const struct rte_flow_item *item, int inner,
5776                            uint32_t group)
5777 {
5778         const struct rte_flow_item_eth *eth_m = item->mask;
5779         const struct rte_flow_item_eth *eth_v = item->spec;
5780         const struct rte_flow_item_eth nic_mask = {
5781                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5782                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5783                 .type = RTE_BE16(0xffff),
5784         };
5785         void *headers_m;
5786         void *headers_v;
5787         char *l24_v;
5788         unsigned int i;
5789
5790         if (!eth_v)
5791                 return;
5792         if (!eth_m)
5793                 eth_m = &nic_mask;
5794         if (inner) {
5795                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5796                                          inner_headers);
5797                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5798         } else {
5799                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5800                                          outer_headers);
5801                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5802         }
5803         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5804                &eth_m->dst, sizeof(eth_m->dst));
5805         /* The value must be in the range of the mask. */
5806         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5807         for (i = 0; i < sizeof(eth_m->dst); ++i)
5808                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5809         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5810                &eth_m->src, sizeof(eth_m->src));
5811         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5812         /* The value must be in the range of the mask. */
5813         for (i = 0; i < sizeof(eth_m->dst); ++i)
5814                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5815         if (eth_v->type) {
5816                 /* When ethertype is present set mask for tagged VLAN. */
5817                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5818                 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5819                 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5820                     eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5821                         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5822                                  1);
5823                         /* Return here to avoid setting match on ethertype. */
5824                         return;
5825                 }
5826         }
5827         /*
5828          * HW supports match on one Ethertype, the Ethertype following the last
5829          * VLAN tag of the packet (see PRM).
5830          * Set match on ethertype only if ETH header is not followed by VLAN.
5831          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5832          * ethertype, and use ip_version field instead.
5833          */
5834         if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5835             eth_m->type == 0xFFFF) {
5836                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5837         } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5838                    eth_m->type == 0xFFFF) {
5839                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5840         } else {
5841                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5842                          rte_be_to_cpu_16(eth_m->type));
5843                 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5844                                      ethertype);
5845                 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5846         }
5847 }
5848
5849 /**
5850  * Add VLAN item to matcher and to the value.
5851  *
5852  * @param[in, out] dev_flow
5853  *   Flow descriptor.
5854  * @param[in, out] matcher
5855  *   Flow matcher.
5856  * @param[in, out] key
5857  *   Flow matcher value.
5858  * @param[in] item
5859  *   Flow pattern to translate.
5860  * @param[in] inner
5861  *   Item is inner pattern.
5862  */
5863 static void
5864 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5865                             void *matcher, void *key,
5866                             const struct rte_flow_item *item,
5867                             int inner, uint32_t group)
5868 {
5869         const struct rte_flow_item_vlan *vlan_m = item->mask;
5870         const struct rte_flow_item_vlan *vlan_v = item->spec;
5871         void *headers_m;
5872         void *headers_v;
5873         uint16_t tci_m;
5874         uint16_t tci_v;
5875
5876         if (inner) {
5877                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5878                                          inner_headers);
5879                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5880         } else {
5881                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5882                                          outer_headers);
5883                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5884                 /*
5885                  * This is workaround, masks are not supported,
5886                  * and pre-validated.
5887                  */
5888                 if (vlan_v)
5889                         dev_flow->handle->vf_vlan.tag =
5890                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5891         }
5892         /*
5893          * When VLAN item exists in flow, mark packet as tagged,
5894          * even if TCI is not specified.
5895          */
5896         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5897         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5898         if (!vlan_v)
5899                 return;
5900         if (!vlan_m)
5901                 vlan_m = &rte_flow_item_vlan_mask;
5902         tci_m = rte_be_to_cpu_16(vlan_m->tci);
5903         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5904         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5905         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5906         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5907         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5908         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5909         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5910         /*
5911          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5912          * ethertype, and use ip_version field instead.
5913          */
5914         if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5915             vlan_m->inner_type == 0xFFFF) {
5916                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5917         } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5918                    vlan_m->inner_type == 0xFFFF) {
5919                 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5920         } else {
5921                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5922                          rte_be_to_cpu_16(vlan_m->inner_type));
5923                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5924                          rte_be_to_cpu_16(vlan_m->inner_type &
5925                                           vlan_v->inner_type));
5926         }
5927 }
5928
5929 /**
5930  * Add IPV4 item to matcher and to the value.
5931  *
5932  * @param[in, out] matcher
5933  *   Flow matcher.
5934  * @param[in, out] key
5935  *   Flow matcher value.
5936  * @param[in] item
5937  *   Flow pattern to translate.
5938  * @param[in] item_flags
5939  *   Bit-fields that holds the items detected until now.
5940  * @param[in] inner
5941  *   Item is inner pattern.
5942  * @param[in] group
5943  *   The group to insert the rule.
5944  */
5945 static void
5946 flow_dv_translate_item_ipv4(void *matcher, void *key,
5947                             const struct rte_flow_item *item,
5948                             const uint64_t item_flags,
5949                             int inner, uint32_t group)
5950 {
5951         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5952         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5953         const struct rte_flow_item_ipv4 nic_mask = {
5954                 .hdr = {
5955                         .src_addr = RTE_BE32(0xffffffff),
5956                         .dst_addr = RTE_BE32(0xffffffff),
5957                         .type_of_service = 0xff,
5958                         .next_proto_id = 0xff,
5959                         .time_to_live = 0xff,
5960                 },
5961         };
5962         void *headers_m;
5963         void *headers_v;
5964         char *l24_m;
5965         char *l24_v;
5966         uint8_t tos;
5967
5968         if (inner) {
5969                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5970                                          inner_headers);
5971                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5972         } else {
5973                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5974                                          outer_headers);
5975                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5976         }
5977         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5978         /*
5979          * On outer header (which must contains L2), or inner header with L2,
5980          * set cvlan_tag mask bit to mark this packet as untagged.
5981          * This should be done even if item->spec is empty.
5982          */
5983         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
5984                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5985         if (!ipv4_v)
5986                 return;
5987         if (!ipv4_m)
5988                 ipv4_m = &nic_mask;
5989         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5990                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5991         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5992                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5993         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5994         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5995         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5996                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5997         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5998                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
5999         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6000         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6001         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6002         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6003                  ipv4_m->hdr.type_of_service);
6004         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6005         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6006                  ipv4_m->hdr.type_of_service >> 2);
6007         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6008         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6009                  ipv4_m->hdr.next_proto_id);
6010         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6011                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6012         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6013                  ipv4_m->hdr.time_to_live);
6014         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6015                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6016 }
6017
6018 /**
6019  * Add IPV6 item to matcher and to the value.
6020  *
6021  * @param[in, out] matcher
6022  *   Flow matcher.
6023  * @param[in, out] key
6024  *   Flow matcher value.
6025  * @param[in] item
6026  *   Flow pattern to translate.
6027  * @param[in] item_flags
6028  *   Bit-fields that holds the items detected until now.
6029  * @param[in] inner
6030  *   Item is inner pattern.
6031  * @param[in] group
6032  *   The group to insert the rule.
6033  */
6034 static void
6035 flow_dv_translate_item_ipv6(void *matcher, void *key,
6036                             const struct rte_flow_item *item,
6037                             const uint64_t item_flags,
6038                             int inner, uint32_t group)
6039 {
6040         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6041         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6042         const struct rte_flow_item_ipv6 nic_mask = {
6043                 .hdr = {
6044                         .src_addr =
6045                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6046                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6047                         .dst_addr =
6048                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
6049                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
6050                         .vtc_flow = RTE_BE32(0xffffffff),
6051                         .proto = 0xff,
6052                         .hop_limits = 0xff,
6053                 },
6054         };
6055         void *headers_m;
6056         void *headers_v;
6057         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6058         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6059         char *l24_m;
6060         char *l24_v;
6061         uint32_t vtc_m;
6062         uint32_t vtc_v;
6063         int i;
6064         int size;
6065
6066         if (inner) {
6067                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6068                                          inner_headers);
6069                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6070         } else {
6071                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6072                                          outer_headers);
6073                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6074         }
6075         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6076         /*
6077          * On outer header (which must contains L2), or inner header with L2,
6078          * set cvlan_tag mask bit to mark this packet as untagged.
6079          * This should be done even if item->spec is empty.
6080          */
6081         if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6082                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6083         if (!ipv6_v)
6084                 return;
6085         if (!ipv6_m)
6086                 ipv6_m = &nic_mask;
6087         size = sizeof(ipv6_m->hdr.dst_addr);
6088         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6089                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6090         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6091                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6092         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6093         for (i = 0; i < size; ++i)
6094                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6095         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6096                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6097         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6098                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
6099         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6100         for (i = 0; i < size; ++i)
6101                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6102         /* TOS. */
6103         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6104         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6105         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6106         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6107         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6108         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6109         /* Label. */
6110         if (inner) {
6111                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6112                          vtc_m);
6113                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6114                          vtc_v);
6115         } else {
6116                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6117                          vtc_m);
6118                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6119                          vtc_v);
6120         }
6121         /* Protocol. */
6122         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6123                  ipv6_m->hdr.proto);
6124         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6125                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6126         /* Hop limit. */
6127         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6128                  ipv6_m->hdr.hop_limits);
6129         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6130                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6131 }
6132
6133 /**
6134  * Add TCP item to matcher and to the value.
6135  *
6136  * @param[in, out] matcher
6137  *   Flow matcher.
6138  * @param[in, out] key
6139  *   Flow matcher value.
6140  * @param[in] item
6141  *   Flow pattern to translate.
6142  * @param[in] inner
6143  *   Item is inner pattern.
6144  */
6145 static void
6146 flow_dv_translate_item_tcp(void *matcher, void *key,
6147                            const struct rte_flow_item *item,
6148                            int inner)
6149 {
6150         const struct rte_flow_item_tcp *tcp_m = item->mask;
6151         const struct rte_flow_item_tcp *tcp_v = item->spec;
6152         void *headers_m;
6153         void *headers_v;
6154
6155         if (inner) {
6156                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6157                                          inner_headers);
6158                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6159         } else {
6160                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6161                                          outer_headers);
6162                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6163         }
6164         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6165         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6166         if (!tcp_v)
6167                 return;
6168         if (!tcp_m)
6169                 tcp_m = &rte_flow_item_tcp_mask;
6170         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6171                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
6172         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6173                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6174         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6175                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6176         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6177                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6178         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6179                  tcp_m->hdr.tcp_flags);
6180         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6181                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6182 }
6183
6184 /**
6185  * Add UDP item to matcher and to the value.
6186  *
6187  * @param[in, out] matcher
6188  *   Flow matcher.
6189  * @param[in, out] key
6190  *   Flow matcher value.
6191  * @param[in] item
6192  *   Flow pattern to translate.
6193  * @param[in] inner
6194  *   Item is inner pattern.
6195  */
6196 static void
6197 flow_dv_translate_item_udp(void *matcher, void *key,
6198                            const struct rte_flow_item *item,
6199                            int inner)
6200 {
6201         const struct rte_flow_item_udp *udp_m = item->mask;
6202         const struct rte_flow_item_udp *udp_v = item->spec;
6203         void *headers_m;
6204         void *headers_v;
6205
6206         if (inner) {
6207                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6208                                          inner_headers);
6209                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6210         } else {
6211                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6212                                          outer_headers);
6213                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6214         }
6215         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6216         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6217         if (!udp_v)
6218                 return;
6219         if (!udp_m)
6220                 udp_m = &rte_flow_item_udp_mask;
6221         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6222                  rte_be_to_cpu_16(udp_m->hdr.src_port));
6223         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6224                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6225         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6226                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
6227         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6228                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6229 }
6230
6231 /**
6232  * Add GRE optional Key item to matcher and to the value.
6233  *
6234  * @param[in, out] matcher
6235  *   Flow matcher.
6236  * @param[in, out] key
6237  *   Flow matcher value.
6238  * @param[in] item
6239  *   Flow pattern to translate.
6240  * @param[in] inner
6241  *   Item is inner pattern.
6242  */
6243 static void
6244 flow_dv_translate_item_gre_key(void *matcher, void *key,
6245                                    const struct rte_flow_item *item)
6246 {
6247         const rte_be32_t *key_m = item->mask;
6248         const rte_be32_t *key_v = item->spec;
6249         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6250         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6251         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6252
6253         /* GRE K bit must be on and should already be validated */
6254         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6255         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6256         if (!key_v)
6257                 return;
6258         if (!key_m)
6259                 key_m = &gre_key_default_mask;
6260         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6261                  rte_be_to_cpu_32(*key_m) >> 8);
6262         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6263                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6264         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6265                  rte_be_to_cpu_32(*key_m) & 0xFF);
6266         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6267                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6268 }
6269
6270 /**
6271  * Add GRE item to matcher and to the value.
6272  *
6273  * @param[in, out] matcher
6274  *   Flow matcher.
6275  * @param[in, out] key
6276  *   Flow matcher value.
6277  * @param[in] item
6278  *   Flow pattern to translate.
6279  * @param[in] inner
6280  *   Item is inner pattern.
6281  */
6282 static void
6283 flow_dv_translate_item_gre(void *matcher, void *key,
6284                            const struct rte_flow_item *item,
6285                            int inner)
6286 {
6287         const struct rte_flow_item_gre *gre_m = item->mask;
6288         const struct rte_flow_item_gre *gre_v = item->spec;
6289         void *headers_m;
6290         void *headers_v;
6291         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6292         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6293         struct {
6294                 union {
6295                         __extension__
6296                         struct {
6297                                 uint16_t version:3;
6298                                 uint16_t rsvd0:9;
6299                                 uint16_t s_present:1;
6300                                 uint16_t k_present:1;
6301                                 uint16_t rsvd_bit1:1;
6302                                 uint16_t c_present:1;
6303                         };
6304                         uint16_t value;
6305                 };
6306         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6307
6308         if (inner) {
6309                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6310                                          inner_headers);
6311                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6312         } else {
6313                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6314                                          outer_headers);
6315                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6316         }
6317         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6318         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6319         if (!gre_v)
6320                 return;
6321         if (!gre_m)
6322                 gre_m = &rte_flow_item_gre_mask;
6323         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6324                  rte_be_to_cpu_16(gre_m->protocol));
6325         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6326                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6327         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6328         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6329         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6330                  gre_crks_rsvd0_ver_m.c_present);
6331         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6332                  gre_crks_rsvd0_ver_v.c_present &
6333                  gre_crks_rsvd0_ver_m.c_present);
6334         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6335                  gre_crks_rsvd0_ver_m.k_present);
6336         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6337                  gre_crks_rsvd0_ver_v.k_present &
6338                  gre_crks_rsvd0_ver_m.k_present);
6339         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6340                  gre_crks_rsvd0_ver_m.s_present);
6341         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6342                  gre_crks_rsvd0_ver_v.s_present &
6343                  gre_crks_rsvd0_ver_m.s_present);
6344 }
6345
6346 /**
6347  * Add NVGRE item to matcher and to the value.
6348  *
6349  * @param[in, out] matcher
6350  *   Flow matcher.
6351  * @param[in, out] key
6352  *   Flow matcher value.
6353  * @param[in] item
6354  *   Flow pattern to translate.
6355  * @param[in] inner
6356  *   Item is inner pattern.
6357  */
6358 static void
6359 flow_dv_translate_item_nvgre(void *matcher, void *key,
6360                              const struct rte_flow_item *item,
6361                              int inner)
6362 {
6363         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6364         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6365         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6366         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6367         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6368         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6369         char *gre_key_m;
6370         char *gre_key_v;
6371         int size;
6372         int i;
6373
6374         /* For NVGRE, GRE header fields must be set with defined values. */
6375         const struct rte_flow_item_gre gre_spec = {
6376                 .c_rsvd0_ver = RTE_BE16(0x2000),
6377                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6378         };
6379         const struct rte_flow_item_gre gre_mask = {
6380                 .c_rsvd0_ver = RTE_BE16(0xB000),
6381                 .protocol = RTE_BE16(UINT16_MAX),
6382         };
6383         const struct rte_flow_item gre_item = {
6384                 .spec = &gre_spec,
6385                 .mask = &gre_mask,
6386                 .last = NULL,
6387         };
6388         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6389         if (!nvgre_v)
6390                 return;
6391         if (!nvgre_m)
6392                 nvgre_m = &rte_flow_item_nvgre_mask;
6393         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6394         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6395         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6396         memcpy(gre_key_m, tni_flow_id_m, size);
6397         for (i = 0; i < size; ++i)
6398                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6399 }
6400
6401 /**
6402  * Add VXLAN item to matcher and to the value.
6403  *
6404  * @param[in, out] matcher
6405  *   Flow matcher.
6406  * @param[in, out] key
6407  *   Flow matcher value.
6408  * @param[in] item
6409  *   Flow pattern to translate.
6410  * @param[in] inner
6411  *   Item is inner pattern.
6412  */
6413 static void
6414 flow_dv_translate_item_vxlan(void *matcher, void *key,
6415                              const struct rte_flow_item *item,
6416                              int inner)
6417 {
6418         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6419         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6420         void *headers_m;
6421         void *headers_v;
6422         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6423         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6424         char *vni_m;
6425         char *vni_v;
6426         uint16_t dport;
6427         int size;
6428         int i;
6429
6430         if (inner) {
6431                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6432                                          inner_headers);
6433                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6434         } else {
6435                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6436                                          outer_headers);
6437                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6438         }
6439         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6440                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6441         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6442                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6443                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6444         }
6445         if (!vxlan_v)
6446                 return;
6447         if (!vxlan_m)
6448                 vxlan_m = &rte_flow_item_vxlan_mask;
6449         size = sizeof(vxlan_m->vni);
6450         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6451         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6452         memcpy(vni_m, vxlan_m->vni, size);
6453         for (i = 0; i < size; ++i)
6454                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6455 }
6456
6457 /**
6458  * Add VXLAN-GPE item to matcher and to the value.
6459  *
6460  * @param[in, out] matcher
6461  *   Flow matcher.
6462  * @param[in, out] key
6463  *   Flow matcher value.
6464  * @param[in] item
6465  *   Flow pattern to translate.
6466  * @param[in] inner
6467  *   Item is inner pattern.
6468  */
6469
6470 static void
6471 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6472                                  const struct rte_flow_item *item, int inner)
6473 {
6474         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6475         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6476         void *headers_m;
6477         void *headers_v;
6478         void *misc_m =
6479                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6480         void *misc_v =
6481                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6482         char *vni_m;
6483         char *vni_v;
6484         uint16_t dport;
6485         int size;
6486         int i;
6487         uint8_t flags_m = 0xff;
6488         uint8_t flags_v = 0xc;
6489
6490         if (inner) {
6491                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6492                                          inner_headers);
6493                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6494         } else {
6495                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6496                                          outer_headers);
6497                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6498         }
6499         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6500                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6501         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6502                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6503                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6504         }
6505         if (!vxlan_v)
6506                 return;
6507         if (!vxlan_m)
6508                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6509         size = sizeof(vxlan_m->vni);
6510         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6511         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6512         memcpy(vni_m, vxlan_m->vni, size);
6513         for (i = 0; i < size; ++i)
6514                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6515         if (vxlan_m->flags) {
6516                 flags_m = vxlan_m->flags;
6517                 flags_v = vxlan_v->flags;
6518         }
6519         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6520         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6521         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6522                  vxlan_m->protocol);
6523         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6524                  vxlan_v->protocol);
6525 }
6526
6527 /**
6528  * Add Geneve item to matcher and to the value.
6529  *
6530  * @param[in, out] matcher
6531  *   Flow matcher.
6532  * @param[in, out] key
6533  *   Flow matcher value.
6534  * @param[in] item
6535  *   Flow pattern to translate.
6536  * @param[in] inner
6537  *   Item is inner pattern.
6538  */
6539
6540 static void
6541 flow_dv_translate_item_geneve(void *matcher, void *key,
6542                               const struct rte_flow_item *item, int inner)
6543 {
6544         const struct rte_flow_item_geneve *geneve_m = item->mask;
6545         const struct rte_flow_item_geneve *geneve_v = item->spec;
6546         void *headers_m;
6547         void *headers_v;
6548         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6549         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6550         uint16_t dport;
6551         uint16_t gbhdr_m;
6552         uint16_t gbhdr_v;
6553         char *vni_m;
6554         char *vni_v;
6555         size_t size, i;
6556
6557         if (inner) {
6558                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6559                                          inner_headers);
6560                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6561         } else {
6562                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6563                                          outer_headers);
6564                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6565         }
6566         dport = MLX5_UDP_PORT_GENEVE;
6567         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6568                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6569                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6570         }
6571         if (!geneve_v)
6572                 return;
6573         if (!geneve_m)
6574                 geneve_m = &rte_flow_item_geneve_mask;
6575         size = sizeof(geneve_m->vni);
6576         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6577         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6578         memcpy(vni_m, geneve_m->vni, size);
6579         for (i = 0; i < size; ++i)
6580                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6581         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6582                  rte_be_to_cpu_16(geneve_m->protocol));
6583         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6584                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6585         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6586         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6587         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6588                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6589         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6590                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6591         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6592                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6593         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6594                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6595                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6596 }
6597
6598 /**
6599  * Add MPLS item to matcher and to the value.
6600  *
6601  * @param[in, out] matcher
6602  *   Flow matcher.
6603  * @param[in, out] key
6604  *   Flow matcher value.
6605  * @param[in] item
6606  *   Flow pattern to translate.
6607  * @param[in] prev_layer
6608  *   The protocol layer indicated in previous item.
6609  * @param[in] inner
6610  *   Item is inner pattern.
6611  */
6612 static void
6613 flow_dv_translate_item_mpls(void *matcher, void *key,
6614                             const struct rte_flow_item *item,
6615                             uint64_t prev_layer,
6616                             int inner)
6617 {
6618         const uint32_t *in_mpls_m = item->mask;
6619         const uint32_t *in_mpls_v = item->spec;
6620         uint32_t *out_mpls_m = 0;
6621         uint32_t *out_mpls_v = 0;
6622         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6623         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6624         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6625                                      misc_parameters_2);
6626         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6627         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6628         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6629
6630         switch (prev_layer) {
6631         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6632                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6633                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6634                          MLX5_UDP_PORT_MPLS);
6635                 break;
6636         case MLX5_FLOW_LAYER_GRE:
6637                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6638                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6639                          RTE_ETHER_TYPE_MPLS);
6640                 break;
6641         default:
6642                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6643                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6644                          IPPROTO_MPLS);
6645                 break;
6646         }
6647         if (!in_mpls_v)
6648                 return;
6649         if (!in_mpls_m)
6650                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6651         switch (prev_layer) {
6652         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6653                 out_mpls_m =
6654                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6655                                                  outer_first_mpls_over_udp);
6656                 out_mpls_v =
6657                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6658                                                  outer_first_mpls_over_udp);
6659                 break;
6660         case MLX5_FLOW_LAYER_GRE:
6661                 out_mpls_m =
6662                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6663                                                  outer_first_mpls_over_gre);
6664                 out_mpls_v =
6665                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6666                                                  outer_first_mpls_over_gre);
6667                 break;
6668         default:
6669                 /* Inner MPLS not over GRE is not supported. */
6670                 if (!inner) {
6671                         out_mpls_m =
6672                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6673                                                          misc2_m,
6674                                                          outer_first_mpls);
6675                         out_mpls_v =
6676                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6677                                                          misc2_v,
6678                                                          outer_first_mpls);
6679                 }
6680                 break;
6681         }
6682         if (out_mpls_m && out_mpls_v) {
6683                 *out_mpls_m = *in_mpls_m;
6684                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6685         }
6686 }
6687
6688 /**
6689  * Add metadata register item to matcher
6690  *
6691  * @param[in, out] matcher
6692  *   Flow matcher.
6693  * @param[in, out] key
6694  *   Flow matcher value.
6695  * @param[in] reg_type
6696  *   Type of device metadata register
6697  * @param[in] value
6698  *   Register value
6699  * @param[in] mask
6700  *   Register mask
6701  */
6702 static void
6703 flow_dv_match_meta_reg(void *matcher, void *key,
6704                        enum modify_reg reg_type,
6705                        uint32_t data, uint32_t mask)
6706 {
6707         void *misc2_m =
6708                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6709         void *misc2_v =
6710                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6711         uint32_t temp;
6712
6713         data &= mask;
6714         switch (reg_type) {
6715         case REG_A:
6716                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6717                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6718                 break;
6719         case REG_B:
6720                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6721                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6722                 break;
6723         case REG_C_0:
6724                 /*
6725                  * The metadata register C0 field might be divided into
6726                  * source vport index and META item value, we should set
6727                  * this field according to specified mask, not as whole one.
6728                  */
6729                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6730                 temp |= mask;
6731                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6732                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6733                 temp &= ~mask;
6734                 temp |= data;
6735                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6736                 break;
6737         case REG_C_1:
6738                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6739                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6740                 break;
6741         case REG_C_2:
6742                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6743                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6744                 break;
6745         case REG_C_3:
6746                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6747                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6748                 break;
6749         case REG_C_4:
6750                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6751                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6752                 break;
6753         case REG_C_5:
6754                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6755                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6756                 break;
6757         case REG_C_6:
6758                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6759                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6760                 break;
6761         case REG_C_7:
6762                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6763                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6764                 break;
6765         default:
6766                 MLX5_ASSERT(false);
6767                 break;
6768         }
6769 }
6770
6771 /**
6772  * Add MARK item to matcher
6773  *
6774  * @param[in] dev
6775  *   The device to configure through.
6776  * @param[in, out] matcher
6777  *   Flow matcher.
6778  * @param[in, out] key
6779  *   Flow matcher value.
6780  * @param[in] item
6781  *   Flow pattern to translate.
6782  */
6783 static void
6784 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6785                             void *matcher, void *key,
6786                             const struct rte_flow_item *item)
6787 {
6788         struct mlx5_priv *priv = dev->data->dev_private;
6789         const struct rte_flow_item_mark *mark;
6790         uint32_t value;
6791         uint32_t mask;
6792
6793         mark = item->mask ? (const void *)item->mask :
6794                             &rte_flow_item_mark_mask;
6795         mask = mark->id & priv->sh->dv_mark_mask;
6796         mark = (const void *)item->spec;
6797         MLX5_ASSERT(mark);
6798         value = mark->id & priv->sh->dv_mark_mask & mask;
6799         if (mask) {
6800                 enum modify_reg reg;
6801
6802                 /* Get the metadata register index for the mark. */
6803                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6804                 MLX5_ASSERT(reg > 0);
6805                 if (reg == REG_C_0) {
6806                         struct mlx5_priv *priv = dev->data->dev_private;
6807                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6808                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6809
6810                         mask &= msk_c0;
6811                         mask <<= shl_c0;
6812                         value <<= shl_c0;
6813                 }
6814                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6815         }
6816 }
6817
6818 /**
6819  * Add META item to matcher
6820  *
6821  * @param[in] dev
6822  *   The devich to configure through.
6823  * @param[in, out] matcher
6824  *   Flow matcher.
6825  * @param[in, out] key
6826  *   Flow matcher value.
6827  * @param[in] attr
6828  *   Attributes of flow that includes this item.
6829  * @param[in] item
6830  *   Flow pattern to translate.
6831  */
6832 static void
6833 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6834                             void *matcher, void *key,
6835                             const struct rte_flow_attr *attr,
6836                             const struct rte_flow_item *item)
6837 {
6838         const struct rte_flow_item_meta *meta_m;
6839         const struct rte_flow_item_meta *meta_v;
6840
6841         meta_m = (const void *)item->mask;
6842         if (!meta_m)
6843                 meta_m = &rte_flow_item_meta_mask;
6844         meta_v = (const void *)item->spec;
6845         if (meta_v) {
6846                 int reg;
6847                 uint32_t value = meta_v->data;
6848                 uint32_t mask = meta_m->data;
6849
6850                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6851                 if (reg < 0)
6852                         return;
6853                 /*
6854                  * In datapath code there is no endianness
6855                  * coversions for perfromance reasons, all
6856                  * pattern conversions are done in rte_flow.
6857                  */
6858                 value = rte_cpu_to_be_32(value);
6859                 mask = rte_cpu_to_be_32(mask);
6860                 if (reg == REG_C_0) {
6861                         struct mlx5_priv *priv = dev->data->dev_private;
6862                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6863                         uint32_t shl_c0 = rte_bsf32(msk_c0);
6864 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6865                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6866
6867                         value >>= shr_c0;
6868                         mask >>= shr_c0;
6869 #endif
6870                         value <<= shl_c0;
6871                         mask <<= shl_c0;
6872                         MLX5_ASSERT(msk_c0);
6873                         MLX5_ASSERT(!(~msk_c0 & mask));
6874                 }
6875                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6876         }
6877 }
6878
6879 /**
6880  * Add vport metadata Reg C0 item to matcher
6881  *
6882  * @param[in, out] matcher
6883  *   Flow matcher.
6884  * @param[in, out] key
6885  *   Flow matcher value.
6886  * @param[in] reg
6887  *   Flow pattern to translate.
6888  */
6889 static void
6890 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6891                                   uint32_t value, uint32_t mask)
6892 {
6893         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6894 }
6895
6896 /**
6897  * Add tag item to matcher
6898  *
6899  * @param[in] dev
6900  *   The devich to configure through.
6901  * @param[in, out] matcher
6902  *   Flow matcher.
6903  * @param[in, out] key
6904  *   Flow matcher value.
6905  * @param[in] item
6906  *   Flow pattern to translate.
6907  */
6908 static void
6909 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6910                                 void *matcher, void *key,
6911                                 const struct rte_flow_item *item)
6912 {
6913         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6914         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6915         uint32_t mask, value;
6916
6917         MLX5_ASSERT(tag_v);
6918         value = tag_v->data;
6919         mask = tag_m ? tag_m->data : UINT32_MAX;
6920         if (tag_v->id == REG_C_0) {
6921                 struct mlx5_priv *priv = dev->data->dev_private;
6922                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6923                 uint32_t shl_c0 = rte_bsf32(msk_c0);
6924
6925                 mask &= msk_c0;
6926                 mask <<= shl_c0;
6927                 value <<= shl_c0;
6928         }
6929         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6930 }
6931
6932 /**
6933  * Add TAG item to matcher
6934  *
6935  * @param[in] dev
6936  *   The devich to configure through.
6937  * @param[in, out] matcher
6938  *   Flow matcher.
6939  * @param[in, out] key
6940  *   Flow matcher value.
6941  * @param[in] item
6942  *   Flow pattern to translate.
6943  */
6944 static void
6945 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6946                            void *matcher, void *key,
6947                            const struct rte_flow_item *item)
6948 {
6949         const struct rte_flow_item_tag *tag_v = item->spec;
6950         const struct rte_flow_item_tag *tag_m = item->mask;
6951         enum modify_reg reg;
6952
6953         MLX5_ASSERT(tag_v);
6954         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6955         /* Get the metadata register index for the tag. */
6956         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6957         MLX5_ASSERT(reg > 0);
6958         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6959 }
6960
6961 /**
6962  * Add source vport match to the specified matcher.
6963  *
6964  * @param[in, out] matcher
6965  *   Flow matcher.
6966  * @param[in, out] key
6967  *   Flow matcher value.
6968  * @param[in] port
6969  *   Source vport value to match
6970  * @param[in] mask
6971  *   Mask
6972  */
6973 static void
6974 flow_dv_translate_item_source_vport(void *matcher, void *key,
6975                                     int16_t port, uint16_t mask)
6976 {
6977         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6978         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6979
6980         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6981         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6982 }
6983
6984 /**
6985  * Translate port-id item to eswitch match on  port-id.
6986  *
6987  * @param[in] dev
6988  *   The devich to configure through.
6989  * @param[in, out] matcher
6990  *   Flow matcher.
6991  * @param[in, out] key
6992  *   Flow matcher value.
6993  * @param[in] item
6994  *   Flow pattern to translate.
6995  *
6996  * @return
6997  *   0 on success, a negative errno value otherwise.
6998  */
6999 static int
7000 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7001                                void *key, const struct rte_flow_item *item)
7002 {
7003         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7004         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7005         struct mlx5_priv *priv;
7006         uint16_t mask, id;
7007
7008         mask = pid_m ? pid_m->id : 0xffff;
7009         id = pid_v ? pid_v->id : dev->data->port_id;
7010         priv = mlx5_port_to_eswitch_info(id, item == NULL);
7011         if (!priv)
7012                 return -rte_errno;
7013         /* Translate to vport field or to metadata, depending on mode. */
7014         if (priv->vport_meta_mask)
7015                 flow_dv_translate_item_meta_vport(matcher, key,
7016                                                   priv->vport_meta_tag,
7017                                                   priv->vport_meta_mask);
7018         else
7019                 flow_dv_translate_item_source_vport(matcher, key,
7020                                                     priv->vport_id, mask);
7021         return 0;
7022 }
7023
7024 /**
7025  * Add ICMP6 item to matcher and to the value.
7026  *
7027  * @param[in, out] matcher
7028  *   Flow matcher.
7029  * @param[in, out] key
7030  *   Flow matcher value.
7031  * @param[in] item
7032  *   Flow pattern to translate.
7033  * @param[in] inner
7034  *   Item is inner pattern.
7035  */
7036 static void
7037 flow_dv_translate_item_icmp6(void *matcher, void *key,
7038                               const struct rte_flow_item *item,
7039                               int inner)
7040 {
7041         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7042         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7043         void *headers_m;
7044         void *headers_v;
7045         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7046                                      misc_parameters_3);
7047         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7048         if (inner) {
7049                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7050                                          inner_headers);
7051                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7052         } else {
7053                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7054                                          outer_headers);
7055                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7056         }
7057         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7058         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7059         if (!icmp6_v)
7060                 return;
7061         if (!icmp6_m)
7062                 icmp6_m = &rte_flow_item_icmp6_mask;
7063         /*
7064          * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7065          * If only the protocol is specified, no need to match the frag.
7066          */
7067         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7068         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7069         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7070         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7071                  icmp6_v->type & icmp6_m->type);
7072         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7073         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7074                  icmp6_v->code & icmp6_m->code);
7075 }
7076
7077 /**
7078  * Add ICMP item to matcher and to the value.
7079  *
7080  * @param[in, out] matcher
7081  *   Flow matcher.
7082  * @param[in, out] key
7083  *   Flow matcher value.
7084  * @param[in] item
7085  *   Flow pattern to translate.
7086  * @param[in] inner
7087  *   Item is inner pattern.
7088  */
7089 static void
7090 flow_dv_translate_item_icmp(void *matcher, void *key,
7091                             const struct rte_flow_item *item,
7092                             int inner)
7093 {
7094         const struct rte_flow_item_icmp *icmp_m = item->mask;
7095         const struct rte_flow_item_icmp *icmp_v = item->spec;
7096         void *headers_m;
7097         void *headers_v;
7098         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7099                                      misc_parameters_3);
7100         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7101         if (inner) {
7102                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7103                                          inner_headers);
7104                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7105         } else {
7106                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7107                                          outer_headers);
7108                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7109         }
7110         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7111         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7112         if (!icmp_v)
7113                 return;
7114         if (!icmp_m)
7115                 icmp_m = &rte_flow_item_icmp_mask;
7116         /*
7117          * Force flow only to match the non-fragmented IPv4 ICMP packets.
7118          * If only the protocol is specified, no need to match the frag.
7119          */
7120         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7121         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7122         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7123                  icmp_m->hdr.icmp_type);
7124         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7125                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7126         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7127                  icmp_m->hdr.icmp_code);
7128         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7129                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7130 }
7131
7132 /**
7133  * Add GTP item to matcher and to the value.
7134  *
7135  * @param[in, out] matcher
7136  *   Flow matcher.
7137  * @param[in, out] key
7138  *   Flow matcher value.
7139  * @param[in] item
7140  *   Flow pattern to translate.
7141  * @param[in] inner
7142  *   Item is inner pattern.
7143  */
7144 static void
7145 flow_dv_translate_item_gtp(void *matcher, void *key,
7146                            const struct rte_flow_item *item, int inner)
7147 {
7148         const struct rte_flow_item_gtp *gtp_m = item->mask;
7149         const struct rte_flow_item_gtp *gtp_v = item->spec;
7150         void *headers_m;
7151         void *headers_v;
7152         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7153                                      misc_parameters_3);
7154         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7155         uint16_t dport = RTE_GTPU_UDP_PORT;
7156
7157         if (inner) {
7158                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7159                                          inner_headers);
7160                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7161         } else {
7162                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7163                                          outer_headers);
7164                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7165         }
7166         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7167                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7168                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7169         }
7170         if (!gtp_v)
7171                 return;
7172         if (!gtp_m)
7173                 gtp_m = &rte_flow_item_gtp_mask;
7174         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7175                  gtp_m->v_pt_rsv_flags);
7176         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7177                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7178         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7179         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7180                  gtp_v->msg_type & gtp_m->msg_type);
7181         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7182                  rte_be_to_cpu_32(gtp_m->teid));
7183         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7184                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7185 }
7186
7187 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7188
7189 #define HEADER_IS_ZERO(match_criteria, headers)                              \
7190         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
7191                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7192
7193 /**
7194  * Calculate flow matcher enable bitmap.
7195  *
7196  * @param match_criteria
7197  *   Pointer to flow matcher criteria.
7198  *
7199  * @return
7200  *   Bitmap of enabled fields.
7201  */
7202 static uint8_t
7203 flow_dv_matcher_enable(uint32_t *match_criteria)
7204 {
7205         uint8_t match_criteria_enable;
7206
7207         match_criteria_enable =
7208                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7209                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7210         match_criteria_enable |=
7211                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7212                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7213         match_criteria_enable |=
7214                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7215                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7216         match_criteria_enable |=
7217                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7218                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7219         match_criteria_enable |=
7220                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7221                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7222         return match_criteria_enable;
7223 }
7224
7225
7226 /**
7227  * Get a flow table.
7228  *
7229  * @param[in, out] dev
7230  *   Pointer to rte_eth_dev structure.
7231  * @param[in] table_id
7232  *   Table id to use.
7233  * @param[in] egress
7234  *   Direction of the table.
7235  * @param[in] transfer
7236  *   E-Switch or NIC flow.
7237  * @param[out] error
7238  *   pointer to error structure.
7239  *
7240  * @return
7241  *   Returns tables resource based on the index, NULL in case of failed.
7242  */
7243 static struct mlx5_flow_tbl_resource *
7244 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7245                          uint32_t table_id, uint8_t egress,
7246                          uint8_t transfer,
7247                          struct rte_flow_error *error)
7248 {
7249         struct mlx5_priv *priv = dev->data->dev_private;
7250         struct mlx5_dev_ctx_shared *sh = priv->sh;
7251         struct mlx5_flow_tbl_resource *tbl;
7252         union mlx5_flow_tbl_key table_key = {
7253                 {
7254                         .table_id = table_id,
7255                         .reserved = 0,
7256                         .domain = !!transfer,
7257                         .direction = !!egress,
7258                 }
7259         };
7260         struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7261                                                          table_key.v64);
7262         struct mlx5_flow_tbl_data_entry *tbl_data;
7263         uint32_t idx = 0;
7264         int ret;
7265         void *domain;
7266
7267         if (pos) {
7268                 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7269                                         entry);
7270                 tbl = &tbl_data->tbl;
7271                 rte_atomic32_inc(&tbl->refcnt);
7272                 return tbl;
7273         }
7274         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7275         if (!tbl_data) {
7276                 rte_flow_error_set(error, ENOMEM,
7277                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7278                                    NULL,
7279                                    "cannot allocate flow table data entry");
7280                 return NULL;
7281         }
7282         tbl_data->idx = idx;
7283         tbl = &tbl_data->tbl;
7284         pos = &tbl_data->entry;
7285         if (transfer)
7286                 domain = sh->fdb_domain;
7287         else if (egress)
7288                 domain = sh->tx_domain;
7289         else
7290                 domain = sh->rx_domain;
7291         tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
7292         if (!tbl->obj) {
7293                 rte_flow_error_set(error, ENOMEM,
7294                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7295                                    NULL, "cannot create flow table object");
7296                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7297                 return NULL;
7298         }
7299         /*
7300          * No multi-threads now, but still better to initialize the reference
7301          * count before insert it into the hash list.
7302          */
7303         rte_atomic32_init(&tbl->refcnt);
7304         /* Jump action reference count is initialized here. */
7305         rte_atomic32_init(&tbl_data->jump.refcnt);
7306         pos->key = table_key.v64;
7307         ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7308         if (ret < 0) {
7309                 rte_flow_error_set(error, -ret,
7310                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7311                                    "cannot insert flow table data entry");
7312                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7313                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7314         }
7315         rte_atomic32_inc(&tbl->refcnt);
7316         return tbl;
7317 }
7318
7319 /**
7320  * Release a flow table.
7321  *
7322  * @param[in] dev
7323  *   Pointer to rte_eth_dev structure.
7324  * @param[in] tbl
7325  *   Table resource to be released.
7326  *
7327  * @return
7328  *   Returns 0 if table was released, else return 1;
7329  */
7330 static int
7331 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7332                              struct mlx5_flow_tbl_resource *tbl)
7333 {
7334         struct mlx5_priv *priv = dev->data->dev_private;
7335         struct mlx5_dev_ctx_shared *sh = priv->sh;
7336         struct mlx5_flow_tbl_data_entry *tbl_data =
7337                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7338
7339         if (!tbl)
7340                 return 0;
7341         if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7342                 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7343
7344                 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
7345                 tbl->obj = NULL;
7346                 /* remove the entry from the hash list and free memory. */
7347                 mlx5_hlist_remove(sh->flow_tbls, pos);
7348                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7349                                 tbl_data->idx);
7350                 return 0;
7351         }
7352         return 1;
7353 }
7354
7355 /**
7356  * Register the flow matcher.
7357  *
7358  * @param[in, out] dev
7359  *   Pointer to rte_eth_dev structure.
7360  * @param[in, out] matcher
7361  *   Pointer to flow matcher.
7362  * @param[in, out] key
7363  *   Pointer to flow table key.
7364  * @parm[in, out] dev_flow
7365  *   Pointer to the dev_flow.
7366  * @param[out] error
7367  *   pointer to error structure.
7368  *
7369  * @return
7370  *   0 on success otherwise -errno and errno is set.
7371  */
7372 static int
7373 flow_dv_matcher_register(struct rte_eth_dev *dev,
7374                          struct mlx5_flow_dv_matcher *matcher,
7375                          union mlx5_flow_tbl_key *key,
7376                          struct mlx5_flow *dev_flow,
7377                          struct rte_flow_error *error)
7378 {
7379         struct mlx5_priv *priv = dev->data->dev_private;
7380         struct mlx5_dev_ctx_shared *sh = priv->sh;
7381         struct mlx5_flow_dv_matcher *cache_matcher;
7382         struct mlx5dv_flow_matcher_attr dv_attr = {
7383                 .type = IBV_FLOW_ATTR_NORMAL,
7384                 .match_mask = (void *)&matcher->mask,
7385         };
7386         struct mlx5_flow_tbl_resource *tbl;
7387         struct mlx5_flow_tbl_data_entry *tbl_data;
7388
7389         tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7390                                        key->domain, error);
7391         if (!tbl)
7392                 return -rte_errno;      /* No need to refill the error info */
7393         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7394         /* Lookup from cache. */
7395         LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7396                 if (matcher->crc == cache_matcher->crc &&
7397                     matcher->priority == cache_matcher->priority &&
7398                     !memcmp((const void *)matcher->mask.buf,
7399                             (const void *)cache_matcher->mask.buf,
7400                             cache_matcher->mask.size)) {
7401                         DRV_LOG(DEBUG,
7402                                 "%s group %u priority %hd use %s "
7403                                 "matcher %p: refcnt %d++",
7404                                 key->domain ? "FDB" : "NIC", key->table_id,
7405                                 cache_matcher->priority,
7406                                 key->direction ? "tx" : "rx",
7407                                 (void *)cache_matcher,
7408                                 rte_atomic32_read(&cache_matcher->refcnt));
7409                         rte_atomic32_inc(&cache_matcher->refcnt);
7410                         dev_flow->handle->dvh.matcher = cache_matcher;
7411                         /* old matcher should not make the table ref++. */
7412                         flow_dv_tbl_resource_release(dev, tbl);
7413                         return 0;
7414                 }
7415         }
7416         /* Register new matcher. */
7417         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
7418         if (!cache_matcher) {
7419                 flow_dv_tbl_resource_release(dev, tbl);
7420                 return rte_flow_error_set(error, ENOMEM,
7421                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7422                                           "cannot allocate matcher memory");
7423         }
7424         *cache_matcher = *matcher;
7425         dv_attr.match_criteria_enable =
7426                 flow_dv_matcher_enable(cache_matcher->mask.buf);
7427         dv_attr.priority = matcher->priority;
7428         if (key->direction)
7429                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7430         cache_matcher->matcher_object =
7431                 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
7432         if (!cache_matcher->matcher_object) {
7433                 rte_free(cache_matcher);
7434 #ifdef HAVE_MLX5DV_DR
7435                 flow_dv_tbl_resource_release(dev, tbl);
7436 #endif
7437                 return rte_flow_error_set(error, ENOMEM,
7438                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7439                                           NULL, "cannot create matcher");
7440         }
7441         /* Save the table information */
7442         cache_matcher->tbl = tbl;
7443         rte_atomic32_init(&cache_matcher->refcnt);
7444         /* only matcher ref++, table ref++ already done above in get API. */
7445         rte_atomic32_inc(&cache_matcher->refcnt);
7446         LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7447         dev_flow->handle->dvh.matcher = cache_matcher;
7448         DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7449                 key->domain ? "FDB" : "NIC", key->table_id,
7450                 cache_matcher->priority,
7451                 key->direction ? "tx" : "rx", (void *)cache_matcher,
7452                 rte_atomic32_read(&cache_matcher->refcnt));
7453         return 0;
7454 }
7455
7456 /**
7457  * Find existing tag resource or create and register a new one.
7458  *
7459  * @param dev[in, out]
7460  *   Pointer to rte_eth_dev structure.
7461  * @param[in, out] tag_be24
7462  *   Tag value in big endian then R-shift 8.
7463  * @parm[in, out] dev_flow
7464  *   Pointer to the dev_flow.
7465  * @param[out] error
7466  *   pointer to error structure.
7467  *
7468  * @return
7469  *   0 on success otherwise -errno and errno is set.
7470  */
7471 static int
7472 flow_dv_tag_resource_register
7473                         (struct rte_eth_dev *dev,
7474                          uint32_t tag_be24,
7475                          struct mlx5_flow *dev_flow,
7476                          struct rte_flow_error *error)
7477 {
7478         struct mlx5_priv *priv = dev->data->dev_private;
7479         struct mlx5_dev_ctx_shared *sh = priv->sh;
7480         struct mlx5_flow_dv_tag_resource *cache_resource;
7481         struct mlx5_hlist_entry *entry;
7482
7483         /* Lookup a matching resource from cache. */
7484         entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7485         if (entry) {
7486                 cache_resource = container_of
7487                         (entry, struct mlx5_flow_dv_tag_resource, entry);
7488                 rte_atomic32_inc(&cache_resource->refcnt);
7489                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7490                 dev_flow->dv.tag_resource = cache_resource;
7491                 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7492                         (void *)cache_resource,
7493                         rte_atomic32_read(&cache_resource->refcnt));
7494                 return 0;
7495         }
7496         /* Register new resource. */
7497         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7498                                        &dev_flow->handle->dvh.rix_tag);
7499         if (!cache_resource)
7500                 return rte_flow_error_set(error, ENOMEM,
7501                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7502                                           "cannot allocate resource memory");
7503         cache_resource->entry.key = (uint64_t)tag_be24;
7504         cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
7505         if (!cache_resource->action) {
7506                 rte_free(cache_resource);
7507                 return rte_flow_error_set(error, ENOMEM,
7508                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7509                                           NULL, "cannot create action");
7510         }
7511         rte_atomic32_init(&cache_resource->refcnt);
7512         rte_atomic32_inc(&cache_resource->refcnt);
7513         if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7514                 mlx5_glue->destroy_flow_action(cache_resource->action);
7515                 rte_free(cache_resource);
7516                 return rte_flow_error_set(error, EEXIST,
7517                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7518                                           NULL, "cannot insert tag");
7519         }
7520         dev_flow->dv.tag_resource = cache_resource;
7521         DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7522                 (void *)cache_resource,
7523                 rte_atomic32_read(&cache_resource->refcnt));
7524         return 0;
7525 }
7526
7527 /**
7528  * Release the tag.
7529  *
7530  * @param dev
7531  *   Pointer to Ethernet device.
7532  * @param tag_idx
7533  *   Tag index.
7534  *
7535  * @return
7536  *   1 while a reference on it exists, 0 when freed.
7537  */
7538 static int
7539 flow_dv_tag_release(struct rte_eth_dev *dev,
7540                     uint32_t tag_idx)
7541 {
7542         struct mlx5_priv *priv = dev->data->dev_private;
7543         struct mlx5_dev_ctx_shared *sh = priv->sh;
7544         struct mlx5_flow_dv_tag_resource *tag;
7545
7546         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7547         if (!tag)
7548                 return 0;
7549         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7550                 dev->data->port_id, (void *)tag,
7551                 rte_atomic32_read(&tag->refcnt));
7552         if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7553                 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
7554                 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7555                 DRV_LOG(DEBUG, "port %u tag %p: removed",
7556                         dev->data->port_id, (void *)tag);
7557                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7558                 return 0;
7559         }
7560         return 1;
7561 }
7562
7563 /**
7564  * Translate port ID action to vport.
7565  *
7566  * @param[in] dev
7567  *   Pointer to rte_eth_dev structure.
7568  * @param[in] action
7569  *   Pointer to the port ID action.
7570  * @param[out] dst_port_id
7571  *   The target port ID.
7572  * @param[out] error
7573  *   Pointer to the error structure.
7574  *
7575  * @return
7576  *   0 on success, a negative errno value otherwise and rte_errno is set.
7577  */
7578 static int
7579 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7580                                  const struct rte_flow_action *action,
7581                                  uint32_t *dst_port_id,
7582                                  struct rte_flow_error *error)
7583 {
7584         uint32_t port;
7585         struct mlx5_priv *priv;
7586         const struct rte_flow_action_port_id *conf =
7587                         (const struct rte_flow_action_port_id *)action->conf;
7588
7589         port = conf->original ? dev->data->port_id : conf->id;
7590         priv = mlx5_port_to_eswitch_info(port, false);
7591         if (!priv)
7592                 return rte_flow_error_set(error, -rte_errno,
7593                                           RTE_FLOW_ERROR_TYPE_ACTION,
7594                                           NULL,
7595                                           "No eswitch info was found for port");
7596 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7597         /*
7598          * This parameter is transferred to
7599          * mlx5dv_dr_action_create_dest_ib_port().
7600          */
7601         *dst_port_id = priv->dev_port;
7602 #else
7603         /*
7604          * Legacy mode, no LAG configurations is supported.
7605          * This parameter is transferred to
7606          * mlx5dv_dr_action_create_dest_vport().
7607          */
7608         *dst_port_id = priv->vport_id;
7609 #endif
7610         return 0;
7611 }
7612
7613 /**
7614  * Create a counter with aging configuration.
7615  *
7616  * @param[in] dev
7617  *   Pointer to rte_eth_dev structure.
7618  * @param[out] count
7619  *   Pointer to the counter action configuration.
7620  * @param[in] age
7621  *   Pointer to the aging action configuration.
7622  *
7623  * @return
7624  *   Index to flow counter on success, 0 otherwise.
7625  */
7626 static uint32_t
7627 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7628                                 struct mlx5_flow *dev_flow,
7629                                 const struct rte_flow_action_count *count,
7630                                 const struct rte_flow_action_age *age)
7631 {
7632         uint32_t counter;
7633         struct mlx5_age_param *age_param;
7634
7635         counter = flow_dv_counter_alloc(dev,
7636                                 count ? count->shared : 0,
7637                                 count ? count->id : 0,
7638                                 dev_flow->dv.group, !!age);
7639         if (!counter || age == NULL)
7640                 return counter;
7641         age_param  = flow_dv_counter_idx_get_age(dev, counter);
7642         /*
7643          * The counter age accuracy may have a bit delay. Have 3/4
7644          * second bias on the timeount in order to let it age in time.
7645          */
7646         age_param->context = age->context ? age->context :
7647                 (void *)(uintptr_t)(dev_flow->flow_idx);
7648         /*
7649          * The counter age accuracy may have a bit delay. Have 3/4
7650          * second bias on the timeount in order to let it age in time.
7651          */
7652         age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7653         /* Set expire time in unit of 0.1 sec. */
7654         age_param->port_id = dev->data->port_id;
7655         age_param->expire = age_param->timeout +
7656                         rte_rdtsc() / (rte_get_tsc_hz() / 10);
7657         rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7658         return counter;
7659 }
7660 /**
7661  * Add Tx queue matcher
7662  *
7663  * @param[in] dev
7664  *   Pointer to the dev struct.
7665  * @param[in, out] matcher
7666  *   Flow matcher.
7667  * @param[in, out] key
7668  *   Flow matcher value.
7669  * @param[in] item
7670  *   Flow pattern to translate.
7671  * @param[in] inner
7672  *   Item is inner pattern.
7673  */
7674 static void
7675 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7676                                 void *matcher, void *key,
7677                                 const struct rte_flow_item *item)
7678 {
7679         const struct mlx5_rte_flow_item_tx_queue *queue_m;
7680         const struct mlx5_rte_flow_item_tx_queue *queue_v;
7681         void *misc_m =
7682                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7683         void *misc_v =
7684                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7685         struct mlx5_txq_ctrl *txq;
7686         uint32_t queue;
7687
7688
7689         queue_m = (const void *)item->mask;
7690         if (!queue_m)
7691                 return;
7692         queue_v = (const void *)item->spec;
7693         if (!queue_v)
7694                 return;
7695         txq = mlx5_txq_get(dev, queue_v->queue);
7696         if (!txq)
7697                 return;
7698         queue = txq->obj->sq->id;
7699         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7700         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7701                  queue & queue_m->queue);
7702         mlx5_txq_release(dev, queue_v->queue);
7703 }
7704
7705 /**
7706  * Set the hash fields according to the @p flow information.
7707  *
7708  * @param[in] dev_flow
7709  *   Pointer to the mlx5_flow.
7710  * @param[in] rss_desc
7711  *   Pointer to the mlx5_flow_rss_desc.
7712  */
7713 static void
7714 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7715                        struct mlx5_flow_rss_desc *rss_desc)
7716 {
7717         uint64_t items = dev_flow->handle->layers;
7718         int rss_inner = 0;
7719         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7720
7721         dev_flow->hash_fields = 0;
7722 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7723         if (rss_desc->level >= 2) {
7724                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7725                 rss_inner = 1;
7726         }
7727 #endif
7728         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7729             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7730                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7731                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7732                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7733                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7734                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7735                         else
7736                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7737                 }
7738         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7739                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7740                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7741                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
7742                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7743                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
7744                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7745                         else
7746                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7747                 }
7748         }
7749         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7750             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7751                 if (rss_types & ETH_RSS_UDP) {
7752                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7753                                 dev_flow->hash_fields |=
7754                                                 IBV_RX_HASH_SRC_PORT_UDP;
7755                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7756                                 dev_flow->hash_fields |=
7757                                                 IBV_RX_HASH_DST_PORT_UDP;
7758                         else
7759                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7760                 }
7761         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7762                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7763                 if (rss_types & ETH_RSS_TCP) {
7764                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
7765                                 dev_flow->hash_fields |=
7766                                                 IBV_RX_HASH_SRC_PORT_TCP;
7767                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
7768                                 dev_flow->hash_fields |=
7769                                                 IBV_RX_HASH_DST_PORT_TCP;
7770                         else
7771                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7772                 }
7773         }
7774 }
7775
7776 /**
7777  * Fill the flow with DV spec, lock free
7778  * (mutex should be acquired by caller).
7779  *
7780  * @param[in] dev
7781  *   Pointer to rte_eth_dev structure.
7782  * @param[in, out] dev_flow
7783  *   Pointer to the sub flow.
7784  * @param[in] attr
7785  *   Pointer to the flow attributes.
7786  * @param[in] items
7787  *   Pointer to the list of items.
7788  * @param[in] actions
7789  *   Pointer to the list of actions.
7790  * @param[out] error
7791  *   Pointer to the error structure.
7792  *
7793  * @return
7794  *   0 on success, a negative errno value otherwise and rte_errno is set.
7795  */
7796 static int
7797 __flow_dv_translate(struct rte_eth_dev *dev,
7798                     struct mlx5_flow *dev_flow,
7799                     const struct rte_flow_attr *attr,
7800                     const struct rte_flow_item items[],
7801                     const struct rte_flow_action actions[],
7802                     struct rte_flow_error *error)
7803 {
7804         struct mlx5_priv *priv = dev->data->dev_private;
7805         struct mlx5_dev_config *dev_conf = &priv->config;
7806         struct rte_flow *flow = dev_flow->flow;
7807         struct mlx5_flow_handle *handle = dev_flow->handle;
7808         struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
7809                                               priv->rss_desc)
7810                                               [!!priv->flow_nested_idx];
7811         uint64_t item_flags = 0;
7812         uint64_t last_item = 0;
7813         uint64_t action_flags = 0;
7814         uint64_t priority = attr->priority;
7815         struct mlx5_flow_dv_matcher matcher = {
7816                 .mask = {
7817                         .size = sizeof(matcher.mask.buf),
7818                 },
7819         };
7820         int actions_n = 0;
7821         bool actions_end = false;
7822         union {
7823                 struct mlx5_flow_dv_modify_hdr_resource res;
7824                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
7825                             sizeof(struct mlx5_modification_cmd) *
7826                             (MLX5_MAX_MODIFY_NUM + 1)];
7827         } mhdr_dummy;
7828         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7829         const struct rte_flow_action_count *count = NULL;
7830         const struct rte_flow_action_age *age = NULL;
7831         union flow_dv_attr flow_attr = { .attr = 0 };
7832         uint32_t tag_be;
7833         union mlx5_flow_tbl_key tbl_key;
7834         uint32_t modify_action_position = UINT32_MAX;
7835         void *match_mask = matcher.mask.buf;
7836         void *match_value = dev_flow->dv.value.buf;
7837         uint8_t next_protocol = 0xff;
7838         struct rte_vlan_hdr vlan = { 0 };
7839         uint32_t table;
7840         int ret = 0;
7841
7842         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7843                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7844         ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7845                                        !!priv->fdb_def_rule, &table, error);
7846         if (ret)
7847                 return ret;
7848         dev_flow->dv.group = table;
7849         if (attr->transfer)
7850                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7851         if (priority == MLX5_FLOW_PRIO_RSVD)
7852                 priority = dev_conf->flow_prio - 1;
7853         /* number of actions must be set to 0 in case of dirty stack. */
7854         mhdr_res->actions_num = 0;
7855         for (; !actions_end ; actions++) {
7856                 const struct rte_flow_action_queue *queue;
7857                 const struct rte_flow_action_rss *rss;
7858                 const struct rte_flow_action *action = actions;
7859                 const uint8_t *rss_key;
7860                 const struct rte_flow_action_jump *jump_data;
7861                 const struct rte_flow_action_meter *mtr;
7862                 struct mlx5_flow_tbl_resource *tbl;
7863                 uint32_t port_id = 0;
7864                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7865                 int action_type = actions->type;
7866                 const struct rte_flow_action *found_action = NULL;
7867                 struct mlx5_flow_meter *fm = NULL;
7868
7869                 switch (action_type) {
7870                 case RTE_FLOW_ACTION_TYPE_VOID:
7871                         break;
7872                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7873                         if (flow_dv_translate_action_port_id(dev, action,
7874                                                              &port_id, error))
7875                                 return -rte_errno;
7876                         port_id_resource.port_id = port_id;
7877                         MLX5_ASSERT(!handle->rix_port_id_action);
7878                         if (flow_dv_port_id_action_resource_register
7879                             (dev, &port_id_resource, dev_flow, error))
7880                                 return -rte_errno;
7881                         dev_flow->dv.actions[actions_n++] =
7882                                         dev_flow->dv.port_id_action->action;
7883                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7884                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
7885                         break;
7886                 case RTE_FLOW_ACTION_TYPE_FLAG:
7887                         action_flags |= MLX5_FLOW_ACTION_FLAG;
7888                         dev_flow->handle->mark = 1;
7889                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7890                                 struct rte_flow_action_mark mark = {
7891                                         .id = MLX5_FLOW_MARK_DEFAULT,
7892                                 };
7893
7894                                 if (flow_dv_convert_action_mark(dev, &mark,
7895                                                                 mhdr_res,
7896                                                                 error))
7897                                         return -rte_errno;
7898                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7899                                 break;
7900                         }
7901                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7902                         /*
7903                          * Only one FLAG or MARK is supported per device flow
7904                          * right now. So the pointer to the tag resource must be
7905                          * zero before the register process.
7906                          */
7907                         MLX5_ASSERT(!handle->dvh.rix_tag);
7908                         if (flow_dv_tag_resource_register(dev, tag_be,
7909                                                           dev_flow, error))
7910                                 return -rte_errno;
7911                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7912                         dev_flow->dv.actions[actions_n++] =
7913                                         dev_flow->dv.tag_resource->action;
7914                         break;
7915                 case RTE_FLOW_ACTION_TYPE_MARK:
7916                         action_flags |= MLX5_FLOW_ACTION_MARK;
7917                         dev_flow->handle->mark = 1;
7918                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7919                                 const struct rte_flow_action_mark *mark =
7920                                         (const struct rte_flow_action_mark *)
7921                                                 actions->conf;
7922
7923                                 if (flow_dv_convert_action_mark(dev, mark,
7924                                                                 mhdr_res,
7925                                                                 error))
7926                                         return -rte_errno;
7927                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7928                                 break;
7929                         }
7930                         /* Fall-through */
7931                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7932                         /* Legacy (non-extensive) MARK action. */
7933                         tag_be = mlx5_flow_mark_set
7934                               (((const struct rte_flow_action_mark *)
7935                                (actions->conf))->id);
7936                         MLX5_ASSERT(!handle->dvh.rix_tag);
7937                         if (flow_dv_tag_resource_register(dev, tag_be,
7938                                                           dev_flow, error))
7939                                 return -rte_errno;
7940                         MLX5_ASSERT(dev_flow->dv.tag_resource);
7941                         dev_flow->dv.actions[actions_n++] =
7942                                         dev_flow->dv.tag_resource->action;
7943                         break;
7944                 case RTE_FLOW_ACTION_TYPE_SET_META:
7945                         if (flow_dv_convert_action_set_meta
7946                                 (dev, mhdr_res, attr,
7947                                  (const struct rte_flow_action_set_meta *)
7948                                   actions->conf, error))
7949                                 return -rte_errno;
7950                         action_flags |= MLX5_FLOW_ACTION_SET_META;
7951                         break;
7952                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7953                         if (flow_dv_convert_action_set_tag
7954                                 (dev, mhdr_res,
7955                                  (const struct rte_flow_action_set_tag *)
7956                                   actions->conf, error))
7957                                 return -rte_errno;
7958                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7959                         break;
7960                 case RTE_FLOW_ACTION_TYPE_DROP:
7961                         action_flags |= MLX5_FLOW_ACTION_DROP;
7962                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
7963                         break;
7964                 case RTE_FLOW_ACTION_TYPE_QUEUE:
7965                         queue = actions->conf;
7966                         rss_desc->queue_num = 1;
7967                         rss_desc->queue[0] = queue->index;
7968                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
7969                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7970                         break;
7971                 case RTE_FLOW_ACTION_TYPE_RSS:
7972                         rss = actions->conf;
7973                         memcpy(rss_desc->queue, rss->queue,
7974                                rss->queue_num * sizeof(uint16_t));
7975                         rss_desc->queue_num = rss->queue_num;
7976                         /* NULL RSS key indicates default RSS key. */
7977                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
7978                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7979                         /*
7980                          * rss->level and rss.types should be set in advance
7981                          * when expanding items for RSS.
7982                          */
7983                         action_flags |= MLX5_FLOW_ACTION_RSS;
7984                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
7985                         break;
7986                 case RTE_FLOW_ACTION_TYPE_AGE:
7987                 case RTE_FLOW_ACTION_TYPE_COUNT:
7988                         if (!dev_conf->devx) {
7989                                 return rte_flow_error_set
7990                                               (error, ENOTSUP,
7991                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7992                                                NULL,
7993                                                "count action not supported");
7994                         }
7995                         /* Save information first, will apply later. */
7996                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
7997                                 count = action->conf;
7998                         else
7999                                 age = action->conf;
8000                         action_flags |= MLX5_FLOW_ACTION_COUNT;
8001                         break;
8002                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8003                         dev_flow->dv.actions[actions_n++] =
8004                                                 priv->sh->pop_vlan_action;
8005                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8006                         break;
8007                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8008                         if (!(action_flags &
8009                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8010                                 flow_dev_get_vlan_info_from_items(items, &vlan);
8011                         vlan.eth_proto = rte_be_to_cpu_16
8012                              ((((const struct rte_flow_action_of_push_vlan *)
8013                                                    actions->conf)->ethertype));
8014                         found_action = mlx5_flow_find_action
8015                                         (actions + 1,
8016                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8017                         if (found_action)
8018                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8019                         found_action = mlx5_flow_find_action
8020                                         (actions + 1,
8021                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8022                         if (found_action)
8023                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8024                         if (flow_dv_create_action_push_vlan
8025                                             (dev, attr, &vlan, dev_flow, error))
8026                                 return -rte_errno;
8027                         dev_flow->dv.actions[actions_n++] =
8028                                         dev_flow->dv.push_vlan_res->action;
8029                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8030                         break;
8031                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8032                         /* of_vlan_push action handled this action */
8033                         MLX5_ASSERT(action_flags &
8034                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8035                         break;
8036                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8037                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8038                                 break;
8039                         flow_dev_get_vlan_info_from_items(items, &vlan);
8040                         mlx5_update_vlan_vid_pcp(actions, &vlan);
8041                         /* If no VLAN push - this is a modify header action */
8042                         if (flow_dv_convert_action_modify_vlan_vid
8043                                                 (mhdr_res, actions, error))
8044                                 return -rte_errno;
8045                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8046                         break;
8047                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8048                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8049                         if (flow_dv_create_action_l2_encap(dev, actions,
8050                                                            dev_flow,
8051                                                            attr->transfer,
8052                                                            error))
8053                                 return -rte_errno;
8054                         dev_flow->dv.actions[actions_n++] =
8055                                         dev_flow->dv.encap_decap->verbs_action;
8056                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8057                         break;
8058                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8059                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8060                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
8061                                                            attr->transfer,
8062                                                            error))
8063                                 return -rte_errno;
8064                         dev_flow->dv.actions[actions_n++] =
8065                                         dev_flow->dv.encap_decap->verbs_action;
8066                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8067                         break;
8068                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8069                         /* Handle encap with preceding decap. */
8070                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8071                                 if (flow_dv_create_action_raw_encap
8072                                         (dev, actions, dev_flow, attr, error))
8073                                         return -rte_errno;
8074                                 dev_flow->dv.actions[actions_n++] =
8075                                         dev_flow->dv.encap_decap->verbs_action;
8076                         } else {
8077                                 /* Handle encap without preceding decap. */
8078                                 if (flow_dv_create_action_l2_encap
8079                                     (dev, actions, dev_flow, attr->transfer,
8080                                      error))
8081                                         return -rte_errno;
8082                                 dev_flow->dv.actions[actions_n++] =
8083                                         dev_flow->dv.encap_decap->verbs_action;
8084                         }
8085                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
8086                         break;
8087                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8088                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8089                                 ;
8090                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8091                                 if (flow_dv_create_action_l2_decap
8092                                     (dev, dev_flow, attr->transfer, error))
8093                                         return -rte_errno;
8094                                 dev_flow->dv.actions[actions_n++] =
8095                                         dev_flow->dv.encap_decap->verbs_action;
8096                         }
8097                         /* If decap is followed by encap, handle it at encap. */
8098                         action_flags |= MLX5_FLOW_ACTION_DECAP;
8099                         break;
8100                 case RTE_FLOW_ACTION_TYPE_JUMP:
8101                         jump_data = action->conf;
8102                         ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8103                                                        jump_data->group,
8104                                                        !!priv->fdb_def_rule,
8105                                                        &table, error);
8106                         if (ret)
8107                                 return ret;
8108                         tbl = flow_dv_tbl_resource_get(dev, table,
8109                                                        attr->egress,
8110                                                        attr->transfer, error);
8111                         if (!tbl)
8112                                 return rte_flow_error_set
8113                                                 (error, errno,
8114                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8115                                                  NULL,
8116                                                  "cannot create jump action.");
8117                         if (flow_dv_jump_tbl_resource_register
8118                             (dev, tbl, dev_flow, error)) {
8119                                 flow_dv_tbl_resource_release(dev, tbl);
8120                                 return rte_flow_error_set
8121                                                 (error, errno,
8122                                                  RTE_FLOW_ERROR_TYPE_ACTION,
8123                                                  NULL,
8124                                                  "cannot create jump action.");
8125                         }
8126                         dev_flow->dv.actions[actions_n++] =
8127                                         dev_flow->dv.jump->action;
8128                         action_flags |= MLX5_FLOW_ACTION_JUMP;
8129                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8130                         break;
8131                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8132                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8133                         if (flow_dv_convert_action_modify_mac
8134                                         (mhdr_res, actions, error))
8135                                 return -rte_errno;
8136                         action_flags |= actions->type ==
8137                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8138                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
8139                                         MLX5_FLOW_ACTION_SET_MAC_DST;
8140                         break;
8141                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8142                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8143                         if (flow_dv_convert_action_modify_ipv4
8144                                         (mhdr_res, actions, error))
8145                                 return -rte_errno;
8146                         action_flags |= actions->type ==
8147                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8148                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
8149                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
8150                         break;
8151                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8152                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8153                         if (flow_dv_convert_action_modify_ipv6
8154                                         (mhdr_res, actions, error))
8155                                 return -rte_errno;
8156                         action_flags |= actions->type ==
8157                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8158                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
8159                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
8160                         break;
8161                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8162                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8163                         if (flow_dv_convert_action_modify_tp
8164                                         (mhdr_res, actions, items,
8165                                          &flow_attr, dev_flow, !!(action_flags &
8166                                          MLX5_FLOW_ACTION_DECAP), error))
8167                                 return -rte_errno;
8168                         action_flags |= actions->type ==
8169                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8170                                         MLX5_FLOW_ACTION_SET_TP_SRC :
8171                                         MLX5_FLOW_ACTION_SET_TP_DST;
8172                         break;
8173                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8174                         if (flow_dv_convert_action_modify_dec_ttl
8175                                         (mhdr_res, items, &flow_attr, dev_flow,
8176                                          !!(action_flags &
8177                                          MLX5_FLOW_ACTION_DECAP), error))
8178                                 return -rte_errno;
8179                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8180                         break;
8181                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8182                         if (flow_dv_convert_action_modify_ttl
8183                                         (mhdr_res, actions, items, &flow_attr,
8184                                          dev_flow, !!(action_flags &
8185                                          MLX5_FLOW_ACTION_DECAP), error))
8186                                 return -rte_errno;
8187                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8188                         break;
8189                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8190                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8191                         if (flow_dv_convert_action_modify_tcp_seq
8192                                         (mhdr_res, actions, error))
8193                                 return -rte_errno;
8194                         action_flags |= actions->type ==
8195                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8196                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
8197                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8198                         break;
8199
8200                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8201                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8202                         if (flow_dv_convert_action_modify_tcp_ack
8203                                         (mhdr_res, actions, error))
8204                                 return -rte_errno;
8205                         action_flags |= actions->type ==
8206                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8207                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
8208                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
8209                         break;
8210                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8211                         if (flow_dv_convert_action_set_reg
8212                                         (mhdr_res, actions, error))
8213                                 return -rte_errno;
8214                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8215                         break;
8216                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8217                         if (flow_dv_convert_action_copy_mreg
8218                                         (dev, mhdr_res, actions, error))
8219                                 return -rte_errno;
8220                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8221                         break;
8222                 case RTE_FLOW_ACTION_TYPE_METER:
8223                         mtr = actions->conf;
8224                         if (!flow->meter) {
8225                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8226                                                             attr, error);
8227                                 if (!fm)
8228                                         return rte_flow_error_set(error,
8229                                                 rte_errno,
8230                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8231                                                 NULL,
8232                                                 "meter not found "
8233                                                 "or invalid parameters");
8234                                 flow->meter = fm->idx;
8235                         }
8236                         /* Set the meter action. */
8237                         if (!fm) {
8238                                 fm = mlx5_ipool_get(priv->sh->ipool
8239                                                 [MLX5_IPOOL_MTR], flow->meter);
8240                                 if (!fm)
8241                                         return rte_flow_error_set(error,
8242                                                 rte_errno,
8243                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8244                                                 NULL,
8245                                                 "meter not found "
8246                                                 "or invalid parameters");
8247                         }
8248                         dev_flow->dv.actions[actions_n++] =
8249                                 fm->mfts->meter_action;
8250                         action_flags |= MLX5_FLOW_ACTION_METER;
8251                         break;
8252                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8253                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8254                                                               actions, error))
8255                                 return -rte_errno;
8256                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8257                         break;
8258                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8259                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8260                                                               actions, error))
8261                                 return -rte_errno;
8262                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8263                         break;
8264                 case RTE_FLOW_ACTION_TYPE_END:
8265                         actions_end = true;
8266                         if (mhdr_res->actions_num) {
8267                                 /* create modify action if needed. */
8268                                 if (flow_dv_modify_hdr_resource_register
8269                                         (dev, mhdr_res, dev_flow, error))
8270                                         return -rte_errno;
8271                                 dev_flow->dv.actions[modify_action_position] =
8272                                         handle->dvh.modify_hdr->verbs_action;
8273                         }
8274                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8275                                 flow->counter =
8276                                         flow_dv_translate_create_counter(dev,
8277                                                 dev_flow, count, age);
8278
8279                                 if (!flow->counter)
8280                                         return rte_flow_error_set
8281                                                 (error, rte_errno,
8282                                                 RTE_FLOW_ERROR_TYPE_ACTION,
8283                                                 NULL,
8284                                                 "cannot create counter"
8285                                                 " object.");
8286                                 dev_flow->dv.actions[actions_n++] =
8287                                           (flow_dv_counter_get_by_idx(dev,
8288                                           flow->counter, NULL))->action;
8289                         }
8290                         break;
8291                 default:
8292                         break;
8293                 }
8294                 if (mhdr_res->actions_num &&
8295                     modify_action_position == UINT32_MAX)
8296                         modify_action_position = actions_n++;
8297         }
8298         dev_flow->dv.actions_n = actions_n;
8299         dev_flow->act_flags = action_flags;
8300         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8301                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8302                 int item_type = items->type;
8303
8304                 switch (item_type) {
8305                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8306                         flow_dv_translate_item_port_id(dev, match_mask,
8307                                                        match_value, items);
8308                         last_item = MLX5_FLOW_ITEM_PORT_ID;
8309                         break;
8310                 case RTE_FLOW_ITEM_TYPE_ETH:
8311                         flow_dv_translate_item_eth(match_mask, match_value,
8312                                                    items, tunnel,
8313                                                    dev_flow->dv.group);
8314                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8315                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8316                                              MLX5_FLOW_LAYER_OUTER_L2;
8317                         break;
8318                 case RTE_FLOW_ITEM_TYPE_VLAN:
8319                         flow_dv_translate_item_vlan(dev_flow,
8320                                                     match_mask, match_value,
8321                                                     items, tunnel,
8322                                                     dev_flow->dv.group);
8323                         matcher.priority = MLX5_PRIORITY_MAP_L2;
8324                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8325                                               MLX5_FLOW_LAYER_INNER_VLAN) :
8326                                              (MLX5_FLOW_LAYER_OUTER_L2 |
8327                                               MLX5_FLOW_LAYER_OUTER_VLAN);
8328                         break;
8329                 case RTE_FLOW_ITEM_TYPE_IPV4:
8330                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8331                                                   &item_flags, &tunnel);
8332                         flow_dv_translate_item_ipv4(match_mask, match_value,
8333                                                     items, item_flags, tunnel,
8334                                                     dev_flow->dv.group);
8335                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8336                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8337                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8338                         if (items->mask != NULL &&
8339                             ((const struct rte_flow_item_ipv4 *)
8340                              items->mask)->hdr.next_proto_id) {
8341                                 next_protocol =
8342                                         ((const struct rte_flow_item_ipv4 *)
8343                                          (items->spec))->hdr.next_proto_id;
8344                                 next_protocol &=
8345                                         ((const struct rte_flow_item_ipv4 *)
8346                                          (items->mask))->hdr.next_proto_id;
8347                         } else {
8348                                 /* Reset for inner layer. */
8349                                 next_protocol = 0xff;
8350                         }
8351                         break;
8352                 case RTE_FLOW_ITEM_TYPE_IPV6:
8353                         mlx5_flow_tunnel_ip_check(items, next_protocol,
8354                                                   &item_flags, &tunnel);
8355                         flow_dv_translate_item_ipv6(match_mask, match_value,
8356                                                     items, item_flags, tunnel,
8357                                                     dev_flow->dv.group);
8358                         matcher.priority = MLX5_PRIORITY_MAP_L3;
8359                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8360                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8361                         if (items->mask != NULL &&
8362                             ((const struct rte_flow_item_ipv6 *)
8363                              items->mask)->hdr.proto) {
8364                                 next_protocol =
8365                                         ((const struct rte_flow_item_ipv6 *)
8366                                          items->spec)->hdr.proto;
8367                                 next_protocol &=
8368                                         ((const struct rte_flow_item_ipv6 *)
8369                                          items->mask)->hdr.proto;
8370                         } else {
8371                                 /* Reset for inner layer. */
8372                                 next_protocol = 0xff;
8373                         }
8374                         break;
8375                 case RTE_FLOW_ITEM_TYPE_TCP:
8376                         flow_dv_translate_item_tcp(match_mask, match_value,
8377                                                    items, tunnel);
8378                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8379                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8380                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
8381                         break;
8382                 case RTE_FLOW_ITEM_TYPE_UDP:
8383                         flow_dv_translate_item_udp(match_mask, match_value,
8384                                                    items, tunnel);
8385                         matcher.priority = MLX5_PRIORITY_MAP_L4;
8386                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8387                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
8388                         break;
8389                 case RTE_FLOW_ITEM_TYPE_GRE:
8390                         flow_dv_translate_item_gre(match_mask, match_value,
8391                                                    items, tunnel);
8392                         matcher.priority = rss_desc->level >= 2 ?
8393                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8394                         last_item = MLX5_FLOW_LAYER_GRE;
8395                         break;
8396                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8397                         flow_dv_translate_item_gre_key(match_mask,
8398                                                        match_value, items);
8399                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
8400                         break;
8401                 case RTE_FLOW_ITEM_TYPE_NVGRE:
8402                         flow_dv_translate_item_nvgre(match_mask, match_value,
8403                                                      items, tunnel);
8404                         matcher.priority = rss_desc->level >= 2 ?
8405                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8406                         last_item = MLX5_FLOW_LAYER_GRE;
8407                         break;
8408                 case RTE_FLOW_ITEM_TYPE_VXLAN:
8409                         flow_dv_translate_item_vxlan(match_mask, match_value,
8410                                                      items, tunnel);
8411                         matcher.priority = rss_desc->level >= 2 ?
8412                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8413                         last_item = MLX5_FLOW_LAYER_VXLAN;
8414                         break;
8415                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8416                         flow_dv_translate_item_vxlan_gpe(match_mask,
8417                                                          match_value, items,
8418                                                          tunnel);
8419                         matcher.priority = rss_desc->level >= 2 ?
8420                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8421                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8422                         break;
8423                 case RTE_FLOW_ITEM_TYPE_GENEVE:
8424                         flow_dv_translate_item_geneve(match_mask, match_value,
8425                                                       items, tunnel);
8426                         matcher.priority = rss_desc->level >= 2 ?
8427                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8428                         last_item = MLX5_FLOW_LAYER_GENEVE;
8429                         break;
8430                 case RTE_FLOW_ITEM_TYPE_MPLS:
8431                         flow_dv_translate_item_mpls(match_mask, match_value,
8432                                                     items, last_item, tunnel);
8433                         matcher.priority = rss_desc->level >= 2 ?
8434                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8435                         last_item = MLX5_FLOW_LAYER_MPLS;
8436                         break;
8437                 case RTE_FLOW_ITEM_TYPE_MARK:
8438                         flow_dv_translate_item_mark(dev, match_mask,
8439                                                     match_value, items);
8440                         last_item = MLX5_FLOW_ITEM_MARK;
8441                         break;
8442                 case RTE_FLOW_ITEM_TYPE_META:
8443                         flow_dv_translate_item_meta(dev, match_mask,
8444                                                     match_value, attr, items);
8445                         last_item = MLX5_FLOW_ITEM_METADATA;
8446                         break;
8447                 case RTE_FLOW_ITEM_TYPE_ICMP:
8448                         flow_dv_translate_item_icmp(match_mask, match_value,
8449                                                     items, tunnel);
8450                         last_item = MLX5_FLOW_LAYER_ICMP;
8451                         break;
8452                 case RTE_FLOW_ITEM_TYPE_ICMP6:
8453                         flow_dv_translate_item_icmp6(match_mask, match_value,
8454                                                       items, tunnel);
8455                         last_item = MLX5_FLOW_LAYER_ICMP6;
8456                         break;
8457                 case RTE_FLOW_ITEM_TYPE_TAG:
8458                         flow_dv_translate_item_tag(dev, match_mask,
8459                                                    match_value, items);
8460                         last_item = MLX5_FLOW_ITEM_TAG;
8461                         break;
8462                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8463                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
8464                                                         match_value, items);
8465                         last_item = MLX5_FLOW_ITEM_TAG;
8466                         break;
8467                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8468                         flow_dv_translate_item_tx_queue(dev, match_mask,
8469                                                         match_value,
8470                                                         items);
8471                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8472                         break;
8473                 case RTE_FLOW_ITEM_TYPE_GTP:
8474                         flow_dv_translate_item_gtp(match_mask, match_value,
8475                                                    items, tunnel);
8476                         matcher.priority = rss_desc->level >= 2 ?
8477                                     MLX5_PRIORITY_MAP_L2 : MLX5_PRIORITY_MAP_L4;
8478                         last_item = MLX5_FLOW_LAYER_GTP;
8479                         break;
8480                 default:
8481                         break;
8482                 }
8483                 item_flags |= last_item;
8484         }
8485         /*
8486          * When E-Switch mode is enabled, we have two cases where we need to
8487          * set the source port manually.
8488          * The first one, is in case of Nic steering rule, and the second is
8489          * E-Switch rule where no port_id item was found. In both cases
8490          * the source port is set according the current port in use.
8491          */
8492         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8493             (priv->representor || priv->master)) {
8494                 if (flow_dv_translate_item_port_id(dev, match_mask,
8495                                                    match_value, NULL))
8496                         return -rte_errno;
8497         }
8498 #ifdef RTE_LIBRTE_MLX5_DEBUG
8499         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8500                                               dev_flow->dv.value.buf));
8501 #endif
8502         /*
8503          * Layers may be already initialized from prefix flow if this dev_flow
8504          * is the suffix flow.
8505          */
8506         handle->layers |= item_flags;
8507         if (action_flags & MLX5_FLOW_ACTION_RSS)
8508                 flow_dv_hashfields_set(dev_flow, rss_desc);
8509         /* Register matcher. */
8510         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8511                                     matcher.mask.size);
8512         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8513                                                      matcher.priority);
8514         /* reserved field no needs to be set to 0 here. */
8515         tbl_key.domain = attr->transfer;
8516         tbl_key.direction = attr->egress;
8517         tbl_key.table_id = dev_flow->dv.group;
8518         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8519                 return -rte_errno;
8520         return 0;
8521 }
8522
8523 /**
8524  * Apply the flow to the NIC, lock free,
8525  * (mutex should be acquired by caller).
8526  *
8527  * @param[in] dev
8528  *   Pointer to the Ethernet device structure.
8529  * @param[in, out] flow
8530  *   Pointer to flow structure.
8531  * @param[out] error
8532  *   Pointer to error structure.
8533  *
8534  * @return
8535  *   0 on success, a negative errno value otherwise and rte_errno is set.
8536  */
8537 static int
8538 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8539                 struct rte_flow_error *error)
8540 {
8541         struct mlx5_flow_dv_workspace *dv;
8542         struct mlx5_flow_handle *dh;
8543         struct mlx5_flow_handle_dv *dv_h;
8544         struct mlx5_flow *dev_flow;
8545         struct mlx5_priv *priv = dev->data->dev_private;
8546         uint32_t handle_idx;
8547         int n;
8548         int err;
8549         int idx;
8550
8551         for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8552                 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8553                 dv = &dev_flow->dv;
8554                 dh = dev_flow->handle;
8555                 dv_h = &dh->dvh;
8556                 n = dv->actions_n;
8557                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8558                         if (dv->transfer) {
8559                                 dv->actions[n++] = priv->sh->esw_drop_action;
8560                         } else {
8561                                 struct mlx5_hrxq *drop_hrxq;
8562                                 drop_hrxq = mlx5_hrxq_drop_new(dev);
8563                                 if (!drop_hrxq) {
8564                                         rte_flow_error_set
8565                                                 (error, errno,
8566                                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8567                                                  NULL,
8568                                                  "cannot get drop hash queue");
8569                                         goto error;
8570                                 }
8571                                 /*
8572                                  * Drop queues will be released by the specify
8573                                  * mlx5_hrxq_drop_release() function. Assign
8574                                  * the special index to hrxq to mark the queue
8575                                  * has been allocated.
8576                                  */
8577                                 dh->rix_hrxq = UINT32_MAX;
8578                                 dv->actions[n++] = drop_hrxq->action;
8579                         }
8580                 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8581                         struct mlx5_hrxq *hrxq;
8582                         uint32_t hrxq_idx;
8583                         struct mlx5_flow_rss_desc *rss_desc =
8584                                 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8585                                 [!!priv->flow_nested_idx];
8586
8587                         MLX5_ASSERT(rss_desc->queue_num);
8588                         hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8589                                                  MLX5_RSS_HASH_KEY_LEN,
8590                                                  dev_flow->hash_fields,
8591                                                  rss_desc->queue,
8592                                                  rss_desc->queue_num);
8593                         if (!hrxq_idx) {
8594                                 hrxq_idx = mlx5_hrxq_new
8595                                                 (dev, rss_desc->key,
8596                                                 MLX5_RSS_HASH_KEY_LEN,
8597                                                 dev_flow->hash_fields,
8598                                                 rss_desc->queue,
8599                                                 rss_desc->queue_num,
8600                                                 !!(dh->layers &
8601                                                 MLX5_FLOW_LAYER_TUNNEL));
8602                         }
8603                         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8604                                               hrxq_idx);
8605                         if (!hrxq) {
8606                                 rte_flow_error_set
8607                                         (error, rte_errno,
8608                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8609                                          "cannot get hash queue");
8610                                 goto error;
8611                         }
8612                         dh->rix_hrxq = hrxq_idx;
8613                         dv->actions[n++] = hrxq->action;
8614                 }
8615                 dh->ib_flow =
8616                         mlx5_glue->dv_create_flow(dv_h->matcher->matcher_object,
8617                                                   (void *)&dv->value, n,
8618                                                   dv->actions);
8619                 if (!dh->ib_flow) {
8620                         rte_flow_error_set(error, errno,
8621                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8622                                            NULL,
8623                                            "hardware refuses to create flow");
8624                         goto error;
8625                 }
8626                 if (priv->vmwa_context &&
8627                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
8628                         /*
8629                          * The rule contains the VLAN pattern.
8630                          * For VF we are going to create VLAN
8631                          * interface to make hypervisor set correct
8632                          * e-Switch vport context.
8633                          */
8634                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8635                 }
8636         }
8637         return 0;
8638 error:
8639         err = rte_errno; /* Save rte_errno before cleanup. */
8640         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8641                        handle_idx, dh, next) {
8642                 /* hrxq is union, don't clear it if the flag is not set. */
8643                 if (dh->rix_hrxq) {
8644                         if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8645                                 mlx5_hrxq_drop_release(dev);
8646                                 dh->rix_hrxq = 0;
8647                         } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8648                                 mlx5_hrxq_release(dev, dh->rix_hrxq);
8649                                 dh->rix_hrxq = 0;
8650                         }
8651                 }
8652                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8653                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8654         }
8655         rte_errno = err; /* Restore rte_errno. */
8656         return -rte_errno;
8657 }
8658
8659 /**
8660  * Release the flow matcher.
8661  *
8662  * @param dev
8663  *   Pointer to Ethernet device.
8664  * @param handle
8665  *   Pointer to mlx5_flow_handle.
8666  *
8667  * @return
8668  *   1 while a reference on it exists, 0 when freed.
8669  */
8670 static int
8671 flow_dv_matcher_release(struct rte_eth_dev *dev,
8672                         struct mlx5_flow_handle *handle)
8673 {
8674         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8675
8676         MLX5_ASSERT(matcher->matcher_object);
8677         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8678                 dev->data->port_id, (void *)matcher,
8679                 rte_atomic32_read(&matcher->refcnt));
8680         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8681                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8682                            (matcher->matcher_object));
8683                 LIST_REMOVE(matcher, next);
8684                 /* table ref-- in release interface. */
8685                 flow_dv_tbl_resource_release(dev, matcher->tbl);
8686                 rte_free(matcher);
8687                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8688                         dev->data->port_id, (void *)matcher);
8689                 return 0;
8690         }
8691         return 1;
8692 }
8693
8694 /**
8695  * Release an encap/decap resource.
8696  *
8697  * @param dev
8698  *   Pointer to Ethernet device.
8699  * @param handle
8700  *   Pointer to mlx5_flow_handle.
8701  *
8702  * @return
8703  *   1 while a reference on it exists, 0 when freed.
8704  */
8705 static int
8706 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8707                                      struct mlx5_flow_handle *handle)
8708 {
8709         struct mlx5_priv *priv = dev->data->dev_private;
8710         uint32_t idx = handle->dvh.rix_encap_decap;
8711         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8712
8713         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8714                          idx);
8715         if (!cache_resource)
8716                 return 0;
8717         MLX5_ASSERT(cache_resource->verbs_action);
8718         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8719                 (void *)cache_resource,
8720                 rte_atomic32_read(&cache_resource->refcnt));
8721         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8722                 claim_zero(mlx5_glue->destroy_flow_action
8723                                 (cache_resource->verbs_action));
8724                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8725                              &priv->sh->encaps_decaps, idx,
8726                              cache_resource, next);
8727                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8728                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8729                         (void *)cache_resource);
8730                 return 0;
8731         }
8732         return 1;
8733 }
8734
8735 /**
8736  * Release an jump to table action resource.
8737  *
8738  * @param dev
8739  *   Pointer to Ethernet device.
8740  * @param handle
8741  *   Pointer to mlx5_flow_handle.
8742  *
8743  * @return
8744  *   1 while a reference on it exists, 0 when freed.
8745  */
8746 static int
8747 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8748                                   struct mlx5_flow_handle *handle)
8749 {
8750         struct mlx5_priv *priv = dev->data->dev_private;
8751         struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8752         struct mlx5_flow_tbl_data_entry *tbl_data;
8753
8754         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8755                              handle->rix_jump);
8756         if (!tbl_data)
8757                 return 0;
8758         cache_resource = &tbl_data->jump;
8759         MLX5_ASSERT(cache_resource->action);
8760         DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8761                 (void *)cache_resource,
8762                 rte_atomic32_read(&cache_resource->refcnt));
8763         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8764                 claim_zero(mlx5_glue->destroy_flow_action
8765                                 (cache_resource->action));
8766                 /* jump action memory free is inside the table release. */
8767                 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
8768                 DRV_LOG(DEBUG, "jump table resource %p: removed",
8769                         (void *)cache_resource);
8770                 return 0;
8771         }
8772         return 1;
8773 }
8774
8775 /**
8776  * Release a modify-header resource.
8777  *
8778  * @param handle
8779  *   Pointer to mlx5_flow_handle.
8780  *
8781  * @return
8782  *   1 while a reference on it exists, 0 when freed.
8783  */
8784 static int
8785 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
8786 {
8787         struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
8788                                                         handle->dvh.modify_hdr;
8789
8790         MLX5_ASSERT(cache_resource->verbs_action);
8791         DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
8792                 (void *)cache_resource,
8793                 rte_atomic32_read(&cache_resource->refcnt));
8794         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8795                 claim_zero(mlx5_glue->destroy_flow_action
8796                                 (cache_resource->verbs_action));
8797                 LIST_REMOVE(cache_resource, next);
8798                 rte_free(cache_resource);
8799                 DRV_LOG(DEBUG, "modify-header resource %p: removed",
8800                         (void *)cache_resource);
8801                 return 0;
8802         }
8803         return 1;
8804 }
8805
8806 /**
8807  * Release port ID action resource.
8808  *
8809  * @param dev
8810  *   Pointer to Ethernet device.
8811  * @param handle
8812  *   Pointer to mlx5_flow_handle.
8813  *
8814  * @return
8815  *   1 while a reference on it exists, 0 when freed.
8816  */
8817 static int
8818 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
8819                                         struct mlx5_flow_handle *handle)
8820 {
8821         struct mlx5_priv *priv = dev->data->dev_private;
8822         struct mlx5_flow_dv_port_id_action_resource *cache_resource;
8823         uint32_t idx = handle->rix_port_id_action;
8824
8825         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8826                                         idx);
8827         if (!cache_resource)
8828                 return 0;
8829         MLX5_ASSERT(cache_resource->action);
8830         DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
8831                 (void *)cache_resource,
8832                 rte_atomic32_read(&cache_resource->refcnt));
8833         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8834                 claim_zero(mlx5_glue->destroy_flow_action
8835                                 (cache_resource->action));
8836                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
8837                              &priv->sh->port_id_action_list, idx,
8838                              cache_resource, next);
8839                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
8840                 DRV_LOG(DEBUG, "port id action resource %p: removed",
8841                         (void *)cache_resource);
8842                 return 0;
8843         }
8844         return 1;
8845 }
8846
8847 /**
8848  * Release push vlan action resource.
8849  *
8850  * @param dev
8851  *   Pointer to Ethernet device.
8852  * @param handle
8853  *   Pointer to mlx5_flow_handle.
8854  *
8855  * @return
8856  *   1 while a reference on it exists, 0 when freed.
8857  */
8858 static int
8859 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
8860                                           struct mlx5_flow_handle *handle)
8861 {
8862         struct mlx5_priv *priv = dev->data->dev_private;
8863         uint32_t idx = handle->dvh.rix_push_vlan;
8864         struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
8865
8866         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8867                                         idx);
8868         if (!cache_resource)
8869                 return 0;
8870         MLX5_ASSERT(cache_resource->action);
8871         DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
8872                 (void *)cache_resource,
8873                 rte_atomic32_read(&cache_resource->refcnt));
8874         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8875                 claim_zero(mlx5_glue->destroy_flow_action
8876                                 (cache_resource->action));
8877                 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
8878                              &priv->sh->push_vlan_action_list, idx,
8879                              cache_resource, next);
8880                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
8881                 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
8882                         (void *)cache_resource);
8883                 return 0;
8884         }
8885         return 1;
8886 }
8887
8888 /**
8889  * Release the fate resource.
8890  *
8891  * @param dev
8892  *   Pointer to Ethernet device.
8893  * @param handle
8894  *   Pointer to mlx5_flow_handle.
8895  */
8896 static void
8897 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
8898                                struct mlx5_flow_handle *handle)
8899 {
8900         if (!handle->rix_fate)
8901                 return;
8902         if (handle->fate_action == MLX5_FLOW_FATE_DROP)
8903                 mlx5_hrxq_drop_release(dev);
8904         else if (handle->fate_action == MLX5_FLOW_FATE_QUEUE)
8905                 mlx5_hrxq_release(dev, handle->rix_hrxq);
8906         else if (handle->fate_action == MLX5_FLOW_FATE_JUMP)
8907                 flow_dv_jump_tbl_resource_release(dev, handle);
8908         else if (handle->fate_action == MLX5_FLOW_FATE_PORT_ID)
8909                 flow_dv_port_id_action_resource_release(dev, handle);
8910         else
8911                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
8912         handle->rix_fate = 0;
8913 }
8914
8915 /**
8916  * Remove the flow from the NIC but keeps it in memory.
8917  * Lock free, (mutex should be acquired by caller).
8918  *
8919  * @param[in] dev
8920  *   Pointer to Ethernet device.
8921  * @param[in, out] flow
8922  *   Pointer to flow structure.
8923  */
8924 static void
8925 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8926 {
8927         struct mlx5_flow_handle *dh;
8928         uint32_t handle_idx;
8929         struct mlx5_priv *priv = dev->data->dev_private;
8930
8931         if (!flow)
8932                 return;
8933         handle_idx = flow->dev_handles;
8934         while (handle_idx) {
8935                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
8936                                     handle_idx);
8937                 if (!dh)
8938                         return;
8939                 if (dh->ib_flow) {
8940                         claim_zero(mlx5_glue->dv_destroy_flow(dh->ib_flow));
8941                         dh->ib_flow = NULL;
8942                 }
8943                 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
8944                     dh->fate_action == MLX5_FLOW_FATE_QUEUE)
8945                         flow_dv_fate_resource_release(dev, dh);
8946                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8947                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8948                 handle_idx = dh->next.next;
8949         }
8950 }
8951
8952 /**
8953  * Remove the flow from the NIC and the memory.
8954  * Lock free, (mutex should be acquired by caller).
8955  *
8956  * @param[in] dev
8957  *   Pointer to the Ethernet device structure.
8958  * @param[in, out] flow
8959  *   Pointer to flow structure.
8960  */
8961 static void
8962 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8963 {
8964         struct mlx5_flow_handle *dev_handle;
8965         struct mlx5_priv *priv = dev->data->dev_private;
8966
8967         if (!flow)
8968                 return;
8969         __flow_dv_remove(dev, flow);
8970         if (flow->counter) {
8971                 flow_dv_counter_release(dev, flow->counter);
8972                 flow->counter = 0;
8973         }
8974         if (flow->meter) {
8975                 struct mlx5_flow_meter *fm;
8976
8977                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
8978                                     flow->meter);
8979                 if (fm)
8980                         mlx5_flow_meter_detach(fm);
8981                 flow->meter = 0;
8982         }
8983         while (flow->dev_handles) {
8984                 uint32_t tmp_idx = flow->dev_handles;
8985
8986                 dev_handle = mlx5_ipool_get(priv->sh->ipool
8987                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
8988                 if (!dev_handle)
8989                         return;
8990                 flow->dev_handles = dev_handle->next.next;
8991                 if (dev_handle->dvh.matcher)
8992                         flow_dv_matcher_release(dev, dev_handle);
8993                 if (dev_handle->dvh.rix_encap_decap)
8994                         flow_dv_encap_decap_resource_release(dev, dev_handle);
8995                 if (dev_handle->dvh.modify_hdr)
8996                         flow_dv_modify_hdr_resource_release(dev_handle);
8997                 if (dev_handle->dvh.rix_push_vlan)
8998                         flow_dv_push_vlan_action_resource_release(dev,
8999                                                                   dev_handle);
9000                 if (dev_handle->dvh.rix_tag)
9001                         flow_dv_tag_release(dev,
9002                                             dev_handle->dvh.rix_tag);
9003                 flow_dv_fate_resource_release(dev, dev_handle);
9004                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9005                            tmp_idx);
9006         }
9007 }
9008
9009 /**
9010  * Query a dv flow  rule for its statistics via devx.
9011  *
9012  * @param[in] dev
9013  *   Pointer to Ethernet device.
9014  * @param[in] flow
9015  *   Pointer to the sub flow.
9016  * @param[out] data
9017  *   data retrieved by the query.
9018  * @param[out] error
9019  *   Perform verbose error reporting if not NULL.
9020  *
9021  * @return
9022  *   0 on success, a negative errno value otherwise and rte_errno is set.
9023  */
9024 static int
9025 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9026                     void *data, struct rte_flow_error *error)
9027 {
9028         struct mlx5_priv *priv = dev->data->dev_private;
9029         struct rte_flow_query_count *qc = data;
9030
9031         if (!priv->config.devx)
9032                 return rte_flow_error_set(error, ENOTSUP,
9033                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9034                                           NULL,
9035                                           "counters are not supported");
9036         if (flow->counter) {
9037                 uint64_t pkts, bytes;
9038                 struct mlx5_flow_counter *cnt;
9039
9040                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9041                                                  NULL);
9042                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9043                                                &bytes);
9044
9045                 if (err)
9046                         return rte_flow_error_set(error, -err,
9047                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9048                                         NULL, "cannot read counters");
9049                 qc->hits_set = 1;
9050                 qc->bytes_set = 1;
9051                 qc->hits = pkts - cnt->hits;
9052                 qc->bytes = bytes - cnt->bytes;
9053                 if (qc->reset) {
9054                         cnt->hits = pkts;
9055                         cnt->bytes = bytes;
9056                 }
9057                 return 0;
9058         }
9059         return rte_flow_error_set(error, EINVAL,
9060                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9061                                   NULL,
9062                                   "counters are not available");
9063 }
9064
9065 /**
9066  * Query a flow.
9067  *
9068  * @see rte_flow_query()
9069  * @see rte_flow_ops
9070  */
9071 static int
9072 flow_dv_query(struct rte_eth_dev *dev,
9073               struct rte_flow *flow __rte_unused,
9074               const struct rte_flow_action *actions __rte_unused,
9075               void *data __rte_unused,
9076               struct rte_flow_error *error __rte_unused)
9077 {
9078         int ret = -EINVAL;
9079
9080         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9081                 switch (actions->type) {
9082                 case RTE_FLOW_ACTION_TYPE_VOID:
9083                         break;
9084                 case RTE_FLOW_ACTION_TYPE_COUNT:
9085                         ret = flow_dv_query_count(dev, flow, data, error);
9086                         break;
9087                 default:
9088                         return rte_flow_error_set(error, ENOTSUP,
9089                                                   RTE_FLOW_ERROR_TYPE_ACTION,
9090                                                   actions,
9091                                                   "action not supported");
9092                 }
9093         }
9094         return ret;
9095 }
9096
9097 /**
9098  * Destroy the meter table set.
9099  * Lock free, (mutex should be acquired by caller).
9100  *
9101  * @param[in] dev
9102  *   Pointer to Ethernet device.
9103  * @param[in] tbl
9104  *   Pointer to the meter table set.
9105  *
9106  * @return
9107  *   Always 0.
9108  */
9109 static int
9110 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9111                         struct mlx5_meter_domains_infos *tbl)
9112 {
9113         struct mlx5_priv *priv = dev->data->dev_private;
9114         struct mlx5_meter_domains_infos *mtd =
9115                                 (struct mlx5_meter_domains_infos *)tbl;
9116
9117         if (!mtd || !priv->config.dv_flow_en)
9118                 return 0;
9119         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9120                 claim_zero(mlx5_glue->dv_destroy_flow
9121                           (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9122         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9123                 claim_zero(mlx5_glue->dv_destroy_flow
9124                           (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9125         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9126                 claim_zero(mlx5_glue->dv_destroy_flow
9127                           (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9128         if (mtd->egress.color_matcher)
9129                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9130                           (mtd->egress.color_matcher));
9131         if (mtd->egress.any_matcher)
9132                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9133                           (mtd->egress.any_matcher));
9134         if (mtd->egress.tbl)
9135                 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9136         if (mtd->egress.sfx_tbl)
9137                 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9138         if (mtd->ingress.color_matcher)
9139                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9140                           (mtd->ingress.color_matcher));
9141         if (mtd->ingress.any_matcher)
9142                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9143                           (mtd->ingress.any_matcher));
9144         if (mtd->ingress.tbl)
9145                 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9146         if (mtd->ingress.sfx_tbl)
9147                 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9148         if (mtd->transfer.color_matcher)
9149                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9150                           (mtd->transfer.color_matcher));
9151         if (mtd->transfer.any_matcher)
9152                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
9153                           (mtd->transfer.any_matcher));
9154         if (mtd->transfer.tbl)
9155                 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9156         if (mtd->transfer.sfx_tbl)
9157                 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9158         if (mtd->drop_actn)
9159                 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
9160         rte_free(mtd);
9161         return 0;
9162 }
9163
9164 /* Number of meter flow actions, count and jump or count and drop. */
9165 #define METER_ACTIONS 2
9166
9167 /**
9168  * Create specify domain meter table and suffix table.
9169  *
9170  * @param[in] dev
9171  *   Pointer to Ethernet device.
9172  * @param[in,out] mtb
9173  *   Pointer to DV meter table set.
9174  * @param[in] egress
9175  *   Table attribute.
9176  * @param[in] transfer
9177  *   Table attribute.
9178  * @param[in] color_reg_c_idx
9179  *   Reg C index for color match.
9180  *
9181  * @return
9182  *   0 on success, -1 otherwise and rte_errno is set.
9183  */
9184 static int
9185 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9186                            struct mlx5_meter_domains_infos *mtb,
9187                            uint8_t egress, uint8_t transfer,
9188                            uint32_t color_reg_c_idx)
9189 {
9190         struct mlx5_priv *priv = dev->data->dev_private;
9191         struct mlx5_dev_ctx_shared *sh = priv->sh;
9192         struct mlx5_flow_dv_match_params mask = {
9193                 .size = sizeof(mask.buf),
9194         };
9195         struct mlx5_flow_dv_match_params value = {
9196                 .size = sizeof(value.buf),
9197         };
9198         struct mlx5dv_flow_matcher_attr dv_attr = {
9199                 .type = IBV_FLOW_ATTR_NORMAL,
9200                 .priority = 0,
9201                 .match_criteria_enable = 0,
9202                 .match_mask = (void *)&mask,
9203         };
9204         void *actions[METER_ACTIONS];
9205         struct mlx5_meter_domain_info *dtb;
9206         struct rte_flow_error error;
9207         int i = 0;
9208
9209         if (transfer)
9210                 dtb = &mtb->transfer;
9211         else if (egress)
9212                 dtb = &mtb->egress;
9213         else
9214                 dtb = &mtb->ingress;
9215         /* Create the meter table with METER level. */
9216         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9217                                             egress, transfer, &error);
9218         if (!dtb->tbl) {
9219                 DRV_LOG(ERR, "Failed to create meter policer table.");
9220                 return -1;
9221         }
9222         /* Create the meter suffix table with SUFFIX level. */
9223         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9224                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9225                                             egress, transfer, &error);
9226         if (!dtb->sfx_tbl) {
9227                 DRV_LOG(ERR, "Failed to create meter suffix table.");
9228                 return -1;
9229         }
9230         /* Create matchers, Any and Color. */
9231         dv_attr.priority = 3;
9232         dv_attr.match_criteria_enable = 0;
9233         dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9234                                                              &dv_attr,
9235                                                              dtb->tbl->obj);
9236         if (!dtb->any_matcher) {
9237                 DRV_LOG(ERR, "Failed to create meter"
9238                              " policer default matcher.");
9239                 goto error_exit;
9240         }
9241         dv_attr.priority = 0;
9242         dv_attr.match_criteria_enable =
9243                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9244         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9245                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9246         dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
9247                                                                &dv_attr,
9248                                                                dtb->tbl->obj);
9249         if (!dtb->color_matcher) {
9250                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9251                 goto error_exit;
9252         }
9253         if (mtb->count_actns[RTE_MTR_DROPPED])
9254                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9255         actions[i++] = mtb->drop_actn;
9256         /* Default rule: lowest priority, match any, actions: drop. */
9257         dtb->policer_rules[RTE_MTR_DROPPED] =
9258                         mlx5_glue->dv_create_flow(dtb->any_matcher,
9259                                                  (void *)&value, i, actions);
9260         if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
9261                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9262                 goto error_exit;
9263         }
9264         return 0;
9265 error_exit:
9266         return -1;
9267 }
9268
9269 /**
9270  * Create the needed meter and suffix tables.
9271  * Lock free, (mutex should be acquired by caller).
9272  *
9273  * @param[in] dev
9274  *   Pointer to Ethernet device.
9275  * @param[in] fm
9276  *   Pointer to the flow meter.
9277  *
9278  * @return
9279  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
9280  */
9281 static struct mlx5_meter_domains_infos *
9282 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9283                        const struct mlx5_flow_meter *fm)
9284 {
9285         struct mlx5_priv *priv = dev->data->dev_private;
9286         struct mlx5_meter_domains_infos *mtb;
9287         int ret;
9288         int i;
9289
9290         if (!priv->mtr_en) {
9291                 rte_errno = ENOTSUP;
9292                 return NULL;
9293         }
9294         mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
9295         if (!mtb) {
9296                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9297                 return NULL;
9298         }
9299         /* Create meter count actions */
9300         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9301                 struct mlx5_flow_counter *cnt;
9302                 if (!fm->policer_stats.cnt[i])
9303                         continue;
9304                 cnt = flow_dv_counter_get_by_idx(dev,
9305                       fm->policer_stats.cnt[i], NULL);
9306                 mtb->count_actns[i] = cnt->action;
9307         }
9308         /* Create drop action. */
9309         mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
9310         if (!mtb->drop_actn) {
9311                 DRV_LOG(ERR, "Failed to create drop action.");
9312                 goto error_exit;
9313         }
9314         /* Egress meter table. */
9315         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9316         if (ret) {
9317                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9318                 goto error_exit;
9319         }
9320         /* Ingress meter table. */
9321         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9322         if (ret) {
9323                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9324                 goto error_exit;
9325         }
9326         /* FDB meter table. */
9327         if (priv->config.dv_esw_en) {
9328                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9329                                                  priv->mtr_color_reg);
9330                 if (ret) {
9331                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9332                         goto error_exit;
9333                 }
9334         }
9335         return mtb;
9336 error_exit:
9337         flow_dv_destroy_mtr_tbl(dev, mtb);
9338         return NULL;
9339 }
9340
9341 /**
9342  * Destroy domain policer rule.
9343  *
9344  * @param[in] dt
9345  *   Pointer to domain table.
9346  */
9347 static void
9348 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9349 {
9350         int i;
9351
9352         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9353                 if (dt->policer_rules[i]) {
9354                         claim_zero(mlx5_glue->dv_destroy_flow
9355                                   (dt->policer_rules[i]));
9356                         dt->policer_rules[i] = NULL;
9357                 }
9358         }
9359         if (dt->jump_actn) {
9360                 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
9361                 dt->jump_actn = NULL;
9362         }
9363 }
9364
9365 /**
9366  * Destroy policer rules.
9367  *
9368  * @param[in] dev
9369  *   Pointer to Ethernet device.
9370  * @param[in] fm
9371  *   Pointer to flow meter structure.
9372  * @param[in] attr
9373  *   Pointer to flow attributes.
9374  *
9375  * @return
9376  *   Always 0.
9377  */
9378 static int
9379 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9380                               const struct mlx5_flow_meter *fm,
9381                               const struct rte_flow_attr *attr)
9382 {
9383         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9384
9385         if (!mtb)
9386                 return 0;
9387         if (attr->egress)
9388                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9389         if (attr->ingress)
9390                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9391         if (attr->transfer)
9392                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9393         return 0;
9394 }
9395
9396 /**
9397  * Create specify domain meter policer rule.
9398  *
9399  * @param[in] fm
9400  *   Pointer to flow meter structure.
9401  * @param[in] mtb
9402  *   Pointer to DV meter table set.
9403  * @param[in] mtr_reg_c
9404  *   Color match REG_C.
9405  *
9406  * @return
9407  *   0 on success, -1 otherwise.
9408  */
9409 static int
9410 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9411                                     struct mlx5_meter_domain_info *dtb,
9412                                     uint8_t mtr_reg_c)
9413 {
9414         struct mlx5_flow_dv_match_params matcher = {
9415                 .size = sizeof(matcher.buf),
9416         };
9417         struct mlx5_flow_dv_match_params value = {
9418                 .size = sizeof(value.buf),
9419         };
9420         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9421         void *actions[METER_ACTIONS];
9422         int i;
9423
9424         /* Create jump action. */
9425         if (!dtb->jump_actn)
9426                 dtb->jump_actn =
9427                         mlx5_glue->dr_create_flow_action_dest_flow_tbl
9428                                                         (dtb->sfx_tbl->obj);
9429         if (!dtb->jump_actn) {
9430                 DRV_LOG(ERR, "Failed to create policer jump action.");
9431                 goto error;
9432         }
9433         for (i = 0; i < RTE_MTR_DROPPED; i++) {
9434                 int j = 0;
9435
9436                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9437                                        rte_col_2_mlx5_col(i), UINT8_MAX);
9438                 if (mtb->count_actns[i])
9439                         actions[j++] = mtb->count_actns[i];
9440                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9441                         actions[j++] = mtb->drop_actn;
9442                 else
9443                         actions[j++] = dtb->jump_actn;
9444                 dtb->policer_rules[i] =
9445                         mlx5_glue->dv_create_flow(dtb->color_matcher,
9446                                                  (void *)&value,
9447                                                   j, actions);
9448                 if (!dtb->policer_rules[i]) {
9449                         DRV_LOG(ERR, "Failed to create policer rule.");
9450                         goto error;
9451                 }
9452         }
9453         return 0;
9454 error:
9455         rte_errno = errno;
9456         return -1;
9457 }
9458
9459 /**
9460  * Create policer rules.
9461  *
9462  * @param[in] dev
9463  *   Pointer to Ethernet device.
9464  * @param[in] fm
9465  *   Pointer to flow meter structure.
9466  * @param[in] attr
9467  *   Pointer to flow attributes.
9468  *
9469  * @return
9470  *   0 on success, -1 otherwise.
9471  */
9472 static int
9473 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9474                              struct mlx5_flow_meter *fm,
9475                              const struct rte_flow_attr *attr)
9476 {
9477         struct mlx5_priv *priv = dev->data->dev_private;
9478         struct mlx5_meter_domains_infos *mtb = fm->mfts;
9479         int ret;
9480
9481         if (attr->egress) {
9482                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9483                                                 priv->mtr_color_reg);
9484                 if (ret) {
9485                         DRV_LOG(ERR, "Failed to create egress policer.");
9486                         goto error;
9487                 }
9488         }
9489         if (attr->ingress) {
9490                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9491                                                 priv->mtr_color_reg);
9492                 if (ret) {
9493                         DRV_LOG(ERR, "Failed to create ingress policer.");
9494                         goto error;
9495                 }
9496         }
9497         if (attr->transfer) {
9498                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9499                                                 priv->mtr_color_reg);
9500                 if (ret) {
9501                         DRV_LOG(ERR, "Failed to create transfer policer.");
9502                         goto error;
9503                 }
9504         }
9505         return 0;
9506 error:
9507         flow_dv_destroy_policer_rules(dev, fm, attr);
9508         return -1;
9509 }
9510
9511 /**
9512  * Query a devx counter.
9513  *
9514  * @param[in] dev
9515  *   Pointer to the Ethernet device structure.
9516  * @param[in] cnt
9517  *   Index to the flow counter.
9518  * @param[in] clear
9519  *   Set to clear the counter statistics.
9520  * @param[out] pkts
9521  *   The statistics value of packets.
9522  * @param[out] bytes
9523  *   The statistics value of bytes.
9524  *
9525  * @return
9526  *   0 on success, otherwise return -1.
9527  */
9528 static int
9529 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9530                       uint64_t *pkts, uint64_t *bytes)
9531 {
9532         struct mlx5_priv *priv = dev->data->dev_private;
9533         struct mlx5_flow_counter *cnt;
9534         uint64_t inn_pkts, inn_bytes;
9535         int ret;
9536
9537         if (!priv->config.devx)
9538                 return -1;
9539
9540         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9541         if (ret)
9542                 return -1;
9543         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9544         *pkts = inn_pkts - cnt->hits;
9545         *bytes = inn_bytes - cnt->bytes;
9546         if (clear) {
9547                 cnt->hits = inn_pkts;
9548                 cnt->bytes = inn_bytes;
9549         }
9550         return 0;
9551 }
9552
9553 /**
9554  * Get aged-out flows.
9555  *
9556  * @param[in] dev
9557  *   Pointer to the Ethernet device structure.
9558  * @param[in] context
9559  *   The address of an array of pointers to the aged-out flows contexts.
9560  * @param[in] nb_contexts
9561  *   The length of context array pointers.
9562  * @param[out] error
9563  *   Perform verbose error reporting if not NULL. Initialized in case of
9564  *   error only.
9565  *
9566  * @return
9567  *   how many contexts get in success, otherwise negative errno value.
9568  *   if nb_contexts is 0, return the amount of all aged contexts.
9569  *   if nb_contexts is not 0 , return the amount of aged flows reported
9570  *   in the context array.
9571  * @note: only stub for now
9572  */
9573 static int
9574 flow_get_aged_flows(struct rte_eth_dev *dev,
9575                     void **context,
9576                     uint32_t nb_contexts,
9577                     struct rte_flow_error *error)
9578 {
9579         struct mlx5_priv *priv = dev->data->dev_private;
9580         struct mlx5_age_info *age_info;
9581         struct mlx5_age_param *age_param;
9582         struct mlx5_flow_counter *counter;
9583         int nb_flows = 0;
9584
9585         if (nb_contexts && !context)
9586                 return rte_flow_error_set(error, EINVAL,
9587                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9588                                           NULL,
9589                                           "Should assign at least one flow or"
9590                                           " context to get if nb_contexts != 0");
9591         age_info = GET_PORT_AGE_INFO(priv);
9592         rte_spinlock_lock(&age_info->aged_sl);
9593         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9594                 nb_flows++;
9595                 if (nb_contexts) {
9596                         age_param = MLX5_CNT_TO_AGE(counter);
9597                         context[nb_flows - 1] = age_param->context;
9598                         if (!(--nb_contexts))
9599                                 break;
9600                 }
9601         }
9602         rte_spinlock_unlock(&age_info->aged_sl);
9603         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9604         return nb_flows;
9605 }
9606
9607 /*
9608  * Mutex-protected thunk to lock-free  __flow_dv_translate().
9609  */
9610 static int
9611 flow_dv_translate(struct rte_eth_dev *dev,
9612                   struct mlx5_flow *dev_flow,
9613                   const struct rte_flow_attr *attr,
9614                   const struct rte_flow_item items[],
9615                   const struct rte_flow_action actions[],
9616                   struct rte_flow_error *error)
9617 {
9618         int ret;
9619
9620         flow_dv_shared_lock(dev);
9621         ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9622         flow_dv_shared_unlock(dev);
9623         return ret;
9624 }
9625
9626 /*
9627  * Mutex-protected thunk to lock-free  __flow_dv_apply().
9628  */
9629 static int
9630 flow_dv_apply(struct rte_eth_dev *dev,
9631               struct rte_flow *flow,
9632               struct rte_flow_error *error)
9633 {
9634         int ret;
9635
9636         flow_dv_shared_lock(dev);
9637         ret = __flow_dv_apply(dev, flow, error);
9638         flow_dv_shared_unlock(dev);
9639         return ret;
9640 }
9641
9642 /*
9643  * Mutex-protected thunk to lock-free __flow_dv_remove().
9644  */
9645 static void
9646 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9647 {
9648         flow_dv_shared_lock(dev);
9649         __flow_dv_remove(dev, flow);
9650         flow_dv_shared_unlock(dev);
9651 }
9652
9653 /*
9654  * Mutex-protected thunk to lock-free __flow_dv_destroy().
9655  */
9656 static void
9657 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9658 {
9659         flow_dv_shared_lock(dev);
9660         __flow_dv_destroy(dev, flow);
9661         flow_dv_shared_unlock(dev);
9662 }
9663
9664 /*
9665  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9666  */
9667 static uint32_t
9668 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9669 {
9670         uint32_t cnt;
9671
9672         flow_dv_shared_lock(dev);
9673         cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9674         flow_dv_shared_unlock(dev);
9675         return cnt;
9676 }
9677
9678 /*
9679  * Mutex-protected thunk to lock-free flow_dv_counter_release().
9680  */
9681 static void
9682 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9683 {
9684         flow_dv_shared_lock(dev);
9685         flow_dv_counter_release(dev, cnt);
9686         flow_dv_shared_unlock(dev);
9687 }
9688
9689 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9690         .validate = flow_dv_validate,
9691         .prepare = flow_dv_prepare,
9692         .translate = flow_dv_translate,
9693         .apply = flow_dv_apply,
9694         .remove = flow_dv_remove,
9695         .destroy = flow_dv_destroy,
9696         .query = flow_dv_query,
9697         .create_mtr_tbls = flow_dv_create_mtr_tbl,
9698         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9699         .create_policer_rules = flow_dv_create_policer_rules,
9700         .destroy_policer_rules = flow_dv_destroy_policer_rules,
9701         .counter_alloc = flow_dv_counter_allocate,
9702         .counter_free = flow_dv_counter_free,
9703         .counter_query = flow_dv_counter_query,
9704         .get_aged_flows = flow_get_aged_flows,
9705 };
9706
9707 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */