1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
18 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_common.h>
22 #include <rte_ether.h>
23 #include <rte_ethdev_driver.h>
25 #include <rte_flow_driver.h>
26 #include <rte_malloc.h>
29 #include <rte_vxlan.h>
33 #include "mlx5_defs.h"
34 #include "mlx5_glue.h"
35 #include "mlx5_flow.h"
37 #include "mlx5_rxtx.h"
39 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
41 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
42 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
45 #ifndef HAVE_MLX5DV_DR_ESWITCH
46 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
47 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
51 #ifndef HAVE_MLX5DV_DR
52 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
55 #define MLX5_ENCAPSULATION_DECISION_SIZE (sizeof(struct rte_flow_item_eth) + \
56 sizeof(struct rte_flow_item_ipv4))
57 /* VLAN header definitions */
58 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
59 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
60 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
61 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
62 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
77 * Initialize flow attributes structure according to flow items' types.
79 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
80 * mode. For tunnel mode, the items to be modified are the outermost ones.
83 * Pointer to item specification.
85 * Pointer to flow attributes structure.
88 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr)
90 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
92 case RTE_FLOW_ITEM_TYPE_IPV4:
96 case RTE_FLOW_ITEM_TYPE_IPV6:
100 case RTE_FLOW_ITEM_TYPE_UDP:
104 case RTE_FLOW_ITEM_TYPE_TCP:
116 * Convert rte_mtr_color to mlx5 color.
125 rte_col_2_mlx5_col(enum rte_color rcol)
128 case RTE_COLOR_GREEN:
129 return MLX5_FLOW_COLOR_GREEN;
130 case RTE_COLOR_YELLOW:
131 return MLX5_FLOW_COLOR_YELLOW;
133 return MLX5_FLOW_COLOR_RED;
137 return MLX5_FLOW_COLOR_UNDEFINED;
140 struct field_modify_info {
141 uint32_t size; /* Size of field in protocol header, in bytes. */
142 uint32_t offset; /* Offset of field in protocol header, in bytes. */
143 enum mlx5_modification_field id;
146 struct field_modify_info modify_eth[] = {
147 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
148 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
149 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
150 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
154 struct field_modify_info modify_vlan_out_first_vid[] = {
155 /* Size in bits !!! */
156 {12, 0, MLX5_MODI_OUT_FIRST_VID},
160 struct field_modify_info modify_ipv4[] = {
161 {1, 1, MLX5_MODI_OUT_IP_DSCP},
162 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
163 {4, 12, MLX5_MODI_OUT_SIPV4},
164 {4, 16, MLX5_MODI_OUT_DIPV4},
168 struct field_modify_info modify_ipv6[] = {
169 {1, 0, MLX5_MODI_OUT_IP_DSCP},
170 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
171 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
172 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
173 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
174 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
175 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
176 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
177 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
178 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
182 struct field_modify_info modify_udp[] = {
183 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
184 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
188 struct field_modify_info modify_tcp[] = {
189 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
190 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
191 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
192 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
197 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
198 uint8_t next_protocol, uint64_t *item_flags,
201 assert(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
202 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
203 if (next_protocol == IPPROTO_IPIP) {
204 *item_flags |= MLX5_FLOW_LAYER_IPIP;
207 if (next_protocol == IPPROTO_IPV6) {
208 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
214 * Acquire the synchronizing object to protect multithreaded access
215 * to shared dv context. Lock occurs only if context is actually
216 * shared, i.e. we have multiport IB device and representors are
220 * Pointer to the rte_eth_dev structure.
223 flow_dv_shared_lock(struct rte_eth_dev *dev)
225 struct mlx5_priv *priv = dev->data->dev_private;
226 struct mlx5_ibv_shared *sh = priv->sh;
228 if (sh->dv_refcnt > 1) {
231 ret = pthread_mutex_lock(&sh->dv_mutex);
238 flow_dv_shared_unlock(struct rte_eth_dev *dev)
240 struct mlx5_priv *priv = dev->data->dev_private;
241 struct mlx5_ibv_shared *sh = priv->sh;
243 if (sh->dv_refcnt > 1) {
246 ret = pthread_mutex_unlock(&sh->dv_mutex);
252 /* Update VLAN's VID/PCP based on input rte_flow_action.
255 * Pointer to struct rte_flow_action.
257 * Pointer to struct rte_vlan_hdr.
260 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
261 struct rte_vlan_hdr *vlan)
264 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
266 ((const struct rte_flow_action_of_set_vlan_pcp *)
267 action->conf)->vlan_pcp;
268 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
269 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
270 vlan->vlan_tci |= vlan_tci;
271 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
272 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
273 vlan->vlan_tci |= rte_be_to_cpu_16
274 (((const struct rte_flow_action_of_set_vlan_vid *)
275 action->conf)->vlan_vid);
280 * Fetch 1, 2, 3 or 4 byte field from the byte array
281 * and return as unsigned integer in host-endian format.
284 * Pointer to data array.
286 * Size of field to extract.
289 * converted field in host endian format.
291 static inline uint32_t
292 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
301 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
304 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
305 ret = (ret << 8) | *(data + sizeof(uint16_t));
308 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
319 * Convert modify-header action to DV specification.
321 * Data length of each action is determined by provided field description
322 * and the item mask. Data bit offset and width of each action is determined
323 * by provided item mask.
326 * Pointer to item specification.
328 * Pointer to field modification information.
329 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
330 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
331 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
333 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
334 * Negative offset value sets the same offset as source offset.
335 * size field is ignored, value is taken from source field.
336 * @param[in,out] resource
337 * Pointer to the modify-header resource.
339 * Type of modification.
341 * Pointer to the error structure.
344 * 0 on success, a negative errno value otherwise and rte_errno is set.
347 flow_dv_convert_modify_action(struct rte_flow_item *item,
348 struct field_modify_info *field,
349 struct field_modify_info *dcopy,
350 struct mlx5_flow_dv_modify_hdr_resource *resource,
351 uint32_t type, struct rte_flow_error *error)
353 uint32_t i = resource->actions_num;
354 struct mlx5_modification_cmd *actions = resource->actions;
357 * The item and mask are provided in big-endian format.
358 * The fields should be presented as in big-endian format either.
359 * Mask must be always present, it defines the actual field width.
369 if (i >= MLX5_MAX_MODIFY_NUM)
370 return rte_flow_error_set(error, EINVAL,
371 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
372 "too many items to modify");
373 /* Fetch variable byte size mask from the array. */
374 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
375 field->offset, field->size);
380 /* Deduce actual data width in bits from mask value. */
381 off_b = rte_bsf32(mask);
382 size_b = sizeof(uint32_t) * CHAR_BIT -
383 off_b - __builtin_clz(mask);
385 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
386 actions[i].action_type = type;
387 actions[i].field = field->id;
388 actions[i].offset = off_b;
389 actions[i].length = size_b;
390 /* Convert entire record to expected big-endian format. */
391 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
392 if (type == MLX5_MODIFICATION_TYPE_COPY) {
394 actions[i].dst_field = dcopy->id;
395 actions[i].dst_offset =
396 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
397 /* Convert entire record to big-endian format. */
398 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
401 data = flow_dv_fetch_field((const uint8_t *)item->spec +
402 field->offset, field->size);
403 /* Shift out the trailing masked bits from data. */
404 data = (data & mask) >> off_b;
405 actions[i].data1 = rte_cpu_to_be_32(data);
409 } while (field->size);
410 if (resource->actions_num == i)
411 return rte_flow_error_set(error, EINVAL,
412 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
413 "invalid modification flow item");
414 resource->actions_num = i;
419 * Convert modify-header set IPv4 address action to DV specification.
421 * @param[in,out] resource
422 * Pointer to the modify-header resource.
424 * Pointer to action specification.
426 * Pointer to the error structure.
429 * 0 on success, a negative errno value otherwise and rte_errno is set.
432 flow_dv_convert_action_modify_ipv4
433 (struct mlx5_flow_dv_modify_hdr_resource *resource,
434 const struct rte_flow_action *action,
435 struct rte_flow_error *error)
437 const struct rte_flow_action_set_ipv4 *conf =
438 (const struct rte_flow_action_set_ipv4 *)(action->conf);
439 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
440 struct rte_flow_item_ipv4 ipv4;
441 struct rte_flow_item_ipv4 ipv4_mask;
443 memset(&ipv4, 0, sizeof(ipv4));
444 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
445 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
446 ipv4.hdr.src_addr = conf->ipv4_addr;
447 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
449 ipv4.hdr.dst_addr = conf->ipv4_addr;
450 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
453 item.mask = &ipv4_mask;
454 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
455 MLX5_MODIFICATION_TYPE_SET, error);
459 * Convert modify-header set IPv6 address action to DV specification.
461 * @param[in,out] resource
462 * Pointer to the modify-header resource.
464 * Pointer to action specification.
466 * Pointer to the error structure.
469 * 0 on success, a negative errno value otherwise and rte_errno is set.
472 flow_dv_convert_action_modify_ipv6
473 (struct mlx5_flow_dv_modify_hdr_resource *resource,
474 const struct rte_flow_action *action,
475 struct rte_flow_error *error)
477 const struct rte_flow_action_set_ipv6 *conf =
478 (const struct rte_flow_action_set_ipv6 *)(action->conf);
479 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
480 struct rte_flow_item_ipv6 ipv6;
481 struct rte_flow_item_ipv6 ipv6_mask;
483 memset(&ipv6, 0, sizeof(ipv6));
484 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
485 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
486 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
487 sizeof(ipv6.hdr.src_addr));
488 memcpy(&ipv6_mask.hdr.src_addr,
489 &rte_flow_item_ipv6_mask.hdr.src_addr,
490 sizeof(ipv6.hdr.src_addr));
492 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
493 sizeof(ipv6.hdr.dst_addr));
494 memcpy(&ipv6_mask.hdr.dst_addr,
495 &rte_flow_item_ipv6_mask.hdr.dst_addr,
496 sizeof(ipv6.hdr.dst_addr));
499 item.mask = &ipv6_mask;
500 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
501 MLX5_MODIFICATION_TYPE_SET, error);
505 * Convert modify-header set MAC address action to DV specification.
507 * @param[in,out] resource
508 * Pointer to the modify-header resource.
510 * Pointer to action specification.
512 * Pointer to the error structure.
515 * 0 on success, a negative errno value otherwise and rte_errno is set.
518 flow_dv_convert_action_modify_mac
519 (struct mlx5_flow_dv_modify_hdr_resource *resource,
520 const struct rte_flow_action *action,
521 struct rte_flow_error *error)
523 const struct rte_flow_action_set_mac *conf =
524 (const struct rte_flow_action_set_mac *)(action->conf);
525 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
526 struct rte_flow_item_eth eth;
527 struct rte_flow_item_eth eth_mask;
529 memset(ð, 0, sizeof(eth));
530 memset(ð_mask, 0, sizeof(eth_mask));
531 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
532 memcpy(ð.src.addr_bytes, &conf->mac_addr,
533 sizeof(eth.src.addr_bytes));
534 memcpy(ð_mask.src.addr_bytes,
535 &rte_flow_item_eth_mask.src.addr_bytes,
536 sizeof(eth_mask.src.addr_bytes));
538 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
539 sizeof(eth.dst.addr_bytes));
540 memcpy(ð_mask.dst.addr_bytes,
541 &rte_flow_item_eth_mask.dst.addr_bytes,
542 sizeof(eth_mask.dst.addr_bytes));
545 item.mask = ð_mask;
546 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
547 MLX5_MODIFICATION_TYPE_SET, error);
551 * Convert modify-header set VLAN VID action to DV specification.
553 * @param[in,out] resource
554 * Pointer to the modify-header resource.
556 * Pointer to action specification.
558 * Pointer to the error structure.
561 * 0 on success, a negative errno value otherwise and rte_errno is set.
564 flow_dv_convert_action_modify_vlan_vid
565 (struct mlx5_flow_dv_modify_hdr_resource *resource,
566 const struct rte_flow_action *action,
567 struct rte_flow_error *error)
569 const struct rte_flow_action_of_set_vlan_vid *conf =
570 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
571 int i = resource->actions_num;
572 struct mlx5_modification_cmd *actions = &resource->actions[i];
573 struct field_modify_info *field = modify_vlan_out_first_vid;
575 if (i >= MLX5_MAX_MODIFY_NUM)
576 return rte_flow_error_set(error, EINVAL,
577 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
578 "too many items to modify");
579 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
580 actions[i].field = field->id;
581 actions[i].length = field->size;
582 actions[i].offset = field->offset;
583 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
584 actions[i].data1 = conf->vlan_vid;
585 actions[i].data1 = actions[i].data1 << 16;
586 resource->actions_num = ++i;
591 * Convert modify-header set TP action to DV specification.
593 * @param[in,out] resource
594 * Pointer to the modify-header resource.
596 * Pointer to action specification.
598 * Pointer to rte_flow_item objects list.
600 * Pointer to flow attributes structure.
602 * Pointer to the error structure.
605 * 0 on success, a negative errno value otherwise and rte_errno is set.
608 flow_dv_convert_action_modify_tp
609 (struct mlx5_flow_dv_modify_hdr_resource *resource,
610 const struct rte_flow_action *action,
611 const struct rte_flow_item *items,
612 union flow_dv_attr *attr,
613 struct rte_flow_error *error)
615 const struct rte_flow_action_set_tp *conf =
616 (const struct rte_flow_action_set_tp *)(action->conf);
617 struct rte_flow_item item;
618 struct rte_flow_item_udp udp;
619 struct rte_flow_item_udp udp_mask;
620 struct rte_flow_item_tcp tcp;
621 struct rte_flow_item_tcp tcp_mask;
622 struct field_modify_info *field;
625 flow_dv_attr_init(items, attr);
627 memset(&udp, 0, sizeof(udp));
628 memset(&udp_mask, 0, sizeof(udp_mask));
629 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
630 udp.hdr.src_port = conf->port;
631 udp_mask.hdr.src_port =
632 rte_flow_item_udp_mask.hdr.src_port;
634 udp.hdr.dst_port = conf->port;
635 udp_mask.hdr.dst_port =
636 rte_flow_item_udp_mask.hdr.dst_port;
638 item.type = RTE_FLOW_ITEM_TYPE_UDP;
640 item.mask = &udp_mask;
644 memset(&tcp, 0, sizeof(tcp));
645 memset(&tcp_mask, 0, sizeof(tcp_mask));
646 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
647 tcp.hdr.src_port = conf->port;
648 tcp_mask.hdr.src_port =
649 rte_flow_item_tcp_mask.hdr.src_port;
651 tcp.hdr.dst_port = conf->port;
652 tcp_mask.hdr.dst_port =
653 rte_flow_item_tcp_mask.hdr.dst_port;
655 item.type = RTE_FLOW_ITEM_TYPE_TCP;
657 item.mask = &tcp_mask;
660 return flow_dv_convert_modify_action(&item, field, NULL, resource,
661 MLX5_MODIFICATION_TYPE_SET, error);
665 * Convert modify-header set TTL action to DV specification.
667 * @param[in,out] resource
668 * Pointer to the modify-header resource.
670 * Pointer to action specification.
672 * Pointer to rte_flow_item objects list.
674 * Pointer to flow attributes structure.
676 * Pointer to the error structure.
679 * 0 on success, a negative errno value otherwise and rte_errno is set.
682 flow_dv_convert_action_modify_ttl
683 (struct mlx5_flow_dv_modify_hdr_resource *resource,
684 const struct rte_flow_action *action,
685 const struct rte_flow_item *items,
686 union flow_dv_attr *attr,
687 struct rte_flow_error *error)
689 const struct rte_flow_action_set_ttl *conf =
690 (const struct rte_flow_action_set_ttl *)(action->conf);
691 struct rte_flow_item item;
692 struct rte_flow_item_ipv4 ipv4;
693 struct rte_flow_item_ipv4 ipv4_mask;
694 struct rte_flow_item_ipv6 ipv6;
695 struct rte_flow_item_ipv6 ipv6_mask;
696 struct field_modify_info *field;
699 flow_dv_attr_init(items, attr);
701 memset(&ipv4, 0, sizeof(ipv4));
702 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
703 ipv4.hdr.time_to_live = conf->ttl_value;
704 ipv4_mask.hdr.time_to_live = 0xFF;
705 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
707 item.mask = &ipv4_mask;
711 memset(&ipv6, 0, sizeof(ipv6));
712 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
713 ipv6.hdr.hop_limits = conf->ttl_value;
714 ipv6_mask.hdr.hop_limits = 0xFF;
715 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
717 item.mask = &ipv6_mask;
720 return flow_dv_convert_modify_action(&item, field, NULL, resource,
721 MLX5_MODIFICATION_TYPE_SET, error);
725 * Convert modify-header decrement TTL action to DV specification.
727 * @param[in,out] resource
728 * Pointer to the modify-header resource.
730 * Pointer to action specification.
732 * Pointer to rte_flow_item objects list.
734 * Pointer to flow attributes structure.
736 * Pointer to the error structure.
739 * 0 on success, a negative errno value otherwise and rte_errno is set.
742 flow_dv_convert_action_modify_dec_ttl
743 (struct mlx5_flow_dv_modify_hdr_resource *resource,
744 const struct rte_flow_item *items,
745 union flow_dv_attr *attr,
746 struct rte_flow_error *error)
748 struct rte_flow_item item;
749 struct rte_flow_item_ipv4 ipv4;
750 struct rte_flow_item_ipv4 ipv4_mask;
751 struct rte_flow_item_ipv6 ipv6;
752 struct rte_flow_item_ipv6 ipv6_mask;
753 struct field_modify_info *field;
756 flow_dv_attr_init(items, attr);
758 memset(&ipv4, 0, sizeof(ipv4));
759 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
760 ipv4.hdr.time_to_live = 0xFF;
761 ipv4_mask.hdr.time_to_live = 0xFF;
762 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
764 item.mask = &ipv4_mask;
768 memset(&ipv6, 0, sizeof(ipv6));
769 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
770 ipv6.hdr.hop_limits = 0xFF;
771 ipv6_mask.hdr.hop_limits = 0xFF;
772 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
774 item.mask = &ipv6_mask;
777 return flow_dv_convert_modify_action(&item, field, NULL, resource,
778 MLX5_MODIFICATION_TYPE_ADD, error);
782 * Convert modify-header increment/decrement TCP Sequence number
783 * to DV specification.
785 * @param[in,out] resource
786 * Pointer to the modify-header resource.
788 * Pointer to action specification.
790 * Pointer to the error structure.
793 * 0 on success, a negative errno value otherwise and rte_errno is set.
796 flow_dv_convert_action_modify_tcp_seq
797 (struct mlx5_flow_dv_modify_hdr_resource *resource,
798 const struct rte_flow_action *action,
799 struct rte_flow_error *error)
801 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
802 uint64_t value = rte_be_to_cpu_32(*conf);
803 struct rte_flow_item item;
804 struct rte_flow_item_tcp tcp;
805 struct rte_flow_item_tcp tcp_mask;
807 memset(&tcp, 0, sizeof(tcp));
808 memset(&tcp_mask, 0, sizeof(tcp_mask));
809 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
811 * The HW has no decrement operation, only increment operation.
812 * To simulate decrement X from Y using increment operation
813 * we need to add UINT32_MAX X times to Y.
814 * Each adding of UINT32_MAX decrements Y by 1.
817 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
818 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
819 item.type = RTE_FLOW_ITEM_TYPE_TCP;
821 item.mask = &tcp_mask;
822 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
823 MLX5_MODIFICATION_TYPE_ADD, error);
827 * Convert modify-header increment/decrement TCP Acknowledgment number
828 * to DV specification.
830 * @param[in,out] resource
831 * Pointer to the modify-header resource.
833 * Pointer to action specification.
835 * Pointer to the error structure.
838 * 0 on success, a negative errno value otherwise and rte_errno is set.
841 flow_dv_convert_action_modify_tcp_ack
842 (struct mlx5_flow_dv_modify_hdr_resource *resource,
843 const struct rte_flow_action *action,
844 struct rte_flow_error *error)
846 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
847 uint64_t value = rte_be_to_cpu_32(*conf);
848 struct rte_flow_item item;
849 struct rte_flow_item_tcp tcp;
850 struct rte_flow_item_tcp tcp_mask;
852 memset(&tcp, 0, sizeof(tcp));
853 memset(&tcp_mask, 0, sizeof(tcp_mask));
854 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
856 * The HW has no decrement operation, only increment operation.
857 * To simulate decrement X from Y using increment operation
858 * we need to add UINT32_MAX X times to Y.
859 * Each adding of UINT32_MAX decrements Y by 1.
862 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
863 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
864 item.type = RTE_FLOW_ITEM_TYPE_TCP;
866 item.mask = &tcp_mask;
867 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
868 MLX5_MODIFICATION_TYPE_ADD, error);
871 static enum mlx5_modification_field reg_to_field[] = {
872 [REG_NONE] = MLX5_MODI_OUT_NONE,
873 [REG_A] = MLX5_MODI_META_DATA_REG_A,
874 [REG_B] = MLX5_MODI_META_DATA_REG_B,
875 [REG_C_0] = MLX5_MODI_META_REG_C_0,
876 [REG_C_1] = MLX5_MODI_META_REG_C_1,
877 [REG_C_2] = MLX5_MODI_META_REG_C_2,
878 [REG_C_3] = MLX5_MODI_META_REG_C_3,
879 [REG_C_4] = MLX5_MODI_META_REG_C_4,
880 [REG_C_5] = MLX5_MODI_META_REG_C_5,
881 [REG_C_6] = MLX5_MODI_META_REG_C_6,
882 [REG_C_7] = MLX5_MODI_META_REG_C_7,
886 * Convert register set to DV specification.
888 * @param[in,out] resource
889 * Pointer to the modify-header resource.
891 * Pointer to action specification.
893 * Pointer to the error structure.
896 * 0 on success, a negative errno value otherwise and rte_errno is set.
899 flow_dv_convert_action_set_reg
900 (struct mlx5_flow_dv_modify_hdr_resource *resource,
901 const struct rte_flow_action *action,
902 struct rte_flow_error *error)
904 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
905 struct mlx5_modification_cmd *actions = resource->actions;
906 uint32_t i = resource->actions_num;
908 if (i >= MLX5_MAX_MODIFY_NUM)
909 return rte_flow_error_set(error, EINVAL,
910 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
911 "too many items to modify");
912 assert(conf->id != REG_NONE);
913 assert(conf->id < RTE_DIM(reg_to_field));
914 actions[i].action_type = MLX5_MODIFICATION_TYPE_SET;
915 actions[i].field = reg_to_field[conf->id];
916 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
917 actions[i].data1 = rte_cpu_to_be_32(conf->data);
919 resource->actions_num = i;
924 * Convert SET_TAG action to DV specification.
927 * Pointer to the rte_eth_dev structure.
928 * @param[in,out] resource
929 * Pointer to the modify-header resource.
931 * Pointer to action specification.
933 * Pointer to the error structure.
936 * 0 on success, a negative errno value otherwise and rte_errno is set.
939 flow_dv_convert_action_set_tag
940 (struct rte_eth_dev *dev,
941 struct mlx5_flow_dv_modify_hdr_resource *resource,
942 const struct rte_flow_action_set_tag *conf,
943 struct rte_flow_error *error)
945 rte_be32_t data = rte_cpu_to_be_32(conf->data);
946 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
947 struct rte_flow_item item = {
951 struct field_modify_info reg_c_x[] = {
954 enum mlx5_modification_field reg_type;
957 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
960 assert(ret != REG_NONE);
961 assert((unsigned int)ret < RTE_DIM(reg_to_field));
962 reg_type = reg_to_field[ret];
963 assert(reg_type > 0);
964 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
965 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
966 MLX5_MODIFICATION_TYPE_SET, error);
970 * Convert internal COPY_REG action to DV specification.
973 * Pointer to the rte_eth_dev structure.
975 * Pointer to the modify-header resource.
977 * Pointer to action specification.
979 * Pointer to the error structure.
982 * 0 on success, a negative errno value otherwise and rte_errno is set.
985 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
986 struct mlx5_flow_dv_modify_hdr_resource *res,
987 const struct rte_flow_action *action,
988 struct rte_flow_error *error)
990 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
991 rte_be32_t mask = RTE_BE32(UINT32_MAX);
992 struct rte_flow_item item = {
996 struct field_modify_info reg_src[] = {
997 {4, 0, reg_to_field[conf->src]},
1000 struct field_modify_info reg_dst = {
1002 .id = reg_to_field[conf->dst],
1004 /* Adjust reg_c[0] usage according to reported mask. */
1005 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1006 struct mlx5_priv *priv = dev->data->dev_private;
1007 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1010 assert(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1011 if (conf->dst == REG_C_0) {
1012 /* Copy to reg_c[0], within mask only. */
1013 reg_dst.offset = rte_bsf32(reg_c0);
1015 * Mask is ignoring the enianness, because
1016 * there is no conversion in datapath.
1018 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1019 /* Copy from destination lower bits to reg_c[0]. */
1020 mask = reg_c0 >> reg_dst.offset;
1022 /* Copy from destination upper bits to reg_c[0]. */
1023 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1024 rte_fls_u32(reg_c0));
1027 mask = rte_cpu_to_be_32(reg_c0);
1028 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1029 /* Copy from reg_c[0] to destination lower bits. */
1032 /* Copy from reg_c[0] to destination upper bits. */
1033 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1034 (rte_fls_u32(reg_c0) -
1039 return flow_dv_convert_modify_action(&item,
1040 reg_src, ®_dst, res,
1041 MLX5_MODIFICATION_TYPE_COPY,
1046 * Convert MARK action to DV specification. This routine is used
1047 * in extensive metadata only and requires metadata register to be
1048 * handled. In legacy mode hardware tag resource is engaged.
1051 * Pointer to the rte_eth_dev structure.
1053 * Pointer to MARK action specification.
1054 * @param[in,out] resource
1055 * Pointer to the modify-header resource.
1057 * Pointer to the error structure.
1060 * 0 on success, a negative errno value otherwise and rte_errno is set.
1063 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1064 const struct rte_flow_action_mark *conf,
1065 struct mlx5_flow_dv_modify_hdr_resource *resource,
1066 struct rte_flow_error *error)
1068 struct mlx5_priv *priv = dev->data->dev_private;
1069 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1070 priv->sh->dv_mark_mask);
1071 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1072 struct rte_flow_item item = {
1076 struct field_modify_info reg_c_x[] = {
1077 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1083 return rte_flow_error_set(error, EINVAL,
1084 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1085 NULL, "zero mark action mask");
1086 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1090 if (reg == REG_C_0) {
1091 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1092 uint32_t shl_c0 = rte_bsf32(msk_c0);
1094 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1095 mask = rte_cpu_to_be_32(mask) & msk_c0;
1096 mask = rte_cpu_to_be_32(mask << shl_c0);
1098 reg_c_x[0].id = reg_to_field[reg];
1099 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1100 MLX5_MODIFICATION_TYPE_SET, error);
1104 * Get metadata register index for specified steering domain.
1107 * Pointer to the rte_eth_dev structure.
1109 * Attributes of flow to determine steering domain.
1111 * Pointer to the error structure.
1114 * positive index on success, a negative errno value otherwise
1115 * and rte_errno is set.
1117 static enum modify_reg
1118 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1119 const struct rte_flow_attr *attr,
1120 struct rte_flow_error *error)
1123 mlx5_flow_get_reg_id(dev, attr->transfer ?
1127 MLX5_METADATA_RX, 0, error);
1129 return rte_flow_error_set(error,
1130 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1131 NULL, "unavailable "
1132 "metadata register");
1137 * Convert SET_META action to DV specification.
1140 * Pointer to the rte_eth_dev structure.
1141 * @param[in,out] resource
1142 * Pointer to the modify-header resource.
1144 * Attributes of flow that includes this item.
1146 * Pointer to action specification.
1148 * Pointer to the error structure.
1151 * 0 on success, a negative errno value otherwise and rte_errno is set.
1154 flow_dv_convert_action_set_meta
1155 (struct rte_eth_dev *dev,
1156 struct mlx5_flow_dv_modify_hdr_resource *resource,
1157 const struct rte_flow_attr *attr,
1158 const struct rte_flow_action_set_meta *conf,
1159 struct rte_flow_error *error)
1161 uint32_t data = conf->data;
1162 uint32_t mask = conf->mask;
1163 struct rte_flow_item item = {
1167 struct field_modify_info reg_c_x[] = {
1170 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1175 * In datapath code there is no endianness
1176 * coversions for perfromance reasons, all
1177 * pattern conversions are done in rte_flow.
1179 if (reg == REG_C_0) {
1180 struct mlx5_priv *priv = dev->data->dev_private;
1181 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1185 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1186 shl_c0 = rte_bsf32(msk_c0);
1188 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1192 assert(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1194 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1195 /* The routine expects parameters in memory as big-endian ones. */
1196 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1197 MLX5_MODIFICATION_TYPE_SET, error);
1201 * Convert modify-header set IPv4 DSCP action to DV specification.
1203 * @param[in,out] resource
1204 * Pointer to the modify-header resource.
1206 * Pointer to action specification.
1208 * Pointer to the error structure.
1211 * 0 on success, a negative errno value otherwise and rte_errno is set.
1214 flow_dv_convert_action_modify_ipv4_dscp
1215 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1216 const struct rte_flow_action *action,
1217 struct rte_flow_error *error)
1219 const struct rte_flow_action_set_dscp *conf =
1220 (const struct rte_flow_action_set_dscp *)(action->conf);
1221 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1222 struct rte_flow_item_ipv4 ipv4;
1223 struct rte_flow_item_ipv4 ipv4_mask;
1225 memset(&ipv4, 0, sizeof(ipv4));
1226 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1227 ipv4.hdr.type_of_service = conf->dscp;
1228 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1230 item.mask = &ipv4_mask;
1231 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1232 MLX5_MODIFICATION_TYPE_SET, error);
1236 * Convert modify-header set IPv6 DSCP action to DV specification.
1238 * @param[in,out] resource
1239 * Pointer to the modify-header resource.
1241 * Pointer to action specification.
1243 * Pointer to the error structure.
1246 * 0 on success, a negative errno value otherwise and rte_errno is set.
1249 flow_dv_convert_action_modify_ipv6_dscp
1250 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1251 const struct rte_flow_action *action,
1252 struct rte_flow_error *error)
1254 const struct rte_flow_action_set_dscp *conf =
1255 (const struct rte_flow_action_set_dscp *)(action->conf);
1256 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1257 struct rte_flow_item_ipv6 ipv6;
1258 struct rte_flow_item_ipv6 ipv6_mask;
1260 memset(&ipv6, 0, sizeof(ipv6));
1261 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1263 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1264 * rdma-core only accept the DSCP bits byte aligned start from
1265 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1266 * bits in IPv6 case as rdma-core requires byte aligned value.
1268 ipv6.hdr.vtc_flow = conf->dscp;
1269 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1271 item.mask = &ipv6_mask;
1272 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1273 MLX5_MODIFICATION_TYPE_SET, error);
1277 * Validate MARK item.
1280 * Pointer to the rte_eth_dev structure.
1282 * Item specification.
1284 * Attributes of flow that includes this item.
1286 * Pointer to error structure.
1289 * 0 on success, a negative errno value otherwise and rte_errno is set.
1292 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1293 const struct rte_flow_item *item,
1294 const struct rte_flow_attr *attr __rte_unused,
1295 struct rte_flow_error *error)
1297 struct mlx5_priv *priv = dev->data->dev_private;
1298 struct mlx5_dev_config *config = &priv->config;
1299 const struct rte_flow_item_mark *spec = item->spec;
1300 const struct rte_flow_item_mark *mask = item->mask;
1301 const struct rte_flow_item_mark nic_mask = {
1302 .id = priv->sh->dv_mark_mask,
1306 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1307 return rte_flow_error_set(error, ENOTSUP,
1308 RTE_FLOW_ERROR_TYPE_ITEM, item,
1309 "extended metadata feature"
1311 if (!mlx5_flow_ext_mreg_supported(dev))
1312 return rte_flow_error_set(error, ENOTSUP,
1313 RTE_FLOW_ERROR_TYPE_ITEM, item,
1314 "extended metadata register"
1315 " isn't supported");
1317 return rte_flow_error_set(error, ENOTSUP,
1318 RTE_FLOW_ERROR_TYPE_ITEM, item,
1319 "extended metadata register"
1320 " isn't available");
1321 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1325 return rte_flow_error_set(error, EINVAL,
1326 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1328 "data cannot be empty");
1329 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1330 return rte_flow_error_set(error, EINVAL,
1331 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1333 "mark id exceeds the limit");
1336 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1337 (const uint8_t *)&nic_mask,
1338 sizeof(struct rte_flow_item_mark),
1346 * Validate META item.
1349 * Pointer to the rte_eth_dev structure.
1351 * Item specification.
1353 * Attributes of flow that includes this item.
1355 * Pointer to error structure.
1358 * 0 on success, a negative errno value otherwise and rte_errno is set.
1361 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1362 const struct rte_flow_item *item,
1363 const struct rte_flow_attr *attr,
1364 struct rte_flow_error *error)
1366 struct mlx5_priv *priv = dev->data->dev_private;
1367 struct mlx5_dev_config *config = &priv->config;
1368 const struct rte_flow_item_meta *spec = item->spec;
1369 const struct rte_flow_item_meta *mask = item->mask;
1370 struct rte_flow_item_meta nic_mask = {
1377 return rte_flow_error_set(error, EINVAL,
1378 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1380 "data cannot be empty");
1382 return rte_flow_error_set(error, EINVAL,
1383 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1384 "data cannot be zero");
1385 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1386 if (!mlx5_flow_ext_mreg_supported(dev))
1387 return rte_flow_error_set(error, ENOTSUP,
1388 RTE_FLOW_ERROR_TYPE_ITEM, item,
1389 "extended metadata register"
1390 " isn't supported");
1391 reg = flow_dv_get_metadata_reg(dev, attr, error);
1395 return rte_flow_error_set(error, ENOTSUP,
1396 RTE_FLOW_ERROR_TYPE_ITEM, item,
1400 nic_mask.data = priv->sh->dv_meta_mask;
1403 mask = &rte_flow_item_meta_mask;
1404 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1405 (const uint8_t *)&nic_mask,
1406 sizeof(struct rte_flow_item_meta),
1412 * Validate TAG item.
1415 * Pointer to the rte_eth_dev structure.
1417 * Item specification.
1419 * Attributes of flow that includes this item.
1421 * Pointer to error structure.
1424 * 0 on success, a negative errno value otherwise and rte_errno is set.
1427 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1428 const struct rte_flow_item *item,
1429 const struct rte_flow_attr *attr __rte_unused,
1430 struct rte_flow_error *error)
1432 const struct rte_flow_item_tag *spec = item->spec;
1433 const struct rte_flow_item_tag *mask = item->mask;
1434 const struct rte_flow_item_tag nic_mask = {
1435 .data = RTE_BE32(UINT32_MAX),
1440 if (!mlx5_flow_ext_mreg_supported(dev))
1441 return rte_flow_error_set(error, ENOTSUP,
1442 RTE_FLOW_ERROR_TYPE_ITEM, item,
1443 "extensive metadata register"
1444 " isn't supported");
1446 return rte_flow_error_set(error, EINVAL,
1447 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1449 "data cannot be empty");
1451 mask = &rte_flow_item_tag_mask;
1452 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1453 (const uint8_t *)&nic_mask,
1454 sizeof(struct rte_flow_item_tag),
1458 if (mask->index != 0xff)
1459 return rte_flow_error_set(error, EINVAL,
1460 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1461 "partial mask for tag index"
1462 " is not supported");
1463 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1466 assert(ret != REG_NONE);
1471 * Validate vport item.
1474 * Pointer to the rte_eth_dev structure.
1476 * Item specification.
1478 * Attributes of flow that includes this item.
1479 * @param[in] item_flags
1480 * Bit-fields that holds the items detected until now.
1482 * Pointer to error structure.
1485 * 0 on success, a negative errno value otherwise and rte_errno is set.
1488 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1489 const struct rte_flow_item *item,
1490 const struct rte_flow_attr *attr,
1491 uint64_t item_flags,
1492 struct rte_flow_error *error)
1494 const struct rte_flow_item_port_id *spec = item->spec;
1495 const struct rte_flow_item_port_id *mask = item->mask;
1496 const struct rte_flow_item_port_id switch_mask = {
1499 struct mlx5_priv *esw_priv;
1500 struct mlx5_priv *dev_priv;
1503 if (!attr->transfer)
1504 return rte_flow_error_set(error, EINVAL,
1505 RTE_FLOW_ERROR_TYPE_ITEM,
1507 "match on port id is valid only"
1508 " when transfer flag is enabled");
1509 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1510 return rte_flow_error_set(error, ENOTSUP,
1511 RTE_FLOW_ERROR_TYPE_ITEM, item,
1512 "multiple source ports are not"
1515 mask = &switch_mask;
1516 if (mask->id != 0xffffffff)
1517 return rte_flow_error_set(error, ENOTSUP,
1518 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1520 "no support for partial mask on"
1522 ret = mlx5_flow_item_acceptable
1523 (item, (const uint8_t *)mask,
1524 (const uint8_t *)&rte_flow_item_port_id_mask,
1525 sizeof(struct rte_flow_item_port_id),
1531 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1533 return rte_flow_error_set(error, rte_errno,
1534 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1535 "failed to obtain E-Switch info for"
1537 dev_priv = mlx5_dev_to_eswitch_info(dev);
1539 return rte_flow_error_set(error, rte_errno,
1540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1542 "failed to obtain E-Switch info");
1543 if (esw_priv->domain_id != dev_priv->domain_id)
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1546 "cannot match on a port from a"
1547 " different E-Switch");
1552 * Validate GTP item.
1555 * Pointer to the rte_eth_dev structure.
1557 * Item specification.
1558 * @param[in] item_flags
1559 * Bit-fields that holds the items detected until now.
1561 * Pointer to error structure.
1564 * 0 on success, a negative errno value otherwise and rte_errno is set.
1567 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1568 const struct rte_flow_item *item,
1569 uint64_t item_flags,
1570 struct rte_flow_error *error)
1572 struct mlx5_priv *priv = dev->data->dev_private;
1573 const struct rte_flow_item_gtp *mask = item->mask;
1574 const struct rte_flow_item_gtp nic_mask = {
1576 .teid = RTE_BE32(0xffffffff),
1579 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1580 return rte_flow_error_set(error, ENOTSUP,
1581 RTE_FLOW_ERROR_TYPE_ITEM, item,
1582 "GTP support is not enabled");
1583 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1584 return rte_flow_error_set(error, ENOTSUP,
1585 RTE_FLOW_ERROR_TYPE_ITEM, item,
1586 "multiple tunnel layers not"
1588 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1589 return rte_flow_error_set(error, EINVAL,
1590 RTE_FLOW_ERROR_TYPE_ITEM, item,
1591 "no outer UDP layer found");
1593 mask = &rte_flow_item_gtp_mask;
1594 return mlx5_flow_item_acceptable
1595 (item, (const uint8_t *)mask,
1596 (const uint8_t *)&nic_mask,
1597 sizeof(struct rte_flow_item_gtp),
1602 * Validate the pop VLAN action.
1605 * Pointer to the rte_eth_dev structure.
1606 * @param[in] action_flags
1607 * Holds the actions detected until now.
1609 * Pointer to the pop vlan action.
1610 * @param[in] item_flags
1611 * The items found in this flow rule.
1613 * Pointer to flow attributes.
1615 * Pointer to error structure.
1618 * 0 on success, a negative errno value otherwise and rte_errno is set.
1621 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1622 uint64_t action_flags,
1623 const struct rte_flow_action *action,
1624 uint64_t item_flags,
1625 const struct rte_flow_attr *attr,
1626 struct rte_flow_error *error)
1628 struct mlx5_priv *priv = dev->data->dev_private;
1632 if (!priv->sh->pop_vlan_action)
1633 return rte_flow_error_set(error, ENOTSUP,
1634 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1636 "pop vlan action is not supported");
1638 return rte_flow_error_set(error, ENOTSUP,
1639 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1641 "pop vlan action not supported for "
1643 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1644 return rte_flow_error_set(error, ENOTSUP,
1645 RTE_FLOW_ERROR_TYPE_ACTION, action,
1646 "no support for multiple VLAN "
1648 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1649 return rte_flow_error_set(error, ENOTSUP,
1650 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1652 "cannot pop vlan without a "
1653 "match on (outer) vlan in the flow");
1654 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1655 return rte_flow_error_set(error, EINVAL,
1656 RTE_FLOW_ERROR_TYPE_ACTION, action,
1657 "wrong action order, port_id should "
1658 "be after pop VLAN action");
1663 * Get VLAN default info from vlan match info.
1666 * the list of item specifications.
1668 * pointer VLAN info to fill to.
1671 * 0 on success, a negative errno value otherwise and rte_errno is set.
1674 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1675 struct rte_vlan_hdr *vlan)
1677 const struct rte_flow_item_vlan nic_mask = {
1678 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1679 MLX5DV_FLOW_VLAN_VID_MASK),
1680 .inner_type = RTE_BE16(0xffff),
1685 for (; items->type != RTE_FLOW_ITEM_TYPE_END &&
1686 items->type != RTE_FLOW_ITEM_TYPE_VLAN; items++)
1688 if (items->type == RTE_FLOW_ITEM_TYPE_VLAN) {
1689 const struct rte_flow_item_vlan *vlan_m = items->mask;
1690 const struct rte_flow_item_vlan *vlan_v = items->spec;
1694 /* Only full match values are accepted */
1695 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1696 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1697 vlan->vlan_tci &= MLX5DV_FLOW_VLAN_PCP_MASK;
1699 rte_be_to_cpu_16(vlan_v->tci &
1700 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1702 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1703 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1704 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1706 rte_be_to_cpu_16(vlan_v->tci &
1707 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1709 if (vlan_m->inner_type == nic_mask.inner_type)
1710 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1711 vlan_m->inner_type);
1716 * Validate the push VLAN action.
1718 * @param[in] action_flags
1719 * Holds the actions detected until now.
1720 * @param[in] item_flags
1721 * The items found in this flow rule.
1723 * Pointer to the action structure.
1725 * Pointer to flow attributes
1727 * Pointer to error structure.
1730 * 0 on success, a negative errno value otherwise and rte_errno is set.
1733 flow_dv_validate_action_push_vlan(uint64_t action_flags,
1734 uint64_t item_flags __rte_unused,
1735 const struct rte_flow_action *action,
1736 const struct rte_flow_attr *attr,
1737 struct rte_flow_error *error)
1739 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1742 return rte_flow_error_set(error, ENOTSUP,
1743 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1745 "push VLAN action not supported for "
1747 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1748 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1749 return rte_flow_error_set(error, EINVAL,
1750 RTE_FLOW_ERROR_TYPE_ACTION, action,
1751 "invalid vlan ethertype");
1752 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1753 return rte_flow_error_set(error, ENOTSUP,
1754 RTE_FLOW_ERROR_TYPE_ACTION, action,
1755 "no support for multiple VLAN "
1757 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1758 return rte_flow_error_set(error, EINVAL,
1759 RTE_FLOW_ERROR_TYPE_ACTION, action,
1760 "wrong action order, port_id should "
1761 "be after push VLAN");
1767 * Validate the set VLAN PCP.
1769 * @param[in] action_flags
1770 * Holds the actions detected until now.
1771 * @param[in] actions
1772 * Pointer to the list of actions remaining in the flow rule.
1774 * Pointer to error structure.
1777 * 0 on success, a negative errno value otherwise and rte_errno is set.
1780 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
1781 const struct rte_flow_action actions[],
1782 struct rte_flow_error *error)
1784 const struct rte_flow_action *action = actions;
1785 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
1787 if (conf->vlan_pcp > 7)
1788 return rte_flow_error_set(error, EINVAL,
1789 RTE_FLOW_ERROR_TYPE_ACTION, action,
1790 "VLAN PCP value is too big");
1791 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
1792 return rte_flow_error_set(error, ENOTSUP,
1793 RTE_FLOW_ERROR_TYPE_ACTION, action,
1794 "set VLAN PCP action must follow "
1795 "the push VLAN action");
1796 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
1797 return rte_flow_error_set(error, ENOTSUP,
1798 RTE_FLOW_ERROR_TYPE_ACTION, action,
1799 "Multiple VLAN PCP modification are "
1801 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1802 return rte_flow_error_set(error, EINVAL,
1803 RTE_FLOW_ERROR_TYPE_ACTION, action,
1804 "wrong action order, port_id should "
1805 "be after set VLAN PCP");
1810 * Validate the set VLAN VID.
1812 * @param[in] item_flags
1813 * Holds the items detected in this rule.
1814 * @param[in] action_flags
1815 * Holds the actions detected until now.
1816 * @param[in] actions
1817 * Pointer to the list of actions remaining in the flow rule.
1819 * Pointer to error structure.
1822 * 0 on success, a negative errno value otherwise and rte_errno is set.
1825 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
1826 uint64_t action_flags,
1827 const struct rte_flow_action actions[],
1828 struct rte_flow_error *error)
1830 const struct rte_flow_action *action = actions;
1831 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
1833 if (conf->vlan_vid > RTE_BE16(0xFFE))
1834 return rte_flow_error_set(error, EINVAL,
1835 RTE_FLOW_ERROR_TYPE_ACTION, action,
1836 "VLAN VID value is too big");
1837 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
1838 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1839 return rte_flow_error_set(error, ENOTSUP,
1840 RTE_FLOW_ERROR_TYPE_ACTION, action,
1841 "set VLAN VID action must follow push"
1842 " VLAN action or match on VLAN item");
1843 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
1844 return rte_flow_error_set(error, ENOTSUP,
1845 RTE_FLOW_ERROR_TYPE_ACTION, action,
1846 "Multiple VLAN VID modifications are "
1848 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1849 return rte_flow_error_set(error, EINVAL,
1850 RTE_FLOW_ERROR_TYPE_ACTION, action,
1851 "wrong action order, port_id should "
1852 "be after set VLAN VID");
1857 * Validate the FLAG action.
1860 * Pointer to the rte_eth_dev structure.
1861 * @param[in] action_flags
1862 * Holds the actions detected until now.
1864 * Pointer to flow attributes
1866 * Pointer to error structure.
1869 * 0 on success, a negative errno value otherwise and rte_errno is set.
1872 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
1873 uint64_t action_flags,
1874 const struct rte_flow_attr *attr,
1875 struct rte_flow_error *error)
1877 struct mlx5_priv *priv = dev->data->dev_private;
1878 struct mlx5_dev_config *config = &priv->config;
1881 /* Fall back if no extended metadata register support. */
1882 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1883 return mlx5_flow_validate_action_flag(action_flags, attr,
1885 /* Extensive metadata mode requires registers. */
1886 if (!mlx5_flow_ext_mreg_supported(dev))
1887 return rte_flow_error_set(error, ENOTSUP,
1888 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1889 "no metadata registers "
1890 "to support flag action");
1891 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
1892 return rte_flow_error_set(error, ENOTSUP,
1893 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1894 "extended metadata register"
1895 " isn't available");
1896 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1900 if (action_flags & MLX5_FLOW_ACTION_MARK)
1901 return rte_flow_error_set(error, EINVAL,
1902 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1903 "can't mark and flag in same flow");
1904 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1905 return rte_flow_error_set(error, EINVAL,
1906 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1908 " actions in same flow");
1913 * Validate MARK action.
1916 * Pointer to the rte_eth_dev structure.
1918 * Pointer to action.
1919 * @param[in] action_flags
1920 * Holds the actions detected until now.
1922 * Pointer to flow attributes
1924 * Pointer to error structure.
1927 * 0 on success, a negative errno value otherwise and rte_errno is set.
1930 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
1931 const struct rte_flow_action *action,
1932 uint64_t action_flags,
1933 const struct rte_flow_attr *attr,
1934 struct rte_flow_error *error)
1936 struct mlx5_priv *priv = dev->data->dev_private;
1937 struct mlx5_dev_config *config = &priv->config;
1938 const struct rte_flow_action_mark *mark = action->conf;
1941 /* Fall back if no extended metadata register support. */
1942 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1943 return mlx5_flow_validate_action_mark(action, action_flags,
1945 /* Extensive metadata mode requires registers. */
1946 if (!mlx5_flow_ext_mreg_supported(dev))
1947 return rte_flow_error_set(error, ENOTSUP,
1948 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1949 "no metadata registers "
1950 "to support mark action");
1951 if (!priv->sh->dv_mark_mask)
1952 return rte_flow_error_set(error, ENOTSUP,
1953 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1954 "extended metadata register"
1955 " isn't available");
1956 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1961 return rte_flow_error_set(error, EINVAL,
1962 RTE_FLOW_ERROR_TYPE_ACTION, action,
1963 "configuration cannot be null");
1964 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
1965 return rte_flow_error_set(error, EINVAL,
1966 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1968 "mark id exceeds the limit");
1969 if (action_flags & MLX5_FLOW_ACTION_FLAG)
1970 return rte_flow_error_set(error, EINVAL,
1971 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1972 "can't flag and mark in same flow");
1973 if (action_flags & MLX5_FLOW_ACTION_MARK)
1974 return rte_flow_error_set(error, EINVAL,
1975 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
1976 "can't have 2 mark actions in same"
1982 * Validate SET_META action.
1985 * Pointer to the rte_eth_dev structure.
1987 * Pointer to the action structure.
1988 * @param[in] action_flags
1989 * Holds the actions detected until now.
1991 * Pointer to flow attributes
1993 * Pointer to error structure.
1996 * 0 on success, a negative errno value otherwise and rte_errno is set.
1999 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2000 const struct rte_flow_action *action,
2001 uint64_t action_flags __rte_unused,
2002 const struct rte_flow_attr *attr,
2003 struct rte_flow_error *error)
2005 const struct rte_flow_action_set_meta *conf;
2006 uint32_t nic_mask = UINT32_MAX;
2009 if (!mlx5_flow_ext_mreg_supported(dev))
2010 return rte_flow_error_set(error, ENOTSUP,
2011 RTE_FLOW_ERROR_TYPE_ACTION, action,
2012 "extended metadata register"
2013 " isn't supported");
2014 reg = flow_dv_get_metadata_reg(dev, attr, error);
2017 if (reg != REG_A && reg != REG_B) {
2018 struct mlx5_priv *priv = dev->data->dev_private;
2020 nic_mask = priv->sh->dv_meta_mask;
2022 if (!(action->conf))
2023 return rte_flow_error_set(error, EINVAL,
2024 RTE_FLOW_ERROR_TYPE_ACTION, action,
2025 "configuration cannot be null");
2026 conf = (const struct rte_flow_action_set_meta *)action->conf;
2028 return rte_flow_error_set(error, EINVAL,
2029 RTE_FLOW_ERROR_TYPE_ACTION, action,
2030 "zero mask doesn't have any effect");
2031 if (conf->mask & ~nic_mask)
2032 return rte_flow_error_set(error, EINVAL,
2033 RTE_FLOW_ERROR_TYPE_ACTION, action,
2034 "meta data must be within reg C0");
2035 if (!(conf->data & conf->mask))
2036 return rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ACTION, action,
2038 "zero value has no effect");
2043 * Validate SET_TAG action.
2046 * Pointer to the rte_eth_dev structure.
2048 * Pointer to the action structure.
2049 * @param[in] action_flags
2050 * Holds the actions detected until now.
2052 * Pointer to flow attributes
2054 * Pointer to error structure.
2057 * 0 on success, a negative errno value otherwise and rte_errno is set.
2060 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2061 const struct rte_flow_action *action,
2062 uint64_t action_flags,
2063 const struct rte_flow_attr *attr,
2064 struct rte_flow_error *error)
2066 const struct rte_flow_action_set_tag *conf;
2067 const uint64_t terminal_action_flags =
2068 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2069 MLX5_FLOW_ACTION_RSS;
2072 if (!mlx5_flow_ext_mreg_supported(dev))
2073 return rte_flow_error_set(error, ENOTSUP,
2074 RTE_FLOW_ERROR_TYPE_ACTION, action,
2075 "extensive metadata register"
2076 " isn't supported");
2077 if (!(action->conf))
2078 return rte_flow_error_set(error, EINVAL,
2079 RTE_FLOW_ERROR_TYPE_ACTION, action,
2080 "configuration cannot be null");
2081 conf = (const struct rte_flow_action_set_tag *)action->conf;
2083 return rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ACTION, action,
2085 "zero mask doesn't have any effect");
2086 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2089 if (!attr->transfer && attr->ingress &&
2090 (action_flags & terminal_action_flags))
2091 return rte_flow_error_set(error, EINVAL,
2092 RTE_FLOW_ERROR_TYPE_ACTION, action,
2093 "set_tag has no effect"
2094 " with terminal actions");
2099 * Validate count action.
2102 * Pointer to rte_eth_dev structure.
2104 * Pointer to error structure.
2107 * 0 on success, a negative errno value otherwise and rte_errno is set.
2110 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2111 struct rte_flow_error *error)
2113 struct mlx5_priv *priv = dev->data->dev_private;
2115 if (!priv->config.devx)
2117 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2121 return rte_flow_error_set
2123 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2125 "count action not supported");
2129 * Validate the L2 encap action.
2131 * @param[in] action_flags
2132 * Holds the actions detected until now.
2134 * Pointer to the action structure.
2136 * Pointer to flow attributes
2138 * Pointer to error structure.
2141 * 0 on success, a negative errno value otherwise and rte_errno is set.
2144 flow_dv_validate_action_l2_encap(uint64_t action_flags,
2145 const struct rte_flow_action *action,
2146 const struct rte_flow_attr *attr,
2147 struct rte_flow_error *error)
2149 if (!(action->conf))
2150 return rte_flow_error_set(error, EINVAL,
2151 RTE_FLOW_ERROR_TYPE_ACTION, action,
2152 "configuration cannot be null");
2153 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2154 return rte_flow_error_set(error, EINVAL,
2155 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2156 "can only have a single encap or"
2157 " decap action in a flow");
2158 if (!attr->transfer && attr->ingress)
2159 return rte_flow_error_set(error, ENOTSUP,
2160 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2162 "encap action not supported for "
2168 * Validate the L2 decap action.
2170 * @param[in] action_flags
2171 * Holds the actions detected until now.
2173 * Pointer to flow attributes
2175 * Pointer to error structure.
2178 * 0 on success, a negative errno value otherwise and rte_errno is set.
2181 flow_dv_validate_action_l2_decap(uint64_t action_flags,
2182 const struct rte_flow_attr *attr,
2183 struct rte_flow_error *error)
2185 if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
2186 return rte_flow_error_set(error, EINVAL,
2187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 "can only have a single encap or"
2189 " decap action in a flow");
2190 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2191 return rte_flow_error_set(error, EINVAL,
2192 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2193 "can't have decap action after"
2196 return rte_flow_error_set(error, ENOTSUP,
2197 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2199 "decap action not supported for "
2205 * Validate the raw encap action.
2207 * @param[in] action_flags
2208 * Holds the actions detected until now.
2210 * Pointer to the encap action.
2212 * Pointer to flow attributes
2214 * Pointer to error structure.
2217 * 0 on success, a negative errno value otherwise and rte_errno is set.
2220 flow_dv_validate_action_raw_encap(uint64_t action_flags,
2221 const struct rte_flow_action *action,
2222 const struct rte_flow_attr *attr,
2223 struct rte_flow_error *error)
2225 const struct rte_flow_action_raw_encap *raw_encap =
2226 (const struct rte_flow_action_raw_encap *)action->conf;
2227 if (!(action->conf))
2228 return rte_flow_error_set(error, EINVAL,
2229 RTE_FLOW_ERROR_TYPE_ACTION, action,
2230 "configuration cannot be null");
2231 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2232 return rte_flow_error_set(error, EINVAL,
2233 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2234 "can only have a single encap"
2235 " action in a flow");
2236 /* encap without preceding decap is not supported for ingress */
2237 if (!attr->transfer && attr->ingress &&
2238 !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
2239 return rte_flow_error_set(error, ENOTSUP,
2240 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
2242 "encap action not supported for "
2244 if (!raw_encap->size || !raw_encap->data)
2245 return rte_flow_error_set(error, EINVAL,
2246 RTE_FLOW_ERROR_TYPE_ACTION, action,
2247 "raw encap data cannot be empty");
2252 * Validate the raw decap action.
2254 * @param[in] action_flags
2255 * Holds the actions detected until now.
2257 * Pointer to the encap action.
2259 * Pointer to flow attributes
2261 * Pointer to error structure.
2264 * 0 on success, a negative errno value otherwise and rte_errno is set.
2267 flow_dv_validate_action_raw_decap(uint64_t action_flags,
2268 const struct rte_flow_action *action,
2269 const struct rte_flow_attr *attr,
2270 struct rte_flow_error *error)
2272 const struct rte_flow_action_raw_decap *decap = action->conf;
2274 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
2275 return rte_flow_error_set(error, EINVAL,
2276 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2277 "can't have encap action before"
2279 if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
2280 return rte_flow_error_set(error, EINVAL,
2281 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2282 "can only have a single decap"
2283 " action in a flow");
2284 /* decap action is valid on egress only if it is followed by encap */
2285 if (attr->egress && decap &&
2286 decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) {
2287 return rte_flow_error_set(error, ENOTSUP,
2288 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2289 NULL, "decap action not supported"
2291 } else if (decap && decap->size > MLX5_ENCAPSULATION_DECISION_SIZE &&
2292 (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)) {
2293 return rte_flow_error_set(error, EINVAL,
2294 RTE_FLOW_ERROR_TYPE_ACTION,
2296 "can't have decap action "
2297 "after modify action");
2303 * Find existing encap/decap resource or create and register a new one.
2305 * @param[in, out] dev
2306 * Pointer to rte_eth_dev structure.
2307 * @param[in, out] resource
2308 * Pointer to encap/decap resource.
2309 * @parm[in, out] dev_flow
2310 * Pointer to the dev_flow.
2312 * pointer to error structure.
2315 * 0 on success otherwise -errno and errno is set.
2318 flow_dv_encap_decap_resource_register
2319 (struct rte_eth_dev *dev,
2320 struct mlx5_flow_dv_encap_decap_resource *resource,
2321 struct mlx5_flow *dev_flow,
2322 struct rte_flow_error *error)
2324 struct mlx5_priv *priv = dev->data->dev_private;
2325 struct mlx5_ibv_shared *sh = priv->sh;
2326 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2327 struct mlx5dv_dr_domain *domain;
2329 resource->flags = dev_flow->group ? 0 : 1;
2330 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2331 domain = sh->fdb_domain;
2332 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2333 domain = sh->rx_domain;
2335 domain = sh->tx_domain;
2336 /* Lookup a matching resource from cache. */
2337 LIST_FOREACH(cache_resource, &sh->encaps_decaps, next) {
2338 if (resource->reformat_type == cache_resource->reformat_type &&
2339 resource->ft_type == cache_resource->ft_type &&
2340 resource->flags == cache_resource->flags &&
2341 resource->size == cache_resource->size &&
2342 !memcmp((const void *)resource->buf,
2343 (const void *)cache_resource->buf,
2345 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2346 (void *)cache_resource,
2347 rte_atomic32_read(&cache_resource->refcnt));
2348 rte_atomic32_inc(&cache_resource->refcnt);
2349 dev_flow->dv.encap_decap = cache_resource;
2353 /* Register new encap/decap resource. */
2354 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2355 if (!cache_resource)
2356 return rte_flow_error_set(error, ENOMEM,
2357 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2358 "cannot allocate resource memory");
2359 *cache_resource = *resource;
2360 cache_resource->verbs_action =
2361 mlx5_glue->dv_create_flow_action_packet_reformat
2362 (sh->ctx, cache_resource->reformat_type,
2363 cache_resource->ft_type, domain, cache_resource->flags,
2364 cache_resource->size,
2365 (cache_resource->size ? cache_resource->buf : NULL));
2366 if (!cache_resource->verbs_action) {
2367 rte_free(cache_resource);
2368 return rte_flow_error_set(error, ENOMEM,
2369 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2370 NULL, "cannot create action");
2372 rte_atomic32_init(&cache_resource->refcnt);
2373 rte_atomic32_inc(&cache_resource->refcnt);
2374 LIST_INSERT_HEAD(&sh->encaps_decaps, cache_resource, next);
2375 dev_flow->dv.encap_decap = cache_resource;
2376 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2377 (void *)cache_resource,
2378 rte_atomic32_read(&cache_resource->refcnt));
2383 * Find existing table jump resource or create and register a new one.
2385 * @param[in, out] dev
2386 * Pointer to rte_eth_dev structure.
2387 * @param[in, out] tbl
2388 * Pointer to flow table resource.
2389 * @parm[in, out] dev_flow
2390 * Pointer to the dev_flow.
2392 * pointer to error structure.
2395 * 0 on success otherwise -errno and errno is set.
2398 flow_dv_jump_tbl_resource_register
2399 (struct rte_eth_dev *dev __rte_unused,
2400 struct mlx5_flow_tbl_resource *tbl,
2401 struct mlx5_flow *dev_flow,
2402 struct rte_flow_error *error)
2404 struct mlx5_flow_tbl_data_entry *tbl_data =
2405 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2409 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2411 tbl_data->jump.action =
2412 mlx5_glue->dr_create_flow_action_dest_flow_tbl
2414 if (!tbl_data->jump.action)
2415 return rte_flow_error_set(error, ENOMEM,
2416 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2417 NULL, "cannot create jump action");
2418 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2419 (void *)&tbl_data->jump, cnt);
2421 assert(tbl_data->jump.action);
2422 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2423 (void *)&tbl_data->jump, cnt);
2425 rte_atomic32_inc(&tbl_data->jump.refcnt);
2426 dev_flow->dv.jump = &tbl_data->jump;
2431 * Find existing table port ID resource or create and register a new one.
2433 * @param[in, out] dev
2434 * Pointer to rte_eth_dev structure.
2435 * @param[in, out] resource
2436 * Pointer to port ID action resource.
2437 * @parm[in, out] dev_flow
2438 * Pointer to the dev_flow.
2440 * pointer to error structure.
2443 * 0 on success otherwise -errno and errno is set.
2446 flow_dv_port_id_action_resource_register
2447 (struct rte_eth_dev *dev,
2448 struct mlx5_flow_dv_port_id_action_resource *resource,
2449 struct mlx5_flow *dev_flow,
2450 struct rte_flow_error *error)
2452 struct mlx5_priv *priv = dev->data->dev_private;
2453 struct mlx5_ibv_shared *sh = priv->sh;
2454 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2456 /* Lookup a matching resource from cache. */
2457 LIST_FOREACH(cache_resource, &sh->port_id_action_list, next) {
2458 if (resource->port_id == cache_resource->port_id) {
2459 DRV_LOG(DEBUG, "port id action resource resource %p: "
2461 (void *)cache_resource,
2462 rte_atomic32_read(&cache_resource->refcnt));
2463 rte_atomic32_inc(&cache_resource->refcnt);
2464 dev_flow->dv.port_id_action = cache_resource;
2468 /* Register new port id action resource. */
2469 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2470 if (!cache_resource)
2471 return rte_flow_error_set(error, ENOMEM,
2472 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2473 "cannot allocate resource memory");
2474 *cache_resource = *resource;
2476 * Depending on rdma_core version the glue routine calls
2477 * either mlx5dv_dr_action_create_dest_ib_port(domain, ibv_port)
2478 * or mlx5dv_dr_action_create_dest_vport(domain, vport_id).
2480 cache_resource->action =
2481 mlx5_glue->dr_create_flow_action_dest_port
2482 (priv->sh->fdb_domain, resource->port_id);
2483 if (!cache_resource->action) {
2484 rte_free(cache_resource);
2485 return rte_flow_error_set(error, ENOMEM,
2486 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2487 NULL, "cannot create action");
2489 rte_atomic32_init(&cache_resource->refcnt);
2490 rte_atomic32_inc(&cache_resource->refcnt);
2491 LIST_INSERT_HEAD(&sh->port_id_action_list, cache_resource, next);
2492 dev_flow->dv.port_id_action = cache_resource;
2493 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2494 (void *)cache_resource,
2495 rte_atomic32_read(&cache_resource->refcnt));
2500 * Find existing push vlan resource or create and register a new one.
2502 * @param [in, out] dev
2503 * Pointer to rte_eth_dev structure.
2504 * @param[in, out] resource
2505 * Pointer to port ID action resource.
2506 * @parm[in, out] dev_flow
2507 * Pointer to the dev_flow.
2509 * pointer to error structure.
2512 * 0 on success otherwise -errno and errno is set.
2515 flow_dv_push_vlan_action_resource_register
2516 (struct rte_eth_dev *dev,
2517 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2518 struct mlx5_flow *dev_flow,
2519 struct rte_flow_error *error)
2521 struct mlx5_priv *priv = dev->data->dev_private;
2522 struct mlx5_ibv_shared *sh = priv->sh;
2523 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2524 struct mlx5dv_dr_domain *domain;
2526 /* Lookup a matching resource from cache. */
2527 LIST_FOREACH(cache_resource, &sh->push_vlan_action_list, next) {
2528 if (resource->vlan_tag == cache_resource->vlan_tag &&
2529 resource->ft_type == cache_resource->ft_type) {
2530 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2532 (void *)cache_resource,
2533 rte_atomic32_read(&cache_resource->refcnt));
2534 rte_atomic32_inc(&cache_resource->refcnt);
2535 dev_flow->dv.push_vlan_res = cache_resource;
2539 /* Register new push_vlan action resource. */
2540 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
2541 if (!cache_resource)
2542 return rte_flow_error_set(error, ENOMEM,
2543 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2544 "cannot allocate resource memory");
2545 *cache_resource = *resource;
2546 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2547 domain = sh->fdb_domain;
2548 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2549 domain = sh->rx_domain;
2551 domain = sh->tx_domain;
2552 cache_resource->action =
2553 mlx5_glue->dr_create_flow_action_push_vlan(domain,
2554 resource->vlan_tag);
2555 if (!cache_resource->action) {
2556 rte_free(cache_resource);
2557 return rte_flow_error_set(error, ENOMEM,
2558 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2559 NULL, "cannot create action");
2561 rte_atomic32_init(&cache_resource->refcnt);
2562 rte_atomic32_inc(&cache_resource->refcnt);
2563 LIST_INSERT_HEAD(&sh->push_vlan_action_list, cache_resource, next);
2564 dev_flow->dv.push_vlan_res = cache_resource;
2565 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2566 (void *)cache_resource,
2567 rte_atomic32_read(&cache_resource->refcnt));
2571 * Get the size of specific rte_flow_item_type
2573 * @param[in] item_type
2574 * Tested rte_flow_item_type.
2577 * sizeof struct item_type, 0 if void or irrelevant.
2580 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
2584 switch (item_type) {
2585 case RTE_FLOW_ITEM_TYPE_ETH:
2586 retval = sizeof(struct rte_flow_item_eth);
2588 case RTE_FLOW_ITEM_TYPE_VLAN:
2589 retval = sizeof(struct rte_flow_item_vlan);
2591 case RTE_FLOW_ITEM_TYPE_IPV4:
2592 retval = sizeof(struct rte_flow_item_ipv4);
2594 case RTE_FLOW_ITEM_TYPE_IPV6:
2595 retval = sizeof(struct rte_flow_item_ipv6);
2597 case RTE_FLOW_ITEM_TYPE_UDP:
2598 retval = sizeof(struct rte_flow_item_udp);
2600 case RTE_FLOW_ITEM_TYPE_TCP:
2601 retval = sizeof(struct rte_flow_item_tcp);
2603 case RTE_FLOW_ITEM_TYPE_VXLAN:
2604 retval = sizeof(struct rte_flow_item_vxlan);
2606 case RTE_FLOW_ITEM_TYPE_GRE:
2607 retval = sizeof(struct rte_flow_item_gre);
2609 case RTE_FLOW_ITEM_TYPE_NVGRE:
2610 retval = sizeof(struct rte_flow_item_nvgre);
2612 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2613 retval = sizeof(struct rte_flow_item_vxlan_gpe);
2615 case RTE_FLOW_ITEM_TYPE_MPLS:
2616 retval = sizeof(struct rte_flow_item_mpls);
2618 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2626 #define MLX5_ENCAP_IPV4_VERSION 0x40
2627 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2628 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2629 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2630 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2631 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2632 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2635 * Convert the encap action data from list of rte_flow_item to raw buffer
2638 * Pointer to rte_flow_item objects list.
2640 * Pointer to the output buffer.
2642 * Pointer to the output buffer size.
2644 * Pointer to the error structure.
2647 * 0 on success, a negative errno value otherwise and rte_errno is set.
2650 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2651 size_t *size, struct rte_flow_error *error)
2653 struct rte_ether_hdr *eth = NULL;
2654 struct rte_vlan_hdr *vlan = NULL;
2655 struct rte_ipv4_hdr *ipv4 = NULL;
2656 struct rte_ipv6_hdr *ipv6 = NULL;
2657 struct rte_udp_hdr *udp = NULL;
2658 struct rte_vxlan_hdr *vxlan = NULL;
2659 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2660 struct rte_gre_hdr *gre = NULL;
2662 size_t temp_size = 0;
2665 return rte_flow_error_set(error, EINVAL,
2666 RTE_FLOW_ERROR_TYPE_ACTION,
2667 NULL, "invalid empty data");
2668 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2669 len = flow_dv_get_item_len(items->type);
2670 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2671 return rte_flow_error_set(error, EINVAL,
2672 RTE_FLOW_ERROR_TYPE_ACTION,
2673 (void *)items->type,
2674 "items total size is too big"
2675 " for encap action");
2676 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2677 switch (items->type) {
2678 case RTE_FLOW_ITEM_TYPE_ETH:
2679 eth = (struct rte_ether_hdr *)&buf[temp_size];
2681 case RTE_FLOW_ITEM_TYPE_VLAN:
2682 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2684 return rte_flow_error_set(error, EINVAL,
2685 RTE_FLOW_ERROR_TYPE_ACTION,
2686 (void *)items->type,
2687 "eth header not found");
2688 if (!eth->ether_type)
2689 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2691 case RTE_FLOW_ITEM_TYPE_IPV4:
2692 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2694 return rte_flow_error_set(error, EINVAL,
2695 RTE_FLOW_ERROR_TYPE_ACTION,
2696 (void *)items->type,
2697 "neither eth nor vlan"
2699 if (vlan && !vlan->eth_proto)
2700 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2701 else if (eth && !eth->ether_type)
2702 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2703 if (!ipv4->version_ihl)
2704 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
2705 MLX5_ENCAP_IPV4_IHL_MIN;
2706 if (!ipv4->time_to_live)
2707 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
2709 case RTE_FLOW_ITEM_TYPE_IPV6:
2710 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
2712 return rte_flow_error_set(error, EINVAL,
2713 RTE_FLOW_ERROR_TYPE_ACTION,
2714 (void *)items->type,
2715 "neither eth nor vlan"
2717 if (vlan && !vlan->eth_proto)
2718 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2719 else if (eth && !eth->ether_type)
2720 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
2721 if (!ipv6->vtc_flow)
2723 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
2724 if (!ipv6->hop_limits)
2725 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
2727 case RTE_FLOW_ITEM_TYPE_UDP:
2728 udp = (struct rte_udp_hdr *)&buf[temp_size];
2730 return rte_flow_error_set(error, EINVAL,
2731 RTE_FLOW_ERROR_TYPE_ACTION,
2732 (void *)items->type,
2733 "ip header not found");
2734 if (ipv4 && !ipv4->next_proto_id)
2735 ipv4->next_proto_id = IPPROTO_UDP;
2736 else if (ipv6 && !ipv6->proto)
2737 ipv6->proto = IPPROTO_UDP;
2739 case RTE_FLOW_ITEM_TYPE_VXLAN:
2740 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
2742 return rte_flow_error_set(error, EINVAL,
2743 RTE_FLOW_ERROR_TYPE_ACTION,
2744 (void *)items->type,
2745 "udp header not found");
2747 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
2748 if (!vxlan->vx_flags)
2750 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
2752 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2753 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
2755 return rte_flow_error_set(error, EINVAL,
2756 RTE_FLOW_ERROR_TYPE_ACTION,
2757 (void *)items->type,
2758 "udp header not found");
2759 if (!vxlan_gpe->proto)
2760 return rte_flow_error_set(error, EINVAL,
2761 RTE_FLOW_ERROR_TYPE_ACTION,
2762 (void *)items->type,
2763 "next protocol not found");
2766 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
2767 if (!vxlan_gpe->vx_flags)
2768 vxlan_gpe->vx_flags =
2769 MLX5_ENCAP_VXLAN_GPE_FLAGS;
2771 case RTE_FLOW_ITEM_TYPE_GRE:
2772 case RTE_FLOW_ITEM_TYPE_NVGRE:
2773 gre = (struct rte_gre_hdr *)&buf[temp_size];
2775 return rte_flow_error_set(error, EINVAL,
2776 RTE_FLOW_ERROR_TYPE_ACTION,
2777 (void *)items->type,
2778 "next protocol not found");
2780 return rte_flow_error_set(error, EINVAL,
2781 RTE_FLOW_ERROR_TYPE_ACTION,
2782 (void *)items->type,
2783 "ip header not found");
2784 if (ipv4 && !ipv4->next_proto_id)
2785 ipv4->next_proto_id = IPPROTO_GRE;
2786 else if (ipv6 && !ipv6->proto)
2787 ipv6->proto = IPPROTO_GRE;
2789 case RTE_FLOW_ITEM_TYPE_VOID:
2792 return rte_flow_error_set(error, EINVAL,
2793 RTE_FLOW_ERROR_TYPE_ACTION,
2794 (void *)items->type,
2795 "unsupported item type");
2805 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
2807 struct rte_ether_hdr *eth = NULL;
2808 struct rte_vlan_hdr *vlan = NULL;
2809 struct rte_ipv6_hdr *ipv6 = NULL;
2810 struct rte_udp_hdr *udp = NULL;
2814 eth = (struct rte_ether_hdr *)data;
2815 next_hdr = (char *)(eth + 1);
2816 proto = RTE_BE16(eth->ether_type);
2819 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
2820 vlan = (struct rte_vlan_hdr *)next_hdr;
2821 proto = RTE_BE16(vlan->eth_proto);
2822 next_hdr += sizeof(struct rte_vlan_hdr);
2825 /* HW calculates IPv4 csum. no need to proceed */
2826 if (proto == RTE_ETHER_TYPE_IPV4)
2829 /* non IPv4/IPv6 header. not supported */
2830 if (proto != RTE_ETHER_TYPE_IPV6) {
2831 return rte_flow_error_set(error, ENOTSUP,
2832 RTE_FLOW_ERROR_TYPE_ACTION,
2833 NULL, "Cannot offload non IPv4/IPv6");
2836 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
2838 /* ignore non UDP */
2839 if (ipv6->proto != IPPROTO_UDP)
2842 udp = (struct rte_udp_hdr *)(ipv6 + 1);
2843 udp->dgram_cksum = 0;
2849 * Convert L2 encap action to DV specification.
2852 * Pointer to rte_eth_dev structure.
2854 * Pointer to action structure.
2855 * @param[in, out] dev_flow
2856 * Pointer to the mlx5_flow.
2857 * @param[in] transfer
2858 * Mark if the flow is E-Switch flow.
2860 * Pointer to the error structure.
2863 * 0 on success, a negative errno value otherwise and rte_errno is set.
2866 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
2867 const struct rte_flow_action *action,
2868 struct mlx5_flow *dev_flow,
2870 struct rte_flow_error *error)
2872 const struct rte_flow_item *encap_data;
2873 const struct rte_flow_action_raw_encap *raw_encap_data;
2874 struct mlx5_flow_dv_encap_decap_resource res = {
2876 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
2877 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2878 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
2881 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
2883 (const struct rte_flow_action_raw_encap *)action->conf;
2884 res.size = raw_encap_data->size;
2885 memcpy(res.buf, raw_encap_data->data, res.size);
2887 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
2889 ((const struct rte_flow_action_vxlan_encap *)
2890 action->conf)->definition;
2893 ((const struct rte_flow_action_nvgre_encap *)
2894 action->conf)->definition;
2895 if (flow_dv_convert_encap_data(encap_data, res.buf,
2899 if (flow_dv_zero_encap_udp_csum(res.buf, error))
2901 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2902 return rte_flow_error_set(error, EINVAL,
2903 RTE_FLOW_ERROR_TYPE_ACTION,
2904 NULL, "can't create L2 encap action");
2909 * Convert L2 decap action to DV specification.
2912 * Pointer to rte_eth_dev structure.
2913 * @param[in, out] dev_flow
2914 * Pointer to the mlx5_flow.
2915 * @param[in] transfer
2916 * Mark if the flow is E-Switch flow.
2918 * Pointer to the error structure.
2921 * 0 on success, a negative errno value otherwise and rte_errno is set.
2924 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
2925 struct mlx5_flow *dev_flow,
2927 struct rte_flow_error *error)
2929 struct mlx5_flow_dv_encap_decap_resource res = {
2932 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
2933 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
2934 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
2937 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2938 return rte_flow_error_set(error, EINVAL,
2939 RTE_FLOW_ERROR_TYPE_ACTION,
2940 NULL, "can't create L2 decap action");
2945 * Convert raw decap/encap (L3 tunnel) action to DV specification.
2948 * Pointer to rte_eth_dev structure.
2950 * Pointer to action structure.
2951 * @param[in, out] dev_flow
2952 * Pointer to the mlx5_flow.
2954 * Pointer to the flow attributes.
2956 * Pointer to the error structure.
2959 * 0 on success, a negative errno value otherwise and rte_errno is set.
2962 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
2963 const struct rte_flow_action *action,
2964 struct mlx5_flow *dev_flow,
2965 const struct rte_flow_attr *attr,
2966 struct rte_flow_error *error)
2968 const struct rte_flow_action_raw_encap *encap_data;
2969 struct mlx5_flow_dv_encap_decap_resource res;
2971 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
2972 res.size = encap_data->size;
2973 memcpy(res.buf, encap_data->data, res.size);
2974 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
2975 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
2976 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
2978 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
2980 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
2981 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
2982 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
2983 return rte_flow_error_set(error, EINVAL,
2984 RTE_FLOW_ERROR_TYPE_ACTION,
2985 NULL, "can't create encap action");
2990 * Create action push VLAN.
2993 * Pointer to rte_eth_dev structure.
2995 * Pointer to the flow attributes.
2997 * Pointer to the vlan to push to the Ethernet header.
2998 * @param[in, out] dev_flow
2999 * Pointer to the mlx5_flow.
3001 * Pointer to the error structure.
3004 * 0 on success, a negative errno value otherwise and rte_errno is set.
3007 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3008 const struct rte_flow_attr *attr,
3009 const struct rte_vlan_hdr *vlan,
3010 struct mlx5_flow *dev_flow,
3011 struct rte_flow_error *error)
3013 struct mlx5_flow_dv_push_vlan_action_resource res;
3016 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3019 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3021 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3022 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3023 return flow_dv_push_vlan_action_resource_register
3024 (dev, &res, dev_flow, error);
3028 * Validate the modify-header actions.
3030 * @param[in] action_flags
3031 * Holds the actions detected until now.
3033 * Pointer to the modify action.
3035 * Pointer to error structure.
3038 * 0 on success, a negative errno value otherwise and rte_errno is set.
3041 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3042 const struct rte_flow_action *action,
3043 struct rte_flow_error *error)
3045 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3046 return rte_flow_error_set(error, EINVAL,
3047 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3048 NULL, "action configuration not set");
3049 if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
3050 return rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3052 "can't have encap action before"
3058 * Validate the modify-header MAC address actions.
3060 * @param[in] action_flags
3061 * Holds the actions detected until now.
3063 * Pointer to the modify action.
3064 * @param[in] item_flags
3065 * Holds the items detected.
3067 * Pointer to error structure.
3070 * 0 on success, a negative errno value otherwise and rte_errno is set.
3073 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3074 const struct rte_flow_action *action,
3075 const uint64_t item_flags,
3076 struct rte_flow_error *error)
3080 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3082 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3083 return rte_flow_error_set(error, EINVAL,
3084 RTE_FLOW_ERROR_TYPE_ACTION,
3086 "no L2 item in pattern");
3092 * Validate the modify-header IPv4 address actions.
3094 * @param[in] action_flags
3095 * Holds the actions detected until now.
3097 * Pointer to the modify action.
3098 * @param[in] item_flags
3099 * Holds the items detected.
3101 * Pointer to error structure.
3104 * 0 on success, a negative errno value otherwise and rte_errno is set.
3107 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3108 const struct rte_flow_action *action,
3109 const uint64_t item_flags,
3110 struct rte_flow_error *error)
3114 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3116 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3117 return rte_flow_error_set(error, EINVAL,
3118 RTE_FLOW_ERROR_TYPE_ACTION,
3120 "no ipv4 item in pattern");
3126 * Validate the modify-header IPv6 address actions.
3128 * @param[in] action_flags
3129 * Holds the actions detected until now.
3131 * Pointer to the modify action.
3132 * @param[in] item_flags
3133 * Holds the items detected.
3135 * Pointer to error structure.
3138 * 0 on success, a negative errno value otherwise and rte_errno is set.
3141 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3142 const struct rte_flow_action *action,
3143 const uint64_t item_flags,
3144 struct rte_flow_error *error)
3148 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3150 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3151 return rte_flow_error_set(error, EINVAL,
3152 RTE_FLOW_ERROR_TYPE_ACTION,
3154 "no ipv6 item in pattern");
3160 * Validate the modify-header TP actions.
3162 * @param[in] action_flags
3163 * Holds the actions detected until now.
3165 * Pointer to the modify action.
3166 * @param[in] item_flags
3167 * Holds the items detected.
3169 * Pointer to error structure.
3172 * 0 on success, a negative errno value otherwise and rte_errno is set.
3175 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3176 const struct rte_flow_action *action,
3177 const uint64_t item_flags,
3178 struct rte_flow_error *error)
3182 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3184 if (!(item_flags & MLX5_FLOW_LAYER_L4))
3185 return rte_flow_error_set(error, EINVAL,
3186 RTE_FLOW_ERROR_TYPE_ACTION,
3187 NULL, "no transport layer "
3194 * Validate the modify-header actions of increment/decrement
3195 * TCP Sequence-number.
3197 * @param[in] action_flags
3198 * Holds the actions detected until now.
3200 * Pointer to the modify action.
3201 * @param[in] item_flags
3202 * Holds the items detected.
3204 * Pointer to error structure.
3207 * 0 on success, a negative errno value otherwise and rte_errno is set.
3210 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3211 const struct rte_flow_action *action,
3212 const uint64_t item_flags,
3213 struct rte_flow_error *error)
3217 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3219 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3220 return rte_flow_error_set(error, EINVAL,
3221 RTE_FLOW_ERROR_TYPE_ACTION,
3222 NULL, "no TCP item in"
3224 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3225 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3226 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3227 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3228 return rte_flow_error_set(error, EINVAL,
3229 RTE_FLOW_ERROR_TYPE_ACTION,
3231 "cannot decrease and increase"
3232 " TCP sequence number"
3233 " at the same time");
3239 * Validate the modify-header actions of increment/decrement
3240 * TCP Acknowledgment number.
3242 * @param[in] action_flags
3243 * Holds the actions detected until now.
3245 * Pointer to the modify action.
3246 * @param[in] item_flags
3247 * Holds the items detected.
3249 * Pointer to error structure.
3252 * 0 on success, a negative errno value otherwise and rte_errno is set.
3255 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3256 const struct rte_flow_action *action,
3257 const uint64_t item_flags,
3258 struct rte_flow_error *error)
3262 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3264 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP))
3265 return rte_flow_error_set(error, EINVAL,
3266 RTE_FLOW_ERROR_TYPE_ACTION,
3267 NULL, "no TCP item in"
3269 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3270 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3271 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3272 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3273 return rte_flow_error_set(error, EINVAL,
3274 RTE_FLOW_ERROR_TYPE_ACTION,
3276 "cannot decrease and increase"
3277 " TCP acknowledgment number"
3278 " at the same time");
3284 * Validate the modify-header TTL actions.
3286 * @param[in] action_flags
3287 * Holds the actions detected until now.
3289 * Pointer to the modify action.
3290 * @param[in] item_flags
3291 * Holds the items detected.
3293 * Pointer to error structure.
3296 * 0 on success, a negative errno value otherwise and rte_errno is set.
3299 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3300 const struct rte_flow_action *action,
3301 const uint64_t item_flags,
3302 struct rte_flow_error *error)
3306 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3308 if (!(item_flags & MLX5_FLOW_LAYER_L3))
3309 return rte_flow_error_set(error, EINVAL,
3310 RTE_FLOW_ERROR_TYPE_ACTION,
3312 "no IP protocol in pattern");
3318 * Validate jump action.
3321 * Pointer to the jump action.
3322 * @param[in] action_flags
3323 * Holds the actions detected until now.
3324 * @param[in] attributes
3325 * Pointer to flow attributes
3326 * @param[in] external
3327 * Action belongs to flow rule created by request external to PMD.
3329 * Pointer to error structure.
3332 * 0 on success, a negative errno value otherwise and rte_errno is set.
3335 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3336 uint64_t action_flags,
3337 const struct rte_flow_attr *attributes,
3338 bool external, struct rte_flow_error *error)
3340 uint32_t target_group, table;
3343 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3344 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3345 return rte_flow_error_set(error, EINVAL,
3346 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3347 "can't have 2 fate actions in"
3349 if (action_flags & MLX5_FLOW_ACTION_METER)
3350 return rte_flow_error_set(error, ENOTSUP,
3351 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3352 "jump with meter not support");
3354 return rte_flow_error_set(error, EINVAL,
3355 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3356 NULL, "action configuration not set");
3358 ((const struct rte_flow_action_jump *)action->conf)->group;
3359 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3363 if (attributes->group == target_group)
3364 return rte_flow_error_set(error, EINVAL,
3365 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3366 "target group must be other than"
3367 " the current flow group");
3372 * Validate the port_id action.
3375 * Pointer to rte_eth_dev structure.
3376 * @param[in] action_flags
3377 * Bit-fields that holds the actions detected until now.
3379 * Port_id RTE action structure.
3381 * Attributes of flow that includes this action.
3383 * Pointer to error structure.
3386 * 0 on success, a negative errno value otherwise and rte_errno is set.
3389 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3390 uint64_t action_flags,
3391 const struct rte_flow_action *action,
3392 const struct rte_flow_attr *attr,
3393 struct rte_flow_error *error)
3395 const struct rte_flow_action_port_id *port_id;
3396 struct mlx5_priv *act_priv;
3397 struct mlx5_priv *dev_priv;
3400 if (!attr->transfer)
3401 return rte_flow_error_set(error, ENOTSUP,
3402 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3404 "port id action is valid in transfer"
3406 if (!action || !action->conf)
3407 return rte_flow_error_set(error, ENOTSUP,
3408 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3410 "port id action parameters must be"
3412 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3413 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3414 return rte_flow_error_set(error, EINVAL,
3415 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3416 "can have only one fate actions in"
3418 dev_priv = mlx5_dev_to_eswitch_info(dev);
3420 return rte_flow_error_set(error, rte_errno,
3421 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3423 "failed to obtain E-Switch info");
3424 port_id = action->conf;
3425 port = port_id->original ? dev->data->port_id : port_id->id;
3426 act_priv = mlx5_port_to_eswitch_info(port, false);
3428 return rte_flow_error_set
3430 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3431 "failed to obtain E-Switch port id for port");
3432 if (act_priv->domain_id != dev_priv->domain_id)
3433 return rte_flow_error_set
3435 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3436 "port does not belong to"
3437 " E-Switch being configured");
3442 * Get the maximum number of modify header actions.
3445 * Pointer to rte_eth_dev structure.
3447 * Flags bits to check if root level.
3450 * Max number of modify header actions device can support.
3453 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev, uint64_t flags)
3456 * There's no way to directly query the max cap. Although it has to be
3457 * acquried by iterative trial, it is a safe assumption that more
3458 * actions are supported by FW if extensive metadata register is
3459 * supported. (Only in the root table)
3461 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3462 return MLX5_MAX_MODIFY_NUM;
3464 return mlx5_flow_ext_mreg_supported(dev) ?
3465 MLX5_ROOT_TBL_MODIFY_NUM :
3466 MLX5_ROOT_TBL_MODIFY_NUM_NO_MREG;
3470 * Validate the meter action.
3473 * Pointer to rte_eth_dev structure.
3474 * @param[in] action_flags
3475 * Bit-fields that holds the actions detected until now.
3477 * Pointer to the meter action.
3479 * Attributes of flow that includes this action.
3481 * Pointer to error structure.
3484 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3487 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3488 uint64_t action_flags,
3489 const struct rte_flow_action *action,
3490 const struct rte_flow_attr *attr,
3491 struct rte_flow_error *error)
3493 struct mlx5_priv *priv = dev->data->dev_private;
3494 const struct rte_flow_action_meter *am = action->conf;
3495 struct mlx5_flow_meter *fm;
3498 return rte_flow_error_set(error, EINVAL,
3499 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3500 "meter action conf is NULL");
3502 if (action_flags & MLX5_FLOW_ACTION_METER)
3503 return rte_flow_error_set(error, ENOTSUP,
3504 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3505 "meter chaining not support");
3506 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3507 return rte_flow_error_set(error, ENOTSUP,
3508 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3509 "meter with jump not support");
3511 return rte_flow_error_set(error, ENOTSUP,
3512 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3514 "meter action not supported");
3515 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3517 return rte_flow_error_set(error, EINVAL,
3518 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3520 if (fm->ref_cnt && (!(fm->attr.transfer == attr->transfer ||
3521 (!fm->attr.ingress && !attr->ingress && attr->egress) ||
3522 (!fm->attr.egress && !attr->egress && attr->ingress))))
3523 return rte_flow_error_set(error, EINVAL,
3524 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3525 "Flow attributes are either invalid "
3526 "or have a conflict with current "
3527 "meter attributes");
3532 * Validate the modify-header IPv4 DSCP actions.
3534 * @param[in] action_flags
3535 * Holds the actions detected until now.
3537 * Pointer to the modify action.
3538 * @param[in] item_flags
3539 * Holds the items detected.
3541 * Pointer to error structure.
3544 * 0 on success, a negative errno value otherwise and rte_errno is set.
3547 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3548 const struct rte_flow_action *action,
3549 const uint64_t item_flags,
3550 struct rte_flow_error *error)
3554 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3556 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3557 return rte_flow_error_set(error, EINVAL,
3558 RTE_FLOW_ERROR_TYPE_ACTION,
3560 "no ipv4 item in pattern");
3566 * Validate the modify-header IPv6 DSCP actions.
3568 * @param[in] action_flags
3569 * Holds the actions detected until now.
3571 * Pointer to the modify action.
3572 * @param[in] item_flags
3573 * Holds the items detected.
3575 * Pointer to error structure.
3578 * 0 on success, a negative errno value otherwise and rte_errno is set.
3581 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3582 const struct rte_flow_action *action,
3583 const uint64_t item_flags,
3584 struct rte_flow_error *error)
3588 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3590 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3591 return rte_flow_error_set(error, EINVAL,
3592 RTE_FLOW_ERROR_TYPE_ACTION,
3594 "no ipv6 item in pattern");
3600 * Find existing modify-header resource or create and register a new one.
3602 * @param dev[in, out]
3603 * Pointer to rte_eth_dev structure.
3604 * @param[in, out] resource
3605 * Pointer to modify-header resource.
3606 * @parm[in, out] dev_flow
3607 * Pointer to the dev_flow.
3609 * pointer to error structure.
3612 * 0 on success otherwise -errno and errno is set.
3615 flow_dv_modify_hdr_resource_register
3616 (struct rte_eth_dev *dev,
3617 struct mlx5_flow_dv_modify_hdr_resource *resource,
3618 struct mlx5_flow *dev_flow,
3619 struct rte_flow_error *error)
3621 struct mlx5_priv *priv = dev->data->dev_private;
3622 struct mlx5_ibv_shared *sh = priv->sh;
3623 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3624 struct mlx5dv_dr_domain *ns;
3625 uint32_t actions_len;
3628 dev_flow->group ? 0 : MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3629 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3631 return rte_flow_error_set(error, EOVERFLOW,
3632 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3633 "too many modify header items");
3634 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3635 ns = sh->fdb_domain;
3636 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
3640 /* Lookup a matching resource from cache. */
3641 actions_len = resource->actions_num * sizeof(resource->actions[0]);
3642 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
3643 if (resource->ft_type == cache_resource->ft_type &&
3644 resource->actions_num == cache_resource->actions_num &&
3645 resource->flags == cache_resource->flags &&
3646 !memcmp((const void *)resource->actions,
3647 (const void *)cache_resource->actions,
3649 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
3650 (void *)cache_resource,
3651 rte_atomic32_read(&cache_resource->refcnt));
3652 rte_atomic32_inc(&cache_resource->refcnt);
3653 dev_flow->dv.modify_hdr = cache_resource;
3657 /* Register new modify-header resource. */
3658 cache_resource = rte_calloc(__func__, 1,
3659 sizeof(*cache_resource) + actions_len, 0);
3660 if (!cache_resource)
3661 return rte_flow_error_set(error, ENOMEM,
3662 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3663 "cannot allocate resource memory");
3664 *cache_resource = *resource;
3665 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
3666 cache_resource->verbs_action =
3667 mlx5_glue->dv_create_flow_action_modify_header
3668 (sh->ctx, cache_resource->ft_type, ns,
3669 cache_resource->flags, actions_len,
3670 (uint64_t *)cache_resource->actions);
3671 if (!cache_resource->verbs_action) {
3672 rte_free(cache_resource);
3673 return rte_flow_error_set(error, ENOMEM,
3674 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3675 NULL, "cannot create action");
3677 rte_atomic32_init(&cache_resource->refcnt);
3678 rte_atomic32_inc(&cache_resource->refcnt);
3679 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
3680 dev_flow->dv.modify_hdr = cache_resource;
3681 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
3682 (void *)cache_resource,
3683 rte_atomic32_read(&cache_resource->refcnt));
3687 #define MLX5_CNT_CONTAINER_RESIZE 64
3690 * Get or create a flow counter.
3693 * Pointer to the Ethernet device structure.
3695 * Indicate if this counter is shared with other flows.
3697 * Counter identifier.
3700 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
3702 static struct mlx5_flow_counter *
3703 flow_dv_counter_alloc_fallback(struct rte_eth_dev *dev, uint32_t shared,
3706 struct mlx5_priv *priv = dev->data->dev_private;
3707 struct mlx5_flow_counter *cnt = NULL;
3708 struct mlx5_devx_obj *dcs = NULL;
3710 if (!priv->config.devx) {
3711 rte_errno = ENOTSUP;
3715 TAILQ_FOREACH(cnt, &priv->sh->cmng.flow_counters, next) {
3716 if (cnt->shared && cnt->id == id) {
3722 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
3725 cnt = rte_calloc(__func__, 1, sizeof(*cnt), 0);
3727 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3731 struct mlx5_flow_counter tmpl = {
3737 tmpl.action = mlx5_glue->dv_create_flow_action_counter(dcs->obj, 0);
3739 claim_zero(mlx5_devx_cmd_destroy(cnt->dcs));
3745 TAILQ_INSERT_HEAD(&priv->sh->cmng.flow_counters, cnt, next);
3750 * Release a flow counter.
3753 * Pointer to the Ethernet device structure.
3754 * @param[in] counter
3755 * Pointer to the counter handler.
3758 flow_dv_counter_release_fallback(struct rte_eth_dev *dev,
3759 struct mlx5_flow_counter *counter)
3761 struct mlx5_priv *priv = dev->data->dev_private;
3765 if (--counter->ref_cnt == 0) {
3766 TAILQ_REMOVE(&priv->sh->cmng.flow_counters, counter, next);
3767 claim_zero(mlx5_devx_cmd_destroy(counter->dcs));
3773 * Query a devx flow counter.
3776 * Pointer to the Ethernet device structure.
3778 * Pointer to the flow counter.
3780 * The statistics value of packets.
3782 * The statistics value of bytes.
3785 * 0 on success, otherwise a negative errno value and rte_errno is set.
3788 _flow_dv_query_count_fallback(struct rte_eth_dev *dev __rte_unused,
3789 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3792 return mlx5_devx_cmd_flow_counter_query(cnt->dcs, 0, 0, pkts, bytes,
3797 * Get a pool by a counter.
3800 * Pointer to the counter.
3805 static struct mlx5_flow_counter_pool *
3806 flow_dv_counter_pool_get(struct mlx5_flow_counter *cnt)
3809 cnt -= cnt->dcs->id % MLX5_COUNTERS_PER_POOL;
3810 return (struct mlx5_flow_counter_pool *)cnt - 1;
3816 * Get a pool by devx counter ID.
3819 * Pointer to the counter container.
3821 * The counter devx ID.
3824 * The counter pool pointer if exists, NULL otherwise,
3826 static struct mlx5_flow_counter_pool *
3827 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
3829 struct mlx5_flow_counter_pool *pool;
3831 TAILQ_FOREACH(pool, &cont->pool_list, next) {
3832 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
3833 MLX5_COUNTERS_PER_POOL;
3835 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
3842 * Allocate a new memory for the counter values wrapped by all the needed
3846 * Pointer to the Ethernet device structure.
3848 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
3851 * The new memory management pointer on success, otherwise NULL and rte_errno
3854 static struct mlx5_counter_stats_mem_mng *
3855 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
3857 struct mlx5_ibv_shared *sh = ((struct mlx5_priv *)
3858 (dev->data->dev_private))->sh;
3859 struct mlx5_devx_mkey_attr mkey_attr;
3860 struct mlx5_counter_stats_mem_mng *mem_mng;
3861 volatile struct flow_counter_stats *raw_data;
3862 int size = (sizeof(struct flow_counter_stats) *
3863 MLX5_COUNTERS_PER_POOL +
3864 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
3865 sizeof(struct mlx5_counter_stats_mem_mng);
3866 uint8_t *mem = rte_calloc(__func__, 1, size, sysconf(_SC_PAGESIZE));
3873 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
3874 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
3875 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
3876 IBV_ACCESS_LOCAL_WRITE);
3877 if (!mem_mng->umem) {
3882 mkey_attr.addr = (uintptr_t)mem;
3883 mkey_attr.size = size;
3884 mkey_attr.umem_id = mem_mng->umem->umem_id;
3885 mkey_attr.pd = sh->pdn;
3886 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
3888 mlx5_glue->devx_umem_dereg(mem_mng->umem);
3893 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
3894 raw_data = (volatile struct flow_counter_stats *)mem;
3895 for (i = 0; i < raws_n; ++i) {
3896 mem_mng->raws[i].mem_mng = mem_mng;
3897 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
3899 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
3904 * Resize a counter container.
3907 * Pointer to the Ethernet device structure.
3909 * Whether the pool is for counter that was allocated by batch command.
3912 * The new container pointer on success, otherwise NULL and rte_errno is set.
3914 static struct mlx5_pools_container *
3915 flow_dv_container_resize(struct rte_eth_dev *dev, uint32_t batch)
3917 struct mlx5_priv *priv = dev->data->dev_private;
3918 struct mlx5_pools_container *cont =
3919 MLX5_CNT_CONTAINER(priv->sh, batch, 0);
3920 struct mlx5_pools_container *new_cont =
3921 MLX5_CNT_CONTAINER_UNUSED(priv->sh, batch, 0);
3922 struct mlx5_counter_stats_mem_mng *mem_mng;
3923 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
3924 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
3927 if (cont != MLX5_CNT_CONTAINER(priv->sh, batch, 1)) {
3928 /* The last resize still hasn't detected by the host thread. */
3932 new_cont->pools = rte_calloc(__func__, 1, mem_size, 0);
3933 if (!new_cont->pools) {
3938 memcpy(new_cont->pools, cont->pools, cont->n *
3939 sizeof(struct mlx5_flow_counter_pool *));
3940 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
3941 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
3943 rte_free(new_cont->pools);
3946 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
3947 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
3948 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE +
3950 new_cont->n = resize;
3951 rte_atomic16_set(&new_cont->n_valid, rte_atomic16_read(&cont->n_valid));
3952 TAILQ_INIT(&new_cont->pool_list);
3953 TAILQ_CONCAT(&new_cont->pool_list, &cont->pool_list, next);
3954 new_cont->init_mem_mng = mem_mng;
3956 /* Flip the master container. */
3957 priv->sh->cmng.mhi[batch] ^= (uint8_t)1;
3962 * Query a devx flow counter.
3965 * Pointer to the Ethernet device structure.
3967 * Pointer to the flow counter.
3969 * The statistics value of packets.
3971 * The statistics value of bytes.
3974 * 0 on success, otherwise a negative errno value and rte_errno is set.
3977 _flow_dv_query_count(struct rte_eth_dev *dev,
3978 struct mlx5_flow_counter *cnt, uint64_t *pkts,
3981 struct mlx5_priv *priv = dev->data->dev_private;
3982 struct mlx5_flow_counter_pool *pool =
3983 flow_dv_counter_pool_get(cnt);
3984 int offset = cnt - &pool->counters_raw[0];
3986 if (priv->counter_fallback)
3987 return _flow_dv_query_count_fallback(dev, cnt, pkts, bytes);
3989 rte_spinlock_lock(&pool->sl);
3991 * The single counters allocation may allocate smaller ID than the
3992 * current allocated in parallel to the host reading.
3993 * In this case the new counter values must be reported as 0.
3995 if (unlikely(!cnt->batch && cnt->dcs->id < pool->raw->min_dcs_id)) {
3999 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4000 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4002 rte_spinlock_unlock(&pool->sl);
4007 * Create and initialize a new counter pool.
4010 * Pointer to the Ethernet device structure.
4012 * The devX counter handle.
4014 * Whether the pool is for counter that was allocated by batch command.
4017 * A new pool pointer on success, NULL otherwise and rte_errno is set.
4019 static struct mlx5_flow_counter_pool *
4020 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4023 struct mlx5_priv *priv = dev->data->dev_private;
4024 struct mlx5_flow_counter_pool *pool;
4025 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4027 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4030 if (cont->n == n_valid) {
4031 cont = flow_dv_container_resize(dev, batch);
4035 size = sizeof(*pool) + MLX5_COUNTERS_PER_POOL *
4036 sizeof(struct mlx5_flow_counter);
4037 pool = rte_calloc(__func__, 1, size, 0);
4042 pool->min_dcs = dcs;
4043 pool->raw = cont->init_mem_mng->raws + n_valid %
4044 MLX5_CNT_CONTAINER_RESIZE;
4045 pool->raw_hw = NULL;
4046 rte_spinlock_init(&pool->sl);
4048 * The generation of the new allocated counters in this pool is 0, 2 in
4049 * the pool generation makes all the counters valid for allocation.
4051 rte_atomic64_set(&pool->query_gen, 0x2);
4052 TAILQ_INIT(&pool->counters);
4053 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4054 cont->pools[n_valid] = pool;
4055 /* Pool initialization must be updated before host thread access. */
4057 rte_atomic16_add(&cont->n_valid, 1);
4062 * Prepare a new counter and/or a new counter pool.
4065 * Pointer to the Ethernet device structure.
4066 * @param[out] cnt_free
4067 * Where to put the pointer of a new counter.
4069 * Whether the pool is for counter that was allocated by batch command.
4072 * The free counter pool pointer and @p cnt_free is set on success,
4073 * NULL otherwise and rte_errno is set.
4075 static struct mlx5_flow_counter_pool *
4076 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4077 struct mlx5_flow_counter **cnt_free,
4080 struct mlx5_priv *priv = dev->data->dev_private;
4081 struct mlx5_flow_counter_pool *pool;
4082 struct mlx5_devx_obj *dcs = NULL;
4083 struct mlx5_flow_counter *cnt;
4087 /* bulk_bitmap must be 0 for single counter allocation. */
4088 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4091 pool = flow_dv_find_pool_by_id
4092 (MLX5_CNT_CONTAINER(priv->sh, batch, 0), dcs->id);
4094 pool = flow_dv_pool_create(dev, dcs, batch);
4096 mlx5_devx_cmd_destroy(dcs);
4099 } else if (dcs->id < pool->min_dcs->id) {
4100 rte_atomic64_set(&pool->a64_dcs,
4101 (int64_t)(uintptr_t)dcs);
4103 cnt = &pool->counters_raw[dcs->id % MLX5_COUNTERS_PER_POOL];
4104 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4109 /* bulk_bitmap is in 128 counters units. */
4110 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4111 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4113 rte_errno = ENODATA;
4116 pool = flow_dv_pool_create(dev, dcs, batch);
4118 mlx5_devx_cmd_destroy(dcs);
4121 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4122 cnt = &pool->counters_raw[i];
4124 TAILQ_INSERT_HEAD(&pool->counters, cnt, next);
4126 *cnt_free = &pool->counters_raw[0];
4131 * Search for existed shared counter.
4134 * Pointer to the relevant counter pool container.
4136 * The shared counter ID to search.
4139 * NULL if not existed, otherwise pointer to the shared counter.
4141 static struct mlx5_flow_counter *
4142 flow_dv_counter_shared_search(struct mlx5_pools_container *cont,
4145 static struct mlx5_flow_counter *cnt;
4146 struct mlx5_flow_counter_pool *pool;
4149 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4150 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) {
4151 cnt = &pool->counters_raw[i];
4152 if (cnt->ref_cnt && cnt->shared && cnt->id == id)
4160 * Allocate a flow counter.
4163 * Pointer to the Ethernet device structure.
4165 * Indicate if this counter is shared with other flows.
4167 * Counter identifier.
4169 * Counter flow group.
4172 * pointer to flow counter on success, NULL otherwise and rte_errno is set.
4174 static struct mlx5_flow_counter *
4175 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4178 struct mlx5_priv *priv = dev->data->dev_private;
4179 struct mlx5_flow_counter_pool *pool = NULL;
4180 struct mlx5_flow_counter *cnt_free = NULL;
4182 * Currently group 0 flow counter cannot be assigned to a flow if it is
4183 * not the first one in the batch counter allocation, so it is better
4184 * to allocate counters one by one for these flows in a separate
4186 * A counter can be shared between different groups so need to take
4187 * shared counters from the single container.
4189 uint32_t batch = (group && !shared) ? 1 : 0;
4190 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4193 if (priv->counter_fallback)
4194 return flow_dv_counter_alloc_fallback(dev, shared, id);
4195 if (!priv->config.devx) {
4196 rte_errno = ENOTSUP;
4200 cnt_free = flow_dv_counter_shared_search(cont, id);
4202 if (cnt_free->ref_cnt + 1 == 0) {
4206 cnt_free->ref_cnt++;
4210 /* Pools which has a free counters are in the start. */
4211 TAILQ_FOREACH(pool, &cont->pool_list, next) {
4213 * The free counter reset values must be updated between the
4214 * counter release to the counter allocation, so, at least one
4215 * query must be done in this time. ensure it by saving the
4216 * query generation in the release time.
4217 * The free list is sorted according to the generation - so if
4218 * the first one is not updated, all the others are not
4221 cnt_free = TAILQ_FIRST(&pool->counters);
4222 if (cnt_free && cnt_free->query_gen + 1 <
4223 rte_atomic64_read(&pool->query_gen))
4228 pool = flow_dv_counter_pool_prepare(dev, &cnt_free, batch);
4232 cnt_free->batch = batch;
4233 /* Create a DV counter action only in the first time usage. */
4234 if (!cnt_free->action) {
4236 struct mlx5_devx_obj *dcs;
4239 offset = cnt_free - &pool->counters_raw[0];
4240 dcs = pool->min_dcs;
4243 dcs = cnt_free->dcs;
4245 cnt_free->action = mlx5_glue->dv_create_flow_action_counter
4247 if (!cnt_free->action) {
4252 /* Update the counter reset values. */
4253 if (_flow_dv_query_count(dev, cnt_free, &cnt_free->hits,
4256 cnt_free->shared = shared;
4257 cnt_free->ref_cnt = 1;
4259 if (!priv->sh->cmng.query_thread_on)
4260 /* Start the asynchronous batch query by the host thread. */
4261 mlx5_set_query_alarm(priv->sh);
4262 TAILQ_REMOVE(&pool->counters, cnt_free, next);
4263 if (TAILQ_EMPTY(&pool->counters)) {
4264 /* Move the pool to the end of the container pool list. */
4265 TAILQ_REMOVE(&cont->pool_list, pool, next);
4266 TAILQ_INSERT_TAIL(&cont->pool_list, pool, next);
4272 * Release a flow counter.
4275 * Pointer to the Ethernet device structure.
4276 * @param[in] counter
4277 * Pointer to the counter handler.
4280 flow_dv_counter_release(struct rte_eth_dev *dev,
4281 struct mlx5_flow_counter *counter)
4283 struct mlx5_priv *priv = dev->data->dev_private;
4287 if (priv->counter_fallback) {
4288 flow_dv_counter_release_fallback(dev, counter);
4291 if (--counter->ref_cnt == 0) {
4292 struct mlx5_flow_counter_pool *pool =
4293 flow_dv_counter_pool_get(counter);
4295 /* Put the counter in the end - the last updated one. */
4296 TAILQ_INSERT_TAIL(&pool->counters, counter, next);
4297 counter->query_gen = rte_atomic64_read(&pool->query_gen);
4302 * Verify the @p attributes will be correctly understood by the NIC and store
4303 * them in the @p flow if everything is correct.
4306 * Pointer to dev struct.
4307 * @param[in] attributes
4308 * Pointer to flow attributes
4309 * @param[in] external
4310 * This flow rule is created by request external to PMD.
4312 * Pointer to error structure.
4315 * 0 on success, a negative errno value otherwise and rte_errno is set.
4318 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4319 const struct rte_flow_attr *attributes,
4320 bool external __rte_unused,
4321 struct rte_flow_error *error)
4323 struct mlx5_priv *priv = dev->data->dev_private;
4324 uint32_t priority_max = priv->config.flow_prio - 1;
4326 #ifndef HAVE_MLX5DV_DR
4327 if (attributes->group)
4328 return rte_flow_error_set(error, ENOTSUP,
4329 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4331 "groups are not supported");
4336 ret = mlx5_flow_group_to_table(attributes, external,
4342 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4343 attributes->priority >= priority_max)
4344 return rte_flow_error_set(error, ENOTSUP,
4345 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4347 "priority out of range");
4348 if (attributes->transfer) {
4349 if (!priv->config.dv_esw_en)
4350 return rte_flow_error_set
4352 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4353 "E-Switch dr is not supported");
4354 if (!(priv->representor || priv->master))
4355 return rte_flow_error_set
4356 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4357 NULL, "E-Switch configuration can only be"
4358 " done by a master or a representor device");
4359 if (attributes->egress)
4360 return rte_flow_error_set
4362 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4363 "egress is not supported");
4365 if (!(attributes->egress ^ attributes->ingress))
4366 return rte_flow_error_set(error, ENOTSUP,
4367 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4368 "must specify exactly one of "
4369 "ingress or egress");
4374 * Internal validation function. For validating both actions and items.
4377 * Pointer to the rte_eth_dev structure.
4379 * Pointer to the flow attributes.
4381 * Pointer to the list of items.
4382 * @param[in] actions
4383 * Pointer to the list of actions.
4384 * @param[in] external
4385 * This flow rule is created by request external to PMD.
4387 * Pointer to the error structure.
4390 * 0 on success, a negative errno value otherwise and rte_errno is set.
4393 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4394 const struct rte_flow_item items[],
4395 const struct rte_flow_action actions[],
4396 bool external, struct rte_flow_error *error)
4399 uint64_t action_flags = 0;
4400 uint64_t item_flags = 0;
4401 uint64_t last_item = 0;
4402 uint8_t next_protocol = 0xff;
4403 uint16_t ether_type = 0;
4405 uint8_t item_ipv6_proto = 0;
4406 const struct rte_flow_item *gre_item = NULL;
4407 struct rte_flow_item_tcp nic_tcp_mask = {
4410 .src_port = RTE_BE16(UINT16_MAX),
4411 .dst_port = RTE_BE16(UINT16_MAX),
4414 struct mlx5_priv *priv = dev->data->dev_private;
4415 struct mlx5_dev_config *dev_conf = &priv->config;
4419 ret = flow_dv_validate_attributes(dev, attr, external, error);
4422 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4423 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4424 int type = items->type;
4427 case RTE_FLOW_ITEM_TYPE_VOID:
4429 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4430 ret = flow_dv_validate_item_port_id
4431 (dev, items, attr, item_flags, error);
4434 last_item = MLX5_FLOW_ITEM_PORT_ID;
4436 case RTE_FLOW_ITEM_TYPE_ETH:
4437 ret = mlx5_flow_validate_item_eth(items, item_flags,
4441 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4442 MLX5_FLOW_LAYER_OUTER_L2;
4443 if (items->mask != NULL && items->spec != NULL) {
4445 ((const struct rte_flow_item_eth *)
4448 ((const struct rte_flow_item_eth *)
4450 ether_type = rte_be_to_cpu_16(ether_type);
4455 case RTE_FLOW_ITEM_TYPE_VLAN:
4456 ret = mlx5_flow_validate_item_vlan(items, item_flags,
4460 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4461 MLX5_FLOW_LAYER_OUTER_VLAN;
4462 if (items->mask != NULL && items->spec != NULL) {
4464 ((const struct rte_flow_item_vlan *)
4465 items->spec)->inner_type;
4467 ((const struct rte_flow_item_vlan *)
4468 items->mask)->inner_type;
4469 ether_type = rte_be_to_cpu_16(ether_type);
4474 case RTE_FLOW_ITEM_TYPE_IPV4:
4475 mlx5_flow_tunnel_ip_check(items, next_protocol,
4476 &item_flags, &tunnel);
4477 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
4483 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4484 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4485 if (items->mask != NULL &&
4486 ((const struct rte_flow_item_ipv4 *)
4487 items->mask)->hdr.next_proto_id) {
4489 ((const struct rte_flow_item_ipv4 *)
4490 (items->spec))->hdr.next_proto_id;
4492 ((const struct rte_flow_item_ipv4 *)
4493 (items->mask))->hdr.next_proto_id;
4495 /* Reset for inner layer. */
4496 next_protocol = 0xff;
4499 case RTE_FLOW_ITEM_TYPE_IPV6:
4500 mlx5_flow_tunnel_ip_check(items, next_protocol,
4501 &item_flags, &tunnel);
4502 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
4508 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4509 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4510 if (items->mask != NULL &&
4511 ((const struct rte_flow_item_ipv6 *)
4512 items->mask)->hdr.proto) {
4514 ((const struct rte_flow_item_ipv6 *)
4515 items->spec)->hdr.proto;
4517 ((const struct rte_flow_item_ipv6 *)
4518 items->spec)->hdr.proto;
4520 ((const struct rte_flow_item_ipv6 *)
4521 items->mask)->hdr.proto;
4523 /* Reset for inner layer. */
4524 next_protocol = 0xff;
4527 case RTE_FLOW_ITEM_TYPE_TCP:
4528 ret = mlx5_flow_validate_item_tcp
4535 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
4536 MLX5_FLOW_LAYER_OUTER_L4_TCP;
4538 case RTE_FLOW_ITEM_TYPE_UDP:
4539 ret = mlx5_flow_validate_item_udp(items, item_flags,
4544 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
4545 MLX5_FLOW_LAYER_OUTER_L4_UDP;
4547 case RTE_FLOW_ITEM_TYPE_GRE:
4548 ret = mlx5_flow_validate_item_gre(items, item_flags,
4549 next_protocol, error);
4553 last_item = MLX5_FLOW_LAYER_GRE;
4555 case RTE_FLOW_ITEM_TYPE_NVGRE:
4556 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
4561 last_item = MLX5_FLOW_LAYER_NVGRE;
4563 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
4564 ret = mlx5_flow_validate_item_gre_key
4565 (items, item_flags, gre_item, error);
4568 last_item = MLX5_FLOW_LAYER_GRE_KEY;
4570 case RTE_FLOW_ITEM_TYPE_VXLAN:
4571 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
4575 last_item = MLX5_FLOW_LAYER_VXLAN;
4577 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
4578 ret = mlx5_flow_validate_item_vxlan_gpe(items,
4583 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
4585 case RTE_FLOW_ITEM_TYPE_GENEVE:
4586 ret = mlx5_flow_validate_item_geneve(items,
4591 last_item = MLX5_FLOW_LAYER_GENEVE;
4593 case RTE_FLOW_ITEM_TYPE_MPLS:
4594 ret = mlx5_flow_validate_item_mpls(dev, items,
4599 last_item = MLX5_FLOW_LAYER_MPLS;
4602 case RTE_FLOW_ITEM_TYPE_MARK:
4603 ret = flow_dv_validate_item_mark(dev, items, attr,
4607 last_item = MLX5_FLOW_ITEM_MARK;
4609 case RTE_FLOW_ITEM_TYPE_META:
4610 ret = flow_dv_validate_item_meta(dev, items, attr,
4614 last_item = MLX5_FLOW_ITEM_METADATA;
4616 case RTE_FLOW_ITEM_TYPE_ICMP:
4617 ret = mlx5_flow_validate_item_icmp(items, item_flags,
4622 last_item = MLX5_FLOW_LAYER_ICMP;
4624 case RTE_FLOW_ITEM_TYPE_ICMP6:
4625 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
4630 last_item = MLX5_FLOW_LAYER_ICMP6;
4632 case RTE_FLOW_ITEM_TYPE_TAG:
4633 ret = flow_dv_validate_item_tag(dev, items,
4637 last_item = MLX5_FLOW_ITEM_TAG;
4639 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
4640 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
4642 case RTE_FLOW_ITEM_TYPE_GTP:
4643 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
4647 last_item = MLX5_FLOW_LAYER_GTP;
4650 return rte_flow_error_set(error, ENOTSUP,
4651 RTE_FLOW_ERROR_TYPE_ITEM,
4652 NULL, "item not supported");
4654 item_flags |= last_item;
4656 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
4657 int type = actions->type;
4658 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
4659 return rte_flow_error_set(error, ENOTSUP,
4660 RTE_FLOW_ERROR_TYPE_ACTION,
4661 actions, "too many actions");
4663 case RTE_FLOW_ACTION_TYPE_VOID:
4665 case RTE_FLOW_ACTION_TYPE_PORT_ID:
4666 ret = flow_dv_validate_action_port_id(dev,
4673 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
4676 case RTE_FLOW_ACTION_TYPE_FLAG:
4677 ret = flow_dv_validate_action_flag(dev, action_flags,
4681 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4682 /* Count all modify-header actions as one. */
4683 if (!(action_flags &
4684 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4686 action_flags |= MLX5_FLOW_ACTION_FLAG |
4687 MLX5_FLOW_ACTION_MARK_EXT;
4689 action_flags |= MLX5_FLOW_ACTION_FLAG;
4693 case RTE_FLOW_ACTION_TYPE_MARK:
4694 ret = flow_dv_validate_action_mark(dev, actions,
4699 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
4700 /* Count all modify-header actions as one. */
4701 if (!(action_flags &
4702 MLX5_FLOW_MODIFY_HDR_ACTIONS))
4704 action_flags |= MLX5_FLOW_ACTION_MARK |
4705 MLX5_FLOW_ACTION_MARK_EXT;
4707 action_flags |= MLX5_FLOW_ACTION_MARK;
4711 case RTE_FLOW_ACTION_TYPE_SET_META:
4712 ret = flow_dv_validate_action_set_meta(dev, actions,
4717 /* Count all modify-header actions as one action. */
4718 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4720 action_flags |= MLX5_FLOW_ACTION_SET_META;
4722 case RTE_FLOW_ACTION_TYPE_SET_TAG:
4723 ret = flow_dv_validate_action_set_tag(dev, actions,
4728 /* Count all modify-header actions as one action. */
4729 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4731 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
4733 case RTE_FLOW_ACTION_TYPE_DROP:
4734 ret = mlx5_flow_validate_action_drop(action_flags,
4738 action_flags |= MLX5_FLOW_ACTION_DROP;
4741 case RTE_FLOW_ACTION_TYPE_QUEUE:
4742 ret = mlx5_flow_validate_action_queue(actions,
4747 action_flags |= MLX5_FLOW_ACTION_QUEUE;
4750 case RTE_FLOW_ACTION_TYPE_RSS:
4751 ret = mlx5_flow_validate_action_rss(actions,
4757 action_flags |= MLX5_FLOW_ACTION_RSS;
4760 case RTE_FLOW_ACTION_TYPE_COUNT:
4761 ret = flow_dv_validate_action_count(dev, error);
4764 action_flags |= MLX5_FLOW_ACTION_COUNT;
4767 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
4768 if (flow_dv_validate_action_pop_vlan(dev,
4774 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
4777 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
4778 ret = flow_dv_validate_action_push_vlan(action_flags,
4784 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
4787 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
4788 ret = flow_dv_validate_action_set_vlan_pcp
4789 (action_flags, actions, error);
4792 /* Count PCP with push_vlan command. */
4793 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
4795 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
4796 ret = flow_dv_validate_action_set_vlan_vid
4797 (item_flags, action_flags,
4801 /* Count VID with push_vlan command. */
4802 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
4804 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
4805 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
4806 ret = flow_dv_validate_action_l2_encap(action_flags,
4811 action_flags |= actions->type ==
4812 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
4813 MLX5_FLOW_ACTION_VXLAN_ENCAP :
4814 MLX5_FLOW_ACTION_NVGRE_ENCAP;
4817 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
4818 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
4819 ret = flow_dv_validate_action_l2_decap(action_flags,
4823 action_flags |= actions->type ==
4824 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
4825 MLX5_FLOW_ACTION_VXLAN_DECAP :
4826 MLX5_FLOW_ACTION_NVGRE_DECAP;
4829 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
4830 ret = flow_dv_validate_action_raw_encap(action_flags,
4835 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
4838 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
4839 ret = flow_dv_validate_action_raw_decap(action_flags,
4844 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
4847 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
4848 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
4849 ret = flow_dv_validate_action_modify_mac(action_flags,
4855 /* Count all modify-header actions as one action. */
4856 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4858 action_flags |= actions->type ==
4859 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
4860 MLX5_FLOW_ACTION_SET_MAC_SRC :
4861 MLX5_FLOW_ACTION_SET_MAC_DST;
4864 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
4865 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
4866 ret = flow_dv_validate_action_modify_ipv4(action_flags,
4872 /* Count all modify-header actions as one action. */
4873 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4875 action_flags |= actions->type ==
4876 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
4877 MLX5_FLOW_ACTION_SET_IPV4_SRC :
4878 MLX5_FLOW_ACTION_SET_IPV4_DST;
4880 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
4881 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
4882 ret = flow_dv_validate_action_modify_ipv6(action_flags,
4888 if (item_ipv6_proto == IPPROTO_ICMPV6)
4889 return rte_flow_error_set(error, ENOTSUP,
4890 RTE_FLOW_ERROR_TYPE_ACTION,
4892 "Can't change header "
4893 "with ICMPv6 proto");
4894 /* Count all modify-header actions as one action. */
4895 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4897 action_flags |= actions->type ==
4898 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
4899 MLX5_FLOW_ACTION_SET_IPV6_SRC :
4900 MLX5_FLOW_ACTION_SET_IPV6_DST;
4902 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
4903 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
4904 ret = flow_dv_validate_action_modify_tp(action_flags,
4910 /* Count all modify-header actions as one action. */
4911 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4913 action_flags |= actions->type ==
4914 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
4915 MLX5_FLOW_ACTION_SET_TP_SRC :
4916 MLX5_FLOW_ACTION_SET_TP_DST;
4918 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
4919 case RTE_FLOW_ACTION_TYPE_SET_TTL:
4920 ret = flow_dv_validate_action_modify_ttl(action_flags,
4926 /* Count all modify-header actions as one action. */
4927 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4929 action_flags |= actions->type ==
4930 RTE_FLOW_ACTION_TYPE_SET_TTL ?
4931 MLX5_FLOW_ACTION_SET_TTL :
4932 MLX5_FLOW_ACTION_DEC_TTL;
4934 case RTE_FLOW_ACTION_TYPE_JUMP:
4935 ret = flow_dv_validate_action_jump(actions,
4942 action_flags |= MLX5_FLOW_ACTION_JUMP;
4944 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
4945 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
4946 ret = flow_dv_validate_action_modify_tcp_seq
4953 /* Count all modify-header actions as one action. */
4954 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4956 action_flags |= actions->type ==
4957 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
4958 MLX5_FLOW_ACTION_INC_TCP_SEQ :
4959 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
4961 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
4962 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
4963 ret = flow_dv_validate_action_modify_tcp_ack
4970 /* Count all modify-header actions as one action. */
4971 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
4973 action_flags |= actions->type ==
4974 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
4975 MLX5_FLOW_ACTION_INC_TCP_ACK :
4976 MLX5_FLOW_ACTION_DEC_TCP_ACK;
4978 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
4979 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
4980 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
4982 case RTE_FLOW_ACTION_TYPE_METER:
4983 ret = mlx5_flow_validate_action_meter(dev,
4989 action_flags |= MLX5_FLOW_ACTION_METER;
4992 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
4993 ret = flow_dv_validate_action_modify_ipv4_dscp
5000 /* Count all modify-header actions as one action. */
5001 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5003 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5005 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5006 ret = flow_dv_validate_action_modify_ipv6_dscp
5013 /* Count all modify-header actions as one action. */
5014 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5016 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5019 return rte_flow_error_set(error, ENOTSUP,
5020 RTE_FLOW_ERROR_TYPE_ACTION,
5022 "action not supported");
5026 * Validate the drop action mutual exclusion with other actions.
5027 * Drop action is mutually-exclusive with any other action, except for
5030 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5031 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5032 return rte_flow_error_set(error, EINVAL,
5033 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5034 "Drop action is mutually-exclusive "
5035 "with any other action, except for "
5037 /* Eswitch has few restrictions on using items and actions */
5038 if (attr->transfer) {
5039 if (!mlx5_flow_ext_mreg_supported(dev) &&
5040 action_flags & MLX5_FLOW_ACTION_FLAG)
5041 return rte_flow_error_set(error, ENOTSUP,
5042 RTE_FLOW_ERROR_TYPE_ACTION,
5044 "unsupported action FLAG");
5045 if (!mlx5_flow_ext_mreg_supported(dev) &&
5046 action_flags & MLX5_FLOW_ACTION_MARK)
5047 return rte_flow_error_set(error, ENOTSUP,
5048 RTE_FLOW_ERROR_TYPE_ACTION,
5050 "unsupported action MARK");
5051 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5052 return rte_flow_error_set(error, ENOTSUP,
5053 RTE_FLOW_ERROR_TYPE_ACTION,
5055 "unsupported action QUEUE");
5056 if (action_flags & MLX5_FLOW_ACTION_RSS)
5057 return rte_flow_error_set(error, ENOTSUP,
5058 RTE_FLOW_ERROR_TYPE_ACTION,
5060 "unsupported action RSS");
5061 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5062 return rte_flow_error_set(error, EINVAL,
5063 RTE_FLOW_ERROR_TYPE_ACTION,
5065 "no fate action is found");
5067 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5068 return rte_flow_error_set(error, EINVAL,
5069 RTE_FLOW_ERROR_TYPE_ACTION,
5071 "no fate action is found");
5077 * Internal preparation function. Allocates the DV flow size,
5078 * this size is constant.
5081 * Pointer to the flow attributes.
5083 * Pointer to the list of items.
5084 * @param[in] actions
5085 * Pointer to the list of actions.
5087 * Pointer to the error structure.
5090 * Pointer to mlx5_flow object on success,
5091 * otherwise NULL and rte_errno is set.
5093 static struct mlx5_flow *
5094 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
5095 const struct rte_flow_item items[] __rte_unused,
5096 const struct rte_flow_action actions[] __rte_unused,
5097 struct rte_flow_error *error)
5099 size_t size = sizeof(struct mlx5_flow);
5100 struct mlx5_flow *dev_flow;
5102 dev_flow = rte_calloc(__func__, 1, size, 0);
5104 rte_flow_error_set(error, ENOMEM,
5105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5106 "not enough memory to create flow");
5109 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);
5110 dev_flow->ingress = attr->ingress;
5111 dev_flow->transfer = attr->transfer;
5117 * Sanity check for match mask and value. Similar to check_valid_spec() in
5118 * kernel driver. If unmasked bit is present in value, it returns failure.
5121 * pointer to match mask buffer.
5122 * @param match_value
5123 * pointer to match value buffer.
5126 * 0 if valid, -EINVAL otherwise.
5129 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5131 uint8_t *m = match_mask;
5132 uint8_t *v = match_value;
5135 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5138 "match_value differs from match_criteria"
5139 " %p[%u] != %p[%u]",
5140 match_value, i, match_mask, i);
5149 * Add Ethernet item to matcher and to the value.
5151 * @param[in, out] matcher
5153 * @param[in, out] key
5154 * Flow matcher value.
5156 * Flow pattern to translate.
5158 * Item is inner pattern.
5161 flow_dv_translate_item_eth(void *matcher, void *key,
5162 const struct rte_flow_item *item, int inner)
5164 const struct rte_flow_item_eth *eth_m = item->mask;
5165 const struct rte_flow_item_eth *eth_v = item->spec;
5166 const struct rte_flow_item_eth nic_mask = {
5167 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5168 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5169 .type = RTE_BE16(0xffff),
5181 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5183 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5185 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5187 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5189 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5190 ð_m->dst, sizeof(eth_m->dst));
5191 /* The value must be in the range of the mask. */
5192 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5193 for (i = 0; i < sizeof(eth_m->dst); ++i)
5194 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5195 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5196 ð_m->src, sizeof(eth_m->src));
5197 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5198 /* The value must be in the range of the mask. */
5199 for (i = 0; i < sizeof(eth_m->dst); ++i)
5200 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5201 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5202 rte_be_to_cpu_16(eth_m->type));
5203 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
5204 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5208 * Add VLAN item to matcher and to the value.
5210 * @param[in, out] dev_flow
5212 * @param[in, out] matcher
5214 * @param[in, out] key
5215 * Flow matcher value.
5217 * Flow pattern to translate.
5219 * Item is inner pattern.
5222 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5223 void *matcher, void *key,
5224 const struct rte_flow_item *item,
5227 const struct rte_flow_item_vlan *vlan_m = item->mask;
5228 const struct rte_flow_item_vlan *vlan_v = item->spec;
5237 vlan_m = &rte_flow_item_vlan_mask;
5239 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5241 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5243 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5245 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5247 * This is workaround, masks are not supported,
5248 * and pre-validated.
5250 dev_flow->dv.vf_vlan.tag =
5251 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5253 tci_m = rte_be_to_cpu_16(vlan_m->tci);
5254 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
5255 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5256 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
5257 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
5258 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
5259 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
5260 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
5261 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
5262 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
5263 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5264 rte_be_to_cpu_16(vlan_m->inner_type));
5265 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
5266 rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
5270 * Add IPV4 item to matcher and to the value.
5272 * @param[in, out] matcher
5274 * @param[in, out] key
5275 * Flow matcher value.
5277 * Flow pattern to translate.
5279 * Item is inner pattern.
5281 * The group to insert the rule.
5284 flow_dv_translate_item_ipv4(void *matcher, void *key,
5285 const struct rte_flow_item *item,
5286 int inner, uint32_t group)
5288 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
5289 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
5290 const struct rte_flow_item_ipv4 nic_mask = {
5292 .src_addr = RTE_BE32(0xffffffff),
5293 .dst_addr = RTE_BE32(0xffffffff),
5294 .type_of_service = 0xff,
5295 .next_proto_id = 0xff,
5305 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5307 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5309 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5311 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5314 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5316 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x4);
5317 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
5322 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5323 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5324 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5325 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
5326 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
5327 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
5328 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5329 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5330 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5331 src_ipv4_src_ipv6.ipv4_layout.ipv4);
5332 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
5333 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
5334 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
5335 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
5336 ipv4_m->hdr.type_of_service);
5337 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
5338 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
5339 ipv4_m->hdr.type_of_service >> 2);
5340 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
5341 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5342 ipv4_m->hdr.next_proto_id);
5343 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5344 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
5348 * Add IPV6 item to matcher and to the value.
5350 * @param[in, out] matcher
5352 * @param[in, out] key
5353 * Flow matcher value.
5355 * Flow pattern to translate.
5357 * Item is inner pattern.
5359 * The group to insert the rule.
5362 flow_dv_translate_item_ipv6(void *matcher, void *key,
5363 const struct rte_flow_item *item,
5364 int inner, uint32_t group)
5366 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
5367 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
5368 const struct rte_flow_item_ipv6 nic_mask = {
5371 "\xff\xff\xff\xff\xff\xff\xff\xff"
5372 "\xff\xff\xff\xff\xff\xff\xff\xff",
5374 "\xff\xff\xff\xff\xff\xff\xff\xff"
5375 "\xff\xff\xff\xff\xff\xff\xff\xff",
5376 .vtc_flow = RTE_BE32(0xffffffff),
5383 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5384 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5393 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5395 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5397 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5399 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5402 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5404 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0x6);
5405 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
5410 size = sizeof(ipv6_m->hdr.dst_addr);
5411 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5412 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5413 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5414 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
5415 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
5416 for (i = 0; i < size; ++i)
5417 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
5418 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
5419 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5420 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5421 src_ipv4_src_ipv6.ipv6_layout.ipv6);
5422 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
5423 for (i = 0; i < size; ++i)
5424 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
5426 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
5427 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
5428 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
5429 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
5430 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
5431 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
5434 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
5436 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
5439 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
5441 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
5445 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
5447 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5448 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
5452 * Add TCP item to matcher and to the value.
5454 * @param[in, out] matcher
5456 * @param[in, out] key
5457 * Flow matcher value.
5459 * Flow pattern to translate.
5461 * Item is inner pattern.
5464 flow_dv_translate_item_tcp(void *matcher, void *key,
5465 const struct rte_flow_item *item,
5468 const struct rte_flow_item_tcp *tcp_m = item->mask;
5469 const struct rte_flow_item_tcp *tcp_v = item->spec;
5474 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5476 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5478 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5480 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5482 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5483 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
5487 tcp_m = &rte_flow_item_tcp_mask;
5488 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
5489 rte_be_to_cpu_16(tcp_m->hdr.src_port));
5490 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
5491 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
5492 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
5493 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
5494 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
5495 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
5496 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
5497 tcp_m->hdr.tcp_flags);
5498 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
5499 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
5503 * Add UDP item to matcher and to the value.
5505 * @param[in, out] matcher
5507 * @param[in, out] key
5508 * Flow matcher value.
5510 * Flow pattern to translate.
5512 * Item is inner pattern.
5515 flow_dv_translate_item_udp(void *matcher, void *key,
5516 const struct rte_flow_item *item,
5519 const struct rte_flow_item_udp *udp_m = item->mask;
5520 const struct rte_flow_item_udp *udp_v = item->spec;
5525 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5527 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5529 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5531 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5533 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5534 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
5538 udp_m = &rte_flow_item_udp_mask;
5539 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
5540 rte_be_to_cpu_16(udp_m->hdr.src_port));
5541 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
5542 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
5543 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
5544 rte_be_to_cpu_16(udp_m->hdr.dst_port));
5545 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5546 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
5550 * Add GRE optional Key item to matcher and to the value.
5552 * @param[in, out] matcher
5554 * @param[in, out] key
5555 * Flow matcher value.
5557 * Flow pattern to translate.
5559 * Item is inner pattern.
5562 flow_dv_translate_item_gre_key(void *matcher, void *key,
5563 const struct rte_flow_item *item)
5565 const rte_be32_t *key_m = item->mask;
5566 const rte_be32_t *key_v = item->spec;
5567 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5568 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5569 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
5574 key_m = &gre_key_default_mask;
5575 /* GRE K bit must be on and should already be validated */
5576 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
5577 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
5578 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
5579 rte_be_to_cpu_32(*key_m) >> 8);
5580 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
5581 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
5582 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
5583 rte_be_to_cpu_32(*key_m) & 0xFF);
5584 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
5585 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
5589 * Add GRE item to matcher and to the value.
5591 * @param[in, out] matcher
5593 * @param[in, out] key
5594 * Flow matcher value.
5596 * Flow pattern to translate.
5598 * Item is inner pattern.
5601 flow_dv_translate_item_gre(void *matcher, void *key,
5602 const struct rte_flow_item *item,
5605 const struct rte_flow_item_gre *gre_m = item->mask;
5606 const struct rte_flow_item_gre *gre_v = item->spec;
5609 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5610 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5617 uint16_t s_present:1;
5618 uint16_t k_present:1;
5619 uint16_t rsvd_bit1:1;
5620 uint16_t c_present:1;
5624 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
5627 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5629 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5631 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5633 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5635 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5636 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
5640 gre_m = &rte_flow_item_gre_mask;
5641 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
5642 rte_be_to_cpu_16(gre_m->protocol));
5643 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5644 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
5645 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
5646 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
5647 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
5648 gre_crks_rsvd0_ver_m.c_present);
5649 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
5650 gre_crks_rsvd0_ver_v.c_present &
5651 gre_crks_rsvd0_ver_m.c_present);
5652 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
5653 gre_crks_rsvd0_ver_m.k_present);
5654 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
5655 gre_crks_rsvd0_ver_v.k_present &
5656 gre_crks_rsvd0_ver_m.k_present);
5657 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
5658 gre_crks_rsvd0_ver_m.s_present);
5659 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
5660 gre_crks_rsvd0_ver_v.s_present &
5661 gre_crks_rsvd0_ver_m.s_present);
5665 * Add NVGRE item to matcher and to the value.
5667 * @param[in, out] matcher
5669 * @param[in, out] key
5670 * Flow matcher value.
5672 * Flow pattern to translate.
5674 * Item is inner pattern.
5677 flow_dv_translate_item_nvgre(void *matcher, void *key,
5678 const struct rte_flow_item *item,
5681 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
5682 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
5683 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5684 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5685 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
5686 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
5692 /* For NVGRE, GRE header fields must be set with defined values. */
5693 const struct rte_flow_item_gre gre_spec = {
5694 .c_rsvd0_ver = RTE_BE16(0x2000),
5695 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
5697 const struct rte_flow_item_gre gre_mask = {
5698 .c_rsvd0_ver = RTE_BE16(0xB000),
5699 .protocol = RTE_BE16(UINT16_MAX),
5701 const struct rte_flow_item gre_item = {
5706 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
5710 nvgre_m = &rte_flow_item_nvgre_mask;
5711 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
5712 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
5713 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
5714 memcpy(gre_key_m, tni_flow_id_m, size);
5715 for (i = 0; i < size; ++i)
5716 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
5720 * Add VXLAN item to matcher and to the value.
5722 * @param[in, out] matcher
5724 * @param[in, out] key
5725 * Flow matcher value.
5727 * Flow pattern to translate.
5729 * Item is inner pattern.
5732 flow_dv_translate_item_vxlan(void *matcher, void *key,
5733 const struct rte_flow_item *item,
5736 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
5737 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
5740 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5741 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5749 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5751 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5753 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5755 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5757 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
5758 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
5759 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5760 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5761 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5766 vxlan_m = &rte_flow_item_vxlan_mask;
5767 size = sizeof(vxlan_m->vni);
5768 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
5769 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
5770 memcpy(vni_m, vxlan_m->vni, size);
5771 for (i = 0; i < size; ++i)
5772 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
5776 * Add Geneve item to matcher and to the value.
5778 * @param[in, out] matcher
5780 * @param[in, out] key
5781 * Flow matcher value.
5783 * Flow pattern to translate.
5785 * Item is inner pattern.
5789 flow_dv_translate_item_geneve(void *matcher, void *key,
5790 const struct rte_flow_item *item, int inner)
5792 const struct rte_flow_item_geneve *geneve_m = item->mask;
5793 const struct rte_flow_item_geneve *geneve_v = item->spec;
5796 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5797 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5806 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5808 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5810 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5812 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5814 dport = MLX5_UDP_PORT_GENEVE;
5815 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
5816 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
5817 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
5822 geneve_m = &rte_flow_item_geneve_mask;
5823 size = sizeof(geneve_m->vni);
5824 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
5825 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
5826 memcpy(vni_m, geneve_m->vni, size);
5827 for (i = 0; i < size; ++i)
5828 vni_v[i] = vni_m[i] & geneve_v->vni[i];
5829 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
5830 rte_be_to_cpu_16(geneve_m->protocol));
5831 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
5832 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
5833 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
5834 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
5835 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
5836 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5837 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
5838 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
5839 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
5840 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5841 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
5842 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
5843 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
5847 * Add MPLS item to matcher and to the value.
5849 * @param[in, out] matcher
5851 * @param[in, out] key
5852 * Flow matcher value.
5854 * Flow pattern to translate.
5855 * @param[in] prev_layer
5856 * The protocol layer indicated in previous item.
5858 * Item is inner pattern.
5861 flow_dv_translate_item_mpls(void *matcher, void *key,
5862 const struct rte_flow_item *item,
5863 uint64_t prev_layer,
5866 const uint32_t *in_mpls_m = item->mask;
5867 const uint32_t *in_mpls_v = item->spec;
5868 uint32_t *out_mpls_m = 0;
5869 uint32_t *out_mpls_v = 0;
5870 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
5871 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
5872 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
5874 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5875 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
5876 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5878 switch (prev_layer) {
5879 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5880 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
5881 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
5882 MLX5_UDP_PORT_MPLS);
5884 case MLX5_FLOW_LAYER_GRE:
5885 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
5886 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
5887 RTE_ETHER_TYPE_MPLS);
5890 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
5891 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
5898 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
5899 switch (prev_layer) {
5900 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
5902 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5903 outer_first_mpls_over_udp);
5905 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5906 outer_first_mpls_over_udp);
5908 case MLX5_FLOW_LAYER_GRE:
5910 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
5911 outer_first_mpls_over_gre);
5913 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
5914 outer_first_mpls_over_gre);
5917 /* Inner MPLS not over GRE is not supported. */
5920 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5924 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
5930 if (out_mpls_m && out_mpls_v) {
5931 *out_mpls_m = *in_mpls_m;
5932 *out_mpls_v = *in_mpls_v & *in_mpls_m;
5937 * Add metadata register item to matcher
5939 * @param[in, out] matcher
5941 * @param[in, out] key
5942 * Flow matcher value.
5943 * @param[in] reg_type
5944 * Type of device metadata register
5951 flow_dv_match_meta_reg(void *matcher, void *key,
5952 enum modify_reg reg_type,
5953 uint32_t data, uint32_t mask)
5956 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
5958 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
5964 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
5965 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
5968 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
5969 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
5973 * The metadata register C0 field might be divided into
5974 * source vport index and META item value, we should set
5975 * this field according to specified mask, not as whole one.
5977 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
5979 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
5980 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
5983 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
5986 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
5987 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
5990 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
5991 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
5994 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
5995 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
5998 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
5999 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6002 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6003 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6006 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6007 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6010 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6011 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6020 * Add MARK item to matcher
6023 * The device to configure through.
6024 * @param[in, out] matcher
6026 * @param[in, out] key
6027 * Flow matcher value.
6029 * Flow pattern to translate.
6032 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6033 void *matcher, void *key,
6034 const struct rte_flow_item *item)
6036 struct mlx5_priv *priv = dev->data->dev_private;
6037 const struct rte_flow_item_mark *mark;
6041 mark = item->mask ? (const void *)item->mask :
6042 &rte_flow_item_mark_mask;
6043 mask = mark->id & priv->sh->dv_mark_mask;
6044 mark = (const void *)item->spec;
6046 value = mark->id & priv->sh->dv_mark_mask & mask;
6048 enum modify_reg reg;
6050 /* Get the metadata register index for the mark. */
6051 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6053 if (reg == REG_C_0) {
6054 struct mlx5_priv *priv = dev->data->dev_private;
6055 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6056 uint32_t shl_c0 = rte_bsf32(msk_c0);
6062 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6067 * Add META item to matcher
6070 * The devich to configure through.
6071 * @param[in, out] matcher
6073 * @param[in, out] key
6074 * Flow matcher value.
6076 * Attributes of flow that includes this item.
6078 * Flow pattern to translate.
6081 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6082 void *matcher, void *key,
6083 const struct rte_flow_attr *attr,
6084 const struct rte_flow_item *item)
6086 const struct rte_flow_item_meta *meta_m;
6087 const struct rte_flow_item_meta *meta_v;
6089 meta_m = (const void *)item->mask;
6091 meta_m = &rte_flow_item_meta_mask;
6092 meta_v = (const void *)item->spec;
6095 uint32_t value = meta_v->data;
6096 uint32_t mask = meta_m->data;
6098 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6102 * In datapath code there is no endianness
6103 * coversions for perfromance reasons, all
6104 * pattern conversions are done in rte_flow.
6106 value = rte_cpu_to_be_32(value);
6107 mask = rte_cpu_to_be_32(mask);
6108 if (reg == REG_C_0) {
6109 struct mlx5_priv *priv = dev->data->dev_private;
6110 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6111 uint32_t shl_c0 = rte_bsf32(msk_c0);
6112 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6113 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6121 assert(!(~msk_c0 & mask));
6123 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6128 * Add vport metadata Reg C0 item to matcher
6130 * @param[in, out] matcher
6132 * @param[in, out] key
6133 * Flow matcher value.
6135 * Flow pattern to translate.
6138 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6139 uint32_t value, uint32_t mask)
6141 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6145 * Add tag item to matcher
6148 * The devich to configure through.
6149 * @param[in, out] matcher
6151 * @param[in, out] key
6152 * Flow matcher value.
6154 * Flow pattern to translate.
6157 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
6158 void *matcher, void *key,
6159 const struct rte_flow_item *item)
6161 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
6162 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
6163 uint32_t mask, value;
6166 value = tag_v->data;
6167 mask = tag_m ? tag_m->data : UINT32_MAX;
6168 if (tag_v->id == REG_C_0) {
6169 struct mlx5_priv *priv = dev->data->dev_private;
6170 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6171 uint32_t shl_c0 = rte_bsf32(msk_c0);
6177 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
6181 * Add TAG item to matcher
6184 * The devich to configure through.
6185 * @param[in, out] matcher
6187 * @param[in, out] key
6188 * Flow matcher value.
6190 * Flow pattern to translate.
6193 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
6194 void *matcher, void *key,
6195 const struct rte_flow_item *item)
6197 const struct rte_flow_item_tag *tag_v = item->spec;
6198 const struct rte_flow_item_tag *tag_m = item->mask;
6199 enum modify_reg reg;
6202 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
6203 /* Get the metadata register index for the tag. */
6204 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
6206 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
6210 * Add source vport match to the specified matcher.
6212 * @param[in, out] matcher
6214 * @param[in, out] key
6215 * Flow matcher value.
6217 * Source vport value to match
6222 flow_dv_translate_item_source_vport(void *matcher, void *key,
6223 int16_t port, uint16_t mask)
6225 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6226 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6228 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
6229 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
6233 * Translate port-id item to eswitch match on port-id.
6236 * The devich to configure through.
6237 * @param[in, out] matcher
6239 * @param[in, out] key
6240 * Flow matcher value.
6242 * Flow pattern to translate.
6245 * 0 on success, a negative errno value otherwise.
6248 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
6249 void *key, const struct rte_flow_item *item)
6251 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
6252 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
6253 struct mlx5_priv *priv;
6256 mask = pid_m ? pid_m->id : 0xffff;
6257 id = pid_v ? pid_v->id : dev->data->port_id;
6258 priv = mlx5_port_to_eswitch_info(id, item == NULL);
6261 /* Translate to vport field or to metadata, depending on mode. */
6262 if (priv->vport_meta_mask)
6263 flow_dv_translate_item_meta_vport(matcher, key,
6264 priv->vport_meta_tag,
6265 priv->vport_meta_mask);
6267 flow_dv_translate_item_source_vport(matcher, key,
6268 priv->vport_id, mask);
6273 * Add ICMP6 item to matcher and to the value.
6275 * @param[in, out] matcher
6277 * @param[in, out] key
6278 * Flow matcher value.
6280 * Flow pattern to translate.
6282 * Item is inner pattern.
6285 flow_dv_translate_item_icmp6(void *matcher, void *key,
6286 const struct rte_flow_item *item,
6289 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
6290 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
6293 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6295 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6297 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6299 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6301 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6303 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6305 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6306 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
6310 icmp6_m = &rte_flow_item_icmp6_mask;
6311 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
6312 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
6313 icmp6_v->type & icmp6_m->type);
6314 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
6315 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
6316 icmp6_v->code & icmp6_m->code);
6320 * Add ICMP item to matcher and to the value.
6322 * @param[in, out] matcher
6324 * @param[in, out] key
6325 * Flow matcher value.
6327 * Flow pattern to translate.
6329 * Item is inner pattern.
6332 flow_dv_translate_item_icmp(void *matcher, void *key,
6333 const struct rte_flow_item *item,
6336 const struct rte_flow_item_icmp *icmp_m = item->mask;
6337 const struct rte_flow_item_icmp *icmp_v = item->spec;
6340 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6342 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6344 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6346 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6348 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6350 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6352 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
6353 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
6357 icmp_m = &rte_flow_item_icmp_mask;
6358 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
6359 icmp_m->hdr.icmp_type);
6360 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
6361 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
6362 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
6363 icmp_m->hdr.icmp_code);
6364 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
6365 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
6369 * Add GTP item to matcher and to the value.
6371 * @param[in, out] matcher
6373 * @param[in, out] key
6374 * Flow matcher value.
6376 * Flow pattern to translate.
6378 * Item is inner pattern.
6381 flow_dv_translate_item_gtp(void *matcher, void *key,
6382 const struct rte_flow_item *item, int inner)
6384 const struct rte_flow_item_gtp *gtp_m = item->mask;
6385 const struct rte_flow_item_gtp *gtp_v = item->spec;
6388 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
6390 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6391 uint16_t dport = RTE_GTPU_UDP_PORT;
6394 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6396 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6398 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6400 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6402 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6403 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6404 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6409 gtp_m = &rte_flow_item_gtp_mask;
6410 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
6411 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
6412 gtp_v->msg_type & gtp_m->msg_type);
6413 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
6414 rte_be_to_cpu_32(gtp_m->teid));
6415 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
6416 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
6419 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
6421 #define HEADER_IS_ZERO(match_criteria, headers) \
6422 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
6423 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
6426 * Calculate flow matcher enable bitmap.
6428 * @param match_criteria
6429 * Pointer to flow matcher criteria.
6432 * Bitmap of enabled fields.
6435 flow_dv_matcher_enable(uint32_t *match_criteria)
6437 uint8_t match_criteria_enable;
6439 match_criteria_enable =
6440 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
6441 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
6442 match_criteria_enable |=
6443 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
6444 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
6445 match_criteria_enable |=
6446 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
6447 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
6448 match_criteria_enable |=
6449 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
6450 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
6451 match_criteria_enable |=
6452 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
6453 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
6454 return match_criteria_enable;
6461 * @param[in, out] dev
6462 * Pointer to rte_eth_dev structure.
6463 * @param[in] table_id
6466 * Direction of the table.
6467 * @param[in] transfer
6468 * E-Switch or NIC flow.
6470 * pointer to error structure.
6473 * Returns tables resource based on the index, NULL in case of failed.
6475 static struct mlx5_flow_tbl_resource *
6476 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
6477 uint32_t table_id, uint8_t egress,
6479 struct rte_flow_error *error)
6481 struct mlx5_priv *priv = dev->data->dev_private;
6482 struct mlx5_ibv_shared *sh = priv->sh;
6483 struct mlx5_flow_tbl_resource *tbl;
6484 union mlx5_flow_tbl_key table_key = {
6486 .table_id = table_id,
6488 .domain = !!transfer,
6489 .direction = !!egress,
6492 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
6494 struct mlx5_flow_tbl_data_entry *tbl_data;
6499 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
6501 tbl = &tbl_data->tbl;
6502 rte_atomic32_inc(&tbl->refcnt);
6505 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0);
6507 rte_flow_error_set(error, ENOMEM,
6508 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6510 "cannot allocate flow table data entry");
6513 tbl = &tbl_data->tbl;
6514 pos = &tbl_data->entry;
6516 domain = sh->fdb_domain;
6518 domain = sh->tx_domain;
6520 domain = sh->rx_domain;
6521 tbl->obj = mlx5_glue->dr_create_flow_tbl(domain, table_id);
6523 rte_flow_error_set(error, ENOMEM,
6524 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6525 NULL, "cannot create flow table object");
6530 * No multi-threads now, but still better to initialize the reference
6531 * count before insert it into the hash list.
6533 rte_atomic32_init(&tbl->refcnt);
6534 /* Jump action reference count is initialized here. */
6535 rte_atomic32_init(&tbl_data->jump.refcnt);
6536 pos->key = table_key.v64;
6537 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
6539 rte_flow_error_set(error, -ret,
6540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6541 "cannot insert flow table data entry");
6542 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6545 rte_atomic32_inc(&tbl->refcnt);
6550 * Release a flow table.
6553 * Pointer to rte_eth_dev structure.
6555 * Table resource to be released.
6558 * Returns 0 if table was released, else return 1;
6561 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
6562 struct mlx5_flow_tbl_resource *tbl)
6564 struct mlx5_priv *priv = dev->data->dev_private;
6565 struct mlx5_ibv_shared *sh = priv->sh;
6566 struct mlx5_flow_tbl_data_entry *tbl_data =
6567 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6571 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
6572 struct mlx5_hlist_entry *pos = &tbl_data->entry;
6574 mlx5_glue->dr_destroy_flow_tbl(tbl->obj);
6576 /* remove the entry from the hash list and free memory. */
6577 mlx5_hlist_remove(sh->flow_tbls, pos);
6585 * Register the flow matcher.
6587 * @param[in, out] dev
6588 * Pointer to rte_eth_dev structure.
6589 * @param[in, out] matcher
6590 * Pointer to flow matcher.
6591 * @param[in, out] key
6592 * Pointer to flow table key.
6593 * @parm[in, out] dev_flow
6594 * Pointer to the dev_flow.
6596 * pointer to error structure.
6599 * 0 on success otherwise -errno and errno is set.
6602 flow_dv_matcher_register(struct rte_eth_dev *dev,
6603 struct mlx5_flow_dv_matcher *matcher,
6604 union mlx5_flow_tbl_key *key,
6605 struct mlx5_flow *dev_flow,
6606 struct rte_flow_error *error)
6608 struct mlx5_priv *priv = dev->data->dev_private;
6609 struct mlx5_ibv_shared *sh = priv->sh;
6610 struct mlx5_flow_dv_matcher *cache_matcher;
6611 struct mlx5dv_flow_matcher_attr dv_attr = {
6612 .type = IBV_FLOW_ATTR_NORMAL,
6613 .match_mask = (void *)&matcher->mask,
6615 struct mlx5_flow_tbl_resource *tbl;
6616 struct mlx5_flow_tbl_data_entry *tbl_data;
6618 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
6619 key->domain, error);
6621 return -rte_errno; /* No need to refill the error info */
6622 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
6623 /* Lookup from cache. */
6624 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
6625 if (matcher->crc == cache_matcher->crc &&
6626 matcher->priority == cache_matcher->priority &&
6627 !memcmp((const void *)matcher->mask.buf,
6628 (const void *)cache_matcher->mask.buf,
6629 cache_matcher->mask.size)) {
6631 "%s group %u priority %hd use %s "
6632 "matcher %p: refcnt %d++",
6633 key->domain ? "FDB" : "NIC", key->table_id,
6634 cache_matcher->priority,
6635 key->direction ? "tx" : "rx",
6636 (void *)cache_matcher,
6637 rte_atomic32_read(&cache_matcher->refcnt));
6638 rte_atomic32_inc(&cache_matcher->refcnt);
6639 dev_flow->dv.matcher = cache_matcher;
6640 /* old matcher should not make the table ref++. */
6641 flow_dv_tbl_resource_release(dev, tbl);
6645 /* Register new matcher. */
6646 cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
6647 if (!cache_matcher) {
6648 flow_dv_tbl_resource_release(dev, tbl);
6649 return rte_flow_error_set(error, ENOMEM,
6650 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6651 "cannot allocate matcher memory");
6653 *cache_matcher = *matcher;
6654 dv_attr.match_criteria_enable =
6655 flow_dv_matcher_enable(cache_matcher->mask.buf);
6656 dv_attr.priority = matcher->priority;
6658 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
6659 cache_matcher->matcher_object =
6660 mlx5_glue->dv_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj);
6661 if (!cache_matcher->matcher_object) {
6662 rte_free(cache_matcher);
6663 #ifdef HAVE_MLX5DV_DR
6664 flow_dv_tbl_resource_release(dev, tbl);
6666 return rte_flow_error_set(error, ENOMEM,
6667 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6668 NULL, "cannot create matcher");
6670 /* Save the table information */
6671 cache_matcher->tbl = tbl;
6672 rte_atomic32_init(&cache_matcher->refcnt);
6673 /* only matcher ref++, table ref++ already done above in get API. */
6674 rte_atomic32_inc(&cache_matcher->refcnt);
6675 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
6676 dev_flow->dv.matcher = cache_matcher;
6677 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
6678 key->domain ? "FDB" : "NIC", key->table_id,
6679 cache_matcher->priority,
6680 key->direction ? "tx" : "rx", (void *)cache_matcher,
6681 rte_atomic32_read(&cache_matcher->refcnt));
6686 * Find existing tag resource or create and register a new one.
6688 * @param dev[in, out]
6689 * Pointer to rte_eth_dev structure.
6690 * @param[in, out] tag_be24
6691 * Tag value in big endian then R-shift 8.
6692 * @parm[in, out] dev_flow
6693 * Pointer to the dev_flow.
6695 * pointer to error structure.
6698 * 0 on success otherwise -errno and errno is set.
6701 flow_dv_tag_resource_register
6702 (struct rte_eth_dev *dev,
6704 struct mlx5_flow *dev_flow,
6705 struct rte_flow_error *error)
6707 struct mlx5_priv *priv = dev->data->dev_private;
6708 struct mlx5_ibv_shared *sh = priv->sh;
6709 struct mlx5_flow_dv_tag_resource *cache_resource;
6710 struct mlx5_hlist_entry *entry;
6712 /* Lookup a matching resource from cache. */
6713 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
6715 cache_resource = container_of
6716 (entry, struct mlx5_flow_dv_tag_resource, entry);
6717 rte_atomic32_inc(&cache_resource->refcnt);
6718 dev_flow->dv.tag_resource = cache_resource;
6719 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
6720 (void *)cache_resource,
6721 rte_atomic32_read(&cache_resource->refcnt));
6724 /* Register new resource. */
6725 cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
6726 if (!cache_resource)
6727 return rte_flow_error_set(error, ENOMEM,
6728 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6729 "cannot allocate resource memory");
6730 cache_resource->entry.key = (uint64_t)tag_be24;
6731 cache_resource->action = mlx5_glue->dv_create_flow_action_tag(tag_be24);
6732 if (!cache_resource->action) {
6733 rte_free(cache_resource);
6734 return rte_flow_error_set(error, ENOMEM,
6735 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6736 NULL, "cannot create action");
6738 rte_atomic32_init(&cache_resource->refcnt);
6739 rte_atomic32_inc(&cache_resource->refcnt);
6740 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
6741 mlx5_glue->destroy_flow_action(cache_resource->action);
6742 rte_free(cache_resource);
6743 return rte_flow_error_set(error, EEXIST,
6744 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6745 NULL, "cannot insert tag");
6747 dev_flow->dv.tag_resource = cache_resource;
6748 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
6749 (void *)cache_resource,
6750 rte_atomic32_read(&cache_resource->refcnt));
6758 * Pointer to Ethernet device.
6760 * Pointer to mlx5_flow.
6763 * 1 while a reference on it exists, 0 when freed.
6766 flow_dv_tag_release(struct rte_eth_dev *dev,
6767 struct mlx5_flow_dv_tag_resource *tag)
6769 struct mlx5_priv *priv = dev->data->dev_private;
6770 struct mlx5_ibv_shared *sh = priv->sh;
6773 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
6774 dev->data->port_id, (void *)tag,
6775 rte_atomic32_read(&tag->refcnt));
6776 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
6777 claim_zero(mlx5_glue->destroy_flow_action(tag->action));
6778 mlx5_hlist_remove(sh->tag_table, &tag->entry);
6779 DRV_LOG(DEBUG, "port %u tag %p: removed",
6780 dev->data->port_id, (void *)tag);
6788 * Translate port ID action to vport.
6791 * Pointer to rte_eth_dev structure.
6793 * Pointer to the port ID action.
6794 * @param[out] dst_port_id
6795 * The target port ID.
6797 * Pointer to the error structure.
6800 * 0 on success, a negative errno value otherwise and rte_errno is set.
6803 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
6804 const struct rte_flow_action *action,
6805 uint32_t *dst_port_id,
6806 struct rte_flow_error *error)
6809 struct mlx5_priv *priv;
6810 const struct rte_flow_action_port_id *conf =
6811 (const struct rte_flow_action_port_id *)action->conf;
6813 port = conf->original ? dev->data->port_id : conf->id;
6814 priv = mlx5_port_to_eswitch_info(port, false);
6816 return rte_flow_error_set(error, -rte_errno,
6817 RTE_FLOW_ERROR_TYPE_ACTION,
6819 "No eswitch info was found for port");
6820 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
6822 * This parameter is transferred to
6823 * mlx5dv_dr_action_create_dest_ib_port().
6825 *dst_port_id = priv->ibv_port;
6828 * Legacy mode, no LAG configurations is supported.
6829 * This parameter is transferred to
6830 * mlx5dv_dr_action_create_dest_vport().
6832 *dst_port_id = priv->vport_id;
6838 * Add Tx queue matcher
6841 * Pointer to the dev struct.
6842 * @param[in, out] matcher
6844 * @param[in, out] key
6845 * Flow matcher value.
6847 * Flow pattern to translate.
6849 * Item is inner pattern.
6852 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
6853 void *matcher, void *key,
6854 const struct rte_flow_item *item)
6856 const struct mlx5_rte_flow_item_tx_queue *queue_m;
6857 const struct mlx5_rte_flow_item_tx_queue *queue_v;
6859 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6861 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6862 struct mlx5_txq_ctrl *txq;
6866 queue_m = (const void *)item->mask;
6869 queue_v = (const void *)item->spec;
6872 txq = mlx5_txq_get(dev, queue_v->queue);
6875 queue = txq->obj->sq->id;
6876 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
6877 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
6878 queue & queue_m->queue);
6879 mlx5_txq_release(dev, queue_v->queue);
6883 * Set the hash fields according to the @p flow information.
6885 * @param[in] dev_flow
6886 * Pointer to the mlx5_flow.
6889 flow_dv_hashfields_set(struct mlx5_flow *dev_flow)
6891 struct rte_flow *flow = dev_flow->flow;
6892 uint64_t items = dev_flow->layers;
6894 uint64_t rss_types = rte_eth_rss_hf_refine(flow->rss.types);
6896 dev_flow->hash_fields = 0;
6897 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
6898 if (flow->rss.level >= 2) {
6899 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
6903 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
6904 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
6905 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
6906 if (rss_types & ETH_RSS_L3_SRC_ONLY)
6907 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
6908 else if (rss_types & ETH_RSS_L3_DST_ONLY)
6909 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
6911 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
6913 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
6914 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
6915 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
6916 if (rss_types & ETH_RSS_L3_SRC_ONLY)
6917 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
6918 else if (rss_types & ETH_RSS_L3_DST_ONLY)
6919 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
6921 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
6924 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
6925 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
6926 if (rss_types & ETH_RSS_UDP) {
6927 if (rss_types & ETH_RSS_L4_SRC_ONLY)
6928 dev_flow->hash_fields |=
6929 IBV_RX_HASH_SRC_PORT_UDP;
6930 else if (rss_types & ETH_RSS_L4_DST_ONLY)
6931 dev_flow->hash_fields |=
6932 IBV_RX_HASH_DST_PORT_UDP;
6934 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
6936 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
6937 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
6938 if (rss_types & ETH_RSS_TCP) {
6939 if (rss_types & ETH_RSS_L4_SRC_ONLY)
6940 dev_flow->hash_fields |=
6941 IBV_RX_HASH_SRC_PORT_TCP;
6942 else if (rss_types & ETH_RSS_L4_DST_ONLY)
6943 dev_flow->hash_fields |=
6944 IBV_RX_HASH_DST_PORT_TCP;
6946 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
6952 * Fill the flow with DV spec, lock free
6953 * (mutex should be acquired by caller).
6956 * Pointer to rte_eth_dev structure.
6957 * @param[in, out] dev_flow
6958 * Pointer to the sub flow.
6960 * Pointer to the flow attributes.
6962 * Pointer to the list of items.
6963 * @param[in] actions
6964 * Pointer to the list of actions.
6966 * Pointer to the error structure.
6969 * 0 on success, a negative errno value otherwise and rte_errno is set.
6972 __flow_dv_translate(struct rte_eth_dev *dev,
6973 struct mlx5_flow *dev_flow,
6974 const struct rte_flow_attr *attr,
6975 const struct rte_flow_item items[],
6976 const struct rte_flow_action actions[],
6977 struct rte_flow_error *error)
6979 struct mlx5_priv *priv = dev->data->dev_private;
6980 struct mlx5_dev_config *dev_conf = &priv->config;
6981 struct rte_flow *flow = dev_flow->flow;
6982 uint64_t item_flags = 0;
6983 uint64_t last_item = 0;
6984 uint64_t action_flags = 0;
6985 uint64_t priority = attr->priority;
6986 struct mlx5_flow_dv_matcher matcher = {
6988 .size = sizeof(matcher.mask.buf),
6992 bool actions_end = false;
6994 struct mlx5_flow_dv_modify_hdr_resource res;
6995 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
6996 sizeof(struct mlx5_modification_cmd) *
6997 (MLX5_MAX_MODIFY_NUM + 1)];
6999 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
7000 union flow_dv_attr flow_attr = { .attr = 0 };
7002 union mlx5_flow_tbl_key tbl_key;
7003 uint32_t modify_action_position = UINT32_MAX;
7004 void *match_mask = matcher.mask.buf;
7005 void *match_value = dev_flow->dv.value.buf;
7006 uint8_t next_protocol = 0xff;
7007 struct rte_vlan_hdr vlan = { 0 };
7011 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
7012 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
7013 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
7017 dev_flow->group = table;
7019 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
7020 if (priority == MLX5_FLOW_PRIO_RSVD)
7021 priority = dev_conf->flow_prio - 1;
7022 /* number of actions must be set to 0 in case of dirty stack. */
7023 mhdr_res->actions_num = 0;
7024 for (; !actions_end ; actions++) {
7025 const struct rte_flow_action_queue *queue;
7026 const struct rte_flow_action_rss *rss;
7027 const struct rte_flow_action *action = actions;
7028 const struct rte_flow_action_count *count = action->conf;
7029 const uint8_t *rss_key;
7030 const struct rte_flow_action_jump *jump_data;
7031 const struct rte_flow_action_meter *mtr;
7032 struct mlx5_flow_tbl_resource *tbl;
7033 uint32_t port_id = 0;
7034 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
7035 int action_type = actions->type;
7036 const struct rte_flow_action *found_action = NULL;
7038 switch (action_type) {
7039 case RTE_FLOW_ACTION_TYPE_VOID:
7041 case RTE_FLOW_ACTION_TYPE_PORT_ID:
7042 if (flow_dv_translate_action_port_id(dev, action,
7045 port_id_resource.port_id = port_id;
7046 if (flow_dv_port_id_action_resource_register
7047 (dev, &port_id_resource, dev_flow, error))
7049 dev_flow->dv.actions[actions_n++] =
7050 dev_flow->dv.port_id_action->action;
7051 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
7053 case RTE_FLOW_ACTION_TYPE_FLAG:
7054 action_flags |= MLX5_FLOW_ACTION_FLAG;
7055 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7056 struct rte_flow_action_mark mark = {
7057 .id = MLX5_FLOW_MARK_DEFAULT,
7060 if (flow_dv_convert_action_mark(dev, &mark,
7064 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7067 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
7068 if (!dev_flow->dv.tag_resource)
7069 if (flow_dv_tag_resource_register
7070 (dev, tag_be, dev_flow, error))
7072 dev_flow->dv.actions[actions_n++] =
7073 dev_flow->dv.tag_resource->action;
7075 case RTE_FLOW_ACTION_TYPE_MARK:
7076 action_flags |= MLX5_FLOW_ACTION_MARK;
7077 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
7078 const struct rte_flow_action_mark *mark =
7079 (const struct rte_flow_action_mark *)
7082 if (flow_dv_convert_action_mark(dev, mark,
7086 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
7090 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
7091 /* Legacy (non-extensive) MARK action. */
7092 tag_be = mlx5_flow_mark_set
7093 (((const struct rte_flow_action_mark *)
7094 (actions->conf))->id);
7095 if (!dev_flow->dv.tag_resource)
7096 if (flow_dv_tag_resource_register
7097 (dev, tag_be, dev_flow, error))
7099 dev_flow->dv.actions[actions_n++] =
7100 dev_flow->dv.tag_resource->action;
7102 case RTE_FLOW_ACTION_TYPE_SET_META:
7103 if (flow_dv_convert_action_set_meta
7104 (dev, mhdr_res, attr,
7105 (const struct rte_flow_action_set_meta *)
7106 actions->conf, error))
7108 action_flags |= MLX5_FLOW_ACTION_SET_META;
7110 case RTE_FLOW_ACTION_TYPE_SET_TAG:
7111 if (flow_dv_convert_action_set_tag
7113 (const struct rte_flow_action_set_tag *)
7114 actions->conf, error))
7116 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7118 case RTE_FLOW_ACTION_TYPE_DROP:
7119 action_flags |= MLX5_FLOW_ACTION_DROP;
7121 case RTE_FLOW_ACTION_TYPE_QUEUE:
7122 assert(flow->rss.queue);
7123 queue = actions->conf;
7124 flow->rss.queue_num = 1;
7125 (*flow->rss.queue)[0] = queue->index;
7126 action_flags |= MLX5_FLOW_ACTION_QUEUE;
7128 case RTE_FLOW_ACTION_TYPE_RSS:
7129 assert(flow->rss.queue);
7130 rss = actions->conf;
7131 if (flow->rss.queue)
7132 memcpy((*flow->rss.queue), rss->queue,
7133 rss->queue_num * sizeof(uint16_t));
7134 flow->rss.queue_num = rss->queue_num;
7135 /* NULL RSS key indicates default RSS key. */
7136 rss_key = !rss->key ? rss_hash_default_key : rss->key;
7137 memcpy(flow->rss.key, rss_key, MLX5_RSS_HASH_KEY_LEN);
7139 * rss->level and rss.types should be set in advance
7140 * when expanding items for RSS.
7142 action_flags |= MLX5_FLOW_ACTION_RSS;
7144 case RTE_FLOW_ACTION_TYPE_COUNT:
7145 if (!dev_conf->devx) {
7146 rte_errno = ENOTSUP;
7149 flow->counter = flow_dv_counter_alloc(dev,
7153 if (flow->counter == NULL)
7155 dev_flow->dv.actions[actions_n++] =
7156 flow->counter->action;
7157 action_flags |= MLX5_FLOW_ACTION_COUNT;
7160 if (rte_errno == ENOTSUP)
7161 return rte_flow_error_set
7163 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7165 "count action not supported");
7167 return rte_flow_error_set
7169 RTE_FLOW_ERROR_TYPE_ACTION,
7171 "cannot create counter"
7174 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
7175 dev_flow->dv.actions[actions_n++] =
7176 priv->sh->pop_vlan_action;
7177 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
7179 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
7180 flow_dev_get_vlan_info_from_items(items, &vlan);
7181 vlan.eth_proto = rte_be_to_cpu_16
7182 ((((const struct rte_flow_action_of_push_vlan *)
7183 actions->conf)->ethertype));
7184 found_action = mlx5_flow_find_action
7186 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
7188 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7189 found_action = mlx5_flow_find_action
7191 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
7193 mlx5_update_vlan_vid_pcp(found_action, &vlan);
7194 if (flow_dv_create_action_push_vlan
7195 (dev, attr, &vlan, dev_flow, error))
7197 dev_flow->dv.actions[actions_n++] =
7198 dev_flow->dv.push_vlan_res->action;
7199 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
7201 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
7202 /* of_vlan_push action handled this action */
7203 assert(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN);
7205 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
7206 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7208 flow_dev_get_vlan_info_from_items(items, &vlan);
7209 mlx5_update_vlan_vid_pcp(actions, &vlan);
7210 /* If no VLAN push - this is a modify header action */
7211 if (flow_dv_convert_action_modify_vlan_vid
7212 (mhdr_res, actions, error))
7214 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
7216 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
7217 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
7218 if (flow_dv_create_action_l2_encap(dev, actions,
7223 dev_flow->dv.actions[actions_n++] =
7224 dev_flow->dv.encap_decap->verbs_action;
7225 action_flags |= actions->type ==
7226 RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
7227 MLX5_FLOW_ACTION_VXLAN_ENCAP :
7228 MLX5_FLOW_ACTION_NVGRE_ENCAP;
7230 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
7231 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
7232 if (flow_dv_create_action_l2_decap(dev, dev_flow,
7236 dev_flow->dv.actions[actions_n++] =
7237 dev_flow->dv.encap_decap->verbs_action;
7238 action_flags |= actions->type ==
7239 RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
7240 MLX5_FLOW_ACTION_VXLAN_DECAP :
7241 MLX5_FLOW_ACTION_NVGRE_DECAP;
7243 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
7244 /* Handle encap with preceding decap. */
7245 if (action_flags & MLX5_FLOW_ACTION_RAW_DECAP) {
7246 if (flow_dv_create_action_raw_encap
7247 (dev, actions, dev_flow, attr, error))
7249 dev_flow->dv.actions[actions_n++] =
7250 dev_flow->dv.encap_decap->verbs_action;
7252 /* Handle encap without preceding decap. */
7253 if (flow_dv_create_action_l2_encap
7254 (dev, actions, dev_flow, attr->transfer,
7257 dev_flow->dv.actions[actions_n++] =
7258 dev_flow->dv.encap_decap->verbs_action;
7260 action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
7262 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
7263 /* Check if this decap is followed by encap. */
7264 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
7265 action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
7268 /* Handle decap only if it isn't followed by encap. */
7269 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
7270 if (flow_dv_create_action_l2_decap
7271 (dev, dev_flow, attr->transfer, error))
7273 dev_flow->dv.actions[actions_n++] =
7274 dev_flow->dv.encap_decap->verbs_action;
7276 /* If decap is followed by encap, handle it at encap. */
7277 action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
7279 case RTE_FLOW_ACTION_TYPE_JUMP:
7280 jump_data = action->conf;
7281 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
7282 jump_data->group, &table,
7286 tbl = flow_dv_tbl_resource_get(dev, table,
7288 attr->transfer, error);
7290 return rte_flow_error_set
7292 RTE_FLOW_ERROR_TYPE_ACTION,
7294 "cannot create jump action.");
7295 if (flow_dv_jump_tbl_resource_register
7296 (dev, tbl, dev_flow, error)) {
7297 flow_dv_tbl_resource_release(dev, tbl);
7298 return rte_flow_error_set
7300 RTE_FLOW_ERROR_TYPE_ACTION,
7302 "cannot create jump action.");
7304 dev_flow->dv.actions[actions_n++] =
7305 dev_flow->dv.jump->action;
7306 action_flags |= MLX5_FLOW_ACTION_JUMP;
7308 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
7309 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
7310 if (flow_dv_convert_action_modify_mac
7311 (mhdr_res, actions, error))
7313 action_flags |= actions->type ==
7314 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
7315 MLX5_FLOW_ACTION_SET_MAC_SRC :
7316 MLX5_FLOW_ACTION_SET_MAC_DST;
7318 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
7319 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
7320 if (flow_dv_convert_action_modify_ipv4
7321 (mhdr_res, actions, error))
7323 action_flags |= actions->type ==
7324 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
7325 MLX5_FLOW_ACTION_SET_IPV4_SRC :
7326 MLX5_FLOW_ACTION_SET_IPV4_DST;
7328 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
7329 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
7330 if (flow_dv_convert_action_modify_ipv6
7331 (mhdr_res, actions, error))
7333 action_flags |= actions->type ==
7334 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
7335 MLX5_FLOW_ACTION_SET_IPV6_SRC :
7336 MLX5_FLOW_ACTION_SET_IPV6_DST;
7338 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
7339 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
7340 if (flow_dv_convert_action_modify_tp
7341 (mhdr_res, actions, items,
7344 action_flags |= actions->type ==
7345 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
7346 MLX5_FLOW_ACTION_SET_TP_SRC :
7347 MLX5_FLOW_ACTION_SET_TP_DST;
7349 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
7350 if (flow_dv_convert_action_modify_dec_ttl
7351 (mhdr_res, items, &flow_attr, error))
7353 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
7355 case RTE_FLOW_ACTION_TYPE_SET_TTL:
7356 if (flow_dv_convert_action_modify_ttl
7357 (mhdr_res, actions, items,
7360 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
7362 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
7363 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
7364 if (flow_dv_convert_action_modify_tcp_seq
7365 (mhdr_res, actions, error))
7367 action_flags |= actions->type ==
7368 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
7369 MLX5_FLOW_ACTION_INC_TCP_SEQ :
7370 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
7373 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
7374 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
7375 if (flow_dv_convert_action_modify_tcp_ack
7376 (mhdr_res, actions, error))
7378 action_flags |= actions->type ==
7379 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
7380 MLX5_FLOW_ACTION_INC_TCP_ACK :
7381 MLX5_FLOW_ACTION_DEC_TCP_ACK;
7383 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
7384 if (flow_dv_convert_action_set_reg
7385 (mhdr_res, actions, error))
7387 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7389 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
7390 if (flow_dv_convert_action_copy_mreg
7391 (dev, mhdr_res, actions, error))
7393 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
7395 case RTE_FLOW_ACTION_TYPE_METER:
7396 mtr = actions->conf;
7398 flow->meter = mlx5_flow_meter_attach(priv,
7402 return rte_flow_error_set(error,
7404 RTE_FLOW_ERROR_TYPE_ACTION,
7407 "or invalid parameters");
7409 /* Set the meter action. */
7410 dev_flow->dv.actions[actions_n++] =
7411 flow->meter->mfts->meter_action;
7412 action_flags |= MLX5_FLOW_ACTION_METER;
7414 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
7415 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
7418 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
7420 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
7421 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
7424 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
7426 case RTE_FLOW_ACTION_TYPE_END:
7428 if (mhdr_res->actions_num) {
7429 /* create modify action if needed. */
7430 if (flow_dv_modify_hdr_resource_register
7431 (dev, mhdr_res, dev_flow, error))
7433 dev_flow->dv.actions[modify_action_position] =
7434 dev_flow->dv.modify_hdr->verbs_action;
7440 if (mhdr_res->actions_num &&
7441 modify_action_position == UINT32_MAX)
7442 modify_action_position = actions_n++;
7444 dev_flow->dv.actions_n = actions_n;
7445 dev_flow->actions = action_flags;
7446 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
7447 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
7448 int item_type = items->type;
7450 switch (item_type) {
7451 case RTE_FLOW_ITEM_TYPE_PORT_ID:
7452 flow_dv_translate_item_port_id(dev, match_mask,
7453 match_value, items);
7454 last_item = MLX5_FLOW_ITEM_PORT_ID;
7456 case RTE_FLOW_ITEM_TYPE_ETH:
7457 flow_dv_translate_item_eth(match_mask, match_value,
7459 matcher.priority = MLX5_PRIORITY_MAP_L2;
7460 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
7461 MLX5_FLOW_LAYER_OUTER_L2;
7463 case RTE_FLOW_ITEM_TYPE_VLAN:
7464 flow_dv_translate_item_vlan(dev_flow,
7465 match_mask, match_value,
7467 matcher.priority = MLX5_PRIORITY_MAP_L2;
7468 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
7469 MLX5_FLOW_LAYER_INNER_VLAN) :
7470 (MLX5_FLOW_LAYER_OUTER_L2 |
7471 MLX5_FLOW_LAYER_OUTER_VLAN);
7473 case RTE_FLOW_ITEM_TYPE_IPV4:
7474 mlx5_flow_tunnel_ip_check(items, next_protocol,
7475 &item_flags, &tunnel);
7476 flow_dv_translate_item_ipv4(match_mask, match_value,
7479 matcher.priority = MLX5_PRIORITY_MAP_L3;
7480 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
7481 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
7482 if (items->mask != NULL &&
7483 ((const struct rte_flow_item_ipv4 *)
7484 items->mask)->hdr.next_proto_id) {
7486 ((const struct rte_flow_item_ipv4 *)
7487 (items->spec))->hdr.next_proto_id;
7489 ((const struct rte_flow_item_ipv4 *)
7490 (items->mask))->hdr.next_proto_id;
7492 /* Reset for inner layer. */
7493 next_protocol = 0xff;
7496 case RTE_FLOW_ITEM_TYPE_IPV6:
7497 mlx5_flow_tunnel_ip_check(items, next_protocol,
7498 &item_flags, &tunnel);
7499 flow_dv_translate_item_ipv6(match_mask, match_value,
7502 matcher.priority = MLX5_PRIORITY_MAP_L3;
7503 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
7504 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
7505 if (items->mask != NULL &&
7506 ((const struct rte_flow_item_ipv6 *)
7507 items->mask)->hdr.proto) {
7509 ((const struct rte_flow_item_ipv6 *)
7510 items->spec)->hdr.proto;
7512 ((const struct rte_flow_item_ipv6 *)
7513 items->mask)->hdr.proto;
7515 /* Reset for inner layer. */
7516 next_protocol = 0xff;
7519 case RTE_FLOW_ITEM_TYPE_TCP:
7520 flow_dv_translate_item_tcp(match_mask, match_value,
7522 matcher.priority = MLX5_PRIORITY_MAP_L4;
7523 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
7524 MLX5_FLOW_LAYER_OUTER_L4_TCP;
7526 case RTE_FLOW_ITEM_TYPE_UDP:
7527 flow_dv_translate_item_udp(match_mask, match_value,
7529 matcher.priority = MLX5_PRIORITY_MAP_L4;
7530 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
7531 MLX5_FLOW_LAYER_OUTER_L4_UDP;
7533 case RTE_FLOW_ITEM_TYPE_GRE:
7534 flow_dv_translate_item_gre(match_mask, match_value,
7536 last_item = MLX5_FLOW_LAYER_GRE;
7538 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
7539 flow_dv_translate_item_gre_key(match_mask,
7540 match_value, items);
7541 last_item = MLX5_FLOW_LAYER_GRE_KEY;
7543 case RTE_FLOW_ITEM_TYPE_NVGRE:
7544 flow_dv_translate_item_nvgre(match_mask, match_value,
7546 last_item = MLX5_FLOW_LAYER_GRE;
7548 case RTE_FLOW_ITEM_TYPE_VXLAN:
7549 flow_dv_translate_item_vxlan(match_mask, match_value,
7551 last_item = MLX5_FLOW_LAYER_VXLAN;
7553 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
7554 flow_dv_translate_item_vxlan(match_mask, match_value,
7556 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
7558 case RTE_FLOW_ITEM_TYPE_GENEVE:
7559 flow_dv_translate_item_geneve(match_mask, match_value,
7561 last_item = MLX5_FLOW_LAYER_GENEVE;
7563 case RTE_FLOW_ITEM_TYPE_MPLS:
7564 flow_dv_translate_item_mpls(match_mask, match_value,
7565 items, last_item, tunnel);
7566 last_item = MLX5_FLOW_LAYER_MPLS;
7568 case RTE_FLOW_ITEM_TYPE_MARK:
7569 flow_dv_translate_item_mark(dev, match_mask,
7570 match_value, items);
7571 last_item = MLX5_FLOW_ITEM_MARK;
7573 case RTE_FLOW_ITEM_TYPE_META:
7574 flow_dv_translate_item_meta(dev, match_mask,
7575 match_value, attr, items);
7576 last_item = MLX5_FLOW_ITEM_METADATA;
7578 case RTE_FLOW_ITEM_TYPE_ICMP:
7579 flow_dv_translate_item_icmp(match_mask, match_value,
7581 last_item = MLX5_FLOW_LAYER_ICMP;
7583 case RTE_FLOW_ITEM_TYPE_ICMP6:
7584 flow_dv_translate_item_icmp6(match_mask, match_value,
7586 last_item = MLX5_FLOW_LAYER_ICMP6;
7588 case RTE_FLOW_ITEM_TYPE_TAG:
7589 flow_dv_translate_item_tag(dev, match_mask,
7590 match_value, items);
7591 last_item = MLX5_FLOW_ITEM_TAG;
7593 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
7594 flow_dv_translate_mlx5_item_tag(dev, match_mask,
7595 match_value, items);
7596 last_item = MLX5_FLOW_ITEM_TAG;
7598 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
7599 flow_dv_translate_item_tx_queue(dev, match_mask,
7602 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
7604 case RTE_FLOW_ITEM_TYPE_GTP:
7605 flow_dv_translate_item_gtp(match_mask, match_value,
7607 last_item = MLX5_FLOW_LAYER_GTP;
7612 item_flags |= last_item;
7615 * When E-Switch mode is enabled, we have two cases where we need to
7616 * set the source port manually.
7617 * The first one, is in case of Nic steering rule, and the second is
7618 * E-Switch rule where no port_id item was found. In both cases
7619 * the source port is set according the current port in use.
7621 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
7622 (priv->representor || priv->master)) {
7623 if (flow_dv_translate_item_port_id(dev, match_mask,
7627 assert(!flow_dv_check_valid_spec(matcher.mask.buf,
7628 dev_flow->dv.value.buf));
7629 dev_flow->layers = item_flags;
7630 if (action_flags & MLX5_FLOW_ACTION_RSS)
7631 flow_dv_hashfields_set(dev_flow);
7632 /* Register matcher. */
7633 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
7635 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
7637 /* reserved field no needs to be set to 0 here. */
7638 tbl_key.domain = attr->transfer;
7639 tbl_key.direction = attr->egress;
7640 tbl_key.table_id = dev_flow->group;
7641 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
7647 * Apply the flow to the NIC, lock free,
7648 * (mutex should be acquired by caller).
7651 * Pointer to the Ethernet device structure.
7652 * @param[in, out] flow
7653 * Pointer to flow structure.
7655 * Pointer to error structure.
7658 * 0 on success, a negative errno value otherwise and rte_errno is set.
7661 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
7662 struct rte_flow_error *error)
7664 struct mlx5_flow_dv *dv;
7665 struct mlx5_flow *dev_flow;
7666 struct mlx5_priv *priv = dev->data->dev_private;
7670 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7673 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP) {
7674 if (dev_flow->transfer) {
7675 dv->actions[n++] = priv->sh->esw_drop_action;
7677 dv->hrxq = mlx5_hrxq_drop_new(dev);
7681 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7683 "cannot get drop hash queue");
7686 dv->actions[n++] = dv->hrxq->action;
7688 } else if (dev_flow->actions &
7689 (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
7690 struct mlx5_hrxq *hrxq;
7692 assert(flow->rss.queue);
7693 hrxq = mlx5_hrxq_get(dev, flow->rss.key,
7694 MLX5_RSS_HASH_KEY_LEN,
7695 dev_flow->hash_fields,
7697 flow->rss.queue_num);
7699 hrxq = mlx5_hrxq_new
7700 (dev, flow->rss.key,
7701 MLX5_RSS_HASH_KEY_LEN,
7702 dev_flow->hash_fields,
7704 flow->rss.queue_num,
7705 !!(dev_flow->layers &
7706 MLX5_FLOW_LAYER_TUNNEL));
7711 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7712 "cannot get hash queue");
7716 dv->actions[n++] = dv->hrxq->action;
7719 mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
7720 (void *)&dv->value, n,
7723 rte_flow_error_set(error, errno,
7724 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7726 "hardware refuses to create flow");
7729 if (priv->vmwa_context &&
7730 dev_flow->dv.vf_vlan.tag &&
7731 !dev_flow->dv.vf_vlan.created) {
7733 * The rule contains the VLAN pattern.
7734 * For VF we are going to create VLAN
7735 * interface to make hypervisor set correct
7736 * e-Switch vport context.
7738 mlx5_vlan_vmwa_acquire(dev, &dev_flow->dv.vf_vlan);
7743 err = rte_errno; /* Save rte_errno before cleanup. */
7744 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7745 struct mlx5_flow_dv *dv = &dev_flow->dv;
7747 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7748 mlx5_hrxq_drop_release(dev);
7750 mlx5_hrxq_release(dev, dv->hrxq);
7753 if (dev_flow->dv.vf_vlan.tag &&
7754 dev_flow->dv.vf_vlan.created)
7755 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7757 rte_errno = err; /* Restore rte_errno. */
7762 * Release the flow matcher.
7765 * Pointer to Ethernet device.
7767 * Pointer to mlx5_flow.
7770 * 1 while a reference on it exists, 0 when freed.
7773 flow_dv_matcher_release(struct rte_eth_dev *dev,
7774 struct mlx5_flow *flow)
7776 struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
7778 assert(matcher->matcher_object);
7779 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
7780 dev->data->port_id, (void *)matcher,
7781 rte_atomic32_read(&matcher->refcnt));
7782 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
7783 claim_zero(mlx5_glue->dv_destroy_flow_matcher
7784 (matcher->matcher_object));
7785 LIST_REMOVE(matcher, next);
7786 /* table ref-- in release interface. */
7787 flow_dv_tbl_resource_release(dev, matcher->tbl);
7789 DRV_LOG(DEBUG, "port %u matcher %p: removed",
7790 dev->data->port_id, (void *)matcher);
7797 * Release an encap/decap resource.
7800 * Pointer to mlx5_flow.
7803 * 1 while a reference on it exists, 0 when freed.
7806 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
7808 struct mlx5_flow_dv_encap_decap_resource *cache_resource =
7809 flow->dv.encap_decap;
7811 assert(cache_resource->verbs_action);
7812 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
7813 (void *)cache_resource,
7814 rte_atomic32_read(&cache_resource->refcnt));
7815 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7816 claim_zero(mlx5_glue->destroy_flow_action
7817 (cache_resource->verbs_action));
7818 LIST_REMOVE(cache_resource, next);
7819 rte_free(cache_resource);
7820 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
7821 (void *)cache_resource);
7828 * Release an jump to table action resource.
7831 * Pointer to Ethernet device.
7833 * Pointer to mlx5_flow.
7836 * 1 while a reference on it exists, 0 when freed.
7839 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
7840 struct mlx5_flow *flow)
7842 struct mlx5_flow_dv_jump_tbl_resource *cache_resource = flow->dv.jump;
7843 struct mlx5_flow_tbl_data_entry *tbl_data =
7844 container_of(cache_resource,
7845 struct mlx5_flow_tbl_data_entry, jump);
7847 assert(cache_resource->action);
7848 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
7849 (void *)cache_resource,
7850 rte_atomic32_read(&cache_resource->refcnt));
7851 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7852 claim_zero(mlx5_glue->destroy_flow_action
7853 (cache_resource->action));
7854 /* jump action memory free is inside the table release. */
7855 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
7856 DRV_LOG(DEBUG, "jump table resource %p: removed",
7857 (void *)cache_resource);
7864 * Release a modify-header resource.
7867 * Pointer to mlx5_flow.
7870 * 1 while a reference on it exists, 0 when freed.
7873 flow_dv_modify_hdr_resource_release(struct mlx5_flow *flow)
7875 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
7876 flow->dv.modify_hdr;
7878 assert(cache_resource->verbs_action);
7879 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
7880 (void *)cache_resource,
7881 rte_atomic32_read(&cache_resource->refcnt));
7882 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7883 claim_zero(mlx5_glue->destroy_flow_action
7884 (cache_resource->verbs_action));
7885 LIST_REMOVE(cache_resource, next);
7886 rte_free(cache_resource);
7887 DRV_LOG(DEBUG, "modify-header resource %p: removed",
7888 (void *)cache_resource);
7895 * Release port ID action resource.
7898 * Pointer to mlx5_flow.
7901 * 1 while a reference on it exists, 0 when freed.
7904 flow_dv_port_id_action_resource_release(struct mlx5_flow *flow)
7906 struct mlx5_flow_dv_port_id_action_resource *cache_resource =
7907 flow->dv.port_id_action;
7909 assert(cache_resource->action);
7910 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
7911 (void *)cache_resource,
7912 rte_atomic32_read(&cache_resource->refcnt));
7913 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7914 claim_zero(mlx5_glue->destroy_flow_action
7915 (cache_resource->action));
7916 LIST_REMOVE(cache_resource, next);
7917 rte_free(cache_resource);
7918 DRV_LOG(DEBUG, "port id action resource %p: removed",
7919 (void *)cache_resource);
7926 * Release push vlan action resource.
7929 * Pointer to mlx5_flow.
7932 * 1 while a reference on it exists, 0 when freed.
7935 flow_dv_push_vlan_action_resource_release(struct mlx5_flow *flow)
7937 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource =
7938 flow->dv.push_vlan_res;
7940 assert(cache_resource->action);
7941 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
7942 (void *)cache_resource,
7943 rte_atomic32_read(&cache_resource->refcnt));
7944 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
7945 claim_zero(mlx5_glue->destroy_flow_action
7946 (cache_resource->action));
7947 LIST_REMOVE(cache_resource, next);
7948 rte_free(cache_resource);
7949 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
7950 (void *)cache_resource);
7957 * Remove the flow from the NIC but keeps it in memory.
7958 * Lock free, (mutex should be acquired by caller).
7961 * Pointer to Ethernet device.
7962 * @param[in, out] flow
7963 * Pointer to flow structure.
7966 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
7968 struct mlx5_flow_dv *dv;
7969 struct mlx5_flow *dev_flow;
7973 LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
7976 claim_zero(mlx5_glue->dv_destroy_flow(dv->flow));
7980 if (dev_flow->actions & MLX5_FLOW_ACTION_DROP)
7981 mlx5_hrxq_drop_release(dev);
7983 mlx5_hrxq_release(dev, dv->hrxq);
7986 if (dev_flow->dv.vf_vlan.tag &&
7987 dev_flow->dv.vf_vlan.created)
7988 mlx5_vlan_vmwa_release(dev, &dev_flow->dv.vf_vlan);
7993 * Remove the flow from the NIC and the memory.
7994 * Lock free, (mutex should be acquired by caller).
7997 * Pointer to the Ethernet device structure.
7998 * @param[in, out] flow
7999 * Pointer to flow structure.
8002 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8004 struct mlx5_flow *dev_flow;
8008 __flow_dv_remove(dev, flow);
8009 if (flow->counter) {
8010 flow_dv_counter_release(dev, flow->counter);
8011 flow->counter = NULL;
8014 mlx5_flow_meter_detach(flow->meter);
8017 while (!LIST_EMPTY(&flow->dev_flows)) {
8018 dev_flow = LIST_FIRST(&flow->dev_flows);
8019 LIST_REMOVE(dev_flow, next);
8020 if (dev_flow->dv.matcher)
8021 flow_dv_matcher_release(dev, dev_flow);
8022 if (dev_flow->dv.encap_decap)
8023 flow_dv_encap_decap_resource_release(dev_flow);
8024 if (dev_flow->dv.modify_hdr)
8025 flow_dv_modify_hdr_resource_release(dev_flow);
8026 if (dev_flow->dv.jump)
8027 flow_dv_jump_tbl_resource_release(dev, dev_flow);
8028 if (dev_flow->dv.port_id_action)
8029 flow_dv_port_id_action_resource_release(dev_flow);
8030 if (dev_flow->dv.push_vlan_res)
8031 flow_dv_push_vlan_action_resource_release(dev_flow);
8032 if (dev_flow->dv.tag_resource)
8033 flow_dv_tag_release(dev, dev_flow->dv.tag_resource);
8039 * Query a dv flow rule for its statistics via devx.
8042 * Pointer to Ethernet device.
8044 * Pointer to the sub flow.
8046 * data retrieved by the query.
8048 * Perform verbose error reporting if not NULL.
8051 * 0 on success, a negative errno value otherwise and rte_errno is set.
8054 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
8055 void *data, struct rte_flow_error *error)
8057 struct mlx5_priv *priv = dev->data->dev_private;
8058 struct rte_flow_query_count *qc = data;
8060 if (!priv->config.devx)
8061 return rte_flow_error_set(error, ENOTSUP,
8062 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8064 "counters are not supported");
8065 if (flow->counter) {
8066 uint64_t pkts, bytes;
8067 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
8071 return rte_flow_error_set(error, -err,
8072 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8073 NULL, "cannot read counters");
8076 qc->hits = pkts - flow->counter->hits;
8077 qc->bytes = bytes - flow->counter->bytes;
8079 flow->counter->hits = pkts;
8080 flow->counter->bytes = bytes;
8084 return rte_flow_error_set(error, EINVAL,
8085 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8087 "counters are not available");
8093 * @see rte_flow_query()
8097 flow_dv_query(struct rte_eth_dev *dev,
8098 struct rte_flow *flow __rte_unused,
8099 const struct rte_flow_action *actions __rte_unused,
8100 void *data __rte_unused,
8101 struct rte_flow_error *error __rte_unused)
8105 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
8106 switch (actions->type) {
8107 case RTE_FLOW_ACTION_TYPE_VOID:
8109 case RTE_FLOW_ACTION_TYPE_COUNT:
8110 ret = flow_dv_query_count(dev, flow, data, error);
8113 return rte_flow_error_set(error, ENOTSUP,
8114 RTE_FLOW_ERROR_TYPE_ACTION,
8116 "action not supported");
8123 * Destroy the meter table set.
8124 * Lock free, (mutex should be acquired by caller).
8127 * Pointer to Ethernet device.
8129 * Pointer to the meter table set.
8135 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
8136 struct mlx5_meter_domains_infos *tbl)
8138 struct mlx5_priv *priv = dev->data->dev_private;
8139 struct mlx5_meter_domains_infos *mtd =
8140 (struct mlx5_meter_domains_infos *)tbl;
8142 if (!mtd || !priv->config.dv_flow_en)
8144 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
8145 claim_zero(mlx5_glue->dv_destroy_flow
8146 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
8147 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
8148 claim_zero(mlx5_glue->dv_destroy_flow
8149 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
8150 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
8151 claim_zero(mlx5_glue->dv_destroy_flow
8152 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
8153 if (mtd->egress.color_matcher)
8154 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8155 (mtd->egress.color_matcher));
8156 if (mtd->egress.any_matcher)
8157 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8158 (mtd->egress.any_matcher));
8159 if (mtd->egress.tbl)
8160 claim_zero(flow_dv_tbl_resource_release(dev,
8162 if (mtd->ingress.color_matcher)
8163 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8164 (mtd->ingress.color_matcher));
8165 if (mtd->ingress.any_matcher)
8166 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8167 (mtd->ingress.any_matcher));
8168 if (mtd->ingress.tbl)
8169 claim_zero(flow_dv_tbl_resource_release(dev,
8171 if (mtd->transfer.color_matcher)
8172 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8173 (mtd->transfer.color_matcher));
8174 if (mtd->transfer.any_matcher)
8175 claim_zero(mlx5_glue->dv_destroy_flow_matcher
8176 (mtd->transfer.any_matcher));
8177 if (mtd->transfer.tbl)
8178 claim_zero(flow_dv_tbl_resource_release(dev,
8179 mtd->transfer.tbl));
8181 claim_zero(mlx5_glue->destroy_flow_action(mtd->drop_actn));
8186 /* Number of meter flow actions, count and jump or count and drop. */
8187 #define METER_ACTIONS 2
8190 * Create specify domain meter table and suffix table.
8193 * Pointer to Ethernet device.
8194 * @param[in,out] mtb
8195 * Pointer to DV meter table set.
8198 * @param[in] transfer
8200 * @param[in] color_reg_c_idx
8201 * Reg C index for color match.
8204 * 0 on success, -1 otherwise and rte_errno is set.
8207 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
8208 struct mlx5_meter_domains_infos *mtb,
8209 uint8_t egress, uint8_t transfer,
8210 uint32_t color_reg_c_idx)
8212 struct mlx5_priv *priv = dev->data->dev_private;
8213 struct mlx5_ibv_shared *sh = priv->sh;
8214 struct mlx5_flow_dv_match_params mask = {
8215 .size = sizeof(mask.buf),
8217 struct mlx5_flow_dv_match_params value = {
8218 .size = sizeof(value.buf),
8220 struct mlx5dv_flow_matcher_attr dv_attr = {
8221 .type = IBV_FLOW_ATTR_NORMAL,
8223 .match_criteria_enable = 0,
8224 .match_mask = (void *)&mask,
8226 void *actions[METER_ACTIONS];
8227 struct mlx5_flow_tbl_resource **sfx_tbl;
8228 struct mlx5_meter_domain_info *dtb;
8229 struct rte_flow_error error;
8233 sfx_tbl = &sh->fdb_mtr_sfx_tbl;
8234 dtb = &mtb->transfer;
8235 } else if (egress) {
8236 sfx_tbl = &sh->tx_mtr_sfx_tbl;
8239 sfx_tbl = &sh->rx_mtr_sfx_tbl;
8240 dtb = &mtb->ingress;
8242 /* If the suffix table in missing, create it. */
8244 *sfx_tbl = flow_dv_tbl_resource_get(dev,
8245 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
8246 egress, transfer, &error);
8248 DRV_LOG(ERR, "Failed to create meter suffix table.");
8252 /* Create the meter table with METER level. */
8253 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
8254 egress, transfer, &error);
8256 DRV_LOG(ERR, "Failed to create meter policer table.");
8259 /* Create matchers, Any and Color. */
8260 dv_attr.priority = 3;
8261 dv_attr.match_criteria_enable = 0;
8262 dtb->any_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8265 if (!dtb->any_matcher) {
8266 DRV_LOG(ERR, "Failed to create meter"
8267 " policer default matcher.");
8270 dv_attr.priority = 0;
8271 dv_attr.match_criteria_enable =
8272 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
8273 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
8274 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
8275 dtb->color_matcher = mlx5_glue->dv_create_flow_matcher(sh->ctx,
8278 if (!dtb->color_matcher) {
8279 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
8282 if (mtb->count_actns[RTE_MTR_DROPPED])
8283 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
8284 actions[i++] = mtb->drop_actn;
8285 /* Default rule: lowest priority, match any, actions: drop. */
8286 dtb->policer_rules[RTE_MTR_DROPPED] =
8287 mlx5_glue->dv_create_flow(dtb->any_matcher,
8288 (void *)&value, i, actions);
8289 if (!dtb->policer_rules[RTE_MTR_DROPPED]) {
8290 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
8299 * Create the needed meter and suffix tables.
8300 * Lock free, (mutex should be acquired by caller).
8303 * Pointer to Ethernet device.
8305 * Pointer to the flow meter.
8308 * Pointer to table set on success, NULL otherwise and rte_errno is set.
8310 static struct mlx5_meter_domains_infos *
8311 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
8312 const struct mlx5_flow_meter *fm)
8314 struct mlx5_priv *priv = dev->data->dev_private;
8315 struct mlx5_meter_domains_infos *mtb;
8319 if (!priv->mtr_en) {
8320 rte_errno = ENOTSUP;
8323 mtb = rte_calloc(__func__, 1, sizeof(*mtb), 0);
8325 DRV_LOG(ERR, "Failed to allocate memory for meter.");
8328 /* Create meter count actions */
8329 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
8330 if (!fm->policer_stats.cnt[i])
8332 mtb->count_actns[i] = fm->policer_stats.cnt[i]->action;
8334 /* Create drop action. */
8335 mtb->drop_actn = mlx5_glue->dr_create_flow_action_drop();
8336 if (!mtb->drop_actn) {
8337 DRV_LOG(ERR, "Failed to create drop action.");
8340 /* Egress meter table. */
8341 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
8343 DRV_LOG(ERR, "Failed to prepare egress meter table.");
8346 /* Ingress meter table. */
8347 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
8349 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
8352 /* FDB meter table. */
8353 if (priv->config.dv_esw_en) {
8354 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
8355 priv->mtr_color_reg);
8357 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
8363 flow_dv_destroy_mtr_tbl(dev, mtb);
8368 * Destroy domain policer rule.
8371 * Pointer to domain table.
8374 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
8378 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8379 if (dt->policer_rules[i]) {
8380 claim_zero(mlx5_glue->dv_destroy_flow
8381 (dt->policer_rules[i]));
8382 dt->policer_rules[i] = NULL;
8385 if (dt->jump_actn) {
8386 claim_zero(mlx5_glue->destroy_flow_action(dt->jump_actn));
8387 dt->jump_actn = NULL;
8392 * Destroy policer rules.
8395 * Pointer to Ethernet device.
8397 * Pointer to flow meter structure.
8399 * Pointer to flow attributes.
8405 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
8406 const struct mlx5_flow_meter *fm,
8407 const struct rte_flow_attr *attr)
8409 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
8414 flow_dv_destroy_domain_policer_rule(&mtb->egress);
8416 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
8418 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
8423 * Create specify domain meter policer rule.
8426 * Pointer to flow meter structure.
8428 * Pointer to DV meter table set.
8430 * Pointer to suffix table.
8431 * @param[in] mtr_reg_c
8432 * Color match REG_C.
8435 * 0 on success, -1 otherwise.
8438 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
8439 struct mlx5_meter_domain_info *dtb,
8440 struct mlx5_flow_tbl_resource *sfx_tb,
8443 struct mlx5_flow_dv_match_params matcher = {
8444 .size = sizeof(matcher.buf),
8446 struct mlx5_flow_dv_match_params value = {
8447 .size = sizeof(value.buf),
8449 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8450 void *actions[METER_ACTIONS];
8453 /* Create jump action. */
8456 if (!dtb->jump_actn)
8458 mlx5_glue->dr_create_flow_action_dest_flow_tbl
8460 if (!dtb->jump_actn) {
8461 DRV_LOG(ERR, "Failed to create policer jump action.");
8464 for (i = 0; i < RTE_MTR_DROPPED; i++) {
8467 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
8468 rte_col_2_mlx5_col(i), UINT8_MAX);
8469 if (mtb->count_actns[i])
8470 actions[j++] = mtb->count_actns[i];
8471 if (fm->params.action[i] == MTR_POLICER_ACTION_DROP)
8472 actions[j++] = mtb->drop_actn;
8474 actions[j++] = dtb->jump_actn;
8475 dtb->policer_rules[i] =
8476 mlx5_glue->dv_create_flow(dtb->color_matcher,
8479 if (!dtb->policer_rules[i]) {
8480 DRV_LOG(ERR, "Failed to create policer rule.");
8491 * Create policer rules.
8494 * Pointer to Ethernet device.
8496 * Pointer to flow meter structure.
8498 * Pointer to flow attributes.
8501 * 0 on success, -1 otherwise.
8504 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
8505 struct mlx5_flow_meter *fm,
8506 const struct rte_flow_attr *attr)
8508 struct mlx5_priv *priv = dev->data->dev_private;
8509 struct mlx5_meter_domains_infos *mtb = fm->mfts;
8513 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
8514 priv->sh->tx_mtr_sfx_tbl,
8515 priv->mtr_color_reg);
8517 DRV_LOG(ERR, "Failed to create egress policer.");
8521 if (attr->ingress) {
8522 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
8523 priv->sh->rx_mtr_sfx_tbl,
8524 priv->mtr_color_reg);
8526 DRV_LOG(ERR, "Failed to create ingress policer.");
8530 if (attr->transfer) {
8531 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
8532 priv->sh->fdb_mtr_sfx_tbl,
8533 priv->mtr_color_reg);
8535 DRV_LOG(ERR, "Failed to create transfer policer.");
8541 flow_dv_destroy_policer_rules(dev, fm, attr);
8546 * Query a devx counter.
8549 * Pointer to the Ethernet device structure.
8551 * Pointer to the flow counter.
8553 * Set to clear the counter statistics.
8555 * The statistics value of packets.
8557 * The statistics value of bytes.
8560 * 0 on success, otherwise return -1.
8563 flow_dv_counter_query(struct rte_eth_dev *dev,
8564 struct mlx5_flow_counter *cnt, bool clear,
8565 uint64_t *pkts, uint64_t *bytes)
8567 struct mlx5_priv *priv = dev->data->dev_private;
8568 uint64_t inn_pkts, inn_bytes;
8571 if (!priv->config.devx)
8573 ret = _flow_dv_query_count(dev, cnt, &inn_pkts, &inn_bytes);
8576 *pkts = inn_pkts - cnt->hits;
8577 *bytes = inn_bytes - cnt->bytes;
8579 cnt->hits = inn_pkts;
8580 cnt->bytes = inn_bytes;
8586 * Mutex-protected thunk to lock-free __flow_dv_translate().
8589 flow_dv_translate(struct rte_eth_dev *dev,
8590 struct mlx5_flow *dev_flow,
8591 const struct rte_flow_attr *attr,
8592 const struct rte_flow_item items[],
8593 const struct rte_flow_action actions[],
8594 struct rte_flow_error *error)
8598 flow_dv_shared_lock(dev);
8599 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
8600 flow_dv_shared_unlock(dev);
8605 * Mutex-protected thunk to lock-free __flow_dv_apply().
8608 flow_dv_apply(struct rte_eth_dev *dev,
8609 struct rte_flow *flow,
8610 struct rte_flow_error *error)
8614 flow_dv_shared_lock(dev);
8615 ret = __flow_dv_apply(dev, flow, error);
8616 flow_dv_shared_unlock(dev);
8621 * Mutex-protected thunk to lock-free __flow_dv_remove().
8624 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
8626 flow_dv_shared_lock(dev);
8627 __flow_dv_remove(dev, flow);
8628 flow_dv_shared_unlock(dev);
8632 * Mutex-protected thunk to lock-free __flow_dv_destroy().
8635 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
8637 flow_dv_shared_lock(dev);
8638 __flow_dv_destroy(dev, flow);
8639 flow_dv_shared_unlock(dev);
8643 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
8645 static struct mlx5_flow_counter *
8646 flow_dv_counter_allocate(struct rte_eth_dev *dev)
8648 struct mlx5_flow_counter *cnt;
8650 flow_dv_shared_lock(dev);
8651 cnt = flow_dv_counter_alloc(dev, 0, 0, 1);
8652 flow_dv_shared_unlock(dev);
8657 * Mutex-protected thunk to lock-free flow_dv_counter_release().
8660 flow_dv_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt)
8662 flow_dv_shared_lock(dev);
8663 flow_dv_counter_release(dev, cnt);
8664 flow_dv_shared_unlock(dev);
8667 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
8668 .validate = flow_dv_validate,
8669 .prepare = flow_dv_prepare,
8670 .translate = flow_dv_translate,
8671 .apply = flow_dv_apply,
8672 .remove = flow_dv_remove,
8673 .destroy = flow_dv_destroy,
8674 .query = flow_dv_query,
8675 .create_mtr_tbls = flow_dv_create_mtr_tbl,
8676 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
8677 .create_policer_rules = flow_dv_create_policer_rules,
8678 .destroy_policer_rules = flow_dv_destroy_policer_rules,
8679 .counter_alloc = flow_dv_counter_allocate,
8680 .counter_free = flow_dv_counter_free,
8681 .counter_query = flow_dv_counter_query,
8684 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */