drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9
  10 /* Verbs header. */
  11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  12 #ifdef PEDANTIC
  13 #pragma GCC diagnostic ignored "-Wpedantic"
  14 #endif
  15 #include <infiniband/verbs.h>
  16 #ifdef PEDANTIC
  17 #pragma GCC diagnostic error "-Wpedantic"
  18 #endif
  19
  20 #include <rte_common.h>
  21 #include <rte_ether.h>
  22 #include <rte_eth_ctrl.h>
  23 #include <rte_ethdev_driver.h>
  24 #include <rte_flow.h>
  25 #include <rte_flow_driver.h>
  26 #include <rte_malloc.h>
  27 #include <rte_ip.h>
  28 #include <rte_gre.h>
  29
  30 #include "mlx5.h"
  31 #include "mlx5_defs.h"
  32 #include "mlx5_prm.h"
  33 #include "mlx5_glue.h"
  34 #include "mlx5_flow.h"
  35
  36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
  37
  38 /**
  39  * Validate META item.
  40  *
  41  * @param[in] dev
  42  *   Pointer to the rte_eth_dev structure.
  43  * @param[in] item
  44  *   Item specification.
  45  * @param[in] attr
  46  *   Attributes of flow that includes this item.
  47  * @param[out] error
  48  *   Pointer to error structure.
  49  *
  50  * @return
  51  *   0 on success, a negative errno value otherwise and rte_errno is set.
  52  */
  53 static int
  54 flow_dv_validate_item_meta(struct rte_eth_dev *dev,
  55                            const struct rte_flow_item *item,
  56                            const struct rte_flow_attr *attr,
  57                            struct rte_flow_error *error)
  58 {
  59         const struct rte_flow_item_meta *spec = item->spec;
  60         const struct rte_flow_item_meta *mask = item->mask;
  61         const struct rte_flow_item_meta nic_mask = {
  62                 .data = RTE_BE32(UINT32_MAX)
  63         };
  64         int ret;
  65         uint64_t offloads = dev->data->dev_conf.txmode.offloads;
  66
  67         if (!(offloads & DEV_TX_OFFLOAD_MATCH_METADATA))
  68                 return rte_flow_error_set(error, EPERM,
  69                                           RTE_FLOW_ERROR_TYPE_ITEM,
  70                                           NULL,
  71                                           "match on metadata offload "
  72                                           "configuration is off for this port");
  73         if (!spec)
  74                 return rte_flow_error_set(error, EINVAL,
  75                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
  76                                           item->spec,
  77                                           "data cannot be empty");
  78         if (!spec->data)
  79                 return rte_flow_error_set(error, EINVAL,
  80                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
  81                                           NULL,
  82                                           "data cannot be zero");
  83         if (!mask)
  84                 mask = &rte_flow_item_meta_mask;
  85         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
  86                                         (const uint8_t *)&nic_mask,
  87                                         sizeof(struct rte_flow_item_meta),
  88                                         error);
  89         if (ret < 0)
  90                 return ret;
  91         if (attr->ingress)
  92                 return rte_flow_error_set(error, ENOTSUP,
  93                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
  94                                           NULL,
  95                                           "pattern not supported for ingress");
  96         return 0;
  97 }
  98
  99 /**
 100  * Validate the L2 encap action.
 101  *
 102  * @param[in] action_flags
 103  *   Holds the actions detected until now.
 104  * @param[in] action
 105  *   Pointer to the encap action.
 106  * @param[in] attr
 107  *   Pointer to flow attributes
 108  * @param[out] error
 109  *   Pointer to error structure.
 110  *
 111  * @return
 112  *   0 on success, a negative errno value otherwise and rte_errno is set.
 113  */
 114 static int
 115 flow_dv_validate_action_l2_encap(uint64_t action_flags,
 116                                  const struct rte_flow_action *action,
 117                                  const struct rte_flow_attr *attr,
 118                                  struct rte_flow_error *error)
 119 {
 120         if (!(action->conf))
 121                 return rte_flow_error_set(error, EINVAL,
 122                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
 123                                           "configuration cannot be null");
 124         if (action_flags & MLX5_FLOW_ACTION_DROP)
 125                 return rte_flow_error_set(error, EINVAL,
 126                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 127                                           "can't drop and encap in same flow");
 128         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
 129                 return rte_flow_error_set(error, EINVAL,
 130                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 131                                           "can only have a single encap or"
 132                                           " decap action in a flow");
 133         if (attr->ingress)
 134                 return rte_flow_error_set(error, ENOTSUP,
 135                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
 136                                           NULL,
 137                                           "encap action not supported for "
 138                                           "ingress");
 139         return 0;
 140 }
 141
 142 /**
 143  * Validate the L2 decap action.
 144  *
 145  * @param[in] action_flags
 146  *   Holds the actions detected until now.
 147  * @param[in] attr
 148  *   Pointer to flow attributes
 149  * @param[out] error
 150  *   Pointer to error structure.
 151  *
 152  * @return
 153  *   0 on success, a negative errno value otherwise and rte_errno is set.
 154  */
 155 static int
 156 flow_dv_validate_action_l2_decap(uint64_t action_flags,
 157                                  const struct rte_flow_attr *attr,
 158                                  struct rte_flow_error *error)
 159 {
 160         if (action_flags & MLX5_FLOW_ACTION_DROP)
 161                 return rte_flow_error_set(error, EINVAL,
 162                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 163                                           "can't drop and decap in same flow");
 164         if (action_flags & (MLX5_FLOW_ENCAP_ACTIONS | MLX5_FLOW_DECAP_ACTIONS))
 165                 return rte_flow_error_set(error, EINVAL,
 166                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 167                                           "can only have a single encap or"
 168                                           " decap action in a flow");
 169         if (attr->egress)
 170                 return rte_flow_error_set(error, ENOTSUP,
 171                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
 172                                           NULL,
 173                                           "decap action not supported for "
 174                                           "egress");
 175         return 0;
 176 }
 177
 178 /**
 179  * Validate the raw encap action.
 180  *
 181  * @param[in] action_flags
 182  *   Holds the actions detected until now.
 183  * @param[in] action
 184  *   Pointer to the encap action.
 185  * @param[in] attr
 186  *   Pointer to flow attributes
 187  * @param[out] error
 188  *   Pointer to error structure.
 189  *
 190  * @return
 191  *   0 on success, a negative errno value otherwise and rte_errno is set.
 192  */
 193 static int
 194 flow_dv_validate_action_raw_encap(uint64_t action_flags,
 195                                   const struct rte_flow_action *action,
 196                                   const struct rte_flow_attr *attr,
 197                                   struct rte_flow_error *error)
 198 {
 199         if (!(action->conf))
 200                 return rte_flow_error_set(error, EINVAL,
 201                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
 202                                           "configuration cannot be null");
 203         if (action_flags & MLX5_FLOW_ACTION_DROP)
 204                 return rte_flow_error_set(error, EINVAL,
 205                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 206                                           "can't drop and encap in same flow");
 207         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
 208                 return rte_flow_error_set(error, EINVAL,
 209                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 210                                           "can only have a single encap"
 211                                           " action in a flow");
 212         /* encap without preceding decap is not supported for ingress */
 213         if (attr->ingress && !(action_flags & MLX5_FLOW_ACTION_RAW_DECAP))
 214                 return rte_flow_error_set(error, ENOTSUP,
 215                                           RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
 216                                           NULL,
 217                                           "encap action not supported for "
 218                                           "ingress");
 219         return 0;
 220 }
 221
 222 /**
 223  * Validate the raw decap action.
 224  *
 225  * @param[in] action_flags
 226  *   Holds the actions detected until now.
 227  * @param[in] action
 228  *   Pointer to the encap action.
 229  * @param[in] attr
 230  *   Pointer to flow attributes
 231  * @param[out] error
 232  *   Pointer to error structure.
 233  *
 234  * @return
 235  *   0 on success, a negative errno value otherwise and rte_errno is set.
 236  */
 237 static int
 238 flow_dv_validate_action_raw_decap(uint64_t action_flags,
 239                                   const struct rte_flow_action *action,
 240                                   const struct rte_flow_attr *attr,
 241                                   struct rte_flow_error *error)
 242 {
 243         if (action_flags & MLX5_FLOW_ACTION_DROP)
 244                 return rte_flow_error_set(error, EINVAL,
 245                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 246                                           "can't drop and decap in same flow");
 247         if (action_flags & MLX5_FLOW_ENCAP_ACTIONS)
 248                 return rte_flow_error_set(error, EINVAL,
 249                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 250                                           "can't have encap action before"
 251                                           " decap action");
 252         if (action_flags & MLX5_FLOW_DECAP_ACTIONS)
 253                 return rte_flow_error_set(error, EINVAL,
 254                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 255                                           "can only have a single decap"
 256                                           " action in a flow");
 257         /* decap action is valid on egress only if it is followed by encap */
 258         if (attr->egress) {
 259                 for (; action->type != RTE_FLOW_ACTION_TYPE_END &&
 260                        action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
 261                        action++) {
 262                 }
 263                 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP)
 264                         return rte_flow_error_set
 265                                         (error, ENOTSUP,
 266                                          RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
 267                                          NULL, "decap action not supported"
 268                                          " for egress");
 269         }
 270         return 0;
 271 }
 272
 273
 274 /**
 275  * Find existing encap/decap resource or create and register a new one.
 276  *
 277  * @param dev[in, out]
 278  *   Pointer to rte_eth_dev structure.
 279  * @param[in, out] resource
 280  *   Pointer to encap/decap resource.
 281  * @parm[in, out] dev_flow
 282  *   Pointer to the dev_flow.
 283  * @param[out] error
 284  *   pointer to error structure.
 285  *
 286  * @return
 287  *   0 on success otherwise -errno and errno is set.
 288  */
 289 static int
 290 flow_dv_encap_decap_resource_register
 291                         (struct rte_eth_dev *dev,
 292                          struct mlx5_flow_dv_encap_decap_resource *resource,
 293                          struct mlx5_flow *dev_flow,
 294                          struct rte_flow_error *error)
 295 {
 296         struct priv *priv = dev->data->dev_private;
 297         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
 298
 299         /* Lookup a matching resource from cache. */
 300         LIST_FOREACH(cache_resource, &priv->encaps_decaps, next) {
 301                 if (resource->reformat_type == cache_resource->reformat_type &&
 302                     resource->ft_type == cache_resource->ft_type &&
 303                     resource->size == cache_resource->size &&
 304                     !memcmp((const void *)resource->buf,
 305                             (const void *)cache_resource->buf,
 306                             resource->size)) {
 307                         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
 308                                 (void *)cache_resource,
 309                                 rte_atomic32_read(&cache_resource->refcnt));
 310                         rte_atomic32_inc(&cache_resource->refcnt);
 311                         dev_flow->dv.encap_decap = cache_resource;
 312                         return 0;
 313                 }
 314         }
 315         /* Register new encap/decap resource. */
 316         cache_resource = rte_calloc(__func__, 1, sizeof(*cache_resource), 0);
 317         if (!cache_resource)
 318                 return rte_flow_error_set(error, ENOMEM,
 319                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
 320                                           "cannot allocate resource memory");
 321         *cache_resource = *resource;
 322         cache_resource->verbs_action =
 323                 mlx5_glue->dv_create_flow_action_packet_reformat
 324                         (priv->ctx, cache_resource->size,
 325                          (cache_resource->size ? cache_resource->buf : NULL),
 326                          cache_resource->reformat_type,
 327                          cache_resource->ft_type);
 328         if (!cache_resource->verbs_action) {
 329                 rte_free(cache_resource);
 330                 return rte_flow_error_set(error, ENOMEM,
 331                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
 332                                           NULL, "cannot create action");
 333         }
 334         rte_atomic32_init(&cache_resource->refcnt);
 335         rte_atomic32_inc(&cache_resource->refcnt);
 336         LIST_INSERT_HEAD(&priv->encaps_decaps, cache_resource, next);
 337         dev_flow->dv.encap_decap = cache_resource;
 338         DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
 339                 (void *)cache_resource,
 340                 rte_atomic32_read(&cache_resource->refcnt));
 341         return 0;
 342 }
 343
 344 /**
 345  * Get the size of specific rte_flow_item_type
 346  *
 347  * @param[in] item_type
 348  *   Tested rte_flow_item_type.
 349  *
 350  * @return
 351  *   sizeof struct item_type, 0 if void or irrelevant.
 352  */
 353 static size_t
 354 flow_dv_get_item_len(const enum rte_flow_item_type item_type)
 355 {
 356         size_t retval;
 357
 358         switch (item_type) {
 359         case RTE_FLOW_ITEM_TYPE_ETH:
 360                 retval = sizeof(struct rte_flow_item_eth);
 361                 break;
 362         case RTE_FLOW_ITEM_TYPE_VLAN:
 363                 retval = sizeof(struct rte_flow_item_vlan);
 364                 break;
 365         case RTE_FLOW_ITEM_TYPE_IPV4:
 366                 retval = sizeof(struct rte_flow_item_ipv4);
 367                 break;
 368         case RTE_FLOW_ITEM_TYPE_IPV6:
 369                 retval = sizeof(struct rte_flow_item_ipv6);
 370                 break;
 371         case RTE_FLOW_ITEM_TYPE_UDP:
 372                 retval = sizeof(struct rte_flow_item_udp);
 373                 break;
 374         case RTE_FLOW_ITEM_TYPE_TCP:
 375                 retval = sizeof(struct rte_flow_item_tcp);
 376                 break;
 377         case RTE_FLOW_ITEM_TYPE_VXLAN:
 378                 retval = sizeof(struct rte_flow_item_vxlan);
 379                 break;
 380         case RTE_FLOW_ITEM_TYPE_GRE:
 381                 retval = sizeof(struct rte_flow_item_gre);
 382                 break;
 383         case RTE_FLOW_ITEM_TYPE_NVGRE:
 384                 retval = sizeof(struct rte_flow_item_nvgre);
 385                 break;
 386         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 387                 retval = sizeof(struct rte_flow_item_vxlan_gpe);
 388                 break;
 389         case RTE_FLOW_ITEM_TYPE_MPLS:
 390                 retval = sizeof(struct rte_flow_item_mpls);
 391                 break;
 392         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
 393         default:
 394                 retval = 0;
 395                 break;
 396         }
 397         return retval;
 398 }
 399
 400 #define MLX5_ENCAP_IPV4_VERSION         0x40
 401 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
 402 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
 403 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
 404 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
 405 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
 406 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
 407
 408 /**
 409  * Convert the encap action data from list of rte_flow_item to raw buffer
 410  *
 411  * @param[in] items
 412  *   Pointer to rte_flow_item objects list.
 413  * @param[out] buf
 414  *   Pointer to the output buffer.
 415  * @param[out] size
 416  *   Pointer to the output buffer size.
 417  * @param[out] error
 418  *   Pointer to the error structure.
 419  *
 420  * @return
 421  *   0 on success, a negative errno value otherwise and rte_errno is set.
 422  */
 423 static int
 424 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
 425                            size_t *size, struct rte_flow_error *error)
 426 {
 427         struct ether_hdr *eth = NULL;
 428         struct vlan_hdr *vlan = NULL;
 429         struct ipv4_hdr *ipv4 = NULL;
 430         struct ipv6_hdr *ipv6 = NULL;
 431         struct udp_hdr *udp = NULL;
 432         struct vxlan_hdr *vxlan = NULL;
 433         struct vxlan_gpe_hdr *vxlan_gpe = NULL;
 434         struct gre_hdr *gre = NULL;
 435         size_t len;
 436         size_t temp_size = 0;
 437
 438         if (!items)
 439                 return rte_flow_error_set(error, EINVAL,
 440                                           RTE_FLOW_ERROR_TYPE_ACTION,
 441                                           NULL, "invalid empty data");
 442         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
 443                 len = flow_dv_get_item_len(items->type);
 444                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
 445                         return rte_flow_error_set(error, EINVAL,
 446                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 447                                                   (void *)items->type,
 448                                                   "items total size is too big"
 449                                                   " for encap action");
 450                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
 451                 switch (items->type) {
 452                 case RTE_FLOW_ITEM_TYPE_ETH:
 453                         eth = (struct ether_hdr *)&buf[temp_size];
 454                         break;
 455                 case RTE_FLOW_ITEM_TYPE_VLAN:
 456                         vlan = (struct vlan_hdr *)&buf[temp_size];
 457                         if (!eth)
 458                                 return rte_flow_error_set(error, EINVAL,
 459                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 460                                                 (void *)items->type,
 461                                                 "eth header not found");
 462                         if (!eth->ether_type)
 463                                 eth->ether_type = RTE_BE16(ETHER_TYPE_VLAN);
 464                         break;
 465                 case RTE_FLOW_ITEM_TYPE_IPV4:
 466                         ipv4 = (struct ipv4_hdr *)&buf[temp_size];
 467                         if (!vlan && !eth)
 468                                 return rte_flow_error_set(error, EINVAL,
 469                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 470                                                 (void *)items->type,
 471                                                 "neither eth nor vlan"
 472                                                 " header found");
 473                         if (vlan && !vlan->eth_proto)
 474                                 vlan->eth_proto = RTE_BE16(ETHER_TYPE_IPv4);
 475                         else if (eth && !eth->ether_type)
 476                                 eth->ether_type = RTE_BE16(ETHER_TYPE_IPv4);
 477                         if (!ipv4->version_ihl)
 478                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
 479                                                     MLX5_ENCAP_IPV4_IHL_MIN;
 480                         if (!ipv4->time_to_live)
 481                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
 482                         break;
 483                 case RTE_FLOW_ITEM_TYPE_IPV6:
 484                         ipv6 = (struct ipv6_hdr *)&buf[temp_size];
 485                         if (!vlan && !eth)
 486                                 return rte_flow_error_set(error, EINVAL,
 487                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 488                                                 (void *)items->type,
 489                                                 "neither eth nor vlan"
 490                                                 " header found");
 491                         if (vlan && !vlan->eth_proto)
 492                                 vlan->eth_proto = RTE_BE16(ETHER_TYPE_IPv6);
 493                         else if (eth && !eth->ether_type)
 494                                 eth->ether_type = RTE_BE16(ETHER_TYPE_IPv6);
 495                         if (!ipv6->vtc_flow)
 496                                 ipv6->vtc_flow =
 497                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
 498                         if (!ipv6->hop_limits)
 499                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
 500                         break;
 501                 case RTE_FLOW_ITEM_TYPE_UDP:
 502                         udp = (struct udp_hdr *)&buf[temp_size];
 503                         if (!ipv4 && !ipv6)
 504                                 return rte_flow_error_set(error, EINVAL,
 505                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 506                                                 (void *)items->type,
 507                                                 "ip header not found");
 508                         if (ipv4 && !ipv4->next_proto_id)
 509                                 ipv4->next_proto_id = IPPROTO_UDP;
 510                         else if (ipv6 && !ipv6->proto)
 511                                 ipv6->proto = IPPROTO_UDP;
 512                         break;
 513                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 514                         vxlan = (struct vxlan_hdr *)&buf[temp_size];
 515                         if (!udp)
 516                                 return rte_flow_error_set(error, EINVAL,
 517                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 518                                                 (void *)items->type,
 519                                                 "udp header not found");
 520                         if (!udp->dst_port)
 521                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
 522                         if (!vxlan->vx_flags)
 523                                 vxlan->vx_flags =
 524                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
 525                         break;
 526                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 527                         vxlan_gpe = (struct vxlan_gpe_hdr *)&buf[temp_size];
 528                         if (!udp)
 529                                 return rte_flow_error_set(error, EINVAL,
 530                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 531                                                 (void *)items->type,
 532                                                 "udp header not found");
 533                         if (!vxlan_gpe->proto)
 534                                 return rte_flow_error_set(error, EINVAL,
 535                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 536                                                 (void *)items->type,
 537                                                 "next protocol not found");
 538                         if (!udp->dst_port)
 539                                 udp->dst_port =
 540                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
 541                         if (!vxlan_gpe->vx_flags)
 542                                 vxlan_gpe->vx_flags =
 543                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
 544                         break;
 545                 case RTE_FLOW_ITEM_TYPE_GRE:
 546                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 547                         gre = (struct gre_hdr *)&buf[temp_size];
 548                         if (!gre->proto)
 549                                 return rte_flow_error_set(error, EINVAL,
 550                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 551                                                 (void *)items->type,
 552                                                 "next protocol not found");
 553                         if (!ipv4 && !ipv6)
 554                                 return rte_flow_error_set(error, EINVAL,
 555                                                 RTE_FLOW_ERROR_TYPE_ACTION,
 556                                                 (void *)items->type,
 557                                                 "ip header not found");
 558                         if (ipv4 && !ipv4->next_proto_id)
 559                                 ipv4->next_proto_id = IPPROTO_GRE;
 560                         else if (ipv6 && !ipv6->proto)
 561                                 ipv6->proto = IPPROTO_GRE;
 562                         break;
 563                 case RTE_FLOW_ITEM_TYPE_VOID:
 564                         break;
 565                 default:
 566                         return rte_flow_error_set(error, EINVAL,
 567                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 568                                                   (void *)items->type,
 569                                                   "unsupported item type");
 570                         break;
 571                 }
 572                 temp_size += len;
 573         }
 574         *size = temp_size;
 575         return 0;
 576 }
 577
 578 /**
 579  * Convert L2 encap action to DV specification.
 580  *
 581  * @param[in] dev
 582  *   Pointer to rte_eth_dev structure.
 583  * @param[in] action
 584  *   Pointer to action structure.
 585  * @param[in, out] dev_flow
 586  *   Pointer to the mlx5_flow.
 587  * @param[out] error
 588  *   Pointer to the error structure.
 589  *
 590  * @return
 591  *   0 on success, a negative errno value otherwise and rte_errno is set.
 592  */
 593 static int
 594 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
 595                                const struct rte_flow_action *action,
 596                                struct mlx5_flow *dev_flow,
 597                                struct rte_flow_error *error)
 598 {
 599         const struct rte_flow_item *encap_data;
 600         const struct rte_flow_action_raw_encap *raw_encap_data;
 601         struct mlx5_flow_dv_encap_decap_resource res = {
 602                 .reformat_type =
 603                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
 604                 .ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
 605         };
 606
 607         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
 608                 raw_encap_data =
 609                         (const struct rte_flow_action_raw_encap *)action->conf;
 610                 res.size = raw_encap_data->size;
 611                 memcpy(res.buf, raw_encap_data->data, res.size);
 612         } else {
 613                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
 614                         encap_data =
 615                                 ((const struct rte_flow_action_vxlan_encap *)
 616                                                 action->conf)->definition;
 617                 else
 618                         encap_data =
 619                                 ((const struct rte_flow_action_nvgre_encap *)
 620                                                 action->conf)->definition;
 621                 if (flow_dv_convert_encap_data(encap_data, res.buf,
 622                                                &res.size, error))
 623                         return -rte_errno;
 624         }
 625         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 626                 return rte_flow_error_set(error, EINVAL,
 627                                           RTE_FLOW_ERROR_TYPE_ACTION,
 628                                           NULL, "can't create L2 encap action");
 629         return 0;
 630 }
 631
 632 /**
 633  * Convert L2 decap action to DV specification.
 634  *
 635  * @param[in] dev
 636  *   Pointer to rte_eth_dev structure.
 637  * @param[in, out] dev_flow
 638  *   Pointer to the mlx5_flow.
 639  * @param[out] error
 640  *   Pointer to the error structure.
 641  *
 642  * @return
 643  *   0 on success, a negative errno value otherwise and rte_errno is set.
 644  */
 645 static int
 646 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
 647                                struct mlx5_flow *dev_flow,
 648                                struct rte_flow_error *error)
 649 {
 650         struct mlx5_flow_dv_encap_decap_resource res = {
 651                 .size = 0,
 652                 .reformat_type =
 653                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
 654                 .ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
 655         };
 656
 657         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 658                 return rte_flow_error_set(error, EINVAL,
 659                                           RTE_FLOW_ERROR_TYPE_ACTION,
 660                                           NULL, "can't create L2 decap action");
 661         return 0;
 662 }
 663
 664 /**
 665  * Convert raw decap/encap (L3 tunnel) action to DV specification.
 666  *
 667  * @param[in] dev
 668  *   Pointer to rte_eth_dev structure.
 669  * @param[in] action
 670  *   Pointer to action structure.
 671  * @param[in, out] dev_flow
 672  *   Pointer to the mlx5_flow.
 673  * @param[in] attr
 674  *   Pointer to the flow attributes.
 675  * @param[out] error
 676  *   Pointer to the error structure.
 677  *
 678  * @return
 679  *   0 on success, a negative errno value otherwise and rte_errno is set.
 680  */
 681 static int
 682 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
 683                                 const struct rte_flow_action *action,
 684                                 struct mlx5_flow *dev_flow,
 685                                 const struct rte_flow_attr *attr,
 686                                 struct rte_flow_error *error)
 687 {
 688         const struct rte_flow_action_raw_encap *encap_data;
 689         struct mlx5_flow_dv_encap_decap_resource res;
 690
 691         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
 692         res.size = encap_data->size;
 693         memcpy(res.buf, encap_data->data, res.size);
 694         res.reformat_type = attr->egress ?
 695                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL :
 696                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2;
 697         res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
 698                                      MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
 699         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
 700                 return rte_flow_error_set(error, EINVAL,
 701                                           RTE_FLOW_ERROR_TYPE_ACTION,
 702                                           NULL, "can't create encap action");
 703         return 0;
 704 }
 705
 706 /**
 707  * Verify the @p attributes will be correctly understood by the NIC and store
 708  * them in the @p flow if everything is correct.
 709  *
 710  * @param[in] dev
 711  *   Pointer to dev struct.
 712  * @param[in] attributes
 713  *   Pointer to flow attributes
 714  * @param[out] error
 715  *   Pointer to error structure.
 716  *
 717  * @return
 718  *   0 on success, a negative errno value otherwise and rte_errno is set.
 719  */
 720 static int
 721 flow_dv_validate_attributes(struct rte_eth_dev *dev,
 722                             const struct rte_flow_attr *attributes,
 723                             struct rte_flow_error *error)
 724 {
 725         struct priv *priv = dev->data->dev_private;
 726         uint32_t priority_max = priv->config.flow_prio - 1;
 727
 728         if (attributes->group)
 729                 return rte_flow_error_set(error, ENOTSUP,
 730                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
 731                                           NULL,
 732                                           "groups is not supported");
 733         if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
 734             attributes->priority >= priority_max)
 735                 return rte_flow_error_set(error, ENOTSUP,
 736                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
 737                                           NULL,
 738                                           "priority out of range");
 739         if (attributes->transfer)
 740                 return rte_flow_error_set(error, ENOTSUP,
 741                                           RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER,
 742                                           NULL,
 743                                           "transfer is not supported");
 744         if (!(attributes->egress ^ attributes->ingress))
 745                 return rte_flow_error_set(error, ENOTSUP,
 746                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
 747                                           "must specify exactly one of "
 748                                           "ingress or egress");
 749         return 0;
 750 }
 751
 752 /**
 753  * Internal validation function. For validating both actions and items.
 754  *
 755  * @param[in] dev
 756  *   Pointer to the rte_eth_dev structure.
 757  * @param[in] attr
 758  *   Pointer to the flow attributes.
 759  * @param[in] items
 760  *   Pointer to the list of items.
 761  * @param[in] actions
 762  *   Pointer to the list of actions.
 763  * @param[out] error
 764  *   Pointer to the error structure.
 765  *
 766  * @return
 767  *   0 on success, a negative errno value otherwise and rte_ernno is set.
 768  */
 769 static int
 770 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
 771                  const struct rte_flow_item items[],
 772                  const struct rte_flow_action actions[],
 773                  struct rte_flow_error *error)
 774 {
 775         int ret;
 776         uint64_t action_flags = 0;
 777         uint64_t item_flags = 0;
 778         int tunnel = 0;
 779         uint8_t next_protocol = 0xff;
 780         int actions_n = 0;
 781
 782         if (items == NULL)
 783                 return -1;
 784         ret = flow_dv_validate_attributes(dev, attr, error);
 785         if (ret < 0)
 786                 return ret;
 787         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
 788                 tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
 789                 switch (items->type) {
 790                 case RTE_FLOW_ITEM_TYPE_VOID:
 791                         break;
 792                 case RTE_FLOW_ITEM_TYPE_ETH:
 793                         ret = mlx5_flow_validate_item_eth(items, item_flags,
 794                                                           error);
 795                         if (ret < 0)
 796                                 return ret;
 797                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
 798                                                MLX5_FLOW_LAYER_OUTER_L2;
 799                         break;
 800                 case RTE_FLOW_ITEM_TYPE_VLAN:
 801                         ret = mlx5_flow_validate_item_vlan(items, item_flags,
 802                                                            error);
 803                         if (ret < 0)
 804                                 return ret;
 805                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
 806                                                MLX5_FLOW_LAYER_OUTER_VLAN;
 807                         break;
 808                 case RTE_FLOW_ITEM_TYPE_IPV4:
 809                         ret = mlx5_flow_validate_item_ipv4(items, item_flags,
 810                                                            error);
 811                         if (ret < 0)
 812                                 return ret;
 813                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
 814                                                MLX5_FLOW_LAYER_OUTER_L3_IPV4;
 815                         if (items->mask != NULL &&
 816                             ((const struct rte_flow_item_ipv4 *)
 817                              items->mask)->hdr.next_proto_id)
 818                                 next_protocol =
 819                                         ((const struct rte_flow_item_ipv4 *)
 820                                          (items->spec))->hdr.next_proto_id;
 821                         break;
 822                 case RTE_FLOW_ITEM_TYPE_IPV6:
 823                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
 824                                                            error);
 825                         if (ret < 0)
 826                                 return ret;
 827                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
 828                                                MLX5_FLOW_LAYER_OUTER_L3_IPV6;
 829                         if (items->mask != NULL &&
 830                             ((const struct rte_flow_item_ipv6 *)
 831                              items->mask)->hdr.proto)
 832                                 next_protocol =
 833                                         ((const struct rte_flow_item_ipv6 *)
 834                                          items->spec)->hdr.proto;
 835                         break;
 836                 case RTE_FLOW_ITEM_TYPE_TCP:
 837                         ret = mlx5_flow_validate_item_tcp
 838                                                 (items, item_flags,
 839                                                  next_protocol,
 840                                                  &rte_flow_item_tcp_mask,
 841                                                  error);
 842                         if (ret < 0)
 843                                 return ret;
 844                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
 845                                                MLX5_FLOW_LAYER_OUTER_L4_TCP;
 846                         break;
 847                 case RTE_FLOW_ITEM_TYPE_UDP:
 848                         ret = mlx5_flow_validate_item_udp(items, item_flags,
 849                                                           next_protocol,
 850                                                           error);
 851                         if (ret < 0)
 852                                 return ret;
 853                         item_flags |= tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
 854                                                MLX5_FLOW_LAYER_OUTER_L4_UDP;
 855                         break;
 856                 case RTE_FLOW_ITEM_TYPE_GRE:
 857                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 858                         ret = mlx5_flow_validate_item_gre(items, item_flags,
 859                                                           next_protocol, error);
 860                         if (ret < 0)
 861                                 return ret;
 862                         item_flags |= MLX5_FLOW_LAYER_GRE;
 863                         break;
 864                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 865                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
 866                                                             error);
 867                         if (ret < 0)
 868                                 return ret;
 869                         item_flags |= MLX5_FLOW_LAYER_VXLAN;
 870                         break;
 871                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 872                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
 873                                                                 item_flags, dev,
 874                                                                 error);
 875                         if (ret < 0)
 876                                 return ret;
 877                         item_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;
 878                         break;
 879                 case RTE_FLOW_ITEM_TYPE_META:
 880                         ret = flow_dv_validate_item_meta(dev, items, attr,
 881                                                          error);
 882                         if (ret < 0)
 883                                 return ret;
 884                         item_flags |= MLX5_FLOW_ITEM_METADATA;
 885                         break;
 886                 default:
 887                         return rte_flow_error_set(error, ENOTSUP,
 888                                                   RTE_FLOW_ERROR_TYPE_ITEM,
 889                                                   NULL, "item not supported");
 890                 }
 891         }
 892         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
 893                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
 894                         return rte_flow_error_set(error, ENOTSUP,
 895                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 896                                                   actions, "too many actions");
 897                 switch (actions->type) {
 898                 case RTE_FLOW_ACTION_TYPE_VOID:
 899                         break;
 900                 case RTE_FLOW_ACTION_TYPE_FLAG:
 901                         ret = mlx5_flow_validate_action_flag(action_flags,
 902                                                              attr, error);
 903                         if (ret < 0)
 904                                 return ret;
 905                         action_flags |= MLX5_FLOW_ACTION_FLAG;
 906                         ++actions_n;
 907                         break;
 908                 case RTE_FLOW_ACTION_TYPE_MARK:
 909                         ret = mlx5_flow_validate_action_mark(actions,
 910                                                              action_flags,
 911                                                              attr, error);
 912                         if (ret < 0)
 913                                 return ret;
 914                         action_flags |= MLX5_FLOW_ACTION_MARK;
 915                         ++actions_n;
 916                         break;
 917                 case RTE_FLOW_ACTION_TYPE_DROP:
 918                         ret = mlx5_flow_validate_action_drop(action_flags,
 919                                                              attr, error);
 920                         if (ret < 0)
 921                                 return ret;
 922                         action_flags |= MLX5_FLOW_ACTION_DROP;
 923                         ++actions_n;
 924                         break;
 925                 case RTE_FLOW_ACTION_TYPE_QUEUE:
 926                         ret = mlx5_flow_validate_action_queue(actions,
 927                                                               action_flags, dev,
 928                                                               attr, error);
 929                         if (ret < 0)
 930                                 return ret;
 931                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
 932                         ++actions_n;
 933                         break;
 934                 case RTE_FLOW_ACTION_TYPE_RSS:
 935                         ret = mlx5_flow_validate_action_rss(actions,
 936                                                             action_flags, dev,
 937                                                             attr, error);
 938                         if (ret < 0)
 939                                 return ret;
 940                         action_flags |= MLX5_FLOW_ACTION_RSS;
 941                         ++actions_n;
 942                         break;
 943                 case RTE_FLOW_ACTION_TYPE_COUNT:
 944                         ret = mlx5_flow_validate_action_count(dev, attr, error);
 945                         if (ret < 0)
 946                                 return ret;
 947                         action_flags |= MLX5_FLOW_ACTION_COUNT;
 948                         ++actions_n;
 949                         break;
 950                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
 951                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
 952                         ret = flow_dv_validate_action_l2_encap(action_flags,
 953                                                                actions, attr,
 954                                                                error);
 955                         if (ret < 0)
 956                                 return ret;
 957                         action_flags |= actions->type ==
 958                                         RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
 959                                         MLX5_FLOW_ACTION_VXLAN_ENCAP :
 960                                         MLX5_FLOW_ACTION_NVGRE_ENCAP;
 961                         ++actions_n;
 962                         break;
 963                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
 964                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
 965                         ret = flow_dv_validate_action_l2_decap(action_flags,
 966                                                                attr, error);
 967                         if (ret < 0)
 968                                 return ret;
 969                         action_flags |= actions->type ==
 970                                         RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
 971                                         MLX5_FLOW_ACTION_VXLAN_DECAP :
 972                                         MLX5_FLOW_ACTION_NVGRE_DECAP;
 973                         ++actions_n;
 974                         break;
 975                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
 976                         ret = flow_dv_validate_action_raw_encap(action_flags,
 977                                                                 actions, attr,
 978                                                                 error);
 979                         if (ret < 0)
 980                                 return ret;
 981                         action_flags |= MLX5_FLOW_ACTION_RAW_ENCAP;
 982                         ++actions_n;
 983                         break;
 984                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
 985                         ret = flow_dv_validate_action_raw_decap(action_flags,
 986                                                                 actions, attr,
 987                                                                 error);
 988                         if (ret < 0)
 989                                 return ret;
 990                         action_flags |= MLX5_FLOW_ACTION_RAW_DECAP;
 991                         ++actions_n;
 992                         break;
 993                 default:
 994                         return rte_flow_error_set(error, ENOTSUP,
 995                                                   RTE_FLOW_ERROR_TYPE_ACTION,
 996                                                   actions,
 997                                                   "action not supported");
 998                 }
 999         }
1000         if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
1001                 return rte_flow_error_set(error, EINVAL,
1002                                           RTE_FLOW_ERROR_TYPE_ACTION, actions,
1003                                           "no fate action is found");
1004         return 0;
1005 }
1006
1007 /**
1008  * Internal preparation function. Allocates the DV flow size,
1009  * this size is constant.
1010  *
1011  * @param[in] attr
1012  *   Pointer to the flow attributes.
1013  * @param[in] items
1014  *   Pointer to the list of items.
1015  * @param[in] actions
1016  *   Pointer to the list of actions.
1017  * @param[out] item_flags
1018  *   Pointer to bit mask of all items detected.
1019  * @param[out] action_flags
1020  *   Pointer to bit mask of all actions detected.
1021  * @param[out] error
1022  *   Pointer to the error structure.
1023  *
1024  * @return
1025  *   Pointer to mlx5_flow object on success,
1026  *   otherwise NULL and rte_ernno is set.
1027  */
1028 static struct mlx5_flow *
1029 flow_dv_prepare(const struct rte_flow_attr *attr __rte_unused,
1030                 const struct rte_flow_item items[] __rte_unused,
1031                 const struct rte_flow_action actions[] __rte_unused,
1032                 uint64_t *item_flags __rte_unused,
1033                 uint64_t *action_flags __rte_unused,
1034                 struct rte_flow_error *error)
1035 {
1036         uint32_t size = sizeof(struct mlx5_flow);
1037         struct mlx5_flow *flow;
1038
1039         flow = rte_calloc(__func__, 1, size, 0);
1040         if (!flow) {
1041                 rte_flow_error_set(error, ENOMEM,
1042                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1043                                    "not enough memory to create flow");
1044                 return NULL;
1045         }
1046         flow->dv.value.size = MLX5_ST_SZ_DB(fte_match_param);
1047         return flow;
1048 }
1049
1050 /**
1051  * Add Ethernet item to matcher and to the value.
1052  *
1053  * @param[in, out] matcher
1054  *   Flow matcher.
1055  * @param[in, out] key
1056  *   Flow matcher value.
1057  * @param[in] item
1058  *   Flow pattern to translate.
1059  * @param[in] inner
1060  *   Item is inner pattern.
1061  */
1062 static void
1063 flow_dv_translate_item_eth(void *matcher, void *key,
1064                            const struct rte_flow_item *item, int inner)
1065 {
1066         const struct rte_flow_item_eth *eth_m = item->mask;
1067         const struct rte_flow_item_eth *eth_v = item->spec;
1068         const struct rte_flow_item_eth nic_mask = {
1069                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1070                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
1071                 .type = RTE_BE16(0xffff),
1072         };
1073         void *headers_m;
1074         void *headers_v;
1075         char *l24_v;
1076         unsigned int i;
1077
1078         if (!eth_v)
1079                 return;
1080         if (!eth_m)
1081                 eth_m = &nic_mask;
1082         if (inner) {
1083                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1084                                          inner_headers);
1085                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1086         } else {
1087                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1088                                          outer_headers);
1089                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1090         }
1091         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
1092                &eth_m->dst, sizeof(eth_m->dst));
1093         /* The value must be in the range of the mask. */
1094         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
1095         for (i = 0; i < sizeof(eth_m->dst); ++i)
1096                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
1097         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
1098                &eth_m->src, sizeof(eth_m->src));
1099         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
1100         /* The value must be in the range of the mask. */
1101         for (i = 0; i < sizeof(eth_m->dst); ++i)
1102                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
1103         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
1104                  rte_be_to_cpu_16(eth_m->type));
1105         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, ethertype);
1106         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
1107 }
1108
1109 /**
1110  * Add VLAN item to matcher and to the value.
1111  *
1112  * @param[in, out] matcher
1113  *   Flow matcher.
1114  * @param[in, out] key
1115  *   Flow matcher value.
1116  * @param[in] item
1117  *   Flow pattern to translate.
1118  * @param[in] inner
1119  *   Item is inner pattern.
1120  */
1121 static void
1122 flow_dv_translate_item_vlan(void *matcher, void *key,
1123                             const struct rte_flow_item *item,
1124                             int inner)
1125 {
1126         const struct rte_flow_item_vlan *vlan_m = item->mask;
1127         const struct rte_flow_item_vlan *vlan_v = item->spec;
1128         const struct rte_flow_item_vlan nic_mask = {
1129                 .tci = RTE_BE16(0x0fff),
1130                 .inner_type = RTE_BE16(0xffff),
1131         };
1132         void *headers_m;
1133         void *headers_v;
1134         uint16_t tci_m;
1135         uint16_t tci_v;
1136
1137         if (!vlan_v)
1138                 return;
1139         if (!vlan_m)
1140                 vlan_m = &nic_mask;
1141         if (inner) {
1142                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1143                                          inner_headers);
1144                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1145         } else {
1146                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1147                                          outer_headers);
1148                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1149         }
1150         tci_m = rte_be_to_cpu_16(vlan_m->tci);
1151         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
1152         MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
1153         MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
1154         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
1155         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
1156         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
1157         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
1158         MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
1159         MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
1160 }
1161
1162 /**
1163  * Add IPV4 item to matcher and to the value.
1164  *
1165  * @param[in, out] matcher
1166  *   Flow matcher.
1167  * @param[in, out] key
1168  *   Flow matcher value.
1169  * @param[in] item
1170  *   Flow pattern to translate.
1171  * @param[in] inner
1172  *   Item is inner pattern.
1173  */
1174 static void
1175 flow_dv_translate_item_ipv4(void *matcher, void *key,
1176                             const struct rte_flow_item *item,
1177                             int inner)
1178 {
1179         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
1180         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
1181         const struct rte_flow_item_ipv4 nic_mask = {
1182                 .hdr = {
1183                         .src_addr = RTE_BE32(0xffffffff),
1184                         .dst_addr = RTE_BE32(0xffffffff),
1185                         .type_of_service = 0xff,
1186                         .next_proto_id = 0xff,
1187                 },
1188         };
1189         void *headers_m;
1190         void *headers_v;
1191         char *l24_m;
1192         char *l24_v;
1193         uint8_t tos;
1194
1195         if (inner) {
1196                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1197                                          inner_headers);
1198                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1199         } else {
1200                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1201                                          outer_headers);
1202                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1203         }
1204         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
1205         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 4);
1206         if (!ipv4_v)
1207                 return;
1208         if (!ipv4_m)
1209                 ipv4_m = &nic_mask;
1210         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1211                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
1212         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1213                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
1214         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
1215         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
1216         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1217                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
1218         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1219                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
1220         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
1221         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
1222         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
1223         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
1224                  ipv4_m->hdr.type_of_service);
1225         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
1226         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
1227                  ipv4_m->hdr.type_of_service >> 2);
1228         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
1229         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
1230                  ipv4_m->hdr.next_proto_id);
1231         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1232                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
1233 }
1234
1235 /**
1236  * Add IPV6 item to matcher and to the value.
1237  *
1238  * @param[in, out] matcher
1239  *   Flow matcher.
1240  * @param[in, out] key
1241  *   Flow matcher value.
1242  * @param[in] item
1243  *   Flow pattern to translate.
1244  * @param[in] inner
1245  *   Item is inner pattern.
1246  */
1247 static void
1248 flow_dv_translate_item_ipv6(void *matcher, void *key,
1249                             const struct rte_flow_item *item,
1250                             int inner)
1251 {
1252         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
1253         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
1254         const struct rte_flow_item_ipv6 nic_mask = {
1255                 .hdr = {
1256                         .src_addr =
1257                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
1258                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
1259                         .dst_addr =
1260                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
1261                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
1262                         .vtc_flow = RTE_BE32(0xffffffff),
1263                         .proto = 0xff,
1264                         .hop_limits = 0xff,
1265                 },
1266         };
1267         void *headers_m;
1268         void *headers_v;
1269         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1270         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1271         char *l24_m;
1272         char *l24_v;
1273         uint32_t vtc_m;
1274         uint32_t vtc_v;
1275         int i;
1276         int size;
1277
1278         if (inner) {
1279                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1280                                          inner_headers);
1281                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1282         } else {
1283                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1284                                          outer_headers);
1285                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1286         }
1287         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
1288         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, 6);
1289         if (!ipv6_v)
1290                 return;
1291         if (!ipv6_m)
1292                 ipv6_m = &nic_mask;
1293         size = sizeof(ipv6_m->hdr.dst_addr);
1294         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1295                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
1296         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1297                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
1298         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
1299         for (i = 0; i < size; ++i)
1300                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
1301         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
1302                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
1303         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1304                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
1305         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
1306         for (i = 0; i < size; ++i)
1307                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
1308         /* TOS. */
1309         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
1310         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
1311         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
1312         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
1313         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
1314         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
1315         /* Label. */
1316         if (inner) {
1317                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
1318                          vtc_m);
1319                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
1320                          vtc_v);
1321         } else {
1322                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
1323                          vtc_m);
1324                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
1325                          vtc_v);
1326         }
1327         /* Protocol. */
1328         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
1329                  ipv6_m->hdr.proto);
1330         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1331                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
1332 }
1333
1334 /**
1335  * Add TCP item to matcher and to the value.
1336  *
1337  * @param[in, out] matcher
1338  *   Flow matcher.
1339  * @param[in, out] key
1340  *   Flow matcher value.
1341  * @param[in] item
1342  *   Flow pattern to translate.
1343  * @param[in] inner
1344  *   Item is inner pattern.
1345  */
1346 static void
1347 flow_dv_translate_item_tcp(void *matcher, void *key,
1348                            const struct rte_flow_item *item,
1349                            int inner)
1350 {
1351         const struct rte_flow_item_tcp *tcp_m = item->mask;
1352         const struct rte_flow_item_tcp *tcp_v = item->spec;
1353         void *headers_m;
1354         void *headers_v;
1355
1356         if (inner) {
1357                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1358                                          inner_headers);
1359                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1360         } else {
1361                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1362                                          outer_headers);
1363                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1364         }
1365         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1366         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
1367         if (!tcp_v)
1368                 return;
1369         if (!tcp_m)
1370                 tcp_m = &rte_flow_item_tcp_mask;
1371         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
1372                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
1373         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1374                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
1375         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
1376                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
1377         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1378                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
1379 }
1380
1381 /**
1382  * Add UDP item to matcher and to the value.
1383  *
1384  * @param[in, out] matcher
1385  *   Flow matcher.
1386  * @param[in, out] key
1387  *   Flow matcher value.
1388  * @param[in] item
1389  *   Flow pattern to translate.
1390  * @param[in] inner
1391  *   Item is inner pattern.
1392  */
1393 static void
1394 flow_dv_translate_item_udp(void *matcher, void *key,
1395                            const struct rte_flow_item *item,
1396                            int inner)
1397 {
1398         const struct rte_flow_item_udp *udp_m = item->mask;
1399         const struct rte_flow_item_udp *udp_v = item->spec;
1400         void *headers_m;
1401         void *headers_v;
1402
1403         if (inner) {
1404                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1405                                          inner_headers);
1406                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1407         } else {
1408                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1409                                          outer_headers);
1410                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1411         }
1412         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1413         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1414         if (!udp_v)
1415                 return;
1416         if (!udp_m)
1417                 udp_m = &rte_flow_item_udp_mask;
1418         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
1419                  rte_be_to_cpu_16(udp_m->hdr.src_port));
1420         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1421                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
1422         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
1423                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
1424         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1425                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
1426 }
1427
1428 /**
1429  * Add GRE item to matcher and to the value.
1430  *
1431  * @param[in, out] matcher
1432  *   Flow matcher.
1433  * @param[in, out] key
1434  *   Flow matcher value.
1435  * @param[in] item
1436  *   Flow pattern to translate.
1437  * @param[in] inner
1438  *   Item is inner pattern.
1439  */
1440 static void
1441 flow_dv_translate_item_gre(void *matcher, void *key,
1442                            const struct rte_flow_item *item,
1443                            int inner)
1444 {
1445         const struct rte_flow_item_gre *gre_m = item->mask;
1446         const struct rte_flow_item_gre *gre_v = item->spec;
1447         void *headers_m;
1448         void *headers_v;
1449         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1450         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1451
1452         if (inner) {
1453                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1454                                          inner_headers);
1455                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1456         } else {
1457                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1458                                          outer_headers);
1459                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1460         }
1461         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
1462         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
1463         if (!gre_v)
1464                 return;
1465         if (!gre_m)
1466                 gre_m = &rte_flow_item_gre_mask;
1467         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
1468                  rte_be_to_cpu_16(gre_m->protocol));
1469         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
1470                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
1471 }
1472
1473 /**
1474  * Add NVGRE item to matcher and to the value.
1475  *
1476  * @param[in, out] matcher
1477  *   Flow matcher.
1478  * @param[in, out] key
1479  *   Flow matcher value.
1480  * @param[in] item
1481  *   Flow pattern to translate.
1482  * @param[in] inner
1483  *   Item is inner pattern.
1484  */
1485 static void
1486 flow_dv_translate_item_nvgre(void *matcher, void *key,
1487                              const struct rte_flow_item *item,
1488                              int inner)
1489 {
1490         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
1491         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
1492         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1493         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1494         const char *tni_flow_id_m = (const char *)nvgre_m->tni;
1495         const char *tni_flow_id_v = (const char *)nvgre_v->tni;
1496         char *gre_key_m;
1497         char *gre_key_v;
1498         int size;
1499         int i;
1500
1501         flow_dv_translate_item_gre(matcher, key, item, inner);
1502         if (!nvgre_v)
1503                 return;
1504         if (!nvgre_m)
1505                 nvgre_m = &rte_flow_item_nvgre_mask;
1506         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
1507         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
1508         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
1509         memcpy(gre_key_m, tni_flow_id_m, size);
1510         for (i = 0; i < size; ++i)
1511                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
1512 }
1513
1514 /**
1515  * Add VXLAN item to matcher and to the value.
1516  *
1517  * @param[in, out] matcher
1518  *   Flow matcher.
1519  * @param[in, out] key
1520  *   Flow matcher value.
1521  * @param[in] item
1522  *   Flow pattern to translate.
1523  * @param[in] inner
1524  *   Item is inner pattern.
1525  */
1526 static void
1527 flow_dv_translate_item_vxlan(void *matcher, void *key,
1528                              const struct rte_flow_item *item,
1529                              int inner)
1530 {
1531         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
1532         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
1533         void *headers_m;
1534         void *headers_v;
1535         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
1536         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
1537         char *vni_m;
1538         char *vni_v;
1539         uint16_t dport;
1540         int size;
1541         int i;
1542
1543         if (inner) {
1544                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1545                                          inner_headers);
1546                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
1547         } else {
1548                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
1549                                          outer_headers);
1550                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
1551         }
1552         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
1553                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
1554         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
1555                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
1556                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
1557         }
1558         if (!vxlan_v)
1559                 return;
1560         if (!vxlan_m)
1561                 vxlan_m = &rte_flow_item_vxlan_mask;
1562         size = sizeof(vxlan_m->vni);
1563         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
1564         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
1565         memcpy(vni_m, vxlan_m->vni, size);
1566         for (i = 0; i < size; ++i)
1567                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
1568 }
1569
1570 /**
1571  * Add META item to matcher
1572  *
1573  * @param[in, out] matcher
1574  *   Flow matcher.
1575  * @param[in, out] key
1576  *   Flow matcher value.
1577  * @param[in] item
1578  *   Flow pattern to translate.
1579  * @param[in] inner
1580  *   Item is inner pattern.
1581  */
1582 static void
1583 flow_dv_translate_item_meta(void *matcher, void *key,
1584                             const struct rte_flow_item *item)
1585 {
1586         const struct rte_flow_item_meta *meta_m;
1587         const struct rte_flow_item_meta *meta_v;
1588         void *misc2_m =
1589                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
1590         void *misc2_v =
1591                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
1592
1593         meta_m = (const void *)item->mask;
1594         if (!meta_m)
1595                 meta_m = &rte_flow_item_meta_mask;
1596         meta_v = (const void *)item->spec;
1597         if (meta_v) {
1598                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a,
1599                          rte_be_to_cpu_32(meta_m->data));
1600                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a,
1601                          rte_be_to_cpu_32(meta_v->data & meta_m->data));
1602         }
1603 }
1604
1605 /**
1606  * Update the matcher and the value based the selected item.
1607  *
1608  * @param[in, out] matcher
1609  *   Flow matcher.
1610  * @param[in, out] key
1611  *   Flow matcher value.
1612  * @param[in] item
1613  *   Flow pattern to translate.
1614  * @param[in, out] dev_flow
1615  *   Pointer to the mlx5_flow.
1616  * @param[in] inner
1617  *   Item is inner pattern.
1618  */
1619 static void
1620 flow_dv_create_item(void *matcher, void *key,
1621                     const struct rte_flow_item *item,
1622                     struct mlx5_flow *dev_flow,
1623                     int inner)
1624 {
1625         struct mlx5_flow_dv_matcher *tmatcher = matcher;
1626
1627         switch (item->type) {
1628         case RTE_FLOW_ITEM_TYPE_ETH:
1629                 flow_dv_translate_item_eth(tmatcher->mask.buf, key, item,
1630                                            inner);
1631                 tmatcher->priority = MLX5_PRIORITY_MAP_L2;
1632                 break;
1633         case RTE_FLOW_ITEM_TYPE_VLAN:
1634                 flow_dv_translate_item_vlan(tmatcher->mask.buf, key, item,
1635                                             inner);
1636                 break;
1637         case RTE_FLOW_ITEM_TYPE_IPV4:
1638                 flow_dv_translate_item_ipv4(tmatcher->mask.buf, key, item,
1639                                             inner);
1640                 tmatcher->priority = MLX5_PRIORITY_MAP_L3;
1641                 dev_flow->dv.hash_fields |=
1642                         mlx5_flow_hashfields_adjust(dev_flow, inner,
1643                                                     MLX5_IPV4_LAYER_TYPES,
1644                                                     MLX5_IPV4_IBV_RX_HASH);
1645                 break;
1646         case RTE_FLOW_ITEM_TYPE_IPV6:
1647                 flow_dv_translate_item_ipv6(tmatcher->mask.buf, key, item,
1648                                             inner);
1649                 tmatcher->priority = MLX5_PRIORITY_MAP_L3;
1650                 dev_flow->dv.hash_fields |=
1651                         mlx5_flow_hashfields_adjust(dev_flow, inner,
1652                                                     MLX5_IPV6_LAYER_TYPES,
1653                                                     MLX5_IPV6_IBV_RX_HASH);
1654                 break;
1655         case RTE_FLOW_ITEM_TYPE_TCP:
1656                 flow_dv_translate_item_tcp(tmatcher->mask.buf, key, item,
1657                                            inner);
1658                 tmatcher->priority = MLX5_PRIORITY_MAP_L4;
1659                 dev_flow->dv.hash_fields |=
1660                         mlx5_flow_hashfields_adjust(dev_flow, inner,
1661                                                     ETH_RSS_TCP,
1662                                                     (IBV_RX_HASH_SRC_PORT_TCP |
1663                                                      IBV_RX_HASH_DST_PORT_TCP));
1664                 break;
1665         case RTE_FLOW_ITEM_TYPE_UDP:
1666                 flow_dv_translate_item_udp(tmatcher->mask.buf, key, item,
1667                                            inner);
1668                 tmatcher->priority = MLX5_PRIORITY_MAP_L4;
1669                 dev_flow->verbs.hash_fields |=
1670                         mlx5_flow_hashfields_adjust(dev_flow, inner,
1671                                                     ETH_RSS_UDP,
1672                                                     (IBV_RX_HASH_SRC_PORT_UDP |
1673                                                      IBV_RX_HASH_DST_PORT_UDP));
1674                 break;
1675         case RTE_FLOW_ITEM_TYPE_GRE:
1676                 flow_dv_translate_item_gre(tmatcher->mask.buf, key, item,
1677                                            inner);
1678                 break;
1679         case RTE_FLOW_ITEM_TYPE_NVGRE:
1680                 flow_dv_translate_item_nvgre(tmatcher->mask.buf, key, item,
1681                                              inner);
1682                 break;
1683         case RTE_FLOW_ITEM_TYPE_VXLAN:
1684         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
1685                 flow_dv_translate_item_vxlan(tmatcher->mask.buf, key, item,
1686                                              inner);
1687                 break;
1688         case RTE_FLOW_ITEM_TYPE_META:
1689                 flow_dv_translate_item_meta(tmatcher->mask.buf, key, item);
1690                 break;
1691         default:
1692                 break;
1693         }
1694 }
1695
1696 /**
1697  * Store the requested actions in an array.
1698  *
1699  * @param[in] dev
1700  *   Pointer to rte_eth_dev structure.
1701  * @param[in] action
1702  *   Flow action to translate.
1703  * @param[in, out] dev_flow
1704  *   Pointer to the mlx5_flow.
1705  * @param[in] attr
1706  *   Pointer to the flow attributes.
1707  * @param[out] error
1708  *   Pointer to the error structure.
1709  *
1710  * @return
1711  *   0 on success, a negative errno value otherwise and rte_errno is set.
1712  */
1713 static int
1714 flow_dv_create_action(struct rte_eth_dev *dev,
1715                       const struct rte_flow_action *action,
1716                       struct mlx5_flow *dev_flow,
1717                       const struct rte_flow_attr *attr,
1718                       struct rte_flow_error *error)
1719 {
1720         const struct rte_flow_action_queue *queue;
1721         const struct rte_flow_action_rss *rss;
1722         int actions_n = dev_flow->dv.actions_n;
1723         struct rte_flow *flow = dev_flow->flow;
1724         const struct rte_flow_action *action_ptr = action;
1725
1726         switch (action->type) {
1727         case RTE_FLOW_ACTION_TYPE_VOID:
1728                 break;
1729         case RTE_FLOW_ACTION_TYPE_FLAG:
1730                 dev_flow->dv.actions[actions_n].type = MLX5DV_FLOW_ACTION_TAG;
1731                 dev_flow->dv.actions[actions_n].tag_value =
1732                         mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
1733                 actions_n++;
1734                 flow->actions |= MLX5_FLOW_ACTION_FLAG;
1735                 break;
1736         case RTE_FLOW_ACTION_TYPE_MARK:
1737                 dev_flow->dv.actions[actions_n].type = MLX5DV_FLOW_ACTION_TAG;
1738                 dev_flow->dv.actions[actions_n].tag_value =
1739                         mlx5_flow_mark_set
1740                         (((const struct rte_flow_action_mark *)
1741                           (action->conf))->id);
1742                 flow->actions |= MLX5_FLOW_ACTION_MARK;
1743                 actions_n++;
1744                 break;
1745         case RTE_FLOW_ACTION_TYPE_DROP:
1746                 dev_flow->dv.actions[actions_n].type = MLX5DV_FLOW_ACTION_DROP;
1747                 flow->actions |= MLX5_FLOW_ACTION_DROP;
1748                 break;
1749         case RTE_FLOW_ACTION_TYPE_QUEUE:
1750                 queue = action->conf;
1751                 flow->rss.queue_num = 1;
1752                 (*flow->queue)[0] = queue->index;
1753                 flow->actions |= MLX5_FLOW_ACTION_QUEUE;
1754                 break;
1755         case RTE_FLOW_ACTION_TYPE_RSS:
1756                 rss = action->conf;
1757                 if (flow->queue)
1758                         memcpy((*flow->queue), rss->queue,
1759                                rss->queue_num * sizeof(uint16_t));
1760                 flow->rss.queue_num = rss->queue_num;
1761                 memcpy(flow->key, rss->key, MLX5_RSS_HASH_KEY_LEN);
1762                 flow->rss.types = rss->types;
1763                 flow->rss.level = rss->level;
1764                 /* Added to array only in apply since we need the QP */
1765                 flow->actions |= MLX5_FLOW_ACTION_RSS;
1766                 break;
1767         case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
1768         case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
1769                 if (flow_dv_create_action_l2_encap(dev, action,
1770                                                    dev_flow, error))
1771                         return -rte_errno;
1772                 dev_flow->dv.actions[actions_n].type =
1773                         MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1774                 dev_flow->dv.actions[actions_n].action =
1775                         dev_flow->dv.encap_decap->verbs_action;
1776                 flow->actions |= action->type ==
1777                                  RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP ?
1778                                  MLX5_FLOW_ACTION_VXLAN_ENCAP :
1779                                  MLX5_FLOW_ACTION_NVGRE_ENCAP;
1780                 actions_n++;
1781                 break;
1782         case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
1783         case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
1784                 if (flow_dv_create_action_l2_decap(dev, dev_flow, error))
1785                         return -rte_errno;
1786                 dev_flow->dv.actions[actions_n].type =
1787                         MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1788                 dev_flow->dv.actions[actions_n].action =
1789                         dev_flow->dv.encap_decap->verbs_action;
1790                 flow->actions |= action->type ==
1791                                  RTE_FLOW_ACTION_TYPE_VXLAN_DECAP ?
1792                                  MLX5_FLOW_ACTION_VXLAN_DECAP :
1793                                  MLX5_FLOW_ACTION_NVGRE_DECAP;
1794                 actions_n++;
1795                 break;
1796         case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
1797                 /* Handle encap action with preceding decap */
1798                 if (flow->actions & MLX5_FLOW_ACTION_RAW_DECAP) {
1799                         if (flow_dv_create_action_raw_encap(dev, action,
1800                                                             dev_flow,
1801                                                             attr, error))
1802                                 return -rte_errno;
1803                         dev_flow->dv.actions[actions_n].type =
1804                                 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1805                         dev_flow->dv.actions[actions_n].action =
1806                                         dev_flow->dv.encap_decap->verbs_action;
1807                 } else {
1808                         /* Handle encap action without preceding decap */
1809                         if (flow_dv_create_action_l2_encap(dev, action,
1810                                                            dev_flow, error))
1811                                 return -rte_errno;
1812                         dev_flow->dv.actions[actions_n].type =
1813                                 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1814                         dev_flow->dv.actions[actions_n].action =
1815                                         dev_flow->dv.encap_decap->verbs_action;
1816                 }
1817                 flow->actions |= MLX5_FLOW_ACTION_RAW_ENCAP;
1818                 actions_n++;
1819                 break;
1820         case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
1821                 /* Check if this decap action is followed by encap. */
1822                 for (; action_ptr->type != RTE_FLOW_ACTION_TYPE_END &&
1823                        action_ptr->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP;
1824                        action_ptr++) {
1825                 }
1826                 /* Handle decap action only if it isn't followed by encap */
1827                 if (action_ptr->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
1828                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
1829                                                            error))
1830                                 return -rte_errno;
1831                         dev_flow->dv.actions[actions_n].type =
1832                                 MLX5DV_FLOW_ACTION_IBV_FLOW_ACTION;
1833                         dev_flow->dv.actions[actions_n].action =
1834                                         dev_flow->dv.encap_decap->verbs_action;
1835                         actions_n++;
1836                 }
1837                 /* If decap is followed by encap, handle it at encap case. */
1838                 flow->actions |= MLX5_FLOW_ACTION_RAW_DECAP;
1839                 break;
1840         default:
1841                 break;
1842         }
1843         dev_flow->dv.actions_n = actions_n;
1844         return 0;
1845 }
1846
1847 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
1848
1849 #define HEADER_IS_ZERO(match_criteria, headers)                              \
1850         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
1851                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1852
1853 /**
1854  * Calculate flow matcher enable bitmap.
1855  *
1856  * @param match_criteria
1857  *   Pointer to flow matcher criteria.
1858  *
1859  * @return
1860  *   Bitmap of enabled fields.
1861  */
1862 static uint8_t
1863 flow_dv_matcher_enable(uint32_t *match_criteria)
1864 {
1865         uint8_t match_criteria_enable;
1866
1867         match_criteria_enable =
1868                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1869                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
1870         match_criteria_enable |=
1871                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1872                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
1873         match_criteria_enable |=
1874                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1875                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
1876         match_criteria_enable |=
1877                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
1878                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
1879
1880         return match_criteria_enable;
1881 }
1882
1883 /**
1884  * Register the flow matcher.
1885  *
1886  * @param dev[in, out]
1887  *   Pointer to rte_eth_dev structure.
1888  * @param[in, out] matcher
1889  *   Pointer to flow matcher.
1890  * @parm[in, out] dev_flow
1891  *   Pointer to the dev_flow.
1892  * @param[out] error
1893  *   pointer to error structure.
1894  *
1895  * @return
1896  *   0 on success otherwise -errno and errno is set.
1897  */
1898 static int
1899 flow_dv_matcher_register(struct rte_eth_dev *dev,
1900                          struct mlx5_flow_dv_matcher *matcher,
1901                          struct mlx5_flow *dev_flow,
1902                          struct rte_flow_error *error)
1903 {
1904         struct priv *priv = dev->data->dev_private;
1905         struct mlx5_flow_dv_matcher *cache_matcher;
1906         struct mlx5dv_flow_matcher_attr dv_attr = {
1907                 .type = IBV_FLOW_ATTR_NORMAL,
1908                 .match_mask = (void *)&matcher->mask,
1909         };
1910
1911         /* Lookup from cache. */
1912         LIST_FOREACH(cache_matcher, &priv->matchers, next) {
1913                 if (matcher->crc == cache_matcher->crc &&
1914                     matcher->priority == cache_matcher->priority &&
1915                     matcher->egress == cache_matcher->egress &&
1916                     !memcmp((const void *)matcher->mask.buf,
1917                             (const void *)cache_matcher->mask.buf,
1918                             cache_matcher->mask.size)) {
1919                         DRV_LOG(DEBUG,
1920                                 "priority %hd use %s matcher %p: refcnt %d++",
1921                                 cache_matcher->priority,
1922                                 cache_matcher->egress ? "tx" : "rx",
1923                                 (void *)cache_matcher,
1924                                 rte_atomic32_read(&cache_matcher->refcnt));
1925                         rte_atomic32_inc(&cache_matcher->refcnt);
1926                         dev_flow->dv.matcher = cache_matcher;
1927                         return 0;
1928                 }
1929         }
1930         /* Register new matcher. */
1931         cache_matcher = rte_calloc(__func__, 1, sizeof(*cache_matcher), 0);
1932         if (!cache_matcher)
1933                 return rte_flow_error_set(error, ENOMEM,
1934                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1935                                           "cannot allocate matcher memory");
1936         *cache_matcher = *matcher;
1937         dv_attr.match_criteria_enable =
1938                 flow_dv_matcher_enable(cache_matcher->mask.buf);
1939         dv_attr.priority = matcher->priority;
1940         if (matcher->egress)
1941                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
1942         cache_matcher->matcher_object =
1943                 mlx5_glue->dv_create_flow_matcher(priv->ctx, &dv_attr);
1944         if (!cache_matcher->matcher_object) {
1945                 rte_free(cache_matcher);
1946                 return rte_flow_error_set(error, ENOMEM,
1947                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1948                                           NULL, "cannot create matcher");
1949         }
1950         rte_atomic32_inc(&cache_matcher->refcnt);
1951         LIST_INSERT_HEAD(&priv->matchers, cache_matcher, next);
1952         dev_flow->dv.matcher = cache_matcher;
1953         DRV_LOG(DEBUG, "priority %hd new %s matcher %p: refcnt %d",
1954                 cache_matcher->priority,
1955                 cache_matcher->egress ? "tx" : "rx", (void *)cache_matcher,
1956                 rte_atomic32_read(&cache_matcher->refcnt));
1957         return 0;
1958 }
1959
1960 /**
1961  * Fill the flow with DV spec.
1962  *
1963  * @param[in] dev
1964  *   Pointer to rte_eth_dev structure.
1965  * @param[in, out] dev_flow
1966  *   Pointer to the sub flow.
1967  * @param[in] attr
1968  *   Pointer to the flow attributes.
1969  * @param[in] items
1970  *   Pointer to the list of items.
1971  * @param[in] actions
1972  *   Pointer to the list of actions.
1973  * @param[out] error
1974  *   Pointer to the error structure.
1975  *
1976  * @return
1977  *   0 on success, a negative errno value otherwise and rte_ernno is set.
1978  */
1979 static int
1980 flow_dv_translate(struct rte_eth_dev *dev,
1981                   struct mlx5_flow *dev_flow,
1982                   const struct rte_flow_attr *attr,
1983                   const struct rte_flow_item items[],
1984                   const struct rte_flow_action actions[],
1985                   struct rte_flow_error *error)
1986 {
1987         struct priv *priv = dev->data->dev_private;
1988         uint64_t priority = attr->priority;
1989         struct mlx5_flow_dv_matcher matcher = {
1990                 .mask = {
1991                         .size = sizeof(matcher.mask.buf),
1992                 },
1993         };
1994         void *match_value = dev_flow->dv.value.buf;
1995         int tunnel = 0;
1996
1997         if (priority == MLX5_FLOW_PRIO_RSVD)
1998                 priority = priv->config.flow_prio - 1;
1999         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2000                 tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL);
2001                 flow_dv_create_item(&matcher, match_value, items, dev_flow,
2002                                     tunnel);
2003         }
2004         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
2005                                      matcher.mask.size);
2006         if (priority == MLX5_FLOW_PRIO_RSVD)
2007                 priority = priv->config.flow_prio - 1;
2008         matcher.priority = mlx5_flow_adjust_priority(dev, priority,
2009                                                      matcher.priority);
2010         matcher.egress = attr->egress;
2011         if (flow_dv_matcher_register(dev, &matcher, dev_flow, error))
2012                 return -rte_errno;
2013         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++)
2014                 if (flow_dv_create_action(dev, actions, dev_flow, attr, error))
2015                         return -rte_errno;
2016         return 0;
2017 }
2018
2019 /**
2020  * Apply the flow to the NIC.
2021  *
2022  * @param[in] dev
2023  *   Pointer to the Ethernet device structure.
2024  * @param[in, out] flow
2025  *   Pointer to flow structure.
2026  * @param[out] error
2027  *   Pointer to error structure.
2028  *
2029  * @return
2030  *   0 on success, a negative errno value otherwise and rte_errno is set.
2031  */
2032 static int
2033 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
2034               struct rte_flow_error *error)
2035 {
2036         struct mlx5_flow_dv *dv;
2037         struct mlx5_flow *dev_flow;
2038         int n;
2039         int err;
2040
2041         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2042                 dv = &dev_flow->dv;
2043                 n = dv->actions_n;
2044                 if (flow->actions & MLX5_FLOW_ACTION_DROP) {
2045                         dv->hrxq = mlx5_hrxq_drop_new(dev);
2046                         if (!dv->hrxq) {
2047                                 rte_flow_error_set
2048                                         (error, errno,
2049                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2050                                          "cannot get drop hash queue");
2051                                 goto error;
2052                         }
2053                         dv->actions[n].type = MLX5DV_FLOW_ACTION_DEST_IBV_QP;
2054                         dv->actions[n].qp = dv->hrxq->qp;
2055                         n++;
2056                 } else if (flow->actions &
2057                            (MLX5_FLOW_ACTION_QUEUE | MLX5_FLOW_ACTION_RSS)) {
2058                         struct mlx5_hrxq *hrxq;
2059                         hrxq = mlx5_hrxq_get(dev, flow->key,
2060                                              MLX5_RSS_HASH_KEY_LEN,
2061                                              dv->hash_fields,
2062                                              (*flow->queue),
2063                                              flow->rss.queue_num);
2064                         if (!hrxq)
2065                                 hrxq = mlx5_hrxq_new
2066                                         (dev, flow->key, MLX5_RSS_HASH_KEY_LEN,
2067                                          dv->hash_fields, (*flow->queue),
2068                                          flow->rss.queue_num,
2069                                          !!(dev_flow->layers &
2070                                             MLX5_FLOW_LAYER_TUNNEL));
2071                         if (!hrxq) {
2072                                 rte_flow_error_set
2073                                         (error, rte_errno,
2074                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2075                                          "cannot get hash queue");
2076                                 goto error;
2077                         }
2078                         dv->hrxq = hrxq;
2079                         dv->actions[n].type = MLX5DV_FLOW_ACTION_DEST_IBV_QP;
2080                         dv->actions[n].qp = hrxq->qp;
2081                         n++;
2082                 }
2083                 dv->flow =
2084                         mlx5_glue->dv_create_flow(dv->matcher->matcher_object,
2085                                                   (void *)&dv->value, n,
2086                                                   dv->actions);
2087                 if (!dv->flow) {
2088                         rte_flow_error_set(error, errno,
2089                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2090                                            NULL,
2091                                            "hardware refuses to create flow");
2092                         goto error;
2093                 }
2094         }
2095         return 0;
2096 error:
2097         err = rte_errno; /* Save rte_errno before cleanup. */
2098         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2099                 struct mlx5_flow_dv *dv = &dev_flow->dv;
2100                 if (dv->hrxq) {
2101                         if (flow->actions & MLX5_FLOW_ACTION_DROP)
2102                                 mlx5_hrxq_drop_release(dev);
2103                         else
2104                                 mlx5_hrxq_release(dev, dv->hrxq);
2105                         dv->hrxq = NULL;
2106                 }
2107         }
2108         rte_errno = err; /* Restore rte_errno. */
2109         return -rte_errno;
2110 }
2111
2112 /**
2113  * Release the flow matcher.
2114  *
2115  * @param dev
2116  *   Pointer to Ethernet device.
2117  * @param flow
2118  *   Pointer to mlx5_flow.
2119  *
2120  * @return
2121  *   1 while a reference on it exists, 0 when freed.
2122  */
2123 static int
2124 flow_dv_matcher_release(struct rte_eth_dev *dev,
2125                         struct mlx5_flow *flow)
2126 {
2127         struct mlx5_flow_dv_matcher *matcher = flow->dv.matcher;
2128
2129         assert(matcher->matcher_object);
2130         DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
2131                 dev->data->port_id, (void *)matcher,
2132                 rte_atomic32_read(&matcher->refcnt));
2133         if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
2134                 claim_zero(mlx5_glue->dv_destroy_flow_matcher
2135                            (matcher->matcher_object));
2136                 LIST_REMOVE(matcher, next);
2137                 rte_free(matcher);
2138                 DRV_LOG(DEBUG, "port %u matcher %p: removed",
2139                         dev->data->port_id, (void *)matcher);
2140                 return 0;
2141         }
2142         return 1;
2143 }
2144
2145 /**
2146  * Release an encap/decap resource.
2147  *
2148  * @param flow
2149  *   Pointer to mlx5_flow.
2150  *
2151  * @return
2152  *   1 while a reference on it exists, 0 when freed.
2153  */
2154 static int
2155 flow_dv_encap_decap_resource_release(struct mlx5_flow *flow)
2156 {
2157         struct mlx5_flow_dv_encap_decap_resource *cache_resource =
2158                                                 flow->dv.encap_decap;
2159
2160         assert(cache_resource->verbs_action);
2161         DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
2162                 (void *)cache_resource,
2163                 rte_atomic32_read(&cache_resource->refcnt));
2164         if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
2165                 claim_zero(mlx5_glue->destroy_flow_action
2166                                 (cache_resource->verbs_action));
2167                 LIST_REMOVE(cache_resource, next);
2168                 rte_free(cache_resource);
2169                 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
2170                         (void *)cache_resource);
2171                 return 0;
2172         }
2173         return 1;
2174 }
2175
2176 /**
2177  * Remove the flow from the NIC but keeps it in memory.
2178  *
2179  * @param[in] dev
2180  *   Pointer to Ethernet device.
2181  * @param[in, out] flow
2182  *   Pointer to flow structure.
2183  */
2184 static void
2185 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
2186 {
2187         struct mlx5_flow_dv *dv;
2188         struct mlx5_flow *dev_flow;
2189
2190         if (!flow)
2191                 return;
2192         LIST_FOREACH(dev_flow, &flow->dev_flows, next) {
2193                 dv = &dev_flow->dv;
2194                 if (dv->flow) {
2195                         claim_zero(mlx5_glue->destroy_flow(dv->flow));
2196                         dv->flow = NULL;
2197                 }
2198                 if (dv->hrxq) {
2199                         if (flow->actions & MLX5_FLOW_ACTION_DROP)
2200                                 mlx5_hrxq_drop_release(dev);
2201                         else
2202                                 mlx5_hrxq_release(dev, dv->hrxq);
2203                         dv->hrxq = NULL;
2204                 }
2205         }
2206         if (flow->counter)
2207                 flow->counter = NULL;
2208 }
2209
2210 /**
2211  * Remove the flow from the NIC and the memory.
2212  *
2213  * @param[in] dev
2214  *   Pointer to the Ethernet device structure.
2215  * @param[in, out] flow
2216  *   Pointer to flow structure.
2217  */
2218 static void
2219 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
2220 {
2221         struct mlx5_flow *dev_flow;
2222
2223         if (!flow)
2224                 return;
2225         flow_dv_remove(dev, flow);
2226         while (!LIST_EMPTY(&flow->dev_flows)) {
2227                 dev_flow = LIST_FIRST(&flow->dev_flows);
2228                 LIST_REMOVE(dev_flow, next);
2229                 if (dev_flow->dv.matcher)
2230                         flow_dv_matcher_release(dev, dev_flow);
2231                 if (dev_flow->dv.encap_decap)
2232                         flow_dv_encap_decap_resource_release(dev_flow);
2233                 rte_free(dev_flow);
2234         }
2235 }
2236
2237 /**
2238  * Query a flow.
2239  *
2240  * @see rte_flow_query()
2241  * @see rte_flow_ops
2242  */
2243 static int
2244 flow_dv_query(struct rte_eth_dev *dev __rte_unused,
2245               struct rte_flow *flow __rte_unused,
2246               const struct rte_flow_action *actions __rte_unused,
2247               void *data __rte_unused,
2248               struct rte_flow_error *error __rte_unused)
2249 {
2250         rte_errno = ENOTSUP;
2251         return -rte_errno;
2252 }
2253
2254
2255 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
2256         .validate = flow_dv_validate,
2257         .prepare = flow_dv_prepare,
2258         .translate = flow_dv_translate,
2259         .apply = flow_dv_apply,
2260         .remove = flow_dv_remove,
2261         .destroy = flow_dv_destroy,
2262         .query = flow_dv_query,
2263 };
2264
2265 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */