1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2018 Mellanox Technologies, Ltd
11 #include <rte_common.h>
12 #include <rte_ether.h>
13 #include <rte_ethdev_driver.h>
15 #include <rte_flow_driver.h>
16 #include <rte_malloc.h>
17 #include <rte_cycles.h>
20 #include <rte_vxlan.h>
22 #include <rte_eal_paging.h>
25 #include <mlx5_glue.h>
26 #include <mlx5_devx_cmds.h>
28 #include <mlx5_malloc.h>
30 #include "mlx5_defs.h"
32 #include "mlx5_common_os.h"
33 #include "mlx5_flow.h"
34 #include "mlx5_flow_os.h"
35 #include "mlx5_rxtx.h"
37 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
39 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
40 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
43 #ifndef HAVE_MLX5DV_DR_ESWITCH
44 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
45 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
49 #ifndef HAVE_MLX5DV_DR
50 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
53 /* VLAN header definitions */
54 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
55 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
56 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
57 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
58 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
73 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
74 struct mlx5_flow_tbl_resource *tbl);
77 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev);
80 * Initialize flow attributes structure according to flow items' types.
82 * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
83 * mode. For tunnel mode, the items to be modified are the outermost ones.
86 * Pointer to item specification.
88 * Pointer to flow attributes structure.
90 * Pointer to the sub flow.
91 * @param[in] tunnel_decap
92 * Whether action is after tunnel decapsulation.
95 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
96 struct mlx5_flow *dev_flow, bool tunnel_decap)
98 uint64_t layers = dev_flow->handle->layers;
101 * If layers is already initialized, it means this dev_flow is the
102 * suffix flow, the layers flags is set by the prefix flow. Need to
103 * use the layer flags from prefix flow as the suffix flow may not
104 * have the user defined items as the flow is split.
107 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
109 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
111 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
113 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
118 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
119 uint8_t next_protocol = 0xff;
120 switch (item->type) {
121 case RTE_FLOW_ITEM_TYPE_GRE:
122 case RTE_FLOW_ITEM_TYPE_NVGRE:
123 case RTE_FLOW_ITEM_TYPE_VXLAN:
124 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
125 case RTE_FLOW_ITEM_TYPE_GENEVE:
126 case RTE_FLOW_ITEM_TYPE_MPLS:
130 case RTE_FLOW_ITEM_TYPE_IPV4:
133 if (item->mask != NULL &&
134 ((const struct rte_flow_item_ipv4 *)
135 item->mask)->hdr.next_proto_id)
137 ((const struct rte_flow_item_ipv4 *)
138 (item->spec))->hdr.next_proto_id &
139 ((const struct rte_flow_item_ipv4 *)
140 (item->mask))->hdr.next_proto_id;
141 if ((next_protocol == IPPROTO_IPIP ||
142 next_protocol == IPPROTO_IPV6) && tunnel_decap)
145 case RTE_FLOW_ITEM_TYPE_IPV6:
148 if (item->mask != NULL &&
149 ((const struct rte_flow_item_ipv6 *)
150 item->mask)->hdr.proto)
152 ((const struct rte_flow_item_ipv6 *)
153 (item->spec))->hdr.proto &
154 ((const struct rte_flow_item_ipv6 *)
155 (item->mask))->hdr.proto;
156 if ((next_protocol == IPPROTO_IPIP ||
157 next_protocol == IPPROTO_IPV6) && tunnel_decap)
160 case RTE_FLOW_ITEM_TYPE_UDP:
164 case RTE_FLOW_ITEM_TYPE_TCP:
176 * Convert rte_mtr_color to mlx5 color.
185 rte_col_2_mlx5_col(enum rte_color rcol)
188 case RTE_COLOR_GREEN:
189 return MLX5_FLOW_COLOR_GREEN;
190 case RTE_COLOR_YELLOW:
191 return MLX5_FLOW_COLOR_YELLOW;
193 return MLX5_FLOW_COLOR_RED;
197 return MLX5_FLOW_COLOR_UNDEFINED;
200 struct field_modify_info {
201 uint32_t size; /* Size of field in protocol header, in bytes. */
202 uint32_t offset; /* Offset of field in protocol header, in bytes. */
203 enum mlx5_modification_field id;
206 struct field_modify_info modify_eth[] = {
207 {4, 0, MLX5_MODI_OUT_DMAC_47_16},
208 {2, 4, MLX5_MODI_OUT_DMAC_15_0},
209 {4, 6, MLX5_MODI_OUT_SMAC_47_16},
210 {2, 10, MLX5_MODI_OUT_SMAC_15_0},
214 struct field_modify_info modify_vlan_out_first_vid[] = {
215 /* Size in bits !!! */
216 {12, 0, MLX5_MODI_OUT_FIRST_VID},
220 struct field_modify_info modify_ipv4[] = {
221 {1, 1, MLX5_MODI_OUT_IP_DSCP},
222 {1, 8, MLX5_MODI_OUT_IPV4_TTL},
223 {4, 12, MLX5_MODI_OUT_SIPV4},
224 {4, 16, MLX5_MODI_OUT_DIPV4},
228 struct field_modify_info modify_ipv6[] = {
229 {1, 0, MLX5_MODI_OUT_IP_DSCP},
230 {1, 7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
231 {4, 8, MLX5_MODI_OUT_SIPV6_127_96},
232 {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
233 {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
234 {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
235 {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
236 {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
237 {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
238 {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
242 struct field_modify_info modify_udp[] = {
243 {2, 0, MLX5_MODI_OUT_UDP_SPORT},
244 {2, 2, MLX5_MODI_OUT_UDP_DPORT},
248 struct field_modify_info modify_tcp[] = {
249 {2, 0, MLX5_MODI_OUT_TCP_SPORT},
250 {2, 2, MLX5_MODI_OUT_TCP_DPORT},
251 {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
252 {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
257 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
258 uint8_t next_protocol, uint64_t *item_flags,
261 MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
262 item->type == RTE_FLOW_ITEM_TYPE_IPV6);
263 if (next_protocol == IPPROTO_IPIP) {
264 *item_flags |= MLX5_FLOW_LAYER_IPIP;
267 if (next_protocol == IPPROTO_IPV6) {
268 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
274 * Acquire the synchronizing object to protect multithreaded access
275 * to shared dv context. Lock occurs only if context is actually
276 * shared, i.e. we have multiport IB device and representors are
280 * Pointer to the rte_eth_dev structure.
283 flow_dv_shared_lock(struct rte_eth_dev *dev)
285 struct mlx5_priv *priv = dev->data->dev_private;
286 struct mlx5_dev_ctx_shared *sh = priv->sh;
288 if (sh->dv_refcnt > 1) {
291 ret = pthread_mutex_lock(&sh->dv_mutex);
298 flow_dv_shared_unlock(struct rte_eth_dev *dev)
300 struct mlx5_priv *priv = dev->data->dev_private;
301 struct mlx5_dev_ctx_shared *sh = priv->sh;
303 if (sh->dv_refcnt > 1) {
306 ret = pthread_mutex_unlock(&sh->dv_mutex);
312 /* Update VLAN's VID/PCP based on input rte_flow_action.
315 * Pointer to struct rte_flow_action.
317 * Pointer to struct rte_vlan_hdr.
320 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
321 struct rte_vlan_hdr *vlan)
324 if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
326 ((const struct rte_flow_action_of_set_vlan_pcp *)
327 action->conf)->vlan_pcp;
328 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
329 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
330 vlan->vlan_tci |= vlan_tci;
331 } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
332 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
333 vlan->vlan_tci |= rte_be_to_cpu_16
334 (((const struct rte_flow_action_of_set_vlan_vid *)
335 action->conf)->vlan_vid);
340 * Fetch 1, 2, 3 or 4 byte field from the byte array
341 * and return as unsigned integer in host-endian format.
344 * Pointer to data array.
346 * Size of field to extract.
349 * converted field in host endian format.
351 static inline uint32_t
352 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
361 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
364 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
365 ret = (ret << 8) | *(data + sizeof(uint16_t));
368 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
379 * Convert modify-header action to DV specification.
381 * Data length of each action is determined by provided field description
382 * and the item mask. Data bit offset and width of each action is determined
383 * by provided item mask.
386 * Pointer to item specification.
388 * Pointer to field modification information.
389 * For MLX5_MODIFICATION_TYPE_SET specifies destination field.
390 * For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
391 * For MLX5_MODIFICATION_TYPE_COPY specifies source field.
393 * Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
394 * Negative offset value sets the same offset as source offset.
395 * size field is ignored, value is taken from source field.
396 * @param[in,out] resource
397 * Pointer to the modify-header resource.
399 * Type of modification.
401 * Pointer to the error structure.
404 * 0 on success, a negative errno value otherwise and rte_errno is set.
407 flow_dv_convert_modify_action(struct rte_flow_item *item,
408 struct field_modify_info *field,
409 struct field_modify_info *dcopy,
410 struct mlx5_flow_dv_modify_hdr_resource *resource,
411 uint32_t type, struct rte_flow_error *error)
413 uint32_t i = resource->actions_num;
414 struct mlx5_modification_cmd *actions = resource->actions;
417 * The item and mask are provided in big-endian format.
418 * The fields should be presented as in big-endian format either.
419 * Mask must be always present, it defines the actual field width.
421 MLX5_ASSERT(item->mask);
422 MLX5_ASSERT(field->size);
429 if (i >= MLX5_MAX_MODIFY_NUM)
430 return rte_flow_error_set(error, EINVAL,
431 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
432 "too many items to modify");
433 /* Fetch variable byte size mask from the array. */
434 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
435 field->offset, field->size);
440 /* Deduce actual data width in bits from mask value. */
441 off_b = rte_bsf32(mask);
442 size_b = sizeof(uint32_t) * CHAR_BIT -
443 off_b - __builtin_clz(mask);
445 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
446 actions[i] = (struct mlx5_modification_cmd) {
452 /* Convert entire record to expected big-endian format. */
453 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
454 if (type == MLX5_MODIFICATION_TYPE_COPY) {
456 actions[i].dst_field = dcopy->id;
457 actions[i].dst_offset =
458 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
459 /* Convert entire record to big-endian format. */
460 actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
462 MLX5_ASSERT(item->spec);
463 data = flow_dv_fetch_field((const uint8_t *)item->spec +
464 field->offset, field->size);
465 /* Shift out the trailing masked bits from data. */
466 data = (data & mask) >> off_b;
467 actions[i].data1 = rte_cpu_to_be_32(data);
471 } while (field->size);
472 if (resource->actions_num == i)
473 return rte_flow_error_set(error, EINVAL,
474 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
475 "invalid modification flow item");
476 resource->actions_num = i;
481 * Convert modify-header set IPv4 address action to DV specification.
483 * @param[in,out] resource
484 * Pointer to the modify-header resource.
486 * Pointer to action specification.
488 * Pointer to the error structure.
491 * 0 on success, a negative errno value otherwise and rte_errno is set.
494 flow_dv_convert_action_modify_ipv4
495 (struct mlx5_flow_dv_modify_hdr_resource *resource,
496 const struct rte_flow_action *action,
497 struct rte_flow_error *error)
499 const struct rte_flow_action_set_ipv4 *conf =
500 (const struct rte_flow_action_set_ipv4 *)(action->conf);
501 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
502 struct rte_flow_item_ipv4 ipv4;
503 struct rte_flow_item_ipv4 ipv4_mask;
505 memset(&ipv4, 0, sizeof(ipv4));
506 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
507 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
508 ipv4.hdr.src_addr = conf->ipv4_addr;
509 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
511 ipv4.hdr.dst_addr = conf->ipv4_addr;
512 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
515 item.mask = &ipv4_mask;
516 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
517 MLX5_MODIFICATION_TYPE_SET, error);
521 * Convert modify-header set IPv6 address action to DV specification.
523 * @param[in,out] resource
524 * Pointer to the modify-header resource.
526 * Pointer to action specification.
528 * Pointer to the error structure.
531 * 0 on success, a negative errno value otherwise and rte_errno is set.
534 flow_dv_convert_action_modify_ipv6
535 (struct mlx5_flow_dv_modify_hdr_resource *resource,
536 const struct rte_flow_action *action,
537 struct rte_flow_error *error)
539 const struct rte_flow_action_set_ipv6 *conf =
540 (const struct rte_flow_action_set_ipv6 *)(action->conf);
541 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
542 struct rte_flow_item_ipv6 ipv6;
543 struct rte_flow_item_ipv6 ipv6_mask;
545 memset(&ipv6, 0, sizeof(ipv6));
546 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
547 if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
548 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
549 sizeof(ipv6.hdr.src_addr));
550 memcpy(&ipv6_mask.hdr.src_addr,
551 &rte_flow_item_ipv6_mask.hdr.src_addr,
552 sizeof(ipv6.hdr.src_addr));
554 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
555 sizeof(ipv6.hdr.dst_addr));
556 memcpy(&ipv6_mask.hdr.dst_addr,
557 &rte_flow_item_ipv6_mask.hdr.dst_addr,
558 sizeof(ipv6.hdr.dst_addr));
561 item.mask = &ipv6_mask;
562 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
563 MLX5_MODIFICATION_TYPE_SET, error);
567 * Convert modify-header set MAC address action to DV specification.
569 * @param[in,out] resource
570 * Pointer to the modify-header resource.
572 * Pointer to action specification.
574 * Pointer to the error structure.
577 * 0 on success, a negative errno value otherwise and rte_errno is set.
580 flow_dv_convert_action_modify_mac
581 (struct mlx5_flow_dv_modify_hdr_resource *resource,
582 const struct rte_flow_action *action,
583 struct rte_flow_error *error)
585 const struct rte_flow_action_set_mac *conf =
586 (const struct rte_flow_action_set_mac *)(action->conf);
587 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
588 struct rte_flow_item_eth eth;
589 struct rte_flow_item_eth eth_mask;
591 memset(ð, 0, sizeof(eth));
592 memset(ð_mask, 0, sizeof(eth_mask));
593 if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
594 memcpy(ð.src.addr_bytes, &conf->mac_addr,
595 sizeof(eth.src.addr_bytes));
596 memcpy(ð_mask.src.addr_bytes,
597 &rte_flow_item_eth_mask.src.addr_bytes,
598 sizeof(eth_mask.src.addr_bytes));
600 memcpy(ð.dst.addr_bytes, &conf->mac_addr,
601 sizeof(eth.dst.addr_bytes));
602 memcpy(ð_mask.dst.addr_bytes,
603 &rte_flow_item_eth_mask.dst.addr_bytes,
604 sizeof(eth_mask.dst.addr_bytes));
607 item.mask = ð_mask;
608 return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
609 MLX5_MODIFICATION_TYPE_SET, error);
613 * Convert modify-header set VLAN VID action to DV specification.
615 * @param[in,out] resource
616 * Pointer to the modify-header resource.
618 * Pointer to action specification.
620 * Pointer to the error structure.
623 * 0 on success, a negative errno value otherwise and rte_errno is set.
626 flow_dv_convert_action_modify_vlan_vid
627 (struct mlx5_flow_dv_modify_hdr_resource *resource,
628 const struct rte_flow_action *action,
629 struct rte_flow_error *error)
631 const struct rte_flow_action_of_set_vlan_vid *conf =
632 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
633 int i = resource->actions_num;
634 struct mlx5_modification_cmd *actions = resource->actions;
635 struct field_modify_info *field = modify_vlan_out_first_vid;
637 if (i >= MLX5_MAX_MODIFY_NUM)
638 return rte_flow_error_set(error, EINVAL,
639 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
640 "too many items to modify");
641 actions[i] = (struct mlx5_modification_cmd) {
642 .action_type = MLX5_MODIFICATION_TYPE_SET,
644 .length = field->size,
645 .offset = field->offset,
647 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
648 actions[i].data1 = conf->vlan_vid;
649 actions[i].data1 = actions[i].data1 << 16;
650 resource->actions_num = ++i;
655 * Convert modify-header set TP action to DV specification.
657 * @param[in,out] resource
658 * Pointer to the modify-header resource.
660 * Pointer to action specification.
662 * Pointer to rte_flow_item objects list.
664 * Pointer to flow attributes structure.
665 * @param[in] dev_flow
666 * Pointer to the sub flow.
667 * @param[in] tunnel_decap
668 * Whether action is after tunnel decapsulation.
670 * Pointer to the error structure.
673 * 0 on success, a negative errno value otherwise and rte_errno is set.
676 flow_dv_convert_action_modify_tp
677 (struct mlx5_flow_dv_modify_hdr_resource *resource,
678 const struct rte_flow_action *action,
679 const struct rte_flow_item *items,
680 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
681 bool tunnel_decap, struct rte_flow_error *error)
683 const struct rte_flow_action_set_tp *conf =
684 (const struct rte_flow_action_set_tp *)(action->conf);
685 struct rte_flow_item item;
686 struct rte_flow_item_udp udp;
687 struct rte_flow_item_udp udp_mask;
688 struct rte_flow_item_tcp tcp;
689 struct rte_flow_item_tcp tcp_mask;
690 struct field_modify_info *field;
693 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
695 memset(&udp, 0, sizeof(udp));
696 memset(&udp_mask, 0, sizeof(udp_mask));
697 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
698 udp.hdr.src_port = conf->port;
699 udp_mask.hdr.src_port =
700 rte_flow_item_udp_mask.hdr.src_port;
702 udp.hdr.dst_port = conf->port;
703 udp_mask.hdr.dst_port =
704 rte_flow_item_udp_mask.hdr.dst_port;
706 item.type = RTE_FLOW_ITEM_TYPE_UDP;
708 item.mask = &udp_mask;
711 MLX5_ASSERT(attr->tcp);
712 memset(&tcp, 0, sizeof(tcp));
713 memset(&tcp_mask, 0, sizeof(tcp_mask));
714 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
715 tcp.hdr.src_port = conf->port;
716 tcp_mask.hdr.src_port =
717 rte_flow_item_tcp_mask.hdr.src_port;
719 tcp.hdr.dst_port = conf->port;
720 tcp_mask.hdr.dst_port =
721 rte_flow_item_tcp_mask.hdr.dst_port;
723 item.type = RTE_FLOW_ITEM_TYPE_TCP;
725 item.mask = &tcp_mask;
728 return flow_dv_convert_modify_action(&item, field, NULL, resource,
729 MLX5_MODIFICATION_TYPE_SET, error);
733 * Convert modify-header set TTL action to DV specification.
735 * @param[in,out] resource
736 * Pointer to the modify-header resource.
738 * Pointer to action specification.
740 * Pointer to rte_flow_item objects list.
742 * Pointer to flow attributes structure.
743 * @param[in] dev_flow
744 * Pointer to the sub flow.
745 * @param[in] tunnel_decap
746 * Whether action is after tunnel decapsulation.
748 * Pointer to the error structure.
751 * 0 on success, a negative errno value otherwise and rte_errno is set.
754 flow_dv_convert_action_modify_ttl
755 (struct mlx5_flow_dv_modify_hdr_resource *resource,
756 const struct rte_flow_action *action,
757 const struct rte_flow_item *items,
758 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
759 bool tunnel_decap, struct rte_flow_error *error)
761 const struct rte_flow_action_set_ttl *conf =
762 (const struct rte_flow_action_set_ttl *)(action->conf);
763 struct rte_flow_item item;
764 struct rte_flow_item_ipv4 ipv4;
765 struct rte_flow_item_ipv4 ipv4_mask;
766 struct rte_flow_item_ipv6 ipv6;
767 struct rte_flow_item_ipv6 ipv6_mask;
768 struct field_modify_info *field;
771 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
773 memset(&ipv4, 0, sizeof(ipv4));
774 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
775 ipv4.hdr.time_to_live = conf->ttl_value;
776 ipv4_mask.hdr.time_to_live = 0xFF;
777 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
779 item.mask = &ipv4_mask;
782 MLX5_ASSERT(attr->ipv6);
783 memset(&ipv6, 0, sizeof(ipv6));
784 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
785 ipv6.hdr.hop_limits = conf->ttl_value;
786 ipv6_mask.hdr.hop_limits = 0xFF;
787 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
789 item.mask = &ipv6_mask;
792 return flow_dv_convert_modify_action(&item, field, NULL, resource,
793 MLX5_MODIFICATION_TYPE_SET, error);
797 * Convert modify-header decrement TTL action to DV specification.
799 * @param[in,out] resource
800 * Pointer to the modify-header resource.
802 * Pointer to action specification.
804 * Pointer to rte_flow_item objects list.
806 * Pointer to flow attributes structure.
807 * @param[in] dev_flow
808 * Pointer to the sub flow.
809 * @param[in] tunnel_decap
810 * Whether action is after tunnel decapsulation.
812 * Pointer to the error structure.
815 * 0 on success, a negative errno value otherwise and rte_errno is set.
818 flow_dv_convert_action_modify_dec_ttl
819 (struct mlx5_flow_dv_modify_hdr_resource *resource,
820 const struct rte_flow_item *items,
821 union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
822 bool tunnel_decap, struct rte_flow_error *error)
824 struct rte_flow_item item;
825 struct rte_flow_item_ipv4 ipv4;
826 struct rte_flow_item_ipv4 ipv4_mask;
827 struct rte_flow_item_ipv6 ipv6;
828 struct rte_flow_item_ipv6 ipv6_mask;
829 struct field_modify_info *field;
832 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
834 memset(&ipv4, 0, sizeof(ipv4));
835 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
836 ipv4.hdr.time_to_live = 0xFF;
837 ipv4_mask.hdr.time_to_live = 0xFF;
838 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
840 item.mask = &ipv4_mask;
843 MLX5_ASSERT(attr->ipv6);
844 memset(&ipv6, 0, sizeof(ipv6));
845 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
846 ipv6.hdr.hop_limits = 0xFF;
847 ipv6_mask.hdr.hop_limits = 0xFF;
848 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
850 item.mask = &ipv6_mask;
853 return flow_dv_convert_modify_action(&item, field, NULL, resource,
854 MLX5_MODIFICATION_TYPE_ADD, error);
858 * Convert modify-header increment/decrement TCP Sequence number
859 * to DV specification.
861 * @param[in,out] resource
862 * Pointer to the modify-header resource.
864 * Pointer to action specification.
866 * Pointer to the error structure.
869 * 0 on success, a negative errno value otherwise and rte_errno is set.
872 flow_dv_convert_action_modify_tcp_seq
873 (struct mlx5_flow_dv_modify_hdr_resource *resource,
874 const struct rte_flow_action *action,
875 struct rte_flow_error *error)
877 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
878 uint64_t value = rte_be_to_cpu_32(*conf);
879 struct rte_flow_item item;
880 struct rte_flow_item_tcp tcp;
881 struct rte_flow_item_tcp tcp_mask;
883 memset(&tcp, 0, sizeof(tcp));
884 memset(&tcp_mask, 0, sizeof(tcp_mask));
885 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
887 * The HW has no decrement operation, only increment operation.
888 * To simulate decrement X from Y using increment operation
889 * we need to add UINT32_MAX X times to Y.
890 * Each adding of UINT32_MAX decrements Y by 1.
893 tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
894 tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
895 item.type = RTE_FLOW_ITEM_TYPE_TCP;
897 item.mask = &tcp_mask;
898 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
899 MLX5_MODIFICATION_TYPE_ADD, error);
903 * Convert modify-header increment/decrement TCP Acknowledgment number
904 * to DV specification.
906 * @param[in,out] resource
907 * Pointer to the modify-header resource.
909 * Pointer to action specification.
911 * Pointer to the error structure.
914 * 0 on success, a negative errno value otherwise and rte_errno is set.
917 flow_dv_convert_action_modify_tcp_ack
918 (struct mlx5_flow_dv_modify_hdr_resource *resource,
919 const struct rte_flow_action *action,
920 struct rte_flow_error *error)
922 const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
923 uint64_t value = rte_be_to_cpu_32(*conf);
924 struct rte_flow_item item;
925 struct rte_flow_item_tcp tcp;
926 struct rte_flow_item_tcp tcp_mask;
928 memset(&tcp, 0, sizeof(tcp));
929 memset(&tcp_mask, 0, sizeof(tcp_mask));
930 if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
932 * The HW has no decrement operation, only increment operation.
933 * To simulate decrement X from Y using increment operation
934 * we need to add UINT32_MAX X times to Y.
935 * Each adding of UINT32_MAX decrements Y by 1.
938 tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
939 tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
940 item.type = RTE_FLOW_ITEM_TYPE_TCP;
942 item.mask = &tcp_mask;
943 return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
944 MLX5_MODIFICATION_TYPE_ADD, error);
947 static enum mlx5_modification_field reg_to_field[] = {
948 [REG_NONE] = MLX5_MODI_OUT_NONE,
949 [REG_A] = MLX5_MODI_META_DATA_REG_A,
950 [REG_B] = MLX5_MODI_META_DATA_REG_B,
951 [REG_C_0] = MLX5_MODI_META_REG_C_0,
952 [REG_C_1] = MLX5_MODI_META_REG_C_1,
953 [REG_C_2] = MLX5_MODI_META_REG_C_2,
954 [REG_C_3] = MLX5_MODI_META_REG_C_3,
955 [REG_C_4] = MLX5_MODI_META_REG_C_4,
956 [REG_C_5] = MLX5_MODI_META_REG_C_5,
957 [REG_C_6] = MLX5_MODI_META_REG_C_6,
958 [REG_C_7] = MLX5_MODI_META_REG_C_7,
962 * Convert register set to DV specification.
964 * @param[in,out] resource
965 * Pointer to the modify-header resource.
967 * Pointer to action specification.
969 * Pointer to the error structure.
972 * 0 on success, a negative errno value otherwise and rte_errno is set.
975 flow_dv_convert_action_set_reg
976 (struct mlx5_flow_dv_modify_hdr_resource *resource,
977 const struct rte_flow_action *action,
978 struct rte_flow_error *error)
980 const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
981 struct mlx5_modification_cmd *actions = resource->actions;
982 uint32_t i = resource->actions_num;
984 if (i >= MLX5_MAX_MODIFY_NUM)
985 return rte_flow_error_set(error, EINVAL,
986 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
987 "too many items to modify");
988 MLX5_ASSERT(conf->id != REG_NONE);
989 MLX5_ASSERT(conf->id < RTE_DIM(reg_to_field));
990 actions[i] = (struct mlx5_modification_cmd) {
991 .action_type = MLX5_MODIFICATION_TYPE_SET,
992 .field = reg_to_field[conf->id],
994 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
995 actions[i].data1 = rte_cpu_to_be_32(conf->data);
997 resource->actions_num = i;
1002 * Convert SET_TAG action to DV specification.
1005 * Pointer to the rte_eth_dev structure.
1006 * @param[in,out] resource
1007 * Pointer to the modify-header resource.
1009 * Pointer to action specification.
1011 * Pointer to the error structure.
1014 * 0 on success, a negative errno value otherwise and rte_errno is set.
1017 flow_dv_convert_action_set_tag
1018 (struct rte_eth_dev *dev,
1019 struct mlx5_flow_dv_modify_hdr_resource *resource,
1020 const struct rte_flow_action_set_tag *conf,
1021 struct rte_flow_error *error)
1023 rte_be32_t data = rte_cpu_to_be_32(conf->data);
1024 rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
1025 struct rte_flow_item item = {
1029 struct field_modify_info reg_c_x[] = {
1032 enum mlx5_modification_field reg_type;
1035 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1038 MLX5_ASSERT(ret != REG_NONE);
1039 MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1040 reg_type = reg_to_field[ret];
1041 MLX5_ASSERT(reg_type > 0);
1042 reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1043 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1044 MLX5_MODIFICATION_TYPE_SET, error);
1048 * Convert internal COPY_REG action to DV specification.
1051 * Pointer to the rte_eth_dev structure.
1052 * @param[in,out] res
1053 * Pointer to the modify-header resource.
1055 * Pointer to action specification.
1057 * Pointer to the error structure.
1060 * 0 on success, a negative errno value otherwise and rte_errno is set.
1063 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1064 struct mlx5_flow_dv_modify_hdr_resource *res,
1065 const struct rte_flow_action *action,
1066 struct rte_flow_error *error)
1068 const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1069 rte_be32_t mask = RTE_BE32(UINT32_MAX);
1070 struct rte_flow_item item = {
1074 struct field_modify_info reg_src[] = {
1075 {4, 0, reg_to_field[conf->src]},
1078 struct field_modify_info reg_dst = {
1080 .id = reg_to_field[conf->dst],
1082 /* Adjust reg_c[0] usage according to reported mask. */
1083 if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1084 struct mlx5_priv *priv = dev->data->dev_private;
1085 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1087 MLX5_ASSERT(reg_c0);
1088 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1089 if (conf->dst == REG_C_0) {
1090 /* Copy to reg_c[0], within mask only. */
1091 reg_dst.offset = rte_bsf32(reg_c0);
1093 * Mask is ignoring the enianness, because
1094 * there is no conversion in datapath.
1096 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1097 /* Copy from destination lower bits to reg_c[0]. */
1098 mask = reg_c0 >> reg_dst.offset;
1100 /* Copy from destination upper bits to reg_c[0]. */
1101 mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1102 rte_fls_u32(reg_c0));
1105 mask = rte_cpu_to_be_32(reg_c0);
1106 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1107 /* Copy from reg_c[0] to destination lower bits. */
1110 /* Copy from reg_c[0] to destination upper bits. */
1111 reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1112 (rte_fls_u32(reg_c0) -
1117 return flow_dv_convert_modify_action(&item,
1118 reg_src, ®_dst, res,
1119 MLX5_MODIFICATION_TYPE_COPY,
1124 * Convert MARK action to DV specification. This routine is used
1125 * in extensive metadata only and requires metadata register to be
1126 * handled. In legacy mode hardware tag resource is engaged.
1129 * Pointer to the rte_eth_dev structure.
1131 * Pointer to MARK action specification.
1132 * @param[in,out] resource
1133 * Pointer to the modify-header resource.
1135 * Pointer to the error structure.
1138 * 0 on success, a negative errno value otherwise and rte_errno is set.
1141 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1142 const struct rte_flow_action_mark *conf,
1143 struct mlx5_flow_dv_modify_hdr_resource *resource,
1144 struct rte_flow_error *error)
1146 struct mlx5_priv *priv = dev->data->dev_private;
1147 rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1148 priv->sh->dv_mark_mask);
1149 rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1150 struct rte_flow_item item = {
1154 struct field_modify_info reg_c_x[] = {
1155 {4, 0, 0}, /* dynamic instead of MLX5_MODI_META_REG_C_1. */
1161 return rte_flow_error_set(error, EINVAL,
1162 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1163 NULL, "zero mark action mask");
1164 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1167 MLX5_ASSERT(reg > 0);
1168 if (reg == REG_C_0) {
1169 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1170 uint32_t shl_c0 = rte_bsf32(msk_c0);
1172 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1173 mask = rte_cpu_to_be_32(mask) & msk_c0;
1174 mask = rte_cpu_to_be_32(mask << shl_c0);
1176 reg_c_x[0].id = reg_to_field[reg];
1177 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1178 MLX5_MODIFICATION_TYPE_SET, error);
1182 * Get metadata register index for specified steering domain.
1185 * Pointer to the rte_eth_dev structure.
1187 * Attributes of flow to determine steering domain.
1189 * Pointer to the error structure.
1192 * positive index on success, a negative errno value otherwise
1193 * and rte_errno is set.
1195 static enum modify_reg
1196 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1197 const struct rte_flow_attr *attr,
1198 struct rte_flow_error *error)
1201 mlx5_flow_get_reg_id(dev, attr->transfer ?
1205 MLX5_METADATA_RX, 0, error);
1207 return rte_flow_error_set(error,
1208 ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1209 NULL, "unavailable "
1210 "metadata register");
1215 * Convert SET_META action to DV specification.
1218 * Pointer to the rte_eth_dev structure.
1219 * @param[in,out] resource
1220 * Pointer to the modify-header resource.
1222 * Attributes of flow that includes this item.
1224 * Pointer to action specification.
1226 * Pointer to the error structure.
1229 * 0 on success, a negative errno value otherwise and rte_errno is set.
1232 flow_dv_convert_action_set_meta
1233 (struct rte_eth_dev *dev,
1234 struct mlx5_flow_dv_modify_hdr_resource *resource,
1235 const struct rte_flow_attr *attr,
1236 const struct rte_flow_action_set_meta *conf,
1237 struct rte_flow_error *error)
1239 uint32_t data = conf->data;
1240 uint32_t mask = conf->mask;
1241 struct rte_flow_item item = {
1245 struct field_modify_info reg_c_x[] = {
1248 int reg = flow_dv_get_metadata_reg(dev, attr, error);
1253 * In datapath code there is no endianness
1254 * coversions for perfromance reasons, all
1255 * pattern conversions are done in rte_flow.
1257 if (reg == REG_C_0) {
1258 struct mlx5_priv *priv = dev->data->dev_private;
1259 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1262 MLX5_ASSERT(msk_c0);
1263 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1264 shl_c0 = rte_bsf32(msk_c0);
1266 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1270 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1272 reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1273 /* The routine expects parameters in memory as big-endian ones. */
1274 return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1275 MLX5_MODIFICATION_TYPE_SET, error);
1279 * Convert modify-header set IPv4 DSCP action to DV specification.
1281 * @param[in,out] resource
1282 * Pointer to the modify-header resource.
1284 * Pointer to action specification.
1286 * Pointer to the error structure.
1289 * 0 on success, a negative errno value otherwise and rte_errno is set.
1292 flow_dv_convert_action_modify_ipv4_dscp
1293 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1294 const struct rte_flow_action *action,
1295 struct rte_flow_error *error)
1297 const struct rte_flow_action_set_dscp *conf =
1298 (const struct rte_flow_action_set_dscp *)(action->conf);
1299 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1300 struct rte_flow_item_ipv4 ipv4;
1301 struct rte_flow_item_ipv4 ipv4_mask;
1303 memset(&ipv4, 0, sizeof(ipv4));
1304 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1305 ipv4.hdr.type_of_service = conf->dscp;
1306 ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1308 item.mask = &ipv4_mask;
1309 return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1310 MLX5_MODIFICATION_TYPE_SET, error);
1314 * Convert modify-header set IPv6 DSCP action to DV specification.
1316 * @param[in,out] resource
1317 * Pointer to the modify-header resource.
1319 * Pointer to action specification.
1321 * Pointer to the error structure.
1324 * 0 on success, a negative errno value otherwise and rte_errno is set.
1327 flow_dv_convert_action_modify_ipv6_dscp
1328 (struct mlx5_flow_dv_modify_hdr_resource *resource,
1329 const struct rte_flow_action *action,
1330 struct rte_flow_error *error)
1332 const struct rte_flow_action_set_dscp *conf =
1333 (const struct rte_flow_action_set_dscp *)(action->conf);
1334 struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1335 struct rte_flow_item_ipv6 ipv6;
1336 struct rte_flow_item_ipv6 ipv6_mask;
1338 memset(&ipv6, 0, sizeof(ipv6));
1339 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1341 * Even though the DSCP bits offset of IPv6 is not byte aligned,
1342 * rdma-core only accept the DSCP bits byte aligned start from
1343 * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1344 * bits in IPv6 case as rdma-core requires byte aligned value.
1346 ipv6.hdr.vtc_flow = conf->dscp;
1347 ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1349 item.mask = &ipv6_mask;
1350 return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1351 MLX5_MODIFICATION_TYPE_SET, error);
1355 * Validate MARK item.
1358 * Pointer to the rte_eth_dev structure.
1360 * Item specification.
1362 * Attributes of flow that includes this item.
1364 * Pointer to error structure.
1367 * 0 on success, a negative errno value otherwise and rte_errno is set.
1370 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1371 const struct rte_flow_item *item,
1372 const struct rte_flow_attr *attr __rte_unused,
1373 struct rte_flow_error *error)
1375 struct mlx5_priv *priv = dev->data->dev_private;
1376 struct mlx5_dev_config *config = &priv->config;
1377 const struct rte_flow_item_mark *spec = item->spec;
1378 const struct rte_flow_item_mark *mask = item->mask;
1379 const struct rte_flow_item_mark nic_mask = {
1380 .id = priv->sh->dv_mark_mask,
1384 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1385 return rte_flow_error_set(error, ENOTSUP,
1386 RTE_FLOW_ERROR_TYPE_ITEM, item,
1387 "extended metadata feature"
1389 if (!mlx5_flow_ext_mreg_supported(dev))
1390 return rte_flow_error_set(error, ENOTSUP,
1391 RTE_FLOW_ERROR_TYPE_ITEM, item,
1392 "extended metadata register"
1393 " isn't supported");
1395 return rte_flow_error_set(error, ENOTSUP,
1396 RTE_FLOW_ERROR_TYPE_ITEM, item,
1397 "extended metadata register"
1398 " isn't available");
1399 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1403 return rte_flow_error_set(error, EINVAL,
1404 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1406 "data cannot be empty");
1407 if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1408 return rte_flow_error_set(error, EINVAL,
1409 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1411 "mark id exceeds the limit");
1415 return rte_flow_error_set(error, EINVAL,
1416 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1417 "mask cannot be zero");
1419 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1420 (const uint8_t *)&nic_mask,
1421 sizeof(struct rte_flow_item_mark),
1429 * Validate META item.
1432 * Pointer to the rte_eth_dev structure.
1434 * Item specification.
1436 * Attributes of flow that includes this item.
1438 * Pointer to error structure.
1441 * 0 on success, a negative errno value otherwise and rte_errno is set.
1444 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1445 const struct rte_flow_item *item,
1446 const struct rte_flow_attr *attr,
1447 struct rte_flow_error *error)
1449 struct mlx5_priv *priv = dev->data->dev_private;
1450 struct mlx5_dev_config *config = &priv->config;
1451 const struct rte_flow_item_meta *spec = item->spec;
1452 const struct rte_flow_item_meta *mask = item->mask;
1453 struct rte_flow_item_meta nic_mask = {
1460 return rte_flow_error_set(error, EINVAL,
1461 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1463 "data cannot be empty");
1464 if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1465 if (!mlx5_flow_ext_mreg_supported(dev))
1466 return rte_flow_error_set(error, ENOTSUP,
1467 RTE_FLOW_ERROR_TYPE_ITEM, item,
1468 "extended metadata register"
1469 " isn't supported");
1470 reg = flow_dv_get_metadata_reg(dev, attr, error);
1474 return rte_flow_error_set(error, ENOTSUP,
1475 RTE_FLOW_ERROR_TYPE_ITEM, item,
1479 nic_mask.data = priv->sh->dv_meta_mask;
1480 } else if (attr->transfer) {
1481 return rte_flow_error_set(error, ENOTSUP,
1482 RTE_FLOW_ERROR_TYPE_ITEM, item,
1483 "extended metadata feature "
1484 "should be enabled when "
1485 "meta item is requested "
1486 "with e-switch mode ");
1489 mask = &rte_flow_item_meta_mask;
1491 return rte_flow_error_set(error, EINVAL,
1492 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1493 "mask cannot be zero");
1495 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1496 (const uint8_t *)&nic_mask,
1497 sizeof(struct rte_flow_item_meta),
1503 * Validate TAG item.
1506 * Pointer to the rte_eth_dev structure.
1508 * Item specification.
1510 * Attributes of flow that includes this item.
1512 * Pointer to error structure.
1515 * 0 on success, a negative errno value otherwise and rte_errno is set.
1518 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1519 const struct rte_flow_item *item,
1520 const struct rte_flow_attr *attr __rte_unused,
1521 struct rte_flow_error *error)
1523 const struct rte_flow_item_tag *spec = item->spec;
1524 const struct rte_flow_item_tag *mask = item->mask;
1525 const struct rte_flow_item_tag nic_mask = {
1526 .data = RTE_BE32(UINT32_MAX),
1531 if (!mlx5_flow_ext_mreg_supported(dev))
1532 return rte_flow_error_set(error, ENOTSUP,
1533 RTE_FLOW_ERROR_TYPE_ITEM, item,
1534 "extensive metadata register"
1535 " isn't supported");
1537 return rte_flow_error_set(error, EINVAL,
1538 RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1540 "data cannot be empty");
1542 mask = &rte_flow_item_tag_mask;
1544 return rte_flow_error_set(error, EINVAL,
1545 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1546 "mask cannot be zero");
1548 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1549 (const uint8_t *)&nic_mask,
1550 sizeof(struct rte_flow_item_tag),
1554 if (mask->index != 0xff)
1555 return rte_flow_error_set(error, EINVAL,
1556 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1557 "partial mask for tag index"
1558 " is not supported");
1559 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
1562 MLX5_ASSERT(ret != REG_NONE);
1567 * Validate vport item.
1570 * Pointer to the rte_eth_dev structure.
1572 * Item specification.
1574 * Attributes of flow that includes this item.
1575 * @param[in] item_flags
1576 * Bit-fields that holds the items detected until now.
1578 * Pointer to error structure.
1581 * 0 on success, a negative errno value otherwise and rte_errno is set.
1584 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
1585 const struct rte_flow_item *item,
1586 const struct rte_flow_attr *attr,
1587 uint64_t item_flags,
1588 struct rte_flow_error *error)
1590 const struct rte_flow_item_port_id *spec = item->spec;
1591 const struct rte_flow_item_port_id *mask = item->mask;
1592 const struct rte_flow_item_port_id switch_mask = {
1595 struct mlx5_priv *esw_priv;
1596 struct mlx5_priv *dev_priv;
1599 if (!attr->transfer)
1600 return rte_flow_error_set(error, EINVAL,
1601 RTE_FLOW_ERROR_TYPE_ITEM,
1603 "match on port id is valid only"
1604 " when transfer flag is enabled");
1605 if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
1606 return rte_flow_error_set(error, ENOTSUP,
1607 RTE_FLOW_ERROR_TYPE_ITEM, item,
1608 "multiple source ports are not"
1611 mask = &switch_mask;
1612 if (mask->id != 0xffffffff)
1613 return rte_flow_error_set(error, ENOTSUP,
1614 RTE_FLOW_ERROR_TYPE_ITEM_MASK,
1616 "no support for partial mask on"
1618 ret = mlx5_flow_item_acceptable
1619 (item, (const uint8_t *)mask,
1620 (const uint8_t *)&rte_flow_item_port_id_mask,
1621 sizeof(struct rte_flow_item_port_id),
1627 esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
1629 return rte_flow_error_set(error, rte_errno,
1630 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1631 "failed to obtain E-Switch info for"
1633 dev_priv = mlx5_dev_to_eswitch_info(dev);
1635 return rte_flow_error_set(error, rte_errno,
1636 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1638 "failed to obtain E-Switch info");
1639 if (esw_priv->domain_id != dev_priv->domain_id)
1640 return rte_flow_error_set(error, EINVAL,
1641 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
1642 "cannot match on a port from a"
1643 " different E-Switch");
1648 * Validate VLAN item.
1651 * Item specification.
1652 * @param[in] item_flags
1653 * Bit-fields that holds the items detected until now.
1655 * Ethernet device flow is being created on.
1657 * Pointer to error structure.
1660 * 0 on success, a negative errno value otherwise and rte_errno is set.
1663 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
1664 uint64_t item_flags,
1665 struct rte_eth_dev *dev,
1666 struct rte_flow_error *error)
1668 const struct rte_flow_item_vlan *mask = item->mask;
1669 const struct rte_flow_item_vlan nic_mask = {
1670 .tci = RTE_BE16(UINT16_MAX),
1671 .inner_type = RTE_BE16(UINT16_MAX),
1673 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
1675 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
1676 MLX5_FLOW_LAYER_INNER_L4) :
1677 (MLX5_FLOW_LAYER_OUTER_L3 |
1678 MLX5_FLOW_LAYER_OUTER_L4);
1679 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
1680 MLX5_FLOW_LAYER_OUTER_VLAN;
1682 if (item_flags & vlanm)
1683 return rte_flow_error_set(error, EINVAL,
1684 RTE_FLOW_ERROR_TYPE_ITEM, item,
1685 "multiple VLAN layers not supported");
1686 else if ((item_flags & l34m) != 0)
1687 return rte_flow_error_set(error, EINVAL,
1688 RTE_FLOW_ERROR_TYPE_ITEM, item,
1689 "VLAN cannot follow L3/L4 layer");
1691 mask = &rte_flow_item_vlan_mask;
1692 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1693 (const uint8_t *)&nic_mask,
1694 sizeof(struct rte_flow_item_vlan),
1698 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
1699 struct mlx5_priv *priv = dev->data->dev_private;
1701 if (priv->vmwa_context) {
1703 * Non-NULL context means we have a virtual machine
1704 * and SR-IOV enabled, we have to create VLAN interface
1705 * to make hypervisor to setup E-Switch vport
1706 * context correctly. We avoid creating the multiple
1707 * VLAN interfaces, so we cannot support VLAN tag mask.
1709 return rte_flow_error_set(error, EINVAL,
1710 RTE_FLOW_ERROR_TYPE_ITEM,
1712 "VLAN tag mask is not"
1713 " supported in virtual"
1721 * GTP flags are contained in 1 byte of the format:
1722 * -------------------------------------------
1723 * | bit | 0 - 2 | 3 | 4 | 5 | 6 | 7 |
1724 * |-----------------------------------------|
1725 * | value | Version | PT | Res | E | S | PN |
1726 * -------------------------------------------
1728 * Matching is supported only for GTP flags E, S, PN.
1730 #define MLX5_GTP_FLAGS_MASK 0x07
1733 * Validate GTP item.
1736 * Pointer to the rte_eth_dev structure.
1738 * Item specification.
1739 * @param[in] item_flags
1740 * Bit-fields that holds the items detected until now.
1742 * Pointer to error structure.
1745 * 0 on success, a negative errno value otherwise and rte_errno is set.
1748 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
1749 const struct rte_flow_item *item,
1750 uint64_t item_flags,
1751 struct rte_flow_error *error)
1753 struct mlx5_priv *priv = dev->data->dev_private;
1754 const struct rte_flow_item_gtp *spec = item->spec;
1755 const struct rte_flow_item_gtp *mask = item->mask;
1756 const struct rte_flow_item_gtp nic_mask = {
1757 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
1759 .teid = RTE_BE32(0xffffffff),
1762 if (!priv->config.hca_attr.tunnel_stateless_gtp)
1763 return rte_flow_error_set(error, ENOTSUP,
1764 RTE_FLOW_ERROR_TYPE_ITEM, item,
1765 "GTP support is not enabled");
1766 if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
1767 return rte_flow_error_set(error, ENOTSUP,
1768 RTE_FLOW_ERROR_TYPE_ITEM, item,
1769 "multiple tunnel layers not"
1771 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
1772 return rte_flow_error_set(error, EINVAL,
1773 RTE_FLOW_ERROR_TYPE_ITEM, item,
1774 "no outer UDP layer found");
1776 mask = &rte_flow_item_gtp_mask;
1777 if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
1778 return rte_flow_error_set(error, ENOTSUP,
1779 RTE_FLOW_ERROR_TYPE_ITEM, item,
1780 "Match is supported for GTP"
1782 return mlx5_flow_item_acceptable
1783 (item, (const uint8_t *)mask,
1784 (const uint8_t *)&nic_mask,
1785 sizeof(struct rte_flow_item_gtp),
1790 * Validate the pop VLAN action.
1793 * Pointer to the rte_eth_dev structure.
1794 * @param[in] action_flags
1795 * Holds the actions detected until now.
1797 * Pointer to the pop vlan action.
1798 * @param[in] item_flags
1799 * The items found in this flow rule.
1801 * Pointer to flow attributes.
1803 * Pointer to error structure.
1806 * 0 on success, a negative errno value otherwise and rte_errno is set.
1809 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
1810 uint64_t action_flags,
1811 const struct rte_flow_action *action,
1812 uint64_t item_flags,
1813 const struct rte_flow_attr *attr,
1814 struct rte_flow_error *error)
1816 const struct mlx5_priv *priv = dev->data->dev_private;
1820 if (!priv->sh->pop_vlan_action)
1821 return rte_flow_error_set(error, ENOTSUP,
1822 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1824 "pop vlan action is not supported");
1826 return rte_flow_error_set(error, ENOTSUP,
1827 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1829 "pop vlan action not supported for "
1831 if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
1832 return rte_flow_error_set(error, ENOTSUP,
1833 RTE_FLOW_ERROR_TYPE_ACTION, action,
1834 "no support for multiple VLAN "
1836 /* Pop VLAN with preceding Decap requires inner header with VLAN. */
1837 if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
1838 !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
1839 return rte_flow_error_set(error, ENOTSUP,
1840 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1842 "cannot pop vlan after decap without "
1843 "match on inner vlan in the flow");
1844 /* Pop VLAN without preceding Decap requires outer header with VLAN. */
1845 if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
1846 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
1847 return rte_flow_error_set(error, ENOTSUP,
1848 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
1850 "cannot pop vlan without a "
1851 "match on (outer) vlan in the flow");
1852 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1853 return rte_flow_error_set(error, EINVAL,
1854 RTE_FLOW_ERROR_TYPE_ACTION, action,
1855 "wrong action order, port_id should "
1856 "be after pop VLAN action");
1857 if (!attr->transfer && priv->representor)
1858 return rte_flow_error_set(error, ENOTSUP,
1859 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1860 "pop vlan action for VF representor "
1861 "not supported on NIC table");
1866 * Get VLAN default info from vlan match info.
1869 * the list of item specifications.
1871 * pointer VLAN info to fill to.
1874 * 0 on success, a negative errno value otherwise and rte_errno is set.
1877 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
1878 struct rte_vlan_hdr *vlan)
1880 const struct rte_flow_item_vlan nic_mask = {
1881 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
1882 MLX5DV_FLOW_VLAN_VID_MASK),
1883 .inner_type = RTE_BE16(0xffff),
1888 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
1889 int type = items->type;
1891 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
1892 type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
1895 if (items->type != RTE_FLOW_ITEM_TYPE_END) {
1896 const struct rte_flow_item_vlan *vlan_m = items->mask;
1897 const struct rte_flow_item_vlan *vlan_v = items->spec;
1899 /* If VLAN item in pattern doesn't contain data, return here. */
1904 /* Only full match values are accepted */
1905 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
1906 MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
1907 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
1909 rte_be_to_cpu_16(vlan_v->tci &
1910 MLX5DV_FLOW_VLAN_PCP_MASK_BE);
1912 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
1913 MLX5DV_FLOW_VLAN_VID_MASK_BE) {
1914 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
1916 rte_be_to_cpu_16(vlan_v->tci &
1917 MLX5DV_FLOW_VLAN_VID_MASK_BE);
1919 if (vlan_m->inner_type == nic_mask.inner_type)
1920 vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
1921 vlan_m->inner_type);
1926 * Validate the push VLAN action.
1929 * Pointer to the rte_eth_dev structure.
1930 * @param[in] action_flags
1931 * Holds the actions detected until now.
1932 * @param[in] item_flags
1933 * The items found in this flow rule.
1935 * Pointer to the action structure.
1937 * Pointer to flow attributes
1939 * Pointer to error structure.
1942 * 0 on success, a negative errno value otherwise and rte_errno is set.
1945 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
1946 uint64_t action_flags,
1947 const struct rte_flow_item_vlan *vlan_m,
1948 const struct rte_flow_action *action,
1949 const struct rte_flow_attr *attr,
1950 struct rte_flow_error *error)
1952 const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
1953 const struct mlx5_priv *priv = dev->data->dev_private;
1955 if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
1956 push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
1957 return rte_flow_error_set(error, EINVAL,
1958 RTE_FLOW_ERROR_TYPE_ACTION, action,
1959 "invalid vlan ethertype");
1960 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
1961 return rte_flow_error_set(error, EINVAL,
1962 RTE_FLOW_ERROR_TYPE_ACTION, action,
1963 "wrong action order, port_id should "
1964 "be after push VLAN");
1965 if (!attr->transfer && priv->representor)
1966 return rte_flow_error_set(error, ENOTSUP,
1967 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
1968 "push vlan action for VF representor "
1969 "not supported on NIC table");
1971 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
1972 (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
1973 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
1974 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
1975 !(mlx5_flow_find_action
1976 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
1977 return rte_flow_error_set(error, EINVAL,
1978 RTE_FLOW_ERROR_TYPE_ACTION, action,
1979 "not full match mask on VLAN PCP and "
1980 "there is no of_set_vlan_pcp action, "
1981 "push VLAN action cannot figure out "
1984 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
1985 (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
1986 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
1987 !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
1988 !(mlx5_flow_find_action
1989 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
1990 return rte_flow_error_set(error, EINVAL,
1991 RTE_FLOW_ERROR_TYPE_ACTION, action,
1992 "not full match mask on VLAN VID and "
1993 "there is no of_set_vlan_vid action, "
1994 "push VLAN action cannot figure out "
2001 * Validate the set VLAN PCP.
2003 * @param[in] action_flags
2004 * Holds the actions detected until now.
2005 * @param[in] actions
2006 * Pointer to the list of actions remaining in the flow rule.
2008 * Pointer to error structure.
2011 * 0 on success, a negative errno value otherwise and rte_errno is set.
2014 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2015 const struct rte_flow_action actions[],
2016 struct rte_flow_error *error)
2018 const struct rte_flow_action *action = actions;
2019 const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2021 if (conf->vlan_pcp > 7)
2022 return rte_flow_error_set(error, EINVAL,
2023 RTE_FLOW_ERROR_TYPE_ACTION, action,
2024 "VLAN PCP value is too big");
2025 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2026 return rte_flow_error_set(error, ENOTSUP,
2027 RTE_FLOW_ERROR_TYPE_ACTION, action,
2028 "set VLAN PCP action must follow "
2029 "the push VLAN action");
2030 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2031 return rte_flow_error_set(error, ENOTSUP,
2032 RTE_FLOW_ERROR_TYPE_ACTION, action,
2033 "Multiple VLAN PCP modification are "
2035 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2036 return rte_flow_error_set(error, EINVAL,
2037 RTE_FLOW_ERROR_TYPE_ACTION, action,
2038 "wrong action order, port_id should "
2039 "be after set VLAN PCP");
2044 * Validate the set VLAN VID.
2046 * @param[in] item_flags
2047 * Holds the items detected in this rule.
2048 * @param[in] action_flags
2049 * Holds the actions detected until now.
2050 * @param[in] actions
2051 * Pointer to the list of actions remaining in the flow rule.
2053 * Pointer to error structure.
2056 * 0 on success, a negative errno value otherwise and rte_errno is set.
2059 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2060 uint64_t action_flags,
2061 const struct rte_flow_action actions[],
2062 struct rte_flow_error *error)
2064 const struct rte_flow_action *action = actions;
2065 const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2067 if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2068 return rte_flow_error_set(error, EINVAL,
2069 RTE_FLOW_ERROR_TYPE_ACTION, action,
2070 "VLAN VID value is too big");
2071 if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2072 !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2073 return rte_flow_error_set(error, ENOTSUP,
2074 RTE_FLOW_ERROR_TYPE_ACTION, action,
2075 "set VLAN VID action must follow push"
2076 " VLAN action or match on VLAN item");
2077 if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2078 return rte_flow_error_set(error, ENOTSUP,
2079 RTE_FLOW_ERROR_TYPE_ACTION, action,
2080 "Multiple VLAN VID modifications are "
2082 if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2083 return rte_flow_error_set(error, EINVAL,
2084 RTE_FLOW_ERROR_TYPE_ACTION, action,
2085 "wrong action order, port_id should "
2086 "be after set VLAN VID");
2091 * Validate the FLAG action.
2094 * Pointer to the rte_eth_dev structure.
2095 * @param[in] action_flags
2096 * Holds the actions detected until now.
2098 * Pointer to flow attributes
2100 * Pointer to error structure.
2103 * 0 on success, a negative errno value otherwise and rte_errno is set.
2106 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2107 uint64_t action_flags,
2108 const struct rte_flow_attr *attr,
2109 struct rte_flow_error *error)
2111 struct mlx5_priv *priv = dev->data->dev_private;
2112 struct mlx5_dev_config *config = &priv->config;
2115 /* Fall back if no extended metadata register support. */
2116 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2117 return mlx5_flow_validate_action_flag(action_flags, attr,
2119 /* Extensive metadata mode requires registers. */
2120 if (!mlx5_flow_ext_mreg_supported(dev))
2121 return rte_flow_error_set(error, ENOTSUP,
2122 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2123 "no metadata registers "
2124 "to support flag action");
2125 if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2126 return rte_flow_error_set(error, ENOTSUP,
2127 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2128 "extended metadata register"
2129 " isn't available");
2130 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2133 MLX5_ASSERT(ret > 0);
2134 if (action_flags & MLX5_FLOW_ACTION_MARK)
2135 return rte_flow_error_set(error, EINVAL,
2136 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2137 "can't mark and flag in same flow");
2138 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2139 return rte_flow_error_set(error, EINVAL,
2140 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2142 " actions in same flow");
2147 * Validate MARK action.
2150 * Pointer to the rte_eth_dev structure.
2152 * Pointer to action.
2153 * @param[in] action_flags
2154 * Holds the actions detected until now.
2156 * Pointer to flow attributes
2158 * Pointer to error structure.
2161 * 0 on success, a negative errno value otherwise and rte_errno is set.
2164 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2165 const struct rte_flow_action *action,
2166 uint64_t action_flags,
2167 const struct rte_flow_attr *attr,
2168 struct rte_flow_error *error)
2170 struct mlx5_priv *priv = dev->data->dev_private;
2171 struct mlx5_dev_config *config = &priv->config;
2172 const struct rte_flow_action_mark *mark = action->conf;
2175 /* Fall back if no extended metadata register support. */
2176 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2177 return mlx5_flow_validate_action_mark(action, action_flags,
2179 /* Extensive metadata mode requires registers. */
2180 if (!mlx5_flow_ext_mreg_supported(dev))
2181 return rte_flow_error_set(error, ENOTSUP,
2182 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2183 "no metadata registers "
2184 "to support mark action");
2185 if (!priv->sh->dv_mark_mask)
2186 return rte_flow_error_set(error, ENOTSUP,
2187 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2188 "extended metadata register"
2189 " isn't available");
2190 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2193 MLX5_ASSERT(ret > 0);
2195 return rte_flow_error_set(error, EINVAL,
2196 RTE_FLOW_ERROR_TYPE_ACTION, action,
2197 "configuration cannot be null");
2198 if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2199 return rte_flow_error_set(error, EINVAL,
2200 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2202 "mark id exceeds the limit");
2203 if (action_flags & MLX5_FLOW_ACTION_FLAG)
2204 return rte_flow_error_set(error, EINVAL,
2205 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2206 "can't flag and mark in same flow");
2207 if (action_flags & MLX5_FLOW_ACTION_MARK)
2208 return rte_flow_error_set(error, EINVAL,
2209 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2210 "can't have 2 mark actions in same"
2216 * Validate SET_META action.
2219 * Pointer to the rte_eth_dev structure.
2221 * Pointer to the action structure.
2222 * @param[in] action_flags
2223 * Holds the actions detected until now.
2225 * Pointer to flow attributes
2227 * Pointer to error structure.
2230 * 0 on success, a negative errno value otherwise and rte_errno is set.
2233 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2234 const struct rte_flow_action *action,
2235 uint64_t action_flags __rte_unused,
2236 const struct rte_flow_attr *attr,
2237 struct rte_flow_error *error)
2239 const struct rte_flow_action_set_meta *conf;
2240 uint32_t nic_mask = UINT32_MAX;
2243 if (!mlx5_flow_ext_mreg_supported(dev))
2244 return rte_flow_error_set(error, ENOTSUP,
2245 RTE_FLOW_ERROR_TYPE_ACTION, action,
2246 "extended metadata register"
2247 " isn't supported");
2248 reg = flow_dv_get_metadata_reg(dev, attr, error);
2251 if (reg != REG_A && reg != REG_B) {
2252 struct mlx5_priv *priv = dev->data->dev_private;
2254 nic_mask = priv->sh->dv_meta_mask;
2256 if (!(action->conf))
2257 return rte_flow_error_set(error, EINVAL,
2258 RTE_FLOW_ERROR_TYPE_ACTION, action,
2259 "configuration cannot be null");
2260 conf = (const struct rte_flow_action_set_meta *)action->conf;
2262 return rte_flow_error_set(error, EINVAL,
2263 RTE_FLOW_ERROR_TYPE_ACTION, action,
2264 "zero mask doesn't have any effect");
2265 if (conf->mask & ~nic_mask)
2266 return rte_flow_error_set(error, EINVAL,
2267 RTE_FLOW_ERROR_TYPE_ACTION, action,
2268 "meta data must be within reg C0");
2273 * Validate SET_TAG action.
2276 * Pointer to the rte_eth_dev structure.
2278 * Pointer to the action structure.
2279 * @param[in] action_flags
2280 * Holds the actions detected until now.
2282 * Pointer to flow attributes
2284 * Pointer to error structure.
2287 * 0 on success, a negative errno value otherwise and rte_errno is set.
2290 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
2291 const struct rte_flow_action *action,
2292 uint64_t action_flags,
2293 const struct rte_flow_attr *attr,
2294 struct rte_flow_error *error)
2296 const struct rte_flow_action_set_tag *conf;
2297 const uint64_t terminal_action_flags =
2298 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
2299 MLX5_FLOW_ACTION_RSS;
2302 if (!mlx5_flow_ext_mreg_supported(dev))
2303 return rte_flow_error_set(error, ENOTSUP,
2304 RTE_FLOW_ERROR_TYPE_ACTION, action,
2305 "extensive metadata register"
2306 " isn't supported");
2307 if (!(action->conf))
2308 return rte_flow_error_set(error, EINVAL,
2309 RTE_FLOW_ERROR_TYPE_ACTION, action,
2310 "configuration cannot be null");
2311 conf = (const struct rte_flow_action_set_tag *)action->conf;
2313 return rte_flow_error_set(error, EINVAL,
2314 RTE_FLOW_ERROR_TYPE_ACTION, action,
2315 "zero mask doesn't have any effect");
2316 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
2319 if (!attr->transfer && attr->ingress &&
2320 (action_flags & terminal_action_flags))
2321 return rte_flow_error_set(error, EINVAL,
2322 RTE_FLOW_ERROR_TYPE_ACTION, action,
2323 "set_tag has no effect"
2324 " with terminal actions");
2329 * Validate count action.
2332 * Pointer to rte_eth_dev structure.
2334 * Pointer to error structure.
2337 * 0 on success, a negative errno value otherwise and rte_errno is set.
2340 flow_dv_validate_action_count(struct rte_eth_dev *dev,
2341 struct rte_flow_error *error)
2343 struct mlx5_priv *priv = dev->data->dev_private;
2345 if (!priv->config.devx)
2347 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
2351 return rte_flow_error_set
2353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2355 "count action not supported");
2359 * Validate the L2 encap action.
2362 * Pointer to the rte_eth_dev structure.
2363 * @param[in] action_flags
2364 * Holds the actions detected until now.
2366 * Pointer to the action structure.
2368 * Pointer to flow attributes.
2370 * Pointer to error structure.
2373 * 0 on success, a negative errno value otherwise and rte_errno is set.
2376 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
2377 uint64_t action_flags,
2378 const struct rte_flow_action *action,
2379 const struct rte_flow_attr *attr,
2380 struct rte_flow_error *error)
2382 const struct mlx5_priv *priv = dev->data->dev_private;
2384 if (!(action->conf))
2385 return rte_flow_error_set(error, EINVAL,
2386 RTE_FLOW_ERROR_TYPE_ACTION, action,
2387 "configuration cannot be null");
2388 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
2389 return rte_flow_error_set(error, EINVAL,
2390 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2391 "can only have a single encap action "
2393 if (!attr->transfer && priv->representor)
2394 return rte_flow_error_set(error, ENOTSUP,
2395 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2396 "encap action for VF representor "
2397 "not supported on NIC table");
2402 * Validate a decap action.
2405 * Pointer to the rte_eth_dev structure.
2406 * @param[in] action_flags
2407 * Holds the actions detected until now.
2409 * Pointer to flow attributes
2411 * Pointer to error structure.
2414 * 0 on success, a negative errno value otherwise and rte_errno is set.
2417 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
2418 uint64_t action_flags,
2419 const struct rte_flow_attr *attr,
2420 struct rte_flow_error *error)
2422 const struct mlx5_priv *priv = dev->data->dev_private;
2424 if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
2425 !priv->config.decap_en)
2426 return rte_flow_error_set(error, ENOTSUP,
2427 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2428 "decap is not enabled");
2429 if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
2430 return rte_flow_error_set(error, ENOTSUP,
2431 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2433 MLX5_FLOW_ACTION_DECAP ? "can only "
2434 "have a single decap action" : "decap "
2435 "after encap is not supported");
2436 if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
2437 return rte_flow_error_set(error, EINVAL,
2438 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2439 "can't have decap action after"
2442 return rte_flow_error_set(error, ENOTSUP,
2443 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2445 "decap action not supported for "
2447 if (!attr->transfer && priv->representor)
2448 return rte_flow_error_set(error, ENOTSUP,
2449 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2450 "decap action for VF representor "
2451 "not supported on NIC table");
2455 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
2458 * Validate the raw encap and decap actions.
2461 * Pointer to the rte_eth_dev structure.
2463 * Pointer to the decap action.
2465 * Pointer to the encap action.
2467 * Pointer to flow attributes
2468 * @param[in/out] action_flags
2469 * Holds the actions detected until now.
2470 * @param[out] actions_n
2471 * pointer to the number of actions counter.
2473 * Pointer to error structure.
2476 * 0 on success, a negative errno value otherwise and rte_errno is set.
2479 flow_dv_validate_action_raw_encap_decap
2480 (struct rte_eth_dev *dev,
2481 const struct rte_flow_action_raw_decap *decap,
2482 const struct rte_flow_action_raw_encap *encap,
2483 const struct rte_flow_attr *attr, uint64_t *action_flags,
2484 int *actions_n, struct rte_flow_error *error)
2486 const struct mlx5_priv *priv = dev->data->dev_private;
2489 if (encap && (!encap->size || !encap->data))
2490 return rte_flow_error_set(error, EINVAL,
2491 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2492 "raw encap data cannot be empty");
2493 if (decap && encap) {
2494 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
2495 encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
2498 else if (encap->size <=
2499 MLX5_ENCAPSULATION_DECISION_SIZE &&
2501 MLX5_ENCAPSULATION_DECISION_SIZE)
2504 else if (encap->size >
2505 MLX5_ENCAPSULATION_DECISION_SIZE &&
2507 MLX5_ENCAPSULATION_DECISION_SIZE)
2508 /* 2 L2 actions: encap and decap. */
2511 return rte_flow_error_set(error,
2513 RTE_FLOW_ERROR_TYPE_ACTION,
2514 NULL, "unsupported too small "
2515 "raw decap and too small raw "
2516 "encap combination");
2519 ret = flow_dv_validate_action_decap(dev, *action_flags, attr,
2523 *action_flags |= MLX5_FLOW_ACTION_DECAP;
2527 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
2528 return rte_flow_error_set(error, ENOTSUP,
2529 RTE_FLOW_ERROR_TYPE_ACTION,
2531 "small raw encap size");
2532 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
2533 return rte_flow_error_set(error, EINVAL,
2534 RTE_FLOW_ERROR_TYPE_ACTION,
2536 "more than one encap action");
2537 if (!attr->transfer && priv->representor)
2538 return rte_flow_error_set
2540 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2541 "encap action for VF representor "
2542 "not supported on NIC table");
2543 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
2550 * Find existing encap/decap resource or create and register a new one.
2552 * @param[in, out] dev
2553 * Pointer to rte_eth_dev structure.
2554 * @param[in, out] resource
2555 * Pointer to encap/decap resource.
2556 * @parm[in, out] dev_flow
2557 * Pointer to the dev_flow.
2559 * pointer to error structure.
2562 * 0 on success otherwise -errno and errno is set.
2565 flow_dv_encap_decap_resource_register
2566 (struct rte_eth_dev *dev,
2567 struct mlx5_flow_dv_encap_decap_resource *resource,
2568 struct mlx5_flow *dev_flow,
2569 struct rte_flow_error *error)
2571 struct mlx5_priv *priv = dev->data->dev_private;
2572 struct mlx5_dev_ctx_shared *sh = priv->sh;
2573 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
2574 struct mlx5dv_dr_domain *domain;
2578 resource->flags = dev_flow->dv.group ? 0 : 1;
2579 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2580 domain = sh->fdb_domain;
2581 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2582 domain = sh->rx_domain;
2584 domain = sh->tx_domain;
2585 /* Lookup a matching resource from cache. */
2586 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], sh->encaps_decaps, idx,
2587 cache_resource, next) {
2588 if (resource->reformat_type == cache_resource->reformat_type &&
2589 resource->ft_type == cache_resource->ft_type &&
2590 resource->flags == cache_resource->flags &&
2591 resource->size == cache_resource->size &&
2592 !memcmp((const void *)resource->buf,
2593 (const void *)cache_resource->buf,
2595 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d++",
2596 (void *)cache_resource,
2597 rte_atomic32_read(&cache_resource->refcnt));
2598 rte_atomic32_inc(&cache_resource->refcnt);
2599 dev_flow->handle->dvh.rix_encap_decap = idx;
2600 dev_flow->dv.encap_decap = cache_resource;
2604 /* Register new encap/decap resource. */
2605 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
2606 &dev_flow->handle->dvh.rix_encap_decap);
2607 if (!cache_resource)
2608 return rte_flow_error_set(error, ENOMEM,
2609 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2610 "cannot allocate resource memory");
2611 *cache_resource = *resource;
2612 ret = mlx5_flow_os_create_flow_action_packet_reformat
2613 (sh->ctx, domain, cache_resource,
2614 &cache_resource->action);
2616 mlx5_free(cache_resource);
2617 return rte_flow_error_set(error, ENOMEM,
2618 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2619 NULL, "cannot create action");
2621 rte_atomic32_init(&cache_resource->refcnt);
2622 rte_atomic32_inc(&cache_resource->refcnt);
2623 ILIST_INSERT(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], &sh->encaps_decaps,
2624 dev_flow->handle->dvh.rix_encap_decap, cache_resource,
2626 dev_flow->dv.encap_decap = cache_resource;
2627 DRV_LOG(DEBUG, "new encap/decap resource %p: refcnt %d++",
2628 (void *)cache_resource,
2629 rte_atomic32_read(&cache_resource->refcnt));
2634 * Find existing table jump resource or create and register a new one.
2636 * @param[in, out] dev
2637 * Pointer to rte_eth_dev structure.
2638 * @param[in, out] tbl
2639 * Pointer to flow table resource.
2640 * @parm[in, out] dev_flow
2641 * Pointer to the dev_flow.
2643 * pointer to error structure.
2646 * 0 on success otherwise -errno and errno is set.
2649 flow_dv_jump_tbl_resource_register
2650 (struct rte_eth_dev *dev __rte_unused,
2651 struct mlx5_flow_tbl_resource *tbl,
2652 struct mlx5_flow *dev_flow,
2653 struct rte_flow_error *error)
2655 struct mlx5_flow_tbl_data_entry *tbl_data =
2656 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
2660 cnt = rte_atomic32_read(&tbl_data->jump.refcnt);
2662 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
2663 (tbl->obj, &tbl_data->jump.action);
2665 return rte_flow_error_set(error, ENOMEM,
2666 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2667 NULL, "cannot create jump action");
2668 DRV_LOG(DEBUG, "new jump table resource %p: refcnt %d++",
2669 (void *)&tbl_data->jump, cnt);
2671 /* old jump should not make the table ref++. */
2672 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
2673 MLX5_ASSERT(tbl_data->jump.action);
2674 DRV_LOG(DEBUG, "existed jump table resource %p: refcnt %d++",
2675 (void *)&tbl_data->jump, cnt);
2677 rte_atomic32_inc(&tbl_data->jump.refcnt);
2678 dev_flow->handle->rix_jump = tbl_data->idx;
2679 dev_flow->dv.jump = &tbl_data->jump;
2684 * Find existing default miss resource or create and register a new one.
2686 * @param[in, out] dev
2687 * Pointer to rte_eth_dev structure.
2689 * pointer to error structure.
2692 * 0 on success otherwise -errno and errno is set.
2695 flow_dv_default_miss_resource_register(struct rte_eth_dev *dev,
2696 struct rte_flow_error *error)
2698 struct mlx5_priv *priv = dev->data->dev_private;
2699 struct mlx5_dev_ctx_shared *sh = priv->sh;
2700 struct mlx5_flow_default_miss_resource *cache_resource =
2702 int cnt = rte_atomic32_read(&cache_resource->refcnt);
2705 MLX5_ASSERT(cache_resource->action);
2706 cache_resource->action =
2707 mlx5_glue->dr_create_flow_action_default_miss();
2708 if (!cache_resource->action)
2709 return rte_flow_error_set(error, ENOMEM,
2710 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2711 "cannot create default miss action");
2712 DRV_LOG(DEBUG, "new default miss resource %p: refcnt %d++",
2713 (void *)cache_resource->action, cnt);
2715 rte_atomic32_inc(&cache_resource->refcnt);
2720 * Find existing table port ID resource or create and register a new one.
2722 * @param[in, out] dev
2723 * Pointer to rte_eth_dev structure.
2724 * @param[in, out] resource
2725 * Pointer to port ID action resource.
2726 * @parm[in, out] dev_flow
2727 * Pointer to the dev_flow.
2729 * pointer to error structure.
2732 * 0 on success otherwise -errno and errno is set.
2735 flow_dv_port_id_action_resource_register
2736 (struct rte_eth_dev *dev,
2737 struct mlx5_flow_dv_port_id_action_resource *resource,
2738 struct mlx5_flow *dev_flow,
2739 struct rte_flow_error *error)
2741 struct mlx5_priv *priv = dev->data->dev_private;
2742 struct mlx5_dev_ctx_shared *sh = priv->sh;
2743 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
2747 /* Lookup a matching resource from cache. */
2748 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PORT_ID], sh->port_id_action_list,
2749 idx, cache_resource, next) {
2750 if (resource->port_id == cache_resource->port_id) {
2751 DRV_LOG(DEBUG, "port id action resource resource %p: "
2753 (void *)cache_resource,
2754 rte_atomic32_read(&cache_resource->refcnt));
2755 rte_atomic32_inc(&cache_resource->refcnt);
2756 dev_flow->handle->rix_port_id_action = idx;
2757 dev_flow->dv.port_id_action = cache_resource;
2761 /* Register new port id action resource. */
2762 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID],
2763 &dev_flow->handle->rix_port_id_action);
2764 if (!cache_resource)
2765 return rte_flow_error_set(error, ENOMEM,
2766 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2767 "cannot allocate resource memory");
2768 *cache_resource = *resource;
2769 ret = mlx5_flow_os_create_flow_action_dest_port
2770 (priv->sh->fdb_domain, resource->port_id,
2771 &cache_resource->action);
2773 mlx5_free(cache_resource);
2774 return rte_flow_error_set(error, ENOMEM,
2775 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2776 NULL, "cannot create action");
2778 rte_atomic32_init(&cache_resource->refcnt);
2779 rte_atomic32_inc(&cache_resource->refcnt);
2780 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PORT_ID], &sh->port_id_action_list,
2781 dev_flow->handle->rix_port_id_action, cache_resource,
2783 dev_flow->dv.port_id_action = cache_resource;
2784 DRV_LOG(DEBUG, "new port id action resource %p: refcnt %d++",
2785 (void *)cache_resource,
2786 rte_atomic32_read(&cache_resource->refcnt));
2791 * Find existing push vlan resource or create and register a new one.
2793 * @param [in, out] dev
2794 * Pointer to rte_eth_dev structure.
2795 * @param[in, out] resource
2796 * Pointer to port ID action resource.
2797 * @parm[in, out] dev_flow
2798 * Pointer to the dev_flow.
2800 * pointer to error structure.
2803 * 0 on success otherwise -errno and errno is set.
2806 flow_dv_push_vlan_action_resource_register
2807 (struct rte_eth_dev *dev,
2808 struct mlx5_flow_dv_push_vlan_action_resource *resource,
2809 struct mlx5_flow *dev_flow,
2810 struct rte_flow_error *error)
2812 struct mlx5_priv *priv = dev->data->dev_private;
2813 struct mlx5_dev_ctx_shared *sh = priv->sh;
2814 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
2815 struct mlx5dv_dr_domain *domain;
2819 /* Lookup a matching resource from cache. */
2820 ILIST_FOREACH(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2821 sh->push_vlan_action_list, idx, cache_resource, next) {
2822 if (resource->vlan_tag == cache_resource->vlan_tag &&
2823 resource->ft_type == cache_resource->ft_type) {
2824 DRV_LOG(DEBUG, "push-VLAN action resource resource %p: "
2826 (void *)cache_resource,
2827 rte_atomic32_read(&cache_resource->refcnt));
2828 rte_atomic32_inc(&cache_resource->refcnt);
2829 dev_flow->handle->dvh.rix_push_vlan = idx;
2830 dev_flow->dv.push_vlan_res = cache_resource;
2834 /* Register new push_vlan action resource. */
2835 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2836 &dev_flow->handle->dvh.rix_push_vlan);
2837 if (!cache_resource)
2838 return rte_flow_error_set(error, ENOMEM,
2839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2840 "cannot allocate resource memory");
2841 *cache_resource = *resource;
2842 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
2843 domain = sh->fdb_domain;
2844 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
2845 domain = sh->rx_domain;
2847 domain = sh->tx_domain;
2848 ret = mlx5_flow_os_create_flow_action_push_vlan
2849 (domain, resource->vlan_tag,
2850 &cache_resource->action);
2852 mlx5_free(cache_resource);
2853 return rte_flow_error_set(error, ENOMEM,
2854 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2855 NULL, "cannot create action");
2857 rte_atomic32_init(&cache_resource->refcnt);
2858 rte_atomic32_inc(&cache_resource->refcnt);
2859 ILIST_INSERT(sh->ipool[MLX5_IPOOL_PUSH_VLAN],
2860 &sh->push_vlan_action_list,
2861 dev_flow->handle->dvh.rix_push_vlan,
2862 cache_resource, next);
2863 dev_flow->dv.push_vlan_res = cache_resource;
2864 DRV_LOG(DEBUG, "new push vlan action resource %p: refcnt %d++",
2865 (void *)cache_resource,
2866 rte_atomic32_read(&cache_resource->refcnt));
2870 * Get the size of specific rte_flow_item_type hdr size
2872 * @param[in] item_type
2873 * Tested rte_flow_item_type.
2876 * sizeof struct item_type, 0 if void or irrelevant.
2879 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
2883 switch (item_type) {
2884 case RTE_FLOW_ITEM_TYPE_ETH:
2885 retval = sizeof(struct rte_ether_hdr);
2887 case RTE_FLOW_ITEM_TYPE_VLAN:
2888 retval = sizeof(struct rte_vlan_hdr);
2890 case RTE_FLOW_ITEM_TYPE_IPV4:
2891 retval = sizeof(struct rte_ipv4_hdr);
2893 case RTE_FLOW_ITEM_TYPE_IPV6:
2894 retval = sizeof(struct rte_ipv6_hdr);
2896 case RTE_FLOW_ITEM_TYPE_UDP:
2897 retval = sizeof(struct rte_udp_hdr);
2899 case RTE_FLOW_ITEM_TYPE_TCP:
2900 retval = sizeof(struct rte_tcp_hdr);
2902 case RTE_FLOW_ITEM_TYPE_VXLAN:
2903 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
2904 retval = sizeof(struct rte_vxlan_hdr);
2906 case RTE_FLOW_ITEM_TYPE_GRE:
2907 case RTE_FLOW_ITEM_TYPE_NVGRE:
2908 retval = sizeof(struct rte_gre_hdr);
2910 case RTE_FLOW_ITEM_TYPE_MPLS:
2911 retval = sizeof(struct rte_mpls_hdr);
2913 case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
2921 #define MLX5_ENCAP_IPV4_VERSION 0x40
2922 #define MLX5_ENCAP_IPV4_IHL_MIN 0x05
2923 #define MLX5_ENCAP_IPV4_TTL_DEF 0x40
2924 #define MLX5_ENCAP_IPV6_VTC_FLOW 0x60000000
2925 #define MLX5_ENCAP_IPV6_HOP_LIMIT 0xff
2926 #define MLX5_ENCAP_VXLAN_FLAGS 0x08000000
2927 #define MLX5_ENCAP_VXLAN_GPE_FLAGS 0x04
2930 * Convert the encap action data from list of rte_flow_item to raw buffer
2933 * Pointer to rte_flow_item objects list.
2935 * Pointer to the output buffer.
2937 * Pointer to the output buffer size.
2939 * Pointer to the error structure.
2942 * 0 on success, a negative errno value otherwise and rte_errno is set.
2945 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
2946 size_t *size, struct rte_flow_error *error)
2948 struct rte_ether_hdr *eth = NULL;
2949 struct rte_vlan_hdr *vlan = NULL;
2950 struct rte_ipv4_hdr *ipv4 = NULL;
2951 struct rte_ipv6_hdr *ipv6 = NULL;
2952 struct rte_udp_hdr *udp = NULL;
2953 struct rte_vxlan_hdr *vxlan = NULL;
2954 struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
2955 struct rte_gre_hdr *gre = NULL;
2957 size_t temp_size = 0;
2960 return rte_flow_error_set(error, EINVAL,
2961 RTE_FLOW_ERROR_TYPE_ACTION,
2962 NULL, "invalid empty data");
2963 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2964 len = flow_dv_get_item_hdr_len(items->type);
2965 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
2966 return rte_flow_error_set(error, EINVAL,
2967 RTE_FLOW_ERROR_TYPE_ACTION,
2968 (void *)items->type,
2969 "items total size is too big"
2970 " for encap action");
2971 rte_memcpy((void *)&buf[temp_size], items->spec, len);
2972 switch (items->type) {
2973 case RTE_FLOW_ITEM_TYPE_ETH:
2974 eth = (struct rte_ether_hdr *)&buf[temp_size];
2976 case RTE_FLOW_ITEM_TYPE_VLAN:
2977 vlan = (struct rte_vlan_hdr *)&buf[temp_size];
2979 return rte_flow_error_set(error, EINVAL,
2980 RTE_FLOW_ERROR_TYPE_ACTION,
2981 (void *)items->type,
2982 "eth header not found");
2983 if (!eth->ether_type)
2984 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
2986 case RTE_FLOW_ITEM_TYPE_IPV4:
2987 ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
2989 return rte_flow_error_set(error, EINVAL,
2990 RTE_FLOW_ERROR_TYPE_ACTION,
2991 (void *)items->type,
2992 "neither eth nor vlan"
2994 if (vlan && !vlan->eth_proto)
2995 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2996 else if (eth && !eth->ether_type)
2997 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
2998 if (!ipv4->version_ihl)
2999 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3000 MLX5_ENCAP_IPV4_IHL_MIN;
3001 if (!ipv4->time_to_live)
3002 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3004 case RTE_FLOW_ITEM_TYPE_IPV6:
3005 ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3007 return rte_flow_error_set(error, EINVAL,
3008 RTE_FLOW_ERROR_TYPE_ACTION,
3009 (void *)items->type,
3010 "neither eth nor vlan"
3012 if (vlan && !vlan->eth_proto)
3013 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3014 else if (eth && !eth->ether_type)
3015 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3016 if (!ipv6->vtc_flow)
3018 RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3019 if (!ipv6->hop_limits)
3020 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3022 case RTE_FLOW_ITEM_TYPE_UDP:
3023 udp = (struct rte_udp_hdr *)&buf[temp_size];
3025 return rte_flow_error_set(error, EINVAL,
3026 RTE_FLOW_ERROR_TYPE_ACTION,
3027 (void *)items->type,
3028 "ip header not found");
3029 if (ipv4 && !ipv4->next_proto_id)
3030 ipv4->next_proto_id = IPPROTO_UDP;
3031 else if (ipv6 && !ipv6->proto)
3032 ipv6->proto = IPPROTO_UDP;
3034 case RTE_FLOW_ITEM_TYPE_VXLAN:
3035 vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3037 return rte_flow_error_set(error, EINVAL,
3038 RTE_FLOW_ERROR_TYPE_ACTION,
3039 (void *)items->type,
3040 "udp header not found");
3042 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3043 if (!vxlan->vx_flags)
3045 RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3047 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3048 vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3050 return rte_flow_error_set(error, EINVAL,
3051 RTE_FLOW_ERROR_TYPE_ACTION,
3052 (void *)items->type,
3053 "udp header not found");
3054 if (!vxlan_gpe->proto)
3055 return rte_flow_error_set(error, EINVAL,
3056 RTE_FLOW_ERROR_TYPE_ACTION,
3057 (void *)items->type,
3058 "next protocol not found");
3061 RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3062 if (!vxlan_gpe->vx_flags)
3063 vxlan_gpe->vx_flags =
3064 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3066 case RTE_FLOW_ITEM_TYPE_GRE:
3067 case RTE_FLOW_ITEM_TYPE_NVGRE:
3068 gre = (struct rte_gre_hdr *)&buf[temp_size];
3070 return rte_flow_error_set(error, EINVAL,
3071 RTE_FLOW_ERROR_TYPE_ACTION,
3072 (void *)items->type,
3073 "next protocol not found");
3075 return rte_flow_error_set(error, EINVAL,
3076 RTE_FLOW_ERROR_TYPE_ACTION,
3077 (void *)items->type,
3078 "ip header not found");
3079 if (ipv4 && !ipv4->next_proto_id)
3080 ipv4->next_proto_id = IPPROTO_GRE;
3081 else if (ipv6 && !ipv6->proto)
3082 ipv6->proto = IPPROTO_GRE;
3084 case RTE_FLOW_ITEM_TYPE_VOID:
3087 return rte_flow_error_set(error, EINVAL,
3088 RTE_FLOW_ERROR_TYPE_ACTION,
3089 (void *)items->type,
3090 "unsupported item type");
3100 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3102 struct rte_ether_hdr *eth = NULL;
3103 struct rte_vlan_hdr *vlan = NULL;
3104 struct rte_ipv6_hdr *ipv6 = NULL;
3105 struct rte_udp_hdr *udp = NULL;
3109 eth = (struct rte_ether_hdr *)data;
3110 next_hdr = (char *)(eth + 1);
3111 proto = RTE_BE16(eth->ether_type);
3114 while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3115 vlan = (struct rte_vlan_hdr *)next_hdr;
3116 proto = RTE_BE16(vlan->eth_proto);
3117 next_hdr += sizeof(struct rte_vlan_hdr);
3120 /* HW calculates IPv4 csum. no need to proceed */
3121 if (proto == RTE_ETHER_TYPE_IPV4)
3124 /* non IPv4/IPv6 header. not supported */
3125 if (proto != RTE_ETHER_TYPE_IPV6) {
3126 return rte_flow_error_set(error, ENOTSUP,
3127 RTE_FLOW_ERROR_TYPE_ACTION,
3128 NULL, "Cannot offload non IPv4/IPv6");
3131 ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3133 /* ignore non UDP */
3134 if (ipv6->proto != IPPROTO_UDP)
3137 udp = (struct rte_udp_hdr *)(ipv6 + 1);
3138 udp->dgram_cksum = 0;
3144 * Convert L2 encap action to DV specification.
3147 * Pointer to rte_eth_dev structure.
3149 * Pointer to action structure.
3150 * @param[in, out] dev_flow
3151 * Pointer to the mlx5_flow.
3152 * @param[in] transfer
3153 * Mark if the flow is E-Switch flow.
3155 * Pointer to the error structure.
3158 * 0 on success, a negative errno value otherwise and rte_errno is set.
3161 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
3162 const struct rte_flow_action *action,
3163 struct mlx5_flow *dev_flow,
3165 struct rte_flow_error *error)
3167 const struct rte_flow_item *encap_data;
3168 const struct rte_flow_action_raw_encap *raw_encap_data;
3169 struct mlx5_flow_dv_encap_decap_resource res = {
3171 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
3172 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3173 MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
3176 if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
3178 (const struct rte_flow_action_raw_encap *)action->conf;
3179 res.size = raw_encap_data->size;
3180 memcpy(res.buf, raw_encap_data->data, res.size);
3182 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
3184 ((const struct rte_flow_action_vxlan_encap *)
3185 action->conf)->definition;
3188 ((const struct rte_flow_action_nvgre_encap *)
3189 action->conf)->definition;
3190 if (flow_dv_convert_encap_data(encap_data, res.buf,
3194 if (flow_dv_zero_encap_udp_csum(res.buf, error))
3196 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3197 return rte_flow_error_set(error, EINVAL,
3198 RTE_FLOW_ERROR_TYPE_ACTION,
3199 NULL, "can't create L2 encap action");
3204 * Convert L2 decap action to DV specification.
3207 * Pointer to rte_eth_dev structure.
3208 * @param[in, out] dev_flow
3209 * Pointer to the mlx5_flow.
3210 * @param[in] transfer
3211 * Mark if the flow is E-Switch flow.
3213 * Pointer to the error structure.
3216 * 0 on success, a negative errno value otherwise and rte_errno is set.
3219 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
3220 struct mlx5_flow *dev_flow,
3222 struct rte_flow_error *error)
3224 struct mlx5_flow_dv_encap_decap_resource res = {
3227 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
3228 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
3229 MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
3232 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3233 return rte_flow_error_set(error, EINVAL,
3234 RTE_FLOW_ERROR_TYPE_ACTION,
3235 NULL, "can't create L2 decap action");
3240 * Convert raw decap/encap (L3 tunnel) action to DV specification.
3243 * Pointer to rte_eth_dev structure.
3245 * Pointer to action structure.
3246 * @param[in, out] dev_flow
3247 * Pointer to the mlx5_flow.
3249 * Pointer to the flow attributes.
3251 * Pointer to the error structure.
3254 * 0 on success, a negative errno value otherwise and rte_errno is set.
3257 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
3258 const struct rte_flow_action *action,
3259 struct mlx5_flow *dev_flow,
3260 const struct rte_flow_attr *attr,
3261 struct rte_flow_error *error)
3263 const struct rte_flow_action_raw_encap *encap_data;
3264 struct mlx5_flow_dv_encap_decap_resource res;
3266 memset(&res, 0, sizeof(res));
3267 encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
3268 res.size = encap_data->size;
3269 memcpy(res.buf, encap_data->data, res.size);
3270 res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
3271 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
3272 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
3274 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3276 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3277 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3278 if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
3279 return rte_flow_error_set(error, EINVAL,
3280 RTE_FLOW_ERROR_TYPE_ACTION,
3281 NULL, "can't create encap action");
3286 * Create action push VLAN.
3289 * Pointer to rte_eth_dev structure.
3291 * Pointer to the flow attributes.
3293 * Pointer to the vlan to push to the Ethernet header.
3294 * @param[in, out] dev_flow
3295 * Pointer to the mlx5_flow.
3297 * Pointer to the error structure.
3300 * 0 on success, a negative errno value otherwise and rte_errno is set.
3303 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
3304 const struct rte_flow_attr *attr,
3305 const struct rte_vlan_hdr *vlan,
3306 struct mlx5_flow *dev_flow,
3307 struct rte_flow_error *error)
3309 struct mlx5_flow_dv_push_vlan_action_resource res;
3311 memset(&res, 0, sizeof(res));
3313 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
3316 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
3318 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
3319 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
3320 return flow_dv_push_vlan_action_resource_register
3321 (dev, &res, dev_flow, error);
3325 * Validate the modify-header actions.
3327 * @param[in] action_flags
3328 * Holds the actions detected until now.
3330 * Pointer to the modify action.
3332 * Pointer to error structure.
3335 * 0 on success, a negative errno value otherwise and rte_errno is set.
3338 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
3339 const struct rte_flow_action *action,
3340 struct rte_flow_error *error)
3342 if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
3343 return rte_flow_error_set(error, EINVAL,
3344 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3345 NULL, "action configuration not set");
3346 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3347 return rte_flow_error_set(error, EINVAL,
3348 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3349 "can't have encap action before"
3355 * Validate the modify-header MAC address actions.
3357 * @param[in] action_flags
3358 * Holds the actions detected until now.
3360 * Pointer to the modify action.
3361 * @param[in] item_flags
3362 * Holds the items detected.
3364 * Pointer to error structure.
3367 * 0 on success, a negative errno value otherwise and rte_errno is set.
3370 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
3371 const struct rte_flow_action *action,
3372 const uint64_t item_flags,
3373 struct rte_flow_error *error)
3377 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3379 if (!(item_flags & MLX5_FLOW_LAYER_L2))
3380 return rte_flow_error_set(error, EINVAL,
3381 RTE_FLOW_ERROR_TYPE_ACTION,
3383 "no L2 item in pattern");
3389 * Validate the modify-header IPv4 address actions.
3391 * @param[in] action_flags
3392 * Holds the actions detected until now.
3394 * Pointer to the modify action.
3395 * @param[in] item_flags
3396 * Holds the items detected.
3398 * Pointer to error structure.
3401 * 0 on success, a negative errno value otherwise and rte_errno is set.
3404 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
3405 const struct rte_flow_action *action,
3406 const uint64_t item_flags,
3407 struct rte_flow_error *error)
3412 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3414 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3415 MLX5_FLOW_LAYER_INNER_L3_IPV4 :
3416 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
3417 if (!(item_flags & layer))
3418 return rte_flow_error_set(error, EINVAL,
3419 RTE_FLOW_ERROR_TYPE_ACTION,
3421 "no ipv4 item in pattern");
3427 * Validate the modify-header IPv6 address actions.
3429 * @param[in] action_flags
3430 * Holds the actions detected until now.
3432 * Pointer to the modify action.
3433 * @param[in] item_flags
3434 * Holds the items detected.
3436 * Pointer to error structure.
3439 * 0 on success, a negative errno value otherwise and rte_errno is set.
3442 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
3443 const struct rte_flow_action *action,
3444 const uint64_t item_flags,
3445 struct rte_flow_error *error)
3450 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3452 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3453 MLX5_FLOW_LAYER_INNER_L3_IPV6 :
3454 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
3455 if (!(item_flags & layer))
3456 return rte_flow_error_set(error, EINVAL,
3457 RTE_FLOW_ERROR_TYPE_ACTION,
3459 "no ipv6 item in pattern");
3465 * Validate the modify-header TP actions.
3467 * @param[in] action_flags
3468 * Holds the actions detected until now.
3470 * Pointer to the modify action.
3471 * @param[in] item_flags
3472 * Holds the items detected.
3474 * Pointer to error structure.
3477 * 0 on success, a negative errno value otherwise and rte_errno is set.
3480 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
3481 const struct rte_flow_action *action,
3482 const uint64_t item_flags,
3483 struct rte_flow_error *error)
3488 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3490 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3491 MLX5_FLOW_LAYER_INNER_L4 :
3492 MLX5_FLOW_LAYER_OUTER_L4;
3493 if (!(item_flags & layer))
3494 return rte_flow_error_set(error, EINVAL,
3495 RTE_FLOW_ERROR_TYPE_ACTION,
3496 NULL, "no transport layer "
3503 * Validate the modify-header actions of increment/decrement
3504 * TCP Sequence-number.
3506 * @param[in] action_flags
3507 * Holds the actions detected until now.
3509 * Pointer to the modify action.
3510 * @param[in] item_flags
3511 * Holds the items detected.
3513 * Pointer to error structure.
3516 * 0 on success, a negative errno value otherwise and rte_errno is set.
3519 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
3520 const struct rte_flow_action *action,
3521 const uint64_t item_flags,
3522 struct rte_flow_error *error)
3527 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3529 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3530 MLX5_FLOW_LAYER_INNER_L4_TCP :
3531 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3532 if (!(item_flags & layer))
3533 return rte_flow_error_set(error, EINVAL,
3534 RTE_FLOW_ERROR_TYPE_ACTION,
3535 NULL, "no TCP item in"
3537 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
3538 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
3539 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
3540 (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
3541 return rte_flow_error_set(error, EINVAL,
3542 RTE_FLOW_ERROR_TYPE_ACTION,
3544 "cannot decrease and increase"
3545 " TCP sequence number"
3546 " at the same time");
3552 * Validate the modify-header actions of increment/decrement
3553 * TCP Acknowledgment number.
3555 * @param[in] action_flags
3556 * Holds the actions detected until now.
3558 * Pointer to the modify action.
3559 * @param[in] item_flags
3560 * Holds the items detected.
3562 * Pointer to error structure.
3565 * 0 on success, a negative errno value otherwise and rte_errno is set.
3568 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
3569 const struct rte_flow_action *action,
3570 const uint64_t item_flags,
3571 struct rte_flow_error *error)
3576 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3578 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3579 MLX5_FLOW_LAYER_INNER_L4_TCP :
3580 MLX5_FLOW_LAYER_OUTER_L4_TCP;
3581 if (!(item_flags & layer))
3582 return rte_flow_error_set(error, EINVAL,
3583 RTE_FLOW_ERROR_TYPE_ACTION,
3584 NULL, "no TCP item in"
3586 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
3587 (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
3588 (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
3589 (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
3590 return rte_flow_error_set(error, EINVAL,
3591 RTE_FLOW_ERROR_TYPE_ACTION,
3593 "cannot decrease and increase"
3594 " TCP acknowledgment number"
3595 " at the same time");
3601 * Validate the modify-header TTL actions.
3603 * @param[in] action_flags
3604 * Holds the actions detected until now.
3606 * Pointer to the modify action.
3607 * @param[in] item_flags
3608 * Holds the items detected.
3610 * Pointer to error structure.
3613 * 0 on success, a negative errno value otherwise and rte_errno is set.
3616 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
3617 const struct rte_flow_action *action,
3618 const uint64_t item_flags,
3619 struct rte_flow_error *error)
3624 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3626 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
3627 MLX5_FLOW_LAYER_INNER_L3 :
3628 MLX5_FLOW_LAYER_OUTER_L3;
3629 if (!(item_flags & layer))
3630 return rte_flow_error_set(error, EINVAL,
3631 RTE_FLOW_ERROR_TYPE_ACTION,
3633 "no IP protocol in pattern");
3639 * Validate jump action.
3642 * Pointer to the jump action.
3643 * @param[in] action_flags
3644 * Holds the actions detected until now.
3645 * @param[in] attributes
3646 * Pointer to flow attributes
3647 * @param[in] external
3648 * Action belongs to flow rule created by request external to PMD.
3650 * Pointer to error structure.
3653 * 0 on success, a negative errno value otherwise and rte_errno is set.
3656 flow_dv_validate_action_jump(const struct rte_flow_action *action,
3657 uint64_t action_flags,
3658 const struct rte_flow_attr *attributes,
3659 bool external, struct rte_flow_error *error)
3661 uint32_t target_group, table;
3664 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3665 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3666 return rte_flow_error_set(error, EINVAL,
3667 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3668 "can't have 2 fate actions in"
3670 if (action_flags & MLX5_FLOW_ACTION_METER)
3671 return rte_flow_error_set(error, ENOTSUP,
3672 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3673 "jump with meter not support");
3675 return rte_flow_error_set(error, EINVAL,
3676 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3677 NULL, "action configuration not set");
3679 ((const struct rte_flow_action_jump *)action->conf)->group;
3680 ret = mlx5_flow_group_to_table(attributes, external, target_group,
3681 true, &table, error);
3684 if (attributes->group == target_group)
3685 return rte_flow_error_set(error, EINVAL,
3686 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3687 "target group must be other than"
3688 " the current flow group");
3693 * Validate the port_id action.
3696 * Pointer to rte_eth_dev structure.
3697 * @param[in] action_flags
3698 * Bit-fields that holds the actions detected until now.
3700 * Port_id RTE action structure.
3702 * Attributes of flow that includes this action.
3704 * Pointer to error structure.
3707 * 0 on success, a negative errno value otherwise and rte_errno is set.
3710 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
3711 uint64_t action_flags,
3712 const struct rte_flow_action *action,
3713 const struct rte_flow_attr *attr,
3714 struct rte_flow_error *error)
3716 const struct rte_flow_action_port_id *port_id;
3717 struct mlx5_priv *act_priv;
3718 struct mlx5_priv *dev_priv;
3721 if (!attr->transfer)
3722 return rte_flow_error_set(error, ENOTSUP,
3723 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3725 "port id action is valid in transfer"
3727 if (!action || !action->conf)
3728 return rte_flow_error_set(error, ENOTSUP,
3729 RTE_FLOW_ERROR_TYPE_ACTION_CONF,
3731 "port id action parameters must be"
3733 if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
3734 MLX5_FLOW_FATE_ESWITCH_ACTIONS))
3735 return rte_flow_error_set(error, EINVAL,
3736 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3737 "can have only one fate actions in"
3739 dev_priv = mlx5_dev_to_eswitch_info(dev);
3741 return rte_flow_error_set(error, rte_errno,
3742 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3744 "failed to obtain E-Switch info");
3745 port_id = action->conf;
3746 port = port_id->original ? dev->data->port_id : port_id->id;
3747 act_priv = mlx5_port_to_eswitch_info(port, false);
3749 return rte_flow_error_set
3751 RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
3752 "failed to obtain E-Switch port id for port");
3753 if (act_priv->domain_id != dev_priv->domain_id)
3754 return rte_flow_error_set
3756 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3757 "port does not belong to"
3758 " E-Switch being configured");
3763 * Get the maximum number of modify header actions.
3766 * Pointer to rte_eth_dev structure.
3768 * Flags bits to check if root level.
3771 * Max number of modify header actions device can support.
3773 static inline unsigned int
3774 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
3778 * There's no way to directly query the max capacity from FW.
3779 * The maximal value on root table should be assumed to be supported.
3781 if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
3782 return MLX5_MAX_MODIFY_NUM;
3784 return MLX5_ROOT_TBL_MODIFY_NUM;
3788 * Validate the meter action.
3791 * Pointer to rte_eth_dev structure.
3792 * @param[in] action_flags
3793 * Bit-fields that holds the actions detected until now.
3795 * Pointer to the meter action.
3797 * Attributes of flow that includes this action.
3799 * Pointer to error structure.
3802 * 0 on success, a negative errno value otherwise and rte_ernno is set.
3805 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
3806 uint64_t action_flags,
3807 const struct rte_flow_action *action,
3808 const struct rte_flow_attr *attr,
3809 struct rte_flow_error *error)
3811 struct mlx5_priv *priv = dev->data->dev_private;
3812 const struct rte_flow_action_meter *am = action->conf;
3813 struct mlx5_flow_meter *fm;
3816 return rte_flow_error_set(error, EINVAL,
3817 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3818 "meter action conf is NULL");
3820 if (action_flags & MLX5_FLOW_ACTION_METER)
3821 return rte_flow_error_set(error, ENOTSUP,
3822 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3823 "meter chaining not support");
3824 if (action_flags & MLX5_FLOW_ACTION_JUMP)
3825 return rte_flow_error_set(error, ENOTSUP,
3826 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3827 "meter with jump not support");
3829 return rte_flow_error_set(error, ENOTSUP,
3830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3832 "meter action not supported");
3833 fm = mlx5_flow_meter_find(priv, am->mtr_id);
3835 return rte_flow_error_set(error, EINVAL,
3836 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3838 if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
3839 (!fm->ingress && !attr->ingress && attr->egress) ||
3840 (!fm->egress && !attr->egress && attr->ingress))))
3841 return rte_flow_error_set(error, EINVAL,
3842 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3843 "Flow attributes are either invalid "
3844 "or have a conflict with current "
3845 "meter attributes");
3850 * Validate the age action.
3852 * @param[in] action_flags
3853 * Holds the actions detected until now.
3855 * Pointer to the age action.
3857 * Pointer to the Ethernet device structure.
3859 * Pointer to error structure.
3862 * 0 on success, a negative errno value otherwise and rte_errno is set.
3865 flow_dv_validate_action_age(uint64_t action_flags,
3866 const struct rte_flow_action *action,
3867 struct rte_eth_dev *dev,
3868 struct rte_flow_error *error)
3870 struct mlx5_priv *priv = dev->data->dev_private;
3871 const struct rte_flow_action_age *age = action->conf;
3873 if (!priv->config.devx || priv->counter_fallback)
3874 return rte_flow_error_set(error, ENOTSUP,
3875 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3877 "age action not supported");
3878 if (!(action->conf))
3879 return rte_flow_error_set(error, EINVAL,
3880 RTE_FLOW_ERROR_TYPE_ACTION, action,
3881 "configuration cannot be null");
3882 if (age->timeout >= UINT16_MAX / 2 / 10)
3883 return rte_flow_error_set(error, ENOTSUP,
3884 RTE_FLOW_ERROR_TYPE_ACTION, action,
3885 "Max age time: 3275 seconds");
3886 if (action_flags & MLX5_FLOW_ACTION_AGE)
3887 return rte_flow_error_set(error, EINVAL,
3888 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3889 "Duplicate age ctions set");
3894 * Validate the modify-header IPv4 DSCP actions.
3896 * @param[in] action_flags
3897 * Holds the actions detected until now.
3899 * Pointer to the modify action.
3900 * @param[in] item_flags
3901 * Holds the items detected.
3903 * Pointer to error structure.
3906 * 0 on success, a negative errno value otherwise and rte_errno is set.
3909 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
3910 const struct rte_flow_action *action,
3911 const uint64_t item_flags,
3912 struct rte_flow_error *error)
3916 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3918 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
3919 return rte_flow_error_set(error, EINVAL,
3920 RTE_FLOW_ERROR_TYPE_ACTION,
3922 "no ipv4 item in pattern");
3928 * Validate the modify-header IPv6 DSCP actions.
3930 * @param[in] action_flags
3931 * Holds the actions detected until now.
3933 * Pointer to the modify action.
3934 * @param[in] item_flags
3935 * Holds the items detected.
3937 * Pointer to error structure.
3940 * 0 on success, a negative errno value otherwise and rte_errno is set.
3943 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
3944 const struct rte_flow_action *action,
3945 const uint64_t item_flags,
3946 struct rte_flow_error *error)
3950 ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
3952 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
3953 return rte_flow_error_set(error, EINVAL,
3954 RTE_FLOW_ERROR_TYPE_ACTION,
3956 "no ipv6 item in pattern");
3962 * Find existing modify-header resource or create and register a new one.
3964 * @param dev[in, out]
3965 * Pointer to rte_eth_dev structure.
3966 * @param[in, out] resource
3967 * Pointer to modify-header resource.
3968 * @parm[in, out] dev_flow
3969 * Pointer to the dev_flow.
3971 * pointer to error structure.
3974 * 0 on success otherwise -errno and errno is set.
3977 flow_dv_modify_hdr_resource_register
3978 (struct rte_eth_dev *dev,
3979 struct mlx5_flow_dv_modify_hdr_resource *resource,
3980 struct mlx5_flow *dev_flow,
3981 struct rte_flow_error *error)
3983 struct mlx5_priv *priv = dev->data->dev_private;
3984 struct mlx5_dev_ctx_shared *sh = priv->sh;
3985 struct mlx5_flow_dv_modify_hdr_resource *cache_resource;
3986 struct mlx5dv_dr_domain *ns;
3987 uint32_t actions_len;
3990 resource->flags = dev_flow->dv.group ? 0 :
3991 MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
3992 if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
3994 return rte_flow_error_set(error, EOVERFLOW,
3995 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3996 "too many modify header items");
3997 if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3998 ns = sh->fdb_domain;
3999 else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
4003 /* Lookup a matching resource from cache. */
4004 actions_len = resource->actions_num * sizeof(resource->actions[0]);
4005 LIST_FOREACH(cache_resource, &sh->modify_cmds, next) {
4006 if (resource->ft_type == cache_resource->ft_type &&
4007 resource->actions_num == cache_resource->actions_num &&
4008 resource->flags == cache_resource->flags &&
4009 !memcmp((const void *)resource->actions,
4010 (const void *)cache_resource->actions,
4012 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d++",
4013 (void *)cache_resource,
4014 rte_atomic32_read(&cache_resource->refcnt));
4015 rte_atomic32_inc(&cache_resource->refcnt);
4016 dev_flow->handle->dvh.modify_hdr = cache_resource;
4020 /* Register new modify-header resource. */
4021 cache_resource = mlx5_malloc(MLX5_MEM_ZERO,
4022 sizeof(*cache_resource) + actions_len, 0,
4024 if (!cache_resource)
4025 return rte_flow_error_set(error, ENOMEM,
4026 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4027 "cannot allocate resource memory");
4028 *cache_resource = *resource;
4029 rte_memcpy(cache_resource->actions, resource->actions, actions_len);
4030 ret = mlx5_flow_os_create_flow_action_modify_header
4031 (sh->ctx, ns, cache_resource,
4032 actions_len, &cache_resource->action);
4034 mlx5_free(cache_resource);
4035 return rte_flow_error_set(error, ENOMEM,
4036 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4037 NULL, "cannot create action");
4039 rte_atomic32_init(&cache_resource->refcnt);
4040 rte_atomic32_inc(&cache_resource->refcnt);
4041 LIST_INSERT_HEAD(&sh->modify_cmds, cache_resource, next);
4042 dev_flow->handle->dvh.modify_hdr = cache_resource;
4043 DRV_LOG(DEBUG, "new modify-header resource %p: refcnt %d++",
4044 (void *)cache_resource,
4045 rte_atomic32_read(&cache_resource->refcnt));
4050 * Get DV flow counter by index.
4053 * Pointer to the Ethernet device structure.
4055 * mlx5 flow counter index in the container.
4057 * mlx5 flow counter pool in the container,
4060 * Pointer to the counter, NULL otherwise.
4062 static struct mlx5_flow_counter *
4063 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
4065 struct mlx5_flow_counter_pool **ppool)
4067 struct mlx5_priv *priv = dev->data->dev_private;
4068 struct mlx5_pools_container *cont;
4069 struct mlx5_flow_counter_pool *pool;
4070 uint32_t batch = 0, age = 0;
4073 age = MLX_CNT_IS_AGE(idx);
4074 idx = age ? idx - MLX5_CNT_AGE_OFFSET : idx;
4075 if (idx >= MLX5_CNT_BATCH_OFFSET) {
4076 idx -= MLX5_CNT_BATCH_OFFSET;
4079 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4080 MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cont->n);
4081 pool = cont->pools[idx / MLX5_COUNTERS_PER_POOL];
4085 return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
4089 * Check the devx counter belongs to the pool.
4092 * Pointer to the counter pool.
4094 * The counter devx ID.
4097 * True if counter belongs to the pool, false otherwise.
4100 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
4102 int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
4103 MLX5_COUNTERS_PER_POOL;
4105 if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
4111 * Get a pool by devx counter ID.
4114 * Pointer to the counter container.
4116 * The counter devx ID.
4119 * The counter pool pointer if exists, NULL otherwise,
4121 static struct mlx5_flow_counter_pool *
4122 flow_dv_find_pool_by_id(struct mlx5_pools_container *cont, int id)
4126 /* Check last used pool. */
4127 if (cont->last_pool_idx != POOL_IDX_INVALID &&
4128 flow_dv_is_counter_in_pool(cont->pools[cont->last_pool_idx], id))
4129 return cont->pools[cont->last_pool_idx];
4130 /* ID out of range means no suitable pool in the container. */
4131 if (id > cont->max_id || id < cont->min_id)
4134 * Find the pool from the end of the container, since mostly counter
4135 * ID is sequence increasing, and the last pool should be the needed
4138 i = rte_atomic16_read(&cont->n_valid);
4140 struct mlx5_flow_counter_pool *pool = cont->pools[i];
4142 if (flow_dv_is_counter_in_pool(pool, id))
4149 * Allocate a new memory for the counter values wrapped by all the needed
4153 * Pointer to the Ethernet device structure.
4155 * The raw memory areas - each one for MLX5_COUNTERS_PER_POOL counters.
4158 * The new memory management pointer on success, otherwise NULL and rte_errno
4161 static struct mlx5_counter_stats_mem_mng *
4162 flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
4164 struct mlx5_priv *priv = dev->data->dev_private;
4165 struct mlx5_dev_ctx_shared *sh = priv->sh;
4166 struct mlx5_devx_mkey_attr mkey_attr;
4167 struct mlx5_counter_stats_mem_mng *mem_mng;
4168 volatile struct flow_counter_stats *raw_data;
4169 int size = (sizeof(struct flow_counter_stats) *
4170 MLX5_COUNTERS_PER_POOL +
4171 sizeof(struct mlx5_counter_stats_raw)) * raws_n +
4172 sizeof(struct mlx5_counter_stats_mem_mng);
4173 size_t pgsize = rte_mem_page_size();
4174 if (pgsize == (size_t)-1) {
4175 DRV_LOG(ERR, "Failed to get mem page size");
4179 uint8_t *mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize,
4187 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1;
4188 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n;
4189 mem_mng->umem = mlx5_glue->devx_umem_reg(sh->ctx, mem, size,
4190 IBV_ACCESS_LOCAL_WRITE);
4191 if (!mem_mng->umem) {
4196 mkey_attr.addr = (uintptr_t)mem;
4197 mkey_attr.size = size;
4198 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem);
4199 mkey_attr.pd = sh->pdn;
4200 mkey_attr.log_entity_size = 0;
4201 mkey_attr.pg_access = 0;
4202 mkey_attr.klm_array = NULL;
4203 mkey_attr.klm_num = 0;
4204 if (priv->config.hca_attr.relaxed_ordering_write &&
4205 priv->config.hca_attr.relaxed_ordering_read &&
4206 !haswell_broadwell_cpu)
4207 mkey_attr.relaxed_ordering = 1;
4208 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
4210 mlx5_glue->devx_umem_dereg(mem_mng->umem);
4215 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size);
4216 raw_data = (volatile struct flow_counter_stats *)mem;
4217 for (i = 0; i < raws_n; ++i) {
4218 mem_mng->raws[i].mem_mng = mem_mng;
4219 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL;
4221 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next);
4226 * Resize a counter container.
4229 * Pointer to the Ethernet device structure.
4231 * Whether the pool is for counter that was allocated by batch command.
4233 * Whether the pool is for Aging counter.
4236 * 0 on success, otherwise negative errno value and rte_errno is set.
4239 flow_dv_container_resize(struct rte_eth_dev *dev,
4240 uint32_t batch, uint32_t age)
4242 struct mlx5_priv *priv = dev->data->dev_private;
4243 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4245 struct mlx5_counter_stats_mem_mng *mem_mng = NULL;
4246 void *old_pools = cont->pools;
4247 uint32_t resize = cont->n + MLX5_CNT_CONTAINER_RESIZE;
4248 uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
4249 void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
4256 memcpy(pools, old_pools, cont->n *
4257 sizeof(struct mlx5_flow_counter_pool *));
4259 * Fallback mode query the counter directly, no background query
4260 * resources are needed.
4262 if (!priv->counter_fallback) {
4265 mem_mng = flow_dv_create_counter_stat_mem_mng(dev,
4266 MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES);
4271 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i)
4272 LIST_INSERT_HEAD(&priv->sh->cmng.free_stat_raws,
4274 MLX5_CNT_CONTAINER_RESIZE +
4277 rte_spinlock_lock(&cont->resize_sl);
4279 cont->mem_mng = mem_mng;
4280 cont->pools = pools;
4281 rte_spinlock_unlock(&cont->resize_sl);
4283 mlx5_free(old_pools);
4288 * Query a devx flow counter.
4291 * Pointer to the Ethernet device structure.
4293 * Index to the flow counter.
4295 * The statistics value of packets.
4297 * The statistics value of bytes.
4300 * 0 on success, otherwise a negative errno value and rte_errno is set.
4303 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
4306 struct mlx5_priv *priv = dev->data->dev_private;
4307 struct mlx5_flow_counter_pool *pool = NULL;
4308 struct mlx5_flow_counter *cnt;
4309 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4312 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4314 if (counter < MLX5_CNT_BATCH_OFFSET) {
4315 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4316 if (priv->counter_fallback)
4317 return mlx5_devx_cmd_flow_counter_query(cnt_ext->dcs, 0,
4318 0, pkts, bytes, 0, NULL, NULL, 0);
4321 rte_spinlock_lock(&pool->sl);
4323 * The single counters allocation may allocate smaller ID than the
4324 * current allocated in parallel to the host reading.
4325 * In this case the new counter values must be reported as 0.
4327 if (unlikely(cnt_ext && cnt_ext->dcs->id < pool->raw->min_dcs_id)) {
4331 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
4332 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
4333 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
4335 rte_spinlock_unlock(&pool->sl);
4340 * Create and initialize a new counter pool.
4343 * Pointer to the Ethernet device structure.
4345 * The devX counter handle.
4347 * Whether the pool is for counter that was allocated by batch command.
4349 * Whether the pool is for counter that was allocated for aging.
4350 * @param[in/out] cont_cur
4351 * Pointer to the container pointer, it will be update in pool resize.
4354 * The pool container pointer on success, NULL otherwise and rte_errno is set.
4356 static struct mlx5_flow_counter_pool *
4357 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
4358 uint32_t batch, uint32_t age)
4360 struct mlx5_priv *priv = dev->data->dev_private;
4361 struct mlx5_flow_counter_pool *pool;
4362 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4364 int16_t n_valid = rte_atomic16_read(&cont->n_valid);
4365 uint32_t size = sizeof(*pool);
4367 if (cont->n == n_valid && flow_dv_container_resize(dev, batch, age))
4369 size += MLX5_COUNTERS_PER_POOL * CNT_SIZE;
4370 size += (batch ? 0 : MLX5_COUNTERS_PER_POOL * CNTEXT_SIZE);
4371 size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * AGE_SIZE);
4372 pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
4377 pool->min_dcs = dcs;
4378 if (!priv->counter_fallback)
4379 pool->raw = cont->mem_mng->raws + n_valid %
4380 MLX5_CNT_CONTAINER_RESIZE;
4381 pool->raw_hw = NULL;
4383 pool->type |= (batch ? 0 : CNT_POOL_TYPE_EXT);
4384 pool->type |= (!age ? 0 : CNT_POOL_TYPE_AGE);
4385 pool->query_gen = 0;
4386 rte_spinlock_init(&pool->sl);
4387 TAILQ_INIT(&pool->counters[0]);
4388 TAILQ_INIT(&pool->counters[1]);
4389 TAILQ_INSERT_HEAD(&cont->pool_list, pool, next);
4390 pool->index = n_valid;
4391 cont->pools[n_valid] = pool;
4393 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
4395 if (base < cont->min_id)
4396 cont->min_id = base;
4397 if (base > cont->max_id)
4398 cont->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
4399 cont->last_pool_idx = pool->index;
4401 /* Pool initialization must be updated before host thread access. */
4403 rte_atomic16_add(&cont->n_valid, 1);
4408 * Update the minimum dcs-id for aged or no-aged counter pool.
4411 * Pointer to the Ethernet device structure.
4413 * Current counter pool.
4415 * Whether the pool is for counter that was allocated by batch command.
4417 * Whether the counter is for aging.
4420 flow_dv_counter_update_min_dcs(struct rte_eth_dev *dev,
4421 struct mlx5_flow_counter_pool *pool,
4422 uint32_t batch, uint32_t age)
4424 struct mlx5_priv *priv = dev->data->dev_private;
4425 struct mlx5_flow_counter_pool *other;
4426 struct mlx5_pools_container *cont;
4428 cont = MLX5_CNT_CONTAINER(priv->sh, batch, (age ^ 0x1));
4429 other = flow_dv_find_pool_by_id(cont, pool->min_dcs->id);
4432 if (pool->min_dcs->id < other->min_dcs->id) {
4433 rte_atomic64_set(&other->a64_dcs,
4434 rte_atomic64_read(&pool->a64_dcs));
4436 rte_atomic64_set(&pool->a64_dcs,
4437 rte_atomic64_read(&other->a64_dcs));
4441 * Prepare a new counter and/or a new counter pool.
4444 * Pointer to the Ethernet device structure.
4445 * @param[out] cnt_free
4446 * Where to put the pointer of a new counter.
4448 * Whether the pool is for counter that was allocated by batch command.
4450 * Whether the pool is for counter that was allocated for aging.
4453 * The counter pool pointer and @p cnt_free is set on success,
4454 * NULL otherwise and rte_errno is set.
4456 static struct mlx5_flow_counter_pool *
4457 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
4458 struct mlx5_flow_counter **cnt_free,
4459 uint32_t batch, uint32_t age)
4461 struct mlx5_priv *priv = dev->data->dev_private;
4462 struct mlx5_pools_container *cont;
4463 struct mlx5_flow_counter_pool *pool;
4464 struct mlx5_counters tmp_tq;
4465 struct mlx5_devx_obj *dcs = NULL;
4466 struct mlx5_flow_counter *cnt;
4469 cont = MLX5_CNT_CONTAINER(priv->sh, batch, age);
4471 /* bulk_bitmap must be 0 for single counter allocation. */
4472 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
4475 pool = flow_dv_find_pool_by_id(cont, dcs->id);
4477 pool = flow_dv_pool_create(dev, dcs, batch, age);
4479 mlx5_devx_cmd_destroy(dcs);
4482 } else if (dcs->id < pool->min_dcs->id) {
4483 rte_atomic64_set(&pool->a64_dcs,
4484 (int64_t)(uintptr_t)dcs);
4486 flow_dv_counter_update_min_dcs(dev,
4488 i = dcs->id % MLX5_COUNTERS_PER_POOL;
4489 cnt = MLX5_POOL_GET_CNT(pool, i);
4491 MLX5_GET_POOL_CNT_EXT(pool, i)->dcs = dcs;
4495 /* bulk_bitmap is in 128 counters units. */
4496 if (priv->config.hca_attr.flow_counter_bulk_alloc_bitmap & 0x4)
4497 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
4499 rte_errno = ENODATA;
4502 pool = flow_dv_pool_create(dev, dcs, batch, age);
4504 mlx5_devx_cmd_destroy(dcs);
4507 TAILQ_INIT(&tmp_tq);
4508 for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
4509 cnt = MLX5_POOL_GET_CNT(pool, i);
4511 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
4513 rte_spinlock_lock(&cont->csl);
4514 TAILQ_CONCAT(&cont->counters, &tmp_tq, next);
4515 rte_spinlock_unlock(&cont->csl);
4516 *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
4517 (*cnt_free)->pool = pool;
4522 * Search for existed shared counter.
4525 * Pointer to the Ethernet device structure.
4527 * The shared counter ID to search.
4529 * mlx5 flow counter pool in the container,
4532 * NULL if not existed, otherwise pointer to the shared extend counter.
4534 static struct mlx5_flow_counter_ext *
4535 flow_dv_counter_shared_search(struct rte_eth_dev *dev, uint32_t id,
4536 struct mlx5_flow_counter_pool **ppool)
4538 struct mlx5_priv *priv = dev->data->dev_private;
4539 union mlx5_l3t_data data;
4542 if (mlx5_l3t_get_entry(priv->sh->cnt_id_tbl, id, &data) || !data.dword)
4544 cnt_idx = data.dword;
4546 * Shared counters don't have age info. The counter extend is after
4547 * the counter datat structure.
4549 return (struct mlx5_flow_counter_ext *)
4550 ((flow_dv_counter_get_by_idx(dev, cnt_idx, ppool)) + 1);
4554 * Allocate a flow counter.
4557 * Pointer to the Ethernet device structure.
4559 * Indicate if this counter is shared with other flows.
4561 * Counter identifier.
4563 * Counter flow group.
4565 * Whether the counter was allocated for aging.
4568 * Index to flow counter on success, 0 otherwise and rte_errno is set.
4571 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t shared, uint32_t id,
4572 uint16_t group, uint32_t age)
4574 struct mlx5_priv *priv = dev->data->dev_private;
4575 struct mlx5_flow_counter_pool *pool = NULL;
4576 struct mlx5_flow_counter *cnt_free = NULL;
4577 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4579 * Currently group 0 flow counter cannot be assigned to a flow if it is
4580 * not the first one in the batch counter allocation, so it is better
4581 * to allocate counters one by one for these flows in a separate
4583 * A counter can be shared between different groups so need to take
4584 * shared counters from the single container.
4586 uint32_t batch = (group && !shared && !priv->counter_fallback) ? 1 : 0;
4587 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(priv->sh, batch,
4591 if (!priv->config.devx) {
4592 rte_errno = ENOTSUP;
4596 cnt_ext = flow_dv_counter_shared_search(dev, id, &pool);
4598 if (cnt_ext->ref_cnt + 1 == 0) {
4603 cnt_idx = pool->index * MLX5_COUNTERS_PER_POOL +
4604 (cnt_ext->dcs->id % MLX5_COUNTERS_PER_POOL)
4609 /* Get free counters from container. */
4610 rte_spinlock_lock(&cont->csl);
4611 cnt_free = TAILQ_FIRST(&cont->counters);
4613 TAILQ_REMOVE(&cont->counters, cnt_free, next);
4614 rte_spinlock_unlock(&cont->csl);
4615 if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free,
4618 pool = cnt_free->pool;
4620 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt_free);
4621 /* Create a DV counter action only in the first time usage. */
4622 if (!cnt_free->action) {
4624 struct mlx5_devx_obj *dcs;
4628 offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
4629 dcs = pool->min_dcs;
4634 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
4641 cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
4642 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
4643 cnt_idx += batch * MLX5_CNT_BATCH_OFFSET;
4644 cnt_idx += age * MLX5_CNT_AGE_OFFSET;
4645 /* Update the counter reset values. */
4646 if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
4650 cnt_ext->shared = shared;
4651 cnt_ext->ref_cnt = 1;
4654 union mlx5_l3t_data data;
4656 data.dword = cnt_idx;
4657 if (mlx5_l3t_set_entry(priv->sh->cnt_id_tbl, id, &data))
4661 if (!priv->counter_fallback && !priv->sh->cmng.query_thread_on)
4662 /* Start the asynchronous batch query by the host thread. */
4663 mlx5_set_query_alarm(priv->sh);
4667 cnt_free->pool = pool;
4668 rte_spinlock_lock(&cont->csl);
4669 TAILQ_INSERT_TAIL(&cont->counters, cnt_free, next);
4670 rte_spinlock_unlock(&cont->csl);
4676 * Get age param from counter index.
4679 * Pointer to the Ethernet device structure.
4680 * @param[in] counter
4681 * Index to the counter handler.
4684 * The aging parameter specified for the counter index.
4686 static struct mlx5_age_param*
4687 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
4690 struct mlx5_flow_counter *cnt;
4691 struct mlx5_flow_counter_pool *pool = NULL;
4693 flow_dv_counter_get_by_idx(dev, counter, &pool);
4694 counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
4695 cnt = MLX5_POOL_GET_CNT(pool, counter);
4696 return MLX5_CNT_TO_AGE(cnt);
4700 * Remove a flow counter from aged counter list.
4703 * Pointer to the Ethernet device structure.
4704 * @param[in] counter
4705 * Index to the counter handler.
4707 * Pointer to the counter handler.
4710 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
4711 uint32_t counter, struct mlx5_flow_counter *cnt)
4713 struct mlx5_age_info *age_info;
4714 struct mlx5_age_param *age_param;
4715 struct mlx5_priv *priv = dev->data->dev_private;
4717 age_info = GET_PORT_AGE_INFO(priv);
4718 age_param = flow_dv_counter_idx_get_age(dev, counter);
4719 if (rte_atomic16_cmpset((volatile uint16_t *)
4721 AGE_CANDIDATE, AGE_FREE)
4724 * We need the lock even it is age timeout,
4725 * since counter may still in process.
4727 rte_spinlock_lock(&age_info->aged_sl);
4728 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
4729 rte_spinlock_unlock(&age_info->aged_sl);
4731 rte_atomic16_set(&age_param->state, AGE_FREE);
4734 * Release a flow counter.
4737 * Pointer to the Ethernet device structure.
4738 * @param[in] counter
4739 * Index to the counter handler.
4742 flow_dv_counter_release(struct rte_eth_dev *dev, uint32_t counter)
4744 struct mlx5_priv *priv = dev->data->dev_private;
4745 struct mlx5_flow_counter_pool *pool = NULL;
4746 struct mlx5_flow_counter *cnt;
4747 struct mlx5_flow_counter_ext *cnt_ext = NULL;
4751 cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
4753 if (counter < MLX5_CNT_BATCH_OFFSET) {
4754 cnt_ext = MLX5_CNT_TO_CNT_EXT(pool, cnt);
4756 if (--cnt_ext->ref_cnt)
4758 if (cnt_ext->shared)
4759 mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl,
4763 if (IS_AGE_POOL(pool))
4764 flow_dv_counter_remove_from_age(dev, counter, cnt);
4767 * Put the counter back to list to be updated in none fallback mode.
4768 * Currently, we are using two list alternately, while one is in query,
4769 * add the freed counter to the other list based on the pool query_gen
4770 * value. After query finishes, add counter the list to the global
4771 * container counter list. The list changes while query starts. In
4772 * this case, lock will not be needed as query callback and release
4773 * function both operate with the different list.
4776 if (!priv->counter_fallback)
4777 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
4779 TAILQ_INSERT_TAIL(&((MLX5_CNT_CONTAINER
4780 (priv->sh, 0, 0))->counters),
4785 * Verify the @p attributes will be correctly understood by the NIC and store
4786 * them in the @p flow if everything is correct.
4789 * Pointer to dev struct.
4790 * @param[in] attributes
4791 * Pointer to flow attributes
4792 * @param[in] external
4793 * This flow rule is created by request external to PMD.
4795 * Pointer to error structure.
4798 * - 0 on success and non root table.
4799 * - 1 on success and root table.
4800 * - a negative errno value otherwise and rte_errno is set.
4803 flow_dv_validate_attributes(struct rte_eth_dev *dev,
4804 const struct rte_flow_attr *attributes,
4805 bool external __rte_unused,
4806 struct rte_flow_error *error)
4808 struct mlx5_priv *priv = dev->data->dev_private;
4809 uint32_t priority_max = priv->config.flow_prio - 1;
4812 #ifndef HAVE_MLX5DV_DR
4813 if (attributes->group)
4814 return rte_flow_error_set(error, ENOTSUP,
4815 RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
4817 "groups are not supported");
4821 ret = mlx5_flow_group_to_table(attributes, external,
4822 attributes->group, !!priv->fdb_def_rule,
4827 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
4829 if (attributes->priority != MLX5_FLOW_PRIO_RSVD &&
4830 attributes->priority >= priority_max)
4831 return rte_flow_error_set(error, ENOTSUP,
4832 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
4834 "priority out of range");
4835 if (attributes->transfer) {
4836 if (!priv->config.dv_esw_en)
4837 return rte_flow_error_set
4839 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
4840 "E-Switch dr is not supported");
4841 if (!(priv->representor || priv->master))
4842 return rte_flow_error_set
4843 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4844 NULL, "E-Switch configuration can only be"
4845 " done by a master or a representor device");
4846 if (attributes->egress)
4847 return rte_flow_error_set
4849 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
4850 "egress is not supported");
4852 if (!(attributes->egress ^ attributes->ingress))
4853 return rte_flow_error_set(error, ENOTSUP,
4854 RTE_FLOW_ERROR_TYPE_ATTR, NULL,
4855 "must specify exactly one of "
4856 "ingress or egress");
4861 * Internal validation function. For validating both actions and items.
4864 * Pointer to the rte_eth_dev structure.
4866 * Pointer to the flow attributes.
4868 * Pointer to the list of items.
4869 * @param[in] actions
4870 * Pointer to the list of actions.
4871 * @param[in] external
4872 * This flow rule is created by request external to PMD.
4873 * @param[in] hairpin
4874 * Number of hairpin TX actions, 0 means classic flow.
4876 * Pointer to the error structure.
4879 * 0 on success, a negative errno value otherwise and rte_errno is set.
4882 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
4883 const struct rte_flow_item items[],
4884 const struct rte_flow_action actions[],
4885 bool external, int hairpin, struct rte_flow_error *error)
4888 uint64_t action_flags = 0;
4889 uint64_t item_flags = 0;
4890 uint64_t last_item = 0;
4891 uint8_t next_protocol = 0xff;
4892 uint16_t ether_type = 0;
4894 uint8_t item_ipv6_proto = 0;
4895 const struct rte_flow_item *gre_item = NULL;
4896 const struct rte_flow_action_raw_decap *decap;
4897 const struct rte_flow_action_raw_encap *encap;
4898 const struct rte_flow_action_rss *rss;
4899 const struct rte_flow_item_tcp nic_tcp_mask = {
4902 .src_port = RTE_BE16(UINT16_MAX),
4903 .dst_port = RTE_BE16(UINT16_MAX),
4906 const struct rte_flow_item_ipv4 nic_ipv4_mask = {
4908 .src_addr = RTE_BE32(0xffffffff),
4909 .dst_addr = RTE_BE32(0xffffffff),
4910 .type_of_service = 0xff,
4911 .next_proto_id = 0xff,
4912 .time_to_live = 0xff,
4915 const struct rte_flow_item_ipv6 nic_ipv6_mask = {
4918 "\xff\xff\xff\xff\xff\xff\xff\xff"
4919 "\xff\xff\xff\xff\xff\xff\xff\xff",
4921 "\xff\xff\xff\xff\xff\xff\xff\xff"
4922 "\xff\xff\xff\xff\xff\xff\xff\xff",
4923 .vtc_flow = RTE_BE32(0xffffffff),
4928 const struct rte_flow_item_ecpri nic_ecpri_mask = {
4932 RTE_BE32(((const struct rte_ecpri_common_hdr) {
4936 .dummy[0] = 0xffffffff,
4939 struct mlx5_priv *priv = dev->data->dev_private;
4940 struct mlx5_dev_config *dev_conf = &priv->config;
4941 uint16_t queue_index = 0xFFFF;
4942 const struct rte_flow_item_vlan *vlan_m = NULL;
4943 int16_t rw_act_num = 0;
4948 ret = flow_dv_validate_attributes(dev, attr, external, error);
4951 is_root = (uint64_t)ret;
4952 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
4953 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
4954 int type = items->type;
4956 if (!mlx5_flow_os_item_supported(type))
4957 return rte_flow_error_set(error, ENOTSUP,
4958 RTE_FLOW_ERROR_TYPE_ITEM,
4959 NULL, "item not supported");
4961 case RTE_FLOW_ITEM_TYPE_VOID:
4963 case RTE_FLOW_ITEM_TYPE_PORT_ID:
4964 ret = flow_dv_validate_item_port_id
4965 (dev, items, attr, item_flags, error);
4968 last_item = MLX5_FLOW_ITEM_PORT_ID;
4970 case RTE_FLOW_ITEM_TYPE_ETH:
4971 ret = mlx5_flow_validate_item_eth(items, item_flags,
4975 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
4976 MLX5_FLOW_LAYER_OUTER_L2;
4977 if (items->mask != NULL && items->spec != NULL) {
4979 ((const struct rte_flow_item_eth *)
4982 ((const struct rte_flow_item_eth *)
4984 ether_type = rte_be_to_cpu_16(ether_type);
4989 case RTE_FLOW_ITEM_TYPE_VLAN:
4990 ret = flow_dv_validate_item_vlan(items, item_flags,
4994 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
4995 MLX5_FLOW_LAYER_OUTER_VLAN;
4996 if (items->mask != NULL && items->spec != NULL) {
4998 ((const struct rte_flow_item_vlan *)
4999 items->spec)->inner_type;
5001 ((const struct rte_flow_item_vlan *)
5002 items->mask)->inner_type;
5003 ether_type = rte_be_to_cpu_16(ether_type);
5007 /* Store outer VLAN mask for of_push_vlan action. */
5009 vlan_m = items->mask;
5011 case RTE_FLOW_ITEM_TYPE_IPV4:
5012 mlx5_flow_tunnel_ip_check(items, next_protocol,
5013 &item_flags, &tunnel);
5014 ret = mlx5_flow_validate_item_ipv4(items, item_flags,
5021 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
5022 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
5023 if (items->mask != NULL &&
5024 ((const struct rte_flow_item_ipv4 *)
5025 items->mask)->hdr.next_proto_id) {
5027 ((const struct rte_flow_item_ipv4 *)
5028 (items->spec))->hdr.next_proto_id;
5030 ((const struct rte_flow_item_ipv4 *)
5031 (items->mask))->hdr.next_proto_id;
5033 /* Reset for inner layer. */
5034 next_protocol = 0xff;
5037 case RTE_FLOW_ITEM_TYPE_IPV6:
5038 mlx5_flow_tunnel_ip_check(items, next_protocol,
5039 &item_flags, &tunnel);
5040 ret = mlx5_flow_validate_item_ipv6(items, item_flags,
5047 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
5048 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
5049 if (items->mask != NULL &&
5050 ((const struct rte_flow_item_ipv6 *)
5051 items->mask)->hdr.proto) {
5053 ((const struct rte_flow_item_ipv6 *)
5054 items->spec)->hdr.proto;
5056 ((const struct rte_flow_item_ipv6 *)
5057 items->spec)->hdr.proto;
5059 ((const struct rte_flow_item_ipv6 *)
5060 items->mask)->hdr.proto;
5062 /* Reset for inner layer. */
5063 next_protocol = 0xff;
5066 case RTE_FLOW_ITEM_TYPE_TCP:
5067 ret = mlx5_flow_validate_item_tcp
5074 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
5075 MLX5_FLOW_LAYER_OUTER_L4_TCP;
5077 case RTE_FLOW_ITEM_TYPE_UDP:
5078 ret = mlx5_flow_validate_item_udp(items, item_flags,
5083 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
5084 MLX5_FLOW_LAYER_OUTER_L4_UDP;
5086 case RTE_FLOW_ITEM_TYPE_GRE:
5087 ret = mlx5_flow_validate_item_gre(items, item_flags,
5088 next_protocol, error);
5092 last_item = MLX5_FLOW_LAYER_GRE;
5094 case RTE_FLOW_ITEM_TYPE_NVGRE:
5095 ret = mlx5_flow_validate_item_nvgre(items, item_flags,
5100 last_item = MLX5_FLOW_LAYER_NVGRE;
5102 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
5103 ret = mlx5_flow_validate_item_gre_key
5104 (items, item_flags, gre_item, error);
5107 last_item = MLX5_FLOW_LAYER_GRE_KEY;
5109 case RTE_FLOW_ITEM_TYPE_VXLAN:
5110 ret = mlx5_flow_validate_item_vxlan(items, item_flags,
5114 last_item = MLX5_FLOW_LAYER_VXLAN;
5116 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
5117 ret = mlx5_flow_validate_item_vxlan_gpe(items,
5122 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
5124 case RTE_FLOW_ITEM_TYPE_GENEVE:
5125 ret = mlx5_flow_validate_item_geneve(items,
5130 last_item = MLX5_FLOW_LAYER_GENEVE;
5132 case RTE_FLOW_ITEM_TYPE_MPLS:
5133 ret = mlx5_flow_validate_item_mpls(dev, items,
5138 last_item = MLX5_FLOW_LAYER_MPLS;
5141 case RTE_FLOW_ITEM_TYPE_MARK:
5142 ret = flow_dv_validate_item_mark(dev, items, attr,
5146 last_item = MLX5_FLOW_ITEM_MARK;
5148 case RTE_FLOW_ITEM_TYPE_META:
5149 ret = flow_dv_validate_item_meta(dev, items, attr,
5153 last_item = MLX5_FLOW_ITEM_METADATA;
5155 case RTE_FLOW_ITEM_TYPE_ICMP:
5156 ret = mlx5_flow_validate_item_icmp(items, item_flags,
5161 last_item = MLX5_FLOW_LAYER_ICMP;
5163 case RTE_FLOW_ITEM_TYPE_ICMP6:
5164 ret = mlx5_flow_validate_item_icmp6(items, item_flags,
5169 item_ipv6_proto = IPPROTO_ICMPV6;
5170 last_item = MLX5_FLOW_LAYER_ICMP6;
5172 case RTE_FLOW_ITEM_TYPE_TAG:
5173 ret = flow_dv_validate_item_tag(dev, items,
5177 last_item = MLX5_FLOW_ITEM_TAG;
5179 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
5180 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
5182 case RTE_FLOW_ITEM_TYPE_GTP:
5183 ret = flow_dv_validate_item_gtp(dev, items, item_flags,
5187 last_item = MLX5_FLOW_LAYER_GTP;
5189 case RTE_FLOW_ITEM_TYPE_ECPRI:
5190 /* Capacity will be checked in the translate stage. */
5191 ret = mlx5_flow_validate_item_ecpri(items, item_flags,
5198 last_item = MLX5_FLOW_LAYER_ECPRI;
5201 return rte_flow_error_set(error, ENOTSUP,
5202 RTE_FLOW_ERROR_TYPE_ITEM,
5203 NULL, "item not supported");
5205 item_flags |= last_item;
5207 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
5208 int type = actions->type;
5210 if (!mlx5_flow_os_action_supported(type))
5211 return rte_flow_error_set(error, ENOTSUP,
5212 RTE_FLOW_ERROR_TYPE_ACTION,
5214 "action not supported");
5215 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5216 return rte_flow_error_set(error, ENOTSUP,
5217 RTE_FLOW_ERROR_TYPE_ACTION,
5218 actions, "too many actions");
5220 case RTE_FLOW_ACTION_TYPE_VOID:
5222 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5223 ret = flow_dv_validate_action_port_id(dev,
5230 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5233 case RTE_FLOW_ACTION_TYPE_FLAG:
5234 ret = flow_dv_validate_action_flag(dev, action_flags,
5238 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5239 /* Count all modify-header actions as one. */
5240 if (!(action_flags &
5241 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5243 action_flags |= MLX5_FLOW_ACTION_FLAG |
5244 MLX5_FLOW_ACTION_MARK_EXT;
5246 action_flags |= MLX5_FLOW_ACTION_FLAG;
5249 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5251 case RTE_FLOW_ACTION_TYPE_MARK:
5252 ret = flow_dv_validate_action_mark(dev, actions,
5257 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
5258 /* Count all modify-header actions as one. */
5259 if (!(action_flags &
5260 MLX5_FLOW_MODIFY_HDR_ACTIONS))
5262 action_flags |= MLX5_FLOW_ACTION_MARK |
5263 MLX5_FLOW_ACTION_MARK_EXT;
5265 action_flags |= MLX5_FLOW_ACTION_MARK;
5268 rw_act_num += MLX5_ACT_NUM_SET_MARK;
5270 case RTE_FLOW_ACTION_TYPE_SET_META:
5271 ret = flow_dv_validate_action_set_meta(dev, actions,
5276 /* Count all modify-header actions as one action. */
5277 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5279 action_flags |= MLX5_FLOW_ACTION_SET_META;
5280 rw_act_num += MLX5_ACT_NUM_SET_META;
5282 case RTE_FLOW_ACTION_TYPE_SET_TAG:
5283 ret = flow_dv_validate_action_set_tag(dev, actions,
5288 /* Count all modify-header actions as one action. */
5289 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5291 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
5292 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5294 case RTE_FLOW_ACTION_TYPE_DROP:
5295 ret = mlx5_flow_validate_action_drop(action_flags,
5299 action_flags |= MLX5_FLOW_ACTION_DROP;
5302 case RTE_FLOW_ACTION_TYPE_QUEUE:
5303 ret = mlx5_flow_validate_action_queue(actions,
5308 queue_index = ((const struct rte_flow_action_queue *)
5309 (actions->conf))->index;
5310 action_flags |= MLX5_FLOW_ACTION_QUEUE;
5313 case RTE_FLOW_ACTION_TYPE_RSS:
5314 rss = actions->conf;
5315 ret = mlx5_flow_validate_action_rss(actions,
5321 if (rss != NULL && rss->queue_num)
5322 queue_index = rss->queue[0];
5323 action_flags |= MLX5_FLOW_ACTION_RSS;
5326 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
5328 mlx5_flow_validate_action_default_miss(action_flags,
5332 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
5335 case RTE_FLOW_ACTION_TYPE_COUNT:
5336 ret = flow_dv_validate_action_count(dev, error);
5339 action_flags |= MLX5_FLOW_ACTION_COUNT;
5342 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
5343 if (flow_dv_validate_action_pop_vlan(dev,
5349 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
5352 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
5353 ret = flow_dv_validate_action_push_vlan(dev,
5360 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
5363 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
5364 ret = flow_dv_validate_action_set_vlan_pcp
5365 (action_flags, actions, error);
5368 /* Count PCP with push_vlan command. */
5369 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
5371 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
5372 ret = flow_dv_validate_action_set_vlan_vid
5373 (item_flags, action_flags,
5377 /* Count VID with push_vlan command. */
5378 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
5379 rw_act_num += MLX5_ACT_NUM_MDF_VID;
5381 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
5382 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
5383 ret = flow_dv_validate_action_l2_encap(dev,
5389 action_flags |= MLX5_FLOW_ACTION_ENCAP;
5392 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
5393 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
5394 ret = flow_dv_validate_action_decap(dev, action_flags,
5398 action_flags |= MLX5_FLOW_ACTION_DECAP;
5401 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5402 ret = flow_dv_validate_action_raw_encap_decap
5403 (dev, NULL, actions->conf, attr, &action_flags,
5408 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
5409 decap = actions->conf;
5410 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
5412 if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
5416 encap = actions->conf;
5418 ret = flow_dv_validate_action_raw_encap_decap
5420 decap ? decap : &empty_decap, encap,
5421 attr, &action_flags, &actions_n,
5426 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
5427 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
5428 ret = flow_dv_validate_action_modify_mac(action_flags,
5434 /* Count all modify-header actions as one action. */
5435 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5437 action_flags |= actions->type ==
5438 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
5439 MLX5_FLOW_ACTION_SET_MAC_SRC :
5440 MLX5_FLOW_ACTION_SET_MAC_DST;
5442 * Even if the source and destination MAC addresses have
5443 * overlap in the header with 4B alignment, the convert
5444 * function will handle them separately and 4 SW actions
5445 * will be created. And 2 actions will be added each
5446 * time no matter how many bytes of address will be set.
5448 rw_act_num += MLX5_ACT_NUM_MDF_MAC;
5450 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
5451 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
5452 ret = flow_dv_validate_action_modify_ipv4(action_flags,
5458 /* Count all modify-header actions as one action. */
5459 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5461 action_flags |= actions->type ==
5462 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
5463 MLX5_FLOW_ACTION_SET_IPV4_SRC :
5464 MLX5_FLOW_ACTION_SET_IPV4_DST;
5465 rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
5467 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
5468 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
5469 ret = flow_dv_validate_action_modify_ipv6(action_flags,
5475 if (item_ipv6_proto == IPPROTO_ICMPV6)
5476 return rte_flow_error_set(error, ENOTSUP,
5477 RTE_FLOW_ERROR_TYPE_ACTION,
5479 "Can't change header "
5480 "with ICMPv6 proto");
5481 /* Count all modify-header actions as one action. */
5482 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5484 action_flags |= actions->type ==
5485 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
5486 MLX5_FLOW_ACTION_SET_IPV6_SRC :
5487 MLX5_FLOW_ACTION_SET_IPV6_DST;
5488 rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
5490 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
5491 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
5492 ret = flow_dv_validate_action_modify_tp(action_flags,
5498 /* Count all modify-header actions as one action. */
5499 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5501 action_flags |= actions->type ==
5502 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
5503 MLX5_FLOW_ACTION_SET_TP_SRC :
5504 MLX5_FLOW_ACTION_SET_TP_DST;
5505 rw_act_num += MLX5_ACT_NUM_MDF_PORT;
5507 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
5508 case RTE_FLOW_ACTION_TYPE_SET_TTL:
5509 ret = flow_dv_validate_action_modify_ttl(action_flags,
5515 /* Count all modify-header actions as one action. */
5516 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5518 action_flags |= actions->type ==
5519 RTE_FLOW_ACTION_TYPE_SET_TTL ?
5520 MLX5_FLOW_ACTION_SET_TTL :
5521 MLX5_FLOW_ACTION_DEC_TTL;
5522 rw_act_num += MLX5_ACT_NUM_MDF_TTL;
5524 case RTE_FLOW_ACTION_TYPE_JUMP:
5525 ret = flow_dv_validate_action_jump(actions,
5532 action_flags |= MLX5_FLOW_ACTION_JUMP;
5534 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
5535 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
5536 ret = flow_dv_validate_action_modify_tcp_seq
5543 /* Count all modify-header actions as one action. */
5544 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5546 action_flags |= actions->type ==
5547 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
5548 MLX5_FLOW_ACTION_INC_TCP_SEQ :
5549 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
5550 rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
5552 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
5553 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
5554 ret = flow_dv_validate_action_modify_tcp_ack
5561 /* Count all modify-header actions as one action. */
5562 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5564 action_flags |= actions->type ==
5565 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
5566 MLX5_FLOW_ACTION_INC_TCP_ACK :
5567 MLX5_FLOW_ACTION_DEC_TCP_ACK;
5568 rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
5570 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
5572 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
5573 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
5574 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5576 case RTE_FLOW_ACTION_TYPE_METER:
5577 ret = mlx5_flow_validate_action_meter(dev,
5583 action_flags |= MLX5_FLOW_ACTION_METER;
5585 /* Meter action will add one more TAG action. */
5586 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5588 case RTE_FLOW_ACTION_TYPE_AGE:
5589 ret = flow_dv_validate_action_age(action_flags,
5594 action_flags |= MLX5_FLOW_ACTION_AGE;
5597 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
5598 ret = flow_dv_validate_action_modify_ipv4_dscp
5605 /* Count all modify-header actions as one action. */
5606 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5608 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
5609 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5611 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
5612 ret = flow_dv_validate_action_modify_ipv6_dscp
5619 /* Count all modify-header actions as one action. */
5620 if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
5622 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
5623 rw_act_num += MLX5_ACT_NUM_SET_DSCP;
5626 return rte_flow_error_set(error, ENOTSUP,
5627 RTE_FLOW_ERROR_TYPE_ACTION,
5629 "action not supported");
5633 * Validate the drop action mutual exclusion with other actions.
5634 * Drop action is mutually-exclusive with any other action, except for
5637 if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
5638 (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
5639 return rte_flow_error_set(error, EINVAL,
5640 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5641 "Drop action is mutually-exclusive "
5642 "with any other action, except for "
5644 /* Eswitch has few restrictions on using items and actions */
5645 if (attr->transfer) {
5646 if (!mlx5_flow_ext_mreg_supported(dev) &&
5647 action_flags & MLX5_FLOW_ACTION_FLAG)
5648 return rte_flow_error_set(error, ENOTSUP,
5649 RTE_FLOW_ERROR_TYPE_ACTION,
5651 "unsupported action FLAG");
5652 if (!mlx5_flow_ext_mreg_supported(dev) &&
5653 action_flags & MLX5_FLOW_ACTION_MARK)
5654 return rte_flow_error_set(error, ENOTSUP,
5655 RTE_FLOW_ERROR_TYPE_ACTION,
5657 "unsupported action MARK");
5658 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
5659 return rte_flow_error_set(error, ENOTSUP,
5660 RTE_FLOW_ERROR_TYPE_ACTION,
5662 "unsupported action QUEUE");
5663 if (action_flags & MLX5_FLOW_ACTION_RSS)
5664 return rte_flow_error_set(error, ENOTSUP,
5665 RTE_FLOW_ERROR_TYPE_ACTION,
5667 "unsupported action RSS");
5668 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
5669 return rte_flow_error_set(error, EINVAL,
5670 RTE_FLOW_ERROR_TYPE_ACTION,
5672 "no fate action is found");
5674 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
5675 return rte_flow_error_set(error, EINVAL,
5676 RTE_FLOW_ERROR_TYPE_ACTION,
5678 "no fate action is found");
5680 /* Continue validation for Xcap and VLAN actions.*/
5681 if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
5682 MLX5_FLOW_VLAN_ACTIONS)) &&
5683 (queue_index == 0xFFFF ||
5684 mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5685 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5686 MLX5_FLOW_XCAP_ACTIONS)
5687 return rte_flow_error_set(error, ENOTSUP,
5688 RTE_FLOW_ERROR_TYPE_ACTION,
5689 NULL, "encap and decap "
5690 "combination aren't supported");
5691 if (!attr->transfer && attr->ingress) {
5692 if (action_flags & MLX5_FLOW_ACTION_ENCAP)
5693 return rte_flow_error_set
5695 RTE_FLOW_ERROR_TYPE_ACTION,
5696 NULL, "encap is not supported"
5697 " for ingress traffic");
5698 else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
5699 return rte_flow_error_set
5701 RTE_FLOW_ERROR_TYPE_ACTION,
5702 NULL, "push VLAN action not "
5703 "supported for ingress");
5704 else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
5705 MLX5_FLOW_VLAN_ACTIONS)
5706 return rte_flow_error_set
5708 RTE_FLOW_ERROR_TYPE_ACTION,
5709 NULL, "no support for "
5710 "multiple VLAN actions");
5713 /* Hairpin flow will add one more TAG action. */
5715 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5716 /* extra metadata enabled: one more TAG action will be add. */
5717 if (dev_conf->dv_flow_en &&
5718 dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
5719 mlx5_flow_ext_mreg_supported(dev))
5720 rw_act_num += MLX5_ACT_NUM_SET_TAG;
5721 if ((uint32_t)rw_act_num >
5722 flow_dv_modify_hdr_action_max(dev, is_root)) {
5723 return rte_flow_error_set(error, ENOTSUP,
5724 RTE_FLOW_ERROR_TYPE_ACTION,
5725 NULL, "too many header modify"
5726 " actions to support");
5732 * Internal preparation function. Allocates the DV flow size,
5733 * this size is constant.
5736 * Pointer to the rte_eth_dev structure.
5738 * Pointer to the flow attributes.
5740 * Pointer to the list of items.
5741 * @param[in] actions
5742 * Pointer to the list of actions.
5744 * Pointer to the error structure.
5747 * Pointer to mlx5_flow object on success,
5748 * otherwise NULL and rte_errno is set.
5750 static struct mlx5_flow *
5751 flow_dv_prepare(struct rte_eth_dev *dev,
5752 const struct rte_flow_attr *attr __rte_unused,
5753 const struct rte_flow_item items[] __rte_unused,
5754 const struct rte_flow_action actions[] __rte_unused,
5755 struct rte_flow_error *error)
5757 uint32_t handle_idx = 0;
5758 struct mlx5_flow *dev_flow;
5759 struct mlx5_flow_handle *dev_handle;
5760 struct mlx5_priv *priv = dev->data->dev_private;
5762 /* In case of corrupting the memory. */
5763 if (priv->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
5764 rte_flow_error_set(error, ENOSPC,
5765 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5766 "not free temporary device flow");
5769 dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
5772 rte_flow_error_set(error, ENOMEM,
5773 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5774 "not enough memory to create flow handle");
5777 /* No multi-thread supporting. */
5778 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[priv->flow_idx++];
5779 dev_flow->handle = dev_handle;
5780 dev_flow->handle_idx = handle_idx;
5782 * In some old rdma-core releases, before continuing, a check of the
5783 * length of matching parameter will be done at first. It needs to use
5784 * the length without misc4 param. If the flow has misc4 support, then
5785 * the length needs to be adjusted accordingly. Each param member is
5786 * aligned with a 64B boundary naturally.
5788 dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
5789 MLX5_ST_SZ_BYTES(fte_match_set_misc4);
5791 * The matching value needs to be cleared to 0 before using. In the
5792 * past, it will be automatically cleared when using rte_*alloc
5793 * API. The time consumption will be almost the same as before.
5795 memset(dev_flow->dv.value.buf, 0, MLX5_ST_SZ_BYTES(fte_match_param));
5796 dev_flow->ingress = attr->ingress;
5797 dev_flow->dv.transfer = attr->transfer;
5801 #ifdef RTE_LIBRTE_MLX5_DEBUG
5803 * Sanity check for match mask and value. Similar to check_valid_spec() in
5804 * kernel driver. If unmasked bit is present in value, it returns failure.
5807 * pointer to match mask buffer.
5808 * @param match_value
5809 * pointer to match value buffer.
5812 * 0 if valid, -EINVAL otherwise.
5815 flow_dv_check_valid_spec(void *match_mask, void *match_value)
5817 uint8_t *m = match_mask;
5818 uint8_t *v = match_value;
5821 for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
5824 "match_value differs from match_criteria"
5825 " %p[%u] != %p[%u]",
5826 match_value, i, match_mask, i);
5835 * Add match of ip_version.
5839 * @param[in] headers_v
5840 * Values header pointer.
5841 * @param[in] headers_m
5842 * Masks header pointer.
5843 * @param[in] ip_version
5844 * The IP version to set.
5847 flow_dv_set_match_ip_version(uint32_t group,
5853 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
5855 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
5857 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
5858 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
5859 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
5863 * Add Ethernet item to matcher and to the value.
5865 * @param[in, out] matcher
5867 * @param[in, out] key
5868 * Flow matcher value.
5870 * Flow pattern to translate.
5872 * Item is inner pattern.
5875 flow_dv_translate_item_eth(void *matcher, void *key,
5876 const struct rte_flow_item *item, int inner,
5879 const struct rte_flow_item_eth *eth_m = item->mask;
5880 const struct rte_flow_item_eth *eth_v = item->spec;
5881 const struct rte_flow_item_eth nic_mask = {
5882 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5883 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
5884 .type = RTE_BE16(0xffff),
5896 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5898 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5900 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5902 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5904 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, dmac_47_16),
5905 ð_m->dst, sizeof(eth_m->dst));
5906 /* The value must be in the range of the mask. */
5907 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, dmac_47_16);
5908 for (i = 0; i < sizeof(eth_m->dst); ++i)
5909 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
5910 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m, smac_47_16),
5911 ð_m->src, sizeof(eth_m->src));
5912 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v, smac_47_16);
5913 /* The value must be in the range of the mask. */
5914 for (i = 0; i < sizeof(eth_m->dst); ++i)
5915 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
5917 /* When ethertype is present set mask for tagged VLAN. */
5918 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5919 /* Set value for tagged VLAN if ethertype is 802.1Q. */
5920 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
5921 eth_v->type == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
5922 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag,
5924 /* Return here to avoid setting match on ethertype. */
5929 * HW supports match on one Ethertype, the Ethertype following the last
5930 * VLAN tag of the packet (see PRM).
5931 * Set match on ethertype only if ETH header is not followed by VLAN.
5932 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
5933 * ethertype, and use ip_version field instead.
5934 * eCPRI over Ether layer will use type value 0xAEFE.
5936 if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
5937 eth_m->type == 0xFFFF) {
5938 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
5939 } else if (eth_v->type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
5940 eth_m->type == 0xFFFF) {
5941 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
5943 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
5944 rte_be_to_cpu_16(eth_m->type));
5945 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
5947 *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
5952 * Add VLAN item to matcher and to the value.
5954 * @param[in, out] dev_flow
5956 * @param[in, out] matcher
5958 * @param[in, out] key
5959 * Flow matcher value.
5961 * Flow pattern to translate.
5963 * Item is inner pattern.
5966 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
5967 void *matcher, void *key,
5968 const struct rte_flow_item *item,
5969 int inner, uint32_t group)
5971 const struct rte_flow_item_vlan *vlan_m = item->mask;
5972 const struct rte_flow_item_vlan *vlan_v = item->spec;
5979 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5981 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
5983 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
5985 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
5987 * This is workaround, masks are not supported,
5988 * and pre-validated.
5991 dev_flow->handle->vf_vlan.tag =
5992 rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
5995 * When VLAN item exists in flow, mark packet as tagged,
5996 * even if TCI is not specified.
5998 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
5999 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
6003 vlan_m = &rte_flow_item_vlan_mask;
6004 tci_m = rte_be_to_cpu_16(vlan_m->tci);
6005 tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
6006 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_vid, tci_m);
6007 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, tci_v);
6008 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_cfi, tci_m >> 12);
6009 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_cfi, tci_v >> 12);
6010 MLX5_SET(fte_match_set_lyr_2_4, headers_m, first_prio, tci_m >> 13);
6011 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, tci_v >> 13);
6013 * HW is optimized for IPv4/IPv6. In such cases, avoid setting
6014 * ethertype, and use ip_version field instead.
6016 if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV4) &&
6017 vlan_m->inner_type == 0xFFFF) {
6018 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6019 } else if (vlan_v->inner_type == RTE_BE16(RTE_ETHER_TYPE_IPV6) &&
6020 vlan_m->inner_type == 0xFFFF) {
6021 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6023 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype,
6024 rte_be_to_cpu_16(vlan_m->inner_type));
6025 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
6026 rte_be_to_cpu_16(vlan_m->inner_type &
6027 vlan_v->inner_type));
6032 * Add IPV4 item to matcher and to the value.
6034 * @param[in, out] matcher
6036 * @param[in, out] key
6037 * Flow matcher value.
6039 * Flow pattern to translate.
6040 * @param[in] item_flags
6041 * Bit-fields that holds the items detected until now.
6043 * Item is inner pattern.
6045 * The group to insert the rule.
6048 flow_dv_translate_item_ipv4(void *matcher, void *key,
6049 const struct rte_flow_item *item,
6050 const uint64_t item_flags,
6051 int inner, uint32_t group)
6053 const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
6054 const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
6055 const struct rte_flow_item_ipv4 nic_mask = {
6057 .src_addr = RTE_BE32(0xffffffff),
6058 .dst_addr = RTE_BE32(0xffffffff),
6059 .type_of_service = 0xff,
6060 .next_proto_id = 0xff,
6061 .time_to_live = 0xff,
6071 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6073 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6075 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6077 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6079 flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
6081 * On outer header (which must contains L2), or inner header with L2,
6082 * set cvlan_tag mask bit to mark this packet as untagged.
6083 * This should be done even if item->spec is empty.
6085 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6086 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6091 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6092 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6093 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6094 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
6095 *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
6096 *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
6097 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6098 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6099 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6100 src_ipv4_src_ipv6.ipv4_layout.ipv4);
6101 *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
6102 *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
6103 tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
6104 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
6105 ipv4_m->hdr.type_of_service);
6106 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
6107 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
6108 ipv4_m->hdr.type_of_service >> 2);
6109 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
6110 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6111 ipv4_m->hdr.next_proto_id);
6112 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6113 ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
6114 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6115 ipv4_m->hdr.time_to_live);
6116 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6117 ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
6121 * Add IPV6 item to matcher and to the value.
6123 * @param[in, out] matcher
6125 * @param[in, out] key
6126 * Flow matcher value.
6128 * Flow pattern to translate.
6129 * @param[in] item_flags
6130 * Bit-fields that holds the items detected until now.
6132 * Item is inner pattern.
6134 * The group to insert the rule.
6137 flow_dv_translate_item_ipv6(void *matcher, void *key,
6138 const struct rte_flow_item *item,
6139 const uint64_t item_flags,
6140 int inner, uint32_t group)
6142 const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
6143 const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
6144 const struct rte_flow_item_ipv6 nic_mask = {
6147 "\xff\xff\xff\xff\xff\xff\xff\xff"
6148 "\xff\xff\xff\xff\xff\xff\xff\xff",
6150 "\xff\xff\xff\xff\xff\xff\xff\xff"
6151 "\xff\xff\xff\xff\xff\xff\xff\xff",
6152 .vtc_flow = RTE_BE32(0xffffffff),
6159 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6160 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6169 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6171 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6173 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6175 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6177 flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
6179 * On outer header (which must contains L2), or inner header with L2,
6180 * set cvlan_tag mask bit to mark this packet as untagged.
6181 * This should be done even if item->spec is empty.
6183 if (!inner || item_flags & MLX5_FLOW_LAYER_INNER_L2)
6184 MLX5_SET(fte_match_set_lyr_2_4, headers_m, cvlan_tag, 1);
6189 size = sizeof(ipv6_m->hdr.dst_addr);
6190 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6191 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6192 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6193 dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
6194 memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
6195 for (i = 0; i < size; ++i)
6196 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
6197 l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
6198 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6199 l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
6200 src_ipv4_src_ipv6.ipv6_layout.ipv6);
6201 memcpy(l24_m, ipv6_m->hdr.src_addr, size);
6202 for (i = 0; i < size; ++i)
6203 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
6205 vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
6206 vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
6207 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
6208 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
6209 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
6210 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
6213 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
6215 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
6218 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
6220 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
6224 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
6226 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6227 ipv6_v->hdr.proto & ipv6_m->hdr.proto);
6229 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
6230 ipv6_m->hdr.hop_limits);
6231 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
6232 ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
6236 * Add TCP item to matcher and to the value.
6238 * @param[in, out] matcher
6240 * @param[in, out] key
6241 * Flow matcher value.
6243 * Flow pattern to translate.
6245 * Item is inner pattern.
6248 flow_dv_translate_item_tcp(void *matcher, void *key,
6249 const struct rte_flow_item *item,
6252 const struct rte_flow_item_tcp *tcp_m = item->mask;
6253 const struct rte_flow_item_tcp *tcp_v = item->spec;
6258 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6260 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6262 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6264 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6266 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6267 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
6271 tcp_m = &rte_flow_item_tcp_mask;
6272 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
6273 rte_be_to_cpu_16(tcp_m->hdr.src_port));
6274 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
6275 rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
6276 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
6277 rte_be_to_cpu_16(tcp_m->hdr.dst_port));
6278 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
6279 rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
6280 MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
6281 tcp_m->hdr.tcp_flags);
6282 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
6283 (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
6287 * Add UDP item to matcher and to the value.
6289 * @param[in, out] matcher
6291 * @param[in, out] key
6292 * Flow matcher value.
6294 * Flow pattern to translate.
6296 * Item is inner pattern.
6299 flow_dv_translate_item_udp(void *matcher, void *key,
6300 const struct rte_flow_item *item,
6303 const struct rte_flow_item_udp *udp_m = item->mask;
6304 const struct rte_flow_item_udp *udp_v = item->spec;
6309 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6311 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6313 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6315 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6317 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6318 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
6322 udp_m = &rte_flow_item_udp_mask;
6323 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
6324 rte_be_to_cpu_16(udp_m->hdr.src_port));
6325 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
6326 rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
6327 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
6328 rte_be_to_cpu_16(udp_m->hdr.dst_port));
6329 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6330 rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
6334 * Add GRE optional Key item to matcher and to the value.
6336 * @param[in, out] matcher
6338 * @param[in, out] key
6339 * Flow matcher value.
6341 * Flow pattern to translate.
6343 * Item is inner pattern.
6346 flow_dv_translate_item_gre_key(void *matcher, void *key,
6347 const struct rte_flow_item *item)
6349 const rte_be32_t *key_m = item->mask;
6350 const rte_be32_t *key_v = item->spec;
6351 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6352 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6353 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
6355 /* GRE K bit must be on and should already be validated */
6356 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
6357 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
6361 key_m = &gre_key_default_mask;
6362 MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
6363 rte_be_to_cpu_32(*key_m) >> 8);
6364 MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
6365 rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
6366 MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
6367 rte_be_to_cpu_32(*key_m) & 0xFF);
6368 MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
6369 rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
6373 * Add GRE item to matcher and to the value.
6375 * @param[in, out] matcher
6377 * @param[in, out] key
6378 * Flow matcher value.
6380 * Flow pattern to translate.
6382 * Item is inner pattern.
6385 flow_dv_translate_item_gre(void *matcher, void *key,
6386 const struct rte_flow_item *item,
6389 const struct rte_flow_item_gre *gre_m = item->mask;
6390 const struct rte_flow_item_gre *gre_v = item->spec;
6393 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6394 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6401 uint16_t s_present:1;
6402 uint16_t k_present:1;
6403 uint16_t rsvd_bit1:1;
6404 uint16_t c_present:1;
6408 } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
6411 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6413 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6415 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6417 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6419 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6420 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
6424 gre_m = &rte_flow_item_gre_mask;
6425 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
6426 rte_be_to_cpu_16(gre_m->protocol));
6427 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6428 rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
6429 gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
6430 gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
6431 MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
6432 gre_crks_rsvd0_ver_m.c_present);
6433 MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
6434 gre_crks_rsvd0_ver_v.c_present &
6435 gre_crks_rsvd0_ver_m.c_present);
6436 MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
6437 gre_crks_rsvd0_ver_m.k_present);
6438 MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
6439 gre_crks_rsvd0_ver_v.k_present &
6440 gre_crks_rsvd0_ver_m.k_present);
6441 MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
6442 gre_crks_rsvd0_ver_m.s_present);
6443 MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
6444 gre_crks_rsvd0_ver_v.s_present &
6445 gre_crks_rsvd0_ver_m.s_present);
6449 * Add NVGRE item to matcher and to the value.
6451 * @param[in, out] matcher
6453 * @param[in, out] key
6454 * Flow matcher value.
6456 * Flow pattern to translate.
6458 * Item is inner pattern.
6461 flow_dv_translate_item_nvgre(void *matcher, void *key,
6462 const struct rte_flow_item *item,
6465 const struct rte_flow_item_nvgre *nvgre_m = item->mask;
6466 const struct rte_flow_item_nvgre *nvgre_v = item->spec;
6467 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6468 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6469 const char *tni_flow_id_m = (const char *)nvgre_m->tni;
6470 const char *tni_flow_id_v = (const char *)nvgre_v->tni;
6476 /* For NVGRE, GRE header fields must be set with defined values. */
6477 const struct rte_flow_item_gre gre_spec = {
6478 .c_rsvd0_ver = RTE_BE16(0x2000),
6479 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
6481 const struct rte_flow_item_gre gre_mask = {
6482 .c_rsvd0_ver = RTE_BE16(0xB000),
6483 .protocol = RTE_BE16(UINT16_MAX),
6485 const struct rte_flow_item gre_item = {
6490 flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
6494 nvgre_m = &rte_flow_item_nvgre_mask;
6495 size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
6496 gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
6497 gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
6498 memcpy(gre_key_m, tni_flow_id_m, size);
6499 for (i = 0; i < size; ++i)
6500 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
6504 * Add VXLAN item to matcher and to the value.
6506 * @param[in, out] matcher
6508 * @param[in, out] key
6509 * Flow matcher value.
6511 * Flow pattern to translate.
6513 * Item is inner pattern.
6516 flow_dv_translate_item_vxlan(void *matcher, void *key,
6517 const struct rte_flow_item *item,
6520 const struct rte_flow_item_vxlan *vxlan_m = item->mask;
6521 const struct rte_flow_item_vxlan *vxlan_v = item->spec;
6524 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6525 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6533 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6535 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6537 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6539 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6541 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6542 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6543 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6544 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6545 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6550 vxlan_m = &rte_flow_item_vxlan_mask;
6551 size = sizeof(vxlan_m->vni);
6552 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
6553 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
6554 memcpy(vni_m, vxlan_m->vni, size);
6555 for (i = 0; i < size; ++i)
6556 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6560 * Add VXLAN-GPE item to matcher and to the value.
6562 * @param[in, out] matcher
6564 * @param[in, out] key
6565 * Flow matcher value.
6567 * Flow pattern to translate.
6569 * Item is inner pattern.
6573 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
6574 const struct rte_flow_item *item, int inner)
6576 const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
6577 const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
6581 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
6583 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
6589 uint8_t flags_m = 0xff;
6590 uint8_t flags_v = 0xc;
6593 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6595 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6597 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6599 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6601 dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
6602 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
6603 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6604 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6605 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6610 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
6611 size = sizeof(vxlan_m->vni);
6612 vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
6613 vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
6614 memcpy(vni_m, vxlan_m->vni, size);
6615 for (i = 0; i < size; ++i)
6616 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
6617 if (vxlan_m->flags) {
6618 flags_m = vxlan_m->flags;
6619 flags_v = vxlan_v->flags;
6621 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
6622 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
6623 MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
6625 MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
6630 * Add Geneve item to matcher and to the value.
6632 * @param[in, out] matcher
6634 * @param[in, out] key
6635 * Flow matcher value.
6637 * Flow pattern to translate.
6639 * Item is inner pattern.
6643 flow_dv_translate_item_geneve(void *matcher, void *key,
6644 const struct rte_flow_item *item, int inner)
6646 const struct rte_flow_item_geneve *geneve_m = item->mask;
6647 const struct rte_flow_item_geneve *geneve_v = item->spec;
6650 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6651 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6660 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6662 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
6664 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
6666 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6668 dport = MLX5_UDP_PORT_GENEVE;
6669 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
6670 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
6671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
6676 geneve_m = &rte_flow_item_geneve_mask;
6677 size = sizeof(geneve_m->vni);
6678 vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
6679 vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
6680 memcpy(vni_m, geneve_m->vni, size);
6681 for (i = 0; i < size; ++i)
6682 vni_v[i] = vni_m[i] & geneve_v->vni[i];
6683 MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
6684 rte_be_to_cpu_16(geneve_m->protocol));
6685 MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
6686 rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
6687 gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
6688 gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
6689 MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
6690 MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6691 MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
6692 MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
6693 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
6694 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6695 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
6696 MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
6697 MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
6701 * Add MPLS item to matcher and to the value.
6703 * @param[in, out] matcher
6705 * @param[in, out] key
6706 * Flow matcher value.
6708 * Flow pattern to translate.
6709 * @param[in] prev_layer
6710 * The protocol layer indicated in previous item.
6712 * Item is inner pattern.
6715 flow_dv_translate_item_mpls(void *matcher, void *key,
6716 const struct rte_flow_item *item,
6717 uint64_t prev_layer,
6720 const uint32_t *in_mpls_m = item->mask;
6721 const uint32_t *in_mpls_v = item->spec;
6722 uint32_t *out_mpls_m = 0;
6723 uint32_t *out_mpls_v = 0;
6724 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
6725 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
6726 void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
6728 void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6729 void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
6730 void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
6732 switch (prev_layer) {
6733 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6734 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
6735 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
6736 MLX5_UDP_PORT_MPLS);
6738 case MLX5_FLOW_LAYER_GRE:
6739 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
6740 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
6741 RTE_ETHER_TYPE_MPLS);
6744 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
6745 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
6752 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
6753 switch (prev_layer) {
6754 case MLX5_FLOW_LAYER_OUTER_L4_UDP:
6756 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6757 outer_first_mpls_over_udp);
6759 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6760 outer_first_mpls_over_udp);
6762 case MLX5_FLOW_LAYER_GRE:
6764 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
6765 outer_first_mpls_over_gre);
6767 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
6768 outer_first_mpls_over_gre);
6771 /* Inner MPLS not over GRE is not supported. */
6774 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6778 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
6784 if (out_mpls_m && out_mpls_v) {
6785 *out_mpls_m = *in_mpls_m;
6786 *out_mpls_v = *in_mpls_v & *in_mpls_m;
6791 * Add metadata register item to matcher
6793 * @param[in, out] matcher
6795 * @param[in, out] key
6796 * Flow matcher value.
6797 * @param[in] reg_type
6798 * Type of device metadata register
6805 flow_dv_match_meta_reg(void *matcher, void *key,
6806 enum modify_reg reg_type,
6807 uint32_t data, uint32_t mask)
6810 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
6812 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
6818 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
6819 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
6822 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
6823 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
6827 * The metadata register C0 field might be divided into
6828 * source vport index and META item value, we should set
6829 * this field according to specified mask, not as whole one.
6831 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
6833 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
6834 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
6837 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
6840 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
6841 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
6844 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
6845 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
6848 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
6849 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
6852 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
6853 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
6856 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
6857 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
6860 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
6861 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
6864 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
6865 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
6874 * Add MARK item to matcher
6877 * The device to configure through.
6878 * @param[in, out] matcher
6880 * @param[in, out] key
6881 * Flow matcher value.
6883 * Flow pattern to translate.
6886 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
6887 void *matcher, void *key,
6888 const struct rte_flow_item *item)
6890 struct mlx5_priv *priv = dev->data->dev_private;
6891 const struct rte_flow_item_mark *mark;
6895 mark = item->mask ? (const void *)item->mask :
6896 &rte_flow_item_mark_mask;
6897 mask = mark->id & priv->sh->dv_mark_mask;
6898 mark = (const void *)item->spec;
6900 value = mark->id & priv->sh->dv_mark_mask & mask;
6902 enum modify_reg reg;
6904 /* Get the metadata register index for the mark. */
6905 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
6906 MLX5_ASSERT(reg > 0);
6907 if (reg == REG_C_0) {
6908 struct mlx5_priv *priv = dev->data->dev_private;
6909 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6910 uint32_t shl_c0 = rte_bsf32(msk_c0);
6916 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6921 * Add META item to matcher
6924 * The devich to configure through.
6925 * @param[in, out] matcher
6927 * @param[in, out] key
6928 * Flow matcher value.
6930 * Attributes of flow that includes this item.
6932 * Flow pattern to translate.
6935 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
6936 void *matcher, void *key,
6937 const struct rte_flow_attr *attr,
6938 const struct rte_flow_item *item)
6940 const struct rte_flow_item_meta *meta_m;
6941 const struct rte_flow_item_meta *meta_v;
6943 meta_m = (const void *)item->mask;
6945 meta_m = &rte_flow_item_meta_mask;
6946 meta_v = (const void *)item->spec;
6949 uint32_t value = meta_v->data;
6950 uint32_t mask = meta_m->data;
6952 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
6956 * In datapath code there is no endianness
6957 * coversions for perfromance reasons, all
6958 * pattern conversions are done in rte_flow.
6960 value = rte_cpu_to_be_32(value);
6961 mask = rte_cpu_to_be_32(mask);
6962 if (reg == REG_C_0) {
6963 struct mlx5_priv *priv = dev->data->dev_private;
6964 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
6965 uint32_t shl_c0 = rte_bsf32(msk_c0);
6966 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
6967 uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
6974 MLX5_ASSERT(msk_c0);
6975 MLX5_ASSERT(!(~msk_c0 & mask));
6977 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
6982 * Add vport metadata Reg C0 item to matcher
6984 * @param[in, out] matcher
6986 * @param[in, out] key
6987 * Flow matcher value.
6989 * Flow pattern to translate.
6992 flow_dv_translate_item_meta_vport(void *matcher, void *key,
6993 uint32_t value, uint32_t mask)
6995 flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
6999 * Add tag item to matcher
7002 * The devich to configure through.
7003 * @param[in, out] matcher
7005 * @param[in, out] key
7006 * Flow matcher value.
7008 * Flow pattern to translate.
7011 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
7012 void *matcher, void *key,
7013 const struct rte_flow_item *item)
7015 const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
7016 const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
7017 uint32_t mask, value;
7020 value = tag_v->data;
7021 mask = tag_m ? tag_m->data : UINT32_MAX;
7022 if (tag_v->id == REG_C_0) {
7023 struct mlx5_priv *priv = dev->data->dev_private;
7024 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
7025 uint32_t shl_c0 = rte_bsf32(msk_c0);
7031 flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
7035 * Add TAG item to matcher
7038 * The devich to configure through.
7039 * @param[in, out] matcher
7041 * @param[in, out] key
7042 * Flow matcher value.
7044 * Flow pattern to translate.
7047 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
7048 void *matcher, void *key,
7049 const struct rte_flow_item *item)
7051 const struct rte_flow_item_tag *tag_v = item->spec;
7052 const struct rte_flow_item_tag *tag_m = item->mask;
7053 enum modify_reg reg;
7056 tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
7057 /* Get the metadata register index for the tag. */
7058 reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
7059 MLX5_ASSERT(reg > 0);
7060 flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
7064 * Add source vport match to the specified matcher.
7066 * @param[in, out] matcher
7068 * @param[in, out] key
7069 * Flow matcher value.
7071 * Source vport value to match
7076 flow_dv_translate_item_source_vport(void *matcher, void *key,
7077 int16_t port, uint16_t mask)
7079 void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7080 void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7082 MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
7083 MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
7087 * Translate port-id item to eswitch match on port-id.
7090 * The devich to configure through.
7091 * @param[in, out] matcher
7093 * @param[in, out] key
7094 * Flow matcher value.
7096 * Flow pattern to translate.
7099 * 0 on success, a negative errno value otherwise.
7102 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
7103 void *key, const struct rte_flow_item *item)
7105 const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
7106 const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
7107 struct mlx5_priv *priv;
7110 mask = pid_m ? pid_m->id : 0xffff;
7111 id = pid_v ? pid_v->id : dev->data->port_id;
7112 priv = mlx5_port_to_eswitch_info(id, item == NULL);
7115 /* Translate to vport field or to metadata, depending on mode. */
7116 if (priv->vport_meta_mask)
7117 flow_dv_translate_item_meta_vport(matcher, key,
7118 priv->vport_meta_tag,
7119 priv->vport_meta_mask);
7121 flow_dv_translate_item_source_vport(matcher, key,
7122 priv->vport_id, mask);
7127 * Add ICMP6 item to matcher and to the value.
7129 * @param[in, out] matcher
7131 * @param[in, out] key
7132 * Flow matcher value.
7134 * Flow pattern to translate.
7136 * Item is inner pattern.
7139 flow_dv_translate_item_icmp6(void *matcher, void *key,
7140 const struct rte_flow_item *item,
7143 const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
7144 const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
7147 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7149 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7151 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7153 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7155 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7157 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7159 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7160 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
7164 icmp6_m = &rte_flow_item_icmp6_mask;
7166 * Force flow only to match the non-fragmented IPv6 ICMPv6 packets.
7167 * If only the protocol is specified, no need to match the frag.
7169 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7170 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7171 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
7172 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
7173 icmp6_v->type & icmp6_m->type);
7174 MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
7175 MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
7176 icmp6_v->code & icmp6_m->code);
7180 * Add ICMP item to matcher and to the value.
7182 * @param[in, out] matcher
7184 * @param[in, out] key
7185 * Flow matcher value.
7187 * Flow pattern to translate.
7189 * Item is inner pattern.
7192 flow_dv_translate_item_icmp(void *matcher, void *key,
7193 const struct rte_flow_item *item,
7196 const struct rte_flow_item_icmp *icmp_m = item->mask;
7197 const struct rte_flow_item_icmp *icmp_v = item->spec;
7200 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7202 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7204 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7206 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7208 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7210 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7212 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
7213 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
7217 icmp_m = &rte_flow_item_icmp_mask;
7219 * Force flow only to match the non-fragmented IPv4 ICMP packets.
7220 * If only the protocol is specified, no need to match the frag.
7222 MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7223 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
7224 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
7225 icmp_m->hdr.icmp_type);
7226 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
7227 icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
7228 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
7229 icmp_m->hdr.icmp_code);
7230 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
7231 icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
7235 * Add GTP item to matcher and to the value.
7237 * @param[in, out] matcher
7239 * @param[in, out] key
7240 * Flow matcher value.
7242 * Flow pattern to translate.
7244 * Item is inner pattern.
7247 flow_dv_translate_item_gtp(void *matcher, void *key,
7248 const struct rte_flow_item *item, int inner)
7250 const struct rte_flow_item_gtp *gtp_m = item->mask;
7251 const struct rte_flow_item_gtp *gtp_v = item->spec;
7254 void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
7256 void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
7257 uint16_t dport = RTE_GTPU_UDP_PORT;
7260 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7262 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7264 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7266 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7268 if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7269 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7270 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7275 gtp_m = &rte_flow_item_gtp_mask;
7276 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
7277 gtp_m->v_pt_rsv_flags);
7278 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
7279 gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
7280 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
7281 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
7282 gtp_v->msg_type & gtp_m->msg_type);
7283 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
7284 rte_be_to_cpu_32(gtp_m->teid));
7285 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
7286 rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
7290 * Add eCPRI item to matcher and to the value.
7293 * The devich to configure through.
7294 * @param[in, out] matcher
7296 * @param[in, out] key
7297 * Flow matcher value.
7299 * Flow pattern to translate.
7300 * @param[in] samples
7301 * Sample IDs to be used in the matching.
7304 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
7305 void *key, const struct rte_flow_item *item)
7307 struct mlx5_priv *priv = dev->data->dev_private;
7308 const struct rte_flow_item_ecpri *ecpri_m = item->mask;
7309 const struct rte_flow_item_ecpri *ecpri_v = item->spec;
7310 void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
7312 void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
7320 ecpri_m = &rte_flow_item_ecpri_mask;
7322 * Maximal four DW samples are supported in a single matching now.
7323 * Two are used now for a eCPRI matching:
7324 * 1. Type: one byte, mask should be 0x00ff0000 in network order
7325 * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
7328 if (!ecpri_m->hdr.common.u32)
7330 samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
7331 /* Need to take the whole DW as the mask to fill the entry. */
7332 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7333 prog_sample_field_value_0);
7334 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7335 prog_sample_field_value_0);
7336 /* Already big endian (network order) in the header. */
7337 *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
7338 *(uint32_t *)dw_v = ecpri_v->hdr.common.u32;
7339 /* Sample#0, used for matching type, offset 0. */
7340 MLX5_SET(fte_match_set_misc4, misc4_m,
7341 prog_sample_field_id_0, samples[0]);
7342 /* It makes no sense to set the sample ID in the mask field. */
7343 MLX5_SET(fte_match_set_misc4, misc4_v,
7344 prog_sample_field_id_0, samples[0]);
7346 * Checking if message body part needs to be matched.
7347 * Some wildcard rules only matching type field should be supported.
7349 if (ecpri_m->hdr.dummy[0]) {
7350 switch (ecpri_v->hdr.common.type) {
7351 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
7352 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
7353 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
7354 dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
7355 prog_sample_field_value_1);
7356 dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
7357 prog_sample_field_value_1);
7358 *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
7359 *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0];
7360 /* Sample#1, to match message body, offset 4. */
7361 MLX5_SET(fte_match_set_misc4, misc4_m,
7362 prog_sample_field_id_1, samples[1]);
7363 MLX5_SET(fte_match_set_misc4, misc4_v,
7364 prog_sample_field_id_1, samples[1]);
7367 /* Others, do not match any sample ID. */
7373 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
7375 #define HEADER_IS_ZERO(match_criteria, headers) \
7376 !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
7377 matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
7380 * Calculate flow matcher enable bitmap.
7382 * @param match_criteria
7383 * Pointer to flow matcher criteria.
7386 * Bitmap of enabled fields.
7389 flow_dv_matcher_enable(uint32_t *match_criteria)
7391 uint8_t match_criteria_enable;
7393 match_criteria_enable =
7394 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
7395 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
7396 match_criteria_enable |=
7397 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
7398 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
7399 match_criteria_enable |=
7400 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
7401 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
7402 match_criteria_enable |=
7403 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
7404 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
7405 match_criteria_enable |=
7406 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
7407 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
7408 match_criteria_enable |=
7409 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
7410 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
7411 return match_criteria_enable;
7418 * @param[in, out] dev
7419 * Pointer to rte_eth_dev structure.
7420 * @param[in] table_id
7423 * Direction of the table.
7424 * @param[in] transfer
7425 * E-Switch or NIC flow.
7427 * pointer to error structure.
7430 * Returns tables resource based on the index, NULL in case of failed.
7432 static struct mlx5_flow_tbl_resource *
7433 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
7434 uint32_t table_id, uint8_t egress,
7436 struct rte_flow_error *error)
7438 struct mlx5_priv *priv = dev->data->dev_private;
7439 struct mlx5_dev_ctx_shared *sh = priv->sh;
7440 struct mlx5_flow_tbl_resource *tbl;
7441 union mlx5_flow_tbl_key table_key = {
7443 .table_id = table_id,
7445 .domain = !!transfer,
7446 .direction = !!egress,
7449 struct mlx5_hlist_entry *pos = mlx5_hlist_lookup(sh->flow_tbls,
7451 struct mlx5_flow_tbl_data_entry *tbl_data;
7457 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry,
7459 tbl = &tbl_data->tbl;
7460 rte_atomic32_inc(&tbl->refcnt);
7463 tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
7465 rte_flow_error_set(error, ENOMEM,
7466 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7468 "cannot allocate flow table data entry");
7471 tbl_data->idx = idx;
7472 tbl = &tbl_data->tbl;
7473 pos = &tbl_data->entry;
7475 domain = sh->fdb_domain;
7477 domain = sh->tx_domain;
7479 domain = sh->rx_domain;
7480 ret = mlx5_flow_os_create_flow_tbl(domain, table_id, &tbl->obj);
7482 rte_flow_error_set(error, ENOMEM,
7483 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7484 NULL, "cannot create flow table object");
7485 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7489 * No multi-threads now, but still better to initialize the reference
7490 * count before insert it into the hash list.
7492 rte_atomic32_init(&tbl->refcnt);
7493 /* Jump action reference count is initialized here. */
7494 rte_atomic32_init(&tbl_data->jump.refcnt);
7495 pos->key = table_key.v64;
7496 ret = mlx5_hlist_insert(sh->flow_tbls, pos);
7498 rte_flow_error_set(error, -ret,
7499 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7500 "cannot insert flow table data entry");
7501 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7502 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
7504 rte_atomic32_inc(&tbl->refcnt);
7509 * Release a flow table.
7512 * Pointer to rte_eth_dev structure.
7514 * Table resource to be released.
7517 * Returns 0 if table was released, else return 1;
7520 flow_dv_tbl_resource_release(struct rte_eth_dev *dev,
7521 struct mlx5_flow_tbl_resource *tbl)
7523 struct mlx5_priv *priv = dev->data->dev_private;
7524 struct mlx5_dev_ctx_shared *sh = priv->sh;
7525 struct mlx5_flow_tbl_data_entry *tbl_data =
7526 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7530 if (rte_atomic32_dec_and_test(&tbl->refcnt)) {
7531 struct mlx5_hlist_entry *pos = &tbl_data->entry;
7533 mlx5_flow_os_destroy_flow_tbl(tbl->obj);
7535 /* remove the entry from the hash list and free memory. */
7536 mlx5_hlist_remove(sh->flow_tbls, pos);
7537 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_JUMP],
7545 * Register the flow matcher.
7547 * @param[in, out] dev
7548 * Pointer to rte_eth_dev structure.
7549 * @param[in, out] matcher
7550 * Pointer to flow matcher.
7551 * @param[in, out] key
7552 * Pointer to flow table key.
7553 * @parm[in, out] dev_flow
7554 * Pointer to the dev_flow.
7556 * pointer to error structure.
7559 * 0 on success otherwise -errno and errno is set.
7562 flow_dv_matcher_register(struct rte_eth_dev *dev,
7563 struct mlx5_flow_dv_matcher *matcher,
7564 union mlx5_flow_tbl_key *key,
7565 struct mlx5_flow *dev_flow,
7566 struct rte_flow_error *error)
7568 struct mlx5_priv *priv = dev->data->dev_private;
7569 struct mlx5_dev_ctx_shared *sh = priv->sh;
7570 struct mlx5_flow_dv_matcher *cache_matcher;
7571 struct mlx5dv_flow_matcher_attr dv_attr = {
7572 .type = IBV_FLOW_ATTR_NORMAL,
7573 .match_mask = (void *)&matcher->mask,
7575 struct mlx5_flow_tbl_resource *tbl;
7576 struct mlx5_flow_tbl_data_entry *tbl_data;
7579 tbl = flow_dv_tbl_resource_get(dev, key->table_id, key->direction,
7580 key->domain, error);
7582 return -rte_errno; /* No need to refill the error info */
7583 tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
7584 /* Lookup from cache. */
7585 LIST_FOREACH(cache_matcher, &tbl_data->matchers, next) {
7586 if (matcher->crc == cache_matcher->crc &&
7587 matcher->priority == cache_matcher->priority &&
7588 !memcmp((const void *)matcher->mask.buf,
7589 (const void *)cache_matcher->mask.buf,
7590 cache_matcher->mask.size)) {
7592 "%s group %u priority %hd use %s "
7593 "matcher %p: refcnt %d++",
7594 key->domain ? "FDB" : "NIC", key->table_id,
7595 cache_matcher->priority,
7596 key->direction ? "tx" : "rx",
7597 (void *)cache_matcher,
7598 rte_atomic32_read(&cache_matcher->refcnt));
7599 rte_atomic32_inc(&cache_matcher->refcnt);
7600 dev_flow->handle->dvh.matcher = cache_matcher;
7601 /* old matcher should not make the table ref++. */
7602 flow_dv_tbl_resource_release(dev, tbl);
7606 /* Register new matcher. */
7607 cache_matcher = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache_matcher), 0,
7609 if (!cache_matcher) {
7610 flow_dv_tbl_resource_release(dev, tbl);
7611 return rte_flow_error_set(error, ENOMEM,
7612 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7613 "cannot allocate matcher memory");
7615 *cache_matcher = *matcher;
7616 dv_attr.match_criteria_enable =
7617 flow_dv_matcher_enable(cache_matcher->mask.buf);
7618 dv_attr.priority = matcher->priority;
7620 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
7621 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
7622 &cache_matcher->matcher_object);
7624 mlx5_free(cache_matcher);
7625 #ifdef HAVE_MLX5DV_DR
7626 flow_dv_tbl_resource_release(dev, tbl);
7628 return rte_flow_error_set(error, ENOMEM,
7629 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7630 NULL, "cannot create matcher");
7632 /* Save the table information */
7633 cache_matcher->tbl = tbl;
7634 rte_atomic32_init(&cache_matcher->refcnt);
7635 /* only matcher ref++, table ref++ already done above in get API. */
7636 rte_atomic32_inc(&cache_matcher->refcnt);
7637 LIST_INSERT_HEAD(&tbl_data->matchers, cache_matcher, next);
7638 dev_flow->handle->dvh.matcher = cache_matcher;
7639 DRV_LOG(DEBUG, "%s group %u priority %hd new %s matcher %p: refcnt %d",
7640 key->domain ? "FDB" : "NIC", key->table_id,
7641 cache_matcher->priority,
7642 key->direction ? "tx" : "rx", (void *)cache_matcher,
7643 rte_atomic32_read(&cache_matcher->refcnt));
7648 * Find existing tag resource or create and register a new one.
7650 * @param dev[in, out]
7651 * Pointer to rte_eth_dev structure.
7652 * @param[in, out] tag_be24
7653 * Tag value in big endian then R-shift 8.
7654 * @parm[in, out] dev_flow
7655 * Pointer to the dev_flow.
7657 * pointer to error structure.
7660 * 0 on success otherwise -errno and errno is set.
7663 flow_dv_tag_resource_register
7664 (struct rte_eth_dev *dev,
7666 struct mlx5_flow *dev_flow,
7667 struct rte_flow_error *error)
7669 struct mlx5_priv *priv = dev->data->dev_private;
7670 struct mlx5_dev_ctx_shared *sh = priv->sh;
7671 struct mlx5_flow_dv_tag_resource *cache_resource;
7672 struct mlx5_hlist_entry *entry;
7675 /* Lookup a matching resource from cache. */
7676 entry = mlx5_hlist_lookup(sh->tag_table, (uint64_t)tag_be24);
7678 cache_resource = container_of
7679 (entry, struct mlx5_flow_dv_tag_resource, entry);
7680 rte_atomic32_inc(&cache_resource->refcnt);
7681 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
7682 dev_flow->dv.tag_resource = cache_resource;
7683 DRV_LOG(DEBUG, "cached tag resource %p: refcnt now %d++",
7684 (void *)cache_resource,
7685 rte_atomic32_read(&cache_resource->refcnt));
7688 /* Register new resource. */
7689 cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG],
7690 &dev_flow->handle->dvh.rix_tag);
7691 if (!cache_resource)
7692 return rte_flow_error_set(error, ENOMEM,
7693 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7694 "cannot allocate resource memory");
7695 cache_resource->entry.key = (uint64_t)tag_be24;
7696 ret = mlx5_flow_os_create_flow_action_tag(tag_be24,
7697 &cache_resource->action);
7699 mlx5_free(cache_resource);
7700 return rte_flow_error_set(error, ENOMEM,
7701 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7702 NULL, "cannot create action");
7704 rte_atomic32_init(&cache_resource->refcnt);
7705 rte_atomic32_inc(&cache_resource->refcnt);
7706 if (mlx5_hlist_insert(sh->tag_table, &cache_resource->entry)) {
7707 mlx5_flow_os_destroy_flow_action(cache_resource->action);
7708 mlx5_free(cache_resource);
7709 return rte_flow_error_set(error, EEXIST,
7710 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
7711 NULL, "cannot insert tag");
7713 dev_flow->dv.tag_resource = cache_resource;
7714 DRV_LOG(DEBUG, "new tag resource %p: refcnt now %d++",
7715 (void *)cache_resource,
7716 rte_atomic32_read(&cache_resource->refcnt));
7724 * Pointer to Ethernet device.
7729 * 1 while a reference on it exists, 0 when freed.
7732 flow_dv_tag_release(struct rte_eth_dev *dev,
7735 struct mlx5_priv *priv = dev->data->dev_private;
7736 struct mlx5_dev_ctx_shared *sh = priv->sh;
7737 struct mlx5_flow_dv_tag_resource *tag;
7739 tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7742 DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
7743 dev->data->port_id, (void *)tag,
7744 rte_atomic32_read(&tag->refcnt));
7745 if (rte_atomic32_dec_and_test(&tag->refcnt)) {
7746 claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
7747 mlx5_hlist_remove(sh->tag_table, &tag->entry);
7748 DRV_LOG(DEBUG, "port %u tag %p: removed",
7749 dev->data->port_id, (void *)tag);
7750 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
7757 * Translate port ID action to vport.
7760 * Pointer to rte_eth_dev structure.
7762 * Pointer to the port ID action.
7763 * @param[out] dst_port_id
7764 * The target port ID.
7766 * Pointer to the error structure.
7769 * 0 on success, a negative errno value otherwise and rte_errno is set.
7772 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
7773 const struct rte_flow_action *action,
7774 uint32_t *dst_port_id,
7775 struct rte_flow_error *error)
7778 struct mlx5_priv *priv;
7779 const struct rte_flow_action_port_id *conf =
7780 (const struct rte_flow_action_port_id *)action->conf;
7782 port = conf->original ? dev->data->port_id : conf->id;
7783 priv = mlx5_port_to_eswitch_info(port, false);
7785 return rte_flow_error_set(error, -rte_errno,
7786 RTE_FLOW_ERROR_TYPE_ACTION,
7788 "No eswitch info was found for port");
7789 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
7791 * This parameter is transferred to
7792 * mlx5dv_dr_action_create_dest_ib_port().
7794 *dst_port_id = priv->dev_port;
7797 * Legacy mode, no LAG configurations is supported.
7798 * This parameter is transferred to
7799 * mlx5dv_dr_action_create_dest_vport().
7801 *dst_port_id = priv->vport_id;
7807 * Create a counter with aging configuration.
7810 * Pointer to rte_eth_dev structure.
7812 * Pointer to the counter action configuration.
7814 * Pointer to the aging action configuration.
7817 * Index to flow counter on success, 0 otherwise.
7820 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
7821 struct mlx5_flow *dev_flow,
7822 const struct rte_flow_action_count *count,
7823 const struct rte_flow_action_age *age)
7826 struct mlx5_age_param *age_param;
7828 counter = flow_dv_counter_alloc(dev,
7829 count ? count->shared : 0,
7830 count ? count->id : 0,
7831 dev_flow->dv.group, !!age);
7832 if (!counter || age == NULL)
7834 age_param = flow_dv_counter_idx_get_age(dev, counter);
7836 * The counter age accuracy may have a bit delay. Have 3/4
7837 * second bias on the timeount in order to let it age in time.
7839 age_param->context = age->context ? age->context :
7840 (void *)(uintptr_t)(dev_flow->flow_idx);
7842 * The counter age accuracy may have a bit delay. Have 3/4
7843 * second bias on the timeount in order to let it age in time.
7845 age_param->timeout = age->timeout * 10 - MLX5_AGING_TIME_DELAY;
7846 /* Set expire time in unit of 0.1 sec. */
7847 age_param->port_id = dev->data->port_id;
7848 age_param->expire = age_param->timeout +
7849 rte_rdtsc() / (rte_get_tsc_hz() / 10);
7850 rte_atomic16_set(&age_param->state, AGE_CANDIDATE);
7854 * Add Tx queue matcher
7857 * Pointer to the dev struct.
7858 * @param[in, out] matcher
7860 * @param[in, out] key
7861 * Flow matcher value.
7863 * Flow pattern to translate.
7865 * Item is inner pattern.
7868 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
7869 void *matcher, void *key,
7870 const struct rte_flow_item *item)
7872 const struct mlx5_rte_flow_item_tx_queue *queue_m;
7873 const struct mlx5_rte_flow_item_tx_queue *queue_v;
7875 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7877 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7878 struct mlx5_txq_ctrl *txq;
7882 queue_m = (const void *)item->mask;
7885 queue_v = (const void *)item->spec;
7888 txq = mlx5_txq_get(dev, queue_v->queue);
7891 queue = txq->obj->sq->id;
7892 MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
7893 MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
7894 queue & queue_m->queue);
7895 mlx5_txq_release(dev, queue_v->queue);
7899 * Set the hash fields according to the @p flow information.
7901 * @param[in] dev_flow
7902 * Pointer to the mlx5_flow.
7903 * @param[in] rss_desc
7904 * Pointer to the mlx5_flow_rss_desc.
7907 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
7908 struct mlx5_flow_rss_desc *rss_desc)
7910 uint64_t items = dev_flow->handle->layers;
7912 uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
7914 dev_flow->hash_fields = 0;
7915 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
7916 if (rss_desc->level >= 2) {
7917 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
7921 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
7922 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
7923 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
7924 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7925 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
7926 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7927 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
7929 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
7931 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
7932 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
7933 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
7934 if (rss_types & ETH_RSS_L3_SRC_ONLY)
7935 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
7936 else if (rss_types & ETH_RSS_L3_DST_ONLY)
7937 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
7939 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
7942 if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
7943 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
7944 if (rss_types & ETH_RSS_UDP) {
7945 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7946 dev_flow->hash_fields |=
7947 IBV_RX_HASH_SRC_PORT_UDP;
7948 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7949 dev_flow->hash_fields |=
7950 IBV_RX_HASH_DST_PORT_UDP;
7952 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
7954 } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
7955 (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
7956 if (rss_types & ETH_RSS_TCP) {
7957 if (rss_types & ETH_RSS_L4_SRC_ONLY)
7958 dev_flow->hash_fields |=
7959 IBV_RX_HASH_SRC_PORT_TCP;
7960 else if (rss_types & ETH_RSS_L4_DST_ONLY)
7961 dev_flow->hash_fields |=
7962 IBV_RX_HASH_DST_PORT_TCP;
7964 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
7970 * Fill the flow with DV spec, lock free
7971 * (mutex should be acquired by caller).
7974 * Pointer to rte_eth_dev structure.
7975 * @param[in, out] dev_flow
7976 * Pointer to the sub flow.
7978 * Pointer to the flow attributes.
7980 * Pointer to the list of items.
7981 * @param[in] actions
7982 * Pointer to the list of actions.
7984 * Pointer to the error structure.
7987 * 0 on success, a negative errno value otherwise and rte_errno is set.
7990 __flow_dv_translate(struct rte_eth_dev *dev,
7991 struct mlx5_flow *dev_flow,
7992 const struct rte_flow_attr *attr,
7993 const struct rte_flow_item items[],
7994 const struct rte_flow_action actions[],
7995 struct rte_flow_error *error)
7997 struct mlx5_priv *priv = dev->data->dev_private;
7998 struct mlx5_dev_config *dev_conf = &priv->config;
7999 struct rte_flow *flow = dev_flow->flow;
8000 struct mlx5_flow_handle *handle = dev_flow->handle;
8001 struct mlx5_flow_rss_desc *rss_desc = &((struct mlx5_flow_rss_desc *)
8003 [!!priv->flow_nested_idx];
8004 uint64_t item_flags = 0;
8005 uint64_t last_item = 0;
8006 uint64_t action_flags = 0;
8007 uint64_t priority = attr->priority;
8008 struct mlx5_flow_dv_matcher matcher = {
8010 .size = sizeof(matcher.mask.buf) -
8011 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
8015 bool actions_end = false;
8017 struct mlx5_flow_dv_modify_hdr_resource res;
8018 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
8019 sizeof(struct mlx5_modification_cmd) *
8020 (MLX5_MAX_MODIFY_NUM + 1)];
8022 struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
8023 const struct rte_flow_action_count *count = NULL;
8024 const struct rte_flow_action_age *age = NULL;
8025 union flow_dv_attr flow_attr = { .attr = 0 };
8027 union mlx5_flow_tbl_key tbl_key;
8028 uint32_t modify_action_position = UINT32_MAX;
8029 void *match_mask = matcher.mask.buf;
8030 void *match_value = dev_flow->dv.value.buf;
8031 uint8_t next_protocol = 0xff;
8032 struct rte_vlan_hdr vlan = { 0 };
8036 mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
8037 MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
8038 ret = mlx5_flow_group_to_table(attr, dev_flow->external, attr->group,
8039 !!priv->fdb_def_rule, &table, error);
8042 dev_flow->dv.group = table;
8044 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
8045 if (priority == MLX5_FLOW_PRIO_RSVD)
8046 priority = dev_conf->flow_prio - 1;
8047 /* number of actions must be set to 0 in case of dirty stack. */
8048 mhdr_res->actions_num = 0;
8049 for (; !actions_end ; actions++) {
8050 const struct rte_flow_action_queue *queue;
8051 const struct rte_flow_action_rss *rss;
8052 const struct rte_flow_action *action = actions;
8053 const uint8_t *rss_key;
8054 const struct rte_flow_action_jump *jump_data;
8055 const struct rte_flow_action_meter *mtr;
8056 struct mlx5_flow_tbl_resource *tbl;
8057 uint32_t port_id = 0;
8058 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
8059 int action_type = actions->type;
8060 const struct rte_flow_action *found_action = NULL;
8061 struct mlx5_flow_meter *fm = NULL;
8063 if (!mlx5_flow_os_action_supported(action_type))
8064 return rte_flow_error_set(error, ENOTSUP,
8065 RTE_FLOW_ERROR_TYPE_ACTION,
8067 "action not supported");
8068 switch (action_type) {
8069 case RTE_FLOW_ACTION_TYPE_VOID:
8071 case RTE_FLOW_ACTION_TYPE_PORT_ID:
8072 if (flow_dv_translate_action_port_id(dev, action,
8075 port_id_resource.port_id = port_id;
8076 MLX5_ASSERT(!handle->rix_port_id_action);
8077 if (flow_dv_port_id_action_resource_register
8078 (dev, &port_id_resource, dev_flow, error))
8080 dev_flow->dv.actions[actions_n++] =
8081 dev_flow->dv.port_id_action->action;
8082 action_flags |= MLX5_FLOW_ACTION_PORT_ID;
8083 dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
8085 case RTE_FLOW_ACTION_TYPE_FLAG:
8086 action_flags |= MLX5_FLOW_ACTION_FLAG;
8087 dev_flow->handle->mark = 1;
8088 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8089 struct rte_flow_action_mark mark = {
8090 .id = MLX5_FLOW_MARK_DEFAULT,
8093 if (flow_dv_convert_action_mark(dev, &mark,
8097 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8100 tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
8102 * Only one FLAG or MARK is supported per device flow
8103 * right now. So the pointer to the tag resource must be
8104 * zero before the register process.
8106 MLX5_ASSERT(!handle->dvh.rix_tag);
8107 if (flow_dv_tag_resource_register(dev, tag_be,
8110 MLX5_ASSERT(dev_flow->dv.tag_resource);
8111 dev_flow->dv.actions[actions_n++] =
8112 dev_flow->dv.tag_resource->action;
8114 case RTE_FLOW_ACTION_TYPE_MARK:
8115 action_flags |= MLX5_FLOW_ACTION_MARK;
8116 dev_flow->handle->mark = 1;
8117 if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
8118 const struct rte_flow_action_mark *mark =
8119 (const struct rte_flow_action_mark *)
8122 if (flow_dv_convert_action_mark(dev, mark,
8126 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
8130 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
8131 /* Legacy (non-extensive) MARK action. */
8132 tag_be = mlx5_flow_mark_set
8133 (((const struct rte_flow_action_mark *)
8134 (actions->conf))->id);
8135 MLX5_ASSERT(!handle->dvh.rix_tag);
8136 if (flow_dv_tag_resource_register(dev, tag_be,
8139 MLX5_ASSERT(dev_flow->dv.tag_resource);
8140 dev_flow->dv.actions[actions_n++] =
8141 dev_flow->dv.tag_resource->action;
8143 case RTE_FLOW_ACTION_TYPE_SET_META:
8144 if (flow_dv_convert_action_set_meta
8145 (dev, mhdr_res, attr,
8146 (const struct rte_flow_action_set_meta *)
8147 actions->conf, error))
8149 action_flags |= MLX5_FLOW_ACTION_SET_META;
8151 case RTE_FLOW_ACTION_TYPE_SET_TAG:
8152 if (flow_dv_convert_action_set_tag
8154 (const struct rte_flow_action_set_tag *)
8155 actions->conf, error))
8157 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8159 case RTE_FLOW_ACTION_TYPE_DROP:
8160 action_flags |= MLX5_FLOW_ACTION_DROP;
8161 dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
8163 case RTE_FLOW_ACTION_TYPE_QUEUE:
8164 queue = actions->conf;
8165 rss_desc->queue_num = 1;
8166 rss_desc->queue[0] = queue->index;
8167 action_flags |= MLX5_FLOW_ACTION_QUEUE;
8168 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8170 case RTE_FLOW_ACTION_TYPE_RSS:
8171 rss = actions->conf;
8172 memcpy(rss_desc->queue, rss->queue,
8173 rss->queue_num * sizeof(uint16_t));
8174 rss_desc->queue_num = rss->queue_num;
8175 /* NULL RSS key indicates default RSS key. */
8176 rss_key = !rss->key ? rss_hash_default_key : rss->key;
8177 memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
8179 * rss->level and rss.types should be set in advance
8180 * when expanding items for RSS.
8182 action_flags |= MLX5_FLOW_ACTION_RSS;
8183 dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
8185 case RTE_FLOW_ACTION_TYPE_AGE:
8186 case RTE_FLOW_ACTION_TYPE_COUNT:
8187 if (!dev_conf->devx) {
8188 return rte_flow_error_set
8190 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8192 "count action not supported");
8194 /* Save information first, will apply later. */
8195 if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
8196 count = action->conf;
8199 action_flags |= MLX5_FLOW_ACTION_COUNT;
8201 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
8202 dev_flow->dv.actions[actions_n++] =
8203 priv->sh->pop_vlan_action;
8204 action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
8206 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
8207 if (!(action_flags &
8208 MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
8209 flow_dev_get_vlan_info_from_items(items, &vlan);
8210 vlan.eth_proto = rte_be_to_cpu_16
8211 ((((const struct rte_flow_action_of_push_vlan *)
8212 actions->conf)->ethertype));
8213 found_action = mlx5_flow_find_action
8215 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
8217 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8218 found_action = mlx5_flow_find_action
8220 RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
8222 mlx5_update_vlan_vid_pcp(found_action, &vlan);
8223 if (flow_dv_create_action_push_vlan
8224 (dev, attr, &vlan, dev_flow, error))
8226 dev_flow->dv.actions[actions_n++] =
8227 dev_flow->dv.push_vlan_res->action;
8228 action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
8230 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
8231 /* of_vlan_push action handled this action */
8232 MLX5_ASSERT(action_flags &
8233 MLX5_FLOW_ACTION_OF_PUSH_VLAN);
8235 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
8236 if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
8238 flow_dev_get_vlan_info_from_items(items, &vlan);
8239 mlx5_update_vlan_vid_pcp(actions, &vlan);
8240 /* If no VLAN push - this is a modify header action */
8241 if (flow_dv_convert_action_modify_vlan_vid
8242 (mhdr_res, actions, error))
8244 action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
8246 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
8247 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
8248 if (flow_dv_create_action_l2_encap(dev, actions,
8253 dev_flow->dv.actions[actions_n++] =
8254 dev_flow->dv.encap_decap->action;
8255 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8257 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
8258 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
8259 if (flow_dv_create_action_l2_decap(dev, dev_flow,
8263 dev_flow->dv.actions[actions_n++] =
8264 dev_flow->dv.encap_decap->action;
8265 action_flags |= MLX5_FLOW_ACTION_DECAP;
8267 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
8268 /* Handle encap with preceding decap. */
8269 if (action_flags & MLX5_FLOW_ACTION_DECAP) {
8270 if (flow_dv_create_action_raw_encap
8271 (dev, actions, dev_flow, attr, error))
8273 dev_flow->dv.actions[actions_n++] =
8274 dev_flow->dv.encap_decap->action;
8276 /* Handle encap without preceding decap. */
8277 if (flow_dv_create_action_l2_encap
8278 (dev, actions, dev_flow, attr->transfer,
8281 dev_flow->dv.actions[actions_n++] =
8282 dev_flow->dv.encap_decap->action;
8284 action_flags |= MLX5_FLOW_ACTION_ENCAP;
8286 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
8287 while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
8289 if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
8290 if (flow_dv_create_action_l2_decap
8291 (dev, dev_flow, attr->transfer, error))
8293 dev_flow->dv.actions[actions_n++] =
8294 dev_flow->dv.encap_decap->action;
8296 /* If decap is followed by encap, handle it at encap. */
8297 action_flags |= MLX5_FLOW_ACTION_DECAP;
8299 case RTE_FLOW_ACTION_TYPE_JUMP:
8300 jump_data = action->conf;
8301 ret = mlx5_flow_group_to_table(attr, dev_flow->external,
8303 !!priv->fdb_def_rule,
8307 tbl = flow_dv_tbl_resource_get(dev, table,
8309 attr->transfer, error);
8311 return rte_flow_error_set
8313 RTE_FLOW_ERROR_TYPE_ACTION,
8315 "cannot create jump action.");
8316 if (flow_dv_jump_tbl_resource_register
8317 (dev, tbl, dev_flow, error)) {
8318 flow_dv_tbl_resource_release(dev, tbl);
8319 return rte_flow_error_set
8321 RTE_FLOW_ERROR_TYPE_ACTION,
8323 "cannot create jump action.");
8325 dev_flow->dv.actions[actions_n++] =
8326 dev_flow->dv.jump->action;
8327 action_flags |= MLX5_FLOW_ACTION_JUMP;
8328 dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
8330 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
8331 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
8332 if (flow_dv_convert_action_modify_mac
8333 (mhdr_res, actions, error))
8335 action_flags |= actions->type ==
8336 RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
8337 MLX5_FLOW_ACTION_SET_MAC_SRC :
8338 MLX5_FLOW_ACTION_SET_MAC_DST;
8340 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
8341 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
8342 if (flow_dv_convert_action_modify_ipv4
8343 (mhdr_res, actions, error))
8345 action_flags |= actions->type ==
8346 RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
8347 MLX5_FLOW_ACTION_SET_IPV4_SRC :
8348 MLX5_FLOW_ACTION_SET_IPV4_DST;
8350 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
8351 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
8352 if (flow_dv_convert_action_modify_ipv6
8353 (mhdr_res, actions, error))
8355 action_flags |= actions->type ==
8356 RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
8357 MLX5_FLOW_ACTION_SET_IPV6_SRC :
8358 MLX5_FLOW_ACTION_SET_IPV6_DST;
8360 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
8361 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
8362 if (flow_dv_convert_action_modify_tp
8363 (mhdr_res, actions, items,
8364 &flow_attr, dev_flow, !!(action_flags &
8365 MLX5_FLOW_ACTION_DECAP), error))
8367 action_flags |= actions->type ==
8368 RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
8369 MLX5_FLOW_ACTION_SET_TP_SRC :
8370 MLX5_FLOW_ACTION_SET_TP_DST;
8372 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
8373 if (flow_dv_convert_action_modify_dec_ttl
8374 (mhdr_res, items, &flow_attr, dev_flow,
8376 MLX5_FLOW_ACTION_DECAP), error))
8378 action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
8380 case RTE_FLOW_ACTION_TYPE_SET_TTL:
8381 if (flow_dv_convert_action_modify_ttl
8382 (mhdr_res, actions, items, &flow_attr,
8383 dev_flow, !!(action_flags &
8384 MLX5_FLOW_ACTION_DECAP), error))
8386 action_flags |= MLX5_FLOW_ACTION_SET_TTL;
8388 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
8389 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
8390 if (flow_dv_convert_action_modify_tcp_seq
8391 (mhdr_res, actions, error))
8393 action_flags |= actions->type ==
8394 RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
8395 MLX5_FLOW_ACTION_INC_TCP_SEQ :
8396 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
8399 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
8400 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
8401 if (flow_dv_convert_action_modify_tcp_ack
8402 (mhdr_res, actions, error))
8404 action_flags |= actions->type ==
8405 RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
8406 MLX5_FLOW_ACTION_INC_TCP_ACK :
8407 MLX5_FLOW_ACTION_DEC_TCP_ACK;
8409 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
8410 if (flow_dv_convert_action_set_reg
8411 (mhdr_res, actions, error))
8413 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8415 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
8416 if (flow_dv_convert_action_copy_mreg
8417 (dev, mhdr_res, actions, error))
8419 action_flags |= MLX5_FLOW_ACTION_SET_TAG;
8421 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
8422 action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
8423 dev_flow->handle->fate_action =
8424 MLX5_FLOW_FATE_DEFAULT_MISS;
8426 case RTE_FLOW_ACTION_TYPE_METER:
8427 mtr = actions->conf;
8429 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
8432 return rte_flow_error_set(error,
8434 RTE_FLOW_ERROR_TYPE_ACTION,
8437 "or invalid parameters");
8438 flow->meter = fm->idx;
8440 /* Set the meter action. */
8442 fm = mlx5_ipool_get(priv->sh->ipool
8443 [MLX5_IPOOL_MTR], flow->meter);
8445 return rte_flow_error_set(error,
8447 RTE_FLOW_ERROR_TYPE_ACTION,
8450 "or invalid parameters");
8452 dev_flow->dv.actions[actions_n++] =
8453 fm->mfts->meter_action;
8454 action_flags |= MLX5_FLOW_ACTION_METER;
8456 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
8457 if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
8460 action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
8462 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
8463 if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
8466 action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
8468 case RTE_FLOW_ACTION_TYPE_END:
8470 if (mhdr_res->actions_num) {
8471 /* create modify action if needed. */
8472 if (flow_dv_modify_hdr_resource_register
8473 (dev, mhdr_res, dev_flow, error))
8475 dev_flow->dv.actions[modify_action_position] =
8476 handle->dvh.modify_hdr->action;
8478 if (action_flags & MLX5_FLOW_ACTION_COUNT) {
8480 flow_dv_translate_create_counter(dev,
8481 dev_flow, count, age);
8484 return rte_flow_error_set
8486 RTE_FLOW_ERROR_TYPE_ACTION,
8488 "cannot create counter"
8490 dev_flow->dv.actions[actions_n++] =
8491 (flow_dv_counter_get_by_idx(dev,
8492 flow->counter, NULL))->action;
8498 if (mhdr_res->actions_num &&
8499 modify_action_position == UINT32_MAX)
8500 modify_action_position = actions_n++;
8502 dev_flow->dv.actions_n = actions_n;
8503 dev_flow->act_flags = action_flags;
8504 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
8505 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
8506 int item_type = items->type;
8508 if (!mlx5_flow_os_item_supported(item_type))
8509 return rte_flow_error_set(error, ENOTSUP,
8510 RTE_FLOW_ERROR_TYPE_ITEM,
8511 NULL, "item not supported");
8512 switch (item_type) {
8513 case RTE_FLOW_ITEM_TYPE_PORT_ID:
8514 flow_dv_translate_item_port_id(dev, match_mask,
8515 match_value, items);
8516 last_item = MLX5_FLOW_ITEM_PORT_ID;
8518 case RTE_FLOW_ITEM_TYPE_ETH:
8519 flow_dv_translate_item_eth(match_mask, match_value,
8521 dev_flow->dv.group);
8522 matcher.priority = action_flags &
8523 MLX5_FLOW_ACTION_DEFAULT_MISS &&
8524 !dev_flow->external ?
8525 MLX5_PRIORITY_MAP_L3 :
8526 MLX5_PRIORITY_MAP_L2;
8527 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
8528 MLX5_FLOW_LAYER_OUTER_L2;
8530 case RTE_FLOW_ITEM_TYPE_VLAN:
8531 flow_dv_translate_item_vlan(dev_flow,
8532 match_mask, match_value,
8534 dev_flow->dv.group);
8535 matcher.priority = MLX5_PRIORITY_MAP_L2;
8536 last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
8537 MLX5_FLOW_LAYER_INNER_VLAN) :
8538 (MLX5_FLOW_LAYER_OUTER_L2 |
8539 MLX5_FLOW_LAYER_OUTER_VLAN);
8541 case RTE_FLOW_ITEM_TYPE_IPV4:
8542 mlx5_flow_tunnel_ip_check(items, next_protocol,
8543 &item_flags, &tunnel);
8544 flow_dv_translate_item_ipv4(match_mask, match_value,
8545 items, item_flags, tunnel,
8546 dev_flow->dv.group);
8547 matcher.priority = MLX5_PRIORITY_MAP_L3;
8548 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
8549 MLX5_FLOW_LAYER_OUTER_L3_IPV4;
8550 if (items->mask != NULL &&
8551 ((const struct rte_flow_item_ipv4 *)
8552 items->mask)->hdr.next_proto_id) {
8554 ((const struct rte_flow_item_ipv4 *)
8555 (items->spec))->hdr.next_proto_id;
8557 ((const struct rte_flow_item_ipv4 *)
8558 (items->mask))->hdr.next_proto_id;
8560 /* Reset for inner layer. */
8561 next_protocol = 0xff;
8564 case RTE_FLOW_ITEM_TYPE_IPV6:
8565 mlx5_flow_tunnel_ip_check(items, next_protocol,
8566 &item_flags, &tunnel);
8567 flow_dv_translate_item_ipv6(match_mask, match_value,
8568 items, item_flags, tunnel,
8569 dev_flow->dv.group);
8570 matcher.priority = MLX5_PRIORITY_MAP_L3;
8571 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
8572 MLX5_FLOW_LAYER_OUTER_L3_IPV6;
8573 if (items->mask != NULL &&
8574 ((const struct rte_flow_item_ipv6 *)
8575 items->mask)->hdr.proto) {
8577 ((const struct rte_flow_item_ipv6 *)
8578 items->spec)->hdr.proto;
8580 ((const struct rte_flow_item_ipv6 *)
8581 items->mask)->hdr.proto;
8583 /* Reset for inner layer. */
8584 next_protocol = 0xff;
8587 case RTE_FLOW_ITEM_TYPE_TCP:
8588 flow_dv_translate_item_tcp(match_mask, match_value,
8590 matcher.priority = MLX5_PRIORITY_MAP_L4;
8591 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
8592 MLX5_FLOW_LAYER_OUTER_L4_TCP;
8594 case RTE_FLOW_ITEM_TYPE_UDP:
8595 flow_dv_translate_item_udp(match_mask, match_value,
8597 matcher.priority = MLX5_PRIORITY_MAP_L4;
8598 last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
8599 MLX5_FLOW_LAYER_OUTER_L4_UDP;
8601 case RTE_FLOW_ITEM_TYPE_GRE:
8602 flow_dv_translate_item_gre(match_mask, match_value,
8604 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8605 last_item = MLX5_FLOW_LAYER_GRE;
8607 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
8608 flow_dv_translate_item_gre_key(match_mask,
8609 match_value, items);
8610 last_item = MLX5_FLOW_LAYER_GRE_KEY;
8612 case RTE_FLOW_ITEM_TYPE_NVGRE:
8613 flow_dv_translate_item_nvgre(match_mask, match_value,
8615 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8616 last_item = MLX5_FLOW_LAYER_GRE;
8618 case RTE_FLOW_ITEM_TYPE_VXLAN:
8619 flow_dv_translate_item_vxlan(match_mask, match_value,
8621 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8622 last_item = MLX5_FLOW_LAYER_VXLAN;
8624 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
8625 flow_dv_translate_item_vxlan_gpe(match_mask,
8628 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8629 last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
8631 case RTE_FLOW_ITEM_TYPE_GENEVE:
8632 flow_dv_translate_item_geneve(match_mask, match_value,
8634 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8635 last_item = MLX5_FLOW_LAYER_GENEVE;
8637 case RTE_FLOW_ITEM_TYPE_MPLS:
8638 flow_dv_translate_item_mpls(match_mask, match_value,
8639 items, last_item, tunnel);
8640 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8641 last_item = MLX5_FLOW_LAYER_MPLS;
8643 case RTE_FLOW_ITEM_TYPE_MARK:
8644 flow_dv_translate_item_mark(dev, match_mask,
8645 match_value, items);
8646 last_item = MLX5_FLOW_ITEM_MARK;
8648 case RTE_FLOW_ITEM_TYPE_META:
8649 flow_dv_translate_item_meta(dev, match_mask,
8650 match_value, attr, items);
8651 last_item = MLX5_FLOW_ITEM_METADATA;
8653 case RTE_FLOW_ITEM_TYPE_ICMP:
8654 flow_dv_translate_item_icmp(match_mask, match_value,
8656 last_item = MLX5_FLOW_LAYER_ICMP;
8658 case RTE_FLOW_ITEM_TYPE_ICMP6:
8659 flow_dv_translate_item_icmp6(match_mask, match_value,
8661 last_item = MLX5_FLOW_LAYER_ICMP6;
8663 case RTE_FLOW_ITEM_TYPE_TAG:
8664 flow_dv_translate_item_tag(dev, match_mask,
8665 match_value, items);
8666 last_item = MLX5_FLOW_ITEM_TAG;
8668 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
8669 flow_dv_translate_mlx5_item_tag(dev, match_mask,
8670 match_value, items);
8671 last_item = MLX5_FLOW_ITEM_TAG;
8673 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
8674 flow_dv_translate_item_tx_queue(dev, match_mask,
8677 last_item = MLX5_FLOW_ITEM_TX_QUEUE;
8679 case RTE_FLOW_ITEM_TYPE_GTP:
8680 flow_dv_translate_item_gtp(match_mask, match_value,
8682 matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
8683 last_item = MLX5_FLOW_LAYER_GTP;
8685 case RTE_FLOW_ITEM_TYPE_ECPRI:
8686 if (!mlx5_flex_parser_ecpri_exist(dev)) {
8687 /* Create it only the first time to be used. */
8688 ret = mlx5_flex_parser_ecpri_alloc(dev);
8690 return rte_flow_error_set
8692 RTE_FLOW_ERROR_TYPE_ITEM,
8694 "cannot create eCPRI parser");
8696 /* Adjust the length matcher and device flow value. */
8697 matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
8698 dev_flow->dv.value.size =
8699 MLX5_ST_SZ_BYTES(fte_match_param);
8700 flow_dv_translate_item_ecpri(dev, match_mask,
8701 match_value, items);
8702 /* No other protocol should follow eCPRI layer. */
8703 last_item = MLX5_FLOW_LAYER_ECPRI;
8708 item_flags |= last_item;
8711 * When E-Switch mode is enabled, we have two cases where we need to
8712 * set the source port manually.
8713 * The first one, is in case of Nic steering rule, and the second is
8714 * E-Switch rule where no port_id item was found. In both cases
8715 * the source port is set according the current port in use.
8717 if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
8718 (priv->representor || priv->master)) {
8719 if (flow_dv_translate_item_port_id(dev, match_mask,
8723 #ifdef RTE_LIBRTE_MLX5_DEBUG
8724 MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
8725 dev_flow->dv.value.buf));
8728 * Layers may be already initialized from prefix flow if this dev_flow
8729 * is the suffix flow.
8731 handle->layers |= item_flags;
8732 if (action_flags & MLX5_FLOW_ACTION_RSS)
8733 flow_dv_hashfields_set(dev_flow, rss_desc);
8734 /* Register matcher. */
8735 matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
8737 matcher.priority = mlx5_flow_adjust_priority(dev, priority,
8739 /* reserved field no needs to be set to 0 here. */
8740 tbl_key.domain = attr->transfer;
8741 tbl_key.direction = attr->egress;
8742 tbl_key.table_id = dev_flow->dv.group;
8743 if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow, error))
8749 * Apply the flow to the NIC, lock free,
8750 * (mutex should be acquired by caller).
8753 * Pointer to the Ethernet device structure.
8754 * @param[in, out] flow
8755 * Pointer to flow structure.
8757 * Pointer to error structure.
8760 * 0 on success, a negative errno value otherwise and rte_errno is set.
8763 __flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
8764 struct rte_flow_error *error)
8766 struct mlx5_flow_dv_workspace *dv;
8767 struct mlx5_flow_handle *dh;
8768 struct mlx5_flow_handle_dv *dv_h;
8769 struct mlx5_flow *dev_flow;
8770 struct mlx5_priv *priv = dev->data->dev_private;
8771 uint32_t handle_idx;
8776 for (idx = priv->flow_idx - 1; idx >= priv->flow_nested_idx; idx--) {
8777 dev_flow = &((struct mlx5_flow *)priv->inter_flows)[idx];
8779 dh = dev_flow->handle;
8782 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8784 dv->actions[n++] = priv->sh->esw_drop_action;
8786 struct mlx5_hrxq *drop_hrxq;
8787 drop_hrxq = mlx5_hrxq_drop_new(dev);
8791 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8793 "cannot get drop hash queue");
8797 * Drop queues will be released by the specify
8798 * mlx5_hrxq_drop_release() function. Assign
8799 * the special index to hrxq to mark the queue
8800 * has been allocated.
8802 dh->rix_hrxq = UINT32_MAX;
8803 dv->actions[n++] = drop_hrxq->action;
8805 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8806 struct mlx5_hrxq *hrxq;
8808 struct mlx5_flow_rss_desc *rss_desc =
8809 &((struct mlx5_flow_rss_desc *)priv->rss_desc)
8810 [!!priv->flow_nested_idx];
8812 MLX5_ASSERT(rss_desc->queue_num);
8813 hrxq_idx = mlx5_hrxq_get(dev, rss_desc->key,
8814 MLX5_RSS_HASH_KEY_LEN,
8815 dev_flow->hash_fields,
8817 rss_desc->queue_num);
8819 hrxq_idx = mlx5_hrxq_new
8820 (dev, rss_desc->key,
8821 MLX5_RSS_HASH_KEY_LEN,
8822 dev_flow->hash_fields,
8824 rss_desc->queue_num,
8826 MLX5_FLOW_LAYER_TUNNEL));
8828 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
8833 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8834 "cannot get hash queue");
8837 dh->rix_hrxq = hrxq_idx;
8838 dv->actions[n++] = hrxq->action;
8839 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
8840 if (flow_dv_default_miss_resource_register
8844 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8845 "cannot create default miss resource");
8846 goto error_default_miss;
8848 dh->rix_default_fate = MLX5_FLOW_FATE_DEFAULT_MISS;
8849 dv->actions[n++] = priv->sh->default_miss.action;
8851 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
8852 (void *)&dv->value, n,
8853 dv->actions, &dh->drv_flow);
8855 rte_flow_error_set(error, errno,
8856 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
8858 "hardware refuses to create flow");
8861 if (priv->vmwa_context &&
8862 dh->vf_vlan.tag && !dh->vf_vlan.created) {
8864 * The rule contains the VLAN pattern.
8865 * For VF we are going to create VLAN
8866 * interface to make hypervisor set correct
8867 * e-Switch vport context.
8869 mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
8874 if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
8875 flow_dv_default_miss_resource_release(dev);
8877 err = rte_errno; /* Save rte_errno before cleanup. */
8878 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
8879 handle_idx, dh, next) {
8880 /* hrxq is union, don't clear it if the flag is not set. */
8882 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
8883 mlx5_hrxq_drop_release(dev);
8885 } else if (dh->fate_action == MLX5_FLOW_FATE_QUEUE) {
8886 mlx5_hrxq_release(dev, dh->rix_hrxq);
8890 if (dh->vf_vlan.tag && dh->vf_vlan.created)
8891 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
8893 rte_errno = err; /* Restore rte_errno. */
8898 * Release the flow matcher.
8901 * Pointer to Ethernet device.
8903 * Pointer to mlx5_flow_handle.
8906 * 1 while a reference on it exists, 0 when freed.
8909 flow_dv_matcher_release(struct rte_eth_dev *dev,
8910 struct mlx5_flow_handle *handle)
8912 struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
8914 MLX5_ASSERT(matcher->matcher_object);
8915 DRV_LOG(DEBUG, "port %u matcher %p: refcnt %d--",
8916 dev->data->port_id, (void *)matcher,
8917 rte_atomic32_read(&matcher->refcnt));
8918 if (rte_atomic32_dec_and_test(&matcher->refcnt)) {
8919 claim_zero(mlx5_flow_os_destroy_flow_matcher
8920 (matcher->matcher_object));
8921 LIST_REMOVE(matcher, next);
8922 /* table ref-- in release interface. */
8923 flow_dv_tbl_resource_release(dev, matcher->tbl);
8925 DRV_LOG(DEBUG, "port %u matcher %p: removed",
8926 dev->data->port_id, (void *)matcher);
8933 * Release an encap/decap resource.
8936 * Pointer to Ethernet device.
8938 * Pointer to mlx5_flow_handle.
8941 * 1 while a reference on it exists, 0 when freed.
8944 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
8945 struct mlx5_flow_handle *handle)
8947 struct mlx5_priv *priv = dev->data->dev_private;
8948 uint32_t idx = handle->dvh.rix_encap_decap;
8949 struct mlx5_flow_dv_encap_decap_resource *cache_resource;
8951 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8953 if (!cache_resource)
8955 MLX5_ASSERT(cache_resource->action);
8956 DRV_LOG(DEBUG, "encap/decap resource %p: refcnt %d--",
8957 (void *)cache_resource,
8958 rte_atomic32_read(&cache_resource->refcnt));
8959 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
8960 claim_zero(mlx5_flow_os_destroy_flow_action
8961 (cache_resource->action));
8962 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
8963 &priv->sh->encaps_decaps, idx,
8964 cache_resource, next);
8965 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
8966 DRV_LOG(DEBUG, "encap/decap resource %p: removed",
8967 (void *)cache_resource);
8974 * Release an jump to table action resource.
8977 * Pointer to Ethernet device.
8979 * Pointer to mlx5_flow_handle.
8982 * 1 while a reference on it exists, 0 when freed.
8985 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
8986 struct mlx5_flow_handle *handle)
8988 struct mlx5_priv *priv = dev->data->dev_private;
8989 struct mlx5_flow_dv_jump_tbl_resource *cache_resource;
8990 struct mlx5_flow_tbl_data_entry *tbl_data;
8992 tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
8996 cache_resource = &tbl_data->jump;
8997 MLX5_ASSERT(cache_resource->action);
8998 DRV_LOG(DEBUG, "jump table resource %p: refcnt %d--",
8999 (void *)cache_resource,
9000 rte_atomic32_read(&cache_resource->refcnt));
9001 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9002 claim_zero(mlx5_flow_os_destroy_flow_action
9003 (cache_resource->action));
9004 /* jump action memory free is inside the table release. */
9005 flow_dv_tbl_resource_release(dev, &tbl_data->tbl);
9006 DRV_LOG(DEBUG, "jump table resource %p: removed",
9007 (void *)cache_resource);
9014 * Release a default miss resource.
9017 * Pointer to Ethernet device.
9019 * 1 while a reference on it exists, 0 when freed.
9022 flow_dv_default_miss_resource_release(struct rte_eth_dev *dev)
9024 struct mlx5_priv *priv = dev->data->dev_private;
9025 struct mlx5_dev_ctx_shared *sh = priv->sh;
9026 struct mlx5_flow_default_miss_resource *cache_resource =
9029 MLX5_ASSERT(cache_resource->action);
9030 DRV_LOG(DEBUG, "default miss resource %p: refcnt %d--",
9031 (void *)cache_resource->action,
9032 rte_atomic32_read(&cache_resource->refcnt));
9033 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9034 claim_zero(mlx5_glue->destroy_flow_action
9035 (cache_resource->action));
9036 DRV_LOG(DEBUG, "default miss resource %p: removed",
9037 (void *)cache_resource->action);
9044 * Release a modify-header resource.
9047 * Pointer to mlx5_flow_handle.
9050 * 1 while a reference on it exists, 0 when freed.
9053 flow_dv_modify_hdr_resource_release(struct mlx5_flow_handle *handle)
9055 struct mlx5_flow_dv_modify_hdr_resource *cache_resource =
9056 handle->dvh.modify_hdr;
9058 MLX5_ASSERT(cache_resource->action);
9059 DRV_LOG(DEBUG, "modify-header resource %p: refcnt %d--",
9060 (void *)cache_resource,
9061 rte_atomic32_read(&cache_resource->refcnt));
9062 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9063 claim_zero(mlx5_flow_os_destroy_flow_action
9064 (cache_resource->action));
9065 LIST_REMOVE(cache_resource, next);
9066 mlx5_free(cache_resource);
9067 DRV_LOG(DEBUG, "modify-header resource %p: removed",
9068 (void *)cache_resource);
9075 * Release port ID action resource.
9078 * Pointer to Ethernet device.
9080 * Pointer to mlx5_flow_handle.
9083 * 1 while a reference on it exists, 0 when freed.
9086 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
9087 struct mlx5_flow_handle *handle)
9089 struct mlx5_priv *priv = dev->data->dev_private;
9090 struct mlx5_flow_dv_port_id_action_resource *cache_resource;
9091 uint32_t idx = handle->rix_port_id_action;
9093 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9095 if (!cache_resource)
9097 MLX5_ASSERT(cache_resource->action);
9098 DRV_LOG(DEBUG, "port ID action resource %p: refcnt %d--",
9099 (void *)cache_resource,
9100 rte_atomic32_read(&cache_resource->refcnt));
9101 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9102 claim_zero(mlx5_flow_os_destroy_flow_action
9103 (cache_resource->action));
9104 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PORT_ID],
9105 &priv->sh->port_id_action_list, idx,
9106 cache_resource, next);
9107 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PORT_ID], idx);
9108 DRV_LOG(DEBUG, "port id action resource %p: removed",
9109 (void *)cache_resource);
9116 * Release push vlan action resource.
9119 * Pointer to Ethernet device.
9121 * Pointer to mlx5_flow_handle.
9124 * 1 while a reference on it exists, 0 when freed.
9127 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
9128 struct mlx5_flow_handle *handle)
9130 struct mlx5_priv *priv = dev->data->dev_private;
9131 uint32_t idx = handle->dvh.rix_push_vlan;
9132 struct mlx5_flow_dv_push_vlan_action_resource *cache_resource;
9134 cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9136 if (!cache_resource)
9138 MLX5_ASSERT(cache_resource->action);
9139 DRV_LOG(DEBUG, "push VLAN action resource %p: refcnt %d--",
9140 (void *)cache_resource,
9141 rte_atomic32_read(&cache_resource->refcnt));
9142 if (rte_atomic32_dec_and_test(&cache_resource->refcnt)) {
9143 claim_zero(mlx5_flow_os_destroy_flow_action
9144 (cache_resource->action));
9145 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN],
9146 &priv->sh->push_vlan_action_list, idx,
9147 cache_resource, next);
9148 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
9149 DRV_LOG(DEBUG, "push vlan action resource %p: removed",
9150 (void *)cache_resource);
9157 * Release the fate resource.
9160 * Pointer to Ethernet device.
9162 * Pointer to mlx5_flow_handle.
9165 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
9166 struct mlx5_flow_handle *handle)
9168 if (!handle->rix_fate)
9170 switch (handle->fate_action) {
9171 case MLX5_FLOW_FATE_DROP:
9172 mlx5_hrxq_drop_release(dev);
9174 case MLX5_FLOW_FATE_QUEUE:
9175 mlx5_hrxq_release(dev, handle->rix_hrxq);
9177 case MLX5_FLOW_FATE_JUMP:
9178 flow_dv_jump_tbl_resource_release(dev, handle);
9180 case MLX5_FLOW_FATE_PORT_ID:
9181 flow_dv_port_id_action_resource_release(dev, handle);
9183 case MLX5_FLOW_FATE_DEFAULT_MISS:
9184 flow_dv_default_miss_resource_release(dev);
9187 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
9190 handle->rix_fate = 0;
9194 * Remove the flow from the NIC but keeps it in memory.
9195 * Lock free, (mutex should be acquired by caller).
9198 * Pointer to Ethernet device.
9199 * @param[in, out] flow
9200 * Pointer to flow structure.
9203 __flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9205 struct mlx5_flow_handle *dh;
9206 uint32_t handle_idx;
9207 struct mlx5_priv *priv = dev->data->dev_private;
9211 handle_idx = flow->dev_handles;
9212 while (handle_idx) {
9213 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9218 claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
9219 dh->drv_flow = NULL;
9221 if (dh->fate_action == MLX5_FLOW_FATE_DROP ||
9222 dh->fate_action == MLX5_FLOW_FATE_QUEUE ||
9223 dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS)
9224 flow_dv_fate_resource_release(dev, dh);
9225 if (dh->vf_vlan.tag && dh->vf_vlan.created)
9226 mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
9227 handle_idx = dh->next.next;
9232 * Remove the flow from the NIC and the memory.
9233 * Lock free, (mutex should be acquired by caller).
9236 * Pointer to the Ethernet device structure.
9237 * @param[in, out] flow
9238 * Pointer to flow structure.
9241 __flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9243 struct mlx5_flow_handle *dev_handle;
9244 struct mlx5_priv *priv = dev->data->dev_private;
9248 __flow_dv_remove(dev, flow);
9249 if (flow->counter) {
9250 flow_dv_counter_release(dev, flow->counter);
9254 struct mlx5_flow_meter *fm;
9256 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
9259 mlx5_flow_meter_detach(fm);
9262 while (flow->dev_handles) {
9263 uint32_t tmp_idx = flow->dev_handles;
9265 dev_handle = mlx5_ipool_get(priv->sh->ipool
9266 [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
9269 flow->dev_handles = dev_handle->next.next;
9270 if (dev_handle->dvh.matcher)
9271 flow_dv_matcher_release(dev, dev_handle);
9272 if (dev_handle->dvh.rix_encap_decap)
9273 flow_dv_encap_decap_resource_release(dev, dev_handle);
9274 if (dev_handle->dvh.modify_hdr)
9275 flow_dv_modify_hdr_resource_release(dev_handle);
9276 if (dev_handle->dvh.rix_push_vlan)
9277 flow_dv_push_vlan_action_resource_release(dev,
9279 if (dev_handle->dvh.rix_tag)
9280 flow_dv_tag_release(dev,
9281 dev_handle->dvh.rix_tag);
9282 flow_dv_fate_resource_release(dev, dev_handle);
9283 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
9289 * Query a dv flow rule for its statistics via devx.
9292 * Pointer to Ethernet device.
9294 * Pointer to the sub flow.
9296 * data retrieved by the query.
9298 * Perform verbose error reporting if not NULL.
9301 * 0 on success, a negative errno value otherwise and rte_errno is set.
9304 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
9305 void *data, struct rte_flow_error *error)
9307 struct mlx5_priv *priv = dev->data->dev_private;
9308 struct rte_flow_query_count *qc = data;
9310 if (!priv->config.devx)
9311 return rte_flow_error_set(error, ENOTSUP,
9312 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9314 "counters are not supported");
9315 if (flow->counter) {
9316 uint64_t pkts, bytes;
9317 struct mlx5_flow_counter *cnt;
9319 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
9321 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
9325 return rte_flow_error_set(error, -err,
9326 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9327 NULL, "cannot read counters");
9330 qc->hits = pkts - cnt->hits;
9331 qc->bytes = bytes - cnt->bytes;
9338 return rte_flow_error_set(error, EINVAL,
9339 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9341 "counters are not available");
9347 * @see rte_flow_query()
9351 flow_dv_query(struct rte_eth_dev *dev,
9352 struct rte_flow *flow __rte_unused,
9353 const struct rte_flow_action *actions __rte_unused,
9354 void *data __rte_unused,
9355 struct rte_flow_error *error __rte_unused)
9359 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
9360 switch (actions->type) {
9361 case RTE_FLOW_ACTION_TYPE_VOID:
9363 case RTE_FLOW_ACTION_TYPE_COUNT:
9364 ret = flow_dv_query_count(dev, flow, data, error);
9367 return rte_flow_error_set(error, ENOTSUP,
9368 RTE_FLOW_ERROR_TYPE_ACTION,
9370 "action not supported");
9377 * Destroy the meter table set.
9378 * Lock free, (mutex should be acquired by caller).
9381 * Pointer to Ethernet device.
9383 * Pointer to the meter table set.
9389 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
9390 struct mlx5_meter_domains_infos *tbl)
9392 struct mlx5_priv *priv = dev->data->dev_private;
9393 struct mlx5_meter_domains_infos *mtd =
9394 (struct mlx5_meter_domains_infos *)tbl;
9396 if (!mtd || !priv->config.dv_flow_en)
9398 if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
9399 claim_zero(mlx5_flow_os_destroy_flow
9400 (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
9401 if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
9402 claim_zero(mlx5_flow_os_destroy_flow
9403 (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
9404 if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
9405 claim_zero(mlx5_flow_os_destroy_flow
9406 (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
9407 if (mtd->egress.color_matcher)
9408 claim_zero(mlx5_flow_os_destroy_flow_matcher
9409 (mtd->egress.color_matcher));
9410 if (mtd->egress.any_matcher)
9411 claim_zero(mlx5_flow_os_destroy_flow_matcher
9412 (mtd->egress.any_matcher));
9413 if (mtd->egress.tbl)
9414 flow_dv_tbl_resource_release(dev, mtd->egress.tbl);
9415 if (mtd->egress.sfx_tbl)
9416 flow_dv_tbl_resource_release(dev, mtd->egress.sfx_tbl);
9417 if (mtd->ingress.color_matcher)
9418 claim_zero(mlx5_flow_os_destroy_flow_matcher
9419 (mtd->ingress.color_matcher));
9420 if (mtd->ingress.any_matcher)
9421 claim_zero(mlx5_flow_os_destroy_flow_matcher
9422 (mtd->ingress.any_matcher));
9423 if (mtd->ingress.tbl)
9424 flow_dv_tbl_resource_release(dev, mtd->ingress.tbl);
9425 if (mtd->ingress.sfx_tbl)
9426 flow_dv_tbl_resource_release(dev, mtd->ingress.sfx_tbl);
9427 if (mtd->transfer.color_matcher)
9428 claim_zero(mlx5_flow_os_destroy_flow_matcher
9429 (mtd->transfer.color_matcher));
9430 if (mtd->transfer.any_matcher)
9431 claim_zero(mlx5_flow_os_destroy_flow_matcher
9432 (mtd->transfer.any_matcher));
9433 if (mtd->transfer.tbl)
9434 flow_dv_tbl_resource_release(dev, mtd->transfer.tbl);
9435 if (mtd->transfer.sfx_tbl)
9436 flow_dv_tbl_resource_release(dev, mtd->transfer.sfx_tbl);
9438 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
9443 /* Number of meter flow actions, count and jump or count and drop. */
9444 #define METER_ACTIONS 2
9447 * Create specify domain meter table and suffix table.
9450 * Pointer to Ethernet device.
9451 * @param[in,out] mtb
9452 * Pointer to DV meter table set.
9455 * @param[in] transfer
9457 * @param[in] color_reg_c_idx
9458 * Reg C index for color match.
9461 * 0 on success, -1 otherwise and rte_errno is set.
9464 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
9465 struct mlx5_meter_domains_infos *mtb,
9466 uint8_t egress, uint8_t transfer,
9467 uint32_t color_reg_c_idx)
9469 struct mlx5_priv *priv = dev->data->dev_private;
9470 struct mlx5_dev_ctx_shared *sh = priv->sh;
9471 struct mlx5_flow_dv_match_params mask = {
9472 .size = sizeof(mask.buf),
9474 struct mlx5_flow_dv_match_params value = {
9475 .size = sizeof(value.buf),
9477 struct mlx5dv_flow_matcher_attr dv_attr = {
9478 .type = IBV_FLOW_ATTR_NORMAL,
9480 .match_criteria_enable = 0,
9481 .match_mask = (void *)&mask,
9483 void *actions[METER_ACTIONS];
9484 struct mlx5_meter_domain_info *dtb;
9485 struct rte_flow_error error;
9490 dtb = &mtb->transfer;
9494 dtb = &mtb->ingress;
9495 /* Create the meter table with METER level. */
9496 dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
9497 egress, transfer, &error);
9499 DRV_LOG(ERR, "Failed to create meter policer table.");
9502 /* Create the meter suffix table with SUFFIX level. */
9503 dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
9504 MLX5_FLOW_TABLE_LEVEL_SUFFIX,
9505 egress, transfer, &error);
9506 if (!dtb->sfx_tbl) {
9507 DRV_LOG(ERR, "Failed to create meter suffix table.");
9510 /* Create matchers, Any and Color. */
9511 dv_attr.priority = 3;
9512 dv_attr.match_criteria_enable = 0;
9513 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9516 DRV_LOG(ERR, "Failed to create meter"
9517 " policer default matcher.");
9520 dv_attr.priority = 0;
9521 dv_attr.match_criteria_enable =
9522 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9523 flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
9524 rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
9525 ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
9526 &dtb->color_matcher);
9528 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
9531 if (mtb->count_actns[RTE_MTR_DROPPED])
9532 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
9533 actions[i++] = mtb->drop_actn;
9534 /* Default rule: lowest priority, match any, actions: drop. */
9535 ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
9537 &dtb->policer_rules[RTE_MTR_DROPPED]);
9539 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
9548 * Create the needed meter and suffix tables.
9549 * Lock free, (mutex should be acquired by caller).
9552 * Pointer to Ethernet device.
9554 * Pointer to the flow meter.
9557 * Pointer to table set on success, NULL otherwise and rte_errno is set.
9559 static struct mlx5_meter_domains_infos *
9560 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
9561 const struct mlx5_flow_meter *fm)
9563 struct mlx5_priv *priv = dev->data->dev_private;
9564 struct mlx5_meter_domains_infos *mtb;
9568 if (!priv->mtr_en) {
9569 rte_errno = ENOTSUP;
9572 mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
9574 DRV_LOG(ERR, "Failed to allocate memory for meter.");
9577 /* Create meter count actions */
9578 for (i = 0; i <= RTE_MTR_DROPPED; i++) {
9579 struct mlx5_flow_counter *cnt;
9580 if (!fm->policer_stats.cnt[i])
9582 cnt = flow_dv_counter_get_by_idx(dev,
9583 fm->policer_stats.cnt[i], NULL);
9584 mtb->count_actns[i] = cnt->action;
9586 /* Create drop action. */
9587 ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
9589 DRV_LOG(ERR, "Failed to create drop action.");
9592 /* Egress meter table. */
9593 ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
9595 DRV_LOG(ERR, "Failed to prepare egress meter table.");
9598 /* Ingress meter table. */
9599 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
9601 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
9604 /* FDB meter table. */
9605 if (priv->config.dv_esw_en) {
9606 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
9607 priv->mtr_color_reg);
9609 DRV_LOG(ERR, "Failed to prepare fdb meter table.");
9615 flow_dv_destroy_mtr_tbl(dev, mtb);
9620 * Destroy domain policer rule.
9623 * Pointer to domain table.
9626 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
9630 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9631 if (dt->policer_rules[i]) {
9632 claim_zero(mlx5_flow_os_destroy_flow
9633 (dt->policer_rules[i]));
9634 dt->policer_rules[i] = NULL;
9637 if (dt->jump_actn) {
9638 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
9639 dt->jump_actn = NULL;
9644 * Destroy policer rules.
9647 * Pointer to Ethernet device.
9649 * Pointer to flow meter structure.
9651 * Pointer to flow attributes.
9657 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
9658 const struct mlx5_flow_meter *fm,
9659 const struct rte_flow_attr *attr)
9661 struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
9666 flow_dv_destroy_domain_policer_rule(&mtb->egress);
9668 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
9670 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
9675 * Create specify domain meter policer rule.
9678 * Pointer to flow meter structure.
9680 * Pointer to DV meter table set.
9681 * @param[in] mtr_reg_c
9682 * Color match REG_C.
9685 * 0 on success, -1 otherwise.
9688 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
9689 struct mlx5_meter_domain_info *dtb,
9692 struct mlx5_flow_dv_match_params matcher = {
9693 .size = sizeof(matcher.buf),
9695 struct mlx5_flow_dv_match_params value = {
9696 .size = sizeof(value.buf),
9698 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9699 void *actions[METER_ACTIONS];
9703 /* Create jump action. */
9704 if (!dtb->jump_actn)
9705 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9706 (dtb->sfx_tbl->obj, &dtb->jump_actn);
9708 DRV_LOG(ERR, "Failed to create policer jump action.");
9711 for (i = 0; i < RTE_MTR_DROPPED; i++) {
9714 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
9715 rte_col_2_mlx5_col(i), UINT8_MAX);
9716 if (mtb->count_actns[i])
9717 actions[j++] = mtb->count_actns[i];
9718 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
9719 actions[j++] = mtb->drop_actn;
9721 actions[j++] = dtb->jump_actn;
9722 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
9723 (void *)&value, j, actions,
9724 &dtb->policer_rules[i]);
9726 DRV_LOG(ERR, "Failed to create policer rule.");
9737 * Create policer rules.
9740 * Pointer to Ethernet device.
9742 * Pointer to flow meter structure.
9744 * Pointer to flow attributes.
9747 * 0 on success, -1 otherwise.
9750 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
9751 struct mlx5_flow_meter *fm,
9752 const struct rte_flow_attr *attr)
9754 struct mlx5_priv *priv = dev->data->dev_private;
9755 struct mlx5_meter_domains_infos *mtb = fm->mfts;
9759 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
9760 priv->mtr_color_reg);
9762 DRV_LOG(ERR, "Failed to create egress policer.");
9766 if (attr->ingress) {
9767 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
9768 priv->mtr_color_reg);
9770 DRV_LOG(ERR, "Failed to create ingress policer.");
9774 if (attr->transfer) {
9775 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
9776 priv->mtr_color_reg);
9778 DRV_LOG(ERR, "Failed to create transfer policer.");
9784 flow_dv_destroy_policer_rules(dev, fm, attr);
9789 * Query a devx counter.
9792 * Pointer to the Ethernet device structure.
9794 * Index to the flow counter.
9796 * Set to clear the counter statistics.
9798 * The statistics value of packets.
9800 * The statistics value of bytes.
9803 * 0 on success, otherwise return -1.
9806 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
9807 uint64_t *pkts, uint64_t *bytes)
9809 struct mlx5_priv *priv = dev->data->dev_private;
9810 struct mlx5_flow_counter *cnt;
9811 uint64_t inn_pkts, inn_bytes;
9814 if (!priv->config.devx)
9817 ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
9820 cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
9821 *pkts = inn_pkts - cnt->hits;
9822 *bytes = inn_bytes - cnt->bytes;
9824 cnt->hits = inn_pkts;
9825 cnt->bytes = inn_bytes;
9831 * Get aged-out flows.
9834 * Pointer to the Ethernet device structure.
9835 * @param[in] context
9836 * The address of an array of pointers to the aged-out flows contexts.
9837 * @param[in] nb_contexts
9838 * The length of context array pointers.
9840 * Perform verbose error reporting if not NULL. Initialized in case of
9844 * how many contexts get in success, otherwise negative errno value.
9845 * if nb_contexts is 0, return the amount of all aged contexts.
9846 * if nb_contexts is not 0 , return the amount of aged flows reported
9847 * in the context array.
9848 * @note: only stub for now
9851 flow_get_aged_flows(struct rte_eth_dev *dev,
9853 uint32_t nb_contexts,
9854 struct rte_flow_error *error)
9856 struct mlx5_priv *priv = dev->data->dev_private;
9857 struct mlx5_age_info *age_info;
9858 struct mlx5_age_param *age_param;
9859 struct mlx5_flow_counter *counter;
9862 if (nb_contexts && !context)
9863 return rte_flow_error_set(error, EINVAL,
9864 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9866 "Should assign at least one flow or"
9867 " context to get if nb_contexts != 0");
9868 age_info = GET_PORT_AGE_INFO(priv);
9869 rte_spinlock_lock(&age_info->aged_sl);
9870 TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
9873 age_param = MLX5_CNT_TO_AGE(counter);
9874 context[nb_flows - 1] = age_param->context;
9875 if (!(--nb_contexts))
9879 rte_spinlock_unlock(&age_info->aged_sl);
9880 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
9885 * Mutex-protected thunk to lock-free __flow_dv_translate().
9888 flow_dv_translate(struct rte_eth_dev *dev,
9889 struct mlx5_flow *dev_flow,
9890 const struct rte_flow_attr *attr,
9891 const struct rte_flow_item items[],
9892 const struct rte_flow_action actions[],
9893 struct rte_flow_error *error)
9897 flow_dv_shared_lock(dev);
9898 ret = __flow_dv_translate(dev, dev_flow, attr, items, actions, error);
9899 flow_dv_shared_unlock(dev);
9904 * Mutex-protected thunk to lock-free __flow_dv_apply().
9907 flow_dv_apply(struct rte_eth_dev *dev,
9908 struct rte_flow *flow,
9909 struct rte_flow_error *error)
9913 flow_dv_shared_lock(dev);
9914 ret = __flow_dv_apply(dev, flow, error);
9915 flow_dv_shared_unlock(dev);
9920 * Mutex-protected thunk to lock-free __flow_dv_remove().
9923 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
9925 flow_dv_shared_lock(dev);
9926 __flow_dv_remove(dev, flow);
9927 flow_dv_shared_unlock(dev);
9931 * Mutex-protected thunk to lock-free __flow_dv_destroy().
9934 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
9936 flow_dv_shared_lock(dev);
9937 __flow_dv_destroy(dev, flow);
9938 flow_dv_shared_unlock(dev);
9942 * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
9945 flow_dv_counter_allocate(struct rte_eth_dev *dev)
9949 flow_dv_shared_lock(dev);
9950 cnt = flow_dv_counter_alloc(dev, 0, 0, 1, 0);
9951 flow_dv_shared_unlock(dev);
9956 * Mutex-protected thunk to lock-free flow_dv_counter_release().
9959 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t cnt)
9961 flow_dv_shared_lock(dev);
9962 flow_dv_counter_release(dev, cnt);
9963 flow_dv_shared_unlock(dev);
9966 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
9967 .validate = flow_dv_validate,
9968 .prepare = flow_dv_prepare,
9969 .translate = flow_dv_translate,
9970 .apply = flow_dv_apply,
9971 .remove = flow_dv_remove,
9972 .destroy = flow_dv_destroy,
9973 .query = flow_dv_query,
9974 .create_mtr_tbls = flow_dv_create_mtr_tbl,
9975 .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
9976 .create_policer_rules = flow_dv_create_policer_rules,
9977 .destroy_policer_rules = flow_dv_destroy_policer_rules,
9978 .counter_alloc = flow_dv_counter_allocate,
9979 .counter_free = flow_dv_counter_free,
9980 .counter_query = flow_dv_counter_query,
9981 .get_aged_flows = flow_get_aged_flows,
9984 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */