drivers/net/mlx5/mlx5_flow_dv.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdalign.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10
  11 #include <rte_common.h>
  12 #include <rte_ether.h>
  13 #include <ethdev_driver.h>
  14 #include <rte_flow.h>
  15 #include <rte_flow_driver.h>
  16 #include <rte_malloc.h>
  17 #include <rte_cycles.h>
  18 #include <rte_ip.h>
  19 #include <rte_gre.h>
  20 #include <rte_vxlan.h>
  21 #include <rte_gtp.h>
  22 #include <rte_eal_paging.h>
  23 #include <rte_mpls.h>
  24
  25 #include <mlx5_glue.h>
  26 #include <mlx5_devx_cmds.h>
  27 #include <mlx5_prm.h>
  28 #include <mlx5_malloc.h>
  29
  30 #include "mlx5_defs.h"
  31 #include "mlx5.h"
  32 #include "mlx5_common_os.h"
  33 #include "mlx5_flow.h"
  34 #include "mlx5_flow_os.h"
  35 #include "mlx5_rxtx.h"
  36 #include "rte_pmd_mlx5.h"
  37
  38 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
  39
  40 #ifndef HAVE_IBV_FLOW_DEVX_COUNTERS
  41 #define MLX5DV_FLOW_ACTION_COUNTERS_DEVX 0
  42 #endif
  43
  44 #ifndef HAVE_MLX5DV_DR_ESWITCH
  45 #ifndef MLX5DV_FLOW_TABLE_TYPE_FDB
  46 #define MLX5DV_FLOW_TABLE_TYPE_FDB 0
  47 #endif
  48 #endif
  49
  50 #ifndef HAVE_MLX5DV_DR
  51 #define MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL 1
  52 #endif
  53
  54 /* VLAN header definitions */
  55 #define MLX5DV_FLOW_VLAN_PCP_SHIFT 13
  56 #define MLX5DV_FLOW_VLAN_PCP_MASK (0x7 << MLX5DV_FLOW_VLAN_PCP_SHIFT)
  57 #define MLX5DV_FLOW_VLAN_VID_MASK 0x0fff
  58 #define MLX5DV_FLOW_VLAN_PCP_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK)
  59 #define MLX5DV_FLOW_VLAN_VID_MASK_BE RTE_BE16(MLX5DV_FLOW_VLAN_VID_MASK)
  60
  61 union flow_dv_attr {
  62         struct {
  63                 uint32_t valid:1;
  64                 uint32_t ipv4:1;
  65                 uint32_t ipv6:1;
  66                 uint32_t tcp:1;
  67                 uint32_t udp:1;
  68                 uint32_t reserved:27;
  69         };
  70         uint32_t attr;
  71 };
  72
  73 static int
  74 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
  75                              struct mlx5_flow_tbl_resource *tbl);
  76
  77 static int
  78 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
  79                                      uint32_t encap_decap_idx);
  80
  81 static int
  82 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
  83                                         uint32_t port_id);
  84 static void
  85 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss);
  86
  87 static int
  88 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
  89                                   uint32_t rix_jump);
  90
  91 /**
  92  * Initialize flow attributes structure according to flow items' types.
  93  *
  94  * flow_dv_validate() avoids multiple L3/L4 layers cases other than tunnel
  95  * mode. For tunnel mode, the items to be modified are the outermost ones.
  96  *
  97  * @param[in] item
  98  *   Pointer to item specification.
  99  * @param[out] attr
 100  *   Pointer to flow attributes structure.
 101  * @param[in] dev_flow
 102  *   Pointer to the sub flow.
 103  * @param[in] tunnel_decap
 104  *   Whether action is after tunnel decapsulation.
 105  */
 106 static void
 107 flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,
 108                   struct mlx5_flow *dev_flow, bool tunnel_decap)
 109 {
 110         uint64_t layers = dev_flow->handle->layers;
 111
 112         /*
 113          * If layers is already initialized, it means this dev_flow is the
 114          * suffix flow, the layers flags is set by the prefix flow. Need to
 115          * use the layer flags from prefix flow as the suffix flow may not
 116          * have the user defined items as the flow is split.
 117          */
 118         if (layers) {
 119                 if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV4)
 120                         attr->ipv4 = 1;
 121                 else if (layers & MLX5_FLOW_LAYER_OUTER_L3_IPV6)
 122                         attr->ipv6 = 1;
 123                 if (layers & MLX5_FLOW_LAYER_OUTER_L4_TCP)
 124                         attr->tcp = 1;
 125                 else if (layers & MLX5_FLOW_LAYER_OUTER_L4_UDP)
 126                         attr->udp = 1;
 127                 attr->valid = 1;
 128                 return;
 129         }
 130         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
 131                 uint8_t next_protocol = 0xff;
 132                 switch (item->type) {
 133                 case RTE_FLOW_ITEM_TYPE_GRE:
 134                 case RTE_FLOW_ITEM_TYPE_NVGRE:
 135                 case RTE_FLOW_ITEM_TYPE_VXLAN:
 136                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
 137                 case RTE_FLOW_ITEM_TYPE_GENEVE:
 138                 case RTE_FLOW_ITEM_TYPE_MPLS:
 139                         if (tunnel_decap)
 140                                 attr->attr = 0;
 141                         break;
 142                 case RTE_FLOW_ITEM_TYPE_IPV4:
 143                         if (!attr->ipv6)
 144                                 attr->ipv4 = 1;
 145                         if (item->mask != NULL &&
 146                             ((const struct rte_flow_item_ipv4 *)
 147                             item->mask)->hdr.next_proto_id)
 148                                 next_protocol =
 149                                     ((const struct rte_flow_item_ipv4 *)
 150                                       (item->spec))->hdr.next_proto_id &
 151                                     ((const struct rte_flow_item_ipv4 *)
 152                                       (item->mask))->hdr.next_proto_id;
 153                         if ((next_protocol == IPPROTO_IPIP ||
 154                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 155                                 attr->attr = 0;
 156                         break;
 157                 case RTE_FLOW_ITEM_TYPE_IPV6:
 158                         if (!attr->ipv4)
 159                                 attr->ipv6 = 1;
 160                         if (item->mask != NULL &&
 161                             ((const struct rte_flow_item_ipv6 *)
 162                             item->mask)->hdr.proto)
 163                                 next_protocol =
 164                                     ((const struct rte_flow_item_ipv6 *)
 165                                       (item->spec))->hdr.proto &
 166                                     ((const struct rte_flow_item_ipv6 *)
 167                                       (item->mask))->hdr.proto;
 168                         if ((next_protocol == IPPROTO_IPIP ||
 169                             next_protocol == IPPROTO_IPV6) && tunnel_decap)
 170                                 attr->attr = 0;
 171                         break;
 172                 case RTE_FLOW_ITEM_TYPE_UDP:
 173                         if (!attr->tcp)
 174                                 attr->udp = 1;
 175                         break;
 176                 case RTE_FLOW_ITEM_TYPE_TCP:
 177                         if (!attr->udp)
 178                                 attr->tcp = 1;
 179                         break;
 180                 default:
 181                         break;
 182                 }
 183         }
 184         attr->valid = 1;
 185 }
 186
 187 /**
 188  * Convert rte_mtr_color to mlx5 color.
 189  *
 190  * @param[in] rcol
 191  *   rte_mtr_color.
 192  *
 193  * @return
 194  *   mlx5 color.
 195  */
 196 static int
 197 rte_col_2_mlx5_col(enum rte_color rcol)
 198 {
 199         switch (rcol) {
 200         case RTE_COLOR_GREEN:
 201                 return MLX5_FLOW_COLOR_GREEN;
 202         case RTE_COLOR_YELLOW:
 203                 return MLX5_FLOW_COLOR_YELLOW;
 204         case RTE_COLOR_RED:
 205                 return MLX5_FLOW_COLOR_RED;
 206         default:
 207                 break;
 208         }
 209         return MLX5_FLOW_COLOR_UNDEFINED;
 210 }
 211
 212 struct field_modify_info {
 213         uint32_t size; /* Size of field in protocol header, in bytes. */
 214         uint32_t offset; /* Offset of field in protocol header, in bytes. */
 215         enum mlx5_modification_field id;
 216 };
 217
 218 struct field_modify_info modify_eth[] = {
 219         {4,  0, MLX5_MODI_OUT_DMAC_47_16},
 220         {2,  4, MLX5_MODI_OUT_DMAC_15_0},
 221         {4,  6, MLX5_MODI_OUT_SMAC_47_16},
 222         {2, 10, MLX5_MODI_OUT_SMAC_15_0},
 223         {0, 0, 0},
 224 };
 225
 226 struct field_modify_info modify_vlan_out_first_vid[] = {
 227         /* Size in bits !!! */
 228         {12, 0, MLX5_MODI_OUT_FIRST_VID},
 229         {0, 0, 0},
 230 };
 231
 232 struct field_modify_info modify_ipv4[] = {
 233         {1,  1, MLX5_MODI_OUT_IP_DSCP},
 234         {1,  8, MLX5_MODI_OUT_IPV4_TTL},
 235         {4, 12, MLX5_MODI_OUT_SIPV4},
 236         {4, 16, MLX5_MODI_OUT_DIPV4},
 237         {0, 0, 0},
 238 };
 239
 240 struct field_modify_info modify_ipv6[] = {
 241         {1,  0, MLX5_MODI_OUT_IP_DSCP},
 242         {1,  7, MLX5_MODI_OUT_IPV6_HOPLIMIT},
 243         {4,  8, MLX5_MODI_OUT_SIPV6_127_96},
 244         {4, 12, MLX5_MODI_OUT_SIPV6_95_64},
 245         {4, 16, MLX5_MODI_OUT_SIPV6_63_32},
 246         {4, 20, MLX5_MODI_OUT_SIPV6_31_0},
 247         {4, 24, MLX5_MODI_OUT_DIPV6_127_96},
 248         {4, 28, MLX5_MODI_OUT_DIPV6_95_64},
 249         {4, 32, MLX5_MODI_OUT_DIPV6_63_32},
 250         {4, 36, MLX5_MODI_OUT_DIPV6_31_0},
 251         {0, 0, 0},
 252 };
 253
 254 struct field_modify_info modify_udp[] = {
 255         {2, 0, MLX5_MODI_OUT_UDP_SPORT},
 256         {2, 2, MLX5_MODI_OUT_UDP_DPORT},
 257         {0, 0, 0},
 258 };
 259
 260 struct field_modify_info modify_tcp[] = {
 261         {2, 0, MLX5_MODI_OUT_TCP_SPORT},
 262         {2, 2, MLX5_MODI_OUT_TCP_DPORT},
 263         {4, 4, MLX5_MODI_OUT_TCP_SEQ_NUM},
 264         {4, 8, MLX5_MODI_OUT_TCP_ACK_NUM},
 265         {0, 0, 0},
 266 };
 267
 268 static void
 269 mlx5_flow_tunnel_ip_check(const struct rte_flow_item *item __rte_unused,
 270                           uint8_t next_protocol, uint64_t *item_flags,
 271                           int *tunnel)
 272 {
 273         MLX5_ASSERT(item->type == RTE_FLOW_ITEM_TYPE_IPV4 ||
 274                     item->type == RTE_FLOW_ITEM_TYPE_IPV6);
 275         if (next_protocol == IPPROTO_IPIP) {
 276                 *item_flags |= MLX5_FLOW_LAYER_IPIP;
 277                 *tunnel = 1;
 278         }
 279         if (next_protocol == IPPROTO_IPV6) {
 280                 *item_flags |= MLX5_FLOW_LAYER_IPV6_ENCAP;
 281                 *tunnel = 1;
 282         }
 283 }
 284
 285 /* Update VLAN's VID/PCP based on input rte_flow_action.
 286  *
 287  * @param[in] action
 288  *   Pointer to struct rte_flow_action.
 289  * @param[out] vlan
 290  *   Pointer to struct rte_vlan_hdr.
 291  */
 292 static void
 293 mlx5_update_vlan_vid_pcp(const struct rte_flow_action *action,
 294                          struct rte_vlan_hdr *vlan)
 295 {
 296         uint16_t vlan_tci;
 297         if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP) {
 298                 vlan_tci =
 299                     ((const struct rte_flow_action_of_set_vlan_pcp *)
 300                                                action->conf)->vlan_pcp;
 301                 vlan_tci = vlan_tci << MLX5DV_FLOW_VLAN_PCP_SHIFT;
 302                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
 303                 vlan->vlan_tci |= vlan_tci;
 304         } else if (action->type == RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID) {
 305                 vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
 306                 vlan->vlan_tci |= rte_be_to_cpu_16
 307                     (((const struct rte_flow_action_of_set_vlan_vid *)
 308                                              action->conf)->vlan_vid);
 309         }
 310 }
 311
 312 /**
 313  * Fetch 1, 2, 3 or 4 byte field from the byte array
 314  * and return as unsigned integer in host-endian format.
 315  *
 316  * @param[in] data
 317  *   Pointer to data array.
 318  * @param[in] size
 319  *   Size of field to extract.
 320  *
 321  * @return
 322  *   converted field in host endian format.
 323  */
 324 static inline uint32_t
 325 flow_dv_fetch_field(const uint8_t *data, uint32_t size)
 326 {
 327         uint32_t ret;
 328
 329         switch (size) {
 330         case 1:
 331                 ret = *data;
 332                 break;
 333         case 2:
 334                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 335                 break;
 336         case 3:
 337                 ret = rte_be_to_cpu_16(*(const unaligned_uint16_t *)data);
 338                 ret = (ret << 8) | *(data + sizeof(uint16_t));
 339                 break;
 340         case 4:
 341                 ret = rte_be_to_cpu_32(*(const unaligned_uint32_t *)data);
 342                 break;
 343         default:
 344                 MLX5_ASSERT(false);
 345                 ret = 0;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 /**
 352  * Convert modify-header action to DV specification.
 353  *
 354  * Data length of each action is determined by provided field description
 355  * and the item mask. Data bit offset and width of each action is determined
 356  * by provided item mask.
 357  *
 358  * @param[in] item
 359  *   Pointer to item specification.
 360  * @param[in] field
 361  *   Pointer to field modification information.
 362  *     For MLX5_MODIFICATION_TYPE_SET specifies destination field.
 363  *     For MLX5_MODIFICATION_TYPE_ADD specifies destination field.
 364  *     For MLX5_MODIFICATION_TYPE_COPY specifies source field.
 365  * @param[in] dcopy
 366  *   Destination field info for MLX5_MODIFICATION_TYPE_COPY in @type.
 367  *   Negative offset value sets the same offset as source offset.
 368  *   size field is ignored, value is taken from source field.
 369  * @param[in,out] resource
 370  *   Pointer to the modify-header resource.
 371  * @param[in] type
 372  *   Type of modification.
 373  * @param[out] error
 374  *   Pointer to the error structure.
 375  *
 376  * @return
 377  *   0 on success, a negative errno value otherwise and rte_errno is set.
 378  */
 379 static int
 380 flow_dv_convert_modify_action(struct rte_flow_item *item,
 381                               struct field_modify_info *field,
 382                               struct field_modify_info *dcopy,
 383                               struct mlx5_flow_dv_modify_hdr_resource *resource,
 384                               uint32_t type, struct rte_flow_error *error)
 385 {
 386         uint32_t i = resource->actions_num;
 387         struct mlx5_modification_cmd *actions = resource->actions;
 388
 389         /*
 390          * The item and mask are provided in big-endian format.
 391          * The fields should be presented as in big-endian format either.
 392          * Mask must be always present, it defines the actual field width.
 393          */
 394         MLX5_ASSERT(item->mask);
 395         MLX5_ASSERT(field->size);
 396         do {
 397                 unsigned int size_b;
 398                 unsigned int off_b;
 399                 uint32_t mask;
 400                 uint32_t data;
 401
 402                 if (i >= MLX5_MAX_MODIFY_NUM)
 403                         return rte_flow_error_set(error, EINVAL,
 404                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 405                                  "too many items to modify");
 406                 /* Fetch variable byte size mask from the array. */
 407                 mask = flow_dv_fetch_field((const uint8_t *)item->mask +
 408                                            field->offset, field->size);
 409                 if (!mask) {
 410                         ++field;
 411                         continue;
 412                 }
 413                 /* Deduce actual data width in bits from mask value. */
 414                 off_b = rte_bsf32(mask);
 415                 size_b = sizeof(uint32_t) * CHAR_BIT -
 416                          off_b - __builtin_clz(mask);
 417                 MLX5_ASSERT(size_b);
 418                 size_b = size_b == sizeof(uint32_t) * CHAR_BIT ? 0 : size_b;
 419                 actions[i] = (struct mlx5_modification_cmd) {
 420                         .action_type = type,
 421                         .field = field->id,
 422                         .offset = off_b,
 423                         .length = size_b,
 424                 };
 425                 /* Convert entire record to expected big-endian format. */
 426                 actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 427                 if (type == MLX5_MODIFICATION_TYPE_COPY) {
 428                         MLX5_ASSERT(dcopy);
 429                         actions[i].dst_field = dcopy->id;
 430                         actions[i].dst_offset =
 431                                 (int)dcopy->offset < 0 ? off_b : dcopy->offset;
 432                         /* Convert entire record to big-endian format. */
 433                         actions[i].data1 = rte_cpu_to_be_32(actions[i].data1);
 434                         ++dcopy;
 435                 } else {
 436                         MLX5_ASSERT(item->spec);
 437                         data = flow_dv_fetch_field((const uint8_t *)item->spec +
 438                                                    field->offset, field->size);
 439                         /* Shift out the trailing masked bits from data. */
 440                         data = (data & mask) >> off_b;
 441                         actions[i].data1 = rte_cpu_to_be_32(data);
 442                 }
 443                 ++i;
 444                 ++field;
 445         } while (field->size);
 446         if (resource->actions_num == i)
 447                 return rte_flow_error_set(error, EINVAL,
 448                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 449                                           "invalid modification flow item");
 450         resource->actions_num = i;
 451         return 0;
 452 }
 453
 454 /**
 455  * Convert modify-header set IPv4 address action to DV specification.
 456  *
 457  * @param[in,out] resource
 458  *   Pointer to the modify-header resource.
 459  * @param[in] action
 460  *   Pointer to action specification.
 461  * @param[out] error
 462  *   Pointer to the error structure.
 463  *
 464  * @return
 465  *   0 on success, a negative errno value otherwise and rte_errno is set.
 466  */
 467 static int
 468 flow_dv_convert_action_modify_ipv4
 469                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 470                          const struct rte_flow_action *action,
 471                          struct rte_flow_error *error)
 472 {
 473         const struct rte_flow_action_set_ipv4 *conf =
 474                 (const struct rte_flow_action_set_ipv4 *)(action->conf);
 475         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
 476         struct rte_flow_item_ipv4 ipv4;
 477         struct rte_flow_item_ipv4 ipv4_mask;
 478
 479         memset(&ipv4, 0, sizeof(ipv4));
 480         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 481         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC) {
 482                 ipv4.hdr.src_addr = conf->ipv4_addr;
 483                 ipv4_mask.hdr.src_addr = rte_flow_item_ipv4_mask.hdr.src_addr;
 484         } else {
 485                 ipv4.hdr.dst_addr = conf->ipv4_addr;
 486                 ipv4_mask.hdr.dst_addr = rte_flow_item_ipv4_mask.hdr.dst_addr;
 487         }
 488         item.spec = &ipv4;
 489         item.mask = &ipv4_mask;
 490         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
 491                                              MLX5_MODIFICATION_TYPE_SET, error);
 492 }
 493
 494 /**
 495  * Convert modify-header set IPv6 address action to DV specification.
 496  *
 497  * @param[in,out] resource
 498  *   Pointer to the modify-header resource.
 499  * @param[in] action
 500  *   Pointer to action specification.
 501  * @param[out] error
 502  *   Pointer to the error structure.
 503  *
 504  * @return
 505  *   0 on success, a negative errno value otherwise and rte_errno is set.
 506  */
 507 static int
 508 flow_dv_convert_action_modify_ipv6
 509                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 510                          const struct rte_flow_action *action,
 511                          struct rte_flow_error *error)
 512 {
 513         const struct rte_flow_action_set_ipv6 *conf =
 514                 (const struct rte_flow_action_set_ipv6 *)(action->conf);
 515         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
 516         struct rte_flow_item_ipv6 ipv6;
 517         struct rte_flow_item_ipv6 ipv6_mask;
 518
 519         memset(&ipv6, 0, sizeof(ipv6));
 520         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 521         if (action->type == RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC) {
 522                 memcpy(&ipv6.hdr.src_addr, &conf->ipv6_addr,
 523                        sizeof(ipv6.hdr.src_addr));
 524                 memcpy(&ipv6_mask.hdr.src_addr,
 525                        &rte_flow_item_ipv6_mask.hdr.src_addr,
 526                        sizeof(ipv6.hdr.src_addr));
 527         } else {
 528                 memcpy(&ipv6.hdr.dst_addr, &conf->ipv6_addr,
 529                        sizeof(ipv6.hdr.dst_addr));
 530                 memcpy(&ipv6_mask.hdr.dst_addr,
 531                        &rte_flow_item_ipv6_mask.hdr.dst_addr,
 532                        sizeof(ipv6.hdr.dst_addr));
 533         }
 534         item.spec = &ipv6;
 535         item.mask = &ipv6_mask;
 536         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
 537                                              MLX5_MODIFICATION_TYPE_SET, error);
 538 }
 539
 540 /**
 541  * Convert modify-header set MAC address action to DV specification.
 542  *
 543  * @param[in,out] resource
 544  *   Pointer to the modify-header resource.
 545  * @param[in] action
 546  *   Pointer to action specification.
 547  * @param[out] error
 548  *   Pointer to the error structure.
 549  *
 550  * @return
 551  *   0 on success, a negative errno value otherwise and rte_errno is set.
 552  */
 553 static int
 554 flow_dv_convert_action_modify_mac
 555                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 556                          const struct rte_flow_action *action,
 557                          struct rte_flow_error *error)
 558 {
 559         const struct rte_flow_action_set_mac *conf =
 560                 (const struct rte_flow_action_set_mac *)(action->conf);
 561         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_ETH };
 562         struct rte_flow_item_eth eth;
 563         struct rte_flow_item_eth eth_mask;
 564
 565         memset(&eth, 0, sizeof(eth));
 566         memset(&eth_mask, 0, sizeof(eth_mask));
 567         if (action->type == RTE_FLOW_ACTION_TYPE_SET_MAC_SRC) {
 568                 memcpy(&eth.src.addr_bytes, &conf->mac_addr,
 569                        sizeof(eth.src.addr_bytes));
 570                 memcpy(&eth_mask.src.addr_bytes,
 571                        &rte_flow_item_eth_mask.src.addr_bytes,
 572                        sizeof(eth_mask.src.addr_bytes));
 573         } else {
 574                 memcpy(&eth.dst.addr_bytes, &conf->mac_addr,
 575                        sizeof(eth.dst.addr_bytes));
 576                 memcpy(&eth_mask.dst.addr_bytes,
 577                        &rte_flow_item_eth_mask.dst.addr_bytes,
 578                        sizeof(eth_mask.dst.addr_bytes));
 579         }
 580         item.spec = &eth;
 581         item.mask = &eth_mask;
 582         return flow_dv_convert_modify_action(&item, modify_eth, NULL, resource,
 583                                              MLX5_MODIFICATION_TYPE_SET, error);
 584 }
 585
 586 /**
 587  * Convert modify-header set VLAN VID action to DV specification.
 588  *
 589  * @param[in,out] resource
 590  *   Pointer to the modify-header resource.
 591  * @param[in] action
 592  *   Pointer to action specification.
 593  * @param[out] error
 594  *   Pointer to the error structure.
 595  *
 596  * @return
 597  *   0 on success, a negative errno value otherwise and rte_errno is set.
 598  */
 599 static int
 600 flow_dv_convert_action_modify_vlan_vid
 601                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 602                          const struct rte_flow_action *action,
 603                          struct rte_flow_error *error)
 604 {
 605         const struct rte_flow_action_of_set_vlan_vid *conf =
 606                 (const struct rte_flow_action_of_set_vlan_vid *)(action->conf);
 607         int i = resource->actions_num;
 608         struct mlx5_modification_cmd *actions = resource->actions;
 609         struct field_modify_info *field = modify_vlan_out_first_vid;
 610
 611         if (i >= MLX5_MAX_MODIFY_NUM)
 612                 return rte_flow_error_set(error, EINVAL,
 613                          RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 614                          "too many items to modify");
 615         actions[i] = (struct mlx5_modification_cmd) {
 616                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 617                 .field = field->id,
 618                 .length = field->size,
 619                 .offset = field->offset,
 620         };
 621         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 622         actions[i].data1 = conf->vlan_vid;
 623         actions[i].data1 = actions[i].data1 << 16;
 624         resource->actions_num = ++i;
 625         return 0;
 626 }
 627
 628 /**
 629  * Convert modify-header set TP action to DV specification.
 630  *
 631  * @param[in,out] resource
 632  *   Pointer to the modify-header resource.
 633  * @param[in] action
 634  *   Pointer to action specification.
 635  * @param[in] items
 636  *   Pointer to rte_flow_item objects list.
 637  * @param[in] attr
 638  *   Pointer to flow attributes structure.
 639  * @param[in] dev_flow
 640  *   Pointer to the sub flow.
 641  * @param[in] tunnel_decap
 642  *   Whether action is after tunnel decapsulation.
 643  * @param[out] error
 644  *   Pointer to the error structure.
 645  *
 646  * @return
 647  *   0 on success, a negative errno value otherwise and rte_errno is set.
 648  */
 649 static int
 650 flow_dv_convert_action_modify_tp
 651                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 652                          const struct rte_flow_action *action,
 653                          const struct rte_flow_item *items,
 654                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 655                          bool tunnel_decap, struct rte_flow_error *error)
 656 {
 657         const struct rte_flow_action_set_tp *conf =
 658                 (const struct rte_flow_action_set_tp *)(action->conf);
 659         struct rte_flow_item item;
 660         struct rte_flow_item_udp udp;
 661         struct rte_flow_item_udp udp_mask;
 662         struct rte_flow_item_tcp tcp;
 663         struct rte_flow_item_tcp tcp_mask;
 664         struct field_modify_info *field;
 665
 666         if (!attr->valid)
 667                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 668         if (attr->udp) {
 669                 memset(&udp, 0, sizeof(udp));
 670                 memset(&udp_mask, 0, sizeof(udp_mask));
 671                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 672                         udp.hdr.src_port = conf->port;
 673                         udp_mask.hdr.src_port =
 674                                         rte_flow_item_udp_mask.hdr.src_port;
 675                 } else {
 676                         udp.hdr.dst_port = conf->port;
 677                         udp_mask.hdr.dst_port =
 678                                         rte_flow_item_udp_mask.hdr.dst_port;
 679                 }
 680                 item.type = RTE_FLOW_ITEM_TYPE_UDP;
 681                 item.spec = &udp;
 682                 item.mask = &udp_mask;
 683                 field = modify_udp;
 684         } else {
 685                 MLX5_ASSERT(attr->tcp);
 686                 memset(&tcp, 0, sizeof(tcp));
 687                 memset(&tcp_mask, 0, sizeof(tcp_mask));
 688                 if (action->type == RTE_FLOW_ACTION_TYPE_SET_TP_SRC) {
 689                         tcp.hdr.src_port = conf->port;
 690                         tcp_mask.hdr.src_port =
 691                                         rte_flow_item_tcp_mask.hdr.src_port;
 692                 } else {
 693                         tcp.hdr.dst_port = conf->port;
 694                         tcp_mask.hdr.dst_port =
 695                                         rte_flow_item_tcp_mask.hdr.dst_port;
 696                 }
 697                 item.type = RTE_FLOW_ITEM_TYPE_TCP;
 698                 item.spec = &tcp;
 699                 item.mask = &tcp_mask;
 700                 field = modify_tcp;
 701         }
 702         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 703                                              MLX5_MODIFICATION_TYPE_SET, error);
 704 }
 705
 706 /**
 707  * Convert modify-header set TTL action to DV specification.
 708  *
 709  * @param[in,out] resource
 710  *   Pointer to the modify-header resource.
 711  * @param[in] action
 712  *   Pointer to action specification.
 713  * @param[in] items
 714  *   Pointer to rte_flow_item objects list.
 715  * @param[in] attr
 716  *   Pointer to flow attributes structure.
 717  * @param[in] dev_flow
 718  *   Pointer to the sub flow.
 719  * @param[in] tunnel_decap
 720  *   Whether action is after tunnel decapsulation.
 721  * @param[out] error
 722  *   Pointer to the error structure.
 723  *
 724  * @return
 725  *   0 on success, a negative errno value otherwise and rte_errno is set.
 726  */
 727 static int
 728 flow_dv_convert_action_modify_ttl
 729                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 730                          const struct rte_flow_action *action,
 731                          const struct rte_flow_item *items,
 732                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 733                          bool tunnel_decap, struct rte_flow_error *error)
 734 {
 735         const struct rte_flow_action_set_ttl *conf =
 736                 (const struct rte_flow_action_set_ttl *)(action->conf);
 737         struct rte_flow_item item;
 738         struct rte_flow_item_ipv4 ipv4;
 739         struct rte_flow_item_ipv4 ipv4_mask;
 740         struct rte_flow_item_ipv6 ipv6;
 741         struct rte_flow_item_ipv6 ipv6_mask;
 742         struct field_modify_info *field;
 743
 744         if (!attr->valid)
 745                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 746         if (attr->ipv4) {
 747                 memset(&ipv4, 0, sizeof(ipv4));
 748                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 749                 ipv4.hdr.time_to_live = conf->ttl_value;
 750                 ipv4_mask.hdr.time_to_live = 0xFF;
 751                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 752                 item.spec = &ipv4;
 753                 item.mask = &ipv4_mask;
 754                 field = modify_ipv4;
 755         } else {
 756                 MLX5_ASSERT(attr->ipv6);
 757                 memset(&ipv6, 0, sizeof(ipv6));
 758                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 759                 ipv6.hdr.hop_limits = conf->ttl_value;
 760                 ipv6_mask.hdr.hop_limits = 0xFF;
 761                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 762                 item.spec = &ipv6;
 763                 item.mask = &ipv6_mask;
 764                 field = modify_ipv6;
 765         }
 766         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 767                                              MLX5_MODIFICATION_TYPE_SET, error);
 768 }
 769
 770 /**
 771  * Convert modify-header decrement TTL action to DV specification.
 772  *
 773  * @param[in,out] resource
 774  *   Pointer to the modify-header resource.
 775  * @param[in] action
 776  *   Pointer to action specification.
 777  * @param[in] items
 778  *   Pointer to rte_flow_item objects list.
 779  * @param[in] attr
 780  *   Pointer to flow attributes structure.
 781  * @param[in] dev_flow
 782  *   Pointer to the sub flow.
 783  * @param[in] tunnel_decap
 784  *   Whether action is after tunnel decapsulation.
 785  * @param[out] error
 786  *   Pointer to the error structure.
 787  *
 788  * @return
 789  *   0 on success, a negative errno value otherwise and rte_errno is set.
 790  */
 791 static int
 792 flow_dv_convert_action_modify_dec_ttl
 793                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 794                          const struct rte_flow_item *items,
 795                          union flow_dv_attr *attr, struct mlx5_flow *dev_flow,
 796                          bool tunnel_decap, struct rte_flow_error *error)
 797 {
 798         struct rte_flow_item item;
 799         struct rte_flow_item_ipv4 ipv4;
 800         struct rte_flow_item_ipv4 ipv4_mask;
 801         struct rte_flow_item_ipv6 ipv6;
 802         struct rte_flow_item_ipv6 ipv6_mask;
 803         struct field_modify_info *field;
 804
 805         if (!attr->valid)
 806                 flow_dv_attr_init(items, attr, dev_flow, tunnel_decap);
 807         if (attr->ipv4) {
 808                 memset(&ipv4, 0, sizeof(ipv4));
 809                 memset(&ipv4_mask, 0, sizeof(ipv4_mask));
 810                 ipv4.hdr.time_to_live = 0xFF;
 811                 ipv4_mask.hdr.time_to_live = 0xFF;
 812                 item.type = RTE_FLOW_ITEM_TYPE_IPV4;
 813                 item.spec = &ipv4;
 814                 item.mask = &ipv4_mask;
 815                 field = modify_ipv4;
 816         } else {
 817                 MLX5_ASSERT(attr->ipv6);
 818                 memset(&ipv6, 0, sizeof(ipv6));
 819                 memset(&ipv6_mask, 0, sizeof(ipv6_mask));
 820                 ipv6.hdr.hop_limits = 0xFF;
 821                 ipv6_mask.hdr.hop_limits = 0xFF;
 822                 item.type = RTE_FLOW_ITEM_TYPE_IPV6;
 823                 item.spec = &ipv6;
 824                 item.mask = &ipv6_mask;
 825                 field = modify_ipv6;
 826         }
 827         return flow_dv_convert_modify_action(&item, field, NULL, resource,
 828                                              MLX5_MODIFICATION_TYPE_ADD, error);
 829 }
 830
 831 /**
 832  * Convert modify-header increment/decrement TCP Sequence number
 833  * to DV specification.
 834  *
 835  * @param[in,out] resource
 836  *   Pointer to the modify-header resource.
 837  * @param[in] action
 838  *   Pointer to action specification.
 839  * @param[out] error
 840  *   Pointer to the error structure.
 841  *
 842  * @return
 843  *   0 on success, a negative errno value otherwise and rte_errno is set.
 844  */
 845 static int
 846 flow_dv_convert_action_modify_tcp_seq
 847                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 848                          const struct rte_flow_action *action,
 849                          struct rte_flow_error *error)
 850 {
 851         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 852         uint64_t value = rte_be_to_cpu_32(*conf);
 853         struct rte_flow_item item;
 854         struct rte_flow_item_tcp tcp;
 855         struct rte_flow_item_tcp tcp_mask;
 856
 857         memset(&tcp, 0, sizeof(tcp));
 858         memset(&tcp_mask, 0, sizeof(tcp_mask));
 859         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ)
 860                 /*
 861                  * The HW has no decrement operation, only increment operation.
 862                  * To simulate decrement X from Y using increment operation
 863                  * we need to add UINT32_MAX X times to Y.
 864                  * Each adding of UINT32_MAX decrements Y by 1.
 865                  */
 866                 value *= UINT32_MAX;
 867         tcp.hdr.sent_seq = rte_cpu_to_be_32((uint32_t)value);
 868         tcp_mask.hdr.sent_seq = RTE_BE32(UINT32_MAX);
 869         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 870         item.spec = &tcp;
 871         item.mask = &tcp_mask;
 872         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 873                                              MLX5_MODIFICATION_TYPE_ADD, error);
 874 }
 875
 876 /**
 877  * Convert modify-header increment/decrement TCP Acknowledgment number
 878  * to DV specification.
 879  *
 880  * @param[in,out] resource
 881  *   Pointer to the modify-header resource.
 882  * @param[in] action
 883  *   Pointer to action specification.
 884  * @param[out] error
 885  *   Pointer to the error structure.
 886  *
 887  * @return
 888  *   0 on success, a negative errno value otherwise and rte_errno is set.
 889  */
 890 static int
 891 flow_dv_convert_action_modify_tcp_ack
 892                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 893                          const struct rte_flow_action *action,
 894                          struct rte_flow_error *error)
 895 {
 896         const rte_be32_t *conf = (const rte_be32_t *)(action->conf);
 897         uint64_t value = rte_be_to_cpu_32(*conf);
 898         struct rte_flow_item item;
 899         struct rte_flow_item_tcp tcp;
 900         struct rte_flow_item_tcp tcp_mask;
 901
 902         memset(&tcp, 0, sizeof(tcp));
 903         memset(&tcp_mask, 0, sizeof(tcp_mask));
 904         if (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK)
 905                 /*
 906                  * The HW has no decrement operation, only increment operation.
 907                  * To simulate decrement X from Y using increment operation
 908                  * we need to add UINT32_MAX X times to Y.
 909                  * Each adding of UINT32_MAX decrements Y by 1.
 910                  */
 911                 value *= UINT32_MAX;
 912         tcp.hdr.recv_ack = rte_cpu_to_be_32((uint32_t)value);
 913         tcp_mask.hdr.recv_ack = RTE_BE32(UINT32_MAX);
 914         item.type = RTE_FLOW_ITEM_TYPE_TCP;
 915         item.spec = &tcp;
 916         item.mask = &tcp_mask;
 917         return flow_dv_convert_modify_action(&item, modify_tcp, NULL, resource,
 918                                              MLX5_MODIFICATION_TYPE_ADD, error);
 919 }
 920
 921 static enum mlx5_modification_field reg_to_field[] = {
 922         [REG_NON] = MLX5_MODI_OUT_NONE,
 923         [REG_A] = MLX5_MODI_META_DATA_REG_A,
 924         [REG_B] = MLX5_MODI_META_DATA_REG_B,
 925         [REG_C_0] = MLX5_MODI_META_REG_C_0,
 926         [REG_C_1] = MLX5_MODI_META_REG_C_1,
 927         [REG_C_2] = MLX5_MODI_META_REG_C_2,
 928         [REG_C_3] = MLX5_MODI_META_REG_C_3,
 929         [REG_C_4] = MLX5_MODI_META_REG_C_4,
 930         [REG_C_5] = MLX5_MODI_META_REG_C_5,
 931         [REG_C_6] = MLX5_MODI_META_REG_C_6,
 932         [REG_C_7] = MLX5_MODI_META_REG_C_7,
 933 };
 934
 935 /**
 936  * Convert register set to DV specification.
 937  *
 938  * @param[in,out] resource
 939  *   Pointer to the modify-header resource.
 940  * @param[in] action
 941  *   Pointer to action specification.
 942  * @param[out] error
 943  *   Pointer to the error structure.
 944  *
 945  * @return
 946  *   0 on success, a negative errno value otherwise and rte_errno is set.
 947  */
 948 static int
 949 flow_dv_convert_action_set_reg
 950                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
 951                          const struct rte_flow_action *action,
 952                          struct rte_flow_error *error)
 953 {
 954         const struct mlx5_rte_flow_action_set_tag *conf = action->conf;
 955         struct mlx5_modification_cmd *actions = resource->actions;
 956         uint32_t i = resource->actions_num;
 957
 958         if (i >= MLX5_MAX_MODIFY_NUM)
 959                 return rte_flow_error_set(error, EINVAL,
 960                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
 961                                           "too many items to modify");
 962         MLX5_ASSERT(conf->id != REG_NON);
 963         MLX5_ASSERT(conf->id < (enum modify_reg)RTE_DIM(reg_to_field));
 964         actions[i] = (struct mlx5_modification_cmd) {
 965                 .action_type = MLX5_MODIFICATION_TYPE_SET,
 966                 .field = reg_to_field[conf->id],
 967         };
 968         actions[i].data0 = rte_cpu_to_be_32(actions[i].data0);
 969         actions[i].data1 = rte_cpu_to_be_32(conf->data);
 970         ++i;
 971         resource->actions_num = i;
 972         return 0;
 973 }
 974
 975 /**
 976  * Convert SET_TAG action to DV specification.
 977  *
 978  * @param[in] dev
 979  *   Pointer to the rte_eth_dev structure.
 980  * @param[in,out] resource
 981  *   Pointer to the modify-header resource.
 982  * @param[in] conf
 983  *   Pointer to action specification.
 984  * @param[out] error
 985  *   Pointer to the error structure.
 986  *
 987  * @return
 988  *   0 on success, a negative errno value otherwise and rte_errno is set.
 989  */
 990 static int
 991 flow_dv_convert_action_set_tag
 992                         (struct rte_eth_dev *dev,
 993                          struct mlx5_flow_dv_modify_hdr_resource *resource,
 994                          const struct rte_flow_action_set_tag *conf,
 995                          struct rte_flow_error *error)
 996 {
 997         rte_be32_t data = rte_cpu_to_be_32(conf->data);
 998         rte_be32_t mask = rte_cpu_to_be_32(conf->mask);
 999         struct rte_flow_item item = {
1000                 .spec = &data,
1001                 .mask = &mask,
1002         };
1003         struct field_modify_info reg_c_x[] = {
1004                 [1] = {0, 0, 0},
1005         };
1006         enum mlx5_modification_field reg_type;
1007         int ret;
1008
1009         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
1010         if (ret < 0)
1011                 return ret;
1012         MLX5_ASSERT(ret != REG_NON);
1013         MLX5_ASSERT((unsigned int)ret < RTE_DIM(reg_to_field));
1014         reg_type = reg_to_field[ret];
1015         MLX5_ASSERT(reg_type > 0);
1016         reg_c_x[0] = (struct field_modify_info){4, 0, reg_type};
1017         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1018                                              MLX5_MODIFICATION_TYPE_SET, error);
1019 }
1020
1021 /**
1022  * Convert internal COPY_REG action to DV specification.
1023  *
1024  * @param[in] dev
1025  *   Pointer to the rte_eth_dev structure.
1026  * @param[in,out] res
1027  *   Pointer to the modify-header resource.
1028  * @param[in] action
1029  *   Pointer to action specification.
1030  * @param[out] error
1031  *   Pointer to the error structure.
1032  *
1033  * @return
1034  *   0 on success, a negative errno value otherwise and rte_errno is set.
1035  */
1036 static int
1037 flow_dv_convert_action_copy_mreg(struct rte_eth_dev *dev,
1038                                  struct mlx5_flow_dv_modify_hdr_resource *res,
1039                                  const struct rte_flow_action *action,
1040                                  struct rte_flow_error *error)
1041 {
1042         const struct mlx5_flow_action_copy_mreg *conf = action->conf;
1043         rte_be32_t mask = RTE_BE32(UINT32_MAX);
1044         struct rte_flow_item item = {
1045                 .spec = NULL,
1046                 .mask = &mask,
1047         };
1048         struct field_modify_info reg_src[] = {
1049                 {4, 0, reg_to_field[conf->src]},
1050                 {0, 0, 0},
1051         };
1052         struct field_modify_info reg_dst = {
1053                 .offset = 0,
1054                 .id = reg_to_field[conf->dst],
1055         };
1056         /* Adjust reg_c[0] usage according to reported mask. */
1057         if (conf->dst == REG_C_0 || conf->src == REG_C_0) {
1058                 struct mlx5_priv *priv = dev->data->dev_private;
1059                 uint32_t reg_c0 = priv->sh->dv_regc0_mask;
1060
1061                 MLX5_ASSERT(reg_c0);
1062                 MLX5_ASSERT(priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY);
1063                 if (conf->dst == REG_C_0) {
1064                         /* Copy to reg_c[0], within mask only. */
1065                         reg_dst.offset = rte_bsf32(reg_c0);
1066                         /*
1067                          * Mask is ignoring the enianness, because
1068                          * there is no conversion in datapath.
1069                          */
1070 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1071                         /* Copy from destination lower bits to reg_c[0]. */
1072                         mask = reg_c0 >> reg_dst.offset;
1073 #else
1074                         /* Copy from destination upper bits to reg_c[0]. */
1075                         mask = reg_c0 << (sizeof(reg_c0) * CHAR_BIT -
1076                                           rte_fls_u32(reg_c0));
1077 #endif
1078                 } else {
1079                         mask = rte_cpu_to_be_32(reg_c0);
1080 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1081                         /* Copy from reg_c[0] to destination lower bits. */
1082                         reg_dst.offset = 0;
1083 #else
1084                         /* Copy from reg_c[0] to destination upper bits. */
1085                         reg_dst.offset = sizeof(reg_c0) * CHAR_BIT -
1086                                          (rte_fls_u32(reg_c0) -
1087                                           rte_bsf32(reg_c0));
1088 #endif
1089                 }
1090         }
1091         return flow_dv_convert_modify_action(&item,
1092                                              reg_src, &reg_dst, res,
1093                                              MLX5_MODIFICATION_TYPE_COPY,
1094                                              error);
1095 }
1096
1097 /**
1098  * Convert MARK action to DV specification. This routine is used
1099  * in extensive metadata only and requires metadata register to be
1100  * handled. In legacy mode hardware tag resource is engaged.
1101  *
1102  * @param[in] dev
1103  *   Pointer to the rte_eth_dev structure.
1104  * @param[in] conf
1105  *   Pointer to MARK action specification.
1106  * @param[in,out] resource
1107  *   Pointer to the modify-header resource.
1108  * @param[out] error
1109  *   Pointer to the error structure.
1110  *
1111  * @return
1112  *   0 on success, a negative errno value otherwise and rte_errno is set.
1113  */
1114 static int
1115 flow_dv_convert_action_mark(struct rte_eth_dev *dev,
1116                             const struct rte_flow_action_mark *conf,
1117                             struct mlx5_flow_dv_modify_hdr_resource *resource,
1118                             struct rte_flow_error *error)
1119 {
1120         struct mlx5_priv *priv = dev->data->dev_private;
1121         rte_be32_t mask = rte_cpu_to_be_32(MLX5_FLOW_MARK_MASK &
1122                                            priv->sh->dv_mark_mask);
1123         rte_be32_t data = rte_cpu_to_be_32(conf->id) & mask;
1124         struct rte_flow_item item = {
1125                 .spec = &data,
1126                 .mask = &mask,
1127         };
1128         struct field_modify_info reg_c_x[] = {
1129                 [1] = {0, 0, 0},
1130         };
1131         int reg;
1132
1133         if (!mask)
1134                 return rte_flow_error_set(error, EINVAL,
1135                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1136                                           NULL, "zero mark action mask");
1137         reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1138         if (reg < 0)
1139                 return reg;
1140         MLX5_ASSERT(reg > 0);
1141         if (reg == REG_C_0) {
1142                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1143                 uint32_t shl_c0 = rte_bsf32(msk_c0);
1144
1145                 data = rte_cpu_to_be_32(rte_cpu_to_be_32(data) << shl_c0);
1146                 mask = rte_cpu_to_be_32(mask) & msk_c0;
1147                 mask = rte_cpu_to_be_32(mask << shl_c0);
1148         }
1149         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1150         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1151                                              MLX5_MODIFICATION_TYPE_SET, error);
1152 }
1153
1154 /**
1155  * Get metadata register index for specified steering domain.
1156  *
1157  * @param[in] dev
1158  *   Pointer to the rte_eth_dev structure.
1159  * @param[in] attr
1160  *   Attributes of flow to determine steering domain.
1161  * @param[out] error
1162  *   Pointer to the error structure.
1163  *
1164  * @return
1165  *   positive index on success, a negative errno value otherwise
1166  *   and rte_errno is set.
1167  */
1168 static enum modify_reg
1169 flow_dv_get_metadata_reg(struct rte_eth_dev *dev,
1170                          const struct rte_flow_attr *attr,
1171                          struct rte_flow_error *error)
1172 {
1173         int reg =
1174                 mlx5_flow_get_reg_id(dev, attr->transfer ?
1175                                           MLX5_METADATA_FDB :
1176                                             attr->egress ?
1177                                             MLX5_METADATA_TX :
1178                                             MLX5_METADATA_RX, 0, error);
1179         if (reg < 0)
1180                 return rte_flow_error_set(error,
1181                                           ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM,
1182                                           NULL, "unavailable "
1183                                           "metadata register");
1184         return reg;
1185 }
1186
1187 /**
1188  * Convert SET_META action to DV specification.
1189  *
1190  * @param[in] dev
1191  *   Pointer to the rte_eth_dev structure.
1192  * @param[in,out] resource
1193  *   Pointer to the modify-header resource.
1194  * @param[in] attr
1195  *   Attributes of flow that includes this item.
1196  * @param[in] conf
1197  *   Pointer to action specification.
1198  * @param[out] error
1199  *   Pointer to the error structure.
1200  *
1201  * @return
1202  *   0 on success, a negative errno value otherwise and rte_errno is set.
1203  */
1204 static int
1205 flow_dv_convert_action_set_meta
1206                         (struct rte_eth_dev *dev,
1207                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1208                          const struct rte_flow_attr *attr,
1209                          const struct rte_flow_action_set_meta *conf,
1210                          struct rte_flow_error *error)
1211 {
1212         uint32_t data = conf->data;
1213         uint32_t mask = conf->mask;
1214         struct rte_flow_item item = {
1215                 .spec = &data,
1216                 .mask = &mask,
1217         };
1218         struct field_modify_info reg_c_x[] = {
1219                 [1] = {0, 0, 0},
1220         };
1221         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1222
1223         if (reg < 0)
1224                 return reg;
1225         MLX5_ASSERT(reg != REG_NON);
1226         /*
1227          * In datapath code there is no endianness
1228          * coversions for perfromance reasons, all
1229          * pattern conversions are done in rte_flow.
1230          */
1231         if (reg == REG_C_0) {
1232                 struct mlx5_priv *priv = dev->data->dev_private;
1233                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
1234                 uint32_t shl_c0;
1235
1236                 MLX5_ASSERT(msk_c0);
1237 #if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
1238                 shl_c0 = rte_bsf32(msk_c0);
1239 #else
1240                 shl_c0 = sizeof(msk_c0) * CHAR_BIT - rte_fls_u32(msk_c0);
1241 #endif
1242                 mask <<= shl_c0;
1243                 data <<= shl_c0;
1244                 MLX5_ASSERT(!(~msk_c0 & rte_cpu_to_be_32(mask)));
1245         }
1246         reg_c_x[0] = (struct field_modify_info){4, 0, reg_to_field[reg]};
1247         /* The routine expects parameters in memory as big-endian ones. */
1248         return flow_dv_convert_modify_action(&item, reg_c_x, NULL, resource,
1249                                              MLX5_MODIFICATION_TYPE_SET, error);
1250 }
1251
1252 /**
1253  * Convert modify-header set IPv4 DSCP action to DV specification.
1254  *
1255  * @param[in,out] resource
1256  *   Pointer to the modify-header resource.
1257  * @param[in] action
1258  *   Pointer to action specification.
1259  * @param[out] error
1260  *   Pointer to the error structure.
1261  *
1262  * @return
1263  *   0 on success, a negative errno value otherwise and rte_errno is set.
1264  */
1265 static int
1266 flow_dv_convert_action_modify_ipv4_dscp
1267                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1268                          const struct rte_flow_action *action,
1269                          struct rte_flow_error *error)
1270 {
1271         const struct rte_flow_action_set_dscp *conf =
1272                 (const struct rte_flow_action_set_dscp *)(action->conf);
1273         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV4 };
1274         struct rte_flow_item_ipv4 ipv4;
1275         struct rte_flow_item_ipv4 ipv4_mask;
1276
1277         memset(&ipv4, 0, sizeof(ipv4));
1278         memset(&ipv4_mask, 0, sizeof(ipv4_mask));
1279         ipv4.hdr.type_of_service = conf->dscp;
1280         ipv4_mask.hdr.type_of_service = RTE_IPV4_HDR_DSCP_MASK >> 2;
1281         item.spec = &ipv4;
1282         item.mask = &ipv4_mask;
1283         return flow_dv_convert_modify_action(&item, modify_ipv4, NULL, resource,
1284                                              MLX5_MODIFICATION_TYPE_SET, error);
1285 }
1286
1287 /**
1288  * Convert modify-header set IPv6 DSCP action to DV specification.
1289  *
1290  * @param[in,out] resource
1291  *   Pointer to the modify-header resource.
1292  * @param[in] action
1293  *   Pointer to action specification.
1294  * @param[out] error
1295  *   Pointer to the error structure.
1296  *
1297  * @return
1298  *   0 on success, a negative errno value otherwise and rte_errno is set.
1299  */
1300 static int
1301 flow_dv_convert_action_modify_ipv6_dscp
1302                         (struct mlx5_flow_dv_modify_hdr_resource *resource,
1303                          const struct rte_flow_action *action,
1304                          struct rte_flow_error *error)
1305 {
1306         const struct rte_flow_action_set_dscp *conf =
1307                 (const struct rte_flow_action_set_dscp *)(action->conf);
1308         struct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };
1309         struct rte_flow_item_ipv6 ipv6;
1310         struct rte_flow_item_ipv6 ipv6_mask;
1311
1312         memset(&ipv6, 0, sizeof(ipv6));
1313         memset(&ipv6_mask, 0, sizeof(ipv6_mask));
1314         /*
1315          * Even though the DSCP bits offset of IPv6 is not byte aligned,
1316          * rdma-core only accept the DSCP bits byte aligned start from
1317          * bit 0 to 5 as to be compatible with IPv4. No need to shift the
1318          * bits in IPv6 case as rdma-core requires byte aligned value.
1319          */
1320         ipv6.hdr.vtc_flow = conf->dscp;
1321         ipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;
1322         item.spec = &ipv6;
1323         item.mask = &ipv6_mask;
1324         return flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,
1325                                              MLX5_MODIFICATION_TYPE_SET, error);
1326 }
1327
1328 static void
1329 mlx5_flow_field_id_to_modify_info
1330                 (const struct rte_flow_action_modify_data *data,
1331                  struct field_modify_info *info,
1332                  uint32_t *mask, uint32_t *value, uint32_t width,
1333                  struct rte_eth_dev *dev,
1334                  const struct rte_flow_attr *attr,
1335                  struct rte_flow_error *error)
1336 {
1337         uint32_t idx = 0;
1338         switch (data->field) {
1339         case RTE_FLOW_FIELD_START:
1340                 /* not supported yet */
1341                 MLX5_ASSERT(false);
1342                 break;
1343         case RTE_FLOW_FIELD_MAC_DST:
1344                 if (mask) {
1345                         if (data->offset < 32) {
1346                                 info[idx] = (struct field_modify_info){4, 0,
1347                                                 MLX5_MODI_OUT_DMAC_47_16};
1348                                 if (width < 32) {
1349                                         mask[idx] =
1350                                                 rte_cpu_to_be_32(0xffffffff >>
1351                                                                  (32 - width));
1352                                         width = 0;
1353                                 } else {
1354                                         mask[idx] = RTE_BE32(0xffffffff);
1355                                         width -= 32;
1356                                 }
1357                                 if (!width)
1358                                         break;
1359                                 ++idx;
1360                         }
1361                         info[idx] = (struct field_modify_info){2, 4 * idx,
1362                                                 MLX5_MODI_OUT_DMAC_15_0};
1363                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1364                                                      (16 - width));
1365                 } else {
1366                         if (data->offset < 32)
1367                                 info[idx++] = (struct field_modify_info){4, 0,
1368                                                 MLX5_MODI_OUT_DMAC_47_16};
1369                         info[idx] = (struct field_modify_info){2, 0,
1370                                                 MLX5_MODI_OUT_DMAC_15_0};
1371                 }
1372                 break;
1373         case RTE_FLOW_FIELD_MAC_SRC:
1374                 if (mask) {
1375                         if (data->offset < 32) {
1376                                 info[idx] = (struct field_modify_info){4, 0,
1377                                                 MLX5_MODI_OUT_SMAC_47_16};
1378                                 if (width < 32) {
1379                                         mask[idx] =
1380                                                 rte_cpu_to_be_32(0xffffffff >>
1381                                                                 (32 - width));
1382                                         width = 0;
1383                                 } else {
1384                                         mask[idx] = RTE_BE32(0xffffffff);
1385                                         width -= 32;
1386                                 }
1387                                 if (!width)
1388                                         break;
1389                                 ++idx;
1390                         }
1391                         info[idx] = (struct field_modify_info){2, 4 * idx,
1392                                                 MLX5_MODI_OUT_SMAC_15_0};
1393                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1394                                                      (16 - width));
1395                 } else {
1396                         if (data->offset < 32)
1397                                 info[idx++] = (struct field_modify_info){4, 0,
1398                                                 MLX5_MODI_OUT_SMAC_47_16};
1399                         info[idx] = (struct field_modify_info){2, 0,
1400                                                 MLX5_MODI_OUT_SMAC_15_0};
1401                 }
1402                 break;
1403         case RTE_FLOW_FIELD_VLAN_TYPE:
1404                 /* not supported yet */
1405                 break;
1406         case RTE_FLOW_FIELD_VLAN_ID:
1407                 info[idx] = (struct field_modify_info){2, 0,
1408                                         MLX5_MODI_OUT_FIRST_VID};
1409                 if (mask)
1410                         mask[idx] = rte_cpu_to_be_32(0x00000fff >>
1411                                                      (12 - width));
1412                 break;
1413         case RTE_FLOW_FIELD_MAC_TYPE:
1414                 info[idx] = (struct field_modify_info){2, 0,
1415                                         MLX5_MODI_OUT_ETHERTYPE};
1416                 if (mask)
1417                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1418                                                      (16 - width));
1419                 break;
1420         case RTE_FLOW_FIELD_IPV4_DSCP:
1421                 info[idx] = (struct field_modify_info){1, 0,
1422                                         MLX5_MODI_OUT_IP_DSCP};
1423                 if (mask)
1424                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1425                                                      (6 - width));
1426                 break;
1427         case RTE_FLOW_FIELD_IPV4_TTL:
1428                 info[idx] = (struct field_modify_info){1, 0,
1429                                         MLX5_MODI_OUT_IPV4_TTL};
1430                 if (mask)
1431                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1432                                                      (8 - width));
1433                 break;
1434         case RTE_FLOW_FIELD_IPV4_SRC:
1435                 info[idx] = (struct field_modify_info){4, 0,
1436                                         MLX5_MODI_OUT_SIPV4};
1437                 if (mask)
1438                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1439                                                      (32 - width));
1440                 break;
1441         case RTE_FLOW_FIELD_IPV4_DST:
1442                 info[idx] = (struct field_modify_info){4, 0,
1443                                         MLX5_MODI_OUT_DIPV4};
1444                 if (mask)
1445                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1446                                                      (32 - width));
1447                 break;
1448         case RTE_FLOW_FIELD_IPV6_DSCP:
1449                 info[idx] = (struct field_modify_info){1, 0,
1450                                         MLX5_MODI_OUT_IP_DSCP};
1451                 if (mask)
1452                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1453                                                      (6 - width));
1454                 break;
1455         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
1456                 info[idx] = (struct field_modify_info){1, 0,
1457                                         MLX5_MODI_OUT_IPV6_HOPLIMIT};
1458                 if (mask)
1459                         mask[idx] = rte_cpu_to_be_32(0x000000ff >>
1460                                                      (8 - width));
1461                 break;
1462         case RTE_FLOW_FIELD_IPV6_SRC:
1463                 if (mask) {
1464                         if (data->offset < 32) {
1465                                 info[idx] = (struct field_modify_info){4, 0,
1466                                                 MLX5_MODI_OUT_SIPV6_127_96};
1467                                 if (width < 32) {
1468                                         mask[idx] =
1469                                                 rte_cpu_to_be_32(0xffffffff >>
1470                                                                  (32 - width));
1471                                         width = 0;
1472                                 } else {
1473                                         mask[idx] = RTE_BE32(0xffffffff);
1474                                         width -= 32;
1475                                 }
1476                                 if (!width)
1477                                         break;
1478                                 ++idx;
1479                         }
1480                         if (data->offset < 64) {
1481                                 info[idx] = (struct field_modify_info){4,
1482                                                 4 * idx,
1483                                                 MLX5_MODI_OUT_SIPV6_95_64};
1484                                 if (width < 32) {
1485                                         mask[idx] =
1486                                                 rte_cpu_to_be_32(0xffffffff >>
1487                                                                  (32 - width));
1488                                         width = 0;
1489                                 } else {
1490                                         mask[idx] = RTE_BE32(0xffffffff);
1491                                         width -= 32;
1492                                 }
1493                                 if (!width)
1494                                         break;
1495                                 ++idx;
1496                         }
1497                         if (data->offset < 96) {
1498                                 info[idx] = (struct field_modify_info){4,
1499                                                 8 * idx,
1500                                                 MLX5_MODI_OUT_SIPV6_63_32};
1501                                 if (width < 32) {
1502                                         mask[idx] =
1503                                                 rte_cpu_to_be_32(0xffffffff >>
1504                                                                  (32 - width));
1505                                         width = 0;
1506                                 } else {
1507                                         mask[idx] = RTE_BE32(0xffffffff);
1508                                         width -= 32;
1509                                 }
1510                                 if (!width)
1511                                         break;
1512                                 ++idx;
1513                         }
1514                         info[idx] = (struct field_modify_info){4, 12 * idx,
1515                                                 MLX5_MODI_OUT_SIPV6_31_0};
1516                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1517                                                      (32 - width));
1518                 } else {
1519                         if (data->offset < 32)
1520                                 info[idx++] = (struct field_modify_info){4, 0,
1521                                                 MLX5_MODI_OUT_SIPV6_127_96};
1522                         if (data->offset < 64)
1523                                 info[idx++] = (struct field_modify_info){4, 0,
1524                                                 MLX5_MODI_OUT_SIPV6_95_64};
1525                         if (data->offset < 96)
1526                                 info[idx++] = (struct field_modify_info){4, 0,
1527                                                 MLX5_MODI_OUT_SIPV6_63_32};
1528                         if (data->offset < 128)
1529                                 info[idx++] = (struct field_modify_info){4, 0,
1530                                                 MLX5_MODI_OUT_SIPV6_31_0};
1531                 }
1532                 break;
1533         case RTE_FLOW_FIELD_IPV6_DST:
1534                 if (mask) {
1535                         if (data->offset < 32) {
1536                                 info[idx] = (struct field_modify_info){4, 0,
1537                                                 MLX5_MODI_OUT_DIPV6_127_96};
1538                                 if (width < 32) {
1539                                         mask[idx] =
1540                                                 rte_cpu_to_be_32(0xffffffff >>
1541                                                                  (32 - width));
1542                                         width = 0;
1543                                 } else {
1544                                         mask[idx] = RTE_BE32(0xffffffff);
1545                                         width -= 32;
1546                                 }
1547                                 if (!width)
1548                                         break;
1549                                 ++idx;
1550                         }
1551                         if (data->offset < 64) {
1552                                 info[idx] = (struct field_modify_info){4,
1553                                                 4 * idx,
1554                                                 MLX5_MODI_OUT_DIPV6_95_64};
1555                                 if (width < 32) {
1556                                         mask[idx] =
1557                                                 rte_cpu_to_be_32(0xffffffff >>
1558                                                                  (32 - width));
1559                                         width = 0;
1560                                 } else {
1561                                         mask[idx] = RTE_BE32(0xffffffff);
1562                                         width -= 32;
1563                                 }
1564                                 if (!width)
1565                                         break;
1566                                 ++idx;
1567                         }
1568                         if (data->offset < 96) {
1569                                 info[idx] = (struct field_modify_info){4,
1570                                                 8 * idx,
1571                                                 MLX5_MODI_OUT_DIPV6_63_32};
1572                                 if (width < 32) {
1573                                         mask[idx] =
1574                                                 rte_cpu_to_be_32(0xffffffff >>
1575                                                                  (32 - width));
1576                                         width = 0;
1577                                 } else {
1578                                         mask[idx] = RTE_BE32(0xffffffff);
1579                                         width -= 32;
1580                                 }
1581                                 if (!width)
1582                                         break;
1583                                 ++idx;
1584                         }
1585                         info[idx] = (struct field_modify_info){4, 12 * idx,
1586                                                 MLX5_MODI_OUT_DIPV6_31_0};
1587                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1588                                                      (32 - width));
1589                 } else {
1590                         if (data->offset < 32)
1591                                 info[idx++] = (struct field_modify_info){4, 0,
1592                                                 MLX5_MODI_OUT_DIPV6_127_96};
1593                         if (data->offset < 64)
1594                                 info[idx++] = (struct field_modify_info){4, 0,
1595                                                 MLX5_MODI_OUT_DIPV6_95_64};
1596                         if (data->offset < 96)
1597                                 info[idx++] = (struct field_modify_info){4, 0,
1598                                                 MLX5_MODI_OUT_DIPV6_63_32};
1599                         if (data->offset < 128)
1600                                 info[idx++] = (struct field_modify_info){4, 0,
1601                                                 MLX5_MODI_OUT_DIPV6_31_0};
1602                 }
1603                 break;
1604         case RTE_FLOW_FIELD_TCP_PORT_SRC:
1605                 info[idx] = (struct field_modify_info){2, 0,
1606                                         MLX5_MODI_OUT_TCP_SPORT};
1607                 if (mask)
1608                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1609                                                      (16 - width));
1610                 break;
1611         case RTE_FLOW_FIELD_TCP_PORT_DST:
1612                 info[idx] = (struct field_modify_info){2, 0,
1613                                         MLX5_MODI_OUT_TCP_DPORT};
1614                 if (mask)
1615                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1616                                                      (16 - width));
1617                 break;
1618         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
1619                 info[idx] = (struct field_modify_info){4, 0,
1620                                         MLX5_MODI_OUT_TCP_SEQ_NUM};
1621                 if (mask)
1622                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1623                                                      (32 - width));
1624                 break;
1625         case RTE_FLOW_FIELD_TCP_ACK_NUM:
1626                 info[idx] = (struct field_modify_info){4, 0,
1627                                         MLX5_MODI_OUT_TCP_ACK_NUM};
1628                 if (mask)
1629                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1630                                                      (32 - width));
1631                 break;
1632         case RTE_FLOW_FIELD_TCP_FLAGS:
1633                 info[idx] = (struct field_modify_info){1, 0,
1634                                         MLX5_MODI_OUT_TCP_FLAGS};
1635                 if (mask)
1636                         mask[idx] = rte_cpu_to_be_32(0x0000003f >>
1637                                                      (6 - width));
1638                 break;
1639         case RTE_FLOW_FIELD_UDP_PORT_SRC:
1640                 info[idx] = (struct field_modify_info){2, 0,
1641                                         MLX5_MODI_OUT_UDP_SPORT};
1642                 if (mask)
1643                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1644                                                      (16 - width));
1645                 break;
1646         case RTE_FLOW_FIELD_UDP_PORT_DST:
1647                 info[idx] = (struct field_modify_info){2, 0,
1648                                         MLX5_MODI_OUT_UDP_DPORT};
1649                 if (mask)
1650                         mask[idx] = rte_cpu_to_be_32(0x0000ffff >>
1651                                                      (16 - width));
1652                 break;
1653         case RTE_FLOW_FIELD_VXLAN_VNI:
1654                 /* not supported yet */
1655                 break;
1656         case RTE_FLOW_FIELD_GENEVE_VNI:
1657                 /* not supported yet*/
1658                 break;
1659         case RTE_FLOW_FIELD_GTP_TEID:
1660                 info[idx] = (struct field_modify_info){4, 0,
1661                                         MLX5_MODI_GTP_TEID};
1662                 if (mask)
1663                         mask[idx] = rte_cpu_to_be_32(0xffffffff >>
1664                                                      (32 - width));
1665                 break;
1666         case RTE_FLOW_FIELD_TAG:
1667                 {
1668                         int reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG,
1669                                                    data->level, error);
1670                         if (reg < 0)
1671                                 return;
1672                         MLX5_ASSERT(reg != REG_NON);
1673                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1674                         info[idx] = (struct field_modify_info){4, 0,
1675                                                 reg_to_field[reg]};
1676                         if (mask)
1677                                 mask[idx] =
1678                                         rte_cpu_to_be_32(0xffffffff >>
1679                                                          (32 - width));
1680                 }
1681                 break;
1682         case RTE_FLOW_FIELD_MARK:
1683                 {
1684                         int reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK,
1685                                                        0, error);
1686                         if (reg < 0)
1687                                 return;
1688                         MLX5_ASSERT(reg != REG_NON);
1689                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1690                         info[idx] = (struct field_modify_info){4, 0,
1691                                                 reg_to_field[reg]};
1692                         if (mask)
1693                                 mask[idx] =
1694                                         rte_cpu_to_be_32(0xffffffff >>
1695                                                          (32 - width));
1696                 }
1697                 break;
1698         case RTE_FLOW_FIELD_META:
1699                 {
1700                         int reg = flow_dv_get_metadata_reg(dev, attr, error);
1701                         if (reg < 0)
1702                                 return;
1703                         MLX5_ASSERT(reg != REG_NON);
1704                         MLX5_ASSERT((unsigned int)reg < RTE_DIM(reg_to_field));
1705                         info[idx] = (struct field_modify_info){4, 0,
1706                                                 reg_to_field[reg]};
1707                         if (mask)
1708                                 mask[idx] =
1709                                         rte_cpu_to_be_32(0xffffffff >>
1710                                                          (32 - width));
1711                 }
1712                 break;
1713         case RTE_FLOW_FIELD_POINTER:
1714                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1715                         if (mask[idx]) {
1716                                 memcpy(&value[idx],
1717                                         (void *)(uintptr_t)data->value, 32);
1718                                 value[idx] = rte_cpu_to_be_32(value[idx]);
1719                                 break;
1720                         }
1721                 }
1722                 break;
1723         case RTE_FLOW_FIELD_VALUE:
1724                 for (idx = 0; idx < MLX5_ACT_MAX_MOD_FIELDS; idx++) {
1725                         if (mask[idx]) {
1726                                 value[idx] =
1727                                         rte_cpu_to_be_32((uint32_t)data->value);
1728                                 break;
1729                         }
1730                 }
1731                 break;
1732         default:
1733                 MLX5_ASSERT(false);
1734                 break;
1735         }
1736 }
1737
1738 /**
1739  * Convert modify_field action to DV specification.
1740  *
1741  * @param[in] dev
1742  *   Pointer to the rte_eth_dev structure.
1743  * @param[in,out] resource
1744  *   Pointer to the modify-header resource.
1745  * @param[in] action
1746  *   Pointer to action specification.
1747  * @param[in] attr
1748  *   Attributes of flow that includes this item.
1749  * @param[out] error
1750  *   Pointer to the error structure.
1751  *
1752  * @return
1753  *   0 on success, a negative errno value otherwise and rte_errno is set.
1754  */
1755 static int
1756 flow_dv_convert_action_modify_field
1757                         (struct rte_eth_dev *dev,
1758                          struct mlx5_flow_dv_modify_hdr_resource *resource,
1759                          const struct rte_flow_action *action,
1760                          const struct rte_flow_attr *attr,
1761                          struct rte_flow_error *error)
1762 {
1763         const struct rte_flow_action_modify_field *conf =
1764                 (const struct rte_flow_action_modify_field *)(action->conf);
1765         struct rte_flow_item item;
1766         struct field_modify_info field[MLX5_ACT_MAX_MOD_FIELDS] = {
1767                                                                 {0, 0, 0} };
1768         struct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {
1769                                                                 {0, 0, 0} };
1770         uint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1771         uint32_t value[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};
1772         uint32_t type;
1773
1774         if (conf->src.field == RTE_FLOW_FIELD_POINTER ||
1775                 conf->src.field == RTE_FLOW_FIELD_VALUE) {
1776                 type = MLX5_MODIFICATION_TYPE_SET;
1777                 /** For SET fill the destination field (field) first. */
1778                 mlx5_flow_field_id_to_modify_info(&conf->dst, field, mask,
1779                                           value, conf->width, dev, attr, error);
1780                 /** Then copy immediate value from source as per mask. */
1781                 mlx5_flow_field_id_to_modify_info(&conf->src, dcopy, mask,
1782                                           value, conf->width, dev, attr, error);
1783                 item.spec = &value;
1784         } else {
1785                 type = MLX5_MODIFICATION_TYPE_COPY;
1786                 /** For COPY fill the destination field (dcopy) without mask. */
1787                 mlx5_flow_field_id_to_modify_info(&conf->dst, dcopy, NULL,
1788                                           value, conf->width, dev, attr, error);
1789                 /** Then construct the source field (field) with mask. */
1790                 mlx5_flow_field_id_to_modify_info(&conf->src, field, mask,
1791                                           value, conf->width, dev, attr, error);
1792         }
1793         item.mask = &mask;
1794         return flow_dv_convert_modify_action(&item,
1795                         field, dcopy, resource, type, error);
1796 }
1797
1798 /**
1799  * Validate MARK item.
1800  *
1801  * @param[in] dev
1802  *   Pointer to the rte_eth_dev structure.
1803  * @param[in] item
1804  *   Item specification.
1805  * @param[in] attr
1806  *   Attributes of flow that includes this item.
1807  * @param[out] error
1808  *   Pointer to error structure.
1809  *
1810  * @return
1811  *   0 on success, a negative errno value otherwise and rte_errno is set.
1812  */
1813 static int
1814 flow_dv_validate_item_mark(struct rte_eth_dev *dev,
1815                            const struct rte_flow_item *item,
1816                            const struct rte_flow_attr *attr __rte_unused,
1817                            struct rte_flow_error *error)
1818 {
1819         struct mlx5_priv *priv = dev->data->dev_private;
1820         struct mlx5_dev_config *config = &priv->config;
1821         const struct rte_flow_item_mark *spec = item->spec;
1822         const struct rte_flow_item_mark *mask = item->mask;
1823         const struct rte_flow_item_mark nic_mask = {
1824                 .id = priv->sh->dv_mark_mask,
1825         };
1826         int ret;
1827
1828         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
1829                 return rte_flow_error_set(error, ENOTSUP,
1830                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1831                                           "extended metadata feature"
1832                                           " isn't enabled");
1833         if (!mlx5_flow_ext_mreg_supported(dev))
1834                 return rte_flow_error_set(error, ENOTSUP,
1835                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1836                                           "extended metadata register"
1837                                           " isn't supported");
1838         if (!nic_mask.id)
1839                 return rte_flow_error_set(error, ENOTSUP,
1840                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1841                                           "extended metadata register"
1842                                           " isn't available");
1843         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
1844         if (ret < 0)
1845                 return ret;
1846         if (!spec)
1847                 return rte_flow_error_set(error, EINVAL,
1848                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1849                                           item->spec,
1850                                           "data cannot be empty");
1851         if (spec->id >= (MLX5_FLOW_MARK_MAX & nic_mask.id))
1852                 return rte_flow_error_set(error, EINVAL,
1853                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
1854                                           &spec->id,
1855                                           "mark id exceeds the limit");
1856         if (!mask)
1857                 mask = &nic_mask;
1858         if (!mask->id)
1859                 return rte_flow_error_set(error, EINVAL,
1860                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1861                                         "mask cannot be zero");
1862
1863         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1864                                         (const uint8_t *)&nic_mask,
1865                                         sizeof(struct rte_flow_item_mark),
1866                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1867         if (ret < 0)
1868                 return ret;
1869         return 0;
1870 }
1871
1872 /**
1873  * Validate META item.
1874  *
1875  * @param[in] dev
1876  *   Pointer to the rte_eth_dev structure.
1877  * @param[in] item
1878  *   Item specification.
1879  * @param[in] attr
1880  *   Attributes of flow that includes this item.
1881  * @param[out] error
1882  *   Pointer to error structure.
1883  *
1884  * @return
1885  *   0 on success, a negative errno value otherwise and rte_errno is set.
1886  */
1887 static int
1888 flow_dv_validate_item_meta(struct rte_eth_dev *dev __rte_unused,
1889                            const struct rte_flow_item *item,
1890                            const struct rte_flow_attr *attr,
1891                            struct rte_flow_error *error)
1892 {
1893         struct mlx5_priv *priv = dev->data->dev_private;
1894         struct mlx5_dev_config *config = &priv->config;
1895         const struct rte_flow_item_meta *spec = item->spec;
1896         const struct rte_flow_item_meta *mask = item->mask;
1897         struct rte_flow_item_meta nic_mask = {
1898                 .data = UINT32_MAX
1899         };
1900         int reg;
1901         int ret;
1902
1903         if (!spec)
1904                 return rte_flow_error_set(error, EINVAL,
1905                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1906                                           item->spec,
1907                                           "data cannot be empty");
1908         if (config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
1909                 if (!mlx5_flow_ext_mreg_supported(dev))
1910                         return rte_flow_error_set(error, ENOTSUP,
1911                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1912                                           "extended metadata register"
1913                                           " isn't supported");
1914                 reg = flow_dv_get_metadata_reg(dev, attr, error);
1915                 if (reg < 0)
1916                         return reg;
1917                 if (reg == REG_NON)
1918                         return rte_flow_error_set(error, ENOTSUP,
1919                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1920                                         "unavalable extended metadata register");
1921                 if (reg == REG_B)
1922                         return rte_flow_error_set(error, ENOTSUP,
1923                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1924                                           "match on reg_b "
1925                                           "isn't supported");
1926                 if (reg != REG_A)
1927                         nic_mask.data = priv->sh->dv_meta_mask;
1928         } else {
1929                 if (attr->transfer)
1930                         return rte_flow_error_set(error, ENOTSUP,
1931                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1932                                         "extended metadata feature "
1933                                         "should be enabled when "
1934                                         "meta item is requested "
1935                                         "with e-switch mode ");
1936                 if (attr->ingress)
1937                         return rte_flow_error_set(error, ENOTSUP,
1938                                         RTE_FLOW_ERROR_TYPE_ITEM, item,
1939                                         "match on metadata for ingress "
1940                                         "is not supported in legacy "
1941                                         "metadata mode");
1942         }
1943         if (!mask)
1944                 mask = &rte_flow_item_meta_mask;
1945         if (!mask->data)
1946                 return rte_flow_error_set(error, EINVAL,
1947                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
1948                                         "mask cannot be zero");
1949
1950         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
1951                                         (const uint8_t *)&nic_mask,
1952                                         sizeof(struct rte_flow_item_meta),
1953                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
1954         return ret;
1955 }
1956
1957 /**
1958  * Validate TAG item.
1959  *
1960  * @param[in] dev
1961  *   Pointer to the rte_eth_dev structure.
1962  * @param[in] item
1963  *   Item specification.
1964  * @param[in] attr
1965  *   Attributes of flow that includes this item.
1966  * @param[out] error
1967  *   Pointer to error structure.
1968  *
1969  * @return
1970  *   0 on success, a negative errno value otherwise and rte_errno is set.
1971  */
1972 static int
1973 flow_dv_validate_item_tag(struct rte_eth_dev *dev,
1974                           const struct rte_flow_item *item,
1975                           const struct rte_flow_attr *attr __rte_unused,
1976                           struct rte_flow_error *error)
1977 {
1978         const struct rte_flow_item_tag *spec = item->spec;
1979         const struct rte_flow_item_tag *mask = item->mask;
1980         const struct rte_flow_item_tag nic_mask = {
1981                 .data = RTE_BE32(UINT32_MAX),
1982                 .index = 0xff,
1983         };
1984         int ret;
1985
1986         if (!mlx5_flow_ext_mreg_supported(dev))
1987                 return rte_flow_error_set(error, ENOTSUP,
1988                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
1989                                           "extensive metadata register"
1990                                           " isn't supported");
1991         if (!spec)
1992                 return rte_flow_error_set(error, EINVAL,
1993                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC,
1994                                           item->spec,
1995                                           "data cannot be empty");
1996         if (!mask)
1997                 mask = &rte_flow_item_tag_mask;
1998         if (!mask->data)
1999                 return rte_flow_error_set(error, EINVAL,
2000                                         RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2001                                         "mask cannot be zero");
2002
2003         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2004                                         (const uint8_t *)&nic_mask,
2005                                         sizeof(struct rte_flow_item_tag),
2006                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2007         if (ret < 0)
2008                 return ret;
2009         if (mask->index != 0xff)
2010                 return rte_flow_error_set(error, EINVAL,
2011                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, NULL,
2012                                           "partial mask for tag index"
2013                                           " is not supported");
2014         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, spec->index, error);
2015         if (ret < 0)
2016                 return ret;
2017         MLX5_ASSERT(ret != REG_NON);
2018         return 0;
2019 }
2020
2021 /**
2022  * Validate vport item.
2023  *
2024  * @param[in] dev
2025  *   Pointer to the rte_eth_dev structure.
2026  * @param[in] item
2027  *   Item specification.
2028  * @param[in] attr
2029  *   Attributes of flow that includes this item.
2030  * @param[in] item_flags
2031  *   Bit-fields that holds the items detected until now.
2032  * @param[out] error
2033  *   Pointer to error structure.
2034  *
2035  * @return
2036  *   0 on success, a negative errno value otherwise and rte_errno is set.
2037  */
2038 static int
2039 flow_dv_validate_item_port_id(struct rte_eth_dev *dev,
2040                               const struct rte_flow_item *item,
2041                               const struct rte_flow_attr *attr,
2042                               uint64_t item_flags,
2043                               struct rte_flow_error *error)
2044 {
2045         const struct rte_flow_item_port_id *spec = item->spec;
2046         const struct rte_flow_item_port_id *mask = item->mask;
2047         const struct rte_flow_item_port_id switch_mask = {
2048                         .id = 0xffffffff,
2049         };
2050         struct mlx5_priv *esw_priv;
2051         struct mlx5_priv *dev_priv;
2052         int ret;
2053
2054         if (!attr->transfer)
2055                 return rte_flow_error_set(error, EINVAL,
2056                                           RTE_FLOW_ERROR_TYPE_ITEM,
2057                                           NULL,
2058                                           "match on port id is valid only"
2059                                           " when transfer flag is enabled");
2060         if (item_flags & MLX5_FLOW_ITEM_PORT_ID)
2061                 return rte_flow_error_set(error, ENOTSUP,
2062                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2063                                           "multiple source ports are not"
2064                                           " supported");
2065         if (!mask)
2066                 mask = &switch_mask;
2067         if (mask->id != 0xffffffff)
2068                 return rte_flow_error_set(error, ENOTSUP,
2069                                            RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2070                                            mask,
2071                                            "no support for partial mask on"
2072                                            " \"id\" field");
2073         ret = mlx5_flow_item_acceptable
2074                                 (item, (const uint8_t *)mask,
2075                                  (const uint8_t *)&rte_flow_item_port_id_mask,
2076                                  sizeof(struct rte_flow_item_port_id),
2077                                  MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2078         if (ret)
2079                 return ret;
2080         if (!spec)
2081                 return 0;
2082         esw_priv = mlx5_port_to_eswitch_info(spec->id, false);
2083         if (!esw_priv)
2084                 return rte_flow_error_set(error, rte_errno,
2085                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2086                                           "failed to obtain E-Switch info for"
2087                                           " port");
2088         dev_priv = mlx5_dev_to_eswitch_info(dev);
2089         if (!dev_priv)
2090                 return rte_flow_error_set(error, rte_errno,
2091                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2092                                           NULL,
2093                                           "failed to obtain E-Switch info");
2094         if (esw_priv->domain_id != dev_priv->domain_id)
2095                 return rte_flow_error_set(error, EINVAL,
2096                                           RTE_FLOW_ERROR_TYPE_ITEM_SPEC, spec,
2097                                           "cannot match on a port from a"
2098                                           " different E-Switch");
2099         return 0;
2100 }
2101
2102 /**
2103  * Validate VLAN item.
2104  *
2105  * @param[in] item
2106  *   Item specification.
2107  * @param[in] item_flags
2108  *   Bit-fields that holds the items detected until now.
2109  * @param[in] dev
2110  *   Ethernet device flow is being created on.
2111  * @param[out] error
2112  *   Pointer to error structure.
2113  *
2114  * @return
2115  *   0 on success, a negative errno value otherwise and rte_errno is set.
2116  */
2117 static int
2118 flow_dv_validate_item_vlan(const struct rte_flow_item *item,
2119                            uint64_t item_flags,
2120                            struct rte_eth_dev *dev,
2121                            struct rte_flow_error *error)
2122 {
2123         const struct rte_flow_item_vlan *mask = item->mask;
2124         const struct rte_flow_item_vlan nic_mask = {
2125                 .tci = RTE_BE16(UINT16_MAX),
2126                 .inner_type = RTE_BE16(UINT16_MAX),
2127                 .has_more_vlan = 1,
2128         };
2129         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2130         int ret;
2131         const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 |
2132                                         MLX5_FLOW_LAYER_INNER_L4) :
2133                                        (MLX5_FLOW_LAYER_OUTER_L3 |
2134                                         MLX5_FLOW_LAYER_OUTER_L4);
2135         const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
2136                                         MLX5_FLOW_LAYER_OUTER_VLAN;
2137
2138         if (item_flags & vlanm)
2139                 return rte_flow_error_set(error, EINVAL,
2140                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2141                                           "multiple VLAN layers not supported");
2142         else if ((item_flags & l34m) != 0)
2143                 return rte_flow_error_set(error, EINVAL,
2144                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2145                                           "VLAN cannot follow L3/L4 layer");
2146         if (!mask)
2147                 mask = &rte_flow_item_vlan_mask;
2148         ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2149                                         (const uint8_t *)&nic_mask,
2150                                         sizeof(struct rte_flow_item_vlan),
2151                                         MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2152         if (ret)
2153                 return ret;
2154         if (!tunnel && mask->tci != RTE_BE16(0x0fff)) {
2155                 struct mlx5_priv *priv = dev->data->dev_private;
2156
2157                 if (priv->vmwa_context) {
2158                         /*
2159                          * Non-NULL context means we have a virtual machine
2160                          * and SR-IOV enabled, we have to create VLAN interface
2161                          * to make hypervisor to setup E-Switch vport
2162                          * context correctly. We avoid creating the multiple
2163                          * VLAN interfaces, so we cannot support VLAN tag mask.
2164                          */
2165                         return rte_flow_error_set(error, EINVAL,
2166                                                   RTE_FLOW_ERROR_TYPE_ITEM,
2167                                                   item,
2168                                                   "VLAN tag mask is not"
2169                                                   " supported in virtual"
2170                                                   " environment");
2171                 }
2172         }
2173         return 0;
2174 }
2175
2176 /*
2177  * GTP flags are contained in 1 byte of the format:
2178  * -------------------------------------------
2179  * | bit   | 0 - 2   | 3  | 4   | 5 | 6 | 7  |
2180  * |-----------------------------------------|
2181  * | value | Version | PT | Res | E | S | PN |
2182  * -------------------------------------------
2183  *
2184  * Matching is supported only for GTP flags E, S, PN.
2185  */
2186 #define MLX5_GTP_FLAGS_MASK     0x07
2187
2188 /**
2189  * Validate GTP item.
2190  *
2191  * @param[in] dev
2192  *   Pointer to the rte_eth_dev structure.
2193  * @param[in] item
2194  *   Item specification.
2195  * @param[in] item_flags
2196  *   Bit-fields that holds the items detected until now.
2197  * @param[out] error
2198  *   Pointer to error structure.
2199  *
2200  * @return
2201  *   0 on success, a negative errno value otherwise and rte_errno is set.
2202  */
2203 static int
2204 flow_dv_validate_item_gtp(struct rte_eth_dev *dev,
2205                           const struct rte_flow_item *item,
2206                           uint64_t item_flags,
2207                           struct rte_flow_error *error)
2208 {
2209         struct mlx5_priv *priv = dev->data->dev_private;
2210         const struct rte_flow_item_gtp *spec = item->spec;
2211         const struct rte_flow_item_gtp *mask = item->mask;
2212         const struct rte_flow_item_gtp nic_mask = {
2213                 .v_pt_rsv_flags = MLX5_GTP_FLAGS_MASK,
2214                 .msg_type = 0xff,
2215                 .teid = RTE_BE32(0xffffffff),
2216         };
2217
2218         if (!priv->config.hca_attr.tunnel_stateless_gtp)
2219                 return rte_flow_error_set(error, ENOTSUP,
2220                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2221                                           "GTP support is not enabled");
2222         if (item_flags & MLX5_FLOW_LAYER_TUNNEL)
2223                 return rte_flow_error_set(error, ENOTSUP,
2224                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2225                                           "multiple tunnel layers not"
2226                                           " supported");
2227         if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP))
2228                 return rte_flow_error_set(error, EINVAL,
2229                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2230                                           "no outer UDP layer found");
2231         if (!mask)
2232                 mask = &rte_flow_item_gtp_mask;
2233         if (spec && spec->v_pt_rsv_flags & ~MLX5_GTP_FLAGS_MASK)
2234                 return rte_flow_error_set(error, ENOTSUP,
2235                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2236                                           "Match is supported for GTP"
2237                                           " flags only");
2238         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2239                                          (const uint8_t *)&nic_mask,
2240                                          sizeof(struct rte_flow_item_gtp),
2241                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2242 }
2243
2244 /**
2245  * Validate GTP PSC item.
2246  *
2247  * @param[in] item
2248  *   Item specification.
2249  * @param[in] last_item
2250  *   Previous validated item in the pattern items.
2251  * @param[in] gtp_item
2252  *   Previous GTP item specification.
2253  * @param[in] attr
2254  *   Pointer to flow attributes.
2255  * @param[out] error
2256  *   Pointer to error structure.
2257  *
2258  * @return
2259  *   0 on success, a negative errno value otherwise and rte_errno is set.
2260  */
2261 static int
2262 flow_dv_validate_item_gtp_psc(const struct rte_flow_item *item,
2263                               uint64_t last_item,
2264                               const struct rte_flow_item *gtp_item,
2265                               const struct rte_flow_attr *attr,
2266                               struct rte_flow_error *error)
2267 {
2268         const struct rte_flow_item_gtp *gtp_spec;
2269         const struct rte_flow_item_gtp *gtp_mask;
2270         const struct rte_flow_item_gtp_psc *spec;
2271         const struct rte_flow_item_gtp_psc *mask;
2272         const struct rte_flow_item_gtp_psc nic_mask = {
2273                 .pdu_type = 0xFF,
2274                 .qfi = 0xFF,
2275         };
2276
2277         if (!gtp_item || !(last_item & MLX5_FLOW_LAYER_GTP))
2278                 return rte_flow_error_set
2279                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2280                          "GTP PSC item must be preceded with GTP item");
2281         gtp_spec = gtp_item->spec;
2282         gtp_mask = gtp_item->mask ? gtp_item->mask : &rte_flow_item_gtp_mask;
2283         /* GTP spec and E flag is requested to match zero. */
2284         if (gtp_spec &&
2285                 (gtp_mask->v_pt_rsv_flags &
2286                 ~gtp_spec->v_pt_rsv_flags & MLX5_GTP_EXT_HEADER_FLAG))
2287                 return rte_flow_error_set
2288                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2289                          "GTP E flag must be 1 to match GTP PSC");
2290         /* Check the flow is not created in group zero. */
2291         if (!attr->transfer && !attr->group)
2292                 return rte_flow_error_set
2293                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2294                          "GTP PSC is not supported for group 0");
2295         /* GTP spec is here and E flag is requested to match zero. */
2296         if (!item->spec)
2297                 return 0;
2298         spec = item->spec;
2299         mask = item->mask ? item->mask : &rte_flow_item_gtp_psc_mask;
2300         if (spec->pdu_type > MLX5_GTP_EXT_MAX_PDU_TYPE)
2301                 return rte_flow_error_set
2302                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item,
2303                          "PDU type should be smaller than 16");
2304         return mlx5_flow_item_acceptable(item, (const uint8_t *)mask,
2305                                          (const uint8_t *)&nic_mask,
2306                                          sizeof(struct rte_flow_item_gtp_psc),
2307                                          MLX5_ITEM_RANGE_NOT_ACCEPTED, error);
2308 }
2309
2310 /**
2311  * Validate IPV4 item.
2312  * Use existing validation function mlx5_flow_validate_item_ipv4(), and
2313  * add specific validation of fragment_offset field,
2314  *
2315  * @param[in] item
2316  *   Item specification.
2317  * @param[in] item_flags
2318  *   Bit-fields that holds the items detected until now.
2319  * @param[out] error
2320  *   Pointer to error structure.
2321  *
2322  * @return
2323  *   0 on success, a negative errno value otherwise and rte_errno is set.
2324  */
2325 static int
2326 flow_dv_validate_item_ipv4(const struct rte_flow_item *item,
2327                            uint64_t item_flags,
2328                            uint64_t last_item,
2329                            uint16_t ether_type,
2330                            struct rte_flow_error *error)
2331 {
2332         int ret;
2333         const struct rte_flow_item_ipv4 *spec = item->spec;
2334         const struct rte_flow_item_ipv4 *last = item->last;
2335         const struct rte_flow_item_ipv4 *mask = item->mask;
2336         rte_be16_t fragment_offset_spec = 0;
2337         rte_be16_t fragment_offset_last = 0;
2338         const struct rte_flow_item_ipv4 nic_ipv4_mask = {
2339                 .hdr = {
2340                         .src_addr = RTE_BE32(0xffffffff),
2341                         .dst_addr = RTE_BE32(0xffffffff),
2342                         .type_of_service = 0xff,
2343                         .fragment_offset = RTE_BE16(0xffff),
2344                         .next_proto_id = 0xff,
2345                         .time_to_live = 0xff,
2346                 },
2347         };
2348
2349         ret = mlx5_flow_validate_item_ipv4(item, item_flags, last_item,
2350                                            ether_type, &nic_ipv4_mask,
2351                                            MLX5_ITEM_RANGE_ACCEPTED, error);
2352         if (ret < 0)
2353                 return ret;
2354         if (spec && mask)
2355                 fragment_offset_spec = spec->hdr.fragment_offset &
2356                                        mask->hdr.fragment_offset;
2357         if (!fragment_offset_spec)
2358                 return 0;
2359         /*
2360          * spec and mask are valid, enforce using full mask to make sure the
2361          * complete value is used correctly.
2362          */
2363         if ((mask->hdr.fragment_offset & RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2364                         != RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2365                 return rte_flow_error_set(error, EINVAL,
2366                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2367                                           item, "must use full mask for"
2368                                           " fragment_offset");
2369         /*
2370          * Match on fragment_offset 0x2000 means MF is 1 and frag-offset is 0,
2371          * indicating this is 1st fragment of fragmented packet.
2372          * This is not yet supported in MLX5, return appropriate error message.
2373          */
2374         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG))
2375                 return rte_flow_error_set(error, ENOTSUP,
2376                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2377                                           "match on first fragment not "
2378                                           "supported");
2379         if (fragment_offset_spec && !last)
2380                 return rte_flow_error_set(error, ENOTSUP,
2381                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2382                                           "specified value not supported");
2383         /* spec and last are valid, validate the specified range. */
2384         fragment_offset_last = last->hdr.fragment_offset &
2385                                mask->hdr.fragment_offset;
2386         /*
2387          * Match on fragment_offset spec 0x2001 and last 0x3fff
2388          * means MF is 1 and frag-offset is > 0.
2389          * This packet is fragment 2nd and onward, excluding last.
2390          * This is not yet supported in MLX5, return appropriate
2391          * error message.
2392          */
2393         if (fragment_offset_spec == RTE_BE16(RTE_IPV4_HDR_MF_FLAG + 1) &&
2394             fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK))
2395                 return rte_flow_error_set(error, ENOTSUP,
2396                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2397                                           last, "match on following "
2398                                           "fragments not supported");
2399         /*
2400          * Match on fragment_offset spec 0x0001 and last 0x1fff
2401          * means MF is 0 and frag-offset is > 0.
2402          * This packet is last fragment of fragmented packet.
2403          * This is not yet supported in MLX5, return appropriate
2404          * error message.
2405          */
2406         if (fragment_offset_spec == RTE_BE16(1) &&
2407             fragment_offset_last == RTE_BE16(RTE_IPV4_HDR_OFFSET_MASK))
2408                 return rte_flow_error_set(error, ENOTSUP,
2409                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2410                                           last, "match on last "
2411                                           "fragment not supported");
2412         /*
2413          * Match on fragment_offset spec 0x0001 and last 0x3fff
2414          * means MF and/or frag-offset is not 0.
2415          * This is a fragmented packet.
2416          * Other range values are invalid and rejected.
2417          */
2418         if (!(fragment_offset_spec == RTE_BE16(1) &&
2419               fragment_offset_last == RTE_BE16(MLX5_IPV4_FRAG_OFFSET_MASK)))
2420                 return rte_flow_error_set(error, ENOTSUP,
2421                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2422                                           "specified range not supported");
2423         return 0;
2424 }
2425
2426 /**
2427  * Validate IPV6 fragment extension item.
2428  *
2429  * @param[in] item
2430  *   Item specification.
2431  * @param[in] item_flags
2432  *   Bit-fields that holds the items detected until now.
2433  * @param[out] error
2434  *   Pointer to error structure.
2435  *
2436  * @return
2437  *   0 on success, a negative errno value otherwise and rte_errno is set.
2438  */
2439 static int
2440 flow_dv_validate_item_ipv6_frag_ext(const struct rte_flow_item *item,
2441                                     uint64_t item_flags,
2442                                     struct rte_flow_error *error)
2443 {
2444         const struct rte_flow_item_ipv6_frag_ext *spec = item->spec;
2445         const struct rte_flow_item_ipv6_frag_ext *last = item->last;
2446         const struct rte_flow_item_ipv6_frag_ext *mask = item->mask;
2447         rte_be16_t frag_data_spec = 0;
2448         rte_be16_t frag_data_last = 0;
2449         const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
2450         const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 :
2451                                       MLX5_FLOW_LAYER_OUTER_L4;
2452         int ret = 0;
2453         struct rte_flow_item_ipv6_frag_ext nic_mask = {
2454                 .hdr = {
2455                         .next_header = 0xff,
2456                         .frag_data = RTE_BE16(0xffff),
2457                 },
2458         };
2459
2460         if (item_flags & l4m)
2461                 return rte_flow_error_set(error, EINVAL,
2462                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2463                                           "ipv6 fragment extension item cannot "
2464                                           "follow L4 item.");
2465         if ((tunnel && !(item_flags & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
2466             (!tunnel && !(item_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV6)))
2467                 return rte_flow_error_set(error, EINVAL,
2468                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2469                                           "ipv6 fragment extension item must "
2470                                           "follow ipv6 item");
2471         if (spec && mask)
2472                 frag_data_spec = spec->hdr.frag_data & mask->hdr.frag_data;
2473         if (!frag_data_spec)
2474                 return 0;
2475         /*
2476          * spec and mask are valid, enforce using full mask to make sure the
2477          * complete value is used correctly.
2478          */
2479         if ((mask->hdr.frag_data & RTE_BE16(RTE_IPV6_FRAG_USED_MASK)) !=
2480                                 RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2481                 return rte_flow_error_set(error, EINVAL,
2482                                           RTE_FLOW_ERROR_TYPE_ITEM_MASK,
2483                                           item, "must use full mask for"
2484                                           " frag_data");
2485         /*
2486          * Match on frag_data 0x00001 means M is 1 and frag-offset is 0.
2487          * This is 1st fragment of fragmented packet.
2488          */
2489         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_MF_MASK))
2490                 return rte_flow_error_set(error, ENOTSUP,
2491                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2492                                           "match on first fragment not "
2493                                           "supported");
2494         if (frag_data_spec && !last)
2495                 return rte_flow_error_set(error, EINVAL,
2496                                           RTE_FLOW_ERROR_TYPE_ITEM, item,
2497                                           "specified value not supported");
2498         ret = mlx5_flow_item_acceptable
2499                                 (item, (const uint8_t *)mask,
2500                                  (const uint8_t *)&nic_mask,
2501                                  sizeof(struct rte_flow_item_ipv6_frag_ext),
2502                                  MLX5_ITEM_RANGE_ACCEPTED, error);
2503         if (ret)
2504                 return ret;
2505         /* spec and last are valid, validate the specified range. */
2506         frag_data_last = last->hdr.frag_data & mask->hdr.frag_data;
2507         /*
2508          * Match on frag_data spec 0x0009 and last 0xfff9
2509          * means M is 1 and frag-offset is > 0.
2510          * This packet is fragment 2nd and onward, excluding last.
2511          * This is not yet supported in MLX5, return appropriate
2512          * error message.
2513          */
2514         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN |
2515                                        RTE_IPV6_EHDR_MF_MASK) &&
2516             frag_data_last == RTE_BE16(RTE_IPV6_FRAG_USED_MASK))
2517                 return rte_flow_error_set(error, ENOTSUP,
2518                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2519                                           last, "match on following "
2520                                           "fragments not supported");
2521         /*
2522          * Match on frag_data spec 0x0008 and last 0xfff8
2523          * means M is 0 and frag-offset is > 0.
2524          * This packet is last fragment of fragmented packet.
2525          * This is not yet supported in MLX5, return appropriate
2526          * error message.
2527          */
2528         if (frag_data_spec == RTE_BE16(RTE_IPV6_EHDR_FO_ALIGN) &&
2529             frag_data_last == RTE_BE16(RTE_IPV6_EHDR_FO_MASK))
2530                 return rte_flow_error_set(error, ENOTSUP,
2531                                           RTE_FLOW_ERROR_TYPE_ITEM_LAST,
2532                                           last, "match on last "
2533                                           "fragment not supported");
2534         /* Other range values are invalid and rejected. */
2535         return rte_flow_error_set(error, EINVAL,
2536                                   RTE_FLOW_ERROR_TYPE_ITEM_LAST, last,
2537                                   "specified range not supported");
2538 }
2539
2540 /**
2541  * Validate the pop VLAN action.
2542  *
2543  * @param[in] dev
2544  *   Pointer to the rte_eth_dev structure.
2545  * @param[in] action_flags
2546  *   Holds the actions detected until now.
2547  * @param[in] action
2548  *   Pointer to the pop vlan action.
2549  * @param[in] item_flags
2550  *   The items found in this flow rule.
2551  * @param[in] attr
2552  *   Pointer to flow attributes.
2553  * @param[out] error
2554  *   Pointer to error structure.
2555  *
2556  * @return
2557  *   0 on success, a negative errno value otherwise and rte_errno is set.
2558  */
2559 static int
2560 flow_dv_validate_action_pop_vlan(struct rte_eth_dev *dev,
2561                                  uint64_t action_flags,
2562                                  const struct rte_flow_action *action,
2563                                  uint64_t item_flags,
2564                                  const struct rte_flow_attr *attr,
2565                                  struct rte_flow_error *error)
2566 {
2567         const struct mlx5_priv *priv = dev->data->dev_private;
2568
2569         (void)action;
2570         (void)attr;
2571         if (!priv->sh->pop_vlan_action)
2572                 return rte_flow_error_set(error, ENOTSUP,
2573                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2574                                           NULL,
2575                                           "pop vlan action is not supported");
2576         if (attr->egress)
2577                 return rte_flow_error_set(error, ENOTSUP,
2578                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
2579                                           NULL,
2580                                           "pop vlan action not supported for "
2581                                           "egress");
2582         if (action_flags & MLX5_FLOW_VLAN_ACTIONS)
2583                 return rte_flow_error_set(error, ENOTSUP,
2584                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2585                                           "no support for multiple VLAN "
2586                                           "actions");
2587         /* Pop VLAN with preceding Decap requires inner header with VLAN. */
2588         if ((action_flags & MLX5_FLOW_ACTION_DECAP) &&
2589             !(item_flags & MLX5_FLOW_LAYER_INNER_VLAN))
2590                 return rte_flow_error_set(error, ENOTSUP,
2591                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2592                                           NULL,
2593                                           "cannot pop vlan after decap without "
2594                                           "match on inner vlan in the flow");
2595         /* Pop VLAN without preceding Decap requires outer header with VLAN. */
2596         if (!(action_flags & MLX5_FLOW_ACTION_DECAP) &&
2597             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2598                 return rte_flow_error_set(error, ENOTSUP,
2599                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
2600                                           NULL,
2601                                           "cannot pop vlan without a "
2602                                           "match on (outer) vlan in the flow");
2603         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2604                 return rte_flow_error_set(error, EINVAL,
2605                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2606                                           "wrong action order, port_id should "
2607                                           "be after pop VLAN action");
2608         if (!attr->transfer && priv->representor)
2609                 return rte_flow_error_set(error, ENOTSUP,
2610                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2611                                           "pop vlan action for VF representor "
2612                                           "not supported on NIC table");
2613         return 0;
2614 }
2615
2616 /**
2617  * Get VLAN default info from vlan match info.
2618  *
2619  * @param[in] items
2620  *   the list of item specifications.
2621  * @param[out] vlan
2622  *   pointer VLAN info to fill to.
2623  *
2624  * @return
2625  *   0 on success, a negative errno value otherwise and rte_errno is set.
2626  */
2627 static void
2628 flow_dev_get_vlan_info_from_items(const struct rte_flow_item *items,
2629                                   struct rte_vlan_hdr *vlan)
2630 {
2631         const struct rte_flow_item_vlan nic_mask = {
2632                 .tci = RTE_BE16(MLX5DV_FLOW_VLAN_PCP_MASK |
2633                                 MLX5DV_FLOW_VLAN_VID_MASK),
2634                 .inner_type = RTE_BE16(0xffff),
2635         };
2636
2637         if (items == NULL)
2638                 return;
2639         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
2640                 int type = items->type;
2641
2642                 if (type == RTE_FLOW_ITEM_TYPE_VLAN ||
2643                     type == MLX5_RTE_FLOW_ITEM_TYPE_VLAN)
2644                         break;
2645         }
2646         if (items->type != RTE_FLOW_ITEM_TYPE_END) {
2647                 const struct rte_flow_item_vlan *vlan_m = items->mask;
2648                 const struct rte_flow_item_vlan *vlan_v = items->spec;
2649
2650                 /* If VLAN item in pattern doesn't contain data, return here. */
2651                 if (!vlan_v)
2652                         return;
2653                 if (!vlan_m)
2654                         vlan_m = &nic_mask;
2655                 /* Only full match values are accepted */
2656                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) ==
2657                      MLX5DV_FLOW_VLAN_PCP_MASK_BE) {
2658                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_PCP_MASK;
2659                         vlan->vlan_tci |=
2660                                 rte_be_to_cpu_16(vlan_v->tci &
2661                                                  MLX5DV_FLOW_VLAN_PCP_MASK_BE);
2662                 }
2663                 if ((vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) ==
2664                      MLX5DV_FLOW_VLAN_VID_MASK_BE) {
2665                         vlan->vlan_tci &= ~MLX5DV_FLOW_VLAN_VID_MASK;
2666                         vlan->vlan_tci |=
2667                                 rte_be_to_cpu_16(vlan_v->tci &
2668                                                  MLX5DV_FLOW_VLAN_VID_MASK_BE);
2669                 }
2670                 if (vlan_m->inner_type == nic_mask.inner_type)
2671                         vlan->eth_proto = rte_be_to_cpu_16(vlan_v->inner_type &
2672                                                            vlan_m->inner_type);
2673         }
2674 }
2675
2676 /**
2677  * Validate the push VLAN action.
2678  *
2679  * @param[in] dev
2680  *   Pointer to the rte_eth_dev structure.
2681  * @param[in] action_flags
2682  *   Holds the actions detected until now.
2683  * @param[in] item_flags
2684  *   The items found in this flow rule.
2685  * @param[in] action
2686  *   Pointer to the action structure.
2687  * @param[in] attr
2688  *   Pointer to flow attributes
2689  * @param[out] error
2690  *   Pointer to error structure.
2691  *
2692  * @return
2693  *   0 on success, a negative errno value otherwise and rte_errno is set.
2694  */
2695 static int
2696 flow_dv_validate_action_push_vlan(struct rte_eth_dev *dev,
2697                                   uint64_t action_flags,
2698                                   const struct rte_flow_item_vlan *vlan_m,
2699                                   const struct rte_flow_action *action,
2700                                   const struct rte_flow_attr *attr,
2701                                   struct rte_flow_error *error)
2702 {
2703         const struct rte_flow_action_of_push_vlan *push_vlan = action->conf;
2704         const struct mlx5_priv *priv = dev->data->dev_private;
2705
2706         if (push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_VLAN) &&
2707             push_vlan->ethertype != RTE_BE16(RTE_ETHER_TYPE_QINQ))
2708                 return rte_flow_error_set(error, EINVAL,
2709                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2710                                           "invalid vlan ethertype");
2711         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2712                 return rte_flow_error_set(error, EINVAL,
2713                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2714                                           "wrong action order, port_id should "
2715                                           "be after push VLAN");
2716         if (!attr->transfer && priv->representor)
2717                 return rte_flow_error_set(error, ENOTSUP,
2718                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
2719                                           "push vlan action for VF representor "
2720                                           "not supported on NIC table");
2721         if (vlan_m &&
2722             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) &&
2723             (vlan_m->tci & MLX5DV_FLOW_VLAN_PCP_MASK_BE) !=
2724                 MLX5DV_FLOW_VLAN_PCP_MASK_BE &&
2725             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP) &&
2726             !(mlx5_flow_find_action
2727                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP)))
2728                 return rte_flow_error_set(error, EINVAL,
2729                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2730                                           "not full match mask on VLAN PCP and "
2731                                           "there is no of_set_vlan_pcp action, "
2732                                           "push VLAN action cannot figure out "
2733                                           "PCP value");
2734         if (vlan_m &&
2735             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) &&
2736             (vlan_m->tci & MLX5DV_FLOW_VLAN_VID_MASK_BE) !=
2737                 MLX5DV_FLOW_VLAN_VID_MASK_BE &&
2738             !(action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID) &&
2739             !(mlx5_flow_find_action
2740                 (action + 1, RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID)))
2741                 return rte_flow_error_set(error, EINVAL,
2742                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2743                                           "not full match mask on VLAN VID and "
2744                                           "there is no of_set_vlan_vid action, "
2745                                           "push VLAN action cannot figure out "
2746                                           "VID value");
2747         (void)attr;
2748         return 0;
2749 }
2750
2751 /**
2752  * Validate the set VLAN PCP.
2753  *
2754  * @param[in] action_flags
2755  *   Holds the actions detected until now.
2756  * @param[in] actions
2757  *   Pointer to the list of actions remaining in the flow rule.
2758  * @param[out] error
2759  *   Pointer to error structure.
2760  *
2761  * @return
2762  *   0 on success, a negative errno value otherwise and rte_errno is set.
2763  */
2764 static int
2765 flow_dv_validate_action_set_vlan_pcp(uint64_t action_flags,
2766                                      const struct rte_flow_action actions[],
2767                                      struct rte_flow_error *error)
2768 {
2769         const struct rte_flow_action *action = actions;
2770         const struct rte_flow_action_of_set_vlan_pcp *conf = action->conf;
2771
2772         if (conf->vlan_pcp > 7)
2773                 return rte_flow_error_set(error, EINVAL,
2774                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2775                                           "VLAN PCP value is too big");
2776         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN))
2777                 return rte_flow_error_set(error, ENOTSUP,
2778                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2779                                           "set VLAN PCP action must follow "
2780                                           "the push VLAN action");
2781         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_PCP)
2782                 return rte_flow_error_set(error, ENOTSUP,
2783                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2784                                           "Multiple VLAN PCP modification are "
2785                                           "not supported");
2786         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2787                 return rte_flow_error_set(error, EINVAL,
2788                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2789                                           "wrong action order, port_id should "
2790                                           "be after set VLAN PCP");
2791         return 0;
2792 }
2793
2794 /**
2795  * Validate the set VLAN VID.
2796  *
2797  * @param[in] item_flags
2798  *   Holds the items detected in this rule.
2799  * @param[in] action_flags
2800  *   Holds the actions detected until now.
2801  * @param[in] actions
2802  *   Pointer to the list of actions remaining in the flow rule.
2803  * @param[out] error
2804  *   Pointer to error structure.
2805  *
2806  * @return
2807  *   0 on success, a negative errno value otherwise and rte_errno is set.
2808  */
2809 static int
2810 flow_dv_validate_action_set_vlan_vid(uint64_t item_flags,
2811                                      uint64_t action_flags,
2812                                      const struct rte_flow_action actions[],
2813                                      struct rte_flow_error *error)
2814 {
2815         const struct rte_flow_action *action = actions;
2816         const struct rte_flow_action_of_set_vlan_vid *conf = action->conf;
2817
2818         if (rte_be_to_cpu_16(conf->vlan_vid) > 0xFFE)
2819                 return rte_flow_error_set(error, EINVAL,
2820                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2821                                           "VLAN VID value is too big");
2822         if (!(action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN) &&
2823             !(item_flags & MLX5_FLOW_LAYER_OUTER_VLAN))
2824                 return rte_flow_error_set(error, ENOTSUP,
2825                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2826                                           "set VLAN VID action must follow push"
2827                                           " VLAN action or match on VLAN item");
2828         if (action_flags & MLX5_FLOW_ACTION_OF_SET_VLAN_VID)
2829                 return rte_flow_error_set(error, ENOTSUP,
2830                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2831                                           "Multiple VLAN VID modifications are "
2832                                           "not supported");
2833         if (action_flags & MLX5_FLOW_ACTION_PORT_ID)
2834                 return rte_flow_error_set(error, EINVAL,
2835                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2836                                           "wrong action order, port_id should "
2837                                           "be after set VLAN VID");
2838         return 0;
2839 }
2840
2841 /*
2842  * Validate the FLAG action.
2843  *
2844  * @param[in] dev
2845  *   Pointer to the rte_eth_dev structure.
2846  * @param[in] action_flags
2847  *   Holds the actions detected until now.
2848  * @param[in] attr
2849  *   Pointer to flow attributes
2850  * @param[out] error
2851  *   Pointer to error structure.
2852  *
2853  * @return
2854  *   0 on success, a negative errno value otherwise and rte_errno is set.
2855  */
2856 static int
2857 flow_dv_validate_action_flag(struct rte_eth_dev *dev,
2858                              uint64_t action_flags,
2859                              const struct rte_flow_attr *attr,
2860                              struct rte_flow_error *error)
2861 {
2862         struct mlx5_priv *priv = dev->data->dev_private;
2863         struct mlx5_dev_config *config = &priv->config;
2864         int ret;
2865
2866         /* Fall back if no extended metadata register support. */
2867         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2868                 return mlx5_flow_validate_action_flag(action_flags, attr,
2869                                                       error);
2870         /* Extensive metadata mode requires registers. */
2871         if (!mlx5_flow_ext_mreg_supported(dev))
2872                 return rte_flow_error_set(error, ENOTSUP,
2873                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2874                                           "no metadata registers "
2875                                           "to support flag action");
2876         if (!(priv->sh->dv_mark_mask & MLX5_FLOW_MARK_DEFAULT))
2877                 return rte_flow_error_set(error, ENOTSUP,
2878                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2879                                           "extended metadata register"
2880                                           " isn't available");
2881         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2882         if (ret < 0)
2883                 return ret;
2884         MLX5_ASSERT(ret > 0);
2885         if (action_flags & MLX5_FLOW_ACTION_MARK)
2886                 return rte_flow_error_set(error, EINVAL,
2887                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2888                                           "can't mark and flag in same flow");
2889         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2890                 return rte_flow_error_set(error, EINVAL,
2891                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2892                                           "can't have 2 flag"
2893                                           " actions in same flow");
2894         return 0;
2895 }
2896
2897 /**
2898  * Validate MARK action.
2899  *
2900  * @param[in] dev
2901  *   Pointer to the rte_eth_dev structure.
2902  * @param[in] action
2903  *   Pointer to action.
2904  * @param[in] action_flags
2905  *   Holds the actions detected until now.
2906  * @param[in] attr
2907  *   Pointer to flow attributes
2908  * @param[out] error
2909  *   Pointer to error structure.
2910  *
2911  * @return
2912  *   0 on success, a negative errno value otherwise and rte_errno is set.
2913  */
2914 static int
2915 flow_dv_validate_action_mark(struct rte_eth_dev *dev,
2916                              const struct rte_flow_action *action,
2917                              uint64_t action_flags,
2918                              const struct rte_flow_attr *attr,
2919                              struct rte_flow_error *error)
2920 {
2921         struct mlx5_priv *priv = dev->data->dev_private;
2922         struct mlx5_dev_config *config = &priv->config;
2923         const struct rte_flow_action_mark *mark = action->conf;
2924         int ret;
2925
2926         if (is_tunnel_offload_active(dev))
2927                 return rte_flow_error_set(error, ENOTSUP,
2928                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2929                                           "no mark action "
2930                                           "if tunnel offload active");
2931         /* Fall back if no extended metadata register support. */
2932         if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY)
2933                 return mlx5_flow_validate_action_mark(action, action_flags,
2934                                                       attr, error);
2935         /* Extensive metadata mode requires registers. */
2936         if (!mlx5_flow_ext_mreg_supported(dev))
2937                 return rte_flow_error_set(error, ENOTSUP,
2938                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2939                                           "no metadata registers "
2940                                           "to support mark action");
2941         if (!priv->sh->dv_mark_mask)
2942                 return rte_flow_error_set(error, ENOTSUP,
2943                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2944                                           "extended metadata register"
2945                                           " isn't available");
2946         ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error);
2947         if (ret < 0)
2948                 return ret;
2949         MLX5_ASSERT(ret > 0);
2950         if (!mark)
2951                 return rte_flow_error_set(error, EINVAL,
2952                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
2953                                           "configuration cannot be null");
2954         if (mark->id >= (MLX5_FLOW_MARK_MAX & priv->sh->dv_mark_mask))
2955                 return rte_flow_error_set(error, EINVAL,
2956                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
2957                                           &mark->id,
2958                                           "mark id exceeds the limit");
2959         if (action_flags & MLX5_FLOW_ACTION_FLAG)
2960                 return rte_flow_error_set(error, EINVAL,
2961                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2962                                           "can't flag and mark in same flow");
2963         if (action_flags & MLX5_FLOW_ACTION_MARK)
2964                 return rte_flow_error_set(error, EINVAL,
2965                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
2966                                           "can't have 2 mark actions in same"
2967                                           " flow");
2968         return 0;
2969 }
2970
2971 /**
2972  * Validate SET_META action.
2973  *
2974  * @param[in] dev
2975  *   Pointer to the rte_eth_dev structure.
2976  * @param[in] action
2977  *   Pointer to the action structure.
2978  * @param[in] action_flags
2979  *   Holds the actions detected until now.
2980  * @param[in] attr
2981  *   Pointer to flow attributes
2982  * @param[out] error
2983  *   Pointer to error structure.
2984  *
2985  * @return
2986  *   0 on success, a negative errno value otherwise and rte_errno is set.
2987  */
2988 static int
2989 flow_dv_validate_action_set_meta(struct rte_eth_dev *dev,
2990                                  const struct rte_flow_action *action,
2991                                  uint64_t action_flags __rte_unused,
2992                                  const struct rte_flow_attr *attr,
2993                                  struct rte_flow_error *error)
2994 {
2995         const struct rte_flow_action_set_meta *conf;
2996         uint32_t nic_mask = UINT32_MAX;
2997         int reg;
2998
2999         if (!mlx5_flow_ext_mreg_supported(dev))
3000                 return rte_flow_error_set(error, ENOTSUP,
3001                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3002                                           "extended metadata register"
3003                                           " isn't supported");
3004         reg = flow_dv_get_metadata_reg(dev, attr, error);
3005         if (reg < 0)
3006                 return reg;
3007         if (reg == REG_NON)
3008                 return rte_flow_error_set(error, ENOTSUP,
3009                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3010                                           "unavalable extended metadata register");
3011         if (reg != REG_A && reg != REG_B) {
3012                 struct mlx5_priv *priv = dev->data->dev_private;
3013
3014                 nic_mask = priv->sh->dv_meta_mask;
3015         }
3016         if (!(action->conf))
3017                 return rte_flow_error_set(error, EINVAL,
3018                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3019                                           "configuration cannot be null");
3020         conf = (const struct rte_flow_action_set_meta *)action->conf;
3021         if (!conf->mask)
3022                 return rte_flow_error_set(error, EINVAL,
3023                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3024                                           "zero mask doesn't have any effect");
3025         if (conf->mask & ~nic_mask)
3026                 return rte_flow_error_set(error, EINVAL,
3027                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3028                                           "meta data must be within reg C0");
3029         return 0;
3030 }
3031
3032 /**
3033  * Validate SET_TAG action.
3034  *
3035  * @param[in] dev
3036  *   Pointer to the rte_eth_dev structure.
3037  * @param[in] action
3038  *   Pointer to the action structure.
3039  * @param[in] action_flags
3040  *   Holds the actions detected until now.
3041  * @param[in] attr
3042  *   Pointer to flow attributes
3043  * @param[out] error
3044  *   Pointer to error structure.
3045  *
3046  * @return
3047  *   0 on success, a negative errno value otherwise and rte_errno is set.
3048  */
3049 static int
3050 flow_dv_validate_action_set_tag(struct rte_eth_dev *dev,
3051                                 const struct rte_flow_action *action,
3052                                 uint64_t action_flags,
3053                                 const struct rte_flow_attr *attr,
3054                                 struct rte_flow_error *error)
3055 {
3056         const struct rte_flow_action_set_tag *conf;
3057         const uint64_t terminal_action_flags =
3058                 MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_QUEUE |
3059                 MLX5_FLOW_ACTION_RSS;
3060         int ret;
3061
3062         if (!mlx5_flow_ext_mreg_supported(dev))
3063                 return rte_flow_error_set(error, ENOTSUP,
3064                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3065                                           "extensive metadata register"
3066                                           " isn't supported");
3067         if (!(action->conf))
3068                 return rte_flow_error_set(error, EINVAL,
3069                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3070                                           "configuration cannot be null");
3071         conf = (const struct rte_flow_action_set_tag *)action->conf;
3072         if (!conf->mask)
3073                 return rte_flow_error_set(error, EINVAL,
3074                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3075                                           "zero mask doesn't have any effect");
3076         ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, conf->index, error);
3077         if (ret < 0)
3078                 return ret;
3079         if (!attr->transfer && attr->ingress &&
3080             (action_flags & terminal_action_flags))
3081                 return rte_flow_error_set(error, EINVAL,
3082                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3083                                           "set_tag has no effect"
3084                                           " with terminal actions");
3085         return 0;
3086 }
3087
3088 /**
3089  * Validate count action.
3090  *
3091  * @param[in] dev
3092  *   Pointer to rte_eth_dev structure.
3093  * @param[in] action
3094  *   Pointer to the action structure.
3095  * @param[in] action_flags
3096  *   Holds the actions detected until now.
3097  * @param[out] error
3098  *   Pointer to error structure.
3099  *
3100  * @return
3101  *   0 on success, a negative errno value otherwise and rte_errno is set.
3102  */
3103 static int
3104 flow_dv_validate_action_count(struct rte_eth_dev *dev,
3105                               const struct rte_flow_action *action,
3106                               uint64_t action_flags,
3107                               struct rte_flow_error *error)
3108 {
3109         struct mlx5_priv *priv = dev->data->dev_private;
3110         const struct rte_flow_action_count *count;
3111
3112         if (!priv->config.devx)
3113                 goto notsup_err;
3114         if (action_flags & MLX5_FLOW_ACTION_COUNT)
3115                 return rte_flow_error_set(error, EINVAL,
3116                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3117                                           "duplicate count actions set");
3118         count = (const struct rte_flow_action_count *)action->conf;
3119         if (count && count->shared && (action_flags & MLX5_FLOW_ACTION_AGE) &&
3120             !priv->sh->flow_hit_aso_en)
3121                 return rte_flow_error_set(error, EINVAL,
3122                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3123                                           "old age and shared count combination is not supported");
3124 #ifdef HAVE_IBV_FLOW_DEVX_COUNTERS
3125         return 0;
3126 #endif
3127 notsup_err:
3128         return rte_flow_error_set
3129                       (error, ENOTSUP,
3130                        RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3131                        NULL,
3132                        "count action not supported");
3133 }
3134
3135 /**
3136  * Validate the L2 encap action.
3137  *
3138  * @param[in] dev
3139  *   Pointer to the rte_eth_dev structure.
3140  * @param[in] action_flags
3141  *   Holds the actions detected until now.
3142  * @param[in] action
3143  *   Pointer to the action structure.
3144  * @param[in] attr
3145  *   Pointer to flow attributes.
3146  * @param[out] error
3147  *   Pointer to error structure.
3148  *
3149  * @return
3150  *   0 on success, a negative errno value otherwise and rte_errno is set.
3151  */
3152 static int
3153 flow_dv_validate_action_l2_encap(struct rte_eth_dev *dev,
3154                                  uint64_t action_flags,
3155                                  const struct rte_flow_action *action,
3156                                  const struct rte_flow_attr *attr,
3157                                  struct rte_flow_error *error)
3158 {
3159         const struct mlx5_priv *priv = dev->data->dev_private;
3160
3161         if (!(action->conf))
3162                 return rte_flow_error_set(error, EINVAL,
3163                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
3164                                           "configuration cannot be null");
3165         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
3166                 return rte_flow_error_set(error, EINVAL,
3167                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3168                                           "can only have a single encap action "
3169                                           "in a flow");
3170         if (!attr->transfer && priv->representor)
3171                 return rte_flow_error_set(error, ENOTSUP,
3172                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3173                                           "encap action for VF representor "
3174                                           "not supported on NIC table");
3175         return 0;
3176 }
3177
3178 /**
3179  * Validate a decap action.
3180  *
3181  * @param[in] dev
3182  *   Pointer to the rte_eth_dev structure.
3183  * @param[in] action_flags
3184  *   Holds the actions detected until now.
3185  * @param[in] action
3186  *   Pointer to the action structure.
3187  * @param[in] item_flags
3188  *   Holds the items detected.
3189  * @param[in] attr
3190  *   Pointer to flow attributes
3191  * @param[out] error
3192  *   Pointer to error structure.
3193  *
3194  * @return
3195  *   0 on success, a negative errno value otherwise and rte_errno is set.
3196  */
3197 static int
3198 flow_dv_validate_action_decap(struct rte_eth_dev *dev,
3199                               uint64_t action_flags,
3200                               const struct rte_flow_action *action,
3201                               const uint64_t item_flags,
3202                               const struct rte_flow_attr *attr,
3203                               struct rte_flow_error *error)
3204 {
3205         const struct mlx5_priv *priv = dev->data->dev_private;
3206
3207         if (priv->config.hca_attr.scatter_fcs_w_decap_disable &&
3208             !priv->config.decap_en)
3209                 return rte_flow_error_set(error, ENOTSUP,
3210                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3211                                           "decap is not enabled");
3212         if (action_flags & MLX5_FLOW_XCAP_ACTIONS)
3213                 return rte_flow_error_set(error, ENOTSUP,
3214                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3215                                           action_flags &
3216                                           MLX5_FLOW_ACTION_DECAP ? "can only "
3217                                           "have a single decap action" : "decap "
3218                                           "after encap is not supported");
3219         if (action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS)
3220                 return rte_flow_error_set(error, EINVAL,
3221                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3222                                           "can't have decap action after"
3223                                           " modify action");
3224         if (attr->egress)
3225                 return rte_flow_error_set(error, ENOTSUP,
3226                                           RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
3227                                           NULL,
3228                                           "decap action not supported for "
3229                                           "egress");
3230         if (!attr->transfer && priv->representor)
3231                 return rte_flow_error_set(error, ENOTSUP,
3232                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3233                                           "decap action for VF representor "
3234                                           "not supported on NIC table");
3235         if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_DECAP &&
3236             !(item_flags & MLX5_FLOW_LAYER_VXLAN))
3237                 return rte_flow_error_set(error, ENOTSUP,
3238                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3239                                 "VXLAN item should be present for VXLAN decap");
3240         return 0;
3241 }
3242
3243 const struct rte_flow_action_raw_decap empty_decap = {.data = NULL, .size = 0,};
3244
3245 /**
3246  * Validate the raw encap and decap actions.
3247  *
3248  * @param[in] dev
3249  *   Pointer to the rte_eth_dev structure.
3250  * @param[in] decap
3251  *   Pointer to the decap action.
3252  * @param[in] encap
3253  *   Pointer to the encap action.
3254  * @param[in] attr
3255  *   Pointer to flow attributes
3256  * @param[in/out] action_flags
3257  *   Holds the actions detected until now.
3258  * @param[out] actions_n
3259  *   pointer to the number of actions counter.
3260  * @param[in] action
3261  *   Pointer to the action structure.
3262  * @param[in] item_flags
3263  *   Holds the items detected.
3264  * @param[out] error
3265  *   Pointer to error structure.
3266  *
3267  * @return
3268  *   0 on success, a negative errno value otherwise and rte_errno is set.
3269  */
3270 static int
3271 flow_dv_validate_action_raw_encap_decap
3272         (struct rte_eth_dev *dev,
3273          const struct rte_flow_action_raw_decap *decap,
3274          const struct rte_flow_action_raw_encap *encap,
3275          const struct rte_flow_attr *attr, uint64_t *action_flags,
3276          int *actions_n, const struct rte_flow_action *action,
3277          uint64_t item_flags, struct rte_flow_error *error)
3278 {
3279         const struct mlx5_priv *priv = dev->data->dev_private;
3280         int ret;
3281
3282         if (encap && (!encap->size || !encap->data))
3283                 return rte_flow_error_set(error, EINVAL,
3284                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
3285                                           "raw encap data cannot be empty");
3286         if (decap && encap) {
3287                 if (decap->size <= MLX5_ENCAPSULATION_DECISION_SIZE &&
3288                     encap->size > MLX5_ENCAPSULATION_DECISION_SIZE)
3289                         /* L3 encap. */
3290                         decap = NULL;
3291                 else if (encap->size <=
3292                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3293                            decap->size >
3294                            MLX5_ENCAPSULATION_DECISION_SIZE)
3295                         /* L3 decap. */
3296                         encap = NULL;
3297                 else if (encap->size >
3298                            MLX5_ENCAPSULATION_DECISION_SIZE &&
3299                            decap->size >
3300                            MLX5_ENCAPSULATION_DECISION_SIZE)
3301                         /* 2 L2 actions: encap and decap. */
3302                         ;
3303                 else
3304                         return rte_flow_error_set(error,
3305                                 ENOTSUP,
3306                                 RTE_FLOW_ERROR_TYPE_ACTION,
3307                                 NULL, "unsupported too small "
3308                                 "raw decap and too small raw "
3309                                 "encap combination");
3310         }
3311         if (decap) {
3312                 ret = flow_dv_validate_action_decap(dev, *action_flags, action,
3313                                                     item_flags, attr, error);
3314                 if (ret < 0)
3315                         return ret;
3316                 *action_flags |= MLX5_FLOW_ACTION_DECAP;
3317                 ++(*actions_n);
3318         }
3319         if (encap) {
3320                 if (encap->size <= MLX5_ENCAPSULATION_DECISION_SIZE)
3321                         return rte_flow_error_set(error, ENOTSUP,
3322                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3323                                                   NULL,
3324                                                   "small raw encap size");
3325                 if (*action_flags & MLX5_FLOW_ACTION_ENCAP)
3326                         return rte_flow_error_set(error, EINVAL,
3327                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3328                                                   NULL,
3329                                                   "more than one encap action");
3330                 if (!attr->transfer && priv->representor)
3331                         return rte_flow_error_set
3332                                         (error, ENOTSUP,
3333                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3334                                          "encap action for VF representor "
3335                                          "not supported on NIC table");
3336                 *action_flags |= MLX5_FLOW_ACTION_ENCAP;
3337                 ++(*actions_n);
3338         }
3339         return 0;
3340 }
3341
3342 /**
3343  * Match encap_decap resource.
3344  *
3345  * @param list
3346  *   Pointer to the hash list.
3347  * @param entry
3348  *   Pointer to exist resource entry object.
3349  * @param key
3350  *   Key of the new entry.
3351  * @param ctx_cb
3352  *   Pointer to new encap_decap resource.
3353  *
3354  * @return
3355  *   0 on matching, none-zero otherwise.
3356  */
3357 int
3358 flow_dv_encap_decap_match_cb(struct mlx5_hlist *list __rte_unused,
3359                              struct mlx5_hlist_entry *entry,
3360                              uint64_t key __rte_unused, void *cb_ctx)
3361 {
3362         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3363         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3364         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3365
3366         cache_resource = container_of(entry,
3367                                       struct mlx5_flow_dv_encap_decap_resource,
3368                                       entry);
3369         if (resource->reformat_type == cache_resource->reformat_type &&
3370             resource->ft_type == cache_resource->ft_type &&
3371             resource->flags == cache_resource->flags &&
3372             resource->size == cache_resource->size &&
3373             !memcmp((const void *)resource->buf,
3374                     (const void *)cache_resource->buf,
3375                     resource->size))
3376                 return 0;
3377         return -1;
3378 }
3379
3380 /**
3381  * Allocate encap_decap resource.
3382  *
3383  * @param list
3384  *   Pointer to the hash list.
3385  * @param entry
3386  *   Pointer to exist resource entry object.
3387  * @param ctx_cb
3388  *   Pointer to new encap_decap resource.
3389  *
3390  * @return
3391  *   0 on matching, none-zero otherwise.
3392  */
3393 struct mlx5_hlist_entry *
3394 flow_dv_encap_decap_create_cb(struct mlx5_hlist *list,
3395                               uint64_t key __rte_unused,
3396                               void *cb_ctx)
3397 {
3398         struct mlx5_dev_ctx_shared *sh = list->ctx;
3399         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3400         struct mlx5dv_dr_domain *domain;
3401         struct mlx5_flow_dv_encap_decap_resource *resource = ctx->data;
3402         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
3403         uint32_t idx;
3404         int ret;
3405
3406         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3407                 domain = sh->fdb_domain;
3408         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3409                 domain = sh->rx_domain;
3410         else
3411                 domain = sh->tx_domain;
3412         /* Register new encap/decap resource. */
3413         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
3414                                        &idx);
3415         if (!cache_resource) {
3416                 rte_flow_error_set(ctx->error, ENOMEM,
3417                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3418                                    "cannot allocate resource memory");
3419                 return NULL;
3420         }
3421         *cache_resource = *resource;
3422         cache_resource->idx = idx;
3423         ret = mlx5_flow_os_create_flow_action_packet_reformat
3424                                         (sh->ctx, domain, cache_resource,
3425                                          &cache_resource->action);
3426         if (ret) {
3427                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], idx);
3428                 rte_flow_error_set(ctx->error, ENOMEM,
3429                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3430                                    NULL, "cannot create action");
3431                 return NULL;
3432         }
3433
3434         return &cache_resource->entry;
3435 }
3436
3437 /**
3438  * Find existing encap/decap resource or create and register a new one.
3439  *
3440  * @param[in, out] dev
3441  *   Pointer to rte_eth_dev structure.
3442  * @param[in, out] resource
3443  *   Pointer to encap/decap resource.
3444  * @parm[in, out] dev_flow
3445  *   Pointer to the dev_flow.
3446  * @param[out] error
3447  *   pointer to error structure.
3448  *
3449  * @return
3450  *   0 on success otherwise -errno and errno is set.
3451  */
3452 static int
3453 flow_dv_encap_decap_resource_register
3454                         (struct rte_eth_dev *dev,
3455                          struct mlx5_flow_dv_encap_decap_resource *resource,
3456                          struct mlx5_flow *dev_flow,
3457                          struct rte_flow_error *error)
3458 {
3459         struct mlx5_priv *priv = dev->data->dev_private;
3460         struct mlx5_dev_ctx_shared *sh = priv->sh;
3461         struct mlx5_hlist_entry *entry;
3462         union {
3463                 struct {
3464                         uint32_t ft_type:8;
3465                         uint32_t refmt_type:8;
3466                         /*
3467                          * Header reformat actions can be shared between
3468                          * non-root tables. One bit to indicate non-root
3469                          * table or not.
3470                          */
3471                         uint32_t is_root:1;
3472                         uint32_t reserve:15;
3473                 };
3474                 uint32_t v32;
3475         } encap_decap_key = {
3476                 {
3477                         .ft_type = resource->ft_type,
3478                         .refmt_type = resource->reformat_type,
3479                         .is_root = !!dev_flow->dv.group,
3480                         .reserve = 0,
3481                 }
3482         };
3483         struct mlx5_flow_cb_ctx ctx = {
3484                 .error = error,
3485                 .data = resource,
3486         };
3487         uint64_t key64;
3488
3489         resource->flags = dev_flow->dv.group ? 0 : 1;
3490         key64 =  __rte_raw_cksum(&encap_decap_key.v32,
3491                                  sizeof(encap_decap_key.v32), 0);
3492         if (resource->reformat_type !=
3493             MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2 &&
3494             resource->size)
3495                 key64 = __rte_raw_cksum(resource->buf, resource->size, key64);
3496         entry = mlx5_hlist_register(sh->encaps_decaps, key64, &ctx);
3497         if (!entry)
3498                 return -rte_errno;
3499         resource = container_of(entry, typeof(*resource), entry);
3500         dev_flow->dv.encap_decap = resource;
3501         dev_flow->handle->dvh.rix_encap_decap = resource->idx;
3502         return 0;
3503 }
3504
3505 /**
3506  * Find existing table jump resource or create and register a new one.
3507  *
3508  * @param[in, out] dev
3509  *   Pointer to rte_eth_dev structure.
3510  * @param[in, out] tbl
3511  *   Pointer to flow table resource.
3512  * @parm[in, out] dev_flow
3513  *   Pointer to the dev_flow.
3514  * @param[out] error
3515  *   pointer to error structure.
3516  *
3517  * @return
3518  *   0 on success otherwise -errno and errno is set.
3519  */
3520 static int
3521 flow_dv_jump_tbl_resource_register
3522                         (struct rte_eth_dev *dev __rte_unused,
3523                          struct mlx5_flow_tbl_resource *tbl,
3524                          struct mlx5_flow *dev_flow,
3525                          struct rte_flow_error *error __rte_unused)
3526 {
3527         struct mlx5_flow_tbl_data_entry *tbl_data =
3528                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
3529
3530         MLX5_ASSERT(tbl);
3531         MLX5_ASSERT(tbl_data->jump.action);
3532         dev_flow->handle->rix_jump = tbl_data->idx;
3533         dev_flow->dv.jump = &tbl_data->jump;
3534         return 0;
3535 }
3536
3537 int
3538 flow_dv_port_id_match_cb(struct mlx5_cache_list *list __rte_unused,
3539                          struct mlx5_cache_entry *entry, void *cb_ctx)
3540 {
3541         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3542         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3543         struct mlx5_flow_dv_port_id_action_resource *res =
3544                         container_of(entry, typeof(*res), entry);
3545
3546         return ref->port_id != res->port_id;
3547 }
3548
3549 struct mlx5_cache_entry *
3550 flow_dv_port_id_create_cb(struct mlx5_cache_list *list,
3551                           struct mlx5_cache_entry *entry __rte_unused,
3552                           void *cb_ctx)
3553 {
3554         struct mlx5_dev_ctx_shared *sh = list->ctx;
3555         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3556         struct mlx5_flow_dv_port_id_action_resource *ref = ctx->data;
3557         struct mlx5_flow_dv_port_id_action_resource *cache;
3558         uint32_t idx;
3559         int ret;
3560
3561         /* Register new port id action resource. */
3562         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PORT_ID], &idx);
3563         if (!cache) {
3564                 rte_flow_error_set(ctx->error, ENOMEM,
3565                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3566                                    "cannot allocate port_id action cache memory");
3567                 return NULL;
3568         }
3569         *cache = *ref;
3570         ret = mlx5_flow_os_create_flow_action_dest_port(sh->fdb_domain,
3571                                                         ref->port_id,
3572                                                         &cache->action);
3573         if (ret) {
3574                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], idx);
3575                 rte_flow_error_set(ctx->error, ENOMEM,
3576                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3577                                    "cannot create action");
3578                 return NULL;
3579         }
3580         cache->idx = idx;
3581         return &cache->entry;
3582 }
3583
3584 /**
3585  * Find existing table port ID resource or create and register a new one.
3586  *
3587  * @param[in, out] dev
3588  *   Pointer to rte_eth_dev structure.
3589  * @param[in, out] resource
3590  *   Pointer to port ID action resource.
3591  * @parm[in, out] dev_flow
3592  *   Pointer to the dev_flow.
3593  * @param[out] error
3594  *   pointer to error structure.
3595  *
3596  * @return
3597  *   0 on success otherwise -errno and errno is set.
3598  */
3599 static int
3600 flow_dv_port_id_action_resource_register
3601                         (struct rte_eth_dev *dev,
3602                          struct mlx5_flow_dv_port_id_action_resource *resource,
3603                          struct mlx5_flow *dev_flow,
3604                          struct rte_flow_error *error)
3605 {
3606         struct mlx5_priv *priv = dev->data->dev_private;
3607         struct mlx5_cache_entry *entry;
3608         struct mlx5_flow_dv_port_id_action_resource *cache;
3609         struct mlx5_flow_cb_ctx ctx = {
3610                 .error = error,
3611                 .data = resource,
3612         };
3613
3614         entry = mlx5_cache_register(&priv->sh->port_id_action_list, &ctx);
3615         if (!entry)
3616                 return -rte_errno;
3617         cache = container_of(entry, typeof(*cache), entry);
3618         dev_flow->dv.port_id_action = cache;
3619         dev_flow->handle->rix_port_id_action = cache->idx;
3620         return 0;
3621 }
3622
3623 int
3624 flow_dv_push_vlan_match_cb(struct mlx5_cache_list *list __rte_unused,
3625                          struct mlx5_cache_entry *entry, void *cb_ctx)
3626 {
3627         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3628         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3629         struct mlx5_flow_dv_push_vlan_action_resource *res =
3630                         container_of(entry, typeof(*res), entry);
3631
3632         return ref->vlan_tag != res->vlan_tag || ref->ft_type != res->ft_type;
3633 }
3634
3635 struct mlx5_cache_entry *
3636 flow_dv_push_vlan_create_cb(struct mlx5_cache_list *list,
3637                           struct mlx5_cache_entry *entry __rte_unused,
3638                           void *cb_ctx)
3639 {
3640         struct mlx5_dev_ctx_shared *sh = list->ctx;
3641         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
3642         struct mlx5_flow_dv_push_vlan_action_resource *ref = ctx->data;
3643         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3644         struct mlx5dv_dr_domain *domain;
3645         uint32_t idx;
3646         int ret;
3647
3648         /* Register new port id action resource. */
3649         cache = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_PUSH_VLAN], &idx);
3650         if (!cache) {
3651                 rte_flow_error_set(ctx->error, ENOMEM,
3652                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3653                                    "cannot allocate push_vlan action cache memory");
3654                 return NULL;
3655         }
3656         *cache = *ref;
3657         if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
3658                 domain = sh->fdb_domain;
3659         else if (ref->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
3660                 domain = sh->rx_domain;
3661         else
3662                 domain = sh->tx_domain;
3663         ret = mlx5_flow_os_create_flow_action_push_vlan(domain, ref->vlan_tag,
3664                                                         &cache->action);
3665         if (ret) {
3666                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
3667                 rte_flow_error_set(ctx->error, ENOMEM,
3668                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
3669                                    "cannot create push vlan action");
3670                 return NULL;
3671         }
3672         cache->idx = idx;
3673         return &cache->entry;
3674 }
3675
3676 /**
3677  * Find existing push vlan resource or create and register a new one.
3678  *
3679  * @param [in, out] dev
3680  *   Pointer to rte_eth_dev structure.
3681  * @param[in, out] resource
3682  *   Pointer to port ID action resource.
3683  * @parm[in, out] dev_flow
3684  *   Pointer to the dev_flow.
3685  * @param[out] error
3686  *   pointer to error structure.
3687  *
3688  * @return
3689  *   0 on success otherwise -errno and errno is set.
3690  */
3691 static int
3692 flow_dv_push_vlan_action_resource_register
3693                        (struct rte_eth_dev *dev,
3694                         struct mlx5_flow_dv_push_vlan_action_resource *resource,
3695                         struct mlx5_flow *dev_flow,
3696                         struct rte_flow_error *error)
3697 {
3698         struct mlx5_priv *priv = dev->data->dev_private;
3699         struct mlx5_flow_dv_push_vlan_action_resource *cache;
3700         struct mlx5_cache_entry *entry;
3701         struct mlx5_flow_cb_ctx ctx = {
3702                 .error = error,
3703                 .data = resource,
3704         };
3705
3706         entry = mlx5_cache_register(&priv->sh->push_vlan_action_list, &ctx);
3707         if (!entry)
3708                 return -rte_errno;
3709         cache = container_of(entry, typeof(*cache), entry);
3710
3711         dev_flow->handle->dvh.rix_push_vlan = cache->idx;
3712         dev_flow->dv.push_vlan_res = cache;
3713         return 0;
3714 }
3715
3716 /**
3717  * Get the size of specific rte_flow_item_type hdr size
3718  *
3719  * @param[in] item_type
3720  *   Tested rte_flow_item_type.
3721  *
3722  * @return
3723  *   sizeof struct item_type, 0 if void or irrelevant.
3724  */
3725 static size_t
3726 flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type)
3727 {
3728         size_t retval;
3729
3730         switch (item_type) {
3731         case RTE_FLOW_ITEM_TYPE_ETH:
3732                 retval = sizeof(struct rte_ether_hdr);
3733                 break;
3734         case RTE_FLOW_ITEM_TYPE_VLAN:
3735                 retval = sizeof(struct rte_vlan_hdr);
3736                 break;
3737         case RTE_FLOW_ITEM_TYPE_IPV4:
3738                 retval = sizeof(struct rte_ipv4_hdr);
3739                 break;
3740         case RTE_FLOW_ITEM_TYPE_IPV6:
3741                 retval = sizeof(struct rte_ipv6_hdr);
3742                 break;
3743         case RTE_FLOW_ITEM_TYPE_UDP:
3744                 retval = sizeof(struct rte_udp_hdr);
3745                 break;
3746         case RTE_FLOW_ITEM_TYPE_TCP:
3747                 retval = sizeof(struct rte_tcp_hdr);
3748                 break;
3749         case RTE_FLOW_ITEM_TYPE_VXLAN:
3750         case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3751                 retval = sizeof(struct rte_vxlan_hdr);
3752                 break;
3753         case RTE_FLOW_ITEM_TYPE_GRE:
3754         case RTE_FLOW_ITEM_TYPE_NVGRE:
3755                 retval = sizeof(struct rte_gre_hdr);
3756                 break;
3757         case RTE_FLOW_ITEM_TYPE_MPLS:
3758                 retval = sizeof(struct rte_mpls_hdr);
3759                 break;
3760         case RTE_FLOW_ITEM_TYPE_VOID: /* Fall through. */
3761         default:
3762                 retval = 0;
3763                 break;
3764         }
3765         return retval;
3766 }
3767
3768 #define MLX5_ENCAP_IPV4_VERSION         0x40
3769 #define MLX5_ENCAP_IPV4_IHL_MIN         0x05
3770 #define MLX5_ENCAP_IPV4_TTL_DEF         0x40
3771 #define MLX5_ENCAP_IPV6_VTC_FLOW        0x60000000
3772 #define MLX5_ENCAP_IPV6_HOP_LIMIT       0xff
3773 #define MLX5_ENCAP_VXLAN_FLAGS          0x08000000
3774 #define MLX5_ENCAP_VXLAN_GPE_FLAGS      0x04
3775
3776 /**
3777  * Convert the encap action data from list of rte_flow_item to raw buffer
3778  *
3779  * @param[in] items
3780  *   Pointer to rte_flow_item objects list.
3781  * @param[out] buf
3782  *   Pointer to the output buffer.
3783  * @param[out] size
3784  *   Pointer to the output buffer size.
3785  * @param[out] error
3786  *   Pointer to the error structure.
3787  *
3788  * @return
3789  *   0 on success, a negative errno value otherwise and rte_errno is set.
3790  */
3791 static int
3792 flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
3793                            size_t *size, struct rte_flow_error *error)
3794 {
3795         struct rte_ether_hdr *eth = NULL;
3796         struct rte_vlan_hdr *vlan = NULL;
3797         struct rte_ipv4_hdr *ipv4 = NULL;
3798         struct rte_ipv6_hdr *ipv6 = NULL;
3799         struct rte_udp_hdr *udp = NULL;
3800         struct rte_vxlan_hdr *vxlan = NULL;
3801         struct rte_vxlan_gpe_hdr *vxlan_gpe = NULL;
3802         struct rte_gre_hdr *gre = NULL;
3803         size_t len;
3804         size_t temp_size = 0;
3805
3806         if (!items)
3807                 return rte_flow_error_set(error, EINVAL,
3808                                           RTE_FLOW_ERROR_TYPE_ACTION,
3809                                           NULL, "invalid empty data");
3810         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
3811                 len = flow_dv_get_item_hdr_len(items->type);
3812                 if (len + temp_size > MLX5_ENCAP_MAX_LEN)
3813                         return rte_flow_error_set(error, EINVAL,
3814                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3815                                                   (void *)items->type,
3816                                                   "items total size is too big"
3817                                                   " for encap action");
3818                 rte_memcpy((void *)&buf[temp_size], items->spec, len);
3819                 switch (items->type) {
3820                 case RTE_FLOW_ITEM_TYPE_ETH:
3821                         eth = (struct rte_ether_hdr *)&buf[temp_size];
3822                         break;
3823                 case RTE_FLOW_ITEM_TYPE_VLAN:
3824                         vlan = (struct rte_vlan_hdr *)&buf[temp_size];
3825                         if (!eth)
3826                                 return rte_flow_error_set(error, EINVAL,
3827                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3828                                                 (void *)items->type,
3829                                                 "eth header not found");
3830                         if (!eth->ether_type)
3831                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_VLAN);
3832                         break;
3833                 case RTE_FLOW_ITEM_TYPE_IPV4:
3834                         ipv4 = (struct rte_ipv4_hdr *)&buf[temp_size];
3835                         if (!vlan && !eth)
3836                                 return rte_flow_error_set(error, EINVAL,
3837                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3838                                                 (void *)items->type,
3839                                                 "neither eth nor vlan"
3840                                                 " header found");
3841                         if (vlan && !vlan->eth_proto)
3842                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3843                         else if (eth && !eth->ether_type)
3844                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV4);
3845                         if (!ipv4->version_ihl)
3846                                 ipv4->version_ihl = MLX5_ENCAP_IPV4_VERSION |
3847                                                     MLX5_ENCAP_IPV4_IHL_MIN;
3848                         if (!ipv4->time_to_live)
3849                                 ipv4->time_to_live = MLX5_ENCAP_IPV4_TTL_DEF;
3850                         break;
3851                 case RTE_FLOW_ITEM_TYPE_IPV6:
3852                         ipv6 = (struct rte_ipv6_hdr *)&buf[temp_size];
3853                         if (!vlan && !eth)
3854                                 return rte_flow_error_set(error, EINVAL,
3855                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3856                                                 (void *)items->type,
3857                                                 "neither eth nor vlan"
3858                                                 " header found");
3859                         if (vlan && !vlan->eth_proto)
3860                                 vlan->eth_proto = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3861                         else if (eth && !eth->ether_type)
3862                                 eth->ether_type = RTE_BE16(RTE_ETHER_TYPE_IPV6);
3863                         if (!ipv6->vtc_flow)
3864                                 ipv6->vtc_flow =
3865                                         RTE_BE32(MLX5_ENCAP_IPV6_VTC_FLOW);
3866                         if (!ipv6->hop_limits)
3867                                 ipv6->hop_limits = MLX5_ENCAP_IPV6_HOP_LIMIT;
3868                         break;
3869                 case RTE_FLOW_ITEM_TYPE_UDP:
3870                         udp = (struct rte_udp_hdr *)&buf[temp_size];
3871                         if (!ipv4 && !ipv6)
3872                                 return rte_flow_error_set(error, EINVAL,
3873                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3874                                                 (void *)items->type,
3875                                                 "ip header not found");
3876                         if (ipv4 && !ipv4->next_proto_id)
3877                                 ipv4->next_proto_id = IPPROTO_UDP;
3878                         else if (ipv6 && !ipv6->proto)
3879                                 ipv6->proto = IPPROTO_UDP;
3880                         break;
3881                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3882                         vxlan = (struct rte_vxlan_hdr *)&buf[temp_size];
3883                         if (!udp)
3884                                 return rte_flow_error_set(error, EINVAL,
3885                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3886                                                 (void *)items->type,
3887                                                 "udp header not found");
3888                         if (!udp->dst_port)
3889                                 udp->dst_port = RTE_BE16(MLX5_UDP_PORT_VXLAN);
3890                         if (!vxlan->vx_flags)
3891                                 vxlan->vx_flags =
3892                                         RTE_BE32(MLX5_ENCAP_VXLAN_FLAGS);
3893                         break;
3894                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
3895                         vxlan_gpe = (struct rte_vxlan_gpe_hdr *)&buf[temp_size];
3896                         if (!udp)
3897                                 return rte_flow_error_set(error, EINVAL,
3898                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3899                                                 (void *)items->type,
3900                                                 "udp header not found");
3901                         if (!vxlan_gpe->proto)
3902                                 return rte_flow_error_set(error, EINVAL,
3903                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3904                                                 (void *)items->type,
3905                                                 "next protocol not found");
3906                         if (!udp->dst_port)
3907                                 udp->dst_port =
3908                                         RTE_BE16(MLX5_UDP_PORT_VXLAN_GPE);
3909                         if (!vxlan_gpe->vx_flags)
3910                                 vxlan_gpe->vx_flags =
3911                                                 MLX5_ENCAP_VXLAN_GPE_FLAGS;
3912                         break;
3913                 case RTE_FLOW_ITEM_TYPE_GRE:
3914                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3915                         gre = (struct rte_gre_hdr *)&buf[temp_size];
3916                         if (!gre->proto)
3917                                 return rte_flow_error_set(error, EINVAL,
3918                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3919                                                 (void *)items->type,
3920                                                 "next protocol not found");
3921                         if (!ipv4 && !ipv6)
3922                                 return rte_flow_error_set(error, EINVAL,
3923                                                 RTE_FLOW_ERROR_TYPE_ACTION,
3924                                                 (void *)items->type,
3925                                                 "ip header not found");
3926                         if (ipv4 && !ipv4->next_proto_id)
3927                                 ipv4->next_proto_id = IPPROTO_GRE;
3928                         else if (ipv6 && !ipv6->proto)
3929                                 ipv6->proto = IPPROTO_GRE;
3930                         break;
3931                 case RTE_FLOW_ITEM_TYPE_VOID:
3932                         break;
3933                 default:
3934                         return rte_flow_error_set(error, EINVAL,
3935                                                   RTE_FLOW_ERROR_TYPE_ACTION,
3936                                                   (void *)items->type,
3937                                                   "unsupported item type");
3938                         break;
3939                 }
3940                 temp_size += len;
3941         }
3942         *size = temp_size;
3943         return 0;
3944 }
3945
3946 static int
3947 flow_dv_zero_encap_udp_csum(void *data, struct rte_flow_error *error)
3948 {
3949         struct rte_ether_hdr *eth = NULL;
3950         struct rte_vlan_hdr *vlan = NULL;
3951         struct rte_ipv6_hdr *ipv6 = NULL;
3952         struct rte_udp_hdr *udp = NULL;
3953         char *next_hdr;
3954         uint16_t proto;
3955
3956         eth = (struct rte_ether_hdr *)data;
3957         next_hdr = (char *)(eth + 1);
3958         proto = RTE_BE16(eth->ether_type);
3959
3960         /* VLAN skipping */
3961         while (proto == RTE_ETHER_TYPE_VLAN || proto == RTE_ETHER_TYPE_QINQ) {
3962                 vlan = (struct rte_vlan_hdr *)next_hdr;
3963                 proto = RTE_BE16(vlan->eth_proto);
3964                 next_hdr += sizeof(struct rte_vlan_hdr);
3965         }
3966
3967         /* HW calculates IPv4 csum. no need to proceed */
3968         if (proto == RTE_ETHER_TYPE_IPV4)
3969                 return 0;
3970
3971         /* non IPv4/IPv6 header. not supported */
3972         if (proto != RTE_ETHER_TYPE_IPV6) {
3973                 return rte_flow_error_set(error, ENOTSUP,
3974                                           RTE_FLOW_ERROR_TYPE_ACTION,
3975                                           NULL, "Cannot offload non IPv4/IPv6");
3976         }
3977
3978         ipv6 = (struct rte_ipv6_hdr *)next_hdr;
3979
3980         /* ignore non UDP */
3981         if (ipv6->proto != IPPROTO_UDP)
3982                 return 0;
3983
3984         udp = (struct rte_udp_hdr *)(ipv6 + 1);
3985         udp->dgram_cksum = 0;
3986
3987         return 0;
3988 }
3989
3990 /**
3991  * Convert L2 encap action to DV specification.
3992  *
3993  * @param[in] dev
3994  *   Pointer to rte_eth_dev structure.
3995  * @param[in] action
3996  *   Pointer to action structure.
3997  * @param[in, out] dev_flow
3998  *   Pointer to the mlx5_flow.
3999  * @param[in] transfer
4000  *   Mark if the flow is E-Switch flow.
4001  * @param[out] error
4002  *   Pointer to the error structure.
4003  *
4004  * @return
4005  *   0 on success, a negative errno value otherwise and rte_errno is set.
4006  */
4007 static int
4008 flow_dv_create_action_l2_encap(struct rte_eth_dev *dev,
4009                                const struct rte_flow_action *action,
4010                                struct mlx5_flow *dev_flow,
4011                                uint8_t transfer,
4012                                struct rte_flow_error *error)
4013 {
4014         const struct rte_flow_item *encap_data;
4015         const struct rte_flow_action_raw_encap *raw_encap_data;
4016         struct mlx5_flow_dv_encap_decap_resource res = {
4017                 .reformat_type =
4018                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L2_TUNNEL,
4019                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4020                                       MLX5DV_FLOW_TABLE_TYPE_NIC_TX,
4021         };
4022
4023         if (action->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
4024                 raw_encap_data =
4025                         (const struct rte_flow_action_raw_encap *)action->conf;
4026                 res.size = raw_encap_data->size;
4027                 memcpy(res.buf, raw_encap_data->data, res.size);
4028         } else {
4029                 if (action->type == RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP)
4030                         encap_data =
4031                                 ((const struct rte_flow_action_vxlan_encap *)
4032                                                 action->conf)->definition;
4033                 else
4034                         encap_data =
4035                                 ((const struct rte_flow_action_nvgre_encap *)
4036                                                 action->conf)->definition;
4037                 if (flow_dv_convert_encap_data(encap_data, res.buf,
4038                                                &res.size, error))
4039                         return -rte_errno;
4040         }
4041         if (flow_dv_zero_encap_udp_csum(res.buf, error))
4042                 return -rte_errno;
4043         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4044                 return rte_flow_error_set(error, EINVAL,
4045                                           RTE_FLOW_ERROR_TYPE_ACTION,
4046                                           NULL, "can't create L2 encap action");
4047         return 0;
4048 }
4049
4050 /**
4051  * Convert L2 decap action to DV specification.
4052  *
4053  * @param[in] dev
4054  *   Pointer to rte_eth_dev structure.
4055  * @param[in, out] dev_flow
4056  *   Pointer to the mlx5_flow.
4057  * @param[in] transfer
4058  *   Mark if the flow is E-Switch flow.
4059  * @param[out] error
4060  *   Pointer to the error structure.
4061  *
4062  * @return
4063  *   0 on success, a negative errno value otherwise and rte_errno is set.
4064  */
4065 static int
4066 flow_dv_create_action_l2_decap(struct rte_eth_dev *dev,
4067                                struct mlx5_flow *dev_flow,
4068                                uint8_t transfer,
4069                                struct rte_flow_error *error)
4070 {
4071         struct mlx5_flow_dv_encap_decap_resource res = {
4072                 .size = 0,
4073                 .reformat_type =
4074                         MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TUNNEL_TO_L2,
4075                 .ft_type = transfer ? MLX5DV_FLOW_TABLE_TYPE_FDB :
4076                                       MLX5DV_FLOW_TABLE_TYPE_NIC_RX,
4077         };
4078
4079         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4080                 return rte_flow_error_set(error, EINVAL,
4081                                           RTE_FLOW_ERROR_TYPE_ACTION,
4082                                           NULL, "can't create L2 decap action");
4083         return 0;
4084 }
4085
4086 /**
4087  * Convert raw decap/encap (L3 tunnel) action to DV specification.
4088  *
4089  * @param[in] dev
4090  *   Pointer to rte_eth_dev structure.
4091  * @param[in] action
4092  *   Pointer to action structure.
4093  * @param[in, out] dev_flow
4094  *   Pointer to the mlx5_flow.
4095  * @param[in] attr
4096  *   Pointer to the flow attributes.
4097  * @param[out] error
4098  *   Pointer to the error structure.
4099  *
4100  * @return
4101  *   0 on success, a negative errno value otherwise and rte_errno is set.
4102  */
4103 static int
4104 flow_dv_create_action_raw_encap(struct rte_eth_dev *dev,
4105                                 const struct rte_flow_action *action,
4106                                 struct mlx5_flow *dev_flow,
4107                                 const struct rte_flow_attr *attr,
4108                                 struct rte_flow_error *error)
4109 {
4110         const struct rte_flow_action_raw_encap *encap_data;
4111         struct mlx5_flow_dv_encap_decap_resource res;
4112
4113         memset(&res, 0, sizeof(res));
4114         encap_data = (const struct rte_flow_action_raw_encap *)action->conf;
4115         res.size = encap_data->size;
4116         memcpy(res.buf, encap_data->data, res.size);
4117         res.reformat_type = res.size < MLX5_ENCAPSULATION_DECISION_SIZE ?
4118                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L3_TUNNEL_TO_L2 :
4119                 MLX5DV_FLOW_ACTION_PACKET_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
4120         if (attr->transfer)
4121                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4122         else
4123                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4124                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4125         if (flow_dv_encap_decap_resource_register(dev, &res, dev_flow, error))
4126                 return rte_flow_error_set(error, EINVAL,
4127                                           RTE_FLOW_ERROR_TYPE_ACTION,
4128                                           NULL, "can't create encap action");
4129         return 0;
4130 }
4131
4132 /**
4133  * Create action push VLAN.
4134  *
4135  * @param[in] dev
4136  *   Pointer to rte_eth_dev structure.
4137  * @param[in] attr
4138  *   Pointer to the flow attributes.
4139  * @param[in] vlan
4140  *   Pointer to the vlan to push to the Ethernet header.
4141  * @param[in, out] dev_flow
4142  *   Pointer to the mlx5_flow.
4143  * @param[out] error
4144  *   Pointer to the error structure.
4145  *
4146  * @return
4147  *   0 on success, a negative errno value otherwise and rte_errno is set.
4148  */
4149 static int
4150 flow_dv_create_action_push_vlan(struct rte_eth_dev *dev,
4151                                 const struct rte_flow_attr *attr,
4152                                 const struct rte_vlan_hdr *vlan,
4153                                 struct mlx5_flow *dev_flow,
4154                                 struct rte_flow_error *error)
4155 {
4156         struct mlx5_flow_dv_push_vlan_action_resource res;
4157
4158         memset(&res, 0, sizeof(res));
4159         res.vlan_tag =
4160                 rte_cpu_to_be_32(((uint32_t)vlan->eth_proto) << 16 |
4161                                  vlan->vlan_tci);
4162         if (attr->transfer)
4163                 res.ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
4164         else
4165                 res.ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
4166                                              MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
4167         return flow_dv_push_vlan_action_resource_register
4168                                             (dev, &res, dev_flow, error);
4169 }
4170
4171 /**
4172  * Validate the modify-header actions.
4173  *
4174  * @param[in] action_flags
4175  *   Holds the actions detected until now.
4176  * @param[in] action
4177  *   Pointer to the modify action.
4178  * @param[out] error
4179  *   Pointer to error structure.
4180  *
4181  * @return
4182  *   0 on success, a negative errno value otherwise and rte_errno is set.
4183  */
4184 static int
4185 flow_dv_validate_action_modify_hdr(const uint64_t action_flags,
4186                                    const struct rte_flow_action *action,
4187                                    struct rte_flow_error *error)
4188 {
4189         if (action->type != RTE_FLOW_ACTION_TYPE_DEC_TTL && !action->conf)
4190                 return rte_flow_error_set(error, EINVAL,
4191                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4192                                           NULL, "action configuration not set");
4193         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
4194                 return rte_flow_error_set(error, EINVAL,
4195                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4196                                           "can't have encap action before"
4197                                           " modify action");
4198         return 0;
4199 }
4200
4201 /**
4202  * Validate the modify-header MAC address actions.
4203  *
4204  * @param[in] action_flags
4205  *   Holds the actions detected until now.
4206  * @param[in] action
4207  *   Pointer to the modify action.
4208  * @param[in] item_flags
4209  *   Holds the items detected.
4210  * @param[out] error
4211  *   Pointer to error structure.
4212  *
4213  * @return
4214  *   0 on success, a negative errno value otherwise and rte_errno is set.
4215  */
4216 static int
4217 flow_dv_validate_action_modify_mac(const uint64_t action_flags,
4218                                    const struct rte_flow_action *action,
4219                                    const uint64_t item_flags,
4220                                    struct rte_flow_error *error)
4221 {
4222         int ret = 0;
4223
4224         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4225         if (!ret) {
4226                 if (!(item_flags & MLX5_FLOW_LAYER_L2))
4227                         return rte_flow_error_set(error, EINVAL,
4228                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4229                                                   NULL,
4230                                                   "no L2 item in pattern");
4231         }
4232         return ret;
4233 }
4234
4235 /**
4236  * Validate the modify-header IPv4 address actions.
4237  *
4238  * @param[in] action_flags
4239  *   Holds the actions detected until now.
4240  * @param[in] action
4241  *   Pointer to the modify action.
4242  * @param[in] item_flags
4243  *   Holds the items detected.
4244  * @param[out] error
4245  *   Pointer to error structure.
4246  *
4247  * @return
4248  *   0 on success, a negative errno value otherwise and rte_errno is set.
4249  */
4250 static int
4251 flow_dv_validate_action_modify_ipv4(const uint64_t action_flags,
4252                                     const struct rte_flow_action *action,
4253                                     const uint64_t item_flags,
4254                                     struct rte_flow_error *error)
4255 {
4256         int ret = 0;
4257         uint64_t layer;
4258
4259         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4260         if (!ret) {
4261                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4262                                  MLX5_FLOW_LAYER_INNER_L3_IPV4 :
4263                                  MLX5_FLOW_LAYER_OUTER_L3_IPV4;
4264                 if (!(item_flags & layer))
4265                         return rte_flow_error_set(error, EINVAL,
4266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4267                                                   NULL,
4268                                                   "no ipv4 item in pattern");
4269         }
4270         return ret;
4271 }
4272
4273 /**
4274  * Validate the modify-header IPv6 address actions.
4275  *
4276  * @param[in] action_flags
4277  *   Holds the actions detected until now.
4278  * @param[in] action
4279  *   Pointer to the modify action.
4280  * @param[in] item_flags
4281  *   Holds the items detected.
4282  * @param[out] error
4283  *   Pointer to error structure.
4284  *
4285  * @return
4286  *   0 on success, a negative errno value otherwise and rte_errno is set.
4287  */
4288 static int
4289 flow_dv_validate_action_modify_ipv6(const uint64_t action_flags,
4290                                     const struct rte_flow_action *action,
4291                                     const uint64_t item_flags,
4292                                     struct rte_flow_error *error)
4293 {
4294         int ret = 0;
4295         uint64_t layer;
4296
4297         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4298         if (!ret) {
4299                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4300                                  MLX5_FLOW_LAYER_INNER_L3_IPV6 :
4301                                  MLX5_FLOW_LAYER_OUTER_L3_IPV6;
4302                 if (!(item_flags & layer))
4303                         return rte_flow_error_set(error, EINVAL,
4304                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4305                                                   NULL,
4306                                                   "no ipv6 item in pattern");
4307         }
4308         return ret;
4309 }
4310
4311 /**
4312  * Validate the modify-header TP actions.
4313  *
4314  * @param[in] action_flags
4315  *   Holds the actions detected until now.
4316  * @param[in] action
4317  *   Pointer to the modify action.
4318  * @param[in] item_flags
4319  *   Holds the items detected.
4320  * @param[out] error
4321  *   Pointer to error structure.
4322  *
4323  * @return
4324  *   0 on success, a negative errno value otherwise and rte_errno is set.
4325  */
4326 static int
4327 flow_dv_validate_action_modify_tp(const uint64_t action_flags,
4328                                   const struct rte_flow_action *action,
4329                                   const uint64_t item_flags,
4330                                   struct rte_flow_error *error)
4331 {
4332         int ret = 0;
4333         uint64_t layer;
4334
4335         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4336         if (!ret) {
4337                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4338                                  MLX5_FLOW_LAYER_INNER_L4 :
4339                                  MLX5_FLOW_LAYER_OUTER_L4;
4340                 if (!(item_flags & layer))
4341                         return rte_flow_error_set(error, EINVAL,
4342                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4343                                                   NULL, "no transport layer "
4344                                                   "in pattern");
4345         }
4346         return ret;
4347 }
4348
4349 /**
4350  * Validate the modify-header actions of increment/decrement
4351  * TCP Sequence-number.
4352  *
4353  * @param[in] action_flags
4354  *   Holds the actions detected until now.
4355  * @param[in] action
4356  *   Pointer to the modify action.
4357  * @param[in] item_flags
4358  *   Holds the items detected.
4359  * @param[out] error
4360  *   Pointer to error structure.
4361  *
4362  * @return
4363  *   0 on success, a negative errno value otherwise and rte_errno is set.
4364  */
4365 static int
4366 flow_dv_validate_action_modify_tcp_seq(const uint64_t action_flags,
4367                                        const struct rte_flow_action *action,
4368                                        const uint64_t item_flags,
4369                                        struct rte_flow_error *error)
4370 {
4371         int ret = 0;
4372         uint64_t layer;
4373
4374         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4375         if (!ret) {
4376                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4377                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4378                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4379                 if (!(item_flags & layer))
4380                         return rte_flow_error_set(error, EINVAL,
4381                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4382                                                   NULL, "no TCP item in"
4383                                                   " pattern");
4384                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ &&
4385                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_SEQ)) ||
4386                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ &&
4387                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_SEQ)))
4388                         return rte_flow_error_set(error, EINVAL,
4389                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4390                                                   NULL,
4391                                                   "cannot decrease and increase"
4392                                                   " TCP sequence number"
4393                                                   " at the same time");
4394         }
4395         return ret;
4396 }
4397
4398 /**
4399  * Validate the modify-header actions of increment/decrement
4400  * TCP Acknowledgment number.
4401  *
4402  * @param[in] action_flags
4403  *   Holds the actions detected until now.
4404  * @param[in] action
4405  *   Pointer to the modify action.
4406  * @param[in] item_flags
4407  *   Holds the items detected.
4408  * @param[out] error
4409  *   Pointer to error structure.
4410  *
4411  * @return
4412  *   0 on success, a negative errno value otherwise and rte_errno is set.
4413  */
4414 static int
4415 flow_dv_validate_action_modify_tcp_ack(const uint64_t action_flags,
4416                                        const struct rte_flow_action *action,
4417                                        const uint64_t item_flags,
4418                                        struct rte_flow_error *error)
4419 {
4420         int ret = 0;
4421         uint64_t layer;
4422
4423         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4424         if (!ret) {
4425                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4426                                  MLX5_FLOW_LAYER_INNER_L4_TCP :
4427                                  MLX5_FLOW_LAYER_OUTER_L4_TCP;
4428                 if (!(item_flags & layer))
4429                         return rte_flow_error_set(error, EINVAL,
4430                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4431                                                   NULL, "no TCP item in"
4432                                                   " pattern");
4433                 if ((action->type == RTE_FLOW_ACTION_TYPE_INC_TCP_ACK &&
4434                         (action_flags & MLX5_FLOW_ACTION_DEC_TCP_ACK)) ||
4435                     (action->type == RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK &&
4436                         (action_flags & MLX5_FLOW_ACTION_INC_TCP_ACK)))
4437                         return rte_flow_error_set(error, EINVAL,
4438                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4439                                                   NULL,
4440                                                   "cannot decrease and increase"
4441                                                   " TCP acknowledgment number"
4442                                                   " at the same time");
4443         }
4444         return ret;
4445 }
4446
4447 /**
4448  * Validate the modify-header TTL actions.
4449  *
4450  * @param[in] action_flags
4451  *   Holds the actions detected until now.
4452  * @param[in] action
4453  *   Pointer to the modify action.
4454  * @param[in] item_flags
4455  *   Holds the items detected.
4456  * @param[out] error
4457  *   Pointer to error structure.
4458  *
4459  * @return
4460  *   0 on success, a negative errno value otherwise and rte_errno is set.
4461  */
4462 static int
4463 flow_dv_validate_action_modify_ttl(const uint64_t action_flags,
4464                                    const struct rte_flow_action *action,
4465                                    const uint64_t item_flags,
4466                                    struct rte_flow_error *error)
4467 {
4468         int ret = 0;
4469         uint64_t layer;
4470
4471         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4472         if (!ret) {
4473                 layer = (action_flags & MLX5_FLOW_ACTION_DECAP) ?
4474                                  MLX5_FLOW_LAYER_INNER_L3 :
4475                                  MLX5_FLOW_LAYER_OUTER_L3;
4476                 if (!(item_flags & layer))
4477                         return rte_flow_error_set(error, EINVAL,
4478                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4479                                                   NULL,
4480                                                   "no IP protocol in pattern");
4481         }
4482         return ret;
4483 }
4484
4485 static int
4486 mlx5_flow_item_field_width(enum rte_flow_field_id field)
4487 {
4488         switch (field) {
4489         case RTE_FLOW_FIELD_START:
4490                 return 32;
4491         case RTE_FLOW_FIELD_MAC_DST:
4492         case RTE_FLOW_FIELD_MAC_SRC:
4493                 return 48;
4494         case RTE_FLOW_FIELD_VLAN_TYPE:
4495                 return 16;
4496         case RTE_FLOW_FIELD_VLAN_ID:
4497                 return 12;
4498         case RTE_FLOW_FIELD_MAC_TYPE:
4499                 return 16;
4500         case RTE_FLOW_FIELD_IPV4_DSCP:
4501                 return 6;
4502         case RTE_FLOW_FIELD_IPV4_TTL:
4503                 return 8;
4504         case RTE_FLOW_FIELD_IPV4_SRC:
4505         case RTE_FLOW_FIELD_IPV4_DST:
4506                 return 32;
4507         case RTE_FLOW_FIELD_IPV6_DSCP:
4508                 return 6;
4509         case RTE_FLOW_FIELD_IPV6_HOPLIMIT:
4510                 return 8;
4511         case RTE_FLOW_FIELD_IPV6_SRC:
4512         case RTE_FLOW_FIELD_IPV6_DST:
4513                 return 128;
4514         case RTE_FLOW_FIELD_TCP_PORT_SRC:
4515         case RTE_FLOW_FIELD_TCP_PORT_DST:
4516                 return 16;
4517         case RTE_FLOW_FIELD_TCP_SEQ_NUM:
4518         case RTE_FLOW_FIELD_TCP_ACK_NUM:
4519                 return 32;
4520         case RTE_FLOW_FIELD_TCP_FLAGS:
4521                 return 6;
4522         case RTE_FLOW_FIELD_UDP_PORT_SRC:
4523         case RTE_FLOW_FIELD_UDP_PORT_DST:
4524                 return 16;
4525         case RTE_FLOW_FIELD_VXLAN_VNI:
4526         case RTE_FLOW_FIELD_GENEVE_VNI:
4527                 return 24;
4528         case RTE_FLOW_FIELD_GTP_TEID:
4529         case RTE_FLOW_FIELD_TAG:
4530                 return 32;
4531         case RTE_FLOW_FIELD_MARK:
4532                 return 24;
4533         case RTE_FLOW_FIELD_META:
4534         case RTE_FLOW_FIELD_POINTER:
4535         case RTE_FLOW_FIELD_VALUE:
4536                 return 32;
4537         default:
4538                 MLX5_ASSERT(false);
4539         }
4540         return 0;
4541 }
4542
4543 /**
4544  * Validate the generic modify field actions.
4545  * @param[in] dev
4546  *   Pointer to the rte_eth_dev structure.
4547  * @param[in] action_flags
4548  *   Holds the actions detected until now.
4549  * @param[in] action
4550  *   Pointer to the modify action.
4551  * @param[in] attr
4552  *   Pointer to the flow attributes.
4553  * @param[out] error
4554  *   Pointer to error structure.
4555  *
4556  * @return
4557  *   Number of header fields to modify (0 or more) on success,
4558  *   a negative errno value otherwise and rte_errno is set.
4559  */
4560 static int
4561 flow_dv_validate_action_modify_field(struct rte_eth_dev *dev,
4562                                    const uint64_t action_flags,
4563                                    const struct rte_flow_action *action,
4564                                    const struct rte_flow_attr *attr,
4565                                    struct rte_flow_error *error)
4566 {
4567         int ret = 0;
4568         struct mlx5_priv *priv = dev->data->dev_private;
4569         struct mlx5_dev_config *config = &priv->config;
4570         const struct rte_flow_action_modify_field *action_modify_field =
4571                 action->conf;
4572         uint32_t dst_width =
4573                 mlx5_flow_item_field_width(action_modify_field->dst.field);
4574         uint32_t src_width =
4575                 mlx5_flow_item_field_width(action_modify_field->src.field);
4576
4577         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4578         if (ret)
4579                 return ret;
4580
4581         if (action_modify_field->width == 0)
4582                 return rte_flow_error_set(error, EINVAL,
4583                                         RTE_FLOW_ERROR_TYPE_ACTION,
4584                                         NULL,
4585                                         "no bits are requested to be modified");
4586         else if (action_modify_field->width > dst_width ||
4587                  action_modify_field->width > src_width)
4588                 return rte_flow_error_set(error, EINVAL,
4589                                         RTE_FLOW_ERROR_TYPE_ACTION,
4590                                         NULL,
4591                                         "cannot modify more bits than"
4592                                         " the width of a field");
4593         if (action_modify_field->dst.field != RTE_FLOW_FIELD_VALUE &&
4594             action_modify_field->dst.field != RTE_FLOW_FIELD_POINTER) {
4595                 if ((action_modify_field->dst.offset +
4596                      action_modify_field->width > dst_width) ||
4597                     (action_modify_field->dst.offset % 32))
4598                         return rte_flow_error_set(error, EINVAL,
4599                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4600                                                 NULL,
4601                                                 "destination offset is too big"
4602                                                 " or not aligned to 4 bytes");
4603                 if (action_modify_field->dst.level &&
4604                     action_modify_field->dst.field != RTE_FLOW_FIELD_TAG)
4605                         return rte_flow_error_set(error, EINVAL,
4606                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4607                                                 NULL,
4608                                                 "cannot modify inner headers");
4609         }
4610         if (action_modify_field->src.field != RTE_FLOW_FIELD_VALUE &&
4611             action_modify_field->src.field != RTE_FLOW_FIELD_POINTER) {
4612                 if (!attr->transfer && !attr->group)
4613                         return rte_flow_error_set(error, ENOTSUP,
4614                                         RTE_FLOW_ERROR_TYPE_ACTION,
4615                                         NULL, "modify field action "
4616                                         "is not supported for group 0");
4617                 if ((action_modify_field->src.offset +
4618                      action_modify_field->width > src_width) ||
4619                     (action_modify_field->src.offset % 32))
4620                         return rte_flow_error_set(error, EINVAL,
4621                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4622                                                 NULL,
4623                                                 "source offset is too big"
4624                                                 " or not aligned to 4 bytes");
4625                 if (action_modify_field->src.level &&
4626                     action_modify_field->src.field != RTE_FLOW_FIELD_TAG)
4627                         return rte_flow_error_set(error, EINVAL,
4628                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4629                                                 NULL,
4630                                                 "cannot copy from inner headers");
4631         }
4632         if (action_modify_field->dst.field ==
4633             action_modify_field->src.field)
4634                 return rte_flow_error_set(error, EINVAL,
4635                                         RTE_FLOW_ERROR_TYPE_ACTION,
4636                                         NULL,
4637                                         "source and destination fields"
4638                                         " cannot be the same");
4639         if (action_modify_field->dst.field == RTE_FLOW_FIELD_VALUE ||
4640             action_modify_field->dst.field == RTE_FLOW_FIELD_POINTER)
4641                 return rte_flow_error_set(error, EINVAL,
4642                                         RTE_FLOW_ERROR_TYPE_ACTION,
4643                                         NULL,
4644                                         "immediate value or a pointer to it"
4645                                         " cannot be used as a destination");
4646         if (action_modify_field->dst.field == RTE_FLOW_FIELD_START ||
4647             action_modify_field->src.field == RTE_FLOW_FIELD_START)
4648                 return rte_flow_error_set(error, EINVAL,
4649                                 RTE_FLOW_ERROR_TYPE_ACTION,
4650                                 NULL,
4651                                 "modifications of an arbitrary"
4652                                 " place in a packet is not supported");
4653         if (action_modify_field->dst.field == RTE_FLOW_FIELD_MARK ||
4654             action_modify_field->src.field == RTE_FLOW_FIELD_MARK) {
4655                 if (config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY ||
4656                     !mlx5_flow_ext_mreg_supported(dev))
4657                         return rte_flow_error_set(error, ENOTSUP,
4658                                         RTE_FLOW_ERROR_TYPE_ACTION, action,
4659                                         "cannot modify mark without extended"
4660                                         " metadata register support");
4661         }
4662         if (action_modify_field->operation != RTE_FLOW_MODIFY_SET)
4663                 return rte_flow_error_set(error, EINVAL,
4664                                 RTE_FLOW_ERROR_TYPE_ACTION,
4665                                 NULL,
4666                                 "add and sub operations"
4667                                 " are not supported");
4668         return (action_modify_field->width / 32) +
4669                !!(action_modify_field->width % 32);
4670 }
4671
4672 /**
4673  * Validate jump action.
4674  *
4675  * @param[in] action
4676  *   Pointer to the jump action.
4677  * @param[in] action_flags
4678  *   Holds the actions detected until now.
4679  * @param[in] attributes
4680  *   Pointer to flow attributes
4681  * @param[in] external
4682  *   Action belongs to flow rule created by request external to PMD.
4683  * @param[out] error
4684  *   Pointer to error structure.
4685  *
4686  * @return
4687  *   0 on success, a negative errno value otherwise and rte_errno is set.
4688  */
4689 static int
4690 flow_dv_validate_action_jump(struct rte_eth_dev *dev,
4691                              const struct mlx5_flow_tunnel *tunnel,
4692                              const struct rte_flow_action *action,
4693                              uint64_t action_flags,
4694                              const struct rte_flow_attr *attributes,
4695                              bool external, struct rte_flow_error *error)
4696 {
4697         uint32_t target_group, table;
4698         int ret = 0;
4699         struct flow_grp_info grp_info = {
4700                 .external = !!external,
4701                 .transfer = !!attributes->transfer,
4702                 .fdb_def_rule = 1,
4703                 .std_tbl_fix = 0
4704         };
4705         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4706                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4707                 return rte_flow_error_set(error, EINVAL,
4708                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4709                                           "can't have 2 fate actions in"
4710                                           " same flow");
4711         if (action_flags & MLX5_FLOW_ACTION_METER)
4712                 return rte_flow_error_set(error, ENOTSUP,
4713                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4714                                           "jump with meter not support");
4715         if (!action->conf)
4716                 return rte_flow_error_set(error, EINVAL,
4717                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4718                                           NULL, "action configuration not set");
4719         target_group =
4720                 ((const struct rte_flow_action_jump *)action->conf)->group;
4721         ret = mlx5_flow_group_to_table(dev, tunnel, target_group, &table,
4722                                        &grp_info, error);
4723         if (ret)
4724                 return ret;
4725         if (attributes->group == target_group &&
4726             !(action_flags & (MLX5_FLOW_ACTION_TUNNEL_SET |
4727                               MLX5_FLOW_ACTION_TUNNEL_MATCH)))
4728                 return rte_flow_error_set(error, EINVAL,
4729                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4730                                           "target group must be other than"
4731                                           " the current flow group");
4732         return 0;
4733 }
4734
4735 /*
4736  * Validate the port_id action.
4737  *
4738  * @param[in] dev
4739  *   Pointer to rte_eth_dev structure.
4740  * @param[in] action_flags
4741  *   Bit-fields that holds the actions detected until now.
4742  * @param[in] action
4743  *   Port_id RTE action structure.
4744  * @param[in] attr
4745  *   Attributes of flow that includes this action.
4746  * @param[out] error
4747  *   Pointer to error structure.
4748  *
4749  * @return
4750  *   0 on success, a negative errno value otherwise and rte_errno is set.
4751  */
4752 static int
4753 flow_dv_validate_action_port_id(struct rte_eth_dev *dev,
4754                                 uint64_t action_flags,
4755                                 const struct rte_flow_action *action,
4756                                 const struct rte_flow_attr *attr,
4757                                 struct rte_flow_error *error)
4758 {
4759         const struct rte_flow_action_port_id *port_id;
4760         struct mlx5_priv *act_priv;
4761         struct mlx5_priv *dev_priv;
4762         uint16_t port;
4763
4764         if (!attr->transfer)
4765                 return rte_flow_error_set(error, ENOTSUP,
4766                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4767                                           NULL,
4768                                           "port id action is valid in transfer"
4769                                           " mode only");
4770         if (!action || !action->conf)
4771                 return rte_flow_error_set(error, ENOTSUP,
4772                                           RTE_FLOW_ERROR_TYPE_ACTION_CONF,
4773                                           NULL,
4774                                           "port id action parameters must be"
4775                                           " specified");
4776         if (action_flags & (MLX5_FLOW_FATE_ACTIONS |
4777                             MLX5_FLOW_FATE_ESWITCH_ACTIONS))
4778                 return rte_flow_error_set(error, EINVAL,
4779                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4780                                           "can have only one fate actions in"
4781                                           " a flow");
4782         dev_priv = mlx5_dev_to_eswitch_info(dev);
4783         if (!dev_priv)
4784                 return rte_flow_error_set(error, rte_errno,
4785                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4786                                           NULL,
4787                                           "failed to obtain E-Switch info");
4788         port_id = action->conf;
4789         port = port_id->original ? dev->data->port_id : port_id->id;
4790         act_priv = mlx5_port_to_eswitch_info(port, false);
4791         if (!act_priv)
4792                 return rte_flow_error_set
4793                                 (error, rte_errno,
4794                                  RTE_FLOW_ERROR_TYPE_ACTION_CONF, port_id,
4795                                  "failed to obtain E-Switch port id for port");
4796         if (act_priv->domain_id != dev_priv->domain_id)
4797                 return rte_flow_error_set
4798                                 (error, EINVAL,
4799                                  RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4800                                  "port does not belong to"
4801                                  " E-Switch being configured");
4802         return 0;
4803 }
4804
4805 /**
4806  * Get the maximum number of modify header actions.
4807  *
4808  * @param dev
4809  *   Pointer to rte_eth_dev structure.
4810  * @param flags
4811  *   Flags bits to check if root level.
4812  *
4813  * @return
4814  *   Max number of modify header actions device can support.
4815  */
4816 static inline unsigned int
4817 flow_dv_modify_hdr_action_max(struct rte_eth_dev *dev __rte_unused,
4818                               uint64_t flags)
4819 {
4820         /*
4821          * There's no way to directly query the max capacity from FW.
4822          * The maximal value on root table should be assumed to be supported.
4823          */
4824         if (!(flags & MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL))
4825                 return MLX5_MAX_MODIFY_NUM;
4826         else
4827                 return MLX5_ROOT_TBL_MODIFY_NUM;
4828 }
4829
4830 /**
4831  * Validate the meter action.
4832  *
4833  * @param[in] dev
4834  *   Pointer to rte_eth_dev structure.
4835  * @param[in] action_flags
4836  *   Bit-fields that holds the actions detected until now.
4837  * @param[in] action
4838  *   Pointer to the meter action.
4839  * @param[in] attr
4840  *   Attributes of flow that includes this action.
4841  * @param[out] error
4842  *   Pointer to error structure.
4843  *
4844  * @return
4845  *   0 on success, a negative errno value otherwise and rte_ernno is set.
4846  */
4847 static int
4848 mlx5_flow_validate_action_meter(struct rte_eth_dev *dev,
4849                                 uint64_t action_flags,
4850                                 const struct rte_flow_action *action,
4851                                 const struct rte_flow_attr *attr,
4852                                 struct rte_flow_error *error)
4853 {
4854         struct mlx5_priv *priv = dev->data->dev_private;
4855         const struct rte_flow_action_meter *am = action->conf;
4856         struct mlx5_flow_meter *fm;
4857
4858         if (!am)
4859                 return rte_flow_error_set(error, EINVAL,
4860                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4861                                           "meter action conf is NULL");
4862
4863         if (action_flags & MLX5_FLOW_ACTION_METER)
4864                 return rte_flow_error_set(error, ENOTSUP,
4865                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4866                                           "meter chaining not support");
4867         if (action_flags & MLX5_FLOW_ACTION_JUMP)
4868                 return rte_flow_error_set(error, ENOTSUP,
4869                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4870                                           "meter with jump not support");
4871         if (!priv->mtr_en)
4872                 return rte_flow_error_set(error, ENOTSUP,
4873                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4874                                           NULL,
4875                                           "meter action not supported");
4876         fm = mlx5_flow_meter_find(priv, am->mtr_id);
4877         if (!fm)
4878                 return rte_flow_error_set(error, EINVAL,
4879                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4880                                           "Meter not found");
4881         if (fm->ref_cnt && (!(fm->transfer == attr->transfer ||
4882               (!fm->ingress && !attr->ingress && attr->egress) ||
4883               (!fm->egress && !attr->egress && attr->ingress))))
4884                 return rte_flow_error_set(error, EINVAL,
4885                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4886                                           "Flow attributes are either invalid "
4887                                           "or have a conflict with current "
4888                                           "meter attributes");
4889         return 0;
4890 }
4891
4892 /**
4893  * Validate the age action.
4894  *
4895  * @param[in] action_flags
4896  *   Holds the actions detected until now.
4897  * @param[in] action
4898  *   Pointer to the age action.
4899  * @param[in] dev
4900  *   Pointer to the Ethernet device structure.
4901  * @param[out] error
4902  *   Pointer to error structure.
4903  *
4904  * @return
4905  *   0 on success, a negative errno value otherwise and rte_errno is set.
4906  */
4907 static int
4908 flow_dv_validate_action_age(uint64_t action_flags,
4909                             const struct rte_flow_action *action,
4910                             struct rte_eth_dev *dev,
4911                             struct rte_flow_error *error)
4912 {
4913         struct mlx5_priv *priv = dev->data->dev_private;
4914         const struct rte_flow_action_age *age = action->conf;
4915
4916         if (!priv->config.devx || (priv->sh->cmng.counter_fallback &&
4917             !priv->sh->aso_age_mng))
4918                 return rte_flow_error_set(error, ENOTSUP,
4919                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
4920                                           NULL,
4921                                           "age action not supported");
4922         if (!(action->conf))
4923                 return rte_flow_error_set(error, EINVAL,
4924                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4925                                           "configuration cannot be null");
4926         if (!(age->timeout))
4927                 return rte_flow_error_set(error, EINVAL,
4928                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
4929                                           "invalid timeout value 0");
4930         if (action_flags & MLX5_FLOW_ACTION_AGE)
4931                 return rte_flow_error_set(error, EINVAL,
4932                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
4933                                           "duplicate age actions set");
4934         return 0;
4935 }
4936
4937 /**
4938  * Validate the modify-header IPv4 DSCP actions.
4939  *
4940  * @param[in] action_flags
4941  *   Holds the actions detected until now.
4942  * @param[in] action
4943  *   Pointer to the modify action.
4944  * @param[in] item_flags
4945  *   Holds the items detected.
4946  * @param[out] error
4947  *   Pointer to error structure.
4948  *
4949  * @return
4950  *   0 on success, a negative errno value otherwise and rte_errno is set.
4951  */
4952 static int
4953 flow_dv_validate_action_modify_ipv4_dscp(const uint64_t action_flags,
4954                                          const struct rte_flow_action *action,
4955                                          const uint64_t item_flags,
4956                                          struct rte_flow_error *error)
4957 {
4958         int ret = 0;
4959
4960         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4961         if (!ret) {
4962                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV4))
4963                         return rte_flow_error_set(error, EINVAL,
4964                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4965                                                   NULL,
4966                                                   "no ipv4 item in pattern");
4967         }
4968         return ret;
4969 }
4970
4971 /**
4972  * Validate the modify-header IPv6 DSCP actions.
4973  *
4974  * @param[in] action_flags
4975  *   Holds the actions detected until now.
4976  * @param[in] action
4977  *   Pointer to the modify action.
4978  * @param[in] item_flags
4979  *   Holds the items detected.
4980  * @param[out] error
4981  *   Pointer to error structure.
4982  *
4983  * @return
4984  *   0 on success, a negative errno value otherwise and rte_errno is set.
4985  */
4986 static int
4987 flow_dv_validate_action_modify_ipv6_dscp(const uint64_t action_flags,
4988                                          const struct rte_flow_action *action,
4989                                          const uint64_t item_flags,
4990                                          struct rte_flow_error *error)
4991 {
4992         int ret = 0;
4993
4994         ret = flow_dv_validate_action_modify_hdr(action_flags, action, error);
4995         if (!ret) {
4996                 if (!(item_flags & MLX5_FLOW_LAYER_L3_IPV6))
4997                         return rte_flow_error_set(error, EINVAL,
4998                                                   RTE_FLOW_ERROR_TYPE_ACTION,
4999                                                   NULL,
5000                                                   "no ipv6 item in pattern");
5001         }
5002         return ret;
5003 }
5004
5005 /**
5006  * Match modify-header resource.
5007  *
5008  * @param list
5009  *   Pointer to the hash list.
5010  * @param entry
5011  *   Pointer to exist resource entry object.
5012  * @param key
5013  *   Key of the new entry.
5014  * @param ctx
5015  *   Pointer to new modify-header resource.
5016  *
5017  * @return
5018  *   0 on matching, non-zero otherwise.
5019  */
5020 int
5021 flow_dv_modify_match_cb(struct mlx5_hlist *list __rte_unused,
5022                         struct mlx5_hlist_entry *entry,
5023                         uint64_t key __rte_unused, void *cb_ctx)
5024 {
5025         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5026         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5027         struct mlx5_flow_dv_modify_hdr_resource *resource =
5028                         container_of(entry, typeof(*resource), entry);
5029         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5030
5031         key_len += ref->actions_num * sizeof(ref->actions[0]);
5032         return ref->actions_num != resource->actions_num ||
5033                memcmp(&ref->ft_type, &resource->ft_type, key_len);
5034 }
5035
5036 struct mlx5_hlist_entry *
5037 flow_dv_modify_create_cb(struct mlx5_hlist *list, uint64_t key __rte_unused,
5038                          void *cb_ctx)
5039 {
5040         struct mlx5_dev_ctx_shared *sh = list->ctx;
5041         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
5042         struct mlx5dv_dr_domain *ns;
5043         struct mlx5_flow_dv_modify_hdr_resource *entry;
5044         struct mlx5_flow_dv_modify_hdr_resource *ref = ctx->data;
5045         int ret;
5046         uint32_t data_len = ref->actions_num * sizeof(ref->actions[0]);
5047         uint32_t key_len = sizeof(*ref) - offsetof(typeof(*ref), ft_type);
5048
5049         entry = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*entry) + data_len, 0,
5050                             SOCKET_ID_ANY);
5051         if (!entry) {
5052                 rte_flow_error_set(ctx->error, ENOMEM,
5053                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5054                                    "cannot allocate resource memory");
5055                 return NULL;
5056         }
5057         rte_memcpy(&entry->ft_type,
5058                    RTE_PTR_ADD(ref, offsetof(typeof(*ref), ft_type)),
5059                    key_len + data_len);
5060         if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
5061                 ns = sh->fdb_domain;
5062         else if (entry->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
5063                 ns = sh->tx_domain;
5064         else
5065                 ns = sh->rx_domain;
5066         ret = mlx5_flow_os_create_flow_action_modify_header
5067                                         (sh->ctx, ns, entry,
5068                                          data_len, &entry->action);
5069         if (ret) {
5070                 mlx5_free(entry);
5071                 rte_flow_error_set(ctx->error, ENOMEM,
5072                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5073                                    NULL, "cannot create modification action");
5074                 return NULL;
5075         }
5076         return &entry->entry;
5077 }
5078
5079 /**
5080  * Validate the sample action.
5081  *
5082  * @param[in, out] action_flags
5083  *   Holds the actions detected until now.
5084  * @param[in] action
5085  *   Pointer to the sample action.
5086  * @param[in] dev
5087  *   Pointer to the Ethernet device structure.
5088  * @param[in] attr
5089  *   Attributes of flow that includes this action.
5090  * @param[in] item_flags
5091  *   Holds the items detected.
5092  * @param[in] rss
5093  *   Pointer to the RSS action.
5094  * @param[out] sample_rss
5095  *   Pointer to the RSS action in sample action list.
5096  * @param[out] count
5097  *   Pointer to the COUNT action in sample action list.
5098  * @param[out] fdb_mirror_limit
5099  *   Pointer to the FDB mirror limitation flag.
5100  * @param[out] error
5101  *   Pointer to error structure.
5102  *
5103  * @return
5104  *   0 on success, a negative errno value otherwise and rte_errno is set.
5105  */
5106 static int
5107 flow_dv_validate_action_sample(uint64_t *action_flags,
5108                                const struct rte_flow_action *action,
5109                                struct rte_eth_dev *dev,
5110                                const struct rte_flow_attr *attr,
5111                                uint64_t item_flags,
5112                                const struct rte_flow_action_rss *rss,
5113                                const struct rte_flow_action_rss **sample_rss,
5114                                const struct rte_flow_action_count **count,
5115                                int *fdb_mirror_limit,
5116                                struct rte_flow_error *error)
5117 {
5118         struct mlx5_priv *priv = dev->data->dev_private;
5119         struct mlx5_dev_config *dev_conf = &priv->config;
5120         const struct rte_flow_action_sample *sample = action->conf;
5121         const struct rte_flow_action *act;
5122         uint64_t sub_action_flags = 0;
5123         uint16_t queue_index = 0xFFFF;
5124         int actions_n = 0;
5125         int ret;
5126
5127         if (!sample)
5128                 return rte_flow_error_set(error, EINVAL,
5129                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5130                                           "configuration cannot be NULL");
5131         if (sample->ratio == 0)
5132                 return rte_flow_error_set(error, EINVAL,
5133                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5134                                           "ratio value starts from 1");
5135         if (!priv->config.devx || (sample->ratio > 0 && !priv->sampler_en))
5136                 return rte_flow_error_set(error, ENOTSUP,
5137                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5138                                           NULL,
5139                                           "sample action not supported");
5140         if (*action_flags & MLX5_FLOW_ACTION_SAMPLE)
5141                 return rte_flow_error_set(error, EINVAL,
5142                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5143                                           "Multiple sample actions not "
5144                                           "supported");
5145         if (*action_flags & MLX5_FLOW_ACTION_METER)
5146                 return rte_flow_error_set(error, EINVAL,
5147                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5148                                           "wrong action order, meter should "
5149                                           "be after sample action");
5150         if (*action_flags & MLX5_FLOW_ACTION_JUMP)
5151                 return rte_flow_error_set(error, EINVAL,
5152                                           RTE_FLOW_ERROR_TYPE_ACTION, action,
5153                                           "wrong action order, jump should "
5154                                           "be after sample action");
5155         act = sample->actions;
5156         for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) {
5157                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
5158                         return rte_flow_error_set(error, ENOTSUP,
5159                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5160                                                   act, "too many actions");
5161                 switch (act->type) {
5162                 case RTE_FLOW_ACTION_TYPE_QUEUE:
5163                         ret = mlx5_flow_validate_action_queue(act,
5164                                                               sub_action_flags,
5165                                                               dev,
5166                                                               attr, error);
5167                         if (ret < 0)
5168                                 return ret;
5169                         queue_index = ((const struct rte_flow_action_queue *)
5170                                                         (act->conf))->index;
5171                         sub_action_flags |= MLX5_FLOW_ACTION_QUEUE;
5172                         ++actions_n;
5173                         break;
5174                 case RTE_FLOW_ACTION_TYPE_RSS:
5175                         *sample_rss = act->conf;
5176                         ret = mlx5_flow_validate_action_rss(act,
5177                                                             sub_action_flags,
5178                                                             dev, attr,
5179                                                             item_flags,
5180                                                             error);
5181                         if (ret < 0)
5182                                 return ret;
5183                         if (rss && *sample_rss &&
5184                             ((*sample_rss)->level != rss->level ||
5185                             (*sample_rss)->types != rss->types))
5186                                 return rte_flow_error_set(error, ENOTSUP,
5187                                         RTE_FLOW_ERROR_TYPE_ACTION,
5188                                         NULL,
5189                                         "Can't use the different RSS types "
5190                                         "or level in the same flow");
5191                         if (*sample_rss != NULL && (*sample_rss)->queue_num)
5192                                 queue_index = (*sample_rss)->queue[0];
5193                         sub_action_flags |= MLX5_FLOW_ACTION_RSS;
5194                         ++actions_n;
5195                         break;
5196                 case RTE_FLOW_ACTION_TYPE_MARK:
5197                         ret = flow_dv_validate_action_mark(dev, act,
5198                                                            sub_action_flags,
5199                                                            attr, error);
5200                         if (ret < 0)
5201                                 return ret;
5202                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY)
5203                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK |
5204                                                 MLX5_FLOW_ACTION_MARK_EXT;
5205                         else
5206                                 sub_action_flags |= MLX5_FLOW_ACTION_MARK;
5207                         ++actions_n;
5208                         break;
5209                 case RTE_FLOW_ACTION_TYPE_COUNT:
5210                         ret = flow_dv_validate_action_count
5211                                 (dev, act,
5212                                  *action_flags | sub_action_flags,
5213                                  error);
5214                         if (ret < 0)
5215                                 return ret;
5216                         *count = act->conf;
5217                         sub_action_flags |= MLX5_FLOW_ACTION_COUNT;
5218                         *action_flags |= MLX5_FLOW_ACTION_COUNT;
5219                         ++actions_n;
5220                         break;
5221                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
5222                         ret = flow_dv_validate_action_port_id(dev,
5223                                                               sub_action_flags,
5224                                                               act,
5225                                                               attr,
5226                                                               error);
5227                         if (ret)
5228                                 return ret;
5229                         sub_action_flags |= MLX5_FLOW_ACTION_PORT_ID;
5230                         ++actions_n;
5231                         break;
5232                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
5233                         ret = flow_dv_validate_action_raw_encap_decap
5234                                 (dev, NULL, act->conf, attr, &sub_action_flags,
5235                                  &actions_n, action, item_flags, error);
5236                         if (ret < 0)
5237                                 return ret;
5238                         ++actions_n;
5239                         break;
5240                 default:
5241                         return rte_flow_error_set(error, ENOTSUP,
5242                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5243                                                   NULL,
5244                                                   "Doesn't support optional "
5245                                                   "action");
5246                 }
5247         }
5248         if (attr->ingress && !attr->transfer) {
5249                 if (!(sub_action_flags & (MLX5_FLOW_ACTION_QUEUE |
5250                                           MLX5_FLOW_ACTION_RSS)))
5251                         return rte_flow_error_set(error, EINVAL,
5252                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5253                                                   NULL,
5254                                                   "Ingress must has a dest "
5255                                                   "QUEUE for Sample");
5256         } else if (attr->egress && !attr->transfer) {
5257                 return rte_flow_error_set(error, ENOTSUP,
5258                                           RTE_FLOW_ERROR_TYPE_ACTION,
5259                                           NULL,
5260                                           "Sample Only support Ingress "
5261                                           "or E-Switch");
5262         } else if (sample->actions->type != RTE_FLOW_ACTION_TYPE_END) {
5263                 MLX5_ASSERT(attr->transfer);
5264                 if (sample->ratio > 1)
5265                         return rte_flow_error_set(error, ENOTSUP,
5266                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5267                                                   NULL,
5268                                                   "E-Switch doesn't support "
5269                                                   "any optional action "
5270                                                   "for sampling");
5271                 if (sub_action_flags & MLX5_FLOW_ACTION_QUEUE)
5272                         return rte_flow_error_set(error, ENOTSUP,
5273                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5274                                                   NULL,
5275                                                   "unsupported action QUEUE");
5276                 if (sub_action_flags & MLX5_FLOW_ACTION_RSS)
5277                         return rte_flow_error_set(error, ENOTSUP,
5278                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5279                                                   NULL,
5280                                                   "unsupported action QUEUE");
5281                 if (!(sub_action_flags & MLX5_FLOW_ACTION_PORT_ID))
5282                         return rte_flow_error_set(error, EINVAL,
5283                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5284                                                   NULL,
5285                                                   "E-Switch must has a dest "
5286                                                   "port for mirroring");
5287                 if (!priv->config.hca_attr.reg_c_preserve &&
5288                      priv->representor_id != -1)
5289                         *fdb_mirror_limit = 1;
5290         }
5291         /* Continue validation for Xcap actions.*/
5292         if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) &&
5293             (queue_index == 0xFFFF ||
5294              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN)) {
5295                 if ((sub_action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
5296                      MLX5_FLOW_XCAP_ACTIONS)
5297                         return rte_flow_error_set(error, ENOTSUP,
5298                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5299                                                   NULL, "encap and decap "
5300                                                   "combination aren't "
5301                                                   "supported");
5302                 if (!attr->transfer && attr->ingress && (sub_action_flags &
5303                                                         MLX5_FLOW_ACTION_ENCAP))
5304                         return rte_flow_error_set(error, ENOTSUP,
5305                                                   RTE_FLOW_ERROR_TYPE_ACTION,
5306                                                   NULL, "encap is not supported"
5307                                                   " for ingress traffic");
5308         }
5309         return 0;
5310 }
5311
5312 /**
5313  * Find existing modify-header resource or create and register a new one.
5314  *
5315  * @param dev[in, out]
5316  *   Pointer to rte_eth_dev structure.
5317  * @param[in, out] resource
5318  *   Pointer to modify-header resource.
5319  * @parm[in, out] dev_flow
5320  *   Pointer to the dev_flow.
5321  * @param[out] error
5322  *   pointer to error structure.
5323  *
5324  * @return
5325  *   0 on success otherwise -errno and errno is set.
5326  */
5327 static int
5328 flow_dv_modify_hdr_resource_register
5329                         (struct rte_eth_dev *dev,
5330                          struct mlx5_flow_dv_modify_hdr_resource *resource,
5331                          struct mlx5_flow *dev_flow,
5332                          struct rte_flow_error *error)
5333 {
5334         struct mlx5_priv *priv = dev->data->dev_private;
5335         struct mlx5_dev_ctx_shared *sh = priv->sh;
5336         uint32_t key_len = sizeof(*resource) -
5337                            offsetof(typeof(*resource), ft_type) +
5338                            resource->actions_num * sizeof(resource->actions[0]);
5339         struct mlx5_hlist_entry *entry;
5340         struct mlx5_flow_cb_ctx ctx = {
5341                 .error = error,
5342                 .data = resource,
5343         };
5344         uint64_t key64;
5345
5346         resource->flags = dev_flow->dv.group ? 0 :
5347                           MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5348         if (resource->actions_num > flow_dv_modify_hdr_action_max(dev,
5349                                     resource->flags))
5350                 return rte_flow_error_set(error, EOVERFLOW,
5351                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
5352                                           "too many modify header items");
5353         key64 = __rte_raw_cksum(&resource->ft_type, key_len, 0);
5354         entry = mlx5_hlist_register(sh->modify_cmds, key64, &ctx);
5355         if (!entry)
5356                 return -rte_errno;
5357         resource = container_of(entry, typeof(*resource), entry);
5358         dev_flow->handle->dvh.modify_hdr = resource;
5359         return 0;
5360 }
5361
5362 /**
5363  * Get DV flow counter by index.
5364  *
5365  * @param[in] dev
5366  *   Pointer to the Ethernet device structure.
5367  * @param[in] idx
5368  *   mlx5 flow counter index in the container.
5369  * @param[out] ppool
5370  *   mlx5 flow counter pool in the container,
5371  *
5372  * @return
5373  *   Pointer to the counter, NULL otherwise.
5374  */
5375 static struct mlx5_flow_counter *
5376 flow_dv_counter_get_by_idx(struct rte_eth_dev *dev,
5377                            uint32_t idx,
5378                            struct mlx5_flow_counter_pool **ppool)
5379 {
5380         struct mlx5_priv *priv = dev->data->dev_private;
5381         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5382         struct mlx5_flow_counter_pool *pool;
5383
5384         /* Decrease to original index and clear shared bit. */
5385         idx = (idx - 1) & (MLX5_CNT_SHARED_OFFSET - 1);
5386         MLX5_ASSERT(idx / MLX5_COUNTERS_PER_POOL < cmng->n);
5387         pool = cmng->pools[idx / MLX5_COUNTERS_PER_POOL];
5388         MLX5_ASSERT(pool);
5389         if (ppool)
5390                 *ppool = pool;
5391         return MLX5_POOL_GET_CNT(pool, idx % MLX5_COUNTERS_PER_POOL);
5392 }
5393
5394 /**
5395  * Check the devx counter belongs to the pool.
5396  *
5397  * @param[in] pool
5398  *   Pointer to the counter pool.
5399  * @param[in] id
5400  *   The counter devx ID.
5401  *
5402  * @return
5403  *   True if counter belongs to the pool, false otherwise.
5404  */
5405 static bool
5406 flow_dv_is_counter_in_pool(struct mlx5_flow_counter_pool *pool, int id)
5407 {
5408         int base = (pool->min_dcs->id / MLX5_COUNTERS_PER_POOL) *
5409                    MLX5_COUNTERS_PER_POOL;
5410
5411         if (id >= base && id < base + MLX5_COUNTERS_PER_POOL)
5412                 return true;
5413         return false;
5414 }
5415
5416 /**
5417  * Get a pool by devx counter ID.
5418  *
5419  * @param[in] cmng
5420  *   Pointer to the counter management.
5421  * @param[in] id
5422  *   The counter devx ID.
5423  *
5424  * @return
5425  *   The counter pool pointer if exists, NULL otherwise,
5426  */
5427 static struct mlx5_flow_counter_pool *
5428 flow_dv_find_pool_by_id(struct mlx5_flow_counter_mng *cmng, int id)
5429 {
5430         uint32_t i;
5431         struct mlx5_flow_counter_pool *pool = NULL;
5432
5433         rte_spinlock_lock(&cmng->pool_update_sl);
5434         /* Check last used pool. */
5435         if (cmng->last_pool_idx != POOL_IDX_INVALID &&
5436             flow_dv_is_counter_in_pool(cmng->pools[cmng->last_pool_idx], id)) {
5437                 pool = cmng->pools[cmng->last_pool_idx];
5438                 goto out;
5439         }
5440         /* ID out of range means no suitable pool in the container. */
5441         if (id > cmng->max_id || id < cmng->min_id)
5442                 goto out;
5443         /*
5444          * Find the pool from the end of the container, since mostly counter
5445          * ID is sequence increasing, and the last pool should be the needed
5446          * one.
5447          */
5448         i = cmng->n_valid;
5449         while (i--) {
5450                 struct mlx5_flow_counter_pool *pool_tmp = cmng->pools[i];
5451
5452                 if (flow_dv_is_counter_in_pool(pool_tmp, id)) {
5453                         pool = pool_tmp;
5454                         break;
5455                 }
5456         }
5457 out:
5458         rte_spinlock_unlock(&cmng->pool_update_sl);
5459         return pool;
5460 }
5461
5462 /**
5463  * Resize a counter container.
5464  *
5465  * @param[in] dev
5466  *   Pointer to the Ethernet device structure.
5467  *
5468  * @return
5469  *   0 on success, otherwise negative errno value and rte_errno is set.
5470  */
5471 static int
5472 flow_dv_container_resize(struct rte_eth_dev *dev)
5473 {
5474         struct mlx5_priv *priv = dev->data->dev_private;
5475         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5476         void *old_pools = cmng->pools;
5477         uint32_t resize = cmng->n + MLX5_CNT_CONTAINER_RESIZE;
5478         uint32_t mem_size = sizeof(struct mlx5_flow_counter_pool *) * resize;
5479         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
5480
5481         if (!pools) {
5482                 rte_errno = ENOMEM;
5483                 return -ENOMEM;
5484         }
5485         if (old_pools)
5486                 memcpy(pools, old_pools, cmng->n *
5487                                        sizeof(struct mlx5_flow_counter_pool *));
5488         cmng->n = resize;
5489         cmng->pools = pools;
5490         if (old_pools)
5491                 mlx5_free(old_pools);
5492         return 0;
5493 }
5494
5495 /**
5496  * Query a devx flow counter.
5497  *
5498  * @param[in] dev
5499  *   Pointer to the Ethernet device structure.
5500  * @param[in] cnt
5501  *   Index to the flow counter.
5502  * @param[out] pkts
5503  *   The statistics value of packets.
5504  * @param[out] bytes
5505  *   The statistics value of bytes.
5506  *
5507  * @return
5508  *   0 on success, otherwise a negative errno value and rte_errno is set.
5509  */
5510 static inline int
5511 _flow_dv_query_count(struct rte_eth_dev *dev, uint32_t counter, uint64_t *pkts,
5512                      uint64_t *bytes)
5513 {
5514         struct mlx5_priv *priv = dev->data->dev_private;
5515         struct mlx5_flow_counter_pool *pool = NULL;
5516         struct mlx5_flow_counter *cnt;
5517         int offset;
5518
5519         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5520         MLX5_ASSERT(pool);
5521         if (priv->sh->cmng.counter_fallback)
5522                 return mlx5_devx_cmd_flow_counter_query(cnt->dcs_when_active, 0,
5523                                         0, pkts, bytes, 0, NULL, NULL, 0);
5524         rte_spinlock_lock(&pool->sl);
5525         if (!pool->raw) {
5526                 *pkts = 0;
5527                 *bytes = 0;
5528         } else {
5529                 offset = MLX5_CNT_ARRAY_IDX(pool, cnt);
5530                 *pkts = rte_be_to_cpu_64(pool->raw->data[offset].hits);
5531                 *bytes = rte_be_to_cpu_64(pool->raw->data[offset].bytes);
5532         }
5533         rte_spinlock_unlock(&pool->sl);
5534         return 0;
5535 }
5536
5537 /**
5538  * Create and initialize a new counter pool.
5539  *
5540  * @param[in] dev
5541  *   Pointer to the Ethernet device structure.
5542  * @param[out] dcs
5543  *   The devX counter handle.
5544  * @param[in] age
5545  *   Whether the pool is for counter that was allocated for aging.
5546  * @param[in/out] cont_cur
5547  *   Pointer to the container pointer, it will be update in pool resize.
5548  *
5549  * @return
5550  *   The pool container pointer on success, NULL otherwise and rte_errno is set.
5551  */
5552 static struct mlx5_flow_counter_pool *
5553 flow_dv_pool_create(struct rte_eth_dev *dev, struct mlx5_devx_obj *dcs,
5554                     uint32_t age)
5555 {
5556         struct mlx5_priv *priv = dev->data->dev_private;
5557         struct mlx5_flow_counter_pool *pool;
5558         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5559         bool fallback = priv->sh->cmng.counter_fallback;
5560         uint32_t size = sizeof(*pool);
5561
5562         size += MLX5_COUNTERS_PER_POOL * MLX5_CNT_SIZE;
5563         size += (!age ? 0 : MLX5_COUNTERS_PER_POOL * MLX5_AGE_SIZE);
5564         pool = mlx5_malloc(MLX5_MEM_ZERO, size, 0, SOCKET_ID_ANY);
5565         if (!pool) {
5566                 rte_errno = ENOMEM;
5567                 return NULL;
5568         }
5569         pool->raw = NULL;
5570         pool->is_aged = !!age;
5571         pool->query_gen = 0;
5572         pool->min_dcs = dcs;
5573         rte_spinlock_init(&pool->sl);
5574         rte_spinlock_init(&pool->csl);
5575         TAILQ_INIT(&pool->counters[0]);
5576         TAILQ_INIT(&pool->counters[1]);
5577         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
5578         rte_spinlock_lock(&cmng->pool_update_sl);
5579         pool->index = cmng->n_valid;
5580         if (pool->index == cmng->n && flow_dv_container_resize(dev)) {
5581                 mlx5_free(pool);
5582                 rte_spinlock_unlock(&cmng->pool_update_sl);
5583                 return NULL;
5584         }
5585         cmng->pools[pool->index] = pool;
5586         cmng->n_valid++;
5587         if (unlikely(fallback)) {
5588                 int base = RTE_ALIGN_FLOOR(dcs->id, MLX5_COUNTERS_PER_POOL);
5589
5590                 if (base < cmng->min_id)
5591                         cmng->min_id = base;
5592                 if (base > cmng->max_id)
5593                         cmng->max_id = base + MLX5_COUNTERS_PER_POOL - 1;
5594                 cmng->last_pool_idx = pool->index;
5595         }
5596         rte_spinlock_unlock(&cmng->pool_update_sl);
5597         return pool;
5598 }
5599
5600 /**
5601  * Prepare a new counter and/or a new counter pool.
5602  *
5603  * @param[in] dev
5604  *   Pointer to the Ethernet device structure.
5605  * @param[out] cnt_free
5606  *   Where to put the pointer of a new counter.
5607  * @param[in] age
5608  *   Whether the pool is for counter that was allocated for aging.
5609  *
5610  * @return
5611  *   The counter pool pointer and @p cnt_free is set on success,
5612  *   NULL otherwise and rte_errno is set.
5613  */
5614 static struct mlx5_flow_counter_pool *
5615 flow_dv_counter_pool_prepare(struct rte_eth_dev *dev,
5616                              struct mlx5_flow_counter **cnt_free,
5617                              uint32_t age)
5618 {
5619         struct mlx5_priv *priv = dev->data->dev_private;
5620         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5621         struct mlx5_flow_counter_pool *pool;
5622         struct mlx5_counters tmp_tq;
5623         struct mlx5_devx_obj *dcs = NULL;
5624         struct mlx5_flow_counter *cnt;
5625         enum mlx5_counter_type cnt_type =
5626                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5627         bool fallback = priv->sh->cmng.counter_fallback;
5628         uint32_t i;
5629
5630         if (fallback) {
5631                 /* bulk_bitmap must be 0 for single counter allocation. */
5632                 dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0);
5633                 if (!dcs)
5634                         return NULL;
5635                 pool = flow_dv_find_pool_by_id(cmng, dcs->id);
5636                 if (!pool) {
5637                         pool = flow_dv_pool_create(dev, dcs, age);
5638                         if (!pool) {
5639                                 mlx5_devx_cmd_destroy(dcs);
5640                                 return NULL;
5641                         }
5642                 }
5643                 i = dcs->id % MLX5_COUNTERS_PER_POOL;
5644                 cnt = MLX5_POOL_GET_CNT(pool, i);
5645                 cnt->pool = pool;
5646                 cnt->dcs_when_free = dcs;
5647                 *cnt_free = cnt;
5648                 return pool;
5649         }
5650         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
5651         if (!dcs) {
5652                 rte_errno = ENODATA;
5653                 return NULL;
5654         }
5655         pool = flow_dv_pool_create(dev, dcs, age);
5656         if (!pool) {
5657                 mlx5_devx_cmd_destroy(dcs);
5658                 return NULL;
5659         }
5660         TAILQ_INIT(&tmp_tq);
5661         for (i = 1; i < MLX5_COUNTERS_PER_POOL; ++i) {
5662                 cnt = MLX5_POOL_GET_CNT(pool, i);
5663                 cnt->pool = pool;
5664                 TAILQ_INSERT_HEAD(&tmp_tq, cnt, next);
5665         }
5666         rte_spinlock_lock(&cmng->csl[cnt_type]);
5667         TAILQ_CONCAT(&cmng->counters[cnt_type], &tmp_tq, next);
5668         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5669         *cnt_free = MLX5_POOL_GET_CNT(pool, 0);
5670         (*cnt_free)->pool = pool;
5671         return pool;
5672 }
5673
5674 /**
5675  * Allocate a flow counter.
5676  *
5677  * @param[in] dev
5678  *   Pointer to the Ethernet device structure.
5679  * @param[in] age
5680  *   Whether the counter was allocated for aging.
5681  *
5682  * @return
5683  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5684  */
5685 static uint32_t
5686 flow_dv_counter_alloc(struct rte_eth_dev *dev, uint32_t age)
5687 {
5688         struct mlx5_priv *priv = dev->data->dev_private;
5689         struct mlx5_flow_counter_pool *pool = NULL;
5690         struct mlx5_flow_counter *cnt_free = NULL;
5691         bool fallback = priv->sh->cmng.counter_fallback;
5692         struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng;
5693         enum mlx5_counter_type cnt_type =
5694                         age ? MLX5_COUNTER_TYPE_AGE : MLX5_COUNTER_TYPE_ORIGIN;
5695         uint32_t cnt_idx;
5696
5697         if (!priv->config.devx) {
5698                 rte_errno = ENOTSUP;
5699                 return 0;
5700         }
5701         /* Get free counters from container. */
5702         rte_spinlock_lock(&cmng->csl[cnt_type]);
5703         cnt_free = TAILQ_FIRST(&cmng->counters[cnt_type]);
5704         if (cnt_free)
5705                 TAILQ_REMOVE(&cmng->counters[cnt_type], cnt_free, next);
5706         rte_spinlock_unlock(&cmng->csl[cnt_type]);
5707         if (!cnt_free && !flow_dv_counter_pool_prepare(dev, &cnt_free, age))
5708                 goto err;
5709         pool = cnt_free->pool;
5710         if (fallback)
5711                 cnt_free->dcs_when_active = cnt_free->dcs_when_free;
5712         /* Create a DV counter action only in the first time usage. */
5713         if (!cnt_free->action) {
5714                 uint16_t offset;
5715                 struct mlx5_devx_obj *dcs;
5716                 int ret;
5717
5718                 if (!fallback) {
5719                         offset = MLX5_CNT_ARRAY_IDX(pool, cnt_free);
5720                         dcs = pool->min_dcs;
5721                 } else {
5722                         offset = 0;
5723                         dcs = cnt_free->dcs_when_free;
5724                 }
5725                 ret = mlx5_flow_os_create_flow_action_count(dcs->obj, offset,
5726                                                             &cnt_free->action);
5727                 if (ret) {
5728                         rte_errno = errno;
5729                         goto err;
5730                 }
5731         }
5732         cnt_idx = MLX5_MAKE_CNT_IDX(pool->index,
5733                                 MLX5_CNT_ARRAY_IDX(pool, cnt_free));
5734         /* Update the counter reset values. */
5735         if (_flow_dv_query_count(dev, cnt_idx, &cnt_free->hits,
5736                                  &cnt_free->bytes))
5737                 goto err;
5738         if (!fallback && !priv->sh->cmng.query_thread_on)
5739                 /* Start the asynchronous batch query by the host thread. */
5740                 mlx5_set_query_alarm(priv->sh);
5741         return cnt_idx;
5742 err:
5743         if (cnt_free) {
5744                 cnt_free->pool = pool;
5745                 if (fallback)
5746                         cnt_free->dcs_when_free = cnt_free->dcs_when_active;
5747                 rte_spinlock_lock(&cmng->csl[cnt_type]);
5748                 TAILQ_INSERT_TAIL(&cmng->counters[cnt_type], cnt_free, next);
5749                 rte_spinlock_unlock(&cmng->csl[cnt_type]);
5750         }
5751         return 0;
5752 }
5753
5754 /**
5755  * Allocate a shared flow counter.
5756  *
5757  * @param[in] ctx
5758  *   Pointer to the shared counter configuration.
5759  * @param[in] data
5760  *   Pointer to save the allocated counter index.
5761  *
5762  * @return
5763  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5764  */
5765
5766 static int32_t
5767 flow_dv_counter_alloc_shared_cb(void *ctx, union mlx5_l3t_data *data)
5768 {
5769         struct mlx5_shared_counter_conf *conf = ctx;
5770         struct rte_eth_dev *dev = conf->dev;
5771         struct mlx5_flow_counter *cnt;
5772
5773         data->dword = flow_dv_counter_alloc(dev, 0);
5774         data->dword |= MLX5_CNT_SHARED_OFFSET;
5775         cnt = flow_dv_counter_get_by_idx(dev, data->dword, NULL);
5776         cnt->shared_info.id = conf->id;
5777         return 0;
5778 }
5779
5780 /**
5781  * Get a shared flow counter.
5782  *
5783  * @param[in] dev
5784  *   Pointer to the Ethernet device structure.
5785  * @param[in] id
5786  *   Counter identifier.
5787  *
5788  * @return
5789  *   Index to flow counter on success, 0 otherwise and rte_errno is set.
5790  */
5791 static uint32_t
5792 flow_dv_counter_get_shared(struct rte_eth_dev *dev, uint32_t id)
5793 {
5794         struct mlx5_priv *priv = dev->data->dev_private;
5795         struct mlx5_shared_counter_conf conf = {
5796                 .dev = dev,
5797                 .id = id,
5798         };
5799         union mlx5_l3t_data data = {
5800                 .dword = 0,
5801         };
5802
5803         mlx5_l3t_prepare_entry(priv->sh->cnt_id_tbl, id, &data,
5804                                flow_dv_counter_alloc_shared_cb, &conf);
5805         return data.dword;
5806 }
5807
5808 /**
5809  * Get age param from counter index.
5810  *
5811  * @param[in] dev
5812  *   Pointer to the Ethernet device structure.
5813  * @param[in] counter
5814  *   Index to the counter handler.
5815  *
5816  * @return
5817  *   The aging parameter specified for the counter index.
5818  */
5819 static struct mlx5_age_param*
5820 flow_dv_counter_idx_get_age(struct rte_eth_dev *dev,
5821                                 uint32_t counter)
5822 {
5823         struct mlx5_flow_counter *cnt;
5824         struct mlx5_flow_counter_pool *pool = NULL;
5825
5826         flow_dv_counter_get_by_idx(dev, counter, &pool);
5827         counter = (counter - 1) % MLX5_COUNTERS_PER_POOL;
5828         cnt = MLX5_POOL_GET_CNT(pool, counter);
5829         return MLX5_CNT_TO_AGE(cnt);
5830 }
5831
5832 /**
5833  * Remove a flow counter from aged counter list.
5834  *
5835  * @param[in] dev
5836  *   Pointer to the Ethernet device structure.
5837  * @param[in] counter
5838  *   Index to the counter handler.
5839  * @param[in] cnt
5840  *   Pointer to the counter handler.
5841  */
5842 static void
5843 flow_dv_counter_remove_from_age(struct rte_eth_dev *dev,
5844                                 uint32_t counter, struct mlx5_flow_counter *cnt)
5845 {
5846         struct mlx5_age_info *age_info;
5847         struct mlx5_age_param *age_param;
5848         struct mlx5_priv *priv = dev->data->dev_private;
5849         uint16_t expected = AGE_CANDIDATE;
5850
5851         age_info = GET_PORT_AGE_INFO(priv);
5852         age_param = flow_dv_counter_idx_get_age(dev, counter);
5853         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
5854                                          AGE_FREE, false, __ATOMIC_RELAXED,
5855                                          __ATOMIC_RELAXED)) {
5856                 /**
5857                  * We need the lock even it is age timeout,
5858                  * since counter may still in process.
5859                  */
5860                 rte_spinlock_lock(&age_info->aged_sl);
5861                 TAILQ_REMOVE(&age_info->aged_counters, cnt, next);
5862                 rte_spinlock_unlock(&age_info->aged_sl);
5863                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
5864         }
5865 }
5866
5867 /**
5868  * Release a flow counter.
5869  *
5870  * @param[in] dev
5871  *   Pointer to the Ethernet device structure.
5872  * @param[in] counter
5873  *   Index to the counter handler.
5874  */
5875 static void
5876 flow_dv_counter_free(struct rte_eth_dev *dev, uint32_t counter)
5877 {
5878         struct mlx5_priv *priv = dev->data->dev_private;
5879         struct mlx5_flow_counter_pool *pool = NULL;
5880         struct mlx5_flow_counter *cnt;
5881         enum mlx5_counter_type cnt_type;
5882
5883         if (!counter)
5884                 return;
5885         cnt = flow_dv_counter_get_by_idx(dev, counter, &pool);
5886         MLX5_ASSERT(pool);
5887         if (IS_SHARED_CNT(counter) &&
5888             mlx5_l3t_clear_entry(priv->sh->cnt_id_tbl, cnt->shared_info.id))
5889                 return;
5890         if (pool->is_aged)
5891                 flow_dv_counter_remove_from_age(dev, counter, cnt);
5892         cnt->pool = pool;
5893         /*
5894          * Put the counter back to list to be updated in none fallback mode.
5895          * Currently, we are using two list alternately, while one is in query,
5896          * add the freed counter to the other list based on the pool query_gen
5897          * value. After query finishes, add counter the list to the global
5898          * container counter list. The list changes while query starts. In
5899          * this case, lock will not be needed as query callback and release
5900          * function both operate with the different list.
5901          *
5902          */
5903         if (!priv->sh->cmng.counter_fallback) {
5904                 rte_spinlock_lock(&pool->csl);
5905                 TAILQ_INSERT_TAIL(&pool->counters[pool->query_gen], cnt, next);
5906                 rte_spinlock_unlock(&pool->csl);
5907         } else {
5908                 cnt->dcs_when_free = cnt->dcs_when_active;
5909                 cnt_type = pool->is_aged ? MLX5_COUNTER_TYPE_AGE :
5910                                            MLX5_COUNTER_TYPE_ORIGIN;
5911                 rte_spinlock_lock(&priv->sh->cmng.csl[cnt_type]);
5912                 TAILQ_INSERT_TAIL(&priv->sh->cmng.counters[cnt_type],
5913                                   cnt, next);
5914                 rte_spinlock_unlock(&priv->sh->cmng.csl[cnt_type]);
5915         }
5916 }
5917
5918 /**
5919  * Verify the @p attributes will be correctly understood by the NIC and store
5920  * them in the @p flow if everything is correct.
5921  *
5922  * @param[in] dev
5923  *   Pointer to dev struct.
5924  * @param[in] attributes
5925  *   Pointer to flow attributes
5926  * @param[in] external
5927  *   This flow rule is created by request external to PMD.
5928  * @param[out] error
5929  *   Pointer to error structure.
5930  *
5931  * @return
5932  *   - 0 on success and non root table.
5933  *   - 1 on success and root table.
5934  *   - a negative errno value otherwise and rte_errno is set.
5935  */
5936 static int
5937 flow_dv_validate_attributes(struct rte_eth_dev *dev,
5938                             const struct mlx5_flow_tunnel *tunnel,
5939                             const struct rte_flow_attr *attributes,
5940                             const struct flow_grp_info *grp_info,
5941                             struct rte_flow_error *error)
5942 {
5943         struct mlx5_priv *priv = dev->data->dev_private;
5944         uint32_t lowest_priority = mlx5_get_lowest_priority(dev, attributes);
5945         int ret = 0;
5946
5947 #ifndef HAVE_MLX5DV_DR
5948         RTE_SET_USED(tunnel);
5949         RTE_SET_USED(grp_info);
5950         if (attributes->group)
5951                 return rte_flow_error_set(error, ENOTSUP,
5952                                           RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
5953                                           NULL,
5954                                           "groups are not supported");
5955 #else
5956         uint32_t table = 0;
5957
5958         ret = mlx5_flow_group_to_table(dev, tunnel, attributes->group, &table,
5959                                        grp_info, error);
5960         if (ret)
5961                 return ret;
5962         if (!table)
5963                 ret = MLX5DV_DR_ACTION_FLAGS_ROOT_LEVEL;
5964 #endif
5965         if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR &&
5966             attributes->priority > lowest_priority)
5967                 return rte_flow_error_set(error, ENOTSUP,
5968                                           RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
5969                                           NULL,
5970                                           "priority out of range");
5971         if (attributes->transfer) {
5972                 if (!priv->config.dv_esw_en)
5973                         return rte_flow_error_set
5974                                 (error, ENOTSUP,
5975                                  RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
5976                                  "E-Switch dr is not supported");
5977                 if (!(priv->representor || priv->master))
5978                         return rte_flow_error_set
5979                                 (error, EINVAL, RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
5980                                  NULL, "E-Switch configuration can only be"
5981                                  " done by a master or a representor device");
5982                 if (attributes->egress)
5983                         return rte_flow_error_set
5984                                 (error, ENOTSUP,
5985                                  RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, attributes,
5986                                  "egress is not supported");
5987         }
5988         if (!(attributes->egress ^ attributes->ingress))
5989                 return rte_flow_error_set(error, ENOTSUP,
5990                                           RTE_FLOW_ERROR_TYPE_ATTR, NULL,
5991                                           "must specify exactly one of "
5992                                           "ingress or egress");
5993         return ret;
5994 }
5995
5996 /**
5997  * Internal validation function. For validating both actions and items.
5998  *
5999  * @param[in] dev
6000  *   Pointer to the rte_eth_dev structure.
6001  * @param[in] attr
6002  *   Pointer to the flow attributes.
6003  * @param[in] items
6004  *   Pointer to the list of items.
6005  * @param[in] actions
6006  *   Pointer to the list of actions.
6007  * @param[in] external
6008  *   This flow rule is created by request external to PMD.
6009  * @param[in] hairpin
6010  *   Number of hairpin TX actions, 0 means classic flow.
6011  * @param[out] error
6012  *   Pointer to the error structure.
6013  *
6014  * @return
6015  *   0 on success, a negative errno value otherwise and rte_errno is set.
6016  */
6017 static int
6018 flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,
6019                  const struct rte_flow_item items[],
6020                  const struct rte_flow_action actions[],
6021                  bool external, int hairpin, struct rte_flow_error *error)
6022 {
6023         int ret;
6024         uint64_t action_flags = 0;
6025         uint64_t item_flags = 0;
6026         uint64_t last_item = 0;
6027         uint8_t next_protocol = 0xff;
6028         uint16_t ether_type = 0;
6029         int actions_n = 0;
6030         uint8_t item_ipv6_proto = 0;
6031         int fdb_mirror_limit = 0;
6032         int modify_after_mirror = 0;
6033         const struct rte_flow_item *geneve_item = NULL;
6034         const struct rte_flow_item *gre_item = NULL;
6035         const struct rte_flow_item *gtp_item = NULL;
6036         const struct rte_flow_action_raw_decap *decap;
6037         const struct rte_flow_action_raw_encap *encap;
6038         const struct rte_flow_action_rss *rss = NULL;
6039         const struct rte_flow_action_rss *sample_rss = NULL;
6040         const struct rte_flow_action_count *count = NULL;
6041         const struct rte_flow_action_count *sample_count = NULL;
6042         const struct rte_flow_item_tcp nic_tcp_mask = {
6043                 .hdr = {
6044                         .tcp_flags = 0xFF,
6045                         .src_port = RTE_BE16(UINT16_MAX),
6046                         .dst_port = RTE_BE16(UINT16_MAX),
6047                 }
6048         };
6049         const struct rte_flow_item_ipv6 nic_ipv6_mask = {
6050                 .hdr = {
6051                         .src_addr =
6052                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6053                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6054                         .dst_addr =
6055                         "\xff\xff\xff\xff\xff\xff\xff\xff"
6056                         "\xff\xff\xff\xff\xff\xff\xff\xff",
6057                         .vtc_flow = RTE_BE32(0xffffffff),
6058                         .proto = 0xff,
6059                         .hop_limits = 0xff,
6060                 },
6061                 .has_frag_ext = 1,
6062         };
6063         const struct rte_flow_item_ecpri nic_ecpri_mask = {
6064                 .hdr = {
6065                         .common = {
6066                                 .u32 =
6067                                 RTE_BE32(((const struct rte_ecpri_common_hdr) {
6068                                         .type = 0xFF,
6069                                         }).u32),
6070                         },
6071                         .dummy[0] = 0xffffffff,
6072                 },
6073         };
6074         struct mlx5_priv *priv = dev->data->dev_private;
6075         struct mlx5_dev_config *dev_conf = &priv->config;
6076         uint16_t queue_index = 0xFFFF;
6077         const struct rte_flow_item_vlan *vlan_m = NULL;
6078         uint32_t rw_act_num = 0;
6079         uint64_t is_root;
6080         const struct mlx5_flow_tunnel *tunnel;
6081         struct flow_grp_info grp_info = {
6082                 .external = !!external,
6083                 .transfer = !!attr->transfer,
6084                 .fdb_def_rule = !!priv->fdb_def_rule,
6085         };
6086         const struct rte_eth_hairpin_conf *conf;
6087
6088         if (items == NULL)
6089                 return -1;
6090         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
6091                 tunnel = flow_items_to_tunnel(items);
6092                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_MATCH |
6093                                 MLX5_FLOW_ACTION_DECAP;
6094         } else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) {
6095                 tunnel = flow_actions_to_tunnel(actions);
6096                 action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6097         } else {
6098                 tunnel = NULL;
6099         }
6100         if (tunnel && priv->representor)
6101                 return rte_flow_error_set(error, ENOTSUP,
6102                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
6103                                           "decap not supported "
6104                                           "for VF representor");
6105         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
6106                                 (dev, tunnel, attr, items, actions);
6107         ret = flow_dv_validate_attributes(dev, tunnel, attr, &grp_info, error);
6108         if (ret < 0)
6109                 return ret;
6110         is_root = (uint64_t)ret;
6111         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
6112                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
6113                 int type = items->type;
6114
6115                 if (!mlx5_flow_os_item_supported(type))
6116                         return rte_flow_error_set(error, ENOTSUP,
6117                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6118                                                   NULL, "item not supported");
6119                 switch (type) {
6120                 case MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL:
6121                         if (items[0].type != (typeof(items[0].type))
6122                                                 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL)
6123                                 return rte_flow_error_set
6124                                                 (error, EINVAL,
6125                                                 RTE_FLOW_ERROR_TYPE_ITEM,
6126                                                 NULL, "MLX5 private items "
6127                                                 "must be the first");
6128                         break;
6129                 case RTE_FLOW_ITEM_TYPE_VOID:
6130                         break;
6131                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
6132                         ret = flow_dv_validate_item_port_id
6133                                         (dev, items, attr, item_flags, error);
6134                         if (ret < 0)
6135                                 return ret;
6136                         last_item = MLX5_FLOW_ITEM_PORT_ID;
6137                         break;
6138                 case RTE_FLOW_ITEM_TYPE_ETH:
6139                         ret = mlx5_flow_validate_item_eth(items, item_flags,
6140                                                           true, error);
6141                         if (ret < 0)
6142                                 return ret;
6143                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
6144                                              MLX5_FLOW_LAYER_OUTER_L2;
6145                         if (items->mask != NULL && items->spec != NULL) {
6146                                 ether_type =
6147                                         ((const struct rte_flow_item_eth *)
6148                                          items->spec)->type;
6149                                 ether_type &=
6150                                         ((const struct rte_flow_item_eth *)
6151                                          items->mask)->type;
6152                                 ether_type = rte_be_to_cpu_16(ether_type);
6153                         } else {
6154                                 ether_type = 0;
6155                         }
6156                         break;
6157                 case RTE_FLOW_ITEM_TYPE_VLAN:
6158                         ret = flow_dv_validate_item_vlan(items, item_flags,
6159                                                          dev, error);
6160                         if (ret < 0)
6161                                 return ret;
6162                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN :
6163                                              MLX5_FLOW_LAYER_OUTER_VLAN;
6164                         if (items->mask != NULL && items->spec != NULL) {
6165                                 ether_type =
6166                                         ((const struct rte_flow_item_vlan *)
6167                                          items->spec)->inner_type;
6168                                 ether_type &=
6169                                         ((const struct rte_flow_item_vlan *)
6170                                          items->mask)->inner_type;
6171                                 ether_type = rte_be_to_cpu_16(ether_type);
6172                         } else {
6173                                 ether_type = 0;
6174                         }
6175                         /* Store outer VLAN mask for of_push_vlan action. */
6176                         if (!tunnel)
6177                                 vlan_m = items->mask;
6178                         break;
6179                 case RTE_FLOW_ITEM_TYPE_IPV4:
6180                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6181                                                   &item_flags, &tunnel);
6182                         ret = flow_dv_validate_item_ipv4(items, item_flags,
6183                                                          last_item, ether_type,
6184                                                          error);
6185                         if (ret < 0)
6186                                 return ret;
6187                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
6188                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
6189                         if (items->mask != NULL &&
6190                             ((const struct rte_flow_item_ipv4 *)
6191                              items->mask)->hdr.next_proto_id) {
6192                                 next_protocol =
6193                                         ((const struct rte_flow_item_ipv4 *)
6194                                          (items->spec))->hdr.next_proto_id;
6195                                 next_protocol &=
6196                                         ((const struct rte_flow_item_ipv4 *)
6197                                          (items->mask))->hdr.next_proto_id;
6198                         } else {
6199                                 /* Reset for inner layer. */
6200                                 next_protocol = 0xff;
6201                         }
6202                         break;
6203                 case RTE_FLOW_ITEM_TYPE_IPV6:
6204                         mlx5_flow_tunnel_ip_check(items, next_protocol,
6205                                                   &item_flags, &tunnel);
6206                         ret = mlx5_flow_validate_item_ipv6(items, item_flags,
6207                                                            last_item,
6208                                                            ether_type,
6209                                                            &nic_ipv6_mask,
6210                                                            error);
6211                         if (ret < 0)
6212                                 return ret;
6213                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
6214                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
6215                         if (items->mask != NULL &&
6216                             ((const struct rte_flow_item_ipv6 *)
6217                              items->mask)->hdr.proto) {
6218                                 item_ipv6_proto =
6219                                         ((const struct rte_flow_item_ipv6 *)
6220                                          items->spec)->hdr.proto;
6221                                 next_protocol =
6222                                         ((const struct rte_flow_item_ipv6 *)
6223                                          items->spec)->hdr.proto;
6224                                 next_protocol &=
6225                                         ((const struct rte_flow_item_ipv6 *)
6226                                          items->mask)->hdr.proto;
6227                         } else {
6228                                 /* Reset for inner layer. */
6229                                 next_protocol = 0xff;
6230                         }
6231                         break;
6232                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
6233                         ret = flow_dv_validate_item_ipv6_frag_ext(items,
6234                                                                   item_flags,
6235                                                                   error);
6236                         if (ret < 0)
6237                                 return ret;
6238                         last_item = tunnel ?
6239                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
6240                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
6241                         if (items->mask != NULL &&
6242                             ((const struct rte_flow_item_ipv6_frag_ext *)
6243                              items->mask)->hdr.next_header) {
6244                                 next_protocol =
6245                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6246                                  items->spec)->hdr.next_header;
6247                                 next_protocol &=
6248                                 ((const struct rte_flow_item_ipv6_frag_ext *)
6249                                  items->mask)->hdr.next_header;
6250                         } else {
6251                                 /* Reset for inner layer. */
6252                                 next_protocol = 0xff;
6253                         }
6254                         break;
6255                 case RTE_FLOW_ITEM_TYPE_TCP:
6256                         ret = mlx5_flow_validate_item_tcp
6257                                                 (items, item_flags,
6258                                                  next_protocol,
6259                                                  &nic_tcp_mask,
6260                                                  error);
6261                         if (ret < 0)
6262                                 return ret;
6263                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
6264                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
6265                         break;
6266                 case RTE_FLOW_ITEM_TYPE_UDP:
6267                         ret = mlx5_flow_validate_item_udp(items, item_flags,
6268                                                           next_protocol,
6269                                                           error);
6270                         if (ret < 0)
6271                                 return ret;
6272                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
6273                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
6274                         break;
6275                 case RTE_FLOW_ITEM_TYPE_GRE:
6276                         ret = mlx5_flow_validate_item_gre(items, item_flags,
6277                                                           next_protocol, error);
6278                         if (ret < 0)
6279                                 return ret;
6280                         gre_item = items;
6281                         last_item = MLX5_FLOW_LAYER_GRE;
6282                         break;
6283                 case RTE_FLOW_ITEM_TYPE_NVGRE:
6284                         ret = mlx5_flow_validate_item_nvgre(items, item_flags,
6285                                                             next_protocol,
6286                                                             error);
6287                         if (ret < 0)
6288                                 return ret;
6289                         last_item = MLX5_FLOW_LAYER_NVGRE;
6290                         break;
6291                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
6292                         ret = mlx5_flow_validate_item_gre_key
6293                                 (items, item_flags, gre_item, error);
6294                         if (ret < 0)
6295                                 return ret;
6296                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
6297                         break;
6298                 case RTE_FLOW_ITEM_TYPE_VXLAN:
6299                         ret = mlx5_flow_validate_item_vxlan(items, item_flags,
6300                                                             error);
6301                         if (ret < 0)
6302                                 return ret;
6303                         last_item = MLX5_FLOW_LAYER_VXLAN;
6304                         break;
6305                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
6306                         ret = mlx5_flow_validate_item_vxlan_gpe(items,
6307                                                                 item_flags, dev,
6308                                                                 error);
6309                         if (ret < 0)
6310                                 return ret;
6311                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
6312                         break;
6313                 case RTE_FLOW_ITEM_TYPE_GENEVE:
6314                         ret = mlx5_flow_validate_item_geneve(items,
6315                                                              item_flags, dev,
6316                                                              error);
6317                         if (ret < 0)
6318                                 return ret;
6319                         geneve_item = items;
6320                         last_item = MLX5_FLOW_LAYER_GENEVE;
6321                         break;
6322                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
6323                         ret = mlx5_flow_validate_item_geneve_opt(items,
6324                                                                  last_item,
6325                                                                  geneve_item,
6326                                                                  dev,
6327                                                                  error);
6328                         if (ret < 0)
6329                                 return ret;
6330                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
6331                         break;
6332                 case RTE_FLOW_ITEM_TYPE_MPLS:
6333                         ret = mlx5_flow_validate_item_mpls(dev, items,
6334                                                            item_flags,
6335                                                            last_item, error);
6336                         if (ret < 0)
6337                                 return ret;
6338                         last_item = MLX5_FLOW_LAYER_MPLS;
6339                         break;
6340
6341                 case RTE_FLOW_ITEM_TYPE_MARK:
6342                         ret = flow_dv_validate_item_mark(dev, items, attr,
6343                                                          error);
6344                         if (ret < 0)
6345                                 return ret;
6346                         last_item = MLX5_FLOW_ITEM_MARK;
6347                         break;
6348                 case RTE_FLOW_ITEM_TYPE_META:
6349                         ret = flow_dv_validate_item_meta(dev, items, attr,
6350                                                          error);
6351                         if (ret < 0)
6352                                 return ret;
6353                         last_item = MLX5_FLOW_ITEM_METADATA;
6354                         break;
6355                 case RTE_FLOW_ITEM_TYPE_ICMP:
6356                         ret = mlx5_flow_validate_item_icmp(items, item_flags,
6357                                                            next_protocol,
6358                                                            error);
6359                         if (ret < 0)
6360                                 return ret;
6361                         last_item = MLX5_FLOW_LAYER_ICMP;
6362                         break;
6363                 case RTE_FLOW_ITEM_TYPE_ICMP6:
6364                         ret = mlx5_flow_validate_item_icmp6(items, item_flags,
6365                                                             next_protocol,
6366                                                             error);
6367                         if (ret < 0)
6368                                 return ret;
6369                         item_ipv6_proto = IPPROTO_ICMPV6;
6370                         last_item = MLX5_FLOW_LAYER_ICMP6;
6371                         break;
6372                 case RTE_FLOW_ITEM_TYPE_TAG:
6373                         ret = flow_dv_validate_item_tag(dev, items,
6374                                                         attr, error);
6375                         if (ret < 0)
6376                                 return ret;
6377                         last_item = MLX5_FLOW_ITEM_TAG;
6378                         break;
6379                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
6380                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
6381                         break;
6382                 case RTE_FLOW_ITEM_TYPE_GTP:
6383                         ret = flow_dv_validate_item_gtp(dev, items, item_flags,
6384                                                         error);
6385                         if (ret < 0)
6386                                 return ret;
6387                         gtp_item = items;
6388                         last_item = MLX5_FLOW_LAYER_GTP;
6389                         break;
6390                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
6391                         ret = flow_dv_validate_item_gtp_psc(items, last_item,
6392                                                             gtp_item, attr,
6393                                                             error);
6394                         if (ret < 0)
6395                                 return ret;
6396                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
6397                         break;
6398                 case RTE_FLOW_ITEM_TYPE_ECPRI:
6399                         /* Capacity will be checked in the translate stage. */
6400                         ret = mlx5_flow_validate_item_ecpri(items, item_flags,
6401                                                             last_item,
6402                                                             ether_type,
6403                                                             &nic_ecpri_mask,
6404                                                             error);
6405                         if (ret < 0)
6406                                 return ret;
6407                         last_item = MLX5_FLOW_LAYER_ECPRI;
6408                         break;
6409                 default:
6410                         return rte_flow_error_set(error, ENOTSUP,
6411                                                   RTE_FLOW_ERROR_TYPE_ITEM,
6412                                                   NULL, "item not supported");
6413                 }
6414                 item_flags |= last_item;
6415         }
6416         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
6417                 int type = actions->type;
6418
6419                 if (!mlx5_flow_os_action_supported(type))
6420                         return rte_flow_error_set(error, ENOTSUP,
6421                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6422                                                   actions,
6423                                                   "action not supported");
6424                 if (actions_n == MLX5_DV_MAX_NUMBER_OF_ACTIONS)
6425                         return rte_flow_error_set(error, ENOTSUP,
6426                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6427                                                   actions, "too many actions");
6428                 switch (type) {
6429                 case RTE_FLOW_ACTION_TYPE_VOID:
6430                         break;
6431                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
6432                         ret = flow_dv_validate_action_port_id(dev,
6433                                                               action_flags,
6434                                                               actions,
6435                                                               attr,
6436                                                               error);
6437                         if (ret)
6438                                 return ret;
6439                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
6440                         ++actions_n;
6441                         break;
6442                 case RTE_FLOW_ACTION_TYPE_FLAG:
6443                         ret = flow_dv_validate_action_flag(dev, action_flags,
6444                                                            attr, error);
6445                         if (ret < 0)
6446                                 return ret;
6447                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6448                                 /* Count all modify-header actions as one. */
6449                                 if (!(action_flags &
6450                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6451                                         ++actions_n;
6452                                 action_flags |= MLX5_FLOW_ACTION_FLAG |
6453                                                 MLX5_FLOW_ACTION_MARK_EXT;
6454                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6455                                         modify_after_mirror = 1;
6456
6457                         } else {
6458                                 action_flags |= MLX5_FLOW_ACTION_FLAG;
6459                                 ++actions_n;
6460                         }
6461                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6462                         break;
6463                 case RTE_FLOW_ACTION_TYPE_MARK:
6464                         ret = flow_dv_validate_action_mark(dev, actions,
6465                                                            action_flags,
6466                                                            attr, error);
6467                         if (ret < 0)
6468                                 return ret;
6469                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
6470                                 /* Count all modify-header actions as one. */
6471                                 if (!(action_flags &
6472                                       MLX5_FLOW_MODIFY_HDR_ACTIONS))
6473                                         ++actions_n;
6474                                 action_flags |= MLX5_FLOW_ACTION_MARK |
6475                                                 MLX5_FLOW_ACTION_MARK_EXT;
6476                                 if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6477                                         modify_after_mirror = 1;
6478                         } else {
6479                                 action_flags |= MLX5_FLOW_ACTION_MARK;
6480                                 ++actions_n;
6481                         }
6482                         rw_act_num += MLX5_ACT_NUM_SET_MARK;
6483                         break;
6484                 case RTE_FLOW_ACTION_TYPE_SET_META:
6485                         ret = flow_dv_validate_action_set_meta(dev, actions,
6486                                                                action_flags,
6487                                                                attr, error);
6488                         if (ret < 0)
6489                                 return ret;
6490                         /* Count all modify-header actions as one action. */
6491                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6492                                 ++actions_n;
6493                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6494                                 modify_after_mirror = 1;
6495                         action_flags |= MLX5_FLOW_ACTION_SET_META;
6496                         rw_act_num += MLX5_ACT_NUM_SET_META;
6497                         break;
6498                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
6499                         ret = flow_dv_validate_action_set_tag(dev, actions,
6500                                                               action_flags,
6501                                                               attr, error);
6502                         if (ret < 0)
6503                                 return ret;
6504                         /* Count all modify-header actions as one action. */
6505                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6506                                 ++actions_n;
6507                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6508                                 modify_after_mirror = 1;
6509                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
6510                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6511                         break;
6512                 case RTE_FLOW_ACTION_TYPE_DROP:
6513                         ret = mlx5_flow_validate_action_drop(action_flags,
6514                                                              attr, error);
6515                         if (ret < 0)
6516                                 return ret;
6517                         action_flags |= MLX5_FLOW_ACTION_DROP;
6518                         ++actions_n;
6519                         break;
6520                 case RTE_FLOW_ACTION_TYPE_QUEUE:
6521                         ret = mlx5_flow_validate_action_queue(actions,
6522                                                               action_flags, dev,
6523                                                               attr, error);
6524                         if (ret < 0)
6525                                 return ret;
6526                         queue_index = ((const struct rte_flow_action_queue *)
6527                                                         (actions->conf))->index;
6528                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
6529                         ++actions_n;
6530                         break;
6531                 case RTE_FLOW_ACTION_TYPE_RSS:
6532                         rss = actions->conf;
6533                         ret = mlx5_flow_validate_action_rss(actions,
6534                                                             action_flags, dev,
6535                                                             attr, item_flags,
6536                                                             error);
6537                         if (ret < 0)
6538                                 return ret;
6539                         if (rss && sample_rss &&
6540                             (sample_rss->level != rss->level ||
6541                             sample_rss->types != rss->types))
6542                                 return rte_flow_error_set(error, ENOTSUP,
6543                                         RTE_FLOW_ERROR_TYPE_ACTION,
6544                                         NULL,
6545                                         "Can't use the different RSS types "
6546                                         "or level in the same flow");
6547                         if (rss != NULL && rss->queue_num)
6548                                 queue_index = rss->queue[0];
6549                         action_flags |= MLX5_FLOW_ACTION_RSS;
6550                         ++actions_n;
6551                         break;
6552                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
6553                         ret =
6554                         mlx5_flow_validate_action_default_miss(action_flags,
6555                                         attr, error);
6556                         if (ret < 0)
6557                                 return ret;
6558                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
6559                         ++actions_n;
6560                         break;
6561                 case RTE_FLOW_ACTION_TYPE_COUNT:
6562                         ret = flow_dv_validate_action_count(dev, actions,
6563                                                             action_flags,
6564                                                             error);
6565                         if (ret < 0)
6566                                 return ret;
6567                         count = actions->conf;
6568                         action_flags |= MLX5_FLOW_ACTION_COUNT;
6569                         ++actions_n;
6570                         break;
6571                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
6572                         if (flow_dv_validate_action_pop_vlan(dev,
6573                                                              action_flags,
6574                                                              actions,
6575                                                              item_flags, attr,
6576                                                              error))
6577                                 return -rte_errno;
6578                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
6579                         ++actions_n;
6580                         break;
6581                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
6582                         ret = flow_dv_validate_action_push_vlan(dev,
6583                                                                 action_flags,
6584                                                                 vlan_m,
6585                                                                 actions, attr,
6586                                                                 error);
6587                         if (ret < 0)
6588                                 return ret;
6589                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
6590                         ++actions_n;
6591                         break;
6592                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
6593                         ret = flow_dv_validate_action_set_vlan_pcp
6594                                                 (action_flags, actions, error);
6595                         if (ret < 0)
6596                                 return ret;
6597                         /* Count PCP with push_vlan command. */
6598                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_PCP;
6599                         break;
6600                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
6601                         ret = flow_dv_validate_action_set_vlan_vid
6602                                                 (item_flags, action_flags,
6603                                                  actions, error);
6604                         if (ret < 0)
6605                                 return ret;
6606                         /* Count VID with push_vlan command. */
6607                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
6608                         rw_act_num += MLX5_ACT_NUM_MDF_VID;
6609                         break;
6610                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
6611                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
6612                         ret = flow_dv_validate_action_l2_encap(dev,
6613                                                                action_flags,
6614                                                                actions, attr,
6615                                                                error);
6616                         if (ret < 0)
6617                                 return ret;
6618                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
6619                         ++actions_n;
6620                         break;
6621                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
6622                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
6623                         ret = flow_dv_validate_action_decap(dev, action_flags,
6624                                                             actions, item_flags,
6625                                                             attr, error);
6626                         if (ret < 0)
6627                                 return ret;
6628                         action_flags |= MLX5_FLOW_ACTION_DECAP;
6629                         ++actions_n;
6630                         break;
6631                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
6632                         ret = flow_dv_validate_action_raw_encap_decap
6633                                 (dev, NULL, actions->conf, attr, &action_flags,
6634                                  &actions_n, actions, item_flags, error);
6635                         if (ret < 0)
6636                                 return ret;
6637                         break;
6638                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
6639                         decap = actions->conf;
6640                         while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID)
6641                                 ;
6642                         if (actions->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
6643                                 encap = NULL;
6644                                 actions--;
6645                         } else {
6646                                 encap = actions->conf;
6647                         }
6648                         ret = flow_dv_validate_action_raw_encap_decap
6649                                            (dev,
6650                                             decap ? decap : &empty_decap, encap,
6651                                             attr, &action_flags, &actions_n,
6652                                             actions, item_flags, error);
6653                         if (ret < 0)
6654                                 return ret;
6655                         break;
6656                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
6657                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
6658                         ret = flow_dv_validate_action_modify_mac(action_flags,
6659                                                                  actions,
6660                                                                  item_flags,
6661                                                                  error);
6662                         if (ret < 0)
6663                                 return ret;
6664                         /* Count all modify-header actions as one action. */
6665                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6666                                 ++actions_n;
6667                         action_flags |= actions->type ==
6668                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
6669                                                 MLX5_FLOW_ACTION_SET_MAC_SRC :
6670                                                 MLX5_FLOW_ACTION_SET_MAC_DST;
6671                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6672                                 modify_after_mirror = 1;
6673                         /*
6674                          * Even if the source and destination MAC addresses have
6675                          * overlap in the header with 4B alignment, the convert
6676                          * function will handle them separately and 4 SW actions
6677                          * will be created. And 2 actions will be added each
6678                          * time no matter how many bytes of address will be set.
6679                          */
6680                         rw_act_num += MLX5_ACT_NUM_MDF_MAC;
6681                         break;
6682                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
6683                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
6684                         ret = flow_dv_validate_action_modify_ipv4(action_flags,
6685                                                                   actions,
6686                                                                   item_flags,
6687                                                                   error);
6688                         if (ret < 0)
6689                                 return ret;
6690                         /* Count all modify-header actions as one action. */
6691                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6692                                 ++actions_n;
6693                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6694                                 modify_after_mirror = 1;
6695                         action_flags |= actions->type ==
6696                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
6697                                                 MLX5_FLOW_ACTION_SET_IPV4_SRC :
6698                                                 MLX5_FLOW_ACTION_SET_IPV4_DST;
6699                         rw_act_num += MLX5_ACT_NUM_MDF_IPV4;
6700                         break;
6701                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
6702                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
6703                         ret = flow_dv_validate_action_modify_ipv6(action_flags,
6704                                                                   actions,
6705                                                                   item_flags,
6706                                                                   error);
6707                         if (ret < 0)
6708                                 return ret;
6709                         if (item_ipv6_proto == IPPROTO_ICMPV6)
6710                                 return rte_flow_error_set(error, ENOTSUP,
6711                                         RTE_FLOW_ERROR_TYPE_ACTION,
6712                                         actions,
6713                                         "Can't change header "
6714                                         "with ICMPv6 proto");
6715                         /* Count all modify-header actions as one action. */
6716                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6717                                 ++actions_n;
6718                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6719                                 modify_after_mirror = 1;
6720                         action_flags |= actions->type ==
6721                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
6722                                                 MLX5_FLOW_ACTION_SET_IPV6_SRC :
6723                                                 MLX5_FLOW_ACTION_SET_IPV6_DST;
6724                         rw_act_num += MLX5_ACT_NUM_MDF_IPV6;
6725                         break;
6726                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
6727                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
6728                         ret = flow_dv_validate_action_modify_tp(action_flags,
6729                                                                 actions,
6730                                                                 item_flags,
6731                                                                 error);
6732                         if (ret < 0)
6733                                 return ret;
6734                         /* Count all modify-header actions as one action. */
6735                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6736                                 ++actions_n;
6737                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6738                                 modify_after_mirror = 1;
6739                         action_flags |= actions->type ==
6740                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
6741                                                 MLX5_FLOW_ACTION_SET_TP_SRC :
6742                                                 MLX5_FLOW_ACTION_SET_TP_DST;
6743                         rw_act_num += MLX5_ACT_NUM_MDF_PORT;
6744                         break;
6745                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
6746                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
6747                         ret = flow_dv_validate_action_modify_ttl(action_flags,
6748                                                                  actions,
6749                                                                  item_flags,
6750                                                                  error);
6751                         if (ret < 0)
6752                                 return ret;
6753                         /* Count all modify-header actions as one action. */
6754                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6755                                 ++actions_n;
6756                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6757                                 modify_after_mirror = 1;
6758                         action_flags |= actions->type ==
6759                                         RTE_FLOW_ACTION_TYPE_SET_TTL ?
6760                                                 MLX5_FLOW_ACTION_SET_TTL :
6761                                                 MLX5_FLOW_ACTION_DEC_TTL;
6762                         rw_act_num += MLX5_ACT_NUM_MDF_TTL;
6763                         break;
6764                 case RTE_FLOW_ACTION_TYPE_JUMP:
6765                         ret = flow_dv_validate_action_jump(dev, tunnel, actions,
6766                                                            action_flags,
6767                                                            attr, external,
6768                                                            error);
6769                         if (ret)
6770                                 return ret;
6771                         if ((action_flags & MLX5_FLOW_ACTION_SAMPLE) &&
6772                             fdb_mirror_limit)
6773                                 return rte_flow_error_set(error, EINVAL,
6774                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6775                                                   NULL,
6776                                                   "sample and jump action combination is not supported");
6777                         ++actions_n;
6778                         action_flags |= MLX5_FLOW_ACTION_JUMP;
6779                         break;
6780                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
6781                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
6782                         ret = flow_dv_validate_action_modify_tcp_seq
6783                                                                 (action_flags,
6784                                                                  actions,
6785                                                                  item_flags,
6786                                                                  error);
6787                         if (ret < 0)
6788                                 return ret;
6789                         /* Count all modify-header actions as one action. */
6790                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6791                                 ++actions_n;
6792                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6793                                 modify_after_mirror = 1;
6794                         action_flags |= actions->type ==
6795                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
6796                                                 MLX5_FLOW_ACTION_INC_TCP_SEQ :
6797                                                 MLX5_FLOW_ACTION_DEC_TCP_SEQ;
6798                         rw_act_num += MLX5_ACT_NUM_MDF_TCPSEQ;
6799                         break;
6800                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
6801                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
6802                         ret = flow_dv_validate_action_modify_tcp_ack
6803                                                                 (action_flags,
6804                                                                  actions,
6805                                                                  item_flags,
6806                                                                  error);
6807                         if (ret < 0)
6808                                 return ret;
6809                         /* Count all modify-header actions as one action. */
6810                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6811                                 ++actions_n;
6812                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6813                                 modify_after_mirror = 1;
6814                         action_flags |= actions->type ==
6815                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
6816                                                 MLX5_FLOW_ACTION_INC_TCP_ACK :
6817                                                 MLX5_FLOW_ACTION_DEC_TCP_ACK;
6818                         rw_act_num += MLX5_ACT_NUM_MDF_TCPACK;
6819                         break;
6820                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
6821                         break;
6822                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
6823                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
6824                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6825                         break;
6826                 case RTE_FLOW_ACTION_TYPE_METER:
6827                         ret = mlx5_flow_validate_action_meter(dev,
6828                                                               action_flags,
6829                                                               actions, attr,
6830                                                               error);
6831                         if (ret < 0)
6832                                 return ret;
6833                         action_flags |= MLX5_FLOW_ACTION_METER;
6834                         ++actions_n;
6835                         /* Meter action will add one more TAG action. */
6836                         rw_act_num += MLX5_ACT_NUM_SET_TAG;
6837                         break;
6838                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
6839                         if (!attr->transfer && !attr->group)
6840                                 return rte_flow_error_set(error, ENOTSUP,
6841                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
6842                                                                            NULL,
6843                           "Shared ASO age action is not supported for group 0");
6844                         action_flags |= MLX5_FLOW_ACTION_AGE;
6845                         ++actions_n;
6846                         break;
6847                 case RTE_FLOW_ACTION_TYPE_AGE:
6848                         ret = flow_dv_validate_action_age(action_flags,
6849                                                           actions, dev,
6850                                                           error);
6851                         if (ret < 0)
6852                                 return ret;
6853                         /*
6854                          * Validate the regular AGE action (using counter)
6855                          * mutual exclusion with share counter actions.
6856                          */
6857                         if (!priv->sh->flow_hit_aso_en) {
6858                                 if (count && count->shared)
6859                                         return rte_flow_error_set
6860                                                 (error, EINVAL,
6861                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6862                                                 NULL,
6863                                                 "old age and shared count combination is not supported");
6864                                 if (sample_count)
6865                                         return rte_flow_error_set
6866                                                 (error, EINVAL,
6867                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6868                                                 NULL,
6869                                                 "old age action and count must be in the same sub flow");
6870                         }
6871                         action_flags |= MLX5_FLOW_ACTION_AGE;
6872                         ++actions_n;
6873                         break;
6874                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
6875                         ret = flow_dv_validate_action_modify_ipv4_dscp
6876                                                          (action_flags,
6877                                                           actions,
6878                                                           item_flags,
6879                                                           error);
6880                         if (ret < 0)
6881                                 return ret;
6882                         /* Count all modify-header actions as one action. */
6883                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6884                                 ++actions_n;
6885                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6886                                 modify_after_mirror = 1;
6887                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
6888                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6889                         break;
6890                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
6891                         ret = flow_dv_validate_action_modify_ipv6_dscp
6892                                                                 (action_flags,
6893                                                                  actions,
6894                                                                  item_flags,
6895                                                                  error);
6896                         if (ret < 0)
6897                                 return ret;
6898                         /* Count all modify-header actions as one action. */
6899                         if (!(action_flags & MLX5_FLOW_MODIFY_HDR_ACTIONS))
6900                                 ++actions_n;
6901                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
6902                                 modify_after_mirror = 1;
6903                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
6904                         rw_act_num += MLX5_ACT_NUM_SET_DSCP;
6905                         break;
6906                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
6907                         ret = flow_dv_validate_action_sample(&action_flags,
6908                                                              actions, dev,
6909                                                              attr, item_flags,
6910                                                              rss, &sample_rss,
6911                                                              &sample_count,
6912                                                              &fdb_mirror_limit,
6913                                                              error);
6914                         if (ret < 0)
6915                                 return ret;
6916                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
6917                         ++actions_n;
6918                         break;
6919                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
6920                         if (actions[0].type != (typeof(actions[0].type))
6921                                 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET)
6922                                 return rte_flow_error_set
6923                                                 (error, EINVAL,
6924                                                 RTE_FLOW_ERROR_TYPE_ACTION,
6925                                                 NULL, "MLX5 private action "
6926                                                 "must be the first");
6927
6928                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
6929                         break;
6930                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
6931                         ret = flow_dv_validate_action_modify_field(dev,
6932                                                                    action_flags,
6933                                                                    actions,
6934                                                                    attr,
6935                                                                    error);
6936                         if (ret < 0)
6937                                 return ret;
6938                         /* Count all modify-header actions as one action. */
6939                         if (!(action_flags & MLX5_FLOW_ACTION_MODIFY_FIELD))
6940                                 ++actions_n;
6941                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
6942                         rw_act_num += ret;
6943                         break;
6944                 default:
6945                         return rte_flow_error_set(error, ENOTSUP,
6946                                                   RTE_FLOW_ERROR_TYPE_ACTION,
6947                                                   actions,
6948                                                   "action not supported");
6949                 }
6950         }
6951         /*
6952          * Validate actions in flow rules
6953          * - Explicit decap action is prohibited by the tunnel offload API.
6954          * - Drop action in tunnel steer rule is prohibited by the API.
6955          * - Application cannot use MARK action because it's value can mask
6956          *   tunnel default miss nitification.
6957          * - JUMP in tunnel match rule has no support in current PMD
6958          *   implementation.
6959          * - TAG & META are reserved for future uses.
6960          */
6961         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_SET) {
6962                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_DECAP    |
6963                                             MLX5_FLOW_ACTION_MARK     |
6964                                             MLX5_FLOW_ACTION_SET_TAG  |
6965                                             MLX5_FLOW_ACTION_SET_META |
6966                                             MLX5_FLOW_ACTION_DROP;
6967
6968                 if (action_flags & bad_actions_mask)
6969                         return rte_flow_error_set
6970                                         (error, EINVAL,
6971                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6972                                         "Invalid RTE action in tunnel "
6973                                         "set decap rule");
6974                 if (!(action_flags & MLX5_FLOW_ACTION_JUMP))
6975                         return rte_flow_error_set
6976                                         (error, EINVAL,
6977                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6978                                         "tunnel set decap rule must terminate "
6979                                         "with JUMP");
6980                 if (!attr->ingress)
6981                         return rte_flow_error_set
6982                                         (error, EINVAL,
6983                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6984                                         "tunnel flows for ingress traffic only");
6985         }
6986         if (action_flags & MLX5_FLOW_ACTION_TUNNEL_MATCH) {
6987                 uint64_t bad_actions_mask = MLX5_FLOW_ACTION_JUMP    |
6988                                             MLX5_FLOW_ACTION_MARK    |
6989                                             MLX5_FLOW_ACTION_SET_TAG |
6990                                             MLX5_FLOW_ACTION_SET_META;
6991
6992                 if (action_flags & bad_actions_mask)
6993                         return rte_flow_error_set
6994                                         (error, EINVAL,
6995                                         RTE_FLOW_ERROR_TYPE_ACTION, NULL,
6996                                         "Invalid RTE action in tunnel "
6997                                         "set match rule");
6998         }
6999         /*
7000          * Validate the drop action mutual exclusion with other actions.
7001          * Drop action is mutually-exclusive with any other action, except for
7002          * Count action.
7003          * Drop action compatibility with tunnel offload was already validated.
7004          */
7005         if (action_flags & (MLX5_FLOW_ACTION_TUNNEL_MATCH |
7006                             MLX5_FLOW_ACTION_TUNNEL_MATCH));
7007         else if ((action_flags & MLX5_FLOW_ACTION_DROP) &&
7008             (action_flags & ~(MLX5_FLOW_ACTION_DROP | MLX5_FLOW_ACTION_COUNT)))
7009                 return rte_flow_error_set(error, EINVAL,
7010                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7011                                           "Drop action is mutually-exclusive "
7012                                           "with any other action, except for "
7013                                           "Count action");
7014         /* Eswitch has few restrictions on using items and actions */
7015         if (attr->transfer) {
7016                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7017                     action_flags & MLX5_FLOW_ACTION_FLAG)
7018                         return rte_flow_error_set(error, ENOTSUP,
7019                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7020                                                   NULL,
7021                                                   "unsupported action FLAG");
7022                 if (!mlx5_flow_ext_mreg_supported(dev) &&
7023                     action_flags & MLX5_FLOW_ACTION_MARK)
7024                         return rte_flow_error_set(error, ENOTSUP,
7025                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7026                                                   NULL,
7027                                                   "unsupported action MARK");
7028                 if (action_flags & MLX5_FLOW_ACTION_QUEUE)
7029                         return rte_flow_error_set(error, ENOTSUP,
7030                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7031                                                   NULL,
7032                                                   "unsupported action QUEUE");
7033                 if (action_flags & MLX5_FLOW_ACTION_RSS)
7034                         return rte_flow_error_set(error, ENOTSUP,
7035                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7036                                                   NULL,
7037                                                   "unsupported action RSS");
7038                 if (!(action_flags & MLX5_FLOW_FATE_ESWITCH_ACTIONS))
7039                         return rte_flow_error_set(error, EINVAL,
7040                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7041                                                   actions,
7042                                                   "no fate action is found");
7043         } else {
7044                 if (!(action_flags & MLX5_FLOW_FATE_ACTIONS) && attr->ingress)
7045                         return rte_flow_error_set(error, EINVAL,
7046                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7047                                                   actions,
7048                                                   "no fate action is found");
7049         }
7050         /*
7051          * Continue validation for Xcap and VLAN actions.
7052          * If hairpin is working in explicit TX rule mode, there is no actions
7053          * splitting and the validation of hairpin ingress flow should be the
7054          * same as other standard flows.
7055          */
7056         if ((action_flags & (MLX5_FLOW_XCAP_ACTIONS |
7057                              MLX5_FLOW_VLAN_ACTIONS)) &&
7058             (queue_index == 0xFFFF ||
7059              mlx5_rxq_get_type(dev, queue_index) != MLX5_RXQ_TYPE_HAIRPIN ||
7060              ((conf = mlx5_rxq_get_hairpin_conf(dev, queue_index)) != NULL &&
7061              conf->tx_explicit != 0))) {
7062                 if ((action_flags & MLX5_FLOW_XCAP_ACTIONS) ==
7063                     MLX5_FLOW_XCAP_ACTIONS)
7064                         return rte_flow_error_set(error, ENOTSUP,
7065                                                   RTE_FLOW_ERROR_TYPE_ACTION,
7066                                                   NULL, "encap and decap "
7067                                                   "combination aren't supported");
7068                 if (!attr->transfer && attr->ingress) {
7069                         if (action_flags & MLX5_FLOW_ACTION_ENCAP)
7070                                 return rte_flow_error_set
7071                                                 (error, ENOTSUP,
7072                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7073                                                  NULL, "encap is not supported"
7074                                                  " for ingress traffic");
7075                         else if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
7076                                 return rte_flow_error_set
7077                                                 (error, ENOTSUP,
7078                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7079                                                  NULL, "push VLAN action not "
7080                                                  "supported for ingress");
7081                         else if ((action_flags & MLX5_FLOW_VLAN_ACTIONS) ==
7082                                         MLX5_FLOW_VLAN_ACTIONS)
7083                                 return rte_flow_error_set
7084                                                 (error, ENOTSUP,
7085                                                  RTE_FLOW_ERROR_TYPE_ACTION,
7086                                                  NULL, "no support for "
7087                                                  "multiple VLAN actions");
7088                 }
7089         }
7090         /*
7091          * Hairpin flow will add one more TAG action in TX implicit mode.
7092          * In TX explicit mode, there will be no hairpin flow ID.
7093          */
7094         if (hairpin > 0)
7095                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7096         /* extra metadata enabled: one more TAG action will be add. */
7097         if (dev_conf->dv_flow_en &&
7098             dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY &&
7099             mlx5_flow_ext_mreg_supported(dev))
7100                 rw_act_num += MLX5_ACT_NUM_SET_TAG;
7101         if (rw_act_num >
7102                         flow_dv_modify_hdr_action_max(dev, is_root)) {
7103                 return rte_flow_error_set(error, ENOTSUP,
7104                                           RTE_FLOW_ERROR_TYPE_ACTION,
7105                                           NULL, "too many header modify"
7106                                           " actions to support");
7107         }
7108         /* Eswitch egress mirror and modify flow has limitation on CX5 */
7109         if (fdb_mirror_limit && modify_after_mirror)
7110                 return rte_flow_error_set(error, EINVAL,
7111                                 RTE_FLOW_ERROR_TYPE_ACTION, NULL,
7112                                 "sample before modify action is not supported");
7113         return 0;
7114 }
7115
7116 /**
7117  * Internal preparation function. Allocates the DV flow size,
7118  * this size is constant.
7119  *
7120  * @param[in] dev
7121  *   Pointer to the rte_eth_dev structure.
7122  * @param[in] attr
7123  *   Pointer to the flow attributes.
7124  * @param[in] items
7125  *   Pointer to the list of items.
7126  * @param[in] actions
7127  *   Pointer to the list of actions.
7128  * @param[out] error
7129  *   Pointer to the error structure.
7130  *
7131  * @return
7132  *   Pointer to mlx5_flow object on success,
7133  *   otherwise NULL and rte_errno is set.
7134  */
7135 static struct mlx5_flow *
7136 flow_dv_prepare(struct rte_eth_dev *dev,
7137                 const struct rte_flow_attr *attr __rte_unused,
7138                 const struct rte_flow_item items[] __rte_unused,
7139                 const struct rte_flow_action actions[] __rte_unused,
7140                 struct rte_flow_error *error)
7141 {
7142         uint32_t handle_idx = 0;
7143         struct mlx5_flow *dev_flow;
7144         struct mlx5_flow_handle *dev_handle;
7145         struct mlx5_priv *priv = dev->data->dev_private;
7146         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
7147
7148         MLX5_ASSERT(wks);
7149         /* In case of corrupting the memory. */
7150         if (wks->flow_idx >= MLX5_NUM_MAX_DEV_FLOWS) {
7151                 rte_flow_error_set(error, ENOSPC,
7152                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7153                                    "not free temporary device flow");
7154                 return NULL;
7155         }
7156         dev_handle = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
7157                                    &handle_idx);
7158         if (!dev_handle) {
7159                 rte_flow_error_set(error, ENOMEM,
7160                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
7161                                    "not enough memory to create flow handle");
7162                 return NULL;
7163         }
7164         MLX5_ASSERT(wks->flow_idx < RTE_DIM(wks->flows));
7165         dev_flow = &wks->flows[wks->flow_idx++];
7166         memset(dev_flow, 0, sizeof(*dev_flow));
7167         dev_flow->handle = dev_handle;
7168         dev_flow->handle_idx = handle_idx;
7169         /*
7170          * In some old rdma-core releases, before continuing, a check of the
7171          * length of matching parameter will be done at first. It needs to use
7172          * the length without misc4 param. If the flow has misc4 support, then
7173          * the length needs to be adjusted accordingly. Each param member is
7174          * aligned with a 64B boundary naturally.
7175          */
7176         dev_flow->dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param) -
7177                                   MLX5_ST_SZ_BYTES(fte_match_set_misc4);
7178         dev_flow->ingress = attr->ingress;
7179         dev_flow->dv.transfer = attr->transfer;
7180         return dev_flow;
7181 }
7182
7183 #ifdef RTE_LIBRTE_MLX5_DEBUG
7184 /**
7185  * Sanity check for match mask and value. Similar to check_valid_spec() in
7186  * kernel driver. If unmasked bit is present in value, it returns failure.
7187  *
7188  * @param match_mask
7189  *   pointer to match mask buffer.
7190  * @param match_value
7191  *   pointer to match value buffer.
7192  *
7193  * @return
7194  *   0 if valid, -EINVAL otherwise.
7195  */
7196 static int
7197 flow_dv_check_valid_spec(void *match_mask, void *match_value)
7198 {
7199         uint8_t *m = match_mask;
7200         uint8_t *v = match_value;
7201         unsigned int i;
7202
7203         for (i = 0; i < MLX5_ST_SZ_BYTES(fte_match_param); ++i) {
7204                 if (v[i] & ~m[i]) {
7205                         DRV_LOG(ERR,
7206                                 "match_value differs from match_criteria"
7207                                 " %p[%u] != %p[%u]",
7208                                 match_value, i, match_mask, i);
7209                         return -EINVAL;
7210                 }
7211         }
7212         return 0;
7213 }
7214 #endif
7215
7216 /**
7217  * Add match of ip_version.
7218  *
7219  * @param[in] group
7220  *   Flow group.
7221  * @param[in] headers_v
7222  *   Values header pointer.
7223  * @param[in] headers_m
7224  *   Masks header pointer.
7225  * @param[in] ip_version
7226  *   The IP version to set.
7227  */
7228 static inline void
7229 flow_dv_set_match_ip_version(uint32_t group,
7230                              void *headers_v,
7231                              void *headers_m,
7232                              uint8_t ip_version)
7233 {
7234         if (group == 0)
7235                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version, 0xf);
7236         else
7237                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_version,
7238                          ip_version);
7239         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version, ip_version);
7240         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, 0);
7241         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ethertype, 0);
7242 }
7243
7244 /**
7245  * Add Ethernet item to matcher and to the value.
7246  *
7247  * @param[in, out] matcher
7248  *   Flow matcher.
7249  * @param[in, out] key
7250  *   Flow matcher value.
7251  * @param[in] item
7252  *   Flow pattern to translate.
7253  * @param[in] inner
7254  *   Item is inner pattern.
7255  */
7256 static void
7257 flow_dv_translate_item_eth(void *matcher, void *key,
7258                            const struct rte_flow_item *item, int inner,
7259                            uint32_t group)
7260 {
7261         const struct rte_flow_item_eth *eth_m = item->mask;
7262         const struct rte_flow_item_eth *eth_v = item->spec;
7263         const struct rte_flow_item_eth nic_mask = {
7264                 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7265                 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff",
7266                 .type = RTE_BE16(0xffff),
7267                 .has_vlan = 0,
7268         };
7269         void *hdrs_m;
7270         void *hdrs_v;
7271         char *l24_v;
7272         unsigned int i;
7273
7274         if (!eth_v)
7275                 return;
7276         if (!eth_m)
7277                 eth_m = &nic_mask;
7278         if (inner) {
7279                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7280                                          inner_headers);
7281                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7282         } else {
7283                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7284                                          outer_headers);
7285                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7286         }
7287         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, dmac_47_16),
7288                &eth_m->dst, sizeof(eth_m->dst));
7289         /* The value must be in the range of the mask. */
7290         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, dmac_47_16);
7291         for (i = 0; i < sizeof(eth_m->dst); ++i)
7292                 l24_v[i] = eth_m->dst.addr_bytes[i] & eth_v->dst.addr_bytes[i];
7293         memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_m, smac_47_16),
7294                &eth_m->src, sizeof(eth_m->src));
7295         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, smac_47_16);
7296         /* The value must be in the range of the mask. */
7297         for (i = 0; i < sizeof(eth_m->dst); ++i)
7298                 l24_v[i] = eth_m->src.addr_bytes[i] & eth_v->src.addr_bytes[i];
7299         /*
7300          * HW supports match on one Ethertype, the Ethertype following the last
7301          * VLAN tag of the packet (see PRM).
7302          * Set match on ethertype only if ETH header is not followed by VLAN.
7303          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7304          * ethertype, and use ip_version field instead.
7305          * eCPRI over Ether layer will use type value 0xAEFE.
7306          */
7307         if (eth_m->type == 0xFFFF) {
7308                 /* Set cvlan_tag mask for any single\multi\un-tagged case. */
7309                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7310                 switch (eth_v->type) {
7311                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7312                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7313                         return;
7314                 case RTE_BE16(RTE_ETHER_TYPE_QINQ):
7315                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7316                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7317                         return;
7318                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7319                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7320                         return;
7321                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7322                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7323                         return;
7324                 default:
7325                         break;
7326                 }
7327         }
7328         if (eth_m->has_vlan) {
7329                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7330                 if (eth_v->has_vlan) {
7331                         /*
7332                          * Here, when also has_more_vlan field in VLAN item is
7333                          * not set, only single-tagged packets will be matched.
7334                          */
7335                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7336                         return;
7337                 }
7338         }
7339         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7340                  rte_be_to_cpu_16(eth_m->type));
7341         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, hdrs_v, ethertype);
7342         *(uint16_t *)(l24_v) = eth_m->type & eth_v->type;
7343 }
7344
7345 /**
7346  * Add VLAN item to matcher and to the value.
7347  *
7348  * @param[in, out] dev_flow
7349  *   Flow descriptor.
7350  * @param[in, out] matcher
7351  *   Flow matcher.
7352  * @param[in, out] key
7353  *   Flow matcher value.
7354  * @param[in] item
7355  *   Flow pattern to translate.
7356  * @param[in] inner
7357  *   Item is inner pattern.
7358  */
7359 static void
7360 flow_dv_translate_item_vlan(struct mlx5_flow *dev_flow,
7361                             void *matcher, void *key,
7362                             const struct rte_flow_item *item,
7363                             int inner, uint32_t group)
7364 {
7365         const struct rte_flow_item_vlan *vlan_m = item->mask;
7366         const struct rte_flow_item_vlan *vlan_v = item->spec;
7367         void *hdrs_m;
7368         void *hdrs_v;
7369         uint16_t tci_m;
7370         uint16_t tci_v;
7371
7372         if (inner) {
7373                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7374                                          inner_headers);
7375                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7376         } else {
7377                 hdrs_m = MLX5_ADDR_OF(fte_match_param, matcher,
7378                                          outer_headers);
7379                 hdrs_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7380                 /*
7381                  * This is workaround, masks are not supported,
7382                  * and pre-validated.
7383                  */
7384                 if (vlan_v)
7385                         dev_flow->handle->vf_vlan.tag =
7386                                         rte_be_to_cpu_16(vlan_v->tci) & 0x0fff;
7387         }
7388         /*
7389          * When VLAN item exists in flow, mark packet as tagged,
7390          * even if TCI is not specified.
7391          */
7392         if (!MLX5_GET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag)) {
7393                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, cvlan_tag, 1);
7394                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 1);
7395         }
7396         if (!vlan_v)
7397                 return;
7398         if (!vlan_m)
7399                 vlan_m = &rte_flow_item_vlan_mask;
7400         tci_m = rte_be_to_cpu_16(vlan_m->tci);
7401         tci_v = rte_be_to_cpu_16(vlan_m->tci & vlan_v->tci);
7402         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_vid, tci_m);
7403         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_vid, tci_v);
7404         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_cfi, tci_m >> 12);
7405         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_cfi, tci_v >> 12);
7406         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, first_prio, tci_m >> 13);
7407         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, first_prio, tci_v >> 13);
7408         /*
7409          * HW is optimized for IPv4/IPv6. In such cases, avoid setting
7410          * ethertype, and use ip_version field instead.
7411          */
7412         if (vlan_m->inner_type == 0xFFFF) {
7413                 switch (vlan_v->inner_type) {
7414                 case RTE_BE16(RTE_ETHER_TYPE_VLAN):
7415                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7416                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7417                         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7418                         return;
7419                 case RTE_BE16(RTE_ETHER_TYPE_IPV4):
7420                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 4);
7421                         return;
7422                 case RTE_BE16(RTE_ETHER_TYPE_IPV6):
7423                         flow_dv_set_match_ip_version(group, hdrs_v, hdrs_m, 6);
7424                         return;
7425                 default:
7426                         break;
7427                 }
7428         }
7429         if (vlan_m->has_more_vlan && vlan_v->has_more_vlan) {
7430                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, svlan_tag, 1);
7431                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, svlan_tag, 1);
7432                 /* Only one vlan_tag bit can be set. */
7433                 MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, cvlan_tag, 0);
7434                 return;
7435         }
7436         MLX5_SET(fte_match_set_lyr_2_4, hdrs_m, ethertype,
7437                  rte_be_to_cpu_16(vlan_m->inner_type));
7438         MLX5_SET(fte_match_set_lyr_2_4, hdrs_v, ethertype,
7439                  rte_be_to_cpu_16(vlan_m->inner_type & vlan_v->inner_type));
7440 }
7441
7442 /**
7443  * Add IPV4 item to matcher and to the value.
7444  *
7445  * @param[in, out] matcher
7446  *   Flow matcher.
7447  * @param[in, out] key
7448  *   Flow matcher value.
7449  * @param[in] item
7450  *   Flow pattern to translate.
7451  * @param[in] inner
7452  *   Item is inner pattern.
7453  * @param[in] group
7454  *   The group to insert the rule.
7455  */
7456 static void
7457 flow_dv_translate_item_ipv4(void *matcher, void *key,
7458                             const struct rte_flow_item *item,
7459                             int inner, uint32_t group)
7460 {
7461         const struct rte_flow_item_ipv4 *ipv4_m = item->mask;
7462         const struct rte_flow_item_ipv4 *ipv4_v = item->spec;
7463         const struct rte_flow_item_ipv4 nic_mask = {
7464                 .hdr = {
7465                         .src_addr = RTE_BE32(0xffffffff),
7466                         .dst_addr = RTE_BE32(0xffffffff),
7467                         .type_of_service = 0xff,
7468                         .next_proto_id = 0xff,
7469                         .time_to_live = 0xff,
7470                 },
7471         };
7472         void *headers_m;
7473         void *headers_v;
7474         char *l24_m;
7475         char *l24_v;
7476         uint8_t tos;
7477
7478         if (inner) {
7479                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7480                                          inner_headers);
7481                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7482         } else {
7483                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7484                                          outer_headers);
7485                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7486         }
7487         flow_dv_set_match_ip_version(group, headers_v, headers_m, 4);
7488         if (!ipv4_v)
7489                 return;
7490         if (!ipv4_m)
7491                 ipv4_m = &nic_mask;
7492         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7493                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7494         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7495                              dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
7496         *(uint32_t *)l24_m = ipv4_m->hdr.dst_addr;
7497         *(uint32_t *)l24_v = ipv4_m->hdr.dst_addr & ipv4_v->hdr.dst_addr;
7498         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7499                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7500         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7501                           src_ipv4_src_ipv6.ipv4_layout.ipv4);
7502         *(uint32_t *)l24_m = ipv4_m->hdr.src_addr;
7503         *(uint32_t *)l24_v = ipv4_m->hdr.src_addr & ipv4_v->hdr.src_addr;
7504         tos = ipv4_m->hdr.type_of_service & ipv4_v->hdr.type_of_service;
7505         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn,
7506                  ipv4_m->hdr.type_of_service);
7507         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, tos);
7508         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp,
7509                  ipv4_m->hdr.type_of_service >> 2);
7510         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, tos >> 2);
7511         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7512                  ipv4_m->hdr.next_proto_id);
7513         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7514                  ipv4_v->hdr.next_proto_id & ipv4_m->hdr.next_proto_id);
7515         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7516                  ipv4_m->hdr.time_to_live);
7517         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7518                  ipv4_v->hdr.time_to_live & ipv4_m->hdr.time_to_live);
7519         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7520                  !!(ipv4_m->hdr.fragment_offset));
7521         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7522                  !!(ipv4_v->hdr.fragment_offset & ipv4_m->hdr.fragment_offset));
7523 }
7524
7525 /**
7526  * Add IPV6 item to matcher and to the value.
7527  *
7528  * @param[in, out] matcher
7529  *   Flow matcher.
7530  * @param[in, out] key
7531  *   Flow matcher value.
7532  * @param[in] item
7533  *   Flow pattern to translate.
7534  * @param[in] inner
7535  *   Item is inner pattern.
7536  * @param[in] group
7537  *   The group to insert the rule.
7538  */
7539 static void
7540 flow_dv_translate_item_ipv6(void *matcher, void *key,
7541                             const struct rte_flow_item *item,
7542                             int inner, uint32_t group)
7543 {
7544         const struct rte_flow_item_ipv6 *ipv6_m = item->mask;
7545         const struct rte_flow_item_ipv6 *ipv6_v = item->spec;
7546         const struct rte_flow_item_ipv6 nic_mask = {
7547                 .hdr = {
7548                         .src_addr =
7549                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7550                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7551                         .dst_addr =
7552                                 "\xff\xff\xff\xff\xff\xff\xff\xff"
7553                                 "\xff\xff\xff\xff\xff\xff\xff\xff",
7554                         .vtc_flow = RTE_BE32(0xffffffff),
7555                         .proto = 0xff,
7556                         .hop_limits = 0xff,
7557                 },
7558         };
7559         void *headers_m;
7560         void *headers_v;
7561         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7562         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7563         char *l24_m;
7564         char *l24_v;
7565         uint32_t vtc_m;
7566         uint32_t vtc_v;
7567         int i;
7568         int size;
7569
7570         if (inner) {
7571                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7572                                          inner_headers);
7573                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7574         } else {
7575                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7576                                          outer_headers);
7577                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7578         }
7579         flow_dv_set_match_ip_version(group, headers_v, headers_m, 6);
7580         if (!ipv6_v)
7581                 return;
7582         if (!ipv6_m)
7583                 ipv6_m = &nic_mask;
7584         size = sizeof(ipv6_m->hdr.dst_addr);
7585         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7586                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7587         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7588                              dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
7589         memcpy(l24_m, ipv6_m->hdr.dst_addr, size);
7590         for (i = 0; i < size; ++i)
7591                 l24_v[i] = l24_m[i] & ipv6_v->hdr.dst_addr[i];
7592         l24_m = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_m,
7593                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7594         l24_v = MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
7595                              src_ipv4_src_ipv6.ipv6_layout.ipv6);
7596         memcpy(l24_m, ipv6_m->hdr.src_addr, size);
7597         for (i = 0; i < size; ++i)
7598                 l24_v[i] = l24_m[i] & ipv6_v->hdr.src_addr[i];
7599         /* TOS. */
7600         vtc_m = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow);
7601         vtc_v = rte_be_to_cpu_32(ipv6_m->hdr.vtc_flow & ipv6_v->hdr.vtc_flow);
7602         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ecn, vtc_m >> 20);
7603         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, vtc_v >> 20);
7604         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_dscp, vtc_m >> 22);
7605         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, vtc_v >> 22);
7606         /* Label. */
7607         if (inner) {
7608                 MLX5_SET(fte_match_set_misc, misc_m, inner_ipv6_flow_label,
7609                          vtc_m);
7610                 MLX5_SET(fte_match_set_misc, misc_v, inner_ipv6_flow_label,
7611                          vtc_v);
7612         } else {
7613                 MLX5_SET(fte_match_set_misc, misc_m, outer_ipv6_flow_label,
7614                          vtc_m);
7615                 MLX5_SET(fte_match_set_misc, misc_v, outer_ipv6_flow_label,
7616                          vtc_v);
7617         }
7618         /* Protocol. */
7619         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7620                  ipv6_m->hdr.proto);
7621         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7622                  ipv6_v->hdr.proto & ipv6_m->hdr.proto);
7623         /* Hop limit. */
7624         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_ttl_hoplimit,
7625                  ipv6_m->hdr.hop_limits);
7626         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ttl_hoplimit,
7627                  ipv6_v->hdr.hop_limits & ipv6_m->hdr.hop_limits);
7628         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag,
7629                  !!(ipv6_m->has_frag_ext));
7630         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
7631                  !!(ipv6_v->has_frag_ext & ipv6_m->has_frag_ext));
7632 }
7633
7634 /**
7635  * Add IPV6 fragment extension item to matcher and to the value.
7636  *
7637  * @param[in, out] matcher
7638  *   Flow matcher.
7639  * @param[in, out] key
7640  *   Flow matcher value.
7641  * @param[in] item
7642  *   Flow pattern to translate.
7643  * @param[in] inner
7644  *   Item is inner pattern.
7645  */
7646 static void
7647 flow_dv_translate_item_ipv6_frag_ext(void *matcher, void *key,
7648                                      const struct rte_flow_item *item,
7649                                      int inner)
7650 {
7651         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_m = item->mask;
7652         const struct rte_flow_item_ipv6_frag_ext *ipv6_frag_ext_v = item->spec;
7653         const struct rte_flow_item_ipv6_frag_ext nic_mask = {
7654                 .hdr = {
7655                         .next_header = 0xff,
7656                         .frag_data = RTE_BE16(0xffff),
7657                 },
7658         };
7659         void *headers_m;
7660         void *headers_v;
7661
7662         if (inner) {
7663                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7664                                          inner_headers);
7665                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7666         } else {
7667                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7668                                          outer_headers);
7669                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7670         }
7671         /* IPv6 fragment extension item exists, so packet is IP fragment. */
7672         MLX5_SET(fte_match_set_lyr_2_4, headers_m, frag, 1);
7673         MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 1);
7674         if (!ipv6_frag_ext_v)
7675                 return;
7676         if (!ipv6_frag_ext_m)
7677                 ipv6_frag_ext_m = &nic_mask;
7678         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol,
7679                  ipv6_frag_ext_m->hdr.next_header);
7680         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
7681                  ipv6_frag_ext_v->hdr.next_header &
7682                  ipv6_frag_ext_m->hdr.next_header);
7683 }
7684
7685 /**
7686  * Add TCP item to matcher and to the value.
7687  *
7688  * @param[in, out] matcher
7689  *   Flow matcher.
7690  * @param[in, out] key
7691  *   Flow matcher value.
7692  * @param[in] item
7693  *   Flow pattern to translate.
7694  * @param[in] inner
7695  *   Item is inner pattern.
7696  */
7697 static void
7698 flow_dv_translate_item_tcp(void *matcher, void *key,
7699                            const struct rte_flow_item *item,
7700                            int inner)
7701 {
7702         const struct rte_flow_item_tcp *tcp_m = item->mask;
7703         const struct rte_flow_item_tcp *tcp_v = item->spec;
7704         void *headers_m;
7705         void *headers_v;
7706
7707         if (inner) {
7708                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7709                                          inner_headers);
7710                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7711         } else {
7712                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7713                                          outer_headers);
7714                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7715         }
7716         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7717         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_TCP);
7718         if (!tcp_v)
7719                 return;
7720         if (!tcp_m)
7721                 tcp_m = &rte_flow_item_tcp_mask;
7722         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_sport,
7723                  rte_be_to_cpu_16(tcp_m->hdr.src_port));
7724         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
7725                  rte_be_to_cpu_16(tcp_v->hdr.src_port & tcp_m->hdr.src_port));
7726         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_dport,
7727                  rte_be_to_cpu_16(tcp_m->hdr.dst_port));
7728         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
7729                  rte_be_to_cpu_16(tcp_v->hdr.dst_port & tcp_m->hdr.dst_port));
7730         MLX5_SET(fte_match_set_lyr_2_4, headers_m, tcp_flags,
7731                  tcp_m->hdr.tcp_flags);
7732         MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
7733                  (tcp_v->hdr.tcp_flags & tcp_m->hdr.tcp_flags));
7734 }
7735
7736 /**
7737  * Add UDP item to matcher and to the value.
7738  *
7739  * @param[in, out] matcher
7740  *   Flow matcher.
7741  * @param[in, out] key
7742  *   Flow matcher value.
7743  * @param[in] item
7744  *   Flow pattern to translate.
7745  * @param[in] inner
7746  *   Item is inner pattern.
7747  */
7748 static void
7749 flow_dv_translate_item_udp(void *matcher, void *key,
7750                            const struct rte_flow_item *item,
7751                            int inner)
7752 {
7753         const struct rte_flow_item_udp *udp_m = item->mask;
7754         const struct rte_flow_item_udp *udp_v = item->spec;
7755         void *headers_m;
7756         void *headers_v;
7757
7758         if (inner) {
7759                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7760                                          inner_headers);
7761                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7762         } else {
7763                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7764                                          outer_headers);
7765                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7766         }
7767         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7768         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
7769         if (!udp_v)
7770                 return;
7771         if (!udp_m)
7772                 udp_m = &rte_flow_item_udp_mask;
7773         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_sport,
7774                  rte_be_to_cpu_16(udp_m->hdr.src_port));
7775         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
7776                  rte_be_to_cpu_16(udp_v->hdr.src_port & udp_m->hdr.src_port));
7777         MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport,
7778                  rte_be_to_cpu_16(udp_m->hdr.dst_port));
7779         MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
7780                  rte_be_to_cpu_16(udp_v->hdr.dst_port & udp_m->hdr.dst_port));
7781 }
7782
7783 /**
7784  * Add GRE optional Key item to matcher and to the value.
7785  *
7786  * @param[in, out] matcher
7787  *   Flow matcher.
7788  * @param[in, out] key
7789  *   Flow matcher value.
7790  * @param[in] item
7791  *   Flow pattern to translate.
7792  * @param[in] inner
7793  *   Item is inner pattern.
7794  */
7795 static void
7796 flow_dv_translate_item_gre_key(void *matcher, void *key,
7797                                    const struct rte_flow_item *item)
7798 {
7799         const rte_be32_t *key_m = item->mask;
7800         const rte_be32_t *key_v = item->spec;
7801         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7802         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7803         rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX);
7804
7805         /* GRE K bit must be on and should already be validated */
7806         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present, 1);
7807         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present, 1);
7808         if (!key_v)
7809                 return;
7810         if (!key_m)
7811                 key_m = &gre_key_default_mask;
7812         MLX5_SET(fte_match_set_misc, misc_m, gre_key_h,
7813                  rte_be_to_cpu_32(*key_m) >> 8);
7814         MLX5_SET(fte_match_set_misc, misc_v, gre_key_h,
7815                  rte_be_to_cpu_32((*key_v) & (*key_m)) >> 8);
7816         MLX5_SET(fte_match_set_misc, misc_m, gre_key_l,
7817                  rte_be_to_cpu_32(*key_m) & 0xFF);
7818         MLX5_SET(fte_match_set_misc, misc_v, gre_key_l,
7819                  rte_be_to_cpu_32((*key_v) & (*key_m)) & 0xFF);
7820 }
7821
7822 /**
7823  * Add GRE item to matcher and to the value.
7824  *
7825  * @param[in, out] matcher
7826  *   Flow matcher.
7827  * @param[in, out] key
7828  *   Flow matcher value.
7829  * @param[in] item
7830  *   Flow pattern to translate.
7831  * @param[in] inner
7832  *   Item is inner pattern.
7833  */
7834 static void
7835 flow_dv_translate_item_gre(void *matcher, void *key,
7836                            const struct rte_flow_item *item,
7837                            int inner)
7838 {
7839         const struct rte_flow_item_gre *gre_m = item->mask;
7840         const struct rte_flow_item_gre *gre_v = item->spec;
7841         void *headers_m;
7842         void *headers_v;
7843         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7844         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7845         struct {
7846                 union {
7847                         __extension__
7848                         struct {
7849                                 uint16_t version:3;
7850                                 uint16_t rsvd0:9;
7851                                 uint16_t s_present:1;
7852                                 uint16_t k_present:1;
7853                                 uint16_t rsvd_bit1:1;
7854                                 uint16_t c_present:1;
7855                         };
7856                         uint16_t value;
7857                 };
7858         } gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
7859
7860         if (inner) {
7861                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7862                                          inner_headers);
7863                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7864         } else {
7865                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7866                                          outer_headers);
7867                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7868         }
7869         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
7870         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_GRE);
7871         if (!gre_v)
7872                 return;
7873         if (!gre_m)
7874                 gre_m = &rte_flow_item_gre_mask;
7875         MLX5_SET(fte_match_set_misc, misc_m, gre_protocol,
7876                  rte_be_to_cpu_16(gre_m->protocol));
7877         MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
7878                  rte_be_to_cpu_16(gre_v->protocol & gre_m->protocol));
7879         gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
7880         gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
7881         MLX5_SET(fte_match_set_misc, misc_m, gre_c_present,
7882                  gre_crks_rsvd0_ver_m.c_present);
7883         MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
7884                  gre_crks_rsvd0_ver_v.c_present &
7885                  gre_crks_rsvd0_ver_m.c_present);
7886         MLX5_SET(fte_match_set_misc, misc_m, gre_k_present,
7887                  gre_crks_rsvd0_ver_m.k_present);
7888         MLX5_SET(fte_match_set_misc, misc_v, gre_k_present,
7889                  gre_crks_rsvd0_ver_v.k_present &
7890                  gre_crks_rsvd0_ver_m.k_present);
7891         MLX5_SET(fte_match_set_misc, misc_m, gre_s_present,
7892                  gre_crks_rsvd0_ver_m.s_present);
7893         MLX5_SET(fte_match_set_misc, misc_v, gre_s_present,
7894                  gre_crks_rsvd0_ver_v.s_present &
7895                  gre_crks_rsvd0_ver_m.s_present);
7896 }
7897
7898 /**
7899  * Add NVGRE item to matcher and to the value.
7900  *
7901  * @param[in, out] matcher
7902  *   Flow matcher.
7903  * @param[in, out] key
7904  *   Flow matcher value.
7905  * @param[in] item
7906  *   Flow pattern to translate.
7907  * @param[in] inner
7908  *   Item is inner pattern.
7909  */
7910 static void
7911 flow_dv_translate_item_nvgre(void *matcher, void *key,
7912                              const struct rte_flow_item *item,
7913                              int inner)
7914 {
7915         const struct rte_flow_item_nvgre *nvgre_m = item->mask;
7916         const struct rte_flow_item_nvgre *nvgre_v = item->spec;
7917         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7918         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7919         const char *tni_flow_id_m;
7920         const char *tni_flow_id_v;
7921         char *gre_key_m;
7922         char *gre_key_v;
7923         int size;
7924         int i;
7925
7926         /* For NVGRE, GRE header fields must be set with defined values. */
7927         const struct rte_flow_item_gre gre_spec = {
7928                 .c_rsvd0_ver = RTE_BE16(0x2000),
7929                 .protocol = RTE_BE16(RTE_ETHER_TYPE_TEB)
7930         };
7931         const struct rte_flow_item_gre gre_mask = {
7932                 .c_rsvd0_ver = RTE_BE16(0xB000),
7933                 .protocol = RTE_BE16(UINT16_MAX),
7934         };
7935         const struct rte_flow_item gre_item = {
7936                 .spec = &gre_spec,
7937                 .mask = &gre_mask,
7938                 .last = NULL,
7939         };
7940         flow_dv_translate_item_gre(matcher, key, &gre_item, inner);
7941         if (!nvgre_v)
7942                 return;
7943         if (!nvgre_m)
7944                 nvgre_m = &rte_flow_item_nvgre_mask;
7945         tni_flow_id_m = (const char *)nvgre_m->tni;
7946         tni_flow_id_v = (const char *)nvgre_v->tni;
7947         size = sizeof(nvgre_m->tni) + sizeof(nvgre_m->flow_id);
7948         gre_key_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, gre_key_h);
7949         gre_key_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, gre_key_h);
7950         memcpy(gre_key_m, tni_flow_id_m, size);
7951         for (i = 0; i < size; ++i)
7952                 gre_key_v[i] = gre_key_m[i] & tni_flow_id_v[i];
7953 }
7954
7955 /**
7956  * Add VXLAN item to matcher and to the value.
7957  *
7958  * @param[in, out] matcher
7959  *   Flow matcher.
7960  * @param[in, out] key
7961  *   Flow matcher value.
7962  * @param[in] item
7963  *   Flow pattern to translate.
7964  * @param[in] inner
7965  *   Item is inner pattern.
7966  */
7967 static void
7968 flow_dv_translate_item_vxlan(void *matcher, void *key,
7969                              const struct rte_flow_item *item,
7970                              int inner)
7971 {
7972         const struct rte_flow_item_vxlan *vxlan_m = item->mask;
7973         const struct rte_flow_item_vxlan *vxlan_v = item->spec;
7974         void *headers_m;
7975         void *headers_v;
7976         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
7977         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
7978         char *vni_m;
7979         char *vni_v;
7980         uint16_t dport;
7981         int size;
7982         int i;
7983
7984         if (inner) {
7985                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7986                                          inner_headers);
7987                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
7988         } else {
7989                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
7990                                          outer_headers);
7991                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
7992         }
7993         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
7994                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
7995         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
7996                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
7997                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
7998         }
7999         if (!vxlan_v)
8000                 return;
8001         if (!vxlan_m)
8002                 vxlan_m = &rte_flow_item_vxlan_mask;
8003         size = sizeof(vxlan_m->vni);
8004         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, vxlan_vni);
8005         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, vxlan_vni);
8006         memcpy(vni_m, vxlan_m->vni, size);
8007         for (i = 0; i < size; ++i)
8008                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8009 }
8010
8011 /**
8012  * Add VXLAN-GPE item to matcher and to the value.
8013  *
8014  * @param[in, out] matcher
8015  *   Flow matcher.
8016  * @param[in, out] key
8017  *   Flow matcher value.
8018  * @param[in] item
8019  *   Flow pattern to translate.
8020  * @param[in] inner
8021  *   Item is inner pattern.
8022  */
8023
8024 static void
8025 flow_dv_translate_item_vxlan_gpe(void *matcher, void *key,
8026                                  const struct rte_flow_item *item, int inner)
8027 {
8028         const struct rte_flow_item_vxlan_gpe *vxlan_m = item->mask;
8029         const struct rte_flow_item_vxlan_gpe *vxlan_v = item->spec;
8030         void *headers_m;
8031         void *headers_v;
8032         void *misc_m =
8033                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_3);
8034         void *misc_v =
8035                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8036         char *vni_m;
8037         char *vni_v;
8038         uint16_t dport;
8039         int size;
8040         int i;
8041         uint8_t flags_m = 0xff;
8042         uint8_t flags_v = 0xc;
8043
8044         if (inner) {
8045                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8046                                          inner_headers);
8047                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8048         } else {
8049                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8050                                          outer_headers);
8051                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8052         }
8053         dport = item->type == RTE_FLOW_ITEM_TYPE_VXLAN ?
8054                 MLX5_UDP_PORT_VXLAN : MLX5_UDP_PORT_VXLAN_GPE;
8055         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8056                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8057                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8058         }
8059         if (!vxlan_v)
8060                 return;
8061         if (!vxlan_m)
8062                 vxlan_m = &rte_flow_item_vxlan_gpe_mask;
8063         size = sizeof(vxlan_m->vni);
8064         vni_m = MLX5_ADDR_OF(fte_match_set_misc3, misc_m, outer_vxlan_gpe_vni);
8065         vni_v = MLX5_ADDR_OF(fte_match_set_misc3, misc_v, outer_vxlan_gpe_vni);
8066         memcpy(vni_m, vxlan_m->vni, size);
8067         for (i = 0; i < size; ++i)
8068                 vni_v[i] = vni_m[i] & vxlan_v->vni[i];
8069         if (vxlan_m->flags) {
8070                 flags_m = vxlan_m->flags;
8071                 flags_v = vxlan_v->flags;
8072         }
8073         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_flags, flags_m);
8074         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_flags, flags_v);
8075         MLX5_SET(fte_match_set_misc3, misc_m, outer_vxlan_gpe_next_protocol,
8076                  vxlan_m->protocol);
8077         MLX5_SET(fte_match_set_misc3, misc_v, outer_vxlan_gpe_next_protocol,
8078                  vxlan_v->protocol);
8079 }
8080
8081 /**
8082  * Add Geneve item to matcher and to the value.
8083  *
8084  * @param[in, out] matcher
8085  *   Flow matcher.
8086  * @param[in, out] key
8087  *   Flow matcher value.
8088  * @param[in] item
8089  *   Flow pattern to translate.
8090  * @param[in] inner
8091  *   Item is inner pattern.
8092  */
8093
8094 static void
8095 flow_dv_translate_item_geneve(void *matcher, void *key,
8096                               const struct rte_flow_item *item, int inner)
8097 {
8098         const struct rte_flow_item_geneve *geneve_m = item->mask;
8099         const struct rte_flow_item_geneve *geneve_v = item->spec;
8100         void *headers_m;
8101         void *headers_v;
8102         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8103         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8104         uint16_t dport;
8105         uint16_t gbhdr_m;
8106         uint16_t gbhdr_v;
8107         char *vni_m;
8108         char *vni_v;
8109         size_t size, i;
8110
8111         if (inner) {
8112                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8113                                          inner_headers);
8114                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8115         } else {
8116                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8117                                          outer_headers);
8118                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8119         }
8120         dport = MLX5_UDP_PORT_GENEVE;
8121         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8122                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8123                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8124         }
8125         if (!geneve_v)
8126                 return;
8127         if (!geneve_m)
8128                 geneve_m = &rte_flow_item_geneve_mask;
8129         size = sizeof(geneve_m->vni);
8130         vni_m = MLX5_ADDR_OF(fte_match_set_misc, misc_m, geneve_vni);
8131         vni_v = MLX5_ADDR_OF(fte_match_set_misc, misc_v, geneve_vni);
8132         memcpy(vni_m, geneve_m->vni, size);
8133         for (i = 0; i < size; ++i)
8134                 vni_v[i] = vni_m[i] & geneve_v->vni[i];
8135         MLX5_SET(fte_match_set_misc, misc_m, geneve_protocol_type,
8136                  rte_be_to_cpu_16(geneve_m->protocol));
8137         MLX5_SET(fte_match_set_misc, misc_v, geneve_protocol_type,
8138                  rte_be_to_cpu_16(geneve_v->protocol & geneve_m->protocol));
8139         gbhdr_m = rte_be_to_cpu_16(geneve_m->ver_opt_len_o_c_rsvd0);
8140         gbhdr_v = rte_be_to_cpu_16(geneve_v->ver_opt_len_o_c_rsvd0);
8141         MLX5_SET(fte_match_set_misc, misc_m, geneve_oam,
8142                  MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8143         MLX5_SET(fte_match_set_misc, misc_v, geneve_oam,
8144                  MLX5_GENEVE_OAMF_VAL(gbhdr_v) & MLX5_GENEVE_OAMF_VAL(gbhdr_m));
8145         MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8146                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8147         MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8148                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_v) &
8149                  MLX5_GENEVE_OPTLEN_VAL(gbhdr_m));
8150 }
8151
8152 /**
8153  * Create Geneve TLV option resource.
8154  *
8155  * @param dev[in, out]
8156  *   Pointer to rte_eth_dev structure.
8157  * @param[in, out] tag_be24
8158  *   Tag value in big endian then R-shift 8.
8159  * @parm[in, out] dev_flow
8160  *   Pointer to the dev_flow.
8161  * @param[out] error
8162  *   pointer to error structure.
8163  *
8164  * @return
8165  *   0 on success otherwise -errno and errno is set.
8166  */
8167
8168 int
8169 flow_dev_geneve_tlv_option_resource_register(struct rte_eth_dev *dev,
8170                                              const struct rte_flow_item *item,
8171                                              struct rte_flow_error *error)
8172 {
8173         struct mlx5_priv *priv = dev->data->dev_private;
8174         struct mlx5_dev_ctx_shared *sh = priv->sh;
8175         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
8176                         sh->geneve_tlv_option_resource;
8177         struct mlx5_devx_obj *obj;
8178         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8179         int ret = 0;
8180
8181         if (!geneve_opt_v)
8182                 return -1;
8183         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
8184         if (geneve_opt_resource != NULL) {
8185                 if (geneve_opt_resource->option_class ==
8186                         geneve_opt_v->option_class &&
8187                         geneve_opt_resource->option_type ==
8188                         geneve_opt_v->option_type &&
8189                         geneve_opt_resource->length ==
8190                         geneve_opt_v->option_len) {
8191                         /* We already have GENVE TLV option obj allocated. */
8192                         __atomic_fetch_add(&geneve_opt_resource->refcnt, 1,
8193                                            __ATOMIC_RELAXED);
8194                 } else {
8195                         ret = rte_flow_error_set(error, ENOMEM,
8196                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8197                                 "Only one GENEVE TLV option supported");
8198                         goto exit;
8199                 }
8200         } else {
8201                 /* Create a GENEVE TLV object and resource. */
8202                 obj = mlx5_devx_cmd_create_geneve_tlv_option(sh->ctx,
8203                                 geneve_opt_v->option_class,
8204                                 geneve_opt_v->option_type,
8205                                 geneve_opt_v->option_len);
8206                 if (!obj) {
8207                         ret = rte_flow_error_set(error, ENODATA,
8208                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8209                                 "Failed to create GENEVE TLV Devx object");
8210                         goto exit;
8211                 }
8212                 sh->geneve_tlv_option_resource =
8213                                 mlx5_malloc(MLX5_MEM_ZERO,
8214                                                 sizeof(*geneve_opt_resource),
8215                                                 0, SOCKET_ID_ANY);
8216                 if (!sh->geneve_tlv_option_resource) {
8217                         claim_zero(mlx5_devx_cmd_destroy(obj));
8218                         ret = rte_flow_error_set(error, ENOMEM,
8219                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
8220                                 "GENEVE TLV object memory allocation failed");
8221                         goto exit;
8222                 }
8223                 geneve_opt_resource = sh->geneve_tlv_option_resource;
8224                 geneve_opt_resource->obj = obj;
8225                 geneve_opt_resource->option_class = geneve_opt_v->option_class;
8226                 geneve_opt_resource->option_type = geneve_opt_v->option_type;
8227                 geneve_opt_resource->length = geneve_opt_v->option_len;
8228                 __atomic_store_n(&geneve_opt_resource->refcnt, 1,
8229                                 __ATOMIC_RELAXED);
8230         }
8231 exit:
8232         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
8233         return ret;
8234 }
8235
8236 /**
8237  * Add Geneve TLV option item to matcher.
8238  *
8239  * @param[in, out] dev
8240  *   Pointer to rte_eth_dev structure.
8241  * @param[in, out] matcher
8242  *   Flow matcher.
8243  * @param[in, out] key
8244  *   Flow matcher value.
8245  * @param[in] item
8246  *   Flow pattern to translate.
8247  * @param[out] error
8248  *   Pointer to error structure.
8249  */
8250 static int
8251 flow_dv_translate_item_geneve_opt(struct rte_eth_dev *dev, void *matcher,
8252                                   void *key, const struct rte_flow_item *item,
8253                                   struct rte_flow_error *error)
8254 {
8255         const struct rte_flow_item_geneve_opt *geneve_opt_m = item->mask;
8256         const struct rte_flow_item_geneve_opt *geneve_opt_v = item->spec;
8257         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8258         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8259         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8260                         misc_parameters_3);
8261         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8262         rte_be32_t opt_data_key = 0, opt_data_mask = 0;
8263         int ret = 0;
8264
8265         if (!geneve_opt_v)
8266                 return -1;
8267         if (!geneve_opt_m)
8268                 geneve_opt_m = &rte_flow_item_geneve_opt_mask;
8269         ret = flow_dev_geneve_tlv_option_resource_register(dev, item,
8270                                                            error);
8271         if (ret) {
8272                 DRV_LOG(ERR, "Failed to create geneve_tlv_obj");
8273                 return ret;
8274         }
8275         /*
8276          * Set the option length in GENEVE header if not requested.
8277          * The GENEVE TLV option length is expressed by the option length field
8278          * in the GENEVE header.
8279          * If the option length was not requested but the GENEVE TLV option item
8280          * is present we set the option length field implicitly.
8281          */
8282         if (!MLX5_GET16(fte_match_set_misc, misc_m, geneve_opt_len)) {
8283                 MLX5_SET(fte_match_set_misc, misc_m, geneve_opt_len,
8284                          MLX5_GENEVE_OPTLEN_MASK);
8285                 MLX5_SET(fte_match_set_misc, misc_v, geneve_opt_len,
8286                          geneve_opt_v->option_len + 1);
8287         }
8288         /* Set the data. */
8289         if (geneve_opt_v->data) {
8290                 memcpy(&opt_data_key, geneve_opt_v->data,
8291                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8292                                 sizeof(opt_data_key)));
8293                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8294                                 sizeof(opt_data_key));
8295                 memcpy(&opt_data_mask, geneve_opt_m->data,
8296                         RTE_MIN((uint32_t)(geneve_opt_v->option_len * 4),
8297                                 sizeof(opt_data_mask)));
8298                 MLX5_ASSERT((uint32_t)(geneve_opt_v->option_len * 4) <=
8299                                 sizeof(opt_data_mask));
8300                 MLX5_SET(fte_match_set_misc3, misc3_m,
8301                                 geneve_tlv_option_0_data,
8302                                 rte_be_to_cpu_32(opt_data_mask));
8303                 MLX5_SET(fte_match_set_misc3, misc3_v,
8304                                 geneve_tlv_option_0_data,
8305                         rte_be_to_cpu_32(opt_data_key & opt_data_mask));
8306         }
8307         return ret;
8308 }
8309
8310 /**
8311  * Add MPLS item to matcher and to the value.
8312  *
8313  * @param[in, out] matcher
8314  *   Flow matcher.
8315  * @param[in, out] key
8316  *   Flow matcher value.
8317  * @param[in] item
8318  *   Flow pattern to translate.
8319  * @param[in] prev_layer
8320  *   The protocol layer indicated in previous item.
8321  * @param[in] inner
8322  *   Item is inner pattern.
8323  */
8324 static void
8325 flow_dv_translate_item_mpls(void *matcher, void *key,
8326                             const struct rte_flow_item *item,
8327                             uint64_t prev_layer,
8328                             int inner)
8329 {
8330         const uint32_t *in_mpls_m = item->mask;
8331         const uint32_t *in_mpls_v = item->spec;
8332         uint32_t *out_mpls_m = 0;
8333         uint32_t *out_mpls_v = 0;
8334         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8335         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8336         void *misc2_m = MLX5_ADDR_OF(fte_match_param, matcher,
8337                                      misc_parameters_2);
8338         void *misc2_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8339         void *headers_m = MLX5_ADDR_OF(fte_match_param, matcher, outer_headers);
8340         void *headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8341
8342         switch (prev_layer) {
8343         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8344                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xffff);
8345                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
8346                          MLX5_UDP_PORT_MPLS);
8347                 break;
8348         case MLX5_FLOW_LAYER_GRE:
8349                 MLX5_SET(fte_match_set_misc, misc_m, gre_protocol, 0xffff);
8350                 MLX5_SET(fte_match_set_misc, misc_v, gre_protocol,
8351                          RTE_ETHER_TYPE_MPLS);
8352                 break;
8353         default:
8354                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xff);
8355                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
8356                          IPPROTO_MPLS);
8357                 break;
8358         }
8359         if (!in_mpls_v)
8360                 return;
8361         if (!in_mpls_m)
8362                 in_mpls_m = (const uint32_t *)&rte_flow_item_mpls_mask;
8363         switch (prev_layer) {
8364         case MLX5_FLOW_LAYER_OUTER_L4_UDP:
8365                 out_mpls_m =
8366                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8367                                                  outer_first_mpls_over_udp);
8368                 out_mpls_v =
8369                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8370                                                  outer_first_mpls_over_udp);
8371                 break;
8372         case MLX5_FLOW_LAYER_GRE:
8373                 out_mpls_m =
8374                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_m,
8375                                                  outer_first_mpls_over_gre);
8376                 out_mpls_v =
8377                         (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2, misc2_v,
8378                                                  outer_first_mpls_over_gre);
8379                 break;
8380         default:
8381                 /* Inner MPLS not over GRE is not supported. */
8382                 if (!inner) {
8383                         out_mpls_m =
8384                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8385                                                          misc2_m,
8386                                                          outer_first_mpls);
8387                         out_mpls_v =
8388                                 (uint32_t *)MLX5_ADDR_OF(fte_match_set_misc2,
8389                                                          misc2_v,
8390                                                          outer_first_mpls);
8391                 }
8392                 break;
8393         }
8394         if (out_mpls_m && out_mpls_v) {
8395                 *out_mpls_m = *in_mpls_m;
8396                 *out_mpls_v = *in_mpls_v & *in_mpls_m;
8397         }
8398 }
8399
8400 /**
8401  * Add metadata register item to matcher
8402  *
8403  * @param[in, out] matcher
8404  *   Flow matcher.
8405  * @param[in, out] key
8406  *   Flow matcher value.
8407  * @param[in] reg_type
8408  *   Type of device metadata register
8409  * @param[in] value
8410  *   Register value
8411  * @param[in] mask
8412  *   Register mask
8413  */
8414 static void
8415 flow_dv_match_meta_reg(void *matcher, void *key,
8416                        enum modify_reg reg_type,
8417                        uint32_t data, uint32_t mask)
8418 {
8419         void *misc2_m =
8420                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters_2);
8421         void *misc2_v =
8422                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters_2);
8423         uint32_t temp;
8424
8425         data &= mask;
8426         switch (reg_type) {
8427         case REG_A:
8428                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_a, mask);
8429                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_a, data);
8430                 break;
8431         case REG_B:
8432                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_b, mask);
8433                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_b, data);
8434                 break;
8435         case REG_C_0:
8436                 /*
8437                  * The metadata register C0 field might be divided into
8438                  * source vport index and META item value, we should set
8439                  * this field according to specified mask, not as whole one.
8440                  */
8441                 temp = MLX5_GET(fte_match_set_misc2, misc2_m, metadata_reg_c_0);
8442                 temp |= mask;
8443                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_0, temp);
8444                 temp = MLX5_GET(fte_match_set_misc2, misc2_v, metadata_reg_c_0);
8445                 temp &= ~mask;
8446                 temp |= data;
8447                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_0, temp);
8448                 break;
8449         case REG_C_1:
8450                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_1, mask);
8451                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_1, data);
8452                 break;
8453         case REG_C_2:
8454                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_2, mask);
8455                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_2, data);
8456                 break;
8457         case REG_C_3:
8458                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_3, mask);
8459                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_3, data);
8460                 break;
8461         case REG_C_4:
8462                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_4, mask);
8463                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_4, data);
8464                 break;
8465         case REG_C_5:
8466                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_5, mask);
8467                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_5, data);
8468                 break;
8469         case REG_C_6:
8470                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_6, mask);
8471                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_6, data);
8472                 break;
8473         case REG_C_7:
8474                 MLX5_SET(fte_match_set_misc2, misc2_m, metadata_reg_c_7, mask);
8475                 MLX5_SET(fte_match_set_misc2, misc2_v, metadata_reg_c_7, data);
8476                 break;
8477         default:
8478                 MLX5_ASSERT(false);
8479                 break;
8480         }
8481 }
8482
8483 /**
8484  * Add MARK item to matcher
8485  *
8486  * @param[in] dev
8487  *   The device to configure through.
8488  * @param[in, out] matcher
8489  *   Flow matcher.
8490  * @param[in, out] key
8491  *   Flow matcher value.
8492  * @param[in] item
8493  *   Flow pattern to translate.
8494  */
8495 static void
8496 flow_dv_translate_item_mark(struct rte_eth_dev *dev,
8497                             void *matcher, void *key,
8498                             const struct rte_flow_item *item)
8499 {
8500         struct mlx5_priv *priv = dev->data->dev_private;
8501         const struct rte_flow_item_mark *mark;
8502         uint32_t value;
8503         uint32_t mask;
8504
8505         mark = item->mask ? (const void *)item->mask :
8506                             &rte_flow_item_mark_mask;
8507         mask = mark->id & priv->sh->dv_mark_mask;
8508         mark = (const void *)item->spec;
8509         MLX5_ASSERT(mark);
8510         value = mark->id & priv->sh->dv_mark_mask & mask;
8511         if (mask) {
8512                 enum modify_reg reg;
8513
8514                 /* Get the metadata register index for the mark. */
8515                 reg = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, NULL);
8516                 MLX5_ASSERT(reg > 0);
8517                 if (reg == REG_C_0) {
8518                         struct mlx5_priv *priv = dev->data->dev_private;
8519                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8520                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8521
8522                         mask &= msk_c0;
8523                         mask <<= shl_c0;
8524                         value <<= shl_c0;
8525                 }
8526                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8527         }
8528 }
8529
8530 /**
8531  * Add META item to matcher
8532  *
8533  * @param[in] dev
8534  *   The devich to configure through.
8535  * @param[in, out] matcher
8536  *   Flow matcher.
8537  * @param[in, out] key
8538  *   Flow matcher value.
8539  * @param[in] attr
8540  *   Attributes of flow that includes this item.
8541  * @param[in] item
8542  *   Flow pattern to translate.
8543  */
8544 static void
8545 flow_dv_translate_item_meta(struct rte_eth_dev *dev,
8546                             void *matcher, void *key,
8547                             const struct rte_flow_attr *attr,
8548                             const struct rte_flow_item *item)
8549 {
8550         const struct rte_flow_item_meta *meta_m;
8551         const struct rte_flow_item_meta *meta_v;
8552
8553         meta_m = (const void *)item->mask;
8554         if (!meta_m)
8555                 meta_m = &rte_flow_item_meta_mask;
8556         meta_v = (const void *)item->spec;
8557         if (meta_v) {
8558                 int reg;
8559                 uint32_t value = meta_v->data;
8560                 uint32_t mask = meta_m->data;
8561
8562                 reg = flow_dv_get_metadata_reg(dev, attr, NULL);
8563                 if (reg < 0)
8564                         return;
8565                 MLX5_ASSERT(reg != REG_NON);
8566                 /*
8567                  * In datapath code there is no endianness
8568                  * coversions for perfromance reasons, all
8569                  * pattern conversions are done in rte_flow.
8570                  */
8571                 value = rte_cpu_to_be_32(value);
8572                 mask = rte_cpu_to_be_32(mask);
8573                 if (reg == REG_C_0) {
8574                         struct mlx5_priv *priv = dev->data->dev_private;
8575                         uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8576                         uint32_t shl_c0 = rte_bsf32(msk_c0);
8577 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
8578                         uint32_t shr_c0 = __builtin_clz(priv->sh->dv_meta_mask);
8579
8580                         value >>= shr_c0;
8581                         mask >>= shr_c0;
8582 #endif
8583                         value <<= shl_c0;
8584                         mask <<= shl_c0;
8585                         MLX5_ASSERT(msk_c0);
8586                         MLX5_ASSERT(!(~msk_c0 & mask));
8587                 }
8588                 flow_dv_match_meta_reg(matcher, key, reg, value, mask);
8589         }
8590 }
8591
8592 /**
8593  * Add vport metadata Reg C0 item to matcher
8594  *
8595  * @param[in, out] matcher
8596  *   Flow matcher.
8597  * @param[in, out] key
8598  *   Flow matcher value.
8599  * @param[in] reg
8600  *   Flow pattern to translate.
8601  */
8602 static void
8603 flow_dv_translate_item_meta_vport(void *matcher, void *key,
8604                                   uint32_t value, uint32_t mask)
8605 {
8606         flow_dv_match_meta_reg(matcher, key, REG_C_0, value, mask);
8607 }
8608
8609 /**
8610  * Add tag item to matcher
8611  *
8612  * @param[in] dev
8613  *   The devich to configure through.
8614  * @param[in, out] matcher
8615  *   Flow matcher.
8616  * @param[in, out] key
8617  *   Flow matcher value.
8618  * @param[in] item
8619  *   Flow pattern to translate.
8620  */
8621 static void
8622 flow_dv_translate_mlx5_item_tag(struct rte_eth_dev *dev,
8623                                 void *matcher, void *key,
8624                                 const struct rte_flow_item *item)
8625 {
8626         const struct mlx5_rte_flow_item_tag *tag_v = item->spec;
8627         const struct mlx5_rte_flow_item_tag *tag_m = item->mask;
8628         uint32_t mask, value;
8629
8630         MLX5_ASSERT(tag_v);
8631         value = tag_v->data;
8632         mask = tag_m ? tag_m->data : UINT32_MAX;
8633         if (tag_v->id == REG_C_0) {
8634                 struct mlx5_priv *priv = dev->data->dev_private;
8635                 uint32_t msk_c0 = priv->sh->dv_regc0_mask;
8636                 uint32_t shl_c0 = rte_bsf32(msk_c0);
8637
8638                 mask &= msk_c0;
8639                 mask <<= shl_c0;
8640                 value <<= shl_c0;
8641         }
8642         flow_dv_match_meta_reg(matcher, key, tag_v->id, value, mask);
8643 }
8644
8645 /**
8646  * Add TAG item to matcher
8647  *
8648  * @param[in] dev
8649  *   The devich to configure through.
8650  * @param[in, out] matcher
8651  *   Flow matcher.
8652  * @param[in, out] key
8653  *   Flow matcher value.
8654  * @param[in] item
8655  *   Flow pattern to translate.
8656  */
8657 static void
8658 flow_dv_translate_item_tag(struct rte_eth_dev *dev,
8659                            void *matcher, void *key,
8660                            const struct rte_flow_item *item)
8661 {
8662         const struct rte_flow_item_tag *tag_v = item->spec;
8663         const struct rte_flow_item_tag *tag_m = item->mask;
8664         enum modify_reg reg;
8665
8666         MLX5_ASSERT(tag_v);
8667         tag_m = tag_m ? tag_m : &rte_flow_item_tag_mask;
8668         /* Get the metadata register index for the tag. */
8669         reg = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, tag_v->index, NULL);
8670         MLX5_ASSERT(reg > 0);
8671         flow_dv_match_meta_reg(matcher, key, reg, tag_v->data, tag_m->data);
8672 }
8673
8674 /**
8675  * Add source vport match to the specified matcher.
8676  *
8677  * @param[in, out] matcher
8678  *   Flow matcher.
8679  * @param[in, out] key
8680  *   Flow matcher value.
8681  * @param[in] port
8682  *   Source vport value to match
8683  * @param[in] mask
8684  *   Mask
8685  */
8686 static void
8687 flow_dv_translate_item_source_vport(void *matcher, void *key,
8688                                     int16_t port, uint16_t mask)
8689 {
8690         void *misc_m = MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
8691         void *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
8692
8693         MLX5_SET(fte_match_set_misc, misc_m, source_port, mask);
8694         MLX5_SET(fte_match_set_misc, misc_v, source_port, port);
8695 }
8696
8697 /**
8698  * Translate port-id item to eswitch match on  port-id.
8699  *
8700  * @param[in] dev
8701  *   The devich to configure through.
8702  * @param[in, out] matcher
8703  *   Flow matcher.
8704  * @param[in, out] key
8705  *   Flow matcher value.
8706  * @param[in] item
8707  *   Flow pattern to translate.
8708  * @param[in]
8709  *   Flow attributes.
8710  *
8711  * @return
8712  *   0 on success, a negative errno value otherwise.
8713  */
8714 static int
8715 flow_dv_translate_item_port_id(struct rte_eth_dev *dev, void *matcher,
8716                                void *key, const struct rte_flow_item *item,
8717                                const struct rte_flow_attr *attr)
8718 {
8719         const struct rte_flow_item_port_id *pid_m = item ? item->mask : NULL;
8720         const struct rte_flow_item_port_id *pid_v = item ? item->spec : NULL;
8721         struct mlx5_priv *priv;
8722         uint16_t mask, id;
8723
8724         mask = pid_m ? pid_m->id : 0xffff;
8725         id = pid_v ? pid_v->id : dev->data->port_id;
8726         priv = mlx5_port_to_eswitch_info(id, item == NULL);
8727         if (!priv)
8728                 return -rte_errno;
8729         /*
8730          * Translate to vport field or to metadata, depending on mode.
8731          * Kernel can use either misc.source_port or half of C0 metadata
8732          * register.
8733          */
8734         if (priv->vport_meta_mask) {
8735                 /*
8736                  * Provide the hint for SW steering library
8737                  * to insert the flow into ingress domain and
8738                  * save the extra vport match.
8739                  */
8740                 if (mask == 0xffff && priv->vport_id == 0xffff &&
8741                     priv->pf_bond < 0 && attr->transfer)
8742                         flow_dv_translate_item_source_vport
8743                                 (matcher, key, priv->vport_id, mask);
8744                 /*
8745                  * We should always set the vport metadata register,
8746                  * otherwise the SW steering library can drop
8747                  * the rule if wire vport metadata value is not zero,
8748                  * it depends on kernel configuration.
8749                  */
8750                 flow_dv_translate_item_meta_vport(matcher, key,
8751                                                   priv->vport_meta_tag,
8752                                                   priv->vport_meta_mask);
8753         } else {
8754                 flow_dv_translate_item_source_vport(matcher, key,
8755                                                     priv->vport_id, mask);
8756         }
8757         return 0;
8758 }
8759
8760 /**
8761  * Add ICMP6 item to matcher and to the value.
8762  *
8763  * @param[in, out] matcher
8764  *   Flow matcher.
8765  * @param[in, out] key
8766  *   Flow matcher value.
8767  * @param[in] item
8768  *   Flow pattern to translate.
8769  * @param[in] inner
8770  *   Item is inner pattern.
8771  */
8772 static void
8773 flow_dv_translate_item_icmp6(void *matcher, void *key,
8774                               const struct rte_flow_item *item,
8775                               int inner)
8776 {
8777         const struct rte_flow_item_icmp6 *icmp6_m = item->mask;
8778         const struct rte_flow_item_icmp6 *icmp6_v = item->spec;
8779         void *headers_m;
8780         void *headers_v;
8781         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8782                                      misc_parameters_3);
8783         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8784         if (inner) {
8785                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8786                                          inner_headers);
8787                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8788         } else {
8789                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8790                                          outer_headers);
8791                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8792         }
8793         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8794         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMPV6);
8795         if (!icmp6_v)
8796                 return;
8797         if (!icmp6_m)
8798                 icmp6_m = &rte_flow_item_icmp6_mask;
8799         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_type, icmp6_m->type);
8800         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_type,
8801                  icmp6_v->type & icmp6_m->type);
8802         MLX5_SET(fte_match_set_misc3, misc3_m, icmpv6_code, icmp6_m->code);
8803         MLX5_SET(fte_match_set_misc3, misc3_v, icmpv6_code,
8804                  icmp6_v->code & icmp6_m->code);
8805 }
8806
8807 /**
8808  * Add ICMP item to matcher and to the value.
8809  *
8810  * @param[in, out] matcher
8811  *   Flow matcher.
8812  * @param[in, out] key
8813  *   Flow matcher value.
8814  * @param[in] item
8815  *   Flow pattern to translate.
8816  * @param[in] inner
8817  *   Item is inner pattern.
8818  */
8819 static void
8820 flow_dv_translate_item_icmp(void *matcher, void *key,
8821                             const struct rte_flow_item *item,
8822                             int inner)
8823 {
8824         const struct rte_flow_item_icmp *icmp_m = item->mask;
8825         const struct rte_flow_item_icmp *icmp_v = item->spec;
8826         uint32_t icmp_header_data_m = 0;
8827         uint32_t icmp_header_data_v = 0;
8828         void *headers_m;
8829         void *headers_v;
8830         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8831                                      misc_parameters_3);
8832         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8833         if (inner) {
8834                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8835                                          inner_headers);
8836                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8837         } else {
8838                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8839                                          outer_headers);
8840                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8841         }
8842         MLX5_SET(fte_match_set_lyr_2_4, headers_m, ip_protocol, 0xFF);
8843         MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_ICMP);
8844         if (!icmp_v)
8845                 return;
8846         if (!icmp_m)
8847                 icmp_m = &rte_flow_item_icmp_mask;
8848         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_type,
8849                  icmp_m->hdr.icmp_type);
8850         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_type,
8851                  icmp_v->hdr.icmp_type & icmp_m->hdr.icmp_type);
8852         MLX5_SET(fte_match_set_misc3, misc3_m, icmp_code,
8853                  icmp_m->hdr.icmp_code);
8854         MLX5_SET(fte_match_set_misc3, misc3_v, icmp_code,
8855                  icmp_v->hdr.icmp_code & icmp_m->hdr.icmp_code);
8856         icmp_header_data_m = rte_be_to_cpu_16(icmp_m->hdr.icmp_seq_nb);
8857         icmp_header_data_m |= rte_be_to_cpu_16(icmp_m->hdr.icmp_ident) << 16;
8858         if (icmp_header_data_m) {
8859                 icmp_header_data_v = rte_be_to_cpu_16(icmp_v->hdr.icmp_seq_nb);
8860                 icmp_header_data_v |=
8861                          rte_be_to_cpu_16(icmp_v->hdr.icmp_ident) << 16;
8862                 MLX5_SET(fte_match_set_misc3, misc3_m, icmp_header_data,
8863                          icmp_header_data_m);
8864                 MLX5_SET(fte_match_set_misc3, misc3_v, icmp_header_data,
8865                          icmp_header_data_v & icmp_header_data_m);
8866         }
8867 }
8868
8869 /**
8870  * Add GTP item to matcher and to the value.
8871  *
8872  * @param[in, out] matcher
8873  *   Flow matcher.
8874  * @param[in, out] key
8875  *   Flow matcher value.
8876  * @param[in] item
8877  *   Flow pattern to translate.
8878  * @param[in] inner
8879  *   Item is inner pattern.
8880  */
8881 static void
8882 flow_dv_translate_item_gtp(void *matcher, void *key,
8883                            const struct rte_flow_item *item, int inner)
8884 {
8885         const struct rte_flow_item_gtp *gtp_m = item->mask;
8886         const struct rte_flow_item_gtp *gtp_v = item->spec;
8887         void *headers_m;
8888         void *headers_v;
8889         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8890                                      misc_parameters_3);
8891         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8892         uint16_t dport = RTE_GTPU_UDP_PORT;
8893
8894         if (inner) {
8895                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8896                                          inner_headers);
8897                 headers_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);
8898         } else {
8899                 headers_m = MLX5_ADDR_OF(fte_match_param, matcher,
8900                                          outer_headers);
8901                 headers_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);
8902         }
8903         if (!MLX5_GET16(fte_match_set_lyr_2_4, headers_v, udp_dport)) {
8904                 MLX5_SET(fte_match_set_lyr_2_4, headers_m, udp_dport, 0xFFFF);
8905                 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport, dport);
8906         }
8907         if (!gtp_v)
8908                 return;
8909         if (!gtp_m)
8910                 gtp_m = &rte_flow_item_gtp_mask;
8911         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags,
8912                  gtp_m->v_pt_rsv_flags);
8913         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags,
8914                  gtp_v->v_pt_rsv_flags & gtp_m->v_pt_rsv_flags);
8915         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_type, gtp_m->msg_type);
8916         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_type,
8917                  gtp_v->msg_type & gtp_m->msg_type);
8918         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_teid,
8919                  rte_be_to_cpu_32(gtp_m->teid));
8920         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_teid,
8921                  rte_be_to_cpu_32(gtp_v->teid & gtp_m->teid));
8922 }
8923
8924 /**
8925  * Add GTP PSC item to matcher.
8926  *
8927  * @param[in, out] matcher
8928  *   Flow matcher.
8929  * @param[in, out] key
8930  *   Flow matcher value.
8931  * @param[in] item
8932  *   Flow pattern to translate.
8933  */
8934 static int
8935 flow_dv_translate_item_gtp_psc(void *matcher, void *key,
8936                                const struct rte_flow_item *item)
8937 {
8938         const struct rte_flow_item_gtp_psc *gtp_psc_m = item->mask;
8939         const struct rte_flow_item_gtp_psc *gtp_psc_v = item->spec;
8940         void *misc3_m = MLX5_ADDR_OF(fte_match_param, matcher,
8941                         misc_parameters_3);
8942         void *misc3_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_3);
8943         union {
8944                 uint32_t w32;
8945                 struct {
8946                         uint16_t seq_num;
8947                         uint8_t npdu_num;
8948                         uint8_t next_ext_header_type;
8949                 };
8950         } dw_2;
8951         uint8_t gtp_flags;
8952
8953         /* Always set E-flag match on one, regardless of GTP item settings. */
8954         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_m, gtpu_msg_flags);
8955         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8956         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_msg_flags, gtp_flags);
8957         gtp_flags = MLX5_GET(fte_match_set_misc3, misc3_v, gtpu_msg_flags);
8958         gtp_flags |= MLX5_GTP_EXT_HEADER_FLAG;
8959         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_msg_flags, gtp_flags);
8960         /*Set next extension header type. */
8961         dw_2.seq_num = 0;
8962         dw_2.npdu_num = 0;
8963         dw_2.next_ext_header_type = 0xff;
8964         MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_dw_2,
8965                  rte_cpu_to_be_32(dw_2.w32));
8966         dw_2.seq_num = 0;
8967         dw_2.npdu_num = 0;
8968         dw_2.next_ext_header_type = 0x85;
8969         MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_dw_2,
8970                  rte_cpu_to_be_32(dw_2.w32));
8971         if (gtp_psc_v) {
8972                 union {
8973                         uint32_t w32;
8974                         struct {
8975                                 uint8_t len;
8976                                 uint8_t type_flags;
8977                                 uint8_t qfi;
8978                                 uint8_t reserved;
8979                         };
8980                 } dw_0;
8981
8982                 /*Set extension header PDU type and Qos. */
8983                 if (!gtp_psc_m)
8984                         gtp_psc_m = &rte_flow_item_gtp_psc_mask;
8985                 dw_0.w32 = 0;
8986                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_m->pdu_type);
8987                 dw_0.qfi = gtp_psc_m->qfi;
8988                 MLX5_SET(fte_match_set_misc3, misc3_m, gtpu_first_ext_dw_0,
8989                          rte_cpu_to_be_32(dw_0.w32));
8990                 dw_0.w32 = 0;
8991                 dw_0.type_flags = MLX5_GTP_PDU_TYPE_SHIFT(gtp_psc_v->pdu_type &
8992                                                         gtp_psc_m->pdu_type);
8993                 dw_0.qfi = gtp_psc_v->qfi & gtp_psc_m->qfi;
8994                 MLX5_SET(fte_match_set_misc3, misc3_v, gtpu_first_ext_dw_0,
8995                          rte_cpu_to_be_32(dw_0.w32));
8996         }
8997         return 0;
8998 }
8999
9000 /**
9001  * Add eCPRI item to matcher and to the value.
9002  *
9003  * @param[in] dev
9004  *   The devich to configure through.
9005  * @param[in, out] matcher
9006  *   Flow matcher.
9007  * @param[in, out] key
9008  *   Flow matcher value.
9009  * @param[in] item
9010  *   Flow pattern to translate.
9011  * @param[in] samples
9012  *   Sample IDs to be used in the matching.
9013  */
9014 static void
9015 flow_dv_translate_item_ecpri(struct rte_eth_dev *dev, void *matcher,
9016                              void *key, const struct rte_flow_item *item)
9017 {
9018         struct mlx5_priv *priv = dev->data->dev_private;
9019         const struct rte_flow_item_ecpri *ecpri_m = item->mask;
9020         const struct rte_flow_item_ecpri *ecpri_v = item->spec;
9021         struct rte_ecpri_common_hdr common;
9022         void *misc4_m = MLX5_ADDR_OF(fte_match_param, matcher,
9023                                      misc_parameters_4);
9024         void *misc4_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters_4);
9025         uint32_t *samples;
9026         void *dw_m;
9027         void *dw_v;
9028
9029         if (!ecpri_v)
9030                 return;
9031         if (!ecpri_m)
9032                 ecpri_m = &rte_flow_item_ecpri_mask;
9033         /*
9034          * Maximal four DW samples are supported in a single matching now.
9035          * Two are used now for a eCPRI matching:
9036          * 1. Type: one byte, mask should be 0x00ff0000 in network order
9037          * 2. ID of a message: one or two bytes, mask 0xffff0000 or 0xff000000
9038          *    if any.
9039          */
9040         if (!ecpri_m->hdr.common.u32)
9041                 return;
9042         samples = priv->sh->fp[MLX5_FLEX_PARSER_ECPRI_0].ids;
9043         /* Need to take the whole DW as the mask to fill the entry. */
9044         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9045                             prog_sample_field_value_0);
9046         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9047                             prog_sample_field_value_0);
9048         /* Already big endian (network order) in the header. */
9049         *(uint32_t *)dw_m = ecpri_m->hdr.common.u32;
9050         *(uint32_t *)dw_v = ecpri_v->hdr.common.u32 & ecpri_m->hdr.common.u32;
9051         /* Sample#0, used for matching type, offset 0. */
9052         MLX5_SET(fte_match_set_misc4, misc4_m,
9053                  prog_sample_field_id_0, samples[0]);
9054         /* It makes no sense to set the sample ID in the mask field. */
9055         MLX5_SET(fte_match_set_misc4, misc4_v,
9056                  prog_sample_field_id_0, samples[0]);
9057         /*
9058          * Checking if message body part needs to be matched.
9059          * Some wildcard rules only matching type field should be supported.
9060          */
9061         if (ecpri_m->hdr.dummy[0]) {
9062                 common.u32 = rte_be_to_cpu_32(ecpri_v->hdr.common.u32);
9063                 switch (common.type) {
9064                 case RTE_ECPRI_MSG_TYPE_IQ_DATA:
9065                 case RTE_ECPRI_MSG_TYPE_RTC_CTRL:
9066                 case RTE_ECPRI_MSG_TYPE_DLY_MSR:
9067                         dw_m = MLX5_ADDR_OF(fte_match_set_misc4, misc4_m,
9068                                             prog_sample_field_value_1);
9069                         dw_v = MLX5_ADDR_OF(fte_match_set_misc4, misc4_v,
9070                                             prog_sample_field_value_1);
9071                         *(uint32_t *)dw_m = ecpri_m->hdr.dummy[0];
9072                         *(uint32_t *)dw_v = ecpri_v->hdr.dummy[0] &
9073                                             ecpri_m->hdr.dummy[0];
9074                         /* Sample#1, to match message body, offset 4. */
9075                         MLX5_SET(fte_match_set_misc4, misc4_m,
9076                                  prog_sample_field_id_1, samples[1]);
9077                         MLX5_SET(fte_match_set_misc4, misc4_v,
9078                                  prog_sample_field_id_1, samples[1]);
9079                         break;
9080                 default:
9081                         /* Others, do not match any sample ID. */
9082                         break;
9083                 }
9084         }
9085 }
9086
9087 static uint32_t matcher_zero[MLX5_ST_SZ_DW(fte_match_param)] = { 0 };
9088
9089 #define HEADER_IS_ZERO(match_criteria, headers)                              \
9090         !(memcmp(MLX5_ADDR_OF(fte_match_param, match_criteria, headers),     \
9091                  matcher_zero, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
9092
9093 /**
9094  * Calculate flow matcher enable bitmap.
9095  *
9096  * @param match_criteria
9097  *   Pointer to flow matcher criteria.
9098  *
9099  * @return
9100  *   Bitmap of enabled fields.
9101  */
9102 static uint8_t
9103 flow_dv_matcher_enable(uint32_t *match_criteria)
9104 {
9105         uint8_t match_criteria_enable;
9106
9107         match_criteria_enable =
9108                 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
9109                 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT;
9110         match_criteria_enable |=
9111                 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
9112                 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT;
9113         match_criteria_enable |=
9114                 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
9115                 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT;
9116         match_criteria_enable |=
9117                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
9118                 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
9119         match_criteria_enable |=
9120                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_3)) <<
9121                 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT;
9122         match_criteria_enable |=
9123                 (!HEADER_IS_ZERO(match_criteria, misc_parameters_4)) <<
9124                 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT;
9125         return match_criteria_enable;
9126 }
9127
9128 struct mlx5_hlist_entry *
9129 flow_dv_tbl_create_cb(struct mlx5_hlist *list, uint64_t key64, void *cb_ctx)
9130 {
9131         struct mlx5_dev_ctx_shared *sh = list->ctx;
9132         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9133         struct rte_eth_dev *dev = ctx->dev;
9134         struct mlx5_flow_tbl_data_entry *tbl_data;
9135         struct mlx5_flow_tbl_tunnel_prm *tt_prm = ctx->data;
9136         struct rte_flow_error *error = ctx->error;
9137         union mlx5_flow_tbl_key key = { .v64 = key64 };
9138         struct mlx5_flow_tbl_resource *tbl;
9139         void *domain;
9140         uint32_t idx = 0;
9141         int ret;
9142
9143         tbl_data = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_JUMP], &idx);
9144         if (!tbl_data) {
9145                 rte_flow_error_set(error, ENOMEM,
9146                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9147                                    NULL,
9148                                    "cannot allocate flow table data entry");
9149                 return NULL;
9150         }
9151         tbl_data->idx = idx;
9152         tbl_data->tunnel = tt_prm->tunnel;
9153         tbl_data->group_id = tt_prm->group_id;
9154         tbl_data->external = !!tt_prm->external;
9155         tbl_data->tunnel_offload = is_tunnel_offload_active(dev);
9156         tbl_data->is_egress = !!key.direction;
9157         tbl_data->is_transfer = !!key.domain;
9158         tbl_data->dummy = !!key.dummy;
9159         tbl_data->table_id = key.table_id;
9160         tbl = &tbl_data->tbl;
9161         if (key.dummy)
9162                 return &tbl_data->entry;
9163         if (key.domain)
9164                 domain = sh->fdb_domain;
9165         else if (key.direction)
9166                 domain = sh->tx_domain;
9167         else
9168                 domain = sh->rx_domain;
9169         ret = mlx5_flow_os_create_flow_tbl(domain, key.table_id, &tbl->obj);
9170         if (ret) {
9171                 rte_flow_error_set(error, ENOMEM,
9172                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9173                                    NULL, "cannot create flow table object");
9174                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9175                 return NULL;
9176         }
9177         if (key.table_id) {
9178                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
9179                                         (tbl->obj, &tbl_data->jump.action);
9180                 if (ret) {
9181                         rte_flow_error_set(error, ENOMEM,
9182                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9183                                            NULL,
9184                                            "cannot create flow jump action");
9185                         mlx5_flow_os_destroy_flow_tbl(tbl->obj);
9186                         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], idx);
9187                         return NULL;
9188                 }
9189         }
9190         MKSTR(matcher_name, "%s_%s_%u_matcher_cache",
9191               key.domain ? "FDB" : "NIC", key.direction ? "egress" : "ingress",
9192               key.table_id);
9193         mlx5_cache_list_init(&tbl_data->matchers, matcher_name, 0, sh,
9194                              flow_dv_matcher_create_cb,
9195                              flow_dv_matcher_match_cb,
9196                              flow_dv_matcher_remove_cb);
9197         return &tbl_data->entry;
9198 }
9199
9200 int
9201 flow_dv_tbl_match_cb(struct mlx5_hlist *list __rte_unused,
9202                      struct mlx5_hlist_entry *entry, uint64_t key64,
9203                      void *cb_ctx __rte_unused)
9204 {
9205         struct mlx5_flow_tbl_data_entry *tbl_data =
9206                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9207         union mlx5_flow_tbl_key key = { .v64 = key64 };
9208
9209         return tbl_data->table_id != key.table_id ||
9210                tbl_data->dummy != key.dummy ||
9211                tbl_data->is_transfer != key.domain ||
9212                tbl_data->is_egress != key.direction;
9213 }
9214
9215 /**
9216  * Get a flow table.
9217  *
9218  * @param[in, out] dev
9219  *   Pointer to rte_eth_dev structure.
9220  * @param[in] table_id
9221  *   Table id to use.
9222  * @param[in] egress
9223  *   Direction of the table.
9224  * @param[in] transfer
9225  *   E-Switch or NIC flow.
9226  * @param[in] dummy
9227  *   Dummy entry for dv API.
9228  * @param[out] error
9229  *   pointer to error structure.
9230  *
9231  * @return
9232  *   Returns tables resource based on the index, NULL in case of failed.
9233  */
9234 struct mlx5_flow_tbl_resource *
9235 flow_dv_tbl_resource_get(struct rte_eth_dev *dev,
9236                          uint32_t table_id, uint8_t egress,
9237                          uint8_t transfer,
9238                          bool external,
9239                          const struct mlx5_flow_tunnel *tunnel,
9240                          uint32_t group_id, uint8_t dummy,
9241                          struct rte_flow_error *error)
9242 {
9243         struct mlx5_priv *priv = dev->data->dev_private;
9244         union mlx5_flow_tbl_key table_key = {
9245                 {
9246                         .table_id = table_id,
9247                         .dummy = dummy,
9248                         .domain = !!transfer,
9249                         .direction = !!egress,
9250                 }
9251         };
9252         struct mlx5_flow_tbl_tunnel_prm tt_prm = {
9253                 .tunnel = tunnel,
9254                 .group_id = group_id,
9255                 .external = external,
9256         };
9257         struct mlx5_flow_cb_ctx ctx = {
9258                 .dev = dev,
9259                 .error = error,
9260                 .data = &tt_prm,
9261         };
9262         struct mlx5_hlist_entry *entry;
9263         struct mlx5_flow_tbl_data_entry *tbl_data;
9264
9265         entry = mlx5_hlist_register(priv->sh->flow_tbls, table_key.v64, &ctx);
9266         if (!entry) {
9267                 rte_flow_error_set(error, ENOMEM,
9268                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9269                                    "cannot get table");
9270                 return NULL;
9271         }
9272         DRV_LOG(DEBUG, "Table_id %u tunnel %u group %u registered.",
9273                 table_id, tunnel ? tunnel->tunnel_id : 0, group_id);
9274         tbl_data = container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9275         return &tbl_data->tbl;
9276 }
9277
9278 void
9279 flow_dv_tbl_remove_cb(struct mlx5_hlist *list,
9280                       struct mlx5_hlist_entry *entry)
9281 {
9282         struct mlx5_dev_ctx_shared *sh = list->ctx;
9283         struct mlx5_flow_tbl_data_entry *tbl_data =
9284                 container_of(entry, struct mlx5_flow_tbl_data_entry, entry);
9285
9286         MLX5_ASSERT(entry && sh);
9287         if (tbl_data->jump.action)
9288                 mlx5_flow_os_destroy_flow_action(tbl_data->jump.action);
9289         if (tbl_data->tbl.obj)
9290                 mlx5_flow_os_destroy_flow_tbl(tbl_data->tbl.obj);
9291         if (tbl_data->tunnel_offload && tbl_data->external) {
9292                 struct mlx5_hlist_entry *he;
9293                 struct mlx5_hlist *tunnel_grp_hash;
9294                 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub;
9295                 union tunnel_tbl_key tunnel_key = {
9296                         .tunnel_id = tbl_data->tunnel ?
9297                                         tbl_data->tunnel->tunnel_id : 0,
9298                         .group = tbl_data->group_id
9299                 };
9300                 uint32_t table_id = tbl_data->table_id;
9301
9302                 tunnel_grp_hash = tbl_data->tunnel ?
9303                                         tbl_data->tunnel->groups :
9304                                         thub->groups;
9305                 he = mlx5_hlist_lookup(tunnel_grp_hash, tunnel_key.val, NULL);
9306                 if (he)
9307                         mlx5_hlist_unregister(tunnel_grp_hash, he);
9308                 DRV_LOG(DEBUG,
9309                         "Table_id %u tunnel %u group %u released.",
9310                         table_id,
9311                         tbl_data->tunnel ?
9312                         tbl_data->tunnel->tunnel_id : 0,
9313                         tbl_data->group_id);
9314         }
9315         mlx5_cache_list_destroy(&tbl_data->matchers);
9316         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_JUMP], tbl_data->idx);
9317 }
9318
9319 /**
9320  * Release a flow table.
9321  *
9322  * @param[in] sh
9323  *   Pointer to device shared structure.
9324  * @param[in] tbl
9325  *   Table resource to be released.
9326  *
9327  * @return
9328  *   Returns 0 if table was released, else return 1;
9329  */
9330 static int
9331 flow_dv_tbl_resource_release(struct mlx5_dev_ctx_shared *sh,
9332                              struct mlx5_flow_tbl_resource *tbl)
9333 {
9334         struct mlx5_flow_tbl_data_entry *tbl_data =
9335                 container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9336
9337         if (!tbl)
9338                 return 0;
9339         return mlx5_hlist_unregister(sh->flow_tbls, &tbl_data->entry);
9340 }
9341
9342 int
9343 flow_dv_matcher_match_cb(struct mlx5_cache_list *list __rte_unused,
9344                          struct mlx5_cache_entry *entry, void *cb_ctx)
9345 {
9346         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9347         struct mlx5_flow_dv_matcher *ref = ctx->data;
9348         struct mlx5_flow_dv_matcher *cur = container_of(entry, typeof(*cur),
9349                                                         entry);
9350
9351         return cur->crc != ref->crc ||
9352                cur->priority != ref->priority ||
9353                memcmp((const void *)cur->mask.buf,
9354                       (const void *)ref->mask.buf, ref->mask.size);
9355 }
9356
9357 struct mlx5_cache_entry *
9358 flow_dv_matcher_create_cb(struct mlx5_cache_list *list,
9359                           struct mlx5_cache_entry *entry __rte_unused,
9360                           void *cb_ctx)
9361 {
9362         struct mlx5_dev_ctx_shared *sh = list->ctx;
9363         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9364         struct mlx5_flow_dv_matcher *ref = ctx->data;
9365         struct mlx5_flow_dv_matcher *cache;
9366         struct mlx5dv_flow_matcher_attr dv_attr = {
9367                 .type = IBV_FLOW_ATTR_NORMAL,
9368                 .match_mask = (void *)&ref->mask,
9369         };
9370         struct mlx5_flow_tbl_data_entry *tbl = container_of(ref->tbl,
9371                                                             typeof(*tbl), tbl);
9372         int ret;
9373
9374         cache = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*cache), 0, SOCKET_ID_ANY);
9375         if (!cache) {
9376                 rte_flow_error_set(ctx->error, ENOMEM,
9377                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9378                                    "cannot create matcher");
9379                 return NULL;
9380         }
9381         *cache = *ref;
9382         dv_attr.match_criteria_enable =
9383                 flow_dv_matcher_enable(cache->mask.buf);
9384         dv_attr.priority = ref->priority;
9385         if (tbl->is_egress)
9386                 dv_attr.flags |= IBV_FLOW_ATTR_FLAGS_EGRESS;
9387         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->tbl.obj,
9388                                                &cache->matcher_object);
9389         if (ret) {
9390                 mlx5_free(cache);
9391                 rte_flow_error_set(ctx->error, ENOMEM,
9392                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9393                                    "cannot create matcher");
9394                 return NULL;
9395         }
9396         return &cache->entry;
9397 }
9398
9399 /**
9400  * Register the flow matcher.
9401  *
9402  * @param[in, out] dev
9403  *   Pointer to rte_eth_dev structure.
9404  * @param[in, out] matcher
9405  *   Pointer to flow matcher.
9406  * @param[in, out] key
9407  *   Pointer to flow table key.
9408  * @parm[in, out] dev_flow
9409  *   Pointer to the dev_flow.
9410  * @param[out] error
9411  *   pointer to error structure.
9412  *
9413  * @return
9414  *   0 on success otherwise -errno and errno is set.
9415  */
9416 static int
9417 flow_dv_matcher_register(struct rte_eth_dev *dev,
9418                          struct mlx5_flow_dv_matcher *ref,
9419                          union mlx5_flow_tbl_key *key,
9420                          struct mlx5_flow *dev_flow,
9421                          const struct mlx5_flow_tunnel *tunnel,
9422                          uint32_t group_id,
9423                          struct rte_flow_error *error)
9424 {
9425         struct mlx5_cache_entry *entry;
9426         struct mlx5_flow_dv_matcher *cache;
9427         struct mlx5_flow_tbl_resource *tbl;
9428         struct mlx5_flow_tbl_data_entry *tbl_data;
9429         struct mlx5_flow_cb_ctx ctx = {
9430                 .error = error,
9431                 .data = ref,
9432         };
9433
9434         /**
9435          * tunnel offload API requires this registration for cases when
9436          * tunnel match rule was inserted before tunnel set rule.
9437          */
9438         tbl = flow_dv_tbl_resource_get(dev, key->table_id,
9439                                        key->direction, key->domain,
9440                                        dev_flow->external, tunnel,
9441                                        group_id, 0, error);
9442         if (!tbl)
9443                 return -rte_errno;      /* No need to refill the error info */
9444         tbl_data = container_of(tbl, struct mlx5_flow_tbl_data_entry, tbl);
9445         ref->tbl = tbl;
9446         entry = mlx5_cache_register(&tbl_data->matchers, &ctx);
9447         if (!entry) {
9448                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
9449                 return rte_flow_error_set(error, ENOMEM,
9450                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9451                                           "cannot allocate ref memory");
9452         }
9453         cache = container_of(entry, typeof(*cache), entry);
9454         dev_flow->handle->dvh.matcher = cache;
9455         return 0;
9456 }
9457
9458 struct mlx5_hlist_entry *
9459 flow_dv_tag_create_cb(struct mlx5_hlist *list, uint64_t key, void *ctx)
9460 {
9461         struct mlx5_dev_ctx_shared *sh = list->ctx;
9462         struct rte_flow_error *error = ctx;
9463         struct mlx5_flow_dv_tag_resource *entry;
9464         uint32_t idx = 0;
9465         int ret;
9466
9467         entry = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_TAG], &idx);
9468         if (!entry) {
9469                 rte_flow_error_set(error, ENOMEM,
9470                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
9471                                    "cannot allocate resource memory");
9472                 return NULL;
9473         }
9474         entry->idx = idx;
9475         entry->tag_id = key;
9476         ret = mlx5_flow_os_create_flow_action_tag(key,
9477                                                   &entry->action);
9478         if (ret) {
9479                 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], idx);
9480                 rte_flow_error_set(error, ENOMEM,
9481                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9482                                    NULL, "cannot create action");
9483                 return NULL;
9484         }
9485         return &entry->entry;
9486 }
9487
9488 int
9489 flow_dv_tag_match_cb(struct mlx5_hlist *list __rte_unused,
9490                      struct mlx5_hlist_entry *entry, uint64_t key,
9491                      void *cb_ctx __rte_unused)
9492 {
9493         struct mlx5_flow_dv_tag_resource *tag =
9494                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9495
9496         return key != tag->tag_id;
9497 }
9498
9499 /**
9500  * Find existing tag resource or create and register a new one.
9501  *
9502  * @param dev[in, out]
9503  *   Pointer to rte_eth_dev structure.
9504  * @param[in, out] tag_be24
9505  *   Tag value in big endian then R-shift 8.
9506  * @parm[in, out] dev_flow
9507  *   Pointer to the dev_flow.
9508  * @param[out] error
9509  *   pointer to error structure.
9510  *
9511  * @return
9512  *   0 on success otherwise -errno and errno is set.
9513  */
9514 static int
9515 flow_dv_tag_resource_register
9516                         (struct rte_eth_dev *dev,
9517                          uint32_t tag_be24,
9518                          struct mlx5_flow *dev_flow,
9519                          struct rte_flow_error *error)
9520 {
9521         struct mlx5_priv *priv = dev->data->dev_private;
9522         struct mlx5_flow_dv_tag_resource *cache_resource;
9523         struct mlx5_hlist_entry *entry;
9524
9525         entry = mlx5_hlist_register(priv->sh->tag_table, tag_be24, error);
9526         if (entry) {
9527                 cache_resource = container_of
9528                         (entry, struct mlx5_flow_dv_tag_resource, entry);
9529                 dev_flow->handle->dvh.rix_tag = cache_resource->idx;
9530                 dev_flow->dv.tag_resource = cache_resource;
9531                 return 0;
9532         }
9533         return -rte_errno;
9534 }
9535
9536 void
9537 flow_dv_tag_remove_cb(struct mlx5_hlist *list,
9538                       struct mlx5_hlist_entry *entry)
9539 {
9540         struct mlx5_dev_ctx_shared *sh = list->ctx;
9541         struct mlx5_flow_dv_tag_resource *tag =
9542                 container_of(entry, struct mlx5_flow_dv_tag_resource, entry);
9543
9544         MLX5_ASSERT(tag && sh && tag->action);
9545         claim_zero(mlx5_flow_os_destroy_flow_action(tag->action));
9546         DRV_LOG(DEBUG, "Tag %p: removed.", (void *)tag);
9547         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TAG], tag->idx);
9548 }
9549
9550 /**
9551  * Release the tag.
9552  *
9553  * @param dev
9554  *   Pointer to Ethernet device.
9555  * @param tag_idx
9556  *   Tag index.
9557  *
9558  * @return
9559  *   1 while a reference on it exists, 0 when freed.
9560  */
9561 static int
9562 flow_dv_tag_release(struct rte_eth_dev *dev,
9563                     uint32_t tag_idx)
9564 {
9565         struct mlx5_priv *priv = dev->data->dev_private;
9566         struct mlx5_flow_dv_tag_resource *tag;
9567
9568         tag = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_TAG], tag_idx);
9569         if (!tag)
9570                 return 0;
9571         DRV_LOG(DEBUG, "port %u tag %p: refcnt %d--",
9572                 dev->data->port_id, (void *)tag, tag->entry.ref_cnt);
9573         return mlx5_hlist_unregister(priv->sh->tag_table, &tag->entry);
9574 }
9575
9576 /**
9577  * Translate port ID action to vport.
9578  *
9579  * @param[in] dev
9580  *   Pointer to rte_eth_dev structure.
9581  * @param[in] action
9582  *   Pointer to the port ID action.
9583  * @param[out] dst_port_id
9584  *   The target port ID.
9585  * @param[out] error
9586  *   Pointer to the error structure.
9587  *
9588  * @return
9589  *   0 on success, a negative errno value otherwise and rte_errno is set.
9590  */
9591 static int
9592 flow_dv_translate_action_port_id(struct rte_eth_dev *dev,
9593                                  const struct rte_flow_action *action,
9594                                  uint32_t *dst_port_id,
9595                                  struct rte_flow_error *error)
9596 {
9597         uint32_t port;
9598         struct mlx5_priv *priv;
9599         const struct rte_flow_action_port_id *conf =
9600                         (const struct rte_flow_action_port_id *)action->conf;
9601
9602         port = conf->original ? dev->data->port_id : conf->id;
9603         priv = mlx5_port_to_eswitch_info(port, false);
9604         if (!priv)
9605                 return rte_flow_error_set(error, -rte_errno,
9606                                           RTE_FLOW_ERROR_TYPE_ACTION,
9607                                           NULL,
9608                                           "No eswitch info was found for port");
9609 #ifdef HAVE_MLX5DV_DR_DEVX_PORT
9610         /*
9611          * This parameter is transferred to
9612          * mlx5dv_dr_action_create_dest_ib_port().
9613          */
9614         *dst_port_id = priv->dev_port;
9615 #else
9616         /*
9617          * Legacy mode, no LAG configurations is supported.
9618          * This parameter is transferred to
9619          * mlx5dv_dr_action_create_dest_vport().
9620          */
9621         *dst_port_id = priv->vport_id;
9622 #endif
9623         return 0;
9624 }
9625
9626 /**
9627  * Create a counter with aging configuration.
9628  *
9629  * @param[in] dev
9630  *   Pointer to rte_eth_dev structure.
9631  * @param[out] count
9632  *   Pointer to the counter action configuration.
9633  * @param[in] age
9634  *   Pointer to the aging action configuration.
9635  *
9636  * @return
9637  *   Index to flow counter on success, 0 otherwise.
9638  */
9639 static uint32_t
9640 flow_dv_translate_create_counter(struct rte_eth_dev *dev,
9641                                 struct mlx5_flow *dev_flow,
9642                                 const struct rte_flow_action_count *count,
9643                                 const struct rte_flow_action_age *age)
9644 {
9645         uint32_t counter;
9646         struct mlx5_age_param *age_param;
9647
9648         if (count && count->shared)
9649                 counter = flow_dv_counter_get_shared(dev, count->id);
9650         else
9651                 counter = flow_dv_counter_alloc(dev, !!age);
9652         if (!counter || age == NULL)
9653                 return counter;
9654         age_param  = flow_dv_counter_idx_get_age(dev, counter);
9655         age_param->context = age->context ? age->context :
9656                 (void *)(uintptr_t)(dev_flow->flow_idx);
9657         age_param->timeout = age->timeout;
9658         age_param->port_id = dev->data->port_id;
9659         __atomic_store_n(&age_param->sec_since_last_hit, 0, __ATOMIC_RELAXED);
9660         __atomic_store_n(&age_param->state, AGE_CANDIDATE, __ATOMIC_RELAXED);
9661         return counter;
9662 }
9663
9664 /**
9665  * Add Tx queue matcher
9666  *
9667  * @param[in] dev
9668  *   Pointer to the dev struct.
9669  * @param[in, out] matcher
9670  *   Flow matcher.
9671  * @param[in, out] key
9672  *   Flow matcher value.
9673  * @param[in] item
9674  *   Flow pattern to translate.
9675  * @param[in] inner
9676  *   Item is inner pattern.
9677  */
9678 static void
9679 flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,
9680                                 void *matcher, void *key,
9681                                 const struct rte_flow_item *item)
9682 {
9683         const struct mlx5_rte_flow_item_tx_queue *queue_m;
9684         const struct mlx5_rte_flow_item_tx_queue *queue_v;
9685         void *misc_m =
9686                 MLX5_ADDR_OF(fte_match_param, matcher, misc_parameters);
9687         void *misc_v =
9688                 MLX5_ADDR_OF(fte_match_param, key, misc_parameters);
9689         struct mlx5_txq_ctrl *txq;
9690         uint32_t queue;
9691
9692
9693         queue_m = (const void *)item->mask;
9694         if (!queue_m)
9695                 return;
9696         queue_v = (const void *)item->spec;
9697         if (!queue_v)
9698                 return;
9699         txq = mlx5_txq_get(dev, queue_v->queue);
9700         if (!txq)
9701                 return;
9702         queue = txq->obj->sq->id;
9703         MLX5_SET(fte_match_set_misc, misc_m, source_sqn, queue_m->queue);
9704         MLX5_SET(fte_match_set_misc, misc_v, source_sqn,
9705                  queue & queue_m->queue);
9706         mlx5_txq_release(dev, queue_v->queue);
9707 }
9708
9709 /**
9710  * Set the hash fields according to the @p flow information.
9711  *
9712  * @param[in] dev_flow
9713  *   Pointer to the mlx5_flow.
9714  * @param[in] rss_desc
9715  *   Pointer to the mlx5_flow_rss_desc.
9716  */
9717 static void
9718 flow_dv_hashfields_set(struct mlx5_flow *dev_flow,
9719                        struct mlx5_flow_rss_desc *rss_desc)
9720 {
9721         uint64_t items = dev_flow->handle->layers;
9722         int rss_inner = 0;
9723         uint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);
9724
9725         dev_flow->hash_fields = 0;
9726 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
9727         if (rss_desc->level >= 2) {
9728                 dev_flow->hash_fields |= IBV_RX_HASH_INNER;
9729                 rss_inner = 1;
9730         }
9731 #endif
9732         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||
9733             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {
9734                 if (rss_types & MLX5_IPV4_LAYER_TYPES) {
9735                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9736                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV4;
9737                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9738                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV4;
9739                         else
9740                                 dev_flow->hash_fields |= MLX5_IPV4_IBV_RX_HASH;
9741                 }
9742         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||
9743                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {
9744                 if (rss_types & MLX5_IPV6_LAYER_TYPES) {
9745                         if (rss_types & ETH_RSS_L3_SRC_ONLY)
9746                                 dev_flow->hash_fields |= IBV_RX_HASH_SRC_IPV6;
9747                         else if (rss_types & ETH_RSS_L3_DST_ONLY)
9748                                 dev_flow->hash_fields |= IBV_RX_HASH_DST_IPV6;
9749                         else
9750                                 dev_flow->hash_fields |= MLX5_IPV6_IBV_RX_HASH;
9751                 }
9752         }
9753         if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||
9754             (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {
9755                 if (rss_types & ETH_RSS_UDP) {
9756                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9757                                 dev_flow->hash_fields |=
9758                                                 IBV_RX_HASH_SRC_PORT_UDP;
9759                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9760                                 dev_flow->hash_fields |=
9761                                                 IBV_RX_HASH_DST_PORT_UDP;
9762                         else
9763                                 dev_flow->hash_fields |= MLX5_UDP_IBV_RX_HASH;
9764                 }
9765         } else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||
9766                    (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {
9767                 if (rss_types & ETH_RSS_TCP) {
9768                         if (rss_types & ETH_RSS_L4_SRC_ONLY)
9769                                 dev_flow->hash_fields |=
9770                                                 IBV_RX_HASH_SRC_PORT_TCP;
9771                         else if (rss_types & ETH_RSS_L4_DST_ONLY)
9772                                 dev_flow->hash_fields |=
9773                                                 IBV_RX_HASH_DST_PORT_TCP;
9774                         else
9775                                 dev_flow->hash_fields |= MLX5_TCP_IBV_RX_HASH;
9776                 }
9777         }
9778 }
9779
9780 /**
9781  * Prepare an Rx Hash queue.
9782  *
9783  * @param dev
9784  *   Pointer to Ethernet device.
9785  * @param[in] dev_flow
9786  *   Pointer to the mlx5_flow.
9787  * @param[in] rss_desc
9788  *   Pointer to the mlx5_flow_rss_desc.
9789  * @param[out] hrxq_idx
9790  *   Hash Rx queue index.
9791  *
9792  * @return
9793  *   The Verbs/DevX object initialised, NULL otherwise and rte_errno is set.
9794  */
9795 static struct mlx5_hrxq *
9796 flow_dv_hrxq_prepare(struct rte_eth_dev *dev,
9797                      struct mlx5_flow *dev_flow,
9798                      struct mlx5_flow_rss_desc *rss_desc,
9799                      uint32_t *hrxq_idx)
9800 {
9801         struct mlx5_priv *priv = dev->data->dev_private;
9802         struct mlx5_flow_handle *dh = dev_flow->handle;
9803         struct mlx5_hrxq *hrxq;
9804
9805         MLX5_ASSERT(rss_desc->queue_num);
9806         rss_desc->key_len = MLX5_RSS_HASH_KEY_LEN;
9807         rss_desc->hash_fields = dev_flow->hash_fields;
9808         rss_desc->tunnel = !!(dh->layers & MLX5_FLOW_LAYER_TUNNEL);
9809         rss_desc->shared_rss = 0;
9810         *hrxq_idx = mlx5_hrxq_get(dev, rss_desc);
9811         if (!*hrxq_idx)
9812                 return NULL;
9813         hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ],
9814                               *hrxq_idx);
9815         return hrxq;
9816 }
9817
9818 /**
9819  * Release sample sub action resource.
9820  *
9821  * @param[in, out] dev
9822  *   Pointer to rte_eth_dev structure.
9823  * @param[in] act_res
9824  *   Pointer to sample sub action resource.
9825  */
9826 static void
9827 flow_dv_sample_sub_actions_release(struct rte_eth_dev *dev,
9828                                    struct mlx5_flow_sub_actions_idx *act_res)
9829 {
9830         if (act_res->rix_hrxq) {
9831                 mlx5_hrxq_release(dev, act_res->rix_hrxq);
9832                 act_res->rix_hrxq = 0;
9833         }
9834         if (act_res->rix_encap_decap) {
9835                 flow_dv_encap_decap_resource_release(dev,
9836                                                      act_res->rix_encap_decap);
9837                 act_res->rix_encap_decap = 0;
9838         }
9839         if (act_res->rix_port_id_action) {
9840                 flow_dv_port_id_action_resource_release(dev,
9841                                                 act_res->rix_port_id_action);
9842                 act_res->rix_port_id_action = 0;
9843         }
9844         if (act_res->rix_tag) {
9845                 flow_dv_tag_release(dev, act_res->rix_tag);
9846                 act_res->rix_tag = 0;
9847         }
9848         if (act_res->rix_jump) {
9849                 flow_dv_jump_tbl_resource_release(dev, act_res->rix_jump);
9850                 act_res->rix_jump = 0;
9851         }
9852 }
9853
9854 int
9855 flow_dv_sample_match_cb(struct mlx5_cache_list *list __rte_unused,
9856                         struct mlx5_cache_entry *entry, void *cb_ctx)
9857 {
9858         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9859         struct rte_eth_dev *dev = ctx->dev;
9860         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9861         struct mlx5_flow_dv_sample_resource *cache_resource =
9862                         container_of(entry, typeof(*cache_resource), entry);
9863
9864         if (resource->ratio == cache_resource->ratio &&
9865             resource->ft_type == cache_resource->ft_type &&
9866             resource->ft_id == cache_resource->ft_id &&
9867             resource->set_action == cache_resource->set_action &&
9868             !memcmp((void *)&resource->sample_act,
9869                     (void *)&cache_resource->sample_act,
9870                     sizeof(struct mlx5_flow_sub_actions_list))) {
9871                 /*
9872                  * Existing sample action should release the prepared
9873                  * sub-actions reference counter.
9874                  */
9875                 flow_dv_sample_sub_actions_release(dev,
9876                                                 &resource->sample_idx);
9877                 return 0;
9878         }
9879         return 1;
9880 }
9881
9882 struct mlx5_cache_entry *
9883 flow_dv_sample_create_cb(struct mlx5_cache_list *list __rte_unused,
9884                          struct mlx5_cache_entry *entry __rte_unused,
9885                          void *cb_ctx)
9886 {
9887         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
9888         struct rte_eth_dev *dev = ctx->dev;
9889         struct mlx5_flow_dv_sample_resource *resource = ctx->data;
9890         void **sample_dv_actions = resource->sub_actions;
9891         struct mlx5_flow_dv_sample_resource *cache_resource;
9892         struct mlx5dv_dr_flow_sampler_attr sampler_attr;
9893         struct mlx5_priv *priv = dev->data->dev_private;
9894         struct mlx5_dev_ctx_shared *sh = priv->sh;
9895         struct mlx5_flow_tbl_resource *tbl;
9896         uint32_t idx = 0;
9897         const uint32_t next_ft_step = 1;
9898         uint32_t next_ft_id = resource->ft_id + next_ft_step;
9899         uint8_t is_egress = 0;
9900         uint8_t is_transfer = 0;
9901         struct rte_flow_error *error = ctx->error;
9902
9903         /* Register new sample resource. */
9904         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_SAMPLE], &idx);
9905         if (!cache_resource) {
9906                 rte_flow_error_set(error, ENOMEM,
9907                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9908                                           NULL,
9909                                           "cannot allocate resource memory");
9910                 return NULL;
9911         }
9912         *cache_resource = *resource;
9913         /* Create normal path table level */
9914         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
9915                 is_transfer = 1;
9916         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_TX)
9917                 is_egress = 1;
9918         tbl = flow_dv_tbl_resource_get(dev, next_ft_id,
9919                                         is_egress, is_transfer,
9920                                         true, NULL, 0, 0, error);
9921         if (!tbl) {
9922                 rte_flow_error_set(error, ENOMEM,
9923                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9924                                           NULL,
9925                                           "fail to create normal path table "
9926                                           "for sample");
9927                 goto error;
9928         }
9929         cache_resource->normal_path_tbl = tbl;
9930         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB) {
9931                 if (!sh->default_miss_action) {
9932                         rte_flow_error_set(error, ENOMEM,
9933                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9934                                                 NULL,
9935                                                 "default miss action was not "
9936                                                 "created");
9937                         goto error;
9938                 }
9939                 sample_dv_actions[resource->sample_act.actions_num++] =
9940                                                 sh->default_miss_action;
9941         }
9942         /* Create a DR sample action */
9943         sampler_attr.sample_ratio = cache_resource->ratio;
9944         sampler_attr.default_next_table = tbl->obj;
9945         sampler_attr.num_sample_actions = resource->sample_act.actions_num;
9946         sampler_attr.sample_actions = (struct mlx5dv_dr_action **)
9947                                                         &sample_dv_actions[0];
9948         sampler_attr.action = cache_resource->set_action;
9949         if (mlx5_os_flow_dr_create_flow_action_sampler
9950                         (&sampler_attr, &cache_resource->verbs_action)) {
9951                 rte_flow_error_set(error, ENOMEM,
9952                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
9953                                         NULL, "cannot create sample action");
9954                 goto error;
9955         }
9956         cache_resource->idx = idx;
9957         cache_resource->dev = dev;
9958         return &cache_resource->entry;
9959 error:
9960         if (cache_resource->ft_type != MLX5DV_FLOW_TABLE_TYPE_FDB)
9961                 flow_dv_sample_sub_actions_release(dev,
9962                                                    &cache_resource->sample_idx);
9963         if (cache_resource->normal_path_tbl)
9964                 flow_dv_tbl_resource_release(MLX5_SH(dev),
9965                                 cache_resource->normal_path_tbl);
9966         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_SAMPLE], idx);
9967         return NULL;
9968
9969 }
9970
9971 /**
9972  * Find existing sample resource or create and register a new one.
9973  *
9974  * @param[in, out] dev
9975  *   Pointer to rte_eth_dev structure.
9976  * @param[in] resource
9977  *   Pointer to sample resource.
9978  * @parm[in, out] dev_flow
9979  *   Pointer to the dev_flow.
9980  * @param[out] error
9981  *   pointer to error structure.
9982  *
9983  * @return
9984  *   0 on success otherwise -errno and errno is set.
9985  */
9986 static int
9987 flow_dv_sample_resource_register(struct rte_eth_dev *dev,
9988                          struct mlx5_flow_dv_sample_resource *resource,
9989                          struct mlx5_flow *dev_flow,
9990                          struct rte_flow_error *error)
9991 {
9992         struct mlx5_flow_dv_sample_resource *cache_resource;
9993         struct mlx5_cache_entry *entry;
9994         struct mlx5_priv *priv = dev->data->dev_private;
9995         struct mlx5_flow_cb_ctx ctx = {
9996                 .dev = dev,
9997                 .error = error,
9998                 .data = resource,
9999         };
10000
10001         entry = mlx5_cache_register(&priv->sh->sample_action_list, &ctx);
10002         if (!entry)
10003                 return -rte_errno;
10004         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10005         dev_flow->handle->dvh.rix_sample = cache_resource->idx;
10006         dev_flow->dv.sample_res = cache_resource;
10007         return 0;
10008 }
10009
10010 int
10011 flow_dv_dest_array_match_cb(struct mlx5_cache_list *list __rte_unused,
10012                             struct mlx5_cache_entry *entry, void *cb_ctx)
10013 {
10014         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10015         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10016         struct rte_eth_dev *dev = ctx->dev;
10017         struct mlx5_flow_dv_dest_array_resource *cache_resource =
10018                         container_of(entry, typeof(*cache_resource), entry);
10019         uint32_t idx = 0;
10020
10021         if (resource->num_of_dest == cache_resource->num_of_dest &&
10022             resource->ft_type == cache_resource->ft_type &&
10023             !memcmp((void *)cache_resource->sample_act,
10024                     (void *)resource->sample_act,
10025                    (resource->num_of_dest *
10026                    sizeof(struct mlx5_flow_sub_actions_list)))) {
10027                 /*
10028                  * Existing sample action should release the prepared
10029                  * sub-actions reference counter.
10030                  */
10031                 for (idx = 0; idx < resource->num_of_dest; idx++)
10032                         flow_dv_sample_sub_actions_release(dev,
10033                                         &resource->sample_idx[idx]);
10034                 return 0;
10035         }
10036         return 1;
10037 }
10038
10039 struct mlx5_cache_entry *
10040 flow_dv_dest_array_create_cb(struct mlx5_cache_list *list __rte_unused,
10041                          struct mlx5_cache_entry *entry __rte_unused,
10042                          void *cb_ctx)
10043 {
10044         struct mlx5_flow_cb_ctx *ctx = cb_ctx;
10045         struct rte_eth_dev *dev = ctx->dev;
10046         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10047         struct mlx5_flow_dv_dest_array_resource *resource = ctx->data;
10048         struct mlx5dv_dr_action_dest_attr *dest_attr[MLX5_MAX_DEST_NUM] = { 0 };
10049         struct mlx5dv_dr_action_dest_reformat dest_reformat[MLX5_MAX_DEST_NUM];
10050         struct mlx5_priv *priv = dev->data->dev_private;
10051         struct mlx5_dev_ctx_shared *sh = priv->sh;
10052         struct mlx5_flow_sub_actions_list *sample_act;
10053         struct mlx5dv_dr_domain *domain;
10054         uint32_t idx = 0, res_idx = 0;
10055         struct rte_flow_error *error = ctx->error;
10056         uint64_t action_flags;
10057         int ret;
10058
10059         /* Register new destination array resource. */
10060         cache_resource = mlx5_ipool_zmalloc(sh->ipool[MLX5_IPOOL_DEST_ARRAY],
10061                                             &res_idx);
10062         if (!cache_resource) {
10063                 rte_flow_error_set(error, ENOMEM,
10064                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10065                                           NULL,
10066                                           "cannot allocate resource memory");
10067                 return NULL;
10068         }
10069         *cache_resource = *resource;
10070         if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_FDB)
10071                 domain = sh->fdb_domain;
10072         else if (resource->ft_type == MLX5DV_FLOW_TABLE_TYPE_NIC_RX)
10073                 domain = sh->rx_domain;
10074         else
10075                 domain = sh->tx_domain;
10076         for (idx = 0; idx < resource->num_of_dest; idx++) {
10077                 dest_attr[idx] = (struct mlx5dv_dr_action_dest_attr *)
10078                                  mlx5_malloc(MLX5_MEM_ZERO,
10079                                  sizeof(struct mlx5dv_dr_action_dest_attr),
10080                                  0, SOCKET_ID_ANY);
10081                 if (!dest_attr[idx]) {
10082                         rte_flow_error_set(error, ENOMEM,
10083                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10084                                            NULL,
10085                                            "cannot allocate resource memory");
10086                         goto error;
10087                 }
10088                 dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST;
10089                 sample_act = &resource->sample_act[idx];
10090                 action_flags = sample_act->action_flags;
10091                 switch (action_flags) {
10092                 case MLX5_FLOW_ACTION_QUEUE:
10093                         dest_attr[idx]->dest = sample_act->dr_queue_action;
10094                         break;
10095                 case (MLX5_FLOW_ACTION_PORT_ID | MLX5_FLOW_ACTION_ENCAP):
10096                         dest_attr[idx]->type = MLX5DV_DR_ACTION_DEST_REFORMAT;
10097                         dest_attr[idx]->dest_reformat = &dest_reformat[idx];
10098                         dest_attr[idx]->dest_reformat->reformat =
10099                                         sample_act->dr_encap_action;
10100                         dest_attr[idx]->dest_reformat->dest =
10101                                         sample_act->dr_port_id_action;
10102                         break;
10103                 case MLX5_FLOW_ACTION_PORT_ID:
10104                         dest_attr[idx]->dest = sample_act->dr_port_id_action;
10105                         break;
10106                 case MLX5_FLOW_ACTION_JUMP:
10107                         dest_attr[idx]->dest = sample_act->dr_jump_action;
10108                         break;
10109                 default:
10110                         rte_flow_error_set(error, EINVAL,
10111                                            RTE_FLOW_ERROR_TYPE_ACTION,
10112                                            NULL,
10113                                            "unsupported actions type");
10114                         goto error;
10115                 }
10116         }
10117         /* create a dest array actioin */
10118         ret = mlx5_os_flow_dr_create_flow_action_dest_array
10119                                                 (domain,
10120                                                  cache_resource->num_of_dest,
10121                                                  dest_attr,
10122                                                  &cache_resource->action);
10123         if (ret) {
10124                 rte_flow_error_set(error, ENOMEM,
10125                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10126                                    NULL,
10127                                    "cannot create destination array action");
10128                 goto error;
10129         }
10130         cache_resource->idx = res_idx;
10131         cache_resource->dev = dev;
10132         for (idx = 0; idx < resource->num_of_dest; idx++)
10133                 mlx5_free(dest_attr[idx]);
10134         return &cache_resource->entry;
10135 error:
10136         for (idx = 0; idx < resource->num_of_dest; idx++) {
10137                 struct mlx5_flow_sub_actions_idx *act_res =
10138                                         &cache_resource->sample_idx[idx];
10139                 if (act_res->rix_hrxq &&
10140                     !mlx5_hrxq_release(dev,
10141                                 act_res->rix_hrxq))
10142                         act_res->rix_hrxq = 0;
10143                 if (act_res->rix_encap_decap &&
10144                         !flow_dv_encap_decap_resource_release(dev,
10145                                 act_res->rix_encap_decap))
10146                         act_res->rix_encap_decap = 0;
10147                 if (act_res->rix_port_id_action &&
10148                         !flow_dv_port_id_action_resource_release(dev,
10149                                 act_res->rix_port_id_action))
10150                         act_res->rix_port_id_action = 0;
10151                 if (act_res->rix_jump &&
10152                         !flow_dv_jump_tbl_resource_release(dev,
10153                                 act_res->rix_jump))
10154                         act_res->rix_jump = 0;
10155                 if (dest_attr[idx])
10156                         mlx5_free(dest_attr[idx]);
10157         }
10158
10159         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DEST_ARRAY], res_idx);
10160         return NULL;
10161 }
10162
10163 /**
10164  * Find existing destination array resource or create and register a new one.
10165  *
10166  * @param[in, out] dev
10167  *   Pointer to rte_eth_dev structure.
10168  * @param[in] resource
10169  *   Pointer to destination array resource.
10170  * @parm[in, out] dev_flow
10171  *   Pointer to the dev_flow.
10172  * @param[out] error
10173  *   pointer to error structure.
10174  *
10175  * @return
10176  *   0 on success otherwise -errno and errno is set.
10177  */
10178 static int
10179 flow_dv_dest_array_resource_register(struct rte_eth_dev *dev,
10180                          struct mlx5_flow_dv_dest_array_resource *resource,
10181                          struct mlx5_flow *dev_flow,
10182                          struct rte_flow_error *error)
10183 {
10184         struct mlx5_flow_dv_dest_array_resource *cache_resource;
10185         struct mlx5_priv *priv = dev->data->dev_private;
10186         struct mlx5_cache_entry *entry;
10187         struct mlx5_flow_cb_ctx ctx = {
10188                 .dev = dev,
10189                 .error = error,
10190                 .data = resource,
10191         };
10192
10193         entry = mlx5_cache_register(&priv->sh->dest_array_list, &ctx);
10194         if (!entry)
10195                 return -rte_errno;
10196         cache_resource = container_of(entry, typeof(*cache_resource), entry);
10197         dev_flow->handle->dvh.rix_dest_array = cache_resource->idx;
10198         dev_flow->dv.dest_array_res = cache_resource;
10199         return 0;
10200 }
10201
10202 /**
10203  * Convert Sample action to DV specification.
10204  *
10205  * @param[in] dev
10206  *   Pointer to rte_eth_dev structure.
10207  * @param[in] action
10208  *   Pointer to sample action structure.
10209  * @param[in, out] dev_flow
10210  *   Pointer to the mlx5_flow.
10211  * @param[in] attr
10212  *   Pointer to the flow attributes.
10213  * @param[in, out] num_of_dest
10214  *   Pointer to the num of destination.
10215  * @param[in, out] sample_actions
10216  *   Pointer to sample actions list.
10217  * @param[in, out] res
10218  *   Pointer to sample resource.
10219  * @param[out] error
10220  *   Pointer to the error structure.
10221  *
10222  * @return
10223  *   0 on success, a negative errno value otherwise and rte_errno is set.
10224  */
10225 static int
10226 flow_dv_translate_action_sample(struct rte_eth_dev *dev,
10227                                 const struct rte_flow_action_sample *action,
10228                                 struct mlx5_flow *dev_flow,
10229                                 const struct rte_flow_attr *attr,
10230                                 uint32_t *num_of_dest,
10231                                 void **sample_actions,
10232                                 struct mlx5_flow_dv_sample_resource *res,
10233                                 struct rte_flow_error *error)
10234 {
10235         struct mlx5_priv *priv = dev->data->dev_private;
10236         const struct rte_flow_action *sub_actions;
10237         struct mlx5_flow_sub_actions_list *sample_act;
10238         struct mlx5_flow_sub_actions_idx *sample_idx;
10239         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10240         struct rte_flow *flow = dev_flow->flow;
10241         struct mlx5_flow_rss_desc *rss_desc;
10242         uint64_t action_flags = 0;
10243
10244         MLX5_ASSERT(wks);
10245         rss_desc = &wks->rss_desc;
10246         sample_act = &res->sample_act;
10247         sample_idx = &res->sample_idx;
10248         res->ratio = action->ratio;
10249         sub_actions = action->actions;
10250         for (; sub_actions->type != RTE_FLOW_ACTION_TYPE_END; sub_actions++) {
10251                 int type = sub_actions->type;
10252                 uint32_t pre_rix = 0;
10253                 void *pre_r;
10254                 switch (type) {
10255                 case RTE_FLOW_ACTION_TYPE_QUEUE:
10256                 {
10257                         const struct rte_flow_action_queue *queue;
10258                         struct mlx5_hrxq *hrxq;
10259                         uint32_t hrxq_idx;
10260
10261                         queue = sub_actions->conf;
10262                         rss_desc->queue_num = 1;
10263                         rss_desc->queue[0] = queue->index;
10264                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10265                                                     rss_desc, &hrxq_idx);
10266                         if (!hrxq)
10267                                 return rte_flow_error_set
10268                                         (error, rte_errno,
10269                                          RTE_FLOW_ERROR_TYPE_ACTION,
10270                                          NULL,
10271                                          "cannot create fate queue");
10272                         sample_act->dr_queue_action = hrxq->action;
10273                         sample_idx->rix_hrxq = hrxq_idx;
10274                         sample_actions[sample_act->actions_num++] =
10275                                                 hrxq->action;
10276                         (*num_of_dest)++;
10277                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
10278                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10279                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10280                         dev_flow->handle->fate_action =
10281                                         MLX5_FLOW_FATE_QUEUE;
10282                         break;
10283                 }
10284                 case RTE_FLOW_ACTION_TYPE_RSS:
10285                 {
10286                         struct mlx5_hrxq *hrxq;
10287                         uint32_t hrxq_idx;
10288                         const struct rte_flow_action_rss *rss;
10289                         const uint8_t *rss_key;
10290
10291                         rss = sub_actions->conf;
10292                         memcpy(rss_desc->queue, rss->queue,
10293                                rss->queue_num * sizeof(uint16_t));
10294                         rss_desc->queue_num = rss->queue_num;
10295                         /* NULL RSS key indicates default RSS key. */
10296                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
10297                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
10298                         /*
10299                          * rss->level and rss.types should be set in advance
10300                          * when expanding items for RSS.
10301                          */
10302                         flow_dv_hashfields_set(dev_flow, rss_desc);
10303                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10304                                                     rss_desc, &hrxq_idx);
10305                         if (!hrxq)
10306                                 return rte_flow_error_set
10307                                         (error, rte_errno,
10308                                          RTE_FLOW_ERROR_TYPE_ACTION,
10309                                          NULL,
10310                                          "cannot create fate queue");
10311                         sample_act->dr_queue_action = hrxq->action;
10312                         sample_idx->rix_hrxq = hrxq_idx;
10313                         sample_actions[sample_act->actions_num++] =
10314                                                 hrxq->action;
10315                         (*num_of_dest)++;
10316                         action_flags |= MLX5_FLOW_ACTION_RSS;
10317                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10318                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10319                         dev_flow->handle->fate_action =
10320                                         MLX5_FLOW_FATE_QUEUE;
10321                         break;
10322                 }
10323                 case RTE_FLOW_ACTION_TYPE_MARK:
10324                 {
10325                         uint32_t tag_be = mlx5_flow_mark_set
10326                                 (((const struct rte_flow_action_mark *)
10327                                 (sub_actions->conf))->id);
10328
10329                         dev_flow->handle->mark = 1;
10330                         pre_rix = dev_flow->handle->dvh.rix_tag;
10331                         /* Save the mark resource before sample */
10332                         pre_r = dev_flow->dv.tag_resource;
10333                         if (flow_dv_tag_resource_register(dev, tag_be,
10334                                                   dev_flow, error))
10335                                 return -rte_errno;
10336                         MLX5_ASSERT(dev_flow->dv.tag_resource);
10337                         sample_act->dr_tag_action =
10338                                 dev_flow->dv.tag_resource->action;
10339                         sample_idx->rix_tag =
10340                                 dev_flow->handle->dvh.rix_tag;
10341                         sample_actions[sample_act->actions_num++] =
10342                                                 sample_act->dr_tag_action;
10343                         /* Recover the mark resource after sample */
10344                         dev_flow->dv.tag_resource = pre_r;
10345                         dev_flow->handle->dvh.rix_tag = pre_rix;
10346                         action_flags |= MLX5_FLOW_ACTION_MARK;
10347                         break;
10348                 }
10349                 case RTE_FLOW_ACTION_TYPE_COUNT:
10350                 {
10351                         if (!flow->counter) {
10352                                 flow->counter =
10353                                         flow_dv_translate_create_counter(dev,
10354                                                 dev_flow, sub_actions->conf,
10355                                                 0);
10356                                 if (!flow->counter)
10357                                         return rte_flow_error_set
10358                                                 (error, rte_errno,
10359                                                 RTE_FLOW_ERROR_TYPE_ACTION,
10360                                                 NULL,
10361                                                 "cannot create counter"
10362                                                 " object.");
10363                         }
10364                         sample_act->dr_cnt_action =
10365                                   (flow_dv_counter_get_by_idx(dev,
10366                                   flow->counter, NULL))->action;
10367                         sample_actions[sample_act->actions_num++] =
10368                                                 sample_act->dr_cnt_action;
10369                         action_flags |= MLX5_FLOW_ACTION_COUNT;
10370                         break;
10371                 }
10372                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10373                 {
10374                         struct mlx5_flow_dv_port_id_action_resource
10375                                         port_id_resource;
10376                         uint32_t port_id = 0;
10377
10378                         memset(&port_id_resource, 0, sizeof(port_id_resource));
10379                         /* Save the port id resource before sample */
10380                         pre_rix = dev_flow->handle->rix_port_id_action;
10381                         pre_r = dev_flow->dv.port_id_action;
10382                         if (flow_dv_translate_action_port_id(dev, sub_actions,
10383                                                              &port_id, error))
10384                                 return -rte_errno;
10385                         port_id_resource.port_id = port_id;
10386                         if (flow_dv_port_id_action_resource_register
10387                             (dev, &port_id_resource, dev_flow, error))
10388                                 return -rte_errno;
10389                         sample_act->dr_port_id_action =
10390                                 dev_flow->dv.port_id_action->action;
10391                         sample_idx->rix_port_id_action =
10392                                 dev_flow->handle->rix_port_id_action;
10393                         sample_actions[sample_act->actions_num++] =
10394                                                 sample_act->dr_port_id_action;
10395                         /* Recover the port id resource after sample */
10396                         dev_flow->dv.port_id_action = pre_r;
10397                         dev_flow->handle->rix_port_id_action = pre_rix;
10398                         (*num_of_dest)++;
10399                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
10400                         break;
10401                 }
10402                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
10403                         /* Save the encap resource before sample */
10404                         pre_rix = dev_flow->handle->dvh.rix_encap_decap;
10405                         pre_r = dev_flow->dv.encap_decap;
10406                         if (flow_dv_create_action_l2_encap(dev, sub_actions,
10407                                                            dev_flow,
10408                                                            attr->transfer,
10409                                                            error))
10410                                 return -rte_errno;
10411                         sample_act->dr_encap_action =
10412                                 dev_flow->dv.encap_decap->action;
10413                         sample_idx->rix_encap_decap =
10414                                 dev_flow->handle->dvh.rix_encap_decap;
10415                         sample_actions[sample_act->actions_num++] =
10416                                                 sample_act->dr_encap_action;
10417                         /* Recover the encap resource after sample */
10418                         dev_flow->dv.encap_decap = pre_r;
10419                         dev_flow->handle->dvh.rix_encap_decap = pre_rix;
10420                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
10421                         break;
10422                 default:
10423                         return rte_flow_error_set(error, EINVAL,
10424                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10425                                 NULL,
10426                                 "Not support for sampler action");
10427                 }
10428         }
10429         sample_act->action_flags = action_flags;
10430         res->ft_id = dev_flow->dv.group;
10431         if (attr->transfer) {
10432                 union {
10433                         uint32_t action_in[MLX5_ST_SZ_DW(set_action_in)];
10434                         uint64_t set_action;
10435                 } action_ctx = { .set_action = 0 };
10436
10437                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10438                 MLX5_SET(set_action_in, action_ctx.action_in, action_type,
10439                          MLX5_MODIFICATION_TYPE_SET);
10440                 MLX5_SET(set_action_in, action_ctx.action_in, field,
10441                          MLX5_MODI_META_REG_C_0);
10442                 MLX5_SET(set_action_in, action_ctx.action_in, data,
10443                          priv->vport_meta_tag);
10444                 res->set_action = action_ctx.set_action;
10445         } else if (attr->ingress) {
10446                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10447         } else {
10448                 res->ft_type = MLX5DV_FLOW_TABLE_TYPE_NIC_TX;
10449         }
10450         return 0;
10451 }
10452
10453 /**
10454  * Convert Sample action to DV specification.
10455  *
10456  * @param[in] dev
10457  *   Pointer to rte_eth_dev structure.
10458  * @param[in, out] dev_flow
10459  *   Pointer to the mlx5_flow.
10460  * @param[in] num_of_dest
10461  *   The num of destination.
10462  * @param[in, out] res
10463  *   Pointer to sample resource.
10464  * @param[in, out] mdest_res
10465  *   Pointer to destination array resource.
10466  * @param[in] sample_actions
10467  *   Pointer to sample path actions list.
10468  * @param[in] action_flags
10469  *   Holds the actions detected until now.
10470  * @param[out] error
10471  *   Pointer to the error structure.
10472  *
10473  * @return
10474  *   0 on success, a negative errno value otherwise and rte_errno is set.
10475  */
10476 static int
10477 flow_dv_create_action_sample(struct rte_eth_dev *dev,
10478                              struct mlx5_flow *dev_flow,
10479                              uint32_t num_of_dest,
10480                              struct mlx5_flow_dv_sample_resource *res,
10481                              struct mlx5_flow_dv_dest_array_resource *mdest_res,
10482                              void **sample_actions,
10483                              uint64_t action_flags,
10484                              struct rte_flow_error *error)
10485 {
10486         /* update normal path action resource into last index of array */
10487         uint32_t dest_index = MLX5_MAX_DEST_NUM - 1;
10488         struct mlx5_flow_sub_actions_list *sample_act =
10489                                         &mdest_res->sample_act[dest_index];
10490         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10491         struct mlx5_flow_rss_desc *rss_desc;
10492         uint32_t normal_idx = 0;
10493         struct mlx5_hrxq *hrxq;
10494         uint32_t hrxq_idx;
10495
10496         MLX5_ASSERT(wks);
10497         rss_desc = &wks->rss_desc;
10498         if (num_of_dest > 1) {
10499                 if (sample_act->action_flags & MLX5_FLOW_ACTION_QUEUE) {
10500                         /* Handle QP action for mirroring */
10501                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow,
10502                                                     rss_desc, &hrxq_idx);
10503                         if (!hrxq)
10504                                 return rte_flow_error_set
10505                                      (error, rte_errno,
10506                                       RTE_FLOW_ERROR_TYPE_ACTION,
10507                                       NULL,
10508                                       "cannot create rx queue");
10509                         normal_idx++;
10510                         mdest_res->sample_idx[dest_index].rix_hrxq = hrxq_idx;
10511                         sample_act->dr_queue_action = hrxq->action;
10512                         if (action_flags & MLX5_FLOW_ACTION_MARK)
10513                                 dev_flow->handle->rix_hrxq = hrxq_idx;
10514                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
10515                 }
10516                 if (sample_act->action_flags & MLX5_FLOW_ACTION_ENCAP) {
10517                         normal_idx++;
10518                         mdest_res->sample_idx[dest_index].rix_encap_decap =
10519                                 dev_flow->handle->dvh.rix_encap_decap;
10520                         sample_act->dr_encap_action =
10521                                 dev_flow->dv.encap_decap->action;
10522                 }
10523                 if (sample_act->action_flags & MLX5_FLOW_ACTION_PORT_ID) {
10524                         normal_idx++;
10525                         mdest_res->sample_idx[dest_index].rix_port_id_action =
10526                                 dev_flow->handle->rix_port_id_action;
10527                         sample_act->dr_port_id_action =
10528                                 dev_flow->dv.port_id_action->action;
10529                 }
10530                 if (sample_act->action_flags & MLX5_FLOW_ACTION_JUMP) {
10531                         normal_idx++;
10532                         mdest_res->sample_idx[dest_index].rix_jump =
10533                                 dev_flow->handle->rix_jump;
10534                         sample_act->dr_jump_action =
10535                                 dev_flow->dv.jump->action;
10536                         dev_flow->handle->rix_jump = 0;
10537                 }
10538                 sample_act->actions_num = normal_idx;
10539                 /* update sample action resource into first index of array */
10540                 mdest_res->ft_type = res->ft_type;
10541                 memcpy(&mdest_res->sample_idx[0], &res->sample_idx,
10542                                 sizeof(struct mlx5_flow_sub_actions_idx));
10543                 memcpy(&mdest_res->sample_act[0], &res->sample_act,
10544                                 sizeof(struct mlx5_flow_sub_actions_list));
10545                 mdest_res->num_of_dest = num_of_dest;
10546                 if (flow_dv_dest_array_resource_register(dev, mdest_res,
10547                                                          dev_flow, error))
10548                         return rte_flow_error_set(error, EINVAL,
10549                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10550                                                   NULL, "can't create sample "
10551                                                   "action");
10552         } else {
10553                 res->sub_actions = sample_actions;
10554                 if (flow_dv_sample_resource_register(dev, res, dev_flow, error))
10555                         return rte_flow_error_set(error, EINVAL,
10556                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10557                                                   NULL,
10558                                                   "can't create sample action");
10559         }
10560         return 0;
10561 }
10562
10563 /**
10564  * Remove an ASO age action from age actions list.
10565  *
10566  * @param[in] dev
10567  *   Pointer to the Ethernet device structure.
10568  * @param[in] age
10569  *   Pointer to the aso age action handler.
10570  */
10571 static void
10572 flow_dv_aso_age_remove_from_age(struct rte_eth_dev *dev,
10573                                 struct mlx5_aso_age_action *age)
10574 {
10575         struct mlx5_age_info *age_info;
10576         struct mlx5_age_param *age_param = &age->age_params;
10577         struct mlx5_priv *priv = dev->data->dev_private;
10578         uint16_t expected = AGE_CANDIDATE;
10579
10580         age_info = GET_PORT_AGE_INFO(priv);
10581         if (!__atomic_compare_exchange_n(&age_param->state, &expected,
10582                                          AGE_FREE, false, __ATOMIC_RELAXED,
10583                                          __ATOMIC_RELAXED)) {
10584                 /**
10585                  * We need the lock even it is age timeout,
10586                  * since age action may still in process.
10587                  */
10588                 rte_spinlock_lock(&age_info->aged_sl);
10589                 LIST_REMOVE(age, next);
10590                 rte_spinlock_unlock(&age_info->aged_sl);
10591                 __atomic_store_n(&age_param->state, AGE_FREE, __ATOMIC_RELAXED);
10592         }
10593 }
10594
10595 /**
10596  * Release an ASO age action.
10597  *
10598  * @param[in] dev
10599  *   Pointer to the Ethernet device structure.
10600  * @param[in] age_idx
10601  *   Index of ASO age action to release.
10602  * @param[in] flow
10603  *   True if the release operation is during flow destroy operation.
10604  *   False if the release operation is during action destroy operation.
10605  *
10606  * @return
10607  *   0 when age action was removed, otherwise the number of references.
10608  */
10609 static int
10610 flow_dv_aso_age_release(struct rte_eth_dev *dev, uint32_t age_idx)
10611 {
10612         struct mlx5_priv *priv = dev->data->dev_private;
10613         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10614         struct mlx5_aso_age_action *age = flow_aso_age_get_by_idx(dev, age_idx);
10615         uint32_t ret = __atomic_sub_fetch(&age->refcnt, 1, __ATOMIC_RELAXED);
10616
10617         if (!ret) {
10618                 flow_dv_aso_age_remove_from_age(dev, age);
10619                 rte_spinlock_lock(&mng->free_sl);
10620                 LIST_INSERT_HEAD(&mng->free, age, next);
10621                 rte_spinlock_unlock(&mng->free_sl);
10622         }
10623         return ret;
10624 }
10625
10626 /**
10627  * Resize the ASO age pools array by MLX5_CNT_CONTAINER_RESIZE pools.
10628  *
10629  * @param[in] dev
10630  *   Pointer to the Ethernet device structure.
10631  *
10632  * @return
10633  *   0 on success, otherwise negative errno value and rte_errno is set.
10634  */
10635 static int
10636 flow_dv_aso_age_pools_resize(struct rte_eth_dev *dev)
10637 {
10638         struct mlx5_priv *priv = dev->data->dev_private;
10639         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10640         void *old_pools = mng->pools;
10641         uint32_t resize = mng->n + MLX5_CNT_CONTAINER_RESIZE;
10642         uint32_t mem_size = sizeof(struct mlx5_aso_age_pool *) * resize;
10643         void *pools = mlx5_malloc(MLX5_MEM_ZERO, mem_size, 0, SOCKET_ID_ANY);
10644
10645         if (!pools) {
10646                 rte_errno = ENOMEM;
10647                 return -ENOMEM;
10648         }
10649         if (old_pools) {
10650                 memcpy(pools, old_pools,
10651                        mng->n * sizeof(struct mlx5_flow_counter_pool *));
10652                 mlx5_free(old_pools);
10653         } else {
10654                 /* First ASO flow hit allocation - starting ASO data-path. */
10655                 int ret = mlx5_aso_queue_start(priv->sh);
10656
10657                 if (ret) {
10658                         mlx5_free(pools);
10659                         return ret;
10660                 }
10661         }
10662         mng->n = resize;
10663         mng->pools = pools;
10664         return 0;
10665 }
10666
10667 /**
10668  * Create and initialize a new ASO aging pool.
10669  *
10670  * @param[in] dev
10671  *   Pointer to the Ethernet device structure.
10672  * @param[out] age_free
10673  *   Where to put the pointer of a new age action.
10674  *
10675  * @return
10676  *   The age actions pool pointer and @p age_free is set on success,
10677  *   NULL otherwise and rte_errno is set.
10678  */
10679 static struct mlx5_aso_age_pool *
10680 flow_dv_age_pool_create(struct rte_eth_dev *dev,
10681                         struct mlx5_aso_age_action **age_free)
10682 {
10683         struct mlx5_priv *priv = dev->data->dev_private;
10684         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10685         struct mlx5_aso_age_pool *pool = NULL;
10686         struct mlx5_devx_obj *obj = NULL;
10687         uint32_t i;
10688
10689         obj = mlx5_devx_cmd_create_flow_hit_aso_obj(priv->sh->ctx,
10690                                                     priv->sh->pdn);
10691         if (!obj) {
10692                 rte_errno = ENODATA;
10693                 DRV_LOG(ERR, "Failed to create flow_hit_aso_obj using DevX.");
10694                 return NULL;
10695         }
10696         pool = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*pool), 0, SOCKET_ID_ANY);
10697         if (!pool) {
10698                 claim_zero(mlx5_devx_cmd_destroy(obj));
10699                 rte_errno = ENOMEM;
10700                 return NULL;
10701         }
10702         pool->flow_hit_aso_obj = obj;
10703         pool->time_of_last_age_check = MLX5_CURR_TIME_SEC;
10704         rte_spinlock_lock(&mng->resize_sl);
10705         pool->index = mng->next;
10706         /* Resize pools array if there is no room for the new pool in it. */
10707         if (pool->index == mng->n && flow_dv_aso_age_pools_resize(dev)) {
10708                 claim_zero(mlx5_devx_cmd_destroy(obj));
10709                 mlx5_free(pool);
10710                 rte_spinlock_unlock(&mng->resize_sl);
10711                 return NULL;
10712         }
10713         mng->pools[pool->index] = pool;
10714         mng->next++;
10715         rte_spinlock_unlock(&mng->resize_sl);
10716         /* Assign the first action in the new pool, the rest go to free list. */
10717         *age_free = &pool->actions[0];
10718         for (i = 1; i < MLX5_ASO_AGE_ACTIONS_PER_POOL; i++) {
10719                 pool->actions[i].offset = i;
10720                 LIST_INSERT_HEAD(&mng->free, &pool->actions[i], next);
10721         }
10722         return pool;
10723 }
10724
10725 /**
10726  * Allocate a ASO aging bit.
10727  *
10728  * @param[in] dev
10729  *   Pointer to the Ethernet device structure.
10730  * @param[out] error
10731  *   Pointer to the error structure.
10732  *
10733  * @return
10734  *   Index to ASO age action on success, 0 otherwise and rte_errno is set.
10735  */
10736 static uint32_t
10737 flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
10738 {
10739         struct mlx5_priv *priv = dev->data->dev_private;
10740         const struct mlx5_aso_age_pool *pool;
10741         struct mlx5_aso_age_action *age_free = NULL;
10742         struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng;
10743
10744         MLX5_ASSERT(mng);
10745         /* Try to get the next free age action bit. */
10746         rte_spinlock_lock(&mng->free_sl);
10747         age_free = LIST_FIRST(&mng->free);
10748         if (age_free) {
10749                 LIST_REMOVE(age_free, next);
10750         } else if (!flow_dv_age_pool_create(dev, &age_free)) {
10751                 rte_spinlock_unlock(&mng->free_sl);
10752                 rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
10753                                    NULL, "failed to create ASO age pool");
10754                 return 0; /* 0 is an error. */
10755         }
10756         rte_spinlock_unlock(&mng->free_sl);
10757         pool = container_of
10758           ((const struct mlx5_aso_age_action (*)[MLX5_ASO_AGE_ACTIONS_PER_POOL])
10759                   (age_free - age_free->offset), const struct mlx5_aso_age_pool,
10760                                                                        actions);
10761         if (!age_free->dr_action) {
10762                 int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
10763                                                  error);
10764
10765                 if (reg_c < 0) {
10766                         rte_flow_error_set(error, rte_errno,
10767                                            RTE_FLOW_ERROR_TYPE_ACTION,
10768                                            NULL, "failed to get reg_c "
10769                                            "for ASO flow hit");
10770                         return 0; /* 0 is an error. */
10771                 }
10772 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO
10773                 age_free->dr_action = mlx5_glue->dv_create_flow_action_aso
10774                                 (priv->sh->rx_domain,
10775                                  pool->flow_hit_aso_obj->obj, age_free->offset,
10776                                  MLX5DV_DR_ACTION_FLAGS_ASO_FIRST_HIT_SET,
10777                                  (reg_c - REG_C_0));
10778 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */
10779                 if (!age_free->dr_action) {
10780                         rte_errno = errno;
10781                         rte_spinlock_lock(&mng->free_sl);
10782                         LIST_INSERT_HEAD(&mng->free, age_free, next);
10783                         rte_spinlock_unlock(&mng->free_sl);
10784                         rte_flow_error_set(error, rte_errno,
10785                                            RTE_FLOW_ERROR_TYPE_ACTION,
10786                                            NULL, "failed to create ASO "
10787                                            "flow hit action");
10788                         return 0; /* 0 is an error. */
10789                 }
10790         }
10791         __atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
10792         return pool->index | ((age_free->offset + 1) << 16);
10793 }
10794
10795 /**
10796  * Create a age action using ASO mechanism.
10797  *
10798  * @param[in] dev
10799  *   Pointer to rte_eth_dev structure.
10800  * @param[in] age
10801  *   Pointer to the aging action configuration.
10802  * @param[out] error
10803  *   Pointer to the error structure.
10804  *
10805  * @return
10806  *   Index to flow counter on success, 0 otherwise.
10807  */
10808 static uint32_t
10809 flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
10810                                  const struct rte_flow_action_age *age,
10811                                  struct rte_flow_error *error)
10812 {
10813         uint32_t age_idx = 0;
10814         struct mlx5_aso_age_action *aso_age;
10815
10816         age_idx = flow_dv_aso_age_alloc(dev, error);
10817         if (!age_idx)
10818                 return 0;
10819         aso_age = flow_aso_age_get_by_idx(dev, age_idx);
10820         aso_age->age_params.context = age->context;
10821         aso_age->age_params.timeout = age->timeout;
10822         aso_age->age_params.port_id = dev->data->port_id;
10823         __atomic_store_n(&aso_age->age_params.sec_since_last_hit, 0,
10824                          __ATOMIC_RELAXED);
10825         __atomic_store_n(&aso_age->age_params.state, AGE_CANDIDATE,
10826                          __ATOMIC_RELAXED);
10827         return age_idx;
10828 }
10829
10830 /**
10831  * Fill the flow with DV spec, lock free
10832  * (mutex should be acquired by caller).
10833  *
10834  * @param[in] dev
10835  *   Pointer to rte_eth_dev structure.
10836  * @param[in, out] dev_flow
10837  *   Pointer to the sub flow.
10838  * @param[in] attr
10839  *   Pointer to the flow attributes.
10840  * @param[in] items
10841  *   Pointer to the list of items.
10842  * @param[in] actions
10843  *   Pointer to the list of actions.
10844  * @param[out] error
10845  *   Pointer to the error structure.
10846  *
10847  * @return
10848  *   0 on success, a negative errno value otherwise and rte_errno is set.
10849  */
10850 static int
10851 flow_dv_translate(struct rte_eth_dev *dev,
10852                   struct mlx5_flow *dev_flow,
10853                   const struct rte_flow_attr *attr,
10854                   const struct rte_flow_item items[],
10855                   const struct rte_flow_action actions[],
10856                   struct rte_flow_error *error)
10857 {
10858         struct mlx5_priv *priv = dev->data->dev_private;
10859         struct mlx5_dev_config *dev_conf = &priv->config;
10860         struct rte_flow *flow = dev_flow->flow;
10861         struct mlx5_flow_handle *handle = dev_flow->handle;
10862         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
10863         struct mlx5_flow_rss_desc *rss_desc;
10864         uint64_t item_flags = 0;
10865         uint64_t last_item = 0;
10866         uint64_t action_flags = 0;
10867         struct mlx5_flow_dv_matcher matcher = {
10868                 .mask = {
10869                         .size = sizeof(matcher.mask.buf) -
10870                                 MLX5_ST_SZ_BYTES(fte_match_set_misc4),
10871                 },
10872         };
10873         int actions_n = 0;
10874         bool actions_end = false;
10875         union {
10876                 struct mlx5_flow_dv_modify_hdr_resource res;
10877                 uint8_t len[sizeof(struct mlx5_flow_dv_modify_hdr_resource) +
10878                             sizeof(struct mlx5_modification_cmd) *
10879                             (MLX5_MAX_MODIFY_NUM + 1)];
10880         } mhdr_dummy;
10881         struct mlx5_flow_dv_modify_hdr_resource *mhdr_res = &mhdr_dummy.res;
10882         const struct rte_flow_action_count *count = NULL;
10883         const struct rte_flow_action_age *age = NULL;
10884         union flow_dv_attr flow_attr = { .attr = 0 };
10885         uint32_t tag_be;
10886         union mlx5_flow_tbl_key tbl_key;
10887         uint32_t modify_action_position = UINT32_MAX;
10888         void *match_mask = matcher.mask.buf;
10889         void *match_value = dev_flow->dv.value.buf;
10890         uint8_t next_protocol = 0xff;
10891         struct rte_vlan_hdr vlan = { 0 };
10892         struct mlx5_flow_dv_dest_array_resource mdest_res;
10893         struct mlx5_flow_dv_sample_resource sample_res;
10894         void *sample_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
10895         const struct rte_flow_action_sample *sample = NULL;
10896         struct mlx5_flow_sub_actions_list *sample_act;
10897         uint32_t sample_act_pos = UINT32_MAX;
10898         uint32_t num_of_dest = 0;
10899         int tmp_actions_n = 0;
10900         uint32_t table;
10901         int ret = 0;
10902         const struct mlx5_flow_tunnel *tunnel;
10903         struct flow_grp_info grp_info = {
10904                 .external = !!dev_flow->external,
10905                 .transfer = !!attr->transfer,
10906                 .fdb_def_rule = !!priv->fdb_def_rule,
10907                 .skip_scale = dev_flow->skip_scale &
10908                         (1 << MLX5_SCALE_FLOW_GROUP_BIT),
10909         };
10910
10911         if (!wks)
10912                 return rte_flow_error_set(error, ENOMEM,
10913                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
10914                                           NULL,
10915                                           "failed to push flow workspace");
10916         rss_desc = &wks->rss_desc;
10917         memset(&mdest_res, 0, sizeof(struct mlx5_flow_dv_dest_array_resource));
10918         memset(&sample_res, 0, sizeof(struct mlx5_flow_dv_sample_resource));
10919         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10920                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10921         /* update normal path action resource into last index of array */
10922         sample_act = &mdest_res.sample_act[MLX5_MAX_DEST_NUM - 1];
10923         tunnel = is_flow_tunnel_match_rule(dev, attr, items, actions) ?
10924                  flow_items_to_tunnel(items) :
10925                  is_flow_tunnel_steer_rule(dev, attr, items, actions) ?
10926                  flow_actions_to_tunnel(actions) :
10927                  dev_flow->tunnel ? dev_flow->tunnel : NULL;
10928         mhdr_res->ft_type = attr->egress ? MLX5DV_FLOW_TABLE_TYPE_NIC_TX :
10929                                            MLX5DV_FLOW_TABLE_TYPE_NIC_RX;
10930         grp_info.std_tbl_fix = tunnel_use_standard_attr_group_translate
10931                                 (dev, tunnel, attr, items, actions);
10932         ret = mlx5_flow_group_to_table(dev, tunnel, attr->group, &table,
10933                                        &grp_info, error);
10934         if (ret)
10935                 return ret;
10936         dev_flow->dv.group = table;
10937         if (attr->transfer)
10938                 mhdr_res->ft_type = MLX5DV_FLOW_TABLE_TYPE_FDB;
10939         /* number of actions must be set to 0 in case of dirty stack. */
10940         mhdr_res->actions_num = 0;
10941         if (is_flow_tunnel_match_rule(dev, attr, items, actions)) {
10942                 /*
10943                  * do not add decap action if match rule drops packet
10944                  * HW rejects rules with decap & drop
10945                  *
10946                  * if tunnel match rule was inserted before matching tunnel set
10947                  * rule flow table used in the match rule must be registered.
10948                  * current implementation handles that in the
10949                  * flow_dv_match_register() at the function end.
10950                  */
10951                 bool add_decap = true;
10952                 const struct rte_flow_action *ptr = actions;
10953
10954                 for (; ptr->type != RTE_FLOW_ACTION_TYPE_END; ptr++) {
10955                         if (ptr->type == RTE_FLOW_ACTION_TYPE_DROP) {
10956                                 add_decap = false;
10957                                 break;
10958                         }
10959                 }
10960                 if (add_decap) {
10961                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
10962                                                            attr->transfer,
10963                                                            error))
10964                                 return -rte_errno;
10965                         dev_flow->dv.actions[actions_n++] =
10966                                         dev_flow->dv.encap_decap->action;
10967                         action_flags |= MLX5_FLOW_ACTION_DECAP;
10968                 }
10969         }
10970         for (; !actions_end ; actions++) {
10971                 const struct rte_flow_action_queue *queue;
10972                 const struct rte_flow_action_rss *rss;
10973                 const struct rte_flow_action *action = actions;
10974                 const uint8_t *rss_key;
10975                 const struct rte_flow_action_meter *mtr;
10976                 struct mlx5_flow_tbl_resource *tbl;
10977                 struct mlx5_aso_age_action *age_act;
10978                 uint32_t port_id = 0;
10979                 struct mlx5_flow_dv_port_id_action_resource port_id_resource;
10980                 int action_type = actions->type;
10981                 const struct rte_flow_action *found_action = NULL;
10982                 struct mlx5_flow_meter *fm = NULL;
10983                 uint32_t jump_group = 0;
10984
10985                 if (!mlx5_flow_os_action_supported(action_type))
10986                         return rte_flow_error_set(error, ENOTSUP,
10987                                                   RTE_FLOW_ERROR_TYPE_ACTION,
10988                                                   actions,
10989                                                   "action not supported");
10990                 switch (action_type) {
10991                 case MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET:
10992                         action_flags |= MLX5_FLOW_ACTION_TUNNEL_SET;
10993                         break;
10994                 case RTE_FLOW_ACTION_TYPE_VOID:
10995                         break;
10996                 case RTE_FLOW_ACTION_TYPE_PORT_ID:
10997                         if (flow_dv_translate_action_port_id(dev, action,
10998                                                              &port_id, error))
10999                                 return -rte_errno;
11000                         port_id_resource.port_id = port_id;
11001                         MLX5_ASSERT(!handle->rix_port_id_action);
11002                         if (flow_dv_port_id_action_resource_register
11003                             (dev, &port_id_resource, dev_flow, error))
11004                                 return -rte_errno;
11005                         dev_flow->dv.actions[actions_n++] =
11006                                         dev_flow->dv.port_id_action->action;
11007                         action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11008                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_PORT_ID;
11009                         sample_act->action_flags |= MLX5_FLOW_ACTION_PORT_ID;
11010                         num_of_dest++;
11011                         break;
11012                 case RTE_FLOW_ACTION_TYPE_FLAG:
11013                         action_flags |= MLX5_FLOW_ACTION_FLAG;
11014                         dev_flow->handle->mark = 1;
11015                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11016                                 struct rte_flow_action_mark mark = {
11017                                         .id = MLX5_FLOW_MARK_DEFAULT,
11018                                 };
11019
11020                                 if (flow_dv_convert_action_mark(dev, &mark,
11021                                                                 mhdr_res,
11022                                                                 error))
11023                                         return -rte_errno;
11024                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11025                                 break;
11026                         }
11027                         tag_be = mlx5_flow_mark_set(MLX5_FLOW_MARK_DEFAULT);
11028                         /*
11029                          * Only one FLAG or MARK is supported per device flow
11030                          * right now. So the pointer to the tag resource must be
11031                          * zero before the register process.
11032                          */
11033                         MLX5_ASSERT(!handle->dvh.rix_tag);
11034                         if (flow_dv_tag_resource_register(dev, tag_be,
11035                                                           dev_flow, error))
11036                                 return -rte_errno;
11037                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11038                         dev_flow->dv.actions[actions_n++] =
11039                                         dev_flow->dv.tag_resource->action;
11040                         break;
11041                 case RTE_FLOW_ACTION_TYPE_MARK:
11042                         action_flags |= MLX5_FLOW_ACTION_MARK;
11043                         dev_flow->handle->mark = 1;
11044                         if (dev_conf->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) {
11045                                 const struct rte_flow_action_mark *mark =
11046                                         (const struct rte_flow_action_mark *)
11047                                                 actions->conf;
11048
11049                                 if (flow_dv_convert_action_mark(dev, mark,
11050                                                                 mhdr_res,
11051                                                                 error))
11052                                         return -rte_errno;
11053                                 action_flags |= MLX5_FLOW_ACTION_MARK_EXT;
11054                                 break;
11055                         }
11056                         /* Fall-through */
11057                 case MLX5_RTE_FLOW_ACTION_TYPE_MARK:
11058                         /* Legacy (non-extensive) MARK action. */
11059                         tag_be = mlx5_flow_mark_set
11060                               (((const struct rte_flow_action_mark *)
11061                                (actions->conf))->id);
11062                         MLX5_ASSERT(!handle->dvh.rix_tag);
11063                         if (flow_dv_tag_resource_register(dev, tag_be,
11064                                                           dev_flow, error))
11065                                 return -rte_errno;
11066                         MLX5_ASSERT(dev_flow->dv.tag_resource);
11067                         dev_flow->dv.actions[actions_n++] =
11068                                         dev_flow->dv.tag_resource->action;
11069                         break;
11070                 case RTE_FLOW_ACTION_TYPE_SET_META:
11071                         if (flow_dv_convert_action_set_meta
11072                                 (dev, mhdr_res, attr,
11073                                  (const struct rte_flow_action_set_meta *)
11074                                   actions->conf, error))
11075                                 return -rte_errno;
11076                         action_flags |= MLX5_FLOW_ACTION_SET_META;
11077                         break;
11078                 case RTE_FLOW_ACTION_TYPE_SET_TAG:
11079                         if (flow_dv_convert_action_set_tag
11080                                 (dev, mhdr_res,
11081                                  (const struct rte_flow_action_set_tag *)
11082                                   actions->conf, error))
11083                                 return -rte_errno;
11084                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11085                         break;
11086                 case RTE_FLOW_ACTION_TYPE_DROP:
11087                         action_flags |= MLX5_FLOW_ACTION_DROP;
11088                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_DROP;
11089                         break;
11090                 case RTE_FLOW_ACTION_TYPE_QUEUE:
11091                         queue = actions->conf;
11092                         rss_desc->queue_num = 1;
11093                         rss_desc->queue[0] = queue->index;
11094                         action_flags |= MLX5_FLOW_ACTION_QUEUE;
11095                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_QUEUE;
11096                         sample_act->action_flags |= MLX5_FLOW_ACTION_QUEUE;
11097                         num_of_dest++;
11098                         break;
11099                 case RTE_FLOW_ACTION_TYPE_RSS:
11100                         rss = actions->conf;
11101                         memcpy(rss_desc->queue, rss->queue,
11102                                rss->queue_num * sizeof(uint16_t));
11103                         rss_desc->queue_num = rss->queue_num;
11104                         /* NULL RSS key indicates default RSS key. */
11105                         rss_key = !rss->key ? rss_hash_default_key : rss->key;
11106                         memcpy(rss_desc->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
11107                         /*
11108                          * rss->level and rss.types should be set in advance
11109                          * when expanding items for RSS.
11110                          */
11111                         action_flags |= MLX5_FLOW_ACTION_RSS;
11112                         dev_flow->handle->fate_action = rss_desc->shared_rss ?
11113                                 MLX5_FLOW_FATE_SHARED_RSS :
11114                                 MLX5_FLOW_FATE_QUEUE;
11115                         break;
11116                 case MLX5_RTE_FLOW_ACTION_TYPE_AGE:
11117                         flow->age = (uint32_t)(uintptr_t)(action->conf);
11118                         age_act = flow_aso_age_get_by_idx(dev, flow->age);
11119                         __atomic_fetch_add(&age_act->refcnt, 1,
11120                                            __ATOMIC_RELAXED);
11121                         dev_flow->dv.actions[actions_n++] = age_act->dr_action;
11122                         action_flags |= MLX5_FLOW_ACTION_AGE;
11123                         break;
11124                 case RTE_FLOW_ACTION_TYPE_AGE:
11125                         if (priv->sh->flow_hit_aso_en && attr->group) {
11126                                 /*
11127                                  * Create one shared age action, to be used
11128                                  * by all sub-flows.
11129                                  */
11130                                 if (!flow->age) {
11131                                         flow->age =
11132                                                 flow_dv_translate_create_aso_age
11133                                                         (dev, action->conf,
11134                                                          error);
11135                                         if (!flow->age)
11136                                                 return rte_flow_error_set
11137                                                 (error, rte_errno,
11138                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11139                                                  NULL,
11140                                                  "can't create ASO age action");
11141                                 }
11142                                 dev_flow->dv.actions[actions_n++] =
11143                                           (flow_aso_age_get_by_idx
11144                                                 (dev, flow->age))->dr_action;
11145                                 action_flags |= MLX5_FLOW_ACTION_AGE;
11146                                 break;
11147                         }
11148                         /* Fall-through */
11149                 case RTE_FLOW_ACTION_TYPE_COUNT:
11150                         if (!dev_conf->devx) {
11151                                 return rte_flow_error_set
11152                                               (error, ENOTSUP,
11153                                                RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
11154                                                NULL,
11155                                                "count action not supported");
11156                         }
11157                         /* Save information first, will apply later. */
11158                         if (actions->type == RTE_FLOW_ACTION_TYPE_COUNT)
11159                                 count = action->conf;
11160                         else
11161                                 age = action->conf;
11162                         action_flags |= MLX5_FLOW_ACTION_COUNT;
11163                         break;
11164                 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN:
11165                         dev_flow->dv.actions[actions_n++] =
11166                                                 priv->sh->pop_vlan_action;
11167                         action_flags |= MLX5_FLOW_ACTION_OF_POP_VLAN;
11168                         break;
11169                 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN:
11170                         if (!(action_flags &
11171                               MLX5_FLOW_ACTION_OF_SET_VLAN_VID))
11172                                 flow_dev_get_vlan_info_from_items(items, &vlan);
11173                         vlan.eth_proto = rte_be_to_cpu_16
11174                              ((((const struct rte_flow_action_of_push_vlan *)
11175                                                    actions->conf)->ethertype));
11176                         found_action = mlx5_flow_find_action
11177                                         (actions + 1,
11178                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID);
11179                         if (found_action)
11180                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11181                         found_action = mlx5_flow_find_action
11182                                         (actions + 1,
11183                                          RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP);
11184                         if (found_action)
11185                                 mlx5_update_vlan_vid_pcp(found_action, &vlan);
11186                         if (flow_dv_create_action_push_vlan
11187                                             (dev, attr, &vlan, dev_flow, error))
11188                                 return -rte_errno;
11189                         dev_flow->dv.actions[actions_n++] =
11190                                         dev_flow->dv.push_vlan_res->action;
11191                         action_flags |= MLX5_FLOW_ACTION_OF_PUSH_VLAN;
11192                         break;
11193                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP:
11194                         /* of_vlan_push action handled this action */
11195                         MLX5_ASSERT(action_flags &
11196                                     MLX5_FLOW_ACTION_OF_PUSH_VLAN);
11197                         break;
11198                 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID:
11199                         if (action_flags & MLX5_FLOW_ACTION_OF_PUSH_VLAN)
11200                                 break;
11201                         flow_dev_get_vlan_info_from_items(items, &vlan);
11202                         mlx5_update_vlan_vid_pcp(actions, &vlan);
11203                         /* If no VLAN push - this is a modify header action */
11204                         if (flow_dv_convert_action_modify_vlan_vid
11205                                                 (mhdr_res, actions, error))
11206                                 return -rte_errno;
11207                         action_flags |= MLX5_FLOW_ACTION_OF_SET_VLAN_VID;
11208                         break;
11209                 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:
11210                 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:
11211                         if (flow_dv_create_action_l2_encap(dev, actions,
11212                                                            dev_flow,
11213                                                            attr->transfer,
11214                                                            error))
11215                                 return -rte_errno;
11216                         dev_flow->dv.actions[actions_n++] =
11217                                         dev_flow->dv.encap_decap->action;
11218                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11219                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11220                                 sample_act->action_flags |=
11221                                                         MLX5_FLOW_ACTION_ENCAP;
11222                         break;
11223                 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP:
11224                 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP:
11225                         if (flow_dv_create_action_l2_decap(dev, dev_flow,
11226                                                            attr->transfer,
11227                                                            error))
11228                                 return -rte_errno;
11229                         dev_flow->dv.actions[actions_n++] =
11230                                         dev_flow->dv.encap_decap->action;
11231                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11232                         break;
11233                 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP:
11234                         /* Handle encap with preceding decap. */
11235                         if (action_flags & MLX5_FLOW_ACTION_DECAP) {
11236                                 if (flow_dv_create_action_raw_encap
11237                                         (dev, actions, dev_flow, attr, error))
11238                                         return -rte_errno;
11239                                 dev_flow->dv.actions[actions_n++] =
11240                                         dev_flow->dv.encap_decap->action;
11241                         } else {
11242                                 /* Handle encap without preceding decap. */
11243                                 if (flow_dv_create_action_l2_encap
11244                                     (dev, actions, dev_flow, attr->transfer,
11245                                      error))
11246                                         return -rte_errno;
11247                                 dev_flow->dv.actions[actions_n++] =
11248                                         dev_flow->dv.encap_decap->action;
11249                         }
11250                         action_flags |= MLX5_FLOW_ACTION_ENCAP;
11251                         if (action_flags & MLX5_FLOW_ACTION_SAMPLE)
11252                                 sample_act->action_flags |=
11253                                                         MLX5_FLOW_ACTION_ENCAP;
11254                         break;
11255                 case RTE_FLOW_ACTION_TYPE_RAW_DECAP:
11256                         while ((++action)->type == RTE_FLOW_ACTION_TYPE_VOID)
11257                                 ;
11258                         if (action->type != RTE_FLOW_ACTION_TYPE_RAW_ENCAP) {
11259                                 if (flow_dv_create_action_l2_decap
11260                                     (dev, dev_flow, attr->transfer, error))
11261                                         return -rte_errno;
11262                                 dev_flow->dv.actions[actions_n++] =
11263                                         dev_flow->dv.encap_decap->action;
11264                         }
11265                         /* If decap is followed by encap, handle it at encap. */
11266                         action_flags |= MLX5_FLOW_ACTION_DECAP;
11267                         break;
11268                 case RTE_FLOW_ACTION_TYPE_JUMP:
11269                         jump_group = ((const struct rte_flow_action_jump *)
11270                                                         action->conf)->group;
11271                         grp_info.std_tbl_fix = 0;
11272                         if (dev_flow->skip_scale &
11273                                 (1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT))
11274                                 grp_info.skip_scale = 1;
11275                         else
11276                                 grp_info.skip_scale = 0;
11277                         ret = mlx5_flow_group_to_table(dev, tunnel,
11278                                                        jump_group,
11279                                                        &table,
11280                                                        &grp_info, error);
11281                         if (ret)
11282                                 return ret;
11283                         tbl = flow_dv_tbl_resource_get(dev, table, attr->egress,
11284                                                        attr->transfer,
11285                                                        !!dev_flow->external,
11286                                                        tunnel, jump_group, 0,
11287                                                        error);
11288                         if (!tbl)
11289                                 return rte_flow_error_set
11290                                                 (error, errno,
11291                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11292                                                  NULL,
11293                                                  "cannot create jump action.");
11294                         if (flow_dv_jump_tbl_resource_register
11295                             (dev, tbl, dev_flow, error)) {
11296                                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
11297                                 return rte_flow_error_set
11298                                                 (error, errno,
11299                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11300                                                  NULL,
11301                                                  "cannot create jump action.");
11302                         }
11303                         dev_flow->dv.actions[actions_n++] =
11304                                         dev_flow->dv.jump->action;
11305                         action_flags |= MLX5_FLOW_ACTION_JUMP;
11306                         dev_flow->handle->fate_action = MLX5_FLOW_FATE_JUMP;
11307                         sample_act->action_flags |= MLX5_FLOW_ACTION_JUMP;
11308                         num_of_dest++;
11309                         break;
11310                 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC:
11311                 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST:
11312                         if (flow_dv_convert_action_modify_mac
11313                                         (mhdr_res, actions, error))
11314                                 return -rte_errno;
11315                         action_flags |= actions->type ==
11316                                         RTE_FLOW_ACTION_TYPE_SET_MAC_SRC ?
11317                                         MLX5_FLOW_ACTION_SET_MAC_SRC :
11318                                         MLX5_FLOW_ACTION_SET_MAC_DST;
11319                         break;
11320                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC:
11321                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST:
11322                         if (flow_dv_convert_action_modify_ipv4
11323                                         (mhdr_res, actions, error))
11324                                 return -rte_errno;
11325                         action_flags |= actions->type ==
11326                                         RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC ?
11327                                         MLX5_FLOW_ACTION_SET_IPV4_SRC :
11328                                         MLX5_FLOW_ACTION_SET_IPV4_DST;
11329                         break;
11330                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC:
11331                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST:
11332                         if (flow_dv_convert_action_modify_ipv6
11333                                         (mhdr_res, actions, error))
11334                                 return -rte_errno;
11335                         action_flags |= actions->type ==
11336                                         RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC ?
11337                                         MLX5_FLOW_ACTION_SET_IPV6_SRC :
11338                                         MLX5_FLOW_ACTION_SET_IPV6_DST;
11339                         break;
11340                 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC:
11341                 case RTE_FLOW_ACTION_TYPE_SET_TP_DST:
11342                         if (flow_dv_convert_action_modify_tp
11343                                         (mhdr_res, actions, items,
11344                                          &flow_attr, dev_flow, !!(action_flags &
11345                                          MLX5_FLOW_ACTION_DECAP), error))
11346                                 return -rte_errno;
11347                         action_flags |= actions->type ==
11348                                         RTE_FLOW_ACTION_TYPE_SET_TP_SRC ?
11349                                         MLX5_FLOW_ACTION_SET_TP_SRC :
11350                                         MLX5_FLOW_ACTION_SET_TP_DST;
11351                         break;
11352                 case RTE_FLOW_ACTION_TYPE_DEC_TTL:
11353                         if (flow_dv_convert_action_modify_dec_ttl
11354                                         (mhdr_res, items, &flow_attr, dev_flow,
11355                                          !!(action_flags &
11356                                          MLX5_FLOW_ACTION_DECAP), error))
11357                                 return -rte_errno;
11358                         action_flags |= MLX5_FLOW_ACTION_DEC_TTL;
11359                         break;
11360                 case RTE_FLOW_ACTION_TYPE_SET_TTL:
11361                         if (flow_dv_convert_action_modify_ttl
11362                                         (mhdr_res, actions, items, &flow_attr,
11363                                          dev_flow, !!(action_flags &
11364                                          MLX5_FLOW_ACTION_DECAP), error))
11365                                 return -rte_errno;
11366                         action_flags |= MLX5_FLOW_ACTION_SET_TTL;
11367                         break;
11368                 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ:
11369                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ:
11370                         if (flow_dv_convert_action_modify_tcp_seq
11371                                         (mhdr_res, actions, error))
11372                                 return -rte_errno;
11373                         action_flags |= actions->type ==
11374                                         RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ ?
11375                                         MLX5_FLOW_ACTION_INC_TCP_SEQ :
11376                                         MLX5_FLOW_ACTION_DEC_TCP_SEQ;
11377                         break;
11378
11379                 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK:
11380                 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK:
11381                         if (flow_dv_convert_action_modify_tcp_ack
11382                                         (mhdr_res, actions, error))
11383                                 return -rte_errno;
11384                         action_flags |= actions->type ==
11385                                         RTE_FLOW_ACTION_TYPE_INC_TCP_ACK ?
11386                                         MLX5_FLOW_ACTION_INC_TCP_ACK :
11387                                         MLX5_FLOW_ACTION_DEC_TCP_ACK;
11388                         break;
11389                 case MLX5_RTE_FLOW_ACTION_TYPE_TAG:
11390                         if (flow_dv_convert_action_set_reg
11391                                         (mhdr_res, actions, error))
11392                                 return -rte_errno;
11393                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11394                         break;
11395                 case MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG:
11396                         if (flow_dv_convert_action_copy_mreg
11397                                         (dev, mhdr_res, actions, error))
11398                                 return -rte_errno;
11399                         action_flags |= MLX5_FLOW_ACTION_SET_TAG;
11400                         break;
11401                 case MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS:
11402                         action_flags |= MLX5_FLOW_ACTION_DEFAULT_MISS;
11403                         dev_flow->handle->fate_action =
11404                                         MLX5_FLOW_FATE_DEFAULT_MISS;
11405                         break;
11406                 case RTE_FLOW_ACTION_TYPE_METER:
11407                         mtr = actions->conf;
11408                         if (!flow->meter) {
11409                                 fm = mlx5_flow_meter_attach(priv, mtr->mtr_id,
11410                                                             attr, error);
11411                                 if (!fm)
11412                                         return rte_flow_error_set(error,
11413                                                 rte_errno,
11414                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11415                                                 NULL,
11416                                                 "meter not found "
11417                                                 "or invalid parameters");
11418                                 flow->meter = fm->idx;
11419                         }
11420                         /* Set the meter action. */
11421                         if (!fm) {
11422                                 fm = mlx5_ipool_get(priv->sh->ipool
11423                                                 [MLX5_IPOOL_MTR], flow->meter);
11424                                 if (!fm)
11425                                         return rte_flow_error_set(error,
11426                                                 rte_errno,
11427                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11428                                                 NULL,
11429                                                 "meter not found "
11430                                                 "or invalid parameters");
11431                         }
11432                         dev_flow->dv.actions[actions_n++] =
11433                                 fm->mfts->meter_action;
11434                         action_flags |= MLX5_FLOW_ACTION_METER;
11435                         break;
11436                 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP:
11437                         if (flow_dv_convert_action_modify_ipv4_dscp(mhdr_res,
11438                                                               actions, error))
11439                                 return -rte_errno;
11440                         action_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;
11441                         break;
11442                 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:
11443                         if (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,
11444                                                               actions, error))
11445                                 return -rte_errno;
11446                         action_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;
11447                         break;
11448                 case RTE_FLOW_ACTION_TYPE_SAMPLE:
11449                         sample_act_pos = actions_n;
11450                         sample = (const struct rte_flow_action_sample *)
11451                                  action->conf;
11452                         actions_n++;
11453                         action_flags |= MLX5_FLOW_ACTION_SAMPLE;
11454                         /* put encap action into group if work with port id */
11455                         if ((action_flags & MLX5_FLOW_ACTION_ENCAP) &&
11456                             (action_flags & MLX5_FLOW_ACTION_PORT_ID))
11457                                 sample_act->action_flags |=
11458                                                         MLX5_FLOW_ACTION_ENCAP;
11459                         break;
11460                 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD:
11461                         if (flow_dv_convert_action_modify_field
11462                                         (dev, mhdr_res, actions, attr, error))
11463                                 return -rte_errno;
11464                         action_flags |= MLX5_FLOW_ACTION_MODIFY_FIELD;
11465                         break;
11466                 case RTE_FLOW_ACTION_TYPE_END:
11467                         actions_end = true;
11468                         if (mhdr_res->actions_num) {
11469                                 /* create modify action if needed. */
11470                                 if (flow_dv_modify_hdr_resource_register
11471                                         (dev, mhdr_res, dev_flow, error))
11472                                         return -rte_errno;
11473                                 dev_flow->dv.actions[modify_action_position] =
11474                                         handle->dvh.modify_hdr->action;
11475                         }
11476                         if (action_flags & MLX5_FLOW_ACTION_COUNT) {
11477                                 /*
11478                                  * Create one count action, to be used
11479                                  * by all sub-flows.
11480                                  */
11481                                 if (!flow->counter) {
11482                                         flow->counter =
11483                                                 flow_dv_translate_create_counter
11484                                                         (dev, dev_flow, count,
11485                                                          age);
11486                                         if (!flow->counter)
11487                                                 return rte_flow_error_set
11488                                                 (error, rte_errno,
11489                                                  RTE_FLOW_ERROR_TYPE_ACTION,
11490                                                  NULL, "cannot create counter"
11491                                                  " object.");
11492                                 }
11493                                 dev_flow->dv.actions[actions_n] =
11494                                           (flow_dv_counter_get_by_idx(dev,
11495                                           flow->counter, NULL))->action;
11496                                 actions_n++;
11497                         }
11498                 default:
11499                         break;
11500                 }
11501                 if (mhdr_res->actions_num &&
11502                     modify_action_position == UINT32_MAX)
11503                         modify_action_position = actions_n++;
11504         }
11505         for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {
11506                 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL);
11507                 int item_type = items->type;
11508
11509                 if (!mlx5_flow_os_item_supported(item_type))
11510                         return rte_flow_error_set(error, ENOTSUP,
11511                                                   RTE_FLOW_ERROR_TYPE_ITEM,
11512                                                   NULL, "item not supported");
11513                 switch (item_type) {
11514                 case RTE_FLOW_ITEM_TYPE_PORT_ID:
11515                         flow_dv_translate_item_port_id
11516                                 (dev, match_mask, match_value, items, attr);
11517                         last_item = MLX5_FLOW_ITEM_PORT_ID;
11518                         break;
11519                 case RTE_FLOW_ITEM_TYPE_ETH:
11520                         flow_dv_translate_item_eth(match_mask, match_value,
11521                                                    items, tunnel,
11522                                                    dev_flow->dv.group);
11523                         matcher.priority = action_flags &
11524                                         MLX5_FLOW_ACTION_DEFAULT_MISS &&
11525                                         !dev_flow->external ?
11526                                         MLX5_PRIORITY_MAP_L3 :
11527                                         MLX5_PRIORITY_MAP_L2;
11528                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L2 :
11529                                              MLX5_FLOW_LAYER_OUTER_L2;
11530                         break;
11531                 case RTE_FLOW_ITEM_TYPE_VLAN:
11532                         flow_dv_translate_item_vlan(dev_flow,
11533                                                     match_mask, match_value,
11534                                                     items, tunnel,
11535                                                     dev_flow->dv.group);
11536                         matcher.priority = MLX5_PRIORITY_MAP_L2;
11537                         last_item = tunnel ? (MLX5_FLOW_LAYER_INNER_L2 |
11538                                               MLX5_FLOW_LAYER_INNER_VLAN) :
11539                                              (MLX5_FLOW_LAYER_OUTER_L2 |
11540                                               MLX5_FLOW_LAYER_OUTER_VLAN);
11541                         break;
11542                 case RTE_FLOW_ITEM_TYPE_IPV4:
11543                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11544                                                   &item_flags, &tunnel);
11545                         flow_dv_translate_item_ipv4(match_mask, match_value,
11546                                                     items, tunnel,
11547                                                     dev_flow->dv.group);
11548                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11549                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 :
11550                                              MLX5_FLOW_LAYER_OUTER_L3_IPV4;
11551                         if (items->mask != NULL &&
11552                             ((const struct rte_flow_item_ipv4 *)
11553                              items->mask)->hdr.next_proto_id) {
11554                                 next_protocol =
11555                                         ((const struct rte_flow_item_ipv4 *)
11556                                          (items->spec))->hdr.next_proto_id;
11557                                 next_protocol &=
11558                                         ((const struct rte_flow_item_ipv4 *)
11559                                          (items->mask))->hdr.next_proto_id;
11560                         } else {
11561                                 /* Reset for inner layer. */
11562                                 next_protocol = 0xff;
11563                         }
11564                         break;
11565                 case RTE_FLOW_ITEM_TYPE_IPV6:
11566                         mlx5_flow_tunnel_ip_check(items, next_protocol,
11567                                                   &item_flags, &tunnel);
11568                         flow_dv_translate_item_ipv6(match_mask, match_value,
11569                                                     items, tunnel,
11570                                                     dev_flow->dv.group);
11571                         matcher.priority = MLX5_PRIORITY_MAP_L3;
11572                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 :
11573                                              MLX5_FLOW_LAYER_OUTER_L3_IPV6;
11574                         if (items->mask != NULL &&
11575                             ((const struct rte_flow_item_ipv6 *)
11576                              items->mask)->hdr.proto) {
11577                                 next_protocol =
11578                                         ((const struct rte_flow_item_ipv6 *)
11579                                          items->spec)->hdr.proto;
11580                                 next_protocol &=
11581                                         ((const struct rte_flow_item_ipv6 *)
11582                                          items->mask)->hdr.proto;
11583                         } else {
11584                                 /* Reset for inner layer. */
11585                                 next_protocol = 0xff;
11586                         }
11587                         break;
11588                 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT:
11589                         flow_dv_translate_item_ipv6_frag_ext(match_mask,
11590                                                              match_value,
11591                                                              items, tunnel);
11592                         last_item = tunnel ?
11593                                         MLX5_FLOW_LAYER_INNER_L3_IPV6_FRAG_EXT :
11594                                         MLX5_FLOW_LAYER_OUTER_L3_IPV6_FRAG_EXT;
11595                         if (items->mask != NULL &&
11596                             ((const struct rte_flow_item_ipv6_frag_ext *)
11597                              items->mask)->hdr.next_header) {
11598                                 next_protocol =
11599                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11600                                  items->spec)->hdr.next_header;
11601                                 next_protocol &=
11602                                 ((const struct rte_flow_item_ipv6_frag_ext *)
11603                                  items->mask)->hdr.next_header;
11604                         } else {
11605                                 /* Reset for inner layer. */
11606                                 next_protocol = 0xff;
11607                         }
11608                         break;
11609                 case RTE_FLOW_ITEM_TYPE_TCP:
11610                         flow_dv_translate_item_tcp(match_mask, match_value,
11611                                                    items, tunnel);
11612                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11613                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_TCP :
11614                                              MLX5_FLOW_LAYER_OUTER_L4_TCP;
11615                         break;
11616                 case RTE_FLOW_ITEM_TYPE_UDP:
11617                         flow_dv_translate_item_udp(match_mask, match_value,
11618                                                    items, tunnel);
11619                         matcher.priority = MLX5_PRIORITY_MAP_L4;
11620                         last_item = tunnel ? MLX5_FLOW_LAYER_INNER_L4_UDP :
11621                                              MLX5_FLOW_LAYER_OUTER_L4_UDP;
11622                         break;
11623                 case RTE_FLOW_ITEM_TYPE_GRE:
11624                         flow_dv_translate_item_gre(match_mask, match_value,
11625                                                    items, tunnel);
11626                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11627                         last_item = MLX5_FLOW_LAYER_GRE;
11628                         break;
11629                 case RTE_FLOW_ITEM_TYPE_GRE_KEY:
11630                         flow_dv_translate_item_gre_key(match_mask,
11631                                                        match_value, items);
11632                         last_item = MLX5_FLOW_LAYER_GRE_KEY;
11633                         break;
11634                 case RTE_FLOW_ITEM_TYPE_NVGRE:
11635                         flow_dv_translate_item_nvgre(match_mask, match_value,
11636                                                      items, tunnel);
11637                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11638                         last_item = MLX5_FLOW_LAYER_GRE;
11639                         break;
11640                 case RTE_FLOW_ITEM_TYPE_VXLAN:
11641                         flow_dv_translate_item_vxlan(match_mask, match_value,
11642                                                      items, tunnel);
11643                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11644                         last_item = MLX5_FLOW_LAYER_VXLAN;
11645                         break;
11646                 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE:
11647                         flow_dv_translate_item_vxlan_gpe(match_mask,
11648                                                          match_value, items,
11649                                                          tunnel);
11650                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11651                         last_item = MLX5_FLOW_LAYER_VXLAN_GPE;
11652                         break;
11653                 case RTE_FLOW_ITEM_TYPE_GENEVE:
11654                         flow_dv_translate_item_geneve(match_mask, match_value,
11655                                                       items, tunnel);
11656                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11657                         last_item = MLX5_FLOW_LAYER_GENEVE;
11658                         break;
11659                 case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
11660                         ret = flow_dv_translate_item_geneve_opt(dev, match_mask,
11661                                                           match_value,
11662                                                           items, error);
11663                         if (ret)
11664                                 return rte_flow_error_set(error, -ret,
11665                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11666                                         "cannot create GENEVE TLV option");
11667                         flow->geneve_tlv_option = 1;
11668                         last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
11669                         break;
11670                 case RTE_FLOW_ITEM_TYPE_MPLS:
11671                         flow_dv_translate_item_mpls(match_mask, match_value,
11672                                                     items, last_item, tunnel);
11673                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11674                         last_item = MLX5_FLOW_LAYER_MPLS;
11675                         break;
11676                 case RTE_FLOW_ITEM_TYPE_MARK:
11677                         flow_dv_translate_item_mark(dev, match_mask,
11678                                                     match_value, items);
11679                         last_item = MLX5_FLOW_ITEM_MARK;
11680                         break;
11681                 case RTE_FLOW_ITEM_TYPE_META:
11682                         flow_dv_translate_item_meta(dev, match_mask,
11683                                                     match_value, attr, items);
11684                         last_item = MLX5_FLOW_ITEM_METADATA;
11685                         break;
11686                 case RTE_FLOW_ITEM_TYPE_ICMP:
11687                         flow_dv_translate_item_icmp(match_mask, match_value,
11688                                                     items, tunnel);
11689                         last_item = MLX5_FLOW_LAYER_ICMP;
11690                         break;
11691                 case RTE_FLOW_ITEM_TYPE_ICMP6:
11692                         flow_dv_translate_item_icmp6(match_mask, match_value,
11693                                                       items, tunnel);
11694                         last_item = MLX5_FLOW_LAYER_ICMP6;
11695                         break;
11696                 case RTE_FLOW_ITEM_TYPE_TAG:
11697                         flow_dv_translate_item_tag(dev, match_mask,
11698                                                    match_value, items);
11699                         last_item = MLX5_FLOW_ITEM_TAG;
11700                         break;
11701                 case MLX5_RTE_FLOW_ITEM_TYPE_TAG:
11702                         flow_dv_translate_mlx5_item_tag(dev, match_mask,
11703                                                         match_value, items);
11704                         last_item = MLX5_FLOW_ITEM_TAG;
11705                         break;
11706                 case MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:
11707                         flow_dv_translate_item_tx_queue(dev, match_mask,
11708                                                         match_value,
11709                                                         items);
11710                         last_item = MLX5_FLOW_ITEM_TX_QUEUE;
11711                         break;
11712                 case RTE_FLOW_ITEM_TYPE_GTP:
11713                         flow_dv_translate_item_gtp(match_mask, match_value,
11714                                                    items, tunnel);
11715                         matcher.priority = MLX5_TUNNEL_PRIO_GET(rss_desc);
11716                         last_item = MLX5_FLOW_LAYER_GTP;
11717                         break;
11718                 case RTE_FLOW_ITEM_TYPE_GTP_PSC:
11719                         ret = flow_dv_translate_item_gtp_psc(match_mask,
11720                                                           match_value,
11721                                                           items);
11722                         if (ret)
11723                                 return rte_flow_error_set(error, -ret,
11724                                         RTE_FLOW_ERROR_TYPE_ITEM, NULL,
11725                                         "cannot create GTP PSC item");
11726                         last_item = MLX5_FLOW_LAYER_GTP_PSC;
11727                         break;
11728                 case RTE_FLOW_ITEM_TYPE_ECPRI:
11729                         if (!mlx5_flex_parser_ecpri_exist(dev)) {
11730                                 /* Create it only the first time to be used. */
11731                                 ret = mlx5_flex_parser_ecpri_alloc(dev);
11732                                 if (ret)
11733                                         return rte_flow_error_set
11734                                                 (error, -ret,
11735                                                 RTE_FLOW_ERROR_TYPE_ITEM,
11736                                                 NULL,
11737                                                 "cannot create eCPRI parser");
11738                         }
11739                         /* Adjust the length matcher and device flow value. */
11740                         matcher.mask.size = MLX5_ST_SZ_BYTES(fte_match_param);
11741                         dev_flow->dv.value.size =
11742                                         MLX5_ST_SZ_BYTES(fte_match_param);
11743                         flow_dv_translate_item_ecpri(dev, match_mask,
11744                                                      match_value, items);
11745                         /* No other protocol should follow eCPRI layer. */
11746                         last_item = MLX5_FLOW_LAYER_ECPRI;
11747                         break;
11748                 default:
11749                         break;
11750                 }
11751                 item_flags |= last_item;
11752         }
11753         /*
11754          * When E-Switch mode is enabled, we have two cases where we need to
11755          * set the source port manually.
11756          * The first one, is in case of Nic steering rule, and the second is
11757          * E-Switch rule where no port_id item was found. In both cases
11758          * the source port is set according the current port in use.
11759          */
11760         if (!(item_flags & MLX5_FLOW_ITEM_PORT_ID) &&
11761             (priv->representor || priv->master)) {
11762                 if (flow_dv_translate_item_port_id(dev, match_mask,
11763                                                    match_value, NULL, attr))
11764                         return -rte_errno;
11765         }
11766 #ifdef RTE_LIBRTE_MLX5_DEBUG
11767         MLX5_ASSERT(!flow_dv_check_valid_spec(matcher.mask.buf,
11768                                               dev_flow->dv.value.buf));
11769 #endif
11770         /*
11771          * Layers may be already initialized from prefix flow if this dev_flow
11772          * is the suffix flow.
11773          */
11774         handle->layers |= item_flags;
11775         if (action_flags & MLX5_FLOW_ACTION_RSS)
11776                 flow_dv_hashfields_set(dev_flow, rss_desc);
11777         /* If has RSS action in the sample action, the Sample/Mirror resource
11778          * should be registered after the hash filed be update.
11779          */
11780         if (action_flags & MLX5_FLOW_ACTION_SAMPLE) {
11781                 ret = flow_dv_translate_action_sample(dev,
11782                                                       sample,
11783                                                       dev_flow, attr,
11784                                                       &num_of_dest,
11785                                                       sample_actions,
11786                                                       &sample_res,
11787                                                       error);
11788                 if (ret < 0)
11789                         return ret;
11790                 ret = flow_dv_create_action_sample(dev,
11791                                                    dev_flow,
11792                                                    num_of_dest,
11793                                                    &sample_res,
11794                                                    &mdest_res,
11795                                                    sample_actions,
11796                                                    action_flags,
11797                                                    error);
11798                 if (ret < 0)
11799                         return rte_flow_error_set
11800                                                 (error, rte_errno,
11801                                                 RTE_FLOW_ERROR_TYPE_ACTION,
11802                                                 NULL,
11803                                                 "cannot create sample action");
11804                 if (num_of_dest > 1) {
11805                         dev_flow->dv.actions[sample_act_pos] =
11806                         dev_flow->dv.dest_array_res->action;
11807                 } else {
11808                         dev_flow->dv.actions[sample_act_pos] =
11809                         dev_flow->dv.sample_res->verbs_action;
11810                 }
11811         }
11812         /*
11813          * For multiple destination (sample action with ratio=1), the encap
11814          * action and port id action will be combined into group action.
11815          * So need remove the original these actions in the flow and only
11816          * use the sample action instead of.
11817          */
11818         if (num_of_dest > 1 &&
11819             (sample_act->dr_port_id_action || sample_act->dr_jump_action)) {
11820                 int i;
11821                 void *temp_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS] = {0};
11822
11823                 for (i = 0; i < actions_n; i++) {
11824                         if ((sample_act->dr_encap_action &&
11825                                 sample_act->dr_encap_action ==
11826                                 dev_flow->dv.actions[i]) ||
11827                                 (sample_act->dr_port_id_action &&
11828                                 sample_act->dr_port_id_action ==
11829                                 dev_flow->dv.actions[i]) ||
11830                                 (sample_act->dr_jump_action &&
11831                                 sample_act->dr_jump_action ==
11832                                 dev_flow->dv.actions[i]))
11833                                 continue;
11834                         temp_actions[tmp_actions_n++] = dev_flow->dv.actions[i];
11835                 }
11836                 memcpy((void *)dev_flow->dv.actions,
11837                                 (void *)temp_actions,
11838                                 tmp_actions_n * sizeof(void *));
11839                 actions_n = tmp_actions_n;
11840         }
11841         dev_flow->dv.actions_n = actions_n;
11842         dev_flow->act_flags = action_flags;
11843         /* Register matcher. */
11844         matcher.crc = rte_raw_cksum((const void *)matcher.mask.buf,
11845                                     matcher.mask.size);
11846         matcher.priority = mlx5_get_matcher_priority(dev, attr,
11847                                         matcher.priority);
11848         /* reserved field no needs to be set to 0 here. */
11849         tbl_key.domain = attr->transfer;
11850         tbl_key.direction = attr->egress;
11851         tbl_key.table_id = dev_flow->dv.group;
11852         if (flow_dv_matcher_register(dev, &matcher, &tbl_key, dev_flow,
11853                                      tunnel, attr->group, error))
11854                 return -rte_errno;
11855         return 0;
11856 }
11857
11858 /**
11859  * Set hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11860  * and tunnel.
11861  *
11862  * @param[in, out] action
11863  *   Shred RSS action holding hash RX queue objects.
11864  * @param[in] hash_fields
11865  *   Defines combination of packet fields to participate in RX hash.
11866  * @param[in] tunnel
11867  *   Tunnel type
11868  * @param[in] hrxq_idx
11869  *   Hash RX queue index to set.
11870  *
11871  * @return
11872  *   0 on success, otherwise negative errno value.
11873  */
11874 static int
11875 __flow_dv_action_rss_hrxq_set(struct mlx5_shared_action_rss *action,
11876                               const uint64_t hash_fields,
11877                               const int tunnel,
11878                               uint32_t hrxq_idx)
11879 {
11880         uint32_t *hrxqs = tunnel ? action->hrxq : action->hrxq_tunnel;
11881
11882         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11883         case MLX5_RSS_HASH_IPV4:
11884                 hrxqs[0] = hrxq_idx;
11885                 return 0;
11886         case MLX5_RSS_HASH_IPV4_TCP:
11887                 hrxqs[1] = hrxq_idx;
11888                 return 0;
11889         case MLX5_RSS_HASH_IPV4_UDP:
11890                 hrxqs[2] = hrxq_idx;
11891                 return 0;
11892         case MLX5_RSS_HASH_IPV6:
11893                 hrxqs[3] = hrxq_idx;
11894                 return 0;
11895         case MLX5_RSS_HASH_IPV6_TCP:
11896                 hrxqs[4] = hrxq_idx;
11897                 return 0;
11898         case MLX5_RSS_HASH_IPV6_UDP:
11899                 hrxqs[5] = hrxq_idx;
11900                 return 0;
11901         case MLX5_RSS_HASH_NONE:
11902                 hrxqs[6] = hrxq_idx;
11903                 return 0;
11904         default:
11905                 return -1;
11906         }
11907 }
11908
11909 /**
11910  * Look up for hash RX queue by hash fields (see enum ibv_rx_hash_fields)
11911  * and tunnel.
11912  *
11913  * @param[in] dev
11914  *   Pointer to the Ethernet device structure.
11915  * @param[in] idx
11916  *   Shared RSS action ID holding hash RX queue objects.
11917  * @param[in] hash_fields
11918  *   Defines combination of packet fields to participate in RX hash.
11919  * @param[in] tunnel
11920  *   Tunnel type
11921  *
11922  * @return
11923  *   Valid hash RX queue index, otherwise 0.
11924  */
11925 static uint32_t
11926 __flow_dv_action_rss_hrxq_lookup(struct rte_eth_dev *dev, uint32_t idx,
11927                                  const uint64_t hash_fields,
11928                                  const int tunnel)
11929 {
11930         struct mlx5_priv *priv = dev->data->dev_private;
11931         struct mlx5_shared_action_rss *shared_rss =
11932             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
11933         const uint32_t *hrxqs = tunnel ? shared_rss->hrxq :
11934                                                         shared_rss->hrxq_tunnel;
11935
11936         switch (hash_fields & ~IBV_RX_HASH_INNER) {
11937         case MLX5_RSS_HASH_IPV4:
11938                 return hrxqs[0];
11939         case MLX5_RSS_HASH_IPV4_TCP:
11940                 return hrxqs[1];
11941         case MLX5_RSS_HASH_IPV4_UDP:
11942                 return hrxqs[2];
11943         case MLX5_RSS_HASH_IPV6:
11944                 return hrxqs[3];
11945         case MLX5_RSS_HASH_IPV6_TCP:
11946                 return hrxqs[4];
11947         case MLX5_RSS_HASH_IPV6_UDP:
11948                 return hrxqs[5];
11949         case MLX5_RSS_HASH_NONE:
11950                 return hrxqs[6];
11951         default:
11952                 return 0;
11953         }
11954 }
11955
11956 /**
11957  * Apply the flow to the NIC, lock free,
11958  * (mutex should be acquired by caller).
11959  *
11960  * @param[in] dev
11961  *   Pointer to the Ethernet device structure.
11962  * @param[in, out] flow
11963  *   Pointer to flow structure.
11964  * @param[out] error
11965  *   Pointer to error structure.
11966  *
11967  * @return
11968  *   0 on success, a negative errno value otherwise and rte_errno is set.
11969  */
11970 static int
11971 flow_dv_apply(struct rte_eth_dev *dev, struct rte_flow *flow,
11972               struct rte_flow_error *error)
11973 {
11974         struct mlx5_flow_dv_workspace *dv;
11975         struct mlx5_flow_handle *dh;
11976         struct mlx5_flow_handle_dv *dv_h;
11977         struct mlx5_flow *dev_flow;
11978         struct mlx5_priv *priv = dev->data->dev_private;
11979         uint32_t handle_idx;
11980         int n;
11981         int err;
11982         int idx;
11983         struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace();
11984         struct mlx5_flow_rss_desc *rss_desc = &wks->rss_desc;
11985
11986         MLX5_ASSERT(wks);
11987         for (idx = wks->flow_idx - 1; idx >= 0; idx--) {
11988                 dev_flow = &wks->flows[idx];
11989                 dv = &dev_flow->dv;
11990                 dh = dev_flow->handle;
11991                 dv_h = &dh->dvh;
11992                 n = dv->actions_n;
11993                 if (dh->fate_action == MLX5_FLOW_FATE_DROP) {
11994                         if (dv->transfer) {
11995                                 dv->actions[n++] = priv->sh->esw_drop_action;
11996                         } else {
11997                                 MLX5_ASSERT(priv->drop_queue.hrxq);
11998                                 dv->actions[n++] =
11999                                                 priv->drop_queue.hrxq->action;
12000                         }
12001                 } else if ((dh->fate_action == MLX5_FLOW_FATE_QUEUE &&
12002                            !dv_h->rix_sample && !dv_h->rix_dest_array)) {
12003                         struct mlx5_hrxq *hrxq;
12004                         uint32_t hrxq_idx;
12005
12006                         hrxq = flow_dv_hrxq_prepare(dev, dev_flow, rss_desc,
12007                                                     &hrxq_idx);
12008                         if (!hrxq) {
12009                                 rte_flow_error_set
12010                                         (error, rte_errno,
12011                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12012                                          "cannot get hash queue");
12013                                 goto error;
12014                         }
12015                         dh->rix_hrxq = hrxq_idx;
12016                         dv->actions[n++] = hrxq->action;
12017                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12018                         struct mlx5_hrxq *hrxq = NULL;
12019                         uint32_t hrxq_idx;
12020
12021                         hrxq_idx = __flow_dv_action_rss_hrxq_lookup(dev,
12022                                                 rss_desc->shared_rss,
12023                                                 dev_flow->hash_fields,
12024                                                 !!(dh->layers &
12025                                                 MLX5_FLOW_LAYER_TUNNEL));
12026                         if (hrxq_idx)
12027                                 hrxq = mlx5_ipool_get
12028                                         (priv->sh->ipool[MLX5_IPOOL_HRXQ],
12029                                          hrxq_idx);
12030                         if (!hrxq) {
12031                                 rte_flow_error_set
12032                                         (error, rte_errno,
12033                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12034                                          "cannot get hash queue");
12035                                 goto error;
12036                         }
12037                         dh->rix_srss = rss_desc->shared_rss;
12038                         dv->actions[n++] = hrxq->action;
12039                 } else if (dh->fate_action == MLX5_FLOW_FATE_DEFAULT_MISS) {
12040                         if (!priv->sh->default_miss_action) {
12041                                 rte_flow_error_set
12042                                         (error, rte_errno,
12043                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12044                                          "default miss action not be created.");
12045                                 goto error;
12046                         }
12047                         dv->actions[n++] = priv->sh->default_miss_action;
12048                 }
12049                 err = mlx5_flow_os_create_flow(dv_h->matcher->matcher_object,
12050                                                (void *)&dv->value, n,
12051                                                dv->actions, &dh->drv_flow);
12052                 if (err) {
12053                         rte_flow_error_set(error, errno,
12054                                            RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
12055                                            NULL,
12056                                            "hardware refuses to create flow");
12057                         goto error;
12058                 }
12059                 if (priv->vmwa_context &&
12060                     dh->vf_vlan.tag && !dh->vf_vlan.created) {
12061                         /*
12062                          * The rule contains the VLAN pattern.
12063                          * For VF we are going to create VLAN
12064                          * interface to make hypervisor set correct
12065                          * e-Switch vport context.
12066                          */
12067                         mlx5_vlan_vmwa_acquire(dev, &dh->vf_vlan);
12068                 }
12069         }
12070         return 0;
12071 error:
12072         err = rte_errno; /* Save rte_errno before cleanup. */
12073         SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles,
12074                        handle_idx, dh, next) {
12075                 /* hrxq is union, don't clear it if the flag is not set. */
12076                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE && dh->rix_hrxq) {
12077                         mlx5_hrxq_release(dev, dh->rix_hrxq);
12078                         dh->rix_hrxq = 0;
12079                 } else if (dh->fate_action == MLX5_FLOW_FATE_SHARED_RSS) {
12080                         dh->rix_srss = 0;
12081                 }
12082                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12083                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12084         }
12085         rte_errno = err; /* Restore rte_errno. */
12086         return -rte_errno;
12087 }
12088
12089 void
12090 flow_dv_matcher_remove_cb(struct mlx5_cache_list *list __rte_unused,
12091                           struct mlx5_cache_entry *entry)
12092 {
12093         struct mlx5_flow_dv_matcher *cache = container_of(entry, typeof(*cache),
12094                                                           entry);
12095
12096         claim_zero(mlx5_flow_os_destroy_flow_matcher(cache->matcher_object));
12097         mlx5_free(cache);
12098 }
12099
12100 /**
12101  * Release the flow matcher.
12102  *
12103  * @param dev
12104  *   Pointer to Ethernet device.
12105  * @param port_id
12106  *   Index to port ID action resource.
12107  *
12108  * @return
12109  *   1 while a reference on it exists, 0 when freed.
12110  */
12111 static int
12112 flow_dv_matcher_release(struct rte_eth_dev *dev,
12113                         struct mlx5_flow_handle *handle)
12114 {
12115         struct mlx5_flow_dv_matcher *matcher = handle->dvh.matcher;
12116         struct mlx5_flow_tbl_data_entry *tbl = container_of(matcher->tbl,
12117                                                             typeof(*tbl), tbl);
12118         int ret;
12119
12120         MLX5_ASSERT(matcher->matcher_object);
12121         ret = mlx5_cache_unregister(&tbl->matchers, &matcher->entry);
12122         flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl->tbl);
12123         return ret;
12124 }
12125
12126 /**
12127  * Release encap_decap resource.
12128  *
12129  * @param list
12130  *   Pointer to the hash list.
12131  * @param entry
12132  *   Pointer to exist resource entry object.
12133  */
12134 void
12135 flow_dv_encap_decap_remove_cb(struct mlx5_hlist *list,
12136                               struct mlx5_hlist_entry *entry)
12137 {
12138         struct mlx5_dev_ctx_shared *sh = list->ctx;
12139         struct mlx5_flow_dv_encap_decap_resource *res =
12140                 container_of(entry, typeof(*res), entry);
12141
12142         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12143         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_DECAP_ENCAP], res->idx);
12144 }
12145
12146 /**
12147  * Release an encap/decap resource.
12148  *
12149  * @param dev
12150  *   Pointer to Ethernet device.
12151  * @param encap_decap_idx
12152  *   Index of encap decap resource.
12153  *
12154  * @return
12155  *   1 while a reference on it exists, 0 when freed.
12156  */
12157 static int
12158 flow_dv_encap_decap_resource_release(struct rte_eth_dev *dev,
12159                                      uint32_t encap_decap_idx)
12160 {
12161         struct mlx5_priv *priv = dev->data->dev_private;
12162         struct mlx5_flow_dv_encap_decap_resource *cache_resource;
12163
12164         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DECAP_ENCAP],
12165                                         encap_decap_idx);
12166         if (!cache_resource)
12167                 return 0;
12168         MLX5_ASSERT(cache_resource->action);
12169         return mlx5_hlist_unregister(priv->sh->encaps_decaps,
12170                                      &cache_resource->entry);
12171 }
12172
12173 /**
12174  * Release an jump to table action resource.
12175  *
12176  * @param dev
12177  *   Pointer to Ethernet device.
12178  * @param rix_jump
12179  *   Index to the jump action resource.
12180  *
12181  * @return
12182  *   1 while a reference on it exists, 0 when freed.
12183  */
12184 static int
12185 flow_dv_jump_tbl_resource_release(struct rte_eth_dev *dev,
12186                                   uint32_t rix_jump)
12187 {
12188         struct mlx5_priv *priv = dev->data->dev_private;
12189         struct mlx5_flow_tbl_data_entry *tbl_data;
12190
12191         tbl_data = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_JUMP],
12192                                   rix_jump);
12193         if (!tbl_data)
12194                 return 0;
12195         return flow_dv_tbl_resource_release(MLX5_SH(dev), &tbl_data->tbl);
12196 }
12197
12198 void
12199 flow_dv_modify_remove_cb(struct mlx5_hlist *list __rte_unused,
12200                          struct mlx5_hlist_entry *entry)
12201 {
12202         struct mlx5_flow_dv_modify_hdr_resource *res =
12203                 container_of(entry, typeof(*res), entry);
12204
12205         claim_zero(mlx5_flow_os_destroy_flow_action(res->action));
12206         mlx5_free(entry);
12207 }
12208
12209 /**
12210  * Release a modify-header resource.
12211  *
12212  * @param dev
12213  *   Pointer to Ethernet device.
12214  * @param handle
12215  *   Pointer to mlx5_flow_handle.
12216  *
12217  * @return
12218  *   1 while a reference on it exists, 0 when freed.
12219  */
12220 static int
12221 flow_dv_modify_hdr_resource_release(struct rte_eth_dev *dev,
12222                                     struct mlx5_flow_handle *handle)
12223 {
12224         struct mlx5_priv *priv = dev->data->dev_private;
12225         struct mlx5_flow_dv_modify_hdr_resource *entry = handle->dvh.modify_hdr;
12226
12227         MLX5_ASSERT(entry->action);
12228         return mlx5_hlist_unregister(priv->sh->modify_cmds, &entry->entry);
12229 }
12230
12231 void
12232 flow_dv_port_id_remove_cb(struct mlx5_cache_list *list,
12233                           struct mlx5_cache_entry *entry)
12234 {
12235         struct mlx5_dev_ctx_shared *sh = list->ctx;
12236         struct mlx5_flow_dv_port_id_action_resource *cache =
12237                         container_of(entry, typeof(*cache), entry);
12238
12239         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12240         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PORT_ID], cache->idx);
12241 }
12242
12243 /**
12244  * Release port ID action resource.
12245  *
12246  * @param dev
12247  *   Pointer to Ethernet device.
12248  * @param handle
12249  *   Pointer to mlx5_flow_handle.
12250  *
12251  * @return
12252  *   1 while a reference on it exists, 0 when freed.
12253  */
12254 static int
12255 flow_dv_port_id_action_resource_release(struct rte_eth_dev *dev,
12256                                         uint32_t port_id)
12257 {
12258         struct mlx5_priv *priv = dev->data->dev_private;
12259         struct mlx5_flow_dv_port_id_action_resource *cache;
12260
12261         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PORT_ID], port_id);
12262         if (!cache)
12263                 return 0;
12264         MLX5_ASSERT(cache->action);
12265         return mlx5_cache_unregister(&priv->sh->port_id_action_list,
12266                                      &cache->entry);
12267 }
12268
12269 /**
12270  * Release shared RSS action resource.
12271  *
12272  * @param dev
12273  *   Pointer to Ethernet device.
12274  * @param srss
12275  *   Shared RSS action index.
12276  */
12277 static void
12278 flow_dv_shared_rss_action_release(struct rte_eth_dev *dev, uint32_t srss)
12279 {
12280         struct mlx5_priv *priv = dev->data->dev_private;
12281         struct mlx5_shared_action_rss *shared_rss;
12282
12283         shared_rss = mlx5_ipool_get
12284                         (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], srss);
12285         __atomic_sub_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12286 }
12287
12288 void
12289 flow_dv_push_vlan_remove_cb(struct mlx5_cache_list *list,
12290                             struct mlx5_cache_entry *entry)
12291 {
12292         struct mlx5_dev_ctx_shared *sh = list->ctx;
12293         struct mlx5_flow_dv_push_vlan_action_resource *cache =
12294                         container_of(entry, typeof(*cache), entry);
12295
12296         claim_zero(mlx5_flow_os_destroy_flow_action(cache->action));
12297         mlx5_ipool_free(sh->ipool[MLX5_IPOOL_PUSH_VLAN], cache->idx);
12298 }
12299
12300 /**
12301  * Release push vlan action resource.
12302  *
12303  * @param dev
12304  *   Pointer to Ethernet device.
12305  * @param handle
12306  *   Pointer to mlx5_flow_handle.
12307  *
12308  * @return
12309  *   1 while a reference on it exists, 0 when freed.
12310  */
12311 static int
12312 flow_dv_push_vlan_action_resource_release(struct rte_eth_dev *dev,
12313                                           struct mlx5_flow_handle *handle)
12314 {
12315         struct mlx5_priv *priv = dev->data->dev_private;
12316         struct mlx5_flow_dv_push_vlan_action_resource *cache;
12317         uint32_t idx = handle->dvh.rix_push_vlan;
12318
12319         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_PUSH_VLAN], idx);
12320         if (!cache)
12321                 return 0;
12322         MLX5_ASSERT(cache->action);
12323         return mlx5_cache_unregister(&priv->sh->push_vlan_action_list,
12324                                      &cache->entry);
12325 }
12326
12327 /**
12328  * Release the fate resource.
12329  *
12330  * @param dev
12331  *   Pointer to Ethernet device.
12332  * @param handle
12333  *   Pointer to mlx5_flow_handle.
12334  */
12335 static void
12336 flow_dv_fate_resource_release(struct rte_eth_dev *dev,
12337                                struct mlx5_flow_handle *handle)
12338 {
12339         if (!handle->rix_fate)
12340                 return;
12341         switch (handle->fate_action) {
12342         case MLX5_FLOW_FATE_QUEUE:
12343                 mlx5_hrxq_release(dev, handle->rix_hrxq);
12344                 break;
12345         case MLX5_FLOW_FATE_JUMP:
12346                 flow_dv_jump_tbl_resource_release(dev, handle->rix_jump);
12347                 break;
12348         case MLX5_FLOW_FATE_PORT_ID:
12349                 flow_dv_port_id_action_resource_release(dev,
12350                                 handle->rix_port_id_action);
12351                 break;
12352         default:
12353                 DRV_LOG(DEBUG, "Incorrect fate action:%d", handle->fate_action);
12354                 break;
12355         }
12356         handle->rix_fate = 0;
12357 }
12358
12359 void
12360 flow_dv_sample_remove_cb(struct mlx5_cache_list *list __rte_unused,
12361                          struct mlx5_cache_entry *entry)
12362 {
12363         struct mlx5_flow_dv_sample_resource *cache_resource =
12364                         container_of(entry, typeof(*cache_resource), entry);
12365         struct rte_eth_dev *dev = cache_resource->dev;
12366         struct mlx5_priv *priv = dev->data->dev_private;
12367
12368         if (cache_resource->verbs_action)
12369                 claim_zero(mlx5_flow_os_destroy_flow_action
12370                                 (cache_resource->verbs_action));
12371         if (cache_resource->normal_path_tbl)
12372                 flow_dv_tbl_resource_release(MLX5_SH(dev),
12373                         cache_resource->normal_path_tbl);
12374         flow_dv_sample_sub_actions_release(dev,
12375                                 &cache_resource->sample_idx);
12376         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12377                         cache_resource->idx);
12378         DRV_LOG(DEBUG, "sample resource %p: removed",
12379                 (void *)cache_resource);
12380 }
12381
12382 /**
12383  * Release an sample resource.
12384  *
12385  * @param dev
12386  *   Pointer to Ethernet device.
12387  * @param handle
12388  *   Pointer to mlx5_flow_handle.
12389  *
12390  * @return
12391  *   1 while a reference on it exists, 0 when freed.
12392  */
12393 static int
12394 flow_dv_sample_resource_release(struct rte_eth_dev *dev,
12395                                      struct mlx5_flow_handle *handle)
12396 {
12397         struct mlx5_priv *priv = dev->data->dev_private;
12398         struct mlx5_flow_dv_sample_resource *cache_resource;
12399
12400         cache_resource = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_SAMPLE],
12401                          handle->dvh.rix_sample);
12402         if (!cache_resource)
12403                 return 0;
12404         MLX5_ASSERT(cache_resource->verbs_action);
12405         return mlx5_cache_unregister(&priv->sh->sample_action_list,
12406                                      &cache_resource->entry);
12407 }
12408
12409 void
12410 flow_dv_dest_array_remove_cb(struct mlx5_cache_list *list __rte_unused,
12411                              struct mlx5_cache_entry *entry)
12412 {
12413         struct mlx5_flow_dv_dest_array_resource *cache_resource =
12414                         container_of(entry, typeof(*cache_resource), entry);
12415         struct rte_eth_dev *dev = cache_resource->dev;
12416         struct mlx5_priv *priv = dev->data->dev_private;
12417         uint32_t i = 0;
12418
12419         MLX5_ASSERT(cache_resource->action);
12420         if (cache_resource->action)
12421                 claim_zero(mlx5_flow_os_destroy_flow_action
12422                                         (cache_resource->action));
12423         for (; i < cache_resource->num_of_dest; i++)
12424                 flow_dv_sample_sub_actions_release(dev,
12425                                 &cache_resource->sample_idx[i]);
12426         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12427                         cache_resource->idx);
12428         DRV_LOG(DEBUG, "destination array resource %p: removed",
12429                 (void *)cache_resource);
12430 }
12431
12432 /**
12433  * Release an destination array resource.
12434  *
12435  * @param dev
12436  *   Pointer to Ethernet device.
12437  * @param handle
12438  *   Pointer to mlx5_flow_handle.
12439  *
12440  * @return
12441  *   1 while a reference on it exists, 0 when freed.
12442  */
12443 static int
12444 flow_dv_dest_array_resource_release(struct rte_eth_dev *dev,
12445                                     struct mlx5_flow_handle *handle)
12446 {
12447         struct mlx5_priv *priv = dev->data->dev_private;
12448         struct mlx5_flow_dv_dest_array_resource *cache;
12449
12450         cache = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_DEST_ARRAY],
12451                                handle->dvh.rix_dest_array);
12452         if (!cache)
12453                 return 0;
12454         MLX5_ASSERT(cache->action);
12455         return mlx5_cache_unregister(&priv->sh->dest_array_list,
12456                                      &cache->entry);
12457 }
12458
12459 static void
12460 flow_dv_geneve_tlv_option_resource_release(struct rte_eth_dev *dev)
12461 {
12462         struct mlx5_priv *priv = dev->data->dev_private;
12463         struct mlx5_dev_ctx_shared *sh = priv->sh;
12464         struct mlx5_geneve_tlv_option_resource *geneve_opt_resource =
12465                                 sh->geneve_tlv_option_resource;
12466         rte_spinlock_lock(&sh->geneve_tlv_opt_sl);
12467         if (geneve_opt_resource) {
12468                 if (!(__atomic_sub_fetch(&geneve_opt_resource->refcnt, 1,
12469                                          __ATOMIC_RELAXED))) {
12470                         claim_zero(mlx5_devx_cmd_destroy
12471                                         (geneve_opt_resource->obj));
12472                         mlx5_free(sh->geneve_tlv_option_resource);
12473                         sh->geneve_tlv_option_resource = NULL;
12474                 }
12475         }
12476         rte_spinlock_unlock(&sh->geneve_tlv_opt_sl);
12477 }
12478
12479 /**
12480  * Remove the flow from the NIC but keeps it in memory.
12481  * Lock free, (mutex should be acquired by caller).
12482  *
12483  * @param[in] dev
12484  *   Pointer to Ethernet device.
12485  * @param[in, out] flow
12486  *   Pointer to flow structure.
12487  */
12488 static void
12489 flow_dv_remove(struct rte_eth_dev *dev, struct rte_flow *flow)
12490 {
12491         struct mlx5_flow_handle *dh;
12492         uint32_t handle_idx;
12493         struct mlx5_priv *priv = dev->data->dev_private;
12494
12495         if (!flow)
12496                 return;
12497         handle_idx = flow->dev_handles;
12498         while (handle_idx) {
12499                 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12500                                     handle_idx);
12501                 if (!dh)
12502                         return;
12503                 if (dh->drv_flow) {
12504                         claim_zero(mlx5_flow_os_destroy_flow(dh->drv_flow));
12505                         dh->drv_flow = NULL;
12506                 }
12507                 if (dh->fate_action == MLX5_FLOW_FATE_QUEUE)
12508                         flow_dv_fate_resource_release(dev, dh);
12509                 if (dh->vf_vlan.tag && dh->vf_vlan.created)
12510                         mlx5_vlan_vmwa_release(dev, &dh->vf_vlan);
12511                 handle_idx = dh->next.next;
12512         }
12513 }
12514
12515 /**
12516  * Remove the flow from the NIC and the memory.
12517  * Lock free, (mutex should be acquired by caller).
12518  *
12519  * @param[in] dev
12520  *   Pointer to the Ethernet device structure.
12521  * @param[in, out] flow
12522  *   Pointer to flow structure.
12523  */
12524 static void
12525 flow_dv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow)
12526 {
12527         struct mlx5_flow_handle *dev_handle;
12528         struct mlx5_priv *priv = dev->data->dev_private;
12529         uint32_t srss = 0;
12530
12531         if (!flow)
12532                 return;
12533         flow_dv_remove(dev, flow);
12534         if (flow->counter) {
12535                 flow_dv_counter_free(dev, flow->counter);
12536                 flow->counter = 0;
12537         }
12538         if (flow->meter) {
12539                 struct mlx5_flow_meter *fm;
12540
12541                 fm = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MTR],
12542                                     flow->meter);
12543                 if (fm)
12544                         mlx5_flow_meter_detach(fm);
12545                 flow->meter = 0;
12546         }
12547         if (flow->age)
12548                 flow_dv_aso_age_release(dev, flow->age);
12549         if (flow->geneve_tlv_option) {
12550                 flow_dv_geneve_tlv_option_resource_release(dev);
12551                 flow->geneve_tlv_option = 0;
12552         }
12553         while (flow->dev_handles) {
12554                 uint32_t tmp_idx = flow->dev_handles;
12555
12556                 dev_handle = mlx5_ipool_get(priv->sh->ipool
12557                                             [MLX5_IPOOL_MLX5_FLOW], tmp_idx);
12558                 if (!dev_handle)
12559                         return;
12560                 flow->dev_handles = dev_handle->next.next;
12561                 if (dev_handle->dvh.matcher)
12562                         flow_dv_matcher_release(dev, dev_handle);
12563                 if (dev_handle->dvh.rix_sample)
12564                         flow_dv_sample_resource_release(dev, dev_handle);
12565                 if (dev_handle->dvh.rix_dest_array)
12566                         flow_dv_dest_array_resource_release(dev, dev_handle);
12567                 if (dev_handle->dvh.rix_encap_decap)
12568                         flow_dv_encap_decap_resource_release(dev,
12569                                 dev_handle->dvh.rix_encap_decap);
12570                 if (dev_handle->dvh.modify_hdr)
12571                         flow_dv_modify_hdr_resource_release(dev, dev_handle);
12572                 if (dev_handle->dvh.rix_push_vlan)
12573                         flow_dv_push_vlan_action_resource_release(dev,
12574                                                                   dev_handle);
12575                 if (dev_handle->dvh.rix_tag)
12576                         flow_dv_tag_release(dev,
12577                                             dev_handle->dvh.rix_tag);
12578                 if (dev_handle->fate_action != MLX5_FLOW_FATE_SHARED_RSS)
12579                         flow_dv_fate_resource_release(dev, dev_handle);
12580                 else if (!srss)
12581                         srss = dev_handle->rix_srss;
12582                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW],
12583                            tmp_idx);
12584         }
12585         if (srss)
12586                 flow_dv_shared_rss_action_release(dev, srss);
12587 }
12588
12589 /**
12590  * Release array of hash RX queue objects.
12591  * Helper function.
12592  *
12593  * @param[in] dev
12594  *   Pointer to the Ethernet device structure.
12595  * @param[in, out] hrxqs
12596  *   Array of hash RX queue objects.
12597  *
12598  * @return
12599  *   Total number of references to hash RX queue objects in *hrxqs* array
12600  *   after this operation.
12601  */
12602 static int
12603 __flow_dv_hrxqs_release(struct rte_eth_dev *dev,
12604                         uint32_t (*hrxqs)[MLX5_RSS_HASH_FIELDS_LEN])
12605 {
12606         size_t i;
12607         int remaining = 0;
12608
12609         for (i = 0; i < RTE_DIM(*hrxqs); i++) {
12610                 int ret = mlx5_hrxq_release(dev, (*hrxqs)[i]);
12611
12612                 if (!ret)
12613                         (*hrxqs)[i] = 0;
12614                 remaining += ret;
12615         }
12616         return remaining;
12617 }
12618
12619 /**
12620  * Release all hash RX queue objects representing shared RSS action.
12621  *
12622  * @param[in] dev
12623  *   Pointer to the Ethernet device structure.
12624  * @param[in, out] action
12625  *   Shared RSS action to remove hash RX queue objects from.
12626  *
12627  * @return
12628  *   Total number of references to hash RX queue objects stored in *action*
12629  *   after this operation.
12630  *   Expected to be 0 if no external references held.
12631  */
12632 static int
12633 __flow_dv_action_rss_hrxqs_release(struct rte_eth_dev *dev,
12634                                  struct mlx5_shared_action_rss *shared_rss)
12635 {
12636         return __flow_dv_hrxqs_release(dev, &shared_rss->hrxq) +
12637                 __flow_dv_hrxqs_release(dev, &shared_rss->hrxq_tunnel);
12638 }
12639
12640 /**
12641  * Setup shared RSS action.
12642  * Prepare set of hash RX queue objects sufficient to handle all valid
12643  * hash_fields combinations (see enum ibv_rx_hash_fields).
12644  *
12645  * @param[in] dev
12646  *   Pointer to the Ethernet device structure.
12647  * @param[in] action_idx
12648  *   Shared RSS action ipool index.
12649  * @param[in, out] action
12650  *   Partially initialized shared RSS action.
12651  * @param[out] error
12652  *   Perform verbose error reporting if not NULL. Initialized in case of
12653  *   error only.
12654  *
12655  * @return
12656  *   0 on success, otherwise negative errno value.
12657  */
12658 static int
12659 __flow_dv_action_rss_setup(struct rte_eth_dev *dev,
12660                            uint32_t action_idx,
12661                            struct mlx5_shared_action_rss *shared_rss,
12662                            struct rte_flow_error *error)
12663 {
12664         struct mlx5_flow_rss_desc rss_desc = { 0 };
12665         size_t i;
12666         int err;
12667
12668         if (mlx5_ind_table_obj_setup(dev, shared_rss->ind_tbl)) {
12669                 return rte_flow_error_set(error, rte_errno,
12670                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12671                                           "cannot setup indirection table");
12672         }
12673         memcpy(rss_desc.key, shared_rss->origin.key, MLX5_RSS_HASH_KEY_LEN);
12674         rss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;
12675         rss_desc.const_q = shared_rss->origin.queue;
12676         rss_desc.queue_num = shared_rss->origin.queue_num;
12677         /* Set non-zero value to indicate a shared RSS. */
12678         rss_desc.shared_rss = action_idx;
12679         rss_desc.ind_tbl = shared_rss->ind_tbl;
12680         for (i = 0; i < MLX5_RSS_HASH_FIELDS_LEN; i++) {
12681                 uint32_t hrxq_idx;
12682                 uint64_t hash_fields = mlx5_rss_hash_fields[i];
12683                 int tunnel;
12684
12685                 for (tunnel = 0; tunnel < 2; tunnel++) {
12686                         rss_desc.tunnel = tunnel;
12687                         rss_desc.hash_fields = hash_fields;
12688                         hrxq_idx = mlx5_hrxq_get(dev, &rss_desc);
12689                         if (!hrxq_idx) {
12690                                 rte_flow_error_set
12691                                         (error, rte_errno,
12692                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12693                                          "cannot get hash queue");
12694                                 goto error_hrxq_new;
12695                         }
12696                         err = __flow_dv_action_rss_hrxq_set
12697                                 (shared_rss, hash_fields, tunnel, hrxq_idx);
12698                         MLX5_ASSERT(!err);
12699                 }
12700         }
12701         return 0;
12702 error_hrxq_new:
12703         err = rte_errno;
12704         __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12705         if (!mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true))
12706                 shared_rss->ind_tbl = NULL;
12707         rte_errno = err;
12708         return -rte_errno;
12709 }
12710
12711 /**
12712  * Create shared RSS action.
12713  *
12714  * @param[in] dev
12715  *   Pointer to the Ethernet device structure.
12716  * @param[in] conf
12717  *   Shared action configuration.
12718  * @param[in] rss
12719  *   RSS action specification used to create shared action.
12720  * @param[out] error
12721  *   Perform verbose error reporting if not NULL. Initialized in case of
12722  *   error only.
12723  *
12724  * @return
12725  *   A valid shared action ID in case of success, 0 otherwise and
12726  *   rte_errno is set.
12727  */
12728 static uint32_t
12729 __flow_dv_action_rss_create(struct rte_eth_dev *dev,
12730                             const struct rte_flow_shared_action_conf *conf,
12731                             const struct rte_flow_action_rss *rss,
12732                             struct rte_flow_error *error)
12733 {
12734         struct mlx5_priv *priv = dev->data->dev_private;
12735         struct mlx5_shared_action_rss *shared_rss = NULL;
12736         void *queue = NULL;
12737         struct rte_flow_action_rss *origin;
12738         const uint8_t *rss_key;
12739         uint32_t queue_size = rss->queue_num * sizeof(uint16_t);
12740         uint32_t idx;
12741
12742         RTE_SET_USED(conf);
12743         queue = mlx5_malloc(0, RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
12744                             0, SOCKET_ID_ANY);
12745         shared_rss = mlx5_ipool_zmalloc
12746                          (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], &idx);
12747         if (!shared_rss || !queue) {
12748                 rte_flow_error_set(error, ENOMEM,
12749                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12750                                    "cannot allocate resource memory");
12751                 goto error_rss_init;
12752         }
12753         if (idx > (1u << MLX5_SHARED_ACTION_TYPE_OFFSET)) {
12754                 rte_flow_error_set(error, E2BIG,
12755                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12756                                    "rss action number out of range");
12757                 goto error_rss_init;
12758         }
12759         shared_rss->ind_tbl = mlx5_malloc(MLX5_MEM_ZERO,
12760                                           sizeof(*shared_rss->ind_tbl),
12761                                           0, SOCKET_ID_ANY);
12762         if (!shared_rss->ind_tbl) {
12763                 rte_flow_error_set(error, ENOMEM,
12764                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,
12765                                    "cannot allocate resource memory");
12766                 goto error_rss_init;
12767         }
12768         memcpy(queue, rss->queue, queue_size);
12769         shared_rss->ind_tbl->queues = queue;
12770         shared_rss->ind_tbl->queues_n = rss->queue_num;
12771         origin = &shared_rss->origin;
12772         origin->func = rss->func;
12773         origin->level = rss->level;
12774         /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */
12775         origin->types = !rss->types ? ETH_RSS_IP : rss->types;
12776         /* NULL RSS key indicates default RSS key. */
12777         rss_key = !rss->key ? rss_hash_default_key : rss->key;
12778         memcpy(shared_rss->key, rss_key, MLX5_RSS_HASH_KEY_LEN);
12779         origin->key = &shared_rss->key[0];
12780         origin->key_len = MLX5_RSS_HASH_KEY_LEN;
12781         origin->queue = queue;
12782         origin->queue_num = rss->queue_num;
12783         if (__flow_dv_action_rss_setup(dev, idx, shared_rss, error))
12784                 goto error_rss_init;
12785         rte_spinlock_init(&shared_rss->action_rss_sl);
12786         __atomic_add_fetch(&shared_rss->refcnt, 1, __ATOMIC_RELAXED);
12787         rte_spinlock_lock(&priv->shared_act_sl);
12788         ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12789                      &priv->rss_shared_actions, idx, shared_rss, next);
12790         rte_spinlock_unlock(&priv->shared_act_sl);
12791         return idx;
12792 error_rss_init:
12793         if (shared_rss) {
12794                 if (shared_rss->ind_tbl)
12795                         mlx5_free(shared_rss->ind_tbl);
12796                 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12797                                 idx);
12798         }
12799         if (queue)
12800                 mlx5_free(queue);
12801         return 0;
12802 }
12803
12804 /**
12805  * Destroy the shared RSS action.
12806  * Release related hash RX queue objects.
12807  *
12808  * @param[in] dev
12809  *   Pointer to the Ethernet device structure.
12810  * @param[in] idx
12811  *   The shared RSS action object ID to be removed.
12812  * @param[out] error
12813  *   Perform verbose error reporting if not NULL. Initialized in case of
12814  *   error only.
12815  *
12816  * @return
12817  *   0 on success, otherwise negative errno value.
12818  */
12819 static int
12820 __flow_dv_action_rss_release(struct rte_eth_dev *dev, uint32_t idx,
12821                              struct rte_flow_error *error)
12822 {
12823         struct mlx5_priv *priv = dev->data->dev_private;
12824         struct mlx5_shared_action_rss *shared_rss =
12825             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12826         uint32_t old_refcnt = 1;
12827         int remaining;
12828         uint16_t *queue = NULL;
12829
12830         if (!shared_rss)
12831                 return rte_flow_error_set(error, EINVAL,
12832                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
12833                                           "invalid shared action");
12834         remaining = __flow_dv_action_rss_hrxqs_release(dev, shared_rss);
12835         if (remaining)
12836                 return rte_flow_error_set(error, EBUSY,
12837                                           RTE_FLOW_ERROR_TYPE_ACTION,
12838                                           NULL,
12839                                           "shared rss hrxq has references");
12840         if (!__atomic_compare_exchange_n(&shared_rss->refcnt, &old_refcnt,
12841                                          0, 0, __ATOMIC_ACQUIRE,
12842                                          __ATOMIC_RELAXED))
12843                 return rte_flow_error_set(error, EBUSY,
12844                                           RTE_FLOW_ERROR_TYPE_ACTION,
12845                                           NULL,
12846                                           "shared rss has references");
12847         queue = shared_rss->ind_tbl->queues;
12848         remaining = mlx5_ind_table_obj_release(dev, shared_rss->ind_tbl, true);
12849         if (remaining)
12850                 return rte_flow_error_set(error, EBUSY,
12851                                           RTE_FLOW_ERROR_TYPE_ACTION,
12852                                           NULL,
12853                                           "shared rss indirection table has"
12854                                           " references");
12855         mlx5_free(queue);
12856         rte_spinlock_lock(&priv->shared_act_sl);
12857         ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12858                      &priv->rss_shared_actions, idx, shared_rss, next);
12859         rte_spinlock_unlock(&priv->shared_act_sl);
12860         mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS],
12861                         idx);
12862         return 0;
12863 }
12864
12865 /**
12866  * Create shared action, lock free,
12867  * (mutex should be acquired by caller).
12868  * Dispatcher for action type specific call.
12869  *
12870  * @param[in] dev
12871  *   Pointer to the Ethernet device structure.
12872  * @param[in] conf
12873  *   Shared action configuration.
12874  * @param[in] action
12875  *   Action specification used to create shared action.
12876  * @param[out] error
12877  *   Perform verbose error reporting if not NULL. Initialized in case of
12878  *   error only.
12879  *
12880  * @return
12881  *   A valid shared action handle in case of success, NULL otherwise and
12882  *   rte_errno is set.
12883  */
12884 static struct rte_flow_shared_action *
12885 flow_dv_action_create(struct rte_eth_dev *dev,
12886                       const struct rte_flow_shared_action_conf *conf,
12887                       const struct rte_flow_action *action,
12888                       struct rte_flow_error *err)
12889 {
12890         uint32_t idx = 0;
12891         uint32_t ret = 0;
12892
12893         switch (action->type) {
12894         case RTE_FLOW_ACTION_TYPE_RSS:
12895                 ret = __flow_dv_action_rss_create(dev, conf, action->conf, err);
12896                 idx = (MLX5_SHARED_ACTION_TYPE_RSS <<
12897                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12898                 break;
12899         case RTE_FLOW_ACTION_TYPE_AGE:
12900                 ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
12901                 idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
12902                        MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
12903                 if (ret) {
12904                         struct mlx5_aso_age_action *aso_age =
12905                                               flow_aso_age_get_by_idx(dev, ret);
12906
12907                         if (!aso_age->age_params.context)
12908                                 aso_age->age_params.context =
12909                                                          (void *)(uintptr_t)idx;
12910                 }
12911                 break;
12912         default:
12913                 rte_flow_error_set(err, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION,
12914                                    NULL, "action type not supported");
12915                 break;
12916         }
12917         return ret ? (struct rte_flow_shared_action *)(uintptr_t)idx : NULL;
12918 }
12919
12920 /**
12921  * Destroy the shared action.
12922  * Release action related resources on the NIC and the memory.
12923  * Lock free, (mutex should be acquired by caller).
12924  * Dispatcher for action type specific call.
12925  *
12926  * @param[in] dev
12927  *   Pointer to the Ethernet device structure.
12928  * @param[in] action
12929  *   The shared action object to be removed.
12930  * @param[out] error
12931  *   Perform verbose error reporting if not NULL. Initialized in case of
12932  *   error only.
12933  *
12934  * @return
12935  *   0 on success, otherwise negative errno value.
12936  */
12937 static int
12938 flow_dv_action_destroy(struct rte_eth_dev *dev,
12939                        struct rte_flow_shared_action *action,
12940                        struct rte_flow_error *error)
12941 {
12942         uint32_t act_idx = (uint32_t)(uintptr_t)action;
12943         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
12944         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
12945         int ret;
12946
12947         switch (type) {
12948         case MLX5_SHARED_ACTION_TYPE_RSS:
12949                 return __flow_dv_action_rss_release(dev, idx, error);
12950         case MLX5_SHARED_ACTION_TYPE_AGE:
12951                 ret = flow_dv_aso_age_release(dev, idx);
12952                 if (ret)
12953                         /*
12954                          * In this case, the last flow has a reference will
12955                          * actually release the age action.
12956                          */
12957                         DRV_LOG(DEBUG, "Shared age action %" PRIu32 " was"
12958                                 " released with references %d.", idx, ret);
12959                 return 0;
12960         default:
12961                 return rte_flow_error_set(error, ENOTSUP,
12962                                           RTE_FLOW_ERROR_TYPE_ACTION,
12963                                           NULL,
12964                                           "action type not supported");
12965         }
12966 }
12967
12968 /**
12969  * Updates in place shared RSS action configuration.
12970  *
12971  * @param[in] dev
12972  *   Pointer to the Ethernet device structure.
12973  * @param[in] idx
12974  *   The shared RSS action object ID to be updated.
12975  * @param[in] action_conf
12976  *   RSS action specification used to modify *shared_rss*.
12977  * @param[out] error
12978  *   Perform verbose error reporting if not NULL. Initialized in case of
12979  *   error only.
12980  *
12981  * @return
12982  *   0 on success, otherwise negative errno value.
12983  * @note: currently only support update of RSS queues.
12984  */
12985 static int
12986 __flow_dv_action_rss_update(struct rte_eth_dev *dev, uint32_t idx,
12987                             const struct rte_flow_action_rss *action_conf,
12988                             struct rte_flow_error *error)
12989 {
12990         struct mlx5_priv *priv = dev->data->dev_private;
12991         struct mlx5_shared_action_rss *shared_rss =
12992             mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx);
12993         int ret = 0;
12994         void *queue = NULL;
12995         uint16_t *queue_old = NULL;
12996         uint32_t queue_size = action_conf->queue_num * sizeof(uint16_t);
12997
12998         if (!shared_rss)
12999                 return rte_flow_error_set(error, EINVAL,
13000                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13001                                           "invalid shared action to update");
13002         if (priv->obj_ops.ind_table_modify == NULL)
13003                 return rte_flow_error_set(error, ENOTSUP,
13004                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13005                                           "cannot modify indirection table");
13006         queue = mlx5_malloc(MLX5_MEM_ZERO,
13007                             RTE_ALIGN_CEIL(queue_size, sizeof(void *)),
13008                             0, SOCKET_ID_ANY);
13009         if (!queue)
13010                 return rte_flow_error_set(error, ENOMEM,
13011                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13012                                           NULL,
13013                                           "cannot allocate resource memory");
13014         memcpy(queue, action_conf->queue, queue_size);
13015         MLX5_ASSERT(shared_rss->ind_tbl);
13016         rte_spinlock_lock(&shared_rss->action_rss_sl);
13017         queue_old = shared_rss->ind_tbl->queues;
13018         ret = mlx5_ind_table_obj_modify(dev, shared_rss->ind_tbl,
13019                                         queue, action_conf->queue_num, true);
13020         if (ret) {
13021                 mlx5_free(queue);
13022                 ret = rte_flow_error_set(error, rte_errno,
13023                                           RTE_FLOW_ERROR_TYPE_ACTION, NULL,
13024                                           "cannot update indirection table");
13025         } else {
13026                 mlx5_free(queue_old);
13027                 shared_rss->origin.queue = queue;
13028                 shared_rss->origin.queue_num = action_conf->queue_num;
13029         }
13030         rte_spinlock_unlock(&shared_rss->action_rss_sl);
13031         return ret;
13032 }
13033
13034 /**
13035  * Updates in place shared action configuration, lock free,
13036  * (mutex should be acquired by caller).
13037  *
13038  * @param[in] dev
13039  *   Pointer to the Ethernet device structure.
13040  * @param[in] action
13041  *   The shared action object to be updated.
13042  * @param[in] action_conf
13043  *   Action specification used to modify *action*.
13044  *   *action_conf* should be of type correlating with type of the *action*,
13045  *   otherwise considered as invalid.
13046  * @param[out] error
13047  *   Perform verbose error reporting if not NULL. Initialized in case of
13048  *   error only.
13049  *
13050  * @return
13051  *   0 on success, otherwise negative errno value.
13052  */
13053 static int
13054 flow_dv_action_update(struct rte_eth_dev *dev,
13055                         struct rte_flow_shared_action *action,
13056                         const void *action_conf,
13057                         struct rte_flow_error *err)
13058 {
13059         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13060         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13061         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13062
13063         switch (type) {
13064         case MLX5_SHARED_ACTION_TYPE_RSS:
13065                 return __flow_dv_action_rss_update(dev, idx, action_conf, err);
13066         default:
13067                 return rte_flow_error_set(err, ENOTSUP,
13068                                           RTE_FLOW_ERROR_TYPE_ACTION,
13069                                           NULL,
13070                                           "action type update not supported");
13071         }
13072 }
13073
13074 static int
13075 flow_dv_action_query(struct rte_eth_dev *dev,
13076                      const struct rte_flow_shared_action *action, void *data,
13077                      struct rte_flow_error *error)
13078 {
13079         struct mlx5_age_param *age_param;
13080         struct rte_flow_query_age *resp;
13081         uint32_t act_idx = (uint32_t)(uintptr_t)action;
13082         uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET;
13083         uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1);
13084
13085         switch (type) {
13086         case MLX5_SHARED_ACTION_TYPE_AGE:
13087                 age_param = &flow_aso_age_get_by_idx(dev, idx)->age_params;
13088                 resp = data;
13089                 resp->aged = __atomic_load_n(&age_param->state,
13090                                               __ATOMIC_RELAXED) == AGE_TMOUT ?
13091                                                                           1 : 0;
13092                 resp->sec_since_last_hit_valid = !resp->aged;
13093                 if (resp->sec_since_last_hit_valid)
13094                         resp->sec_since_last_hit = __atomic_load_n
13095                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13096                 return 0;
13097         default:
13098                 return rte_flow_error_set(error, ENOTSUP,
13099                                           RTE_FLOW_ERROR_TYPE_ACTION,
13100                                           NULL,
13101                                           "action type query not supported");
13102         }
13103 }
13104
13105 /**
13106  * Query a dv flow  rule for its statistics via devx.
13107  *
13108  * @param[in] dev
13109  *   Pointer to Ethernet device.
13110  * @param[in] flow
13111  *   Pointer to the sub flow.
13112  * @param[out] data
13113  *   data retrieved by the query.
13114  * @param[out] error
13115  *   Perform verbose error reporting if not NULL.
13116  *
13117  * @return
13118  *   0 on success, a negative errno value otherwise and rte_errno is set.
13119  */
13120 static int
13121 flow_dv_query_count(struct rte_eth_dev *dev, struct rte_flow *flow,
13122                     void *data, struct rte_flow_error *error)
13123 {
13124         struct mlx5_priv *priv = dev->data->dev_private;
13125         struct rte_flow_query_count *qc = data;
13126
13127         if (!priv->config.devx)
13128                 return rte_flow_error_set(error, ENOTSUP,
13129                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13130                                           NULL,
13131                                           "counters are not supported");
13132         if (flow->counter) {
13133                 uint64_t pkts, bytes;
13134                 struct mlx5_flow_counter *cnt;
13135
13136                 cnt = flow_dv_counter_get_by_idx(dev, flow->counter,
13137                                                  NULL);
13138                 int err = _flow_dv_query_count(dev, flow->counter, &pkts,
13139                                                &bytes);
13140
13141                 if (err)
13142                         return rte_flow_error_set(error, -err,
13143                                         RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13144                                         NULL, "cannot read counters");
13145                 qc->hits_set = 1;
13146                 qc->bytes_set = 1;
13147                 qc->hits = pkts - cnt->hits;
13148                 qc->bytes = bytes - cnt->bytes;
13149                 if (qc->reset) {
13150                         cnt->hits = pkts;
13151                         cnt->bytes = bytes;
13152                 }
13153                 return 0;
13154         }
13155         return rte_flow_error_set(error, EINVAL,
13156                                   RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13157                                   NULL,
13158                                   "counters are not available");
13159 }
13160
13161 /**
13162  * Query a flow rule AGE action for aging information.
13163  *
13164  * @param[in] dev
13165  *   Pointer to Ethernet device.
13166  * @param[in] flow
13167  *   Pointer to the sub flow.
13168  * @param[out] data
13169  *   data retrieved by the query.
13170  * @param[out] error
13171  *   Perform verbose error reporting if not NULL.
13172  *
13173  * @return
13174  *   0 on success, a negative errno value otherwise and rte_errno is set.
13175  */
13176 static int
13177 flow_dv_query_age(struct rte_eth_dev *dev, struct rte_flow *flow,
13178                   void *data, struct rte_flow_error *error)
13179 {
13180         struct rte_flow_query_age *resp = data;
13181         struct mlx5_age_param *age_param;
13182
13183         if (flow->age) {
13184                 struct mlx5_aso_age_action *act =
13185                                      flow_aso_age_get_by_idx(dev, flow->age);
13186
13187                 age_param = &act->age_params;
13188         } else if (flow->counter) {
13189                 age_param = flow_dv_counter_idx_get_age(dev, flow->counter);
13190
13191                 if (!age_param || !age_param->timeout)
13192                         return rte_flow_error_set
13193                                         (error, EINVAL,
13194                                          RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13195                                          NULL, "cannot read age data");
13196         } else {
13197                 return rte_flow_error_set(error, EINVAL,
13198                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13199                                           NULL, "age data not available");
13200         }
13201         resp->aged = __atomic_load_n(&age_param->state, __ATOMIC_RELAXED) ==
13202                                      AGE_TMOUT ? 1 : 0;
13203         resp->sec_since_last_hit_valid = !resp->aged;
13204         if (resp->sec_since_last_hit_valid)
13205                 resp->sec_since_last_hit = __atomic_load_n
13206                              (&age_param->sec_since_last_hit, __ATOMIC_RELAXED);
13207         return 0;
13208 }
13209
13210 /**
13211  * Query a flow.
13212  *
13213  * @see rte_flow_query()
13214  * @see rte_flow_ops
13215  */
13216 static int
13217 flow_dv_query(struct rte_eth_dev *dev,
13218               struct rte_flow *flow __rte_unused,
13219               const struct rte_flow_action *actions __rte_unused,
13220               void *data __rte_unused,
13221               struct rte_flow_error *error __rte_unused)
13222 {
13223         int ret = -EINVAL;
13224
13225         for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) {
13226                 switch (actions->type) {
13227                 case RTE_FLOW_ACTION_TYPE_VOID:
13228                         break;
13229                 case RTE_FLOW_ACTION_TYPE_COUNT:
13230                         ret = flow_dv_query_count(dev, flow, data, error);
13231                         break;
13232                 case RTE_FLOW_ACTION_TYPE_AGE:
13233                         ret = flow_dv_query_age(dev, flow, data, error);
13234                         break;
13235                 default:
13236                         return rte_flow_error_set(error, ENOTSUP,
13237                                                   RTE_FLOW_ERROR_TYPE_ACTION,
13238                                                   actions,
13239                                                   "action not supported");
13240                 }
13241         }
13242         return ret;
13243 }
13244
13245 /**
13246  * Destroy the meter table set.
13247  * Lock free, (mutex should be acquired by caller).
13248  *
13249  * @param[in] dev
13250  *   Pointer to Ethernet device.
13251  * @param[in] tbl
13252  *   Pointer to the meter table set.
13253  *
13254  * @return
13255  *   Always 0.
13256  */
13257 static int
13258 flow_dv_destroy_mtr_tbl(struct rte_eth_dev *dev,
13259                         struct mlx5_meter_domains_infos *tbl)
13260 {
13261         struct mlx5_priv *priv = dev->data->dev_private;
13262         struct mlx5_meter_domains_infos *mtd =
13263                                 (struct mlx5_meter_domains_infos *)tbl;
13264
13265         if (!mtd || !priv->config.dv_flow_en)
13266                 return 0;
13267         if (mtd->ingress.policer_rules[RTE_MTR_DROPPED])
13268                 claim_zero(mlx5_flow_os_destroy_flow
13269                            (mtd->ingress.policer_rules[RTE_MTR_DROPPED]));
13270         if (mtd->egress.policer_rules[RTE_MTR_DROPPED])
13271                 claim_zero(mlx5_flow_os_destroy_flow
13272                            (mtd->egress.policer_rules[RTE_MTR_DROPPED]));
13273         if (mtd->transfer.policer_rules[RTE_MTR_DROPPED])
13274                 claim_zero(mlx5_flow_os_destroy_flow
13275                            (mtd->transfer.policer_rules[RTE_MTR_DROPPED]));
13276         if (mtd->egress.color_matcher)
13277                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13278                            (mtd->egress.color_matcher));
13279         if (mtd->egress.any_matcher)
13280                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13281                            (mtd->egress.any_matcher));
13282         if (mtd->egress.tbl)
13283                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.tbl);
13284         if (mtd->egress.sfx_tbl)
13285                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->egress.sfx_tbl);
13286         if (mtd->ingress.color_matcher)
13287                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13288                            (mtd->ingress.color_matcher));
13289         if (mtd->ingress.any_matcher)
13290                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13291                            (mtd->ingress.any_matcher));
13292         if (mtd->ingress.tbl)
13293                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->ingress.tbl);
13294         if (mtd->ingress.sfx_tbl)
13295                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13296                                              mtd->ingress.sfx_tbl);
13297         if (mtd->transfer.color_matcher)
13298                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13299                            (mtd->transfer.color_matcher));
13300         if (mtd->transfer.any_matcher)
13301                 claim_zero(mlx5_flow_os_destroy_flow_matcher
13302                            (mtd->transfer.any_matcher));
13303         if (mtd->transfer.tbl)
13304                 flow_dv_tbl_resource_release(MLX5_SH(dev), mtd->transfer.tbl);
13305         if (mtd->transfer.sfx_tbl)
13306                 flow_dv_tbl_resource_release(MLX5_SH(dev),
13307                                              mtd->transfer.sfx_tbl);
13308         if (mtd->drop_actn)
13309                 claim_zero(mlx5_flow_os_destroy_flow_action(mtd->drop_actn));
13310         mlx5_free(mtd);
13311         return 0;
13312 }
13313
13314 /* Number of meter flow actions, count and jump or count and drop. */
13315 #define METER_ACTIONS 2
13316
13317 /**
13318  * Create specify domain meter table and suffix table.
13319  *
13320  * @param[in] dev
13321  *   Pointer to Ethernet device.
13322  * @param[in,out] mtb
13323  *   Pointer to DV meter table set.
13324  * @param[in] egress
13325  *   Table attribute.
13326  * @param[in] transfer
13327  *   Table attribute.
13328  * @param[in] color_reg_c_idx
13329  *   Reg C index for color match.
13330  *
13331  * @return
13332  *   0 on success, -1 otherwise and rte_errno is set.
13333  */
13334 static int
13335 flow_dv_prepare_mtr_tables(struct rte_eth_dev *dev,
13336                            struct mlx5_meter_domains_infos *mtb,
13337                            uint8_t egress, uint8_t transfer,
13338                            uint32_t color_reg_c_idx)
13339 {
13340         struct mlx5_priv *priv = dev->data->dev_private;
13341         struct mlx5_dev_ctx_shared *sh = priv->sh;
13342         struct mlx5_flow_dv_match_params mask = {
13343                 .size = sizeof(mask.buf),
13344         };
13345         struct mlx5_flow_dv_match_params value = {
13346                 .size = sizeof(value.buf),
13347         };
13348         struct mlx5dv_flow_matcher_attr dv_attr = {
13349                 .type = IBV_FLOW_ATTR_NORMAL,
13350                 .priority = 0,
13351                 .match_criteria_enable = 0,
13352                 .match_mask = (void *)&mask,
13353         };
13354         void *actions[METER_ACTIONS];
13355         struct mlx5_meter_domain_info *dtb;
13356         struct rte_flow_error error;
13357         int i = 0;
13358         int ret;
13359
13360         if (transfer)
13361                 dtb = &mtb->transfer;
13362         else if (egress)
13363                 dtb = &mtb->egress;
13364         else
13365                 dtb = &mtb->ingress;
13366         /* Create the meter table with METER level. */
13367         dtb->tbl = flow_dv_tbl_resource_get(dev, MLX5_FLOW_TABLE_LEVEL_METER,
13368                                             egress, transfer, false, NULL, 0,
13369                                             0, &error);
13370         if (!dtb->tbl) {
13371                 DRV_LOG(ERR, "Failed to create meter policer table.");
13372                 return -1;
13373         }
13374         /* Create the meter suffix table with SUFFIX level. */
13375         dtb->sfx_tbl = flow_dv_tbl_resource_get(dev,
13376                                             MLX5_FLOW_TABLE_LEVEL_SUFFIX,
13377                                             egress, transfer, false, NULL, 0,
13378                                             0, &error);
13379         if (!dtb->sfx_tbl) {
13380                 DRV_LOG(ERR, "Failed to create meter suffix table.");
13381                 return -1;
13382         }
13383         /* Create matchers, Any and Color. */
13384         dv_attr.priority = 3;
13385         dv_attr.match_criteria_enable = 0;
13386         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13387                                                &dtb->any_matcher);
13388         if (ret) {
13389                 DRV_LOG(ERR, "Failed to create meter"
13390                              " policer default matcher.");
13391                 goto error_exit;
13392         }
13393         dv_attr.priority = 0;
13394         dv_attr.match_criteria_enable =
13395                                 1 << MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT;
13396         flow_dv_match_meta_reg(mask.buf, value.buf, color_reg_c_idx,
13397                                rte_col_2_mlx5_col(RTE_COLORS), UINT8_MAX);
13398         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, dtb->tbl->obj,
13399                                                &dtb->color_matcher);
13400         if (ret) {
13401                 DRV_LOG(ERR, "Failed to create meter policer color matcher.");
13402                 goto error_exit;
13403         }
13404         if (mtb->count_actns[RTE_MTR_DROPPED])
13405                 actions[i++] = mtb->count_actns[RTE_MTR_DROPPED];
13406         actions[i++] = mtb->drop_actn;
13407         /* Default rule: lowest priority, match any, actions: drop. */
13408         ret = mlx5_flow_os_create_flow(dtb->any_matcher, (void *)&value, i,
13409                                        actions,
13410                                        &dtb->policer_rules[RTE_MTR_DROPPED]);
13411         if (ret) {
13412                 DRV_LOG(ERR, "Failed to create meter policer drop rule.");
13413                 goto error_exit;
13414         }
13415         return 0;
13416 error_exit:
13417         return -1;
13418 }
13419
13420 /**
13421  * Create the needed meter and suffix tables.
13422  * Lock free, (mutex should be acquired by caller).
13423  *
13424  * @param[in] dev
13425  *   Pointer to Ethernet device.
13426  * @param[in] fm
13427  *   Pointer to the flow meter.
13428  *
13429  * @return
13430  *   Pointer to table set on success, NULL otherwise and rte_errno is set.
13431  */
13432 static struct mlx5_meter_domains_infos *
13433 flow_dv_create_mtr_tbl(struct rte_eth_dev *dev,
13434                        const struct mlx5_flow_meter *fm)
13435 {
13436         struct mlx5_priv *priv = dev->data->dev_private;
13437         struct mlx5_meter_domains_infos *mtb;
13438         int ret;
13439         int i;
13440
13441         if (!priv->mtr_en) {
13442                 rte_errno = ENOTSUP;
13443                 return NULL;
13444         }
13445         mtb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mtb), 0, SOCKET_ID_ANY);
13446         if (!mtb) {
13447                 DRV_LOG(ERR, "Failed to allocate memory for meter.");
13448                 return NULL;
13449         }
13450         /* Create meter count actions */
13451         for (i = 0; i <= RTE_MTR_DROPPED; i++) {
13452                 struct mlx5_flow_counter *cnt;
13453                 if (!fm->policer_stats.cnt[i])
13454                         continue;
13455                 cnt = flow_dv_counter_get_by_idx(dev,
13456                       fm->policer_stats.cnt[i], NULL);
13457                 mtb->count_actns[i] = cnt->action;
13458         }
13459         /* Create drop action. */
13460         ret = mlx5_flow_os_create_flow_action_drop(&mtb->drop_actn);
13461         if (ret) {
13462                 DRV_LOG(ERR, "Failed to create drop action.");
13463                 goto error_exit;
13464         }
13465         /* Egress meter table. */
13466         ret = flow_dv_prepare_mtr_tables(dev, mtb, 1, 0, priv->mtr_color_reg);
13467         if (ret) {
13468                 DRV_LOG(ERR, "Failed to prepare egress meter table.");
13469                 goto error_exit;
13470         }
13471         /* Ingress meter table. */
13472         ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 0, priv->mtr_color_reg);
13473         if (ret) {
13474                 DRV_LOG(ERR, "Failed to prepare ingress meter table.");
13475                 goto error_exit;
13476         }
13477         /* FDB meter table. */
13478         if (priv->config.dv_esw_en) {
13479                 ret = flow_dv_prepare_mtr_tables(dev, mtb, 0, 1,
13480                                                  priv->mtr_color_reg);
13481                 if (ret) {
13482                         DRV_LOG(ERR, "Failed to prepare fdb meter table.");
13483                         goto error_exit;
13484                 }
13485         }
13486         return mtb;
13487 error_exit:
13488         flow_dv_destroy_mtr_tbl(dev, mtb);
13489         return NULL;
13490 }
13491
13492 /**
13493  * Destroy domain policer rule.
13494  *
13495  * @param[in] dt
13496  *   Pointer to domain table.
13497  */
13498 static void
13499 flow_dv_destroy_domain_policer_rule(struct mlx5_meter_domain_info *dt)
13500 {
13501         int i;
13502
13503         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13504                 if (dt->policer_rules[i]) {
13505                         claim_zero(mlx5_flow_os_destroy_flow
13506                                    (dt->policer_rules[i]));
13507                         dt->policer_rules[i] = NULL;
13508                 }
13509         }
13510         if (dt->jump_actn) {
13511                 claim_zero(mlx5_flow_os_destroy_flow_action(dt->jump_actn));
13512                 dt->jump_actn = NULL;
13513         }
13514 }
13515
13516 /**
13517  * Destroy policer rules.
13518  *
13519  * @param[in] dev
13520  *   Pointer to Ethernet device.
13521  * @param[in] fm
13522  *   Pointer to flow meter structure.
13523  * @param[in] attr
13524  *   Pointer to flow attributes.
13525  *
13526  * @return
13527  *   Always 0.
13528  */
13529 static int
13530 flow_dv_destroy_policer_rules(struct rte_eth_dev *dev __rte_unused,
13531                               const struct mlx5_flow_meter *fm,
13532                               const struct rte_flow_attr *attr)
13533 {
13534         struct mlx5_meter_domains_infos *mtb = fm ? fm->mfts : NULL;
13535
13536         if (!mtb)
13537                 return 0;
13538         if (attr->egress)
13539                 flow_dv_destroy_domain_policer_rule(&mtb->egress);
13540         if (attr->ingress)
13541                 flow_dv_destroy_domain_policer_rule(&mtb->ingress);
13542         if (attr->transfer)
13543                 flow_dv_destroy_domain_policer_rule(&mtb->transfer);
13544         return 0;
13545 }
13546
13547 /**
13548  * Create specify domain meter policer rule.
13549  *
13550  * @param[in] fm
13551  *   Pointer to flow meter structure.
13552  * @param[in] mtb
13553  *   Pointer to DV meter table set.
13554  * @param[in] mtr_reg_c
13555  *   Color match REG_C.
13556  *
13557  * @return
13558  *   0 on success, -1 otherwise.
13559  */
13560 static int
13561 flow_dv_create_policer_forward_rule(struct mlx5_flow_meter *fm,
13562                                     struct mlx5_meter_domain_info *dtb,
13563                                     uint8_t mtr_reg_c)
13564 {
13565         struct mlx5_flow_dv_match_params matcher = {
13566                 .size = sizeof(matcher.buf),
13567         };
13568         struct mlx5_flow_dv_match_params value = {
13569                 .size = sizeof(value.buf),
13570         };
13571         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13572         void *actions[METER_ACTIONS];
13573         int i;
13574         int ret = 0;
13575
13576         /* Create jump action. */
13577         if (!dtb->jump_actn)
13578                 ret = mlx5_flow_os_create_flow_action_dest_flow_tbl
13579                                 (dtb->sfx_tbl->obj, &dtb->jump_actn);
13580         if (ret) {
13581                 DRV_LOG(ERR, "Failed to create policer jump action.");
13582                 goto error;
13583         }
13584         for (i = 0; i < RTE_MTR_DROPPED; i++) {
13585                 int j = 0;
13586
13587                 flow_dv_match_meta_reg(matcher.buf, value.buf, mtr_reg_c,
13588                                        rte_col_2_mlx5_col(i), UINT8_MAX);
13589                 if (mtb->count_actns[i])
13590                         actions[j++] = mtb->count_actns[i];
13591                 if (fm->action[i] == MTR_POLICER_ACTION_DROP)
13592                         actions[j++] = mtb->drop_actn;
13593                 else
13594                         actions[j++] = dtb->jump_actn;
13595                 ret = mlx5_flow_os_create_flow(dtb->color_matcher,
13596                                                (void *)&value, j, actions,
13597                                                &dtb->policer_rules[i]);
13598                 if (ret) {
13599                         DRV_LOG(ERR, "Failed to create policer rule.");
13600                         goto error;
13601                 }
13602         }
13603         return 0;
13604 error:
13605         rte_errno = errno;
13606         return -1;
13607 }
13608
13609 /**
13610  * Create policer rules.
13611  *
13612  * @param[in] dev
13613  *   Pointer to Ethernet device.
13614  * @param[in] fm
13615  *   Pointer to flow meter structure.
13616  * @param[in] attr
13617  *   Pointer to flow attributes.
13618  *
13619  * @return
13620  *   0 on success, -1 otherwise.
13621  */
13622 static int
13623 flow_dv_create_policer_rules(struct rte_eth_dev *dev,
13624                              struct mlx5_flow_meter *fm,
13625                              const struct rte_flow_attr *attr)
13626 {
13627         struct mlx5_priv *priv = dev->data->dev_private;
13628         struct mlx5_meter_domains_infos *mtb = fm->mfts;
13629         int ret;
13630
13631         if (attr->egress) {
13632                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->egress,
13633                                                 priv->mtr_color_reg);
13634                 if (ret) {
13635                         DRV_LOG(ERR, "Failed to create egress policer.");
13636                         goto error;
13637                 }
13638         }
13639         if (attr->ingress) {
13640                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->ingress,
13641                                                 priv->mtr_color_reg);
13642                 if (ret) {
13643                         DRV_LOG(ERR, "Failed to create ingress policer.");
13644                         goto error;
13645                 }
13646         }
13647         if (attr->transfer) {
13648                 ret = flow_dv_create_policer_forward_rule(fm, &mtb->transfer,
13649                                                 priv->mtr_color_reg);
13650                 if (ret) {
13651                         DRV_LOG(ERR, "Failed to create transfer policer.");
13652                         goto error;
13653                 }
13654         }
13655         return 0;
13656 error:
13657         flow_dv_destroy_policer_rules(dev, fm, attr);
13658         return -1;
13659 }
13660
13661 /**
13662  * Validate the batch counter support in root table.
13663  *
13664  * Create a simple flow with invalid counter and drop action on root table to
13665  * validate if batch counter with offset on root table is supported or not.
13666  *
13667  * @param[in] dev
13668  *   Pointer to rte_eth_dev structure.
13669  *
13670  * @return
13671  *   0 on success, a negative errno value otherwise and rte_errno is set.
13672  */
13673 int
13674 mlx5_flow_dv_discover_counter_offset_support(struct rte_eth_dev *dev)
13675 {
13676         struct mlx5_priv *priv = dev->data->dev_private;
13677         struct mlx5_dev_ctx_shared *sh = priv->sh;
13678         struct mlx5_flow_dv_match_params mask = {
13679                 .size = sizeof(mask.buf),
13680         };
13681         struct mlx5_flow_dv_match_params value = {
13682                 .size = sizeof(value.buf),
13683         };
13684         struct mlx5dv_flow_matcher_attr dv_attr = {
13685                 .type = IBV_FLOW_ATTR_NORMAL,
13686                 .priority = 0,
13687                 .match_criteria_enable = 0,
13688                 .match_mask = (void *)&mask,
13689         };
13690         void *actions[2] = { 0 };
13691         struct mlx5_flow_tbl_resource *tbl = NULL;
13692         struct mlx5_devx_obj *dcs = NULL;
13693         void *matcher = NULL;
13694         void *flow = NULL;
13695         int ret = -1;
13696
13697         tbl = flow_dv_tbl_resource_get(dev, 0, 0, 0, false, NULL, 0, 0, NULL);
13698         if (!tbl)
13699                 goto err;
13700         dcs = mlx5_devx_cmd_flow_counter_alloc(priv->sh->ctx, 0x4);
13701         if (!dcs)
13702                 goto err;
13703         ret = mlx5_flow_os_create_flow_action_count(dcs->obj, UINT16_MAX,
13704                                                     &actions[0]);
13705         if (ret)
13706                 goto err;
13707         actions[1] = priv->drop_queue.hrxq->action;
13708         dv_attr.match_criteria_enable = flow_dv_matcher_enable(mask.buf);
13709         ret = mlx5_flow_os_create_flow_matcher(sh->ctx, &dv_attr, tbl->obj,
13710                                                &matcher);
13711         if (ret)
13712                 goto err;
13713         ret = mlx5_flow_os_create_flow(matcher, (void *)&value, 2,
13714                                        actions, &flow);
13715 err:
13716         /*
13717          * If batch counter with offset is not supported, the driver will not
13718          * validate the invalid offset value, flow create should success.
13719          * In this case, it means batch counter is not supported in root table.
13720          *
13721          * Otherwise, if flow create is failed, counter offset is supported.
13722          */
13723         if (flow) {
13724                 DRV_LOG(INFO, "Batch counter is not supported in root "
13725                               "table. Switch to fallback mode.");
13726                 rte_errno = ENOTSUP;
13727                 ret = -rte_errno;
13728                 claim_zero(mlx5_flow_os_destroy_flow(flow));
13729         } else {
13730                 /* Check matcher to make sure validate fail at flow create. */
13731                 if (!matcher || (matcher && errno != EINVAL))
13732                         DRV_LOG(ERR, "Unexpected error in counter offset "
13733                                      "support detection");
13734                 ret = 0;
13735         }
13736         if (actions[0])
13737                 claim_zero(mlx5_flow_os_destroy_flow_action(actions[0]));
13738         if (matcher)
13739                 claim_zero(mlx5_flow_os_destroy_flow_matcher(matcher));
13740         if (tbl)
13741                 flow_dv_tbl_resource_release(MLX5_SH(dev), tbl);
13742         if (dcs)
13743                 claim_zero(mlx5_devx_cmd_destroy(dcs));
13744         return ret;
13745 }
13746
13747 /**
13748  * Query a devx counter.
13749  *
13750  * @param[in] dev
13751  *   Pointer to the Ethernet device structure.
13752  * @param[in] cnt
13753  *   Index to the flow counter.
13754  * @param[in] clear
13755  *   Set to clear the counter statistics.
13756  * @param[out] pkts
13757  *   The statistics value of packets.
13758  * @param[out] bytes
13759  *   The statistics value of bytes.
13760  *
13761  * @return
13762  *   0 on success, otherwise return -1.
13763  */
13764 static int
13765 flow_dv_counter_query(struct rte_eth_dev *dev, uint32_t counter, bool clear,
13766                       uint64_t *pkts, uint64_t *bytes)
13767 {
13768         struct mlx5_priv *priv = dev->data->dev_private;
13769         struct mlx5_flow_counter *cnt;
13770         uint64_t inn_pkts, inn_bytes;
13771         int ret;
13772
13773         if (!priv->config.devx)
13774                 return -1;
13775
13776         ret = _flow_dv_query_count(dev, counter, &inn_pkts, &inn_bytes);
13777         if (ret)
13778                 return -1;
13779         cnt = flow_dv_counter_get_by_idx(dev, counter, NULL);
13780         *pkts = inn_pkts - cnt->hits;
13781         *bytes = inn_bytes - cnt->bytes;
13782         if (clear) {
13783                 cnt->hits = inn_pkts;
13784                 cnt->bytes = inn_bytes;
13785         }
13786         return 0;
13787 }
13788
13789 /**
13790  * Get aged-out flows.
13791  *
13792  * @param[in] dev
13793  *   Pointer to the Ethernet device structure.
13794  * @param[in] context
13795  *   The address of an array of pointers to the aged-out flows contexts.
13796  * @param[in] nb_contexts
13797  *   The length of context array pointers.
13798  * @param[out] error
13799  *   Perform verbose error reporting if not NULL. Initialized in case of
13800  *   error only.
13801  *
13802  * @return
13803  *   how many contexts get in success, otherwise negative errno value.
13804  *   if nb_contexts is 0, return the amount of all aged contexts.
13805  *   if nb_contexts is not 0 , return the amount of aged flows reported
13806  *   in the context array.
13807  * @note: only stub for now
13808  */
13809 static int
13810 flow_get_aged_flows(struct rte_eth_dev *dev,
13811                     void **context,
13812                     uint32_t nb_contexts,
13813                     struct rte_flow_error *error)
13814 {
13815         struct mlx5_priv *priv = dev->data->dev_private;
13816         struct mlx5_age_info *age_info;
13817         struct mlx5_age_param *age_param;
13818         struct mlx5_flow_counter *counter;
13819         struct mlx5_aso_age_action *act;
13820         int nb_flows = 0;
13821
13822         if (nb_contexts && !context)
13823                 return rte_flow_error_set(error, EINVAL,
13824                                           RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13825                                           NULL, "empty context");
13826         age_info = GET_PORT_AGE_INFO(priv);
13827         rte_spinlock_lock(&age_info->aged_sl);
13828         LIST_FOREACH(act, &age_info->aged_aso, next) {
13829                 nb_flows++;
13830                 if (nb_contexts) {
13831                         context[nb_flows - 1] =
13832                                                 act->age_params.context;
13833                         if (!(--nb_contexts))
13834                                 break;
13835                 }
13836         }
13837         TAILQ_FOREACH(counter, &age_info->aged_counters, next) {
13838                 nb_flows++;
13839                 if (nb_contexts) {
13840                         age_param = MLX5_CNT_TO_AGE(counter);
13841                         context[nb_flows - 1] = age_param->context;
13842                         if (!(--nb_contexts))
13843                                 break;
13844                 }
13845         }
13846         rte_spinlock_unlock(&age_info->aged_sl);
13847         MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER);
13848         return nb_flows;
13849 }
13850
13851 /*
13852  * Mutex-protected thunk to lock-free flow_dv_counter_alloc().
13853  */
13854 static uint32_t
13855 flow_dv_counter_allocate(struct rte_eth_dev *dev)
13856 {
13857         return flow_dv_counter_alloc(dev, 0);
13858 }
13859
13860 /**
13861  * Validate shared action.
13862  * Dispatcher for action type specific validation.
13863  *
13864  * @param[in] dev
13865  *   Pointer to the Ethernet device structure.
13866  * @param[in] conf
13867  *   Shared action configuration.
13868  * @param[in] action
13869  *   The shared action object to validate.
13870  * @param[out] error
13871  *   Perform verbose error reporting if not NULL. Initialized in case of
13872  *   error only.
13873  *
13874  * @return
13875  *   0 on success, otherwise negative errno value.
13876  */
13877 static int
13878 flow_dv_action_validate(struct rte_eth_dev *dev,
13879                         const struct rte_flow_shared_action_conf *conf,
13880                         const struct rte_flow_action *action,
13881                         struct rte_flow_error *err)
13882 {
13883         struct mlx5_priv *priv = dev->data->dev_private;
13884
13885         RTE_SET_USED(conf);
13886         switch (action->type) {
13887         case RTE_FLOW_ACTION_TYPE_RSS:
13888                 /*
13889                  * priv->obj_ops is set according to driver capabilities.
13890                  * When DevX capabilities are
13891                  * sufficient, it is set to devx_obj_ops.
13892                  * Otherwise, it is set to ibv_obj_ops.
13893                  * ibv_obj_ops doesn't support ind_table_modify operation.
13894                  * In this case the shared RSS action can't be used.
13895                  */
13896                 if (priv->obj_ops.ind_table_modify == NULL)
13897                         return rte_flow_error_set
13898                                         (err, ENOTSUP,
13899                                          RTE_FLOW_ERROR_TYPE_ACTION,
13900                                          NULL,
13901                                          "shared RSS action not supported");
13902                 return mlx5_validate_action_rss(dev, action, err);
13903         case RTE_FLOW_ACTION_TYPE_AGE:
13904                 if (!priv->sh->aso_age_mng)
13905                         return rte_flow_error_set(err, ENOTSUP,
13906                                                 RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
13907                                                 NULL,
13908                                              "shared age action not supported");
13909                 return flow_dv_validate_action_age(0, action, dev, err);
13910         default:
13911                 return rte_flow_error_set(err, ENOTSUP,
13912                                           RTE_FLOW_ERROR_TYPE_ACTION,
13913                                           NULL,
13914                                           "action type not supported");
13915         }
13916 }
13917
13918 static int
13919 flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)
13920 {
13921         struct mlx5_priv *priv = dev->data->dev_private;
13922         int ret = 0;
13923
13924         if ((domains & MLX5_DOMAIN_BIT_NIC_RX) && priv->sh->rx_domain != NULL) {
13925                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->rx_domain,
13926                                                 flags);
13927                 if (ret != 0)
13928                         return ret;
13929         }
13930         if ((domains & MLX5_DOMAIN_BIT_NIC_TX) && priv->sh->tx_domain != NULL) {
13931                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->tx_domain, flags);
13932                 if (ret != 0)
13933                         return ret;
13934         }
13935         if ((domains & MLX5_DOMAIN_BIT_FDB) && priv->sh->fdb_domain != NULL) {
13936                 ret = mlx5_os_flow_dr_sync_domain(priv->sh->fdb_domain, flags);
13937                 if (ret != 0)
13938                         return ret;
13939         }
13940         return 0;
13941 }
13942
13943 const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {
13944         .validate = flow_dv_validate,
13945         .prepare = flow_dv_prepare,
13946         .translate = flow_dv_translate,
13947         .apply = flow_dv_apply,
13948         .remove = flow_dv_remove,
13949         .destroy = flow_dv_destroy,
13950         .query = flow_dv_query,
13951         .create_mtr_tbls = flow_dv_create_mtr_tbl,
13952         .destroy_mtr_tbls = flow_dv_destroy_mtr_tbl,
13953         .create_policer_rules = flow_dv_create_policer_rules,
13954         .destroy_policer_rules = flow_dv_destroy_policer_rules,
13955         .counter_alloc = flow_dv_counter_allocate,
13956         .counter_free = flow_dv_counter_free,
13957         .counter_query = flow_dv_counter_query,
13958         .get_aged_flows = flow_get_aged_flows,
13959         .action_validate = flow_dv_action_validate,
13960         .action_create = flow_dv_action_create,
13961         .action_destroy = flow_dv_action_destroy,
13962         .action_update = flow_dv_action_update,
13963         .action_query = flow_dv_action_query,
13964         .sync_domain = flow_dv_sync_domain,
13965 };
13966
13967 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
13968